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i965: Fix compiler warning about write being undefined.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct ac_nir_context {
49 struct ac_llvm_context ac;
50 struct ac_shader_abi *abi;
51
52 gl_shader_stage stage;
53
54 struct hash_table *defs;
55 struct hash_table *phis;
56 struct hash_table *vars;
57
58 LLVMValueRef main_function;
59 LLVMBasicBlockRef continue_block;
60 LLVMBasicBlockRef break_block;
61
62 int num_locals;
63 LLVMValueRef *locals;
64 };
65
66 struct radv_shader_context {
67 struct ac_llvm_context ac;
68 const struct ac_nir_compiler_options *options;
69 struct ac_shader_variant_info *shader_info;
70 struct ac_shader_abi abi;
71
72 unsigned max_workgroup_size;
73 LLVMContextRef context;
74 LLVMValueRef main_function;
75
76 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
77 LLVMValueRef ring_offsets;
78
79 LLVMValueRef vertex_buffers;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef ls_out_layout;
83 LLVMValueRef es2gs_offset;
84
85 LLVMValueRef tcs_offchip_layout;
86 LLVMValueRef tcs_out_offsets;
87 LLVMValueRef tcs_out_layout;
88 LLVMValueRef tcs_in_layout;
89 LLVMValueRef oc_lds;
90 LLVMValueRef merged_wave_info;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tes_rel_patch_id;
93 LLVMValueRef tes_u;
94 LLVMValueRef tes_v;
95
96 LLVMValueRef gsvs_ring_stride;
97 LLVMValueRef gsvs_num_entries;
98 LLVMValueRef gs2vs_offset;
99 LLVMValueRef gs_wave_id;
100 LLVMValueRef gs_vtx_offset[6];
101
102 LLVMValueRef esgs_ring;
103 LLVMValueRef gsvs_ring;
104 LLVMValueRef hs_ring_tess_offchip;
105 LLVMValueRef hs_ring_tess_factor;
106
107 LLVMValueRef sample_pos_offset;
108 LLVMValueRef persp_sample, persp_center, persp_centroid;
109 LLVMValueRef linear_sample, linear_center, linear_centroid;
110
111 gl_shader_stage stage;
112
113 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
114
115 uint64_t input_mask;
116 uint64_t output_mask;
117 uint8_t num_output_clips;
118 uint8_t num_output_culls;
119
120 bool is_gs_copy_shader;
121 LLVMValueRef gs_next_vertex;
122 unsigned gs_max_out_vertices;
123
124 unsigned tes_primitive_mode;
125 uint64_t tess_outputs_written;
126 uint64_t tess_patch_outputs_written;
127
128 uint32_t tcs_patch_outputs_read;
129 uint64_t tcs_outputs_read;
130 uint32_t tcs_vertices_per_patch;
131 };
132
133 static inline struct radv_shader_context *
134 radv_shader_context_from_abi(struct ac_shader_abi *abi)
135 {
136 struct radv_shader_context *ctx = NULL;
137 return container_of(abi, ctx, abi);
138 }
139
140 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
141 const nir_deref_var *deref,
142 enum ac_descriptor_type desc_type,
143 const nir_tex_instr *instr,
144 bool image, bool write);
145
146 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
147 {
148 return (index * 4) + chan;
149 }
150
151 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
152 {
153 /* handle patch indices separate */
154 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
155 return 0;
156 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
157 return 1;
158 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
159 return 2 + (slot - VARYING_SLOT_PATCH0);
160
161 if (slot == VARYING_SLOT_POS)
162 return 0;
163 if (slot == VARYING_SLOT_PSIZ)
164 return 1;
165 if (slot == VARYING_SLOT_CLIP_DIST0)
166 return 2;
167 /* 3 is reserved for clip dist as well */
168 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
169 return 4 + (slot - VARYING_SLOT_VAR0);
170 unreachable("illegal slot in get unique index\n");
171 }
172
173 static void set_llvm_calling_convention(LLVMValueRef func,
174 gl_shader_stage stage)
175 {
176 enum radeon_llvm_calling_convention calling_conv;
177
178 switch (stage) {
179 case MESA_SHADER_VERTEX:
180 case MESA_SHADER_TESS_EVAL:
181 calling_conv = RADEON_LLVM_AMDGPU_VS;
182 break;
183 case MESA_SHADER_GEOMETRY:
184 calling_conv = RADEON_LLVM_AMDGPU_GS;
185 break;
186 case MESA_SHADER_TESS_CTRL:
187 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
188 break;
189 case MESA_SHADER_FRAGMENT:
190 calling_conv = RADEON_LLVM_AMDGPU_PS;
191 break;
192 case MESA_SHADER_COMPUTE:
193 calling_conv = RADEON_LLVM_AMDGPU_CS;
194 break;
195 default:
196 unreachable("Unhandle shader type");
197 }
198
199 LLVMSetFunctionCallConv(func, calling_conv);
200 }
201
202 #define MAX_ARGS 23
203 struct arg_info {
204 LLVMTypeRef types[MAX_ARGS];
205 LLVMValueRef *assign[MAX_ARGS];
206 unsigned array_params_mask;
207 uint8_t count;
208 uint8_t sgpr_count;
209 uint8_t num_sgprs_used;
210 uint8_t num_vgprs_used;
211 };
212
213 enum ac_arg_regfile {
214 ARG_SGPR,
215 ARG_VGPR,
216 };
217
218 static void
219 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
220 LLVMValueRef *param_ptr)
221 {
222 assert(info->count < MAX_ARGS);
223
224 info->assign[info->count] = param_ptr;
225 info->types[info->count] = type;
226 info->count++;
227
228 if (regfile == ARG_SGPR) {
229 info->num_sgprs_used += ac_get_type_size(type) / 4;
230 info->sgpr_count++;
231 } else {
232 assert(regfile == ARG_VGPR);
233 info->num_vgprs_used += ac_get_type_size(type) / 4;
234 }
235 }
236
237 static inline void
238 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
239 {
240 info->array_params_mask |= (1 << info->count);
241 add_arg(info, ARG_SGPR, type, param_ptr);
242 }
243
244 static void assign_arguments(LLVMValueRef main_function,
245 struct arg_info *info)
246 {
247 unsigned i;
248 for (i = 0; i < info->count; i++) {
249 if (info->assign[i])
250 *info->assign[i] = LLVMGetParam(main_function, i);
251 }
252 }
253
254 static LLVMValueRef
255 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
256 LLVMBuilderRef builder, LLVMTypeRef *return_types,
257 unsigned num_return_elems,
258 struct arg_info *args,
259 unsigned max_workgroup_size,
260 bool unsafe_math)
261 {
262 LLVMTypeRef main_function_type, ret_type;
263 LLVMBasicBlockRef main_function_body;
264
265 if (num_return_elems)
266 ret_type = LLVMStructTypeInContext(ctx, return_types,
267 num_return_elems, true);
268 else
269 ret_type = LLVMVoidTypeInContext(ctx);
270
271 /* Setup the function */
272 main_function_type =
273 LLVMFunctionType(ret_type, args->types, args->count, 0);
274 LLVMValueRef main_function =
275 LLVMAddFunction(module, "main", main_function_type);
276 main_function_body =
277 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
278 LLVMPositionBuilderAtEnd(builder, main_function_body);
279
280 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
281 for (unsigned i = 0; i < args->sgpr_count; ++i) {
282 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
283
284 if (args->array_params_mask & (1 << i)) {
285 LLVMValueRef P = LLVMGetParam(main_function, i);
286 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
287 ac_add_attr_dereferenceable(P, UINT64_MAX);
288 }
289 }
290
291 if (max_workgroup_size) {
292 ac_llvm_add_target_dep_function_attr(main_function,
293 "amdgpu-max-work-group-size",
294 max_workgroup_size);
295 }
296 if (unsafe_math) {
297 /* These were copied from some LLVM test. */
298 LLVMAddTargetDependentFunctionAttr(main_function,
299 "less-precise-fpmad",
300 "true");
301 LLVMAddTargetDependentFunctionAttr(main_function,
302 "no-infs-fp-math",
303 "true");
304 LLVMAddTargetDependentFunctionAttr(main_function,
305 "no-nans-fp-math",
306 "true");
307 LLVMAddTargetDependentFunctionAttr(main_function,
308 "unsafe-fp-math",
309 "true");
310 LLVMAddTargetDependentFunctionAttr(main_function,
311 "no-signed-zeros-fp-math",
312 "true");
313 }
314 return main_function;
315 }
316
317 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
318 LLVMValueRef param, unsigned rshift,
319 unsigned bitwidth)
320 {
321 LLVMValueRef value = param;
322 if (rshift)
323 value = LLVMBuildLShr(ctx->builder, value,
324 LLVMConstInt(ctx->i32, rshift, false), "");
325
326 if (rshift + bitwidth < 32) {
327 unsigned mask = (1 << bitwidth) - 1;
328 value = LLVMBuildAnd(ctx->builder, value,
329 LLVMConstInt(ctx->i32, mask, false), "");
330 }
331 return value;
332 }
333
334 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
335 {
336 switch (ctx->stage) {
337 case MESA_SHADER_TESS_CTRL:
338 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
339 case MESA_SHADER_TESS_EVAL:
340 return ctx->tes_rel_patch_id;
341 break;
342 default:
343 unreachable("Illegal stage");
344 }
345 }
346
347 /* Tessellation shaders pass outputs to the next shader using LDS.
348 *
349 * LS outputs = TCS inputs
350 * TCS outputs = TES inputs
351 *
352 * The LDS layout is:
353 * - TCS inputs for patch 0
354 * - TCS inputs for patch 1
355 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
356 * - ...
357 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
358 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
359 * - TCS outputs for patch 1
360 * - Per-patch TCS outputs for patch 1
361 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
362 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
363 * - ...
364 *
365 * All three shaders VS(LS), TCS, TES share the same LDS space.
366 */
367 static LLVMValueRef
368 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
369 {
370 if (ctx->stage == MESA_SHADER_VERTEX)
371 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
372 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
373 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
374 else {
375 assert(0);
376 return NULL;
377 }
378 }
379
380 static LLVMValueRef
381 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
382 {
383 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
384 }
385
386 static LLVMValueRef
387 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
388 {
389 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
390 }
391
392 static LLVMValueRef
393 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
394 {
395 return LLVMBuildMul(ctx->ac.builder,
396 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
397 LLVMConstInt(ctx->ac.i32, 4, false), "");
398 }
399
400 static LLVMValueRef
401 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
402 {
403 return LLVMBuildMul(ctx->ac.builder,
404 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
405 LLVMConstInt(ctx->ac.i32, 4, false), "");
406 }
407
408 static LLVMValueRef
409 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
410 {
411 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
412 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
413
414 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
415 }
416
417 static LLVMValueRef
418 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
419 {
420 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
421 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
422 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
423
424 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
425 LLVMBuildMul(ctx->ac.builder, patch_stride,
426 rel_patch_id, ""),
427 "");
428 }
429
430 static LLVMValueRef
431 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
432 {
433 LLVMValueRef patch0_patch_data_offset =
434 get_tcs_out_patch0_patch_data_offset(ctx);
435 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
436 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
437
438 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
439 LLVMBuildMul(ctx->ac.builder, patch_stride,
440 rel_patch_id, ""),
441 "");
442 }
443
444 static void
445 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
446 uint32_t indirect_offset)
447 {
448 ud_info->sgpr_idx = *sgpr_idx;
449 ud_info->num_sgprs = num_sgprs;
450 ud_info->indirect = indirect_offset > 0;
451 ud_info->indirect_offset = indirect_offset;
452 *sgpr_idx += num_sgprs;
453 }
454
455 static void
456 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
457 uint8_t num_sgprs)
458 {
459 struct ac_userdata_info *ud_info =
460 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
461 assert(ud_info);
462
463 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
464 }
465
466 static void
467 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
468 uint32_t indirect_offset)
469 {
470 struct ac_userdata_info *ud_info =
471 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
472 assert(ud_info);
473
474 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
475 }
476
477 struct user_sgpr_info {
478 bool need_ring_offsets;
479 uint8_t sgpr_count;
480 bool indirect_all_descriptor_sets;
481 };
482
483 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
484 gl_shader_stage stage)
485 {
486 switch (stage) {
487 case MESA_SHADER_VERTEX:
488 if (ctx->shader_info->info.needs_multiview_view_index ||
489 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
490 return true;
491 break;
492 case MESA_SHADER_TESS_EVAL:
493 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
494 return true;
495 break;
496 case MESA_SHADER_GEOMETRY:
497 case MESA_SHADER_TESS_CTRL:
498 if (ctx->shader_info->info.needs_multiview_view_index)
499 return true;
500 break;
501 default:
502 break;
503 }
504 return false;
505 }
506
507 static uint8_t
508 count_vs_user_sgprs(struct radv_shader_context *ctx)
509 {
510 uint8_t count = 0;
511
512 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
513 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
514
515 return count;
516 }
517
518 static void allocate_user_sgprs(struct radv_shader_context *ctx,
519 gl_shader_stage stage,
520 bool has_previous_stage,
521 gl_shader_stage previous_stage,
522 bool needs_view_index,
523 struct user_sgpr_info *user_sgpr_info)
524 {
525 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
526
527 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
528 if (stage == MESA_SHADER_GEOMETRY ||
529 stage == MESA_SHADER_VERTEX ||
530 stage == MESA_SHADER_TESS_CTRL ||
531 stage == MESA_SHADER_TESS_EVAL ||
532 ctx->is_gs_copy_shader)
533 user_sgpr_info->need_ring_offsets = true;
534
535 if (stage == MESA_SHADER_FRAGMENT &&
536 ctx->shader_info->info.ps.needs_sample_positions)
537 user_sgpr_info->need_ring_offsets = true;
538
539 /* 2 user sgprs will nearly always be allocated for scratch/rings */
540 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
541 user_sgpr_info->sgpr_count += 2;
542 }
543
544 switch (stage) {
545 case MESA_SHADER_COMPUTE:
546 if (ctx->shader_info->info.cs.uses_grid_size)
547 user_sgpr_info->sgpr_count += 3;
548 break;
549 case MESA_SHADER_FRAGMENT:
550 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
551 break;
552 case MESA_SHADER_VERTEX:
553 if (!ctx->is_gs_copy_shader)
554 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
555 if (ctx->options->key.vs.as_ls)
556 user_sgpr_info->sgpr_count++;
557 break;
558 case MESA_SHADER_TESS_CTRL:
559 if (has_previous_stage) {
560 if (previous_stage == MESA_SHADER_VERTEX)
561 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
562 user_sgpr_info->sgpr_count++;
563 }
564 user_sgpr_info->sgpr_count += 4;
565 break;
566 case MESA_SHADER_TESS_EVAL:
567 user_sgpr_info->sgpr_count += 1;
568 break;
569 case MESA_SHADER_GEOMETRY:
570 if (has_previous_stage) {
571 if (previous_stage == MESA_SHADER_VERTEX) {
572 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
573 } else {
574 user_sgpr_info->sgpr_count++;
575 }
576 }
577 user_sgpr_info->sgpr_count += 2;
578 break;
579 default:
580 break;
581 }
582
583 if (needs_view_index)
584 user_sgpr_info->sgpr_count++;
585
586 if (ctx->shader_info->info.loads_push_constants)
587 user_sgpr_info->sgpr_count += 2;
588
589 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
590 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
591
592 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
593 user_sgpr_info->sgpr_count += 2;
594 user_sgpr_info->indirect_all_descriptor_sets = true;
595 } else {
596 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
597 }
598 }
599
600 static void
601 declare_global_input_sgprs(struct radv_shader_context *ctx,
602 gl_shader_stage stage,
603 bool has_previous_stage,
604 gl_shader_stage previous_stage,
605 const struct user_sgpr_info *user_sgpr_info,
606 struct arg_info *args,
607 LLVMValueRef *desc_sets)
608 {
609 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
610 unsigned num_sets = ctx->options->layout ?
611 ctx->options->layout->num_sets : 0;
612 unsigned stage_mask = 1 << stage;
613
614 if (has_previous_stage)
615 stage_mask |= 1 << previous_stage;
616
617 /* 1 for each descriptor set */
618 if (!user_sgpr_info->indirect_all_descriptor_sets) {
619 for (unsigned i = 0; i < num_sets; ++i) {
620 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
621 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
622 add_array_arg(args, type,
623 &ctx->descriptor_sets[i]);
624 }
625 }
626 } else {
627 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
628 }
629
630 if (ctx->shader_info->info.loads_push_constants) {
631 /* 1 for push constants and dynamic descriptors */
632 add_array_arg(args, type, &ctx->abi.push_constants);
633 }
634 }
635
636 static void
637 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
638 gl_shader_stage stage,
639 bool has_previous_stage,
640 gl_shader_stage previous_stage,
641 struct arg_info *args)
642 {
643 if (!ctx->is_gs_copy_shader &&
644 (stage == MESA_SHADER_VERTEX ||
645 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
646 if (ctx->shader_info->info.vs.has_vertex_buffers) {
647 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
648 &ctx->vertex_buffers);
649 }
650 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
651 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
652 if (ctx->shader_info->info.vs.needs_draw_id) {
653 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
654 }
655 }
656 }
657
658 static void
659 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
660 {
661 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
662 if (!ctx->is_gs_copy_shader) {
663 if (ctx->options->key.vs.as_ls) {
664 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
665 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
666 } else {
667 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
668 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
669 }
670 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
671 }
672 }
673
674 static void
675 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
676 {
677 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
678 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
679 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
680 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
681 }
682
683 static void
684 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
685 bool has_previous_stage, gl_shader_stage previous_stage,
686 const struct user_sgpr_info *user_sgpr_info,
687 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
688 {
689 unsigned num_sets = ctx->options->layout ?
690 ctx->options->layout->num_sets : 0;
691 unsigned stage_mask = 1 << stage;
692
693 if (has_previous_stage)
694 stage_mask |= 1 << previous_stage;
695
696 if (!user_sgpr_info->indirect_all_descriptor_sets) {
697 for (unsigned i = 0; i < num_sets; ++i) {
698 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
699 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
700 set_loc_desc(ctx, i, user_sgpr_idx, 0);
701 } else
702 ctx->descriptor_sets[i] = NULL;
703 }
704 } else {
705 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
706 user_sgpr_idx, 2);
707
708 for (unsigned i = 0; i < num_sets; ++i) {
709 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
710 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
711 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
712 ctx->descriptor_sets[i] =
713 ac_build_load_to_sgpr(&ctx->ac,
714 desc_sets,
715 LLVMConstInt(ctx->ac.i32, i, false));
716
717 } else
718 ctx->descriptor_sets[i] = NULL;
719 }
720 ctx->shader_info->need_indirect_descriptor_sets = true;
721 }
722
723 if (ctx->shader_info->info.loads_push_constants) {
724 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
725 }
726 }
727
728 static void
729 set_vs_specific_input_locs(struct radv_shader_context *ctx,
730 gl_shader_stage stage, bool has_previous_stage,
731 gl_shader_stage previous_stage,
732 uint8_t *user_sgpr_idx)
733 {
734 if (!ctx->is_gs_copy_shader &&
735 (stage == MESA_SHADER_VERTEX ||
736 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
737 if (ctx->shader_info->info.vs.has_vertex_buffers) {
738 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
739 user_sgpr_idx, 2);
740 }
741
742 unsigned vs_num = 2;
743 if (ctx->shader_info->info.vs.needs_draw_id)
744 vs_num++;
745
746 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
747 user_sgpr_idx, vs_num);
748 }
749 }
750
751 static void create_function(struct radv_shader_context *ctx,
752 gl_shader_stage stage,
753 bool has_previous_stage,
754 gl_shader_stage previous_stage)
755 {
756 uint8_t user_sgpr_idx;
757 struct user_sgpr_info user_sgpr_info;
758 struct arg_info args = {};
759 LLVMValueRef desc_sets;
760 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
761 allocate_user_sgprs(ctx, stage, has_previous_stage,
762 previous_stage, needs_view_index, &user_sgpr_info);
763
764 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
765 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
766 &ctx->ring_offsets);
767 }
768
769 switch (stage) {
770 case MESA_SHADER_COMPUTE:
771 declare_global_input_sgprs(ctx, stage, has_previous_stage,
772 previous_stage, &user_sgpr_info,
773 &args, &desc_sets);
774
775 if (ctx->shader_info->info.cs.uses_grid_size) {
776 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
777 &ctx->abi.num_work_groups);
778 }
779
780 for (int i = 0; i < 3; i++) {
781 ctx->abi.workgroup_ids[i] = NULL;
782 if (ctx->shader_info->info.cs.uses_block_id[i]) {
783 add_arg(&args, ARG_SGPR, ctx->ac.i32,
784 &ctx->abi.workgroup_ids[i]);
785 }
786 }
787
788 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
789 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
790 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
791 &ctx->abi.local_invocation_ids);
792 break;
793 case MESA_SHADER_VERTEX:
794 declare_global_input_sgprs(ctx, stage, has_previous_stage,
795 previous_stage, &user_sgpr_info,
796 &args, &desc_sets);
797 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
798 previous_stage, &args);
799
800 if (needs_view_index)
801 add_arg(&args, ARG_SGPR, ctx->ac.i32,
802 &ctx->abi.view_index);
803 if (ctx->options->key.vs.as_es)
804 add_arg(&args, ARG_SGPR, ctx->ac.i32,
805 &ctx->es2gs_offset);
806 else if (ctx->options->key.vs.as_ls)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32,
808 &ctx->ls_out_layout);
809
810 declare_vs_input_vgprs(ctx, &args);
811 break;
812 case MESA_SHADER_TESS_CTRL:
813 if (has_previous_stage) {
814 // First 6 system regs
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->merged_wave_info);
818 add_arg(&args, ARG_SGPR, ctx->ac.i32,
819 &ctx->tess_factor_offset);
820
821 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
822 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
823 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
824
825 declare_global_input_sgprs(ctx, stage,
826 has_previous_stage,
827 previous_stage,
828 &user_sgpr_info, &args,
829 &desc_sets);
830 declare_vs_specific_input_sgprs(ctx, stage,
831 has_previous_stage,
832 previous_stage, &args);
833
834 add_arg(&args, ARG_SGPR, ctx->ac.i32,
835 &ctx->ls_out_layout);
836
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->tcs_offchip_layout);
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->tcs_out_offsets);
841 add_arg(&args, ARG_SGPR, ctx->ac.i32,
842 &ctx->tcs_out_layout);
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->tcs_in_layout);
845 if (needs_view_index)
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->abi.view_index);
848
849 add_arg(&args, ARG_VGPR, ctx->ac.i32,
850 &ctx->abi.tcs_patch_id);
851 add_arg(&args, ARG_VGPR, ctx->ac.i32,
852 &ctx->abi.tcs_rel_ids);
853
854 declare_vs_input_vgprs(ctx, &args);
855 } else {
856 declare_global_input_sgprs(ctx, stage,
857 has_previous_stage,
858 previous_stage,
859 &user_sgpr_info, &args,
860 &desc_sets);
861
862 add_arg(&args, ARG_SGPR, ctx->ac.i32,
863 &ctx->tcs_offchip_layout);
864 add_arg(&args, ARG_SGPR, ctx->ac.i32,
865 &ctx->tcs_out_offsets);
866 add_arg(&args, ARG_SGPR, ctx->ac.i32,
867 &ctx->tcs_out_layout);
868 add_arg(&args, ARG_SGPR, ctx->ac.i32,
869 &ctx->tcs_in_layout);
870 if (needs_view_index)
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->abi.view_index);
873
874 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tess_factor_offset);
877 add_arg(&args, ARG_VGPR, ctx->ac.i32,
878 &ctx->abi.tcs_patch_id);
879 add_arg(&args, ARG_VGPR, ctx->ac.i32,
880 &ctx->abi.tcs_rel_ids);
881 }
882 break;
883 case MESA_SHADER_TESS_EVAL:
884 declare_global_input_sgprs(ctx, stage, has_previous_stage,
885 previous_stage, &user_sgpr_info,
886 &args, &desc_sets);
887
888 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
889 if (needs_view_index)
890 add_arg(&args, ARG_SGPR, ctx->ac.i32,
891 &ctx->abi.view_index);
892
893 if (ctx->options->key.tes.as_es) {
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
895 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
896 add_arg(&args, ARG_SGPR, ctx->ac.i32,
897 &ctx->es2gs_offset);
898 } else {
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
900 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
901 }
902 declare_tes_input_vgprs(ctx, &args);
903 break;
904 case MESA_SHADER_GEOMETRY:
905 if (has_previous_stage) {
906 // First 6 system regs
907 add_arg(&args, ARG_SGPR, ctx->ac.i32,
908 &ctx->gs2vs_offset);
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->merged_wave_info);
911 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
912
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
915 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
916
917 declare_global_input_sgprs(ctx, stage,
918 has_previous_stage,
919 previous_stage,
920 &user_sgpr_info, &args,
921 &desc_sets);
922
923 if (previous_stage == MESA_SHADER_TESS_EVAL) {
924 add_arg(&args, ARG_SGPR, ctx->ac.i32,
925 &ctx->tcs_offchip_layout);
926 } else {
927 declare_vs_specific_input_sgprs(ctx, stage,
928 has_previous_stage,
929 previous_stage,
930 &args);
931 }
932
933 add_arg(&args, ARG_SGPR, ctx->ac.i32,
934 &ctx->gsvs_ring_stride);
935 add_arg(&args, ARG_SGPR, ctx->ac.i32,
936 &ctx->gsvs_num_entries);
937 if (needs_view_index)
938 add_arg(&args, ARG_SGPR, ctx->ac.i32,
939 &ctx->abi.view_index);
940
941 add_arg(&args, ARG_VGPR, ctx->ac.i32,
942 &ctx->gs_vtx_offset[0]);
943 add_arg(&args, ARG_VGPR, ctx->ac.i32,
944 &ctx->gs_vtx_offset[2]);
945 add_arg(&args, ARG_VGPR, ctx->ac.i32,
946 &ctx->abi.gs_prim_id);
947 add_arg(&args, ARG_VGPR, ctx->ac.i32,
948 &ctx->abi.gs_invocation_id);
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->gs_vtx_offset[4]);
951
952 if (previous_stage == MESA_SHADER_VERTEX) {
953 declare_vs_input_vgprs(ctx, &args);
954 } else {
955 declare_tes_input_vgprs(ctx, &args);
956 }
957 } else {
958 declare_global_input_sgprs(ctx, stage,
959 has_previous_stage,
960 previous_stage,
961 &user_sgpr_info, &args,
962 &desc_sets);
963
964 add_arg(&args, ARG_SGPR, ctx->ac.i32,
965 &ctx->gsvs_ring_stride);
966 add_arg(&args, ARG_SGPR, ctx->ac.i32,
967 &ctx->gsvs_num_entries);
968 if (needs_view_index)
969 add_arg(&args, ARG_SGPR, ctx->ac.i32,
970 &ctx->abi.view_index);
971
972 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
973 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
974 add_arg(&args, ARG_VGPR, ctx->ac.i32,
975 &ctx->gs_vtx_offset[0]);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[1]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->abi.gs_prim_id);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->gs_vtx_offset[2]);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[3]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[4]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[5]);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->abi.gs_invocation_id);
990 }
991 break;
992 case MESA_SHADER_FRAGMENT:
993 declare_global_input_sgprs(ctx, stage, has_previous_stage,
994 previous_stage, &user_sgpr_info,
995 &args, &desc_sets);
996
997 if (ctx->shader_info->info.ps.needs_sample_positions)
998 add_arg(&args, ARG_SGPR, ctx->ac.i32,
999 &ctx->sample_pos_offset);
1000
1001 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1002 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1003 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1005 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1009 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1010 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1014 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1018 break;
1019 default:
1020 unreachable("Shader stage not implemented");
1021 }
1022
1023 ctx->main_function = create_llvm_function(
1024 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1025 ctx->max_workgroup_size,
1026 ctx->options->unsafe_math);
1027 set_llvm_calling_convention(ctx->main_function, stage);
1028
1029
1030 ctx->shader_info->num_input_vgprs = 0;
1031 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1032
1033 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1034
1035 if (ctx->stage != MESA_SHADER_FRAGMENT)
1036 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1037
1038 assign_arguments(ctx->main_function, &args);
1039
1040 user_sgpr_idx = 0;
1041
1042 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1043 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1044 &user_sgpr_idx, 2);
1045 if (ctx->options->supports_spill) {
1046 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1047 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1048 NULL, 0, AC_FUNC_ATTR_READNONE);
1049 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1050 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1051 }
1052 }
1053
1054 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1055 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1056 if (has_previous_stage)
1057 user_sgpr_idx = 0;
1058
1059 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1060 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1061
1062 switch (stage) {
1063 case MESA_SHADER_COMPUTE:
1064 if (ctx->shader_info->info.cs.uses_grid_size) {
1065 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1066 &user_sgpr_idx, 3);
1067 }
1068 break;
1069 case MESA_SHADER_VERTEX:
1070 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1071 previous_stage, &user_sgpr_idx);
1072 if (ctx->abi.view_index)
1073 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1074 if (ctx->options->key.vs.as_ls) {
1075 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1076 &user_sgpr_idx, 1);
1077 }
1078 break;
1079 case MESA_SHADER_TESS_CTRL:
1080 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1081 previous_stage, &user_sgpr_idx);
1082 if (has_previous_stage)
1083 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1084 &user_sgpr_idx, 1);
1085 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1086 if (ctx->abi.view_index)
1087 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1088 break;
1089 case MESA_SHADER_TESS_EVAL:
1090 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1091 if (ctx->abi.view_index)
1092 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1093 break;
1094 case MESA_SHADER_GEOMETRY:
1095 if (has_previous_stage) {
1096 if (previous_stage == MESA_SHADER_VERTEX)
1097 set_vs_specific_input_locs(ctx, stage,
1098 has_previous_stage,
1099 previous_stage,
1100 &user_sgpr_idx);
1101 else
1102 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1103 &user_sgpr_idx, 1);
1104 }
1105 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1106 &user_sgpr_idx, 2);
1107 if (ctx->abi.view_index)
1108 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1109 break;
1110 case MESA_SHADER_FRAGMENT:
1111 if (ctx->shader_info->info.ps.needs_sample_positions) {
1112 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1113 &user_sgpr_idx, 1);
1114 }
1115 break;
1116 default:
1117 unreachable("Shader stage not implemented");
1118 }
1119
1120 if (stage == MESA_SHADER_TESS_CTRL ||
1121 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1122 /* GFX9 has the ESGS ring buffer in LDS. */
1123 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1124 ac_declare_lds_as_pointer(&ctx->ac);
1125 }
1126
1127 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1128 }
1129
1130 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1131 LLVMValueRef value, unsigned count)
1132 {
1133 unsigned num_components = ac_get_llvm_num_components(value);
1134 if (count == num_components)
1135 return value;
1136
1137 LLVMValueRef masks[] = {
1138 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1139 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1140
1141 if (count == 1)
1142 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1143 "");
1144
1145 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1146 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1147 }
1148
1149 static void
1150 build_store_values_extended(struct ac_llvm_context *ac,
1151 LLVMValueRef *values,
1152 unsigned value_count,
1153 unsigned value_stride,
1154 LLVMValueRef vec)
1155 {
1156 LLVMBuilderRef builder = ac->builder;
1157 unsigned i;
1158
1159 for (i = 0; i < value_count; i++) {
1160 LLVMValueRef ptr = values[i * value_stride];
1161 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1162 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1163 LLVMBuildStore(builder, value, ptr);
1164 }
1165 }
1166
1167 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1168 const nir_ssa_def *def)
1169 {
1170 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1171 if (def->num_components > 1) {
1172 type = LLVMVectorType(type, def->num_components);
1173 }
1174 return type;
1175 }
1176
1177 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1178 {
1179 assert(src.is_ssa);
1180 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1181 return (LLVMValueRef)entry->data;
1182 }
1183
1184 static LLVMValueRef
1185 get_memory_ptr(struct ac_nir_context *ctx, nir_src src)
1186 {
1187 LLVMValueRef ptr = get_src(ctx, src);
1188 ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ac.lds, &ptr, 1, "");
1189 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1190
1191 return LLVMBuildBitCast(ctx->ac.builder, ptr,
1192 LLVMPointerType(ctx->ac.i32, addr_space), "");
1193 }
1194
1195 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1196 const struct nir_block *b)
1197 {
1198 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1199 return (LLVMBasicBlockRef)entry->data;
1200 }
1201
1202 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1203 nir_alu_src src,
1204 unsigned num_components)
1205 {
1206 LLVMValueRef value = get_src(ctx, src.src);
1207 bool need_swizzle = false;
1208
1209 assert(value);
1210 LLVMTypeRef type = LLVMTypeOf(value);
1211 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1212 ? LLVMGetVectorSize(type)
1213 : 1;
1214
1215 for (unsigned i = 0; i < num_components; ++i) {
1216 assert(src.swizzle[i] < src_components);
1217 if (src.swizzle[i] != i)
1218 need_swizzle = true;
1219 }
1220
1221 if (need_swizzle || num_components != src_components) {
1222 LLVMValueRef masks[] = {
1223 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1224 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1225 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1226 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1227
1228 if (src_components > 1 && num_components == 1) {
1229 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1230 masks[0], "");
1231 } else if (src_components == 1 && num_components > 1) {
1232 LLVMValueRef values[] = {value, value, value, value};
1233 value = ac_build_gather_values(&ctx->ac, values, num_components);
1234 } else {
1235 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1236 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1237 swizzle, "");
1238 }
1239 }
1240 assert(!src.negate);
1241 assert(!src.abs);
1242 return value;
1243 }
1244
1245 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1246 LLVMIntPredicate pred, LLVMValueRef src0,
1247 LLVMValueRef src1)
1248 {
1249 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1250 return LLVMBuildSelect(ctx->builder, result,
1251 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1252 ctx->i32_0, "");
1253 }
1254
1255 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1256 LLVMRealPredicate pred, LLVMValueRef src0,
1257 LLVMValueRef src1)
1258 {
1259 LLVMValueRef result;
1260 src0 = ac_to_float(ctx, src0);
1261 src1 = ac_to_float(ctx, src1);
1262 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1263 return LLVMBuildSelect(ctx->builder, result,
1264 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1265 ctx->i32_0, "");
1266 }
1267
1268 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1269 const char *intrin,
1270 LLVMTypeRef result_type,
1271 LLVMValueRef src0)
1272 {
1273 char name[64];
1274 LLVMValueRef params[] = {
1275 ac_to_float(ctx, src0),
1276 };
1277
1278 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1279 ac_get_elem_bits(ctx, result_type));
1280 assert(length < sizeof(name));
1281 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1282 }
1283
1284 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1285 const char *intrin,
1286 LLVMTypeRef result_type,
1287 LLVMValueRef src0, LLVMValueRef src1)
1288 {
1289 char name[64];
1290 LLVMValueRef params[] = {
1291 ac_to_float(ctx, src0),
1292 ac_to_float(ctx, src1),
1293 };
1294
1295 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1296 ac_get_elem_bits(ctx, result_type));
1297 assert(length < sizeof(name));
1298 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1299 }
1300
1301 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1302 const char *intrin,
1303 LLVMTypeRef result_type,
1304 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1305 {
1306 char name[64];
1307 LLVMValueRef params[] = {
1308 ac_to_float(ctx, src0),
1309 ac_to_float(ctx, src1),
1310 ac_to_float(ctx, src2),
1311 };
1312
1313 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1314 ac_get_elem_bits(ctx, result_type));
1315 assert(length < sizeof(name));
1316 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1317 }
1318
1319 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1320 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1321 {
1322 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1323 ctx->i32_0, "");
1324 return LLVMBuildSelect(ctx->builder, v, ac_to_integer(ctx, src1),
1325 ac_to_integer(ctx, src2), "");
1326 }
1327
1328 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1329 LLVMIntPredicate pred,
1330 LLVMValueRef src0, LLVMValueRef src1)
1331 {
1332 return LLVMBuildSelect(ctx->builder,
1333 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1334 src0,
1335 src1, "");
1336
1337 }
1338 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1339 LLVMValueRef src0)
1340 {
1341 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1342 LLVMBuildNeg(ctx->builder, src0, ""));
1343 }
1344
1345 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1346 LLVMValueRef src0,
1347 unsigned bitsize)
1348 {
1349 LLVMValueRef cmp, val, zero, one;
1350 LLVMTypeRef type;
1351
1352 if (bitsize == 32) {
1353 type = ctx->f32;
1354 zero = ctx->f32_0;
1355 one = ctx->f32_1;
1356 } else {
1357 type = ctx->f64;
1358 zero = ctx->f64_0;
1359 one = ctx->f64_1;
1360 }
1361
1362 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1363 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1364 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1365 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1366 return val;
1367 }
1368
1369 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1370 LLVMValueRef src0, unsigned bitsize)
1371 {
1372 LLVMValueRef cmp, val, zero, one;
1373 LLVMTypeRef type;
1374
1375 if (bitsize == 32) {
1376 type = ctx->i32;
1377 zero = ctx->i32_0;
1378 one = ctx->i32_1;
1379 } else {
1380 type = ctx->i64;
1381 zero = ctx->i64_0;
1382 one = ctx->i64_1;
1383 }
1384
1385 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1386 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1387 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1388 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1389 return val;
1390 }
1391
1392 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1393 LLVMValueRef src0, unsigned bitsize)
1394 {
1395 LLVMTypeRef type;
1396 char *intr;
1397
1398 if (bitsize == 32) {
1399 intr = "llvm.floor.f32";
1400 type = ctx->f32;
1401 } else {
1402 intr = "llvm.floor.f64";
1403 type = ctx->f64;
1404 }
1405
1406 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1407 LLVMValueRef params[] = {
1408 fsrc0,
1409 };
1410 LLVMValueRef floor = ac_build_intrinsic(ctx, intr, type, params, 1,
1411 AC_FUNC_ATTR_READNONE);
1412 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1413 }
1414
1415 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1416 const char *intrin,
1417 LLVMValueRef src0, LLVMValueRef src1)
1418 {
1419 LLVMTypeRef ret_type;
1420 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1421 LLVMValueRef res;
1422 LLVMValueRef params[] = { src0, src1 };
1423 ret_type = LLVMStructTypeInContext(ctx->context, types,
1424 2, true);
1425
1426 res = ac_build_intrinsic(ctx, intrin, ret_type,
1427 params, 2, AC_FUNC_ATTR_READNONE);
1428
1429 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1430 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1431 return res;
1432 }
1433
1434 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1435 LLVMValueRef src0)
1436 {
1437 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1438 }
1439
1440 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1441 LLVMValueRef src0)
1442 {
1443 src0 = ac_to_float(ctx, src0);
1444 return LLVMBuildSExt(ctx->builder,
1445 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1446 ctx->i32, "");
1447 }
1448
1449 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1450 LLVMValueRef src0,
1451 unsigned bitsize)
1452 {
1453 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1454
1455 if (bitsize == 32)
1456 return result;
1457
1458 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1459 }
1460
1461 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1462 LLVMValueRef src0)
1463 {
1464 return LLVMBuildSExt(ctx->builder,
1465 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1466 ctx->i32, "");
1467 }
1468
1469 static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx,
1470 LLVMValueRef src0)
1471 {
1472 LLVMValueRef result;
1473 LLVMValueRef cond = NULL;
1474
1475 src0 = ac_to_float(ctx, src0);
1476 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1477
1478 if (ctx->chip_class >= VI) {
1479 LLVMValueRef args[2];
1480 /* Check if the result is a denormal - and flush to 0 if so. */
1481 args[0] = result;
1482 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1483 cond = ac_build_intrinsic(ctx, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1484 }
1485
1486 /* need to convert back up to f32 */
1487 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1488
1489 if (ctx->chip_class >= VI)
1490 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1491 else {
1492 /* for SI/CIK */
1493 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1494 * so compare the result and flush to 0 if it's smaller.
1495 */
1496 LLVMValueRef temp, cond2;
1497 temp = emit_intrin_1f_param(ctx, "llvm.fabs", ctx->f32, result);
1498 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1499 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1500 temp, "");
1501 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1502 temp, ctx->f32_0, "");
1503 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1504 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1505 }
1506 return result;
1507 }
1508
1509 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1510 LLVMValueRef src0, LLVMValueRef src1)
1511 {
1512 LLVMValueRef dst64, result;
1513 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1514 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1515
1516 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1517 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1518 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1519 return result;
1520 }
1521
1522 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1523 LLVMValueRef src0, LLVMValueRef src1)
1524 {
1525 LLVMValueRef dst64, result;
1526 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1527 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1528
1529 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1530 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1531 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1532 return result;
1533 }
1534
1535 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1536 bool is_signed,
1537 const LLVMValueRef srcs[3])
1538 {
1539 LLVMValueRef result;
1540 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1541
1542 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1543 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1544 return result;
1545 }
1546
1547 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1548 LLVMValueRef src0, LLVMValueRef src1,
1549 LLVMValueRef src2, LLVMValueRef src3)
1550 {
1551 LLVMValueRef bfi_args[3], result;
1552
1553 bfi_args[0] = LLVMBuildShl(ctx->builder,
1554 LLVMBuildSub(ctx->builder,
1555 LLVMBuildShl(ctx->builder,
1556 ctx->i32_1,
1557 src3, ""),
1558 ctx->i32_1, ""),
1559 src2, "");
1560 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1561 bfi_args[2] = src0;
1562
1563 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1564
1565 /* Calculate:
1566 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1567 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1568 */
1569 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1570 LLVMBuildAnd(ctx->builder, bfi_args[0],
1571 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1572
1573 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1574 return result;
1575 }
1576
1577 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1578 LLVMValueRef src0)
1579 {
1580 LLVMValueRef comp[2];
1581
1582 src0 = ac_to_float(ctx, src0);
1583 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1584 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1585
1586 return ac_build_cvt_pkrtz_f16(ctx, comp);
1587 }
1588
1589 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1590 LLVMValueRef src0)
1591 {
1592 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1593 LLVMValueRef temps[2], result, val;
1594 int i;
1595
1596 for (i = 0; i < 2; i++) {
1597 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1598 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1599 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1600 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1601 }
1602
1603 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1604 ctx->i32_0, "");
1605 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1606 ctx->i32_1, "");
1607 return result;
1608 }
1609
1610 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1611 nir_op op,
1612 LLVMValueRef src0)
1613 {
1614 unsigned mask;
1615 int idx;
1616 LLVMValueRef result;
1617
1618 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1619 mask = AC_TID_MASK_LEFT;
1620 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1621 mask = AC_TID_MASK_TOP;
1622 else
1623 mask = AC_TID_MASK_TOP_LEFT;
1624
1625 /* for DDX we want to next X pixel, DDY next Y pixel. */
1626 if (op == nir_op_fddx_fine ||
1627 op == nir_op_fddx_coarse ||
1628 op == nir_op_fddx)
1629 idx = 1;
1630 else
1631 idx = 2;
1632
1633 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1634 return result;
1635 }
1636
1637 /*
1638 * this takes an I,J coordinate pair,
1639 * and works out the X and Y derivatives.
1640 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1641 */
1642 static LLVMValueRef emit_ddxy_interp(
1643 struct ac_nir_context *ctx,
1644 LLVMValueRef interp_ij)
1645 {
1646 LLVMValueRef result[4], a;
1647 unsigned i;
1648
1649 for (i = 0; i < 2; i++) {
1650 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1651 LLVMConstInt(ctx->ac.i32, i, false), "");
1652 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1653 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1654 }
1655 return ac_build_gather_values(&ctx->ac, result, 4);
1656 }
1657
1658 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1659 {
1660 LLVMValueRef src[4], result = NULL;
1661 unsigned num_components = instr->dest.dest.ssa.num_components;
1662 unsigned src_components;
1663 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1664
1665 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1666 switch (instr->op) {
1667 case nir_op_vec2:
1668 case nir_op_vec3:
1669 case nir_op_vec4:
1670 src_components = 1;
1671 break;
1672 case nir_op_pack_half_2x16:
1673 src_components = 2;
1674 break;
1675 case nir_op_unpack_half_2x16:
1676 src_components = 1;
1677 break;
1678 default:
1679 src_components = num_components;
1680 break;
1681 }
1682 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1683 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1684
1685 switch (instr->op) {
1686 case nir_op_fmov:
1687 case nir_op_imov:
1688 result = src[0];
1689 break;
1690 case nir_op_fneg:
1691 src[0] = ac_to_float(&ctx->ac, src[0]);
1692 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1693 break;
1694 case nir_op_ineg:
1695 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1696 break;
1697 case nir_op_inot:
1698 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1699 break;
1700 case nir_op_iadd:
1701 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1702 break;
1703 case nir_op_fadd:
1704 src[0] = ac_to_float(&ctx->ac, src[0]);
1705 src[1] = ac_to_float(&ctx->ac, src[1]);
1706 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1707 break;
1708 case nir_op_fsub:
1709 src[0] = ac_to_float(&ctx->ac, src[0]);
1710 src[1] = ac_to_float(&ctx->ac, src[1]);
1711 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1712 break;
1713 case nir_op_isub:
1714 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1715 break;
1716 case nir_op_imul:
1717 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1718 break;
1719 case nir_op_imod:
1720 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1721 break;
1722 case nir_op_umod:
1723 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1724 break;
1725 case nir_op_fmod:
1726 src[0] = ac_to_float(&ctx->ac, src[0]);
1727 src[1] = ac_to_float(&ctx->ac, src[1]);
1728 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1729 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1730 ac_to_float_type(&ctx->ac, def_type), result);
1731 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1732 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1733 break;
1734 case nir_op_frem:
1735 src[0] = ac_to_float(&ctx->ac, src[0]);
1736 src[1] = ac_to_float(&ctx->ac, src[1]);
1737 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1738 break;
1739 case nir_op_irem:
1740 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1741 break;
1742 case nir_op_idiv:
1743 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1744 break;
1745 case nir_op_udiv:
1746 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1747 break;
1748 case nir_op_fmul:
1749 src[0] = ac_to_float(&ctx->ac, src[0]);
1750 src[1] = ac_to_float(&ctx->ac, src[1]);
1751 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1752 break;
1753 case nir_op_frcp:
1754 src[0] = ac_to_float(&ctx->ac, src[0]);
1755 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1756 src[0]);
1757 break;
1758 case nir_op_iand:
1759 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1760 break;
1761 case nir_op_ior:
1762 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1763 break;
1764 case nir_op_ixor:
1765 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1766 break;
1767 case nir_op_ishl:
1768 result = LLVMBuildShl(ctx->ac.builder, src[0],
1769 LLVMBuildZExt(ctx->ac.builder, src[1],
1770 LLVMTypeOf(src[0]), ""),
1771 "");
1772 break;
1773 case nir_op_ishr:
1774 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1775 LLVMBuildZExt(ctx->ac.builder, src[1],
1776 LLVMTypeOf(src[0]), ""),
1777 "");
1778 break;
1779 case nir_op_ushr:
1780 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1781 LLVMBuildZExt(ctx->ac.builder, src[1],
1782 LLVMTypeOf(src[0]), ""),
1783 "");
1784 break;
1785 case nir_op_ilt:
1786 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1787 break;
1788 case nir_op_ine:
1789 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1790 break;
1791 case nir_op_ieq:
1792 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1793 break;
1794 case nir_op_ige:
1795 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1796 break;
1797 case nir_op_ult:
1798 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1799 break;
1800 case nir_op_uge:
1801 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1802 break;
1803 case nir_op_feq:
1804 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1805 break;
1806 case nir_op_fne:
1807 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1808 break;
1809 case nir_op_flt:
1810 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1811 break;
1812 case nir_op_fge:
1813 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1814 break;
1815 case nir_op_fabs:
1816 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1817 ac_to_float_type(&ctx->ac, def_type), src[0]);
1818 break;
1819 case nir_op_iabs:
1820 result = emit_iabs(&ctx->ac, src[0]);
1821 break;
1822 case nir_op_imax:
1823 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1824 break;
1825 case nir_op_imin:
1826 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1827 break;
1828 case nir_op_umax:
1829 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1830 break;
1831 case nir_op_umin:
1832 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1833 break;
1834 case nir_op_isign:
1835 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1836 break;
1837 case nir_op_fsign:
1838 src[0] = ac_to_float(&ctx->ac, src[0]);
1839 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1840 break;
1841 case nir_op_ffloor:
1842 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1843 ac_to_float_type(&ctx->ac, def_type), src[0]);
1844 break;
1845 case nir_op_ftrunc:
1846 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1847 ac_to_float_type(&ctx->ac, def_type), src[0]);
1848 break;
1849 case nir_op_fceil:
1850 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1851 ac_to_float_type(&ctx->ac, def_type), src[0]);
1852 break;
1853 case nir_op_fround_even:
1854 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1855 ac_to_float_type(&ctx->ac, def_type),src[0]);
1856 break;
1857 case nir_op_ffract:
1858 result = emit_ffract(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1859 break;
1860 case nir_op_fsin:
1861 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1862 ac_to_float_type(&ctx->ac, def_type), src[0]);
1863 break;
1864 case nir_op_fcos:
1865 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1866 ac_to_float_type(&ctx->ac, def_type), src[0]);
1867 break;
1868 case nir_op_fsqrt:
1869 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1870 ac_to_float_type(&ctx->ac, def_type), src[0]);
1871 break;
1872 case nir_op_fexp2:
1873 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1874 ac_to_float_type(&ctx->ac, def_type), src[0]);
1875 break;
1876 case nir_op_flog2:
1877 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1878 ac_to_float_type(&ctx->ac, def_type), src[0]);
1879 break;
1880 case nir_op_frsq:
1881 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1882 ac_to_float_type(&ctx->ac, def_type), src[0]);
1883 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1884 result);
1885 break;
1886 case nir_op_fpow:
1887 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1888 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1889 break;
1890 case nir_op_fmax:
1891 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1892 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1893 if (ctx->ac.chip_class < GFX9 &&
1894 instr->dest.dest.ssa.bit_size == 32) {
1895 /* Only pre-GFX9 chips do not flush denorms. */
1896 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1897 ac_to_float_type(&ctx->ac, def_type),
1898 result);
1899 }
1900 break;
1901 case nir_op_fmin:
1902 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1903 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1904 if (ctx->ac.chip_class < GFX9 &&
1905 instr->dest.dest.ssa.bit_size == 32) {
1906 /* Only pre-GFX9 chips do not flush denorms. */
1907 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1908 ac_to_float_type(&ctx->ac, def_type),
1909 result);
1910 }
1911 break;
1912 case nir_op_ffma:
1913 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1914 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1915 break;
1916 case nir_op_ibitfield_extract:
1917 result = emit_bitfield_extract(&ctx->ac, true, src);
1918 break;
1919 case nir_op_ubitfield_extract:
1920 result = emit_bitfield_extract(&ctx->ac, false, src);
1921 break;
1922 case nir_op_bitfield_insert:
1923 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1924 break;
1925 case nir_op_bitfield_reverse:
1926 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1927 break;
1928 case nir_op_bit_count:
1929 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1930 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1931 else {
1932 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1933 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1934 }
1935 break;
1936 case nir_op_vec2:
1937 case nir_op_vec3:
1938 case nir_op_vec4:
1939 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1940 src[i] = ac_to_integer(&ctx->ac, src[i]);
1941 result = ac_build_gather_values(&ctx->ac, src, num_components);
1942 break;
1943 case nir_op_f2i32:
1944 case nir_op_f2i64:
1945 src[0] = ac_to_float(&ctx->ac, src[0]);
1946 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1947 break;
1948 case nir_op_f2u32:
1949 case nir_op_f2u64:
1950 src[0] = ac_to_float(&ctx->ac, src[0]);
1951 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1952 break;
1953 case nir_op_i2f32:
1954 case nir_op_i2f64:
1955 src[0] = ac_to_integer(&ctx->ac, src[0]);
1956 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1957 break;
1958 case nir_op_u2f32:
1959 case nir_op_u2f64:
1960 src[0] = ac_to_integer(&ctx->ac, src[0]);
1961 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1962 break;
1963 case nir_op_f2f64:
1964 src[0] = ac_to_float(&ctx->ac, src[0]);
1965 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1966 break;
1967 case nir_op_f2f32:
1968 src[0] = ac_to_float(&ctx->ac, src[0]);
1969 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1970 break;
1971 case nir_op_u2u32:
1972 case nir_op_u2u64:
1973 src[0] = ac_to_integer(&ctx->ac, src[0]);
1974 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1975 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1976 else
1977 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1978 break;
1979 case nir_op_i2i32:
1980 case nir_op_i2i64:
1981 src[0] = ac_to_integer(&ctx->ac, src[0]);
1982 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1983 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1984 else
1985 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1986 break;
1987 case nir_op_bcsel:
1988 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1989 break;
1990 case nir_op_find_lsb:
1991 src[0] = ac_to_integer(&ctx->ac, src[0]);
1992 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1993 break;
1994 case nir_op_ufind_msb:
1995 src[0] = ac_to_integer(&ctx->ac, src[0]);
1996 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1997 break;
1998 case nir_op_ifind_msb:
1999 src[0] = ac_to_integer(&ctx->ac, src[0]);
2000 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
2001 break;
2002 case nir_op_uadd_carry:
2003 src[0] = ac_to_integer(&ctx->ac, src[0]);
2004 src[1] = ac_to_integer(&ctx->ac, src[1]);
2005 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
2006 break;
2007 case nir_op_usub_borrow:
2008 src[0] = ac_to_integer(&ctx->ac, src[0]);
2009 src[1] = ac_to_integer(&ctx->ac, src[1]);
2010 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
2011 break;
2012 case nir_op_b2f:
2013 result = emit_b2f(&ctx->ac, src[0]);
2014 break;
2015 case nir_op_f2b:
2016 result = emit_f2b(&ctx->ac, src[0]);
2017 break;
2018 case nir_op_b2i:
2019 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2020 break;
2021 case nir_op_i2b:
2022 src[0] = ac_to_integer(&ctx->ac, src[0]);
2023 result = emit_i2b(&ctx->ac, src[0]);
2024 break;
2025 case nir_op_fquantize2f16:
2026 result = emit_f2f16(&ctx->ac, src[0]);
2027 break;
2028 case nir_op_umul_high:
2029 src[0] = ac_to_integer(&ctx->ac, src[0]);
2030 src[1] = ac_to_integer(&ctx->ac, src[1]);
2031 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2032 break;
2033 case nir_op_imul_high:
2034 src[0] = ac_to_integer(&ctx->ac, src[0]);
2035 src[1] = ac_to_integer(&ctx->ac, src[1]);
2036 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2037 break;
2038 case nir_op_pack_half_2x16:
2039 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2040 break;
2041 case nir_op_unpack_half_2x16:
2042 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2043 break;
2044 case nir_op_fddx:
2045 case nir_op_fddy:
2046 case nir_op_fddx_fine:
2047 case nir_op_fddy_fine:
2048 case nir_op_fddx_coarse:
2049 case nir_op_fddy_coarse:
2050 result = emit_ddxy(ctx, instr->op, src[0]);
2051 break;
2052
2053 case nir_op_unpack_64_2x32_split_x: {
2054 assert(ac_get_llvm_num_components(src[0]) == 1);
2055 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2056 ctx->ac.v2i32,
2057 "");
2058 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2059 ctx->ac.i32_0, "");
2060 break;
2061 }
2062
2063 case nir_op_unpack_64_2x32_split_y: {
2064 assert(ac_get_llvm_num_components(src[0]) == 1);
2065 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2066 ctx->ac.v2i32,
2067 "");
2068 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2069 ctx->ac.i32_1, "");
2070 break;
2071 }
2072
2073 case nir_op_pack_64_2x32_split: {
2074 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2075 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2076 src[0], ctx->ac.i32_0, "");
2077 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2078 src[1], ctx->ac.i32_1, "");
2079 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2080 break;
2081 }
2082
2083 default:
2084 fprintf(stderr, "Unknown NIR alu instr: ");
2085 nir_print_instr(&instr->instr, stderr);
2086 fprintf(stderr, "\n");
2087 abort();
2088 }
2089
2090 if (result) {
2091 assert(instr->dest.dest.is_ssa);
2092 result = ac_to_integer(&ctx->ac, result);
2093 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2094 result);
2095 }
2096 }
2097
2098 static void visit_load_const(struct ac_nir_context *ctx,
2099 const nir_load_const_instr *instr)
2100 {
2101 LLVMValueRef values[4], value = NULL;
2102 LLVMTypeRef element_type =
2103 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2104
2105 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2106 switch (instr->def.bit_size) {
2107 case 32:
2108 values[i] = LLVMConstInt(element_type,
2109 instr->value.u32[i], false);
2110 break;
2111 case 64:
2112 values[i] = LLVMConstInt(element_type,
2113 instr->value.u64[i], false);
2114 break;
2115 default:
2116 fprintf(stderr,
2117 "unsupported nir load_const bit_size: %d\n",
2118 instr->def.bit_size);
2119 abort();
2120 }
2121 }
2122 if (instr->def.num_components > 1) {
2123 value = LLVMConstVector(values, instr->def.num_components);
2124 } else
2125 value = values[0];
2126
2127 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2128 }
2129
2130 static LLVMValueRef cast_ptr(struct ac_llvm_context *ctx, LLVMValueRef ptr,
2131 LLVMTypeRef type)
2132 {
2133 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2134 return LLVMBuildBitCast(ctx->builder, ptr,
2135 LLVMPointerType(type, addr_space), "");
2136 }
2137
2138 static LLVMValueRef
2139 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2140 {
2141 LLVMValueRef size =
2142 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2143 LLVMConstInt(ctx->ac.i32, 2, false), "");
2144
2145 /* VI only */
2146 if (ctx->ac.chip_class == VI && in_elements) {
2147 /* On VI, the descriptor contains the size in bytes,
2148 * but TXQ must return the size in elements.
2149 * The stride is always non-zero for resources using TXQ.
2150 */
2151 LLVMValueRef stride =
2152 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2153 ctx->ac.i32_1, "");
2154 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2155 LLVMConstInt(ctx->ac.i32, 16, false), "");
2156 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2157 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2158
2159 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2160 }
2161 return size;
2162 }
2163
2164 /**
2165 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2166 * intrinsic names).
2167 */
2168 static void build_int_type_name(
2169 LLVMTypeRef type,
2170 char *buf, unsigned bufsize)
2171 {
2172 assert(bufsize >= 6);
2173
2174 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2175 snprintf(buf, bufsize, "v%ui32",
2176 LLVMGetVectorSize(type));
2177 else
2178 strcpy(buf, "i32");
2179 }
2180
2181 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2182 struct ac_image_args *args,
2183 const nir_tex_instr *instr)
2184 {
2185 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2186 LLVMValueRef coord = args->addr;
2187 LLVMValueRef half_texel[2];
2188 LLVMValueRef compare_cube_wa = NULL;
2189 LLVMValueRef result;
2190 int c;
2191 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2192
2193 //TODO Rect
2194 {
2195 struct ac_image_args txq_args = { 0 };
2196
2197 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2198 txq_args.opcode = ac_image_get_resinfo;
2199 txq_args.dmask = 0xf;
2200 txq_args.addr = ctx->i32_0;
2201 txq_args.resource = args->resource;
2202 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2203
2204 for (c = 0; c < 2; c++) {
2205 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2206 LLVMConstInt(ctx->i32, c, false), "");
2207 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2208 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2209 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2210 LLVMConstReal(ctx->f32, -0.5), "");
2211 }
2212 }
2213
2214 LLVMValueRef orig_coords = args->addr;
2215
2216 for (c = 0; c < 2; c++) {
2217 LLVMValueRef tmp;
2218 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2219 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2220 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2221 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2222 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2223 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2224 }
2225
2226
2227 /*
2228 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2229 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2230 * workaround by sampling using a scaled type and converting.
2231 * This is taken from amdgpu-pro shaders.
2232 */
2233 /* NOTE this produces some ugly code compared to amdgpu-pro,
2234 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2235 * and then reads them back. -pro generates two selects,
2236 * one s_cmp for the descriptor rewriting
2237 * one v_cmp for the coordinate and result changes.
2238 */
2239 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2240 LLVMValueRef tmp, tmp2;
2241
2242 /* workaround 8/8/8/8 uint/sint cube gather bug */
2243 /* first detect it then change to a scaled read and f2i */
2244 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2245 tmp2 = tmp;
2246
2247 /* extract the DATA_FORMAT */
2248 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2249 LLVMConstInt(ctx->i32, 6, false), false);
2250
2251 /* is the DATA_FORMAT == 8_8_8_8 */
2252 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2253
2254 if (stype == GLSL_TYPE_UINT)
2255 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2256 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2257 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2258 else
2259 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2260 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2261 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2262
2263 /* replace the NUM FORMAT in the descriptor */
2264 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2265 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2266
2267 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2268
2269 /* don't modify the coordinates for this case */
2270 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2271 }
2272 args->addr = coord;
2273 result = ac_build_image_opcode(ctx, args);
2274
2275 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2276 LLVMValueRef tmp, tmp2;
2277
2278 /* if the cube workaround is in place, f2i the result. */
2279 for (c = 0; c < 4; c++) {
2280 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2281 if (stype == GLSL_TYPE_UINT)
2282 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2283 else
2284 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2285 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2286 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2287 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2288 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2289 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2290 }
2291 }
2292 return result;
2293 }
2294
2295 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2296 const nir_tex_instr *instr,
2297 bool lod_is_zero,
2298 struct ac_image_args *args)
2299 {
2300 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2301 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2302
2303 return ac_build_buffer_load_format(&ctx->ac,
2304 args->resource,
2305 args->addr,
2306 ctx->ac.i32_0,
2307 util_last_bit(mask),
2308 false, true);
2309 }
2310
2311 args->opcode = ac_image_sample;
2312 args->compare = instr->is_shadow;
2313
2314 switch (instr->op) {
2315 case nir_texop_txf:
2316 case nir_texop_txf_ms:
2317 case nir_texop_samples_identical:
2318 args->opcode = lod_is_zero ||
2319 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2320 ac_image_load : ac_image_load_mip;
2321 args->compare = false;
2322 args->offset = false;
2323 break;
2324 case nir_texop_txb:
2325 args->bias = true;
2326 break;
2327 case nir_texop_txl:
2328 if (lod_is_zero)
2329 args->level_zero = true;
2330 else
2331 args->lod = true;
2332 break;
2333 case nir_texop_txs:
2334 case nir_texop_query_levels:
2335 args->opcode = ac_image_get_resinfo;
2336 break;
2337 case nir_texop_tex:
2338 if (ctx->stage != MESA_SHADER_FRAGMENT)
2339 args->level_zero = true;
2340 break;
2341 case nir_texop_txd:
2342 args->deriv = true;
2343 break;
2344 case nir_texop_tg4:
2345 args->opcode = ac_image_gather4;
2346 args->level_zero = true;
2347 break;
2348 case nir_texop_lod:
2349 args->opcode = ac_image_get_lod;
2350 args->compare = false;
2351 args->offset = false;
2352 break;
2353 default:
2354 break;
2355 }
2356
2357 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2358 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2359 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2360 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2361 }
2362 }
2363 return ac_build_image_opcode(&ctx->ac, args);
2364 }
2365
2366 static LLVMValueRef
2367 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2368 unsigned desc_set, unsigned binding)
2369 {
2370 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2371 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2372 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2373 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2374 unsigned base_offset = layout->binding[binding].offset;
2375 LLVMValueRef offset, stride;
2376
2377 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2378 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2379 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2380 layout->binding[binding].dynamic_offset_offset;
2381 desc_ptr = ctx->abi.push_constants;
2382 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2383 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2384 } else
2385 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2386
2387 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2388 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
2389 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
2390
2391 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2392 desc_ptr = cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
2393 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2394
2395 return desc_ptr;
2396 }
2397
2398 static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
2399 nir_intrinsic_instr *instr)
2400 {
2401 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2402 LLVMValueRef index = get_src(ctx, instr->src[1]);
2403
2404 LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
2405 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2406 return result;
2407 }
2408
2409 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
2410 nir_intrinsic_instr *instr)
2411 {
2412 LLVMValueRef ptr, addr;
2413
2414 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2415 addr = LLVMBuildAdd(ctx->ac.builder, addr,
2416 get_src(ctx, instr->src[0]), "");
2417
2418 ptr = ac_build_gep0(&ctx->ac, ctx->abi->push_constants, addr);
2419 ptr = cast_ptr(&ctx->ac, ptr, get_def_type(ctx, &instr->dest.ssa));
2420
2421 return LLVMBuildLoad(ctx->ac.builder, ptr, "");
2422 }
2423
2424 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2425 const nir_intrinsic_instr *instr)
2426 {
2427 LLVMValueRef index = get_src(ctx, instr->src[0]);
2428
2429 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2430 }
2431
2432 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2433 {
2434 uint32_t new_mask = 0;
2435 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2436 if (mask & (1u << i))
2437 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2438 return new_mask;
2439 }
2440
2441 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2442 unsigned start, unsigned count)
2443 {
2444 LLVMTypeRef type = LLVMTypeOf(src);
2445
2446 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2447 assert(start == 0);
2448 assert(count == 1);
2449 return src;
2450 }
2451
2452 unsigned src_elements = LLVMGetVectorSize(type);
2453 assert(start < src_elements);
2454 assert(start + count <= src_elements);
2455
2456 if (start == 0 && count == src_elements)
2457 return src;
2458
2459 if (count == 1)
2460 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2461
2462 assert(count <= 8);
2463 LLVMValueRef indices[8];
2464 for (unsigned i = 0; i < count; ++i)
2465 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2466
2467 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2468 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2469 }
2470
2471 static void visit_store_ssbo(struct ac_nir_context *ctx,
2472 nir_intrinsic_instr *instr)
2473 {
2474 const char *store_name;
2475 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2476 LLVMTypeRef data_type = ctx->ac.f32;
2477 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2478 int components_32bit = elem_size_mult * instr->num_components;
2479 unsigned writemask = nir_intrinsic_write_mask(instr);
2480 LLVMValueRef base_data, base_offset;
2481 LLVMValueRef params[6];
2482
2483 params[1] = ctx->abi->load_ssbo(ctx->abi,
2484 get_src(ctx, instr->src[1]), true);
2485 params[2] = ctx->ac.i32_0; /* vindex */
2486 params[4] = ctx->ac.i1false; /* glc */
2487 params[5] = ctx->ac.i1false; /* slc */
2488
2489 if (components_32bit > 1)
2490 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2491
2492 writemask = widen_mask(writemask, elem_size_mult);
2493
2494 base_data = ac_to_float(&ctx->ac, src_data);
2495 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2496 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2497 data_type, "");
2498 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2499 while (writemask) {
2500 int start, count;
2501 LLVMValueRef data;
2502 LLVMValueRef offset;
2503
2504 u_bit_scan_consecutive_range(&writemask, &start, &count);
2505
2506 /* Due to an LLVM limitation, split 3-element writes
2507 * into a 2-element and a 1-element write. */
2508 if (count == 3) {
2509 writemask |= 1 << (start + 2);
2510 count = 2;
2511 }
2512
2513 if (count > 4) {
2514 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2515 count = 4;
2516 }
2517
2518 if (count == 4) {
2519 store_name = "llvm.amdgcn.buffer.store.v4f32";
2520 } else if (count == 2) {
2521 store_name = "llvm.amdgcn.buffer.store.v2f32";
2522
2523 } else {
2524 assert(count == 1);
2525 store_name = "llvm.amdgcn.buffer.store.f32";
2526 }
2527 data = extract_vector_range(&ctx->ac, base_data, start, count);
2528
2529 offset = base_offset;
2530 if (start != 0) {
2531 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2532 }
2533 params[0] = data;
2534 params[3] = offset;
2535 ac_build_intrinsic(&ctx->ac, store_name,
2536 ctx->ac.voidt, params, 6, 0);
2537 }
2538 }
2539
2540 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2541 const nir_intrinsic_instr *instr)
2542 {
2543 const char *name;
2544 LLVMValueRef params[6];
2545 int arg_count = 0;
2546
2547 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2548 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2549 }
2550 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2551 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2552 get_src(ctx, instr->src[0]),
2553 true);
2554 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2555 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2556 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2557
2558 switch (instr->intrinsic) {
2559 case nir_intrinsic_ssbo_atomic_add:
2560 name = "llvm.amdgcn.buffer.atomic.add";
2561 break;
2562 case nir_intrinsic_ssbo_atomic_imin:
2563 name = "llvm.amdgcn.buffer.atomic.smin";
2564 break;
2565 case nir_intrinsic_ssbo_atomic_umin:
2566 name = "llvm.amdgcn.buffer.atomic.umin";
2567 break;
2568 case nir_intrinsic_ssbo_atomic_imax:
2569 name = "llvm.amdgcn.buffer.atomic.smax";
2570 break;
2571 case nir_intrinsic_ssbo_atomic_umax:
2572 name = "llvm.amdgcn.buffer.atomic.umax";
2573 break;
2574 case nir_intrinsic_ssbo_atomic_and:
2575 name = "llvm.amdgcn.buffer.atomic.and";
2576 break;
2577 case nir_intrinsic_ssbo_atomic_or:
2578 name = "llvm.amdgcn.buffer.atomic.or";
2579 break;
2580 case nir_intrinsic_ssbo_atomic_xor:
2581 name = "llvm.amdgcn.buffer.atomic.xor";
2582 break;
2583 case nir_intrinsic_ssbo_atomic_exchange:
2584 name = "llvm.amdgcn.buffer.atomic.swap";
2585 break;
2586 case nir_intrinsic_ssbo_atomic_comp_swap:
2587 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2588 break;
2589 default:
2590 abort();
2591 }
2592
2593 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2594 }
2595
2596 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2597 const nir_intrinsic_instr *instr)
2598 {
2599 LLVMValueRef results[2];
2600 int load_components;
2601 int num_components = instr->num_components;
2602 if (instr->dest.ssa.bit_size == 64)
2603 num_components *= 2;
2604
2605 for (int i = 0; i < num_components; i += load_components) {
2606 load_components = MIN2(num_components - i, 4);
2607 const char *load_name;
2608 LLVMTypeRef data_type = ctx->ac.f32;
2609 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2610 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2611
2612 if (load_components == 3)
2613 data_type = LLVMVectorType(ctx->ac.f32, 4);
2614 else if (load_components > 1)
2615 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2616
2617 if (load_components >= 3)
2618 load_name = "llvm.amdgcn.buffer.load.v4f32";
2619 else if (load_components == 2)
2620 load_name = "llvm.amdgcn.buffer.load.v2f32";
2621 else if (load_components == 1)
2622 load_name = "llvm.amdgcn.buffer.load.f32";
2623 else
2624 unreachable("unhandled number of components");
2625
2626 LLVMValueRef params[] = {
2627 ctx->abi->load_ssbo(ctx->abi,
2628 get_src(ctx, instr->src[0]),
2629 false),
2630 ctx->ac.i32_0,
2631 offset,
2632 ctx->ac.i1false,
2633 ctx->ac.i1false,
2634 };
2635
2636 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2637 }
2638
2639 assume(results[0]);
2640 LLVMValueRef ret = results[0];
2641 if (num_components > 4 || num_components == 3) {
2642 LLVMValueRef masks[] = {
2643 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2644 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2645 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2646 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2647 };
2648
2649 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2650 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2651 results[num_components > 4 ? 1 : 0], swizzle, "");
2652 }
2653
2654 return LLVMBuildBitCast(ctx->ac.builder, ret,
2655 get_def_type(ctx, &instr->dest.ssa), "");
2656 }
2657
2658 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2659 const nir_intrinsic_instr *instr)
2660 {
2661 LLVMValueRef ret;
2662 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2663 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2664 int num_components = instr->num_components;
2665
2666 if (ctx->abi->load_ubo)
2667 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2668
2669 if (instr->dest.ssa.bit_size == 64)
2670 num_components *= 2;
2671
2672 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2673 NULL, 0, false, false, true, true);
2674 ret = trim_vector(&ctx->ac, ret, num_components);
2675 return LLVMBuildBitCast(ctx->ac.builder, ret,
2676 get_def_type(ctx, &instr->dest.ssa), "");
2677 }
2678
2679 static void
2680 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2681 bool vs_in, unsigned *vertex_index_out,
2682 LLVMValueRef *vertex_index_ref,
2683 unsigned *const_out, LLVMValueRef *indir_out)
2684 {
2685 unsigned const_offset = 0;
2686 nir_deref *tail = &deref->deref;
2687 LLVMValueRef offset = NULL;
2688
2689 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2690 tail = tail->child;
2691 nir_deref_array *deref_array = nir_deref_as_array(tail);
2692 if (vertex_index_out)
2693 *vertex_index_out = deref_array->base_offset;
2694
2695 if (vertex_index_ref) {
2696 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2697 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2698 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2699 }
2700 *vertex_index_ref = vtx;
2701 }
2702 }
2703
2704 if (deref->var->data.compact) {
2705 assert(tail->child->deref_type == nir_deref_type_array);
2706 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2707 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2708 /* We always lower indirect dereferences for "compact" array vars. */
2709 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2710
2711 const_offset = deref_array->base_offset;
2712 goto out;
2713 }
2714
2715 while (tail->child != NULL) {
2716 const struct glsl_type *parent_type = tail->type;
2717 tail = tail->child;
2718
2719 if (tail->deref_type == nir_deref_type_array) {
2720 nir_deref_array *deref_array = nir_deref_as_array(tail);
2721 LLVMValueRef index, stride, local_offset;
2722 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2723
2724 const_offset += size * deref_array->base_offset;
2725 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2726 continue;
2727
2728 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2729 index = get_src(ctx, deref_array->indirect);
2730 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2731 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2732
2733 if (offset)
2734 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2735 else
2736 offset = local_offset;
2737 } else if (tail->deref_type == nir_deref_type_struct) {
2738 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2739
2740 for (unsigned i = 0; i < deref_struct->index; i++) {
2741 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2742 const_offset += glsl_count_attribute_slots(ft, vs_in);
2743 }
2744 } else
2745 unreachable("unsupported deref type");
2746
2747 }
2748 out:
2749 if (const_offset && offset)
2750 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2751 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2752 "");
2753
2754 *const_out = const_offset;
2755 *indir_out = offset;
2756 }
2757
2758
2759 /* The offchip buffer layout for TCS->TES is
2760 *
2761 * - attribute 0 of patch 0 vertex 0
2762 * - attribute 0 of patch 0 vertex 1
2763 * - attribute 0 of patch 0 vertex 2
2764 * ...
2765 * - attribute 0 of patch 1 vertex 0
2766 * - attribute 0 of patch 1 vertex 1
2767 * ...
2768 * - attribute 1 of patch 0 vertex 0
2769 * - attribute 1 of patch 0 vertex 1
2770 * ...
2771 * - per patch attribute 0 of patch 0
2772 * - per patch attribute 0 of patch 1
2773 * ...
2774 *
2775 * Note that every attribute has 4 components.
2776 */
2777 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
2778 LLVMValueRef vertex_index,
2779 LLVMValueRef param_index)
2780 {
2781 LLVMValueRef base_addr, vertices_per_patch, num_patches;
2782 LLVMValueRef param_stride, constant16;
2783 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2784
2785 vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
2786 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2787
2788 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2789 if (vertex_index) {
2790 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2791 vertices_per_patch, "");
2792
2793 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2794 vertex_index, "");
2795
2796 param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
2797 num_patches, "");
2798 } else {
2799 base_addr = rel_patch_id;
2800 param_stride = num_patches;
2801 }
2802
2803 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2804 LLVMBuildMul(ctx->ac.builder, param_index,
2805 param_stride, ""), "");
2806
2807 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
2808
2809 if (!vertex_index) {
2810 LLVMValueRef patch_data_offset =
2811 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2812
2813 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2814 patch_data_offset, "");
2815 }
2816 return base_addr;
2817 }
2818
2819 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
2820 unsigned param,
2821 unsigned const_index,
2822 bool is_compact,
2823 LLVMValueRef vertex_index,
2824 LLVMValueRef indir_index)
2825 {
2826 LLVMValueRef param_index;
2827
2828 if (indir_index)
2829 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
2830 indir_index, "");
2831 else {
2832 if (const_index && !is_compact)
2833 param += const_index;
2834 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2835 }
2836 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2837 }
2838
2839 static void
2840 mark_tess_output(struct radv_shader_context *ctx,
2841 bool is_patch, uint32_t param)
2842
2843 {
2844 if (is_patch) {
2845 ctx->tess_patch_outputs_written |= (1ull << param);
2846 } else
2847 ctx->tess_outputs_written |= (1ull << param);
2848 }
2849
2850 static LLVMValueRef
2851 get_dw_address(struct radv_shader_context *ctx,
2852 LLVMValueRef dw_addr,
2853 unsigned param,
2854 unsigned const_index,
2855 bool compact_const_index,
2856 LLVMValueRef vertex_index,
2857 LLVMValueRef stride,
2858 LLVMValueRef indir_index)
2859
2860 {
2861
2862 if (vertex_index) {
2863 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2864 LLVMBuildMul(ctx->ac.builder,
2865 vertex_index,
2866 stride, ""), "");
2867 }
2868
2869 if (indir_index)
2870 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2871 LLVMBuildMul(ctx->ac.builder, indir_index,
2872 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2873 else if (const_index && !compact_const_index)
2874 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2875 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2876
2877 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2878 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2879
2880 if (const_index && compact_const_index)
2881 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2882 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2883 return dw_addr;
2884 }
2885
2886 static LLVMValueRef
2887 load_tcs_varyings(struct ac_shader_abi *abi,
2888 LLVMValueRef vertex_index,
2889 LLVMValueRef indir_index,
2890 unsigned const_index,
2891 unsigned location,
2892 unsigned driver_location,
2893 unsigned component,
2894 unsigned num_components,
2895 bool is_patch,
2896 bool is_compact,
2897 bool load_input)
2898 {
2899 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2900 LLVMValueRef dw_addr, stride;
2901 LLVMValueRef value[4], result;
2902 unsigned param = shader_io_get_unique_index(location);
2903
2904 if (load_input) {
2905 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2906 dw_addr = get_tcs_in_current_patch_offset(ctx);
2907 } else {
2908 if (!is_patch) {
2909 stride = get_tcs_out_vertex_stride(ctx);
2910 dw_addr = get_tcs_out_current_patch_offset(ctx);
2911 } else {
2912 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2913 stride = NULL;
2914 }
2915 }
2916
2917 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2918 indir_index);
2919
2920 for (unsigned i = 0; i < num_components + component; i++) {
2921 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2922 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2923 ctx->ac.i32_1, "");
2924 }
2925 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2926 return result;
2927 }
2928
2929 static void
2930 store_tcs_output(struct ac_shader_abi *abi,
2931 LLVMValueRef vertex_index,
2932 LLVMValueRef param_index,
2933 unsigned const_index,
2934 unsigned location,
2935 unsigned driver_location,
2936 LLVMValueRef src,
2937 unsigned component,
2938 bool is_patch,
2939 bool is_compact,
2940 unsigned writemask)
2941 {
2942 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2943 LLVMValueRef dw_addr;
2944 LLVMValueRef stride = NULL;
2945 LLVMValueRef buf_addr = NULL;
2946 unsigned param;
2947 bool store_lds = true;
2948
2949 if (is_patch) {
2950 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2951 store_lds = false;
2952 } else {
2953 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2954 store_lds = false;
2955 }
2956
2957 param = shader_io_get_unique_index(location);
2958 if (location == VARYING_SLOT_CLIP_DIST0 &&
2959 is_compact && const_index > 3) {
2960 const_index -= 3;
2961 param++;
2962 }
2963
2964 if (!is_patch) {
2965 stride = get_tcs_out_vertex_stride(ctx);
2966 dw_addr = get_tcs_out_current_patch_offset(ctx);
2967 } else {
2968 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2969 }
2970
2971 mark_tess_output(ctx, is_patch, param);
2972
2973 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2974 param_index);
2975 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2976 vertex_index, param_index);
2977
2978 bool is_tess_factor = false;
2979 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2980 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2981 is_tess_factor = true;
2982
2983 unsigned base = is_compact ? const_index : 0;
2984 for (unsigned chan = 0; chan < 8; chan++) {
2985 if (!(writemask & (1 << chan)))
2986 continue;
2987 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2988
2989 if (store_lds || is_tess_factor) {
2990 LLVMValueRef dw_addr_chan =
2991 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2992 LLVMConstInt(ctx->ac.i32, chan, false), "");
2993 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2994 }
2995
2996 if (!is_tess_factor && writemask != 0xF)
2997 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2998 buf_addr, ctx->oc_lds,
2999 4 * (base + chan), 1, 0, true, false);
3000 }
3001
3002 if (writemask == 0xF) {
3003 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
3004 buf_addr, ctx->oc_lds,
3005 (base * 4), 1, 0, true, false);
3006 }
3007 }
3008
3009 static LLVMValueRef
3010 load_tes_input(struct ac_shader_abi *abi,
3011 LLVMValueRef vertex_index,
3012 LLVMValueRef param_index,
3013 unsigned const_index,
3014 unsigned location,
3015 unsigned driver_location,
3016 unsigned component,
3017 unsigned num_components,
3018 bool is_patch,
3019 bool is_compact,
3020 bool load_input)
3021 {
3022 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3023 LLVMValueRef buf_addr;
3024 LLVMValueRef result;
3025 unsigned param = shader_io_get_unique_index(location);
3026
3027 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3028 const_index -= 3;
3029 param++;
3030 }
3031
3032 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3033 is_compact, vertex_index, param_index);
3034
3035 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3036 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
3037
3038 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3039 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3040 result = trim_vector(&ctx->ac, result, num_components);
3041 return result;
3042 }
3043
3044 static LLVMValueRef
3045 load_gs_input(struct ac_shader_abi *abi,
3046 unsigned location,
3047 unsigned driver_location,
3048 unsigned component,
3049 unsigned num_components,
3050 unsigned vertex_index,
3051 unsigned const_index,
3052 LLVMTypeRef type)
3053 {
3054 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3055 LLVMValueRef vtx_offset;
3056 unsigned param, vtx_offset_param;
3057 LLVMValueRef value[4], result;
3058
3059 vtx_offset_param = vertex_index;
3060 assert(vtx_offset_param < 6);
3061 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
3062 LLVMConstInt(ctx->ac.i32, 4, false), "");
3063
3064 param = shader_io_get_unique_index(location);
3065
3066 for (unsigned i = component; i < num_components + component; i++) {
3067 if (ctx->ac.chip_class >= GFX9) {
3068 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3069 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3070 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3071 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3072 } else {
3073 LLVMValueRef soffset =
3074 LLVMConstInt(ctx->ac.i32,
3075 (param * 4 + i + const_index) * 256,
3076 false);
3077
3078 value[i] = ac_build_buffer_load(&ctx->ac,
3079 ctx->esgs_ring, 1,
3080 ctx->ac.i32_0,
3081 vtx_offset, soffset,
3082 0, 1, 0, true, false);
3083
3084 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
3085 type, "");
3086 }
3087 }
3088 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3089 result = ac_to_integer(&ctx->ac, result);
3090 return result;
3091 }
3092
3093 static LLVMValueRef
3094 build_gep_for_deref(struct ac_nir_context *ctx,
3095 nir_deref_var *deref)
3096 {
3097 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3098 assert(entry->data);
3099 LLVMValueRef val = entry->data;
3100 nir_deref *tail = deref->deref.child;
3101 while (tail != NULL) {
3102 LLVMValueRef offset;
3103 switch (tail->deref_type) {
3104 case nir_deref_type_array: {
3105 nir_deref_array *array = nir_deref_as_array(tail);
3106 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3107 if (array->deref_array_type ==
3108 nir_deref_array_type_indirect) {
3109 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3110 get_src(ctx,
3111 array->indirect),
3112 "");
3113 }
3114 break;
3115 }
3116 case nir_deref_type_struct: {
3117 nir_deref_struct *deref_struct =
3118 nir_deref_as_struct(tail);
3119 offset = LLVMConstInt(ctx->ac.i32,
3120 deref_struct->index, 0);
3121 break;
3122 }
3123 default:
3124 unreachable("bad deref type");
3125 }
3126 val = ac_build_gep0(&ctx->ac, val, offset);
3127 tail = tail->child;
3128 }
3129 return val;
3130 }
3131
3132 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3133 nir_intrinsic_instr *instr,
3134 bool load_inputs)
3135 {
3136 LLVMValueRef result;
3137 LLVMValueRef vertex_index = NULL;
3138 LLVMValueRef indir_index = NULL;
3139 unsigned const_index = 0;
3140 unsigned location = instr->variables[0]->var->data.location;
3141 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3142 const bool is_patch = instr->variables[0]->var->data.patch;
3143 const bool is_compact = instr->variables[0]->var->data.compact;
3144
3145 get_deref_offset(ctx, instr->variables[0],
3146 false, NULL, is_patch ? NULL : &vertex_index,
3147 &const_index, &indir_index);
3148
3149 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3150 const_index, location, driver_location,
3151 instr->variables[0]->var->data.location_frac,
3152 instr->num_components,
3153 is_patch, is_compact, load_inputs);
3154 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3155 }
3156
3157 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3158 nir_intrinsic_instr *instr)
3159 {
3160 LLVMValueRef values[8];
3161 int idx = instr->variables[0]->var->data.driver_location;
3162 int ve = instr->dest.ssa.num_components;
3163 unsigned comp = instr->variables[0]->var->data.location_frac;
3164 LLVMValueRef indir_index;
3165 LLVMValueRef ret;
3166 unsigned const_index;
3167 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3168 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3169 instr->variables[0]->var->data.mode == nir_var_shader_in;
3170 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3171 &const_index, &indir_index);
3172
3173 if (instr->dest.ssa.bit_size == 64)
3174 ve *= 2;
3175
3176 switch (instr->variables[0]->var->data.mode) {
3177 case nir_var_shader_in:
3178 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3179 ctx->stage == MESA_SHADER_TESS_EVAL) {
3180 return load_tess_varyings(ctx, instr, true);
3181 }
3182
3183 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3184 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3185 LLVMValueRef indir_index;
3186 unsigned const_index, vertex_index;
3187 get_deref_offset(ctx, instr->variables[0],
3188 false, &vertex_index, NULL,
3189 &const_index, &indir_index);
3190
3191 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3192 instr->variables[0]->var->data.driver_location,
3193 instr->variables[0]->var->data.location_frac, ve,
3194 vertex_index, const_index, type);
3195 }
3196
3197 for (unsigned chan = comp; chan < ve + comp; chan++) {
3198 if (indir_index) {
3199 unsigned count = glsl_count_attribute_slots(
3200 instr->variables[0]->var->type,
3201 ctx->stage == MESA_SHADER_VERTEX);
3202 count -= chan / 4;
3203 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3204 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3205 stride, false, true);
3206
3207 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3208 tmp_vec,
3209 indir_index, "");
3210 } else
3211 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3212 }
3213 break;
3214 case nir_var_local:
3215 for (unsigned chan = 0; chan < ve; chan++) {
3216 if (indir_index) {
3217 unsigned count = glsl_count_attribute_slots(
3218 instr->variables[0]->var->type, false);
3219 count -= chan / 4;
3220 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3221 &ctx->ac, ctx->locals + idx + chan, count,
3222 stride, true, true);
3223
3224 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3225 tmp_vec,
3226 indir_index, "");
3227 } else {
3228 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3229 }
3230 }
3231 break;
3232 case nir_var_shared: {
3233 LLVMValueRef address = build_gep_for_deref(ctx,
3234 instr->variables[0]);
3235 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3236 return LLVMBuildBitCast(ctx->ac.builder, val,
3237 get_def_type(ctx, &instr->dest.ssa),
3238 "");
3239 }
3240 case nir_var_shader_out:
3241 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3242 return load_tess_varyings(ctx, instr, false);
3243 }
3244
3245 for (unsigned chan = comp; chan < ve + comp; chan++) {
3246 if (indir_index) {
3247 unsigned count = glsl_count_attribute_slots(
3248 instr->variables[0]->var->type, false);
3249 count -= chan / 4;
3250 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3251 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3252 stride, true, true);
3253
3254 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3255 tmp_vec,
3256 indir_index, "");
3257 } else {
3258 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3259 ctx->abi->outputs[idx + chan + const_index * stride],
3260 "");
3261 }
3262 }
3263 break;
3264 default:
3265 unreachable("unhandle variable mode");
3266 }
3267 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3268 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3269 }
3270
3271 static void
3272 visit_store_var(struct ac_nir_context *ctx,
3273 nir_intrinsic_instr *instr)
3274 {
3275 LLVMValueRef temp_ptr, value;
3276 int idx = instr->variables[0]->var->data.driver_location;
3277 unsigned comp = instr->variables[0]->var->data.location_frac;
3278 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3279 int writemask = instr->const_index[0] << comp;
3280 LLVMValueRef indir_index;
3281 unsigned const_index;
3282 get_deref_offset(ctx, instr->variables[0], false,
3283 NULL, NULL, &const_index, &indir_index);
3284
3285 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3286
3287 src = LLVMBuildBitCast(ctx->ac.builder, src,
3288 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3289 "");
3290
3291 writemask = widen_mask(writemask, 2);
3292 }
3293
3294 switch (instr->variables[0]->var->data.mode) {
3295 case nir_var_shader_out:
3296
3297 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3298 LLVMValueRef vertex_index = NULL;
3299 LLVMValueRef indir_index = NULL;
3300 unsigned const_index = 0;
3301 const unsigned location = instr->variables[0]->var->data.location;
3302 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3303 const unsigned comp = instr->variables[0]->var->data.location_frac;
3304 const bool is_patch = instr->variables[0]->var->data.patch;
3305 const bool is_compact = instr->variables[0]->var->data.compact;
3306
3307 get_deref_offset(ctx, instr->variables[0],
3308 false, NULL, is_patch ? NULL : &vertex_index,
3309 &const_index, &indir_index);
3310
3311 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3312 const_index, location, driver_location,
3313 src, comp, is_patch, is_compact, writemask);
3314 return;
3315 }
3316
3317 for (unsigned chan = 0; chan < 8; chan++) {
3318 int stride = 4;
3319 if (!(writemask & (1 << chan)))
3320 continue;
3321
3322 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3323
3324 if (instr->variables[0]->var->data.compact)
3325 stride = 1;
3326 if (indir_index) {
3327 unsigned count = glsl_count_attribute_slots(
3328 instr->variables[0]->var->type, false);
3329 count -= chan / 4;
3330 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3331 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3332 stride, true, true);
3333
3334 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3335 value, indir_index, "");
3336 build_store_values_extended(&ctx->ac, ctx->abi->outputs + idx + chan,
3337 count, stride, tmp_vec);
3338
3339 } else {
3340 temp_ptr = ctx->abi->outputs[idx + chan + const_index * stride];
3341
3342 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3343 }
3344 }
3345 break;
3346 case nir_var_local:
3347 for (unsigned chan = 0; chan < 8; chan++) {
3348 if (!(writemask & (1 << chan)))
3349 continue;
3350
3351 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3352 if (indir_index) {
3353 unsigned count = glsl_count_attribute_slots(
3354 instr->variables[0]->var->type, false);
3355 count -= chan / 4;
3356 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3357 &ctx->ac, ctx->locals + idx + chan, count,
3358 4, true, true);
3359
3360 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3361 value, indir_index, "");
3362 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3363 count, 4, tmp_vec);
3364 } else {
3365 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3366
3367 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3368 }
3369 }
3370 break;
3371 case nir_var_shared: {
3372 int writemask = instr->const_index[0];
3373 LLVMValueRef address = build_gep_for_deref(ctx,
3374 instr->variables[0]);
3375 LLVMValueRef val = get_src(ctx, instr->src[0]);
3376 unsigned components =
3377 glsl_get_vector_elements(
3378 nir_deref_tail(&instr->variables[0]->deref)->type);
3379 if (writemask == (1 << components) - 1) {
3380 val = LLVMBuildBitCast(
3381 ctx->ac.builder, val,
3382 LLVMGetElementType(LLVMTypeOf(address)), "");
3383 LLVMBuildStore(ctx->ac.builder, val, address);
3384 } else {
3385 for (unsigned chan = 0; chan < 4; chan++) {
3386 if (!(writemask & (1 << chan)))
3387 continue;
3388 LLVMValueRef ptr =
3389 LLVMBuildStructGEP(ctx->ac.builder,
3390 address, chan, "");
3391 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3392 chan);
3393 src = LLVMBuildBitCast(
3394 ctx->ac.builder, src,
3395 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3396 LLVMBuildStore(ctx->ac.builder, src, ptr);
3397 }
3398 }
3399 break;
3400 }
3401 default:
3402 break;
3403 }
3404 }
3405
3406 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3407 {
3408 switch (dim) {
3409 case GLSL_SAMPLER_DIM_BUF:
3410 return 1;
3411 case GLSL_SAMPLER_DIM_1D:
3412 return array ? 2 : 1;
3413 case GLSL_SAMPLER_DIM_2D:
3414 return array ? 3 : 2;
3415 case GLSL_SAMPLER_DIM_MS:
3416 return array ? 4 : 3;
3417 case GLSL_SAMPLER_DIM_3D:
3418 case GLSL_SAMPLER_DIM_CUBE:
3419 return 3;
3420 case GLSL_SAMPLER_DIM_RECT:
3421 case GLSL_SAMPLER_DIM_SUBPASS:
3422 return 2;
3423 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3424 return 3;
3425 default:
3426 break;
3427 }
3428 return 0;
3429 }
3430
3431
3432
3433 /* Adjust the sample index according to FMASK.
3434 *
3435 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3436 * which is the identity mapping. Each nibble says which physical sample
3437 * should be fetched to get that sample.
3438 *
3439 * For example, 0x11111100 means there are only 2 samples stored and
3440 * the second sample covers 3/4 of the pixel. When reading samples 0
3441 * and 1, return physical sample 0 (determined by the first two 0s
3442 * in FMASK), otherwise return physical sample 1.
3443 *
3444 * The sample index should be adjusted as follows:
3445 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3446 */
3447 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3448 LLVMValueRef coord_x, LLVMValueRef coord_y,
3449 LLVMValueRef coord_z,
3450 LLVMValueRef sample_index,
3451 LLVMValueRef fmask_desc_ptr)
3452 {
3453 LLVMValueRef fmask_load_address[4];
3454 LLVMValueRef res;
3455
3456 fmask_load_address[0] = coord_x;
3457 fmask_load_address[1] = coord_y;
3458 if (coord_z) {
3459 fmask_load_address[2] = coord_z;
3460 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3461 }
3462
3463 struct ac_image_args args = {0};
3464
3465 args.opcode = ac_image_load;
3466 args.da = coord_z ? true : false;
3467 args.resource = fmask_desc_ptr;
3468 args.dmask = 0xf;
3469 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3470
3471 res = ac_build_image_opcode(ctx, &args);
3472
3473 res = ac_to_integer(ctx, res);
3474 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3475 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3476
3477 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3478 res,
3479 ctx->i32_0, "");
3480
3481 LLVMValueRef sample_index4 =
3482 LLVMBuildMul(ctx->builder, sample_index, four, "");
3483 LLVMValueRef shifted_fmask =
3484 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3485 LLVMValueRef final_sample =
3486 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3487
3488 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3489 * resource descriptor is 0 (invalid),
3490 */
3491 LLVMValueRef fmask_desc =
3492 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3493 ctx->v8i32, "");
3494
3495 LLVMValueRef fmask_word1 =
3496 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3497 ctx->i32_1, "");
3498
3499 LLVMValueRef word1_is_nonzero =
3500 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3501 fmask_word1, ctx->i32_0, "");
3502
3503 /* Replace the MSAA sample index. */
3504 sample_index =
3505 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3506 final_sample, sample_index, "");
3507 return sample_index;
3508 }
3509
3510 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3511 const nir_intrinsic_instr *instr)
3512 {
3513 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3514
3515 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3516 LLVMValueRef coords[4];
3517 LLVMValueRef masks[] = {
3518 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3519 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3520 };
3521 LLVMValueRef res;
3522 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3523
3524 int count;
3525 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3526 bool is_array = glsl_sampler_type_is_array(type);
3527 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3528 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3529 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3530 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3531 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3532 count = image_type_to_components_count(dim, is_array);
3533
3534 if (is_ms) {
3535 LLVMValueRef fmask_load_address[3];
3536 int chan;
3537
3538 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3539 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3540 if (is_array)
3541 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3542 else
3543 fmask_load_address[2] = NULL;
3544 if (add_frag_pos) {
3545 for (chan = 0; chan < 2; ++chan)
3546 fmask_load_address[chan] =
3547 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3548 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3549 ctx->ac.i32, ""), "");
3550 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3551 }
3552 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3553 fmask_load_address[0],
3554 fmask_load_address[1],
3555 fmask_load_address[2],
3556 sample_index,
3557 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3558 }
3559 if (count == 1 && !gfx9_1d) {
3560 if (instr->src[0].ssa->num_components)
3561 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3562 else
3563 res = src0;
3564 } else {
3565 int chan;
3566 if (is_ms)
3567 count--;
3568 for (chan = 0; chan < count; ++chan) {
3569 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3570 }
3571 if (add_frag_pos) {
3572 for (chan = 0; chan < 2; ++chan)
3573 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3574 ctx->ac.i32, ""), "");
3575 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3576 count++;
3577 }
3578
3579 if (gfx9_1d) {
3580 if (is_array) {
3581 coords[2] = coords[1];
3582 coords[1] = ctx->ac.i32_0;
3583 } else
3584 coords[1] = ctx->ac.i32_0;
3585 count++;
3586 }
3587
3588 if (is_ms) {
3589 coords[count] = sample_index;
3590 count++;
3591 }
3592
3593 if (count == 3) {
3594 coords[3] = LLVMGetUndef(ctx->ac.i32);
3595 count = 4;
3596 }
3597 res = ac_build_gather_values(&ctx->ac, coords, count);
3598 }
3599 return res;
3600 }
3601
3602 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3603 const nir_intrinsic_instr *instr)
3604 {
3605 LLVMValueRef params[7];
3606 LLVMValueRef res;
3607 char intrinsic_name[64];
3608 const nir_variable *var = instr->variables[0]->var;
3609 const struct glsl_type *type = var->type;
3610
3611 if(instr->variables[0]->deref.child)
3612 type = instr->variables[0]->deref.child->type;
3613
3614 type = glsl_without_array(type);
3615
3616 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3617 if (dim == GLSL_SAMPLER_DIM_BUF) {
3618 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3619 unsigned num_channels = util_last_bit(mask);
3620 LLVMValueRef rsrc, vindex;
3621
3622 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3623 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3624 ctx->ac.i32_0, "");
3625
3626 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3627 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3628 ctx->ac.i32_0, num_channels,
3629 false, false);
3630 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3631
3632 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3633 res = ac_to_integer(&ctx->ac, res);
3634 } else {
3635 bool is_da = glsl_sampler_type_is_array(type) ||
3636 dim == GLSL_SAMPLER_DIM_CUBE ||
3637 dim == GLSL_SAMPLER_DIM_3D ||
3638 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3639 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3640 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3641 LLVMValueRef glc = ctx->ac.i1false;
3642 LLVMValueRef slc = ctx->ac.i1false;
3643
3644 params[0] = get_image_coords(ctx, instr);
3645 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3646 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3647 params[3] = glc;
3648 params[4] = slc;
3649 params[5] = ctx->ac.i1false;
3650 params[6] = da;
3651
3652 ac_get_image_intr_name("llvm.amdgcn.image.load",
3653 ctx->ac.v4f32, /* vdata */
3654 LLVMTypeOf(params[0]), /* coords */
3655 LLVMTypeOf(params[1]), /* rsrc */
3656 intrinsic_name, sizeof(intrinsic_name));
3657
3658 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3659 params, 7, AC_FUNC_ATTR_READONLY);
3660 }
3661 return ac_to_integer(&ctx->ac, res);
3662 }
3663
3664 static void visit_image_store(struct ac_nir_context *ctx,
3665 nir_intrinsic_instr *instr)
3666 {
3667 LLVMValueRef params[8];
3668 char intrinsic_name[64];
3669 const nir_variable *var = instr->variables[0]->var;
3670 const struct glsl_type *type = glsl_without_array(var->type);
3671 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3672 LLVMValueRef glc = ctx->ac.i1false;
3673 bool force_glc = ctx->ac.chip_class == SI;
3674 if (force_glc)
3675 glc = ctx->ac.i1true;
3676
3677 if (dim == GLSL_SAMPLER_DIM_BUF) {
3678 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3679 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3680 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3681 ctx->ac.i32_0, ""); /* vindex */
3682 params[3] = ctx->ac.i32_0; /* voffset */
3683 params[4] = glc; /* glc */
3684 params[5] = ctx->ac.i1false; /* slc */
3685 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3686 params, 6, 0);
3687 } else {
3688 bool is_da = glsl_sampler_type_is_array(type) ||
3689 dim == GLSL_SAMPLER_DIM_CUBE ||
3690 dim == GLSL_SAMPLER_DIM_3D;
3691 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3692 LLVMValueRef slc = ctx->ac.i1false;
3693
3694 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3695 params[1] = get_image_coords(ctx, instr); /* coords */
3696 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3697 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3698 params[4] = glc;
3699 params[5] = slc;
3700 params[6] = ctx->ac.i1false;
3701 params[7] = da;
3702
3703 ac_get_image_intr_name("llvm.amdgcn.image.store",
3704 LLVMTypeOf(params[0]), /* vdata */
3705 LLVMTypeOf(params[1]), /* coords */
3706 LLVMTypeOf(params[2]), /* rsrc */
3707 intrinsic_name, sizeof(intrinsic_name));
3708
3709 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3710 params, 8, 0);
3711 }
3712
3713 }
3714
3715 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3716 const nir_intrinsic_instr *instr)
3717 {
3718 LLVMValueRef params[7];
3719 int param_count = 0;
3720 const nir_variable *var = instr->variables[0]->var;
3721
3722 const char *atomic_name;
3723 char intrinsic_name[41];
3724 const struct glsl_type *type = glsl_without_array(var->type);
3725 MAYBE_UNUSED int length;
3726
3727 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3728
3729 switch (instr->intrinsic) {
3730 case nir_intrinsic_image_atomic_add:
3731 atomic_name = "add";
3732 break;
3733 case nir_intrinsic_image_atomic_min:
3734 atomic_name = is_unsigned ? "umin" : "smin";
3735 break;
3736 case nir_intrinsic_image_atomic_max:
3737 atomic_name = is_unsigned ? "umax" : "smax";
3738 break;
3739 case nir_intrinsic_image_atomic_and:
3740 atomic_name = "and";
3741 break;
3742 case nir_intrinsic_image_atomic_or:
3743 atomic_name = "or";
3744 break;
3745 case nir_intrinsic_image_atomic_xor:
3746 atomic_name = "xor";
3747 break;
3748 case nir_intrinsic_image_atomic_exchange:
3749 atomic_name = "swap";
3750 break;
3751 case nir_intrinsic_image_atomic_comp_swap:
3752 atomic_name = "cmpswap";
3753 break;
3754 default:
3755 abort();
3756 }
3757
3758 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3759 params[param_count++] = get_src(ctx, instr->src[3]);
3760 params[param_count++] = get_src(ctx, instr->src[2]);
3761
3762 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3763 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3764 NULL, true, true);
3765 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3766 ctx->ac.i32_0, ""); /* vindex */
3767 params[param_count++] = ctx->ac.i32_0; /* voffset */
3768 params[param_count++] = ctx->ac.i1false; /* slc */
3769
3770 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3771 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3772 } else {
3773 char coords_type[8];
3774
3775 bool da = glsl_sampler_type_is_array(type) ||
3776 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3777
3778 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3779 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3780 NULL, true, true);
3781 params[param_count++] = ctx->ac.i1false; /* r128 */
3782 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3783 params[param_count++] = ctx->ac.i1false; /* slc */
3784
3785 build_int_type_name(LLVMTypeOf(coords),
3786 coords_type, sizeof(coords_type));
3787
3788 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3789 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3790 }
3791
3792 assert(length < sizeof(intrinsic_name));
3793 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3794 }
3795
3796 static LLVMValueRef visit_image_samples(struct ac_nir_context *ctx,
3797 const nir_intrinsic_instr *instr)
3798 {
3799 const nir_variable *var = instr->variables[0]->var;
3800 const struct glsl_type *type = glsl_without_array(var->type);
3801 bool da = glsl_sampler_type_is_array(type) ||
3802 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3803 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_3D;
3804
3805 struct ac_image_args args = { 0 };
3806 args.da = da;
3807 args.dmask = 0xf;
3808 args.resource = get_sampler_desc(ctx, instr->variables[0],
3809 AC_DESC_IMAGE, NULL, true, false);
3810 args.opcode = ac_image_get_resinfo;
3811 args.addr = ctx->ac.i32_0;
3812
3813 return ac_build_image_opcode(&ctx->ac, &args);
3814 }
3815
3816 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3817 const nir_intrinsic_instr *instr)
3818 {
3819 LLVMValueRef res;
3820 const nir_variable *var = instr->variables[0]->var;
3821 const struct glsl_type *type = glsl_without_array(var->type);
3822 bool da = glsl_sampler_type_is_array(type) ||
3823 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3824 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_3D;
3825
3826 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3827 return get_buffer_size(ctx,
3828 get_sampler_desc(ctx, instr->variables[0],
3829 AC_DESC_BUFFER, NULL, true, false), true);
3830
3831 struct ac_image_args args = { 0 };
3832
3833 args.da = da;
3834 args.dmask = 0xf;
3835 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3836 args.opcode = ac_image_get_resinfo;
3837 args.addr = ctx->ac.i32_0;
3838
3839 res = ac_build_image_opcode(&ctx->ac, &args);
3840
3841 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3842
3843 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3844 glsl_sampler_type_is_array(type)) {
3845 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3846 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3847 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3848 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3849 }
3850 if (ctx->ac.chip_class >= GFX9 &&
3851 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3852 glsl_sampler_type_is_array(type)) {
3853 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3854 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3855 ctx->ac.i32_1, "");
3856
3857 }
3858 return res;
3859 }
3860
3861 #define NOOP_WAITCNT 0xf7f
3862 #define LGKM_CNT 0x07f
3863 #define VM_CNT 0xf70
3864
3865 static void emit_membar(struct ac_llvm_context *ac,
3866 const nir_intrinsic_instr *instr)
3867 {
3868 unsigned waitcnt = NOOP_WAITCNT;
3869
3870 switch (instr->intrinsic) {
3871 case nir_intrinsic_memory_barrier:
3872 case nir_intrinsic_group_memory_barrier:
3873 waitcnt &= VM_CNT & LGKM_CNT;
3874 break;
3875 case nir_intrinsic_memory_barrier_atomic_counter:
3876 case nir_intrinsic_memory_barrier_buffer:
3877 case nir_intrinsic_memory_barrier_image:
3878 waitcnt &= VM_CNT;
3879 break;
3880 case nir_intrinsic_memory_barrier_shared:
3881 waitcnt &= LGKM_CNT;
3882 break;
3883 default:
3884 break;
3885 }
3886 if (waitcnt != NOOP_WAITCNT)
3887 ac_build_waitcnt(ac, waitcnt);
3888 }
3889
3890 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3891 {
3892 /* SI only (thanks to a hw bug workaround):
3893 * The real barrier instruction isn’t needed, because an entire patch
3894 * always fits into a single wave.
3895 */
3896 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3897 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3898 return;
3899 }
3900 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3901 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3902 }
3903
3904 static void emit_discard(struct ac_nir_context *ctx,
3905 const nir_intrinsic_instr *instr)
3906 {
3907 LLVMValueRef cond;
3908
3909 if (instr->intrinsic == nir_intrinsic_discard_if) {
3910 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3911 get_src(ctx, instr->src[0]),
3912 ctx->ac.i32_0, "");
3913 } else {
3914 assert(instr->intrinsic == nir_intrinsic_discard);
3915 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3916 }
3917
3918 ac_build_kill_if_false(&ctx->ac, cond);
3919 }
3920
3921 static LLVMValueRef
3922 visit_load_helper_invocation(struct ac_nir_context *ctx)
3923 {
3924 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3925 "llvm.amdgcn.ps.live",
3926 ctx->ac.i1, NULL, 0,
3927 AC_FUNC_ATTR_READNONE);
3928 result = LLVMBuildNot(ctx->ac.builder, result, "");
3929 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3930 }
3931
3932 static LLVMValueRef
3933 visit_load_local_invocation_index(struct ac_nir_context *ctx)
3934 {
3935 LLVMValueRef result;
3936 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3937 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3938 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3939
3940 return LLVMBuildAdd(ctx->ac.builder, result, thread_id, "");
3941 }
3942
3943 static LLVMValueRef
3944 visit_load_shared(struct ac_nir_context *ctx,
3945 const nir_intrinsic_instr *instr)
3946 {
3947 LLVMValueRef values[4], derived_ptr, index, ret;
3948
3949 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
3950
3951 for (int chan = 0; chan < instr->num_components; chan++) {
3952 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3953 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
3954 values[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
3955 }
3956
3957 ret = ac_build_gather_values(&ctx->ac, values, instr->num_components);
3958 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3959 }
3960
3961 static void
3962 visit_store_shared(struct ac_nir_context *ctx,
3963 const nir_intrinsic_instr *instr)
3964 {
3965 LLVMValueRef derived_ptr, data,index;
3966 LLVMBuilderRef builder = ctx->ac.builder;
3967
3968 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
3969 LLVMValueRef src = get_src(ctx, instr->src[0]);
3970
3971 int writemask = nir_intrinsic_write_mask(instr);
3972 for (int chan = 0; chan < 4; chan++) {
3973 if (!(writemask & (1 << chan))) {
3974 continue;
3975 }
3976 data = ac_llvm_extract_elem(&ctx->ac, src, chan);
3977 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3978 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3979 LLVMBuildStore(builder, data, derived_ptr);
3980 }
3981 }
3982
3983 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
3984 const nir_intrinsic_instr *instr,
3985 LLVMValueRef ptr)
3986 {
3987 LLVMValueRef result;
3988 LLVMValueRef src = get_src(ctx, instr->src[0]);
3989
3990 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
3991 instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
3992 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3993 result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
3994 ptr, src, src1,
3995 LLVMAtomicOrderingSequentiallyConsistent,
3996 LLVMAtomicOrderingSequentiallyConsistent,
3997 false);
3998 } else {
3999 LLVMAtomicRMWBinOp op;
4000 switch (instr->intrinsic) {
4001 case nir_intrinsic_var_atomic_add:
4002 case nir_intrinsic_shared_atomic_add:
4003 op = LLVMAtomicRMWBinOpAdd;
4004 break;
4005 case nir_intrinsic_var_atomic_umin:
4006 case nir_intrinsic_shared_atomic_umin:
4007 op = LLVMAtomicRMWBinOpUMin;
4008 break;
4009 case nir_intrinsic_var_atomic_umax:
4010 case nir_intrinsic_shared_atomic_umax:
4011 op = LLVMAtomicRMWBinOpUMax;
4012 break;
4013 case nir_intrinsic_var_atomic_imin:
4014 case nir_intrinsic_shared_atomic_imin:
4015 op = LLVMAtomicRMWBinOpMin;
4016 break;
4017 case nir_intrinsic_var_atomic_imax:
4018 case nir_intrinsic_shared_atomic_imax:
4019 op = LLVMAtomicRMWBinOpMax;
4020 break;
4021 case nir_intrinsic_var_atomic_and:
4022 case nir_intrinsic_shared_atomic_and:
4023 op = LLVMAtomicRMWBinOpAnd;
4024 break;
4025 case nir_intrinsic_var_atomic_or:
4026 case nir_intrinsic_shared_atomic_or:
4027 op = LLVMAtomicRMWBinOpOr;
4028 break;
4029 case nir_intrinsic_var_atomic_xor:
4030 case nir_intrinsic_shared_atomic_xor:
4031 op = LLVMAtomicRMWBinOpXor;
4032 break;
4033 case nir_intrinsic_var_atomic_exchange:
4034 case nir_intrinsic_shared_atomic_exchange:
4035 op = LLVMAtomicRMWBinOpXchg;
4036 break;
4037 default:
4038 return NULL;
4039 }
4040
4041 result = LLVMBuildAtomicRMW(ctx->ac.builder, op, ptr, ac_to_integer(&ctx->ac, src),
4042 LLVMAtomicOrderingSequentiallyConsistent,
4043 false);
4044 }
4045 return result;
4046 }
4047
4048 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
4049 enum glsl_interp_mode interp, unsigned location)
4050 {
4051 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4052
4053 switch (interp) {
4054 case INTERP_MODE_FLAT:
4055 default:
4056 return NULL;
4057 case INTERP_MODE_SMOOTH:
4058 case INTERP_MODE_NONE:
4059 if (location == INTERP_CENTER)
4060 return ctx->persp_center;
4061 else if (location == INTERP_CENTROID)
4062 return ctx->persp_centroid;
4063 else if (location == INTERP_SAMPLE)
4064 return ctx->persp_sample;
4065 break;
4066 case INTERP_MODE_NOPERSPECTIVE:
4067 if (location == INTERP_CENTER)
4068 return ctx->linear_center;
4069 else if (location == INTERP_CENTROID)
4070 return ctx->linear_centroid;
4071 else if (location == INTERP_SAMPLE)
4072 return ctx->linear_sample;
4073 break;
4074 }
4075 return NULL;
4076 }
4077
4078 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
4079 LLVMValueRef sample_id)
4080 {
4081 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4082
4083 LLVMValueRef result;
4084 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4085
4086 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
4087 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4088
4089 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
4090 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4091
4092 return result;
4093 }
4094
4095 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4096 {
4097 LLVMValueRef values[2];
4098
4099 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0], 32);
4100 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1], 32);
4101 return ac_build_gather_values(&ctx->ac, values, 2);
4102 }
4103
4104 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4105 {
4106 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4107 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4108 ctx->options->key.fs.log2_num_samples :
4109 ctx->options->key.fs.log2_ps_iter_samples;
4110
4111 /* The bit pattern matches that used by fixed function fragment
4112 * processing. */
4113 static const uint16_t ps_iter_masks[] = {
4114 0xffff, /* not used */
4115 0x5555,
4116 0x1111,
4117 0x0101,
4118 0x0001,
4119 };
4120 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4121
4122 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4123
4124 LLVMValueRef result, sample_id;
4125 sample_id = unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4126 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4127 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4128 return result;
4129 }
4130
4131 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4132 const nir_intrinsic_instr *instr)
4133 {
4134 LLVMValueRef result[4];
4135 LLVMValueRef interp_param, attr_number;
4136 unsigned location;
4137 unsigned chan;
4138 LLVMValueRef src_c0 = NULL;
4139 LLVMValueRef src_c1 = NULL;
4140 LLVMValueRef src0 = NULL;
4141 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4142 switch (instr->intrinsic) {
4143 case nir_intrinsic_interp_var_at_centroid:
4144 location = INTERP_CENTROID;
4145 break;
4146 case nir_intrinsic_interp_var_at_sample:
4147 case nir_intrinsic_interp_var_at_offset:
4148 location = INTERP_CENTER;
4149 src0 = get_src(ctx, instr->src[0]);
4150 break;
4151 default:
4152 break;
4153 }
4154
4155 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4156 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4157 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4158 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4159 LLVMValueRef sample_position;
4160 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4161
4162 /* fetch sample ID */
4163 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4164
4165 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4166 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4167 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4168 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4169 }
4170 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4171 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4172
4173 if (location == INTERP_CENTER) {
4174 LLVMValueRef ij_out[2];
4175 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4176
4177 /*
4178 * take the I then J parameters, and the DDX/Y for it, and
4179 * calculate the IJ inputs for the interpolator.
4180 * temp1 = ddx * offset/sample.x + I;
4181 * interp_param.I = ddy * offset/sample.y + temp1;
4182 * temp1 = ddx * offset/sample.x + J;
4183 * interp_param.J = ddy * offset/sample.y + temp1;
4184 */
4185 for (unsigned i = 0; i < 2; i++) {
4186 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4187 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4188 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4189 ddxy_out, ix_ll, "");
4190 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4191 ddxy_out, iy_ll, "");
4192 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4193 interp_param, ix_ll, "");
4194 LLVMValueRef temp1, temp2;
4195
4196 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4197 ctx->ac.f32, "");
4198
4199 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4200 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4201
4202 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4203 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4204
4205 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4206 temp2, ctx->ac.i32, "");
4207 }
4208 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4209
4210 }
4211
4212 for (chan = 0; chan < 4; chan++) {
4213 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4214
4215 if (interp_param) {
4216 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4217 interp_param, ctx->ac.v2f32, "");
4218 LLVMValueRef i = LLVMBuildExtractElement(
4219 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4220 LLVMValueRef j = LLVMBuildExtractElement(
4221 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4222
4223 result[chan] = ac_build_fs_interp(&ctx->ac,
4224 llvm_chan, attr_number,
4225 ctx->abi->prim_mask, i, j);
4226 } else {
4227 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4228 LLVMConstInt(ctx->ac.i32, 2, false),
4229 llvm_chan, attr_number,
4230 ctx->abi->prim_mask);
4231 }
4232 }
4233 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4234 instr->variables[0]->var->data.location_frac);
4235 }
4236
4237 static void
4238 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4239 {
4240 LLVMValueRef gs_next_vertex;
4241 LLVMValueRef can_emit;
4242 int idx;
4243 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4244
4245 assert(stream == 0);
4246
4247 /* Write vertex attribute values to GSVS ring */
4248 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4249 ctx->gs_next_vertex,
4250 "");
4251
4252 /* If this thread has already emitted the declared maximum number of
4253 * vertices, kill it: excessive vertex emissions are not supposed to
4254 * have any effect, and GS threads have no externally observable
4255 * effects other than emitting vertices.
4256 */
4257 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4258 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4259 ac_build_kill_if_false(&ctx->ac, can_emit);
4260
4261 /* loop num outputs */
4262 idx = 0;
4263 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4264 LLVMValueRef *out_ptr = &addrs[i * 4];
4265 int length = 4;
4266 int slot = idx;
4267 int slot_inc = 1;
4268
4269 if (!(ctx->output_mask & (1ull << i)))
4270 continue;
4271
4272 if (i == VARYING_SLOT_CLIP_DIST0) {
4273 /* pack clip and cull into a single set of slots */
4274 length = ctx->num_output_clips + ctx->num_output_culls;
4275 if (length > 4)
4276 slot_inc = 2;
4277 }
4278 for (unsigned j = 0; j < length; j++) {
4279 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4280 out_ptr[j], "");
4281 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4282 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4283 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4284
4285 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4286
4287 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4288 out_val, 1,
4289 voffset, ctx->gs2vs_offset, 0,
4290 1, 1, true, true);
4291 }
4292 idx += slot_inc;
4293 }
4294
4295 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
4296 ctx->ac.i32_1, "");
4297 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
4298
4299 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4300 }
4301
4302 static void
4303 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4304 {
4305 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4306 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4307 }
4308
4309 static LLVMValueRef
4310 load_tess_coord(struct ac_shader_abi *abi)
4311 {
4312 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4313
4314 LLVMValueRef coord[4] = {
4315 ctx->tes_u,
4316 ctx->tes_v,
4317 ctx->ac.f32_0,
4318 ctx->ac.f32_0,
4319 };
4320
4321 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4322 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
4323 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
4324
4325 return ac_build_gather_values(&ctx->ac, coord, 3);
4326 }
4327
4328 static LLVMValueRef
4329 load_patch_vertices_in(struct ac_shader_abi *abi)
4330 {
4331 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4332 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4333 }
4334
4335 static void visit_intrinsic(struct ac_nir_context *ctx,
4336 nir_intrinsic_instr *instr)
4337 {
4338 LLVMValueRef result = NULL;
4339
4340 switch (instr->intrinsic) {
4341 case nir_intrinsic_ballot:
4342 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4343 break;
4344 case nir_intrinsic_read_invocation:
4345 case nir_intrinsic_read_first_invocation: {
4346 LLVMValueRef args[2];
4347
4348 /* Value */
4349 args[0] = get_src(ctx, instr->src[0]);
4350
4351 unsigned num_args;
4352 const char *intr_name;
4353 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4354 num_args = 2;
4355 intr_name = "llvm.amdgcn.readlane";
4356
4357 /* Invocation */
4358 args[1] = get_src(ctx, instr->src[1]);
4359 } else {
4360 num_args = 1;
4361 intr_name = "llvm.amdgcn.readfirstlane";
4362 }
4363
4364 /* We currently have no other way to prevent LLVM from lifting the icmp
4365 * calls to a dominating basic block.
4366 */
4367 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4368
4369 result = ac_build_intrinsic(&ctx->ac, intr_name,
4370 ctx->ac.i32, args, num_args,
4371 AC_FUNC_ATTR_READNONE |
4372 AC_FUNC_ATTR_CONVERGENT);
4373 break;
4374 }
4375 case nir_intrinsic_load_subgroup_invocation:
4376 result = ac_get_thread_id(&ctx->ac);
4377 break;
4378 case nir_intrinsic_load_work_group_id: {
4379 LLVMValueRef values[3];
4380
4381 for (int i = 0; i < 3; i++) {
4382 values[i] = ctx->abi->workgroup_ids[i] ?
4383 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4384 }
4385
4386 result = ac_build_gather_values(&ctx->ac, values, 3);
4387 break;
4388 }
4389 case nir_intrinsic_load_base_vertex: {
4390 result = ctx->abi->base_vertex;
4391 break;
4392 }
4393 case nir_intrinsic_load_local_group_size:
4394 result = ctx->abi->load_local_group_size(ctx->abi);
4395 break;
4396 case nir_intrinsic_load_vertex_id_zero_base: {
4397 result = ctx->abi->vertex_id;
4398 break;
4399 }
4400 case nir_intrinsic_load_local_invocation_id: {
4401 result = ctx->abi->local_invocation_ids;
4402 break;
4403 }
4404 case nir_intrinsic_load_base_instance:
4405 result = ctx->abi->start_instance;
4406 break;
4407 case nir_intrinsic_load_draw_id:
4408 result = ctx->abi->draw_id;
4409 break;
4410 case nir_intrinsic_load_view_index:
4411 result = ctx->abi->view_index;
4412 break;
4413 case nir_intrinsic_load_invocation_id:
4414 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4415 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4416 else
4417 result = ctx->abi->gs_invocation_id;
4418 break;
4419 case nir_intrinsic_load_primitive_id:
4420 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4421 result = ctx->abi->gs_prim_id;
4422 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4423 result = ctx->abi->tcs_patch_id;
4424 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4425 result = ctx->abi->tes_patch_id;
4426 } else
4427 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4428 break;
4429 case nir_intrinsic_load_sample_id:
4430 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4431 break;
4432 case nir_intrinsic_load_sample_pos:
4433 result = load_sample_pos(ctx);
4434 break;
4435 case nir_intrinsic_load_sample_mask_in:
4436 result = ctx->abi->load_sample_mask_in(ctx->abi);
4437 break;
4438 case nir_intrinsic_load_frag_coord: {
4439 LLVMValueRef values[4] = {
4440 ctx->abi->frag_pos[0],
4441 ctx->abi->frag_pos[1],
4442 ctx->abi->frag_pos[2],
4443 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4444 };
4445 result = ac_build_gather_values(&ctx->ac, values, 4);
4446 break;
4447 }
4448 case nir_intrinsic_load_front_face:
4449 result = ctx->abi->front_face;
4450 break;
4451 case nir_intrinsic_load_helper_invocation:
4452 result = visit_load_helper_invocation(ctx);
4453 break;
4454 case nir_intrinsic_load_instance_id:
4455 result = ctx->abi->instance_id;
4456 break;
4457 case nir_intrinsic_load_num_work_groups:
4458 result = ctx->abi->num_work_groups;
4459 break;
4460 case nir_intrinsic_load_local_invocation_index:
4461 result = visit_load_local_invocation_index(ctx);
4462 break;
4463 case nir_intrinsic_load_push_constant:
4464 result = visit_load_push_constant(ctx, instr);
4465 break;
4466 case nir_intrinsic_vulkan_resource_index: {
4467 LLVMValueRef index = get_src(ctx, instr->src[0]);
4468 unsigned desc_set = nir_intrinsic_desc_set(instr);
4469 unsigned binding = nir_intrinsic_binding(instr);
4470
4471 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4472 binding);
4473 break;
4474 }
4475 case nir_intrinsic_vulkan_resource_reindex:
4476 result = visit_vulkan_resource_reindex(ctx, instr);
4477 break;
4478 case nir_intrinsic_store_ssbo:
4479 visit_store_ssbo(ctx, instr);
4480 break;
4481 case nir_intrinsic_load_ssbo:
4482 result = visit_load_buffer(ctx, instr);
4483 break;
4484 case nir_intrinsic_ssbo_atomic_add:
4485 case nir_intrinsic_ssbo_atomic_imin:
4486 case nir_intrinsic_ssbo_atomic_umin:
4487 case nir_intrinsic_ssbo_atomic_imax:
4488 case nir_intrinsic_ssbo_atomic_umax:
4489 case nir_intrinsic_ssbo_atomic_and:
4490 case nir_intrinsic_ssbo_atomic_or:
4491 case nir_intrinsic_ssbo_atomic_xor:
4492 case nir_intrinsic_ssbo_atomic_exchange:
4493 case nir_intrinsic_ssbo_atomic_comp_swap:
4494 result = visit_atomic_ssbo(ctx, instr);
4495 break;
4496 case nir_intrinsic_load_ubo:
4497 result = visit_load_ubo_buffer(ctx, instr);
4498 break;
4499 case nir_intrinsic_get_buffer_size:
4500 result = visit_get_buffer_size(ctx, instr);
4501 break;
4502 case nir_intrinsic_load_var:
4503 result = visit_load_var(ctx, instr);
4504 break;
4505 case nir_intrinsic_store_var:
4506 visit_store_var(ctx, instr);
4507 break;
4508 case nir_intrinsic_load_shared:
4509 result = visit_load_shared(ctx, instr);
4510 break;
4511 case nir_intrinsic_store_shared:
4512 visit_store_shared(ctx, instr);
4513 break;
4514 case nir_intrinsic_image_samples:
4515 result = visit_image_samples(ctx, instr);
4516 break;
4517 case nir_intrinsic_image_load:
4518 result = visit_image_load(ctx, instr);
4519 break;
4520 case nir_intrinsic_image_store:
4521 visit_image_store(ctx, instr);
4522 break;
4523 case nir_intrinsic_image_atomic_add:
4524 case nir_intrinsic_image_atomic_min:
4525 case nir_intrinsic_image_atomic_max:
4526 case nir_intrinsic_image_atomic_and:
4527 case nir_intrinsic_image_atomic_or:
4528 case nir_intrinsic_image_atomic_xor:
4529 case nir_intrinsic_image_atomic_exchange:
4530 case nir_intrinsic_image_atomic_comp_swap:
4531 result = visit_image_atomic(ctx, instr);
4532 break;
4533 case nir_intrinsic_image_size:
4534 result = visit_image_size(ctx, instr);
4535 break;
4536 case nir_intrinsic_shader_clock:
4537 result = ac_build_shader_clock(&ctx->ac);
4538 break;
4539 case nir_intrinsic_discard:
4540 case nir_intrinsic_discard_if:
4541 emit_discard(ctx, instr);
4542 break;
4543 case nir_intrinsic_memory_barrier:
4544 case nir_intrinsic_group_memory_barrier:
4545 case nir_intrinsic_memory_barrier_atomic_counter:
4546 case nir_intrinsic_memory_barrier_buffer:
4547 case nir_intrinsic_memory_barrier_image:
4548 case nir_intrinsic_memory_barrier_shared:
4549 emit_membar(&ctx->ac, instr);
4550 break;
4551 case nir_intrinsic_barrier:
4552 emit_barrier(&ctx->ac, ctx->stage);
4553 break;
4554 case nir_intrinsic_shared_atomic_add:
4555 case nir_intrinsic_shared_atomic_imin:
4556 case nir_intrinsic_shared_atomic_umin:
4557 case nir_intrinsic_shared_atomic_imax:
4558 case nir_intrinsic_shared_atomic_umax:
4559 case nir_intrinsic_shared_atomic_and:
4560 case nir_intrinsic_shared_atomic_or:
4561 case nir_intrinsic_shared_atomic_xor:
4562 case nir_intrinsic_shared_atomic_exchange:
4563 case nir_intrinsic_shared_atomic_comp_swap: {
4564 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
4565 result = visit_var_atomic(ctx, instr, ptr);
4566 break;
4567 }
4568 case nir_intrinsic_var_atomic_add:
4569 case nir_intrinsic_var_atomic_imin:
4570 case nir_intrinsic_var_atomic_umin:
4571 case nir_intrinsic_var_atomic_imax:
4572 case nir_intrinsic_var_atomic_umax:
4573 case nir_intrinsic_var_atomic_and:
4574 case nir_intrinsic_var_atomic_or:
4575 case nir_intrinsic_var_atomic_xor:
4576 case nir_intrinsic_var_atomic_exchange:
4577 case nir_intrinsic_var_atomic_comp_swap: {
4578 LLVMValueRef ptr = build_gep_for_deref(ctx, instr->variables[0]);
4579 result = visit_var_atomic(ctx, instr, ptr);
4580 break;
4581 }
4582 case nir_intrinsic_interp_var_at_centroid:
4583 case nir_intrinsic_interp_var_at_sample:
4584 case nir_intrinsic_interp_var_at_offset:
4585 result = visit_interp(ctx, instr);
4586 break;
4587 case nir_intrinsic_emit_vertex:
4588 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->abi->outputs);
4589 break;
4590 case nir_intrinsic_end_primitive:
4591 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4592 break;
4593 case nir_intrinsic_load_tess_coord:
4594 result = ctx->abi->load_tess_coord(ctx->abi);
4595 break;
4596 case nir_intrinsic_load_tess_level_outer:
4597 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4598 break;
4599 case nir_intrinsic_load_tess_level_inner:
4600 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4601 break;
4602 case nir_intrinsic_load_patch_vertices_in:
4603 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4604 break;
4605 case nir_intrinsic_vote_all: {
4606 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4607 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4608 break;
4609 }
4610 case nir_intrinsic_vote_any: {
4611 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4612 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4613 break;
4614 }
4615 case nir_intrinsic_vote_eq: {
4616 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4617 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4618 break;
4619 }
4620 default:
4621 fprintf(stderr, "Unknown intrinsic: ");
4622 nir_print_instr(&instr->instr, stderr);
4623 fprintf(stderr, "\n");
4624 break;
4625 }
4626 if (result) {
4627 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4628 }
4629 }
4630
4631 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4632 LLVMValueRef buffer_ptr, bool write)
4633 {
4634 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4635 LLVMValueRef result;
4636
4637 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4638
4639 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4640 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4641
4642 return result;
4643 }
4644
4645 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4646 {
4647 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4648 LLVMValueRef result;
4649
4650 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4651
4652 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4653 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4654
4655 return result;
4656 }
4657
4658 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4659 unsigned descriptor_set,
4660 unsigned base_index,
4661 unsigned constant_index,
4662 LLVMValueRef index,
4663 enum ac_descriptor_type desc_type,
4664 bool image, bool write)
4665 {
4666 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4667 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4668 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4669 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4670 unsigned offset = binding->offset;
4671 unsigned stride = binding->size;
4672 unsigned type_size;
4673 LLVMBuilderRef builder = ctx->ac.builder;
4674 LLVMTypeRef type;
4675
4676 assert(base_index < layout->binding_count);
4677
4678 switch (desc_type) {
4679 case AC_DESC_IMAGE:
4680 type = ctx->ac.v8i32;
4681 type_size = 32;
4682 break;
4683 case AC_DESC_FMASK:
4684 type = ctx->ac.v8i32;
4685 offset += 32;
4686 type_size = 32;
4687 break;
4688 case AC_DESC_SAMPLER:
4689 type = ctx->ac.v4i32;
4690 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4691 offset += 64;
4692
4693 type_size = 16;
4694 break;
4695 case AC_DESC_BUFFER:
4696 type = ctx->ac.v4i32;
4697 type_size = 16;
4698 break;
4699 default:
4700 unreachable("invalid desc_type\n");
4701 }
4702
4703 offset += constant_index * stride;
4704
4705 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4706 (!index || binding->immutable_samplers_equal)) {
4707 if (binding->immutable_samplers_equal)
4708 constant_index = 0;
4709
4710 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4711
4712 LLVMValueRef constants[] = {
4713 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4714 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4715 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4716 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4717 };
4718 return ac_build_gather_values(&ctx->ac, constants, 4);
4719 }
4720
4721 assert(stride % type_size == 0);
4722
4723 if (!index)
4724 index = ctx->ac.i32_0;
4725
4726 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4727
4728 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4729 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4730
4731 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4732 }
4733
4734 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4735 const nir_deref_var *deref,
4736 enum ac_descriptor_type desc_type,
4737 const nir_tex_instr *tex_instr,
4738 bool image, bool write)
4739 {
4740 LLVMValueRef index = NULL;
4741 unsigned constant_index = 0;
4742 unsigned descriptor_set;
4743 unsigned base_index;
4744
4745 if (!deref) {
4746 assert(tex_instr && !image);
4747 descriptor_set = 0;
4748 base_index = tex_instr->sampler_index;
4749 } else {
4750 const nir_deref *tail = &deref->deref;
4751 while (tail->child) {
4752 const nir_deref_array *child = nir_deref_as_array(tail->child);
4753 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4754
4755 if (!array_size)
4756 array_size = 1;
4757
4758 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4759
4760 if (child->deref_array_type == nir_deref_array_type_indirect) {
4761 LLVMValueRef indirect = get_src(ctx, child->indirect);
4762
4763 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4764 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4765
4766 if (!index)
4767 index = indirect;
4768 else
4769 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4770 }
4771
4772 constant_index += child->base_offset * array_size;
4773
4774 tail = &child->deref;
4775 }
4776 descriptor_set = deref->var->data.descriptor_set;
4777 base_index = deref->var->data.binding;
4778 }
4779
4780 return ctx->abi->load_sampler_desc(ctx->abi,
4781 descriptor_set,
4782 base_index,
4783 constant_index, index,
4784 desc_type, image, write);
4785 }
4786
4787 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4788 struct ac_image_args *args,
4789 const nir_tex_instr *instr,
4790 nir_texop op,
4791 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4792 LLVMValueRef *param, unsigned count,
4793 unsigned dmask)
4794 {
4795 unsigned is_rect = 0;
4796 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4797
4798 if (op == nir_texop_lod)
4799 da = false;
4800 /* Pad to power of two vector */
4801 while (count < util_next_power_of_two(count))
4802 param[count++] = LLVMGetUndef(ctx->i32);
4803
4804 if (count > 1)
4805 args->addr = ac_build_gather_values(ctx, param, count);
4806 else
4807 args->addr = param[0];
4808
4809 args->resource = res_ptr;
4810 args->sampler = samp_ptr;
4811
4812 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4813 args->addr = param[0];
4814 return;
4815 }
4816
4817 args->dmask = dmask;
4818 args->unorm = is_rect;
4819 args->da = da;
4820 }
4821
4822 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4823 *
4824 * SI-CI:
4825 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4826 * filtering manually. The driver sets img7 to a mask clearing
4827 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4828 * s_and_b32 samp0, samp0, img7
4829 *
4830 * VI:
4831 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4832 */
4833 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4834 LLVMValueRef res, LLVMValueRef samp)
4835 {
4836 LLVMBuilderRef builder = ctx->ac.builder;
4837 LLVMValueRef img7, samp0;
4838
4839 if (ctx->ac.chip_class >= VI)
4840 return samp;
4841
4842 img7 = LLVMBuildExtractElement(builder, res,
4843 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4844 samp0 = LLVMBuildExtractElement(builder, samp,
4845 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4846 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4847 return LLVMBuildInsertElement(builder, samp, samp0,
4848 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4849 }
4850
4851 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4852 nir_tex_instr *instr,
4853 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4854 LLVMValueRef *fmask_ptr)
4855 {
4856 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4857 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4858 else
4859 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4860 if (samp_ptr) {
4861 if (instr->sampler)
4862 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4863 else
4864 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4865 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4866 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4867 }
4868 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4869 instr->op == nir_texop_samples_identical))
4870 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4871 }
4872
4873 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4874 LLVMValueRef coord)
4875 {
4876 coord = ac_to_float(ctx, coord);
4877 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4878 coord = ac_to_integer(ctx, coord);
4879 return coord;
4880 }
4881
4882 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4883 {
4884 LLVMValueRef result = NULL;
4885 struct ac_image_args args = { 0 };
4886 unsigned dmask = 0xf;
4887 LLVMValueRef address[16];
4888 LLVMValueRef coords[5];
4889 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4890 LLVMValueRef bias = NULL, offsets = NULL;
4891 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4892 LLVMValueRef ddx = NULL, ddy = NULL;
4893 LLVMValueRef derivs[6];
4894 unsigned chan, count = 0;
4895 unsigned const_src = 0, num_deriv_comp = 0;
4896 bool lod_is_zero = false;
4897
4898 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4899
4900 for (unsigned i = 0; i < instr->num_srcs; i++) {
4901 switch (instr->src[i].src_type) {
4902 case nir_tex_src_coord:
4903 coord = get_src(ctx, instr->src[i].src);
4904 break;
4905 case nir_tex_src_projector:
4906 break;
4907 case nir_tex_src_comparator:
4908 comparator = get_src(ctx, instr->src[i].src);
4909 break;
4910 case nir_tex_src_offset:
4911 offsets = get_src(ctx, instr->src[i].src);
4912 const_src = i;
4913 break;
4914 case nir_tex_src_bias:
4915 bias = get_src(ctx, instr->src[i].src);
4916 break;
4917 case nir_tex_src_lod: {
4918 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4919
4920 if (val && val->i32[0] == 0)
4921 lod_is_zero = true;
4922 lod = get_src(ctx, instr->src[i].src);
4923 break;
4924 }
4925 case nir_tex_src_ms_index:
4926 sample_index = get_src(ctx, instr->src[i].src);
4927 break;
4928 case nir_tex_src_ms_mcs:
4929 break;
4930 case nir_tex_src_ddx:
4931 ddx = get_src(ctx, instr->src[i].src);
4932 num_deriv_comp = instr->src[i].src.ssa->num_components;
4933 break;
4934 case nir_tex_src_ddy:
4935 ddy = get_src(ctx, instr->src[i].src);
4936 break;
4937 case nir_tex_src_texture_offset:
4938 case nir_tex_src_sampler_offset:
4939 case nir_tex_src_plane:
4940 default:
4941 break;
4942 }
4943 }
4944
4945 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4946 result = get_buffer_size(ctx, res_ptr, true);
4947 goto write_result;
4948 }
4949
4950 if (instr->op == nir_texop_texture_samples) {
4951 LLVMValueRef res, samples, is_msaa;
4952 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4953 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4954 LLVMConstInt(ctx->ac.i32, 3, false), "");
4955 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4956 LLVMConstInt(ctx->ac.i32, 28, false), "");
4957 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4958 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4959 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4960 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4961
4962 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4963 LLVMConstInt(ctx->ac.i32, 16, false), "");
4964 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4965 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4966 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4967 samples, "");
4968 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4969 ctx->ac.i32_1, "");
4970 result = samples;
4971 goto write_result;
4972 }
4973
4974 if (coord)
4975 for (chan = 0; chan < instr->coord_components; chan++)
4976 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4977
4978 if (offsets && instr->op != nir_texop_txf) {
4979 LLVMValueRef offset[3], pack;
4980 for (chan = 0; chan < 3; ++chan)
4981 offset[chan] = ctx->ac.i32_0;
4982
4983 args.offset = true;
4984 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4985 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4986 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4987 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4988 if (chan)
4989 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4990 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4991 }
4992 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4993 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4994 address[count++] = pack;
4995
4996 }
4997 /* pack LOD bias value */
4998 if (instr->op == nir_texop_txb && bias) {
4999 address[count++] = bias;
5000 }
5001
5002 /* Pack depth comparison value */
5003 if (instr->is_shadow && comparator) {
5004 LLVMValueRef z = ac_to_float(&ctx->ac,
5005 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
5006
5007 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
5008 * so the depth comparison value isn't clamped for Z16 and
5009 * Z24 anymore. Do it manually here.
5010 *
5011 * It's unnecessary if the original texture format was
5012 * Z32_FLOAT, but we don't know that here.
5013 */
5014 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
5015 z = ac_build_clamp(&ctx->ac, z);
5016
5017 address[count++] = z;
5018 }
5019
5020 /* pack derivatives */
5021 if (ddx || ddy) {
5022 int num_src_deriv_channels, num_dest_deriv_channels;
5023 switch (instr->sampler_dim) {
5024 case GLSL_SAMPLER_DIM_3D:
5025 case GLSL_SAMPLER_DIM_CUBE:
5026 num_deriv_comp = 3;
5027 num_src_deriv_channels = 3;
5028 num_dest_deriv_channels = 3;
5029 break;
5030 case GLSL_SAMPLER_DIM_2D:
5031 default:
5032 num_src_deriv_channels = 2;
5033 num_dest_deriv_channels = 2;
5034 num_deriv_comp = 2;
5035 break;
5036 case GLSL_SAMPLER_DIM_1D:
5037 num_src_deriv_channels = 1;
5038 if (ctx->ac.chip_class >= GFX9) {
5039 num_dest_deriv_channels = 2;
5040 num_deriv_comp = 2;
5041 } else {
5042 num_dest_deriv_channels = 1;
5043 num_deriv_comp = 1;
5044 }
5045 break;
5046 }
5047
5048 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
5049 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
5050 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
5051 }
5052 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
5053 derivs[i] = ctx->ac.f32_0;
5054 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
5055 }
5056 }
5057
5058 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
5059 for (chan = 0; chan < instr->coord_components; chan++)
5060 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
5061 if (instr->coord_components == 3)
5062 coords[3] = LLVMGetUndef(ctx->ac.f32);
5063 ac_prepare_cube_coords(&ctx->ac,
5064 instr->op == nir_texop_txd, instr->is_array,
5065 instr->op == nir_texop_lod, coords, derivs);
5066 if (num_deriv_comp)
5067 num_deriv_comp--;
5068 }
5069
5070 if (ddx || ddy) {
5071 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
5072 address[count++] = derivs[i];
5073 }
5074
5075 /* Pack texture coordinates */
5076 if (coord) {
5077 address[count++] = coords[0];
5078 if (instr->coord_components > 1) {
5079 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
5080 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
5081 }
5082 address[count++] = coords[1];
5083 }
5084 if (instr->coord_components > 2) {
5085 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
5086 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
5087 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
5088 instr->op != nir_texop_txf) {
5089 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
5090 }
5091 address[count++] = coords[2];
5092 }
5093
5094 if (ctx->ac.chip_class >= GFX9) {
5095 LLVMValueRef filler;
5096 if (instr->op == nir_texop_txf)
5097 filler = ctx->ac.i32_0;
5098 else
5099 filler = LLVMConstReal(ctx->ac.f32, 0.5);
5100
5101 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
5102 /* No nir_texop_lod, because it does not take a slice
5103 * even with array textures. */
5104 if (instr->is_array && instr->op != nir_texop_lod ) {
5105 address[count] = address[count - 1];
5106 address[count - 1] = filler;
5107 count++;
5108 } else
5109 address[count++] = filler;
5110 }
5111 }
5112 }
5113
5114 /* Pack LOD */
5115 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5116 instr->op == nir_texop_txf)) {
5117 address[count++] = lod;
5118 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5119 address[count++] = sample_index;
5120 } else if(instr->op == nir_texop_txs) {
5121 count = 0;
5122 if (lod)
5123 address[count++] = lod;
5124 else
5125 address[count++] = ctx->ac.i32_0;
5126 }
5127
5128 for (chan = 0; chan < count; chan++) {
5129 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5130 address[chan], ctx->ac.i32, "");
5131 }
5132
5133 if (instr->op == nir_texop_samples_identical) {
5134 LLVMValueRef txf_address[4];
5135 struct ac_image_args txf_args = { 0 };
5136 unsigned txf_count = count;
5137 memcpy(txf_address, address, sizeof(txf_address));
5138
5139 if (!instr->is_array)
5140 txf_address[2] = ctx->ac.i32_0;
5141 txf_address[3] = ctx->ac.i32_0;
5142
5143 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5144 fmask_ptr, NULL,
5145 txf_address, txf_count, 0xf);
5146
5147 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5148
5149 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5150 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5151 goto write_result;
5152 }
5153
5154 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5155 instr->op != nir_texop_txs) {
5156 unsigned sample_chan = instr->is_array ? 3 : 2;
5157 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5158 address[0],
5159 address[1],
5160 instr->is_array ? address[2] : NULL,
5161 address[sample_chan],
5162 fmask_ptr);
5163 }
5164
5165 if (offsets && instr->op == nir_texop_txf) {
5166 nir_const_value *const_offset =
5167 nir_src_as_const_value(instr->src[const_src].src);
5168 int num_offsets = instr->src[const_src].src.ssa->num_components;
5169 assert(const_offset);
5170 num_offsets = MIN2(num_offsets, instr->coord_components);
5171 if (num_offsets > 2)
5172 address[2] = LLVMBuildAdd(ctx->ac.builder,
5173 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5174 if (num_offsets > 1)
5175 address[1] = LLVMBuildAdd(ctx->ac.builder,
5176 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5177 address[0] = LLVMBuildAdd(ctx->ac.builder,
5178 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5179
5180 }
5181
5182 /* TODO TG4 support */
5183 if (instr->op == nir_texop_tg4) {
5184 if (instr->is_shadow)
5185 dmask = 1;
5186 else
5187 dmask = 1 << instr->component;
5188 }
5189 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5190 res_ptr, samp_ptr, address, count, dmask);
5191
5192 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5193
5194 if (instr->op == nir_texop_query_levels)
5195 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5196 else if (instr->is_shadow && instr->is_new_style_shadow &&
5197 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5198 instr->op != nir_texop_tg4)
5199 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5200 else if (instr->op == nir_texop_txs &&
5201 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5202 instr->is_array) {
5203 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5204 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5205 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5206 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5207 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5208 } else if (ctx->ac.chip_class >= GFX9 &&
5209 instr->op == nir_texop_txs &&
5210 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5211 instr->is_array) {
5212 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5213 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5214 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5215 ctx->ac.i32_1, "");
5216 } else if (instr->dest.ssa.num_components != 4)
5217 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5218
5219 write_result:
5220 if (result) {
5221 assert(instr->dest.is_ssa);
5222 result = ac_to_integer(&ctx->ac, result);
5223 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5224 }
5225 }
5226
5227
5228 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5229 {
5230 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5231 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5232
5233 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5234 _mesa_hash_table_insert(ctx->phis, instr, result);
5235 }
5236
5237 static void visit_post_phi(struct ac_nir_context *ctx,
5238 nir_phi_instr *instr,
5239 LLVMValueRef llvm_phi)
5240 {
5241 nir_foreach_phi_src(src, instr) {
5242 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5243 LLVMValueRef llvm_src = get_src(ctx, src->src);
5244
5245 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5246 }
5247 }
5248
5249 static void phi_post_pass(struct ac_nir_context *ctx)
5250 {
5251 struct hash_entry *entry;
5252 hash_table_foreach(ctx->phis, entry) {
5253 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5254 (LLVMValueRef)entry->data);
5255 }
5256 }
5257
5258
5259 static void visit_ssa_undef(struct ac_nir_context *ctx,
5260 const nir_ssa_undef_instr *instr)
5261 {
5262 unsigned num_components = instr->def.num_components;
5263 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5264 LLVMValueRef undef;
5265
5266 if (num_components == 1)
5267 undef = LLVMGetUndef(type);
5268 else {
5269 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5270 }
5271 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5272 }
5273
5274 static void visit_jump(struct ac_nir_context *ctx,
5275 const nir_jump_instr *instr)
5276 {
5277 switch (instr->type) {
5278 case nir_jump_break:
5279 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5280 LLVMClearInsertionPosition(ctx->ac.builder);
5281 break;
5282 case nir_jump_continue:
5283 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5284 LLVMClearInsertionPosition(ctx->ac.builder);
5285 break;
5286 default:
5287 fprintf(stderr, "Unknown NIR jump instr: ");
5288 nir_print_instr(&instr->instr, stderr);
5289 fprintf(stderr, "\n");
5290 abort();
5291 }
5292 }
5293
5294 static void visit_cf_list(struct ac_nir_context *ctx,
5295 struct exec_list *list);
5296
5297 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5298 {
5299 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5300 nir_foreach_instr(instr, block)
5301 {
5302 switch (instr->type) {
5303 case nir_instr_type_alu:
5304 visit_alu(ctx, nir_instr_as_alu(instr));
5305 break;
5306 case nir_instr_type_load_const:
5307 visit_load_const(ctx, nir_instr_as_load_const(instr));
5308 break;
5309 case nir_instr_type_intrinsic:
5310 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5311 break;
5312 case nir_instr_type_tex:
5313 visit_tex(ctx, nir_instr_as_tex(instr));
5314 break;
5315 case nir_instr_type_phi:
5316 visit_phi(ctx, nir_instr_as_phi(instr));
5317 break;
5318 case nir_instr_type_ssa_undef:
5319 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5320 break;
5321 case nir_instr_type_jump:
5322 visit_jump(ctx, nir_instr_as_jump(instr));
5323 break;
5324 default:
5325 fprintf(stderr, "Unknown NIR instr type: ");
5326 nir_print_instr(instr, stderr);
5327 fprintf(stderr, "\n");
5328 abort();
5329 }
5330 }
5331
5332 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5333 }
5334
5335 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5336 {
5337 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5338
5339 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5340 LLVMBasicBlockRef merge_block =
5341 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5342 LLVMBasicBlockRef if_block =
5343 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5344 LLVMBasicBlockRef else_block = merge_block;
5345 if (!exec_list_is_empty(&if_stmt->else_list))
5346 else_block = LLVMAppendBasicBlockInContext(
5347 ctx->ac.context, fn, "");
5348
5349 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5350 ctx->ac.i32_0, "");
5351 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5352
5353 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5354 visit_cf_list(ctx, &if_stmt->then_list);
5355 if (LLVMGetInsertBlock(ctx->ac.builder))
5356 LLVMBuildBr(ctx->ac.builder, merge_block);
5357
5358 if (!exec_list_is_empty(&if_stmt->else_list)) {
5359 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5360 visit_cf_list(ctx, &if_stmt->else_list);
5361 if (LLVMGetInsertBlock(ctx->ac.builder))
5362 LLVMBuildBr(ctx->ac.builder, merge_block);
5363 }
5364
5365 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5366 }
5367
5368 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5369 {
5370 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5371 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5372 LLVMBasicBlockRef break_parent = ctx->break_block;
5373
5374 ctx->continue_block =
5375 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5376 ctx->break_block =
5377 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5378
5379 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5380 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5381 visit_cf_list(ctx, &loop->body);
5382
5383 if (LLVMGetInsertBlock(ctx->ac.builder))
5384 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5385 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5386
5387 ctx->continue_block = continue_parent;
5388 ctx->break_block = break_parent;
5389 }
5390
5391 static void visit_cf_list(struct ac_nir_context *ctx,
5392 struct exec_list *list)
5393 {
5394 foreach_list_typed(nir_cf_node, node, node, list)
5395 {
5396 switch (node->type) {
5397 case nir_cf_node_block:
5398 visit_block(ctx, nir_cf_node_as_block(node));
5399 break;
5400
5401 case nir_cf_node_if:
5402 visit_if(ctx, nir_cf_node_as_if(node));
5403 break;
5404
5405 case nir_cf_node_loop:
5406 visit_loop(ctx, nir_cf_node_as_loop(node));
5407 break;
5408
5409 default:
5410 assert(0);
5411 }
5412 }
5413 }
5414
5415 static void
5416 handle_vs_input_decl(struct radv_shader_context *ctx,
5417 struct nir_variable *variable)
5418 {
5419 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5420 LLVMValueRef t_offset;
5421 LLVMValueRef t_list;
5422 LLVMValueRef input;
5423 LLVMValueRef buffer_index;
5424 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5425 int idx = variable->data.location;
5426 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5427 uint8_t input_usage_mask =
5428 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5429 unsigned num_channels = util_last_bit(input_usage_mask);
5430
5431 variable->data.driver_location = idx * 4;
5432
5433 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5434 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5435 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
5436 ctx->abi.start_instance, "");
5437 if (ctx->options->key.vs.as_ls) {
5438 ctx->shader_info->vs.vgpr_comp_cnt =
5439 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5440 } else {
5441 ctx->shader_info->vs.vgpr_comp_cnt =
5442 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5443 }
5444 } else
5445 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
5446 ctx->abi.base_vertex, "");
5447 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5448
5449 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5450
5451 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5452 buffer_index,
5453 ctx->ac.i32_0,
5454 num_channels, false, true);
5455
5456 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5457
5458 for (unsigned chan = 0; chan < 4; chan++) {
5459 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5460 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5461 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
5462 input, llvm_chan, ""));
5463 }
5464 }
5465 }
5466
5467 static void interp_fs_input(struct radv_shader_context *ctx,
5468 unsigned attr,
5469 LLVMValueRef interp_param,
5470 LLVMValueRef prim_mask,
5471 LLVMValueRef result[4])
5472 {
5473 LLVMValueRef attr_number;
5474 unsigned chan;
5475 LLVMValueRef i, j;
5476 bool interp = interp_param != NULL;
5477
5478 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5479
5480 /* fs.constant returns the param from the middle vertex, so it's not
5481 * really useful for flat shading. It's meant to be used for custom
5482 * interpolation (but the intrinsic can't fetch from the other two
5483 * vertices).
5484 *
5485 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5486 * to do the right thing. The only reason we use fs.constant is that
5487 * fs.interp cannot be used on integers, because they can be equal
5488 * to NaN.
5489 */
5490 if (interp) {
5491 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
5492 ctx->ac.v2f32, "");
5493
5494 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5495 ctx->ac.i32_0, "");
5496 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5497 ctx->ac.i32_1, "");
5498 }
5499
5500 for (chan = 0; chan < 4; chan++) {
5501 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5502
5503 if (interp) {
5504 result[chan] = ac_build_fs_interp(&ctx->ac,
5505 llvm_chan,
5506 attr_number,
5507 prim_mask, i, j);
5508 } else {
5509 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5510 LLVMConstInt(ctx->ac.i32, 2, false),
5511 llvm_chan,
5512 attr_number,
5513 prim_mask);
5514 }
5515 }
5516 }
5517
5518 static void
5519 handle_fs_input_decl(struct radv_shader_context *ctx,
5520 struct nir_variable *variable)
5521 {
5522 int idx = variable->data.location;
5523 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5524 LLVMValueRef interp;
5525
5526 variable->data.driver_location = idx * 4;
5527 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5528
5529 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5530 unsigned interp_type;
5531 if (variable->data.sample)
5532 interp_type = INTERP_SAMPLE;
5533 else if (variable->data.centroid)
5534 interp_type = INTERP_CENTROID;
5535 else
5536 interp_type = INTERP_CENTER;
5537
5538 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5539 } else
5540 interp = NULL;
5541
5542 for (unsigned i = 0; i < attrib_count; ++i)
5543 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5544
5545 }
5546
5547 static void
5548 handle_vs_inputs(struct radv_shader_context *ctx,
5549 struct nir_shader *nir) {
5550 nir_foreach_variable(variable, &nir->inputs)
5551 handle_vs_input_decl(ctx, variable);
5552 }
5553
5554 static void
5555 prepare_interp_optimize(struct radv_shader_context *ctx,
5556 struct nir_shader *nir)
5557 {
5558 if (!ctx->options->key.fs.multisample)
5559 return;
5560
5561 bool uses_center = false;
5562 bool uses_centroid = false;
5563 nir_foreach_variable(variable, &nir->inputs) {
5564 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5565 variable->data.sample)
5566 continue;
5567
5568 if (variable->data.centroid)
5569 uses_centroid = true;
5570 else
5571 uses_center = true;
5572 }
5573
5574 if (uses_center && uses_centroid) {
5575 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5576 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5577 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5578 }
5579 }
5580
5581 static void
5582 handle_fs_inputs(struct radv_shader_context *ctx,
5583 struct nir_shader *nir)
5584 {
5585 prepare_interp_optimize(ctx, nir);
5586
5587 nir_foreach_variable(variable, &nir->inputs)
5588 handle_fs_input_decl(ctx, variable);
5589
5590 unsigned index = 0;
5591
5592 if (ctx->shader_info->info.ps.uses_input_attachments ||
5593 ctx->shader_info->info.needs_multiview_view_index)
5594 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5595
5596 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5597 LLVMValueRef interp_param;
5598 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5599
5600 if (!(ctx->input_mask & (1ull << i)))
5601 continue;
5602
5603 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5604 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5605 interp_param = *inputs;
5606 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5607 inputs);
5608
5609 if (!interp_param)
5610 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5611 ++index;
5612 } else if (i == VARYING_SLOT_POS) {
5613 for(int i = 0; i < 3; ++i)
5614 inputs[i] = ctx->abi.frag_pos[i];
5615
5616 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5617 ctx->abi.frag_pos[3]);
5618 }
5619 }
5620 ctx->shader_info->fs.num_interp = index;
5621 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5622 ctx->shader_info->fs.has_pcoord = true;
5623 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5624 ctx->shader_info->fs.prim_id_input = true;
5625 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5626 ctx->shader_info->fs.layer_input = true;
5627 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5628
5629 if (ctx->shader_info->info.needs_multiview_view_index)
5630 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5631 }
5632
5633 static LLVMValueRef
5634 ac_build_alloca(struct ac_llvm_context *ac,
5635 LLVMTypeRef type,
5636 const char *name)
5637 {
5638 LLVMBuilderRef builder = ac->builder;
5639 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5640 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5641 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5642 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5643 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5644 LLVMValueRef res;
5645
5646 if (first_instr) {
5647 LLVMPositionBuilderBefore(first_builder, first_instr);
5648 } else {
5649 LLVMPositionBuilderAtEnd(first_builder, first_block);
5650 }
5651
5652 res = LLVMBuildAlloca(first_builder, type, name);
5653 LLVMBuildStore(builder, LLVMConstNull(type), res);
5654
5655 LLVMDisposeBuilder(first_builder);
5656
5657 return res;
5658 }
5659
5660 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5661 LLVMTypeRef type,
5662 const char *name)
5663 {
5664 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5665 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5666 return ptr;
5667 }
5668
5669 static void
5670 scan_shader_output_decl(struct radv_shader_context *ctx,
5671 struct nir_variable *variable,
5672 struct nir_shader *shader,
5673 gl_shader_stage stage)
5674 {
5675 int idx = variable->data.location + variable->data.index;
5676 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5677 uint64_t mask_attribs;
5678
5679 variable->data.driver_location = idx * 4;
5680
5681 /* tess ctrl has it's own load/store paths for outputs */
5682 if (stage == MESA_SHADER_TESS_CTRL)
5683 return;
5684
5685 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5686 if (stage == MESA_SHADER_VERTEX ||
5687 stage == MESA_SHADER_TESS_EVAL ||
5688 stage == MESA_SHADER_GEOMETRY) {
5689 if (idx == VARYING_SLOT_CLIP_DIST0) {
5690 int length = shader->info.clip_distance_array_size +
5691 shader->info.cull_distance_array_size;
5692 if (stage == MESA_SHADER_VERTEX) {
5693 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5694 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5695 }
5696 if (stage == MESA_SHADER_TESS_EVAL) {
5697 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5698 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5699 }
5700
5701 if (length > 4)
5702 attrib_count = 2;
5703 else
5704 attrib_count = 1;
5705 mask_attribs = 1ull << idx;
5706 }
5707 }
5708
5709 ctx->output_mask |= mask_attribs;
5710 }
5711
5712 static void
5713 handle_shader_output_decl(struct ac_nir_context *ctx,
5714 struct nir_shader *nir,
5715 struct nir_variable *variable)
5716 {
5717 unsigned output_loc = variable->data.driver_location / 4;
5718 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5719
5720 /* tess ctrl has it's own load/store paths for outputs */
5721 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5722 return;
5723
5724 if (ctx->stage == MESA_SHADER_VERTEX ||
5725 ctx->stage == MESA_SHADER_TESS_EVAL ||
5726 ctx->stage == MESA_SHADER_GEOMETRY) {
5727 int idx = variable->data.location + variable->data.index;
5728 if (idx == VARYING_SLOT_CLIP_DIST0) {
5729 int length = nir->info.clip_distance_array_size +
5730 nir->info.cull_distance_array_size;
5731
5732 if (length > 4)
5733 attrib_count = 2;
5734 else
5735 attrib_count = 1;
5736 }
5737 }
5738
5739 for (unsigned i = 0; i < attrib_count; ++i) {
5740 for (unsigned chan = 0; chan < 4; chan++) {
5741 ctx->abi->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5742 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5743 }
5744 }
5745 }
5746
5747 static LLVMTypeRef
5748 glsl_base_to_llvm_type(struct ac_llvm_context *ac,
5749 enum glsl_base_type type)
5750 {
5751 switch (type) {
5752 case GLSL_TYPE_INT:
5753 case GLSL_TYPE_UINT:
5754 case GLSL_TYPE_BOOL:
5755 case GLSL_TYPE_SUBROUTINE:
5756 return ac->i32;
5757 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5758 return ac->f32;
5759 case GLSL_TYPE_INT64:
5760 case GLSL_TYPE_UINT64:
5761 return ac->i64;
5762 case GLSL_TYPE_DOUBLE:
5763 return ac->f64;
5764 default:
5765 unreachable("unknown GLSL type");
5766 }
5767 }
5768
5769 static LLVMTypeRef
5770 glsl_to_llvm_type(struct ac_llvm_context *ac,
5771 const struct glsl_type *type)
5772 {
5773 if (glsl_type_is_scalar(type)) {
5774 return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
5775 }
5776
5777 if (glsl_type_is_vector(type)) {
5778 return LLVMVectorType(
5779 glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
5780 glsl_get_vector_elements(type));
5781 }
5782
5783 if (glsl_type_is_matrix(type)) {
5784 return LLVMArrayType(
5785 glsl_to_llvm_type(ac, glsl_get_column_type(type)),
5786 glsl_get_matrix_columns(type));
5787 }
5788
5789 if (glsl_type_is_array(type)) {
5790 return LLVMArrayType(
5791 glsl_to_llvm_type(ac, glsl_get_array_element(type)),
5792 glsl_get_length(type));
5793 }
5794
5795 assert(glsl_type_is_struct(type));
5796
5797 LLVMTypeRef member_types[glsl_get_length(type)];
5798
5799 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5800 member_types[i] =
5801 glsl_to_llvm_type(ac,
5802 glsl_get_struct_field(type, i));
5803 }
5804
5805 return LLVMStructTypeInContext(ac->context, member_types,
5806 glsl_get_length(type), false);
5807 }
5808
5809 static void
5810 setup_locals(struct ac_nir_context *ctx,
5811 struct nir_function *func)
5812 {
5813 int i, j;
5814 ctx->num_locals = 0;
5815 nir_foreach_variable(variable, &func->impl->locals) {
5816 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5817 variable->data.driver_location = ctx->num_locals * 4;
5818 variable->data.location_frac = 0;
5819 ctx->num_locals += attrib_count;
5820 }
5821 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5822 if (!ctx->locals)
5823 return;
5824
5825 for (i = 0; i < ctx->num_locals; i++) {
5826 for (j = 0; j < 4; j++) {
5827 ctx->locals[i * 4 + j] =
5828 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5829 }
5830 }
5831 }
5832
5833 static void
5834 setup_shared(struct ac_nir_context *ctx,
5835 struct nir_shader *nir)
5836 {
5837 nir_foreach_variable(variable, &nir->shared) {
5838 LLVMValueRef shared =
5839 LLVMAddGlobalInAddressSpace(
5840 ctx->ac.module, glsl_to_llvm_type(&ctx->ac, variable->type),
5841 variable->name ? variable->name : "",
5842 AC_LOCAL_ADDR_SPACE);
5843 _mesa_hash_table_insert(ctx->vars, variable, shared);
5844 }
5845 }
5846
5847 /* Initialize arguments for the shader export intrinsic */
5848 static void
5849 si_llvm_init_export_args(struct radv_shader_context *ctx,
5850 LLVMValueRef *values,
5851 unsigned target,
5852 struct ac_export_args *args)
5853 {
5854 /* Default is 0xf. Adjusted below depending on the format. */
5855 args->enabled_channels = 0xf;
5856
5857 /* Specify whether the EXEC mask represents the valid mask */
5858 args->valid_mask = 0;
5859
5860 /* Specify whether this is the last export */
5861 args->done = 0;
5862
5863 /* Specify the target we are exporting */
5864 args->target = target;
5865
5866 args->compr = false;
5867 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5868 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5869 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5870 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5871
5872 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5873 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5874 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5875 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5876 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5877 unsigned chan;
5878
5879 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5880 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5881 unsigned bits, bool hi) = NULL;
5882
5883 switch(col_format) {
5884 case V_028714_SPI_SHADER_ZERO:
5885 args->enabled_channels = 0; /* writemask */
5886 args->target = V_008DFC_SQ_EXP_NULL;
5887 break;
5888
5889 case V_028714_SPI_SHADER_32_R:
5890 args->enabled_channels = 1;
5891 args->out[0] = values[0];
5892 break;
5893
5894 case V_028714_SPI_SHADER_32_GR:
5895 args->enabled_channels = 0x3;
5896 args->out[0] = values[0];
5897 args->out[1] = values[1];
5898 break;
5899
5900 case V_028714_SPI_SHADER_32_AR:
5901 args->enabled_channels = 0x9;
5902 args->out[0] = values[0];
5903 args->out[3] = values[3];
5904 break;
5905
5906 case V_028714_SPI_SHADER_FP16_ABGR:
5907 packf = ac_build_cvt_pkrtz_f16;
5908 break;
5909
5910 case V_028714_SPI_SHADER_UNORM16_ABGR:
5911 packf = ac_build_cvt_pknorm_u16;
5912 break;
5913
5914 case V_028714_SPI_SHADER_SNORM16_ABGR:
5915 packf = ac_build_cvt_pknorm_i16;
5916 break;
5917
5918 case V_028714_SPI_SHADER_UINT16_ABGR:
5919 packi = ac_build_cvt_pk_u16;
5920 break;
5921
5922 case V_028714_SPI_SHADER_SINT16_ABGR:
5923 packi = ac_build_cvt_pk_i16;
5924 break;
5925
5926 default:
5927 case V_028714_SPI_SHADER_32_ABGR:
5928 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5929 break;
5930 }
5931
5932 /* Pack f16 or norm_i16/u16. */
5933 if (packf) {
5934 for (chan = 0; chan < 2; chan++) {
5935 LLVMValueRef pack_args[2] = {
5936 values[2 * chan],
5937 values[2 * chan + 1]
5938 };
5939 LLVMValueRef packed;
5940
5941 packed = packf(&ctx->ac, pack_args);
5942 args->out[chan] = ac_to_float(&ctx->ac, packed);
5943 }
5944 args->compr = 1; /* COMPR flag */
5945 }
5946
5947 /* Pack i16/u16. */
5948 if (packi) {
5949 for (chan = 0; chan < 2; chan++) {
5950 LLVMValueRef pack_args[2] = {
5951 ac_to_integer(&ctx->ac, values[2 * chan]),
5952 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5953 };
5954 LLVMValueRef packed;
5955
5956 packed = packi(&ctx->ac, pack_args,
5957 is_int8 ? 8 : is_int10 ? 10 : 16,
5958 chan == 1);
5959 args->out[chan] = ac_to_float(&ctx->ac, packed);
5960 }
5961 args->compr = 1; /* COMPR flag */
5962 }
5963 return;
5964 }
5965
5966 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5967
5968 for (unsigned i = 0; i < 4; ++i)
5969 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5970 }
5971
5972 static void
5973 radv_export_param(struct radv_shader_context *ctx, unsigned index,
5974 LLVMValueRef *values)
5975 {
5976 struct ac_export_args args;
5977
5978 si_llvm_init_export_args(ctx, values,
5979 V_008DFC_SQ_EXP_PARAM + index, &args);
5980 ac_build_export(&ctx->ac, &args);
5981 }
5982
5983 static LLVMValueRef
5984 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
5985 {
5986 LLVMValueRef output =
5987 ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
5988
5989 return LLVMBuildLoad(ctx->ac.builder, output, "");
5990 }
5991
5992 static void
5993 handle_vs_outputs_post(struct radv_shader_context *ctx,
5994 bool export_prim_id,
5995 struct ac_vs_output_info *outinfo)
5996 {
5997 uint32_t param_count = 0;
5998 unsigned target;
5999 unsigned pos_idx, num_pos_exports = 0;
6000 struct ac_export_args args, pos_args[4] = {};
6001 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
6002 int i;
6003
6004 if (ctx->options->key.has_multiview_view_index) {
6005 LLVMValueRef* tmp_out = &ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
6006 if(!*tmp_out) {
6007 for(unsigned i = 0; i < 4; ++i)
6008 ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
6009 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
6010 }
6011
6012 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
6013 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
6014 }
6015
6016 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6017 sizeof(outinfo->vs_output_param_offset));
6018
6019 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
6020 LLVMValueRef slots[8];
6021 unsigned j;
6022
6023 if (outinfo->cull_dist_mask)
6024 outinfo->cull_dist_mask <<= ctx->num_output_clips;
6025
6026 i = VARYING_SLOT_CLIP_DIST0;
6027 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
6028 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6029
6030 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
6031 slots[i] = LLVMGetUndef(ctx->ac.f32);
6032
6033 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
6034 target = V_008DFC_SQ_EXP_POS + 3;
6035 si_llvm_init_export_args(ctx, &slots[4], target, &args);
6036 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6037 &args, sizeof(args));
6038 }
6039
6040 target = V_008DFC_SQ_EXP_POS + 2;
6041 si_llvm_init_export_args(ctx, &slots[0], target, &args);
6042 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6043 &args, sizeof(args));
6044
6045 }
6046
6047 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
6048 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
6049 for (unsigned j = 0; j < 4; j++)
6050 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
6051 }
6052 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
6053
6054 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
6055 outinfo->writes_pointsize = true;
6056 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
6057 }
6058
6059 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
6060 outinfo->writes_layer = true;
6061 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
6062 }
6063
6064 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
6065 outinfo->writes_viewport_index = true;
6066 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
6067 }
6068
6069 if (outinfo->writes_pointsize ||
6070 outinfo->writes_layer ||
6071 outinfo->writes_viewport_index) {
6072 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
6073 (outinfo->writes_layer == true ? 4 : 0));
6074 pos_args[1].valid_mask = 0;
6075 pos_args[1].done = 0;
6076 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6077 pos_args[1].compr = 0;
6078 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6079 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6080 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6081 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6082
6083 if (outinfo->writes_pointsize == true)
6084 pos_args[1].out[0] = psize_value;
6085 if (outinfo->writes_layer == true)
6086 pos_args[1].out[2] = layer_value;
6087 if (outinfo->writes_viewport_index == true) {
6088 if (ctx->options->chip_class >= GFX9) {
6089 /* GFX9 has the layer in out.z[10:0] and the viewport
6090 * index in out.z[19:16].
6091 */
6092 LLVMValueRef v = viewport_index_value;
6093 v = ac_to_integer(&ctx->ac, v);
6094 v = LLVMBuildShl(ctx->ac.builder, v,
6095 LLVMConstInt(ctx->ac.i32, 16, false),
6096 "");
6097 v = LLVMBuildOr(ctx->ac.builder, v,
6098 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6099
6100 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6101 pos_args[1].enabled_channels |= 1 << 2;
6102 } else {
6103 pos_args[1].out[3] = viewport_index_value;
6104 pos_args[1].enabled_channels |= 1 << 3;
6105 }
6106 }
6107 }
6108 for (i = 0; i < 4; i++) {
6109 if (pos_args[i].out[0])
6110 num_pos_exports++;
6111 }
6112
6113 pos_idx = 0;
6114 for (i = 0; i < 4; i++) {
6115 if (!pos_args[i].out[0])
6116 continue;
6117
6118 /* Specify the target we are exporting */
6119 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6120 if (pos_idx == num_pos_exports)
6121 pos_args[i].done = 1;
6122 ac_build_export(&ctx->ac, &pos_args[i]);
6123 }
6124
6125 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6126 LLVMValueRef values[4];
6127 if (!(ctx->output_mask & (1ull << i)))
6128 continue;
6129
6130 if (i != VARYING_SLOT_LAYER &&
6131 i != VARYING_SLOT_PRIMITIVE_ID &&
6132 i < VARYING_SLOT_VAR0)
6133 continue;
6134
6135 for (unsigned j = 0; j < 4; j++)
6136 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6137
6138 radv_export_param(ctx, param_count, values);
6139
6140 outinfo->vs_output_param_offset[i] = param_count++;
6141 }
6142
6143 if (export_prim_id) {
6144 LLVMValueRef values[4];
6145
6146 values[0] = ctx->vs_prim_id;
6147 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6148 ctx->shader_info->vs.vgpr_comp_cnt);
6149 for (unsigned j = 1; j < 4; j++)
6150 values[j] = ctx->ac.f32_0;
6151
6152 radv_export_param(ctx, param_count, values);
6153
6154 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6155 outinfo->export_prim_id = true;
6156 }
6157
6158 outinfo->pos_exports = num_pos_exports;
6159 outinfo->param_exports = param_count;
6160 }
6161
6162 static void
6163 handle_es_outputs_post(struct radv_shader_context *ctx,
6164 struct ac_es_output_info *outinfo)
6165 {
6166 int j;
6167 uint64_t max_output_written = 0;
6168 LLVMValueRef lds_base = NULL;
6169
6170 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6171 int param_index;
6172 int length = 4;
6173
6174 if (!(ctx->output_mask & (1ull << i)))
6175 continue;
6176
6177 if (i == VARYING_SLOT_CLIP_DIST0)
6178 length = ctx->num_output_clips + ctx->num_output_culls;
6179
6180 param_index = shader_io_get_unique_index(i);
6181
6182 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6183 }
6184
6185 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6186
6187 if (ctx->ac.chip_class >= GFX9) {
6188 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6189 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6190 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6191 LLVMConstInt(ctx->ac.i32, 24, false),
6192 LLVMConstInt(ctx->ac.i32, 4, false), false);
6193 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6194 LLVMBuildMul(ctx->ac.builder, wave_idx,
6195 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6196 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6197 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6198 }
6199
6200 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6201 LLVMValueRef dw_addr = NULL;
6202 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6203 int param_index;
6204 int length = 4;
6205
6206 if (!(ctx->output_mask & (1ull << i)))
6207 continue;
6208
6209 if (i == VARYING_SLOT_CLIP_DIST0)
6210 length = ctx->num_output_clips + ctx->num_output_culls;
6211
6212 param_index = shader_io_get_unique_index(i);
6213
6214 if (lds_base) {
6215 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
6216 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6217 "");
6218 }
6219 for (j = 0; j < length; j++) {
6220 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
6221 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
6222
6223 if (ctx->ac.chip_class >= GFX9) {
6224 ac_lds_store(&ctx->ac, dw_addr,
6225 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6226 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6227 } else {
6228 ac_build_buffer_store_dword(&ctx->ac,
6229 ctx->esgs_ring,
6230 out_val, 1,
6231 NULL, ctx->es2gs_offset,
6232 (4 * param_index + j) * 4,
6233 1, 1, true, true);
6234 }
6235 }
6236 }
6237 }
6238
6239 static void
6240 handle_ls_outputs_post(struct radv_shader_context *ctx)
6241 {
6242 LLVMValueRef vertex_id = ctx->rel_auto_id;
6243 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6244 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
6245 vertex_dw_stride, "");
6246
6247 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6248 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6249 int length = 4;
6250
6251 if (!(ctx->output_mask & (1ull << i)))
6252 continue;
6253
6254 if (i == VARYING_SLOT_CLIP_DIST0)
6255 length = ctx->num_output_clips + ctx->num_output_culls;
6256 int param = shader_io_get_unique_index(i);
6257 mark_tess_output(ctx, false, param);
6258 if (length > 4)
6259 mark_tess_output(ctx, false, param + 1);
6260 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
6261 LLVMConstInt(ctx->ac.i32, param * 4, false),
6262 "");
6263 for (unsigned j = 0; j < length; j++) {
6264 ac_lds_store(&ctx->ac, dw_addr,
6265 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6266 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6267 }
6268 }
6269 }
6270
6271 struct ac_build_if_state
6272 {
6273 struct radv_shader_context *ctx;
6274 LLVMValueRef condition;
6275 LLVMBasicBlockRef entry_block;
6276 LLVMBasicBlockRef true_block;
6277 LLVMBasicBlockRef false_block;
6278 LLVMBasicBlockRef merge_block;
6279 };
6280
6281 static LLVMBasicBlockRef
6282 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
6283 {
6284 LLVMBasicBlockRef current_block;
6285 LLVMBasicBlockRef next_block;
6286 LLVMBasicBlockRef new_block;
6287
6288 /* get current basic block */
6289 current_block = LLVMGetInsertBlock(ctx->ac.builder);
6290
6291 /* chqeck if there's another block after this one */
6292 next_block = LLVMGetNextBasicBlock(current_block);
6293 if (next_block) {
6294 /* insert the new block before the next block */
6295 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6296 }
6297 else {
6298 /* append new block after current block */
6299 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6300 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6301 }
6302 return new_block;
6303 }
6304
6305 static void
6306 ac_nir_build_if(struct ac_build_if_state *ifthen,
6307 struct radv_shader_context *ctx,
6308 LLVMValueRef condition)
6309 {
6310 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
6311
6312 memset(ifthen, 0, sizeof *ifthen);
6313 ifthen->ctx = ctx;
6314 ifthen->condition = condition;
6315 ifthen->entry_block = block;
6316
6317 /* create endif/merge basic block for the phi functions */
6318 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6319
6320 /* create/insert true_block before merge_block */
6321 ifthen->true_block =
6322 LLVMInsertBasicBlockInContext(ctx->context,
6323 ifthen->merge_block,
6324 "if-true-block");
6325
6326 /* successive code goes into the true block */
6327 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
6328 }
6329
6330 /**
6331 * End a conditional.
6332 */
6333 static void
6334 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6335 {
6336 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
6337
6338 /* Insert branch to the merge block from current block */
6339 LLVMBuildBr(builder, ifthen->merge_block);
6340
6341 /*
6342 * Now patch in the various branch instructions.
6343 */
6344
6345 /* Insert the conditional branch instruction at the end of entry_block */
6346 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6347 if (ifthen->false_block) {
6348 /* we have an else clause */
6349 LLVMBuildCondBr(builder, ifthen->condition,
6350 ifthen->true_block, ifthen->false_block);
6351 }
6352 else {
6353 /* no else clause */
6354 LLVMBuildCondBr(builder, ifthen->condition,
6355 ifthen->true_block, ifthen->merge_block);
6356 }
6357
6358 /* Resume building code at end of the ifthen->merge_block */
6359 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6360 }
6361
6362 static void
6363 write_tess_factors(struct radv_shader_context *ctx)
6364 {
6365 unsigned stride, outer_comps, inner_comps;
6366 struct ac_build_if_state if_ctx, inner_if_ctx;
6367 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6368 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6369 unsigned tess_inner_index = 0, tess_outer_index;
6370 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
6371 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6372 int i;
6373 emit_barrier(&ctx->ac, ctx->stage);
6374
6375 switch (ctx->options->key.tcs.primitive_mode) {
6376 case GL_ISOLINES:
6377 stride = 2;
6378 outer_comps = 2;
6379 inner_comps = 0;
6380 break;
6381 case GL_TRIANGLES:
6382 stride = 4;
6383 outer_comps = 3;
6384 inner_comps = 1;
6385 break;
6386 case GL_QUADS:
6387 stride = 6;
6388 outer_comps = 4;
6389 inner_comps = 2;
6390 break;
6391 default:
6392 return;
6393 }
6394
6395 ac_nir_build_if(&if_ctx, ctx,
6396 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6397 invocation_id, ctx->ac.i32_0, ""));
6398
6399 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6400
6401 if (inner_comps) {
6402 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6403 mark_tess_output(ctx, true, tess_inner_index);
6404 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
6405 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6406 }
6407
6408 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6409 mark_tess_output(ctx, true, tess_outer_index);
6410 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
6411 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6412
6413 for (i = 0; i < 4; i++) {
6414 inner[i] = LLVMGetUndef(ctx->ac.i32);
6415 outer[i] = LLVMGetUndef(ctx->ac.i32);
6416 }
6417
6418 // LINES reverseal
6419 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6420 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6421 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6422 ctx->ac.i32_1, "");
6423 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6424 } else {
6425 for (i = 0; i < outer_comps; i++) {
6426 outer[i] = out[i] =
6427 ac_lds_load(&ctx->ac, lds_outer);
6428 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6429 ctx->ac.i32_1, "");
6430 }
6431 for (i = 0; i < inner_comps; i++) {
6432 inner[i] = out[outer_comps+i] =
6433 ac_lds_load(&ctx->ac, lds_inner);
6434 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
6435 ctx->ac.i32_1, "");
6436 }
6437 }
6438
6439 /* Convert the outputs to vectors for stores. */
6440 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6441 vec1 = NULL;
6442
6443 if (stride > 4)
6444 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6445
6446
6447 buffer = ctx->hs_ring_tess_factor;
6448 tf_base = ctx->tess_factor_offset;
6449 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
6450 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6451 unsigned tf_offset = 0;
6452
6453 if (ctx->options->chip_class <= VI) {
6454 ac_nir_build_if(&inner_if_ctx, ctx,
6455 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6456 rel_patch_id, ctx->ac.i32_0, ""));
6457
6458 /* Store the dynamic HS control word. */
6459 ac_build_buffer_store_dword(&ctx->ac, buffer,
6460 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6461 1, ctx->ac.i32_0, tf_base,
6462 0, 1, 0, true, false);
6463 tf_offset += 4;
6464
6465 ac_nir_build_endif(&inner_if_ctx);
6466 }
6467
6468 /* Store the tessellation factors. */
6469 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6470 MIN2(stride, 4), byteoffset, tf_base,
6471 tf_offset, 1, 0, true, false);
6472 if (vec1)
6473 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6474 stride - 4, byteoffset, tf_base,
6475 16 + tf_offset, 1, 0, true, false);
6476
6477 //store to offchip for TES to read - only if TES reads them
6478 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6479 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6480 LLVMValueRef tf_inner_offset;
6481 unsigned param_outer, param_inner;
6482
6483 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6484 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6485 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6486
6487 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6488 util_next_power_of_two(outer_comps));
6489
6490 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6491 outer_comps, tf_outer_offset,
6492 ctx->oc_lds, 0, 1, 0, true, false);
6493 if (inner_comps) {
6494 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6495 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6496 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6497
6498 inner_vec = inner_comps == 1 ? inner[0] :
6499 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6500 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6501 inner_comps, tf_inner_offset,
6502 ctx->oc_lds, 0, 1, 0, true, false);
6503 }
6504 }
6505 ac_nir_build_endif(&if_ctx);
6506 }
6507
6508 static void
6509 handle_tcs_outputs_post(struct radv_shader_context *ctx)
6510 {
6511 write_tess_factors(ctx);
6512 }
6513
6514 static bool
6515 si_export_mrt_color(struct radv_shader_context *ctx,
6516 LLVMValueRef *color, unsigned index, bool is_last,
6517 struct ac_export_args *args)
6518 {
6519 /* Export */
6520 si_llvm_init_export_args(ctx, color,
6521 V_008DFC_SQ_EXP_MRT + index, args);
6522
6523 if (is_last) {
6524 args->valid_mask = 1; /* whether the EXEC mask is valid */
6525 args->done = 1; /* DONE bit */
6526 } else if (!args->enabled_channels)
6527 return false; /* unnecessary NULL export */
6528
6529 return true;
6530 }
6531
6532 static void
6533 radv_export_mrt_z(struct radv_shader_context *ctx,
6534 LLVMValueRef depth, LLVMValueRef stencil,
6535 LLVMValueRef samplemask)
6536 {
6537 struct ac_export_args args;
6538
6539 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6540
6541 ac_build_export(&ctx->ac, &args);
6542 }
6543
6544 static void
6545 handle_fs_outputs_post(struct radv_shader_context *ctx)
6546 {
6547 unsigned index = 0;
6548 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6549 struct ac_export_args color_args[8];
6550
6551 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6552 LLVMValueRef values[4];
6553 bool last = false;
6554
6555 if (!(ctx->output_mask & (1ull << i)))
6556 continue;
6557
6558 if (i < FRAG_RESULT_DATA0)
6559 continue;
6560
6561 for (unsigned j = 0; j < 4; j++)
6562 values[j] = ac_to_float(&ctx->ac,
6563 radv_load_output(ctx, i, j));
6564
6565 if (!ctx->shader_info->info.ps.writes_z &&
6566 !ctx->shader_info->info.ps.writes_stencil &&
6567 !ctx->shader_info->info.ps.writes_sample_mask)
6568 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6569
6570 bool ret = si_export_mrt_color(ctx, values,
6571 i - FRAG_RESULT_DATA0,
6572 last, &color_args[index]);
6573 if (ret)
6574 index++;
6575 }
6576
6577 /* Process depth, stencil, samplemask. */
6578 if (ctx->shader_info->info.ps.writes_z) {
6579 depth = ac_to_float(&ctx->ac,
6580 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6581 }
6582 if (ctx->shader_info->info.ps.writes_stencil) {
6583 stencil = ac_to_float(&ctx->ac,
6584 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6585 }
6586 if (ctx->shader_info->info.ps.writes_sample_mask) {
6587 samplemask = ac_to_float(&ctx->ac,
6588 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6589 }
6590
6591 /* Export PS outputs. */
6592 for (unsigned i = 0; i < index; i++)
6593 ac_build_export(&ctx->ac, &color_args[i]);
6594
6595 if (depth || stencil || samplemask)
6596 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6597 else if (!index)
6598 ac_build_export_null(&ctx->ac);
6599 }
6600
6601 static void
6602 emit_gs_epilogue(struct radv_shader_context *ctx)
6603 {
6604 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6605 }
6606
6607 static void
6608 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6609 LLVMValueRef *addrs)
6610 {
6611 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
6612
6613 switch (ctx->stage) {
6614 case MESA_SHADER_VERTEX:
6615 if (ctx->options->key.vs.as_ls)
6616 handle_ls_outputs_post(ctx);
6617 else if (ctx->options->key.vs.as_es)
6618 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6619 else
6620 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6621 &ctx->shader_info->vs.outinfo);
6622 break;
6623 case MESA_SHADER_FRAGMENT:
6624 handle_fs_outputs_post(ctx);
6625 break;
6626 case MESA_SHADER_GEOMETRY:
6627 emit_gs_epilogue(ctx);
6628 break;
6629 case MESA_SHADER_TESS_CTRL:
6630 handle_tcs_outputs_post(ctx);
6631 break;
6632 case MESA_SHADER_TESS_EVAL:
6633 if (ctx->options->key.tes.as_es)
6634 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6635 else
6636 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6637 &ctx->shader_info->tes.outinfo);
6638 break;
6639 default:
6640 break;
6641 }
6642 }
6643
6644 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
6645 {
6646 LLVMPassManagerRef passmgr;
6647 /* Create the pass manager */
6648 passmgr = LLVMCreateFunctionPassManagerForModule(
6649 ctx->ac.module);
6650
6651 /* This pass should eliminate all the load and store instructions */
6652 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6653
6654 /* Add some optimization passes */
6655 LLVMAddScalarReplAggregatesPass(passmgr);
6656 LLVMAddLICMPass(passmgr);
6657 LLVMAddAggressiveDCEPass(passmgr);
6658 LLVMAddCFGSimplificationPass(passmgr);
6659 LLVMAddInstructionCombiningPass(passmgr);
6660
6661 /* Run the pass */
6662 LLVMInitializeFunctionPassManager(passmgr);
6663 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6664 LLVMFinalizeFunctionPassManager(passmgr);
6665
6666 LLVMDisposeBuilder(ctx->ac.builder);
6667 LLVMDisposePassManager(passmgr);
6668 }
6669
6670 static void
6671 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
6672 {
6673 struct ac_vs_output_info *outinfo;
6674
6675 switch (ctx->stage) {
6676 case MESA_SHADER_FRAGMENT:
6677 case MESA_SHADER_COMPUTE:
6678 case MESA_SHADER_TESS_CTRL:
6679 case MESA_SHADER_GEOMETRY:
6680 return;
6681 case MESA_SHADER_VERTEX:
6682 if (ctx->options->key.vs.as_ls ||
6683 ctx->options->key.vs.as_es)
6684 return;
6685 outinfo = &ctx->shader_info->vs.outinfo;
6686 break;
6687 case MESA_SHADER_TESS_EVAL:
6688 if (ctx->options->key.vs.as_es)
6689 return;
6690 outinfo = &ctx->shader_info->tes.outinfo;
6691 break;
6692 default:
6693 unreachable("Unhandled shader type");
6694 }
6695
6696 ac_optimize_vs_outputs(&ctx->ac,
6697 ctx->main_function,
6698 outinfo->vs_output_param_offset,
6699 VARYING_SLOT_MAX,
6700 &outinfo->param_exports);
6701 }
6702
6703 static void
6704 ac_setup_rings(struct radv_shader_context *ctx)
6705 {
6706 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6707 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6708 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6709 }
6710
6711 if (ctx->is_gs_copy_shader) {
6712 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6713 }
6714 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6715 LLVMValueRef tmp;
6716 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6717 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6718
6719 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6720
6721 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6722 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6723 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
6724 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6725 }
6726
6727 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6728 ctx->stage == MESA_SHADER_TESS_EVAL) {
6729 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6730 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6731 }
6732 }
6733
6734 static unsigned
6735 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6736 const struct nir_shader *nir)
6737 {
6738 switch (nir->info.stage) {
6739 case MESA_SHADER_TESS_CTRL:
6740 return chip_class >= CIK ? 128 : 64;
6741 case MESA_SHADER_GEOMETRY:
6742 return chip_class >= GFX9 ? 128 : 64;
6743 case MESA_SHADER_COMPUTE:
6744 break;
6745 default:
6746 return 0;
6747 }
6748
6749 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6750 nir->info.cs.local_size[1] *
6751 nir->info.cs.local_size[2];
6752 return max_workgroup_size;
6753 }
6754
6755 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6756 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
6757 {
6758 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6759 LLVMConstInt(ctx->ac.i32, 8, false),
6760 LLVMConstInt(ctx->ac.i32, 8, false), false);
6761 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6762 ctx->ac.i32_0, "");
6763 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6764 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6765 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6766 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6767 }
6768
6769 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
6770 {
6771 for(int i = 5; i >= 0; --i) {
6772 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6773 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6774 LLVMConstInt(ctx->ac.i32, 16, false), false);
6775 }
6776
6777 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6778 LLVMConstInt(ctx->ac.i32, 16, false),
6779 LLVMConstInt(ctx->ac.i32, 8, false), false);
6780 }
6781
6782 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6783 struct nir_shader *nir)
6784 {
6785 struct ac_nir_context ctx = {};
6786 struct nir_function *func;
6787
6788 ctx.ac = *ac;
6789 ctx.abi = abi;
6790
6791 ctx.stage = nir->info.stage;
6792
6793 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6794
6795 nir_foreach_variable(variable, &nir->outputs)
6796 handle_shader_output_decl(&ctx, nir, variable);
6797
6798 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6799 _mesa_key_pointer_equal);
6800 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6801 _mesa_key_pointer_equal);
6802 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6803 _mesa_key_pointer_equal);
6804
6805 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6806
6807 setup_locals(&ctx, func);
6808
6809 if (nir->info.stage == MESA_SHADER_COMPUTE)
6810 setup_shared(&ctx, nir);
6811
6812 visit_cf_list(&ctx, &func->impl->body);
6813 phi_post_pass(&ctx);
6814
6815 if (nir->info.stage != MESA_SHADER_COMPUTE)
6816 ctx.abi->emit_outputs(ctx.abi, AC_LLVM_MAX_OUTPUTS,
6817 ctx.abi->outputs);
6818
6819 free(ctx.locals);
6820 ralloc_free(ctx.defs);
6821 ralloc_free(ctx.phis);
6822 ralloc_free(ctx.vars);
6823 }
6824
6825 static
6826 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6827 struct nir_shader *const *shaders,
6828 int shader_count,
6829 struct ac_shader_variant_info *shader_info,
6830 const struct ac_nir_compiler_options *options)
6831 {
6832 struct radv_shader_context ctx = {0};
6833 unsigned i;
6834 ctx.options = options;
6835 ctx.shader_info = shader_info;
6836 ctx.context = LLVMContextCreate();
6837
6838 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6839 options->family);
6840 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6841 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6842
6843 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6844 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6845 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
6846 LLVMDisposeTargetData(data_layout);
6847 LLVMDisposeMessage(data_layout_str);
6848
6849 enum ac_float_mode float_mode =
6850 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6851 AC_FLOAT_MODE_DEFAULT;
6852
6853 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
6854
6855 memset(shader_info, 0, sizeof(*shader_info));
6856
6857 for(int i = 0; i < shader_count; ++i)
6858 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6859
6860 for (i = 0; i < AC_UD_MAX_SETS; i++)
6861 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6862 for (i = 0; i < AC_UD_MAX_UD; i++)
6863 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6864
6865 ctx.max_workgroup_size = 0;
6866 for (int i = 0; i < shader_count; ++i) {
6867 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6868 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6869 shaders[i]));
6870 }
6871
6872 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6873 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6874
6875 ctx.abi.inputs = &ctx.inputs[0];
6876 ctx.abi.emit_outputs = handle_shader_outputs_post;
6877 ctx.abi.emit_vertex = visit_emit_vertex;
6878 ctx.abi.load_ubo = radv_load_ubo;
6879 ctx.abi.load_ssbo = radv_load_ssbo;
6880 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6881 ctx.abi.load_resource = radv_load_resource;
6882 ctx.abi.clamp_shadow_reference = false;
6883
6884 if (shader_count >= 2)
6885 ac_init_exec_full_mask(&ctx.ac);
6886
6887 if (ctx.ac.chip_class == GFX9 &&
6888 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6889 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6890
6891 for(int i = 0; i < shader_count; ++i) {
6892 ctx.stage = shaders[i]->info.stage;
6893 ctx.output_mask = 0;
6894 ctx.tess_outputs_written = 0;
6895 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6896 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6897
6898 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6899 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6900 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6901 ctx.abi.load_inputs = load_gs_input;
6902 ctx.abi.emit_primitive = visit_end_primitive;
6903 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6904 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6905 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6906 ctx.abi.load_tess_varyings = load_tcs_varyings;
6907 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6908 ctx.abi.store_tcs_outputs = store_tcs_output;
6909 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6910 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6911 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6912 ctx.abi.load_tess_varyings = load_tes_input;
6913 ctx.abi.load_tess_coord = load_tess_coord;
6914 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6915 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6916 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6917 if (shader_info->info.vs.needs_instance_id) {
6918 if (ctx.options->key.vs.as_ls) {
6919 ctx.shader_info->vs.vgpr_comp_cnt =
6920 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6921 } else {
6922 ctx.shader_info->vs.vgpr_comp_cnt =
6923 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6924 }
6925 }
6926 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6927 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6928 ctx.abi.lookup_interp_param = lookup_interp_param;
6929 ctx.abi.load_sample_position = load_sample_position;
6930 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6931 }
6932
6933 if (i)
6934 emit_barrier(&ctx.ac, ctx.stage);
6935
6936 ac_setup_rings(&ctx);
6937
6938 LLVMBasicBlockRef merge_block;
6939 if (shader_count >= 2) {
6940 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6941 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6942 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6943
6944 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6945 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6946 LLVMConstInt(ctx.ac.i32, 8, false), false);
6947 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6948 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6949 thread_id, count, "");
6950 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6951
6952 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6953 }
6954
6955 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6956 handle_fs_inputs(&ctx, shaders[i]);
6957 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6958 handle_vs_inputs(&ctx, shaders[i]);
6959 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6960 prepare_gs_input_vgprs(&ctx);
6961
6962 nir_foreach_variable(variable, &shaders[i]->outputs)
6963 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6964
6965 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
6966
6967 if (shader_count >= 2) {
6968 LLVMBuildBr(ctx.ac.builder, merge_block);
6969 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6970 }
6971
6972 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6973 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6974 shaders[i]->info.cull_distance_array_size > 4;
6975 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6976 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6977 shaders[i]->info.gs.vertices_out;
6978 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6979 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6980 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6981 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6982 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6983 }
6984 }
6985
6986 LLVMBuildRetVoid(ctx.ac.builder);
6987
6988 if (options->dump_preoptir)
6989 ac_dump_module(ctx.ac.module);
6990
6991 ac_llvm_finalize_module(&ctx);
6992
6993 if (shader_count == 1)
6994 ac_nir_eliminate_const_vs_outputs(&ctx);
6995
6996 return ctx.ac.module;
6997 }
6998
6999 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
7000 {
7001 unsigned *retval = (unsigned *)context;
7002 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
7003 char *description = LLVMGetDiagInfoDescription(di);
7004
7005 if (severity == LLVMDSError) {
7006 *retval = 1;
7007 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
7008 description);
7009 }
7010
7011 LLVMDisposeMessage(description);
7012 }
7013
7014 static unsigned ac_llvm_compile(LLVMModuleRef M,
7015 struct ac_shader_binary *binary,
7016 LLVMTargetMachineRef tm)
7017 {
7018 unsigned retval = 0;
7019 char *err;
7020 LLVMContextRef llvm_ctx;
7021 LLVMMemoryBufferRef out_buffer;
7022 unsigned buffer_size;
7023 const char *buffer_data;
7024 LLVMBool mem_err;
7025
7026 /* Setup Diagnostic Handler*/
7027 llvm_ctx = LLVMGetModuleContext(M);
7028
7029 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
7030 &retval);
7031
7032 /* Compile IR*/
7033 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
7034 &err, &out_buffer);
7035
7036 /* Process Errors/Warnings */
7037 if (mem_err) {
7038 fprintf(stderr, "%s: %s", __FUNCTION__, err);
7039 free(err);
7040 retval = 1;
7041 goto out;
7042 }
7043
7044 /* Extract Shader Code*/
7045 buffer_size = LLVMGetBufferSize(out_buffer);
7046 buffer_data = LLVMGetBufferStart(out_buffer);
7047
7048 ac_elf_read(buffer_data, buffer_size, binary);
7049
7050 /* Clean up */
7051 LLVMDisposeMemoryBuffer(out_buffer);
7052
7053 out:
7054 return retval;
7055 }
7056
7057 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
7058 LLVMModuleRef llvm_module,
7059 struct ac_shader_binary *binary,
7060 struct ac_shader_config *config,
7061 struct ac_shader_variant_info *shader_info,
7062 gl_shader_stage stage,
7063 bool dump_shader, bool supports_spill)
7064 {
7065 if (dump_shader)
7066 ac_dump_module(llvm_module);
7067
7068 memset(binary, 0, sizeof(*binary));
7069 int v = ac_llvm_compile(llvm_module, binary, tm);
7070 if (v) {
7071 fprintf(stderr, "compile failed\n");
7072 }
7073
7074 if (dump_shader)
7075 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7076
7077 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7078
7079 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7080 LLVMDisposeModule(llvm_module);
7081 LLVMContextDispose(ctx);
7082
7083 if (stage == MESA_SHADER_FRAGMENT) {
7084 shader_info->num_input_vgprs = 0;
7085 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7086 shader_info->num_input_vgprs += 2;
7087 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7088 shader_info->num_input_vgprs += 2;
7089 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7090 shader_info->num_input_vgprs += 2;
7091 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7092 shader_info->num_input_vgprs += 3;
7093 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7094 shader_info->num_input_vgprs += 2;
7095 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7096 shader_info->num_input_vgprs += 2;
7097 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7098 shader_info->num_input_vgprs += 2;
7099 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7100 shader_info->num_input_vgprs += 1;
7101 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7102 shader_info->num_input_vgprs += 1;
7103 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7104 shader_info->num_input_vgprs += 1;
7105 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7106 shader_info->num_input_vgprs += 1;
7107 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7108 shader_info->num_input_vgprs += 1;
7109 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7110 shader_info->num_input_vgprs += 1;
7111 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7112 shader_info->num_input_vgprs += 1;
7113 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7114 shader_info->num_input_vgprs += 1;
7115 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7116 shader_info->num_input_vgprs += 1;
7117 }
7118 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7119
7120 /* +3 for scratch wave offset and VCC */
7121 config->num_sgprs = MAX2(config->num_sgprs,
7122 shader_info->num_input_sgprs + 3);
7123
7124 /* Enable 64-bit and 16-bit denormals, because there is no performance
7125 * cost.
7126 *
7127 * If denormals are enabled, all floating-point output modifiers are
7128 * ignored.
7129 *
7130 * Don't enable denormals for 32-bit floats, because:
7131 * - Floating-point output modifiers would be ignored by the hw.
7132 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7133 * have to stop using those.
7134 * - SI & CI would be very slow.
7135 */
7136 config->float_mode |= V_00B028_FP_64_DENORMS;
7137 }
7138
7139 static void
7140 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7141 {
7142 switch (nir->info.stage) {
7143 case MESA_SHADER_COMPUTE:
7144 for (int i = 0; i < 3; ++i)
7145 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7146 break;
7147 case MESA_SHADER_FRAGMENT:
7148 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7149 break;
7150 case MESA_SHADER_GEOMETRY:
7151 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7152 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7153 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7154 shader_info->gs.invocations = nir->info.gs.invocations;
7155 break;
7156 case MESA_SHADER_TESS_EVAL:
7157 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7158 shader_info->tes.spacing = nir->info.tess.spacing;
7159 shader_info->tes.ccw = nir->info.tess.ccw;
7160 shader_info->tes.point_mode = nir->info.tess.point_mode;
7161 shader_info->tes.as_es = options->key.tes.as_es;
7162 break;
7163 case MESA_SHADER_TESS_CTRL:
7164 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7165 break;
7166 case MESA_SHADER_VERTEX:
7167 shader_info->vs.as_es = options->key.vs.as_es;
7168 shader_info->vs.as_ls = options->key.vs.as_ls;
7169 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7170 if (options->key.vs.as_ls)
7171 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7172 break;
7173 default:
7174 break;
7175 }
7176 }
7177
7178 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7179 struct ac_shader_binary *binary,
7180 struct ac_shader_config *config,
7181 struct ac_shader_variant_info *shader_info,
7182 struct nir_shader *const *nir,
7183 int nir_count,
7184 const struct ac_nir_compiler_options *options,
7185 bool dump_shader)
7186 {
7187
7188 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7189 options);
7190
7191 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7192 for (int i = 0; i < nir_count; ++i)
7193 ac_fill_shader_info(shader_info, nir[i], options);
7194
7195 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7196 if (options->chip_class == GFX9) {
7197 if (nir_count == 2 &&
7198 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7199 shader_info->gs.es_type = nir[0]->info.stage;
7200 }
7201 }
7202 }
7203
7204 static void
7205 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
7206 {
7207 LLVMValueRef vtx_offset =
7208 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
7209 LLVMConstInt(ctx->ac.i32, 4, false), "");
7210 int idx = 0;
7211
7212 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
7213 int length = 4;
7214 int slot = idx;
7215 int slot_inc = 1;
7216 if (!(ctx->output_mask & (1ull << i)))
7217 continue;
7218
7219 if (i == VARYING_SLOT_CLIP_DIST0) {
7220 /* unpack clip and cull from a single set of slots */
7221 length = ctx->num_output_clips + ctx->num_output_culls;
7222 if (length > 4)
7223 slot_inc = 2;
7224 }
7225
7226 for (unsigned j = 0; j < length; j++) {
7227 LLVMValueRef value, soffset;
7228
7229 soffset = LLVMConstInt(ctx->ac.i32,
7230 (slot * 4 + j) *
7231 ctx->gs_max_out_vertices * 16 * 4, false);
7232
7233 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7234 1, ctx->ac.i32_0,
7235 vtx_offset, soffset,
7236 0, 1, 1, true, false);
7237
7238 LLVMBuildStore(ctx->ac.builder,
7239 ac_to_float(&ctx->ac, value), ctx->abi.outputs[radeon_llvm_reg_index_soa(i, j)]);
7240 }
7241 idx += slot_inc;
7242 }
7243 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7244 }
7245
7246 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7247 struct nir_shader *geom_shader,
7248 struct ac_shader_binary *binary,
7249 struct ac_shader_config *config,
7250 struct ac_shader_variant_info *shader_info,
7251 const struct ac_nir_compiler_options *options,
7252 bool dump_shader)
7253 {
7254 struct radv_shader_context ctx = {0};
7255 ctx.context = LLVMContextCreate();
7256 ctx.options = options;
7257 ctx.shader_info = shader_info;
7258
7259 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7260 options->family);
7261 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7262
7263 ctx.is_gs_copy_shader = true;
7264 LLVMSetTarget(ctx.ac.module, "amdgcn--");
7265
7266 enum ac_float_mode float_mode =
7267 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7268 AC_FLOAT_MODE_DEFAULT;
7269
7270 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
7271 ctx.stage = MESA_SHADER_VERTEX;
7272
7273 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7274
7275 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7276 ac_setup_rings(&ctx);
7277
7278 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7279 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7280
7281 struct ac_nir_context nir_ctx = {};
7282 nir_ctx.ac = ctx.ac;
7283 nir_ctx.abi = &ctx.abi;
7284
7285 nir_foreach_variable(variable, &geom_shader->outputs) {
7286 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7287 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7288 }
7289
7290 ac_gs_copy_shader_emit(&ctx);
7291
7292 LLVMBuildRetVoid(ctx.ac.builder);
7293
7294 ac_llvm_finalize_module(&ctx);
7295
7296 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
7297 MESA_SHADER_VERTEX,
7298 dump_shader, options->supports_spill);
7299 }