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amd/common: replace set_userdata_location_indirect() by set_loc_desc()
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tcs_patch_id;
115 LLVMValueRef tcs_rel_ids;
116 LLVMValueRef tes_rel_patch_id;
117 LLVMValueRef tes_patch_id;
118 LLVMValueRef tes_u;
119 LLVMValueRef tes_v;
120
121 LLVMValueRef gsvs_ring_stride;
122 LLVMValueRef gsvs_num_entries;
123 LLVMValueRef gs2vs_offset;
124 LLVMValueRef gs_wave_id;
125 LLVMValueRef gs_vtx_offset[6];
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 gl_shader_stage stage;
138
139 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
140
141 uint64_t input_mask;
142 uint64_t output_mask;
143 uint8_t num_output_clips;
144 uint8_t num_output_culls;
145
146 bool is_gs_copy_shader;
147 LLVMValueRef gs_next_vertex;
148 unsigned gs_max_out_vertices;
149
150 unsigned tes_primitive_mode;
151 uint64_t tess_outputs_written;
152 uint64_t tess_patch_outputs_written;
153
154 uint32_t tcs_patch_outputs_read;
155 uint64_t tcs_outputs_read;
156 };
157
158 static inline struct nir_to_llvm_context *
159 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
160 {
161 struct nir_to_llvm_context *ctx = NULL;
162 return container_of(abi, ctx, abi);
163 }
164
165 static LLVMTypeRef
166 nir2llvmtype(struct ac_nir_context *ctx,
167 const struct glsl_type *type)
168 {
169 switch (glsl_get_base_type(glsl_without_array(type))) {
170 case GLSL_TYPE_UINT:
171 case GLSL_TYPE_INT:
172 return ctx->ac.i32;
173 case GLSL_TYPE_UINT64:
174 case GLSL_TYPE_INT64:
175 return ctx->ac.i64;
176 case GLSL_TYPE_DOUBLE:
177 return ctx->ac.f64;
178 case GLSL_TYPE_FLOAT:
179 return ctx->ac.f32;
180 default:
181 assert(!"Unsupported type in nir2llvmtype()");
182 break;
183 }
184 return 0;
185 }
186
187 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
188 const nir_deref_var *deref,
189 enum ac_descriptor_type desc_type,
190 const nir_tex_instr *instr,
191 bool image, bool write);
192
193 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
194 {
195 return (index * 4) + chan;
196 }
197
198 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
199 {
200 /* handle patch indices separate */
201 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
202 return 0;
203 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
204 return 1;
205 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
206 return 2 + (slot - VARYING_SLOT_PATCH0);
207
208 if (slot == VARYING_SLOT_POS)
209 return 0;
210 if (slot == VARYING_SLOT_PSIZ)
211 return 1;
212 if (slot == VARYING_SLOT_CLIP_DIST0)
213 return 2;
214 /* 3 is reserved for clip dist as well */
215 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
216 return 4 + (slot - VARYING_SLOT_VAR0);
217 unreachable("illegal slot in get unique index\n");
218 }
219
220 static void set_llvm_calling_convention(LLVMValueRef func,
221 gl_shader_stage stage)
222 {
223 enum radeon_llvm_calling_convention calling_conv;
224
225 switch (stage) {
226 case MESA_SHADER_VERTEX:
227 case MESA_SHADER_TESS_EVAL:
228 calling_conv = RADEON_LLVM_AMDGPU_VS;
229 break;
230 case MESA_SHADER_GEOMETRY:
231 calling_conv = RADEON_LLVM_AMDGPU_GS;
232 break;
233 case MESA_SHADER_TESS_CTRL:
234 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
235 break;
236 case MESA_SHADER_FRAGMENT:
237 calling_conv = RADEON_LLVM_AMDGPU_PS;
238 break;
239 case MESA_SHADER_COMPUTE:
240 calling_conv = RADEON_LLVM_AMDGPU_CS;
241 break;
242 default:
243 unreachable("Unhandle shader type");
244 }
245
246 LLVMSetFunctionCallConv(func, calling_conv);
247 }
248
249 #define MAX_ARGS 23
250 struct arg_info {
251 LLVMTypeRef types[MAX_ARGS];
252 LLVMValueRef *assign[MAX_ARGS];
253 unsigned array_params_mask;
254 uint8_t count;
255 uint8_t sgpr_count;
256 uint8_t num_sgprs_used;
257 uint8_t num_vgprs_used;
258 };
259
260 enum ac_arg_regfile {
261 ARG_SGPR,
262 ARG_VGPR,
263 };
264
265 static void
266 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
267 LLVMValueRef *param_ptr)
268 {
269 assert(info->count < MAX_ARGS);
270
271 info->assign[info->count] = param_ptr;
272 info->types[info->count] = type;
273 info->count++;
274
275 if (regfile == ARG_SGPR) {
276 info->num_sgprs_used += ac_get_type_size(type) / 4;
277 info->sgpr_count++;
278 } else {
279 assert(regfile == ARG_VGPR);
280 info->num_vgprs_used += ac_get_type_size(type) / 4;
281 }
282 }
283
284 static inline void
285 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
286 {
287 info->array_params_mask |= (1 << info->count);
288 add_arg(info, ARG_SGPR, type, param_ptr);
289 }
290
291 static void assign_arguments(LLVMValueRef main_function,
292 struct arg_info *info)
293 {
294 unsigned i;
295 for (i = 0; i < info->count; i++) {
296 if (info->assign[i])
297 *info->assign[i] = LLVMGetParam(main_function, i);
298 }
299 }
300
301 static LLVMValueRef
302 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
303 LLVMBuilderRef builder, LLVMTypeRef *return_types,
304 unsigned num_return_elems,
305 struct arg_info *args,
306 unsigned max_workgroup_size,
307 bool unsafe_math)
308 {
309 LLVMTypeRef main_function_type, ret_type;
310 LLVMBasicBlockRef main_function_body;
311
312 if (num_return_elems)
313 ret_type = LLVMStructTypeInContext(ctx, return_types,
314 num_return_elems, true);
315 else
316 ret_type = LLVMVoidTypeInContext(ctx);
317
318 /* Setup the function */
319 main_function_type =
320 LLVMFunctionType(ret_type, args->types, args->count, 0);
321 LLVMValueRef main_function =
322 LLVMAddFunction(module, "main", main_function_type);
323 main_function_body =
324 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
325 LLVMPositionBuilderAtEnd(builder, main_function_body);
326
327 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
328 for (unsigned i = 0; i < args->sgpr_count; ++i) {
329 if (args->array_params_mask & (1 << i)) {
330 LLVMValueRef P = LLVMGetParam(main_function, i);
331 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
332 ac_add_attr_dereferenceable(P, UINT64_MAX);
333 }
334 else {
335 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
336 }
337 }
338
339 if (max_workgroup_size) {
340 ac_llvm_add_target_dep_function_attr(main_function,
341 "amdgpu-max-work-group-size",
342 max_workgroup_size);
343 }
344 if (unsafe_math) {
345 /* These were copied from some LLVM test. */
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "less-precise-fpmad",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-infs-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "no-nans-fp-math",
354 "true");
355 LLVMAddTargetDependentFunctionAttr(main_function,
356 "unsafe-fp-math",
357 "true");
358 }
359 return main_function;
360 }
361
362 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
363 {
364 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
365 CONST_ADDR_SPACE);
366 }
367
368 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
369 {
370 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
371 type = LLVMGetElementType(type);
372
373 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
374 return LLVMGetIntTypeWidth(type);
375
376 if (type == ctx->f16)
377 return 16;
378 if (type == ctx->f32)
379 return 32;
380 if (type == ctx->f64)
381 return 64;
382
383 unreachable("Unhandled type kind in get_elem_bits");
384 }
385
386 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
387 LLVMValueRef param, unsigned rshift,
388 unsigned bitwidth)
389 {
390 LLVMValueRef value = param;
391 if (rshift)
392 value = LLVMBuildLShr(ctx->builder, value,
393 LLVMConstInt(ctx->i32, rshift, false), "");
394
395 if (rshift + bitwidth < 32) {
396 unsigned mask = (1 << bitwidth) - 1;
397 value = LLVMBuildAnd(ctx->builder, value,
398 LLVMConstInt(ctx->i32, mask, false), "");
399 }
400 return value;
401 }
402
403 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
404 {
405 switch (ctx->stage) {
406 case MESA_SHADER_TESS_CTRL:
407 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
408 case MESA_SHADER_TESS_EVAL:
409 return ctx->tes_rel_patch_id;
410 break;
411 default:
412 unreachable("Illegal stage");
413 }
414 }
415
416 /* Tessellation shaders pass outputs to the next shader using LDS.
417 *
418 * LS outputs = TCS inputs
419 * TCS outputs = TES inputs
420 *
421 * The LDS layout is:
422 * - TCS inputs for patch 0
423 * - TCS inputs for patch 1
424 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
425 * - ...
426 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
427 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
428 * - TCS outputs for patch 1
429 * - Per-patch TCS outputs for patch 1
430 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
431 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
432 * - ...
433 *
434 * All three shaders VS(LS), TCS, TES share the same LDS space.
435 */
436 static LLVMValueRef
437 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
438 {
439 if (ctx->stage == MESA_SHADER_VERTEX)
440 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
441 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
442 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
443 else {
444 assert(0);
445 return NULL;
446 }
447 }
448
449 static LLVMValueRef
450 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
451 {
452 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
453 }
454
455 static LLVMValueRef
456 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
457 {
458 return LLVMBuildMul(ctx->builder,
459 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
460 LLVMConstInt(ctx->ac.i32, 4, false), "");
461 }
462
463 static LLVMValueRef
464 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
465 {
466 return LLVMBuildMul(ctx->builder,
467 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
468 LLVMConstInt(ctx->ac.i32, 4, false), "");
469 }
470
471 static LLVMValueRef
472 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
473 {
474 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
475 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
476
477 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
478 }
479
480 static LLVMValueRef
481 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
482 {
483 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
484 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
485 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
486
487 return LLVMBuildAdd(ctx->builder, patch0_offset,
488 LLVMBuildMul(ctx->builder, patch_stride,
489 rel_patch_id, ""),
490 "");
491 }
492
493 static LLVMValueRef
494 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
495 {
496 LLVMValueRef patch0_patch_data_offset =
497 get_tcs_out_patch0_patch_data_offset(ctx);
498 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
499 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
500
501 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
502 LLVMBuildMul(ctx->builder, patch_stride,
503 rel_patch_id, ""),
504 "");
505 }
506
507 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
508 {
509 ud_info->sgpr_idx = *sgpr_idx;
510 ud_info->num_sgprs = num_sgprs;
511 ud_info->indirect = false;
512 ud_info->indirect_offset = 0;
513 *sgpr_idx += num_sgprs;
514 }
515
516 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
517 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
518 {
519 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
520 }
521
522 static void
523 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
524 uint32_t indirect_offset)
525 {
526 struct ac_userdata_info *ud_info =
527 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
528 assert(ud_info);
529
530 ud_info->sgpr_idx = *sgpr_idx;
531 ud_info->num_sgprs = 2;
532 ud_info->indirect = indirect_offset > 0;
533 ud_info->indirect_offset = indirect_offset;
534 }
535
536 struct user_sgpr_info {
537 bool need_ring_offsets;
538 uint8_t sgpr_count;
539 bool indirect_all_descriptor_sets;
540 };
541
542 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
543 struct user_sgpr_info *user_sgpr_info)
544 {
545 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
546
547 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
548 if (ctx->stage == MESA_SHADER_GEOMETRY ||
549 ctx->stage == MESA_SHADER_VERTEX ||
550 ctx->stage == MESA_SHADER_TESS_CTRL ||
551 ctx->stage == MESA_SHADER_TESS_EVAL ||
552 ctx->is_gs_copy_shader)
553 user_sgpr_info->need_ring_offsets = true;
554
555 if (ctx->stage == MESA_SHADER_FRAGMENT &&
556 ctx->shader_info->info.ps.needs_sample_positions)
557 user_sgpr_info->need_ring_offsets = true;
558
559 /* 2 user sgprs will nearly always be allocated for scratch/rings */
560 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
561 user_sgpr_info->sgpr_count += 2;
562 }
563
564 switch (ctx->stage) {
565 case MESA_SHADER_COMPUTE:
566 if (ctx->shader_info->info.cs.uses_grid_size)
567 user_sgpr_info->sgpr_count += 3;
568 break;
569 case MESA_SHADER_FRAGMENT:
570 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
571 break;
572 case MESA_SHADER_VERTEX:
573 if (!ctx->is_gs_copy_shader) {
574 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
575 if (ctx->shader_info->info.vs.needs_draw_id) {
576 user_sgpr_info->sgpr_count += 3;
577 } else {
578 user_sgpr_info->sgpr_count += 2;
579 }
580 }
581 if (ctx->options->key.vs.as_ls)
582 user_sgpr_info->sgpr_count++;
583 break;
584 case MESA_SHADER_TESS_CTRL:
585 user_sgpr_info->sgpr_count += 4;
586 break;
587 case MESA_SHADER_TESS_EVAL:
588 user_sgpr_info->sgpr_count += 1;
589 break;
590 case MESA_SHADER_GEOMETRY:
591 user_sgpr_info->sgpr_count += 2;
592 break;
593 default:
594 break;
595 }
596
597 if (ctx->shader_info->info.needs_push_constants)
598 user_sgpr_info->sgpr_count += 2;
599
600 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
601 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
602 user_sgpr_info->sgpr_count += 2;
603 user_sgpr_info->indirect_all_descriptor_sets = true;
604 } else {
605 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
606 }
607 }
608
609 static void
610 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
611 gl_shader_stage stage,
612 bool has_previous_stage,
613 gl_shader_stage previous_stage,
614 const struct user_sgpr_info *user_sgpr_info,
615 struct arg_info *args,
616 LLVMValueRef *desc_sets)
617 {
618 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
619 unsigned num_sets = ctx->options->layout ?
620 ctx->options->layout->num_sets : 0;
621 unsigned stage_mask = 1 << stage;
622
623 if (has_previous_stage)
624 stage_mask |= 1 << previous_stage;
625
626 /* 1 for each descriptor set */
627 if (!user_sgpr_info->indirect_all_descriptor_sets) {
628 for (unsigned i = 0; i < num_sets; ++i) {
629 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
630 add_array_arg(args, type,
631 &ctx->descriptor_sets[i]);
632 }
633 }
634 } else {
635 add_array_arg(args, const_array(type, 32), desc_sets);
636 }
637
638 if (ctx->shader_info->info.needs_push_constants) {
639 /* 1 for push constants and dynamic descriptors */
640 add_array_arg(args, type, &ctx->push_constants);
641 }
642 }
643
644 static void
645 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
646 gl_shader_stage stage,
647 bool has_previous_stage,
648 gl_shader_stage previous_stage,
649 struct arg_info *args)
650 {
651 if (!ctx->is_gs_copy_shader &&
652 (stage == MESA_SHADER_VERTEX ||
653 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
654 if (ctx->shader_info->info.vs.has_vertex_buffers) {
655 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
656 &ctx->vertex_buffers);
657 }
658 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
659 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
660 if (ctx->shader_info->info.vs.needs_draw_id) {
661 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
662 }
663 }
664 }
665
666 static void
667 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
668 {
669 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
670 if (!ctx->is_gs_copy_shader) {
671 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
672 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
673 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
674 }
675 }
676
677 static void
678 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
679 {
680 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
681 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
682 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
683 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_patch_id);
684 }
685
686 static void
687 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
688 bool has_previous_stage, gl_shader_stage previous_stage,
689 const struct user_sgpr_info *user_sgpr_info,
690 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
691 {
692 unsigned num_sets = ctx->options->layout ?
693 ctx->options->layout->num_sets : 0;
694 unsigned stage_mask = 1 << stage;
695
696 if (has_previous_stage)
697 stage_mask |= 1 << previous_stage;
698
699 if (!user_sgpr_info->indirect_all_descriptor_sets) {
700 for (unsigned i = 0; i < num_sets; ++i) {
701 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
702 set_loc_desc(ctx, i, user_sgpr_idx, 0);
703 } else
704 ctx->descriptor_sets[i] = NULL;
705 }
706 } else {
707 set_userdata_location_shader(ctx,
708 AC_UD_INDIRECT_DESCRIPTOR_SETS,
709 user_sgpr_idx, 2);
710
711 for (unsigned i = 0; i < num_sets; ++i) {
712 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
713 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
714 ctx->descriptor_sets[i] =
715 ac_build_load_to_sgpr(&ctx->ac,
716 desc_sets,
717 LLVMConstInt(ctx->ac.i32, i, false));
718
719 } else
720 ctx->descriptor_sets[i] = NULL;
721 }
722 ctx->shader_info->need_indirect_descriptor_sets = true;
723 }
724
725 if (ctx->shader_info->info.needs_push_constants) {
726 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS,
727 user_sgpr_idx, 2);
728 }
729 }
730
731 static void
732 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
733 gl_shader_stage stage, bool has_previous_stage,
734 gl_shader_stage previous_stage,
735 uint8_t *user_sgpr_idx)
736 {
737 if (!ctx->is_gs_copy_shader &&
738 (stage == MESA_SHADER_VERTEX ||
739 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
740 if (ctx->shader_info->info.vs.has_vertex_buffers) {
741 set_userdata_location_shader(ctx,
742 AC_UD_VS_VERTEX_BUFFERS,
743 user_sgpr_idx, 2);
744 }
745
746 unsigned vs_num = 2;
747 if (ctx->shader_info->info.vs.needs_draw_id)
748 vs_num++;
749
750 set_userdata_location_shader(ctx,
751 AC_UD_VS_BASE_VERTEX_START_INSTANCE,
752 user_sgpr_idx, vs_num);
753 }
754 }
755
756 static void create_function(struct nir_to_llvm_context *ctx,
757 gl_shader_stage stage,
758 bool has_previous_stage,
759 gl_shader_stage previous_stage)
760 {
761 uint8_t user_sgpr_idx;
762 struct user_sgpr_info user_sgpr_info;
763 struct arg_info args = {};
764 LLVMValueRef desc_sets;
765
766 allocate_user_sgprs(ctx, &user_sgpr_info);
767
768 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
769 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
770 &ctx->ring_offsets);
771 }
772
773 switch (stage) {
774 case MESA_SHADER_COMPUTE:
775 declare_global_input_sgprs(ctx, stage, has_previous_stage,
776 previous_stage, &user_sgpr_info,
777 &args, &desc_sets);
778
779 if (ctx->shader_info->info.cs.uses_grid_size) {
780 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
781 &ctx->num_work_groups);
782 }
783
784 for (int i = 0; i < 3; i++) {
785 ctx->workgroup_ids[i] = NULL;
786 if (ctx->shader_info->info.cs.uses_block_id[i]) {
787 add_arg(&args, ARG_SGPR, ctx->ac.i32,
788 &ctx->workgroup_ids[i]);
789 }
790 }
791
792 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
793 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
794 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
795 &ctx->local_invocation_ids);
796 break;
797 case MESA_SHADER_VERTEX:
798 declare_global_input_sgprs(ctx, stage, has_previous_stage,
799 previous_stage, &user_sgpr_info,
800 &args, &desc_sets);
801 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
802 previous_stage, &args);
803
804 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
805 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
806 if (ctx->options->key.vs.as_es)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32,
808 &ctx->es2gs_offset);
809 else if (ctx->options->key.vs.as_ls)
810 add_arg(&args, ARG_SGPR, ctx->ac.i32,
811 &ctx->ls_out_layout);
812
813 declare_vs_input_vgprs(ctx, &args);
814 break;
815 case MESA_SHADER_TESS_CTRL:
816 if (has_previous_stage) {
817 // First 6 system regs
818 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
819 add_arg(&args, ARG_SGPR, ctx->ac.i32,
820 &ctx->merged_wave_info);
821 add_arg(&args, ARG_SGPR, ctx->ac.i32,
822 &ctx->tess_factor_offset);
823
824 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
825 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
826 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
827
828 declare_global_input_sgprs(ctx, stage,
829 has_previous_stage,
830 previous_stage,
831 &user_sgpr_info, &args,
832 &desc_sets);
833 declare_vs_specific_input_sgprs(ctx, stage,
834 has_previous_stage,
835 previous_stage, &args);
836
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->ls_out_layout);
839
840 add_arg(&args, ARG_SGPR, ctx->ac.i32,
841 &ctx->tcs_offchip_layout);
842 add_arg(&args, ARG_SGPR, ctx->ac.i32,
843 &ctx->tcs_out_offsets);
844 add_arg(&args, ARG_SGPR, ctx->ac.i32,
845 &ctx->tcs_out_layout);
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->tcs_in_layout);
848 if (ctx->shader_info->info.needs_multiview_view_index)
849 add_arg(&args, ARG_SGPR, ctx->ac.i32,
850 &ctx->view_index);
851
852 add_arg(&args, ARG_VGPR, ctx->ac.i32,
853 &ctx->tcs_patch_id);
854 add_arg(&args, ARG_VGPR, ctx->ac.i32,
855 &ctx->tcs_rel_ids);
856
857 declare_vs_input_vgprs(ctx, &args);
858 } else {
859 declare_global_input_sgprs(ctx, stage,
860 has_previous_stage,
861 previous_stage,
862 &user_sgpr_info, &args,
863 &desc_sets);
864
865 add_arg(&args, ARG_SGPR, ctx->ac.i32,
866 &ctx->tcs_offchip_layout);
867 add_arg(&args, ARG_SGPR, ctx->ac.i32,
868 &ctx->tcs_out_offsets);
869 add_arg(&args, ARG_SGPR, ctx->ac.i32,
870 &ctx->tcs_out_layout);
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->tcs_in_layout);
873 if (ctx->shader_info->info.needs_multiview_view_index)
874 add_arg(&args, ARG_SGPR, ctx->ac.i32,
875 &ctx->view_index);
876
877 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
878 add_arg(&args, ARG_SGPR, ctx->ac.i32,
879 &ctx->tess_factor_offset);
880 add_arg(&args, ARG_VGPR, ctx->ac.i32,
881 &ctx->tcs_patch_id);
882 add_arg(&args, ARG_VGPR, ctx->ac.i32,
883 &ctx->tcs_rel_ids);
884 }
885 break;
886 case MESA_SHADER_TESS_EVAL:
887 declare_global_input_sgprs(ctx, stage, has_previous_stage,
888 previous_stage, &user_sgpr_info,
889 &args, &desc_sets);
890
891 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
892 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
893 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
894
895 if (ctx->options->key.tes.as_es) {
896 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
897 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
898 add_arg(&args, ARG_SGPR, ctx->ac.i32,
899 &ctx->es2gs_offset);
900 } else {
901 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
902 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
903 }
904 declare_tes_input_vgprs(ctx, &args);
905 break;
906 case MESA_SHADER_GEOMETRY:
907 if (has_previous_stage) {
908 // First 6 system regs
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->gs2vs_offset);
911 add_arg(&args, ARG_SGPR, ctx->ac.i32,
912 &ctx->merged_wave_info);
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
914
915 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
916 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
917 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
918
919 declare_global_input_sgprs(ctx, stage,
920 has_previous_stage,
921 previous_stage,
922 &user_sgpr_info, &args,
923 &desc_sets);
924
925 if (previous_stage == MESA_SHADER_TESS_EVAL) {
926 add_arg(&args, ARG_SGPR, ctx->ac.i32,
927 &ctx->tcs_offchip_layout);
928 } else {
929 declare_vs_specific_input_sgprs(ctx, stage,
930 has_previous_stage,
931 previous_stage,
932 &args);
933 }
934
935 add_arg(&args, ARG_SGPR, ctx->ac.i32,
936 &ctx->gsvs_ring_stride);
937 add_arg(&args, ARG_SGPR, ctx->ac.i32,
938 &ctx->gsvs_num_entries);
939 if (ctx->shader_info->info.needs_multiview_view_index)
940 add_arg(&args, ARG_SGPR, ctx->ac.i32,
941 &ctx->view_index);
942
943 add_arg(&args, ARG_VGPR, ctx->ac.i32,
944 &ctx->gs_vtx_offset[0]);
945 add_arg(&args, ARG_VGPR, ctx->ac.i32,
946 &ctx->gs_vtx_offset[2]);
947 add_arg(&args, ARG_VGPR, ctx->ac.i32,
948 &ctx->abi.gs_prim_id);
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->abi.gs_invocation_id);
951 add_arg(&args, ARG_VGPR, ctx->ac.i32,
952 &ctx->gs_vtx_offset[4]);
953
954 if (previous_stage == MESA_SHADER_VERTEX) {
955 declare_vs_input_vgprs(ctx, &args);
956 } else {
957 declare_tes_input_vgprs(ctx, &args);
958 }
959 } else {
960 declare_global_input_sgprs(ctx, stage,
961 has_previous_stage,
962 previous_stage,
963 &user_sgpr_info, &args,
964 &desc_sets);
965
966 add_arg(&args, ARG_SGPR, ctx->ac.i32,
967 &ctx->gsvs_ring_stride);
968 add_arg(&args, ARG_SGPR, ctx->ac.i32,
969 &ctx->gsvs_num_entries);
970 if (ctx->shader_info->info.needs_multiview_view_index)
971 add_arg(&args, ARG_SGPR, ctx->ac.i32,
972 &ctx->view_index);
973
974 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
975 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[0]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->gs_vtx_offset[1]);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->abi.gs_prim_id);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[2]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[3]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[4]);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->gs_vtx_offset[5]);
990 add_arg(&args, ARG_VGPR, ctx->ac.i32,
991 &ctx->abi.gs_invocation_id);
992 }
993 break;
994 case MESA_SHADER_FRAGMENT:
995 declare_global_input_sgprs(ctx, stage, has_previous_stage,
996 previous_stage, &user_sgpr_info,
997 &args, &desc_sets);
998
999 if (ctx->shader_info->info.ps.needs_sample_positions)
1000 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1001 &ctx->sample_pos_offset);
1002
1003 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1005 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1009 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1010 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1014 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1015 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1018 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1019 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1020 break;
1021 default:
1022 unreachable("Shader stage not implemented");
1023 }
1024
1025 ctx->main_function = create_llvm_function(
1026 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1027 ctx->max_workgroup_size,
1028 ctx->options->unsafe_math);
1029 set_llvm_calling_convention(ctx->main_function, stage);
1030
1031
1032 ctx->shader_info->num_input_vgprs = 0;
1033 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1034
1035 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1036
1037 if (ctx->stage != MESA_SHADER_FRAGMENT)
1038 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1039
1040 assign_arguments(ctx->main_function, &args);
1041
1042 user_sgpr_idx = 0;
1043
1044 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1045 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
1046 if (ctx->options->supports_spill) {
1047 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1048 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1049 NULL, 0, AC_FUNC_ATTR_READNONE);
1050 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1051 const_array(ctx->ac.v4i32, 16), "");
1052 }
1053 }
1054
1055 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1056 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1057 if (has_previous_stage)
1058 user_sgpr_idx = 0;
1059
1060 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1061 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1062
1063 switch (stage) {
1064 case MESA_SHADER_COMPUTE:
1065 if (ctx->shader_info->info.cs.uses_grid_size) {
1066 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE,
1067 &user_sgpr_idx, 3);
1068 }
1069 break;
1070 case MESA_SHADER_VERTEX:
1071 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1072 previous_stage, &user_sgpr_idx);
1073 if (ctx->view_index)
1074 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1075 if (ctx->options->key.vs.as_ls) {
1076 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
1077 }
1078 if (ctx->options->key.vs.as_ls)
1079 ac_declare_lds_as_pointer(&ctx->ac);
1080 break;
1081 case MESA_SHADER_TESS_CTRL:
1082 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1083 previous_stage, &user_sgpr_idx);
1084 if (has_previous_stage)
1085 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
1086 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1087 if (ctx->view_index)
1088 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1089 ac_declare_lds_as_pointer(&ctx->ac);
1090 break;
1091 case MESA_SHADER_TESS_EVAL:
1092 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1093 if (ctx->view_index)
1094 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1095 break;
1096 case MESA_SHADER_GEOMETRY:
1097 if (has_previous_stage) {
1098 if (previous_stage == MESA_SHADER_VERTEX)
1099 set_vs_specific_input_locs(ctx, stage,
1100 has_previous_stage,
1101 previous_stage,
1102 &user_sgpr_idx);
1103 else
1104 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1105 }
1106 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
1107 if (ctx->view_index)
1108 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1109 if (has_previous_stage)
1110 ac_declare_lds_as_pointer(&ctx->ac);
1111 break;
1112 case MESA_SHADER_FRAGMENT:
1113 if (ctx->shader_info->info.ps.needs_sample_positions) {
1114 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
1115 }
1116 break;
1117 default:
1118 unreachable("Shader stage not implemented");
1119 }
1120
1121 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1122 }
1123
1124 static int get_llvm_num_components(LLVMValueRef value)
1125 {
1126 LLVMTypeRef type = LLVMTypeOf(value);
1127 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1128 ? LLVMGetVectorSize(type)
1129 : 1;
1130 return num_components;
1131 }
1132
1133 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1134 LLVMValueRef value,
1135 int index)
1136 {
1137 int count = get_llvm_num_components(value);
1138
1139 if (count == 1)
1140 return value;
1141
1142 return LLVMBuildExtractElement(ac->builder, value,
1143 LLVMConstInt(ac->i32, index, false), "");
1144 }
1145
1146 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1147 LLVMValueRef value, unsigned count)
1148 {
1149 unsigned num_components = get_llvm_num_components(value);
1150 if (count == num_components)
1151 return value;
1152
1153 LLVMValueRef masks[] = {
1154 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1155 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1156
1157 if (count == 1)
1158 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1159 "");
1160
1161 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1162 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1163 }
1164
1165 static void
1166 build_store_values_extended(struct ac_llvm_context *ac,
1167 LLVMValueRef *values,
1168 unsigned value_count,
1169 unsigned value_stride,
1170 LLVMValueRef vec)
1171 {
1172 LLVMBuilderRef builder = ac->builder;
1173 unsigned i;
1174
1175 for (i = 0; i < value_count; i++) {
1176 LLVMValueRef ptr = values[i * value_stride];
1177 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1178 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1179 LLVMBuildStore(builder, value, ptr);
1180 }
1181 }
1182
1183 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1184 const nir_ssa_def *def)
1185 {
1186 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1187 if (def->num_components > 1) {
1188 type = LLVMVectorType(type, def->num_components);
1189 }
1190 return type;
1191 }
1192
1193 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1194 {
1195 assert(src.is_ssa);
1196 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1197 return (LLVMValueRef)entry->data;
1198 }
1199
1200
1201 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1202 const struct nir_block *b)
1203 {
1204 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1205 return (LLVMBasicBlockRef)entry->data;
1206 }
1207
1208 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1209 nir_alu_src src,
1210 unsigned num_components)
1211 {
1212 LLVMValueRef value = get_src(ctx, src.src);
1213 bool need_swizzle = false;
1214
1215 assert(value);
1216 LLVMTypeRef type = LLVMTypeOf(value);
1217 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1218 ? LLVMGetVectorSize(type)
1219 : 1;
1220
1221 for (unsigned i = 0; i < num_components; ++i) {
1222 assert(src.swizzle[i] < src_components);
1223 if (src.swizzle[i] != i)
1224 need_swizzle = true;
1225 }
1226
1227 if (need_swizzle || num_components != src_components) {
1228 LLVMValueRef masks[] = {
1229 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1230 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1231 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1232 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1233
1234 if (src_components > 1 && num_components == 1) {
1235 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1236 masks[0], "");
1237 } else if (src_components == 1 && num_components > 1) {
1238 LLVMValueRef values[] = {value, value, value, value};
1239 value = ac_build_gather_values(&ctx->ac, values, num_components);
1240 } else {
1241 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1242 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1243 swizzle, "");
1244 }
1245 }
1246 assert(!src.negate);
1247 assert(!src.abs);
1248 return value;
1249 }
1250
1251 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1252 LLVMIntPredicate pred, LLVMValueRef src0,
1253 LLVMValueRef src1)
1254 {
1255 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1256 return LLVMBuildSelect(ctx->builder, result,
1257 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1258 ctx->i32_0, "");
1259 }
1260
1261 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1262 LLVMRealPredicate pred, LLVMValueRef src0,
1263 LLVMValueRef src1)
1264 {
1265 LLVMValueRef result;
1266 src0 = ac_to_float(ctx, src0);
1267 src1 = ac_to_float(ctx, src1);
1268 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1269 return LLVMBuildSelect(ctx->builder, result,
1270 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1271 ctx->i32_0, "");
1272 }
1273
1274 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1275 const char *intrin,
1276 LLVMTypeRef result_type,
1277 LLVMValueRef src0)
1278 {
1279 char name[64];
1280 LLVMValueRef params[] = {
1281 ac_to_float(ctx, src0),
1282 };
1283
1284 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1285 get_elem_bits(ctx, result_type));
1286 assert(length < sizeof(name));
1287 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1288 }
1289
1290 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1291 const char *intrin,
1292 LLVMTypeRef result_type,
1293 LLVMValueRef src0, LLVMValueRef src1)
1294 {
1295 char name[64];
1296 LLVMValueRef params[] = {
1297 ac_to_float(ctx, src0),
1298 ac_to_float(ctx, src1),
1299 };
1300
1301 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1302 get_elem_bits(ctx, result_type));
1303 assert(length < sizeof(name));
1304 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1305 }
1306
1307 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1308 const char *intrin,
1309 LLVMTypeRef result_type,
1310 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1311 {
1312 char name[64];
1313 LLVMValueRef params[] = {
1314 ac_to_float(ctx, src0),
1315 ac_to_float(ctx, src1),
1316 ac_to_float(ctx, src2),
1317 };
1318
1319 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1320 get_elem_bits(ctx, result_type));
1321 assert(length < sizeof(name));
1322 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1323 }
1324
1325 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1326 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1327 {
1328 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1329 ctx->i32_0, "");
1330 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1331 }
1332
1333 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1334 LLVMIntPredicate pred,
1335 LLVMValueRef src0, LLVMValueRef src1)
1336 {
1337 return LLVMBuildSelect(ctx->builder,
1338 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1339 src0,
1340 src1, "");
1341
1342 }
1343 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1344 LLVMValueRef src0)
1345 {
1346 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1347 LLVMBuildNeg(ctx->builder, src0, ""));
1348 }
1349
1350 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1351 LLVMValueRef src0)
1352 {
1353 LLVMValueRef cmp, val;
1354
1355 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1356 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1357 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1358 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1359 return val;
1360 }
1361
1362 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1363 LLVMValueRef src0)
1364 {
1365 LLVMValueRef cmp, val;
1366
1367 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1368 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1369 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1370 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1371 return val;
1372 }
1373
1374 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1375 LLVMValueRef src0)
1376 {
1377 const char *intr = "llvm.floor.f32";
1378 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1379 LLVMValueRef params[] = {
1380 fsrc0,
1381 };
1382 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1383 ctx->f32, params, 1,
1384 AC_FUNC_ATTR_READNONE);
1385 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1386 }
1387
1388 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1389 const char *intrin,
1390 LLVMValueRef src0, LLVMValueRef src1)
1391 {
1392 LLVMTypeRef ret_type;
1393 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1394 LLVMValueRef res;
1395 LLVMValueRef params[] = { src0, src1 };
1396 ret_type = LLVMStructTypeInContext(ctx->context, types,
1397 2, true);
1398
1399 res = ac_build_intrinsic(ctx, intrin, ret_type,
1400 params, 2, AC_FUNC_ATTR_READNONE);
1401
1402 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1403 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1404 return res;
1405 }
1406
1407 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1408 LLVMValueRef src0)
1409 {
1410 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1411 }
1412
1413 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1414 LLVMValueRef src0)
1415 {
1416 src0 = ac_to_float(ctx, src0);
1417 return LLVMBuildSExt(ctx->builder,
1418 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1419 ctx->i32, "");
1420 }
1421
1422 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1423 LLVMValueRef src0)
1424 {
1425 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1426 }
1427
1428 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1429 LLVMValueRef src0)
1430 {
1431 return LLVMBuildSExt(ctx->builder,
1432 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1433 ctx->i32, "");
1434 }
1435
1436 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1437 LLVMValueRef src0)
1438 {
1439 LLVMValueRef result;
1440 LLVMValueRef cond = NULL;
1441
1442 src0 = ac_to_float(&ctx->ac, src0);
1443 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1444
1445 if (ctx->options->chip_class >= VI) {
1446 LLVMValueRef args[2];
1447 /* Check if the result is a denormal - and flush to 0 if so. */
1448 args[0] = result;
1449 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1450 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1451 }
1452
1453 /* need to convert back up to f32 */
1454 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1455
1456 if (ctx->options->chip_class >= VI)
1457 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1458 else {
1459 /* for SI/CIK */
1460 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1461 * so compare the result and flush to 0 if it's smaller.
1462 */
1463 LLVMValueRef temp, cond2;
1464 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1465 ctx->ac.f32, result);
1466 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1467 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1468 temp, "");
1469 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1470 temp, ctx->ac.f32_0, "");
1471 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1472 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1473 }
1474 return result;
1475 }
1476
1477 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1478 LLVMValueRef src0, LLVMValueRef src1)
1479 {
1480 LLVMValueRef dst64, result;
1481 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1482 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1483
1484 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1485 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1486 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1487 return result;
1488 }
1489
1490 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1491 LLVMValueRef src0, LLVMValueRef src1)
1492 {
1493 LLVMValueRef dst64, result;
1494 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1495 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1496
1497 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1498 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1499 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1500 return result;
1501 }
1502
1503 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1504 bool is_signed,
1505 const LLVMValueRef srcs[3])
1506 {
1507 LLVMValueRef result;
1508 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1509
1510 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1511 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1512 return result;
1513 }
1514
1515 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1516 LLVMValueRef src0, LLVMValueRef src1,
1517 LLVMValueRef src2, LLVMValueRef src3)
1518 {
1519 LLVMValueRef bfi_args[3], result;
1520
1521 bfi_args[0] = LLVMBuildShl(ctx->builder,
1522 LLVMBuildSub(ctx->builder,
1523 LLVMBuildShl(ctx->builder,
1524 ctx->i32_1,
1525 src3, ""),
1526 ctx->i32_1, ""),
1527 src2, "");
1528 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1529 bfi_args[2] = src0;
1530
1531 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1532
1533 /* Calculate:
1534 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1535 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1536 */
1537 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1538 LLVMBuildAnd(ctx->builder, bfi_args[0],
1539 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1540
1541 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1542 return result;
1543 }
1544
1545 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1546 LLVMValueRef src0)
1547 {
1548 LLVMValueRef comp[2];
1549
1550 src0 = ac_to_float(ctx, src0);
1551 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1552 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1553
1554 return ac_build_cvt_pkrtz_f16(ctx, comp);
1555 }
1556
1557 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1558 LLVMValueRef src0)
1559 {
1560 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1561 LLVMValueRef temps[2], result, val;
1562 int i;
1563
1564 for (i = 0; i < 2; i++) {
1565 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1566 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1567 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1568 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1569 }
1570
1571 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1572 ctx->i32_0, "");
1573 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1574 ctx->i32_1, "");
1575 return result;
1576 }
1577
1578 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1579 nir_op op,
1580 LLVMValueRef src0)
1581 {
1582 unsigned mask;
1583 int idx;
1584 LLVMValueRef result;
1585
1586 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1587 mask = AC_TID_MASK_LEFT;
1588 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1589 mask = AC_TID_MASK_TOP;
1590 else
1591 mask = AC_TID_MASK_TOP_LEFT;
1592
1593 /* for DDX we want to next X pixel, DDY next Y pixel. */
1594 if (op == nir_op_fddx_fine ||
1595 op == nir_op_fddx_coarse ||
1596 op == nir_op_fddx)
1597 idx = 1;
1598 else
1599 idx = 2;
1600
1601 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1602 return result;
1603 }
1604
1605 /*
1606 * this takes an I,J coordinate pair,
1607 * and works out the X and Y derivatives.
1608 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1609 */
1610 static LLVMValueRef emit_ddxy_interp(
1611 struct ac_nir_context *ctx,
1612 LLVMValueRef interp_ij)
1613 {
1614 LLVMValueRef result[4], a;
1615 unsigned i;
1616
1617 for (i = 0; i < 2; i++) {
1618 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1619 LLVMConstInt(ctx->ac.i32, i, false), "");
1620 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1621 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1622 }
1623 return ac_build_gather_values(&ctx->ac, result, 4);
1624 }
1625
1626 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1627 {
1628 LLVMValueRef src[4], result = NULL;
1629 unsigned num_components = instr->dest.dest.ssa.num_components;
1630 unsigned src_components;
1631 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1632
1633 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1634 switch (instr->op) {
1635 case nir_op_vec2:
1636 case nir_op_vec3:
1637 case nir_op_vec4:
1638 src_components = 1;
1639 break;
1640 case nir_op_pack_half_2x16:
1641 src_components = 2;
1642 break;
1643 case nir_op_unpack_half_2x16:
1644 src_components = 1;
1645 break;
1646 default:
1647 src_components = num_components;
1648 break;
1649 }
1650 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1651 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1652
1653 switch (instr->op) {
1654 case nir_op_fmov:
1655 case nir_op_imov:
1656 result = src[0];
1657 break;
1658 case nir_op_fneg:
1659 src[0] = ac_to_float(&ctx->ac, src[0]);
1660 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1661 break;
1662 case nir_op_ineg:
1663 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1664 break;
1665 case nir_op_inot:
1666 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1667 break;
1668 case nir_op_iadd:
1669 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1670 break;
1671 case nir_op_fadd:
1672 src[0] = ac_to_float(&ctx->ac, src[0]);
1673 src[1] = ac_to_float(&ctx->ac, src[1]);
1674 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1675 break;
1676 case nir_op_fsub:
1677 src[0] = ac_to_float(&ctx->ac, src[0]);
1678 src[1] = ac_to_float(&ctx->ac, src[1]);
1679 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1680 break;
1681 case nir_op_isub:
1682 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1683 break;
1684 case nir_op_imul:
1685 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1686 break;
1687 case nir_op_imod:
1688 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1689 break;
1690 case nir_op_umod:
1691 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1692 break;
1693 case nir_op_fmod:
1694 src[0] = ac_to_float(&ctx->ac, src[0]);
1695 src[1] = ac_to_float(&ctx->ac, src[1]);
1696 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1697 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1698 ac_to_float_type(&ctx->ac, def_type), result);
1699 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1700 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1701 break;
1702 case nir_op_frem:
1703 src[0] = ac_to_float(&ctx->ac, src[0]);
1704 src[1] = ac_to_float(&ctx->ac, src[1]);
1705 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1706 break;
1707 case nir_op_irem:
1708 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1709 break;
1710 case nir_op_idiv:
1711 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1712 break;
1713 case nir_op_udiv:
1714 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1715 break;
1716 case nir_op_fmul:
1717 src[0] = ac_to_float(&ctx->ac, src[0]);
1718 src[1] = ac_to_float(&ctx->ac, src[1]);
1719 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1720 break;
1721 case nir_op_fdiv:
1722 src[0] = ac_to_float(&ctx->ac, src[0]);
1723 src[1] = ac_to_float(&ctx->ac, src[1]);
1724 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1725 break;
1726 case nir_op_frcp:
1727 src[0] = ac_to_float(&ctx->ac, src[0]);
1728 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1729 break;
1730 case nir_op_iand:
1731 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1732 break;
1733 case nir_op_ior:
1734 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1735 break;
1736 case nir_op_ixor:
1737 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1738 break;
1739 case nir_op_ishl:
1740 result = LLVMBuildShl(ctx->ac.builder, src[0],
1741 LLVMBuildZExt(ctx->ac.builder, src[1],
1742 LLVMTypeOf(src[0]), ""),
1743 "");
1744 break;
1745 case nir_op_ishr:
1746 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1747 LLVMBuildZExt(ctx->ac.builder, src[1],
1748 LLVMTypeOf(src[0]), ""),
1749 "");
1750 break;
1751 case nir_op_ushr:
1752 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1753 LLVMBuildZExt(ctx->ac.builder, src[1],
1754 LLVMTypeOf(src[0]), ""),
1755 "");
1756 break;
1757 case nir_op_ilt:
1758 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1759 break;
1760 case nir_op_ine:
1761 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1762 break;
1763 case nir_op_ieq:
1764 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1765 break;
1766 case nir_op_ige:
1767 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1768 break;
1769 case nir_op_ult:
1770 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1771 break;
1772 case nir_op_uge:
1773 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1774 break;
1775 case nir_op_feq:
1776 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1777 break;
1778 case nir_op_fne:
1779 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1780 break;
1781 case nir_op_flt:
1782 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1783 break;
1784 case nir_op_fge:
1785 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1786 break;
1787 case nir_op_fabs:
1788 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1789 ac_to_float_type(&ctx->ac, def_type), src[0]);
1790 break;
1791 case nir_op_iabs:
1792 result = emit_iabs(&ctx->ac, src[0]);
1793 break;
1794 case nir_op_imax:
1795 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1796 break;
1797 case nir_op_imin:
1798 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1799 break;
1800 case nir_op_umax:
1801 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1802 break;
1803 case nir_op_umin:
1804 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1805 break;
1806 case nir_op_isign:
1807 result = emit_isign(&ctx->ac, src[0]);
1808 break;
1809 case nir_op_fsign:
1810 src[0] = ac_to_float(&ctx->ac, src[0]);
1811 result = emit_fsign(&ctx->ac, src[0]);
1812 break;
1813 case nir_op_ffloor:
1814 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1815 ac_to_float_type(&ctx->ac, def_type), src[0]);
1816 break;
1817 case nir_op_ftrunc:
1818 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1819 ac_to_float_type(&ctx->ac, def_type), src[0]);
1820 break;
1821 case nir_op_fceil:
1822 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1823 ac_to_float_type(&ctx->ac, def_type), src[0]);
1824 break;
1825 case nir_op_fround_even:
1826 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1827 ac_to_float_type(&ctx->ac, def_type),src[0]);
1828 break;
1829 case nir_op_ffract:
1830 result = emit_ffract(&ctx->ac, src[0]);
1831 break;
1832 case nir_op_fsin:
1833 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1834 ac_to_float_type(&ctx->ac, def_type), src[0]);
1835 break;
1836 case nir_op_fcos:
1837 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1838 ac_to_float_type(&ctx->ac, def_type), src[0]);
1839 break;
1840 case nir_op_fsqrt:
1841 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1842 ac_to_float_type(&ctx->ac, def_type), src[0]);
1843 break;
1844 case nir_op_fexp2:
1845 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1846 ac_to_float_type(&ctx->ac, def_type), src[0]);
1847 break;
1848 case nir_op_flog2:
1849 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1850 ac_to_float_type(&ctx->ac, def_type), src[0]);
1851 break;
1852 case nir_op_frsq:
1853 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1854 ac_to_float_type(&ctx->ac, def_type), src[0]);
1855 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1856 break;
1857 case nir_op_fpow:
1858 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1859 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1860 break;
1861 case nir_op_fmax:
1862 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1863 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1864 if (instr->dest.dest.ssa.bit_size == 32)
1865 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1866 ac_to_float_type(&ctx->ac, def_type),
1867 result);
1868 break;
1869 case nir_op_fmin:
1870 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1871 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1872 if (instr->dest.dest.ssa.bit_size == 32)
1873 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1874 ac_to_float_type(&ctx->ac, def_type),
1875 result);
1876 break;
1877 case nir_op_ffma:
1878 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1879 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1880 break;
1881 case nir_op_ibitfield_extract:
1882 result = emit_bitfield_extract(&ctx->ac, true, src);
1883 break;
1884 case nir_op_ubitfield_extract:
1885 result = emit_bitfield_extract(&ctx->ac, false, src);
1886 break;
1887 case nir_op_bitfield_insert:
1888 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1889 break;
1890 case nir_op_bitfield_reverse:
1891 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1892 break;
1893 case nir_op_bit_count:
1894 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1895 break;
1896 case nir_op_vec2:
1897 case nir_op_vec3:
1898 case nir_op_vec4:
1899 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1900 src[i] = ac_to_integer(&ctx->ac, src[i]);
1901 result = ac_build_gather_values(&ctx->ac, src, num_components);
1902 break;
1903 case nir_op_f2i32:
1904 case nir_op_f2i64:
1905 src[0] = ac_to_float(&ctx->ac, src[0]);
1906 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1907 break;
1908 case nir_op_f2u32:
1909 case nir_op_f2u64:
1910 src[0] = ac_to_float(&ctx->ac, src[0]);
1911 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1912 break;
1913 case nir_op_i2f32:
1914 case nir_op_i2f64:
1915 src[0] = ac_to_integer(&ctx->ac, src[0]);
1916 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1917 break;
1918 case nir_op_u2f32:
1919 case nir_op_u2f64:
1920 src[0] = ac_to_integer(&ctx->ac, src[0]);
1921 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1922 break;
1923 case nir_op_f2f64:
1924 src[0] = ac_to_float(&ctx->ac, src[0]);
1925 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1926 break;
1927 case nir_op_f2f32:
1928 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1929 break;
1930 case nir_op_u2u32:
1931 case nir_op_u2u64:
1932 src[0] = ac_to_integer(&ctx->ac, src[0]);
1933 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1934 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1935 else
1936 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1937 break;
1938 case nir_op_i2i32:
1939 case nir_op_i2i64:
1940 src[0] = ac_to_integer(&ctx->ac, src[0]);
1941 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1942 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1943 else
1944 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1945 break;
1946 case nir_op_bcsel:
1947 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1948 break;
1949 case nir_op_find_lsb:
1950 src[0] = ac_to_integer(&ctx->ac, src[0]);
1951 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1952 break;
1953 case nir_op_ufind_msb:
1954 src[0] = ac_to_integer(&ctx->ac, src[0]);
1955 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1956 break;
1957 case nir_op_ifind_msb:
1958 src[0] = ac_to_integer(&ctx->ac, src[0]);
1959 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1960 break;
1961 case nir_op_uadd_carry:
1962 src[0] = ac_to_integer(&ctx->ac, src[0]);
1963 src[1] = ac_to_integer(&ctx->ac, src[1]);
1964 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1965 break;
1966 case nir_op_usub_borrow:
1967 src[0] = ac_to_integer(&ctx->ac, src[0]);
1968 src[1] = ac_to_integer(&ctx->ac, src[1]);
1969 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1970 break;
1971 case nir_op_b2f:
1972 result = emit_b2f(&ctx->ac, src[0]);
1973 break;
1974 case nir_op_f2b:
1975 result = emit_f2b(&ctx->ac, src[0]);
1976 break;
1977 case nir_op_b2i:
1978 result = emit_b2i(&ctx->ac, src[0]);
1979 break;
1980 case nir_op_i2b:
1981 src[0] = ac_to_integer(&ctx->ac, src[0]);
1982 result = emit_i2b(&ctx->ac, src[0]);
1983 break;
1984 case nir_op_fquantize2f16:
1985 result = emit_f2f16(ctx->nctx, src[0]);
1986 break;
1987 case nir_op_umul_high:
1988 src[0] = ac_to_integer(&ctx->ac, src[0]);
1989 src[1] = ac_to_integer(&ctx->ac, src[1]);
1990 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1991 break;
1992 case nir_op_imul_high:
1993 src[0] = ac_to_integer(&ctx->ac, src[0]);
1994 src[1] = ac_to_integer(&ctx->ac, src[1]);
1995 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1996 break;
1997 case nir_op_pack_half_2x16:
1998 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1999 break;
2000 case nir_op_unpack_half_2x16:
2001 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2002 break;
2003 case nir_op_fddx:
2004 case nir_op_fddy:
2005 case nir_op_fddx_fine:
2006 case nir_op_fddy_fine:
2007 case nir_op_fddx_coarse:
2008 case nir_op_fddy_coarse:
2009 result = emit_ddxy(ctx, instr->op, src[0]);
2010 break;
2011
2012 case nir_op_unpack_64_2x32_split_x: {
2013 assert(instr->src[0].src.ssa->num_components == 1);
2014 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2015 ctx->ac.v2i32,
2016 "");
2017 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2018 ctx->ac.i32_0, "");
2019 break;
2020 }
2021
2022 case nir_op_unpack_64_2x32_split_y: {
2023 assert(instr->src[0].src.ssa->num_components == 1);
2024 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2025 ctx->ac.v2i32,
2026 "");
2027 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2028 ctx->ac.i32_1, "");
2029 break;
2030 }
2031
2032 case nir_op_pack_64_2x32_split: {
2033 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2034 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2035 src[0], ctx->ac.i32_0, "");
2036 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2037 src[1], ctx->ac.i32_1, "");
2038 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2039 break;
2040 }
2041
2042 default:
2043 fprintf(stderr, "Unknown NIR alu instr: ");
2044 nir_print_instr(&instr->instr, stderr);
2045 fprintf(stderr, "\n");
2046 abort();
2047 }
2048
2049 if (result) {
2050 assert(instr->dest.dest.is_ssa);
2051 result = ac_to_integer(&ctx->ac, result);
2052 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2053 result);
2054 }
2055 }
2056
2057 static void visit_load_const(struct ac_nir_context *ctx,
2058 const nir_load_const_instr *instr)
2059 {
2060 LLVMValueRef values[4], value = NULL;
2061 LLVMTypeRef element_type =
2062 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2063
2064 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2065 switch (instr->def.bit_size) {
2066 case 32:
2067 values[i] = LLVMConstInt(element_type,
2068 instr->value.u32[i], false);
2069 break;
2070 case 64:
2071 values[i] = LLVMConstInt(element_type,
2072 instr->value.u64[i], false);
2073 break;
2074 default:
2075 fprintf(stderr,
2076 "unsupported nir load_const bit_size: %d\n",
2077 instr->def.bit_size);
2078 abort();
2079 }
2080 }
2081 if (instr->def.num_components > 1) {
2082 value = LLVMConstVector(values, instr->def.num_components);
2083 } else
2084 value = values[0];
2085
2086 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2087 }
2088
2089 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2090 LLVMTypeRef type)
2091 {
2092 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2093 return LLVMBuildBitCast(ctx->builder, ptr,
2094 LLVMPointerType(type, addr_space), "");
2095 }
2096
2097 static LLVMValueRef
2098 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2099 {
2100 LLVMValueRef size =
2101 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2102 LLVMConstInt(ctx->ac.i32, 2, false), "");
2103
2104 /* VI only */
2105 if (ctx->ac.chip_class == VI && in_elements) {
2106 /* On VI, the descriptor contains the size in bytes,
2107 * but TXQ must return the size in elements.
2108 * The stride is always non-zero for resources using TXQ.
2109 */
2110 LLVMValueRef stride =
2111 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2112 ctx->ac.i32_1, "");
2113 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2114 LLVMConstInt(ctx->ac.i32, 16, false), "");
2115 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2116 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2117
2118 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2119 }
2120 return size;
2121 }
2122
2123 /**
2124 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2125 * intrinsic names).
2126 */
2127 static void build_int_type_name(
2128 LLVMTypeRef type,
2129 char *buf, unsigned bufsize)
2130 {
2131 assert(bufsize >= 6);
2132
2133 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2134 snprintf(buf, bufsize, "v%ui32",
2135 LLVMGetVectorSize(type));
2136 else
2137 strcpy(buf, "i32");
2138 }
2139
2140 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2141 struct ac_image_args *args,
2142 const nir_tex_instr *instr)
2143 {
2144 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2145 LLVMValueRef coord = args->addr;
2146 LLVMValueRef half_texel[2];
2147 LLVMValueRef compare_cube_wa = NULL;
2148 LLVMValueRef result;
2149 int c;
2150 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2151
2152 //TODO Rect
2153 {
2154 struct ac_image_args txq_args = { 0 };
2155
2156 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2157 txq_args.opcode = ac_image_get_resinfo;
2158 txq_args.dmask = 0xf;
2159 txq_args.addr = ctx->i32_0;
2160 txq_args.resource = args->resource;
2161 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2162
2163 for (c = 0; c < 2; c++) {
2164 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2165 LLVMConstInt(ctx->i32, c, false), "");
2166 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2167 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2168 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2169 LLVMConstReal(ctx->f32, -0.5), "");
2170 }
2171 }
2172
2173 LLVMValueRef orig_coords = args->addr;
2174
2175 for (c = 0; c < 2; c++) {
2176 LLVMValueRef tmp;
2177 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2178 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2179 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2180 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2181 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2182 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2183 }
2184
2185
2186 /*
2187 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2188 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2189 * workaround by sampling using a scaled type and converting.
2190 * This is taken from amdgpu-pro shaders.
2191 */
2192 /* NOTE this produces some ugly code compared to amdgpu-pro,
2193 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2194 * and then reads them back. -pro generates two selects,
2195 * one s_cmp for the descriptor rewriting
2196 * one v_cmp for the coordinate and result changes.
2197 */
2198 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2199 LLVMValueRef tmp, tmp2;
2200
2201 /* workaround 8/8/8/8 uint/sint cube gather bug */
2202 /* first detect it then change to a scaled read and f2i */
2203 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2204 tmp2 = tmp;
2205
2206 /* extract the DATA_FORMAT */
2207 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2208 LLVMConstInt(ctx->i32, 6, false), false);
2209
2210 /* is the DATA_FORMAT == 8_8_8_8 */
2211 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2212
2213 if (stype == GLSL_TYPE_UINT)
2214 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2215 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2216 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2217 else
2218 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2219 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2220 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2221
2222 /* replace the NUM FORMAT in the descriptor */
2223 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2224 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2225
2226 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2227
2228 /* don't modify the coordinates for this case */
2229 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2230 }
2231 args->addr = coord;
2232 result = ac_build_image_opcode(ctx, args);
2233
2234 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2235 LLVMValueRef tmp, tmp2;
2236
2237 /* if the cube workaround is in place, f2i the result. */
2238 for (c = 0; c < 4; c++) {
2239 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2240 if (stype == GLSL_TYPE_UINT)
2241 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2242 else
2243 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2244 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2245 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2246 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2247 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2248 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2249 }
2250 }
2251 return result;
2252 }
2253
2254 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2255 const nir_tex_instr *instr,
2256 bool lod_is_zero,
2257 struct ac_image_args *args)
2258 {
2259 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2260 return ac_build_buffer_load_format(&ctx->ac,
2261 args->resource,
2262 args->addr,
2263 ctx->ac.i32_0,
2264 true);
2265 }
2266
2267 args->opcode = ac_image_sample;
2268 args->compare = instr->is_shadow;
2269
2270 switch (instr->op) {
2271 case nir_texop_txf:
2272 case nir_texop_txf_ms:
2273 case nir_texop_samples_identical:
2274 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2275 args->compare = false;
2276 args->offset = false;
2277 break;
2278 case nir_texop_txb:
2279 args->bias = true;
2280 break;
2281 case nir_texop_txl:
2282 if (lod_is_zero)
2283 args->level_zero = true;
2284 else
2285 args->lod = true;
2286 break;
2287 case nir_texop_txs:
2288 case nir_texop_query_levels:
2289 args->opcode = ac_image_get_resinfo;
2290 break;
2291 case nir_texop_tex:
2292 if (ctx->stage != MESA_SHADER_FRAGMENT)
2293 args->level_zero = true;
2294 break;
2295 case nir_texop_txd:
2296 args->deriv = true;
2297 break;
2298 case nir_texop_tg4:
2299 args->opcode = ac_image_gather4;
2300 args->level_zero = true;
2301 break;
2302 case nir_texop_lod:
2303 args->opcode = ac_image_get_lod;
2304 args->compare = false;
2305 args->offset = false;
2306 break;
2307 default:
2308 break;
2309 }
2310
2311 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2312 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2313 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2314 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2315 }
2316 }
2317 return ac_build_image_opcode(&ctx->ac, args);
2318 }
2319
2320 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2321 nir_intrinsic_instr *instr)
2322 {
2323 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2324 unsigned desc_set = nir_intrinsic_desc_set(instr);
2325 unsigned binding = nir_intrinsic_binding(instr);
2326 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2327 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2328 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2329 unsigned base_offset = layout->binding[binding].offset;
2330 LLVMValueRef offset, stride;
2331
2332 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2333 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2334 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2335 layout->binding[binding].dynamic_offset_offset;
2336 desc_ptr = ctx->push_constants;
2337 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2338 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2339 } else
2340 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2341
2342 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2343 index = LLVMBuildMul(ctx->builder, index, stride, "");
2344 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2345
2346 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2347 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2348 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2349
2350 return desc_ptr;
2351 }
2352
2353 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2354 nir_intrinsic_instr *instr)
2355 {
2356 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2357 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2358
2359 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2360 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2361 return result;
2362 }
2363
2364 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2365 nir_intrinsic_instr *instr)
2366 {
2367 LLVMValueRef ptr, addr;
2368
2369 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2370 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2371
2372 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2373 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2374
2375 return LLVMBuildLoad(ctx->builder, ptr, "");
2376 }
2377
2378 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2379 const nir_intrinsic_instr *instr)
2380 {
2381 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2382
2383 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2384 }
2385 static void visit_store_ssbo(struct ac_nir_context *ctx,
2386 nir_intrinsic_instr *instr)
2387 {
2388 const char *store_name;
2389 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2390 LLVMTypeRef data_type = ctx->ac.f32;
2391 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2392 int components_32bit = elem_size_mult * instr->num_components;
2393 unsigned writemask = nir_intrinsic_write_mask(instr);
2394 LLVMValueRef base_data, base_offset;
2395 LLVMValueRef params[6];
2396
2397 params[1] = ctx->abi->load_ssbo(ctx->abi,
2398 get_src(ctx, instr->src[1]), true);
2399 params[2] = ctx->ac.i32_0; /* vindex */
2400 params[4] = ctx->ac.i1false; /* glc */
2401 params[5] = ctx->ac.i1false; /* slc */
2402
2403 if (components_32bit > 1)
2404 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2405
2406 base_data = ac_to_float(&ctx->ac, src_data);
2407 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2408 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2409 data_type, "");
2410 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2411 while (writemask) {
2412 int start, count;
2413 LLVMValueRef data;
2414 LLVMValueRef offset;
2415 LLVMValueRef tmp;
2416 u_bit_scan_consecutive_range(&writemask, &start, &count);
2417
2418 /* Due to an LLVM limitation, split 3-element writes
2419 * into a 2-element and a 1-element write. */
2420 if (count == 3) {
2421 writemask |= 1 << (start + 2);
2422 count = 2;
2423 }
2424
2425 start *= elem_size_mult;
2426 count *= elem_size_mult;
2427
2428 if (count > 4) {
2429 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2430 count = 4;
2431 }
2432
2433 if (count == 4) {
2434 store_name = "llvm.amdgcn.buffer.store.v4f32";
2435 data = base_data;
2436 } else if (count == 2) {
2437 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2438 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2439 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2440 ctx->ac.i32_0, "");
2441
2442 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2443 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2444 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2445 ctx->ac.i32_1, "");
2446 store_name = "llvm.amdgcn.buffer.store.v2f32";
2447
2448 } else {
2449 assert(count == 1);
2450 if (get_llvm_num_components(base_data) > 1)
2451 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2452 LLVMConstInt(ctx->ac.i32, start, false), "");
2453 else
2454 data = base_data;
2455 store_name = "llvm.amdgcn.buffer.store.f32";
2456 }
2457
2458 offset = base_offset;
2459 if (start != 0) {
2460 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2461 }
2462 params[0] = data;
2463 params[3] = offset;
2464 ac_build_intrinsic(&ctx->ac, store_name,
2465 ctx->ac.voidt, params, 6, 0);
2466 }
2467 }
2468
2469 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2470 const nir_intrinsic_instr *instr)
2471 {
2472 const char *name;
2473 LLVMValueRef params[6];
2474 int arg_count = 0;
2475
2476 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2477 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2478 }
2479 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2480 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2481 get_src(ctx, instr->src[0]),
2482 true);
2483 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2484 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2485 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2486
2487 switch (instr->intrinsic) {
2488 case nir_intrinsic_ssbo_atomic_add:
2489 name = "llvm.amdgcn.buffer.atomic.add";
2490 break;
2491 case nir_intrinsic_ssbo_atomic_imin:
2492 name = "llvm.amdgcn.buffer.atomic.smin";
2493 break;
2494 case nir_intrinsic_ssbo_atomic_umin:
2495 name = "llvm.amdgcn.buffer.atomic.umin";
2496 break;
2497 case nir_intrinsic_ssbo_atomic_imax:
2498 name = "llvm.amdgcn.buffer.atomic.smax";
2499 break;
2500 case nir_intrinsic_ssbo_atomic_umax:
2501 name = "llvm.amdgcn.buffer.atomic.umax";
2502 break;
2503 case nir_intrinsic_ssbo_atomic_and:
2504 name = "llvm.amdgcn.buffer.atomic.and";
2505 break;
2506 case nir_intrinsic_ssbo_atomic_or:
2507 name = "llvm.amdgcn.buffer.atomic.or";
2508 break;
2509 case nir_intrinsic_ssbo_atomic_xor:
2510 name = "llvm.amdgcn.buffer.atomic.xor";
2511 break;
2512 case nir_intrinsic_ssbo_atomic_exchange:
2513 name = "llvm.amdgcn.buffer.atomic.swap";
2514 break;
2515 case nir_intrinsic_ssbo_atomic_comp_swap:
2516 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2517 break;
2518 default:
2519 abort();
2520 }
2521
2522 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2523 }
2524
2525 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2526 const nir_intrinsic_instr *instr)
2527 {
2528 LLVMValueRef results[2];
2529 int load_components;
2530 int num_components = instr->num_components;
2531 if (instr->dest.ssa.bit_size == 64)
2532 num_components *= 2;
2533
2534 for (int i = 0; i < num_components; i += load_components) {
2535 load_components = MIN2(num_components - i, 4);
2536 const char *load_name;
2537 LLVMTypeRef data_type = ctx->ac.f32;
2538 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2539 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2540
2541 if (load_components == 3)
2542 data_type = LLVMVectorType(ctx->ac.f32, 4);
2543 else if (load_components > 1)
2544 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2545
2546 if (load_components >= 3)
2547 load_name = "llvm.amdgcn.buffer.load.v4f32";
2548 else if (load_components == 2)
2549 load_name = "llvm.amdgcn.buffer.load.v2f32";
2550 else if (load_components == 1)
2551 load_name = "llvm.amdgcn.buffer.load.f32";
2552 else
2553 unreachable("unhandled number of components");
2554
2555 LLVMValueRef params[] = {
2556 ctx->abi->load_ssbo(ctx->abi,
2557 get_src(ctx, instr->src[0]),
2558 false),
2559 ctx->ac.i32_0,
2560 offset,
2561 ctx->ac.i1false,
2562 ctx->ac.i1false,
2563 };
2564
2565 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2566
2567 }
2568
2569 assume(results[0]);
2570 LLVMValueRef ret = results[0];
2571 if (num_components > 4 || num_components == 3) {
2572 LLVMValueRef masks[] = {
2573 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2574 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2575 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2576 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2577 };
2578
2579 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2580 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2581 results[num_components > 4 ? 1 : 0], swizzle, "");
2582 }
2583
2584 return LLVMBuildBitCast(ctx->ac.builder, ret,
2585 get_def_type(ctx, &instr->dest.ssa), "");
2586 }
2587
2588 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2589 const nir_intrinsic_instr *instr)
2590 {
2591 LLVMValueRef results[8], ret;
2592 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2593 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2594 int num_components = instr->num_components;
2595
2596 if (ctx->abi->load_ubo)
2597 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2598
2599 if (instr->dest.ssa.bit_size == 64)
2600 num_components *= 2;
2601
2602 for (unsigned i = 0; i < num_components; ++i) {
2603 LLVMValueRef params[] = {
2604 rsrc,
2605 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2606 offset, "")
2607 };
2608 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2609 params, 2,
2610 AC_FUNC_ATTR_READNONE |
2611 AC_FUNC_ATTR_LEGACY);
2612 }
2613
2614
2615 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2616 return LLVMBuildBitCast(ctx->ac.builder, ret,
2617 get_def_type(ctx, &instr->dest.ssa), "");
2618 }
2619
2620 static void
2621 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2622 bool vs_in, unsigned *vertex_index_out,
2623 LLVMValueRef *vertex_index_ref,
2624 unsigned *const_out, LLVMValueRef *indir_out)
2625 {
2626 unsigned const_offset = 0;
2627 nir_deref *tail = &deref->deref;
2628 LLVMValueRef offset = NULL;
2629
2630 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2631 tail = tail->child;
2632 nir_deref_array *deref_array = nir_deref_as_array(tail);
2633 if (vertex_index_out)
2634 *vertex_index_out = deref_array->base_offset;
2635
2636 if (vertex_index_ref) {
2637 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2638 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2639 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2640 }
2641 *vertex_index_ref = vtx;
2642 }
2643 }
2644
2645 if (deref->var->data.compact) {
2646 assert(tail->child->deref_type == nir_deref_type_array);
2647 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2648 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2649 /* We always lower indirect dereferences for "compact" array vars. */
2650 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2651
2652 const_offset = deref_array->base_offset;
2653 goto out;
2654 }
2655
2656 while (tail->child != NULL) {
2657 const struct glsl_type *parent_type = tail->type;
2658 tail = tail->child;
2659
2660 if (tail->deref_type == nir_deref_type_array) {
2661 nir_deref_array *deref_array = nir_deref_as_array(tail);
2662 LLVMValueRef index, stride, local_offset;
2663 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2664
2665 const_offset += size * deref_array->base_offset;
2666 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2667 continue;
2668
2669 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2670 index = get_src(ctx, deref_array->indirect);
2671 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2672 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2673
2674 if (offset)
2675 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2676 else
2677 offset = local_offset;
2678 } else if (tail->deref_type == nir_deref_type_struct) {
2679 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2680
2681 for (unsigned i = 0; i < deref_struct->index; i++) {
2682 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2683 const_offset += glsl_count_attribute_slots(ft, vs_in);
2684 }
2685 } else
2686 unreachable("unsupported deref type");
2687
2688 }
2689 out:
2690 if (const_offset && offset)
2691 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2692 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2693 "");
2694
2695 *const_out = const_offset;
2696 *indir_out = offset;
2697 }
2698
2699
2700 /* The offchip buffer layout for TCS->TES is
2701 *
2702 * - attribute 0 of patch 0 vertex 0
2703 * - attribute 0 of patch 0 vertex 1
2704 * - attribute 0 of patch 0 vertex 2
2705 * ...
2706 * - attribute 0 of patch 1 vertex 0
2707 * - attribute 0 of patch 1 vertex 1
2708 * ...
2709 * - attribute 1 of patch 0 vertex 0
2710 * - attribute 1 of patch 0 vertex 1
2711 * ...
2712 * - per patch attribute 0 of patch 0
2713 * - per patch attribute 0 of patch 1
2714 * ...
2715 *
2716 * Note that every attribute has 4 components.
2717 */
2718 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2719 LLVMValueRef vertex_index,
2720 LLVMValueRef param_index)
2721 {
2722 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2723 LLVMValueRef param_stride, constant16;
2724 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2725
2726 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2727 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2728 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2729 num_patches, "");
2730
2731 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2732 if (vertex_index) {
2733 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2734 vertices_per_patch, "");
2735
2736 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2737 vertex_index, "");
2738
2739 param_stride = total_vertices;
2740 } else {
2741 base_addr = rel_patch_id;
2742 param_stride = num_patches;
2743 }
2744
2745 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2746 LLVMBuildMul(ctx->builder, param_index,
2747 param_stride, ""), "");
2748
2749 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2750
2751 if (!vertex_index) {
2752 LLVMValueRef patch_data_offset =
2753 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2754
2755 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2756 patch_data_offset, "");
2757 }
2758 return base_addr;
2759 }
2760
2761 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2762 unsigned param,
2763 unsigned const_index,
2764 bool is_compact,
2765 LLVMValueRef vertex_index,
2766 LLVMValueRef indir_index)
2767 {
2768 LLVMValueRef param_index;
2769
2770 if (indir_index)
2771 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2772 indir_index, "");
2773 else {
2774 if (const_index && !is_compact)
2775 param += const_index;
2776 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2777 }
2778 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2779 }
2780
2781 static void
2782 mark_tess_output(struct nir_to_llvm_context *ctx,
2783 bool is_patch, uint32_t param)
2784
2785 {
2786 if (is_patch) {
2787 ctx->tess_patch_outputs_written |= (1ull << param);
2788 } else
2789 ctx->tess_outputs_written |= (1ull << param);
2790 }
2791
2792 static LLVMValueRef
2793 get_dw_address(struct nir_to_llvm_context *ctx,
2794 LLVMValueRef dw_addr,
2795 unsigned param,
2796 unsigned const_index,
2797 bool compact_const_index,
2798 LLVMValueRef vertex_index,
2799 LLVMValueRef stride,
2800 LLVMValueRef indir_index)
2801
2802 {
2803
2804 if (vertex_index) {
2805 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2806 LLVMBuildMul(ctx->builder,
2807 vertex_index,
2808 stride, ""), "");
2809 }
2810
2811 if (indir_index)
2812 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2813 LLVMBuildMul(ctx->builder, indir_index,
2814 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2815 else if (const_index && !compact_const_index)
2816 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2817 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2818
2819 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2820 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2821
2822 if (const_index && compact_const_index)
2823 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2824 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2825 return dw_addr;
2826 }
2827
2828 static LLVMValueRef
2829 load_tcs_input(struct nir_to_llvm_context *ctx,
2830 nir_intrinsic_instr *instr)
2831 {
2832 LLVMValueRef dw_addr, stride;
2833 unsigned const_index;
2834 LLVMValueRef vertex_index;
2835 LLVMValueRef indir_index;
2836 unsigned param;
2837 LLVMValueRef value[4], result;
2838 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2839 const bool is_compact = instr->variables[0]->var->data.compact;
2840 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2841 get_deref_offset(ctx->nir, instr->variables[0],
2842 false, NULL, per_vertex ? &vertex_index : NULL,
2843 &const_index, &indir_index);
2844
2845 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2846 dw_addr = get_tcs_in_current_patch_offset(ctx);
2847 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2848 indir_index);
2849
2850 unsigned comp = instr->variables[0]->var->data.location_frac;
2851 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2852 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2853 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2854 ctx->ac.i32_1, "");
2855 }
2856 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2857 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2858 return result;
2859 }
2860
2861 static LLVMValueRef
2862 load_tcs_output(struct nir_to_llvm_context *ctx,
2863 nir_intrinsic_instr *instr)
2864 {
2865 LLVMValueRef dw_addr;
2866 LLVMValueRef stride = NULL;
2867 LLVMValueRef value[4], result;
2868 LLVMValueRef vertex_index = NULL;
2869 LLVMValueRef indir_index = NULL;
2870 unsigned const_index = 0;
2871 unsigned param;
2872 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2873 const bool is_compact = instr->variables[0]->var->data.compact;
2874 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2875 get_deref_offset(ctx->nir, instr->variables[0],
2876 false, NULL, per_vertex ? &vertex_index : NULL,
2877 &const_index, &indir_index);
2878
2879 if (!instr->variables[0]->var->data.patch) {
2880 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2881 dw_addr = get_tcs_out_current_patch_offset(ctx);
2882 } else {
2883 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2884 }
2885
2886 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2887 indir_index);
2888
2889 unsigned comp = instr->variables[0]->var->data.location_frac;
2890 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2891 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2892 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2893 ctx->ac.i32_1, "");
2894 }
2895 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2896 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2897 return result;
2898 }
2899
2900 static void
2901 store_tcs_output(struct nir_to_llvm_context *ctx,
2902 nir_intrinsic_instr *instr,
2903 LLVMValueRef src,
2904 unsigned writemask)
2905 {
2906 LLVMValueRef dw_addr;
2907 LLVMValueRef stride = NULL;
2908 LLVMValueRef buf_addr = NULL;
2909 LLVMValueRef vertex_index = NULL;
2910 LLVMValueRef indir_index = NULL;
2911 unsigned const_index = 0;
2912 unsigned param;
2913 const unsigned comp = instr->variables[0]->var->data.location_frac;
2914 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2915 const bool is_compact = instr->variables[0]->var->data.compact;
2916 bool store_lds = true;
2917
2918 if (instr->variables[0]->var->data.patch) {
2919 if (!(ctx->tcs_patch_outputs_read & (1U << (instr->variables[0]->var->data.location - VARYING_SLOT_PATCH0))))
2920 store_lds = false;
2921 } else {
2922 if (!(ctx->tcs_outputs_read & (1ULL << instr->variables[0]->var->data.location)))
2923 store_lds = false;
2924 }
2925 get_deref_offset(ctx->nir, instr->variables[0],
2926 false, NULL, per_vertex ? &vertex_index : NULL,
2927 &const_index, &indir_index);
2928
2929 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2930 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2931 is_compact && const_index > 3) {
2932 const_index -= 3;
2933 param++;
2934 }
2935
2936 if (!instr->variables[0]->var->data.patch) {
2937 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2938 dw_addr = get_tcs_out_current_patch_offset(ctx);
2939 } else {
2940 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2941 }
2942
2943 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2944
2945 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2946 indir_index);
2947 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2948 vertex_index, indir_index);
2949
2950 bool is_tess_factor = false;
2951 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2952 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2953 is_tess_factor = true;
2954
2955 unsigned base = is_compact ? const_index : 0;
2956 for (unsigned chan = 0; chan < 8; chan++) {
2957 if (!(writemask & (1 << chan)))
2958 continue;
2959 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2960
2961 if (store_lds || is_tess_factor)
2962 ac_lds_store(&ctx->ac, dw_addr, value);
2963
2964 if (!is_tess_factor && writemask != 0xF)
2965 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2966 buf_addr, ctx->oc_lds,
2967 4 * (base + chan), 1, 0, true, false);
2968
2969 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2970 ctx->ac.i32_1, "");
2971 }
2972
2973 if (writemask == 0xF) {
2974 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2975 buf_addr, ctx->oc_lds,
2976 (base * 4), 1, 0, true, false);
2977 }
2978 }
2979
2980 static LLVMValueRef
2981 load_tes_input(struct nir_to_llvm_context *ctx,
2982 const nir_intrinsic_instr *instr)
2983 {
2984 LLVMValueRef buf_addr;
2985 LLVMValueRef result;
2986 LLVMValueRef vertex_index = NULL;
2987 LLVMValueRef indir_index = NULL;
2988 unsigned const_index = 0;
2989 unsigned param;
2990 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2991 const bool is_compact = instr->variables[0]->var->data.compact;
2992
2993 get_deref_offset(ctx->nir, instr->variables[0],
2994 false, NULL, per_vertex ? &vertex_index : NULL,
2995 &const_index, &indir_index);
2996 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2997 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2998 is_compact && const_index > 3) {
2999 const_index -= 3;
3000 param++;
3001 }
3002
3003 unsigned comp = instr->variables[0]->var->data.location_frac;
3004 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3005 is_compact, vertex_index, indir_index);
3006
3007 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, comp * 4, false);
3008 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3009
3010 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
3011 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3012 result = trim_vector(&ctx->ac, result, instr->num_components);
3013 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
3014 return result;
3015 }
3016
3017 static LLVMValueRef
3018 load_gs_input(struct ac_shader_abi *abi,
3019 unsigned location,
3020 unsigned driver_location,
3021 unsigned component,
3022 unsigned num_components,
3023 unsigned vertex_index,
3024 unsigned const_index,
3025 LLVMTypeRef type)
3026 {
3027 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3028 LLVMValueRef vtx_offset;
3029 LLVMValueRef args[9];
3030 unsigned param, vtx_offset_param;
3031 LLVMValueRef value[4], result;
3032
3033 vtx_offset_param = vertex_index;
3034 assert(vtx_offset_param < 6);
3035 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3036 LLVMConstInt(ctx->ac.i32, 4, false), "");
3037
3038 param = shader_io_get_unique_index(location);
3039
3040 for (unsigned i = component; i < num_components + component; i++) {
3041 if (ctx->ac.chip_class >= GFX9) {
3042 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3043 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3044 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3045 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3046 } else {
3047 args[0] = ctx->esgs_ring;
3048 args[1] = vtx_offset;
3049 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3050 args[3] = ctx->ac.i32_0;
3051 args[4] = ctx->ac.i32_1; /* OFFEN */
3052 args[5] = ctx->ac.i32_0; /* IDXEN */
3053 args[6] = ctx->ac.i32_1; /* GLC */
3054 args[7] = ctx->ac.i32_0; /* SLC */
3055 args[8] = ctx->ac.i32_0; /* TFE */
3056
3057 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3058 ctx->ac.i32, args, 9,
3059 AC_FUNC_ATTR_READONLY |
3060 AC_FUNC_ATTR_LEGACY);
3061 }
3062 }
3063 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3064
3065 return result;
3066 }
3067
3068 static LLVMValueRef
3069 build_gep_for_deref(struct ac_nir_context *ctx,
3070 nir_deref_var *deref)
3071 {
3072 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3073 assert(entry->data);
3074 LLVMValueRef val = entry->data;
3075 nir_deref *tail = deref->deref.child;
3076 while (tail != NULL) {
3077 LLVMValueRef offset;
3078 switch (tail->deref_type) {
3079 case nir_deref_type_array: {
3080 nir_deref_array *array = nir_deref_as_array(tail);
3081 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3082 if (array->deref_array_type ==
3083 nir_deref_array_type_indirect) {
3084 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3085 get_src(ctx,
3086 array->indirect),
3087 "");
3088 }
3089 break;
3090 }
3091 case nir_deref_type_struct: {
3092 nir_deref_struct *deref_struct =
3093 nir_deref_as_struct(tail);
3094 offset = LLVMConstInt(ctx->ac.i32,
3095 deref_struct->index, 0);
3096 break;
3097 }
3098 default:
3099 unreachable("bad deref type");
3100 }
3101 val = ac_build_gep0(&ctx->ac, val, offset);
3102 tail = tail->child;
3103 }
3104 return val;
3105 }
3106
3107 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3108 nir_intrinsic_instr *instr)
3109 {
3110 LLVMValueRef values[8];
3111 int idx = instr->variables[0]->var->data.driver_location;
3112 int ve = instr->dest.ssa.num_components;
3113 unsigned comp = instr->variables[0]->var->data.location_frac;
3114 LLVMValueRef indir_index;
3115 LLVMValueRef ret;
3116 unsigned const_index;
3117 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3118 instr->variables[0]->var->data.mode == nir_var_shader_in;
3119 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3120 &const_index, &indir_index);
3121
3122 if (instr->dest.ssa.bit_size == 64)
3123 ve *= 2;
3124
3125 switch (instr->variables[0]->var->data.mode) {
3126 case nir_var_shader_in:
3127 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3128 return load_tcs_input(ctx->nctx, instr);
3129 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3130 return load_tes_input(ctx->nctx, instr);
3131 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3132 LLVMValueRef indir_index;
3133 unsigned const_index, vertex_index;
3134 get_deref_offset(ctx, instr->variables[0],
3135 false, &vertex_index, NULL,
3136 &const_index, &indir_index);
3137 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3138 instr->variables[0]->var->data.driver_location,
3139 instr->variables[0]->var->data.location_frac, ve,
3140 vertex_index, const_index,
3141 nir2llvmtype(ctx, instr->variables[0]->var->type));
3142 }
3143
3144 for (unsigned chan = comp; chan < ve + comp; chan++) {
3145 if (indir_index) {
3146 unsigned count = glsl_count_attribute_slots(
3147 instr->variables[0]->var->type,
3148 ctx->stage == MESA_SHADER_VERTEX);
3149 count -= chan / 4;
3150 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3151 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3152 4, false, true);
3153
3154 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3155 tmp_vec,
3156 indir_index, "");
3157 } else
3158 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3159 }
3160 break;
3161 case nir_var_local:
3162 for (unsigned chan = 0; chan < ve; chan++) {
3163 if (indir_index) {
3164 unsigned count = glsl_count_attribute_slots(
3165 instr->variables[0]->var->type, false);
3166 count -= chan / 4;
3167 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3168 &ctx->ac, ctx->locals + idx + chan, count,
3169 4, true, true);
3170
3171 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3172 tmp_vec,
3173 indir_index, "");
3174 } else {
3175 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3176 }
3177 }
3178 break;
3179 case nir_var_shared: {
3180 LLVMValueRef address = build_gep_for_deref(ctx,
3181 instr->variables[0]);
3182 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3183 return LLVMBuildBitCast(ctx->ac.builder, val,
3184 get_def_type(ctx, &instr->dest.ssa),
3185 "");
3186 }
3187 case nir_var_shader_out:
3188 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3189 return load_tcs_output(ctx->nctx, instr);
3190
3191 for (unsigned chan = comp; chan < ve + comp; chan++) {
3192 if (indir_index) {
3193 unsigned count = glsl_count_attribute_slots(
3194 instr->variables[0]->var->type, false);
3195 count -= chan / 4;
3196 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3197 &ctx->ac, ctx->outputs + idx + chan, count,
3198 4, true, true);
3199
3200 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3201 tmp_vec,
3202 indir_index, "");
3203 } else {
3204 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3205 ctx->outputs[idx + chan + const_index * 4],
3206 "");
3207 }
3208 }
3209 break;
3210 default:
3211 unreachable("unhandle variable mode");
3212 }
3213 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3214 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3215 }
3216
3217 static void
3218 visit_store_var(struct ac_nir_context *ctx,
3219 nir_intrinsic_instr *instr)
3220 {
3221 LLVMValueRef temp_ptr, value;
3222 int idx = instr->variables[0]->var->data.driver_location;
3223 unsigned comp = instr->variables[0]->var->data.location_frac;
3224 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3225 int writemask = instr->const_index[0] << comp;
3226 LLVMValueRef indir_index;
3227 unsigned const_index;
3228 get_deref_offset(ctx, instr->variables[0], false,
3229 NULL, NULL, &const_index, &indir_index);
3230
3231 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3232 int old_writemask = writemask;
3233
3234 src = LLVMBuildBitCast(ctx->ac.builder, src,
3235 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3236 "");
3237
3238 writemask = 0;
3239 for (unsigned chan = 0; chan < 4; chan++) {
3240 if (old_writemask & (1 << chan))
3241 writemask |= 3u << (2 * chan);
3242 }
3243 }
3244
3245 switch (instr->variables[0]->var->data.mode) {
3246 case nir_var_shader_out:
3247
3248 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3249 store_tcs_output(ctx->nctx, instr, src, writemask);
3250 return;
3251 }
3252
3253 for (unsigned chan = 0; chan < 8; chan++) {
3254 int stride = 4;
3255 if (!(writemask & (1 << chan)))
3256 continue;
3257
3258 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3259
3260 if (instr->variables[0]->var->data.compact)
3261 stride = 1;
3262 if (indir_index) {
3263 unsigned count = glsl_count_attribute_slots(
3264 instr->variables[0]->var->type, false);
3265 count -= chan / 4;
3266 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3267 &ctx->ac, ctx->outputs + idx + chan, count,
3268 stride, true, true);
3269
3270 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3271 value, indir_index, "");
3272 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3273 count, stride, tmp_vec);
3274
3275 } else {
3276 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3277
3278 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3279 }
3280 }
3281 break;
3282 case nir_var_local:
3283 for (unsigned chan = 0; chan < 8; chan++) {
3284 if (!(writemask & (1 << chan)))
3285 continue;
3286
3287 value = llvm_extract_elem(&ctx->ac, src, chan);
3288 if (indir_index) {
3289 unsigned count = glsl_count_attribute_slots(
3290 instr->variables[0]->var->type, false);
3291 count -= chan / 4;
3292 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3293 &ctx->ac, ctx->locals + idx + chan, count,
3294 4, true, true);
3295
3296 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3297 value, indir_index, "");
3298 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3299 count, 4, tmp_vec);
3300 } else {
3301 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3302
3303 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3304 }
3305 }
3306 break;
3307 case nir_var_shared: {
3308 int writemask = instr->const_index[0];
3309 LLVMValueRef address = build_gep_for_deref(ctx,
3310 instr->variables[0]);
3311 LLVMValueRef val = get_src(ctx, instr->src[0]);
3312 unsigned components =
3313 glsl_get_vector_elements(
3314 nir_deref_tail(&instr->variables[0]->deref)->type);
3315 if (writemask == (1 << components) - 1) {
3316 val = LLVMBuildBitCast(
3317 ctx->ac.builder, val,
3318 LLVMGetElementType(LLVMTypeOf(address)), "");
3319 LLVMBuildStore(ctx->ac.builder, val, address);
3320 } else {
3321 for (unsigned chan = 0; chan < 4; chan++) {
3322 if (!(writemask & (1 << chan)))
3323 continue;
3324 LLVMValueRef ptr =
3325 LLVMBuildStructGEP(ctx->ac.builder,
3326 address, chan, "");
3327 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3328 chan);
3329 src = LLVMBuildBitCast(
3330 ctx->ac.builder, src,
3331 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3332 LLVMBuildStore(ctx->ac.builder, src, ptr);
3333 }
3334 }
3335 break;
3336 }
3337 default:
3338 break;
3339 }
3340 }
3341
3342 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3343 {
3344 switch (dim) {
3345 case GLSL_SAMPLER_DIM_BUF:
3346 return 1;
3347 case GLSL_SAMPLER_DIM_1D:
3348 return array ? 2 : 1;
3349 case GLSL_SAMPLER_DIM_2D:
3350 return array ? 3 : 2;
3351 case GLSL_SAMPLER_DIM_MS:
3352 return array ? 4 : 3;
3353 case GLSL_SAMPLER_DIM_3D:
3354 case GLSL_SAMPLER_DIM_CUBE:
3355 return 3;
3356 case GLSL_SAMPLER_DIM_RECT:
3357 case GLSL_SAMPLER_DIM_SUBPASS:
3358 return 2;
3359 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3360 return 3;
3361 default:
3362 break;
3363 }
3364 return 0;
3365 }
3366
3367
3368
3369 /* Adjust the sample index according to FMASK.
3370 *
3371 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3372 * which is the identity mapping. Each nibble says which physical sample
3373 * should be fetched to get that sample.
3374 *
3375 * For example, 0x11111100 means there are only 2 samples stored and
3376 * the second sample covers 3/4 of the pixel. When reading samples 0
3377 * and 1, return physical sample 0 (determined by the first two 0s
3378 * in FMASK), otherwise return physical sample 1.
3379 *
3380 * The sample index should be adjusted as follows:
3381 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3382 */
3383 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3384 LLVMValueRef coord_x, LLVMValueRef coord_y,
3385 LLVMValueRef coord_z,
3386 LLVMValueRef sample_index,
3387 LLVMValueRef fmask_desc_ptr)
3388 {
3389 LLVMValueRef fmask_load_address[4];
3390 LLVMValueRef res;
3391
3392 fmask_load_address[0] = coord_x;
3393 fmask_load_address[1] = coord_y;
3394 if (coord_z) {
3395 fmask_load_address[2] = coord_z;
3396 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3397 }
3398
3399 struct ac_image_args args = {0};
3400
3401 args.opcode = ac_image_load;
3402 args.da = coord_z ? true : false;
3403 args.resource = fmask_desc_ptr;
3404 args.dmask = 0xf;
3405 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3406
3407 res = ac_build_image_opcode(ctx, &args);
3408
3409 res = ac_to_integer(ctx, res);
3410 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3411 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3412
3413 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3414 res,
3415 ctx->i32_0, "");
3416
3417 LLVMValueRef sample_index4 =
3418 LLVMBuildMul(ctx->builder, sample_index, four, "");
3419 LLVMValueRef shifted_fmask =
3420 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3421 LLVMValueRef final_sample =
3422 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3423
3424 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3425 * resource descriptor is 0 (invalid),
3426 */
3427 LLVMValueRef fmask_desc =
3428 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3429 ctx->v8i32, "");
3430
3431 LLVMValueRef fmask_word1 =
3432 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3433 ctx->i32_1, "");
3434
3435 LLVMValueRef word1_is_nonzero =
3436 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3437 fmask_word1, ctx->i32_0, "");
3438
3439 /* Replace the MSAA sample index. */
3440 sample_index =
3441 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3442 final_sample, sample_index, "");
3443 return sample_index;
3444 }
3445
3446 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3447 const nir_intrinsic_instr *instr)
3448 {
3449 const struct glsl_type *type = instr->variables[0]->var->type;
3450 if(instr->variables[0]->deref.child)
3451 type = instr->variables[0]->deref.child->type;
3452
3453 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3454 LLVMValueRef coords[4];
3455 LLVMValueRef masks[] = {
3456 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3457 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3458 };
3459 LLVMValueRef res;
3460 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3461
3462 int count;
3463 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3464 bool is_array = glsl_sampler_type_is_array(type);
3465 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3466 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3467 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3468 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3469 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3470 count = image_type_to_components_count(dim, is_array);
3471
3472 if (is_ms) {
3473 LLVMValueRef fmask_load_address[3];
3474 int chan;
3475
3476 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3477 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3478 if (is_array)
3479 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3480 else
3481 fmask_load_address[2] = NULL;
3482 if (add_frag_pos) {
3483 for (chan = 0; chan < 2; ++chan)
3484 fmask_load_address[chan] =
3485 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3486 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3487 ctx->ac.i32, ""), "");
3488 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3489 }
3490 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3491 fmask_load_address[0],
3492 fmask_load_address[1],
3493 fmask_load_address[2],
3494 sample_index,
3495 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3496 }
3497 if (count == 1 && !gfx9_1d) {
3498 if (instr->src[0].ssa->num_components)
3499 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3500 else
3501 res = src0;
3502 } else {
3503 int chan;
3504 if (is_ms)
3505 count--;
3506 for (chan = 0; chan < count; ++chan) {
3507 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3508 }
3509 if (add_frag_pos) {
3510 for (chan = 0; chan < 2; ++chan)
3511 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3512 ctx->ac.i32, ""), "");
3513 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3514 count++;
3515 }
3516
3517 if (gfx9_1d) {
3518 if (is_array) {
3519 coords[2] = coords[1];
3520 coords[1] = ctx->ac.i32_0;
3521 } else
3522 coords[1] = ctx->ac.i32_0;
3523 count++;
3524 }
3525
3526 if (is_ms) {
3527 coords[count] = sample_index;
3528 count++;
3529 }
3530
3531 if (count == 3) {
3532 coords[3] = LLVMGetUndef(ctx->ac.i32);
3533 count = 4;
3534 }
3535 res = ac_build_gather_values(&ctx->ac, coords, count);
3536 }
3537 return res;
3538 }
3539
3540 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3541 const nir_intrinsic_instr *instr)
3542 {
3543 LLVMValueRef params[7];
3544 LLVMValueRef res;
3545 char intrinsic_name[64];
3546 const nir_variable *var = instr->variables[0]->var;
3547 const struct glsl_type *type = var->type;
3548
3549 if(instr->variables[0]->deref.child)
3550 type = instr->variables[0]->deref.child->type;
3551
3552 type = glsl_without_array(type);
3553 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3554 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3555 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3556 ctx->ac.i32_0, ""); /* vindex */
3557 params[2] = ctx->ac.i32_0; /* voffset */
3558 params[3] = ctx->ac.i1false; /* glc */
3559 params[4] = ctx->ac.i1false; /* slc */
3560 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3561 params, 5, 0);
3562
3563 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3564 res = ac_to_integer(&ctx->ac, res);
3565 } else {
3566 bool is_da = glsl_sampler_type_is_array(type) ||
3567 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3568 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3569 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3570 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3571 LLVMValueRef glc = ctx->ac.i1false;
3572 LLVMValueRef slc = ctx->ac.i1false;
3573
3574 params[0] = get_image_coords(ctx, instr);
3575 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3576 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3577 if (HAVE_LLVM <= 0x0309) {
3578 params[3] = ctx->ac.i1false; /* r128 */
3579 params[4] = da;
3580 params[5] = glc;
3581 params[6] = slc;
3582 } else {
3583 LLVMValueRef lwe = ctx->ac.i1false;
3584 params[3] = glc;
3585 params[4] = slc;
3586 params[5] = lwe;
3587 params[6] = da;
3588 }
3589
3590 ac_get_image_intr_name("llvm.amdgcn.image.load",
3591 ctx->ac.v4f32, /* vdata */
3592 LLVMTypeOf(params[0]), /* coords */
3593 LLVMTypeOf(params[1]), /* rsrc */
3594 intrinsic_name, sizeof(intrinsic_name));
3595
3596 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3597 params, 7, AC_FUNC_ATTR_READONLY);
3598 }
3599 return ac_to_integer(&ctx->ac, res);
3600 }
3601
3602 static void visit_image_store(struct ac_nir_context *ctx,
3603 nir_intrinsic_instr *instr)
3604 {
3605 LLVMValueRef params[8];
3606 char intrinsic_name[64];
3607 const nir_variable *var = instr->variables[0]->var;
3608 const struct glsl_type *type = glsl_without_array(var->type);
3609 LLVMValueRef glc = ctx->ac.i1false;
3610 bool force_glc = ctx->ac.chip_class == SI;
3611 if (force_glc)
3612 glc = ctx->ac.i1true;
3613
3614 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3615 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3616 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3617 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3618 ctx->ac.i32_0, ""); /* vindex */
3619 params[3] = ctx->ac.i32_0; /* voffset */
3620 params[4] = glc; /* glc */
3621 params[5] = ctx->ac.i1false; /* slc */
3622 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3623 params, 6, 0);
3624 } else {
3625 bool is_da = glsl_sampler_type_is_array(type) ||
3626 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3627 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3628 LLVMValueRef slc = ctx->ac.i1false;
3629
3630 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3631 params[1] = get_image_coords(ctx, instr); /* coords */
3632 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3633 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3634 if (HAVE_LLVM <= 0x0309) {
3635 params[4] = ctx->ac.i1false; /* r128 */
3636 params[5] = da;
3637 params[6] = glc;
3638 params[7] = slc;
3639 } else {
3640 LLVMValueRef lwe = ctx->ac.i1false;
3641 params[4] = glc;
3642 params[5] = slc;
3643 params[6] = lwe;
3644 params[7] = da;
3645 }
3646
3647 ac_get_image_intr_name("llvm.amdgcn.image.store",
3648 LLVMTypeOf(params[0]), /* vdata */
3649 LLVMTypeOf(params[1]), /* coords */
3650 LLVMTypeOf(params[2]), /* rsrc */
3651 intrinsic_name, sizeof(intrinsic_name));
3652
3653 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3654 params, 8, 0);
3655 }
3656
3657 }
3658
3659 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3660 const nir_intrinsic_instr *instr)
3661 {
3662 LLVMValueRef params[7];
3663 int param_count = 0;
3664 const nir_variable *var = instr->variables[0]->var;
3665
3666 const char *atomic_name;
3667 char intrinsic_name[41];
3668 const struct glsl_type *type = glsl_without_array(var->type);
3669 MAYBE_UNUSED int length;
3670
3671 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3672
3673 switch (instr->intrinsic) {
3674 case nir_intrinsic_image_atomic_add:
3675 atomic_name = "add";
3676 break;
3677 case nir_intrinsic_image_atomic_min:
3678 atomic_name = is_unsigned ? "umin" : "smin";
3679 break;
3680 case nir_intrinsic_image_atomic_max:
3681 atomic_name = is_unsigned ? "umax" : "smax";
3682 break;
3683 case nir_intrinsic_image_atomic_and:
3684 atomic_name = "and";
3685 break;
3686 case nir_intrinsic_image_atomic_or:
3687 atomic_name = "or";
3688 break;
3689 case nir_intrinsic_image_atomic_xor:
3690 atomic_name = "xor";
3691 break;
3692 case nir_intrinsic_image_atomic_exchange:
3693 atomic_name = "swap";
3694 break;
3695 case nir_intrinsic_image_atomic_comp_swap:
3696 atomic_name = "cmpswap";
3697 break;
3698 default:
3699 abort();
3700 }
3701
3702 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3703 params[param_count++] = get_src(ctx, instr->src[3]);
3704 params[param_count++] = get_src(ctx, instr->src[2]);
3705
3706 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3707 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3708 NULL, true, true);
3709 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3710 ctx->ac.i32_0, ""); /* vindex */
3711 params[param_count++] = ctx->ac.i32_0; /* voffset */
3712 params[param_count++] = ctx->ac.i1false; /* slc */
3713
3714 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3715 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3716 } else {
3717 char coords_type[8];
3718
3719 bool da = glsl_sampler_type_is_array(type) ||
3720 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3721
3722 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3723 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3724 NULL, true, true);
3725 params[param_count++] = ctx->ac.i1false; /* r128 */
3726 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3727 params[param_count++] = ctx->ac.i1false; /* slc */
3728
3729 build_int_type_name(LLVMTypeOf(coords),
3730 coords_type, sizeof(coords_type));
3731
3732 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3733 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3734 }
3735
3736 assert(length < sizeof(intrinsic_name));
3737 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3738 }
3739
3740 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3741 const nir_intrinsic_instr *instr)
3742 {
3743 LLVMValueRef res;
3744 const nir_variable *var = instr->variables[0]->var;
3745 const struct glsl_type *type = instr->variables[0]->var->type;
3746 bool da = glsl_sampler_type_is_array(var->type) ||
3747 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3748 if(instr->variables[0]->deref.child)
3749 type = instr->variables[0]->deref.child->type;
3750
3751 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3752 return get_buffer_size(ctx,
3753 get_sampler_desc(ctx, instr->variables[0],
3754 AC_DESC_BUFFER, NULL, true, false), true);
3755
3756 struct ac_image_args args = { 0 };
3757
3758 args.da = da;
3759 args.dmask = 0xf;
3760 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3761 args.opcode = ac_image_get_resinfo;
3762 args.addr = ctx->ac.i32_0;
3763
3764 res = ac_build_image_opcode(&ctx->ac, &args);
3765
3766 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3767
3768 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3769 glsl_sampler_type_is_array(type)) {
3770 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3771 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3772 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3773 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3774 }
3775 if (ctx->ac.chip_class >= GFX9 &&
3776 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3777 glsl_sampler_type_is_array(type)) {
3778 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3779 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3780 ctx->ac.i32_1, "");
3781
3782 }
3783 return res;
3784 }
3785
3786 #define NOOP_WAITCNT 0xf7f
3787 #define LGKM_CNT 0x07f
3788 #define VM_CNT 0xf70
3789
3790 static void emit_membar(struct nir_to_llvm_context *ctx,
3791 const nir_intrinsic_instr *instr)
3792 {
3793 unsigned waitcnt = NOOP_WAITCNT;
3794
3795 switch (instr->intrinsic) {
3796 case nir_intrinsic_memory_barrier:
3797 case nir_intrinsic_group_memory_barrier:
3798 waitcnt &= VM_CNT & LGKM_CNT;
3799 break;
3800 case nir_intrinsic_memory_barrier_atomic_counter:
3801 case nir_intrinsic_memory_barrier_buffer:
3802 case nir_intrinsic_memory_barrier_image:
3803 waitcnt &= VM_CNT;
3804 break;
3805 case nir_intrinsic_memory_barrier_shared:
3806 waitcnt &= LGKM_CNT;
3807 break;
3808 default:
3809 break;
3810 }
3811 if (waitcnt != NOOP_WAITCNT)
3812 ac_build_waitcnt(&ctx->ac, waitcnt);
3813 }
3814
3815 static void emit_barrier(struct nir_to_llvm_context *ctx)
3816 {
3817 /* SI only (thanks to a hw bug workaround):
3818 * The real barrier instruction isn’t needed, because an entire patch
3819 * always fits into a single wave.
3820 */
3821 if (ctx->options->chip_class == SI &&
3822 ctx->stage == MESA_SHADER_TESS_CTRL) {
3823 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
3824 return;
3825 }
3826 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3827 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3828 }
3829
3830 static void emit_discard_if(struct ac_nir_context *ctx,
3831 const nir_intrinsic_instr *instr)
3832 {
3833 LLVMValueRef cond;
3834
3835 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3836 get_src(ctx, instr->src[0]),
3837 ctx->ac.i32_0, "");
3838 ac_build_kill_if_false(&ctx->ac, cond);
3839 }
3840
3841 static LLVMValueRef
3842 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3843 {
3844 LLVMValueRef result;
3845 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3846 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3847 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3848
3849 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3850 }
3851
3852 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3853 const nir_intrinsic_instr *instr)
3854 {
3855 LLVMValueRef ptr, result;
3856 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3857 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3858
3859 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3860 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3861 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3862 ptr, src, src1,
3863 LLVMAtomicOrderingSequentiallyConsistent,
3864 LLVMAtomicOrderingSequentiallyConsistent,
3865 false);
3866 } else {
3867 LLVMAtomicRMWBinOp op;
3868 switch (instr->intrinsic) {
3869 case nir_intrinsic_var_atomic_add:
3870 op = LLVMAtomicRMWBinOpAdd;
3871 break;
3872 case nir_intrinsic_var_atomic_umin:
3873 op = LLVMAtomicRMWBinOpUMin;
3874 break;
3875 case nir_intrinsic_var_atomic_umax:
3876 op = LLVMAtomicRMWBinOpUMax;
3877 break;
3878 case nir_intrinsic_var_atomic_imin:
3879 op = LLVMAtomicRMWBinOpMin;
3880 break;
3881 case nir_intrinsic_var_atomic_imax:
3882 op = LLVMAtomicRMWBinOpMax;
3883 break;
3884 case nir_intrinsic_var_atomic_and:
3885 op = LLVMAtomicRMWBinOpAnd;
3886 break;
3887 case nir_intrinsic_var_atomic_or:
3888 op = LLVMAtomicRMWBinOpOr;
3889 break;
3890 case nir_intrinsic_var_atomic_xor:
3891 op = LLVMAtomicRMWBinOpXor;
3892 break;
3893 case nir_intrinsic_var_atomic_exchange:
3894 op = LLVMAtomicRMWBinOpXchg;
3895 break;
3896 default:
3897 return NULL;
3898 }
3899
3900 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3901 LLVMAtomicOrderingSequentiallyConsistent,
3902 false);
3903 }
3904 return result;
3905 }
3906
3907 #define INTERP_CENTER 0
3908 #define INTERP_CENTROID 1
3909 #define INTERP_SAMPLE 2
3910
3911 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3912 enum glsl_interp_mode interp, unsigned location)
3913 {
3914 switch (interp) {
3915 case INTERP_MODE_FLAT:
3916 default:
3917 return NULL;
3918 case INTERP_MODE_SMOOTH:
3919 case INTERP_MODE_NONE:
3920 if (location == INTERP_CENTER)
3921 return ctx->persp_center;
3922 else if (location == INTERP_CENTROID)
3923 return ctx->persp_centroid;
3924 else if (location == INTERP_SAMPLE)
3925 return ctx->persp_sample;
3926 break;
3927 case INTERP_MODE_NOPERSPECTIVE:
3928 if (location == INTERP_CENTER)
3929 return ctx->linear_center;
3930 else if (location == INTERP_CENTROID)
3931 return ctx->linear_centroid;
3932 else if (location == INTERP_SAMPLE)
3933 return ctx->linear_sample;
3934 break;
3935 }
3936 return NULL;
3937 }
3938
3939 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3940 LLVMValueRef sample_id)
3941 {
3942 LLVMValueRef result;
3943 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3944
3945 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3946 const_array(ctx->ac.v2f32, 64), "");
3947
3948 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3949 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3950
3951 return result;
3952 }
3953
3954 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3955 {
3956 LLVMValueRef values[2];
3957
3958 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3959 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3960 return ac_build_gather_values(&ctx->ac, values, 2);
3961 }
3962
3963 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3964 const nir_intrinsic_instr *instr)
3965 {
3966 LLVMValueRef result[4];
3967 LLVMValueRef interp_param, attr_number;
3968 unsigned location;
3969 unsigned chan;
3970 LLVMValueRef src_c0 = NULL;
3971 LLVMValueRef src_c1 = NULL;
3972 LLVMValueRef src0 = NULL;
3973 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3974 switch (instr->intrinsic) {
3975 case nir_intrinsic_interp_var_at_centroid:
3976 location = INTERP_CENTROID;
3977 break;
3978 case nir_intrinsic_interp_var_at_sample:
3979 case nir_intrinsic_interp_var_at_offset:
3980 location = INTERP_CENTER;
3981 src0 = get_src(ctx->nir, instr->src[0]);
3982 break;
3983 default:
3984 break;
3985 }
3986
3987 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3988 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3989 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3990 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3991 LLVMValueRef sample_position;
3992 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
3993
3994 /* fetch sample ID */
3995 sample_position = load_sample_position(ctx, src0);
3996
3997 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
3998 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3999 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4000 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4001 }
4002 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4003 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4004
4005 if (location == INTERP_CENTER) {
4006 LLVMValueRef ij_out[2];
4007 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4008
4009 /*
4010 * take the I then J parameters, and the DDX/Y for it, and
4011 * calculate the IJ inputs for the interpolator.
4012 * temp1 = ddx * offset/sample.x + I;
4013 * interp_param.I = ddy * offset/sample.y + temp1;
4014 * temp1 = ddx * offset/sample.x + J;
4015 * interp_param.J = ddy * offset/sample.y + temp1;
4016 */
4017 for (unsigned i = 0; i < 2; i++) {
4018 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4019 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4020 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4021 ddxy_out, ix_ll, "");
4022 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4023 ddxy_out, iy_ll, "");
4024 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4025 interp_param, ix_ll, "");
4026 LLVMValueRef temp1, temp2;
4027
4028 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4029 ctx->ac.f32, "");
4030
4031 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4032 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4033
4034 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4035 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4036
4037 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4038 temp2, ctx->ac.i32, "");
4039 }
4040 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4041
4042 }
4043
4044 for (chan = 0; chan < 4; chan++) {
4045 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4046
4047 if (interp_param) {
4048 interp_param = LLVMBuildBitCast(ctx->builder,
4049 interp_param, ctx->ac.v2f32, "");
4050 LLVMValueRef i = LLVMBuildExtractElement(
4051 ctx->builder, interp_param, ctx->ac.i32_0, "");
4052 LLVMValueRef j = LLVMBuildExtractElement(
4053 ctx->builder, interp_param, ctx->ac.i32_1, "");
4054
4055 result[chan] = ac_build_fs_interp(&ctx->ac,
4056 llvm_chan, attr_number,
4057 ctx->prim_mask, i, j);
4058 } else {
4059 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4060 LLVMConstInt(ctx->ac.i32, 2, false),
4061 llvm_chan, attr_number,
4062 ctx->prim_mask);
4063 }
4064 }
4065 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4066 instr->variables[0]->var->data.location_frac);
4067 }
4068
4069 static void
4070 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4071 {
4072 LLVMValueRef gs_next_vertex;
4073 LLVMValueRef can_emit;
4074 int idx;
4075 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4076
4077 /* Write vertex attribute values to GSVS ring */
4078 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4079 ctx->gs_next_vertex,
4080 "");
4081
4082 /* If this thread has already emitted the declared maximum number of
4083 * vertices, kill it: excessive vertex emissions are not supposed to
4084 * have any effect, and GS threads have no externally observable
4085 * effects other than emitting vertices.
4086 */
4087 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4088 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4089 ac_build_kill_if_false(&ctx->ac, can_emit);
4090
4091 /* loop num outputs */
4092 idx = 0;
4093 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4094 LLVMValueRef *out_ptr = &addrs[i * 4];
4095 int length = 4;
4096 int slot = idx;
4097 int slot_inc = 1;
4098
4099 if (!(ctx->output_mask & (1ull << i)))
4100 continue;
4101
4102 if (i == VARYING_SLOT_CLIP_DIST0) {
4103 /* pack clip and cull into a single set of slots */
4104 length = ctx->num_output_clips + ctx->num_output_culls;
4105 if (length > 4)
4106 slot_inc = 2;
4107 }
4108 for (unsigned j = 0; j < length; j++) {
4109 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4110 out_ptr[j], "");
4111 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4112 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4113 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4114
4115 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4116
4117 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4118 out_val, 1,
4119 voffset, ctx->gs2vs_offset, 0,
4120 1, 1, true, true);
4121 }
4122 idx += slot_inc;
4123 }
4124
4125 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4126 ctx->ac.i32_1, "");
4127 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4128
4129 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4130 }
4131
4132 static void
4133 visit_end_primitive(struct nir_to_llvm_context *ctx,
4134 const nir_intrinsic_instr *instr)
4135 {
4136 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4137 }
4138
4139 static LLVMValueRef
4140 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4141 const nir_intrinsic_instr *instr)
4142 {
4143 LLVMValueRef coord[4] = {
4144 ctx->tes_u,
4145 ctx->tes_v,
4146 ctx->ac.f32_0,
4147 ctx->ac.f32_0,
4148 };
4149
4150 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4151 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4152 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4153
4154 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4155 return LLVMBuildBitCast(ctx->builder, result,
4156 get_def_type(ctx->nir, &instr->dest.ssa), "");
4157 }
4158
4159 static void visit_intrinsic(struct ac_nir_context *ctx,
4160 nir_intrinsic_instr *instr)
4161 {
4162 LLVMValueRef result = NULL;
4163
4164 switch (instr->intrinsic) {
4165 case nir_intrinsic_load_work_group_id: {
4166 LLVMValueRef values[3];
4167
4168 for (int i = 0; i < 3; i++) {
4169 values[i] = ctx->nctx->workgroup_ids[i] ?
4170 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4171 }
4172
4173 result = ac_build_gather_values(&ctx->ac, values, 3);
4174 break;
4175 }
4176 case nir_intrinsic_load_base_vertex: {
4177 result = ctx->abi->base_vertex;
4178 break;
4179 }
4180 case nir_intrinsic_load_vertex_id_zero_base: {
4181 result = ctx->abi->vertex_id;
4182 break;
4183 }
4184 case nir_intrinsic_load_local_invocation_id: {
4185 result = ctx->nctx->local_invocation_ids;
4186 break;
4187 }
4188 case nir_intrinsic_load_base_instance:
4189 result = ctx->abi->start_instance;
4190 break;
4191 case nir_intrinsic_load_draw_id:
4192 result = ctx->abi->draw_id;
4193 break;
4194 case nir_intrinsic_load_view_index:
4195 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4196 break;
4197 case nir_intrinsic_load_invocation_id:
4198 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4199 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4200 else
4201 result = ctx->abi->gs_invocation_id;
4202 break;
4203 case nir_intrinsic_load_primitive_id:
4204 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4205 if (ctx->nctx)
4206 ctx->nctx->shader_info->gs.uses_prim_id = true;
4207 result = ctx->abi->gs_prim_id;
4208 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4209 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4210 result = ctx->nctx->tcs_patch_id;
4211 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4212 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4213 result = ctx->nctx->tes_patch_id;
4214 } else
4215 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4216 break;
4217 case nir_intrinsic_load_sample_id:
4218 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4219 break;
4220 case nir_intrinsic_load_sample_pos:
4221 result = load_sample_pos(ctx);
4222 break;
4223 case nir_intrinsic_load_sample_mask_in:
4224 result = ctx->abi->sample_coverage;
4225 break;
4226 case nir_intrinsic_load_frag_coord: {
4227 LLVMValueRef values[4] = {
4228 ctx->abi->frag_pos[0],
4229 ctx->abi->frag_pos[1],
4230 ctx->abi->frag_pos[2],
4231 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4232 };
4233 result = ac_build_gather_values(&ctx->ac, values, 4);
4234 break;
4235 }
4236 case nir_intrinsic_load_front_face:
4237 result = ctx->abi->front_face;
4238 break;
4239 case nir_intrinsic_load_instance_id:
4240 result = ctx->abi->instance_id;
4241 break;
4242 case nir_intrinsic_load_num_work_groups:
4243 result = ctx->nctx->num_work_groups;
4244 break;
4245 case nir_intrinsic_load_local_invocation_index:
4246 result = visit_load_local_invocation_index(ctx->nctx);
4247 break;
4248 case nir_intrinsic_load_push_constant:
4249 result = visit_load_push_constant(ctx->nctx, instr);
4250 break;
4251 case nir_intrinsic_vulkan_resource_index:
4252 result = visit_vulkan_resource_index(ctx->nctx, instr);
4253 break;
4254 case nir_intrinsic_vulkan_resource_reindex:
4255 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4256 break;
4257 case nir_intrinsic_store_ssbo:
4258 visit_store_ssbo(ctx, instr);
4259 break;
4260 case nir_intrinsic_load_ssbo:
4261 result = visit_load_buffer(ctx, instr);
4262 break;
4263 case nir_intrinsic_ssbo_atomic_add:
4264 case nir_intrinsic_ssbo_atomic_imin:
4265 case nir_intrinsic_ssbo_atomic_umin:
4266 case nir_intrinsic_ssbo_atomic_imax:
4267 case nir_intrinsic_ssbo_atomic_umax:
4268 case nir_intrinsic_ssbo_atomic_and:
4269 case nir_intrinsic_ssbo_atomic_or:
4270 case nir_intrinsic_ssbo_atomic_xor:
4271 case nir_intrinsic_ssbo_atomic_exchange:
4272 case nir_intrinsic_ssbo_atomic_comp_swap:
4273 result = visit_atomic_ssbo(ctx, instr);
4274 break;
4275 case nir_intrinsic_load_ubo:
4276 result = visit_load_ubo_buffer(ctx, instr);
4277 break;
4278 case nir_intrinsic_get_buffer_size:
4279 result = visit_get_buffer_size(ctx, instr);
4280 break;
4281 case nir_intrinsic_load_var:
4282 result = visit_load_var(ctx, instr);
4283 break;
4284 case nir_intrinsic_store_var:
4285 visit_store_var(ctx, instr);
4286 break;
4287 case nir_intrinsic_image_load:
4288 result = visit_image_load(ctx, instr);
4289 break;
4290 case nir_intrinsic_image_store:
4291 visit_image_store(ctx, instr);
4292 break;
4293 case nir_intrinsic_image_atomic_add:
4294 case nir_intrinsic_image_atomic_min:
4295 case nir_intrinsic_image_atomic_max:
4296 case nir_intrinsic_image_atomic_and:
4297 case nir_intrinsic_image_atomic_or:
4298 case nir_intrinsic_image_atomic_xor:
4299 case nir_intrinsic_image_atomic_exchange:
4300 case nir_intrinsic_image_atomic_comp_swap:
4301 result = visit_image_atomic(ctx, instr);
4302 break;
4303 case nir_intrinsic_image_size:
4304 result = visit_image_size(ctx, instr);
4305 break;
4306 case nir_intrinsic_discard:
4307 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4308 LLVMVoidTypeInContext(ctx->ac.context),
4309 NULL, 0, AC_FUNC_ATTR_LEGACY);
4310 break;
4311 case nir_intrinsic_discard_if:
4312 emit_discard_if(ctx, instr);
4313 break;
4314 case nir_intrinsic_memory_barrier:
4315 case nir_intrinsic_group_memory_barrier:
4316 case nir_intrinsic_memory_barrier_atomic_counter:
4317 case nir_intrinsic_memory_barrier_buffer:
4318 case nir_intrinsic_memory_barrier_image:
4319 case nir_intrinsic_memory_barrier_shared:
4320 emit_membar(ctx->nctx, instr);
4321 break;
4322 case nir_intrinsic_barrier:
4323 emit_barrier(ctx->nctx);
4324 break;
4325 case nir_intrinsic_var_atomic_add:
4326 case nir_intrinsic_var_atomic_imin:
4327 case nir_intrinsic_var_atomic_umin:
4328 case nir_intrinsic_var_atomic_imax:
4329 case nir_intrinsic_var_atomic_umax:
4330 case nir_intrinsic_var_atomic_and:
4331 case nir_intrinsic_var_atomic_or:
4332 case nir_intrinsic_var_atomic_xor:
4333 case nir_intrinsic_var_atomic_exchange:
4334 case nir_intrinsic_var_atomic_comp_swap:
4335 result = visit_var_atomic(ctx->nctx, instr);
4336 break;
4337 case nir_intrinsic_interp_var_at_centroid:
4338 case nir_intrinsic_interp_var_at_sample:
4339 case nir_intrinsic_interp_var_at_offset:
4340 result = visit_interp(ctx->nctx, instr);
4341 break;
4342 case nir_intrinsic_emit_vertex:
4343 assert(instr->const_index[0] == 0);
4344 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4345 break;
4346 case nir_intrinsic_end_primitive:
4347 visit_end_primitive(ctx->nctx, instr);
4348 break;
4349 case nir_intrinsic_load_tess_coord:
4350 result = visit_load_tess_coord(ctx->nctx, instr);
4351 break;
4352 case nir_intrinsic_load_patch_vertices_in:
4353 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4354 break;
4355 default:
4356 fprintf(stderr, "Unknown intrinsic: ");
4357 nir_print_instr(&instr->instr, stderr);
4358 fprintf(stderr, "\n");
4359 break;
4360 }
4361 if (result) {
4362 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4363 }
4364 }
4365
4366 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4367 LLVMValueRef buffer_ptr, bool write)
4368 {
4369 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4370
4371 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4372 ctx->shader_info->fs.writes_memory = true;
4373
4374 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4375 }
4376
4377 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4378 {
4379 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4380
4381 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4382 }
4383
4384 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4385 unsigned descriptor_set,
4386 unsigned base_index,
4387 unsigned constant_index,
4388 LLVMValueRef index,
4389 enum ac_descriptor_type desc_type,
4390 bool image, bool write)
4391 {
4392 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4393 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4394 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4395 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4396 unsigned offset = binding->offset;
4397 unsigned stride = binding->size;
4398 unsigned type_size;
4399 LLVMBuilderRef builder = ctx->builder;
4400 LLVMTypeRef type;
4401
4402 assert(base_index < layout->binding_count);
4403
4404 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4405 ctx->shader_info->fs.writes_memory = true;
4406
4407 switch (desc_type) {
4408 case AC_DESC_IMAGE:
4409 type = ctx->ac.v8i32;
4410 type_size = 32;
4411 break;
4412 case AC_DESC_FMASK:
4413 type = ctx->ac.v8i32;
4414 offset += 32;
4415 type_size = 32;
4416 break;
4417 case AC_DESC_SAMPLER:
4418 type = ctx->ac.v4i32;
4419 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4420 offset += 64;
4421
4422 type_size = 16;
4423 break;
4424 case AC_DESC_BUFFER:
4425 type = ctx->ac.v4i32;
4426 type_size = 16;
4427 break;
4428 default:
4429 unreachable("invalid desc_type\n");
4430 }
4431
4432 offset += constant_index * stride;
4433
4434 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4435 (!index || binding->immutable_samplers_equal)) {
4436 if (binding->immutable_samplers_equal)
4437 constant_index = 0;
4438
4439 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4440
4441 LLVMValueRef constants[] = {
4442 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4443 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4444 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4445 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4446 };
4447 return ac_build_gather_values(&ctx->ac, constants, 4);
4448 }
4449
4450 assert(stride % type_size == 0);
4451
4452 if (!index)
4453 index = ctx->ac.i32_0;
4454
4455 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4456
4457 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4458 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4459
4460 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4461 }
4462
4463 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4464 const nir_deref_var *deref,
4465 enum ac_descriptor_type desc_type,
4466 const nir_tex_instr *tex_instr,
4467 bool image, bool write)
4468 {
4469 LLVMValueRef index = NULL;
4470 unsigned constant_index = 0;
4471 unsigned descriptor_set;
4472 unsigned base_index;
4473
4474 if (!deref) {
4475 assert(tex_instr && !image);
4476 descriptor_set = 0;
4477 base_index = tex_instr->sampler_index;
4478 } else {
4479 const nir_deref *tail = &deref->deref;
4480 while (tail->child) {
4481 const nir_deref_array *child = nir_deref_as_array(tail->child);
4482 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4483
4484 if (!array_size)
4485 array_size = 1;
4486
4487 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4488
4489 if (child->deref_array_type == nir_deref_array_type_indirect) {
4490 LLVMValueRef indirect = get_src(ctx, child->indirect);
4491
4492 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4493 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4494
4495 if (!index)
4496 index = indirect;
4497 else
4498 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4499 }
4500
4501 constant_index += child->base_offset * array_size;
4502
4503 tail = &child->deref;
4504 }
4505 descriptor_set = deref->var->data.descriptor_set;
4506 base_index = deref->var->data.binding;
4507 }
4508
4509 return ctx->abi->load_sampler_desc(ctx->abi,
4510 descriptor_set,
4511 base_index,
4512 constant_index, index,
4513 desc_type, image, write);
4514 }
4515
4516 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4517 struct ac_image_args *args,
4518 const nir_tex_instr *instr,
4519 nir_texop op,
4520 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4521 LLVMValueRef *param, unsigned count,
4522 unsigned dmask)
4523 {
4524 unsigned is_rect = 0;
4525 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4526
4527 if (op == nir_texop_lod)
4528 da = false;
4529 /* Pad to power of two vector */
4530 while (count < util_next_power_of_two(count))
4531 param[count++] = LLVMGetUndef(ctx->i32);
4532
4533 if (count > 1)
4534 args->addr = ac_build_gather_values(ctx, param, count);
4535 else
4536 args->addr = param[0];
4537
4538 args->resource = res_ptr;
4539 args->sampler = samp_ptr;
4540
4541 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4542 args->addr = param[0];
4543 return;
4544 }
4545
4546 args->dmask = dmask;
4547 args->unorm = is_rect;
4548 args->da = da;
4549 }
4550
4551 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4552 *
4553 * SI-CI:
4554 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4555 * filtering manually. The driver sets img7 to a mask clearing
4556 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4557 * s_and_b32 samp0, samp0, img7
4558 *
4559 * VI:
4560 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4561 */
4562 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4563 LLVMValueRef res, LLVMValueRef samp)
4564 {
4565 LLVMBuilderRef builder = ctx->ac.builder;
4566 LLVMValueRef img7, samp0;
4567
4568 if (ctx->ac.chip_class >= VI)
4569 return samp;
4570
4571 img7 = LLVMBuildExtractElement(builder, res,
4572 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4573 samp0 = LLVMBuildExtractElement(builder, samp,
4574 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4575 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4576 return LLVMBuildInsertElement(builder, samp, samp0,
4577 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4578 }
4579
4580 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4581 nir_tex_instr *instr,
4582 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4583 LLVMValueRef *fmask_ptr)
4584 {
4585 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4586 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4587 else
4588 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4589 if (samp_ptr) {
4590 if (instr->sampler)
4591 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4592 else
4593 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4594 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4595 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4596 }
4597 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4598 instr->op == nir_texop_samples_identical))
4599 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4600 }
4601
4602 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4603 LLVMValueRef coord)
4604 {
4605 coord = ac_to_float(ctx, coord);
4606 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4607 coord = ac_to_integer(ctx, coord);
4608 return coord;
4609 }
4610
4611 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4612 {
4613 LLVMValueRef result = NULL;
4614 struct ac_image_args args = { 0 };
4615 unsigned dmask = 0xf;
4616 LLVMValueRef address[16];
4617 LLVMValueRef coords[5];
4618 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4619 LLVMValueRef bias = NULL, offsets = NULL;
4620 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4621 LLVMValueRef ddx = NULL, ddy = NULL;
4622 LLVMValueRef derivs[6];
4623 unsigned chan, count = 0;
4624 unsigned const_src = 0, num_deriv_comp = 0;
4625 bool lod_is_zero = false;
4626
4627 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4628
4629 for (unsigned i = 0; i < instr->num_srcs; i++) {
4630 switch (instr->src[i].src_type) {
4631 case nir_tex_src_coord:
4632 coord = get_src(ctx, instr->src[i].src);
4633 break;
4634 case nir_tex_src_projector:
4635 break;
4636 case nir_tex_src_comparator:
4637 comparator = get_src(ctx, instr->src[i].src);
4638 break;
4639 case nir_tex_src_offset:
4640 offsets = get_src(ctx, instr->src[i].src);
4641 const_src = i;
4642 break;
4643 case nir_tex_src_bias:
4644 bias = get_src(ctx, instr->src[i].src);
4645 break;
4646 case nir_tex_src_lod: {
4647 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4648
4649 if (val && val->i32[0] == 0)
4650 lod_is_zero = true;
4651 lod = get_src(ctx, instr->src[i].src);
4652 break;
4653 }
4654 case nir_tex_src_ms_index:
4655 sample_index = get_src(ctx, instr->src[i].src);
4656 break;
4657 case nir_tex_src_ms_mcs:
4658 break;
4659 case nir_tex_src_ddx:
4660 ddx = get_src(ctx, instr->src[i].src);
4661 num_deriv_comp = instr->src[i].src.ssa->num_components;
4662 break;
4663 case nir_tex_src_ddy:
4664 ddy = get_src(ctx, instr->src[i].src);
4665 break;
4666 case nir_tex_src_texture_offset:
4667 case nir_tex_src_sampler_offset:
4668 case nir_tex_src_plane:
4669 default:
4670 break;
4671 }
4672 }
4673
4674 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4675 result = get_buffer_size(ctx, res_ptr, true);
4676 goto write_result;
4677 }
4678
4679 if (instr->op == nir_texop_texture_samples) {
4680 LLVMValueRef res, samples, is_msaa;
4681 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4682 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4683 LLVMConstInt(ctx->ac.i32, 3, false), "");
4684 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4685 LLVMConstInt(ctx->ac.i32, 28, false), "");
4686 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4687 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4688 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4689 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4690
4691 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4692 LLVMConstInt(ctx->ac.i32, 16, false), "");
4693 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4694 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4695 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4696 samples, "");
4697 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4698 ctx->ac.i32_1, "");
4699 result = samples;
4700 goto write_result;
4701 }
4702
4703 if (coord)
4704 for (chan = 0; chan < instr->coord_components; chan++)
4705 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4706
4707 if (offsets && instr->op != nir_texop_txf) {
4708 LLVMValueRef offset[3], pack;
4709 for (chan = 0; chan < 3; ++chan)
4710 offset[chan] = ctx->ac.i32_0;
4711
4712 args.offset = true;
4713 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4714 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4715 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4716 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4717 if (chan)
4718 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4719 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4720 }
4721 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4722 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4723 address[count++] = pack;
4724
4725 }
4726 /* pack LOD bias value */
4727 if (instr->op == nir_texop_txb && bias) {
4728 address[count++] = bias;
4729 }
4730
4731 /* Pack depth comparison value */
4732 if (instr->is_shadow && comparator) {
4733 LLVMValueRef z = ac_to_float(&ctx->ac,
4734 llvm_extract_elem(&ctx->ac, comparator, 0));
4735
4736 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4737 * so the depth comparison value isn't clamped for Z16 and
4738 * Z24 anymore. Do it manually here.
4739 *
4740 * It's unnecessary if the original texture format was
4741 * Z32_FLOAT, but we don't know that here.
4742 */
4743 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4744 z = ac_build_clamp(&ctx->ac, z);
4745
4746 address[count++] = z;
4747 }
4748
4749 /* pack derivatives */
4750 if (ddx || ddy) {
4751 int num_src_deriv_channels, num_dest_deriv_channels;
4752 switch (instr->sampler_dim) {
4753 case GLSL_SAMPLER_DIM_3D:
4754 case GLSL_SAMPLER_DIM_CUBE:
4755 num_deriv_comp = 3;
4756 num_src_deriv_channels = 3;
4757 num_dest_deriv_channels = 3;
4758 break;
4759 case GLSL_SAMPLER_DIM_2D:
4760 default:
4761 num_src_deriv_channels = 2;
4762 num_dest_deriv_channels = 2;
4763 num_deriv_comp = 2;
4764 break;
4765 case GLSL_SAMPLER_DIM_1D:
4766 num_src_deriv_channels = 1;
4767 if (ctx->ac.chip_class >= GFX9) {
4768 num_dest_deriv_channels = 2;
4769 num_deriv_comp = 2;
4770 } else {
4771 num_dest_deriv_channels = 1;
4772 num_deriv_comp = 1;
4773 }
4774 break;
4775 }
4776
4777 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4778 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4779 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4780 }
4781 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4782 derivs[i] = ctx->ac.f32_0;
4783 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4784 }
4785 }
4786
4787 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4788 for (chan = 0; chan < instr->coord_components; chan++)
4789 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4790 if (instr->coord_components == 3)
4791 coords[3] = LLVMGetUndef(ctx->ac.f32);
4792 ac_prepare_cube_coords(&ctx->ac,
4793 instr->op == nir_texop_txd, instr->is_array,
4794 instr->op == nir_texop_lod, coords, derivs);
4795 if (num_deriv_comp)
4796 num_deriv_comp--;
4797 }
4798
4799 if (ddx || ddy) {
4800 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4801 address[count++] = derivs[i];
4802 }
4803
4804 /* Pack texture coordinates */
4805 if (coord) {
4806 address[count++] = coords[0];
4807 if (instr->coord_components > 1) {
4808 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4809 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4810 }
4811 address[count++] = coords[1];
4812 }
4813 if (instr->coord_components > 2) {
4814 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4815 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4816 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4817 instr->op != nir_texop_txf) {
4818 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4819 }
4820 address[count++] = coords[2];
4821 }
4822
4823 if (ctx->ac.chip_class >= GFX9) {
4824 LLVMValueRef filler;
4825 if (instr->op == nir_texop_txf)
4826 filler = ctx->ac.i32_0;
4827 else
4828 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4829
4830 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4831 /* No nir_texop_lod, because it does not take a slice
4832 * even with array textures. */
4833 if (instr->is_array && instr->op != nir_texop_lod ) {
4834 address[count] = address[count - 1];
4835 address[count - 1] = filler;
4836 count++;
4837 } else
4838 address[count++] = filler;
4839 }
4840 }
4841 }
4842
4843 /* Pack LOD */
4844 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4845 instr->op == nir_texop_txf)) {
4846 address[count++] = lod;
4847 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4848 address[count++] = sample_index;
4849 } else if(instr->op == nir_texop_txs) {
4850 count = 0;
4851 if (lod)
4852 address[count++] = lod;
4853 else
4854 address[count++] = ctx->ac.i32_0;
4855 }
4856
4857 for (chan = 0; chan < count; chan++) {
4858 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4859 address[chan], ctx->ac.i32, "");
4860 }
4861
4862 if (instr->op == nir_texop_samples_identical) {
4863 LLVMValueRef txf_address[4];
4864 struct ac_image_args txf_args = { 0 };
4865 unsigned txf_count = count;
4866 memcpy(txf_address, address, sizeof(txf_address));
4867
4868 if (!instr->is_array)
4869 txf_address[2] = ctx->ac.i32_0;
4870 txf_address[3] = ctx->ac.i32_0;
4871
4872 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4873 fmask_ptr, NULL,
4874 txf_address, txf_count, 0xf);
4875
4876 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4877
4878 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4879 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4880 goto write_result;
4881 }
4882
4883 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4884 instr->op != nir_texop_txs) {
4885 unsigned sample_chan = instr->is_array ? 3 : 2;
4886 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4887 address[0],
4888 address[1],
4889 instr->is_array ? address[2] : NULL,
4890 address[sample_chan],
4891 fmask_ptr);
4892 }
4893
4894 if (offsets && instr->op == nir_texop_txf) {
4895 nir_const_value *const_offset =
4896 nir_src_as_const_value(instr->src[const_src].src);
4897 int num_offsets = instr->src[const_src].src.ssa->num_components;
4898 assert(const_offset);
4899 num_offsets = MIN2(num_offsets, instr->coord_components);
4900 if (num_offsets > 2)
4901 address[2] = LLVMBuildAdd(ctx->ac.builder,
4902 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4903 if (num_offsets > 1)
4904 address[1] = LLVMBuildAdd(ctx->ac.builder,
4905 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4906 address[0] = LLVMBuildAdd(ctx->ac.builder,
4907 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4908
4909 }
4910
4911 /* TODO TG4 support */
4912 if (instr->op == nir_texop_tg4) {
4913 if (instr->is_shadow)
4914 dmask = 1;
4915 else
4916 dmask = 1 << instr->component;
4917 }
4918 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4919 res_ptr, samp_ptr, address, count, dmask);
4920
4921 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4922
4923 if (instr->op == nir_texop_query_levels)
4924 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4925 else if (instr->is_shadow && instr->is_new_style_shadow &&
4926 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4927 instr->op != nir_texop_tg4)
4928 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4929 else if (instr->op == nir_texop_txs &&
4930 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4931 instr->is_array) {
4932 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4933 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4934 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4935 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4936 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4937 } else if (ctx->ac.chip_class >= GFX9 &&
4938 instr->op == nir_texop_txs &&
4939 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4940 instr->is_array) {
4941 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4942 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4943 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4944 ctx->ac.i32_1, "");
4945 } else if (instr->dest.ssa.num_components != 4)
4946 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4947
4948 write_result:
4949 if (result) {
4950 assert(instr->dest.is_ssa);
4951 result = ac_to_integer(&ctx->ac, result);
4952 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4953 }
4954 }
4955
4956
4957 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4958 {
4959 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4960 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4961
4962 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4963 _mesa_hash_table_insert(ctx->phis, instr, result);
4964 }
4965
4966 static void visit_post_phi(struct ac_nir_context *ctx,
4967 nir_phi_instr *instr,
4968 LLVMValueRef llvm_phi)
4969 {
4970 nir_foreach_phi_src(src, instr) {
4971 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4972 LLVMValueRef llvm_src = get_src(ctx, src->src);
4973
4974 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4975 }
4976 }
4977
4978 static void phi_post_pass(struct ac_nir_context *ctx)
4979 {
4980 struct hash_entry *entry;
4981 hash_table_foreach(ctx->phis, entry) {
4982 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4983 (LLVMValueRef)entry->data);
4984 }
4985 }
4986
4987
4988 static void visit_ssa_undef(struct ac_nir_context *ctx,
4989 const nir_ssa_undef_instr *instr)
4990 {
4991 unsigned num_components = instr->def.num_components;
4992 LLVMValueRef undef;
4993
4994 if (num_components == 1)
4995 undef = LLVMGetUndef(ctx->ac.i32);
4996 else {
4997 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4998 }
4999 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5000 }
5001
5002 static void visit_jump(struct ac_nir_context *ctx,
5003 const nir_jump_instr *instr)
5004 {
5005 switch (instr->type) {
5006 case nir_jump_break:
5007 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5008 LLVMClearInsertionPosition(ctx->ac.builder);
5009 break;
5010 case nir_jump_continue:
5011 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5012 LLVMClearInsertionPosition(ctx->ac.builder);
5013 break;
5014 default:
5015 fprintf(stderr, "Unknown NIR jump instr: ");
5016 nir_print_instr(&instr->instr, stderr);
5017 fprintf(stderr, "\n");
5018 abort();
5019 }
5020 }
5021
5022 static void visit_cf_list(struct ac_nir_context *ctx,
5023 struct exec_list *list);
5024
5025 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5026 {
5027 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5028 nir_foreach_instr(instr, block)
5029 {
5030 switch (instr->type) {
5031 case nir_instr_type_alu:
5032 visit_alu(ctx, nir_instr_as_alu(instr));
5033 break;
5034 case nir_instr_type_load_const:
5035 visit_load_const(ctx, nir_instr_as_load_const(instr));
5036 break;
5037 case nir_instr_type_intrinsic:
5038 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5039 break;
5040 case nir_instr_type_tex:
5041 visit_tex(ctx, nir_instr_as_tex(instr));
5042 break;
5043 case nir_instr_type_phi:
5044 visit_phi(ctx, nir_instr_as_phi(instr));
5045 break;
5046 case nir_instr_type_ssa_undef:
5047 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5048 break;
5049 case nir_instr_type_jump:
5050 visit_jump(ctx, nir_instr_as_jump(instr));
5051 break;
5052 default:
5053 fprintf(stderr, "Unknown NIR instr type: ");
5054 nir_print_instr(instr, stderr);
5055 fprintf(stderr, "\n");
5056 abort();
5057 }
5058 }
5059
5060 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5061 }
5062
5063 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5064 {
5065 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5066
5067 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5068 LLVMBasicBlockRef merge_block =
5069 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5070 LLVMBasicBlockRef if_block =
5071 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5072 LLVMBasicBlockRef else_block = merge_block;
5073 if (!exec_list_is_empty(&if_stmt->else_list))
5074 else_block = LLVMAppendBasicBlockInContext(
5075 ctx->ac.context, fn, "");
5076
5077 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5078 ctx->ac.i32_0, "");
5079 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5080
5081 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5082 visit_cf_list(ctx, &if_stmt->then_list);
5083 if (LLVMGetInsertBlock(ctx->ac.builder))
5084 LLVMBuildBr(ctx->ac.builder, merge_block);
5085
5086 if (!exec_list_is_empty(&if_stmt->else_list)) {
5087 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5088 visit_cf_list(ctx, &if_stmt->else_list);
5089 if (LLVMGetInsertBlock(ctx->ac.builder))
5090 LLVMBuildBr(ctx->ac.builder, merge_block);
5091 }
5092
5093 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5094 }
5095
5096 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5097 {
5098 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5099 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5100 LLVMBasicBlockRef break_parent = ctx->break_block;
5101
5102 ctx->continue_block =
5103 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5104 ctx->break_block =
5105 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5106
5107 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5108 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5109 visit_cf_list(ctx, &loop->body);
5110
5111 if (LLVMGetInsertBlock(ctx->ac.builder))
5112 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5113 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5114
5115 ctx->continue_block = continue_parent;
5116 ctx->break_block = break_parent;
5117 }
5118
5119 static void visit_cf_list(struct ac_nir_context *ctx,
5120 struct exec_list *list)
5121 {
5122 foreach_list_typed(nir_cf_node, node, node, list)
5123 {
5124 switch (node->type) {
5125 case nir_cf_node_block:
5126 visit_block(ctx, nir_cf_node_as_block(node));
5127 break;
5128
5129 case nir_cf_node_if:
5130 visit_if(ctx, nir_cf_node_as_if(node));
5131 break;
5132
5133 case nir_cf_node_loop:
5134 visit_loop(ctx, nir_cf_node_as_loop(node));
5135 break;
5136
5137 default:
5138 assert(0);
5139 }
5140 }
5141 }
5142
5143 static void
5144 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5145 struct nir_variable *variable)
5146 {
5147 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5148 LLVMValueRef t_offset;
5149 LLVMValueRef t_list;
5150 LLVMValueRef input;
5151 LLVMValueRef buffer_index;
5152 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5153 int idx = variable->data.location;
5154 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5155
5156 variable->data.driver_location = idx * 4;
5157
5158 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5159 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5160 ctx->abi.start_instance, "");
5161 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5162 ctx->shader_info->vs.vgpr_comp_cnt);
5163 } else
5164 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5165 ctx->abi.base_vertex, "");
5166
5167 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5168 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5169
5170 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5171
5172 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5173 buffer_index,
5174 ctx->ac.i32_0,
5175 true);
5176
5177 for (unsigned chan = 0; chan < 4; chan++) {
5178 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5179 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5180 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5181 input, llvm_chan, ""));
5182 }
5183 }
5184 }
5185
5186 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5187 unsigned attr,
5188 LLVMValueRef interp_param,
5189 LLVMValueRef prim_mask,
5190 LLVMValueRef result[4])
5191 {
5192 LLVMValueRef attr_number;
5193 unsigned chan;
5194 LLVMValueRef i, j;
5195 bool interp = interp_param != NULL;
5196
5197 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5198
5199 /* fs.constant returns the param from the middle vertex, so it's not
5200 * really useful for flat shading. It's meant to be used for custom
5201 * interpolation (but the intrinsic can't fetch from the other two
5202 * vertices).
5203 *
5204 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5205 * to do the right thing. The only reason we use fs.constant is that
5206 * fs.interp cannot be used on integers, because they can be equal
5207 * to NaN.
5208 */
5209 if (interp) {
5210 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5211 ctx->ac.v2f32, "");
5212
5213 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5214 ctx->ac.i32_0, "");
5215 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5216 ctx->ac.i32_1, "");
5217 }
5218
5219 for (chan = 0; chan < 4; chan++) {
5220 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5221
5222 if (interp) {
5223 result[chan] = ac_build_fs_interp(&ctx->ac,
5224 llvm_chan,
5225 attr_number,
5226 prim_mask, i, j);
5227 } else {
5228 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5229 LLVMConstInt(ctx->ac.i32, 2, false),
5230 llvm_chan,
5231 attr_number,
5232 prim_mask);
5233 }
5234 }
5235 }
5236
5237 static void
5238 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5239 struct nir_variable *variable)
5240 {
5241 int idx = variable->data.location;
5242 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5243 LLVMValueRef interp;
5244
5245 variable->data.driver_location = idx * 4;
5246 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5247
5248 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5249 unsigned interp_type;
5250 if (variable->data.sample) {
5251 interp_type = INTERP_SAMPLE;
5252 ctx->shader_info->info.ps.force_persample = true;
5253 } else if (variable->data.centroid)
5254 interp_type = INTERP_CENTROID;
5255 else
5256 interp_type = INTERP_CENTER;
5257
5258 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5259 } else
5260 interp = NULL;
5261
5262 for (unsigned i = 0; i < attrib_count; ++i)
5263 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5264
5265 }
5266
5267 static void
5268 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5269 struct nir_shader *nir) {
5270 nir_foreach_variable(variable, &nir->inputs)
5271 handle_vs_input_decl(ctx, variable);
5272 }
5273
5274 static void
5275 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5276 struct nir_shader *nir)
5277 {
5278 if (!ctx->options->key.fs.multisample)
5279 return;
5280
5281 bool uses_center = false;
5282 bool uses_centroid = false;
5283 nir_foreach_variable(variable, &nir->inputs) {
5284 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5285 variable->data.sample)
5286 continue;
5287
5288 if (variable->data.centroid)
5289 uses_centroid = true;
5290 else
5291 uses_center = true;
5292 }
5293
5294 if (uses_center && uses_centroid) {
5295 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5296 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5297 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5298 }
5299 }
5300
5301 static void
5302 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5303 struct nir_shader *nir)
5304 {
5305 prepare_interp_optimize(ctx, nir);
5306
5307 nir_foreach_variable(variable, &nir->inputs)
5308 handle_fs_input_decl(ctx, variable);
5309
5310 unsigned index = 0;
5311
5312 if (ctx->shader_info->info.ps.uses_input_attachments ||
5313 ctx->shader_info->info.needs_multiview_view_index)
5314 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5315
5316 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5317 LLVMValueRef interp_param;
5318 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5319
5320 if (!(ctx->input_mask & (1ull << i)))
5321 continue;
5322
5323 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5324 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5325 interp_param = *inputs;
5326 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5327 inputs);
5328
5329 if (!interp_param)
5330 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5331 ++index;
5332 } else if (i == VARYING_SLOT_POS) {
5333 for(int i = 0; i < 3; ++i)
5334 inputs[i] = ctx->abi.frag_pos[i];
5335
5336 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5337 ctx->abi.frag_pos[3]);
5338 }
5339 }
5340 ctx->shader_info->fs.num_interp = index;
5341 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5342 ctx->shader_info->fs.has_pcoord = true;
5343 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5344 ctx->shader_info->fs.prim_id_input = true;
5345 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5346 ctx->shader_info->fs.layer_input = true;
5347 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5348
5349 if (ctx->shader_info->info.needs_multiview_view_index)
5350 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5351 }
5352
5353 static LLVMValueRef
5354 ac_build_alloca(struct ac_llvm_context *ac,
5355 LLVMTypeRef type,
5356 const char *name)
5357 {
5358 LLVMBuilderRef builder = ac->builder;
5359 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5360 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5361 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5362 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5363 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5364 LLVMValueRef res;
5365
5366 if (first_instr) {
5367 LLVMPositionBuilderBefore(first_builder, first_instr);
5368 } else {
5369 LLVMPositionBuilderAtEnd(first_builder, first_block);
5370 }
5371
5372 res = LLVMBuildAlloca(first_builder, type, name);
5373 LLVMBuildStore(builder, LLVMConstNull(type), res);
5374
5375 LLVMDisposeBuilder(first_builder);
5376
5377 return res;
5378 }
5379
5380 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5381 LLVMTypeRef type,
5382 const char *name)
5383 {
5384 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5385 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5386 return ptr;
5387 }
5388
5389 static void
5390 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5391 struct nir_variable *variable,
5392 struct nir_shader *shader,
5393 gl_shader_stage stage)
5394 {
5395 int idx = variable->data.location + variable->data.index;
5396 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5397 uint64_t mask_attribs;
5398
5399 variable->data.driver_location = idx * 4;
5400
5401 /* tess ctrl has it's own load/store paths for outputs */
5402 if (stage == MESA_SHADER_TESS_CTRL)
5403 return;
5404
5405 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5406 if (stage == MESA_SHADER_VERTEX ||
5407 stage == MESA_SHADER_TESS_EVAL ||
5408 stage == MESA_SHADER_GEOMETRY) {
5409 if (idx == VARYING_SLOT_CLIP_DIST0) {
5410 int length = shader->info.clip_distance_array_size +
5411 shader->info.cull_distance_array_size;
5412 if (stage == MESA_SHADER_VERTEX) {
5413 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5414 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5415 }
5416 if (stage == MESA_SHADER_TESS_EVAL) {
5417 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5418 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5419 }
5420
5421 if (length > 4)
5422 attrib_count = 2;
5423 else
5424 attrib_count = 1;
5425 mask_attribs = 1ull << idx;
5426 }
5427 }
5428
5429 ctx->output_mask |= mask_attribs;
5430 }
5431
5432 static void
5433 handle_shader_output_decl(struct ac_nir_context *ctx,
5434 struct nir_shader *nir,
5435 struct nir_variable *variable)
5436 {
5437 unsigned output_loc = variable->data.driver_location / 4;
5438 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5439
5440 /* tess ctrl has it's own load/store paths for outputs */
5441 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5442 return;
5443
5444 if (ctx->stage == MESA_SHADER_VERTEX ||
5445 ctx->stage == MESA_SHADER_TESS_EVAL ||
5446 ctx->stage == MESA_SHADER_GEOMETRY) {
5447 int idx = variable->data.location + variable->data.index;
5448 if (idx == VARYING_SLOT_CLIP_DIST0) {
5449 int length = nir->info.clip_distance_array_size +
5450 nir->info.cull_distance_array_size;
5451
5452 if (length > 4)
5453 attrib_count = 2;
5454 else
5455 attrib_count = 1;
5456 }
5457 }
5458
5459 for (unsigned i = 0; i < attrib_count; ++i) {
5460 for (unsigned chan = 0; chan < 4; chan++) {
5461 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5462 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5463 }
5464 }
5465 }
5466
5467 static LLVMTypeRef
5468 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5469 enum glsl_base_type type)
5470 {
5471 switch (type) {
5472 case GLSL_TYPE_INT:
5473 case GLSL_TYPE_UINT:
5474 case GLSL_TYPE_BOOL:
5475 case GLSL_TYPE_SUBROUTINE:
5476 return ctx->ac.i32;
5477 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5478 return ctx->ac.f32;
5479 case GLSL_TYPE_INT64:
5480 case GLSL_TYPE_UINT64:
5481 return ctx->ac.i64;
5482 case GLSL_TYPE_DOUBLE:
5483 return ctx->ac.f64;
5484 default:
5485 unreachable("unknown GLSL type");
5486 }
5487 }
5488
5489 static LLVMTypeRef
5490 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5491 const struct glsl_type *type)
5492 {
5493 if (glsl_type_is_scalar(type)) {
5494 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5495 }
5496
5497 if (glsl_type_is_vector(type)) {
5498 return LLVMVectorType(
5499 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5500 glsl_get_vector_elements(type));
5501 }
5502
5503 if (glsl_type_is_matrix(type)) {
5504 return LLVMArrayType(
5505 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5506 glsl_get_matrix_columns(type));
5507 }
5508
5509 if (glsl_type_is_array(type)) {
5510 return LLVMArrayType(
5511 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5512 glsl_get_length(type));
5513 }
5514
5515 assert(glsl_type_is_struct(type));
5516
5517 LLVMTypeRef member_types[glsl_get_length(type)];
5518
5519 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5520 member_types[i] =
5521 glsl_to_llvm_type(ctx,
5522 glsl_get_struct_field(type, i));
5523 }
5524
5525 return LLVMStructTypeInContext(ctx->context, member_types,
5526 glsl_get_length(type), false);
5527 }
5528
5529 static void
5530 setup_locals(struct ac_nir_context *ctx,
5531 struct nir_function *func)
5532 {
5533 int i, j;
5534 ctx->num_locals = 0;
5535 nir_foreach_variable(variable, &func->impl->locals) {
5536 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5537 variable->data.driver_location = ctx->num_locals * 4;
5538 ctx->num_locals += attrib_count;
5539 }
5540 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5541 if (!ctx->locals)
5542 return;
5543
5544 for (i = 0; i < ctx->num_locals; i++) {
5545 for (j = 0; j < 4; j++) {
5546 ctx->locals[i * 4 + j] =
5547 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5548 }
5549 }
5550 }
5551
5552 static void
5553 setup_shared(struct ac_nir_context *ctx,
5554 struct nir_shader *nir)
5555 {
5556 nir_foreach_variable(variable, &nir->shared) {
5557 LLVMValueRef shared =
5558 LLVMAddGlobalInAddressSpace(
5559 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5560 variable->name ? variable->name : "",
5561 LOCAL_ADDR_SPACE);
5562 _mesa_hash_table_insert(ctx->vars, variable, shared);
5563 }
5564 }
5565
5566 static LLVMValueRef
5567 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5568 {
5569 v = ac_to_float(ctx, v);
5570 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5571 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5572 }
5573
5574
5575 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5576 LLVMValueRef src0, LLVMValueRef src1)
5577 {
5578 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5579 LLVMValueRef comp[2];
5580
5581 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5582 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5583 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5584 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5585 }
5586
5587 /* Initialize arguments for the shader export intrinsic */
5588 static void
5589 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5590 LLVMValueRef *values,
5591 unsigned target,
5592 struct ac_export_args *args)
5593 {
5594 /* Default is 0xf. Adjusted below depending on the format. */
5595 args->enabled_channels = 0xf;
5596
5597 /* Specify whether the EXEC mask represents the valid mask */
5598 args->valid_mask = 0;
5599
5600 /* Specify whether this is the last export */
5601 args->done = 0;
5602
5603 /* Specify the target we are exporting */
5604 args->target = target;
5605
5606 args->compr = false;
5607 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5608 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5609 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5610 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5611
5612 if (!values)
5613 return;
5614
5615 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5616 LLVMValueRef val[4];
5617 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5618 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5619 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5620 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5621
5622 switch(col_format) {
5623 case V_028714_SPI_SHADER_ZERO:
5624 args->enabled_channels = 0; /* writemask */
5625 args->target = V_008DFC_SQ_EXP_NULL;
5626 break;
5627
5628 case V_028714_SPI_SHADER_32_R:
5629 args->enabled_channels = 1;
5630 args->out[0] = values[0];
5631 break;
5632
5633 case V_028714_SPI_SHADER_32_GR:
5634 args->enabled_channels = 0x3;
5635 args->out[0] = values[0];
5636 args->out[1] = values[1];
5637 break;
5638
5639 case V_028714_SPI_SHADER_32_AR:
5640 args->enabled_channels = 0x9;
5641 args->out[0] = values[0];
5642 args->out[3] = values[3];
5643 break;
5644
5645 case V_028714_SPI_SHADER_FP16_ABGR:
5646 args->compr = 1;
5647
5648 for (unsigned chan = 0; chan < 2; chan++) {
5649 LLVMValueRef pack_args[2] = {
5650 values[2 * chan],
5651 values[2 * chan + 1]
5652 };
5653 LLVMValueRef packed;
5654
5655 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5656 args->out[chan] = packed;
5657 }
5658 break;
5659
5660 case V_028714_SPI_SHADER_UNORM16_ABGR:
5661 for (unsigned chan = 0; chan < 4; chan++) {
5662 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5663 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5664 LLVMConstReal(ctx->ac.f32, 65535), "");
5665 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5666 LLVMConstReal(ctx->ac.f32, 0.5), "");
5667 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5668 ctx->ac.i32, "");
5669 }
5670
5671 args->compr = 1;
5672 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5673 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5674 break;
5675
5676 case V_028714_SPI_SHADER_SNORM16_ABGR:
5677 for (unsigned chan = 0; chan < 4; chan++) {
5678 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5679 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5680 LLVMConstReal(ctx->ac.f32, 32767), "");
5681
5682 /* If positive, add 0.5, else add -0.5. */
5683 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5684 LLVMBuildSelect(ctx->builder,
5685 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5686 val[chan], ctx->ac.f32_0, ""),
5687 LLVMConstReal(ctx->ac.f32, 0.5),
5688 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5689 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5690 }
5691
5692 args->compr = 1;
5693 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5694 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5695 break;
5696
5697 case V_028714_SPI_SHADER_UINT16_ABGR: {
5698 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5699 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5700 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5701
5702 for (unsigned chan = 0; chan < 4; chan++) {
5703 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5704 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5705 }
5706
5707 args->compr = 1;
5708 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5709 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5710 break;
5711 }
5712
5713 case V_028714_SPI_SHADER_SINT16_ABGR: {
5714 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5715 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5716 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5717 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5718 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5719 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5720
5721 /* Clamp. */
5722 for (unsigned chan = 0; chan < 4; chan++) {
5723 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5724 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5725 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5726 }
5727
5728 args->compr = 1;
5729 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5730 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5731 break;
5732 }
5733
5734 default:
5735 case V_028714_SPI_SHADER_32_ABGR:
5736 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5737 break;
5738 }
5739 } else
5740 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5741
5742 for (unsigned i = 0; i < 4; ++i)
5743 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5744 }
5745
5746 static void
5747 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5748 bool export_prim_id,
5749 struct ac_vs_output_info *outinfo)
5750 {
5751 uint32_t param_count = 0;
5752 unsigned target;
5753 unsigned pos_idx, num_pos_exports = 0;
5754 struct ac_export_args args, pos_args[4] = {};
5755 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5756 int i;
5757
5758 if (ctx->options->key.has_multiview_view_index) {
5759 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5760 if(!*tmp_out) {
5761 for(unsigned i = 0; i < 4; ++i)
5762 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5763 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5764 }
5765
5766 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5767 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5768 }
5769
5770 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5771 sizeof(outinfo->vs_output_param_offset));
5772
5773 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5774 LLVMValueRef slots[8];
5775 unsigned j;
5776
5777 if (outinfo->cull_dist_mask)
5778 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5779
5780 i = VARYING_SLOT_CLIP_DIST0;
5781 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5782 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5783 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5784
5785 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5786 slots[i] = LLVMGetUndef(ctx->ac.f32);
5787
5788 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5789 target = V_008DFC_SQ_EXP_POS + 3;
5790 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5791 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5792 &args, sizeof(args));
5793 }
5794
5795 target = V_008DFC_SQ_EXP_POS + 2;
5796 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5797 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5798 &args, sizeof(args));
5799
5800 }
5801
5802 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5803 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5804 for (unsigned j = 0; j < 4; j++)
5805 pos_values[j] = LLVMBuildLoad(ctx->builder,
5806 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5807 }
5808 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5809
5810 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5811 outinfo->writes_pointsize = true;
5812 psize_value = LLVMBuildLoad(ctx->builder,
5813 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5814 }
5815
5816 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5817 outinfo->writes_layer = true;
5818 layer_value = LLVMBuildLoad(ctx->builder,
5819 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5820 }
5821
5822 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5823 outinfo->writes_viewport_index = true;
5824 viewport_index_value = LLVMBuildLoad(ctx->builder,
5825 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5826 }
5827
5828 if (outinfo->writes_pointsize ||
5829 outinfo->writes_layer ||
5830 outinfo->writes_viewport_index) {
5831 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5832 (outinfo->writes_layer == true ? 4 : 0));
5833 pos_args[1].valid_mask = 0;
5834 pos_args[1].done = 0;
5835 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5836 pos_args[1].compr = 0;
5837 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5838 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5839 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5840 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5841
5842 if (outinfo->writes_pointsize == true)
5843 pos_args[1].out[0] = psize_value;
5844 if (outinfo->writes_layer == true)
5845 pos_args[1].out[2] = layer_value;
5846 if (outinfo->writes_viewport_index == true) {
5847 if (ctx->options->chip_class >= GFX9) {
5848 /* GFX9 has the layer in out.z[10:0] and the viewport
5849 * index in out.z[19:16].
5850 */
5851 LLVMValueRef v = viewport_index_value;
5852 v = ac_to_integer(&ctx->ac, v);
5853 v = LLVMBuildShl(ctx->builder, v,
5854 LLVMConstInt(ctx->ac.i32, 16, false),
5855 "");
5856 v = LLVMBuildOr(ctx->builder, v,
5857 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5858
5859 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5860 pos_args[1].enabled_channels |= 1 << 2;
5861 } else {
5862 pos_args[1].out[3] = viewport_index_value;
5863 pos_args[1].enabled_channels |= 1 << 3;
5864 }
5865 }
5866 }
5867 for (i = 0; i < 4; i++) {
5868 if (pos_args[i].out[0])
5869 num_pos_exports++;
5870 }
5871
5872 pos_idx = 0;
5873 for (i = 0; i < 4; i++) {
5874 if (!pos_args[i].out[0])
5875 continue;
5876
5877 /* Specify the target we are exporting */
5878 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5879 if (pos_idx == num_pos_exports)
5880 pos_args[i].done = 1;
5881 ac_build_export(&ctx->ac, &pos_args[i]);
5882 }
5883
5884 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5885 LLVMValueRef values[4];
5886 if (!(ctx->output_mask & (1ull << i)))
5887 continue;
5888
5889 for (unsigned j = 0; j < 4; j++)
5890 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5891 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5892
5893 if (i == VARYING_SLOT_LAYER) {
5894 target = V_008DFC_SQ_EXP_PARAM + param_count;
5895 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5896 param_count++;
5897 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5898 target = V_008DFC_SQ_EXP_PARAM + param_count;
5899 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5900 param_count++;
5901 } else if (i >= VARYING_SLOT_VAR0) {
5902 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5903 target = V_008DFC_SQ_EXP_PARAM + param_count;
5904 outinfo->vs_output_param_offset[i] = param_count;
5905 param_count++;
5906 } else
5907 continue;
5908
5909 si_llvm_init_export_args(ctx, values, target, &args);
5910
5911 if (target >= V_008DFC_SQ_EXP_POS &&
5912 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5913 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5914 &args, sizeof(args));
5915 } else {
5916 ac_build_export(&ctx->ac, &args);
5917 }
5918 }
5919
5920 if (export_prim_id) {
5921 LLVMValueRef values[4];
5922 target = V_008DFC_SQ_EXP_PARAM + param_count;
5923 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5924 param_count++;
5925
5926 values[0] = ctx->vs_prim_id;
5927 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5928 ctx->shader_info->vs.vgpr_comp_cnt);
5929 for (unsigned j = 1; j < 4; j++)
5930 values[j] = ctx->ac.f32_0;
5931 si_llvm_init_export_args(ctx, values, target, &args);
5932 ac_build_export(&ctx->ac, &args);
5933 outinfo->export_prim_id = true;
5934 }
5935
5936 outinfo->pos_exports = num_pos_exports;
5937 outinfo->param_exports = param_count;
5938 }
5939
5940 static void
5941 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5942 struct ac_es_output_info *outinfo)
5943 {
5944 int j;
5945 uint64_t max_output_written = 0;
5946 LLVMValueRef lds_base = NULL;
5947
5948 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5949 int param_index;
5950 int length = 4;
5951
5952 if (!(ctx->output_mask & (1ull << i)))
5953 continue;
5954
5955 if (i == VARYING_SLOT_CLIP_DIST0)
5956 length = ctx->num_output_clips + ctx->num_output_culls;
5957
5958 param_index = shader_io_get_unique_index(i);
5959
5960 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5961 }
5962
5963 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5964
5965 if (ctx->ac.chip_class >= GFX9) {
5966 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5967 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5968 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5969 LLVMConstInt(ctx->ac.i32, 24, false),
5970 LLVMConstInt(ctx->ac.i32, 4, false), false);
5971 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5972 LLVMBuildMul(ctx->ac.builder, wave_idx,
5973 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5974 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5975 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5976 }
5977
5978 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5979 LLVMValueRef dw_addr;
5980 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5981 int param_index;
5982 int length = 4;
5983
5984 if (!(ctx->output_mask & (1ull << i)))
5985 continue;
5986
5987 if (i == VARYING_SLOT_CLIP_DIST0)
5988 length = ctx->num_output_clips + ctx->num_output_culls;
5989
5990 param_index = shader_io_get_unique_index(i);
5991
5992 if (lds_base) {
5993 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5994 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
5995 "");
5996 }
5997 for (j = 0; j < length; j++) {
5998 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5999 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6000
6001 if (ctx->ac.chip_class >= GFX9) {
6002 ac_lds_store(&ctx->ac, dw_addr,
6003 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6004 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6005 } else {
6006 ac_build_buffer_store_dword(&ctx->ac,
6007 ctx->esgs_ring,
6008 out_val, 1,
6009 NULL, ctx->es2gs_offset,
6010 (4 * param_index + j) * 4,
6011 1, 1, true, true);
6012 }
6013 }
6014 }
6015 }
6016
6017 static void
6018 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6019 {
6020 LLVMValueRef vertex_id = ctx->rel_auto_id;
6021 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6022 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6023 vertex_dw_stride, "");
6024
6025 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6026 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6027 int length = 4;
6028
6029 if (!(ctx->output_mask & (1ull << i)))
6030 continue;
6031
6032 if (i == VARYING_SLOT_CLIP_DIST0)
6033 length = ctx->num_output_clips + ctx->num_output_culls;
6034 int param = shader_io_get_unique_index(i);
6035 mark_tess_output(ctx, false, param);
6036 if (length > 4)
6037 mark_tess_output(ctx, false, param + 1);
6038 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6039 LLVMConstInt(ctx->ac.i32, param * 4, false),
6040 "");
6041 for (unsigned j = 0; j < length; j++) {
6042 ac_lds_store(&ctx->ac, dw_addr,
6043 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6044 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6045 }
6046 }
6047 }
6048
6049 struct ac_build_if_state
6050 {
6051 struct nir_to_llvm_context *ctx;
6052 LLVMValueRef condition;
6053 LLVMBasicBlockRef entry_block;
6054 LLVMBasicBlockRef true_block;
6055 LLVMBasicBlockRef false_block;
6056 LLVMBasicBlockRef merge_block;
6057 };
6058
6059 static LLVMBasicBlockRef
6060 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6061 {
6062 LLVMBasicBlockRef current_block;
6063 LLVMBasicBlockRef next_block;
6064 LLVMBasicBlockRef new_block;
6065
6066 /* get current basic block */
6067 current_block = LLVMGetInsertBlock(ctx->builder);
6068
6069 /* chqeck if there's another block after this one */
6070 next_block = LLVMGetNextBasicBlock(current_block);
6071 if (next_block) {
6072 /* insert the new block before the next block */
6073 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6074 }
6075 else {
6076 /* append new block after current block */
6077 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6078 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6079 }
6080 return new_block;
6081 }
6082
6083 static void
6084 ac_nir_build_if(struct ac_build_if_state *ifthen,
6085 struct nir_to_llvm_context *ctx,
6086 LLVMValueRef condition)
6087 {
6088 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6089
6090 memset(ifthen, 0, sizeof *ifthen);
6091 ifthen->ctx = ctx;
6092 ifthen->condition = condition;
6093 ifthen->entry_block = block;
6094
6095 /* create endif/merge basic block for the phi functions */
6096 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6097
6098 /* create/insert true_block before merge_block */
6099 ifthen->true_block =
6100 LLVMInsertBasicBlockInContext(ctx->context,
6101 ifthen->merge_block,
6102 "if-true-block");
6103
6104 /* successive code goes into the true block */
6105 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6106 }
6107
6108 /**
6109 * End a conditional.
6110 */
6111 static void
6112 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6113 {
6114 LLVMBuilderRef builder = ifthen->ctx->builder;
6115
6116 /* Insert branch to the merge block from current block */
6117 LLVMBuildBr(builder, ifthen->merge_block);
6118
6119 /*
6120 * Now patch in the various branch instructions.
6121 */
6122
6123 /* Insert the conditional branch instruction at the end of entry_block */
6124 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6125 if (ifthen->false_block) {
6126 /* we have an else clause */
6127 LLVMBuildCondBr(builder, ifthen->condition,
6128 ifthen->true_block, ifthen->false_block);
6129 }
6130 else {
6131 /* no else clause */
6132 LLVMBuildCondBr(builder, ifthen->condition,
6133 ifthen->true_block, ifthen->merge_block);
6134 }
6135
6136 /* Resume building code at end of the ifthen->merge_block */
6137 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6138 }
6139
6140 static void
6141 write_tess_factors(struct nir_to_llvm_context *ctx)
6142 {
6143 unsigned stride, outer_comps, inner_comps;
6144 struct ac_build_if_state if_ctx, inner_if_ctx;
6145 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6146 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6147 unsigned tess_inner_index, tess_outer_index;
6148 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6149 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6150 int i;
6151 emit_barrier(ctx);
6152
6153 switch (ctx->options->key.tcs.primitive_mode) {
6154 case GL_ISOLINES:
6155 stride = 2;
6156 outer_comps = 2;
6157 inner_comps = 0;
6158 break;
6159 case GL_TRIANGLES:
6160 stride = 4;
6161 outer_comps = 3;
6162 inner_comps = 1;
6163 break;
6164 case GL_QUADS:
6165 stride = 6;
6166 outer_comps = 4;
6167 inner_comps = 2;
6168 break;
6169 default:
6170 return;
6171 }
6172
6173 ac_nir_build_if(&if_ctx, ctx,
6174 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6175 invocation_id, ctx->ac.i32_0, ""));
6176
6177 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6178 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6179
6180 mark_tess_output(ctx, true, tess_inner_index);
6181 mark_tess_output(ctx, true, tess_outer_index);
6182 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6183 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6184 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6185 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6186 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6187
6188 for (i = 0; i < 4; i++) {
6189 inner[i] = LLVMGetUndef(ctx->ac.i32);
6190 outer[i] = LLVMGetUndef(ctx->ac.i32);
6191 }
6192
6193 // LINES reverseal
6194 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6195 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6196 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6197 ctx->ac.i32_1, "");
6198 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6199 } else {
6200 for (i = 0; i < outer_comps; i++) {
6201 outer[i] = out[i] =
6202 ac_lds_load(&ctx->ac, lds_outer);
6203 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6204 ctx->ac.i32_1, "");
6205 }
6206 for (i = 0; i < inner_comps; i++) {
6207 inner[i] = out[outer_comps+i] =
6208 ac_lds_load(&ctx->ac, lds_inner);
6209 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6210 ctx->ac.i32_1, "");
6211 }
6212 }
6213
6214 /* Convert the outputs to vectors for stores. */
6215 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6216 vec1 = NULL;
6217
6218 if (stride > 4)
6219 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6220
6221
6222 buffer = ctx->hs_ring_tess_factor;
6223 tf_base = ctx->tess_factor_offset;
6224 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6225 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6226 unsigned tf_offset = 0;
6227
6228 if (ctx->options->chip_class <= VI) {
6229 ac_nir_build_if(&inner_if_ctx, ctx,
6230 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6231 rel_patch_id, ctx->ac.i32_0, ""));
6232
6233 /* Store the dynamic HS control word. */
6234 ac_build_buffer_store_dword(&ctx->ac, buffer,
6235 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6236 1, ctx->ac.i32_0, tf_base,
6237 0, 1, 0, true, false);
6238 tf_offset += 4;
6239
6240 ac_nir_build_endif(&inner_if_ctx);
6241 }
6242
6243 /* Store the tessellation factors. */
6244 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6245 MIN2(stride, 4), byteoffset, tf_base,
6246 tf_offset, 1, 0, true, false);
6247 if (vec1)
6248 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6249 stride - 4, byteoffset, tf_base,
6250 16 + tf_offset, 1, 0, true, false);
6251
6252 //store to offchip for TES to read - only if TES reads them
6253 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6254 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6255 LLVMValueRef tf_inner_offset;
6256 unsigned param_outer, param_inner;
6257
6258 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6259 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6260 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6261
6262 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6263 util_next_power_of_two(outer_comps));
6264
6265 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6266 outer_comps, tf_outer_offset,
6267 ctx->oc_lds, 0, 1, 0, true, false);
6268 if (inner_comps) {
6269 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6270 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6271 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6272
6273 inner_vec = inner_comps == 1 ? inner[0] :
6274 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6275 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6276 inner_comps, tf_inner_offset,
6277 ctx->oc_lds, 0, 1, 0, true, false);
6278 }
6279 }
6280 ac_nir_build_endif(&if_ctx);
6281 }
6282
6283 static void
6284 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6285 {
6286 write_tess_factors(ctx);
6287 }
6288
6289 static bool
6290 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6291 LLVMValueRef *color, unsigned param, bool is_last,
6292 struct ac_export_args *args)
6293 {
6294 /* Export */
6295 si_llvm_init_export_args(ctx, color, param,
6296 args);
6297
6298 if (is_last) {
6299 args->valid_mask = 1; /* whether the EXEC mask is valid */
6300 args->done = 1; /* DONE bit */
6301 } else if (!args->enabled_channels)
6302 return false; /* unnecessary NULL export */
6303
6304 return true;
6305 }
6306
6307 static void
6308 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6309 LLVMValueRef depth, LLVMValueRef stencil,
6310 LLVMValueRef samplemask)
6311 {
6312 struct ac_export_args args;
6313
6314 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6315
6316 ac_build_export(&ctx->ac, &args);
6317 }
6318
6319 static void
6320 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6321 {
6322 unsigned index = 0;
6323 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6324 struct ac_export_args color_args[8];
6325
6326 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6327 LLVMValueRef values[4];
6328
6329 if (!(ctx->output_mask & (1ull << i)))
6330 continue;
6331
6332 if (i == FRAG_RESULT_DEPTH) {
6333 ctx->shader_info->fs.writes_z = true;
6334 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6335 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6336 } else if (i == FRAG_RESULT_STENCIL) {
6337 ctx->shader_info->fs.writes_stencil = true;
6338 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6339 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6340 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6341 ctx->shader_info->fs.writes_sample_mask = true;
6342 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6343 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6344 } else {
6345 bool last = false;
6346 for (unsigned j = 0; j < 4; j++)
6347 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6348 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6349
6350 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6351 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6352
6353 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6354 if (ret)
6355 index++;
6356 }
6357 }
6358
6359 for (unsigned i = 0; i < index; i++)
6360 ac_build_export(&ctx->ac, &color_args[i]);
6361 if (depth || stencil || samplemask)
6362 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6363 else if (!index) {
6364 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6365 ac_build_export(&ctx->ac, &color_args[0]);
6366 }
6367
6368 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6369 }
6370
6371 static void
6372 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6373 {
6374 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6375 }
6376
6377 static void
6378 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6379 LLVMValueRef *addrs)
6380 {
6381 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6382
6383 switch (ctx->stage) {
6384 case MESA_SHADER_VERTEX:
6385 if (ctx->options->key.vs.as_ls)
6386 handle_ls_outputs_post(ctx);
6387 else if (ctx->options->key.vs.as_es)
6388 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6389 else
6390 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6391 &ctx->shader_info->vs.outinfo);
6392 break;
6393 case MESA_SHADER_FRAGMENT:
6394 handle_fs_outputs_post(ctx);
6395 break;
6396 case MESA_SHADER_GEOMETRY:
6397 emit_gs_epilogue(ctx);
6398 break;
6399 case MESA_SHADER_TESS_CTRL:
6400 handle_tcs_outputs_post(ctx);
6401 break;
6402 case MESA_SHADER_TESS_EVAL:
6403 if (ctx->options->key.tes.as_es)
6404 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6405 else
6406 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6407 &ctx->shader_info->tes.outinfo);
6408 break;
6409 default:
6410 break;
6411 }
6412 }
6413
6414 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6415 {
6416 LLVMPassManagerRef passmgr;
6417 /* Create the pass manager */
6418 passmgr = LLVMCreateFunctionPassManagerForModule(
6419 ctx->module);
6420
6421 /* This pass should eliminate all the load and store instructions */
6422 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6423
6424 /* Add some optimization passes */
6425 LLVMAddScalarReplAggregatesPass(passmgr);
6426 LLVMAddLICMPass(passmgr);
6427 LLVMAddAggressiveDCEPass(passmgr);
6428 LLVMAddCFGSimplificationPass(passmgr);
6429 LLVMAddInstructionCombiningPass(passmgr);
6430
6431 /* Run the pass */
6432 LLVMInitializeFunctionPassManager(passmgr);
6433 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6434 LLVMFinalizeFunctionPassManager(passmgr);
6435
6436 LLVMDisposeBuilder(ctx->builder);
6437 LLVMDisposePassManager(passmgr);
6438 }
6439
6440 static void
6441 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6442 {
6443 struct ac_vs_output_info *outinfo;
6444
6445 switch (ctx->stage) {
6446 case MESA_SHADER_FRAGMENT:
6447 case MESA_SHADER_COMPUTE:
6448 case MESA_SHADER_TESS_CTRL:
6449 case MESA_SHADER_GEOMETRY:
6450 return;
6451 case MESA_SHADER_VERTEX:
6452 if (ctx->options->key.vs.as_ls ||
6453 ctx->options->key.vs.as_es)
6454 return;
6455 outinfo = &ctx->shader_info->vs.outinfo;
6456 break;
6457 case MESA_SHADER_TESS_EVAL:
6458 if (ctx->options->key.vs.as_es)
6459 return;
6460 outinfo = &ctx->shader_info->tes.outinfo;
6461 break;
6462 default:
6463 unreachable("Unhandled shader type");
6464 }
6465
6466 ac_optimize_vs_outputs(&ctx->ac,
6467 ctx->main_function,
6468 outinfo->vs_output_param_offset,
6469 VARYING_SLOT_MAX,
6470 &outinfo->param_exports);
6471 }
6472
6473 static void
6474 ac_setup_rings(struct nir_to_llvm_context *ctx)
6475 {
6476 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6477 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6478 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6479 }
6480
6481 if (ctx->is_gs_copy_shader) {
6482 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6483 }
6484 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6485 LLVMValueRef tmp;
6486 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6487 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6488
6489 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6490
6491 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6492 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6493 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6494 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6495 }
6496
6497 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6498 ctx->stage == MESA_SHADER_TESS_EVAL) {
6499 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6500 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6501 }
6502 }
6503
6504 static unsigned
6505 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6506 const struct nir_shader *nir)
6507 {
6508 switch (nir->info.stage) {
6509 case MESA_SHADER_TESS_CTRL:
6510 return chip_class >= CIK ? 128 : 64;
6511 case MESA_SHADER_GEOMETRY:
6512 return chip_class >= GFX9 ? 128 : 64;
6513 case MESA_SHADER_COMPUTE:
6514 break;
6515 default:
6516 return 0;
6517 }
6518
6519 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6520 nir->info.cs.local_size[1] *
6521 nir->info.cs.local_size[2];
6522 return max_workgroup_size;
6523 }
6524
6525 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6526 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6527 {
6528 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6529 LLVMConstInt(ctx->ac.i32, 8, false),
6530 LLVMConstInt(ctx->ac.i32, 8, false), false);
6531 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6532 ctx->ac.i32_0, "");
6533 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6534 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6535 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6536 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6537 }
6538
6539 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6540 {
6541 for(int i = 5; i >= 0; --i) {
6542 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6543 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6544 LLVMConstInt(ctx->ac.i32, 16, false), false);
6545 }
6546
6547 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6548 LLVMConstInt(ctx->ac.i32, 16, false),
6549 LLVMConstInt(ctx->ac.i32, 8, false), false);
6550 }
6551
6552 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6553 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6554 {
6555 struct ac_nir_context ctx = {};
6556 struct nir_function *func;
6557
6558 ctx.ac = *ac;
6559 ctx.abi = abi;
6560
6561 ctx.nctx = nctx;
6562 if (nctx)
6563 nctx->nir = &ctx;
6564
6565 ctx.stage = nir->info.stage;
6566
6567 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6568
6569 nir_foreach_variable(variable, &nir->outputs)
6570 handle_shader_output_decl(&ctx, nir, variable);
6571
6572 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6573 _mesa_key_pointer_equal);
6574 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6575 _mesa_key_pointer_equal);
6576 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6577 _mesa_key_pointer_equal);
6578
6579 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6580
6581 setup_locals(&ctx, func);
6582
6583 if (nir->info.stage == MESA_SHADER_COMPUTE)
6584 setup_shared(&ctx, nir);
6585
6586 visit_cf_list(&ctx, &func->impl->body);
6587 phi_post_pass(&ctx);
6588
6589 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6590 ctx.outputs);
6591
6592 free(ctx.locals);
6593 ralloc_free(ctx.defs);
6594 ralloc_free(ctx.phis);
6595 ralloc_free(ctx.vars);
6596
6597 if (nctx)
6598 nctx->nir = NULL;
6599 }
6600
6601 static
6602 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6603 struct nir_shader *const *shaders,
6604 int shader_count,
6605 struct ac_shader_variant_info *shader_info,
6606 const struct ac_nir_compiler_options *options)
6607 {
6608 struct nir_to_llvm_context ctx = {0};
6609 unsigned i;
6610 ctx.options = options;
6611 ctx.shader_info = shader_info;
6612 ctx.context = LLVMContextCreate();
6613 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6614
6615 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6616 options->family);
6617 ctx.ac.module = ctx.module;
6618 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6619
6620 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6621 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6622 LLVMSetDataLayout(ctx.module, data_layout_str);
6623 LLVMDisposeTargetData(data_layout);
6624 LLVMDisposeMessage(data_layout_str);
6625
6626 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6627 ctx.ac.builder = ctx.builder;
6628
6629 memset(shader_info, 0, sizeof(*shader_info));
6630
6631 for(int i = 0; i < shader_count; ++i)
6632 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6633
6634 for (i = 0; i < AC_UD_MAX_SETS; i++)
6635 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6636 for (i = 0; i < AC_UD_MAX_UD; i++)
6637 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6638
6639 ctx.max_workgroup_size = 0;
6640 for (int i = 0; i < shader_count; ++i) {
6641 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6642 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6643 shaders[i]));
6644 }
6645
6646 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6647 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6648
6649 ctx.abi.inputs = &ctx.inputs[0];
6650 ctx.abi.emit_outputs = handle_shader_outputs_post;
6651 ctx.abi.emit_vertex = visit_emit_vertex;
6652 ctx.abi.load_ubo = radv_load_ubo;
6653 ctx.abi.load_ssbo = radv_load_ssbo;
6654 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6655 ctx.abi.clamp_shadow_reference = false;
6656
6657 if (shader_count >= 2)
6658 ac_init_exec_full_mask(&ctx.ac);
6659
6660 if (ctx.ac.chip_class == GFX9 &&
6661 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6662 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6663
6664 for(int i = 0; i < shader_count; ++i) {
6665 ctx.stage = shaders[i]->info.stage;
6666 ctx.output_mask = 0;
6667 ctx.tess_outputs_written = 0;
6668 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6669 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6670
6671 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6672 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6673 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6674 ctx.abi.load_inputs = load_gs_input;
6675 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6676 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6677 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6678 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6679 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6680 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6681 if (shader_info->info.vs.needs_instance_id) {
6682 ctx.shader_info->vs.vgpr_comp_cnt =
6683 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6684 }
6685 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6686 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6687 }
6688
6689 if (i)
6690 emit_barrier(&ctx);
6691
6692 ac_setup_rings(&ctx);
6693
6694 LLVMBasicBlockRef merge_block;
6695 if (shader_count >= 2) {
6696 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6697 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6698 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6699
6700 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6701 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6702 LLVMConstInt(ctx.ac.i32, 8, false), false);
6703 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6704 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6705 thread_id, count, "");
6706 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6707
6708 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6709 }
6710
6711 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6712 handle_fs_inputs(&ctx, shaders[i]);
6713 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6714 handle_vs_inputs(&ctx, shaders[i]);
6715 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6716 prepare_gs_input_vgprs(&ctx);
6717
6718 nir_foreach_variable(variable, &shaders[i]->outputs)
6719 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6720
6721 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6722
6723 if (shader_count >= 2) {
6724 LLVMBuildBr(ctx.ac.builder, merge_block);
6725 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6726 }
6727
6728 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6729 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6730 shaders[i]->info.cull_distance_array_size > 4;
6731 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6732 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6733 shaders[i]->info.gs.vertices_out;
6734 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6735 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6736 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6737 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6738 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6739 }
6740 }
6741
6742 LLVMBuildRetVoid(ctx.builder);
6743
6744 ac_llvm_finalize_module(&ctx);
6745
6746 if (shader_count == 1)
6747 ac_nir_eliminate_const_vs_outputs(&ctx);
6748
6749 return ctx.module;
6750 }
6751
6752 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6753 {
6754 unsigned *retval = (unsigned *)context;
6755 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6756 char *description = LLVMGetDiagInfoDescription(di);
6757
6758 if (severity == LLVMDSError) {
6759 *retval = 1;
6760 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6761 description);
6762 }
6763
6764 LLVMDisposeMessage(description);
6765 }
6766
6767 static unsigned ac_llvm_compile(LLVMModuleRef M,
6768 struct ac_shader_binary *binary,
6769 LLVMTargetMachineRef tm)
6770 {
6771 unsigned retval = 0;
6772 char *err;
6773 LLVMContextRef llvm_ctx;
6774 LLVMMemoryBufferRef out_buffer;
6775 unsigned buffer_size;
6776 const char *buffer_data;
6777 LLVMBool mem_err;
6778
6779 /* Setup Diagnostic Handler*/
6780 llvm_ctx = LLVMGetModuleContext(M);
6781
6782 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6783 &retval);
6784
6785 /* Compile IR*/
6786 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6787 &err, &out_buffer);
6788
6789 /* Process Errors/Warnings */
6790 if (mem_err) {
6791 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6792 free(err);
6793 retval = 1;
6794 goto out;
6795 }
6796
6797 /* Extract Shader Code*/
6798 buffer_size = LLVMGetBufferSize(out_buffer);
6799 buffer_data = LLVMGetBufferStart(out_buffer);
6800
6801 ac_elf_read(buffer_data, buffer_size, binary);
6802
6803 /* Clean up */
6804 LLVMDisposeMemoryBuffer(out_buffer);
6805
6806 out:
6807 return retval;
6808 }
6809
6810 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6811 LLVMModuleRef llvm_module,
6812 struct ac_shader_binary *binary,
6813 struct ac_shader_config *config,
6814 struct ac_shader_variant_info *shader_info,
6815 gl_shader_stage stage,
6816 bool dump_shader, bool supports_spill)
6817 {
6818 if (dump_shader)
6819 ac_dump_module(llvm_module);
6820
6821 memset(binary, 0, sizeof(*binary));
6822 int v = ac_llvm_compile(llvm_module, binary, tm);
6823 if (v) {
6824 fprintf(stderr, "compile failed\n");
6825 }
6826
6827 if (dump_shader)
6828 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6829
6830 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6831
6832 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6833 LLVMDisposeModule(llvm_module);
6834 LLVMContextDispose(ctx);
6835
6836 if (stage == MESA_SHADER_FRAGMENT) {
6837 shader_info->num_input_vgprs = 0;
6838 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6839 shader_info->num_input_vgprs += 2;
6840 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6841 shader_info->num_input_vgprs += 2;
6842 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6843 shader_info->num_input_vgprs += 2;
6844 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6845 shader_info->num_input_vgprs += 3;
6846 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6847 shader_info->num_input_vgprs += 2;
6848 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6849 shader_info->num_input_vgprs += 2;
6850 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6851 shader_info->num_input_vgprs += 2;
6852 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6853 shader_info->num_input_vgprs += 1;
6854 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6855 shader_info->num_input_vgprs += 1;
6856 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6857 shader_info->num_input_vgprs += 1;
6858 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6859 shader_info->num_input_vgprs += 1;
6860 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6861 shader_info->num_input_vgprs += 1;
6862 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6863 shader_info->num_input_vgprs += 1;
6864 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6865 shader_info->num_input_vgprs += 1;
6866 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6867 shader_info->num_input_vgprs += 1;
6868 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6869 shader_info->num_input_vgprs += 1;
6870 }
6871 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6872
6873 /* +3 for scratch wave offset and VCC */
6874 config->num_sgprs = MAX2(config->num_sgprs,
6875 shader_info->num_input_sgprs + 3);
6876 }
6877
6878 static void
6879 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6880 {
6881 switch (nir->info.stage) {
6882 case MESA_SHADER_COMPUTE:
6883 for (int i = 0; i < 3; ++i)
6884 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6885 break;
6886 case MESA_SHADER_FRAGMENT:
6887 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6888 break;
6889 case MESA_SHADER_GEOMETRY:
6890 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6891 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6892 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6893 shader_info->gs.invocations = nir->info.gs.invocations;
6894 break;
6895 case MESA_SHADER_TESS_EVAL:
6896 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6897 shader_info->tes.spacing = nir->info.tess.spacing;
6898 shader_info->tes.ccw = nir->info.tess.ccw;
6899 shader_info->tes.point_mode = nir->info.tess.point_mode;
6900 shader_info->tes.as_es = options->key.tes.as_es;
6901 break;
6902 case MESA_SHADER_TESS_CTRL:
6903 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6904 break;
6905 case MESA_SHADER_VERTEX:
6906 shader_info->vs.as_es = options->key.vs.as_es;
6907 shader_info->vs.as_ls = options->key.vs.as_ls;
6908 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6909 if (options->key.vs.as_ls)
6910 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6911 break;
6912 default:
6913 break;
6914 }
6915 }
6916
6917 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6918 struct ac_shader_binary *binary,
6919 struct ac_shader_config *config,
6920 struct ac_shader_variant_info *shader_info,
6921 struct nir_shader *const *nir,
6922 int nir_count,
6923 const struct ac_nir_compiler_options *options,
6924 bool dump_shader)
6925 {
6926
6927 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6928 options);
6929
6930 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6931 for (int i = 0; i < nir_count; ++i)
6932 ac_fill_shader_info(shader_info, nir[i], options);
6933 }
6934
6935 static void
6936 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6937 {
6938 LLVMValueRef args[9];
6939 args[0] = ctx->gsvs_ring;
6940 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6941 args[3] = ctx->ac.i32_0;
6942 args[4] = ctx->ac.i32_1; /* OFFEN */
6943 args[5] = ctx->ac.i32_0; /* IDXEN */
6944 args[6] = ctx->ac.i32_1; /* GLC */
6945 args[7] = ctx->ac.i32_1; /* SLC */
6946 args[8] = ctx->ac.i32_0; /* TFE */
6947
6948 int idx = 0;
6949
6950 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6951 int length = 4;
6952 int slot = idx;
6953 int slot_inc = 1;
6954 if (!(ctx->output_mask & (1ull << i)))
6955 continue;
6956
6957 if (i == VARYING_SLOT_CLIP_DIST0) {
6958 /* unpack clip and cull from a single set of slots */
6959 length = ctx->num_output_clips + ctx->num_output_culls;
6960 if (length > 4)
6961 slot_inc = 2;
6962 }
6963
6964 for (unsigned j = 0; j < length; j++) {
6965 LLVMValueRef value;
6966 args[2] = LLVMConstInt(ctx->ac.i32,
6967 (slot * 4 + j) *
6968 ctx->gs_max_out_vertices * 16 * 4, false);
6969
6970 value = ac_build_intrinsic(&ctx->ac,
6971 "llvm.SI.buffer.load.dword.i32.i32",
6972 ctx->ac.i32, args, 9,
6973 AC_FUNC_ATTR_READONLY |
6974 AC_FUNC_ATTR_LEGACY);
6975
6976 LLVMBuildStore(ctx->builder,
6977 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6978 }
6979 idx += slot_inc;
6980 }
6981 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6982 }
6983
6984 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6985 struct nir_shader *geom_shader,
6986 struct ac_shader_binary *binary,
6987 struct ac_shader_config *config,
6988 struct ac_shader_variant_info *shader_info,
6989 const struct ac_nir_compiler_options *options,
6990 bool dump_shader)
6991 {
6992 struct nir_to_llvm_context ctx = {0};
6993 ctx.context = LLVMContextCreate();
6994 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6995 ctx.options = options;
6996 ctx.shader_info = shader_info;
6997
6998 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6999 options->family);
7000 ctx.ac.module = ctx.module;
7001
7002 ctx.is_gs_copy_shader = true;
7003 LLVMSetTarget(ctx.module, "amdgcn--");
7004
7005 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
7006 ctx.ac.builder = ctx.builder;
7007 ctx.stage = MESA_SHADER_VERTEX;
7008
7009 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7010
7011 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7012 ac_setup_rings(&ctx);
7013
7014 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7015 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7016
7017 struct ac_nir_context nir_ctx = {};
7018 nir_ctx.ac = ctx.ac;
7019 nir_ctx.abi = &ctx.abi;
7020
7021 nir_ctx.nctx = &ctx;
7022 ctx.nir = &nir_ctx;
7023
7024 nir_foreach_variable(variable, &geom_shader->outputs) {
7025 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7026 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7027 }
7028
7029 ac_gs_copy_shader_emit(&ctx);
7030
7031 ctx.nir = NULL;
7032
7033 LLVMBuildRetVoid(ctx.builder);
7034
7035 ac_llvm_finalize_module(&ctx);
7036
7037 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7038 MESA_SHADER_VERTEX,
7039 dump_shader, options->supports_spill);
7040 }