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[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
48
49 struct nir_to_llvm_context;
50
51 struct ac_nir_context {
52 struct ac_llvm_context ac;
53 struct ac_shader_abi *abi;
54
55 gl_shader_stage stage;
56
57 struct hash_table *defs;
58 struct hash_table *phis;
59 struct hash_table *vars;
60
61 LLVMValueRef main_function;
62 LLVMBasicBlockRef continue_block;
63 LLVMBasicBlockRef break_block;
64
65 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
66
67 int num_locals;
68 LLVMValueRef *locals;
69
70 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
71 };
72
73 struct nir_to_llvm_context {
74 struct ac_llvm_context ac;
75 const struct ac_nir_compiler_options *options;
76 struct ac_shader_variant_info *shader_info;
77 struct ac_shader_abi abi;
78 struct ac_nir_context *nir;
79
80 unsigned max_workgroup_size;
81 LLVMContextRef context;
82 LLVMModuleRef module;
83 LLVMBuilderRef builder;
84 LLVMValueRef main_function;
85
86 struct hash_table *defs;
87 struct hash_table *phis;
88
89 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
90 LLVMValueRef ring_offsets;
91 LLVMValueRef push_constants;
92 LLVMValueRef view_index;
93 LLVMValueRef num_work_groups;
94 LLVMValueRef local_invocation_ids;
95 LLVMValueRef tg_size;
96
97 LLVMValueRef vertex_buffers;
98 LLVMValueRef rel_auto_id;
99 LLVMValueRef vs_prim_id;
100 LLVMValueRef ls_out_layout;
101 LLVMValueRef es2gs_offset;
102
103 LLVMValueRef tcs_offchip_layout;
104 LLVMValueRef tcs_out_offsets;
105 LLVMValueRef tcs_out_layout;
106 LLVMValueRef tcs_in_layout;
107 LLVMValueRef oc_lds;
108 LLVMValueRef merged_wave_info;
109 LLVMValueRef tess_factor_offset;
110 LLVMValueRef tes_rel_patch_id;
111 LLVMValueRef tes_u;
112 LLVMValueRef tes_v;
113
114 LLVMValueRef gsvs_ring_stride;
115 LLVMValueRef gsvs_num_entries;
116 LLVMValueRef gs2vs_offset;
117 LLVMValueRef gs_wave_id;
118 LLVMValueRef gs_vtx_offset[6];
119
120 LLVMValueRef esgs_ring;
121 LLVMValueRef gsvs_ring;
122 LLVMValueRef hs_ring_tess_offchip;
123 LLVMValueRef hs_ring_tess_factor;
124
125 LLVMValueRef sample_pos_offset;
126 LLVMValueRef persp_sample, persp_center, persp_centroid;
127 LLVMValueRef linear_sample, linear_center, linear_centroid;
128
129 gl_shader_stage stage;
130
131 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
132
133 uint64_t input_mask;
134 uint64_t output_mask;
135 uint8_t num_output_clips;
136 uint8_t num_output_culls;
137
138 bool is_gs_copy_shader;
139 LLVMValueRef gs_next_vertex;
140 unsigned gs_max_out_vertices;
141
142 unsigned tes_primitive_mode;
143 uint64_t tess_outputs_written;
144 uint64_t tess_patch_outputs_written;
145
146 uint32_t tcs_patch_outputs_read;
147 uint64_t tcs_outputs_read;
148 };
149
150 static inline struct nir_to_llvm_context *
151 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
152 {
153 struct nir_to_llvm_context *ctx = NULL;
154 return container_of(abi, ctx, abi);
155 }
156
157 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
158 const nir_deref_var *deref,
159 enum ac_descriptor_type desc_type,
160 const nir_tex_instr *instr,
161 bool image, bool write);
162
163 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
164 {
165 return (index * 4) + chan;
166 }
167
168 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
169 {
170 /* handle patch indices separate */
171 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
172 return 0;
173 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
174 return 1;
175 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
176 return 2 + (slot - VARYING_SLOT_PATCH0);
177
178 if (slot == VARYING_SLOT_POS)
179 return 0;
180 if (slot == VARYING_SLOT_PSIZ)
181 return 1;
182 if (slot == VARYING_SLOT_CLIP_DIST0)
183 return 2;
184 /* 3 is reserved for clip dist as well */
185 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
186 return 4 + (slot - VARYING_SLOT_VAR0);
187 unreachable("illegal slot in get unique index\n");
188 }
189
190 static void set_llvm_calling_convention(LLVMValueRef func,
191 gl_shader_stage stage)
192 {
193 enum radeon_llvm_calling_convention calling_conv;
194
195 switch (stage) {
196 case MESA_SHADER_VERTEX:
197 case MESA_SHADER_TESS_EVAL:
198 calling_conv = RADEON_LLVM_AMDGPU_VS;
199 break;
200 case MESA_SHADER_GEOMETRY:
201 calling_conv = RADEON_LLVM_AMDGPU_GS;
202 break;
203 case MESA_SHADER_TESS_CTRL:
204 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
205 break;
206 case MESA_SHADER_FRAGMENT:
207 calling_conv = RADEON_LLVM_AMDGPU_PS;
208 break;
209 case MESA_SHADER_COMPUTE:
210 calling_conv = RADEON_LLVM_AMDGPU_CS;
211 break;
212 default:
213 unreachable("Unhandle shader type");
214 }
215
216 LLVMSetFunctionCallConv(func, calling_conv);
217 }
218
219 #define MAX_ARGS 23
220 struct arg_info {
221 LLVMTypeRef types[MAX_ARGS];
222 LLVMValueRef *assign[MAX_ARGS];
223 unsigned array_params_mask;
224 uint8_t count;
225 uint8_t sgpr_count;
226 uint8_t num_sgprs_used;
227 uint8_t num_vgprs_used;
228 };
229
230 enum ac_arg_regfile {
231 ARG_SGPR,
232 ARG_VGPR,
233 };
234
235 static void
236 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
237 LLVMValueRef *param_ptr)
238 {
239 assert(info->count < MAX_ARGS);
240
241 info->assign[info->count] = param_ptr;
242 info->types[info->count] = type;
243 info->count++;
244
245 if (regfile == ARG_SGPR) {
246 info->num_sgprs_used += ac_get_type_size(type) / 4;
247 info->sgpr_count++;
248 } else {
249 assert(regfile == ARG_VGPR);
250 info->num_vgprs_used += ac_get_type_size(type) / 4;
251 }
252 }
253
254 static inline void
255 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
256 {
257 info->array_params_mask |= (1 << info->count);
258 add_arg(info, ARG_SGPR, type, param_ptr);
259 }
260
261 static void assign_arguments(LLVMValueRef main_function,
262 struct arg_info *info)
263 {
264 unsigned i;
265 for (i = 0; i < info->count; i++) {
266 if (info->assign[i])
267 *info->assign[i] = LLVMGetParam(main_function, i);
268 }
269 }
270
271 static LLVMValueRef
272 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
273 LLVMBuilderRef builder, LLVMTypeRef *return_types,
274 unsigned num_return_elems,
275 struct arg_info *args,
276 unsigned max_workgroup_size,
277 bool unsafe_math)
278 {
279 LLVMTypeRef main_function_type, ret_type;
280 LLVMBasicBlockRef main_function_body;
281
282 if (num_return_elems)
283 ret_type = LLVMStructTypeInContext(ctx, return_types,
284 num_return_elems, true);
285 else
286 ret_type = LLVMVoidTypeInContext(ctx);
287
288 /* Setup the function */
289 main_function_type =
290 LLVMFunctionType(ret_type, args->types, args->count, 0);
291 LLVMValueRef main_function =
292 LLVMAddFunction(module, "main", main_function_type);
293 main_function_body =
294 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
295 LLVMPositionBuilderAtEnd(builder, main_function_body);
296
297 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
298 for (unsigned i = 0; i < args->sgpr_count; ++i) {
299 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
300
301 if (args->array_params_mask & (1 << i)) {
302 LLVMValueRef P = LLVMGetParam(main_function, i);
303 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
304 ac_add_attr_dereferenceable(P, UINT64_MAX);
305 }
306 }
307
308 if (max_workgroup_size) {
309 ac_llvm_add_target_dep_function_attr(main_function,
310 "amdgpu-max-work-group-size",
311 max_workgroup_size);
312 }
313 if (unsafe_math) {
314 /* These were copied from some LLVM test. */
315 LLVMAddTargetDependentFunctionAttr(main_function,
316 "less-precise-fpmad",
317 "true");
318 LLVMAddTargetDependentFunctionAttr(main_function,
319 "no-infs-fp-math",
320 "true");
321 LLVMAddTargetDependentFunctionAttr(main_function,
322 "no-nans-fp-math",
323 "true");
324 LLVMAddTargetDependentFunctionAttr(main_function,
325 "unsafe-fp-math",
326 "true");
327 LLVMAddTargetDependentFunctionAttr(main_function,
328 "no-signed-zeros-fp-math",
329 "true");
330 }
331 return main_function;
332 }
333
334 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
335 {
336 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
337 type = LLVMGetElementType(type);
338
339 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
340 return LLVMGetIntTypeWidth(type);
341
342 if (type == ctx->f16)
343 return 16;
344 if (type == ctx->f32)
345 return 32;
346 if (type == ctx->f64)
347 return 64;
348
349 unreachable("Unhandled type kind in get_elem_bits");
350 }
351
352 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
353 LLVMValueRef param, unsigned rshift,
354 unsigned bitwidth)
355 {
356 LLVMValueRef value = param;
357 if (rshift)
358 value = LLVMBuildLShr(ctx->builder, value,
359 LLVMConstInt(ctx->i32, rshift, false), "");
360
361 if (rshift + bitwidth < 32) {
362 unsigned mask = (1 << bitwidth) - 1;
363 value = LLVMBuildAnd(ctx->builder, value,
364 LLVMConstInt(ctx->i32, mask, false), "");
365 }
366 return value;
367 }
368
369 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
370 {
371 switch (ctx->stage) {
372 case MESA_SHADER_TESS_CTRL:
373 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
374 case MESA_SHADER_TESS_EVAL:
375 return ctx->tes_rel_patch_id;
376 break;
377 default:
378 unreachable("Illegal stage");
379 }
380 }
381
382 /* Tessellation shaders pass outputs to the next shader using LDS.
383 *
384 * LS outputs = TCS inputs
385 * TCS outputs = TES inputs
386 *
387 * The LDS layout is:
388 * - TCS inputs for patch 0
389 * - TCS inputs for patch 1
390 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
391 * - ...
392 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
393 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
394 * - TCS outputs for patch 1
395 * - Per-patch TCS outputs for patch 1
396 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
397 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
398 * - ...
399 *
400 * All three shaders VS(LS), TCS, TES share the same LDS space.
401 */
402 static LLVMValueRef
403 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
404 {
405 if (ctx->stage == MESA_SHADER_VERTEX)
406 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
407 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
408 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
409 else {
410 assert(0);
411 return NULL;
412 }
413 }
414
415 static LLVMValueRef
416 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
417 {
418 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
419 }
420
421 static LLVMValueRef
422 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
423 {
424 return LLVMBuildMul(ctx->builder,
425 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
426 LLVMConstInt(ctx->ac.i32, 4, false), "");
427 }
428
429 static LLVMValueRef
430 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
431 {
432 return LLVMBuildMul(ctx->builder,
433 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
434 LLVMConstInt(ctx->ac.i32, 4, false), "");
435 }
436
437 static LLVMValueRef
438 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
439 {
440 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
441 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
442
443 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
444 }
445
446 static LLVMValueRef
447 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
448 {
449 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
450 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
451 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
452
453 return LLVMBuildAdd(ctx->builder, patch0_offset,
454 LLVMBuildMul(ctx->builder, patch_stride,
455 rel_patch_id, ""),
456 "");
457 }
458
459 static LLVMValueRef
460 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
461 {
462 LLVMValueRef patch0_patch_data_offset =
463 get_tcs_out_patch0_patch_data_offset(ctx);
464 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
465 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
466
467 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
468 LLVMBuildMul(ctx->builder, patch_stride,
469 rel_patch_id, ""),
470 "");
471 }
472
473 static void
474 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
475 uint32_t indirect_offset)
476 {
477 ud_info->sgpr_idx = *sgpr_idx;
478 ud_info->num_sgprs = num_sgprs;
479 ud_info->indirect = indirect_offset > 0;
480 ud_info->indirect_offset = indirect_offset;
481 *sgpr_idx += num_sgprs;
482 }
483
484 static void
485 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
486 uint8_t num_sgprs)
487 {
488 struct ac_userdata_info *ud_info =
489 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
490 assert(ud_info);
491
492 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
493 }
494
495 static void
496 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
497 uint32_t indirect_offset)
498 {
499 struct ac_userdata_info *ud_info =
500 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
501 assert(ud_info);
502
503 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
504 }
505
506 struct user_sgpr_info {
507 bool need_ring_offsets;
508 uint8_t sgpr_count;
509 bool indirect_all_descriptor_sets;
510 };
511
512 static bool needs_view_index_sgpr(struct nir_to_llvm_context *ctx,
513 gl_shader_stage stage)
514 {
515 switch (stage) {
516 case MESA_SHADER_VERTEX:
517 if (ctx->shader_info->info.needs_multiview_view_index ||
518 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
519 return true;
520 break;
521 case MESA_SHADER_TESS_EVAL:
522 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
523 return true;
524 break;
525 case MESA_SHADER_GEOMETRY:
526 case MESA_SHADER_TESS_CTRL:
527 if (ctx->shader_info->info.needs_multiview_view_index)
528 return true;
529 break;
530 default:
531 break;
532 }
533 return false;
534 }
535
536 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
537 gl_shader_stage stage,
538 bool needs_view_index,
539 struct user_sgpr_info *user_sgpr_info)
540 {
541 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
542
543 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
544 if (stage == MESA_SHADER_GEOMETRY ||
545 stage == MESA_SHADER_VERTEX ||
546 stage == MESA_SHADER_TESS_CTRL ||
547 stage == MESA_SHADER_TESS_EVAL ||
548 ctx->is_gs_copy_shader)
549 user_sgpr_info->need_ring_offsets = true;
550
551 if (stage == MESA_SHADER_FRAGMENT &&
552 ctx->shader_info->info.ps.needs_sample_positions)
553 user_sgpr_info->need_ring_offsets = true;
554
555 /* 2 user sgprs will nearly always be allocated for scratch/rings */
556 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
557 user_sgpr_info->sgpr_count += 2;
558 }
559
560 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
561 switch (stage) {
562 case MESA_SHADER_COMPUTE:
563 if (ctx->shader_info->info.cs.uses_grid_size)
564 user_sgpr_info->sgpr_count += 3;
565 break;
566 case MESA_SHADER_FRAGMENT:
567 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
568 break;
569 case MESA_SHADER_VERTEX:
570 if (!ctx->is_gs_copy_shader) {
571 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
572 if (ctx->shader_info->info.vs.needs_draw_id) {
573 user_sgpr_info->sgpr_count += 3;
574 } else {
575 user_sgpr_info->sgpr_count += 2;
576 }
577 }
578 if (ctx->options->key.vs.as_ls)
579 user_sgpr_info->sgpr_count++;
580 break;
581 case MESA_SHADER_TESS_CTRL:
582 user_sgpr_info->sgpr_count += 4;
583 break;
584 case MESA_SHADER_TESS_EVAL:
585 user_sgpr_info->sgpr_count += 1;
586 break;
587 case MESA_SHADER_GEOMETRY:
588 user_sgpr_info->sgpr_count += 2;
589 break;
590 default:
591 break;
592 }
593
594 if (needs_view_index)
595 user_sgpr_info->sgpr_count++;
596
597 if (ctx->shader_info->info.loads_push_constants)
598 user_sgpr_info->sgpr_count += 2;
599
600 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
601 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
602
603 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
604 user_sgpr_info->sgpr_count += 2;
605 user_sgpr_info->indirect_all_descriptor_sets = true;
606 } else {
607 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
608 }
609 }
610
611 static void
612 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
613 gl_shader_stage stage,
614 bool has_previous_stage,
615 gl_shader_stage previous_stage,
616 const struct user_sgpr_info *user_sgpr_info,
617 struct arg_info *args,
618 LLVMValueRef *desc_sets)
619 {
620 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
621 unsigned num_sets = ctx->options->layout ?
622 ctx->options->layout->num_sets : 0;
623 unsigned stage_mask = 1 << stage;
624
625 if (has_previous_stage)
626 stage_mask |= 1 << previous_stage;
627
628 /* 1 for each descriptor set */
629 if (!user_sgpr_info->indirect_all_descriptor_sets) {
630 for (unsigned i = 0; i < num_sets; ++i) {
631 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
632 add_array_arg(args, type,
633 &ctx->descriptor_sets[i]);
634 }
635 }
636 } else {
637 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
638 }
639
640 if (ctx->shader_info->info.loads_push_constants) {
641 /* 1 for push constants and dynamic descriptors */
642 add_array_arg(args, type, &ctx->push_constants);
643 }
644 }
645
646 static void
647 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
648 gl_shader_stage stage,
649 bool has_previous_stage,
650 gl_shader_stage previous_stage,
651 struct arg_info *args)
652 {
653 if (!ctx->is_gs_copy_shader &&
654 (stage == MESA_SHADER_VERTEX ||
655 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
656 if (ctx->shader_info->info.vs.has_vertex_buffers) {
657 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
658 &ctx->vertex_buffers);
659 }
660 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
661 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
662 if (ctx->shader_info->info.vs.needs_draw_id) {
663 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
664 }
665 }
666 }
667
668 static void
669 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
670 {
671 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
672 if (!ctx->is_gs_copy_shader) {
673 if (ctx->options->key.vs.as_ls) {
674 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
675 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
676 } else {
677 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
678 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
679 }
680 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
681 }
682 }
683
684 static void
685 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
686 {
687 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
688 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
689 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
690 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
691 }
692
693 static void
694 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
695 bool has_previous_stage, gl_shader_stage previous_stage,
696 const struct user_sgpr_info *user_sgpr_info,
697 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
698 {
699 unsigned num_sets = ctx->options->layout ?
700 ctx->options->layout->num_sets : 0;
701 unsigned stage_mask = 1 << stage;
702
703 if (has_previous_stage)
704 stage_mask |= 1 << previous_stage;
705
706 if (!user_sgpr_info->indirect_all_descriptor_sets) {
707 for (unsigned i = 0; i < num_sets; ++i) {
708 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
709 set_loc_desc(ctx, i, user_sgpr_idx, 0);
710 } else
711 ctx->descriptor_sets[i] = NULL;
712 }
713 } else {
714 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
715 user_sgpr_idx, 2);
716
717 for (unsigned i = 0; i < num_sets; ++i) {
718 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
719 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
720 ctx->descriptor_sets[i] =
721 ac_build_load_to_sgpr(&ctx->ac,
722 desc_sets,
723 LLVMConstInt(ctx->ac.i32, i, false));
724
725 } else
726 ctx->descriptor_sets[i] = NULL;
727 }
728 ctx->shader_info->need_indirect_descriptor_sets = true;
729 }
730
731 if (ctx->shader_info->info.loads_push_constants) {
732 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
733 }
734 }
735
736 static void
737 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
738 gl_shader_stage stage, bool has_previous_stage,
739 gl_shader_stage previous_stage,
740 uint8_t *user_sgpr_idx)
741 {
742 if (!ctx->is_gs_copy_shader &&
743 (stage == MESA_SHADER_VERTEX ||
744 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
745 if (ctx->shader_info->info.vs.has_vertex_buffers) {
746 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
747 user_sgpr_idx, 2);
748 }
749
750 unsigned vs_num = 2;
751 if (ctx->shader_info->info.vs.needs_draw_id)
752 vs_num++;
753
754 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
755 user_sgpr_idx, vs_num);
756 }
757 }
758
759 static void create_function(struct nir_to_llvm_context *ctx,
760 gl_shader_stage stage,
761 bool has_previous_stage,
762 gl_shader_stage previous_stage)
763 {
764 uint8_t user_sgpr_idx;
765 struct user_sgpr_info user_sgpr_info;
766 struct arg_info args = {};
767 LLVMValueRef desc_sets;
768 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
769 allocate_user_sgprs(ctx, stage, needs_view_index, &user_sgpr_info);
770
771 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
772 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
773 &ctx->ring_offsets);
774 }
775
776 switch (stage) {
777 case MESA_SHADER_COMPUTE:
778 declare_global_input_sgprs(ctx, stage, has_previous_stage,
779 previous_stage, &user_sgpr_info,
780 &args, &desc_sets);
781
782 if (ctx->shader_info->info.cs.uses_grid_size) {
783 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
784 &ctx->num_work_groups);
785 }
786
787 for (int i = 0; i < 3; i++) {
788 ctx->abi.workgroup_ids[i] = NULL;
789 if (ctx->shader_info->info.cs.uses_block_id[i]) {
790 add_arg(&args, ARG_SGPR, ctx->ac.i32,
791 &ctx->abi.workgroup_ids[i]);
792 }
793 }
794
795 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
796 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
797 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
798 &ctx->local_invocation_ids);
799 break;
800 case MESA_SHADER_VERTEX:
801 declare_global_input_sgprs(ctx, stage, has_previous_stage,
802 previous_stage, &user_sgpr_info,
803 &args, &desc_sets);
804 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
805 previous_stage, &args);
806
807 if (needs_view_index)
808 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
809 if (ctx->options->key.vs.as_es)
810 add_arg(&args, ARG_SGPR, ctx->ac.i32,
811 &ctx->es2gs_offset);
812 else if (ctx->options->key.vs.as_ls)
813 add_arg(&args, ARG_SGPR, ctx->ac.i32,
814 &ctx->ls_out_layout);
815
816 declare_vs_input_vgprs(ctx, &args);
817 break;
818 case MESA_SHADER_TESS_CTRL:
819 if (has_previous_stage) {
820 // First 6 system regs
821 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
822 add_arg(&args, ARG_SGPR, ctx->ac.i32,
823 &ctx->merged_wave_info);
824 add_arg(&args, ARG_SGPR, ctx->ac.i32,
825 &ctx->tess_factor_offset);
826
827 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
828 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
829 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
830
831 declare_global_input_sgprs(ctx, stage,
832 has_previous_stage,
833 previous_stage,
834 &user_sgpr_info, &args,
835 &desc_sets);
836 declare_vs_specific_input_sgprs(ctx, stage,
837 has_previous_stage,
838 previous_stage, &args);
839
840 add_arg(&args, ARG_SGPR, ctx->ac.i32,
841 &ctx->ls_out_layout);
842
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->tcs_offchip_layout);
845 add_arg(&args, ARG_SGPR, ctx->ac.i32,
846 &ctx->tcs_out_offsets);
847 add_arg(&args, ARG_SGPR, ctx->ac.i32,
848 &ctx->tcs_out_layout);
849 add_arg(&args, ARG_SGPR, ctx->ac.i32,
850 &ctx->tcs_in_layout);
851 if (needs_view_index)
852 add_arg(&args, ARG_SGPR, ctx->ac.i32,
853 &ctx->view_index);
854
855 add_arg(&args, ARG_VGPR, ctx->ac.i32,
856 &ctx->abi.tcs_patch_id);
857 add_arg(&args, ARG_VGPR, ctx->ac.i32,
858 &ctx->abi.tcs_rel_ids);
859
860 declare_vs_input_vgprs(ctx, &args);
861 } else {
862 declare_global_input_sgprs(ctx, stage,
863 has_previous_stage,
864 previous_stage,
865 &user_sgpr_info, &args,
866 &desc_sets);
867
868 add_arg(&args, ARG_SGPR, ctx->ac.i32,
869 &ctx->tcs_offchip_layout);
870 add_arg(&args, ARG_SGPR, ctx->ac.i32,
871 &ctx->tcs_out_offsets);
872 add_arg(&args, ARG_SGPR, ctx->ac.i32,
873 &ctx->tcs_out_layout);
874 add_arg(&args, ARG_SGPR, ctx->ac.i32,
875 &ctx->tcs_in_layout);
876 if (needs_view_index)
877 add_arg(&args, ARG_SGPR, ctx->ac.i32,
878 &ctx->view_index);
879
880 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
881 add_arg(&args, ARG_SGPR, ctx->ac.i32,
882 &ctx->tess_factor_offset);
883 add_arg(&args, ARG_VGPR, ctx->ac.i32,
884 &ctx->abi.tcs_patch_id);
885 add_arg(&args, ARG_VGPR, ctx->ac.i32,
886 &ctx->abi.tcs_rel_ids);
887 }
888 break;
889 case MESA_SHADER_TESS_EVAL:
890 declare_global_input_sgprs(ctx, stage, has_previous_stage,
891 previous_stage, &user_sgpr_info,
892 &args, &desc_sets);
893
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
895 if (needs_view_index)
896 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
897
898 if (ctx->options->key.tes.as_es) {
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
900 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
901 add_arg(&args, ARG_SGPR, ctx->ac.i32,
902 &ctx->es2gs_offset);
903 } else {
904 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
905 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
906 }
907 declare_tes_input_vgprs(ctx, &args);
908 break;
909 case MESA_SHADER_GEOMETRY:
910 if (has_previous_stage) {
911 // First 6 system regs
912 add_arg(&args, ARG_SGPR, ctx->ac.i32,
913 &ctx->gs2vs_offset);
914 add_arg(&args, ARG_SGPR, ctx->ac.i32,
915 &ctx->merged_wave_info);
916 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
917
918 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
919 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
920 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
921
922 declare_global_input_sgprs(ctx, stage,
923 has_previous_stage,
924 previous_stage,
925 &user_sgpr_info, &args,
926 &desc_sets);
927
928 if (previous_stage == MESA_SHADER_TESS_EVAL) {
929 add_arg(&args, ARG_SGPR, ctx->ac.i32,
930 &ctx->tcs_offchip_layout);
931 } else {
932 declare_vs_specific_input_sgprs(ctx, stage,
933 has_previous_stage,
934 previous_stage,
935 &args);
936 }
937
938 add_arg(&args, ARG_SGPR, ctx->ac.i32,
939 &ctx->gsvs_ring_stride);
940 add_arg(&args, ARG_SGPR, ctx->ac.i32,
941 &ctx->gsvs_num_entries);
942 if (needs_view_index)
943 add_arg(&args, ARG_SGPR, ctx->ac.i32,
944 &ctx->view_index);
945
946 add_arg(&args, ARG_VGPR, ctx->ac.i32,
947 &ctx->gs_vtx_offset[0]);
948 add_arg(&args, ARG_VGPR, ctx->ac.i32,
949 &ctx->gs_vtx_offset[2]);
950 add_arg(&args, ARG_VGPR, ctx->ac.i32,
951 &ctx->abi.gs_prim_id);
952 add_arg(&args, ARG_VGPR, ctx->ac.i32,
953 &ctx->abi.gs_invocation_id);
954 add_arg(&args, ARG_VGPR, ctx->ac.i32,
955 &ctx->gs_vtx_offset[4]);
956
957 if (previous_stage == MESA_SHADER_VERTEX) {
958 declare_vs_input_vgprs(ctx, &args);
959 } else {
960 declare_tes_input_vgprs(ctx, &args);
961 }
962 } else {
963 declare_global_input_sgprs(ctx, stage,
964 has_previous_stage,
965 previous_stage,
966 &user_sgpr_info, &args,
967 &desc_sets);
968
969 add_arg(&args, ARG_SGPR, ctx->ac.i32,
970 &ctx->gsvs_ring_stride);
971 add_arg(&args, ARG_SGPR, ctx->ac.i32,
972 &ctx->gsvs_num_entries);
973 if (needs_view_index)
974 add_arg(&args, ARG_SGPR, ctx->ac.i32,
975 &ctx->view_index);
976
977 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
978 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
979 add_arg(&args, ARG_VGPR, ctx->ac.i32,
980 &ctx->gs_vtx_offset[0]);
981 add_arg(&args, ARG_VGPR, ctx->ac.i32,
982 &ctx->gs_vtx_offset[1]);
983 add_arg(&args, ARG_VGPR, ctx->ac.i32,
984 &ctx->abi.gs_prim_id);
985 add_arg(&args, ARG_VGPR, ctx->ac.i32,
986 &ctx->gs_vtx_offset[2]);
987 add_arg(&args, ARG_VGPR, ctx->ac.i32,
988 &ctx->gs_vtx_offset[3]);
989 add_arg(&args, ARG_VGPR, ctx->ac.i32,
990 &ctx->gs_vtx_offset[4]);
991 add_arg(&args, ARG_VGPR, ctx->ac.i32,
992 &ctx->gs_vtx_offset[5]);
993 add_arg(&args, ARG_VGPR, ctx->ac.i32,
994 &ctx->abi.gs_invocation_id);
995 }
996 break;
997 case MESA_SHADER_FRAGMENT:
998 declare_global_input_sgprs(ctx, stage, has_previous_stage,
999 previous_stage, &user_sgpr_info,
1000 &args, &desc_sets);
1001
1002 if (ctx->shader_info->info.ps.needs_sample_positions)
1003 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1004 &ctx->sample_pos_offset);
1005
1006 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1009 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1010 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1011 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1012 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1013 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1014 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1015 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1016 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1017 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1018 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1019 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1020 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1021 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1022 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1023 break;
1024 default:
1025 unreachable("Shader stage not implemented");
1026 }
1027
1028 ctx->main_function = create_llvm_function(
1029 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1030 ctx->max_workgroup_size,
1031 ctx->options->unsafe_math);
1032 set_llvm_calling_convention(ctx->main_function, stage);
1033
1034
1035 ctx->shader_info->num_input_vgprs = 0;
1036 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1037
1038 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1039
1040 if (ctx->stage != MESA_SHADER_FRAGMENT)
1041 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1042
1043 assign_arguments(ctx->main_function, &args);
1044
1045 user_sgpr_idx = 0;
1046
1047 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1048 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1049 &user_sgpr_idx, 2);
1050 if (ctx->options->supports_spill) {
1051 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1052 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1053 NULL, 0, AC_FUNC_ATTR_READNONE);
1054 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1055 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1056 }
1057 }
1058
1059 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1060 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1061 if (has_previous_stage)
1062 user_sgpr_idx = 0;
1063
1064 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1065 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1066
1067 switch (stage) {
1068 case MESA_SHADER_COMPUTE:
1069 if (ctx->shader_info->info.cs.uses_grid_size) {
1070 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1071 &user_sgpr_idx, 3);
1072 }
1073 break;
1074 case MESA_SHADER_VERTEX:
1075 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1076 previous_stage, &user_sgpr_idx);
1077 if (ctx->view_index)
1078 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1079 if (ctx->options->key.vs.as_ls) {
1080 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1081 &user_sgpr_idx, 1);
1082 }
1083 if (ctx->options->key.vs.as_ls)
1084 ac_declare_lds_as_pointer(&ctx->ac);
1085 break;
1086 case MESA_SHADER_TESS_CTRL:
1087 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1088 previous_stage, &user_sgpr_idx);
1089 if (has_previous_stage)
1090 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1091 &user_sgpr_idx, 1);
1092 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1093 if (ctx->view_index)
1094 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1095 ac_declare_lds_as_pointer(&ctx->ac);
1096 break;
1097 case MESA_SHADER_TESS_EVAL:
1098 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1099 if (ctx->view_index)
1100 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1101 break;
1102 case MESA_SHADER_GEOMETRY:
1103 if (has_previous_stage) {
1104 if (previous_stage == MESA_SHADER_VERTEX)
1105 set_vs_specific_input_locs(ctx, stage,
1106 has_previous_stage,
1107 previous_stage,
1108 &user_sgpr_idx);
1109 else
1110 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1111 &user_sgpr_idx, 1);
1112 }
1113 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1114 &user_sgpr_idx, 2);
1115 if (ctx->view_index)
1116 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1117 if (has_previous_stage)
1118 ac_declare_lds_as_pointer(&ctx->ac);
1119 break;
1120 case MESA_SHADER_FRAGMENT:
1121 if (ctx->shader_info->info.ps.needs_sample_positions) {
1122 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1123 &user_sgpr_idx, 1);
1124 }
1125 break;
1126 default:
1127 unreachable("Shader stage not implemented");
1128 }
1129
1130 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1131 }
1132
1133 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1134 LLVMValueRef value, unsigned count)
1135 {
1136 unsigned num_components = ac_get_llvm_num_components(value);
1137 if (count == num_components)
1138 return value;
1139
1140 LLVMValueRef masks[] = {
1141 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1142 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1143
1144 if (count == 1)
1145 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1146 "");
1147
1148 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1149 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1150 }
1151
1152 static void
1153 build_store_values_extended(struct ac_llvm_context *ac,
1154 LLVMValueRef *values,
1155 unsigned value_count,
1156 unsigned value_stride,
1157 LLVMValueRef vec)
1158 {
1159 LLVMBuilderRef builder = ac->builder;
1160 unsigned i;
1161
1162 for (i = 0; i < value_count; i++) {
1163 LLVMValueRef ptr = values[i * value_stride];
1164 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1165 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1166 LLVMBuildStore(builder, value, ptr);
1167 }
1168 }
1169
1170 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1171 const nir_ssa_def *def)
1172 {
1173 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1174 if (def->num_components > 1) {
1175 type = LLVMVectorType(type, def->num_components);
1176 }
1177 return type;
1178 }
1179
1180 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1181 {
1182 assert(src.is_ssa);
1183 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1184 return (LLVMValueRef)entry->data;
1185 }
1186
1187
1188 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1189 const struct nir_block *b)
1190 {
1191 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1192 return (LLVMBasicBlockRef)entry->data;
1193 }
1194
1195 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1196 nir_alu_src src,
1197 unsigned num_components)
1198 {
1199 LLVMValueRef value = get_src(ctx, src.src);
1200 bool need_swizzle = false;
1201
1202 assert(value);
1203 LLVMTypeRef type = LLVMTypeOf(value);
1204 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1205 ? LLVMGetVectorSize(type)
1206 : 1;
1207
1208 for (unsigned i = 0; i < num_components; ++i) {
1209 assert(src.swizzle[i] < src_components);
1210 if (src.swizzle[i] != i)
1211 need_swizzle = true;
1212 }
1213
1214 if (need_swizzle || num_components != src_components) {
1215 LLVMValueRef masks[] = {
1216 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1217 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1218 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1219 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1220
1221 if (src_components > 1 && num_components == 1) {
1222 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1223 masks[0], "");
1224 } else if (src_components == 1 && num_components > 1) {
1225 LLVMValueRef values[] = {value, value, value, value};
1226 value = ac_build_gather_values(&ctx->ac, values, num_components);
1227 } else {
1228 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1229 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1230 swizzle, "");
1231 }
1232 }
1233 assert(!src.negate);
1234 assert(!src.abs);
1235 return value;
1236 }
1237
1238 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1239 LLVMIntPredicate pred, LLVMValueRef src0,
1240 LLVMValueRef src1)
1241 {
1242 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1243 return LLVMBuildSelect(ctx->builder, result,
1244 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1245 ctx->i32_0, "");
1246 }
1247
1248 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1249 LLVMRealPredicate pred, LLVMValueRef src0,
1250 LLVMValueRef src1)
1251 {
1252 LLVMValueRef result;
1253 src0 = ac_to_float(ctx, src0);
1254 src1 = ac_to_float(ctx, src1);
1255 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1256 return LLVMBuildSelect(ctx->builder, result,
1257 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1258 ctx->i32_0, "");
1259 }
1260
1261 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1262 const char *intrin,
1263 LLVMTypeRef result_type,
1264 LLVMValueRef src0)
1265 {
1266 char name[64];
1267 LLVMValueRef params[] = {
1268 ac_to_float(ctx, src0),
1269 };
1270
1271 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1272 get_elem_bits(ctx, result_type));
1273 assert(length < sizeof(name));
1274 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1275 }
1276
1277 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1278 const char *intrin,
1279 LLVMTypeRef result_type,
1280 LLVMValueRef src0, LLVMValueRef src1)
1281 {
1282 char name[64];
1283 LLVMValueRef params[] = {
1284 ac_to_float(ctx, src0),
1285 ac_to_float(ctx, src1),
1286 };
1287
1288 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1289 get_elem_bits(ctx, result_type));
1290 assert(length < sizeof(name));
1291 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1292 }
1293
1294 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1295 const char *intrin,
1296 LLVMTypeRef result_type,
1297 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1298 {
1299 char name[64];
1300 LLVMValueRef params[] = {
1301 ac_to_float(ctx, src0),
1302 ac_to_float(ctx, src1),
1303 ac_to_float(ctx, src2),
1304 };
1305
1306 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1307 get_elem_bits(ctx, result_type));
1308 assert(length < sizeof(name));
1309 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1310 }
1311
1312 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1313 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1314 {
1315 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1316 ctx->i32_0, "");
1317 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1318 }
1319
1320 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1321 LLVMIntPredicate pred,
1322 LLVMValueRef src0, LLVMValueRef src1)
1323 {
1324 return LLVMBuildSelect(ctx->builder,
1325 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1326 src0,
1327 src1, "");
1328
1329 }
1330 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1331 LLVMValueRef src0)
1332 {
1333 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1334 LLVMBuildNeg(ctx->builder, src0, ""));
1335 }
1336
1337 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1338 LLVMValueRef src0,
1339 unsigned bitsize)
1340 {
1341 LLVMValueRef cmp, val, zero, one;
1342 LLVMTypeRef type;
1343
1344 if (bitsize == 32) {
1345 type = ctx->f32;
1346 zero = ctx->f32_0;
1347 one = ctx->f32_1;
1348 } else {
1349 type = ctx->f64;
1350 zero = ctx->f64_0;
1351 one = ctx->f64_1;
1352 }
1353
1354 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1355 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1356 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1357 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1358 return val;
1359 }
1360
1361 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1362 LLVMValueRef src0, unsigned bitsize)
1363 {
1364 LLVMValueRef cmp, val, zero, one;
1365 LLVMTypeRef type;
1366
1367 if (bitsize == 32) {
1368 type = ctx->i32;
1369 zero = ctx->i32_0;
1370 one = ctx->i32_1;
1371 } else {
1372 type = ctx->i64;
1373 zero = ctx->i64_0;
1374 one = ctx->i64_1;
1375 }
1376
1377 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1378 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1379 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1380 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1381 return val;
1382 }
1383
1384 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1385 LLVMValueRef src0, unsigned bitsize)
1386 {
1387 LLVMTypeRef type;
1388 char *intr;
1389
1390 if (bitsize == 32) {
1391 intr = "llvm.floor.f32";
1392 type = ctx->f32;
1393 } else {
1394 intr = "llvm.floor.f64";
1395 type = ctx->f64;
1396 }
1397
1398 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1399 LLVMValueRef params[] = {
1400 fsrc0,
1401 };
1402 LLVMValueRef floor = ac_build_intrinsic(ctx, intr, type, params, 1,
1403 AC_FUNC_ATTR_READNONE);
1404 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1405 }
1406
1407 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1408 const char *intrin,
1409 LLVMValueRef src0, LLVMValueRef src1)
1410 {
1411 LLVMTypeRef ret_type;
1412 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1413 LLVMValueRef res;
1414 LLVMValueRef params[] = { src0, src1 };
1415 ret_type = LLVMStructTypeInContext(ctx->context, types,
1416 2, true);
1417
1418 res = ac_build_intrinsic(ctx, intrin, ret_type,
1419 params, 2, AC_FUNC_ATTR_READNONE);
1420
1421 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1422 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1423 return res;
1424 }
1425
1426 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1427 LLVMValueRef src0)
1428 {
1429 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1430 }
1431
1432 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1433 LLVMValueRef src0)
1434 {
1435 src0 = ac_to_float(ctx, src0);
1436 return LLVMBuildSExt(ctx->builder,
1437 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1438 ctx->i32, "");
1439 }
1440
1441 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1442 LLVMValueRef src0,
1443 unsigned bitsize)
1444 {
1445 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1446
1447 if (bitsize == 32)
1448 return result;
1449
1450 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1451 }
1452
1453 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1454 LLVMValueRef src0)
1455 {
1456 return LLVMBuildSExt(ctx->builder,
1457 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1458 ctx->i32, "");
1459 }
1460
1461 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1462 LLVMValueRef src0)
1463 {
1464 LLVMValueRef result;
1465 LLVMValueRef cond = NULL;
1466
1467 src0 = ac_to_float(&ctx->ac, src0);
1468 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1469
1470 if (ctx->options->chip_class >= VI) {
1471 LLVMValueRef args[2];
1472 /* Check if the result is a denormal - and flush to 0 if so. */
1473 args[0] = result;
1474 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1475 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1476 }
1477
1478 /* need to convert back up to f32 */
1479 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1480
1481 if (ctx->options->chip_class >= VI)
1482 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1483 else {
1484 /* for SI/CIK */
1485 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1486 * so compare the result and flush to 0 if it's smaller.
1487 */
1488 LLVMValueRef temp, cond2;
1489 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1490 ctx->ac.f32, result);
1491 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1492 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1493 temp, "");
1494 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1495 temp, ctx->ac.f32_0, "");
1496 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1497 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1498 }
1499 return result;
1500 }
1501
1502 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1503 LLVMValueRef src0, LLVMValueRef src1)
1504 {
1505 LLVMValueRef dst64, result;
1506 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1507 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1508
1509 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1510 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1511 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1512 return result;
1513 }
1514
1515 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1516 LLVMValueRef src0, LLVMValueRef src1)
1517 {
1518 LLVMValueRef dst64, result;
1519 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1520 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1521
1522 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1523 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1524 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1525 return result;
1526 }
1527
1528 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1529 bool is_signed,
1530 const LLVMValueRef srcs[3])
1531 {
1532 LLVMValueRef result;
1533 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1534
1535 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1536 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1537 return result;
1538 }
1539
1540 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1541 LLVMValueRef src0, LLVMValueRef src1,
1542 LLVMValueRef src2, LLVMValueRef src3)
1543 {
1544 LLVMValueRef bfi_args[3], result;
1545
1546 bfi_args[0] = LLVMBuildShl(ctx->builder,
1547 LLVMBuildSub(ctx->builder,
1548 LLVMBuildShl(ctx->builder,
1549 ctx->i32_1,
1550 src3, ""),
1551 ctx->i32_1, ""),
1552 src2, "");
1553 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1554 bfi_args[2] = src0;
1555
1556 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1557
1558 /* Calculate:
1559 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1560 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1561 */
1562 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1563 LLVMBuildAnd(ctx->builder, bfi_args[0],
1564 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1565
1566 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1567 return result;
1568 }
1569
1570 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1571 LLVMValueRef src0)
1572 {
1573 LLVMValueRef comp[2];
1574
1575 src0 = ac_to_float(ctx, src0);
1576 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1577 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1578
1579 return ac_build_cvt_pkrtz_f16(ctx, comp);
1580 }
1581
1582 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1583 LLVMValueRef src0)
1584 {
1585 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1586 LLVMValueRef temps[2], result, val;
1587 int i;
1588
1589 for (i = 0; i < 2; i++) {
1590 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1591 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1592 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1593 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1594 }
1595
1596 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1597 ctx->i32_0, "");
1598 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1599 ctx->i32_1, "");
1600 return result;
1601 }
1602
1603 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1604 nir_op op,
1605 LLVMValueRef src0)
1606 {
1607 unsigned mask;
1608 int idx;
1609 LLVMValueRef result;
1610
1611 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1612 mask = AC_TID_MASK_LEFT;
1613 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1614 mask = AC_TID_MASK_TOP;
1615 else
1616 mask = AC_TID_MASK_TOP_LEFT;
1617
1618 /* for DDX we want to next X pixel, DDY next Y pixel. */
1619 if (op == nir_op_fddx_fine ||
1620 op == nir_op_fddx_coarse ||
1621 op == nir_op_fddx)
1622 idx = 1;
1623 else
1624 idx = 2;
1625
1626 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1627 return result;
1628 }
1629
1630 /*
1631 * this takes an I,J coordinate pair,
1632 * and works out the X and Y derivatives.
1633 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1634 */
1635 static LLVMValueRef emit_ddxy_interp(
1636 struct ac_nir_context *ctx,
1637 LLVMValueRef interp_ij)
1638 {
1639 LLVMValueRef result[4], a;
1640 unsigned i;
1641
1642 for (i = 0; i < 2; i++) {
1643 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1644 LLVMConstInt(ctx->ac.i32, i, false), "");
1645 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1646 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1647 }
1648 return ac_build_gather_values(&ctx->ac, result, 4);
1649 }
1650
1651 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1652 {
1653 LLVMValueRef src[4], result = NULL;
1654 unsigned num_components = instr->dest.dest.ssa.num_components;
1655 unsigned src_components;
1656 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1657
1658 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1659 switch (instr->op) {
1660 case nir_op_vec2:
1661 case nir_op_vec3:
1662 case nir_op_vec4:
1663 src_components = 1;
1664 break;
1665 case nir_op_pack_half_2x16:
1666 src_components = 2;
1667 break;
1668 case nir_op_unpack_half_2x16:
1669 src_components = 1;
1670 break;
1671 default:
1672 src_components = num_components;
1673 break;
1674 }
1675 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1676 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1677
1678 switch (instr->op) {
1679 case nir_op_fmov:
1680 case nir_op_imov:
1681 result = src[0];
1682 break;
1683 case nir_op_fneg:
1684 src[0] = ac_to_float(&ctx->ac, src[0]);
1685 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1686 break;
1687 case nir_op_ineg:
1688 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1689 break;
1690 case nir_op_inot:
1691 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1692 break;
1693 case nir_op_iadd:
1694 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1695 break;
1696 case nir_op_fadd:
1697 src[0] = ac_to_float(&ctx->ac, src[0]);
1698 src[1] = ac_to_float(&ctx->ac, src[1]);
1699 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1700 break;
1701 case nir_op_fsub:
1702 src[0] = ac_to_float(&ctx->ac, src[0]);
1703 src[1] = ac_to_float(&ctx->ac, src[1]);
1704 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1705 break;
1706 case nir_op_isub:
1707 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1708 break;
1709 case nir_op_imul:
1710 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1711 break;
1712 case nir_op_imod:
1713 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1714 break;
1715 case nir_op_umod:
1716 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1717 break;
1718 case nir_op_fmod:
1719 src[0] = ac_to_float(&ctx->ac, src[0]);
1720 src[1] = ac_to_float(&ctx->ac, src[1]);
1721 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1722 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1723 ac_to_float_type(&ctx->ac, def_type), result);
1724 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1725 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1726 break;
1727 case nir_op_frem:
1728 src[0] = ac_to_float(&ctx->ac, src[0]);
1729 src[1] = ac_to_float(&ctx->ac, src[1]);
1730 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1731 break;
1732 case nir_op_irem:
1733 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1734 break;
1735 case nir_op_idiv:
1736 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1737 break;
1738 case nir_op_udiv:
1739 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1740 break;
1741 case nir_op_fmul:
1742 src[0] = ac_to_float(&ctx->ac, src[0]);
1743 src[1] = ac_to_float(&ctx->ac, src[1]);
1744 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1745 break;
1746 case nir_op_frcp:
1747 src[0] = ac_to_float(&ctx->ac, src[0]);
1748 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1749 src[0]);
1750 break;
1751 case nir_op_iand:
1752 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1753 break;
1754 case nir_op_ior:
1755 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1756 break;
1757 case nir_op_ixor:
1758 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1759 break;
1760 case nir_op_ishl:
1761 result = LLVMBuildShl(ctx->ac.builder, src[0],
1762 LLVMBuildZExt(ctx->ac.builder, src[1],
1763 LLVMTypeOf(src[0]), ""),
1764 "");
1765 break;
1766 case nir_op_ishr:
1767 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1768 LLVMBuildZExt(ctx->ac.builder, src[1],
1769 LLVMTypeOf(src[0]), ""),
1770 "");
1771 break;
1772 case nir_op_ushr:
1773 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1774 LLVMBuildZExt(ctx->ac.builder, src[1],
1775 LLVMTypeOf(src[0]), ""),
1776 "");
1777 break;
1778 case nir_op_ilt:
1779 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1780 break;
1781 case nir_op_ine:
1782 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1783 break;
1784 case nir_op_ieq:
1785 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1786 break;
1787 case nir_op_ige:
1788 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1789 break;
1790 case nir_op_ult:
1791 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1792 break;
1793 case nir_op_uge:
1794 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1795 break;
1796 case nir_op_feq:
1797 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1798 break;
1799 case nir_op_fne:
1800 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1801 break;
1802 case nir_op_flt:
1803 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1804 break;
1805 case nir_op_fge:
1806 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1807 break;
1808 case nir_op_fabs:
1809 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1810 ac_to_float_type(&ctx->ac, def_type), src[0]);
1811 break;
1812 case nir_op_iabs:
1813 result = emit_iabs(&ctx->ac, src[0]);
1814 break;
1815 case nir_op_imax:
1816 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1817 break;
1818 case nir_op_imin:
1819 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1820 break;
1821 case nir_op_umax:
1822 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1823 break;
1824 case nir_op_umin:
1825 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1826 break;
1827 case nir_op_isign:
1828 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1829 break;
1830 case nir_op_fsign:
1831 src[0] = ac_to_float(&ctx->ac, src[0]);
1832 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1833 break;
1834 case nir_op_ffloor:
1835 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1836 ac_to_float_type(&ctx->ac, def_type), src[0]);
1837 break;
1838 case nir_op_ftrunc:
1839 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1840 ac_to_float_type(&ctx->ac, def_type), src[0]);
1841 break;
1842 case nir_op_fceil:
1843 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1844 ac_to_float_type(&ctx->ac, def_type), src[0]);
1845 break;
1846 case nir_op_fround_even:
1847 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1848 ac_to_float_type(&ctx->ac, def_type),src[0]);
1849 break;
1850 case nir_op_ffract:
1851 result = emit_ffract(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1852 break;
1853 case nir_op_fsin:
1854 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1855 ac_to_float_type(&ctx->ac, def_type), src[0]);
1856 break;
1857 case nir_op_fcos:
1858 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1859 ac_to_float_type(&ctx->ac, def_type), src[0]);
1860 break;
1861 case nir_op_fsqrt:
1862 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1863 ac_to_float_type(&ctx->ac, def_type), src[0]);
1864 break;
1865 case nir_op_fexp2:
1866 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1867 ac_to_float_type(&ctx->ac, def_type), src[0]);
1868 break;
1869 case nir_op_flog2:
1870 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1871 ac_to_float_type(&ctx->ac, def_type), src[0]);
1872 break;
1873 case nir_op_frsq:
1874 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1875 ac_to_float_type(&ctx->ac, def_type), src[0]);
1876 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1877 result);
1878 break;
1879 case nir_op_fpow:
1880 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1881 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1882 break;
1883 case nir_op_fmax:
1884 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1885 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1886 if (ctx->ac.chip_class < GFX9 &&
1887 instr->dest.dest.ssa.bit_size == 32) {
1888 /* Only pre-GFX9 chips do not flush denorms. */
1889 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1890 ac_to_float_type(&ctx->ac, def_type),
1891 result);
1892 }
1893 break;
1894 case nir_op_fmin:
1895 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1896 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1897 if (ctx->ac.chip_class < GFX9 &&
1898 instr->dest.dest.ssa.bit_size == 32) {
1899 /* Only pre-GFX9 chips do not flush denorms. */
1900 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1901 ac_to_float_type(&ctx->ac, def_type),
1902 result);
1903 }
1904 break;
1905 case nir_op_ffma:
1906 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1907 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1908 break;
1909 case nir_op_ibitfield_extract:
1910 result = emit_bitfield_extract(&ctx->ac, true, src);
1911 break;
1912 case nir_op_ubitfield_extract:
1913 result = emit_bitfield_extract(&ctx->ac, false, src);
1914 break;
1915 case nir_op_bitfield_insert:
1916 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1917 break;
1918 case nir_op_bitfield_reverse:
1919 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1920 break;
1921 case nir_op_bit_count:
1922 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1923 break;
1924 case nir_op_vec2:
1925 case nir_op_vec3:
1926 case nir_op_vec4:
1927 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1928 src[i] = ac_to_integer(&ctx->ac, src[i]);
1929 result = ac_build_gather_values(&ctx->ac, src, num_components);
1930 break;
1931 case nir_op_f2i32:
1932 case nir_op_f2i64:
1933 src[0] = ac_to_float(&ctx->ac, src[0]);
1934 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1935 break;
1936 case nir_op_f2u32:
1937 case nir_op_f2u64:
1938 src[0] = ac_to_float(&ctx->ac, src[0]);
1939 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1940 break;
1941 case nir_op_i2f32:
1942 case nir_op_i2f64:
1943 src[0] = ac_to_integer(&ctx->ac, src[0]);
1944 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1945 break;
1946 case nir_op_u2f32:
1947 case nir_op_u2f64:
1948 src[0] = ac_to_integer(&ctx->ac, src[0]);
1949 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1950 break;
1951 case nir_op_f2f64:
1952 src[0] = ac_to_float(&ctx->ac, src[0]);
1953 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1954 break;
1955 case nir_op_f2f32:
1956 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1957 break;
1958 case nir_op_u2u32:
1959 case nir_op_u2u64:
1960 src[0] = ac_to_integer(&ctx->ac, src[0]);
1961 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1962 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1963 else
1964 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1965 break;
1966 case nir_op_i2i32:
1967 case nir_op_i2i64:
1968 src[0] = ac_to_integer(&ctx->ac, src[0]);
1969 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1970 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1971 else
1972 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1973 break;
1974 case nir_op_bcsel:
1975 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1976 break;
1977 case nir_op_find_lsb:
1978 src[0] = ac_to_integer(&ctx->ac, src[0]);
1979 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1980 break;
1981 case nir_op_ufind_msb:
1982 src[0] = ac_to_integer(&ctx->ac, src[0]);
1983 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1984 break;
1985 case nir_op_ifind_msb:
1986 src[0] = ac_to_integer(&ctx->ac, src[0]);
1987 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1988 break;
1989 case nir_op_uadd_carry:
1990 src[0] = ac_to_integer(&ctx->ac, src[0]);
1991 src[1] = ac_to_integer(&ctx->ac, src[1]);
1992 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1993 break;
1994 case nir_op_usub_borrow:
1995 src[0] = ac_to_integer(&ctx->ac, src[0]);
1996 src[1] = ac_to_integer(&ctx->ac, src[1]);
1997 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1998 break;
1999 case nir_op_b2f:
2000 result = emit_b2f(&ctx->ac, src[0]);
2001 break;
2002 case nir_op_f2b:
2003 result = emit_f2b(&ctx->ac, src[0]);
2004 break;
2005 case nir_op_b2i:
2006 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2007 break;
2008 case nir_op_i2b:
2009 src[0] = ac_to_integer(&ctx->ac, src[0]);
2010 result = emit_i2b(&ctx->ac, src[0]);
2011 break;
2012 case nir_op_fquantize2f16:
2013 result = emit_f2f16(ctx->nctx, src[0]);
2014 break;
2015 case nir_op_umul_high:
2016 src[0] = ac_to_integer(&ctx->ac, src[0]);
2017 src[1] = ac_to_integer(&ctx->ac, src[1]);
2018 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2019 break;
2020 case nir_op_imul_high:
2021 src[0] = ac_to_integer(&ctx->ac, src[0]);
2022 src[1] = ac_to_integer(&ctx->ac, src[1]);
2023 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2024 break;
2025 case nir_op_pack_half_2x16:
2026 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2027 break;
2028 case nir_op_unpack_half_2x16:
2029 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2030 break;
2031 case nir_op_fddx:
2032 case nir_op_fddy:
2033 case nir_op_fddx_fine:
2034 case nir_op_fddy_fine:
2035 case nir_op_fddx_coarse:
2036 case nir_op_fddy_coarse:
2037 result = emit_ddxy(ctx, instr->op, src[0]);
2038 break;
2039
2040 case nir_op_unpack_64_2x32_split_x: {
2041 assert(instr->src[0].src.ssa->num_components == 1);
2042 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2043 ctx->ac.v2i32,
2044 "");
2045 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2046 ctx->ac.i32_0, "");
2047 break;
2048 }
2049
2050 case nir_op_unpack_64_2x32_split_y: {
2051 assert(instr->src[0].src.ssa->num_components == 1);
2052 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2053 ctx->ac.v2i32,
2054 "");
2055 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2056 ctx->ac.i32_1, "");
2057 break;
2058 }
2059
2060 case nir_op_pack_64_2x32_split: {
2061 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2062 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2063 src[0], ctx->ac.i32_0, "");
2064 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2065 src[1], ctx->ac.i32_1, "");
2066 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2067 break;
2068 }
2069
2070 default:
2071 fprintf(stderr, "Unknown NIR alu instr: ");
2072 nir_print_instr(&instr->instr, stderr);
2073 fprintf(stderr, "\n");
2074 abort();
2075 }
2076
2077 if (result) {
2078 assert(instr->dest.dest.is_ssa);
2079 result = ac_to_integer(&ctx->ac, result);
2080 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2081 result);
2082 }
2083 }
2084
2085 static void visit_load_const(struct ac_nir_context *ctx,
2086 const nir_load_const_instr *instr)
2087 {
2088 LLVMValueRef values[4], value = NULL;
2089 LLVMTypeRef element_type =
2090 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2091
2092 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2093 switch (instr->def.bit_size) {
2094 case 32:
2095 values[i] = LLVMConstInt(element_type,
2096 instr->value.u32[i], false);
2097 break;
2098 case 64:
2099 values[i] = LLVMConstInt(element_type,
2100 instr->value.u64[i], false);
2101 break;
2102 default:
2103 fprintf(stderr,
2104 "unsupported nir load_const bit_size: %d\n",
2105 instr->def.bit_size);
2106 abort();
2107 }
2108 }
2109 if (instr->def.num_components > 1) {
2110 value = LLVMConstVector(values, instr->def.num_components);
2111 } else
2112 value = values[0];
2113
2114 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2115 }
2116
2117 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2118 LLVMTypeRef type)
2119 {
2120 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2121 return LLVMBuildBitCast(ctx->builder, ptr,
2122 LLVMPointerType(type, addr_space), "");
2123 }
2124
2125 static LLVMValueRef
2126 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2127 {
2128 LLVMValueRef size =
2129 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2130 LLVMConstInt(ctx->ac.i32, 2, false), "");
2131
2132 /* VI only */
2133 if (ctx->ac.chip_class == VI && in_elements) {
2134 /* On VI, the descriptor contains the size in bytes,
2135 * but TXQ must return the size in elements.
2136 * The stride is always non-zero for resources using TXQ.
2137 */
2138 LLVMValueRef stride =
2139 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2140 ctx->ac.i32_1, "");
2141 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2142 LLVMConstInt(ctx->ac.i32, 16, false), "");
2143 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2144 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2145
2146 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2147 }
2148 return size;
2149 }
2150
2151 /**
2152 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2153 * intrinsic names).
2154 */
2155 static void build_int_type_name(
2156 LLVMTypeRef type,
2157 char *buf, unsigned bufsize)
2158 {
2159 assert(bufsize >= 6);
2160
2161 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2162 snprintf(buf, bufsize, "v%ui32",
2163 LLVMGetVectorSize(type));
2164 else
2165 strcpy(buf, "i32");
2166 }
2167
2168 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2169 struct ac_image_args *args,
2170 const nir_tex_instr *instr)
2171 {
2172 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2173 LLVMValueRef coord = args->addr;
2174 LLVMValueRef half_texel[2];
2175 LLVMValueRef compare_cube_wa = NULL;
2176 LLVMValueRef result;
2177 int c;
2178 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2179
2180 //TODO Rect
2181 {
2182 struct ac_image_args txq_args = { 0 };
2183
2184 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2185 txq_args.opcode = ac_image_get_resinfo;
2186 txq_args.dmask = 0xf;
2187 txq_args.addr = ctx->i32_0;
2188 txq_args.resource = args->resource;
2189 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2190
2191 for (c = 0; c < 2; c++) {
2192 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2193 LLVMConstInt(ctx->i32, c, false), "");
2194 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2195 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2196 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2197 LLVMConstReal(ctx->f32, -0.5), "");
2198 }
2199 }
2200
2201 LLVMValueRef orig_coords = args->addr;
2202
2203 for (c = 0; c < 2; c++) {
2204 LLVMValueRef tmp;
2205 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2206 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2207 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2208 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2209 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2210 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2211 }
2212
2213
2214 /*
2215 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2216 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2217 * workaround by sampling using a scaled type and converting.
2218 * This is taken from amdgpu-pro shaders.
2219 */
2220 /* NOTE this produces some ugly code compared to amdgpu-pro,
2221 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2222 * and then reads them back. -pro generates two selects,
2223 * one s_cmp for the descriptor rewriting
2224 * one v_cmp for the coordinate and result changes.
2225 */
2226 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2227 LLVMValueRef tmp, tmp2;
2228
2229 /* workaround 8/8/8/8 uint/sint cube gather bug */
2230 /* first detect it then change to a scaled read and f2i */
2231 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2232 tmp2 = tmp;
2233
2234 /* extract the DATA_FORMAT */
2235 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2236 LLVMConstInt(ctx->i32, 6, false), false);
2237
2238 /* is the DATA_FORMAT == 8_8_8_8 */
2239 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2240
2241 if (stype == GLSL_TYPE_UINT)
2242 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2243 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2244 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2245 else
2246 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2247 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2248 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2249
2250 /* replace the NUM FORMAT in the descriptor */
2251 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2252 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2253
2254 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2255
2256 /* don't modify the coordinates for this case */
2257 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2258 }
2259 args->addr = coord;
2260 result = ac_build_image_opcode(ctx, args);
2261
2262 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2263 LLVMValueRef tmp, tmp2;
2264
2265 /* if the cube workaround is in place, f2i the result. */
2266 for (c = 0; c < 4; c++) {
2267 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2268 if (stype == GLSL_TYPE_UINT)
2269 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2270 else
2271 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2272 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2273 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2274 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2275 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2276 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2277 }
2278 }
2279 return result;
2280 }
2281
2282 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2283 const nir_tex_instr *instr,
2284 bool lod_is_zero,
2285 struct ac_image_args *args)
2286 {
2287 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2288 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2289
2290 return ac_build_buffer_load_format(&ctx->ac,
2291 args->resource,
2292 args->addr,
2293 ctx->ac.i32_0,
2294 util_last_bit(mask),
2295 false, true);
2296 }
2297
2298 args->opcode = ac_image_sample;
2299 args->compare = instr->is_shadow;
2300
2301 switch (instr->op) {
2302 case nir_texop_txf:
2303 case nir_texop_txf_ms:
2304 case nir_texop_samples_identical:
2305 args->opcode = lod_is_zero ||
2306 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2307 ac_image_load : ac_image_load_mip;
2308 args->compare = false;
2309 args->offset = false;
2310 break;
2311 case nir_texop_txb:
2312 args->bias = true;
2313 break;
2314 case nir_texop_txl:
2315 if (lod_is_zero)
2316 args->level_zero = true;
2317 else
2318 args->lod = true;
2319 break;
2320 case nir_texop_txs:
2321 case nir_texop_query_levels:
2322 args->opcode = ac_image_get_resinfo;
2323 break;
2324 case nir_texop_tex:
2325 if (ctx->stage != MESA_SHADER_FRAGMENT)
2326 args->level_zero = true;
2327 break;
2328 case nir_texop_txd:
2329 args->deriv = true;
2330 break;
2331 case nir_texop_tg4:
2332 args->opcode = ac_image_gather4;
2333 args->level_zero = true;
2334 break;
2335 case nir_texop_lod:
2336 args->opcode = ac_image_get_lod;
2337 args->compare = false;
2338 args->offset = false;
2339 break;
2340 default:
2341 break;
2342 }
2343
2344 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2345 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2346 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2347 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2348 }
2349 }
2350 return ac_build_image_opcode(&ctx->ac, args);
2351 }
2352
2353 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2354 nir_intrinsic_instr *instr)
2355 {
2356 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2357 unsigned desc_set = nir_intrinsic_desc_set(instr);
2358 unsigned binding = nir_intrinsic_binding(instr);
2359 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2360 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2361 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2362 unsigned base_offset = layout->binding[binding].offset;
2363 LLVMValueRef offset, stride;
2364
2365 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2366 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2367 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2368 layout->binding[binding].dynamic_offset_offset;
2369 desc_ptr = ctx->push_constants;
2370 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2371 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2372 } else
2373 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2374
2375 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2376 index = LLVMBuildMul(ctx->builder, index, stride, "");
2377 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2378
2379 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2380 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2381 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2382
2383 return desc_ptr;
2384 }
2385
2386 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2387 nir_intrinsic_instr *instr)
2388 {
2389 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2390 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2391
2392 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2393 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2394 return result;
2395 }
2396
2397 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2398 nir_intrinsic_instr *instr)
2399 {
2400 LLVMValueRef ptr, addr;
2401
2402 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2403 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2404
2405 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2406 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2407
2408 return LLVMBuildLoad(ctx->builder, ptr, "");
2409 }
2410
2411 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2412 const nir_intrinsic_instr *instr)
2413 {
2414 LLVMValueRef index = get_src(ctx, instr->src[0]);
2415
2416 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2417 }
2418
2419 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2420 {
2421 uint32_t new_mask = 0;
2422 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2423 if (mask & (1u << i))
2424 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2425 return new_mask;
2426 }
2427
2428 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2429 unsigned start, unsigned count)
2430 {
2431 LLVMTypeRef type = LLVMTypeOf(src);
2432
2433 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2434 assert(start == 0);
2435 assert(count == 1);
2436 return src;
2437 }
2438
2439 unsigned src_elements = LLVMGetVectorSize(type);
2440 assert(start < src_elements);
2441 assert(start + count <= src_elements);
2442
2443 if (start == 0 && count == src_elements)
2444 return src;
2445
2446 if (count == 1)
2447 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2448
2449 assert(count <= 8);
2450 LLVMValueRef indices[8];
2451 for (unsigned i = 0; i < count; ++i)
2452 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2453
2454 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2455 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2456 }
2457
2458 static void visit_store_ssbo(struct ac_nir_context *ctx,
2459 nir_intrinsic_instr *instr)
2460 {
2461 const char *store_name;
2462 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2463 LLVMTypeRef data_type = ctx->ac.f32;
2464 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2465 int components_32bit = elem_size_mult * instr->num_components;
2466 unsigned writemask = nir_intrinsic_write_mask(instr);
2467 LLVMValueRef base_data, base_offset;
2468 LLVMValueRef params[6];
2469
2470 params[1] = ctx->abi->load_ssbo(ctx->abi,
2471 get_src(ctx, instr->src[1]), true);
2472 params[2] = ctx->ac.i32_0; /* vindex */
2473 params[4] = ctx->ac.i1false; /* glc */
2474 params[5] = ctx->ac.i1false; /* slc */
2475
2476 if (components_32bit > 1)
2477 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2478
2479 writemask = widen_mask(writemask, elem_size_mult);
2480
2481 base_data = ac_to_float(&ctx->ac, src_data);
2482 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2483 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2484 data_type, "");
2485 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2486 while (writemask) {
2487 int start, count;
2488 LLVMValueRef data;
2489 LLVMValueRef offset;
2490
2491 u_bit_scan_consecutive_range(&writemask, &start, &count);
2492
2493 /* Due to an LLVM limitation, split 3-element writes
2494 * into a 2-element and a 1-element write. */
2495 if (count == 3) {
2496 writemask |= 1 << (start + 2);
2497 count = 2;
2498 }
2499
2500 if (count > 4) {
2501 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2502 count = 4;
2503 }
2504
2505 if (count == 4) {
2506 store_name = "llvm.amdgcn.buffer.store.v4f32";
2507 } else if (count == 2) {
2508 store_name = "llvm.amdgcn.buffer.store.v2f32";
2509
2510 } else {
2511 assert(count == 1);
2512 store_name = "llvm.amdgcn.buffer.store.f32";
2513 }
2514 data = extract_vector_range(&ctx->ac, base_data, start, count);
2515
2516 offset = base_offset;
2517 if (start != 0) {
2518 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2519 }
2520 params[0] = data;
2521 params[3] = offset;
2522 ac_build_intrinsic(&ctx->ac, store_name,
2523 ctx->ac.voidt, params, 6, 0);
2524 }
2525 }
2526
2527 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2528 const nir_intrinsic_instr *instr)
2529 {
2530 const char *name;
2531 LLVMValueRef params[6];
2532 int arg_count = 0;
2533
2534 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2535 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2536 }
2537 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2538 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2539 get_src(ctx, instr->src[0]),
2540 true);
2541 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2542 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2543 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2544
2545 switch (instr->intrinsic) {
2546 case nir_intrinsic_ssbo_atomic_add:
2547 name = "llvm.amdgcn.buffer.atomic.add";
2548 break;
2549 case nir_intrinsic_ssbo_atomic_imin:
2550 name = "llvm.amdgcn.buffer.atomic.smin";
2551 break;
2552 case nir_intrinsic_ssbo_atomic_umin:
2553 name = "llvm.amdgcn.buffer.atomic.umin";
2554 break;
2555 case nir_intrinsic_ssbo_atomic_imax:
2556 name = "llvm.amdgcn.buffer.atomic.smax";
2557 break;
2558 case nir_intrinsic_ssbo_atomic_umax:
2559 name = "llvm.amdgcn.buffer.atomic.umax";
2560 break;
2561 case nir_intrinsic_ssbo_atomic_and:
2562 name = "llvm.amdgcn.buffer.atomic.and";
2563 break;
2564 case nir_intrinsic_ssbo_atomic_or:
2565 name = "llvm.amdgcn.buffer.atomic.or";
2566 break;
2567 case nir_intrinsic_ssbo_atomic_xor:
2568 name = "llvm.amdgcn.buffer.atomic.xor";
2569 break;
2570 case nir_intrinsic_ssbo_atomic_exchange:
2571 name = "llvm.amdgcn.buffer.atomic.swap";
2572 break;
2573 case nir_intrinsic_ssbo_atomic_comp_swap:
2574 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2575 break;
2576 default:
2577 abort();
2578 }
2579
2580 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2581 }
2582
2583 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2584 const nir_intrinsic_instr *instr)
2585 {
2586 LLVMValueRef results[2];
2587 int load_components;
2588 int num_components = instr->num_components;
2589 if (instr->dest.ssa.bit_size == 64)
2590 num_components *= 2;
2591
2592 for (int i = 0; i < num_components; i += load_components) {
2593 load_components = MIN2(num_components - i, 4);
2594 const char *load_name;
2595 LLVMTypeRef data_type = ctx->ac.f32;
2596 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2597 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2598
2599 if (load_components == 3)
2600 data_type = LLVMVectorType(ctx->ac.f32, 4);
2601 else if (load_components > 1)
2602 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2603
2604 if (load_components >= 3)
2605 load_name = "llvm.amdgcn.buffer.load.v4f32";
2606 else if (load_components == 2)
2607 load_name = "llvm.amdgcn.buffer.load.v2f32";
2608 else if (load_components == 1)
2609 load_name = "llvm.amdgcn.buffer.load.f32";
2610 else
2611 unreachable("unhandled number of components");
2612
2613 LLVMValueRef params[] = {
2614 ctx->abi->load_ssbo(ctx->abi,
2615 get_src(ctx, instr->src[0]),
2616 false),
2617 ctx->ac.i32_0,
2618 offset,
2619 ctx->ac.i1false,
2620 ctx->ac.i1false,
2621 };
2622
2623 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2624 }
2625
2626 assume(results[0]);
2627 LLVMValueRef ret = results[0];
2628 if (num_components > 4 || num_components == 3) {
2629 LLVMValueRef masks[] = {
2630 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2631 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2632 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2633 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2634 };
2635
2636 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2637 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2638 results[num_components > 4 ? 1 : 0], swizzle, "");
2639 }
2640
2641 return LLVMBuildBitCast(ctx->ac.builder, ret,
2642 get_def_type(ctx, &instr->dest.ssa), "");
2643 }
2644
2645 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2646 const nir_intrinsic_instr *instr)
2647 {
2648 LLVMValueRef ret;
2649 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2650 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2651 int num_components = instr->num_components;
2652
2653 if (ctx->abi->load_ubo)
2654 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2655
2656 if (instr->dest.ssa.bit_size == 64)
2657 num_components *= 2;
2658
2659 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2660 NULL, 0, false, false, true, true);
2661 ret = trim_vector(&ctx->ac, ret, num_components);
2662 return LLVMBuildBitCast(ctx->ac.builder, ret,
2663 get_def_type(ctx, &instr->dest.ssa), "");
2664 }
2665
2666 static void
2667 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2668 bool vs_in, unsigned *vertex_index_out,
2669 LLVMValueRef *vertex_index_ref,
2670 unsigned *const_out, LLVMValueRef *indir_out)
2671 {
2672 unsigned const_offset = 0;
2673 nir_deref *tail = &deref->deref;
2674 LLVMValueRef offset = NULL;
2675
2676 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2677 tail = tail->child;
2678 nir_deref_array *deref_array = nir_deref_as_array(tail);
2679 if (vertex_index_out)
2680 *vertex_index_out = deref_array->base_offset;
2681
2682 if (vertex_index_ref) {
2683 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2684 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2685 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2686 }
2687 *vertex_index_ref = vtx;
2688 }
2689 }
2690
2691 if (deref->var->data.compact) {
2692 assert(tail->child->deref_type == nir_deref_type_array);
2693 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2694 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2695 /* We always lower indirect dereferences for "compact" array vars. */
2696 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2697
2698 const_offset = deref_array->base_offset;
2699 goto out;
2700 }
2701
2702 while (tail->child != NULL) {
2703 const struct glsl_type *parent_type = tail->type;
2704 tail = tail->child;
2705
2706 if (tail->deref_type == nir_deref_type_array) {
2707 nir_deref_array *deref_array = nir_deref_as_array(tail);
2708 LLVMValueRef index, stride, local_offset;
2709 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2710
2711 const_offset += size * deref_array->base_offset;
2712 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2713 continue;
2714
2715 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2716 index = get_src(ctx, deref_array->indirect);
2717 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2718 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2719
2720 if (offset)
2721 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2722 else
2723 offset = local_offset;
2724 } else if (tail->deref_type == nir_deref_type_struct) {
2725 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2726
2727 for (unsigned i = 0; i < deref_struct->index; i++) {
2728 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2729 const_offset += glsl_count_attribute_slots(ft, vs_in);
2730 }
2731 } else
2732 unreachable("unsupported deref type");
2733
2734 }
2735 out:
2736 if (const_offset && offset)
2737 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2738 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2739 "");
2740
2741 *const_out = const_offset;
2742 *indir_out = offset;
2743 }
2744
2745
2746 /* The offchip buffer layout for TCS->TES is
2747 *
2748 * - attribute 0 of patch 0 vertex 0
2749 * - attribute 0 of patch 0 vertex 1
2750 * - attribute 0 of patch 0 vertex 2
2751 * ...
2752 * - attribute 0 of patch 1 vertex 0
2753 * - attribute 0 of patch 1 vertex 1
2754 * ...
2755 * - attribute 1 of patch 0 vertex 0
2756 * - attribute 1 of patch 0 vertex 1
2757 * ...
2758 * - per patch attribute 0 of patch 0
2759 * - per patch attribute 0 of patch 1
2760 * ...
2761 *
2762 * Note that every attribute has 4 components.
2763 */
2764 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2765 LLVMValueRef vertex_index,
2766 LLVMValueRef param_index)
2767 {
2768 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2769 LLVMValueRef param_stride, constant16;
2770 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2771
2772 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2773 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2774 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2775 num_patches, "");
2776
2777 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2778 if (vertex_index) {
2779 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2780 vertices_per_patch, "");
2781
2782 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2783 vertex_index, "");
2784
2785 param_stride = total_vertices;
2786 } else {
2787 base_addr = rel_patch_id;
2788 param_stride = num_patches;
2789 }
2790
2791 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2792 LLVMBuildMul(ctx->builder, param_index,
2793 param_stride, ""), "");
2794
2795 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2796
2797 if (!vertex_index) {
2798 LLVMValueRef patch_data_offset =
2799 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2800
2801 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2802 patch_data_offset, "");
2803 }
2804 return base_addr;
2805 }
2806
2807 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2808 unsigned param,
2809 unsigned const_index,
2810 bool is_compact,
2811 LLVMValueRef vertex_index,
2812 LLVMValueRef indir_index)
2813 {
2814 LLVMValueRef param_index;
2815
2816 if (indir_index)
2817 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2818 indir_index, "");
2819 else {
2820 if (const_index && !is_compact)
2821 param += const_index;
2822 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2823 }
2824 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2825 }
2826
2827 static void
2828 mark_tess_output(struct nir_to_llvm_context *ctx,
2829 bool is_patch, uint32_t param)
2830
2831 {
2832 if (is_patch) {
2833 ctx->tess_patch_outputs_written |= (1ull << param);
2834 } else
2835 ctx->tess_outputs_written |= (1ull << param);
2836 }
2837
2838 static LLVMValueRef
2839 get_dw_address(struct nir_to_llvm_context *ctx,
2840 LLVMValueRef dw_addr,
2841 unsigned param,
2842 unsigned const_index,
2843 bool compact_const_index,
2844 LLVMValueRef vertex_index,
2845 LLVMValueRef stride,
2846 LLVMValueRef indir_index)
2847
2848 {
2849
2850 if (vertex_index) {
2851 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2852 LLVMBuildMul(ctx->builder,
2853 vertex_index,
2854 stride, ""), "");
2855 }
2856
2857 if (indir_index)
2858 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2859 LLVMBuildMul(ctx->builder, indir_index,
2860 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2861 else if (const_index && !compact_const_index)
2862 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2863 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2864
2865 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2866 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2867
2868 if (const_index && compact_const_index)
2869 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2870 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2871 return dw_addr;
2872 }
2873
2874 static LLVMValueRef
2875 load_tcs_varyings(struct ac_shader_abi *abi,
2876 LLVMValueRef vertex_index,
2877 LLVMValueRef indir_index,
2878 unsigned const_index,
2879 unsigned location,
2880 unsigned driver_location,
2881 unsigned component,
2882 unsigned num_components,
2883 bool is_patch,
2884 bool is_compact,
2885 bool load_input)
2886 {
2887 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2888 LLVMValueRef dw_addr, stride;
2889 LLVMValueRef value[4], result;
2890 unsigned param = shader_io_get_unique_index(location);
2891
2892 if (load_input) {
2893 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2894 dw_addr = get_tcs_in_current_patch_offset(ctx);
2895 } else {
2896 if (!is_patch) {
2897 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2898 dw_addr = get_tcs_out_current_patch_offset(ctx);
2899 } else {
2900 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2901 stride = NULL;
2902 }
2903 }
2904
2905 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2906 indir_index);
2907
2908 for (unsigned i = 0; i < num_components + component; i++) {
2909 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2910 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2911 ctx->ac.i32_1, "");
2912 }
2913 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2914 return result;
2915 }
2916
2917 static void
2918 store_tcs_output(struct ac_shader_abi *abi,
2919 LLVMValueRef vertex_index,
2920 LLVMValueRef param_index,
2921 unsigned const_index,
2922 unsigned location,
2923 unsigned driver_location,
2924 LLVMValueRef src,
2925 unsigned component,
2926 bool is_patch,
2927 bool is_compact,
2928 unsigned writemask)
2929 {
2930 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2931 LLVMValueRef dw_addr;
2932 LLVMValueRef stride = NULL;
2933 LLVMValueRef buf_addr = NULL;
2934 unsigned param;
2935 bool store_lds = true;
2936
2937 if (is_patch) {
2938 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2939 store_lds = false;
2940 } else {
2941 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2942 store_lds = false;
2943 }
2944
2945 param = shader_io_get_unique_index(location);
2946 if (location == VARYING_SLOT_CLIP_DIST0 &&
2947 is_compact && const_index > 3) {
2948 const_index -= 3;
2949 param++;
2950 }
2951
2952 if (!is_patch) {
2953 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2954 dw_addr = get_tcs_out_current_patch_offset(ctx);
2955 } else {
2956 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2957 }
2958
2959 mark_tess_output(ctx, is_patch, param);
2960
2961 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2962 param_index);
2963 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2964 vertex_index, param_index);
2965
2966 bool is_tess_factor = false;
2967 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2968 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2969 is_tess_factor = true;
2970
2971 unsigned base = is_compact ? const_index : 0;
2972 for (unsigned chan = 0; chan < 8; chan++) {
2973 if (!(writemask & (1 << chan)))
2974 continue;
2975 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2976
2977 if (store_lds || is_tess_factor) {
2978 LLVMValueRef dw_addr_chan =
2979 LLVMBuildAdd(ctx->builder, dw_addr,
2980 LLVMConstInt(ctx->ac.i32, chan, false), "");
2981 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2982 }
2983
2984 if (!is_tess_factor && writemask != 0xF)
2985 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2986 buf_addr, ctx->oc_lds,
2987 4 * (base + chan), 1, 0, true, false);
2988 }
2989
2990 if (writemask == 0xF) {
2991 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2992 buf_addr, ctx->oc_lds,
2993 (base * 4), 1, 0, true, false);
2994 }
2995 }
2996
2997 static LLVMValueRef
2998 load_tes_input(struct ac_shader_abi *abi,
2999 LLVMValueRef vertex_index,
3000 LLVMValueRef param_index,
3001 unsigned const_index,
3002 unsigned location,
3003 unsigned driver_location,
3004 unsigned component,
3005 unsigned num_components,
3006 bool is_patch,
3007 bool is_compact,
3008 bool load_input)
3009 {
3010 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3011 LLVMValueRef buf_addr;
3012 LLVMValueRef result;
3013 unsigned param = shader_io_get_unique_index(location);
3014
3015 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3016 const_index -= 3;
3017 param++;
3018 }
3019
3020 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3021 is_compact, vertex_index, param_index);
3022
3023 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3024 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3025
3026 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3027 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3028 result = trim_vector(&ctx->ac, result, num_components);
3029 return result;
3030 }
3031
3032 static LLVMValueRef
3033 load_gs_input(struct ac_shader_abi *abi,
3034 unsigned location,
3035 unsigned driver_location,
3036 unsigned component,
3037 unsigned num_components,
3038 unsigned vertex_index,
3039 unsigned const_index,
3040 LLVMTypeRef type)
3041 {
3042 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3043 LLVMValueRef vtx_offset;
3044 unsigned param, vtx_offset_param;
3045 LLVMValueRef value[4], result;
3046
3047 vtx_offset_param = vertex_index;
3048 assert(vtx_offset_param < 6);
3049 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3050 LLVMConstInt(ctx->ac.i32, 4, false), "");
3051
3052 param = shader_io_get_unique_index(location);
3053
3054 for (unsigned i = component; i < num_components + component; i++) {
3055 if (ctx->ac.chip_class >= GFX9) {
3056 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3057 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3058 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3059 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3060 } else {
3061 LLVMValueRef soffset =
3062 LLVMConstInt(ctx->ac.i32,
3063 (param * 4 + i + const_index) * 256,
3064 false);
3065
3066 value[i] = ac_build_buffer_load(&ctx->ac,
3067 ctx->esgs_ring, 1,
3068 ctx->ac.i32_0,
3069 vtx_offset, soffset,
3070 0, 1, 0, true, false);
3071
3072 value[i] = LLVMBuildBitCast(ctx->builder, value[i],
3073 type, "");
3074 }
3075 }
3076 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3077 result = ac_to_integer(&ctx->ac, result);
3078 return result;
3079 }
3080
3081 static LLVMValueRef
3082 build_gep_for_deref(struct ac_nir_context *ctx,
3083 nir_deref_var *deref)
3084 {
3085 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3086 assert(entry->data);
3087 LLVMValueRef val = entry->data;
3088 nir_deref *tail = deref->deref.child;
3089 while (tail != NULL) {
3090 LLVMValueRef offset;
3091 switch (tail->deref_type) {
3092 case nir_deref_type_array: {
3093 nir_deref_array *array = nir_deref_as_array(tail);
3094 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3095 if (array->deref_array_type ==
3096 nir_deref_array_type_indirect) {
3097 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3098 get_src(ctx,
3099 array->indirect),
3100 "");
3101 }
3102 break;
3103 }
3104 case nir_deref_type_struct: {
3105 nir_deref_struct *deref_struct =
3106 nir_deref_as_struct(tail);
3107 offset = LLVMConstInt(ctx->ac.i32,
3108 deref_struct->index, 0);
3109 break;
3110 }
3111 default:
3112 unreachable("bad deref type");
3113 }
3114 val = ac_build_gep0(&ctx->ac, val, offset);
3115 tail = tail->child;
3116 }
3117 return val;
3118 }
3119
3120 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3121 nir_intrinsic_instr *instr,
3122 bool load_inputs)
3123 {
3124 LLVMValueRef result;
3125 LLVMValueRef vertex_index = NULL;
3126 LLVMValueRef indir_index = NULL;
3127 unsigned const_index = 0;
3128 unsigned location = instr->variables[0]->var->data.location;
3129 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3130 const bool is_patch = instr->variables[0]->var->data.patch;
3131 const bool is_compact = instr->variables[0]->var->data.compact;
3132
3133 get_deref_offset(ctx, instr->variables[0],
3134 false, NULL, is_patch ? NULL : &vertex_index,
3135 &const_index, &indir_index);
3136
3137 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3138 const_index, location, driver_location,
3139 instr->variables[0]->var->data.location_frac,
3140 instr->num_components,
3141 is_patch, is_compact, load_inputs);
3142 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3143 }
3144
3145 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3146 nir_intrinsic_instr *instr)
3147 {
3148 LLVMValueRef values[8];
3149 int idx = instr->variables[0]->var->data.driver_location;
3150 int ve = instr->dest.ssa.num_components;
3151 unsigned comp = instr->variables[0]->var->data.location_frac;
3152 LLVMValueRef indir_index;
3153 LLVMValueRef ret;
3154 unsigned const_index;
3155 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3156 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3157 instr->variables[0]->var->data.mode == nir_var_shader_in;
3158 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3159 &const_index, &indir_index);
3160
3161 if (instr->dest.ssa.bit_size == 64)
3162 ve *= 2;
3163
3164 switch (instr->variables[0]->var->data.mode) {
3165 case nir_var_shader_in:
3166 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3167 ctx->stage == MESA_SHADER_TESS_EVAL) {
3168 return load_tess_varyings(ctx, instr, true);
3169 }
3170
3171 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3172 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3173 LLVMValueRef indir_index;
3174 unsigned const_index, vertex_index;
3175 get_deref_offset(ctx, instr->variables[0],
3176 false, &vertex_index, NULL,
3177 &const_index, &indir_index);
3178
3179 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3180 instr->variables[0]->var->data.driver_location,
3181 instr->variables[0]->var->data.location_frac, ve,
3182 vertex_index, const_index, type);
3183 }
3184
3185 for (unsigned chan = comp; chan < ve + comp; chan++) {
3186 if (indir_index) {
3187 unsigned count = glsl_count_attribute_slots(
3188 instr->variables[0]->var->type,
3189 ctx->stage == MESA_SHADER_VERTEX);
3190 count -= chan / 4;
3191 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3192 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3193 stride, false, true);
3194
3195 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3196 tmp_vec,
3197 indir_index, "");
3198 } else
3199 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3200 }
3201 break;
3202 case nir_var_local:
3203 for (unsigned chan = 0; chan < ve; chan++) {
3204 if (indir_index) {
3205 unsigned count = glsl_count_attribute_slots(
3206 instr->variables[0]->var->type, false);
3207 count -= chan / 4;
3208 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3209 &ctx->ac, ctx->locals + idx + chan, count,
3210 stride, true, true);
3211
3212 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3213 tmp_vec,
3214 indir_index, "");
3215 } else {
3216 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3217 }
3218 }
3219 break;
3220 case nir_var_shared: {
3221 LLVMValueRef address = build_gep_for_deref(ctx,
3222 instr->variables[0]);
3223 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3224 return LLVMBuildBitCast(ctx->ac.builder, val,
3225 get_def_type(ctx, &instr->dest.ssa),
3226 "");
3227 }
3228 case nir_var_shader_out:
3229 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3230 return load_tess_varyings(ctx, instr, false);
3231 }
3232
3233 for (unsigned chan = comp; chan < ve + comp; chan++) {
3234 if (indir_index) {
3235 unsigned count = glsl_count_attribute_slots(
3236 instr->variables[0]->var->type, false);
3237 count -= chan / 4;
3238 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3239 &ctx->ac, ctx->outputs + idx + chan, count,
3240 stride, true, true);
3241
3242 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3243 tmp_vec,
3244 indir_index, "");
3245 } else {
3246 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3247 ctx->outputs[idx + chan + const_index * stride],
3248 "");
3249 }
3250 }
3251 break;
3252 default:
3253 unreachable("unhandle variable mode");
3254 }
3255 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3256 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3257 }
3258
3259 static void
3260 visit_store_var(struct ac_nir_context *ctx,
3261 nir_intrinsic_instr *instr)
3262 {
3263 LLVMValueRef temp_ptr, value;
3264 int idx = instr->variables[0]->var->data.driver_location;
3265 unsigned comp = instr->variables[0]->var->data.location_frac;
3266 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3267 int writemask = instr->const_index[0] << comp;
3268 LLVMValueRef indir_index;
3269 unsigned const_index;
3270 get_deref_offset(ctx, instr->variables[0], false,
3271 NULL, NULL, &const_index, &indir_index);
3272
3273 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3274
3275 src = LLVMBuildBitCast(ctx->ac.builder, src,
3276 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3277 "");
3278
3279 writemask = widen_mask(writemask, 2);
3280 }
3281
3282 switch (instr->variables[0]->var->data.mode) {
3283 case nir_var_shader_out:
3284
3285 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3286 LLVMValueRef vertex_index = NULL;
3287 LLVMValueRef indir_index = NULL;
3288 unsigned const_index = 0;
3289 const unsigned location = instr->variables[0]->var->data.location;
3290 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3291 const unsigned comp = instr->variables[0]->var->data.location_frac;
3292 const bool is_patch = instr->variables[0]->var->data.patch;
3293 const bool is_compact = instr->variables[0]->var->data.compact;
3294
3295 get_deref_offset(ctx, instr->variables[0],
3296 false, NULL, is_patch ? NULL : &vertex_index,
3297 &const_index, &indir_index);
3298
3299 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3300 const_index, location, driver_location,
3301 src, comp, is_patch, is_compact, writemask);
3302 return;
3303 }
3304
3305 for (unsigned chan = 0; chan < 8; chan++) {
3306 int stride = 4;
3307 if (!(writemask & (1 << chan)))
3308 continue;
3309
3310 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3311
3312 if (instr->variables[0]->var->data.compact)
3313 stride = 1;
3314 if (indir_index) {
3315 unsigned count = glsl_count_attribute_slots(
3316 instr->variables[0]->var->type, false);
3317 count -= chan / 4;
3318 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3319 &ctx->ac, ctx->outputs + idx + chan, count,
3320 stride, true, true);
3321
3322 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3323 value, indir_index, "");
3324 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3325 count, stride, tmp_vec);
3326
3327 } else {
3328 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3329
3330 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3331 }
3332 }
3333 break;
3334 case nir_var_local:
3335 for (unsigned chan = 0; chan < 8; chan++) {
3336 if (!(writemask & (1 << chan)))
3337 continue;
3338
3339 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3340 if (indir_index) {
3341 unsigned count = glsl_count_attribute_slots(
3342 instr->variables[0]->var->type, false);
3343 count -= chan / 4;
3344 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3345 &ctx->ac, ctx->locals + idx + chan, count,
3346 4, true, true);
3347
3348 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3349 value, indir_index, "");
3350 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3351 count, 4, tmp_vec);
3352 } else {
3353 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3354
3355 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3356 }
3357 }
3358 break;
3359 case nir_var_shared: {
3360 int writemask = instr->const_index[0];
3361 LLVMValueRef address = build_gep_for_deref(ctx,
3362 instr->variables[0]);
3363 LLVMValueRef val = get_src(ctx, instr->src[0]);
3364 unsigned components =
3365 glsl_get_vector_elements(
3366 nir_deref_tail(&instr->variables[0]->deref)->type);
3367 if (writemask == (1 << components) - 1) {
3368 val = LLVMBuildBitCast(
3369 ctx->ac.builder, val,
3370 LLVMGetElementType(LLVMTypeOf(address)), "");
3371 LLVMBuildStore(ctx->ac.builder, val, address);
3372 } else {
3373 for (unsigned chan = 0; chan < 4; chan++) {
3374 if (!(writemask & (1 << chan)))
3375 continue;
3376 LLVMValueRef ptr =
3377 LLVMBuildStructGEP(ctx->ac.builder,
3378 address, chan, "");
3379 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3380 chan);
3381 src = LLVMBuildBitCast(
3382 ctx->ac.builder, src,
3383 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3384 LLVMBuildStore(ctx->ac.builder, src, ptr);
3385 }
3386 }
3387 break;
3388 }
3389 default:
3390 break;
3391 }
3392 }
3393
3394 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3395 {
3396 switch (dim) {
3397 case GLSL_SAMPLER_DIM_BUF:
3398 return 1;
3399 case GLSL_SAMPLER_DIM_1D:
3400 return array ? 2 : 1;
3401 case GLSL_SAMPLER_DIM_2D:
3402 return array ? 3 : 2;
3403 case GLSL_SAMPLER_DIM_MS:
3404 return array ? 4 : 3;
3405 case GLSL_SAMPLER_DIM_3D:
3406 case GLSL_SAMPLER_DIM_CUBE:
3407 return 3;
3408 case GLSL_SAMPLER_DIM_RECT:
3409 case GLSL_SAMPLER_DIM_SUBPASS:
3410 return 2;
3411 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3412 return 3;
3413 default:
3414 break;
3415 }
3416 return 0;
3417 }
3418
3419
3420
3421 /* Adjust the sample index according to FMASK.
3422 *
3423 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3424 * which is the identity mapping. Each nibble says which physical sample
3425 * should be fetched to get that sample.
3426 *
3427 * For example, 0x11111100 means there are only 2 samples stored and
3428 * the second sample covers 3/4 of the pixel. When reading samples 0
3429 * and 1, return physical sample 0 (determined by the first two 0s
3430 * in FMASK), otherwise return physical sample 1.
3431 *
3432 * The sample index should be adjusted as follows:
3433 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3434 */
3435 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3436 LLVMValueRef coord_x, LLVMValueRef coord_y,
3437 LLVMValueRef coord_z,
3438 LLVMValueRef sample_index,
3439 LLVMValueRef fmask_desc_ptr)
3440 {
3441 LLVMValueRef fmask_load_address[4];
3442 LLVMValueRef res;
3443
3444 fmask_load_address[0] = coord_x;
3445 fmask_load_address[1] = coord_y;
3446 if (coord_z) {
3447 fmask_load_address[2] = coord_z;
3448 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3449 }
3450
3451 struct ac_image_args args = {0};
3452
3453 args.opcode = ac_image_load;
3454 args.da = coord_z ? true : false;
3455 args.resource = fmask_desc_ptr;
3456 args.dmask = 0xf;
3457 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3458
3459 res = ac_build_image_opcode(ctx, &args);
3460
3461 res = ac_to_integer(ctx, res);
3462 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3463 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3464
3465 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3466 res,
3467 ctx->i32_0, "");
3468
3469 LLVMValueRef sample_index4 =
3470 LLVMBuildMul(ctx->builder, sample_index, four, "");
3471 LLVMValueRef shifted_fmask =
3472 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3473 LLVMValueRef final_sample =
3474 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3475
3476 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3477 * resource descriptor is 0 (invalid),
3478 */
3479 LLVMValueRef fmask_desc =
3480 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3481 ctx->v8i32, "");
3482
3483 LLVMValueRef fmask_word1 =
3484 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3485 ctx->i32_1, "");
3486
3487 LLVMValueRef word1_is_nonzero =
3488 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3489 fmask_word1, ctx->i32_0, "");
3490
3491 /* Replace the MSAA sample index. */
3492 sample_index =
3493 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3494 final_sample, sample_index, "");
3495 return sample_index;
3496 }
3497
3498 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3499 const nir_intrinsic_instr *instr)
3500 {
3501 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3502
3503 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3504 LLVMValueRef coords[4];
3505 LLVMValueRef masks[] = {
3506 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3507 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3508 };
3509 LLVMValueRef res;
3510 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3511
3512 int count;
3513 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3514 bool is_array = glsl_sampler_type_is_array(type);
3515 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3516 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3517 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3518 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3519 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3520 count = image_type_to_components_count(dim, is_array);
3521
3522 if (is_ms) {
3523 LLVMValueRef fmask_load_address[3];
3524 int chan;
3525
3526 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3527 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3528 if (is_array)
3529 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3530 else
3531 fmask_load_address[2] = NULL;
3532 if (add_frag_pos) {
3533 for (chan = 0; chan < 2; ++chan)
3534 fmask_load_address[chan] =
3535 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3536 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3537 ctx->ac.i32, ""), "");
3538 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3539 }
3540 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3541 fmask_load_address[0],
3542 fmask_load_address[1],
3543 fmask_load_address[2],
3544 sample_index,
3545 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3546 }
3547 if (count == 1 && !gfx9_1d) {
3548 if (instr->src[0].ssa->num_components)
3549 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3550 else
3551 res = src0;
3552 } else {
3553 int chan;
3554 if (is_ms)
3555 count--;
3556 for (chan = 0; chan < count; ++chan) {
3557 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3558 }
3559 if (add_frag_pos) {
3560 for (chan = 0; chan < 2; ++chan)
3561 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3562 ctx->ac.i32, ""), "");
3563 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3564 count++;
3565 }
3566
3567 if (gfx9_1d) {
3568 if (is_array) {
3569 coords[2] = coords[1];
3570 coords[1] = ctx->ac.i32_0;
3571 } else
3572 coords[1] = ctx->ac.i32_0;
3573 count++;
3574 }
3575
3576 if (is_ms) {
3577 coords[count] = sample_index;
3578 count++;
3579 }
3580
3581 if (count == 3) {
3582 coords[3] = LLVMGetUndef(ctx->ac.i32);
3583 count = 4;
3584 }
3585 res = ac_build_gather_values(&ctx->ac, coords, count);
3586 }
3587 return res;
3588 }
3589
3590 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3591 const nir_intrinsic_instr *instr)
3592 {
3593 LLVMValueRef params[7];
3594 LLVMValueRef res;
3595 char intrinsic_name[64];
3596 const nir_variable *var = instr->variables[0]->var;
3597 const struct glsl_type *type = var->type;
3598
3599 if(instr->variables[0]->deref.child)
3600 type = instr->variables[0]->deref.child->type;
3601
3602 type = glsl_without_array(type);
3603
3604 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3605 if (dim == GLSL_SAMPLER_DIM_BUF) {
3606 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3607 unsigned num_channels = util_last_bit(mask);
3608 LLVMValueRef rsrc, vindex;
3609
3610 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3611 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3612 ctx->ac.i32_0, "");
3613
3614 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3615 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3616 ctx->ac.i32_0, num_channels,
3617 false, false);
3618 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3619
3620 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3621 res = ac_to_integer(&ctx->ac, res);
3622 } else {
3623 bool is_da = glsl_sampler_type_is_array(type) ||
3624 dim == GLSL_SAMPLER_DIM_CUBE ||
3625 dim == GLSL_SAMPLER_DIM_3D ||
3626 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3627 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3628 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3629 LLVMValueRef glc = ctx->ac.i1false;
3630 LLVMValueRef slc = ctx->ac.i1false;
3631
3632 params[0] = get_image_coords(ctx, instr);
3633 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3634 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3635 params[3] = glc;
3636 params[4] = slc;
3637 params[5] = ctx->ac.i1false;
3638 params[6] = da;
3639
3640 ac_get_image_intr_name("llvm.amdgcn.image.load",
3641 ctx->ac.v4f32, /* vdata */
3642 LLVMTypeOf(params[0]), /* coords */
3643 LLVMTypeOf(params[1]), /* rsrc */
3644 intrinsic_name, sizeof(intrinsic_name));
3645
3646 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3647 params, 7, AC_FUNC_ATTR_READONLY);
3648 }
3649 return ac_to_integer(&ctx->ac, res);
3650 }
3651
3652 static void visit_image_store(struct ac_nir_context *ctx,
3653 nir_intrinsic_instr *instr)
3654 {
3655 LLVMValueRef params[8];
3656 char intrinsic_name[64];
3657 const nir_variable *var = instr->variables[0]->var;
3658 const struct glsl_type *type = glsl_without_array(var->type);
3659 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3660 LLVMValueRef glc = ctx->ac.i1false;
3661 bool force_glc = ctx->ac.chip_class == SI;
3662 if (force_glc)
3663 glc = ctx->ac.i1true;
3664
3665 if (dim == GLSL_SAMPLER_DIM_BUF) {
3666 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3667 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3668 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3669 ctx->ac.i32_0, ""); /* vindex */
3670 params[3] = ctx->ac.i32_0; /* voffset */
3671 params[4] = glc; /* glc */
3672 params[5] = ctx->ac.i1false; /* slc */
3673 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3674 params, 6, 0);
3675 } else {
3676 bool is_da = glsl_sampler_type_is_array(type) ||
3677 dim == GLSL_SAMPLER_DIM_CUBE ||
3678 dim == GLSL_SAMPLER_DIM_3D;
3679 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3680 LLVMValueRef slc = ctx->ac.i1false;
3681
3682 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3683 params[1] = get_image_coords(ctx, instr); /* coords */
3684 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3685 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3686 params[4] = glc;
3687 params[5] = slc;
3688 params[6] = ctx->ac.i1false;
3689 params[7] = da;
3690
3691 ac_get_image_intr_name("llvm.amdgcn.image.store",
3692 LLVMTypeOf(params[0]), /* vdata */
3693 LLVMTypeOf(params[1]), /* coords */
3694 LLVMTypeOf(params[2]), /* rsrc */
3695 intrinsic_name, sizeof(intrinsic_name));
3696
3697 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3698 params, 8, 0);
3699 }
3700
3701 }
3702
3703 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3704 const nir_intrinsic_instr *instr)
3705 {
3706 LLVMValueRef params[7];
3707 int param_count = 0;
3708 const nir_variable *var = instr->variables[0]->var;
3709
3710 const char *atomic_name;
3711 char intrinsic_name[41];
3712 const struct glsl_type *type = glsl_without_array(var->type);
3713 MAYBE_UNUSED int length;
3714
3715 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3716
3717 switch (instr->intrinsic) {
3718 case nir_intrinsic_image_atomic_add:
3719 atomic_name = "add";
3720 break;
3721 case nir_intrinsic_image_atomic_min:
3722 atomic_name = is_unsigned ? "umin" : "smin";
3723 break;
3724 case nir_intrinsic_image_atomic_max:
3725 atomic_name = is_unsigned ? "umax" : "smax";
3726 break;
3727 case nir_intrinsic_image_atomic_and:
3728 atomic_name = "and";
3729 break;
3730 case nir_intrinsic_image_atomic_or:
3731 atomic_name = "or";
3732 break;
3733 case nir_intrinsic_image_atomic_xor:
3734 atomic_name = "xor";
3735 break;
3736 case nir_intrinsic_image_atomic_exchange:
3737 atomic_name = "swap";
3738 break;
3739 case nir_intrinsic_image_atomic_comp_swap:
3740 atomic_name = "cmpswap";
3741 break;
3742 default:
3743 abort();
3744 }
3745
3746 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3747 params[param_count++] = get_src(ctx, instr->src[3]);
3748 params[param_count++] = get_src(ctx, instr->src[2]);
3749
3750 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3751 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3752 NULL, true, true);
3753 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3754 ctx->ac.i32_0, ""); /* vindex */
3755 params[param_count++] = ctx->ac.i32_0; /* voffset */
3756 params[param_count++] = ctx->ac.i1false; /* slc */
3757
3758 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3759 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3760 } else {
3761 char coords_type[8];
3762
3763 bool da = glsl_sampler_type_is_array(type) ||
3764 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3765
3766 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3767 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3768 NULL, true, true);
3769 params[param_count++] = ctx->ac.i1false; /* r128 */
3770 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3771 params[param_count++] = ctx->ac.i1false; /* slc */
3772
3773 build_int_type_name(LLVMTypeOf(coords),
3774 coords_type, sizeof(coords_type));
3775
3776 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3777 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3778 }
3779
3780 assert(length < sizeof(intrinsic_name));
3781 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3782 }
3783
3784 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3785 const nir_intrinsic_instr *instr)
3786 {
3787 LLVMValueRef res;
3788 const nir_variable *var = instr->variables[0]->var;
3789 const struct glsl_type *type = instr->variables[0]->var->type;
3790 bool da = glsl_sampler_type_is_array(var->type) ||
3791 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE ||
3792 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_3D;
3793 if(instr->variables[0]->deref.child)
3794 type = instr->variables[0]->deref.child->type;
3795
3796 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3797 return get_buffer_size(ctx,
3798 get_sampler_desc(ctx, instr->variables[0],
3799 AC_DESC_BUFFER, NULL, true, false), true);
3800
3801 struct ac_image_args args = { 0 };
3802
3803 args.da = da;
3804 args.dmask = 0xf;
3805 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3806 args.opcode = ac_image_get_resinfo;
3807 args.addr = ctx->ac.i32_0;
3808
3809 res = ac_build_image_opcode(&ctx->ac, &args);
3810
3811 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3812
3813 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3814 glsl_sampler_type_is_array(type)) {
3815 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3816 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3817 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3818 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3819 }
3820 if (ctx->ac.chip_class >= GFX9 &&
3821 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3822 glsl_sampler_type_is_array(type)) {
3823 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3824 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3825 ctx->ac.i32_1, "");
3826
3827 }
3828 return res;
3829 }
3830
3831 #define NOOP_WAITCNT 0xf7f
3832 #define LGKM_CNT 0x07f
3833 #define VM_CNT 0xf70
3834
3835 static void emit_membar(struct nir_to_llvm_context *ctx,
3836 const nir_intrinsic_instr *instr)
3837 {
3838 unsigned waitcnt = NOOP_WAITCNT;
3839
3840 switch (instr->intrinsic) {
3841 case nir_intrinsic_memory_barrier:
3842 case nir_intrinsic_group_memory_barrier:
3843 waitcnt &= VM_CNT & LGKM_CNT;
3844 break;
3845 case nir_intrinsic_memory_barrier_atomic_counter:
3846 case nir_intrinsic_memory_barrier_buffer:
3847 case nir_intrinsic_memory_barrier_image:
3848 waitcnt &= VM_CNT;
3849 break;
3850 case nir_intrinsic_memory_barrier_shared:
3851 waitcnt &= LGKM_CNT;
3852 break;
3853 default:
3854 break;
3855 }
3856 if (waitcnt != NOOP_WAITCNT)
3857 ac_build_waitcnt(&ctx->ac, waitcnt);
3858 }
3859
3860 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3861 {
3862 /* SI only (thanks to a hw bug workaround):
3863 * The real barrier instruction isn’t needed, because an entire patch
3864 * always fits into a single wave.
3865 */
3866 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3867 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3868 return;
3869 }
3870 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3871 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3872 }
3873
3874 static void emit_discard(struct ac_nir_context *ctx,
3875 const nir_intrinsic_instr *instr)
3876 {
3877 LLVMValueRef cond;
3878
3879 if (instr->intrinsic == nir_intrinsic_discard_if) {
3880 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3881 get_src(ctx, instr->src[0]),
3882 ctx->ac.i32_0, "");
3883 } else {
3884 assert(instr->intrinsic == nir_intrinsic_discard);
3885 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3886 }
3887
3888 ac_build_kill_if_false(&ctx->ac, cond);
3889 }
3890
3891 static LLVMValueRef
3892 visit_load_helper_invocation(struct ac_nir_context *ctx)
3893 {
3894 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3895 "llvm.amdgcn.ps.live",
3896 ctx->ac.i1, NULL, 0,
3897 AC_FUNC_ATTR_READNONE);
3898 result = LLVMBuildNot(ctx->ac.builder, result, "");
3899 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3900 }
3901
3902 static LLVMValueRef
3903 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3904 {
3905 LLVMValueRef result;
3906 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3907 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3908 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3909
3910 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3911 }
3912
3913 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3914 const nir_intrinsic_instr *instr)
3915 {
3916 LLVMValueRef ptr, result;
3917 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3918 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3919
3920 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3921 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3922 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3923 ptr, src, src1,
3924 LLVMAtomicOrderingSequentiallyConsistent,
3925 LLVMAtomicOrderingSequentiallyConsistent,
3926 false);
3927 } else {
3928 LLVMAtomicRMWBinOp op;
3929 switch (instr->intrinsic) {
3930 case nir_intrinsic_var_atomic_add:
3931 op = LLVMAtomicRMWBinOpAdd;
3932 break;
3933 case nir_intrinsic_var_atomic_umin:
3934 op = LLVMAtomicRMWBinOpUMin;
3935 break;
3936 case nir_intrinsic_var_atomic_umax:
3937 op = LLVMAtomicRMWBinOpUMax;
3938 break;
3939 case nir_intrinsic_var_atomic_imin:
3940 op = LLVMAtomicRMWBinOpMin;
3941 break;
3942 case nir_intrinsic_var_atomic_imax:
3943 op = LLVMAtomicRMWBinOpMax;
3944 break;
3945 case nir_intrinsic_var_atomic_and:
3946 op = LLVMAtomicRMWBinOpAnd;
3947 break;
3948 case nir_intrinsic_var_atomic_or:
3949 op = LLVMAtomicRMWBinOpOr;
3950 break;
3951 case nir_intrinsic_var_atomic_xor:
3952 op = LLVMAtomicRMWBinOpXor;
3953 break;
3954 case nir_intrinsic_var_atomic_exchange:
3955 op = LLVMAtomicRMWBinOpXchg;
3956 break;
3957 default:
3958 return NULL;
3959 }
3960
3961 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3962 LLVMAtomicOrderingSequentiallyConsistent,
3963 false);
3964 }
3965 return result;
3966 }
3967
3968 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
3969 enum glsl_interp_mode interp, unsigned location)
3970 {
3971 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3972
3973 switch (interp) {
3974 case INTERP_MODE_FLAT:
3975 default:
3976 return NULL;
3977 case INTERP_MODE_SMOOTH:
3978 case INTERP_MODE_NONE:
3979 if (location == INTERP_CENTER)
3980 return ctx->persp_center;
3981 else if (location == INTERP_CENTROID)
3982 return ctx->persp_centroid;
3983 else if (location == INTERP_SAMPLE)
3984 return ctx->persp_sample;
3985 break;
3986 case INTERP_MODE_NOPERSPECTIVE:
3987 if (location == INTERP_CENTER)
3988 return ctx->linear_center;
3989 else if (location == INTERP_CENTROID)
3990 return ctx->linear_centroid;
3991 else if (location == INTERP_SAMPLE)
3992 return ctx->linear_sample;
3993 break;
3994 }
3995 return NULL;
3996 }
3997
3998 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
3999 LLVMValueRef sample_id)
4000 {
4001 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4002
4003 LLVMValueRef result;
4004 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4005
4006 ptr = LLVMBuildBitCast(ctx->builder, ptr,
4007 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4008
4009 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
4010 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4011
4012 return result;
4013 }
4014
4015 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4016 {
4017 LLVMValueRef values[2];
4018
4019 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0], 32);
4020 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1], 32);
4021 return ac_build_gather_values(&ctx->ac, values, 2);
4022 }
4023
4024 static LLVMValueRef load_sample_mask_in(struct ac_nir_context *ctx)
4025 {
4026 uint8_t log2_ps_iter_samples = ctx->nctx->shader_info->info.ps.force_persample ? ctx->nctx->options->key.fs.log2_num_samples : ctx->nctx->options->key.fs.log2_ps_iter_samples;
4027
4028 /* The bit pattern matches that used by fixed function fragment
4029 * processing. */
4030 static const uint16_t ps_iter_masks[] = {
4031 0xffff, /* not used */
4032 0x5555,
4033 0x1111,
4034 0x0101,
4035 0x0001,
4036 };
4037 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4038
4039 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4040
4041 LLVMValueRef result, sample_id;
4042 sample_id = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4043 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4044 result = LLVMBuildAnd(ctx->ac.builder, sample_id, ctx->abi->sample_coverage, "");
4045 return result;
4046 }
4047
4048 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4049 const nir_intrinsic_instr *instr)
4050 {
4051 LLVMValueRef result[4];
4052 LLVMValueRef interp_param, attr_number;
4053 unsigned location;
4054 unsigned chan;
4055 LLVMValueRef src_c0 = NULL;
4056 LLVMValueRef src_c1 = NULL;
4057 LLVMValueRef src0 = NULL;
4058 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4059 switch (instr->intrinsic) {
4060 case nir_intrinsic_interp_var_at_centroid:
4061 location = INTERP_CENTROID;
4062 break;
4063 case nir_intrinsic_interp_var_at_sample:
4064 case nir_intrinsic_interp_var_at_offset:
4065 location = INTERP_CENTER;
4066 src0 = get_src(ctx, instr->src[0]);
4067 break;
4068 default:
4069 break;
4070 }
4071
4072 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4073 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4074 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4075 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4076 LLVMValueRef sample_position;
4077 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4078
4079 /* fetch sample ID */
4080 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4081
4082 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4083 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4084 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4085 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4086 }
4087 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4088 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4089
4090 if (location == INTERP_CENTER) {
4091 LLVMValueRef ij_out[2];
4092 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4093
4094 /*
4095 * take the I then J parameters, and the DDX/Y for it, and
4096 * calculate the IJ inputs for the interpolator.
4097 * temp1 = ddx * offset/sample.x + I;
4098 * interp_param.I = ddy * offset/sample.y + temp1;
4099 * temp1 = ddx * offset/sample.x + J;
4100 * interp_param.J = ddy * offset/sample.y + temp1;
4101 */
4102 for (unsigned i = 0; i < 2; i++) {
4103 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4104 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4105 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4106 ddxy_out, ix_ll, "");
4107 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4108 ddxy_out, iy_ll, "");
4109 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4110 interp_param, ix_ll, "");
4111 LLVMValueRef temp1, temp2;
4112
4113 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4114 ctx->ac.f32, "");
4115
4116 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4117 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4118
4119 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4120 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4121
4122 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4123 temp2, ctx->ac.i32, "");
4124 }
4125 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4126
4127 }
4128
4129 for (chan = 0; chan < 4; chan++) {
4130 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4131
4132 if (interp_param) {
4133 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4134 interp_param, ctx->ac.v2f32, "");
4135 LLVMValueRef i = LLVMBuildExtractElement(
4136 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4137 LLVMValueRef j = LLVMBuildExtractElement(
4138 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4139
4140 result[chan] = ac_build_fs_interp(&ctx->ac,
4141 llvm_chan, attr_number,
4142 ctx->abi->prim_mask, i, j);
4143 } else {
4144 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4145 LLVMConstInt(ctx->ac.i32, 2, false),
4146 llvm_chan, attr_number,
4147 ctx->abi->prim_mask);
4148 }
4149 }
4150 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4151 instr->variables[0]->var->data.location_frac);
4152 }
4153
4154 static void
4155 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4156 {
4157 LLVMValueRef gs_next_vertex;
4158 LLVMValueRef can_emit;
4159 int idx;
4160 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4161
4162 assert(stream == 0);
4163
4164 /* Write vertex attribute values to GSVS ring */
4165 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4166 ctx->gs_next_vertex,
4167 "");
4168
4169 /* If this thread has already emitted the declared maximum number of
4170 * vertices, kill it: excessive vertex emissions are not supposed to
4171 * have any effect, and GS threads have no externally observable
4172 * effects other than emitting vertices.
4173 */
4174 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4175 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4176 ac_build_kill_if_false(&ctx->ac, can_emit);
4177
4178 /* loop num outputs */
4179 idx = 0;
4180 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4181 LLVMValueRef *out_ptr = &addrs[i * 4];
4182 int length = 4;
4183 int slot = idx;
4184 int slot_inc = 1;
4185
4186 if (!(ctx->output_mask & (1ull << i)))
4187 continue;
4188
4189 if (i == VARYING_SLOT_CLIP_DIST0) {
4190 /* pack clip and cull into a single set of slots */
4191 length = ctx->num_output_clips + ctx->num_output_culls;
4192 if (length > 4)
4193 slot_inc = 2;
4194 }
4195 for (unsigned j = 0; j < length; j++) {
4196 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4197 out_ptr[j], "");
4198 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4199 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4200 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4201
4202 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4203
4204 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4205 out_val, 1,
4206 voffset, ctx->gs2vs_offset, 0,
4207 1, 1, true, true);
4208 }
4209 idx += slot_inc;
4210 }
4211
4212 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4213 ctx->ac.i32_1, "");
4214 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4215
4216 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4217 }
4218
4219 static void
4220 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4221 {
4222 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4223 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4224 }
4225
4226 static LLVMValueRef
4227 load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
4228 unsigned num_components)
4229 {
4230 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4231
4232 LLVMValueRef coord[4] = {
4233 ctx->tes_u,
4234 ctx->tes_v,
4235 ctx->ac.f32_0,
4236 ctx->ac.f32_0,
4237 };
4238
4239 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4240 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4241 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4242
4243 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, num_components);
4244 return LLVMBuildBitCast(ctx->builder, result, type, "");
4245 }
4246
4247 static LLVMValueRef
4248 load_patch_vertices_in(struct ac_shader_abi *abi)
4249 {
4250 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4251 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4252 }
4253
4254 static void visit_intrinsic(struct ac_nir_context *ctx,
4255 nir_intrinsic_instr *instr)
4256 {
4257 LLVMValueRef result = NULL;
4258
4259 switch (instr->intrinsic) {
4260 case nir_intrinsic_ballot:
4261 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4262 break;
4263 case nir_intrinsic_read_invocation:
4264 case nir_intrinsic_read_first_invocation: {
4265 LLVMValueRef args[2];
4266
4267 /* Value */
4268 args[0] = get_src(ctx, instr->src[0]);
4269
4270 unsigned num_args;
4271 const char *intr_name;
4272 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4273 num_args = 2;
4274 intr_name = "llvm.amdgcn.readlane";
4275
4276 /* Invocation */
4277 args[1] = get_src(ctx, instr->src[1]);
4278 } else {
4279 num_args = 1;
4280 intr_name = "llvm.amdgcn.readfirstlane";
4281 }
4282
4283 /* We currently have no other way to prevent LLVM from lifting the icmp
4284 * calls to a dominating basic block.
4285 */
4286 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4287
4288 result = ac_build_intrinsic(&ctx->ac, intr_name,
4289 ctx->ac.i32, args, num_args,
4290 AC_FUNC_ATTR_READNONE |
4291 AC_FUNC_ATTR_CONVERGENT);
4292 break;
4293 }
4294 case nir_intrinsic_load_subgroup_invocation:
4295 result = ac_get_thread_id(&ctx->ac);
4296 break;
4297 case nir_intrinsic_load_work_group_id: {
4298 LLVMValueRef values[3];
4299
4300 for (int i = 0; i < 3; i++) {
4301 values[i] = ctx->abi->workgroup_ids[i] ?
4302 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4303 }
4304
4305 result = ac_build_gather_values(&ctx->ac, values, 3);
4306 break;
4307 }
4308 case nir_intrinsic_load_base_vertex: {
4309 result = ctx->abi->base_vertex;
4310 break;
4311 }
4312 case nir_intrinsic_load_vertex_id_zero_base: {
4313 result = ctx->abi->vertex_id;
4314 break;
4315 }
4316 case nir_intrinsic_load_local_invocation_id: {
4317 result = ctx->nctx->local_invocation_ids;
4318 break;
4319 }
4320 case nir_intrinsic_load_base_instance:
4321 result = ctx->abi->start_instance;
4322 break;
4323 case nir_intrinsic_load_draw_id:
4324 result = ctx->abi->draw_id;
4325 break;
4326 case nir_intrinsic_load_view_index:
4327 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4328 break;
4329 case nir_intrinsic_load_invocation_id:
4330 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4331 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4332 else
4333 result = ctx->abi->gs_invocation_id;
4334 break;
4335 case nir_intrinsic_load_primitive_id:
4336 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4337 result = ctx->abi->gs_prim_id;
4338 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4339 result = ctx->abi->tcs_patch_id;
4340 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4341 result = ctx->abi->tes_patch_id;
4342 } else
4343 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4344 break;
4345 case nir_intrinsic_load_sample_id:
4346 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4347 break;
4348 case nir_intrinsic_load_sample_pos:
4349 result = load_sample_pos(ctx);
4350 break;
4351 case nir_intrinsic_load_sample_mask_in:
4352 if (ctx->nctx)
4353 result = load_sample_mask_in(ctx);
4354 else
4355 result = ctx->abi->sample_coverage;
4356 break;
4357 case nir_intrinsic_load_frag_coord: {
4358 LLVMValueRef values[4] = {
4359 ctx->abi->frag_pos[0],
4360 ctx->abi->frag_pos[1],
4361 ctx->abi->frag_pos[2],
4362 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4363 };
4364 result = ac_build_gather_values(&ctx->ac, values, 4);
4365 break;
4366 }
4367 case nir_intrinsic_load_front_face:
4368 result = ctx->abi->front_face;
4369 break;
4370 case nir_intrinsic_load_helper_invocation:
4371 result = visit_load_helper_invocation(ctx);
4372 break;
4373 case nir_intrinsic_load_instance_id:
4374 result = ctx->abi->instance_id;
4375 break;
4376 case nir_intrinsic_load_num_work_groups:
4377 result = ctx->nctx->num_work_groups;
4378 break;
4379 case nir_intrinsic_load_local_invocation_index:
4380 result = visit_load_local_invocation_index(ctx->nctx);
4381 break;
4382 case nir_intrinsic_load_push_constant:
4383 result = visit_load_push_constant(ctx->nctx, instr);
4384 break;
4385 case nir_intrinsic_vulkan_resource_index:
4386 result = visit_vulkan_resource_index(ctx->nctx, instr);
4387 break;
4388 case nir_intrinsic_vulkan_resource_reindex:
4389 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4390 break;
4391 case nir_intrinsic_store_ssbo:
4392 visit_store_ssbo(ctx, instr);
4393 break;
4394 case nir_intrinsic_load_ssbo:
4395 result = visit_load_buffer(ctx, instr);
4396 break;
4397 case nir_intrinsic_ssbo_atomic_add:
4398 case nir_intrinsic_ssbo_atomic_imin:
4399 case nir_intrinsic_ssbo_atomic_umin:
4400 case nir_intrinsic_ssbo_atomic_imax:
4401 case nir_intrinsic_ssbo_atomic_umax:
4402 case nir_intrinsic_ssbo_atomic_and:
4403 case nir_intrinsic_ssbo_atomic_or:
4404 case nir_intrinsic_ssbo_atomic_xor:
4405 case nir_intrinsic_ssbo_atomic_exchange:
4406 case nir_intrinsic_ssbo_atomic_comp_swap:
4407 result = visit_atomic_ssbo(ctx, instr);
4408 break;
4409 case nir_intrinsic_load_ubo:
4410 result = visit_load_ubo_buffer(ctx, instr);
4411 break;
4412 case nir_intrinsic_get_buffer_size:
4413 result = visit_get_buffer_size(ctx, instr);
4414 break;
4415 case nir_intrinsic_load_var:
4416 result = visit_load_var(ctx, instr);
4417 break;
4418 case nir_intrinsic_store_var:
4419 visit_store_var(ctx, instr);
4420 break;
4421 case nir_intrinsic_image_load:
4422 result = visit_image_load(ctx, instr);
4423 break;
4424 case nir_intrinsic_image_store:
4425 visit_image_store(ctx, instr);
4426 break;
4427 case nir_intrinsic_image_atomic_add:
4428 case nir_intrinsic_image_atomic_min:
4429 case nir_intrinsic_image_atomic_max:
4430 case nir_intrinsic_image_atomic_and:
4431 case nir_intrinsic_image_atomic_or:
4432 case nir_intrinsic_image_atomic_xor:
4433 case nir_intrinsic_image_atomic_exchange:
4434 case nir_intrinsic_image_atomic_comp_swap:
4435 result = visit_image_atomic(ctx, instr);
4436 break;
4437 case nir_intrinsic_image_size:
4438 result = visit_image_size(ctx, instr);
4439 break;
4440 case nir_intrinsic_discard:
4441 case nir_intrinsic_discard_if:
4442 emit_discard(ctx, instr);
4443 break;
4444 case nir_intrinsic_memory_barrier:
4445 case nir_intrinsic_group_memory_barrier:
4446 case nir_intrinsic_memory_barrier_atomic_counter:
4447 case nir_intrinsic_memory_barrier_buffer:
4448 case nir_intrinsic_memory_barrier_image:
4449 case nir_intrinsic_memory_barrier_shared:
4450 emit_membar(ctx->nctx, instr);
4451 break;
4452 case nir_intrinsic_barrier:
4453 emit_barrier(&ctx->ac, ctx->stage);
4454 break;
4455 case nir_intrinsic_var_atomic_add:
4456 case nir_intrinsic_var_atomic_imin:
4457 case nir_intrinsic_var_atomic_umin:
4458 case nir_intrinsic_var_atomic_imax:
4459 case nir_intrinsic_var_atomic_umax:
4460 case nir_intrinsic_var_atomic_and:
4461 case nir_intrinsic_var_atomic_or:
4462 case nir_intrinsic_var_atomic_xor:
4463 case nir_intrinsic_var_atomic_exchange:
4464 case nir_intrinsic_var_atomic_comp_swap:
4465 result = visit_var_atomic(ctx->nctx, instr);
4466 break;
4467 case nir_intrinsic_interp_var_at_centroid:
4468 case nir_intrinsic_interp_var_at_sample:
4469 case nir_intrinsic_interp_var_at_offset:
4470 result = visit_interp(ctx, instr);
4471 break;
4472 case nir_intrinsic_emit_vertex:
4473 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->outputs);
4474 break;
4475 case nir_intrinsic_end_primitive:
4476 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4477 break;
4478 case nir_intrinsic_load_tess_coord: {
4479 LLVMTypeRef type = ctx->nctx ?
4480 get_def_type(ctx->nctx->nir, &instr->dest.ssa) :
4481 NULL;
4482 result = ctx->abi->load_tess_coord(ctx->abi, type, instr->num_components);
4483 break;
4484 }
4485 case nir_intrinsic_load_tess_level_outer:
4486 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4487 break;
4488 case nir_intrinsic_load_tess_level_inner:
4489 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4490 break;
4491 case nir_intrinsic_load_patch_vertices_in:
4492 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4493 break;
4494 case nir_intrinsic_vote_all: {
4495 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4496 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4497 break;
4498 }
4499 case nir_intrinsic_vote_any: {
4500 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4501 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4502 break;
4503 }
4504 case nir_intrinsic_vote_eq: {
4505 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4506 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4507 break;
4508 }
4509 default:
4510 fprintf(stderr, "Unknown intrinsic: ");
4511 nir_print_instr(&instr->instr, stderr);
4512 fprintf(stderr, "\n");
4513 break;
4514 }
4515 if (result) {
4516 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4517 }
4518 }
4519
4520 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4521 LLVMValueRef buffer_ptr, bool write)
4522 {
4523 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4524 LLVMValueRef result;
4525
4526 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4527
4528 result = LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4529 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4530
4531 return result;
4532 }
4533
4534 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4535 {
4536 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4537 LLVMValueRef result;
4538
4539 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4540
4541 result = LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4542 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4543
4544 return result;
4545 }
4546
4547 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4548 unsigned descriptor_set,
4549 unsigned base_index,
4550 unsigned constant_index,
4551 LLVMValueRef index,
4552 enum ac_descriptor_type desc_type,
4553 bool image, bool write)
4554 {
4555 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4556 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4557 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4558 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4559 unsigned offset = binding->offset;
4560 unsigned stride = binding->size;
4561 unsigned type_size;
4562 LLVMBuilderRef builder = ctx->builder;
4563 LLVMTypeRef type;
4564
4565 assert(base_index < layout->binding_count);
4566
4567 switch (desc_type) {
4568 case AC_DESC_IMAGE:
4569 type = ctx->ac.v8i32;
4570 type_size = 32;
4571 break;
4572 case AC_DESC_FMASK:
4573 type = ctx->ac.v8i32;
4574 offset += 32;
4575 type_size = 32;
4576 break;
4577 case AC_DESC_SAMPLER:
4578 type = ctx->ac.v4i32;
4579 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4580 offset += 64;
4581
4582 type_size = 16;
4583 break;
4584 case AC_DESC_BUFFER:
4585 type = ctx->ac.v4i32;
4586 type_size = 16;
4587 break;
4588 default:
4589 unreachable("invalid desc_type\n");
4590 }
4591
4592 offset += constant_index * stride;
4593
4594 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4595 (!index || binding->immutable_samplers_equal)) {
4596 if (binding->immutable_samplers_equal)
4597 constant_index = 0;
4598
4599 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4600
4601 LLVMValueRef constants[] = {
4602 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4603 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4604 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4605 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4606 };
4607 return ac_build_gather_values(&ctx->ac, constants, 4);
4608 }
4609
4610 assert(stride % type_size == 0);
4611
4612 if (!index)
4613 index = ctx->ac.i32_0;
4614
4615 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4616
4617 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4618 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4619
4620 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4621 }
4622
4623 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4624 const nir_deref_var *deref,
4625 enum ac_descriptor_type desc_type,
4626 const nir_tex_instr *tex_instr,
4627 bool image, bool write)
4628 {
4629 LLVMValueRef index = NULL;
4630 unsigned constant_index = 0;
4631 unsigned descriptor_set;
4632 unsigned base_index;
4633
4634 if (!deref) {
4635 assert(tex_instr && !image);
4636 descriptor_set = 0;
4637 base_index = tex_instr->sampler_index;
4638 } else {
4639 const nir_deref *tail = &deref->deref;
4640 while (tail->child) {
4641 const nir_deref_array *child = nir_deref_as_array(tail->child);
4642 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4643
4644 if (!array_size)
4645 array_size = 1;
4646
4647 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4648
4649 if (child->deref_array_type == nir_deref_array_type_indirect) {
4650 LLVMValueRef indirect = get_src(ctx, child->indirect);
4651
4652 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4653 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4654
4655 if (!index)
4656 index = indirect;
4657 else
4658 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4659 }
4660
4661 constant_index += child->base_offset * array_size;
4662
4663 tail = &child->deref;
4664 }
4665 descriptor_set = deref->var->data.descriptor_set;
4666 base_index = deref->var->data.binding;
4667 }
4668
4669 return ctx->abi->load_sampler_desc(ctx->abi,
4670 descriptor_set,
4671 base_index,
4672 constant_index, index,
4673 desc_type, image, write);
4674 }
4675
4676 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4677 struct ac_image_args *args,
4678 const nir_tex_instr *instr,
4679 nir_texop op,
4680 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4681 LLVMValueRef *param, unsigned count,
4682 unsigned dmask)
4683 {
4684 unsigned is_rect = 0;
4685 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4686
4687 if (op == nir_texop_lod)
4688 da = false;
4689 /* Pad to power of two vector */
4690 while (count < util_next_power_of_two(count))
4691 param[count++] = LLVMGetUndef(ctx->i32);
4692
4693 if (count > 1)
4694 args->addr = ac_build_gather_values(ctx, param, count);
4695 else
4696 args->addr = param[0];
4697
4698 args->resource = res_ptr;
4699 args->sampler = samp_ptr;
4700
4701 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4702 args->addr = param[0];
4703 return;
4704 }
4705
4706 args->dmask = dmask;
4707 args->unorm = is_rect;
4708 args->da = da;
4709 }
4710
4711 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4712 *
4713 * SI-CI:
4714 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4715 * filtering manually. The driver sets img7 to a mask clearing
4716 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4717 * s_and_b32 samp0, samp0, img7
4718 *
4719 * VI:
4720 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4721 */
4722 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4723 LLVMValueRef res, LLVMValueRef samp)
4724 {
4725 LLVMBuilderRef builder = ctx->ac.builder;
4726 LLVMValueRef img7, samp0;
4727
4728 if (ctx->ac.chip_class >= VI)
4729 return samp;
4730
4731 img7 = LLVMBuildExtractElement(builder, res,
4732 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4733 samp0 = LLVMBuildExtractElement(builder, samp,
4734 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4735 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4736 return LLVMBuildInsertElement(builder, samp, samp0,
4737 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4738 }
4739
4740 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4741 nir_tex_instr *instr,
4742 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4743 LLVMValueRef *fmask_ptr)
4744 {
4745 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4746 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4747 else
4748 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4749 if (samp_ptr) {
4750 if (instr->sampler)
4751 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4752 else
4753 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4754 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4755 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4756 }
4757 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4758 instr->op == nir_texop_samples_identical))
4759 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4760 }
4761
4762 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4763 LLVMValueRef coord)
4764 {
4765 coord = ac_to_float(ctx, coord);
4766 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4767 coord = ac_to_integer(ctx, coord);
4768 return coord;
4769 }
4770
4771 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4772 {
4773 LLVMValueRef result = NULL;
4774 struct ac_image_args args = { 0 };
4775 unsigned dmask = 0xf;
4776 LLVMValueRef address[16];
4777 LLVMValueRef coords[5];
4778 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4779 LLVMValueRef bias = NULL, offsets = NULL;
4780 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4781 LLVMValueRef ddx = NULL, ddy = NULL;
4782 LLVMValueRef derivs[6];
4783 unsigned chan, count = 0;
4784 unsigned const_src = 0, num_deriv_comp = 0;
4785 bool lod_is_zero = false;
4786
4787 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4788
4789 for (unsigned i = 0; i < instr->num_srcs; i++) {
4790 switch (instr->src[i].src_type) {
4791 case nir_tex_src_coord:
4792 coord = get_src(ctx, instr->src[i].src);
4793 break;
4794 case nir_tex_src_projector:
4795 break;
4796 case nir_tex_src_comparator:
4797 comparator = get_src(ctx, instr->src[i].src);
4798 break;
4799 case nir_tex_src_offset:
4800 offsets = get_src(ctx, instr->src[i].src);
4801 const_src = i;
4802 break;
4803 case nir_tex_src_bias:
4804 bias = get_src(ctx, instr->src[i].src);
4805 break;
4806 case nir_tex_src_lod: {
4807 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4808
4809 if (val && val->i32[0] == 0)
4810 lod_is_zero = true;
4811 lod = get_src(ctx, instr->src[i].src);
4812 break;
4813 }
4814 case nir_tex_src_ms_index:
4815 sample_index = get_src(ctx, instr->src[i].src);
4816 break;
4817 case nir_tex_src_ms_mcs:
4818 break;
4819 case nir_tex_src_ddx:
4820 ddx = get_src(ctx, instr->src[i].src);
4821 num_deriv_comp = instr->src[i].src.ssa->num_components;
4822 break;
4823 case nir_tex_src_ddy:
4824 ddy = get_src(ctx, instr->src[i].src);
4825 break;
4826 case nir_tex_src_texture_offset:
4827 case nir_tex_src_sampler_offset:
4828 case nir_tex_src_plane:
4829 default:
4830 break;
4831 }
4832 }
4833
4834 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4835 result = get_buffer_size(ctx, res_ptr, true);
4836 goto write_result;
4837 }
4838
4839 if (instr->op == nir_texop_texture_samples) {
4840 LLVMValueRef res, samples, is_msaa;
4841 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4842 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4843 LLVMConstInt(ctx->ac.i32, 3, false), "");
4844 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4845 LLVMConstInt(ctx->ac.i32, 28, false), "");
4846 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4847 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4848 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4849 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4850
4851 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4852 LLVMConstInt(ctx->ac.i32, 16, false), "");
4853 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4854 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4855 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4856 samples, "");
4857 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4858 ctx->ac.i32_1, "");
4859 result = samples;
4860 goto write_result;
4861 }
4862
4863 if (coord)
4864 for (chan = 0; chan < instr->coord_components; chan++)
4865 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4866
4867 if (offsets && instr->op != nir_texop_txf) {
4868 LLVMValueRef offset[3], pack;
4869 for (chan = 0; chan < 3; ++chan)
4870 offset[chan] = ctx->ac.i32_0;
4871
4872 args.offset = true;
4873 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4874 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4875 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4876 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4877 if (chan)
4878 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4879 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4880 }
4881 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4882 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4883 address[count++] = pack;
4884
4885 }
4886 /* pack LOD bias value */
4887 if (instr->op == nir_texop_txb && bias) {
4888 address[count++] = bias;
4889 }
4890
4891 /* Pack depth comparison value */
4892 if (instr->is_shadow && comparator) {
4893 LLVMValueRef z = ac_to_float(&ctx->ac,
4894 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4895
4896 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4897 * so the depth comparison value isn't clamped for Z16 and
4898 * Z24 anymore. Do it manually here.
4899 *
4900 * It's unnecessary if the original texture format was
4901 * Z32_FLOAT, but we don't know that here.
4902 */
4903 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4904 z = ac_build_clamp(&ctx->ac, z);
4905
4906 address[count++] = z;
4907 }
4908
4909 /* pack derivatives */
4910 if (ddx || ddy) {
4911 int num_src_deriv_channels, num_dest_deriv_channels;
4912 switch (instr->sampler_dim) {
4913 case GLSL_SAMPLER_DIM_3D:
4914 case GLSL_SAMPLER_DIM_CUBE:
4915 num_deriv_comp = 3;
4916 num_src_deriv_channels = 3;
4917 num_dest_deriv_channels = 3;
4918 break;
4919 case GLSL_SAMPLER_DIM_2D:
4920 default:
4921 num_src_deriv_channels = 2;
4922 num_dest_deriv_channels = 2;
4923 num_deriv_comp = 2;
4924 break;
4925 case GLSL_SAMPLER_DIM_1D:
4926 num_src_deriv_channels = 1;
4927 if (ctx->ac.chip_class >= GFX9) {
4928 num_dest_deriv_channels = 2;
4929 num_deriv_comp = 2;
4930 } else {
4931 num_dest_deriv_channels = 1;
4932 num_deriv_comp = 1;
4933 }
4934 break;
4935 }
4936
4937 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4938 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4939 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4940 }
4941 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4942 derivs[i] = ctx->ac.f32_0;
4943 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4944 }
4945 }
4946
4947 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4948 for (chan = 0; chan < instr->coord_components; chan++)
4949 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4950 if (instr->coord_components == 3)
4951 coords[3] = LLVMGetUndef(ctx->ac.f32);
4952 ac_prepare_cube_coords(&ctx->ac,
4953 instr->op == nir_texop_txd, instr->is_array,
4954 instr->op == nir_texop_lod, coords, derivs);
4955 if (num_deriv_comp)
4956 num_deriv_comp--;
4957 }
4958
4959 if (ddx || ddy) {
4960 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4961 address[count++] = derivs[i];
4962 }
4963
4964 /* Pack texture coordinates */
4965 if (coord) {
4966 address[count++] = coords[0];
4967 if (instr->coord_components > 1) {
4968 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4969 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4970 }
4971 address[count++] = coords[1];
4972 }
4973 if (instr->coord_components > 2) {
4974 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4975 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4976 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4977 instr->op != nir_texop_txf) {
4978 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4979 }
4980 address[count++] = coords[2];
4981 }
4982
4983 if (ctx->ac.chip_class >= GFX9) {
4984 LLVMValueRef filler;
4985 if (instr->op == nir_texop_txf)
4986 filler = ctx->ac.i32_0;
4987 else
4988 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4989
4990 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4991 /* No nir_texop_lod, because it does not take a slice
4992 * even with array textures. */
4993 if (instr->is_array && instr->op != nir_texop_lod ) {
4994 address[count] = address[count - 1];
4995 address[count - 1] = filler;
4996 count++;
4997 } else
4998 address[count++] = filler;
4999 }
5000 }
5001 }
5002
5003 /* Pack LOD */
5004 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5005 instr->op == nir_texop_txf)) {
5006 address[count++] = lod;
5007 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5008 address[count++] = sample_index;
5009 } else if(instr->op == nir_texop_txs) {
5010 count = 0;
5011 if (lod)
5012 address[count++] = lod;
5013 else
5014 address[count++] = ctx->ac.i32_0;
5015 }
5016
5017 for (chan = 0; chan < count; chan++) {
5018 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5019 address[chan], ctx->ac.i32, "");
5020 }
5021
5022 if (instr->op == nir_texop_samples_identical) {
5023 LLVMValueRef txf_address[4];
5024 struct ac_image_args txf_args = { 0 };
5025 unsigned txf_count = count;
5026 memcpy(txf_address, address, sizeof(txf_address));
5027
5028 if (!instr->is_array)
5029 txf_address[2] = ctx->ac.i32_0;
5030 txf_address[3] = ctx->ac.i32_0;
5031
5032 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5033 fmask_ptr, NULL,
5034 txf_address, txf_count, 0xf);
5035
5036 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5037
5038 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5039 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5040 goto write_result;
5041 }
5042
5043 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5044 instr->op != nir_texop_txs) {
5045 unsigned sample_chan = instr->is_array ? 3 : 2;
5046 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5047 address[0],
5048 address[1],
5049 instr->is_array ? address[2] : NULL,
5050 address[sample_chan],
5051 fmask_ptr);
5052 }
5053
5054 if (offsets && instr->op == nir_texop_txf) {
5055 nir_const_value *const_offset =
5056 nir_src_as_const_value(instr->src[const_src].src);
5057 int num_offsets = instr->src[const_src].src.ssa->num_components;
5058 assert(const_offset);
5059 num_offsets = MIN2(num_offsets, instr->coord_components);
5060 if (num_offsets > 2)
5061 address[2] = LLVMBuildAdd(ctx->ac.builder,
5062 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5063 if (num_offsets > 1)
5064 address[1] = LLVMBuildAdd(ctx->ac.builder,
5065 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5066 address[0] = LLVMBuildAdd(ctx->ac.builder,
5067 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5068
5069 }
5070
5071 /* TODO TG4 support */
5072 if (instr->op == nir_texop_tg4) {
5073 if (instr->is_shadow)
5074 dmask = 1;
5075 else
5076 dmask = 1 << instr->component;
5077 }
5078 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5079 res_ptr, samp_ptr, address, count, dmask);
5080
5081 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5082
5083 if (instr->op == nir_texop_query_levels)
5084 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5085 else if (instr->is_shadow && instr->is_new_style_shadow &&
5086 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5087 instr->op != nir_texop_tg4)
5088 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5089 else if (instr->op == nir_texop_txs &&
5090 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5091 instr->is_array) {
5092 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5093 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5094 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5095 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5096 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5097 } else if (ctx->ac.chip_class >= GFX9 &&
5098 instr->op == nir_texop_txs &&
5099 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5100 instr->is_array) {
5101 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5102 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5103 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5104 ctx->ac.i32_1, "");
5105 } else if (instr->dest.ssa.num_components != 4)
5106 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5107
5108 write_result:
5109 if (result) {
5110 assert(instr->dest.is_ssa);
5111 result = ac_to_integer(&ctx->ac, result);
5112 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5113 }
5114 }
5115
5116
5117 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5118 {
5119 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5120 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5121
5122 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5123 _mesa_hash_table_insert(ctx->phis, instr, result);
5124 }
5125
5126 static void visit_post_phi(struct ac_nir_context *ctx,
5127 nir_phi_instr *instr,
5128 LLVMValueRef llvm_phi)
5129 {
5130 nir_foreach_phi_src(src, instr) {
5131 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5132 LLVMValueRef llvm_src = get_src(ctx, src->src);
5133
5134 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5135 }
5136 }
5137
5138 static void phi_post_pass(struct ac_nir_context *ctx)
5139 {
5140 struct hash_entry *entry;
5141 hash_table_foreach(ctx->phis, entry) {
5142 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5143 (LLVMValueRef)entry->data);
5144 }
5145 }
5146
5147
5148 static void visit_ssa_undef(struct ac_nir_context *ctx,
5149 const nir_ssa_undef_instr *instr)
5150 {
5151 unsigned num_components = instr->def.num_components;
5152 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5153 LLVMValueRef undef;
5154
5155 if (num_components == 1)
5156 undef = LLVMGetUndef(type);
5157 else {
5158 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5159 }
5160 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5161 }
5162
5163 static void visit_jump(struct ac_nir_context *ctx,
5164 const nir_jump_instr *instr)
5165 {
5166 switch (instr->type) {
5167 case nir_jump_break:
5168 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5169 LLVMClearInsertionPosition(ctx->ac.builder);
5170 break;
5171 case nir_jump_continue:
5172 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5173 LLVMClearInsertionPosition(ctx->ac.builder);
5174 break;
5175 default:
5176 fprintf(stderr, "Unknown NIR jump instr: ");
5177 nir_print_instr(&instr->instr, stderr);
5178 fprintf(stderr, "\n");
5179 abort();
5180 }
5181 }
5182
5183 static void visit_cf_list(struct ac_nir_context *ctx,
5184 struct exec_list *list);
5185
5186 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5187 {
5188 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5189 nir_foreach_instr(instr, block)
5190 {
5191 switch (instr->type) {
5192 case nir_instr_type_alu:
5193 visit_alu(ctx, nir_instr_as_alu(instr));
5194 break;
5195 case nir_instr_type_load_const:
5196 visit_load_const(ctx, nir_instr_as_load_const(instr));
5197 break;
5198 case nir_instr_type_intrinsic:
5199 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5200 break;
5201 case nir_instr_type_tex:
5202 visit_tex(ctx, nir_instr_as_tex(instr));
5203 break;
5204 case nir_instr_type_phi:
5205 visit_phi(ctx, nir_instr_as_phi(instr));
5206 break;
5207 case nir_instr_type_ssa_undef:
5208 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5209 break;
5210 case nir_instr_type_jump:
5211 visit_jump(ctx, nir_instr_as_jump(instr));
5212 break;
5213 default:
5214 fprintf(stderr, "Unknown NIR instr type: ");
5215 nir_print_instr(instr, stderr);
5216 fprintf(stderr, "\n");
5217 abort();
5218 }
5219 }
5220
5221 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5222 }
5223
5224 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5225 {
5226 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5227
5228 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5229 LLVMBasicBlockRef merge_block =
5230 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5231 LLVMBasicBlockRef if_block =
5232 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5233 LLVMBasicBlockRef else_block = merge_block;
5234 if (!exec_list_is_empty(&if_stmt->else_list))
5235 else_block = LLVMAppendBasicBlockInContext(
5236 ctx->ac.context, fn, "");
5237
5238 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5239 ctx->ac.i32_0, "");
5240 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5241
5242 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5243 visit_cf_list(ctx, &if_stmt->then_list);
5244 if (LLVMGetInsertBlock(ctx->ac.builder))
5245 LLVMBuildBr(ctx->ac.builder, merge_block);
5246
5247 if (!exec_list_is_empty(&if_stmt->else_list)) {
5248 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5249 visit_cf_list(ctx, &if_stmt->else_list);
5250 if (LLVMGetInsertBlock(ctx->ac.builder))
5251 LLVMBuildBr(ctx->ac.builder, merge_block);
5252 }
5253
5254 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5255 }
5256
5257 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5258 {
5259 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5260 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5261 LLVMBasicBlockRef break_parent = ctx->break_block;
5262
5263 ctx->continue_block =
5264 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5265 ctx->break_block =
5266 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5267
5268 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5269 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5270 visit_cf_list(ctx, &loop->body);
5271
5272 if (LLVMGetInsertBlock(ctx->ac.builder))
5273 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5274 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5275
5276 ctx->continue_block = continue_parent;
5277 ctx->break_block = break_parent;
5278 }
5279
5280 static void visit_cf_list(struct ac_nir_context *ctx,
5281 struct exec_list *list)
5282 {
5283 foreach_list_typed(nir_cf_node, node, node, list)
5284 {
5285 switch (node->type) {
5286 case nir_cf_node_block:
5287 visit_block(ctx, nir_cf_node_as_block(node));
5288 break;
5289
5290 case nir_cf_node_if:
5291 visit_if(ctx, nir_cf_node_as_if(node));
5292 break;
5293
5294 case nir_cf_node_loop:
5295 visit_loop(ctx, nir_cf_node_as_loop(node));
5296 break;
5297
5298 default:
5299 assert(0);
5300 }
5301 }
5302 }
5303
5304 static void
5305 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5306 struct nir_variable *variable)
5307 {
5308 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5309 LLVMValueRef t_offset;
5310 LLVMValueRef t_list;
5311 LLVMValueRef input;
5312 LLVMValueRef buffer_index;
5313 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5314 int idx = variable->data.location;
5315 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5316
5317 variable->data.driver_location = idx * 4;
5318
5319 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5320 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5321 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5322 ctx->abi.start_instance, "");
5323 if (ctx->options->key.vs.as_ls) {
5324 ctx->shader_info->vs.vgpr_comp_cnt =
5325 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5326 } else {
5327 ctx->shader_info->vs.vgpr_comp_cnt =
5328 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5329 }
5330 } else
5331 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5332 ctx->abi.base_vertex, "");
5333 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5334
5335 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5336
5337 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5338 buffer_index,
5339 ctx->ac.i32_0,
5340 4, false, true);
5341
5342 for (unsigned chan = 0; chan < 4; chan++) {
5343 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5344 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5345 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5346 input, llvm_chan, ""));
5347 }
5348 }
5349 }
5350
5351 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5352 unsigned attr,
5353 LLVMValueRef interp_param,
5354 LLVMValueRef prim_mask,
5355 LLVMValueRef result[4])
5356 {
5357 LLVMValueRef attr_number;
5358 unsigned chan;
5359 LLVMValueRef i, j;
5360 bool interp = interp_param != NULL;
5361
5362 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5363
5364 /* fs.constant returns the param from the middle vertex, so it's not
5365 * really useful for flat shading. It's meant to be used for custom
5366 * interpolation (but the intrinsic can't fetch from the other two
5367 * vertices).
5368 *
5369 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5370 * to do the right thing. The only reason we use fs.constant is that
5371 * fs.interp cannot be used on integers, because they can be equal
5372 * to NaN.
5373 */
5374 if (interp) {
5375 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5376 ctx->ac.v2f32, "");
5377
5378 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5379 ctx->ac.i32_0, "");
5380 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5381 ctx->ac.i32_1, "");
5382 }
5383
5384 for (chan = 0; chan < 4; chan++) {
5385 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5386
5387 if (interp) {
5388 result[chan] = ac_build_fs_interp(&ctx->ac,
5389 llvm_chan,
5390 attr_number,
5391 prim_mask, i, j);
5392 } else {
5393 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5394 LLVMConstInt(ctx->ac.i32, 2, false),
5395 llvm_chan,
5396 attr_number,
5397 prim_mask);
5398 }
5399 }
5400 }
5401
5402 static void
5403 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5404 struct nir_variable *variable)
5405 {
5406 int idx = variable->data.location;
5407 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5408 LLVMValueRef interp;
5409
5410 variable->data.driver_location = idx * 4;
5411 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5412
5413 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5414 unsigned interp_type;
5415 if (variable->data.sample) {
5416 interp_type = INTERP_SAMPLE;
5417 ctx->shader_info->info.ps.force_persample = true;
5418 } else if (variable->data.centroid)
5419 interp_type = INTERP_CENTROID;
5420 else
5421 interp_type = INTERP_CENTER;
5422
5423 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5424 } else
5425 interp = NULL;
5426
5427 for (unsigned i = 0; i < attrib_count; ++i)
5428 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5429
5430 }
5431
5432 static void
5433 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5434 struct nir_shader *nir) {
5435 nir_foreach_variable(variable, &nir->inputs)
5436 handle_vs_input_decl(ctx, variable);
5437 }
5438
5439 static void
5440 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5441 struct nir_shader *nir)
5442 {
5443 if (!ctx->options->key.fs.multisample)
5444 return;
5445
5446 bool uses_center = false;
5447 bool uses_centroid = false;
5448 nir_foreach_variable(variable, &nir->inputs) {
5449 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5450 variable->data.sample)
5451 continue;
5452
5453 if (variable->data.centroid)
5454 uses_centroid = true;
5455 else
5456 uses_center = true;
5457 }
5458
5459 if (uses_center && uses_centroid) {
5460 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5461 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5462 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5463 }
5464 }
5465
5466 static void
5467 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5468 struct nir_shader *nir)
5469 {
5470 prepare_interp_optimize(ctx, nir);
5471
5472 nir_foreach_variable(variable, &nir->inputs)
5473 handle_fs_input_decl(ctx, variable);
5474
5475 unsigned index = 0;
5476
5477 if (ctx->shader_info->info.ps.uses_input_attachments ||
5478 ctx->shader_info->info.needs_multiview_view_index)
5479 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5480
5481 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5482 LLVMValueRef interp_param;
5483 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5484
5485 if (!(ctx->input_mask & (1ull << i)))
5486 continue;
5487
5488 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5489 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5490 interp_param = *inputs;
5491 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5492 inputs);
5493
5494 if (!interp_param)
5495 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5496 ++index;
5497 } else if (i == VARYING_SLOT_POS) {
5498 for(int i = 0; i < 3; ++i)
5499 inputs[i] = ctx->abi.frag_pos[i];
5500
5501 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5502 ctx->abi.frag_pos[3]);
5503 }
5504 }
5505 ctx->shader_info->fs.num_interp = index;
5506 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5507 ctx->shader_info->fs.has_pcoord = true;
5508 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5509 ctx->shader_info->fs.prim_id_input = true;
5510 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5511 ctx->shader_info->fs.layer_input = true;
5512 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5513
5514 if (ctx->shader_info->info.needs_multiview_view_index)
5515 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5516 }
5517
5518 static LLVMValueRef
5519 ac_build_alloca(struct ac_llvm_context *ac,
5520 LLVMTypeRef type,
5521 const char *name)
5522 {
5523 LLVMBuilderRef builder = ac->builder;
5524 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5525 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5526 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5527 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5528 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5529 LLVMValueRef res;
5530
5531 if (first_instr) {
5532 LLVMPositionBuilderBefore(first_builder, first_instr);
5533 } else {
5534 LLVMPositionBuilderAtEnd(first_builder, first_block);
5535 }
5536
5537 res = LLVMBuildAlloca(first_builder, type, name);
5538 LLVMBuildStore(builder, LLVMConstNull(type), res);
5539
5540 LLVMDisposeBuilder(first_builder);
5541
5542 return res;
5543 }
5544
5545 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5546 LLVMTypeRef type,
5547 const char *name)
5548 {
5549 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5550 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5551 return ptr;
5552 }
5553
5554 static void
5555 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5556 struct nir_variable *variable,
5557 struct nir_shader *shader,
5558 gl_shader_stage stage)
5559 {
5560 int idx = variable->data.location + variable->data.index;
5561 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5562 uint64_t mask_attribs;
5563
5564 variable->data.driver_location = idx * 4;
5565
5566 /* tess ctrl has it's own load/store paths for outputs */
5567 if (stage == MESA_SHADER_TESS_CTRL)
5568 return;
5569
5570 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5571 if (stage == MESA_SHADER_VERTEX ||
5572 stage == MESA_SHADER_TESS_EVAL ||
5573 stage == MESA_SHADER_GEOMETRY) {
5574 if (idx == VARYING_SLOT_CLIP_DIST0) {
5575 int length = shader->info.clip_distance_array_size +
5576 shader->info.cull_distance_array_size;
5577 if (stage == MESA_SHADER_VERTEX) {
5578 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5579 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5580 }
5581 if (stage == MESA_SHADER_TESS_EVAL) {
5582 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5583 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5584 }
5585
5586 if (length > 4)
5587 attrib_count = 2;
5588 else
5589 attrib_count = 1;
5590 mask_attribs = 1ull << idx;
5591 }
5592 }
5593
5594 ctx->output_mask |= mask_attribs;
5595 }
5596
5597 static void
5598 handle_shader_output_decl(struct ac_nir_context *ctx,
5599 struct nir_shader *nir,
5600 struct nir_variable *variable)
5601 {
5602 unsigned output_loc = variable->data.driver_location / 4;
5603 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5604
5605 /* tess ctrl has it's own load/store paths for outputs */
5606 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5607 return;
5608
5609 if (ctx->stage == MESA_SHADER_VERTEX ||
5610 ctx->stage == MESA_SHADER_TESS_EVAL ||
5611 ctx->stage == MESA_SHADER_GEOMETRY) {
5612 int idx = variable->data.location + variable->data.index;
5613 if (idx == VARYING_SLOT_CLIP_DIST0) {
5614 int length = nir->info.clip_distance_array_size +
5615 nir->info.cull_distance_array_size;
5616
5617 if (length > 4)
5618 attrib_count = 2;
5619 else
5620 attrib_count = 1;
5621 }
5622 }
5623
5624 for (unsigned i = 0; i < attrib_count; ++i) {
5625 for (unsigned chan = 0; chan < 4; chan++) {
5626 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5627 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5628 }
5629 }
5630 }
5631
5632 static LLVMTypeRef
5633 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5634 enum glsl_base_type type)
5635 {
5636 switch (type) {
5637 case GLSL_TYPE_INT:
5638 case GLSL_TYPE_UINT:
5639 case GLSL_TYPE_BOOL:
5640 case GLSL_TYPE_SUBROUTINE:
5641 return ctx->ac.i32;
5642 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5643 return ctx->ac.f32;
5644 case GLSL_TYPE_INT64:
5645 case GLSL_TYPE_UINT64:
5646 return ctx->ac.i64;
5647 case GLSL_TYPE_DOUBLE:
5648 return ctx->ac.f64;
5649 default:
5650 unreachable("unknown GLSL type");
5651 }
5652 }
5653
5654 static LLVMTypeRef
5655 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5656 const struct glsl_type *type)
5657 {
5658 if (glsl_type_is_scalar(type)) {
5659 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5660 }
5661
5662 if (glsl_type_is_vector(type)) {
5663 return LLVMVectorType(
5664 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5665 glsl_get_vector_elements(type));
5666 }
5667
5668 if (glsl_type_is_matrix(type)) {
5669 return LLVMArrayType(
5670 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5671 glsl_get_matrix_columns(type));
5672 }
5673
5674 if (glsl_type_is_array(type)) {
5675 return LLVMArrayType(
5676 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5677 glsl_get_length(type));
5678 }
5679
5680 assert(glsl_type_is_struct(type));
5681
5682 LLVMTypeRef member_types[glsl_get_length(type)];
5683
5684 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5685 member_types[i] =
5686 glsl_to_llvm_type(ctx,
5687 glsl_get_struct_field(type, i));
5688 }
5689
5690 return LLVMStructTypeInContext(ctx->context, member_types,
5691 glsl_get_length(type), false);
5692 }
5693
5694 static void
5695 setup_locals(struct ac_nir_context *ctx,
5696 struct nir_function *func)
5697 {
5698 int i, j;
5699 ctx->num_locals = 0;
5700 nir_foreach_variable(variable, &func->impl->locals) {
5701 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5702 variable->data.driver_location = ctx->num_locals * 4;
5703 variable->data.location_frac = 0;
5704 ctx->num_locals += attrib_count;
5705 }
5706 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5707 if (!ctx->locals)
5708 return;
5709
5710 for (i = 0; i < ctx->num_locals; i++) {
5711 for (j = 0; j < 4; j++) {
5712 ctx->locals[i * 4 + j] =
5713 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5714 }
5715 }
5716 }
5717
5718 static void
5719 setup_shared(struct ac_nir_context *ctx,
5720 struct nir_shader *nir)
5721 {
5722 nir_foreach_variable(variable, &nir->shared) {
5723 LLVMValueRef shared =
5724 LLVMAddGlobalInAddressSpace(
5725 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5726 variable->name ? variable->name : "",
5727 AC_LOCAL_ADDR_SPACE);
5728 _mesa_hash_table_insert(ctx->vars, variable, shared);
5729 }
5730 }
5731
5732 static LLVMValueRef
5733 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5734 {
5735 v = ac_to_float(ctx, v);
5736 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5737 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5738 }
5739
5740
5741 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5742 LLVMValueRef src0, LLVMValueRef src1)
5743 {
5744 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5745 LLVMValueRef comp[2];
5746
5747 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5748 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5749 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5750 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5751 }
5752
5753 /* Initialize arguments for the shader export intrinsic */
5754 static void
5755 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5756 LLVMValueRef *values,
5757 unsigned target,
5758 struct ac_export_args *args)
5759 {
5760 /* Default is 0xf. Adjusted below depending on the format. */
5761 args->enabled_channels = 0xf;
5762
5763 /* Specify whether the EXEC mask represents the valid mask */
5764 args->valid_mask = 0;
5765
5766 /* Specify whether this is the last export */
5767 args->done = 0;
5768
5769 /* Specify the target we are exporting */
5770 args->target = target;
5771
5772 args->compr = false;
5773 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5774 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5775 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5776 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5777
5778 if (!values)
5779 return;
5780
5781 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5782 LLVMValueRef val[4];
5783 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5784 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5785 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5786 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5787
5788 switch(col_format) {
5789 case V_028714_SPI_SHADER_ZERO:
5790 args->enabled_channels = 0; /* writemask */
5791 args->target = V_008DFC_SQ_EXP_NULL;
5792 break;
5793
5794 case V_028714_SPI_SHADER_32_R:
5795 args->enabled_channels = 1;
5796 args->out[0] = values[0];
5797 break;
5798
5799 case V_028714_SPI_SHADER_32_GR:
5800 args->enabled_channels = 0x3;
5801 args->out[0] = values[0];
5802 args->out[1] = values[1];
5803 break;
5804
5805 case V_028714_SPI_SHADER_32_AR:
5806 args->enabled_channels = 0x9;
5807 args->out[0] = values[0];
5808 args->out[3] = values[3];
5809 break;
5810
5811 case V_028714_SPI_SHADER_FP16_ABGR:
5812 args->compr = 1;
5813
5814 for (unsigned chan = 0; chan < 2; chan++) {
5815 LLVMValueRef pack_args[2] = {
5816 values[2 * chan],
5817 values[2 * chan + 1]
5818 };
5819 LLVMValueRef packed;
5820
5821 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5822 args->out[chan] = packed;
5823 }
5824 break;
5825
5826 case V_028714_SPI_SHADER_UNORM16_ABGR:
5827 for (unsigned chan = 0; chan < 4; chan++) {
5828 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5829 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5830 LLVMConstReal(ctx->ac.f32, 65535), "");
5831 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5832 LLVMConstReal(ctx->ac.f32, 0.5), "");
5833 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5834 ctx->ac.i32, "");
5835 }
5836
5837 args->compr = 1;
5838 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5839 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5840 break;
5841
5842 case V_028714_SPI_SHADER_SNORM16_ABGR:
5843 for (unsigned chan = 0; chan < 4; chan++) {
5844 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5845 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5846 LLVMConstReal(ctx->ac.f32, 32767), "");
5847
5848 /* If positive, add 0.5, else add -0.5. */
5849 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5850 LLVMBuildSelect(ctx->builder,
5851 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5852 val[chan], ctx->ac.f32_0, ""),
5853 LLVMConstReal(ctx->ac.f32, 0.5),
5854 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5855 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5856 }
5857
5858 args->compr = 1;
5859 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5860 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5861 break;
5862
5863 case V_028714_SPI_SHADER_UINT16_ABGR: {
5864 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5865 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5866 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5867
5868 for (unsigned chan = 0; chan < 4; chan++) {
5869 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5870 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5871 }
5872
5873 args->compr = 1;
5874 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5875 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5876 break;
5877 }
5878
5879 case V_028714_SPI_SHADER_SINT16_ABGR: {
5880 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5881 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5882 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5883 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5884 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5885 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5886
5887 /* Clamp. */
5888 for (unsigned chan = 0; chan < 4; chan++) {
5889 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5890 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5891 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5892 }
5893
5894 args->compr = 1;
5895 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5896 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5897 break;
5898 }
5899
5900 default:
5901 case V_028714_SPI_SHADER_32_ABGR:
5902 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5903 break;
5904 }
5905 } else
5906 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5907
5908 for (unsigned i = 0; i < 4; ++i)
5909 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5910 }
5911
5912 static void
5913 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5914 bool export_prim_id,
5915 struct ac_vs_output_info *outinfo)
5916 {
5917 uint32_t param_count = 0;
5918 unsigned target;
5919 unsigned pos_idx, num_pos_exports = 0;
5920 struct ac_export_args args, pos_args[4] = {};
5921 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5922 int i;
5923
5924 if (ctx->options->key.has_multiview_view_index) {
5925 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5926 if(!*tmp_out) {
5927 for(unsigned i = 0; i < 4; ++i)
5928 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5929 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5930 }
5931
5932 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5933 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5934 }
5935
5936 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5937 sizeof(outinfo->vs_output_param_offset));
5938
5939 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5940 LLVMValueRef slots[8];
5941 unsigned j;
5942
5943 if (outinfo->cull_dist_mask)
5944 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5945
5946 i = VARYING_SLOT_CLIP_DIST0;
5947 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5948 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5949 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5950
5951 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5952 slots[i] = LLVMGetUndef(ctx->ac.f32);
5953
5954 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5955 target = V_008DFC_SQ_EXP_POS + 3;
5956 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5957 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5958 &args, sizeof(args));
5959 }
5960
5961 target = V_008DFC_SQ_EXP_POS + 2;
5962 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5963 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5964 &args, sizeof(args));
5965
5966 }
5967
5968 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5969 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5970 for (unsigned j = 0; j < 4; j++)
5971 pos_values[j] = LLVMBuildLoad(ctx->builder,
5972 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5973 }
5974 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5975
5976 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5977 outinfo->writes_pointsize = true;
5978 psize_value = LLVMBuildLoad(ctx->builder,
5979 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5980 }
5981
5982 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5983 outinfo->writes_layer = true;
5984 layer_value = LLVMBuildLoad(ctx->builder,
5985 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5986 }
5987
5988 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5989 outinfo->writes_viewport_index = true;
5990 viewport_index_value = LLVMBuildLoad(ctx->builder,
5991 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5992 }
5993
5994 if (outinfo->writes_pointsize ||
5995 outinfo->writes_layer ||
5996 outinfo->writes_viewport_index) {
5997 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5998 (outinfo->writes_layer == true ? 4 : 0));
5999 pos_args[1].valid_mask = 0;
6000 pos_args[1].done = 0;
6001 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6002 pos_args[1].compr = 0;
6003 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6004 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6005 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6006 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6007
6008 if (outinfo->writes_pointsize == true)
6009 pos_args[1].out[0] = psize_value;
6010 if (outinfo->writes_layer == true)
6011 pos_args[1].out[2] = layer_value;
6012 if (outinfo->writes_viewport_index == true) {
6013 if (ctx->options->chip_class >= GFX9) {
6014 /* GFX9 has the layer in out.z[10:0] and the viewport
6015 * index in out.z[19:16].
6016 */
6017 LLVMValueRef v = viewport_index_value;
6018 v = ac_to_integer(&ctx->ac, v);
6019 v = LLVMBuildShl(ctx->builder, v,
6020 LLVMConstInt(ctx->ac.i32, 16, false),
6021 "");
6022 v = LLVMBuildOr(ctx->builder, v,
6023 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6024
6025 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6026 pos_args[1].enabled_channels |= 1 << 2;
6027 } else {
6028 pos_args[1].out[3] = viewport_index_value;
6029 pos_args[1].enabled_channels |= 1 << 3;
6030 }
6031 }
6032 }
6033 for (i = 0; i < 4; i++) {
6034 if (pos_args[i].out[0])
6035 num_pos_exports++;
6036 }
6037
6038 pos_idx = 0;
6039 for (i = 0; i < 4; i++) {
6040 if (!pos_args[i].out[0])
6041 continue;
6042
6043 /* Specify the target we are exporting */
6044 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6045 if (pos_idx == num_pos_exports)
6046 pos_args[i].done = 1;
6047 ac_build_export(&ctx->ac, &pos_args[i]);
6048 }
6049
6050 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6051 LLVMValueRef values[4];
6052 if (!(ctx->output_mask & (1ull << i)))
6053 continue;
6054
6055 for (unsigned j = 0; j < 4; j++)
6056 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6057 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6058
6059 if (i == VARYING_SLOT_LAYER) {
6060 target = V_008DFC_SQ_EXP_PARAM + param_count;
6061 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
6062 param_count++;
6063 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
6064 target = V_008DFC_SQ_EXP_PARAM + param_count;
6065 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
6066 param_count++;
6067 } else if (i >= VARYING_SLOT_VAR0) {
6068 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
6069 target = V_008DFC_SQ_EXP_PARAM + param_count;
6070 outinfo->vs_output_param_offset[i] = param_count;
6071 param_count++;
6072 } else
6073 continue;
6074
6075 si_llvm_init_export_args(ctx, values, target, &args);
6076
6077 if (target >= V_008DFC_SQ_EXP_POS &&
6078 target <= (V_008DFC_SQ_EXP_POS + 3)) {
6079 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6080 &args, sizeof(args));
6081 } else {
6082 ac_build_export(&ctx->ac, &args);
6083 }
6084 }
6085
6086 if (export_prim_id) {
6087 LLVMValueRef values[4];
6088 target = V_008DFC_SQ_EXP_PARAM + param_count;
6089 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
6090 param_count++;
6091
6092 values[0] = ctx->vs_prim_id;
6093 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6094 ctx->shader_info->vs.vgpr_comp_cnt);
6095 for (unsigned j = 1; j < 4; j++)
6096 values[j] = ctx->ac.f32_0;
6097 si_llvm_init_export_args(ctx, values, target, &args);
6098 ac_build_export(&ctx->ac, &args);
6099 outinfo->export_prim_id = true;
6100 }
6101
6102 outinfo->pos_exports = num_pos_exports;
6103 outinfo->param_exports = param_count;
6104 }
6105
6106 static void
6107 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
6108 struct ac_es_output_info *outinfo)
6109 {
6110 int j;
6111 uint64_t max_output_written = 0;
6112 LLVMValueRef lds_base = NULL;
6113
6114 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6115 int param_index;
6116 int length = 4;
6117
6118 if (!(ctx->output_mask & (1ull << i)))
6119 continue;
6120
6121 if (i == VARYING_SLOT_CLIP_DIST0)
6122 length = ctx->num_output_clips + ctx->num_output_culls;
6123
6124 param_index = shader_io_get_unique_index(i);
6125
6126 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6127 }
6128
6129 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6130
6131 if (ctx->ac.chip_class >= GFX9) {
6132 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6133 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6134 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6135 LLVMConstInt(ctx->ac.i32, 24, false),
6136 LLVMConstInt(ctx->ac.i32, 4, false), false);
6137 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6138 LLVMBuildMul(ctx->ac.builder, wave_idx,
6139 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6140 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6141 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6142 }
6143
6144 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6145 LLVMValueRef dw_addr;
6146 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6147 int param_index;
6148 int length = 4;
6149
6150 if (!(ctx->output_mask & (1ull << i)))
6151 continue;
6152
6153 if (i == VARYING_SLOT_CLIP_DIST0)
6154 length = ctx->num_output_clips + ctx->num_output_culls;
6155
6156 param_index = shader_io_get_unique_index(i);
6157
6158 if (lds_base) {
6159 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6160 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6161 "");
6162 }
6163 for (j = 0; j < length; j++) {
6164 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6165 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6166
6167 if (ctx->ac.chip_class >= GFX9) {
6168 ac_lds_store(&ctx->ac, dw_addr,
6169 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6170 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6171 } else {
6172 ac_build_buffer_store_dword(&ctx->ac,
6173 ctx->esgs_ring,
6174 out_val, 1,
6175 NULL, ctx->es2gs_offset,
6176 (4 * param_index + j) * 4,
6177 1, 1, true, true);
6178 }
6179 }
6180 }
6181 }
6182
6183 static void
6184 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6185 {
6186 LLVMValueRef vertex_id = ctx->rel_auto_id;
6187 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6188 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6189 vertex_dw_stride, "");
6190
6191 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6192 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6193 int length = 4;
6194
6195 if (!(ctx->output_mask & (1ull << i)))
6196 continue;
6197
6198 if (i == VARYING_SLOT_CLIP_DIST0)
6199 length = ctx->num_output_clips + ctx->num_output_culls;
6200 int param = shader_io_get_unique_index(i);
6201 mark_tess_output(ctx, false, param);
6202 if (length > 4)
6203 mark_tess_output(ctx, false, param + 1);
6204 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6205 LLVMConstInt(ctx->ac.i32, param * 4, false),
6206 "");
6207 for (unsigned j = 0; j < length; j++) {
6208 ac_lds_store(&ctx->ac, dw_addr,
6209 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6210 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6211 }
6212 }
6213 }
6214
6215 struct ac_build_if_state
6216 {
6217 struct nir_to_llvm_context *ctx;
6218 LLVMValueRef condition;
6219 LLVMBasicBlockRef entry_block;
6220 LLVMBasicBlockRef true_block;
6221 LLVMBasicBlockRef false_block;
6222 LLVMBasicBlockRef merge_block;
6223 };
6224
6225 static LLVMBasicBlockRef
6226 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6227 {
6228 LLVMBasicBlockRef current_block;
6229 LLVMBasicBlockRef next_block;
6230 LLVMBasicBlockRef new_block;
6231
6232 /* get current basic block */
6233 current_block = LLVMGetInsertBlock(ctx->builder);
6234
6235 /* chqeck if there's another block after this one */
6236 next_block = LLVMGetNextBasicBlock(current_block);
6237 if (next_block) {
6238 /* insert the new block before the next block */
6239 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6240 }
6241 else {
6242 /* append new block after current block */
6243 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6244 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6245 }
6246 return new_block;
6247 }
6248
6249 static void
6250 ac_nir_build_if(struct ac_build_if_state *ifthen,
6251 struct nir_to_llvm_context *ctx,
6252 LLVMValueRef condition)
6253 {
6254 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6255
6256 memset(ifthen, 0, sizeof *ifthen);
6257 ifthen->ctx = ctx;
6258 ifthen->condition = condition;
6259 ifthen->entry_block = block;
6260
6261 /* create endif/merge basic block for the phi functions */
6262 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6263
6264 /* create/insert true_block before merge_block */
6265 ifthen->true_block =
6266 LLVMInsertBasicBlockInContext(ctx->context,
6267 ifthen->merge_block,
6268 "if-true-block");
6269
6270 /* successive code goes into the true block */
6271 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6272 }
6273
6274 /**
6275 * End a conditional.
6276 */
6277 static void
6278 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6279 {
6280 LLVMBuilderRef builder = ifthen->ctx->builder;
6281
6282 /* Insert branch to the merge block from current block */
6283 LLVMBuildBr(builder, ifthen->merge_block);
6284
6285 /*
6286 * Now patch in the various branch instructions.
6287 */
6288
6289 /* Insert the conditional branch instruction at the end of entry_block */
6290 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6291 if (ifthen->false_block) {
6292 /* we have an else clause */
6293 LLVMBuildCondBr(builder, ifthen->condition,
6294 ifthen->true_block, ifthen->false_block);
6295 }
6296 else {
6297 /* no else clause */
6298 LLVMBuildCondBr(builder, ifthen->condition,
6299 ifthen->true_block, ifthen->merge_block);
6300 }
6301
6302 /* Resume building code at end of the ifthen->merge_block */
6303 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6304 }
6305
6306 static void
6307 write_tess_factors(struct nir_to_llvm_context *ctx)
6308 {
6309 unsigned stride, outer_comps, inner_comps;
6310 struct ac_build_if_state if_ctx, inner_if_ctx;
6311 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6312 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6313 unsigned tess_inner_index, tess_outer_index;
6314 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6315 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6316 int i;
6317 emit_barrier(&ctx->ac, ctx->stage);
6318
6319 switch (ctx->options->key.tcs.primitive_mode) {
6320 case GL_ISOLINES:
6321 stride = 2;
6322 outer_comps = 2;
6323 inner_comps = 0;
6324 break;
6325 case GL_TRIANGLES:
6326 stride = 4;
6327 outer_comps = 3;
6328 inner_comps = 1;
6329 break;
6330 case GL_QUADS:
6331 stride = 6;
6332 outer_comps = 4;
6333 inner_comps = 2;
6334 break;
6335 default:
6336 return;
6337 }
6338
6339 ac_nir_build_if(&if_ctx, ctx,
6340 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6341 invocation_id, ctx->ac.i32_0, ""));
6342
6343 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6344 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6345
6346 mark_tess_output(ctx, true, tess_inner_index);
6347 mark_tess_output(ctx, true, tess_outer_index);
6348 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6349 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6350 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6351 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6352 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6353
6354 for (i = 0; i < 4; i++) {
6355 inner[i] = LLVMGetUndef(ctx->ac.i32);
6356 outer[i] = LLVMGetUndef(ctx->ac.i32);
6357 }
6358
6359 // LINES reverseal
6360 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6361 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6362 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6363 ctx->ac.i32_1, "");
6364 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6365 } else {
6366 for (i = 0; i < outer_comps; i++) {
6367 outer[i] = out[i] =
6368 ac_lds_load(&ctx->ac, lds_outer);
6369 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6370 ctx->ac.i32_1, "");
6371 }
6372 for (i = 0; i < inner_comps; i++) {
6373 inner[i] = out[outer_comps+i] =
6374 ac_lds_load(&ctx->ac, lds_inner);
6375 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6376 ctx->ac.i32_1, "");
6377 }
6378 }
6379
6380 /* Convert the outputs to vectors for stores. */
6381 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6382 vec1 = NULL;
6383
6384 if (stride > 4)
6385 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6386
6387
6388 buffer = ctx->hs_ring_tess_factor;
6389 tf_base = ctx->tess_factor_offset;
6390 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6391 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6392 unsigned tf_offset = 0;
6393
6394 if (ctx->options->chip_class <= VI) {
6395 ac_nir_build_if(&inner_if_ctx, ctx,
6396 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6397 rel_patch_id, ctx->ac.i32_0, ""));
6398
6399 /* Store the dynamic HS control word. */
6400 ac_build_buffer_store_dword(&ctx->ac, buffer,
6401 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6402 1, ctx->ac.i32_0, tf_base,
6403 0, 1, 0, true, false);
6404 tf_offset += 4;
6405
6406 ac_nir_build_endif(&inner_if_ctx);
6407 }
6408
6409 /* Store the tessellation factors. */
6410 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6411 MIN2(stride, 4), byteoffset, tf_base,
6412 tf_offset, 1, 0, true, false);
6413 if (vec1)
6414 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6415 stride - 4, byteoffset, tf_base,
6416 16 + tf_offset, 1, 0, true, false);
6417
6418 //store to offchip for TES to read - only if TES reads them
6419 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6420 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6421 LLVMValueRef tf_inner_offset;
6422 unsigned param_outer, param_inner;
6423
6424 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6425 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6426 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6427
6428 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6429 util_next_power_of_two(outer_comps));
6430
6431 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6432 outer_comps, tf_outer_offset,
6433 ctx->oc_lds, 0, 1, 0, true, false);
6434 if (inner_comps) {
6435 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6436 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6437 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6438
6439 inner_vec = inner_comps == 1 ? inner[0] :
6440 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6441 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6442 inner_comps, tf_inner_offset,
6443 ctx->oc_lds, 0, 1, 0, true, false);
6444 }
6445 }
6446 ac_nir_build_endif(&if_ctx);
6447 }
6448
6449 static void
6450 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6451 {
6452 write_tess_factors(ctx);
6453 }
6454
6455 static bool
6456 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6457 LLVMValueRef *color, unsigned param, bool is_last,
6458 struct ac_export_args *args)
6459 {
6460 /* Export */
6461 si_llvm_init_export_args(ctx, color, param,
6462 args);
6463
6464 if (is_last) {
6465 args->valid_mask = 1; /* whether the EXEC mask is valid */
6466 args->done = 1; /* DONE bit */
6467 } else if (!args->enabled_channels)
6468 return false; /* unnecessary NULL export */
6469
6470 return true;
6471 }
6472
6473 static void
6474 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6475 LLVMValueRef depth, LLVMValueRef stencil,
6476 LLVMValueRef samplemask)
6477 {
6478 struct ac_export_args args;
6479
6480 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6481
6482 ac_build_export(&ctx->ac, &args);
6483 }
6484
6485 static void
6486 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6487 {
6488 unsigned index = 0;
6489 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6490 struct ac_export_args color_args[8];
6491
6492 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6493 LLVMValueRef values[4];
6494
6495 if (!(ctx->output_mask & (1ull << i)))
6496 continue;
6497
6498 if (i == FRAG_RESULT_DEPTH) {
6499 ctx->shader_info->fs.writes_z = true;
6500 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6501 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6502 } else if (i == FRAG_RESULT_STENCIL) {
6503 ctx->shader_info->fs.writes_stencil = true;
6504 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6505 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6506 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6507 ctx->shader_info->fs.writes_sample_mask = true;
6508 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6509 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6510 } else {
6511 bool last = false;
6512 for (unsigned j = 0; j < 4; j++)
6513 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6514 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6515
6516 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6517 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6518
6519 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6520 if (ret)
6521 index++;
6522 }
6523 }
6524
6525 for (unsigned i = 0; i < index; i++)
6526 ac_build_export(&ctx->ac, &color_args[i]);
6527 if (depth || stencil || samplemask)
6528 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6529 else if (!index) {
6530 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6531 ac_build_export(&ctx->ac, &color_args[0]);
6532 }
6533 }
6534
6535 static void
6536 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6537 {
6538 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6539 }
6540
6541 static void
6542 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6543 LLVMValueRef *addrs)
6544 {
6545 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6546
6547 switch (ctx->stage) {
6548 case MESA_SHADER_VERTEX:
6549 if (ctx->options->key.vs.as_ls)
6550 handle_ls_outputs_post(ctx);
6551 else if (ctx->options->key.vs.as_es)
6552 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6553 else
6554 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6555 &ctx->shader_info->vs.outinfo);
6556 break;
6557 case MESA_SHADER_FRAGMENT:
6558 handle_fs_outputs_post(ctx);
6559 break;
6560 case MESA_SHADER_GEOMETRY:
6561 emit_gs_epilogue(ctx);
6562 break;
6563 case MESA_SHADER_TESS_CTRL:
6564 handle_tcs_outputs_post(ctx);
6565 break;
6566 case MESA_SHADER_TESS_EVAL:
6567 if (ctx->options->key.tes.as_es)
6568 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6569 else
6570 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6571 &ctx->shader_info->tes.outinfo);
6572 break;
6573 default:
6574 break;
6575 }
6576 }
6577
6578 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6579 {
6580 LLVMPassManagerRef passmgr;
6581 /* Create the pass manager */
6582 passmgr = LLVMCreateFunctionPassManagerForModule(
6583 ctx->module);
6584
6585 /* This pass should eliminate all the load and store instructions */
6586 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6587
6588 /* Add some optimization passes */
6589 LLVMAddScalarReplAggregatesPass(passmgr);
6590 LLVMAddLICMPass(passmgr);
6591 LLVMAddAggressiveDCEPass(passmgr);
6592 LLVMAddCFGSimplificationPass(passmgr);
6593 LLVMAddInstructionCombiningPass(passmgr);
6594
6595 /* Run the pass */
6596 LLVMInitializeFunctionPassManager(passmgr);
6597 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6598 LLVMFinalizeFunctionPassManager(passmgr);
6599
6600 LLVMDisposeBuilder(ctx->builder);
6601 LLVMDisposePassManager(passmgr);
6602 }
6603
6604 static void
6605 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6606 {
6607 struct ac_vs_output_info *outinfo;
6608
6609 switch (ctx->stage) {
6610 case MESA_SHADER_FRAGMENT:
6611 case MESA_SHADER_COMPUTE:
6612 case MESA_SHADER_TESS_CTRL:
6613 case MESA_SHADER_GEOMETRY:
6614 return;
6615 case MESA_SHADER_VERTEX:
6616 if (ctx->options->key.vs.as_ls ||
6617 ctx->options->key.vs.as_es)
6618 return;
6619 outinfo = &ctx->shader_info->vs.outinfo;
6620 break;
6621 case MESA_SHADER_TESS_EVAL:
6622 if (ctx->options->key.vs.as_es)
6623 return;
6624 outinfo = &ctx->shader_info->tes.outinfo;
6625 break;
6626 default:
6627 unreachable("Unhandled shader type");
6628 }
6629
6630 ac_optimize_vs_outputs(&ctx->ac,
6631 ctx->main_function,
6632 outinfo->vs_output_param_offset,
6633 VARYING_SLOT_MAX,
6634 &outinfo->param_exports);
6635 }
6636
6637 static void
6638 ac_setup_rings(struct nir_to_llvm_context *ctx)
6639 {
6640 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6641 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6642 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6643 }
6644
6645 if (ctx->is_gs_copy_shader) {
6646 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6647 }
6648 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6649 LLVMValueRef tmp;
6650 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6651 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6652
6653 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6654
6655 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6656 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6657 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6658 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6659 }
6660
6661 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6662 ctx->stage == MESA_SHADER_TESS_EVAL) {
6663 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6664 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6665 }
6666 }
6667
6668 static unsigned
6669 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6670 const struct nir_shader *nir)
6671 {
6672 switch (nir->info.stage) {
6673 case MESA_SHADER_TESS_CTRL:
6674 return chip_class >= CIK ? 128 : 64;
6675 case MESA_SHADER_GEOMETRY:
6676 return chip_class >= GFX9 ? 128 : 64;
6677 case MESA_SHADER_COMPUTE:
6678 break;
6679 default:
6680 return 0;
6681 }
6682
6683 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6684 nir->info.cs.local_size[1] *
6685 nir->info.cs.local_size[2];
6686 return max_workgroup_size;
6687 }
6688
6689 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6690 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6691 {
6692 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6693 LLVMConstInt(ctx->ac.i32, 8, false),
6694 LLVMConstInt(ctx->ac.i32, 8, false), false);
6695 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6696 ctx->ac.i32_0, "");
6697 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6698 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6699 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6700 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6701 }
6702
6703 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6704 {
6705 for(int i = 5; i >= 0; --i) {
6706 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6707 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6708 LLVMConstInt(ctx->ac.i32, 16, false), false);
6709 }
6710
6711 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6712 LLVMConstInt(ctx->ac.i32, 16, false),
6713 LLVMConstInt(ctx->ac.i32, 8, false), false);
6714 }
6715
6716 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6717 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6718 {
6719 struct ac_nir_context ctx = {};
6720 struct nir_function *func;
6721
6722 ctx.ac = *ac;
6723 ctx.abi = abi;
6724
6725 ctx.nctx = nctx;
6726 if (nctx)
6727 nctx->nir = &ctx;
6728
6729 ctx.stage = nir->info.stage;
6730
6731 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6732
6733 nir_foreach_variable(variable, &nir->outputs)
6734 handle_shader_output_decl(&ctx, nir, variable);
6735
6736 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6737 _mesa_key_pointer_equal);
6738 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6739 _mesa_key_pointer_equal);
6740 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6741 _mesa_key_pointer_equal);
6742
6743 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6744
6745 setup_locals(&ctx, func);
6746
6747 if (nir->info.stage == MESA_SHADER_COMPUTE)
6748 setup_shared(&ctx, nir);
6749
6750 visit_cf_list(&ctx, &func->impl->body);
6751 phi_post_pass(&ctx);
6752
6753 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6754 ctx.outputs);
6755
6756 free(ctx.locals);
6757 ralloc_free(ctx.defs);
6758 ralloc_free(ctx.phis);
6759 ralloc_free(ctx.vars);
6760
6761 if (nctx)
6762 nctx->nir = NULL;
6763 }
6764
6765 static
6766 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6767 struct nir_shader *const *shaders,
6768 int shader_count,
6769 struct ac_shader_variant_info *shader_info,
6770 const struct ac_nir_compiler_options *options)
6771 {
6772 struct nir_to_llvm_context ctx = {0};
6773 unsigned i;
6774 ctx.options = options;
6775 ctx.shader_info = shader_info;
6776 ctx.context = LLVMContextCreate();
6777 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6778
6779 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6780 options->family);
6781 ctx.ac.module = ctx.module;
6782 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6783
6784 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6785 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6786 LLVMSetDataLayout(ctx.module, data_layout_str);
6787 LLVMDisposeTargetData(data_layout);
6788 LLVMDisposeMessage(data_layout_str);
6789
6790 enum ac_float_mode float_mode =
6791 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6792 AC_FLOAT_MODE_DEFAULT;
6793
6794 ctx.builder = ac_create_builder(ctx.context, float_mode);
6795 ctx.ac.builder = ctx.builder;
6796
6797 memset(shader_info, 0, sizeof(*shader_info));
6798
6799 for(int i = 0; i < shader_count; ++i)
6800 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6801
6802 for (i = 0; i < AC_UD_MAX_SETS; i++)
6803 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6804 for (i = 0; i < AC_UD_MAX_UD; i++)
6805 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6806
6807 ctx.max_workgroup_size = 0;
6808 for (int i = 0; i < shader_count; ++i) {
6809 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6810 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6811 shaders[i]));
6812 }
6813
6814 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6815 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6816
6817 ctx.abi.inputs = &ctx.inputs[0];
6818 ctx.abi.emit_outputs = handle_shader_outputs_post;
6819 ctx.abi.emit_vertex = visit_emit_vertex;
6820 ctx.abi.load_ubo = radv_load_ubo;
6821 ctx.abi.load_ssbo = radv_load_ssbo;
6822 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6823 ctx.abi.clamp_shadow_reference = false;
6824
6825 if (shader_count >= 2)
6826 ac_init_exec_full_mask(&ctx.ac);
6827
6828 if (ctx.ac.chip_class == GFX9 &&
6829 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6830 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6831
6832 for(int i = 0; i < shader_count; ++i) {
6833 ctx.stage = shaders[i]->info.stage;
6834 ctx.output_mask = 0;
6835 ctx.tess_outputs_written = 0;
6836 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6837 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6838
6839 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6840 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6841 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6842 ctx.abi.load_inputs = load_gs_input;
6843 ctx.abi.emit_primitive = visit_end_primitive;
6844 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6845 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6846 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6847 ctx.abi.load_tess_varyings = load_tcs_varyings;
6848 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6849 ctx.abi.store_tcs_outputs = store_tcs_output;
6850 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6851 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6852 ctx.abi.load_tess_varyings = load_tes_input;
6853 ctx.abi.load_tess_coord = load_tess_coord;
6854 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6855 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6856 if (shader_info->info.vs.needs_instance_id) {
6857 if (ctx.options->key.vs.as_ls) {
6858 ctx.shader_info->vs.vgpr_comp_cnt =
6859 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6860 } else {
6861 ctx.shader_info->vs.vgpr_comp_cnt =
6862 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6863 }
6864 }
6865 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6866 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6867 ctx.abi.lookup_interp_param = lookup_interp_param;
6868 ctx.abi.load_sample_position = load_sample_position;
6869 }
6870
6871 if (i)
6872 emit_barrier(&ctx.ac, ctx.stage);
6873
6874 ac_setup_rings(&ctx);
6875
6876 LLVMBasicBlockRef merge_block;
6877 if (shader_count >= 2) {
6878 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6879 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6880 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6881
6882 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6883 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6884 LLVMConstInt(ctx.ac.i32, 8, false), false);
6885 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6886 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6887 thread_id, count, "");
6888 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6889
6890 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6891 }
6892
6893 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6894 handle_fs_inputs(&ctx, shaders[i]);
6895 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6896 handle_vs_inputs(&ctx, shaders[i]);
6897 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6898 prepare_gs_input_vgprs(&ctx);
6899
6900 nir_foreach_variable(variable, &shaders[i]->outputs)
6901 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6902
6903 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6904
6905 if (shader_count >= 2) {
6906 LLVMBuildBr(ctx.ac.builder, merge_block);
6907 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6908 }
6909
6910 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6911 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6912 shaders[i]->info.cull_distance_array_size > 4;
6913 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6914 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6915 shaders[i]->info.gs.vertices_out;
6916 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6917 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6918 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6919 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6920 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6921 }
6922 }
6923
6924 LLVMBuildRetVoid(ctx.builder);
6925
6926 if (options->dump_preoptir)
6927 ac_dump_module(ctx.module);
6928
6929 ac_llvm_finalize_module(&ctx);
6930
6931 if (shader_count == 1)
6932 ac_nir_eliminate_const_vs_outputs(&ctx);
6933
6934 return ctx.module;
6935 }
6936
6937 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6938 {
6939 unsigned *retval = (unsigned *)context;
6940 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6941 char *description = LLVMGetDiagInfoDescription(di);
6942
6943 if (severity == LLVMDSError) {
6944 *retval = 1;
6945 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6946 description);
6947 }
6948
6949 LLVMDisposeMessage(description);
6950 }
6951
6952 static unsigned ac_llvm_compile(LLVMModuleRef M,
6953 struct ac_shader_binary *binary,
6954 LLVMTargetMachineRef tm)
6955 {
6956 unsigned retval = 0;
6957 char *err;
6958 LLVMContextRef llvm_ctx;
6959 LLVMMemoryBufferRef out_buffer;
6960 unsigned buffer_size;
6961 const char *buffer_data;
6962 LLVMBool mem_err;
6963
6964 /* Setup Diagnostic Handler*/
6965 llvm_ctx = LLVMGetModuleContext(M);
6966
6967 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6968 &retval);
6969
6970 /* Compile IR*/
6971 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6972 &err, &out_buffer);
6973
6974 /* Process Errors/Warnings */
6975 if (mem_err) {
6976 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6977 free(err);
6978 retval = 1;
6979 goto out;
6980 }
6981
6982 /* Extract Shader Code*/
6983 buffer_size = LLVMGetBufferSize(out_buffer);
6984 buffer_data = LLVMGetBufferStart(out_buffer);
6985
6986 ac_elf_read(buffer_data, buffer_size, binary);
6987
6988 /* Clean up */
6989 LLVMDisposeMemoryBuffer(out_buffer);
6990
6991 out:
6992 return retval;
6993 }
6994
6995 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6996 LLVMModuleRef llvm_module,
6997 struct ac_shader_binary *binary,
6998 struct ac_shader_config *config,
6999 struct ac_shader_variant_info *shader_info,
7000 gl_shader_stage stage,
7001 bool dump_shader, bool supports_spill)
7002 {
7003 if (dump_shader)
7004 ac_dump_module(llvm_module);
7005
7006 memset(binary, 0, sizeof(*binary));
7007 int v = ac_llvm_compile(llvm_module, binary, tm);
7008 if (v) {
7009 fprintf(stderr, "compile failed\n");
7010 }
7011
7012 if (dump_shader)
7013 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7014
7015 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7016
7017 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7018 LLVMDisposeModule(llvm_module);
7019 LLVMContextDispose(ctx);
7020
7021 if (stage == MESA_SHADER_FRAGMENT) {
7022 shader_info->num_input_vgprs = 0;
7023 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7024 shader_info->num_input_vgprs += 2;
7025 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7026 shader_info->num_input_vgprs += 2;
7027 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7028 shader_info->num_input_vgprs += 2;
7029 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7030 shader_info->num_input_vgprs += 3;
7031 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7032 shader_info->num_input_vgprs += 2;
7033 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7034 shader_info->num_input_vgprs += 2;
7035 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7036 shader_info->num_input_vgprs += 2;
7037 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7038 shader_info->num_input_vgprs += 1;
7039 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7040 shader_info->num_input_vgprs += 1;
7041 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7042 shader_info->num_input_vgprs += 1;
7043 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7044 shader_info->num_input_vgprs += 1;
7045 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7046 shader_info->num_input_vgprs += 1;
7047 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7048 shader_info->num_input_vgprs += 1;
7049 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7050 shader_info->num_input_vgprs += 1;
7051 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7052 shader_info->num_input_vgprs += 1;
7053 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7054 shader_info->num_input_vgprs += 1;
7055 }
7056 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7057
7058 /* +3 for scratch wave offset and VCC */
7059 config->num_sgprs = MAX2(config->num_sgprs,
7060 shader_info->num_input_sgprs + 3);
7061
7062 /* Enable 64-bit and 16-bit denormals, because there is no performance
7063 * cost.
7064 *
7065 * If denormals are enabled, all floating-point output modifiers are
7066 * ignored.
7067 *
7068 * Don't enable denormals for 32-bit floats, because:
7069 * - Floating-point output modifiers would be ignored by the hw.
7070 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7071 * have to stop using those.
7072 * - SI & CI would be very slow.
7073 */
7074 config->float_mode |= V_00B028_FP_64_DENORMS;
7075 }
7076
7077 static void
7078 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7079 {
7080 switch (nir->info.stage) {
7081 case MESA_SHADER_COMPUTE:
7082 for (int i = 0; i < 3; ++i)
7083 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7084 break;
7085 case MESA_SHADER_FRAGMENT:
7086 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7087 break;
7088 case MESA_SHADER_GEOMETRY:
7089 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7090 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7091 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7092 shader_info->gs.invocations = nir->info.gs.invocations;
7093 break;
7094 case MESA_SHADER_TESS_EVAL:
7095 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7096 shader_info->tes.spacing = nir->info.tess.spacing;
7097 shader_info->tes.ccw = nir->info.tess.ccw;
7098 shader_info->tes.point_mode = nir->info.tess.point_mode;
7099 shader_info->tes.as_es = options->key.tes.as_es;
7100 break;
7101 case MESA_SHADER_TESS_CTRL:
7102 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7103 break;
7104 case MESA_SHADER_VERTEX:
7105 shader_info->vs.as_es = options->key.vs.as_es;
7106 shader_info->vs.as_ls = options->key.vs.as_ls;
7107 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7108 if (options->key.vs.as_ls)
7109 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7110 break;
7111 default:
7112 break;
7113 }
7114 }
7115
7116 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7117 struct ac_shader_binary *binary,
7118 struct ac_shader_config *config,
7119 struct ac_shader_variant_info *shader_info,
7120 struct nir_shader *const *nir,
7121 int nir_count,
7122 const struct ac_nir_compiler_options *options,
7123 bool dump_shader)
7124 {
7125
7126 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7127 options);
7128
7129 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7130 for (int i = 0; i < nir_count; ++i)
7131 ac_fill_shader_info(shader_info, nir[i], options);
7132
7133 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7134 if (options->chip_class == GFX9) {
7135 if (nir_count == 2 &&
7136 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7137 shader_info->gs.es_type = nir[0]->info.stage;
7138 }
7139 }
7140 }
7141
7142 static void
7143 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
7144 {
7145 LLVMValueRef vtx_offset =
7146 LLVMBuildMul(ctx->builder, ctx->abi.vertex_id,
7147 LLVMConstInt(ctx->ac.i32, 4, false), "");
7148 int idx = 0;
7149
7150 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7151 int length = 4;
7152 int slot = idx;
7153 int slot_inc = 1;
7154 if (!(ctx->output_mask & (1ull << i)))
7155 continue;
7156
7157 if (i == VARYING_SLOT_CLIP_DIST0) {
7158 /* unpack clip and cull from a single set of slots */
7159 length = ctx->num_output_clips + ctx->num_output_culls;
7160 if (length > 4)
7161 slot_inc = 2;
7162 }
7163
7164 for (unsigned j = 0; j < length; j++) {
7165 LLVMValueRef value, soffset;
7166
7167 soffset = LLVMConstInt(ctx->ac.i32,
7168 (slot * 4 + j) *
7169 ctx->gs_max_out_vertices * 16 * 4, false);
7170
7171 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7172 1, ctx->ac.i32_0,
7173 vtx_offset, soffset,
7174 0, 1, 1, true, false);
7175
7176 LLVMBuildStore(ctx->builder,
7177 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7178 }
7179 idx += slot_inc;
7180 }
7181 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7182 }
7183
7184 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7185 struct nir_shader *geom_shader,
7186 struct ac_shader_binary *binary,
7187 struct ac_shader_config *config,
7188 struct ac_shader_variant_info *shader_info,
7189 const struct ac_nir_compiler_options *options,
7190 bool dump_shader)
7191 {
7192 struct nir_to_llvm_context ctx = {0};
7193 ctx.context = LLVMContextCreate();
7194 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7195 ctx.options = options;
7196 ctx.shader_info = shader_info;
7197
7198 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7199 options->family);
7200 ctx.ac.module = ctx.module;
7201
7202 ctx.is_gs_copy_shader = true;
7203 LLVMSetTarget(ctx.module, "amdgcn--");
7204
7205 enum ac_float_mode float_mode =
7206 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7207 AC_FLOAT_MODE_DEFAULT;
7208
7209 ctx.builder = ac_create_builder(ctx.context, float_mode);
7210 ctx.ac.builder = ctx.builder;
7211 ctx.stage = MESA_SHADER_VERTEX;
7212
7213 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7214
7215 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7216 ac_setup_rings(&ctx);
7217
7218 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7219 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7220
7221 struct ac_nir_context nir_ctx = {};
7222 nir_ctx.ac = ctx.ac;
7223 nir_ctx.abi = &ctx.abi;
7224
7225 nir_ctx.nctx = &ctx;
7226 ctx.nir = &nir_ctx;
7227
7228 nir_foreach_variable(variable, &geom_shader->outputs) {
7229 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7230 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7231 }
7232
7233 ac_gs_copy_shader_emit(&ctx);
7234
7235 ctx.nir = NULL;
7236
7237 LLVMBuildRetVoid(ctx.builder);
7238
7239 ac_llvm_finalize_module(&ctx);
7240
7241 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7242 MESA_SHADER_VERTEX,
7243 dump_shader, options->supports_spill);
7244 }