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[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_info.h"
34 #include "ac_exp_param.h"
35
36 enum radeon_llvm_calling_convention {
37 RADEON_LLVM_AMDGPU_VS = 87,
38 RADEON_LLVM_AMDGPU_GS = 88,
39 RADEON_LLVM_AMDGPU_PS = 89,
40 RADEON_LLVM_AMDGPU_CS = 90,
41 };
42
43 #define CONST_ADDR_SPACE 2
44 #define LOCAL_ADDR_SPACE 3
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
48
49 enum desc_type {
50 DESC_IMAGE,
51 DESC_FMASK,
52 DESC_SAMPLER,
53 DESC_BUFFER,
54 };
55
56 struct nir_to_llvm_context {
57 struct ac_llvm_context ac;
58 const struct ac_nir_compiler_options *options;
59 struct ac_shader_variant_info *shader_info;
60 unsigned max_workgroup_size;
61 LLVMContextRef context;
62 LLVMModuleRef module;
63 LLVMBuilderRef builder;
64 LLVMValueRef main_function;
65
66 struct hash_table *defs;
67 struct hash_table *phis;
68
69 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
70 LLVMValueRef ring_offsets;
71 LLVMValueRef push_constants;
72 LLVMValueRef num_work_groups;
73 LLVMValueRef workgroup_ids;
74 LLVMValueRef local_invocation_ids;
75 LLVMValueRef tg_size;
76
77 LLVMValueRef vertex_buffers;
78 LLVMValueRef base_vertex;
79 LLVMValueRef start_instance;
80 LLVMValueRef draw_index;
81 LLVMValueRef vertex_id;
82 LLVMValueRef rel_auto_id;
83 LLVMValueRef vs_prim_id;
84 LLVMValueRef instance_id;
85 LLVMValueRef ls_out_layout;
86 LLVMValueRef es2gs_offset;
87
88 LLVMValueRef tcs_offchip_layout;
89 LLVMValueRef tcs_out_offsets;
90 LLVMValueRef tcs_out_layout;
91 LLVMValueRef tcs_in_layout;
92 LLVMValueRef oc_lds;
93 LLVMValueRef tess_factor_offset;
94 LLVMValueRef tcs_patch_id;
95 LLVMValueRef tcs_rel_ids;
96 LLVMValueRef tes_rel_patch_id;
97 LLVMValueRef tes_patch_id;
98 LLVMValueRef tes_u;
99 LLVMValueRef tes_v;
100
101 LLVMValueRef gsvs_ring_stride;
102 LLVMValueRef gsvs_num_entries;
103 LLVMValueRef gs2vs_offset;
104 LLVMValueRef gs_wave_id;
105 LLVMValueRef gs_vtx_offset[6];
106 LLVMValueRef gs_prim_id, gs_invocation_id;
107
108 LLVMValueRef esgs_ring;
109 LLVMValueRef gsvs_ring;
110 LLVMValueRef hs_ring_tess_offchip;
111 LLVMValueRef hs_ring_tess_factor;
112
113 LLVMValueRef prim_mask;
114 LLVMValueRef sample_pos_offset;
115 LLVMValueRef persp_sample, persp_center, persp_centroid;
116 LLVMValueRef linear_sample, linear_center, linear_centroid;
117 LLVMValueRef front_face;
118 LLVMValueRef ancillary;
119 LLVMValueRef sample_coverage;
120 LLVMValueRef frag_pos[4];
121
122 LLVMBasicBlockRef continue_block;
123 LLVMBasicBlockRef break_block;
124
125 LLVMTypeRef i1;
126 LLVMTypeRef i8;
127 LLVMTypeRef i16;
128 LLVMTypeRef i32;
129 LLVMTypeRef i64;
130 LLVMTypeRef v2i32;
131 LLVMTypeRef v3i32;
132 LLVMTypeRef v4i32;
133 LLVMTypeRef v8i32;
134 LLVMTypeRef f64;
135 LLVMTypeRef f32;
136 LLVMTypeRef f16;
137 LLVMTypeRef v2f32;
138 LLVMTypeRef v4f32;
139 LLVMTypeRef v16i8;
140 LLVMTypeRef voidt;
141
142 LLVMValueRef i1true;
143 LLVMValueRef i1false;
144 LLVMValueRef i32zero;
145 LLVMValueRef i32one;
146 LLVMValueRef f32zero;
147 LLVMValueRef f32one;
148 LLVMValueRef v4f32empty;
149
150 unsigned uniform_md_kind;
151 LLVMValueRef empty_md;
152 gl_shader_stage stage;
153
154 LLVMValueRef lds;
155 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
156 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
157
158 LLVMValueRef shared_memory;
159 uint64_t input_mask;
160 uint64_t output_mask;
161 int num_locals;
162 LLVMValueRef *locals;
163 bool has_ddxy;
164 uint8_t num_output_clips;
165 uint8_t num_output_culls;
166
167 bool has_ds_bpermute;
168
169 bool is_gs_copy_shader;
170 LLVMValueRef gs_next_vertex;
171 unsigned gs_max_out_vertices;
172
173 unsigned tes_primitive_mode;
174 uint64_t tess_outputs_written;
175 uint64_t tess_patch_outputs_written;
176 };
177
178 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
179 nir_deref_var *deref,
180 enum desc_type desc_type);
181 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
182 {
183 return (index * 4) + chan;
184 }
185
186 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
187 {
188 /* handle patch indices separate */
189 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
190 return 0;
191 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
192 return 1;
193 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
194 return 2 + (slot - VARYING_SLOT_PATCH0);
195
196 if (slot == VARYING_SLOT_POS)
197 return 0;
198 if (slot == VARYING_SLOT_PSIZ)
199 return 1;
200 if (slot == VARYING_SLOT_CLIP_DIST0)
201 return 2;
202 /* 3 is reserved for clip dist as well */
203 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
204 return 4 + (slot - VARYING_SLOT_VAR0);
205 unreachable("illegal slot in get unique index\n");
206 }
207
208 static unsigned llvm_get_type_size(LLVMTypeRef type)
209 {
210 LLVMTypeKind kind = LLVMGetTypeKind(type);
211
212 switch (kind) {
213 case LLVMIntegerTypeKind:
214 return LLVMGetIntTypeWidth(type) / 8;
215 case LLVMFloatTypeKind:
216 return 4;
217 case LLVMPointerTypeKind:
218 return 8;
219 case LLVMVectorTypeKind:
220 return LLVMGetVectorSize(type) *
221 llvm_get_type_size(LLVMGetElementType(type));
222 default:
223 assert(0);
224 return 0;
225 }
226 }
227
228 static void set_llvm_calling_convention(LLVMValueRef func,
229 gl_shader_stage stage)
230 {
231 enum radeon_llvm_calling_convention calling_conv;
232
233 switch (stage) {
234 case MESA_SHADER_VERTEX:
235 case MESA_SHADER_TESS_CTRL:
236 case MESA_SHADER_TESS_EVAL:
237 calling_conv = RADEON_LLVM_AMDGPU_VS;
238 break;
239 case MESA_SHADER_GEOMETRY:
240 calling_conv = RADEON_LLVM_AMDGPU_GS;
241 break;
242 case MESA_SHADER_FRAGMENT:
243 calling_conv = RADEON_LLVM_AMDGPU_PS;
244 break;
245 case MESA_SHADER_COMPUTE:
246 calling_conv = RADEON_LLVM_AMDGPU_CS;
247 break;
248 default:
249 unreachable("Unhandle shader type");
250 }
251
252 LLVMSetFunctionCallConv(func, calling_conv);
253 }
254
255 static LLVMValueRef
256 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
257 LLVMBuilderRef builder, LLVMTypeRef *return_types,
258 unsigned num_return_elems, LLVMTypeRef *param_types,
259 unsigned param_count, unsigned array_params_mask,
260 unsigned sgpr_params, unsigned max_workgroup_size,
261 bool unsafe_math)
262 {
263 LLVMTypeRef main_function_type, ret_type;
264 LLVMBasicBlockRef main_function_body;
265
266 if (num_return_elems)
267 ret_type = LLVMStructTypeInContext(ctx, return_types,
268 num_return_elems, true);
269 else
270 ret_type = LLVMVoidTypeInContext(ctx);
271
272 /* Setup the function */
273 main_function_type =
274 LLVMFunctionType(ret_type, param_types, param_count, 0);
275 LLVMValueRef main_function =
276 LLVMAddFunction(module, "main", main_function_type);
277 main_function_body =
278 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
279 LLVMPositionBuilderAtEnd(builder, main_function_body);
280
281 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
282 for (unsigned i = 0; i < sgpr_params; ++i) {
283 if (array_params_mask & (1 << i)) {
284 LLVMValueRef P = LLVMGetParam(main_function, i);
285 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
286 ac_add_attr_dereferenceable(P, UINT64_MAX);
287 }
288 else {
289 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
290 }
291 }
292
293 if (max_workgroup_size) {
294 ac_llvm_add_target_dep_function_attr(main_function,
295 "amdgpu-max-work-group-size",
296 max_workgroup_size);
297 }
298 if (unsafe_math) {
299 /* These were copied from some LLVM test. */
300 LLVMAddTargetDependentFunctionAttr(main_function,
301 "less-precise-fpmad",
302 "true");
303 LLVMAddTargetDependentFunctionAttr(main_function,
304 "no-infs-fp-math",
305 "true");
306 LLVMAddTargetDependentFunctionAttr(main_function,
307 "no-nans-fp-math",
308 "true");
309 LLVMAddTargetDependentFunctionAttr(main_function,
310 "unsafe-fp-math",
311 "true");
312 }
313 return main_function;
314 }
315
316 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
317 {
318 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
319 CONST_ADDR_SPACE);
320 }
321
322 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
323 int idx,
324 LLVMTypeRef type)
325 {
326 LLVMValueRef offset;
327 LLVMValueRef ptr;
328 int addr_space;
329
330 offset = LLVMConstInt(ctx->i32, idx * 16, false);
331
332 ptr = ctx->shared_memory;
333 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
334 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
335 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
336 return ptr;
337 }
338
339 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
340 {
341 if (t == ctx->f16 || t == ctx->i16)
342 return ctx->i16;
343 else if (t == ctx->f32 || t == ctx->i32)
344 return ctx->i32;
345 else if (t == ctx->f64 || t == ctx->i64)
346 return ctx->i64;
347 else
348 unreachable("Unhandled integer size");
349 }
350
351 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
352 {
353 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
354 LLVMTypeRef elem_type = LLVMGetElementType(t);
355 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
356 LLVMGetVectorSize(t));
357 }
358 return to_integer_type_scalar(ctx, t);
359 }
360
361 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
362 {
363 LLVMTypeRef type = LLVMTypeOf(v);
364 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
365 }
366
367 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
368 {
369 if (t == ctx->i16 || t == ctx->f16)
370 return ctx->f16;
371 else if (t == ctx->i32 || t == ctx->f32)
372 return ctx->f32;
373 else if (t == ctx->i64 || t == ctx->f64)
374 return ctx->f64;
375 else
376 unreachable("Unhandled float size");
377 }
378
379 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
380 {
381 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
382 LLVMTypeRef elem_type = LLVMGetElementType(t);
383 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
384 LLVMGetVectorSize(t));
385 }
386 return to_float_type_scalar(ctx, t);
387 }
388
389 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
390 {
391 LLVMTypeRef type = LLVMTypeOf(v);
392 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
393 }
394
395 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
396 {
397 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
398 type = LLVMGetElementType(type);
399
400 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
401 return LLVMGetIntTypeWidth(type);
402
403 if (type == ctx->f16)
404 return 16;
405 if (type == ctx->f32)
406 return 32;
407 if (type == ctx->f64)
408 return 64;
409
410 unreachable("Unhandled type kind in get_elem_bits");
411 }
412
413 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
414 LLVMValueRef param, unsigned rshift,
415 unsigned bitwidth)
416 {
417 LLVMValueRef value = param;
418 if (rshift)
419 value = LLVMBuildLShr(ctx->builder, value,
420 LLVMConstInt(ctx->i32, rshift, false), "");
421
422 if (rshift + bitwidth < 32) {
423 unsigned mask = (1 << bitwidth) - 1;
424 value = LLVMBuildAnd(ctx->builder, value,
425 LLVMConstInt(ctx->i32, mask, false), "");
426 }
427 return value;
428 }
429
430 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
431 {
432 switch (ctx->stage) {
433 case MESA_SHADER_TESS_CTRL:
434 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
435 case MESA_SHADER_TESS_EVAL:
436 return ctx->tes_rel_patch_id;
437 break;
438 default:
439 unreachable("Illegal stage");
440 }
441 }
442
443 /* Tessellation shaders pass outputs to the next shader using LDS.
444 *
445 * LS outputs = TCS inputs
446 * TCS outputs = TES inputs
447 *
448 * The LDS layout is:
449 * - TCS inputs for patch 0
450 * - TCS inputs for patch 1
451 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
452 * - ...
453 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
454 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
455 * - TCS outputs for patch 1
456 * - Per-patch TCS outputs for patch 1
457 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
458 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
459 * - ...
460 *
461 * All three shaders VS(LS), TCS, TES share the same LDS space.
462 */
463 static LLVMValueRef
464 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
465 {
466 if (ctx->stage == MESA_SHADER_VERTEX)
467 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
468 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
469 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
470 else {
471 assert(0);
472 return NULL;
473 }
474 }
475
476 static LLVMValueRef
477 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
478 {
479 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
480 }
481
482 static LLVMValueRef
483 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
484 {
485 return LLVMBuildMul(ctx->builder,
486 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
487 LLVMConstInt(ctx->i32, 4, false), "");
488 }
489
490 static LLVMValueRef
491 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
492 {
493 return LLVMBuildMul(ctx->builder,
494 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
495 LLVMConstInt(ctx->i32, 4, false), "");
496 }
497
498 static LLVMValueRef
499 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
500 {
501 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
502 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
503
504 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
505 }
506
507 static LLVMValueRef
508 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
509 {
510 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
511 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
512 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
513
514 return LLVMBuildAdd(ctx->builder, patch0_offset,
515 LLVMBuildMul(ctx->builder, patch_stride,
516 rel_patch_id, ""),
517 "");
518 }
519
520 static LLVMValueRef
521 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
522 {
523 LLVMValueRef patch0_patch_data_offset =
524 get_tcs_out_patch0_patch_data_offset(ctx);
525 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
526 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
527
528 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
529 LLVMBuildMul(ctx->builder, patch_stride,
530 rel_patch_id, ""),
531 "");
532 }
533
534 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
535 {
536 ud_info->sgpr_idx = sgpr_idx;
537 ud_info->num_sgprs = num_sgprs;
538 ud_info->indirect = false;
539 ud_info->indirect_offset = 0;
540 }
541
542 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
543 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
544 {
545 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
546 }
547
548
549 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
550 uint32_t indirect_offset)
551 {
552 ud_info->sgpr_idx = sgpr_idx;
553 ud_info->num_sgprs = num_sgprs;
554 ud_info->indirect = true;
555 ud_info->indirect_offset = indirect_offset;
556 }
557
558 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
559 {
560 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
561 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
562 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
563 "tess_lds");
564 }
565
566 struct user_sgpr_info {
567 bool need_ring_offsets;
568 uint8_t sgpr_count;
569 bool indirect_all_descriptor_sets;
570 };
571
572 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
573 struct user_sgpr_info *user_sgpr_info)
574 {
575 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
576
577 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
578 if (ctx->stage == MESA_SHADER_GEOMETRY ||
579 ctx->stage == MESA_SHADER_VERTEX ||
580 ctx->stage == MESA_SHADER_TESS_CTRL ||
581 ctx->stage == MESA_SHADER_TESS_EVAL ||
582 ctx->is_gs_copy_shader)
583 user_sgpr_info->need_ring_offsets = true;
584
585 if (ctx->stage == MESA_SHADER_FRAGMENT &&
586 ctx->shader_info->info.ps.needs_sample_positions)
587 user_sgpr_info->need_ring_offsets = true;
588
589 /* 2 user sgprs will nearly always be allocated for scratch/rings */
590 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
591 user_sgpr_info->sgpr_count += 2;
592 }
593
594 switch (ctx->stage) {
595 case MESA_SHADER_COMPUTE:
596 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
597 break;
598 case MESA_SHADER_FRAGMENT:
599 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
600 break;
601 case MESA_SHADER_VERTEX:
602 if (!ctx->is_gs_copy_shader) {
603 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
604 if (ctx->shader_info->info.vs.needs_draw_id) {
605 user_sgpr_info->sgpr_count += 3;
606 } else {
607 user_sgpr_info->sgpr_count += 2;
608 }
609 }
610 if (ctx->options->key.vs.as_ls)
611 user_sgpr_info->sgpr_count++;
612 break;
613 case MESA_SHADER_TESS_CTRL:
614 user_sgpr_info->sgpr_count += 4;
615 break;
616 case MESA_SHADER_TESS_EVAL:
617 user_sgpr_info->sgpr_count += 1;
618 break;
619 case MESA_SHADER_GEOMETRY:
620 user_sgpr_info->sgpr_count += 2;
621 break;
622 default:
623 break;
624 }
625
626 if (ctx->shader_info->info.needs_push_constants)
627 user_sgpr_info->sgpr_count += 2;
628
629 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
630 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
631 user_sgpr_info->sgpr_count += 2;
632 user_sgpr_info->indirect_all_descriptor_sets = true;
633 } else {
634 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
635 }
636 }
637
638 static void create_function(struct nir_to_llvm_context *ctx)
639 {
640 LLVMTypeRef arg_types[23];
641 unsigned arg_idx = 0;
642 unsigned array_params_mask = 0;
643 unsigned sgpr_count = 0, user_sgpr_count;
644 unsigned i;
645 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
646 unsigned user_sgpr_idx;
647 struct user_sgpr_info user_sgpr_info;
648
649 allocate_user_sgprs(ctx, &user_sgpr_info);
650 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
651 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* address of rings */
652 }
653
654 /* 1 for each descriptor set */
655 if (!user_sgpr_info.indirect_all_descriptor_sets) {
656 for (unsigned i = 0; i < num_sets; ++i) {
657 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
658 array_params_mask |= (1 << arg_idx);
659 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
660 }
661 }
662 } else {
663 array_params_mask |= (1 << arg_idx);
664 arg_types[arg_idx++] = const_array(const_array(ctx->i8, 1024 * 1024), 32);
665 }
666
667 if (ctx->shader_info->info.needs_push_constants) {
668 /* 1 for push constants and dynamic descriptors */
669 array_params_mask |= (1 << arg_idx);
670 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
671 }
672
673 switch (ctx->stage) {
674 case MESA_SHADER_COMPUTE:
675 if (ctx->shader_info->info.cs.grid_components_used)
676 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used); /* grid size */
677 user_sgpr_count = arg_idx;
678 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
679 arg_types[arg_idx++] = ctx->i32;
680 sgpr_count = arg_idx;
681
682 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
683 break;
684 case MESA_SHADER_VERTEX:
685 if (!ctx->is_gs_copy_shader) {
686 if (ctx->shader_info->info.vs.has_vertex_buffers)
687 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
688 arg_types[arg_idx++] = ctx->i32; // base vertex
689 arg_types[arg_idx++] = ctx->i32; // start instance
690 if (ctx->shader_info->info.vs.needs_draw_id)
691 arg_types[arg_idx++] = ctx->i32; // draw index
692 }
693 user_sgpr_count = arg_idx;
694 if (ctx->options->key.vs.as_es)
695 arg_types[arg_idx++] = ctx->i32; //es2gs offset
696 else if (ctx->options->key.vs.as_ls) {
697 arg_types[arg_idx++] = ctx->i32; //ls out layout
698 user_sgpr_count++;
699 }
700 sgpr_count = arg_idx;
701 arg_types[arg_idx++] = ctx->i32; // vertex id
702 if (!ctx->is_gs_copy_shader) {
703 arg_types[arg_idx++] = ctx->i32; // rel auto id
704 arg_types[arg_idx++] = ctx->i32; // vs prim id
705 arg_types[arg_idx++] = ctx->i32; // instance id
706 }
707 break;
708 case MESA_SHADER_TESS_CTRL:
709 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
710 arg_types[arg_idx++] = ctx->i32; // tcs out offsets
711 arg_types[arg_idx++] = ctx->i32; // tcs out layout
712 arg_types[arg_idx++] = ctx->i32; // tcs in layout
713 user_sgpr_count = arg_idx;
714 arg_types[arg_idx++] = ctx->i32; // param oc lds
715 arg_types[arg_idx++] = ctx->i32; // tess factor offset
716 sgpr_count = arg_idx;
717 arg_types[arg_idx++] = ctx->i32; // patch id
718 arg_types[arg_idx++] = ctx->i32; // rel ids;
719 break;
720 case MESA_SHADER_TESS_EVAL:
721 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
722 user_sgpr_count = arg_idx;
723 if (ctx->options->key.tes.as_es) {
724 arg_types[arg_idx++] = ctx->i32; // OC LDS
725 arg_types[arg_idx++] = ctx->i32; //
726 arg_types[arg_idx++] = ctx->i32; // es2gs offset
727 } else {
728 arg_types[arg_idx++] = ctx->i32; //
729 arg_types[arg_idx++] = ctx->i32; // OC LDS
730 }
731 sgpr_count = arg_idx;
732 arg_types[arg_idx++] = ctx->f32; // tes_u
733 arg_types[arg_idx++] = ctx->f32; // tes_v
734 arg_types[arg_idx++] = ctx->i32; // tes rel patch id
735 arg_types[arg_idx++] = ctx->i32; // tes patch id
736 break;
737 case MESA_SHADER_GEOMETRY:
738 arg_types[arg_idx++] = ctx->i32; // gsvs stride
739 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
740 user_sgpr_count = arg_idx;
741 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
742 arg_types[arg_idx++] = ctx->i32; // wave id
743 sgpr_count = arg_idx;
744 arg_types[arg_idx++] = ctx->i32; // vtx0
745 arg_types[arg_idx++] = ctx->i32; // vtx1
746 arg_types[arg_idx++] = ctx->i32; // prim id
747 arg_types[arg_idx++] = ctx->i32; // vtx2
748 arg_types[arg_idx++] = ctx->i32; // vtx3
749 arg_types[arg_idx++] = ctx->i32; // vtx4
750 arg_types[arg_idx++] = ctx->i32; // vtx5
751 arg_types[arg_idx++] = ctx->i32; // GS instance id
752 break;
753 case MESA_SHADER_FRAGMENT:
754 if (ctx->shader_info->info.ps.needs_sample_positions)
755 arg_types[arg_idx++] = ctx->i32; /* sample position offset */
756 user_sgpr_count = arg_idx;
757 arg_types[arg_idx++] = ctx->i32; /* prim mask */
758 sgpr_count = arg_idx;
759 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
760 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
761 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
762 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
763 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
764 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
765 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
766 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
767 arg_types[arg_idx++] = ctx->f32; /* pos x float */
768 arg_types[arg_idx++] = ctx->f32; /* pos y float */
769 arg_types[arg_idx++] = ctx->f32; /* pos z float */
770 arg_types[arg_idx++] = ctx->f32; /* pos w float */
771 arg_types[arg_idx++] = ctx->i32; /* front face */
772 arg_types[arg_idx++] = ctx->i32; /* ancillary */
773 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
774 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
775 break;
776 default:
777 unreachable("Shader stage not implemented");
778 }
779
780 ctx->main_function = create_llvm_function(
781 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
782 arg_idx, array_params_mask, sgpr_count, ctx->max_workgroup_size,
783 ctx->options->unsafe_math);
784 set_llvm_calling_convention(ctx->main_function, ctx->stage);
785
786 ctx->shader_info->num_input_sgprs = 0;
787 ctx->shader_info->num_input_vgprs = 0;
788
789 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
790 for (i = 0; i < user_sgpr_count; i++)
791 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
792
793 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
794 for (; i < sgpr_count; i++)
795 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
796
797 if (ctx->stage != MESA_SHADER_FRAGMENT)
798 for (; i < arg_idx; ++i)
799 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
800
801 arg_idx = 0;
802 user_sgpr_idx = 0;
803
804 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
805 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
806 user_sgpr_idx += 2;
807 if (ctx->options->supports_spill) {
808 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
809 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
810 NULL, 0, AC_FUNC_ATTR_READNONE);
811 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
812 const_array(ctx->v16i8, 16), "");
813 } else
814 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
815 }
816
817 if (!user_sgpr_info.indirect_all_descriptor_sets) {
818 for (unsigned i = 0; i < num_sets; ++i) {
819 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
820 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
821 user_sgpr_idx += 2;
822 ctx->descriptor_sets[i] =
823 LLVMGetParam(ctx->main_function, arg_idx++);
824 } else
825 ctx->descriptor_sets[i] = NULL;
826 }
827 } else {
828 uint32_t desc_sgpr_idx = user_sgpr_idx;
829 LLVMValueRef desc_sets = LLVMGetParam(ctx->main_function, arg_idx++);
830 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
831 user_sgpr_idx += 2;
832
833 for (unsigned i = 0; i < num_sets; ++i) {
834 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
835 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
836 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
837
838 } else
839 ctx->descriptor_sets[i] = NULL;
840 }
841 ctx->shader_info->need_indirect_descriptor_sets = true;
842 }
843
844 if (ctx->shader_info->info.needs_push_constants) {
845 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
846 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
847 user_sgpr_idx += 2;
848 }
849
850 switch (ctx->stage) {
851 case MESA_SHADER_COMPUTE:
852 if (ctx->shader_info->info.cs.grid_components_used) {
853 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
854 user_sgpr_idx += ctx->shader_info->info.cs.grid_components_used;
855 ctx->num_work_groups =
856 LLVMGetParam(ctx->main_function, arg_idx++);
857 }
858 ctx->workgroup_ids =
859 LLVMGetParam(ctx->main_function, arg_idx++);
860 ctx->tg_size =
861 LLVMGetParam(ctx->main_function, arg_idx++);
862 ctx->local_invocation_ids =
863 LLVMGetParam(ctx->main_function, arg_idx++);
864 break;
865 case MESA_SHADER_VERTEX:
866 if (!ctx->is_gs_copy_shader) {
867 if (ctx->shader_info->info.vs.has_vertex_buffers) {
868 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
869 user_sgpr_idx += 2;
870 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
871 }
872 unsigned vs_num = 2;
873 if (ctx->shader_info->info.vs.needs_draw_id)
874 vs_num++;
875
876 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
877 user_sgpr_idx += vs_num;
878
879 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
880 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
881 if (ctx->shader_info->info.vs.needs_draw_id)
882 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
883 }
884 if (ctx->options->key.vs.as_es)
885 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
886 else if (ctx->options->key.vs.as_ls) {
887 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, user_sgpr_idx, 1);
888 user_sgpr_idx += 1;
889 ctx->ls_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
890 }
891 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
892 if (!ctx->is_gs_copy_shader) {
893 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
894 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
895 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
896 }
897 if (ctx->options->key.vs.as_ls)
898 declare_tess_lds(ctx);
899 break;
900 case MESA_SHADER_TESS_CTRL:
901 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, user_sgpr_idx, 4);
902 user_sgpr_idx += 4;
903 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
904 ctx->tcs_out_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
905 ctx->tcs_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
906 ctx->tcs_in_layout = LLVMGetParam(ctx->main_function, arg_idx++);
907 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
908 ctx->tess_factor_offset = LLVMGetParam(ctx->main_function, arg_idx++);
909 ctx->tcs_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
910 ctx->tcs_rel_ids = LLVMGetParam(ctx->main_function, arg_idx++);
911
912 declare_tess_lds(ctx);
913 break;
914 case MESA_SHADER_TESS_EVAL:
915 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, user_sgpr_idx, 1);
916 user_sgpr_idx += 1;
917 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
918 if (ctx->options->key.tes.as_es) {
919 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
920 arg_idx++;
921 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
922 } else {
923 arg_idx++;
924 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
925 }
926 ctx->tes_u = LLVMGetParam(ctx->main_function, arg_idx++);
927 ctx->tes_v = LLVMGetParam(ctx->main_function, arg_idx++);
928 ctx->tes_rel_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
929 ctx->tes_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
930 break;
931 case MESA_SHADER_GEOMETRY:
932 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
933 user_sgpr_idx += 2;
934 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
935 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
936 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
937 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
938 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
939 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
940 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
941 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
942 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
943 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
944 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
945 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
946 break;
947 case MESA_SHADER_FRAGMENT:
948 if (ctx->shader_info->info.ps.needs_sample_positions) {
949 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, user_sgpr_idx, 1);
950 user_sgpr_idx += 1;
951 ctx->sample_pos_offset = LLVMGetParam(ctx->main_function, arg_idx++);
952 }
953 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
954 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
955 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
956 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
957 arg_idx++;
958 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
959 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
960 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
961 arg_idx++; /* line stipple */
962 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
963 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
964 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
965 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
966 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
967 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
968 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
969 break;
970 default:
971 unreachable("Shader stage not implemented");
972 }
973 }
974
975 static void setup_types(struct nir_to_llvm_context *ctx)
976 {
977 LLVMValueRef args[4];
978
979 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
980 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
981 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
982 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
983 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
984 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
985 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
986 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
987 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
988 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
989 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
990 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
991 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
992 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
993 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
994 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
995
996 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
997 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
998 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
999 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
1000 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
1001 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
1002
1003 args[0] = ctx->f32zero;
1004 args[1] = ctx->f32zero;
1005 args[2] = ctx->f32zero;
1006 args[3] = ctx->f32one;
1007 ctx->v4f32empty = LLVMConstVector(args, 4);
1008
1009 ctx->uniform_md_kind =
1010 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
1011 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
1012
1013 args[0] = LLVMConstReal(ctx->f32, 2.5);
1014 }
1015
1016 static int get_llvm_num_components(LLVMValueRef value)
1017 {
1018 LLVMTypeRef type = LLVMTypeOf(value);
1019 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1020 ? LLVMGetVectorSize(type)
1021 : 1;
1022 return num_components;
1023 }
1024
1025 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
1026 LLVMValueRef value,
1027 int index)
1028 {
1029 int count = get_llvm_num_components(value);
1030
1031 assert(index < count);
1032 if (count == 1)
1033 return value;
1034
1035 return LLVMBuildExtractElement(ctx->builder, value,
1036 LLVMConstInt(ctx->i32, index, false), "");
1037 }
1038
1039 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
1040 LLVMValueRef value, unsigned count)
1041 {
1042 unsigned num_components = get_llvm_num_components(value);
1043 if (count == num_components)
1044 return value;
1045
1046 LLVMValueRef masks[] = {
1047 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1048 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1049
1050 if (count == 1)
1051 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1052 "");
1053
1054 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1055 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1056 }
1057
1058 static void
1059 build_store_values_extended(struct nir_to_llvm_context *ctx,
1060 LLVMValueRef *values,
1061 unsigned value_count,
1062 unsigned value_stride,
1063 LLVMValueRef vec)
1064 {
1065 LLVMBuilderRef builder = ctx->builder;
1066 unsigned i;
1067
1068 if (value_count == 1) {
1069 LLVMBuildStore(builder, vec, values[0]);
1070 return;
1071 }
1072
1073 for (i = 0; i < value_count; i++) {
1074 LLVMValueRef ptr = values[i * value_stride];
1075 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
1076 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1077 LLVMBuildStore(builder, value, ptr);
1078 }
1079 }
1080
1081 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
1082 nir_ssa_def *def)
1083 {
1084 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
1085 if (def->num_components > 1) {
1086 type = LLVMVectorType(type, def->num_components);
1087 }
1088 return type;
1089 }
1090
1091 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
1092 {
1093 assert(src.is_ssa);
1094 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
1095 return (LLVMValueRef)entry->data;
1096 }
1097
1098
1099 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
1100 struct nir_block *b)
1101 {
1102 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
1103 return (LLVMBasicBlockRef)entry->data;
1104 }
1105
1106 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
1107 nir_alu_src src,
1108 unsigned num_components)
1109 {
1110 LLVMValueRef value = get_src(ctx, src.src);
1111 bool need_swizzle = false;
1112
1113 assert(value);
1114 LLVMTypeRef type = LLVMTypeOf(value);
1115 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1116 ? LLVMGetVectorSize(type)
1117 : 1;
1118
1119 for (unsigned i = 0; i < num_components; ++i) {
1120 assert(src.swizzle[i] < src_components);
1121 if (src.swizzle[i] != i)
1122 need_swizzle = true;
1123 }
1124
1125 if (need_swizzle || num_components != src_components) {
1126 LLVMValueRef masks[] = {
1127 LLVMConstInt(ctx->i32, src.swizzle[0], false),
1128 LLVMConstInt(ctx->i32, src.swizzle[1], false),
1129 LLVMConstInt(ctx->i32, src.swizzle[2], false),
1130 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
1131
1132 if (src_components > 1 && num_components == 1) {
1133 value = LLVMBuildExtractElement(ctx->builder, value,
1134 masks[0], "");
1135 } else if (src_components == 1 && num_components > 1) {
1136 LLVMValueRef values[] = {value, value, value, value};
1137 value = ac_build_gather_values(&ctx->ac, values, num_components);
1138 } else {
1139 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1140 value = LLVMBuildShuffleVector(ctx->builder, value, value,
1141 swizzle, "");
1142 }
1143 }
1144 assert(!src.negate);
1145 assert(!src.abs);
1146 return value;
1147 }
1148
1149 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
1150 LLVMIntPredicate pred, LLVMValueRef src0,
1151 LLVMValueRef src1)
1152 {
1153 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1154 return LLVMBuildSelect(ctx->builder, result,
1155 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1156 LLVMConstInt(ctx->i32, 0, false), "");
1157 }
1158
1159 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
1160 LLVMRealPredicate pred, LLVMValueRef src0,
1161 LLVMValueRef src1)
1162 {
1163 LLVMValueRef result;
1164 src0 = to_float(ctx, src0);
1165 src1 = to_float(ctx, src1);
1166 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1167 return LLVMBuildSelect(ctx->builder, result,
1168 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1169 LLVMConstInt(ctx->i32, 0, false), "");
1170 }
1171
1172 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
1173 const char *intrin,
1174 LLVMTypeRef result_type,
1175 LLVMValueRef src0)
1176 {
1177 char name[64];
1178 LLVMValueRef params[] = {
1179 to_float(ctx, src0),
1180 };
1181
1182 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1183 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1184 }
1185
1186 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
1187 const char *intrin,
1188 LLVMTypeRef result_type,
1189 LLVMValueRef src0, LLVMValueRef src1)
1190 {
1191 char name[64];
1192 LLVMValueRef params[] = {
1193 to_float(ctx, src0),
1194 to_float(ctx, src1),
1195 };
1196
1197 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1198 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1199 }
1200
1201 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
1202 const char *intrin,
1203 LLVMTypeRef result_type,
1204 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1205 {
1206 char name[64];
1207 LLVMValueRef params[] = {
1208 to_float(ctx, src0),
1209 to_float(ctx, src1),
1210 to_float(ctx, src2),
1211 };
1212
1213 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1214 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1215 }
1216
1217 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
1218 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1219 {
1220 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1221 ctx->i32zero, "");
1222 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1223 }
1224
1225 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
1226 LLVMValueRef src0)
1227 {
1228 LLVMValueRef params[2] = {
1229 src0,
1230
1231 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1232 * add special code to check for x=0. The reason is that
1233 * the LLVM behavior for x=0 is different from what we
1234 * need here.
1235 *
1236 * The hardware already implements the correct behavior.
1237 */
1238 LLVMConstInt(ctx->i32, 1, false),
1239 };
1240 return ac_build_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1241 }
1242
1243 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
1244 LLVMValueRef src0)
1245 {
1246 return ac_build_imsb(&ctx->ac, src0, ctx->i32);
1247 }
1248
1249 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
1250 LLVMValueRef src0)
1251 {
1252 return ac_build_umsb(&ctx->ac, src0, ctx->i32);
1253 }
1254
1255 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
1256 LLVMIntPredicate pred,
1257 LLVMValueRef src0, LLVMValueRef src1)
1258 {
1259 return LLVMBuildSelect(ctx->builder,
1260 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1261 src0,
1262 src1, "");
1263
1264 }
1265 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
1266 LLVMValueRef src0)
1267 {
1268 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1269 LLVMBuildNeg(ctx->builder, src0, ""));
1270 }
1271
1272 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1273 LLVMValueRef src0)
1274 {
1275 LLVMValueRef cmp, val;
1276
1277 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1278 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1279 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1280 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1281 return val;
1282 }
1283
1284 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1285 LLVMValueRef src0)
1286 {
1287 LLVMValueRef cmp, val;
1288
1289 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1290 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1291 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1292 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1293 return val;
1294 }
1295
1296 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1297 LLVMValueRef src0)
1298 {
1299 const char *intr = "llvm.floor.f32";
1300 LLVMValueRef fsrc0 = to_float(ctx, src0);
1301 LLVMValueRef params[] = {
1302 fsrc0,
1303 };
1304 LLVMValueRef floor = ac_build_intrinsic(&ctx->ac, intr,
1305 ctx->f32, params, 1,
1306 AC_FUNC_ATTR_READNONE);
1307 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1308 }
1309
1310 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1311 const char *intrin,
1312 LLVMValueRef src0, LLVMValueRef src1)
1313 {
1314 LLVMTypeRef ret_type;
1315 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1316 LLVMValueRef res;
1317 LLVMValueRef params[] = { src0, src1 };
1318 ret_type = LLVMStructTypeInContext(ctx->context, types,
1319 2, true);
1320
1321 res = ac_build_intrinsic(&ctx->ac, intrin, ret_type,
1322 params, 2, AC_FUNC_ATTR_READNONE);
1323
1324 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1325 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1326 return res;
1327 }
1328
1329 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1330 LLVMValueRef src0)
1331 {
1332 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1333 }
1334
1335 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1336 LLVMValueRef src0)
1337 {
1338 LLVMValueRef result;
1339 LLVMValueRef cond;
1340
1341 src0 = to_float(ctx, src0);
1342 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1343
1344 /* TODO SI/CIK options here */
1345 if (ctx->options->chip_class >= VI) {
1346 LLVMValueRef args[2];
1347 /* Check if the result is a denormal - and flush to 0 if so. */
1348 args[0] = result;
1349 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1350 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1351 }
1352
1353 /* need to convert back up to f32 */
1354 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1355
1356 if (ctx->options->chip_class >= VI)
1357 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1358
1359 return result;
1360 }
1361
1362 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1363 LLVMValueRef src0, LLVMValueRef src1)
1364 {
1365 LLVMValueRef dst64, result;
1366 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1367 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1368
1369 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1370 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1371 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1372 return result;
1373 }
1374
1375 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1376 LLVMValueRef src0, LLVMValueRef src1)
1377 {
1378 LLVMValueRef dst64, result;
1379 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1380 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1381
1382 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1383 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1384 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1385 return result;
1386 }
1387
1388 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1389 bool is_signed,
1390 LLVMValueRef srcs[3])
1391 {
1392 LLVMValueRef result;
1393 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1394
1395 result = ac_build_bfe(&ctx->ac, srcs[0], srcs[1], srcs[2], is_signed);
1396 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1397 return result;
1398 }
1399
1400 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1401 LLVMValueRef src0, LLVMValueRef src1,
1402 LLVMValueRef src2, LLVMValueRef src3)
1403 {
1404 LLVMValueRef bfi_args[3], result;
1405
1406 bfi_args[0] = LLVMBuildShl(ctx->builder,
1407 LLVMBuildSub(ctx->builder,
1408 LLVMBuildShl(ctx->builder,
1409 ctx->i32one,
1410 src3, ""),
1411 ctx->i32one, ""),
1412 src2, "");
1413 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1414 bfi_args[2] = src0;
1415
1416 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1417
1418 /* Calculate:
1419 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1420 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1421 */
1422 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1423 LLVMBuildAnd(ctx->builder, bfi_args[0],
1424 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1425
1426 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1427 return result;
1428 }
1429
1430 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1431 LLVMValueRef src0)
1432 {
1433 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1434 int i;
1435 LLVMValueRef comp[2];
1436
1437 src0 = to_float(ctx, src0);
1438 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1439 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1440 for (i = 0; i < 2; i++) {
1441 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1442 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1443 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1444 }
1445
1446 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1447 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1448
1449 return comp[0];
1450 }
1451
1452 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1453 LLVMValueRef src0)
1454 {
1455 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1456 LLVMValueRef temps[2], result, val;
1457 int i;
1458
1459 for (i = 0; i < 2; i++) {
1460 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1461 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1462 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1463 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1464 }
1465
1466 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1467 ctx->i32zero, "");
1468 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1469 ctx->i32one, "");
1470 return result;
1471 }
1472
1473 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1474 nir_op op,
1475 LLVMValueRef src0)
1476 {
1477 unsigned mask;
1478 int idx;
1479 LLVMValueRef result;
1480 ctx->has_ddxy = true;
1481
1482 if (!ctx->lds && !ctx->has_ds_bpermute)
1483 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1484 LLVMArrayType(ctx->i32, 64),
1485 "ddxy_lds", LOCAL_ADDR_SPACE);
1486
1487 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1488 mask = AC_TID_MASK_LEFT;
1489 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1490 mask = AC_TID_MASK_TOP;
1491 else
1492 mask = AC_TID_MASK_TOP_LEFT;
1493
1494 /* for DDX we want to next X pixel, DDY next Y pixel. */
1495 if (op == nir_op_fddx_fine ||
1496 op == nir_op_fddx_coarse ||
1497 op == nir_op_fddx)
1498 idx = 1;
1499 else
1500 idx = 2;
1501
1502 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1503 mask, idx, ctx->lds,
1504 src0);
1505 return result;
1506 }
1507
1508 /*
1509 * this takes an I,J coordinate pair,
1510 * and works out the X and Y derivatives.
1511 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1512 */
1513 static LLVMValueRef emit_ddxy_interp(
1514 struct nir_to_llvm_context *ctx,
1515 LLVMValueRef interp_ij)
1516 {
1517 LLVMValueRef result[4], a;
1518 unsigned i;
1519
1520 for (i = 0; i < 2; i++) {
1521 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1522 LLVMConstInt(ctx->i32, i, false), "");
1523 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1524 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1525 }
1526 return ac_build_gather_values(&ctx->ac, result, 4);
1527 }
1528
1529 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1530 {
1531 LLVMValueRef src[4], result = NULL;
1532 unsigned num_components = instr->dest.dest.ssa.num_components;
1533 unsigned src_components;
1534 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1535
1536 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1537 switch (instr->op) {
1538 case nir_op_vec2:
1539 case nir_op_vec3:
1540 case nir_op_vec4:
1541 src_components = 1;
1542 break;
1543 case nir_op_pack_half_2x16:
1544 src_components = 2;
1545 break;
1546 case nir_op_unpack_half_2x16:
1547 src_components = 1;
1548 break;
1549 default:
1550 src_components = num_components;
1551 break;
1552 }
1553 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1554 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1555
1556 switch (instr->op) {
1557 case nir_op_fmov:
1558 case nir_op_imov:
1559 result = src[0];
1560 break;
1561 case nir_op_fneg:
1562 src[0] = to_float(ctx, src[0]);
1563 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1564 break;
1565 case nir_op_ineg:
1566 result = LLVMBuildNeg(ctx->builder, src[0], "");
1567 break;
1568 case nir_op_inot:
1569 result = LLVMBuildNot(ctx->builder, src[0], "");
1570 break;
1571 case nir_op_iadd:
1572 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1573 break;
1574 case nir_op_fadd:
1575 src[0] = to_float(ctx, src[0]);
1576 src[1] = to_float(ctx, src[1]);
1577 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1578 break;
1579 case nir_op_fsub:
1580 src[0] = to_float(ctx, src[0]);
1581 src[1] = to_float(ctx, src[1]);
1582 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1583 break;
1584 case nir_op_isub:
1585 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1586 break;
1587 case nir_op_imul:
1588 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1589 break;
1590 case nir_op_imod:
1591 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1592 break;
1593 case nir_op_umod:
1594 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1595 break;
1596 case nir_op_fmod:
1597 src[0] = to_float(ctx, src[0]);
1598 src[1] = to_float(ctx, src[1]);
1599 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1600 result = emit_intrin_1f_param(ctx, "llvm.floor",
1601 to_float_type(ctx, def_type), result);
1602 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1603 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1604 break;
1605 case nir_op_frem:
1606 src[0] = to_float(ctx, src[0]);
1607 src[1] = to_float(ctx, src[1]);
1608 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1609 break;
1610 case nir_op_irem:
1611 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1612 break;
1613 case nir_op_idiv:
1614 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1615 break;
1616 case nir_op_udiv:
1617 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1618 break;
1619 case nir_op_fmul:
1620 src[0] = to_float(ctx, src[0]);
1621 src[1] = to_float(ctx, src[1]);
1622 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1623 break;
1624 case nir_op_fdiv:
1625 src[0] = to_float(ctx, src[0]);
1626 src[1] = to_float(ctx, src[1]);
1627 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1628 break;
1629 case nir_op_frcp:
1630 src[0] = to_float(ctx, src[0]);
1631 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1632 break;
1633 case nir_op_iand:
1634 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1635 break;
1636 case nir_op_ior:
1637 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1638 break;
1639 case nir_op_ixor:
1640 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1641 break;
1642 case nir_op_ishl:
1643 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1644 break;
1645 case nir_op_ishr:
1646 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1647 break;
1648 case nir_op_ushr:
1649 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1650 break;
1651 case nir_op_ilt:
1652 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1653 break;
1654 case nir_op_ine:
1655 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1656 break;
1657 case nir_op_ieq:
1658 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1659 break;
1660 case nir_op_ige:
1661 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1662 break;
1663 case nir_op_ult:
1664 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1665 break;
1666 case nir_op_uge:
1667 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1668 break;
1669 case nir_op_feq:
1670 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1671 break;
1672 case nir_op_fne:
1673 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1674 break;
1675 case nir_op_flt:
1676 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1677 break;
1678 case nir_op_fge:
1679 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1680 break;
1681 case nir_op_fabs:
1682 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1683 to_float_type(ctx, def_type), src[0]);
1684 break;
1685 case nir_op_iabs:
1686 result = emit_iabs(ctx, src[0]);
1687 break;
1688 case nir_op_imax:
1689 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1690 break;
1691 case nir_op_imin:
1692 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1693 break;
1694 case nir_op_umax:
1695 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1696 break;
1697 case nir_op_umin:
1698 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1699 break;
1700 case nir_op_isign:
1701 result = emit_isign(ctx, src[0]);
1702 break;
1703 case nir_op_fsign:
1704 src[0] = to_float(ctx, src[0]);
1705 result = emit_fsign(ctx, src[0]);
1706 break;
1707 case nir_op_ffloor:
1708 result = emit_intrin_1f_param(ctx, "llvm.floor",
1709 to_float_type(ctx, def_type), src[0]);
1710 break;
1711 case nir_op_ftrunc:
1712 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1713 to_float_type(ctx, def_type), src[0]);
1714 break;
1715 case nir_op_fceil:
1716 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1717 to_float_type(ctx, def_type), src[0]);
1718 break;
1719 case nir_op_fround_even:
1720 result = emit_intrin_1f_param(ctx, "llvm.rint",
1721 to_float_type(ctx, def_type),src[0]);
1722 break;
1723 case nir_op_ffract:
1724 result = emit_ffract(ctx, src[0]);
1725 break;
1726 case nir_op_fsin:
1727 result = emit_intrin_1f_param(ctx, "llvm.sin",
1728 to_float_type(ctx, def_type), src[0]);
1729 break;
1730 case nir_op_fcos:
1731 result = emit_intrin_1f_param(ctx, "llvm.cos",
1732 to_float_type(ctx, def_type), src[0]);
1733 break;
1734 case nir_op_fsqrt:
1735 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1736 to_float_type(ctx, def_type), src[0]);
1737 break;
1738 case nir_op_fexp2:
1739 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1740 to_float_type(ctx, def_type), src[0]);
1741 break;
1742 case nir_op_flog2:
1743 result = emit_intrin_1f_param(ctx, "llvm.log2",
1744 to_float_type(ctx, def_type), src[0]);
1745 break;
1746 case nir_op_frsq:
1747 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1748 to_float_type(ctx, def_type), src[0]);
1749 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1750 break;
1751 case nir_op_fpow:
1752 result = emit_intrin_2f_param(ctx, "llvm.pow",
1753 to_float_type(ctx, def_type), src[0], src[1]);
1754 break;
1755 case nir_op_fmax:
1756 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1757 to_float_type(ctx, def_type), src[0], src[1]);
1758 if (instr->dest.dest.ssa.bit_size == 32)
1759 result = emit_intrin_1f_param(ctx, "llvm.canonicalize",
1760 to_float_type(ctx, def_type),
1761 result);
1762 break;
1763 case nir_op_fmin:
1764 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1765 to_float_type(ctx, def_type), src[0], src[1]);
1766 if (instr->dest.dest.ssa.bit_size == 32)
1767 result = emit_intrin_1f_param(ctx, "llvm.canonicalize",
1768 to_float_type(ctx, def_type),
1769 result);
1770 break;
1771 case nir_op_ffma:
1772 result = emit_intrin_3f_param(ctx, "llvm.fma",
1773 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1774 break;
1775 case nir_op_ibitfield_extract:
1776 result = emit_bitfield_extract(ctx, true, src);
1777 break;
1778 case nir_op_ubitfield_extract:
1779 result = emit_bitfield_extract(ctx, false, src);
1780 break;
1781 case nir_op_bitfield_insert:
1782 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1783 break;
1784 case nir_op_bitfield_reverse:
1785 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1786 break;
1787 case nir_op_bit_count:
1788 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1789 break;
1790 case nir_op_vec2:
1791 case nir_op_vec3:
1792 case nir_op_vec4:
1793 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1794 src[i] = to_integer(ctx, src[i]);
1795 result = ac_build_gather_values(&ctx->ac, src, num_components);
1796 break;
1797 case nir_op_f2i32:
1798 case nir_op_f2i64:
1799 src[0] = to_float(ctx, src[0]);
1800 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1801 break;
1802 case nir_op_f2u32:
1803 case nir_op_f2u64:
1804 src[0] = to_float(ctx, src[0]);
1805 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1806 break;
1807 case nir_op_i2f32:
1808 case nir_op_i2f64:
1809 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1810 break;
1811 case nir_op_u2f32:
1812 case nir_op_u2f64:
1813 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1814 break;
1815 case nir_op_f2f64:
1816 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1817 break;
1818 case nir_op_f2f32:
1819 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1820 break;
1821 case nir_op_u2u32:
1822 case nir_op_u2u64:
1823 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1824 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1825 else
1826 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1827 break;
1828 case nir_op_i2i32:
1829 case nir_op_i2i64:
1830 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1831 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1832 else
1833 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1834 break;
1835 case nir_op_bcsel:
1836 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1837 break;
1838 case nir_op_find_lsb:
1839 result = emit_find_lsb(ctx, src[0]);
1840 break;
1841 case nir_op_ufind_msb:
1842 result = emit_ufind_msb(ctx, src[0]);
1843 break;
1844 case nir_op_ifind_msb:
1845 result = emit_ifind_msb(ctx, src[0]);
1846 break;
1847 case nir_op_uadd_carry:
1848 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1849 break;
1850 case nir_op_usub_borrow:
1851 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1852 break;
1853 case nir_op_b2f:
1854 result = emit_b2f(ctx, src[0]);
1855 break;
1856 case nir_op_fquantize2f16:
1857 result = emit_f2f16(ctx, src[0]);
1858 break;
1859 case nir_op_umul_high:
1860 result = emit_umul_high(ctx, src[0], src[1]);
1861 break;
1862 case nir_op_imul_high:
1863 result = emit_imul_high(ctx, src[0], src[1]);
1864 break;
1865 case nir_op_pack_half_2x16:
1866 result = emit_pack_half_2x16(ctx, src[0]);
1867 break;
1868 case nir_op_unpack_half_2x16:
1869 result = emit_unpack_half_2x16(ctx, src[0]);
1870 break;
1871 case nir_op_fddx:
1872 case nir_op_fddy:
1873 case nir_op_fddx_fine:
1874 case nir_op_fddy_fine:
1875 case nir_op_fddx_coarse:
1876 case nir_op_fddy_coarse:
1877 result = emit_ddxy(ctx, instr->op, src[0]);
1878 break;
1879 default:
1880 fprintf(stderr, "Unknown NIR alu instr: ");
1881 nir_print_instr(&instr->instr, stderr);
1882 fprintf(stderr, "\n");
1883 abort();
1884 }
1885
1886 if (result) {
1887 assert(instr->dest.dest.is_ssa);
1888 result = to_integer(ctx, result);
1889 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1890 result);
1891 }
1892 }
1893
1894 static void visit_load_const(struct nir_to_llvm_context *ctx,
1895 nir_load_const_instr *instr)
1896 {
1897 LLVMValueRef values[4], value = NULL;
1898 LLVMTypeRef element_type =
1899 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1900
1901 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1902 switch (instr->def.bit_size) {
1903 case 32:
1904 values[i] = LLVMConstInt(element_type,
1905 instr->value.u32[i], false);
1906 break;
1907 case 64:
1908 values[i] = LLVMConstInt(element_type,
1909 instr->value.u64[i], false);
1910 break;
1911 default:
1912 fprintf(stderr,
1913 "unsupported nir load_const bit_size: %d\n",
1914 instr->def.bit_size);
1915 abort();
1916 }
1917 }
1918 if (instr->def.num_components > 1) {
1919 value = LLVMConstVector(values, instr->def.num_components);
1920 } else
1921 value = values[0];
1922
1923 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1924 }
1925
1926 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1927 LLVMTypeRef type)
1928 {
1929 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1930 return LLVMBuildBitCast(ctx->builder, ptr,
1931 LLVMPointerType(type, addr_space), "");
1932 }
1933
1934 static LLVMValueRef
1935 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1936 {
1937 LLVMValueRef size =
1938 LLVMBuildExtractElement(ctx->builder, descriptor,
1939 LLVMConstInt(ctx->i32, 2, false), "");
1940
1941 /* VI only */
1942 if (ctx->options->chip_class >= VI && in_elements) {
1943 /* On VI, the descriptor contains the size in bytes,
1944 * but TXQ must return the size in elements.
1945 * The stride is always non-zero for resources using TXQ.
1946 */
1947 LLVMValueRef stride =
1948 LLVMBuildExtractElement(ctx->builder, descriptor,
1949 LLVMConstInt(ctx->i32, 1, false), "");
1950 stride = LLVMBuildLShr(ctx->builder, stride,
1951 LLVMConstInt(ctx->i32, 16, false), "");
1952 stride = LLVMBuildAnd(ctx->builder, stride,
1953 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1954
1955 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1956 }
1957 return size;
1958 }
1959
1960 /**
1961 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1962 * intrinsic names).
1963 */
1964 static void build_int_type_name(
1965 LLVMTypeRef type,
1966 char *buf, unsigned bufsize)
1967 {
1968 assert(bufsize >= 6);
1969
1970 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1971 snprintf(buf, bufsize, "v%ui32",
1972 LLVMGetVectorSize(type));
1973 else
1974 strcpy(buf, "i32");
1975 }
1976
1977 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1978 struct ac_image_args *args,
1979 nir_tex_instr *instr)
1980 {
1981 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1982 LLVMValueRef coord = args->addr;
1983 LLVMValueRef half_texel[2];
1984 LLVMValueRef compare_cube_wa;
1985 LLVMValueRef result;
1986 int c;
1987 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1988
1989 //TODO Rect
1990 {
1991 struct ac_image_args txq_args = { 0 };
1992
1993 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1994 txq_args.opcode = ac_image_get_resinfo;
1995 txq_args.dmask = 0xf;
1996 txq_args.addr = ctx->i32zero;
1997 txq_args.resource = args->resource;
1998 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
1999
2000 for (c = 0; c < 2; c++) {
2001 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2002 LLVMConstInt(ctx->i32, c, false), "");
2003 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2004 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
2005 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2006 LLVMConstReal(ctx->f32, -0.5), "");
2007 }
2008 }
2009
2010 LLVMValueRef orig_coords = args->addr;
2011
2012 for (c = 0; c < 2; c++) {
2013 LLVMValueRef tmp;
2014 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2015 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2016 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2017 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2018 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2019 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2020 }
2021
2022
2023 /*
2024 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2025 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2026 * workaround by sampling using a scaled type and converting.
2027 * This is taken from amdgpu-pro shaders.
2028 */
2029 /* NOTE this produces some ugly code compared to amdgpu-pro,
2030 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2031 * and then reads them back. -pro generates two selects,
2032 * one s_cmp for the descriptor rewriting
2033 * one v_cmp for the coordinate and result changes.
2034 */
2035 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2036 LLVMValueRef tmp, tmp2;
2037
2038 /* workaround 8/8/8/8 uint/sint cube gather bug */
2039 /* first detect it then change to a scaled read and f2i */
2040 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
2041 tmp2 = tmp;
2042
2043 /* extract the DATA_FORMAT */
2044 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
2045 LLVMConstInt(ctx->i32, 6, false), false);
2046
2047 /* is the DATA_FORMAT == 8_8_8_8 */
2048 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2049
2050 if (stype == GLSL_TYPE_UINT)
2051 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2052 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2053 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2054 else
2055 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2056 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2057 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2058
2059 /* replace the NUM FORMAT in the descriptor */
2060 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2061 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2062
2063 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
2064
2065 /* don't modify the coordinates for this case */
2066 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2067 }
2068 args->addr = coord;
2069 result = ac_build_image_opcode(&ctx->ac, args);
2070
2071 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2072 LLVMValueRef tmp, tmp2;
2073
2074 /* if the cube workaround is in place, f2i the result. */
2075 for (c = 0; c < 4; c++) {
2076 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2077 if (stype == GLSL_TYPE_UINT)
2078 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2079 else
2080 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2081 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2082 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2083 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2084 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2085 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2086 }
2087 }
2088 return result;
2089 }
2090
2091 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
2092 nir_tex_instr *instr,
2093 bool lod_is_zero,
2094 struct ac_image_args *args)
2095 {
2096 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2097 return ac_build_buffer_load_format(&ctx->ac,
2098 args->resource,
2099 args->addr,
2100 LLVMConstInt(ctx->i32, 0, false),
2101 true);
2102 }
2103
2104 args->opcode = ac_image_sample;
2105 args->compare = instr->is_shadow;
2106
2107 switch (instr->op) {
2108 case nir_texop_txf:
2109 case nir_texop_txf_ms:
2110 case nir_texop_samples_identical:
2111 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2112 args->compare = false;
2113 args->offset = false;
2114 break;
2115 case nir_texop_txb:
2116 args->bias = true;
2117 break;
2118 case nir_texop_txl:
2119 if (lod_is_zero)
2120 args->level_zero = true;
2121 else
2122 args->lod = true;
2123 break;
2124 case nir_texop_txs:
2125 case nir_texop_query_levels:
2126 args->opcode = ac_image_get_resinfo;
2127 break;
2128 case nir_texop_tex:
2129 if (ctx->stage != MESA_SHADER_FRAGMENT)
2130 args->level_zero = true;
2131 break;
2132 case nir_texop_txd:
2133 args->deriv = true;
2134 break;
2135 case nir_texop_tg4:
2136 args->opcode = ac_image_gather4;
2137 args->level_zero = true;
2138 break;
2139 case nir_texop_lod:
2140 args->opcode = ac_image_get_lod;
2141 args->compare = false;
2142 args->offset = false;
2143 break;
2144 default:
2145 break;
2146 }
2147
2148 if (instr->op == nir_texop_tg4) {
2149 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2150 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2151 return radv_lower_gather4_integer(ctx, args, instr);
2152 }
2153 }
2154 return ac_build_image_opcode(&ctx->ac, args);
2155 }
2156
2157 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2158 nir_intrinsic_instr *instr)
2159 {
2160 LLVMValueRef index = get_src(ctx, instr->src[0]);
2161 unsigned desc_set = nir_intrinsic_desc_set(instr);
2162 unsigned binding = nir_intrinsic_binding(instr);
2163 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2164 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2165 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2166 unsigned base_offset = layout->binding[binding].offset;
2167 LLVMValueRef offset, stride;
2168
2169 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2170 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2171 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2172 layout->binding[binding].dynamic_offset_offset;
2173 desc_ptr = ctx->push_constants;
2174 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2175 stride = LLVMConstInt(ctx->i32, 16, false);
2176 } else
2177 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2178
2179 offset = LLVMConstInt(ctx->i32, base_offset, false);
2180 index = LLVMBuildMul(ctx->builder, index, stride, "");
2181 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2182
2183 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2184 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2185 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2186
2187 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2188 }
2189
2190 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2191 nir_intrinsic_instr *instr)
2192 {
2193 LLVMValueRef ptr, addr;
2194
2195 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2196 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
2197
2198 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2199 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
2200
2201 return LLVMBuildLoad(ctx->builder, ptr, "");
2202 }
2203
2204 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2205 nir_intrinsic_instr *instr)
2206 {
2207 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2208
2209 return get_buffer_size(ctx, desc, false);
2210 }
2211 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2212 nir_intrinsic_instr *instr)
2213 {
2214 const char *store_name;
2215 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2216 LLVMTypeRef data_type = ctx->f32;
2217 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
2218 int components_32bit = elem_size_mult * instr->num_components;
2219 unsigned writemask = nir_intrinsic_write_mask(instr);
2220 LLVMValueRef base_data, base_offset;
2221 LLVMValueRef params[6];
2222
2223 if (ctx->stage == MESA_SHADER_FRAGMENT)
2224 ctx->shader_info->fs.writes_memory = true;
2225
2226 params[1] = get_src(ctx, instr->src[1]);
2227 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2228 params[4] = ctx->i1false; /* glc */
2229 params[5] = ctx->i1false; /* slc */
2230
2231 if (components_32bit > 1)
2232 data_type = LLVMVectorType(ctx->f32, components_32bit);
2233
2234 base_data = to_float(ctx, src_data);
2235 base_data = trim_vector(ctx, base_data, instr->num_components);
2236 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2237 data_type, "");
2238 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2239 while (writemask) {
2240 int start, count;
2241 LLVMValueRef data;
2242 LLVMValueRef offset;
2243 LLVMValueRef tmp;
2244 u_bit_scan_consecutive_range(&writemask, &start, &count);
2245
2246 /* Due to an LLVM limitation, split 3-element writes
2247 * into a 2-element and a 1-element write. */
2248 if (count == 3) {
2249 writemask |= 1 << (start + 2);
2250 count = 2;
2251 }
2252
2253 start *= elem_size_mult;
2254 count *= elem_size_mult;
2255
2256 if (count > 4) {
2257 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2258 count = 4;
2259 }
2260
2261 if (count == 4) {
2262 store_name = "llvm.amdgcn.buffer.store.v4f32";
2263 data = base_data;
2264 } else if (count == 2) {
2265 tmp = LLVMBuildExtractElement(ctx->builder,
2266 base_data, LLVMConstInt(ctx->i32, start, false), "");
2267 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2268 ctx->i32zero, "");
2269
2270 tmp = LLVMBuildExtractElement(ctx->builder,
2271 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2272 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2273 ctx->i32one, "");
2274 store_name = "llvm.amdgcn.buffer.store.v2f32";
2275
2276 } else {
2277 assert(count == 1);
2278 if (get_llvm_num_components(base_data) > 1)
2279 data = LLVMBuildExtractElement(ctx->builder, base_data,
2280 LLVMConstInt(ctx->i32, start, false), "");
2281 else
2282 data = base_data;
2283 store_name = "llvm.amdgcn.buffer.store.f32";
2284 }
2285
2286 offset = base_offset;
2287 if (start != 0) {
2288 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2289 }
2290 params[0] = data;
2291 params[3] = offset;
2292 ac_build_intrinsic(&ctx->ac, store_name,
2293 ctx->voidt, params, 6, 0);
2294 }
2295 }
2296
2297 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2298 nir_intrinsic_instr *instr)
2299 {
2300 const char *name;
2301 LLVMValueRef params[6];
2302 int arg_count = 0;
2303 if (ctx->stage == MESA_SHADER_FRAGMENT)
2304 ctx->shader_info->fs.writes_memory = true;
2305
2306 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2307 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2308 }
2309 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2310 params[arg_count++] = get_src(ctx, instr->src[0]);
2311 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2312 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2313 params[arg_count++] = ctx->i1false; /* slc */
2314
2315 switch (instr->intrinsic) {
2316 case nir_intrinsic_ssbo_atomic_add:
2317 name = "llvm.amdgcn.buffer.atomic.add";
2318 break;
2319 case nir_intrinsic_ssbo_atomic_imin:
2320 name = "llvm.amdgcn.buffer.atomic.smin";
2321 break;
2322 case nir_intrinsic_ssbo_atomic_umin:
2323 name = "llvm.amdgcn.buffer.atomic.umin";
2324 break;
2325 case nir_intrinsic_ssbo_atomic_imax:
2326 name = "llvm.amdgcn.buffer.atomic.smax";
2327 break;
2328 case nir_intrinsic_ssbo_atomic_umax:
2329 name = "llvm.amdgcn.buffer.atomic.umax";
2330 break;
2331 case nir_intrinsic_ssbo_atomic_and:
2332 name = "llvm.amdgcn.buffer.atomic.and";
2333 break;
2334 case nir_intrinsic_ssbo_atomic_or:
2335 name = "llvm.amdgcn.buffer.atomic.or";
2336 break;
2337 case nir_intrinsic_ssbo_atomic_xor:
2338 name = "llvm.amdgcn.buffer.atomic.xor";
2339 break;
2340 case nir_intrinsic_ssbo_atomic_exchange:
2341 name = "llvm.amdgcn.buffer.atomic.swap";
2342 break;
2343 case nir_intrinsic_ssbo_atomic_comp_swap:
2344 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2345 break;
2346 default:
2347 abort();
2348 }
2349
2350 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2351 }
2352
2353 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2354 nir_intrinsic_instr *instr)
2355 {
2356 LLVMValueRef results[2];
2357 int load_components;
2358 int num_components = instr->num_components;
2359 if (instr->dest.ssa.bit_size == 64)
2360 num_components *= 2;
2361
2362 for (int i = 0; i < num_components; i += load_components) {
2363 load_components = MIN2(num_components - i, 4);
2364 const char *load_name;
2365 LLVMTypeRef data_type = ctx->f32;
2366 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2367 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2368
2369 if (load_components == 3)
2370 data_type = LLVMVectorType(ctx->f32, 4);
2371 else if (load_components > 1)
2372 data_type = LLVMVectorType(ctx->f32, load_components);
2373
2374 if (load_components >= 3)
2375 load_name = "llvm.amdgcn.buffer.load.v4f32";
2376 else if (load_components == 2)
2377 load_name = "llvm.amdgcn.buffer.load.v2f32";
2378 else if (load_components == 1)
2379 load_name = "llvm.amdgcn.buffer.load.f32";
2380 else
2381 unreachable("unhandled number of components");
2382
2383 LLVMValueRef params[] = {
2384 get_src(ctx, instr->src[0]),
2385 LLVMConstInt(ctx->i32, 0, false),
2386 offset,
2387 ctx->i1false,
2388 ctx->i1false,
2389 };
2390
2391 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2392
2393 }
2394
2395 LLVMValueRef ret = results[0];
2396 if (num_components > 4 || num_components == 3) {
2397 LLVMValueRef masks[] = {
2398 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2399 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2400 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2401 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2402 };
2403
2404 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2405 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2406 results[num_components > 4 ? 1 : 0], swizzle, "");
2407 }
2408
2409 return LLVMBuildBitCast(ctx->builder, ret,
2410 get_def_type(ctx, &instr->dest.ssa), "");
2411 }
2412
2413 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2414 nir_intrinsic_instr *instr)
2415 {
2416 LLVMValueRef results[8], ret;
2417 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2418 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2419 int num_components = instr->num_components;
2420
2421 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2422
2423 if (instr->dest.ssa.bit_size == 64)
2424 num_components *= 2;
2425
2426 for (unsigned i = 0; i < num_components; ++i) {
2427 LLVMValueRef params[] = {
2428 rsrc,
2429 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2430 offset, "")
2431 };
2432 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2433 params, 2,
2434 AC_FUNC_ATTR_READNONE |
2435 AC_FUNC_ATTR_LEGACY);
2436 }
2437
2438
2439 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2440 return LLVMBuildBitCast(ctx->builder, ret,
2441 get_def_type(ctx, &instr->dest.ssa), "");
2442 }
2443
2444 static void
2445 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref_var *deref,
2446 bool vs_in, unsigned *vertex_index_out,
2447 LLVMValueRef *vertex_index_ref,
2448 unsigned *const_out, LLVMValueRef *indir_out)
2449 {
2450 unsigned const_offset = 0;
2451 nir_deref *tail = &deref->deref;
2452 LLVMValueRef offset = NULL;
2453
2454 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2455 tail = tail->child;
2456 nir_deref_array *deref_array = nir_deref_as_array(tail);
2457 if (vertex_index_out)
2458 *vertex_index_out = deref_array->base_offset;
2459
2460 if (vertex_index_ref) {
2461 LLVMValueRef vtx = LLVMConstInt(ctx->i32, deref_array->base_offset, false);
2462 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2463 vtx = LLVMBuildAdd(ctx->builder, vtx, get_src(ctx, deref_array->indirect), "");
2464 }
2465 *vertex_index_ref = vtx;
2466 }
2467 }
2468
2469 if (deref->var->data.compact) {
2470 assert(tail->child->deref_type == nir_deref_type_array);
2471 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2472 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2473 /* We always lower indirect dereferences for "compact" array vars. */
2474 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2475
2476 const_offset = deref_array->base_offset;
2477 goto out;
2478 }
2479
2480 while (tail->child != NULL) {
2481 const struct glsl_type *parent_type = tail->type;
2482 tail = tail->child;
2483
2484 if (tail->deref_type == nir_deref_type_array) {
2485 nir_deref_array *deref_array = nir_deref_as_array(tail);
2486 LLVMValueRef index, stride, local_offset;
2487 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2488
2489 const_offset += size * deref_array->base_offset;
2490 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2491 continue;
2492
2493 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2494 index = get_src(ctx, deref_array->indirect);
2495 stride = LLVMConstInt(ctx->i32, size, 0);
2496 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2497
2498 if (offset)
2499 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2500 else
2501 offset = local_offset;
2502 } else if (tail->deref_type == nir_deref_type_struct) {
2503 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2504
2505 for (unsigned i = 0; i < deref_struct->index; i++) {
2506 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2507 const_offset += glsl_count_attribute_slots(ft, vs_in);
2508 }
2509 } else
2510 unreachable("unsupported deref type");
2511
2512 }
2513 out:
2514 if (const_offset && offset)
2515 offset = LLVMBuildAdd(ctx->builder, offset,
2516 LLVMConstInt(ctx->i32, const_offset, 0),
2517 "");
2518
2519 *const_out = const_offset;
2520 *indir_out = offset;
2521 }
2522
2523 static LLVMValueRef
2524 lds_load(struct nir_to_llvm_context *ctx,
2525 LLVMValueRef dw_addr)
2526 {
2527 LLVMValueRef value;
2528 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2529 return value;
2530 }
2531
2532 static void
2533 lds_store(struct nir_to_llvm_context *ctx,
2534 LLVMValueRef dw_addr, LLVMValueRef value)
2535 {
2536 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2537 ac_build_indexed_store(&ctx->ac, ctx->lds,
2538 dw_addr, value);
2539 }
2540
2541 /* The offchip buffer layout for TCS->TES is
2542 *
2543 * - attribute 0 of patch 0 vertex 0
2544 * - attribute 0 of patch 0 vertex 1
2545 * - attribute 0 of patch 0 vertex 2
2546 * ...
2547 * - attribute 0 of patch 1 vertex 0
2548 * - attribute 0 of patch 1 vertex 1
2549 * ...
2550 * - attribute 1 of patch 0 vertex 0
2551 * - attribute 1 of patch 0 vertex 1
2552 * ...
2553 * - per patch attribute 0 of patch 0
2554 * - per patch attribute 0 of patch 1
2555 * ...
2556 *
2557 * Note that every attribute has 4 components.
2558 */
2559 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2560 LLVMValueRef vertex_index,
2561 LLVMValueRef param_index)
2562 {
2563 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2564 LLVMValueRef param_stride, constant16;
2565 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2566
2567 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2568 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2569 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2570 num_patches, "");
2571
2572 constant16 = LLVMConstInt(ctx->i32, 16, false);
2573 if (vertex_index) {
2574 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2575 vertices_per_patch, "");
2576
2577 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2578 vertex_index, "");
2579
2580 param_stride = total_vertices;
2581 } else {
2582 base_addr = rel_patch_id;
2583 param_stride = num_patches;
2584 }
2585
2586 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2587 LLVMBuildMul(ctx->builder, param_index,
2588 param_stride, ""), "");
2589
2590 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2591
2592 if (!vertex_index) {
2593 LLVMValueRef patch_data_offset =
2594 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2595
2596 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2597 patch_data_offset, "");
2598 }
2599 return base_addr;
2600 }
2601
2602 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2603 unsigned param,
2604 unsigned const_index,
2605 bool is_compact,
2606 LLVMValueRef vertex_index,
2607 LLVMValueRef indir_index)
2608 {
2609 LLVMValueRef param_index;
2610
2611 if (indir_index)
2612 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2613 indir_index, "");
2614 else {
2615 if (const_index && !is_compact)
2616 param += const_index;
2617 param_index = LLVMConstInt(ctx->i32, param, false);
2618 }
2619 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2620 }
2621
2622 static void
2623 mark_tess_output(struct nir_to_llvm_context *ctx,
2624 bool is_patch, uint32_t param)
2625
2626 {
2627 if (is_patch) {
2628 ctx->tess_patch_outputs_written |= (1ull << param);
2629 } else
2630 ctx->tess_outputs_written |= (1ull << param);
2631 }
2632
2633 static LLVMValueRef
2634 get_dw_address(struct nir_to_llvm_context *ctx,
2635 LLVMValueRef dw_addr,
2636 unsigned param,
2637 unsigned const_index,
2638 bool compact_const_index,
2639 LLVMValueRef vertex_index,
2640 LLVMValueRef stride,
2641 LLVMValueRef indir_index)
2642
2643 {
2644
2645 if (vertex_index) {
2646 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2647 LLVMBuildMul(ctx->builder,
2648 vertex_index,
2649 stride, ""), "");
2650 }
2651
2652 if (indir_index)
2653 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2654 LLVMBuildMul(ctx->builder, indir_index,
2655 LLVMConstInt(ctx->i32, 4, false), ""), "");
2656 else if (const_index && !compact_const_index)
2657 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2658 LLVMConstInt(ctx->i32, const_index, false), "");
2659
2660 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2661 LLVMConstInt(ctx->i32, param * 4, false), "");
2662
2663 if (const_index && compact_const_index)
2664 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2665 LLVMConstInt(ctx->i32, const_index, false), "");
2666 return dw_addr;
2667 }
2668
2669 static LLVMValueRef
2670 load_tcs_input(struct nir_to_llvm_context *ctx,
2671 nir_intrinsic_instr *instr)
2672 {
2673 LLVMValueRef dw_addr, stride;
2674 unsigned const_index;
2675 LLVMValueRef vertex_index;
2676 LLVMValueRef indir_index;
2677 unsigned param;
2678 LLVMValueRef value[4], result;
2679 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2680 const bool is_compact = instr->variables[0]->var->data.compact;
2681 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2682 radv_get_deref_offset(ctx, instr->variables[0],
2683 false, NULL, per_vertex ? &vertex_index : NULL,
2684 &const_index, &indir_index);
2685
2686 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2687 dw_addr = get_tcs_in_current_patch_offset(ctx);
2688 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2689 indir_index);
2690
2691 for (unsigned i = 0; i < instr->num_components; i++) {
2692 value[i] = lds_load(ctx, dw_addr);
2693 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2694 ctx->i32one, "");
2695 }
2696 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2697 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2698 return result;
2699 }
2700
2701 static LLVMValueRef
2702 load_tcs_output(struct nir_to_llvm_context *ctx,
2703 nir_intrinsic_instr *instr)
2704 {
2705 LLVMValueRef dw_addr, stride;
2706 LLVMValueRef value[4], result;
2707 LLVMValueRef vertex_index = NULL;
2708 LLVMValueRef indir_index = NULL;
2709 unsigned const_index = 0;
2710 unsigned param;
2711 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2712 const bool is_compact = instr->variables[0]->var->data.compact;
2713 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2714 radv_get_deref_offset(ctx, instr->variables[0],
2715 false, NULL, per_vertex ? &vertex_index : NULL,
2716 &const_index, &indir_index);
2717
2718 if (!instr->variables[0]->var->data.patch) {
2719 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2720 dw_addr = get_tcs_out_current_patch_offset(ctx);
2721 } else {
2722 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2723 }
2724
2725 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2726 indir_index);
2727
2728 for (unsigned i = 0; i < instr->num_components; i++) {
2729 value[i] = lds_load(ctx, dw_addr);
2730 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2731 ctx->i32one, "");
2732 }
2733 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2734 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2735 return result;
2736 }
2737
2738 static void
2739 store_tcs_output(struct nir_to_llvm_context *ctx,
2740 nir_intrinsic_instr *instr,
2741 LLVMValueRef src,
2742 unsigned writemask)
2743 {
2744 LLVMValueRef stride, dw_addr;
2745 LLVMValueRef buf_addr = NULL;
2746 LLVMValueRef vertex_index = NULL;
2747 LLVMValueRef indir_index = NULL;
2748 unsigned const_index = 0;
2749 unsigned param;
2750 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2751 const bool is_compact = instr->variables[0]->var->data.compact;
2752
2753 radv_get_deref_offset(ctx, instr->variables[0],
2754 false, NULL, per_vertex ? &vertex_index : NULL,
2755 &const_index, &indir_index);
2756
2757 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2758 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2759 is_compact && const_index > 3) {
2760 const_index -= 3;
2761 param++;
2762 }
2763
2764 if (!instr->variables[0]->var->data.patch) {
2765 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2766 dw_addr = get_tcs_out_current_patch_offset(ctx);
2767 } else {
2768 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2769 }
2770
2771 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2772
2773 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2774 indir_index);
2775 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2776 vertex_index, indir_index);
2777
2778 unsigned base = is_compact ? const_index : 0;
2779 for (unsigned chan = 0; chan < 8; chan++) {
2780 bool is_tess_factor = false;
2781 if (!(writemask & (1 << chan)))
2782 continue;
2783 LLVMValueRef value = llvm_extract_elem(ctx, src, chan);
2784
2785 lds_store(ctx, dw_addr, value);
2786
2787 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2788 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2789 is_tess_factor = true;
2790
2791 if (!is_tess_factor && writemask != 0xF)
2792 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2793 buf_addr, ctx->oc_lds,
2794 4 * (base + chan), 1, 0, true, false);
2795
2796 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2797 ctx->i32one, "");
2798 }
2799
2800 if (writemask == 0xF) {
2801 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2802 buf_addr, ctx->oc_lds,
2803 (base * 4), 1, 0, true, false);
2804 }
2805 }
2806
2807 static LLVMValueRef
2808 load_tes_input(struct nir_to_llvm_context *ctx,
2809 nir_intrinsic_instr *instr)
2810 {
2811 LLVMValueRef buf_addr;
2812 LLVMValueRef result;
2813 LLVMValueRef vertex_index = NULL;
2814 LLVMValueRef indir_index = NULL;
2815 unsigned const_index = 0;
2816 unsigned param;
2817 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2818 const bool is_compact = instr->variables[0]->var->data.compact;
2819
2820 radv_get_deref_offset(ctx, instr->variables[0],
2821 false, NULL, per_vertex ? &vertex_index : NULL,
2822 &const_index, &indir_index);
2823 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2824 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2825 is_compact && const_index > 3) {
2826 const_index -= 3;
2827 param++;
2828 }
2829 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2830 is_compact, vertex_index, indir_index);
2831
2832 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2833 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2834 result = trim_vector(ctx, result, instr->num_components);
2835 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2836 return result;
2837 }
2838
2839 static LLVMValueRef
2840 load_gs_input(struct nir_to_llvm_context *ctx,
2841 nir_intrinsic_instr *instr)
2842 {
2843 LLVMValueRef indir_index, vtx_offset;
2844 unsigned const_index;
2845 LLVMValueRef args[9];
2846 unsigned param, vtx_offset_param;
2847 LLVMValueRef value[4], result;
2848 unsigned vertex_index;
2849 radv_get_deref_offset(ctx, instr->variables[0],
2850 false, &vertex_index, NULL,
2851 &const_index, &indir_index);
2852 vtx_offset_param = vertex_index;
2853 assert(vtx_offset_param < 6);
2854 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2855 LLVMConstInt(ctx->i32, 4, false), "");
2856
2857 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2858 for (unsigned i = 0; i < instr->num_components; i++) {
2859
2860 args[0] = ctx->esgs_ring;
2861 args[1] = vtx_offset;
2862 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2863 args[3] = ctx->i32zero;
2864 args[4] = ctx->i32one; /* OFFEN */
2865 args[5] = ctx->i32zero; /* IDXEN */
2866 args[6] = ctx->i32one; /* GLC */
2867 args[7] = ctx->i32zero; /* SLC */
2868 args[8] = ctx->i32zero; /* TFE */
2869
2870 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2871 ctx->i32, args, 9,
2872 AC_FUNC_ATTR_READONLY |
2873 AC_FUNC_ATTR_LEGACY);
2874 }
2875 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2876
2877 return result;
2878 }
2879
2880 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2881 nir_intrinsic_instr *instr)
2882 {
2883 LLVMValueRef values[8];
2884 int idx = instr->variables[0]->var->data.driver_location;
2885 int ve = instr->dest.ssa.num_components;
2886 LLVMValueRef indir_index;
2887 LLVMValueRef ret;
2888 unsigned const_index;
2889 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2890 instr->variables[0]->var->data.mode == nir_var_shader_in;
2891 radv_get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2892 &const_index, &indir_index);
2893
2894 if (instr->dest.ssa.bit_size == 64)
2895 ve *= 2;
2896
2897 switch (instr->variables[0]->var->data.mode) {
2898 case nir_var_shader_in:
2899 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2900 return load_tcs_input(ctx, instr);
2901 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2902 return load_tes_input(ctx, instr);
2903 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2904 return load_gs_input(ctx, instr);
2905 }
2906 for (unsigned chan = 0; chan < ve; chan++) {
2907 if (indir_index) {
2908 unsigned count = glsl_count_attribute_slots(
2909 instr->variables[0]->var->type,
2910 ctx->stage == MESA_SHADER_VERTEX);
2911 count -= chan / 4;
2912 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2913 &ctx->ac, ctx->inputs + idx + chan, count,
2914 4, false);
2915
2916 values[chan] = LLVMBuildExtractElement(ctx->builder,
2917 tmp_vec,
2918 indir_index, "");
2919 } else
2920 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2921 }
2922 break;
2923 case nir_var_local:
2924 for (unsigned chan = 0; chan < ve; chan++) {
2925 if (indir_index) {
2926 unsigned count = glsl_count_attribute_slots(
2927 instr->variables[0]->var->type, false);
2928 count -= chan / 4;
2929 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2930 &ctx->ac, ctx->locals + idx + chan, count,
2931 4, true);
2932
2933 values[chan] = LLVMBuildExtractElement(ctx->builder,
2934 tmp_vec,
2935 indir_index, "");
2936 } else {
2937 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2938 }
2939 }
2940 break;
2941 case nir_var_shader_out:
2942 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2943 return load_tcs_output(ctx, instr);
2944 for (unsigned chan = 0; chan < ve; chan++) {
2945 if (indir_index) {
2946 unsigned count = glsl_count_attribute_slots(
2947 instr->variables[0]->var->type, false);
2948 count -= chan / 4;
2949 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2950 &ctx->ac, ctx->outputs + idx + chan, count,
2951 4, true);
2952
2953 values[chan] = LLVMBuildExtractElement(ctx->builder,
2954 tmp_vec,
2955 indir_index, "");
2956 } else {
2957 values[chan] = LLVMBuildLoad(ctx->builder,
2958 ctx->outputs[idx + chan + const_index * 4],
2959 "");
2960 }
2961 }
2962 break;
2963 case nir_var_shared: {
2964 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2965 LLVMValueRef derived_ptr;
2966
2967 if (indir_index)
2968 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2969
2970 for (unsigned chan = 0; chan < ve; chan++) {
2971 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2972 if (indir_index)
2973 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2974 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2975
2976 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2977 }
2978 break;
2979 }
2980 default:
2981 unreachable("unhandle variable mode");
2982 }
2983 ret = ac_build_gather_values(&ctx->ac, values, ve);
2984 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2985 }
2986
2987 static void
2988 visit_store_var(struct nir_to_llvm_context *ctx,
2989 nir_intrinsic_instr *instr)
2990 {
2991 LLVMValueRef temp_ptr, value;
2992 int idx = instr->variables[0]->var->data.driver_location;
2993 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2994 int writemask = instr->const_index[0];
2995 LLVMValueRef indir_index;
2996 unsigned const_index;
2997 radv_get_deref_offset(ctx, instr->variables[0], false,
2998 NULL, NULL, &const_index, &indir_index);
2999
3000 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
3001 int old_writemask = writemask;
3002
3003 src = LLVMBuildBitCast(ctx->builder, src,
3004 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
3005 "");
3006
3007 writemask = 0;
3008 for (unsigned chan = 0; chan < 4; chan++) {
3009 if (old_writemask & (1 << chan))
3010 writemask |= 3u << (2 * chan);
3011 }
3012 }
3013
3014 switch (instr->variables[0]->var->data.mode) {
3015 case nir_var_shader_out:
3016
3017 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3018 store_tcs_output(ctx, instr, src, writemask);
3019 return;
3020 }
3021
3022 for (unsigned chan = 0; chan < 8; chan++) {
3023 int stride = 4;
3024 if (!(writemask & (1 << chan)))
3025 continue;
3026
3027 value = llvm_extract_elem(ctx, src, chan);
3028
3029 if (instr->variables[0]->var->data.compact)
3030 stride = 1;
3031 if (indir_index) {
3032 unsigned count = glsl_count_attribute_slots(
3033 instr->variables[0]->var->type, false);
3034 count -= chan / 4;
3035 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3036 &ctx->ac, ctx->outputs + idx + chan, count,
3037 stride, true);
3038
3039 if (get_llvm_num_components(tmp_vec) > 1) {
3040 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3041 value, indir_index, "");
3042 } else
3043 tmp_vec = value;
3044 build_store_values_extended(ctx, ctx->outputs + idx + chan,
3045 count, stride, tmp_vec);
3046
3047 } else {
3048 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3049
3050 LLVMBuildStore(ctx->builder, value, temp_ptr);
3051 }
3052 }
3053 break;
3054 case nir_var_local:
3055 for (unsigned chan = 0; chan < 8; chan++) {
3056 if (!(writemask & (1 << chan)))
3057 continue;
3058
3059 value = llvm_extract_elem(ctx, src, chan);
3060 if (indir_index) {
3061 unsigned count = glsl_count_attribute_slots(
3062 instr->variables[0]->var->type, false);
3063 count -= chan / 4;
3064 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3065 &ctx->ac, ctx->locals + idx + chan, count,
3066 4, true);
3067
3068 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3069 value, indir_index, "");
3070 build_store_values_extended(ctx, ctx->locals + idx + chan,
3071 count, 4, tmp_vec);
3072 } else {
3073 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3074
3075 LLVMBuildStore(ctx->builder, value, temp_ptr);
3076 }
3077 }
3078 break;
3079 case nir_var_shared: {
3080 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3081
3082 if (indir_index)
3083 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
3084
3085 for (unsigned chan = 0; chan < 8; chan++) {
3086 if (!(writemask & (1 << chan)))
3087 continue;
3088 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
3089 LLVMValueRef derived_ptr;
3090
3091 if (indir_index)
3092 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
3093
3094 value = llvm_extract_elem(ctx, src, chan);
3095 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
3096 LLVMBuildStore(ctx->builder,
3097 to_integer(ctx, value), derived_ptr);
3098 }
3099 break;
3100 }
3101 default:
3102 break;
3103 }
3104 }
3105
3106 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3107 {
3108 switch (dim) {
3109 case GLSL_SAMPLER_DIM_BUF:
3110 return 1;
3111 case GLSL_SAMPLER_DIM_1D:
3112 return array ? 2 : 1;
3113 case GLSL_SAMPLER_DIM_2D:
3114 return array ? 3 : 2;
3115 case GLSL_SAMPLER_DIM_MS:
3116 return array ? 4 : 3;
3117 case GLSL_SAMPLER_DIM_3D:
3118 case GLSL_SAMPLER_DIM_CUBE:
3119 return 3;
3120 case GLSL_SAMPLER_DIM_RECT:
3121 case GLSL_SAMPLER_DIM_SUBPASS:
3122 return 2;
3123 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3124 return 3;
3125 default:
3126 break;
3127 }
3128 return 0;
3129 }
3130
3131
3132
3133 /* Adjust the sample index according to FMASK.
3134 *
3135 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3136 * which is the identity mapping. Each nibble says which physical sample
3137 * should be fetched to get that sample.
3138 *
3139 * For example, 0x11111100 means there are only 2 samples stored and
3140 * the second sample covers 3/4 of the pixel. When reading samples 0
3141 * and 1, return physical sample 0 (determined by the first two 0s
3142 * in FMASK), otherwise return physical sample 1.
3143 *
3144 * The sample index should be adjusted as follows:
3145 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3146 */
3147 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
3148 LLVMValueRef coord_x, LLVMValueRef coord_y,
3149 LLVMValueRef coord_z,
3150 LLVMValueRef sample_index,
3151 LLVMValueRef fmask_desc_ptr)
3152 {
3153 LLVMValueRef fmask_load_address[4];
3154 LLVMValueRef res;
3155
3156 fmask_load_address[0] = coord_x;
3157 fmask_load_address[1] = coord_y;
3158 if (coord_z) {
3159 fmask_load_address[2] = coord_z;
3160 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3161 }
3162
3163 struct ac_image_args args = {0};
3164
3165 args.opcode = ac_image_load;
3166 args.da = coord_z ? true : false;
3167 args.resource = fmask_desc_ptr;
3168 args.dmask = 0xf;
3169 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
3170
3171 res = ac_build_image_opcode(&ctx->ac, &args);
3172
3173 res = to_integer(ctx, res);
3174 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3175 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3176
3177 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3178 res,
3179 ctx->i32zero, "");
3180
3181 LLVMValueRef sample_index4 =
3182 LLVMBuildMul(ctx->builder, sample_index, four, "");
3183 LLVMValueRef shifted_fmask =
3184 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3185 LLVMValueRef final_sample =
3186 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3187
3188 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3189 * resource descriptor is 0 (invalid),
3190 */
3191 LLVMValueRef fmask_desc =
3192 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3193 ctx->v8i32, "");
3194
3195 LLVMValueRef fmask_word1 =
3196 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3197 ctx->i32one, "");
3198
3199 LLVMValueRef word1_is_nonzero =
3200 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3201 fmask_word1, ctx->i32zero, "");
3202
3203 /* Replace the MSAA sample index. */
3204 sample_index =
3205 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3206 final_sample, sample_index, "");
3207 return sample_index;
3208 }
3209
3210 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
3211 nir_intrinsic_instr *instr)
3212 {
3213 const struct glsl_type *type = instr->variables[0]->var->type;
3214 if(instr->variables[0]->deref.child)
3215 type = instr->variables[0]->deref.child->type;
3216
3217 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3218 LLVMValueRef coords[4];
3219 LLVMValueRef masks[] = {
3220 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
3221 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
3222 };
3223 LLVMValueRef res;
3224 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
3225
3226 int count;
3227 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3228 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3229 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3230 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3231 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3232
3233 count = image_type_to_components_count(dim,
3234 glsl_sampler_type_is_array(type));
3235
3236 if (is_ms) {
3237 LLVMValueRef fmask_load_address[3];
3238 int chan;
3239
3240 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3241 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
3242 if (glsl_sampler_type_is_array(type))
3243 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
3244 else
3245 fmask_load_address[2] = NULL;
3246 if (add_frag_pos) {
3247 for (chan = 0; chan < 2; ++chan)
3248 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3249 }
3250 sample_index = adjust_sample_index_using_fmask(ctx,
3251 fmask_load_address[0],
3252 fmask_load_address[1],
3253 fmask_load_address[2],
3254 sample_index,
3255 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
3256 }
3257 if (count == 1) {
3258 if (instr->src[0].ssa->num_components)
3259 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3260 else
3261 res = src0;
3262 } else {
3263 int chan;
3264 if (is_ms)
3265 count--;
3266 for (chan = 0; chan < count; ++chan) {
3267 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
3268 }
3269
3270 if (add_frag_pos) {
3271 for (chan = 0; chan < count; ++chan)
3272 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3273 }
3274 if (is_ms) {
3275 coords[count] = sample_index;
3276 count++;
3277 }
3278
3279 if (count == 3) {
3280 coords[3] = LLVMGetUndef(ctx->i32);
3281 count = 4;
3282 }
3283 res = ac_build_gather_values(&ctx->ac, coords, count);
3284 }
3285 return res;
3286 }
3287
3288 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
3289 nir_intrinsic_instr *instr)
3290 {
3291 LLVMValueRef params[7];
3292 LLVMValueRef res;
3293 char intrinsic_name[64];
3294 const nir_variable *var = instr->variables[0]->var;
3295 const struct glsl_type *type = var->type;
3296 if(instr->variables[0]->deref.child)
3297 type = instr->variables[0]->deref.child->type;
3298
3299 type = glsl_without_array(type);
3300 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3301 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3302 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3303 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3304 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3305 params[3] = ctx->i1false; /* glc */
3306 params[4] = ctx->i1false; /* slc */
3307 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
3308 params, 5, 0);
3309
3310 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
3311 res = to_integer(ctx, res);
3312 } else {
3313 bool is_da = glsl_sampler_type_is_array(type) ||
3314 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3315 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3316 LLVMValueRef glc = ctx->i1false;
3317 LLVMValueRef slc = ctx->i1false;
3318
3319 params[0] = get_image_coords(ctx, instr);
3320 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3321 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3322 if (HAVE_LLVM <= 0x0309) {
3323 params[3] = ctx->i1false; /* r128 */
3324 params[4] = da;
3325 params[5] = glc;
3326 params[6] = slc;
3327 } else {
3328 LLVMValueRef lwe = ctx->i1false;
3329 params[3] = glc;
3330 params[4] = slc;
3331 params[5] = lwe;
3332 params[6] = da;
3333 }
3334
3335 ac_get_image_intr_name("llvm.amdgcn.image.load",
3336 ctx->v4f32, /* vdata */
3337 LLVMTypeOf(params[0]), /* coords */
3338 LLVMTypeOf(params[1]), /* rsrc */
3339 intrinsic_name, sizeof(intrinsic_name));
3340
3341 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
3342 params, 7, AC_FUNC_ATTR_READONLY);
3343 }
3344 return to_integer(ctx, res);
3345 }
3346
3347 static void visit_image_store(struct nir_to_llvm_context *ctx,
3348 nir_intrinsic_instr *instr)
3349 {
3350 LLVMValueRef params[8];
3351 char intrinsic_name[64];
3352 const nir_variable *var = instr->variables[0]->var;
3353 const struct glsl_type *type = glsl_without_array(var->type);
3354
3355 if (ctx->stage == MESA_SHADER_FRAGMENT)
3356 ctx->shader_info->fs.writes_memory = true;
3357
3358 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3359 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
3360 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3361 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3362 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3363 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3364 params[4] = ctx->i1false; /* glc */
3365 params[5] = ctx->i1false; /* slc */
3366 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
3367 params, 6, 0);
3368 } else {
3369 bool is_da = glsl_sampler_type_is_array(type) ||
3370 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3371 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3372 LLVMValueRef glc = ctx->i1false;
3373 LLVMValueRef slc = ctx->i1false;
3374
3375 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
3376 params[1] = get_image_coords(ctx, instr); /* coords */
3377 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3378 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3379 if (HAVE_LLVM <= 0x0309) {
3380 params[4] = ctx->i1false; /* r128 */
3381 params[5] = da;
3382 params[6] = glc;
3383 params[7] = slc;
3384 } else {
3385 LLVMValueRef lwe = ctx->i1false;
3386 params[4] = glc;
3387 params[5] = slc;
3388 params[6] = lwe;
3389 params[7] = da;
3390 }
3391
3392 ac_get_image_intr_name("llvm.amdgcn.image.store",
3393 LLVMTypeOf(params[0]), /* vdata */
3394 LLVMTypeOf(params[1]), /* coords */
3395 LLVMTypeOf(params[2]), /* rsrc */
3396 intrinsic_name, sizeof(intrinsic_name));
3397
3398 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
3399 params, 8, 0);
3400 }
3401
3402 }
3403
3404 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
3405 nir_intrinsic_instr *instr)
3406 {
3407 LLVMValueRef params[6];
3408 int param_count = 0;
3409 const nir_variable *var = instr->variables[0]->var;
3410
3411 const char *base_name = "llvm.amdgcn.image.atomic";
3412 const char *atomic_name;
3413 LLVMValueRef coords;
3414 char intrinsic_name[32], coords_type[8];
3415 const struct glsl_type *type = glsl_without_array(var->type);
3416
3417 if (ctx->stage == MESA_SHADER_FRAGMENT)
3418 ctx->shader_info->fs.writes_memory = true;
3419
3420 params[param_count++] = get_src(ctx, instr->src[2]);
3421 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3422 params[param_count++] = get_src(ctx, instr->src[3]);
3423
3424 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3425 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3426 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3427 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3428 params[param_count++] = ctx->i32zero; /* voffset */
3429 params[param_count++] = ctx->i1false; /* glc */
3430 params[param_count++] = ctx->i1false; /* slc */
3431 } else {
3432 bool da = glsl_sampler_type_is_array(type) ||
3433 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3434
3435 coords = params[param_count++] = get_image_coords(ctx, instr);
3436 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3437 params[param_count++] = ctx->i1false; /* r128 */
3438 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
3439 params[param_count++] = ctx->i1false; /* slc */
3440 }
3441
3442 switch (instr->intrinsic) {
3443 case nir_intrinsic_image_atomic_add:
3444 atomic_name = "add";
3445 break;
3446 case nir_intrinsic_image_atomic_min:
3447 atomic_name = "smin";
3448 break;
3449 case nir_intrinsic_image_atomic_max:
3450 atomic_name = "smax";
3451 break;
3452 case nir_intrinsic_image_atomic_and:
3453 atomic_name = "and";
3454 break;
3455 case nir_intrinsic_image_atomic_or:
3456 atomic_name = "or";
3457 break;
3458 case nir_intrinsic_image_atomic_xor:
3459 atomic_name = "xor";
3460 break;
3461 case nir_intrinsic_image_atomic_exchange:
3462 atomic_name = "swap";
3463 break;
3464 case nir_intrinsic_image_atomic_comp_swap:
3465 atomic_name = "cmpswap";
3466 break;
3467 default:
3468 abort();
3469 }
3470 build_int_type_name(LLVMTypeOf(coords),
3471 coords_type, sizeof(coords_type));
3472
3473 snprintf(intrinsic_name, sizeof(intrinsic_name),
3474 "%s.%s.%s", base_name, atomic_name, coords_type);
3475 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
3476 }
3477
3478 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
3479 nir_intrinsic_instr *instr)
3480 {
3481 LLVMValueRef res;
3482 const nir_variable *var = instr->variables[0]->var;
3483 const struct glsl_type *type = instr->variables[0]->var->type;
3484 bool da = glsl_sampler_type_is_array(var->type) ||
3485 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3486 if(instr->variables[0]->deref.child)
3487 type = instr->variables[0]->deref.child->type;
3488
3489 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3490 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
3491
3492 struct ac_image_args args = { 0 };
3493
3494 args.da = da;
3495 args.dmask = 0xf;
3496 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3497 args.opcode = ac_image_get_resinfo;
3498 args.addr = ctx->i32zero;
3499
3500 res = ac_build_image_opcode(&ctx->ac, &args);
3501
3502 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3503 glsl_sampler_type_is_array(type)) {
3504 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3505 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3506 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
3507 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3508 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
3509 }
3510 return res;
3511 }
3512
3513 #define NOOP_WAITCNT 0xf7f
3514 #define LGKM_CNT 0x07f
3515 #define VM_CNT 0xf70
3516
3517 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3518 unsigned simm16)
3519 {
3520 LLVMValueRef args[1] = {
3521 LLVMConstInt(ctx->i32, simm16, false),
3522 };
3523 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3524 ctx->voidt, args, 1, 0);
3525 }
3526
3527 static void emit_barrier(struct nir_to_llvm_context *ctx)
3528 {
3529 /* SI only (thanks to a hw bug workaround):
3530 * The real barrier instruction isn’t needed, because an entire patch
3531 * always fits into a single wave.
3532 */
3533 if (ctx->options->chip_class == SI &&
3534 ctx->stage == MESA_SHADER_TESS_CTRL) {
3535 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3536 return;
3537 }
3538 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3539 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3540 }
3541
3542 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3543 nir_intrinsic_instr *instr)
3544 {
3545 LLVMValueRef cond;
3546 ctx->shader_info->fs.can_discard = true;
3547
3548 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3549 get_src(ctx, instr->src[0]),
3550 ctx->i32zero, "");
3551
3552 cond = LLVMBuildSelect(ctx->builder, cond,
3553 LLVMConstReal(ctx->f32, -1.0f),
3554 ctx->f32zero, "");
3555 ac_build_kill(&ctx->ac, cond);
3556 }
3557
3558 static LLVMValueRef
3559 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3560 {
3561 LLVMValueRef result;
3562 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3563 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3564 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3565
3566 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3567 }
3568
3569 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3570 nir_intrinsic_instr *instr)
3571 {
3572 LLVMValueRef ptr, result;
3573 int idx = instr->variables[0]->var->data.driver_location;
3574 LLVMValueRef src = get_src(ctx, instr->src[0]);
3575 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3576
3577 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3578 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3579 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3580 ptr, src, src1,
3581 LLVMAtomicOrderingSequentiallyConsistent,
3582 LLVMAtomicOrderingSequentiallyConsistent,
3583 false);
3584 } else {
3585 LLVMAtomicRMWBinOp op;
3586 switch (instr->intrinsic) {
3587 case nir_intrinsic_var_atomic_add:
3588 op = LLVMAtomicRMWBinOpAdd;
3589 break;
3590 case nir_intrinsic_var_atomic_umin:
3591 op = LLVMAtomicRMWBinOpUMin;
3592 break;
3593 case nir_intrinsic_var_atomic_umax:
3594 op = LLVMAtomicRMWBinOpUMax;
3595 break;
3596 case nir_intrinsic_var_atomic_imin:
3597 op = LLVMAtomicRMWBinOpMin;
3598 break;
3599 case nir_intrinsic_var_atomic_imax:
3600 op = LLVMAtomicRMWBinOpMax;
3601 break;
3602 case nir_intrinsic_var_atomic_and:
3603 op = LLVMAtomicRMWBinOpAnd;
3604 break;
3605 case nir_intrinsic_var_atomic_or:
3606 op = LLVMAtomicRMWBinOpOr;
3607 break;
3608 case nir_intrinsic_var_atomic_xor:
3609 op = LLVMAtomicRMWBinOpXor;
3610 break;
3611 case nir_intrinsic_var_atomic_exchange:
3612 op = LLVMAtomicRMWBinOpXchg;
3613 break;
3614 default:
3615 return NULL;
3616 }
3617
3618 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
3619 LLVMAtomicOrderingSequentiallyConsistent,
3620 false);
3621 }
3622 return result;
3623 }
3624
3625 #define INTERP_CENTER 0
3626 #define INTERP_CENTROID 1
3627 #define INTERP_SAMPLE 2
3628
3629 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3630 enum glsl_interp_mode interp, unsigned location)
3631 {
3632 switch (interp) {
3633 case INTERP_MODE_FLAT:
3634 default:
3635 return NULL;
3636 case INTERP_MODE_SMOOTH:
3637 case INTERP_MODE_NONE:
3638 if (location == INTERP_CENTER)
3639 return ctx->persp_center;
3640 else if (location == INTERP_CENTROID)
3641 return ctx->persp_centroid;
3642 else if (location == INTERP_SAMPLE)
3643 return ctx->persp_sample;
3644 break;
3645 case INTERP_MODE_NOPERSPECTIVE:
3646 if (location == INTERP_CENTER)
3647 return ctx->linear_center;
3648 else if (location == INTERP_CENTROID)
3649 return ctx->linear_centroid;
3650 else if (location == INTERP_SAMPLE)
3651 return ctx->linear_sample;
3652 break;
3653 }
3654 return NULL;
3655 }
3656
3657 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3658 LLVMValueRef sample_id)
3659 {
3660 LLVMValueRef result;
3661 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3662
3663 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3664 const_array(ctx->v2f32, 64), "");
3665
3666 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3667 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3668
3669 return result;
3670 }
3671
3672 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3673 {
3674 LLVMValueRef values[2];
3675
3676 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
3677 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
3678 return ac_build_gather_values(&ctx->ac, values, 2);
3679 }
3680
3681 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3682 nir_intrinsic_instr *instr)
3683 {
3684 LLVMValueRef result[2];
3685 LLVMValueRef interp_param, attr_number;
3686 unsigned location;
3687 unsigned chan;
3688 LLVMValueRef src_c0, src_c1;
3689 LLVMValueRef src0;
3690 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3691 switch (instr->intrinsic) {
3692 case nir_intrinsic_interp_var_at_centroid:
3693 location = INTERP_CENTROID;
3694 break;
3695 case nir_intrinsic_interp_var_at_sample:
3696 case nir_intrinsic_interp_var_at_offset:
3697 location = INTERP_CENTER;
3698 src0 = get_src(ctx, instr->src[0]);
3699 break;
3700 default:
3701 break;
3702 }
3703
3704 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3705 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3706 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3707 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3708 LLVMValueRef sample_position;
3709 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3710
3711 /* fetch sample ID */
3712 sample_position = load_sample_position(ctx, src0);
3713
3714 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3715 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3716 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3717 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3718 }
3719 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3720 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3721
3722 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3723 LLVMValueRef ij_out[2];
3724 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3725
3726 /*
3727 * take the I then J parameters, and the DDX/Y for it, and
3728 * calculate the IJ inputs for the interpolator.
3729 * temp1 = ddx * offset/sample.x + I;
3730 * interp_param.I = ddy * offset/sample.y + temp1;
3731 * temp1 = ddx * offset/sample.x + J;
3732 * interp_param.J = ddy * offset/sample.y + temp1;
3733 */
3734 for (unsigned i = 0; i < 2; i++) {
3735 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3736 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3737 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3738 ddxy_out, ix_ll, "");
3739 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3740 ddxy_out, iy_ll, "");
3741 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3742 interp_param, ix_ll, "");
3743 LLVMValueRef temp1, temp2;
3744
3745 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3746 ctx->f32, "");
3747
3748 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3749 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3750
3751 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3752 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3753
3754 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3755 temp2, ctx->i32, "");
3756 }
3757 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3758
3759 }
3760
3761 for (chan = 0; chan < 2; chan++) {
3762 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3763
3764 if (interp_param) {
3765 interp_param = LLVMBuildBitCast(ctx->builder,
3766 interp_param, LLVMVectorType(ctx->f32, 2), "");
3767 LLVMValueRef i = LLVMBuildExtractElement(
3768 ctx->builder, interp_param, ctx->i32zero, "");
3769 LLVMValueRef j = LLVMBuildExtractElement(
3770 ctx->builder, interp_param, ctx->i32one, "");
3771
3772 result[chan] = ac_build_fs_interp(&ctx->ac,
3773 llvm_chan, attr_number,
3774 ctx->prim_mask, i, j);
3775 } else {
3776 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3777 LLVMConstInt(ctx->i32, 2, false),
3778 llvm_chan, attr_number,
3779 ctx->prim_mask);
3780 }
3781 }
3782 return ac_build_gather_values(&ctx->ac, result, 2);
3783 }
3784
3785 static void
3786 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3787 nir_intrinsic_instr *instr)
3788 {
3789 LLVMValueRef gs_next_vertex;
3790 LLVMValueRef can_emit, kill;
3791 int idx;
3792
3793 assert(instr->const_index[0] == 0);
3794 /* Write vertex attribute values to GSVS ring */
3795 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3796 ctx->gs_next_vertex,
3797 "");
3798
3799 /* If this thread has already emitted the declared maximum number of
3800 * vertices, kill it: excessive vertex emissions are not supposed to
3801 * have any effect, and GS threads have no externally observable
3802 * effects other than emitting vertices.
3803 */
3804 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3805 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3806
3807 kill = LLVMBuildSelect(ctx->builder, can_emit,
3808 LLVMConstReal(ctx->f32, 1.0f),
3809 LLVMConstReal(ctx->f32, -1.0f), "");
3810 ac_build_kill(&ctx->ac, kill);
3811
3812 /* loop num outputs */
3813 idx = 0;
3814 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3815 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3816 int length = 4;
3817 int slot = idx;
3818 int slot_inc = 1;
3819
3820 if (!(ctx->output_mask & (1ull << i)))
3821 continue;
3822
3823 if (i == VARYING_SLOT_CLIP_DIST0) {
3824 /* pack clip and cull into a single set of slots */
3825 length = ctx->num_output_clips + ctx->num_output_culls;
3826 if (length > 4)
3827 slot_inc = 2;
3828 }
3829 for (unsigned j = 0; j < length; j++) {
3830 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3831 out_ptr[j], "");
3832 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3833 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3834 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3835
3836 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3837
3838 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3839 out_val, 1,
3840 voffset, ctx->gs2vs_offset, 0,
3841 1, 1, true, true);
3842 }
3843 idx += slot_inc;
3844 }
3845
3846 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3847 ctx->i32one, "");
3848 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3849
3850 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3851 }
3852
3853 static void
3854 visit_end_primitive(struct nir_to_llvm_context *ctx,
3855 nir_intrinsic_instr *instr)
3856 {
3857 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3858 }
3859
3860 static LLVMValueRef
3861 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3862 nir_intrinsic_instr *instr)
3863 {
3864 LLVMValueRef coord[4] = {
3865 ctx->tes_u,
3866 ctx->tes_v,
3867 ctx->f32zero,
3868 ctx->f32zero,
3869 };
3870
3871 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3872 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3873 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3874
3875 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3876 return LLVMBuildBitCast(ctx->builder, result,
3877 get_def_type(ctx, &instr->dest.ssa), "");
3878 }
3879
3880 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3881 nir_intrinsic_instr *instr)
3882 {
3883 LLVMValueRef result = NULL;
3884
3885 switch (instr->intrinsic) {
3886 case nir_intrinsic_load_work_group_id: {
3887 result = ctx->workgroup_ids;
3888 break;
3889 }
3890 case nir_intrinsic_load_base_vertex: {
3891 result = ctx->base_vertex;
3892 break;
3893 }
3894 case nir_intrinsic_load_vertex_id_zero_base: {
3895 result = ctx->vertex_id;
3896 break;
3897 }
3898 case nir_intrinsic_load_local_invocation_id: {
3899 result = ctx->local_invocation_ids;
3900 break;
3901 }
3902 case nir_intrinsic_load_base_instance:
3903 result = ctx->start_instance;
3904 break;
3905 case nir_intrinsic_load_draw_id:
3906 result = ctx->draw_index;
3907 break;
3908 case nir_intrinsic_load_invocation_id:
3909 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3910 result = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
3911 else
3912 result = ctx->gs_invocation_id;
3913 break;
3914 case nir_intrinsic_load_primitive_id:
3915 if (ctx->stage == MESA_SHADER_GEOMETRY)
3916 result = ctx->gs_prim_id;
3917 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
3918 result = ctx->tcs_patch_id;
3919 else if (ctx->stage == MESA_SHADER_TESS_EVAL)
3920 result = ctx->tes_patch_id;
3921 else
3922 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3923 break;
3924 case nir_intrinsic_load_sample_id:
3925 ctx->shader_info->fs.force_persample = true;
3926 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3927 break;
3928 case nir_intrinsic_load_sample_pos:
3929 ctx->shader_info->fs.force_persample = true;
3930 result = load_sample_pos(ctx);
3931 break;
3932 case nir_intrinsic_load_sample_mask_in:
3933 result = ctx->sample_coverage;
3934 break;
3935 case nir_intrinsic_load_front_face:
3936 result = ctx->front_face;
3937 break;
3938 case nir_intrinsic_load_instance_id:
3939 result = ctx->instance_id;
3940 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3941 ctx->shader_info->vs.vgpr_comp_cnt);
3942 break;
3943 case nir_intrinsic_load_num_work_groups:
3944 result = ctx->num_work_groups;
3945 break;
3946 case nir_intrinsic_load_local_invocation_index:
3947 result = visit_load_local_invocation_index(ctx);
3948 break;
3949 case nir_intrinsic_load_push_constant:
3950 result = visit_load_push_constant(ctx, instr);
3951 break;
3952 case nir_intrinsic_vulkan_resource_index:
3953 result = visit_vulkan_resource_index(ctx, instr);
3954 break;
3955 case nir_intrinsic_store_ssbo:
3956 visit_store_ssbo(ctx, instr);
3957 break;
3958 case nir_intrinsic_load_ssbo:
3959 result = visit_load_buffer(ctx, instr);
3960 break;
3961 case nir_intrinsic_ssbo_atomic_add:
3962 case nir_intrinsic_ssbo_atomic_imin:
3963 case nir_intrinsic_ssbo_atomic_umin:
3964 case nir_intrinsic_ssbo_atomic_imax:
3965 case nir_intrinsic_ssbo_atomic_umax:
3966 case nir_intrinsic_ssbo_atomic_and:
3967 case nir_intrinsic_ssbo_atomic_or:
3968 case nir_intrinsic_ssbo_atomic_xor:
3969 case nir_intrinsic_ssbo_atomic_exchange:
3970 case nir_intrinsic_ssbo_atomic_comp_swap:
3971 result = visit_atomic_ssbo(ctx, instr);
3972 break;
3973 case nir_intrinsic_load_ubo:
3974 result = visit_load_ubo_buffer(ctx, instr);
3975 break;
3976 case nir_intrinsic_get_buffer_size:
3977 result = visit_get_buffer_size(ctx, instr);
3978 break;
3979 case nir_intrinsic_load_var:
3980 result = visit_load_var(ctx, instr);
3981 break;
3982 case nir_intrinsic_store_var:
3983 visit_store_var(ctx, instr);
3984 break;
3985 case nir_intrinsic_image_load:
3986 result = visit_image_load(ctx, instr);
3987 break;
3988 case nir_intrinsic_image_store:
3989 visit_image_store(ctx, instr);
3990 break;
3991 case nir_intrinsic_image_atomic_add:
3992 case nir_intrinsic_image_atomic_min:
3993 case nir_intrinsic_image_atomic_max:
3994 case nir_intrinsic_image_atomic_and:
3995 case nir_intrinsic_image_atomic_or:
3996 case nir_intrinsic_image_atomic_xor:
3997 case nir_intrinsic_image_atomic_exchange:
3998 case nir_intrinsic_image_atomic_comp_swap:
3999 result = visit_image_atomic(ctx, instr);
4000 break;
4001 case nir_intrinsic_image_size:
4002 result = visit_image_size(ctx, instr);
4003 break;
4004 case nir_intrinsic_discard:
4005 ctx->shader_info->fs.can_discard = true;
4006 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4007 ctx->voidt,
4008 NULL, 0, AC_FUNC_ATTR_LEGACY);
4009 break;
4010 case nir_intrinsic_discard_if:
4011 emit_discard_if(ctx, instr);
4012 break;
4013 case nir_intrinsic_memory_barrier:
4014 emit_waitcnt(ctx, VM_CNT);
4015 break;
4016 case nir_intrinsic_barrier:
4017 emit_barrier(ctx);
4018 break;
4019 case nir_intrinsic_var_atomic_add:
4020 case nir_intrinsic_var_atomic_imin:
4021 case nir_intrinsic_var_atomic_umin:
4022 case nir_intrinsic_var_atomic_imax:
4023 case nir_intrinsic_var_atomic_umax:
4024 case nir_intrinsic_var_atomic_and:
4025 case nir_intrinsic_var_atomic_or:
4026 case nir_intrinsic_var_atomic_xor:
4027 case nir_intrinsic_var_atomic_exchange:
4028 case nir_intrinsic_var_atomic_comp_swap:
4029 result = visit_var_atomic(ctx, instr);
4030 break;
4031 case nir_intrinsic_interp_var_at_centroid:
4032 case nir_intrinsic_interp_var_at_sample:
4033 case nir_intrinsic_interp_var_at_offset:
4034 result = visit_interp(ctx, instr);
4035 break;
4036 case nir_intrinsic_emit_vertex:
4037 visit_emit_vertex(ctx, instr);
4038 break;
4039 case nir_intrinsic_end_primitive:
4040 visit_end_primitive(ctx, instr);
4041 break;
4042 case nir_intrinsic_load_tess_coord:
4043 result = visit_load_tess_coord(ctx, instr);
4044 break;
4045 case nir_intrinsic_load_patch_vertices_in:
4046 result = LLVMConstInt(ctx->i32, ctx->options->key.tcs.input_vertices, false);
4047 break;
4048 default:
4049 fprintf(stderr, "Unknown intrinsic: ");
4050 nir_print_instr(&instr->instr, stderr);
4051 fprintf(stderr, "\n");
4052 break;
4053 }
4054 if (result) {
4055 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4056 }
4057 }
4058
4059 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
4060 nir_deref_var *deref,
4061 enum desc_type desc_type)
4062 {
4063 unsigned desc_set = deref->var->data.descriptor_set;
4064 LLVMValueRef list = ctx->descriptor_sets[desc_set];
4065 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4066 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
4067 unsigned offset = binding->offset;
4068 unsigned stride = binding->size;
4069 unsigned type_size;
4070 LLVMBuilderRef builder = ctx->builder;
4071 LLVMTypeRef type;
4072 LLVMValueRef index = NULL;
4073 unsigned constant_index = 0;
4074
4075 assert(deref->var->data.binding < layout->binding_count);
4076
4077 switch (desc_type) {
4078 case DESC_IMAGE:
4079 type = ctx->v8i32;
4080 type_size = 32;
4081 break;
4082 case DESC_FMASK:
4083 type = ctx->v8i32;
4084 offset += 32;
4085 type_size = 32;
4086 break;
4087 case DESC_SAMPLER:
4088 type = ctx->v4i32;
4089 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4090 offset += 64;
4091
4092 type_size = 16;
4093 break;
4094 case DESC_BUFFER:
4095 type = ctx->v4i32;
4096 type_size = 16;
4097 break;
4098 default:
4099 unreachable("invalid desc_type\n");
4100 }
4101
4102 if (deref->deref.child) {
4103 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
4104
4105 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4106 offset += child->base_offset * stride;
4107 if (child->deref_array_type == nir_deref_array_type_indirect) {
4108 index = get_src(ctx, child->indirect);
4109 }
4110
4111 constant_index = child->base_offset;
4112 }
4113 if (desc_type == DESC_SAMPLER && binding->immutable_samplers_offset &&
4114 (!index || binding->immutable_samplers_equal)) {
4115 if (binding->immutable_samplers_equal)
4116 constant_index = 0;
4117
4118 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4119
4120 LLVMValueRef constants[] = {
4121 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4122 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4123 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4124 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4125 };
4126 return ac_build_gather_values(&ctx->ac, constants, 4);
4127 }
4128
4129 assert(stride % type_size == 0);
4130
4131 if (!index)
4132 index = ctx->i32zero;
4133
4134 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4135
4136 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4137 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4138
4139 return ac_build_indexed_load_const(&ctx->ac, list, index);
4140 }
4141
4142 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
4143 struct ac_image_args *args,
4144 nir_tex_instr *instr,
4145 nir_texop op,
4146 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4147 LLVMValueRef *param, unsigned count,
4148 unsigned dmask)
4149 {
4150 unsigned is_rect = 0;
4151 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4152
4153 if (op == nir_texop_lod)
4154 da = false;
4155 /* Pad to power of two vector */
4156 while (count < util_next_power_of_two(count))
4157 param[count++] = LLVMGetUndef(ctx->i32);
4158
4159 if (count > 1)
4160 args->addr = ac_build_gather_values(&ctx->ac, param, count);
4161 else
4162 args->addr = param[0];
4163
4164 args->resource = res_ptr;
4165 args->sampler = samp_ptr;
4166
4167 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4168 args->addr = param[0];
4169 return;
4170 }
4171
4172 args->dmask = dmask;
4173 args->unorm = is_rect;
4174 args->da = da;
4175 }
4176
4177 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4178 *
4179 * SI-CI:
4180 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4181 * filtering manually. The driver sets img7 to a mask clearing
4182 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4183 * s_and_b32 samp0, samp0, img7
4184 *
4185 * VI:
4186 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4187 */
4188 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
4189 LLVMValueRef res, LLVMValueRef samp)
4190 {
4191 LLVMBuilderRef builder = ctx->builder;
4192 LLVMValueRef img7, samp0;
4193
4194 if (ctx->options->chip_class >= VI)
4195 return samp;
4196
4197 img7 = LLVMBuildExtractElement(builder, res,
4198 LLVMConstInt(ctx->i32, 7, 0), "");
4199 samp0 = LLVMBuildExtractElement(builder, samp,
4200 LLVMConstInt(ctx->i32, 0, 0), "");
4201 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4202 return LLVMBuildInsertElement(builder, samp, samp0,
4203 LLVMConstInt(ctx->i32, 0, 0), "");
4204 }
4205
4206 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
4207 nir_tex_instr *instr,
4208 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4209 LLVMValueRef *fmask_ptr)
4210 {
4211 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4212 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
4213 else
4214 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
4215 if (samp_ptr) {
4216 if (instr->sampler)
4217 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
4218 else
4219 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
4220 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4221 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4222 }
4223 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4224 instr->op == nir_texop_samples_identical))
4225 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
4226 }
4227
4228 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
4229 LLVMValueRef coord)
4230 {
4231 coord = to_float(ctx, coord);
4232 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4233 coord = to_integer(ctx, coord);
4234 return coord;
4235 }
4236
4237 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
4238 {
4239 LLVMValueRef result = NULL;
4240 struct ac_image_args args = { 0 };
4241 unsigned dmask = 0xf;
4242 LLVMValueRef address[16];
4243 LLVMValueRef coords[5];
4244 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4245 LLVMValueRef bias = NULL, offsets = NULL;
4246 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4247 LLVMValueRef ddx = NULL, ddy = NULL;
4248 LLVMValueRef derivs[6];
4249 unsigned chan, count = 0;
4250 unsigned const_src = 0, num_deriv_comp = 0;
4251 bool lod_is_zero = false;
4252 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4253
4254 for (unsigned i = 0; i < instr->num_srcs; i++) {
4255 switch (instr->src[i].src_type) {
4256 case nir_tex_src_coord:
4257 coord = get_src(ctx, instr->src[i].src);
4258 break;
4259 case nir_tex_src_projector:
4260 break;
4261 case nir_tex_src_comparator:
4262 comparator = get_src(ctx, instr->src[i].src);
4263 break;
4264 case nir_tex_src_offset:
4265 offsets = get_src(ctx, instr->src[i].src);
4266 const_src = i;
4267 break;
4268 case nir_tex_src_bias:
4269 bias = get_src(ctx, instr->src[i].src);
4270 break;
4271 case nir_tex_src_lod: {
4272 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4273
4274 if (val && val->i32[0] == 0)
4275 lod_is_zero = true;
4276 lod = get_src(ctx, instr->src[i].src);
4277 break;
4278 }
4279 case nir_tex_src_ms_index:
4280 sample_index = get_src(ctx, instr->src[i].src);
4281 break;
4282 case nir_tex_src_ms_mcs:
4283 break;
4284 case nir_tex_src_ddx:
4285 ddx = get_src(ctx, instr->src[i].src);
4286 num_deriv_comp = instr->src[i].src.ssa->num_components;
4287 break;
4288 case nir_tex_src_ddy:
4289 ddy = get_src(ctx, instr->src[i].src);
4290 break;
4291 case nir_tex_src_texture_offset:
4292 case nir_tex_src_sampler_offset:
4293 case nir_tex_src_plane:
4294 default:
4295 break;
4296 }
4297 }
4298
4299 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4300 result = get_buffer_size(ctx, res_ptr, true);
4301 goto write_result;
4302 }
4303
4304 if (instr->op == nir_texop_texture_samples) {
4305 LLVMValueRef res, samples, is_msaa;
4306 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
4307 samples = LLVMBuildExtractElement(ctx->builder, res,
4308 LLVMConstInt(ctx->i32, 3, false), "");
4309 is_msaa = LLVMBuildLShr(ctx->builder, samples,
4310 LLVMConstInt(ctx->i32, 28, false), "");
4311 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
4312 LLVMConstInt(ctx->i32, 0xe, false), "");
4313 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
4314 LLVMConstInt(ctx->i32, 0xe, false), "");
4315
4316 samples = LLVMBuildLShr(ctx->builder, samples,
4317 LLVMConstInt(ctx->i32, 16, false), "");
4318 samples = LLVMBuildAnd(ctx->builder, samples,
4319 LLVMConstInt(ctx->i32, 0xf, false), "");
4320 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
4321 samples, "");
4322 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
4323 ctx->i32one, "");
4324 result = samples;
4325 goto write_result;
4326 }
4327
4328 if (coord)
4329 for (chan = 0; chan < instr->coord_components; chan++)
4330 coords[chan] = llvm_extract_elem(ctx, coord, chan);
4331
4332 if (offsets && instr->op != nir_texop_txf) {
4333 LLVMValueRef offset[3], pack;
4334 for (chan = 0; chan < 3; ++chan)
4335 offset[chan] = ctx->i32zero;
4336
4337 args.offset = true;
4338 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4339 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
4340 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
4341 LLVMConstInt(ctx->i32, 0x3f, false), "");
4342 if (chan)
4343 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
4344 LLVMConstInt(ctx->i32, chan * 8, false), "");
4345 }
4346 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
4347 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
4348 address[count++] = pack;
4349
4350 }
4351 /* pack LOD bias value */
4352 if (instr->op == nir_texop_txb && bias) {
4353 address[count++] = bias;
4354 }
4355
4356 /* Pack depth comparison value */
4357 if (instr->is_shadow && comparator) {
4358 address[count++] = llvm_extract_elem(ctx, comparator, 0);
4359 }
4360
4361 /* pack derivatives */
4362 if (ddx || ddy) {
4363 switch (instr->sampler_dim) {
4364 case GLSL_SAMPLER_DIM_3D:
4365 case GLSL_SAMPLER_DIM_CUBE:
4366 num_deriv_comp = 3;
4367 break;
4368 case GLSL_SAMPLER_DIM_2D:
4369 default:
4370 num_deriv_comp = 2;
4371 break;
4372 case GLSL_SAMPLER_DIM_1D:
4373 num_deriv_comp = 1;
4374 break;
4375 }
4376
4377 for (unsigned i = 0; i < num_deriv_comp; i++) {
4378 derivs[i] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
4379 derivs[num_deriv_comp + i] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
4380 }
4381 }
4382
4383 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4384 if (instr->is_array && instr->op != nir_texop_lod)
4385 coords[3] = apply_round_slice(ctx, coords[3]);
4386 for (chan = 0; chan < instr->coord_components; chan++)
4387 coords[chan] = to_float(ctx, coords[chan]);
4388 if (instr->coord_components == 3)
4389 coords[3] = LLVMGetUndef(ctx->f32);
4390 ac_prepare_cube_coords(&ctx->ac,
4391 instr->op == nir_texop_txd, instr->is_array,
4392 coords, derivs);
4393 if (num_deriv_comp)
4394 num_deriv_comp--;
4395 }
4396
4397 if (ddx || ddy) {
4398 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4399 address[count++] = derivs[i];
4400 }
4401
4402 /* Pack texture coordinates */
4403 if (coord) {
4404 address[count++] = coords[0];
4405 if (instr->coord_components > 1) {
4406 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4407 coords[1] = apply_round_slice(ctx, coords[1]);
4408 }
4409 address[count++] = coords[1];
4410 }
4411 if (instr->coord_components > 2) {
4412 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4413 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4414 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4415 instr->op != nir_texop_txf) {
4416 coords[2] = apply_round_slice(ctx, coords[2]);
4417 }
4418 address[count++] = coords[2];
4419 }
4420 }
4421
4422 /* Pack LOD */
4423 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4424 instr->op == nir_texop_txf)) {
4425 address[count++] = lod;
4426 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4427 address[count++] = sample_index;
4428 } else if(instr->op == nir_texop_txs) {
4429 count = 0;
4430 if (lod)
4431 address[count++] = lod;
4432 else
4433 address[count++] = ctx->i32zero;
4434 }
4435
4436 for (chan = 0; chan < count; chan++) {
4437 address[chan] = LLVMBuildBitCast(ctx->builder,
4438 address[chan], ctx->i32, "");
4439 }
4440
4441 if (instr->op == nir_texop_samples_identical) {
4442 LLVMValueRef txf_address[4];
4443 struct ac_image_args txf_args = { 0 };
4444 unsigned txf_count = count;
4445 memcpy(txf_address, address, sizeof(txf_address));
4446
4447 if (!instr->is_array)
4448 txf_address[2] = ctx->i32zero;
4449 txf_address[3] = ctx->i32zero;
4450
4451 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
4452 fmask_ptr, NULL,
4453 txf_address, txf_count, 0xf);
4454
4455 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4456
4457 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4458 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
4459 goto write_result;
4460 }
4461
4462 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4463 instr->op != nir_texop_txs) {
4464 unsigned sample_chan = instr->is_array ? 3 : 2;
4465 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
4466 address[0],
4467 address[1],
4468 instr->is_array ? address[2] : NULL,
4469 address[sample_chan],
4470 fmask_ptr);
4471 }
4472
4473 if (offsets && instr->op == nir_texop_txf) {
4474 nir_const_value *const_offset =
4475 nir_src_as_const_value(instr->src[const_src].src);
4476 int num_offsets = instr->src[const_src].src.ssa->num_components;
4477 assert(const_offset);
4478 num_offsets = MIN2(num_offsets, instr->coord_components);
4479 if (num_offsets > 2)
4480 address[2] = LLVMBuildAdd(ctx->builder,
4481 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
4482 if (num_offsets > 1)
4483 address[1] = LLVMBuildAdd(ctx->builder,
4484 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
4485 address[0] = LLVMBuildAdd(ctx->builder,
4486 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
4487
4488 }
4489
4490 /* TODO TG4 support */
4491 if (instr->op == nir_texop_tg4) {
4492 if (instr->is_shadow)
4493 dmask = 1;
4494 else
4495 dmask = 1 << instr->component;
4496 }
4497 set_tex_fetch_args(ctx, &args, instr, instr->op,
4498 res_ptr, samp_ptr, address, count, dmask);
4499
4500 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4501
4502 if (instr->op == nir_texop_query_levels)
4503 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
4504 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4505 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4506 else if (instr->op == nir_texop_txs &&
4507 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4508 instr->is_array) {
4509 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
4510 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
4511 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
4512 z = LLVMBuildSDiv(ctx->builder, z, six, "");
4513 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
4514 } else if (instr->dest.ssa.num_components != 4)
4515 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
4516
4517 write_result:
4518 if (result) {
4519 assert(instr->dest.is_ssa);
4520 result = to_integer(ctx, result);
4521 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4522 }
4523 }
4524
4525
4526 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
4527 {
4528 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4529 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
4530
4531 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4532 _mesa_hash_table_insert(ctx->phis, instr, result);
4533 }
4534
4535 static void visit_post_phi(struct nir_to_llvm_context *ctx,
4536 nir_phi_instr *instr,
4537 LLVMValueRef llvm_phi)
4538 {
4539 nir_foreach_phi_src(src, instr) {
4540 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4541 LLVMValueRef llvm_src = get_src(ctx, src->src);
4542
4543 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4544 }
4545 }
4546
4547 static void phi_post_pass(struct nir_to_llvm_context *ctx)
4548 {
4549 struct hash_entry *entry;
4550 hash_table_foreach(ctx->phis, entry) {
4551 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4552 (LLVMValueRef)entry->data);
4553 }
4554 }
4555
4556
4557 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
4558 nir_ssa_undef_instr *instr)
4559 {
4560 unsigned num_components = instr->def.num_components;
4561 LLVMValueRef undef;
4562
4563 if (num_components == 1)
4564 undef = LLVMGetUndef(ctx->i32);
4565 else {
4566 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
4567 }
4568 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4569 }
4570
4571 static void visit_jump(struct nir_to_llvm_context *ctx,
4572 nir_jump_instr *instr)
4573 {
4574 switch (instr->type) {
4575 case nir_jump_break:
4576 LLVMBuildBr(ctx->builder, ctx->break_block);
4577 LLVMClearInsertionPosition(ctx->builder);
4578 break;
4579 case nir_jump_continue:
4580 LLVMBuildBr(ctx->builder, ctx->continue_block);
4581 LLVMClearInsertionPosition(ctx->builder);
4582 break;
4583 default:
4584 fprintf(stderr, "Unknown NIR jump instr: ");
4585 nir_print_instr(&instr->instr, stderr);
4586 fprintf(stderr, "\n");
4587 abort();
4588 }
4589 }
4590
4591 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4592 struct exec_list *list);
4593
4594 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
4595 {
4596 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
4597 nir_foreach_instr(instr, block)
4598 {
4599 switch (instr->type) {
4600 case nir_instr_type_alu:
4601 visit_alu(ctx, nir_instr_as_alu(instr));
4602 break;
4603 case nir_instr_type_load_const:
4604 visit_load_const(ctx, nir_instr_as_load_const(instr));
4605 break;
4606 case nir_instr_type_intrinsic:
4607 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4608 break;
4609 case nir_instr_type_tex:
4610 visit_tex(ctx, nir_instr_as_tex(instr));
4611 break;
4612 case nir_instr_type_phi:
4613 visit_phi(ctx, nir_instr_as_phi(instr));
4614 break;
4615 case nir_instr_type_ssa_undef:
4616 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4617 break;
4618 case nir_instr_type_jump:
4619 visit_jump(ctx, nir_instr_as_jump(instr));
4620 break;
4621 default:
4622 fprintf(stderr, "Unknown NIR instr type: ");
4623 nir_print_instr(instr, stderr);
4624 fprintf(stderr, "\n");
4625 abort();
4626 }
4627 }
4628
4629 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4630 }
4631
4632 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
4633 {
4634 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4635
4636 LLVMBasicBlockRef merge_block =
4637 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4638 LLVMBasicBlockRef if_block =
4639 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4640 LLVMBasicBlockRef else_block = merge_block;
4641 if (!exec_list_is_empty(&if_stmt->else_list))
4642 else_block = LLVMAppendBasicBlockInContext(
4643 ctx->context, ctx->main_function, "");
4644
4645 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
4646 LLVMConstInt(ctx->i32, 0, false), "");
4647 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
4648
4649 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
4650 visit_cf_list(ctx, &if_stmt->then_list);
4651 if (LLVMGetInsertBlock(ctx->builder))
4652 LLVMBuildBr(ctx->builder, merge_block);
4653
4654 if (!exec_list_is_empty(&if_stmt->else_list)) {
4655 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
4656 visit_cf_list(ctx, &if_stmt->else_list);
4657 if (LLVMGetInsertBlock(ctx->builder))
4658 LLVMBuildBr(ctx->builder, merge_block);
4659 }
4660
4661 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
4662 }
4663
4664 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
4665 {
4666 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4667 LLVMBasicBlockRef break_parent = ctx->break_block;
4668
4669 ctx->continue_block =
4670 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4671 ctx->break_block =
4672 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4673
4674 LLVMBuildBr(ctx->builder, ctx->continue_block);
4675 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4676 visit_cf_list(ctx, &loop->body);
4677
4678 if (LLVMGetInsertBlock(ctx->builder))
4679 LLVMBuildBr(ctx->builder, ctx->continue_block);
4680 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4681
4682 ctx->continue_block = continue_parent;
4683 ctx->break_block = break_parent;
4684 }
4685
4686 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4687 struct exec_list *list)
4688 {
4689 foreach_list_typed(nir_cf_node, node, node, list)
4690 {
4691 switch (node->type) {
4692 case nir_cf_node_block:
4693 visit_block(ctx, nir_cf_node_as_block(node));
4694 break;
4695
4696 case nir_cf_node_if:
4697 visit_if(ctx, nir_cf_node_as_if(node));
4698 break;
4699
4700 case nir_cf_node_loop:
4701 visit_loop(ctx, nir_cf_node_as_loop(node));
4702 break;
4703
4704 default:
4705 assert(0);
4706 }
4707 }
4708 }
4709
4710 static void
4711 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4712 struct nir_variable *variable)
4713 {
4714 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4715 LLVMValueRef t_offset;
4716 LLVMValueRef t_list;
4717 LLVMValueRef input;
4718 LLVMValueRef buffer_index;
4719 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4720 int idx = variable->data.location;
4721 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4722
4723 variable->data.driver_location = idx * 4;
4724
4725 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4726 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4727 ctx->start_instance, "");
4728 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4729 ctx->shader_info->vs.vgpr_comp_cnt);
4730 } else
4731 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4732 ctx->base_vertex, "");
4733
4734 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4735 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4736
4737 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4738
4739 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4740 buffer_index,
4741 LLVMConstInt(ctx->i32, 0, false),
4742 true);
4743
4744 for (unsigned chan = 0; chan < 4; chan++) {
4745 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4746 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4747 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4748 input, llvm_chan, ""));
4749 }
4750 }
4751 }
4752
4753 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4754 unsigned attr,
4755 LLVMValueRef interp_param,
4756 LLVMValueRef prim_mask,
4757 LLVMValueRef result[4])
4758 {
4759 LLVMValueRef attr_number;
4760 unsigned chan;
4761 LLVMValueRef i, j;
4762 bool interp = interp_param != NULL;
4763
4764 attr_number = LLVMConstInt(ctx->i32, attr, false);
4765
4766 /* fs.constant returns the param from the middle vertex, so it's not
4767 * really useful for flat shading. It's meant to be used for custom
4768 * interpolation (but the intrinsic can't fetch from the other two
4769 * vertices).
4770 *
4771 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4772 * to do the right thing. The only reason we use fs.constant is that
4773 * fs.interp cannot be used on integers, because they can be equal
4774 * to NaN.
4775 */
4776 if (interp) {
4777 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4778 LLVMVectorType(ctx->f32, 2), "");
4779
4780 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4781 ctx->i32zero, "");
4782 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4783 ctx->i32one, "");
4784 }
4785
4786 for (chan = 0; chan < 4; chan++) {
4787 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4788
4789 if (interp) {
4790 result[chan] = ac_build_fs_interp(&ctx->ac,
4791 llvm_chan,
4792 attr_number,
4793 prim_mask, i, j);
4794 } else {
4795 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4796 LLVMConstInt(ctx->i32, 2, false),
4797 llvm_chan,
4798 attr_number,
4799 prim_mask);
4800 }
4801 }
4802 }
4803
4804 static void
4805 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4806 struct nir_variable *variable)
4807 {
4808 int idx = variable->data.location;
4809 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4810 LLVMValueRef interp;
4811
4812 variable->data.driver_location = idx * 4;
4813 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4814
4815 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4816 unsigned interp_type;
4817 if (variable->data.sample) {
4818 interp_type = INTERP_SAMPLE;
4819 ctx->shader_info->fs.force_persample = true;
4820 } else if (variable->data.centroid)
4821 interp_type = INTERP_CENTROID;
4822 else
4823 interp_type = INTERP_CENTER;
4824
4825 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4826 } else
4827 interp = NULL;
4828
4829 for (unsigned i = 0; i < attrib_count; ++i)
4830 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4831
4832 }
4833
4834 static void
4835 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4836 struct nir_variable *variable)
4837 {
4838 switch (ctx->stage) {
4839 case MESA_SHADER_VERTEX:
4840 handle_vs_input_decl(ctx, variable);
4841 break;
4842 case MESA_SHADER_FRAGMENT:
4843 handle_fs_input_decl(ctx, variable);
4844 break;
4845 default:
4846 break;
4847 }
4848
4849 }
4850
4851 static void
4852 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4853 struct nir_shader *nir)
4854 {
4855 unsigned index = 0;
4856 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4857 LLVMValueRef interp_param;
4858 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4859
4860 if (!(ctx->input_mask & (1ull << i)))
4861 continue;
4862
4863 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4864 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4865 interp_param = *inputs;
4866 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4867 inputs);
4868
4869 if (!interp_param)
4870 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4871 ++index;
4872 } else if (i == VARYING_SLOT_POS) {
4873 for(int i = 0; i < 3; ++i)
4874 inputs[i] = ctx->frag_pos[i];
4875
4876 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4877 }
4878 }
4879 ctx->shader_info->fs.num_interp = index;
4880 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4881 ctx->shader_info->fs.has_pcoord = true;
4882 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4883 ctx->shader_info->fs.prim_id_input = true;
4884 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4885 ctx->shader_info->fs.layer_input = true;
4886 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4887 }
4888
4889 static LLVMValueRef
4890 ac_build_alloca(struct nir_to_llvm_context *ctx,
4891 LLVMTypeRef type,
4892 const char *name)
4893 {
4894 LLVMBuilderRef builder = ctx->builder;
4895 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4896 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4897 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4898 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4899 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4900 LLVMValueRef res;
4901
4902 if (first_instr) {
4903 LLVMPositionBuilderBefore(first_builder, first_instr);
4904 } else {
4905 LLVMPositionBuilderAtEnd(first_builder, first_block);
4906 }
4907
4908 res = LLVMBuildAlloca(first_builder, type, name);
4909 LLVMBuildStore(builder, LLVMConstNull(type), res);
4910
4911 LLVMDisposeBuilder(first_builder);
4912
4913 return res;
4914 }
4915
4916 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4917 LLVMTypeRef type,
4918 const char *name)
4919 {
4920 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4921 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4922 return ptr;
4923 }
4924
4925 static void
4926 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4927 struct nir_variable *variable)
4928 {
4929 int idx = variable->data.location + variable->data.index;
4930 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4931 uint64_t mask_attribs;
4932 variable->data.driver_location = idx * 4;
4933
4934 /* tess ctrl has it's own load/store paths for outputs */
4935 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4936 return;
4937
4938 mask_attribs = ((1ull << attrib_count) - 1) << idx;
4939 if (ctx->stage == MESA_SHADER_VERTEX ||
4940 ctx->stage == MESA_SHADER_TESS_EVAL ||
4941 ctx->stage == MESA_SHADER_GEOMETRY) {
4942 if (idx == VARYING_SLOT_CLIP_DIST0) {
4943 int length = ctx->num_output_clips + ctx->num_output_culls;
4944 if (ctx->stage == MESA_SHADER_VERTEX) {
4945 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4946 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4947 }
4948 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4949 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4950 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4951 }
4952
4953 if (length > 4)
4954 attrib_count = 2;
4955 else
4956 attrib_count = 1;
4957 mask_attribs = 1ull << idx;
4958 }
4959 }
4960
4961 for (unsigned i = 0; i < attrib_count; ++i) {
4962 for (unsigned chan = 0; chan < 4; chan++) {
4963 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4964 si_build_alloca_undef(ctx, ctx->f32, "");
4965 }
4966 }
4967 ctx->output_mask |= mask_attribs;
4968 }
4969
4970 static void
4971 setup_locals(struct nir_to_llvm_context *ctx,
4972 struct nir_function *func)
4973 {
4974 int i, j;
4975 ctx->num_locals = 0;
4976 nir_foreach_variable(variable, &func->impl->locals) {
4977 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4978 variable->data.driver_location = ctx->num_locals * 4;
4979 ctx->num_locals += attrib_count;
4980 }
4981 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4982 if (!ctx->locals)
4983 return;
4984
4985 for (i = 0; i < ctx->num_locals; i++) {
4986 for (j = 0; j < 4; j++) {
4987 ctx->locals[i * 4 + j] =
4988 si_build_alloca_undef(ctx, ctx->f32, "temp");
4989 }
4990 }
4991 }
4992
4993 static LLVMValueRef
4994 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4995 {
4996 v = to_float(ctx, v);
4997 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4998 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4999 }
5000
5001
5002 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5003 LLVMValueRef src0, LLVMValueRef src1)
5004 {
5005 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5006 LLVMValueRef comp[2];
5007
5008 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5009 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5010 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5011 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5012 }
5013
5014 /* Initialize arguments for the shader export intrinsic */
5015 static void
5016 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5017 LLVMValueRef *values,
5018 unsigned target,
5019 struct ac_export_args *args)
5020 {
5021 /* Default is 0xf. Adjusted below depending on the format. */
5022 args->enabled_channels = 0xf;
5023
5024 /* Specify whether the EXEC mask represents the valid mask */
5025 args->valid_mask = 0;
5026
5027 /* Specify whether this is the last export */
5028 args->done = 0;
5029
5030 /* Specify the target we are exporting */
5031 args->target = target;
5032
5033 args->compr = false;
5034 args->out[0] = LLVMGetUndef(ctx->f32);
5035 args->out[1] = LLVMGetUndef(ctx->f32);
5036 args->out[2] = LLVMGetUndef(ctx->f32);
5037 args->out[3] = LLVMGetUndef(ctx->f32);
5038
5039 if (!values)
5040 return;
5041
5042 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5043 LLVMValueRef val[4];
5044 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5045 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5046 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5047
5048 switch(col_format) {
5049 case V_028714_SPI_SHADER_ZERO:
5050 args->enabled_channels = 0; /* writemask */
5051 args->target = V_008DFC_SQ_EXP_NULL;
5052 break;
5053
5054 case V_028714_SPI_SHADER_32_R:
5055 args->enabled_channels = 1;
5056 args->out[0] = values[0];
5057 break;
5058
5059 case V_028714_SPI_SHADER_32_GR:
5060 args->enabled_channels = 0x3;
5061 args->out[0] = values[0];
5062 args->out[1] = values[1];
5063 break;
5064
5065 case V_028714_SPI_SHADER_32_AR:
5066 args->enabled_channels = 0x9;
5067 args->out[0] = values[0];
5068 args->out[3] = values[3];
5069 break;
5070
5071 case V_028714_SPI_SHADER_FP16_ABGR:
5072 args->compr = 1;
5073
5074 for (unsigned chan = 0; chan < 2; chan++) {
5075 LLVMValueRef pack_args[2] = {
5076 values[2 * chan],
5077 values[2 * chan + 1]
5078 };
5079 LLVMValueRef packed;
5080
5081 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5082 args->out[chan] = packed;
5083 }
5084 break;
5085
5086 case V_028714_SPI_SHADER_UNORM16_ABGR:
5087 for (unsigned chan = 0; chan < 4; chan++) {
5088 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5089 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5090 LLVMConstReal(ctx->f32, 65535), "");
5091 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5092 LLVMConstReal(ctx->f32, 0.5), "");
5093 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5094 ctx->i32, "");
5095 }
5096
5097 args->compr = 1;
5098 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5099 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5100 break;
5101
5102 case V_028714_SPI_SHADER_SNORM16_ABGR:
5103 for (unsigned chan = 0; chan < 4; chan++) {
5104 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
5105 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5106 LLVMConstReal(ctx->f32, 32767), "");
5107
5108 /* If positive, add 0.5, else add -0.5. */
5109 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5110 LLVMBuildSelect(ctx->builder,
5111 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5112 val[chan], ctx->f32zero, ""),
5113 LLVMConstReal(ctx->f32, 0.5),
5114 LLVMConstReal(ctx->f32, -0.5), ""), "");
5115 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5116 }
5117
5118 args->compr = 1;
5119 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5120 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5121 break;
5122
5123 case V_028714_SPI_SHADER_UINT16_ABGR: {
5124 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
5125
5126 for (unsigned chan = 0; chan < 4; chan++) {
5127 val[chan] = to_integer(ctx, values[chan]);
5128 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
5129 }
5130
5131 args->compr = 1;
5132 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5133 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5134 break;
5135 }
5136
5137 case V_028714_SPI_SHADER_SINT16_ABGR: {
5138 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5139 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5140
5141 /* Clamp. */
5142 for (unsigned chan = 0; chan < 4; chan++) {
5143 val[chan] = to_integer(ctx, values[chan]);
5144 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
5145 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
5146 }
5147
5148 args->compr = 1;
5149 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5150 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5151 break;
5152 }
5153
5154 default:
5155 case V_028714_SPI_SHADER_32_ABGR:
5156 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5157 break;
5158 }
5159 } else
5160 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5161
5162 for (unsigned i = 0; i < 4; ++i)
5163 args->out[i] = to_float(ctx, args->out[i]);
5164 }
5165
5166 static void
5167 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5168 struct ac_vs_output_info *outinfo)
5169 {
5170 uint32_t param_count = 0;
5171 unsigned target;
5172 unsigned pos_idx, num_pos_exports = 0;
5173 struct ac_export_args args, pos_args[4] = {};
5174 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5175 int i;
5176
5177 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5178 sizeof(outinfo->vs_output_param_offset));
5179
5180 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5181 LLVMValueRef slots[8];
5182 unsigned j;
5183
5184 if (outinfo->cull_dist_mask)
5185 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5186
5187 i = VARYING_SLOT_CLIP_DIST0;
5188 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5189 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5190 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5191
5192 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5193 slots[i] = LLVMGetUndef(ctx->f32);
5194
5195 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5196 target = V_008DFC_SQ_EXP_POS + 3;
5197 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5198 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5199 &args, sizeof(args));
5200 }
5201
5202 target = V_008DFC_SQ_EXP_POS + 2;
5203 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5204 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5205 &args, sizeof(args));
5206
5207 }
5208
5209 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5210 LLVMValueRef values[4];
5211 if (!(ctx->output_mask & (1ull << i)))
5212 continue;
5213
5214 for (unsigned j = 0; j < 4; j++)
5215 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5216 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5217
5218 if (i == VARYING_SLOT_POS) {
5219 target = V_008DFC_SQ_EXP_POS;
5220 } else if (i == VARYING_SLOT_CLIP_DIST0) {
5221 continue;
5222 } else if (i == VARYING_SLOT_PSIZ) {
5223 outinfo->writes_pointsize = true;
5224 psize_value = values[0];
5225 continue;
5226 } else if (i == VARYING_SLOT_LAYER) {
5227 outinfo->writes_layer = true;
5228 layer_value = values[0];
5229 target = V_008DFC_SQ_EXP_PARAM + param_count;
5230 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5231 param_count++;
5232 } else if (i == VARYING_SLOT_VIEWPORT) {
5233 outinfo->writes_viewport_index = true;
5234 viewport_index_value = values[0];
5235 continue;
5236 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5237 target = V_008DFC_SQ_EXP_PARAM + param_count;
5238 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5239 param_count++;
5240 } else if (i >= VARYING_SLOT_VAR0) {
5241 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5242 target = V_008DFC_SQ_EXP_PARAM + param_count;
5243 outinfo->vs_output_param_offset[i] = param_count;
5244 param_count++;
5245 }
5246
5247 si_llvm_init_export_args(ctx, values, target, &args);
5248
5249 if (target >= V_008DFC_SQ_EXP_POS &&
5250 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5251 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5252 &args, sizeof(args));
5253 } else {
5254 ac_build_export(&ctx->ac, &args);
5255 }
5256 }
5257
5258 /* We need to add the position output manually if it's missing. */
5259 if (!pos_args[0].out[0]) {
5260 pos_args[0].enabled_channels = 0xf;
5261 pos_args[0].valid_mask = 0;
5262 pos_args[0].done = 0;
5263 pos_args[0].target = V_008DFC_SQ_EXP_POS;
5264 pos_args[0].compr = 0;
5265 pos_args[0].out[0] = ctx->f32zero; /* X */
5266 pos_args[0].out[1] = ctx->f32zero; /* Y */
5267 pos_args[0].out[2] = ctx->f32zero; /* Z */
5268 pos_args[0].out[3] = ctx->f32one; /* W */
5269 }
5270
5271 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5272 (outinfo->writes_layer == true ? 4 : 0) |
5273 (outinfo->writes_viewport_index == true ? 8 : 0));
5274 if (mask) {
5275 pos_args[1].enabled_channels = mask;
5276 pos_args[1].valid_mask = 0;
5277 pos_args[1].done = 0;
5278 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5279 pos_args[1].compr = 0;
5280 pos_args[1].out[0] = ctx->f32zero; /* X */
5281 pos_args[1].out[1] = ctx->f32zero; /* Y */
5282 pos_args[1].out[2] = ctx->f32zero; /* Z */
5283 pos_args[1].out[3] = ctx->f32zero; /* W */
5284
5285 if (outinfo->writes_pointsize == true)
5286 pos_args[1].out[0] = psize_value;
5287 if (outinfo->writes_layer == true)
5288 pos_args[1].out[2] = layer_value;
5289 if (outinfo->writes_viewport_index == true)
5290 pos_args[1].out[3] = viewport_index_value;
5291 }
5292 for (i = 0; i < 4; i++) {
5293 if (pos_args[i].out[0])
5294 num_pos_exports++;
5295 }
5296
5297 pos_idx = 0;
5298 for (i = 0; i < 4; i++) {
5299 if (!pos_args[i].out[0])
5300 continue;
5301
5302 /* Specify the target we are exporting */
5303 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5304 if (pos_idx == num_pos_exports)
5305 pos_args[i].done = 1;
5306 ac_build_export(&ctx->ac, &pos_args[i]);
5307 }
5308
5309 outinfo->pos_exports = num_pos_exports;
5310 outinfo->param_exports = param_count;
5311 }
5312
5313 static void
5314 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5315 struct ac_es_output_info *outinfo)
5316 {
5317 int j;
5318 uint64_t max_output_written = 0;
5319 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5320 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5321 int param_index;
5322 int length = 4;
5323
5324 if (!(ctx->output_mask & (1ull << i)))
5325 continue;
5326
5327 if (i == VARYING_SLOT_CLIP_DIST0)
5328 length = ctx->num_output_clips + ctx->num_output_culls;
5329
5330 param_index = shader_io_get_unique_index(i);
5331
5332 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5333
5334 for (j = 0; j < length; j++) {
5335 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5336 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5337
5338 ac_build_buffer_store_dword(&ctx->ac,
5339 ctx->esgs_ring,
5340 out_val, 1,
5341 NULL, ctx->es2gs_offset,
5342 (4 * param_index + j) * 4,
5343 1, 1, true, true);
5344 }
5345 }
5346 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5347 }
5348
5349 static void
5350 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5351 {
5352 LLVMValueRef vertex_id = ctx->rel_auto_id;
5353 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5354 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5355 vertex_dw_stride, "");
5356
5357 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5358 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5359 int length = 4;
5360
5361 if (!(ctx->output_mask & (1ull << i)))
5362 continue;
5363
5364 if (i == VARYING_SLOT_CLIP_DIST0)
5365 length = ctx->num_output_clips + ctx->num_output_culls;
5366 int param = shader_io_get_unique_index(i);
5367 mark_tess_output(ctx, false, param);
5368 if (length > 4)
5369 mark_tess_output(ctx, false, param + 1);
5370 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5371 LLVMConstInt(ctx->i32, param * 4, false),
5372 "");
5373 for (unsigned j = 0; j < length; j++) {
5374 lds_store(ctx, dw_addr,
5375 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5376 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5377 }
5378 }
5379 }
5380
5381 struct ac_build_if_state
5382 {
5383 struct nir_to_llvm_context *ctx;
5384 LLVMValueRef condition;
5385 LLVMBasicBlockRef entry_block;
5386 LLVMBasicBlockRef true_block;
5387 LLVMBasicBlockRef false_block;
5388 LLVMBasicBlockRef merge_block;
5389 };
5390
5391 static LLVMBasicBlockRef
5392 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5393 {
5394 LLVMBasicBlockRef current_block;
5395 LLVMBasicBlockRef next_block;
5396 LLVMBasicBlockRef new_block;
5397
5398 /* get current basic block */
5399 current_block = LLVMGetInsertBlock(ctx->builder);
5400
5401 /* chqeck if there's another block after this one */
5402 next_block = LLVMGetNextBasicBlock(current_block);
5403 if (next_block) {
5404 /* insert the new block before the next block */
5405 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5406 }
5407 else {
5408 /* append new block after current block */
5409 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5410 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5411 }
5412 return new_block;
5413 }
5414
5415 static void
5416 ac_nir_build_if(struct ac_build_if_state *ifthen,
5417 struct nir_to_llvm_context *ctx,
5418 LLVMValueRef condition)
5419 {
5420 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5421
5422 memset(ifthen, 0, sizeof *ifthen);
5423 ifthen->ctx = ctx;
5424 ifthen->condition = condition;
5425 ifthen->entry_block = block;
5426
5427 /* create endif/merge basic block for the phi functions */
5428 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5429
5430 /* create/insert true_block before merge_block */
5431 ifthen->true_block =
5432 LLVMInsertBasicBlockInContext(ctx->context,
5433 ifthen->merge_block,
5434 "if-true-block");
5435
5436 /* successive code goes into the true block */
5437 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5438 }
5439
5440 /**
5441 * End a conditional.
5442 */
5443 static void
5444 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5445 {
5446 LLVMBuilderRef builder = ifthen->ctx->builder;
5447
5448 /* Insert branch to the merge block from current block */
5449 LLVMBuildBr(builder, ifthen->merge_block);
5450
5451 /*
5452 * Now patch in the various branch instructions.
5453 */
5454
5455 /* Insert the conditional branch instruction at the end of entry_block */
5456 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5457 if (ifthen->false_block) {
5458 /* we have an else clause */
5459 LLVMBuildCondBr(builder, ifthen->condition,
5460 ifthen->true_block, ifthen->false_block);
5461 }
5462 else {
5463 /* no else clause */
5464 LLVMBuildCondBr(builder, ifthen->condition,
5465 ifthen->true_block, ifthen->merge_block);
5466 }
5467
5468 /* Resume building code at end of the ifthen->merge_block */
5469 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5470 }
5471
5472 static void
5473 write_tess_factors(struct nir_to_llvm_context *ctx)
5474 {
5475 unsigned stride, outer_comps, inner_comps;
5476 struct ac_build_if_state if_ctx, inner_if_ctx;
5477 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5478 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5479 unsigned tess_inner_index, tess_outer_index;
5480 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5481 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5482 int i;
5483 emit_barrier(ctx);
5484
5485 switch (ctx->options->key.tcs.primitive_mode) {
5486 case GL_ISOLINES:
5487 stride = 2;
5488 outer_comps = 2;
5489 inner_comps = 0;
5490 break;
5491 case GL_TRIANGLES:
5492 stride = 4;
5493 outer_comps = 3;
5494 inner_comps = 1;
5495 break;
5496 case GL_QUADS:
5497 stride = 6;
5498 outer_comps = 4;
5499 inner_comps = 2;
5500 break;
5501 default:
5502 return;
5503 }
5504
5505 ac_nir_build_if(&if_ctx, ctx,
5506 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5507 invocation_id, ctx->i32zero, ""));
5508
5509 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5510 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5511
5512 mark_tess_output(ctx, true, tess_inner_index);
5513 mark_tess_output(ctx, true, tess_outer_index);
5514 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5515 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5516 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5517 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5518 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5519
5520 for (i = 0; i < 4; i++) {
5521 inner[i] = LLVMGetUndef(ctx->i32);
5522 outer[i] = LLVMGetUndef(ctx->i32);
5523 }
5524
5525 // LINES reverseal
5526 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5527 outer[0] = out[1] = lds_load(ctx, lds_outer);
5528 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5529 LLVMConstInt(ctx->i32, 1, false), "");
5530 outer[1] = out[0] = lds_load(ctx, lds_outer);
5531 } else {
5532 for (i = 0; i < outer_comps; i++) {
5533 outer[i] = out[i] =
5534 lds_load(ctx, lds_outer);
5535 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5536 LLVMConstInt(ctx->i32, 1, false), "");
5537 }
5538 for (i = 0; i < inner_comps; i++) {
5539 inner[i] = out[outer_comps+i] =
5540 lds_load(ctx, lds_inner);
5541 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5542 LLVMConstInt(ctx->i32, 1, false), "");
5543 }
5544 }
5545
5546 /* Convert the outputs to vectors for stores. */
5547 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5548 vec1 = NULL;
5549
5550 if (stride > 4)
5551 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5552
5553
5554 buffer = ctx->hs_ring_tess_factor;
5555 tf_base = ctx->tess_factor_offset;
5556 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5557 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5558
5559 ac_nir_build_if(&inner_if_ctx, ctx,
5560 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5561 rel_patch_id, ctx->i32zero, ""));
5562
5563 /* Store the dynamic HS control word. */
5564 ac_build_buffer_store_dword(&ctx->ac, buffer,
5565 LLVMConstInt(ctx->i32, 0x80000000, false),
5566 1, ctx->i32zero, tf_base,
5567 0, 1, 0, true, false);
5568 ac_nir_build_endif(&inner_if_ctx);
5569
5570 /* Store the tessellation factors. */
5571 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5572 MIN2(stride, 4), byteoffset, tf_base,
5573 4, 1, 0, true, false);
5574 if (vec1)
5575 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5576 stride - 4, byteoffset, tf_base,
5577 20, 1, 0, true, false);
5578
5579 //TODO store to offchip for TES to read - only if TES reads them
5580 if (1) {
5581 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5582 LLVMValueRef tf_inner_offset;
5583 unsigned param_outer, param_inner;
5584
5585 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5586 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5587 LLVMConstInt(ctx->i32, param_outer, 0));
5588
5589 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5590 util_next_power_of_two(outer_comps));
5591
5592 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5593 outer_comps, tf_outer_offset,
5594 ctx->oc_lds, 0, 1, 0, true, false);
5595 if (inner_comps) {
5596 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5597 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5598 LLVMConstInt(ctx->i32, param_inner, 0));
5599
5600 inner_vec = inner_comps == 1 ? inner[0] :
5601 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5602 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5603 inner_comps, tf_inner_offset,
5604 ctx->oc_lds, 0, 1, 0, true, false);
5605 }
5606 }
5607 ac_nir_build_endif(&if_ctx);
5608 }
5609
5610 static void
5611 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5612 {
5613 write_tess_factors(ctx);
5614 }
5615
5616 static bool
5617 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5618 LLVMValueRef *color, unsigned param, bool is_last,
5619 struct ac_export_args *args)
5620 {
5621 /* Export */
5622 si_llvm_init_export_args(ctx, color, param,
5623 args);
5624
5625 if (is_last) {
5626 args->valid_mask = 1; /* whether the EXEC mask is valid */
5627 args->done = 1; /* DONE bit */
5628 } else if (!args->enabled_channels)
5629 return false; /* unnecessary NULL export */
5630
5631 return true;
5632 }
5633
5634 static void
5635 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5636 LLVMValueRef depth, LLVMValueRef stencil,
5637 LLVMValueRef samplemask)
5638 {
5639 struct ac_export_args args;
5640
5641 args.enabled_channels = 0;
5642 args.valid_mask = 1;
5643 args.done = 1;
5644 args.target = V_008DFC_SQ_EXP_MRTZ;
5645 args.compr = false;
5646
5647 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5648 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5649 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5650 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5651
5652 if (depth) {
5653 args.out[0] = depth;
5654 args.enabled_channels |= 0x1;
5655 }
5656
5657 if (stencil) {
5658 args.out[1] = stencil;
5659 args.enabled_channels |= 0x2;
5660 }
5661
5662 if (samplemask) {
5663 args.out[2] = samplemask;
5664 args.enabled_channels |= 0x4;
5665 }
5666
5667 /* SI (except OLAND) has a bug that it only looks
5668 * at the X writemask component. */
5669 if (ctx->options->chip_class == SI &&
5670 ctx->options->family != CHIP_OLAND)
5671 args.enabled_channels |= 0x1;
5672
5673 ac_build_export(&ctx->ac, &args);
5674 }
5675
5676 static void
5677 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5678 {
5679 unsigned index = 0;
5680 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5681 struct ac_export_args color_args[8];
5682
5683 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5684 LLVMValueRef values[4];
5685
5686 if (!(ctx->output_mask & (1ull << i)))
5687 continue;
5688
5689 if (i == FRAG_RESULT_DEPTH) {
5690 ctx->shader_info->fs.writes_z = true;
5691 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
5692 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5693 } else if (i == FRAG_RESULT_STENCIL) {
5694 ctx->shader_info->fs.writes_stencil = true;
5695 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
5696 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5697 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5698 ctx->shader_info->fs.writes_sample_mask = true;
5699 samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
5700 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5701 } else {
5702 bool last = false;
5703 for (unsigned j = 0; j < 4; j++)
5704 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5705 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5706
5707 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5708 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5709
5710 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
5711 if (ret)
5712 index++;
5713 }
5714 }
5715
5716 for (unsigned i = 0; i < index; i++)
5717 ac_build_export(&ctx->ac, &color_args[i]);
5718 if (depth || stencil || samplemask)
5719 si_export_mrt_z(ctx, depth, stencil, samplemask);
5720 else if (!index) {
5721 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
5722 ac_build_export(&ctx->ac, &color_args[0]);
5723 }
5724
5725 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5726 }
5727
5728 static void
5729 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5730 {
5731 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5732 }
5733
5734 static void
5735 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
5736 {
5737 switch (ctx->stage) {
5738 case MESA_SHADER_VERTEX:
5739 if (ctx->options->key.vs.as_ls)
5740 handle_ls_outputs_post(ctx);
5741 else if (ctx->options->key.vs.as_es)
5742 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5743 else
5744 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
5745 break;
5746 case MESA_SHADER_FRAGMENT:
5747 handle_fs_outputs_post(ctx);
5748 break;
5749 case MESA_SHADER_GEOMETRY:
5750 emit_gs_epilogue(ctx);
5751 break;
5752 case MESA_SHADER_TESS_CTRL:
5753 handle_tcs_outputs_post(ctx);
5754 break;
5755 case MESA_SHADER_TESS_EVAL:
5756 if (ctx->options->key.tes.as_es)
5757 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
5758 else
5759 handle_vs_outputs_post(ctx, &ctx->shader_info->tes.outinfo);
5760 break;
5761 default:
5762 break;
5763 }
5764 }
5765
5766 static void
5767 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
5768 struct nir_variable *variable, uint32_t *offset, int idx)
5769 {
5770 unsigned size = glsl_count_attribute_slots(variable->type, false);
5771 variable->data.driver_location = *offset;
5772 *offset += size;
5773 }
5774
5775 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
5776 {
5777 LLVMPassManagerRef passmgr;
5778 /* Create the pass manager */
5779 passmgr = LLVMCreateFunctionPassManagerForModule(
5780 ctx->module);
5781
5782 /* This pass should eliminate all the load and store instructions */
5783 LLVMAddPromoteMemoryToRegisterPass(passmgr);
5784
5785 /* Add some optimization passes */
5786 LLVMAddScalarReplAggregatesPass(passmgr);
5787 LLVMAddLICMPass(passmgr);
5788 LLVMAddAggressiveDCEPass(passmgr);
5789 LLVMAddCFGSimplificationPass(passmgr);
5790 LLVMAddInstructionCombiningPass(passmgr);
5791
5792 /* Run the pass */
5793 LLVMInitializeFunctionPassManager(passmgr);
5794 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
5795 LLVMFinalizeFunctionPassManager(passmgr);
5796
5797 LLVMDisposeBuilder(ctx->builder);
5798 LLVMDisposePassManager(passmgr);
5799 }
5800
5801 static void
5802 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
5803 {
5804 struct ac_vs_output_info *outinfo;
5805
5806 if (ctx->stage == MESA_SHADER_FRAGMENT ||
5807 ctx->stage == MESA_SHADER_COMPUTE ||
5808 ctx->stage == MESA_SHADER_TESS_CTRL ||
5809 ctx->stage == MESA_SHADER_GEOMETRY)
5810 return;
5811
5812 if (ctx->stage == MESA_SHADER_VERTEX) {
5813 if (ctx->options->key.vs.as_ls ||
5814 ctx->options->key.vs.as_es)
5815 return;
5816 outinfo = &ctx->shader_info->vs.outinfo;
5817 }
5818
5819 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5820 if (ctx->options->key.vs.as_es)
5821 return;
5822 outinfo = &ctx->shader_info->tes.outinfo;
5823 }
5824
5825 ac_optimize_vs_outputs(&ctx->ac,
5826 ctx->main_function,
5827 outinfo->vs_output_param_offset,
5828 VARYING_SLOT_MAX,
5829 &outinfo->param_exports);
5830 }
5831
5832 static void
5833 ac_setup_rings(struct nir_to_llvm_context *ctx)
5834 {
5835 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
5836 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
5837 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
5838 }
5839
5840 if (ctx->is_gs_copy_shader) {
5841 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
5842 }
5843 if (ctx->stage == MESA_SHADER_GEOMETRY) {
5844 LLVMValueRef tmp;
5845 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
5846 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
5847
5848 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
5849
5850 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
5851 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
5852 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
5853 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
5854
5855 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
5856 }
5857
5858 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
5859 ctx->stage == MESA_SHADER_TESS_EVAL) {
5860 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
5861 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
5862 }
5863 }
5864
5865 static unsigned
5866 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
5867 struct nir_shader *nir)
5868 {
5869 switch (nir->stage) {
5870 case MESA_SHADER_TESS_CTRL:
5871 return chip_class >= CIK ? 128 : 64;
5872 case MESA_SHADER_GEOMETRY:
5873 return 64;
5874 case MESA_SHADER_COMPUTE:
5875 break;
5876 default:
5877 return 0;
5878 }
5879
5880 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
5881 nir->info.cs.local_size[1] *
5882 nir->info.cs.local_size[2];
5883 return max_workgroup_size;
5884 }
5885
5886 static
5887 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
5888 struct nir_shader *nir,
5889 struct ac_shader_variant_info *shader_info,
5890 const struct ac_nir_compiler_options *options)
5891 {
5892 struct nir_to_llvm_context ctx = {0};
5893 struct nir_function *func;
5894 unsigned i;
5895 ctx.options = options;
5896 ctx.shader_info = shader_info;
5897 ctx.context = LLVMContextCreate();
5898 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5899
5900 ac_llvm_context_init(&ctx.ac, ctx.context);
5901 ctx.ac.module = ctx.module;
5902
5903 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
5904
5905 memset(shader_info, 0, sizeof(*shader_info));
5906
5907 ac_nir_shader_info_pass(nir, options, &shader_info->info);
5908
5909 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
5910
5911 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
5912 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
5913 LLVMSetDataLayout(ctx.module, data_layout_str);
5914 LLVMDisposeTargetData(data_layout);
5915 LLVMDisposeMessage(data_layout_str);
5916
5917 setup_types(&ctx);
5918
5919 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5920 ctx.ac.builder = ctx.builder;
5921 ctx.stage = nir->stage;
5922 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
5923
5924 for (i = 0; i < AC_UD_MAX_SETS; i++)
5925 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
5926 for (i = 0; i < AC_UD_MAX_UD; i++)
5927 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
5928
5929 create_function(&ctx);
5930
5931 if (nir->stage == MESA_SHADER_COMPUTE) {
5932 int num_shared = 0;
5933 nir_foreach_variable(variable, &nir->shared)
5934 num_shared++;
5935 if (num_shared) {
5936 int idx = 0;
5937 uint32_t shared_size = 0;
5938 LLVMValueRef var;
5939 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
5940 nir_foreach_variable(variable, &nir->shared) {
5941 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
5942 idx++;
5943 }
5944
5945 shared_size *= 16;
5946 var = LLVMAddGlobalInAddressSpace(ctx.module,
5947 LLVMArrayType(ctx.i8, shared_size),
5948 "compute_lds",
5949 LOCAL_ADDR_SPACE);
5950 LLVMSetAlignment(var, 4);
5951 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
5952 }
5953 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
5954 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
5955
5956 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
5957 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
5958 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
5959 }
5960
5961 ac_setup_rings(&ctx);
5962
5963 nir_foreach_variable(variable, &nir->inputs)
5964 handle_shader_input_decl(&ctx, variable);
5965
5966 if (nir->stage == MESA_SHADER_FRAGMENT)
5967 handle_fs_inputs_pre(&ctx, nir);
5968
5969 ctx.num_output_clips = nir->info.clip_distance_array_size;
5970 ctx.num_output_culls = nir->info.cull_distance_array_size;
5971
5972 nir_foreach_variable(variable, &nir->outputs)
5973 handle_shader_output_decl(&ctx, variable);
5974
5975 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5976 _mesa_key_pointer_equal);
5977 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5978 _mesa_key_pointer_equal);
5979
5980 func = (struct nir_function *)exec_list_get_head(&nir->functions);
5981
5982 setup_locals(&ctx, func);
5983
5984 visit_cf_list(&ctx, &func->impl->body);
5985 phi_post_pass(&ctx);
5986
5987 handle_shader_outputs_post(&ctx);
5988 LLVMBuildRetVoid(ctx.builder);
5989
5990 ac_llvm_finalize_module(&ctx);
5991
5992 ac_nir_eliminate_const_vs_outputs(&ctx);
5993 free(ctx.locals);
5994 ralloc_free(ctx.defs);
5995 ralloc_free(ctx.phis);
5996
5997 if (nir->stage == MESA_SHADER_GEOMETRY) {
5998 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
5999 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6000 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6001 nir->info.gs.vertices_out;
6002 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
6003 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6004 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6005 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6006 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6007 }
6008
6009 return ctx.module;
6010 }
6011
6012 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6013 {
6014 unsigned *retval = (unsigned *)context;
6015 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6016 char *description = LLVMGetDiagInfoDescription(di);
6017
6018 if (severity == LLVMDSError) {
6019 *retval = 1;
6020 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6021 description);
6022 }
6023
6024 LLVMDisposeMessage(description);
6025 }
6026
6027 static unsigned ac_llvm_compile(LLVMModuleRef M,
6028 struct ac_shader_binary *binary,
6029 LLVMTargetMachineRef tm)
6030 {
6031 unsigned retval = 0;
6032 char *err;
6033 LLVMContextRef llvm_ctx;
6034 LLVMMemoryBufferRef out_buffer;
6035 unsigned buffer_size;
6036 const char *buffer_data;
6037 LLVMBool mem_err;
6038
6039 /* Setup Diagnostic Handler*/
6040 llvm_ctx = LLVMGetModuleContext(M);
6041
6042 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6043 &retval);
6044
6045 /* Compile IR*/
6046 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6047 &err, &out_buffer);
6048
6049 /* Process Errors/Warnings */
6050 if (mem_err) {
6051 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6052 free(err);
6053 retval = 1;
6054 goto out;
6055 }
6056
6057 /* Extract Shader Code*/
6058 buffer_size = LLVMGetBufferSize(out_buffer);
6059 buffer_data = LLVMGetBufferStart(out_buffer);
6060
6061 ac_elf_read(buffer_data, buffer_size, binary);
6062
6063 /* Clean up */
6064 LLVMDisposeMemoryBuffer(out_buffer);
6065
6066 out:
6067 return retval;
6068 }
6069
6070 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6071 LLVMModuleRef llvm_module,
6072 struct ac_shader_binary *binary,
6073 struct ac_shader_config *config,
6074 struct ac_shader_variant_info *shader_info,
6075 gl_shader_stage stage,
6076 bool dump_shader, bool supports_spill)
6077 {
6078 if (dump_shader)
6079 ac_dump_module(llvm_module);
6080
6081 memset(binary, 0, sizeof(*binary));
6082 int v = ac_llvm_compile(llvm_module, binary, tm);
6083 if (v) {
6084 fprintf(stderr, "compile failed\n");
6085 }
6086
6087 if (dump_shader)
6088 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6089
6090 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6091
6092 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6093 LLVMDisposeModule(llvm_module);
6094 LLVMContextDispose(ctx);
6095
6096 if (stage == MESA_SHADER_FRAGMENT) {
6097 shader_info->num_input_vgprs = 0;
6098 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6099 shader_info->num_input_vgprs += 2;
6100 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6101 shader_info->num_input_vgprs += 2;
6102 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6103 shader_info->num_input_vgprs += 2;
6104 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6105 shader_info->num_input_vgprs += 3;
6106 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6107 shader_info->num_input_vgprs += 2;
6108 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6109 shader_info->num_input_vgprs += 2;
6110 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6111 shader_info->num_input_vgprs += 2;
6112 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6113 shader_info->num_input_vgprs += 1;
6114 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6115 shader_info->num_input_vgprs += 1;
6116 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6117 shader_info->num_input_vgprs += 1;
6118 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6119 shader_info->num_input_vgprs += 1;
6120 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6121 shader_info->num_input_vgprs += 1;
6122 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6123 shader_info->num_input_vgprs += 1;
6124 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6125 shader_info->num_input_vgprs += 1;
6126 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6127 shader_info->num_input_vgprs += 1;
6128 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6129 shader_info->num_input_vgprs += 1;
6130 }
6131 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6132
6133 /* +3 for scratch wave offset and VCC */
6134 config->num_sgprs = MAX2(config->num_sgprs,
6135 shader_info->num_input_sgprs + 3);
6136 }
6137
6138 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6139 struct ac_shader_binary *binary,
6140 struct ac_shader_config *config,
6141 struct ac_shader_variant_info *shader_info,
6142 struct nir_shader *nir,
6143 const struct ac_nir_compiler_options *options,
6144 bool dump_shader)
6145 {
6146
6147 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6148 options);
6149
6150 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6151 switch (nir->stage) {
6152 case MESA_SHADER_COMPUTE:
6153 for (int i = 0; i < 3; ++i)
6154 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6155 break;
6156 case MESA_SHADER_FRAGMENT:
6157 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6158 break;
6159 case MESA_SHADER_GEOMETRY:
6160 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6161 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6162 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6163 shader_info->gs.invocations = nir->info.gs.invocations;
6164 break;
6165 case MESA_SHADER_TESS_EVAL:
6166 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6167 shader_info->tes.spacing = nir->info.tess.spacing;
6168 shader_info->tes.ccw = nir->info.tess.ccw;
6169 shader_info->tes.point_mode = nir->info.tess.point_mode;
6170 shader_info->tes.as_es = options->key.tes.as_es;
6171 break;
6172 case MESA_SHADER_TESS_CTRL:
6173 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6174 break;
6175 case MESA_SHADER_VERTEX:
6176 shader_info->vs.as_es = options->key.vs.as_es;
6177 shader_info->vs.as_ls = options->key.vs.as_ls;
6178 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6179 if (options->key.vs.as_ls)
6180 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6181 break;
6182 default:
6183 break;
6184 }
6185 }
6186
6187 static void
6188 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6189 {
6190 LLVMValueRef args[9];
6191 args[0] = ctx->gsvs_ring;
6192 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6193 args[3] = ctx->i32zero;
6194 args[4] = ctx->i32one; /* OFFEN */
6195 args[5] = ctx->i32zero; /* IDXEN */
6196 args[6] = ctx->i32one; /* GLC */
6197 args[7] = ctx->i32one; /* SLC */
6198 args[8] = ctx->i32zero; /* TFE */
6199
6200 int idx = 0;
6201
6202 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6203 int length = 4;
6204 int slot = idx;
6205 int slot_inc = 1;
6206 if (!(ctx->output_mask & (1ull << i)))
6207 continue;
6208
6209 if (i == VARYING_SLOT_CLIP_DIST0) {
6210 /* unpack clip and cull from a single set of slots */
6211 length = ctx->num_output_clips + ctx->num_output_culls;
6212 if (length > 4)
6213 slot_inc = 2;
6214 }
6215
6216 for (unsigned j = 0; j < length; j++) {
6217 LLVMValueRef value;
6218 args[2] = LLVMConstInt(ctx->i32,
6219 (slot * 4 + j) *
6220 ctx->gs_max_out_vertices * 16 * 4, false);
6221
6222 value = ac_build_intrinsic(&ctx->ac,
6223 "llvm.SI.buffer.load.dword.i32.i32",
6224 ctx->i32, args, 9,
6225 AC_FUNC_ATTR_READONLY |
6226 AC_FUNC_ATTR_LEGACY);
6227
6228 LLVMBuildStore(ctx->builder,
6229 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
6230 }
6231 idx += slot_inc;
6232 }
6233 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
6234 }
6235
6236 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6237 struct nir_shader *geom_shader,
6238 struct ac_shader_binary *binary,
6239 struct ac_shader_config *config,
6240 struct ac_shader_variant_info *shader_info,
6241 const struct ac_nir_compiler_options *options,
6242 bool dump_shader)
6243 {
6244 struct nir_to_llvm_context ctx = {0};
6245 ctx.context = LLVMContextCreate();
6246 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6247 ctx.options = options;
6248 ctx.shader_info = shader_info;
6249
6250 ac_llvm_context_init(&ctx.ac, ctx.context);
6251 ctx.ac.module = ctx.module;
6252
6253 ctx.is_gs_copy_shader = true;
6254 LLVMSetTarget(ctx.module, "amdgcn--");
6255 setup_types(&ctx);
6256
6257 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6258 ctx.ac.builder = ctx.builder;
6259 ctx.stage = MESA_SHADER_VERTEX;
6260
6261 create_function(&ctx);
6262
6263 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6264 ac_setup_rings(&ctx);
6265
6266 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6267 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6268
6269 nir_foreach_variable(variable, &geom_shader->outputs)
6270 handle_shader_output_decl(&ctx, variable);
6271
6272 ac_gs_copy_shader_emit(&ctx);
6273
6274 LLVMBuildRetVoid(ctx.builder);
6275
6276 ac_llvm_finalize_module(&ctx);
6277
6278 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6279 MESA_SHADER_VERTEX,
6280 dump_shader, options->supports_spill);
6281 }