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ac/nir: set the DA field when performing atomics on 3D images
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct ac_nir_context {
49 struct ac_llvm_context ac;
50 struct ac_shader_abi *abi;
51
52 gl_shader_stage stage;
53
54 struct hash_table *defs;
55 struct hash_table *phis;
56 struct hash_table *vars;
57
58 LLVMValueRef main_function;
59 LLVMBasicBlockRef continue_block;
60 LLVMBasicBlockRef break_block;
61
62 int num_locals;
63 LLVMValueRef *locals;
64 };
65
66 struct radv_shader_context {
67 struct ac_llvm_context ac;
68 const struct ac_nir_compiler_options *options;
69 struct ac_shader_variant_info *shader_info;
70 struct ac_shader_abi abi;
71
72 unsigned max_workgroup_size;
73 LLVMContextRef context;
74 LLVMValueRef main_function;
75
76 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
77 LLVMValueRef ring_offsets;
78
79 LLVMValueRef vertex_buffers;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef ls_out_layout;
83 LLVMValueRef es2gs_offset;
84
85 LLVMValueRef tcs_offchip_layout;
86 LLVMValueRef tcs_out_offsets;
87 LLVMValueRef tcs_out_layout;
88 LLVMValueRef tcs_in_layout;
89 LLVMValueRef oc_lds;
90 LLVMValueRef merged_wave_info;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tes_rel_patch_id;
93 LLVMValueRef tes_u;
94 LLVMValueRef tes_v;
95
96 LLVMValueRef gsvs_ring_stride;
97 LLVMValueRef gsvs_num_entries;
98 LLVMValueRef gs2vs_offset;
99 LLVMValueRef gs_wave_id;
100 LLVMValueRef gs_vtx_offset[6];
101
102 LLVMValueRef esgs_ring;
103 LLVMValueRef gsvs_ring;
104 LLVMValueRef hs_ring_tess_offchip;
105 LLVMValueRef hs_ring_tess_factor;
106
107 LLVMValueRef sample_pos_offset;
108 LLVMValueRef persp_sample, persp_center, persp_centroid;
109 LLVMValueRef linear_sample, linear_center, linear_centroid;
110
111 gl_shader_stage stage;
112
113 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
114
115 uint64_t input_mask;
116 uint64_t output_mask;
117 uint8_t num_output_clips;
118 uint8_t num_output_culls;
119
120 bool is_gs_copy_shader;
121 LLVMValueRef gs_next_vertex;
122 unsigned gs_max_out_vertices;
123
124 unsigned tes_primitive_mode;
125 uint64_t tess_outputs_written;
126 uint64_t tess_patch_outputs_written;
127
128 uint32_t tcs_patch_outputs_read;
129 uint64_t tcs_outputs_read;
130 uint32_t tcs_vertices_per_patch;
131 };
132
133 static inline struct radv_shader_context *
134 radv_shader_context_from_abi(struct ac_shader_abi *abi)
135 {
136 struct radv_shader_context *ctx = NULL;
137 return container_of(abi, ctx, abi);
138 }
139
140 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
141 const nir_deref_var *deref,
142 enum ac_descriptor_type desc_type,
143 const nir_tex_instr *instr,
144 bool image, bool write);
145
146 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
147 {
148 return (index * 4) + chan;
149 }
150
151 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
152 {
153 /* handle patch indices separate */
154 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
155 return 0;
156 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
157 return 1;
158 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
159 return 2 + (slot - VARYING_SLOT_PATCH0);
160
161 if (slot == VARYING_SLOT_POS)
162 return 0;
163 if (slot == VARYING_SLOT_PSIZ)
164 return 1;
165 if (slot == VARYING_SLOT_CLIP_DIST0)
166 return 2;
167 /* 3 is reserved for clip dist as well */
168 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
169 return 4 + (slot - VARYING_SLOT_VAR0);
170 unreachable("illegal slot in get unique index\n");
171 }
172
173 static void set_llvm_calling_convention(LLVMValueRef func,
174 gl_shader_stage stage)
175 {
176 enum radeon_llvm_calling_convention calling_conv;
177
178 switch (stage) {
179 case MESA_SHADER_VERTEX:
180 case MESA_SHADER_TESS_EVAL:
181 calling_conv = RADEON_LLVM_AMDGPU_VS;
182 break;
183 case MESA_SHADER_GEOMETRY:
184 calling_conv = RADEON_LLVM_AMDGPU_GS;
185 break;
186 case MESA_SHADER_TESS_CTRL:
187 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
188 break;
189 case MESA_SHADER_FRAGMENT:
190 calling_conv = RADEON_LLVM_AMDGPU_PS;
191 break;
192 case MESA_SHADER_COMPUTE:
193 calling_conv = RADEON_LLVM_AMDGPU_CS;
194 break;
195 default:
196 unreachable("Unhandle shader type");
197 }
198
199 LLVMSetFunctionCallConv(func, calling_conv);
200 }
201
202 #define MAX_ARGS 23
203 struct arg_info {
204 LLVMTypeRef types[MAX_ARGS];
205 LLVMValueRef *assign[MAX_ARGS];
206 unsigned array_params_mask;
207 uint8_t count;
208 uint8_t sgpr_count;
209 uint8_t num_sgprs_used;
210 uint8_t num_vgprs_used;
211 };
212
213 enum ac_arg_regfile {
214 ARG_SGPR,
215 ARG_VGPR,
216 };
217
218 static void
219 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
220 LLVMValueRef *param_ptr)
221 {
222 assert(info->count < MAX_ARGS);
223
224 info->assign[info->count] = param_ptr;
225 info->types[info->count] = type;
226 info->count++;
227
228 if (regfile == ARG_SGPR) {
229 info->num_sgprs_used += ac_get_type_size(type) / 4;
230 info->sgpr_count++;
231 } else {
232 assert(regfile == ARG_VGPR);
233 info->num_vgprs_used += ac_get_type_size(type) / 4;
234 }
235 }
236
237 static inline void
238 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
239 {
240 info->array_params_mask |= (1 << info->count);
241 add_arg(info, ARG_SGPR, type, param_ptr);
242 }
243
244 static void assign_arguments(LLVMValueRef main_function,
245 struct arg_info *info)
246 {
247 unsigned i;
248 for (i = 0; i < info->count; i++) {
249 if (info->assign[i])
250 *info->assign[i] = LLVMGetParam(main_function, i);
251 }
252 }
253
254 static LLVMValueRef
255 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
256 LLVMBuilderRef builder, LLVMTypeRef *return_types,
257 unsigned num_return_elems,
258 struct arg_info *args,
259 unsigned max_workgroup_size,
260 bool unsafe_math)
261 {
262 LLVMTypeRef main_function_type, ret_type;
263 LLVMBasicBlockRef main_function_body;
264
265 if (num_return_elems)
266 ret_type = LLVMStructTypeInContext(ctx, return_types,
267 num_return_elems, true);
268 else
269 ret_type = LLVMVoidTypeInContext(ctx);
270
271 /* Setup the function */
272 main_function_type =
273 LLVMFunctionType(ret_type, args->types, args->count, 0);
274 LLVMValueRef main_function =
275 LLVMAddFunction(module, "main", main_function_type);
276 main_function_body =
277 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
278 LLVMPositionBuilderAtEnd(builder, main_function_body);
279
280 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
281 for (unsigned i = 0; i < args->sgpr_count; ++i) {
282 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
283
284 if (args->array_params_mask & (1 << i)) {
285 LLVMValueRef P = LLVMGetParam(main_function, i);
286 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
287 ac_add_attr_dereferenceable(P, UINT64_MAX);
288 }
289 }
290
291 if (max_workgroup_size) {
292 ac_llvm_add_target_dep_function_attr(main_function,
293 "amdgpu-max-work-group-size",
294 max_workgroup_size);
295 }
296 if (unsafe_math) {
297 /* These were copied from some LLVM test. */
298 LLVMAddTargetDependentFunctionAttr(main_function,
299 "less-precise-fpmad",
300 "true");
301 LLVMAddTargetDependentFunctionAttr(main_function,
302 "no-infs-fp-math",
303 "true");
304 LLVMAddTargetDependentFunctionAttr(main_function,
305 "no-nans-fp-math",
306 "true");
307 LLVMAddTargetDependentFunctionAttr(main_function,
308 "unsafe-fp-math",
309 "true");
310 LLVMAddTargetDependentFunctionAttr(main_function,
311 "no-signed-zeros-fp-math",
312 "true");
313 }
314 return main_function;
315 }
316
317 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
318 LLVMValueRef param, unsigned rshift,
319 unsigned bitwidth)
320 {
321 LLVMValueRef value = param;
322 if (rshift)
323 value = LLVMBuildLShr(ctx->builder, value,
324 LLVMConstInt(ctx->i32, rshift, false), "");
325
326 if (rshift + bitwidth < 32) {
327 unsigned mask = (1 << bitwidth) - 1;
328 value = LLVMBuildAnd(ctx->builder, value,
329 LLVMConstInt(ctx->i32, mask, false), "");
330 }
331 return value;
332 }
333
334 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
335 {
336 switch (ctx->stage) {
337 case MESA_SHADER_TESS_CTRL:
338 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
339 case MESA_SHADER_TESS_EVAL:
340 return ctx->tes_rel_patch_id;
341 break;
342 default:
343 unreachable("Illegal stage");
344 }
345 }
346
347 /* Tessellation shaders pass outputs to the next shader using LDS.
348 *
349 * LS outputs = TCS inputs
350 * TCS outputs = TES inputs
351 *
352 * The LDS layout is:
353 * - TCS inputs for patch 0
354 * - TCS inputs for patch 1
355 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
356 * - ...
357 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
358 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
359 * - TCS outputs for patch 1
360 * - Per-patch TCS outputs for patch 1
361 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
362 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
363 * - ...
364 *
365 * All three shaders VS(LS), TCS, TES share the same LDS space.
366 */
367 static LLVMValueRef
368 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
369 {
370 if (ctx->stage == MESA_SHADER_VERTEX)
371 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
372 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
373 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
374 else {
375 assert(0);
376 return NULL;
377 }
378 }
379
380 static LLVMValueRef
381 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
382 {
383 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
384 }
385
386 static LLVMValueRef
387 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
388 {
389 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
390 }
391
392 static LLVMValueRef
393 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
394 {
395 return LLVMBuildMul(ctx->ac.builder,
396 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
397 LLVMConstInt(ctx->ac.i32, 4, false), "");
398 }
399
400 static LLVMValueRef
401 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
402 {
403 return LLVMBuildMul(ctx->ac.builder,
404 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
405 LLVMConstInt(ctx->ac.i32, 4, false), "");
406 }
407
408 static LLVMValueRef
409 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
410 {
411 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
412 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
413
414 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
415 }
416
417 static LLVMValueRef
418 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
419 {
420 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
421 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
422 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
423
424 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
425 LLVMBuildMul(ctx->ac.builder, patch_stride,
426 rel_patch_id, ""),
427 "");
428 }
429
430 static LLVMValueRef
431 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
432 {
433 LLVMValueRef patch0_patch_data_offset =
434 get_tcs_out_patch0_patch_data_offset(ctx);
435 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
436 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
437
438 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
439 LLVMBuildMul(ctx->ac.builder, patch_stride,
440 rel_patch_id, ""),
441 "");
442 }
443
444 static void
445 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
446 uint32_t indirect_offset)
447 {
448 ud_info->sgpr_idx = *sgpr_idx;
449 ud_info->num_sgprs = num_sgprs;
450 ud_info->indirect = indirect_offset > 0;
451 ud_info->indirect_offset = indirect_offset;
452 *sgpr_idx += num_sgprs;
453 }
454
455 static void
456 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
457 uint8_t num_sgprs)
458 {
459 struct ac_userdata_info *ud_info =
460 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
461 assert(ud_info);
462
463 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
464 }
465
466 static void
467 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
468 uint32_t indirect_offset)
469 {
470 struct ac_userdata_info *ud_info =
471 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
472 assert(ud_info);
473
474 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
475 }
476
477 struct user_sgpr_info {
478 bool need_ring_offsets;
479 uint8_t sgpr_count;
480 bool indirect_all_descriptor_sets;
481 };
482
483 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
484 gl_shader_stage stage)
485 {
486 switch (stage) {
487 case MESA_SHADER_VERTEX:
488 if (ctx->shader_info->info.needs_multiview_view_index ||
489 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
490 return true;
491 break;
492 case MESA_SHADER_TESS_EVAL:
493 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
494 return true;
495 break;
496 case MESA_SHADER_GEOMETRY:
497 case MESA_SHADER_TESS_CTRL:
498 if (ctx->shader_info->info.needs_multiview_view_index)
499 return true;
500 break;
501 default:
502 break;
503 }
504 return false;
505 }
506
507 static uint8_t
508 count_vs_user_sgprs(struct radv_shader_context *ctx)
509 {
510 uint8_t count = 0;
511
512 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
513 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
514
515 return count;
516 }
517
518 static void allocate_user_sgprs(struct radv_shader_context *ctx,
519 gl_shader_stage stage,
520 bool has_previous_stage,
521 gl_shader_stage previous_stage,
522 bool needs_view_index,
523 struct user_sgpr_info *user_sgpr_info)
524 {
525 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
526
527 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
528 if (stage == MESA_SHADER_GEOMETRY ||
529 stage == MESA_SHADER_VERTEX ||
530 stage == MESA_SHADER_TESS_CTRL ||
531 stage == MESA_SHADER_TESS_EVAL ||
532 ctx->is_gs_copy_shader)
533 user_sgpr_info->need_ring_offsets = true;
534
535 if (stage == MESA_SHADER_FRAGMENT &&
536 ctx->shader_info->info.ps.needs_sample_positions)
537 user_sgpr_info->need_ring_offsets = true;
538
539 /* 2 user sgprs will nearly always be allocated for scratch/rings */
540 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
541 user_sgpr_info->sgpr_count += 2;
542 }
543
544 switch (stage) {
545 case MESA_SHADER_COMPUTE:
546 if (ctx->shader_info->info.cs.uses_grid_size)
547 user_sgpr_info->sgpr_count += 3;
548 break;
549 case MESA_SHADER_FRAGMENT:
550 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
551 break;
552 case MESA_SHADER_VERTEX:
553 if (!ctx->is_gs_copy_shader)
554 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
555 if (ctx->options->key.vs.as_ls)
556 user_sgpr_info->sgpr_count++;
557 break;
558 case MESA_SHADER_TESS_CTRL:
559 if (has_previous_stage) {
560 if (previous_stage == MESA_SHADER_VERTEX)
561 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
562 user_sgpr_info->sgpr_count++;
563 }
564 user_sgpr_info->sgpr_count += 4;
565 break;
566 case MESA_SHADER_TESS_EVAL:
567 user_sgpr_info->sgpr_count += 1;
568 break;
569 case MESA_SHADER_GEOMETRY:
570 if (has_previous_stage) {
571 if (previous_stage == MESA_SHADER_VERTEX) {
572 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
573 } else {
574 user_sgpr_info->sgpr_count++;
575 }
576 }
577 user_sgpr_info->sgpr_count += 2;
578 break;
579 default:
580 break;
581 }
582
583 if (needs_view_index)
584 user_sgpr_info->sgpr_count++;
585
586 if (ctx->shader_info->info.loads_push_constants)
587 user_sgpr_info->sgpr_count += 2;
588
589 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
590 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
591
592 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
593 user_sgpr_info->sgpr_count += 2;
594 user_sgpr_info->indirect_all_descriptor_sets = true;
595 } else {
596 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
597 }
598 }
599
600 static void
601 declare_global_input_sgprs(struct radv_shader_context *ctx,
602 gl_shader_stage stage,
603 bool has_previous_stage,
604 gl_shader_stage previous_stage,
605 const struct user_sgpr_info *user_sgpr_info,
606 struct arg_info *args,
607 LLVMValueRef *desc_sets)
608 {
609 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
610 unsigned num_sets = ctx->options->layout ?
611 ctx->options->layout->num_sets : 0;
612 unsigned stage_mask = 1 << stage;
613
614 if (has_previous_stage)
615 stage_mask |= 1 << previous_stage;
616
617 /* 1 for each descriptor set */
618 if (!user_sgpr_info->indirect_all_descriptor_sets) {
619 for (unsigned i = 0; i < num_sets; ++i) {
620 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
621 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
622 add_array_arg(args, type,
623 &ctx->descriptor_sets[i]);
624 }
625 }
626 } else {
627 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
628 }
629
630 if (ctx->shader_info->info.loads_push_constants) {
631 /* 1 for push constants and dynamic descriptors */
632 add_array_arg(args, type, &ctx->abi.push_constants);
633 }
634 }
635
636 static void
637 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
638 gl_shader_stage stage,
639 bool has_previous_stage,
640 gl_shader_stage previous_stage,
641 struct arg_info *args)
642 {
643 if (!ctx->is_gs_copy_shader &&
644 (stage == MESA_SHADER_VERTEX ||
645 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
646 if (ctx->shader_info->info.vs.has_vertex_buffers) {
647 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
648 &ctx->vertex_buffers);
649 }
650 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
651 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
652 if (ctx->shader_info->info.vs.needs_draw_id) {
653 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
654 }
655 }
656 }
657
658 static void
659 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
660 {
661 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
662 if (!ctx->is_gs_copy_shader) {
663 if (ctx->options->key.vs.as_ls) {
664 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
665 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
666 } else {
667 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
668 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
669 }
670 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
671 }
672 }
673
674 static void
675 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
676 {
677 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
678 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
679 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
680 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
681 }
682
683 static void
684 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
685 bool has_previous_stage, gl_shader_stage previous_stage,
686 const struct user_sgpr_info *user_sgpr_info,
687 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
688 {
689 unsigned num_sets = ctx->options->layout ?
690 ctx->options->layout->num_sets : 0;
691 unsigned stage_mask = 1 << stage;
692
693 if (has_previous_stage)
694 stage_mask |= 1 << previous_stage;
695
696 if (!user_sgpr_info->indirect_all_descriptor_sets) {
697 for (unsigned i = 0; i < num_sets; ++i) {
698 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
699 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
700 set_loc_desc(ctx, i, user_sgpr_idx, 0);
701 } else
702 ctx->descriptor_sets[i] = NULL;
703 }
704 } else {
705 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
706 user_sgpr_idx, 2);
707
708 for (unsigned i = 0; i < num_sets; ++i) {
709 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
710 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
711 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
712 ctx->descriptor_sets[i] =
713 ac_build_load_to_sgpr(&ctx->ac,
714 desc_sets,
715 LLVMConstInt(ctx->ac.i32, i, false));
716
717 } else
718 ctx->descriptor_sets[i] = NULL;
719 }
720 ctx->shader_info->need_indirect_descriptor_sets = true;
721 }
722
723 if (ctx->shader_info->info.loads_push_constants) {
724 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
725 }
726 }
727
728 static void
729 set_vs_specific_input_locs(struct radv_shader_context *ctx,
730 gl_shader_stage stage, bool has_previous_stage,
731 gl_shader_stage previous_stage,
732 uint8_t *user_sgpr_idx)
733 {
734 if (!ctx->is_gs_copy_shader &&
735 (stage == MESA_SHADER_VERTEX ||
736 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
737 if (ctx->shader_info->info.vs.has_vertex_buffers) {
738 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
739 user_sgpr_idx, 2);
740 }
741
742 unsigned vs_num = 2;
743 if (ctx->shader_info->info.vs.needs_draw_id)
744 vs_num++;
745
746 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
747 user_sgpr_idx, vs_num);
748 }
749 }
750
751 static void create_function(struct radv_shader_context *ctx,
752 gl_shader_stage stage,
753 bool has_previous_stage,
754 gl_shader_stage previous_stage)
755 {
756 uint8_t user_sgpr_idx;
757 struct user_sgpr_info user_sgpr_info;
758 struct arg_info args = {};
759 LLVMValueRef desc_sets;
760 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
761 allocate_user_sgprs(ctx, stage, has_previous_stage,
762 previous_stage, needs_view_index, &user_sgpr_info);
763
764 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
765 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
766 &ctx->ring_offsets);
767 }
768
769 switch (stage) {
770 case MESA_SHADER_COMPUTE:
771 declare_global_input_sgprs(ctx, stage, has_previous_stage,
772 previous_stage, &user_sgpr_info,
773 &args, &desc_sets);
774
775 if (ctx->shader_info->info.cs.uses_grid_size) {
776 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
777 &ctx->abi.num_work_groups);
778 }
779
780 for (int i = 0; i < 3; i++) {
781 ctx->abi.workgroup_ids[i] = NULL;
782 if (ctx->shader_info->info.cs.uses_block_id[i]) {
783 add_arg(&args, ARG_SGPR, ctx->ac.i32,
784 &ctx->abi.workgroup_ids[i]);
785 }
786 }
787
788 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
789 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
790 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
791 &ctx->abi.local_invocation_ids);
792 break;
793 case MESA_SHADER_VERTEX:
794 declare_global_input_sgprs(ctx, stage, has_previous_stage,
795 previous_stage, &user_sgpr_info,
796 &args, &desc_sets);
797 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
798 previous_stage, &args);
799
800 if (needs_view_index)
801 add_arg(&args, ARG_SGPR, ctx->ac.i32,
802 &ctx->abi.view_index);
803 if (ctx->options->key.vs.as_es)
804 add_arg(&args, ARG_SGPR, ctx->ac.i32,
805 &ctx->es2gs_offset);
806 else if (ctx->options->key.vs.as_ls)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32,
808 &ctx->ls_out_layout);
809
810 declare_vs_input_vgprs(ctx, &args);
811 break;
812 case MESA_SHADER_TESS_CTRL:
813 if (has_previous_stage) {
814 // First 6 system regs
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->merged_wave_info);
818 add_arg(&args, ARG_SGPR, ctx->ac.i32,
819 &ctx->tess_factor_offset);
820
821 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
822 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
823 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
824
825 declare_global_input_sgprs(ctx, stage,
826 has_previous_stage,
827 previous_stage,
828 &user_sgpr_info, &args,
829 &desc_sets);
830 declare_vs_specific_input_sgprs(ctx, stage,
831 has_previous_stage,
832 previous_stage, &args);
833
834 add_arg(&args, ARG_SGPR, ctx->ac.i32,
835 &ctx->ls_out_layout);
836
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->tcs_offchip_layout);
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->tcs_out_offsets);
841 add_arg(&args, ARG_SGPR, ctx->ac.i32,
842 &ctx->tcs_out_layout);
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->tcs_in_layout);
845 if (needs_view_index)
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->abi.view_index);
848
849 add_arg(&args, ARG_VGPR, ctx->ac.i32,
850 &ctx->abi.tcs_patch_id);
851 add_arg(&args, ARG_VGPR, ctx->ac.i32,
852 &ctx->abi.tcs_rel_ids);
853
854 declare_vs_input_vgprs(ctx, &args);
855 } else {
856 declare_global_input_sgprs(ctx, stage,
857 has_previous_stage,
858 previous_stage,
859 &user_sgpr_info, &args,
860 &desc_sets);
861
862 add_arg(&args, ARG_SGPR, ctx->ac.i32,
863 &ctx->tcs_offchip_layout);
864 add_arg(&args, ARG_SGPR, ctx->ac.i32,
865 &ctx->tcs_out_offsets);
866 add_arg(&args, ARG_SGPR, ctx->ac.i32,
867 &ctx->tcs_out_layout);
868 add_arg(&args, ARG_SGPR, ctx->ac.i32,
869 &ctx->tcs_in_layout);
870 if (needs_view_index)
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->abi.view_index);
873
874 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tess_factor_offset);
877 add_arg(&args, ARG_VGPR, ctx->ac.i32,
878 &ctx->abi.tcs_patch_id);
879 add_arg(&args, ARG_VGPR, ctx->ac.i32,
880 &ctx->abi.tcs_rel_ids);
881 }
882 break;
883 case MESA_SHADER_TESS_EVAL:
884 declare_global_input_sgprs(ctx, stage, has_previous_stage,
885 previous_stage, &user_sgpr_info,
886 &args, &desc_sets);
887
888 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
889 if (needs_view_index)
890 add_arg(&args, ARG_SGPR, ctx->ac.i32,
891 &ctx->abi.view_index);
892
893 if (ctx->options->key.tes.as_es) {
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
895 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
896 add_arg(&args, ARG_SGPR, ctx->ac.i32,
897 &ctx->es2gs_offset);
898 } else {
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
900 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
901 }
902 declare_tes_input_vgprs(ctx, &args);
903 break;
904 case MESA_SHADER_GEOMETRY:
905 if (has_previous_stage) {
906 // First 6 system regs
907 add_arg(&args, ARG_SGPR, ctx->ac.i32,
908 &ctx->gs2vs_offset);
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->merged_wave_info);
911 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
912
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
915 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
916
917 declare_global_input_sgprs(ctx, stage,
918 has_previous_stage,
919 previous_stage,
920 &user_sgpr_info, &args,
921 &desc_sets);
922
923 if (previous_stage == MESA_SHADER_TESS_EVAL) {
924 add_arg(&args, ARG_SGPR, ctx->ac.i32,
925 &ctx->tcs_offchip_layout);
926 } else {
927 declare_vs_specific_input_sgprs(ctx, stage,
928 has_previous_stage,
929 previous_stage,
930 &args);
931 }
932
933 add_arg(&args, ARG_SGPR, ctx->ac.i32,
934 &ctx->gsvs_ring_stride);
935 add_arg(&args, ARG_SGPR, ctx->ac.i32,
936 &ctx->gsvs_num_entries);
937 if (needs_view_index)
938 add_arg(&args, ARG_SGPR, ctx->ac.i32,
939 &ctx->abi.view_index);
940
941 add_arg(&args, ARG_VGPR, ctx->ac.i32,
942 &ctx->gs_vtx_offset[0]);
943 add_arg(&args, ARG_VGPR, ctx->ac.i32,
944 &ctx->gs_vtx_offset[2]);
945 add_arg(&args, ARG_VGPR, ctx->ac.i32,
946 &ctx->abi.gs_prim_id);
947 add_arg(&args, ARG_VGPR, ctx->ac.i32,
948 &ctx->abi.gs_invocation_id);
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->gs_vtx_offset[4]);
951
952 if (previous_stage == MESA_SHADER_VERTEX) {
953 declare_vs_input_vgprs(ctx, &args);
954 } else {
955 declare_tes_input_vgprs(ctx, &args);
956 }
957 } else {
958 declare_global_input_sgprs(ctx, stage,
959 has_previous_stage,
960 previous_stage,
961 &user_sgpr_info, &args,
962 &desc_sets);
963
964 add_arg(&args, ARG_SGPR, ctx->ac.i32,
965 &ctx->gsvs_ring_stride);
966 add_arg(&args, ARG_SGPR, ctx->ac.i32,
967 &ctx->gsvs_num_entries);
968 if (needs_view_index)
969 add_arg(&args, ARG_SGPR, ctx->ac.i32,
970 &ctx->abi.view_index);
971
972 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
973 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
974 add_arg(&args, ARG_VGPR, ctx->ac.i32,
975 &ctx->gs_vtx_offset[0]);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[1]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->abi.gs_prim_id);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->gs_vtx_offset[2]);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[3]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[4]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[5]);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->abi.gs_invocation_id);
990 }
991 break;
992 case MESA_SHADER_FRAGMENT:
993 declare_global_input_sgprs(ctx, stage, has_previous_stage,
994 previous_stage, &user_sgpr_info,
995 &args, &desc_sets);
996
997 if (ctx->shader_info->info.ps.needs_sample_positions)
998 add_arg(&args, ARG_SGPR, ctx->ac.i32,
999 &ctx->sample_pos_offset);
1000
1001 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1002 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1003 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1005 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1009 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1010 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1014 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1018 break;
1019 default:
1020 unreachable("Shader stage not implemented");
1021 }
1022
1023 ctx->main_function = create_llvm_function(
1024 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1025 ctx->max_workgroup_size,
1026 ctx->options->unsafe_math);
1027 set_llvm_calling_convention(ctx->main_function, stage);
1028
1029
1030 ctx->shader_info->num_input_vgprs = 0;
1031 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1032
1033 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1034
1035 if (ctx->stage != MESA_SHADER_FRAGMENT)
1036 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1037
1038 assign_arguments(ctx->main_function, &args);
1039
1040 user_sgpr_idx = 0;
1041
1042 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1043 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1044 &user_sgpr_idx, 2);
1045 if (ctx->options->supports_spill) {
1046 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1047 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1048 NULL, 0, AC_FUNC_ATTR_READNONE);
1049 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1050 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1051 }
1052 }
1053
1054 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1055 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1056 if (has_previous_stage)
1057 user_sgpr_idx = 0;
1058
1059 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1060 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1061
1062 switch (stage) {
1063 case MESA_SHADER_COMPUTE:
1064 if (ctx->shader_info->info.cs.uses_grid_size) {
1065 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1066 &user_sgpr_idx, 3);
1067 }
1068 break;
1069 case MESA_SHADER_VERTEX:
1070 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1071 previous_stage, &user_sgpr_idx);
1072 if (ctx->abi.view_index)
1073 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1074 if (ctx->options->key.vs.as_ls) {
1075 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1076 &user_sgpr_idx, 1);
1077 }
1078 break;
1079 case MESA_SHADER_TESS_CTRL:
1080 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1081 previous_stage, &user_sgpr_idx);
1082 if (has_previous_stage)
1083 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1084 &user_sgpr_idx, 1);
1085 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1086 if (ctx->abi.view_index)
1087 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1088 break;
1089 case MESA_SHADER_TESS_EVAL:
1090 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1091 if (ctx->abi.view_index)
1092 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1093 break;
1094 case MESA_SHADER_GEOMETRY:
1095 if (has_previous_stage) {
1096 if (previous_stage == MESA_SHADER_VERTEX)
1097 set_vs_specific_input_locs(ctx, stage,
1098 has_previous_stage,
1099 previous_stage,
1100 &user_sgpr_idx);
1101 else
1102 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1103 &user_sgpr_idx, 1);
1104 }
1105 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1106 &user_sgpr_idx, 2);
1107 if (ctx->abi.view_index)
1108 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1109 break;
1110 case MESA_SHADER_FRAGMENT:
1111 if (ctx->shader_info->info.ps.needs_sample_positions) {
1112 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1113 &user_sgpr_idx, 1);
1114 }
1115 break;
1116 default:
1117 unreachable("Shader stage not implemented");
1118 }
1119
1120 if (stage == MESA_SHADER_TESS_CTRL ||
1121 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1122 /* GFX9 has the ESGS ring buffer in LDS. */
1123 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1124 ac_declare_lds_as_pointer(&ctx->ac);
1125 }
1126
1127 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1128 }
1129
1130 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1131 LLVMValueRef value, unsigned count)
1132 {
1133 unsigned num_components = ac_get_llvm_num_components(value);
1134 if (count == num_components)
1135 return value;
1136
1137 LLVMValueRef masks[] = {
1138 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1139 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1140
1141 if (count == 1)
1142 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1143 "");
1144
1145 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1146 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1147 }
1148
1149 static void
1150 build_store_values_extended(struct ac_llvm_context *ac,
1151 LLVMValueRef *values,
1152 unsigned value_count,
1153 unsigned value_stride,
1154 LLVMValueRef vec)
1155 {
1156 LLVMBuilderRef builder = ac->builder;
1157 unsigned i;
1158
1159 for (i = 0; i < value_count; i++) {
1160 LLVMValueRef ptr = values[i * value_stride];
1161 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1162 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1163 LLVMBuildStore(builder, value, ptr);
1164 }
1165 }
1166
1167 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1168 const nir_ssa_def *def)
1169 {
1170 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1171 if (def->num_components > 1) {
1172 type = LLVMVectorType(type, def->num_components);
1173 }
1174 return type;
1175 }
1176
1177 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1178 {
1179 assert(src.is_ssa);
1180 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1181 return (LLVMValueRef)entry->data;
1182 }
1183
1184 static LLVMValueRef
1185 get_memory_ptr(struct ac_nir_context *ctx, nir_src src)
1186 {
1187 LLVMValueRef ptr = get_src(ctx, src);
1188 ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ac.lds, &ptr, 1, "");
1189 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1190
1191 return LLVMBuildBitCast(ctx->ac.builder, ptr,
1192 LLVMPointerType(ctx->ac.i32, addr_space), "");
1193 }
1194
1195 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1196 const struct nir_block *b)
1197 {
1198 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1199 return (LLVMBasicBlockRef)entry->data;
1200 }
1201
1202 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1203 nir_alu_src src,
1204 unsigned num_components)
1205 {
1206 LLVMValueRef value = get_src(ctx, src.src);
1207 bool need_swizzle = false;
1208
1209 assert(value);
1210 LLVMTypeRef type = LLVMTypeOf(value);
1211 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1212 ? LLVMGetVectorSize(type)
1213 : 1;
1214
1215 for (unsigned i = 0; i < num_components; ++i) {
1216 assert(src.swizzle[i] < src_components);
1217 if (src.swizzle[i] != i)
1218 need_swizzle = true;
1219 }
1220
1221 if (need_swizzle || num_components != src_components) {
1222 LLVMValueRef masks[] = {
1223 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1224 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1225 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1226 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1227
1228 if (src_components > 1 && num_components == 1) {
1229 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1230 masks[0], "");
1231 } else if (src_components == 1 && num_components > 1) {
1232 LLVMValueRef values[] = {value, value, value, value};
1233 value = ac_build_gather_values(&ctx->ac, values, num_components);
1234 } else {
1235 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1236 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1237 swizzle, "");
1238 }
1239 }
1240 assert(!src.negate);
1241 assert(!src.abs);
1242 return value;
1243 }
1244
1245 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1246 LLVMIntPredicate pred, LLVMValueRef src0,
1247 LLVMValueRef src1)
1248 {
1249 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1250 return LLVMBuildSelect(ctx->builder, result,
1251 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1252 ctx->i32_0, "");
1253 }
1254
1255 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1256 LLVMRealPredicate pred, LLVMValueRef src0,
1257 LLVMValueRef src1)
1258 {
1259 LLVMValueRef result;
1260 src0 = ac_to_float(ctx, src0);
1261 src1 = ac_to_float(ctx, src1);
1262 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1263 return LLVMBuildSelect(ctx->builder, result,
1264 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1265 ctx->i32_0, "");
1266 }
1267
1268 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1269 const char *intrin,
1270 LLVMTypeRef result_type,
1271 LLVMValueRef src0)
1272 {
1273 char name[64];
1274 LLVMValueRef params[] = {
1275 ac_to_float(ctx, src0),
1276 };
1277
1278 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1279 ac_get_elem_bits(ctx, result_type));
1280 assert(length < sizeof(name));
1281 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1282 }
1283
1284 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1285 const char *intrin,
1286 LLVMTypeRef result_type,
1287 LLVMValueRef src0, LLVMValueRef src1)
1288 {
1289 char name[64];
1290 LLVMValueRef params[] = {
1291 ac_to_float(ctx, src0),
1292 ac_to_float(ctx, src1),
1293 };
1294
1295 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1296 ac_get_elem_bits(ctx, result_type));
1297 assert(length < sizeof(name));
1298 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1299 }
1300
1301 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1302 const char *intrin,
1303 LLVMTypeRef result_type,
1304 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1305 {
1306 char name[64];
1307 LLVMValueRef params[] = {
1308 ac_to_float(ctx, src0),
1309 ac_to_float(ctx, src1),
1310 ac_to_float(ctx, src2),
1311 };
1312
1313 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1314 ac_get_elem_bits(ctx, result_type));
1315 assert(length < sizeof(name));
1316 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1317 }
1318
1319 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1320 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1321 {
1322 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1323 ctx->i32_0, "");
1324 return LLVMBuildSelect(ctx->builder, v, ac_to_integer(ctx, src1),
1325 ac_to_integer(ctx, src2), "");
1326 }
1327
1328 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1329 LLVMIntPredicate pred,
1330 LLVMValueRef src0, LLVMValueRef src1)
1331 {
1332 return LLVMBuildSelect(ctx->builder,
1333 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1334 src0,
1335 src1, "");
1336
1337 }
1338 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1339 LLVMValueRef src0)
1340 {
1341 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1342 LLVMBuildNeg(ctx->builder, src0, ""));
1343 }
1344
1345 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1346 LLVMValueRef src0,
1347 unsigned bitsize)
1348 {
1349 LLVMValueRef cmp, val, zero, one;
1350 LLVMTypeRef type;
1351
1352 if (bitsize == 32) {
1353 type = ctx->f32;
1354 zero = ctx->f32_0;
1355 one = ctx->f32_1;
1356 } else {
1357 type = ctx->f64;
1358 zero = ctx->f64_0;
1359 one = ctx->f64_1;
1360 }
1361
1362 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1363 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1364 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1365 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1366 return val;
1367 }
1368
1369 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1370 LLVMValueRef src0, unsigned bitsize)
1371 {
1372 LLVMValueRef cmp, val, zero, one;
1373 LLVMTypeRef type;
1374
1375 if (bitsize == 32) {
1376 type = ctx->i32;
1377 zero = ctx->i32_0;
1378 one = ctx->i32_1;
1379 } else {
1380 type = ctx->i64;
1381 zero = ctx->i64_0;
1382 one = ctx->i64_1;
1383 }
1384
1385 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1386 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1387 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1388 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1389 return val;
1390 }
1391
1392 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1393 LLVMValueRef src0, unsigned bitsize)
1394 {
1395 LLVMTypeRef type;
1396 char *intr;
1397
1398 if (bitsize == 32) {
1399 intr = "llvm.floor.f32";
1400 type = ctx->f32;
1401 } else {
1402 intr = "llvm.floor.f64";
1403 type = ctx->f64;
1404 }
1405
1406 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1407 LLVMValueRef params[] = {
1408 fsrc0,
1409 };
1410 LLVMValueRef floor = ac_build_intrinsic(ctx, intr, type, params, 1,
1411 AC_FUNC_ATTR_READNONE);
1412 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1413 }
1414
1415 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1416 const char *intrin,
1417 LLVMValueRef src0, LLVMValueRef src1)
1418 {
1419 LLVMTypeRef ret_type;
1420 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1421 LLVMValueRef res;
1422 LLVMValueRef params[] = { src0, src1 };
1423 ret_type = LLVMStructTypeInContext(ctx->context, types,
1424 2, true);
1425
1426 res = ac_build_intrinsic(ctx, intrin, ret_type,
1427 params, 2, AC_FUNC_ATTR_READNONE);
1428
1429 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1430 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1431 return res;
1432 }
1433
1434 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1435 LLVMValueRef src0)
1436 {
1437 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1438 }
1439
1440 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1441 LLVMValueRef src0)
1442 {
1443 src0 = ac_to_float(ctx, src0);
1444 return LLVMBuildSExt(ctx->builder,
1445 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1446 ctx->i32, "");
1447 }
1448
1449 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1450 LLVMValueRef src0,
1451 unsigned bitsize)
1452 {
1453 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1454
1455 if (bitsize == 32)
1456 return result;
1457
1458 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1459 }
1460
1461 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1462 LLVMValueRef src0)
1463 {
1464 return LLVMBuildSExt(ctx->builder,
1465 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1466 ctx->i32, "");
1467 }
1468
1469 static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx,
1470 LLVMValueRef src0)
1471 {
1472 LLVMValueRef result;
1473 LLVMValueRef cond = NULL;
1474
1475 src0 = ac_to_float(ctx, src0);
1476 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1477
1478 if (ctx->chip_class >= VI) {
1479 LLVMValueRef args[2];
1480 /* Check if the result is a denormal - and flush to 0 if so. */
1481 args[0] = result;
1482 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1483 cond = ac_build_intrinsic(ctx, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1484 }
1485
1486 /* need to convert back up to f32 */
1487 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1488
1489 if (ctx->chip_class >= VI)
1490 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1491 else {
1492 /* for SI/CIK */
1493 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1494 * so compare the result and flush to 0 if it's smaller.
1495 */
1496 LLVMValueRef temp, cond2;
1497 temp = emit_intrin_1f_param(ctx, "llvm.fabs", ctx->f32, result);
1498 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1499 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1500 temp, "");
1501 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1502 temp, ctx->f32_0, "");
1503 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1504 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1505 }
1506 return result;
1507 }
1508
1509 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1510 LLVMValueRef src0, LLVMValueRef src1)
1511 {
1512 LLVMValueRef dst64, result;
1513 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1514 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1515
1516 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1517 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1518 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1519 return result;
1520 }
1521
1522 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1523 LLVMValueRef src0, LLVMValueRef src1)
1524 {
1525 LLVMValueRef dst64, result;
1526 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1527 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1528
1529 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1530 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1531 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1532 return result;
1533 }
1534
1535 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1536 bool is_signed,
1537 const LLVMValueRef srcs[3])
1538 {
1539 LLVMValueRef result;
1540 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1541
1542 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1543 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1544 return result;
1545 }
1546
1547 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1548 LLVMValueRef src0, LLVMValueRef src1,
1549 LLVMValueRef src2, LLVMValueRef src3)
1550 {
1551 LLVMValueRef bfi_args[3], result;
1552
1553 bfi_args[0] = LLVMBuildShl(ctx->builder,
1554 LLVMBuildSub(ctx->builder,
1555 LLVMBuildShl(ctx->builder,
1556 ctx->i32_1,
1557 src3, ""),
1558 ctx->i32_1, ""),
1559 src2, "");
1560 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1561 bfi_args[2] = src0;
1562
1563 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1564
1565 /* Calculate:
1566 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1567 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1568 */
1569 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1570 LLVMBuildAnd(ctx->builder, bfi_args[0],
1571 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1572
1573 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1574 return result;
1575 }
1576
1577 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1578 LLVMValueRef src0)
1579 {
1580 LLVMValueRef comp[2];
1581
1582 src0 = ac_to_float(ctx, src0);
1583 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1584 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1585
1586 return ac_build_cvt_pkrtz_f16(ctx, comp);
1587 }
1588
1589 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1590 LLVMValueRef src0)
1591 {
1592 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1593 LLVMValueRef temps[2], result, val;
1594 int i;
1595
1596 for (i = 0; i < 2; i++) {
1597 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1598 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1599 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1600 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1601 }
1602
1603 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1604 ctx->i32_0, "");
1605 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1606 ctx->i32_1, "");
1607 return result;
1608 }
1609
1610 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1611 nir_op op,
1612 LLVMValueRef src0)
1613 {
1614 unsigned mask;
1615 int idx;
1616 LLVMValueRef result;
1617
1618 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1619 mask = AC_TID_MASK_LEFT;
1620 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1621 mask = AC_TID_MASK_TOP;
1622 else
1623 mask = AC_TID_MASK_TOP_LEFT;
1624
1625 /* for DDX we want to next X pixel, DDY next Y pixel. */
1626 if (op == nir_op_fddx_fine ||
1627 op == nir_op_fddx_coarse ||
1628 op == nir_op_fddx)
1629 idx = 1;
1630 else
1631 idx = 2;
1632
1633 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1634 return result;
1635 }
1636
1637 /*
1638 * this takes an I,J coordinate pair,
1639 * and works out the X and Y derivatives.
1640 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1641 */
1642 static LLVMValueRef emit_ddxy_interp(
1643 struct ac_nir_context *ctx,
1644 LLVMValueRef interp_ij)
1645 {
1646 LLVMValueRef result[4], a;
1647 unsigned i;
1648
1649 for (i = 0; i < 2; i++) {
1650 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1651 LLVMConstInt(ctx->ac.i32, i, false), "");
1652 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1653 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1654 }
1655 return ac_build_gather_values(&ctx->ac, result, 4);
1656 }
1657
1658 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1659 {
1660 LLVMValueRef src[4], result = NULL;
1661 unsigned num_components = instr->dest.dest.ssa.num_components;
1662 unsigned src_components;
1663 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1664
1665 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1666 switch (instr->op) {
1667 case nir_op_vec2:
1668 case nir_op_vec3:
1669 case nir_op_vec4:
1670 src_components = 1;
1671 break;
1672 case nir_op_pack_half_2x16:
1673 src_components = 2;
1674 break;
1675 case nir_op_unpack_half_2x16:
1676 src_components = 1;
1677 break;
1678 default:
1679 src_components = num_components;
1680 break;
1681 }
1682 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1683 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1684
1685 switch (instr->op) {
1686 case nir_op_fmov:
1687 case nir_op_imov:
1688 result = src[0];
1689 break;
1690 case nir_op_fneg:
1691 src[0] = ac_to_float(&ctx->ac, src[0]);
1692 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1693 break;
1694 case nir_op_ineg:
1695 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1696 break;
1697 case nir_op_inot:
1698 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1699 break;
1700 case nir_op_iadd:
1701 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1702 break;
1703 case nir_op_fadd:
1704 src[0] = ac_to_float(&ctx->ac, src[0]);
1705 src[1] = ac_to_float(&ctx->ac, src[1]);
1706 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1707 break;
1708 case nir_op_fsub:
1709 src[0] = ac_to_float(&ctx->ac, src[0]);
1710 src[1] = ac_to_float(&ctx->ac, src[1]);
1711 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1712 break;
1713 case nir_op_isub:
1714 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1715 break;
1716 case nir_op_imul:
1717 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1718 break;
1719 case nir_op_imod:
1720 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1721 break;
1722 case nir_op_umod:
1723 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1724 break;
1725 case nir_op_fmod:
1726 src[0] = ac_to_float(&ctx->ac, src[0]);
1727 src[1] = ac_to_float(&ctx->ac, src[1]);
1728 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1729 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1730 ac_to_float_type(&ctx->ac, def_type), result);
1731 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1732 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1733 break;
1734 case nir_op_frem:
1735 src[0] = ac_to_float(&ctx->ac, src[0]);
1736 src[1] = ac_to_float(&ctx->ac, src[1]);
1737 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1738 break;
1739 case nir_op_irem:
1740 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1741 break;
1742 case nir_op_idiv:
1743 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1744 break;
1745 case nir_op_udiv:
1746 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1747 break;
1748 case nir_op_fmul:
1749 src[0] = ac_to_float(&ctx->ac, src[0]);
1750 src[1] = ac_to_float(&ctx->ac, src[1]);
1751 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1752 break;
1753 case nir_op_frcp:
1754 src[0] = ac_to_float(&ctx->ac, src[0]);
1755 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1756 src[0]);
1757 break;
1758 case nir_op_iand:
1759 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1760 break;
1761 case nir_op_ior:
1762 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1763 break;
1764 case nir_op_ixor:
1765 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1766 break;
1767 case nir_op_ishl:
1768 result = LLVMBuildShl(ctx->ac.builder, src[0],
1769 LLVMBuildZExt(ctx->ac.builder, src[1],
1770 LLVMTypeOf(src[0]), ""),
1771 "");
1772 break;
1773 case nir_op_ishr:
1774 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1775 LLVMBuildZExt(ctx->ac.builder, src[1],
1776 LLVMTypeOf(src[0]), ""),
1777 "");
1778 break;
1779 case nir_op_ushr:
1780 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1781 LLVMBuildZExt(ctx->ac.builder, src[1],
1782 LLVMTypeOf(src[0]), ""),
1783 "");
1784 break;
1785 case nir_op_ilt:
1786 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1787 break;
1788 case nir_op_ine:
1789 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1790 break;
1791 case nir_op_ieq:
1792 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1793 break;
1794 case nir_op_ige:
1795 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1796 break;
1797 case nir_op_ult:
1798 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1799 break;
1800 case nir_op_uge:
1801 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1802 break;
1803 case nir_op_feq:
1804 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1805 break;
1806 case nir_op_fne:
1807 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1808 break;
1809 case nir_op_flt:
1810 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1811 break;
1812 case nir_op_fge:
1813 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1814 break;
1815 case nir_op_fabs:
1816 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1817 ac_to_float_type(&ctx->ac, def_type), src[0]);
1818 break;
1819 case nir_op_iabs:
1820 result = emit_iabs(&ctx->ac, src[0]);
1821 break;
1822 case nir_op_imax:
1823 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1824 break;
1825 case nir_op_imin:
1826 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1827 break;
1828 case nir_op_umax:
1829 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1830 break;
1831 case nir_op_umin:
1832 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1833 break;
1834 case nir_op_isign:
1835 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1836 break;
1837 case nir_op_fsign:
1838 src[0] = ac_to_float(&ctx->ac, src[0]);
1839 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1840 break;
1841 case nir_op_ffloor:
1842 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1843 ac_to_float_type(&ctx->ac, def_type), src[0]);
1844 break;
1845 case nir_op_ftrunc:
1846 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1847 ac_to_float_type(&ctx->ac, def_type), src[0]);
1848 break;
1849 case nir_op_fceil:
1850 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1851 ac_to_float_type(&ctx->ac, def_type), src[0]);
1852 break;
1853 case nir_op_fround_even:
1854 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1855 ac_to_float_type(&ctx->ac, def_type),src[0]);
1856 break;
1857 case nir_op_ffract:
1858 result = emit_ffract(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1859 break;
1860 case nir_op_fsin:
1861 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1862 ac_to_float_type(&ctx->ac, def_type), src[0]);
1863 break;
1864 case nir_op_fcos:
1865 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1866 ac_to_float_type(&ctx->ac, def_type), src[0]);
1867 break;
1868 case nir_op_fsqrt:
1869 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1870 ac_to_float_type(&ctx->ac, def_type), src[0]);
1871 break;
1872 case nir_op_fexp2:
1873 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1874 ac_to_float_type(&ctx->ac, def_type), src[0]);
1875 break;
1876 case nir_op_flog2:
1877 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1878 ac_to_float_type(&ctx->ac, def_type), src[0]);
1879 break;
1880 case nir_op_frsq:
1881 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1882 ac_to_float_type(&ctx->ac, def_type), src[0]);
1883 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1884 result);
1885 break;
1886 case nir_op_fpow:
1887 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1888 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1889 break;
1890 case nir_op_fmax:
1891 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1892 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1893 if (ctx->ac.chip_class < GFX9 &&
1894 instr->dest.dest.ssa.bit_size == 32) {
1895 /* Only pre-GFX9 chips do not flush denorms. */
1896 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1897 ac_to_float_type(&ctx->ac, def_type),
1898 result);
1899 }
1900 break;
1901 case nir_op_fmin:
1902 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1903 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1904 if (ctx->ac.chip_class < GFX9 &&
1905 instr->dest.dest.ssa.bit_size == 32) {
1906 /* Only pre-GFX9 chips do not flush denorms. */
1907 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1908 ac_to_float_type(&ctx->ac, def_type),
1909 result);
1910 }
1911 break;
1912 case nir_op_ffma:
1913 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1914 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1915 break;
1916 case nir_op_ibitfield_extract:
1917 result = emit_bitfield_extract(&ctx->ac, true, src);
1918 break;
1919 case nir_op_ubitfield_extract:
1920 result = emit_bitfield_extract(&ctx->ac, false, src);
1921 break;
1922 case nir_op_bitfield_insert:
1923 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1924 break;
1925 case nir_op_bitfield_reverse:
1926 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1927 break;
1928 case nir_op_bit_count:
1929 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1930 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1931 else {
1932 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1933 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1934 }
1935 break;
1936 case nir_op_vec2:
1937 case nir_op_vec3:
1938 case nir_op_vec4:
1939 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1940 src[i] = ac_to_integer(&ctx->ac, src[i]);
1941 result = ac_build_gather_values(&ctx->ac, src, num_components);
1942 break;
1943 case nir_op_f2i32:
1944 case nir_op_f2i64:
1945 src[0] = ac_to_float(&ctx->ac, src[0]);
1946 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1947 break;
1948 case nir_op_f2u32:
1949 case nir_op_f2u64:
1950 src[0] = ac_to_float(&ctx->ac, src[0]);
1951 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1952 break;
1953 case nir_op_i2f32:
1954 case nir_op_i2f64:
1955 src[0] = ac_to_integer(&ctx->ac, src[0]);
1956 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1957 break;
1958 case nir_op_u2f32:
1959 case nir_op_u2f64:
1960 src[0] = ac_to_integer(&ctx->ac, src[0]);
1961 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1962 break;
1963 case nir_op_f2f64:
1964 src[0] = ac_to_float(&ctx->ac, src[0]);
1965 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1966 break;
1967 case nir_op_f2f32:
1968 src[0] = ac_to_float(&ctx->ac, src[0]);
1969 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1970 break;
1971 case nir_op_u2u32:
1972 case nir_op_u2u64:
1973 src[0] = ac_to_integer(&ctx->ac, src[0]);
1974 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1975 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1976 else
1977 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1978 break;
1979 case nir_op_i2i32:
1980 case nir_op_i2i64:
1981 src[0] = ac_to_integer(&ctx->ac, src[0]);
1982 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1983 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1984 else
1985 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1986 break;
1987 case nir_op_bcsel:
1988 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1989 break;
1990 case nir_op_find_lsb:
1991 src[0] = ac_to_integer(&ctx->ac, src[0]);
1992 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1993 break;
1994 case nir_op_ufind_msb:
1995 src[0] = ac_to_integer(&ctx->ac, src[0]);
1996 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1997 break;
1998 case nir_op_ifind_msb:
1999 src[0] = ac_to_integer(&ctx->ac, src[0]);
2000 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
2001 break;
2002 case nir_op_uadd_carry:
2003 src[0] = ac_to_integer(&ctx->ac, src[0]);
2004 src[1] = ac_to_integer(&ctx->ac, src[1]);
2005 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
2006 break;
2007 case nir_op_usub_borrow:
2008 src[0] = ac_to_integer(&ctx->ac, src[0]);
2009 src[1] = ac_to_integer(&ctx->ac, src[1]);
2010 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
2011 break;
2012 case nir_op_b2f:
2013 result = emit_b2f(&ctx->ac, src[0]);
2014 break;
2015 case nir_op_f2b:
2016 result = emit_f2b(&ctx->ac, src[0]);
2017 break;
2018 case nir_op_b2i:
2019 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2020 break;
2021 case nir_op_i2b:
2022 src[0] = ac_to_integer(&ctx->ac, src[0]);
2023 result = emit_i2b(&ctx->ac, src[0]);
2024 break;
2025 case nir_op_fquantize2f16:
2026 result = emit_f2f16(&ctx->ac, src[0]);
2027 break;
2028 case nir_op_umul_high:
2029 src[0] = ac_to_integer(&ctx->ac, src[0]);
2030 src[1] = ac_to_integer(&ctx->ac, src[1]);
2031 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2032 break;
2033 case nir_op_imul_high:
2034 src[0] = ac_to_integer(&ctx->ac, src[0]);
2035 src[1] = ac_to_integer(&ctx->ac, src[1]);
2036 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2037 break;
2038 case nir_op_pack_half_2x16:
2039 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2040 break;
2041 case nir_op_unpack_half_2x16:
2042 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2043 break;
2044 case nir_op_fddx:
2045 case nir_op_fddy:
2046 case nir_op_fddx_fine:
2047 case nir_op_fddy_fine:
2048 case nir_op_fddx_coarse:
2049 case nir_op_fddy_coarse:
2050 result = emit_ddxy(ctx, instr->op, src[0]);
2051 break;
2052
2053 case nir_op_unpack_64_2x32_split_x: {
2054 assert(ac_get_llvm_num_components(src[0]) == 1);
2055 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2056 ctx->ac.v2i32,
2057 "");
2058 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2059 ctx->ac.i32_0, "");
2060 break;
2061 }
2062
2063 case nir_op_unpack_64_2x32_split_y: {
2064 assert(ac_get_llvm_num_components(src[0]) == 1);
2065 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2066 ctx->ac.v2i32,
2067 "");
2068 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2069 ctx->ac.i32_1, "");
2070 break;
2071 }
2072
2073 case nir_op_pack_64_2x32_split: {
2074 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2075 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2076 src[0], ctx->ac.i32_0, "");
2077 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2078 src[1], ctx->ac.i32_1, "");
2079 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2080 break;
2081 }
2082
2083 default:
2084 fprintf(stderr, "Unknown NIR alu instr: ");
2085 nir_print_instr(&instr->instr, stderr);
2086 fprintf(stderr, "\n");
2087 abort();
2088 }
2089
2090 if (result) {
2091 assert(instr->dest.dest.is_ssa);
2092 result = ac_to_integer(&ctx->ac, result);
2093 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2094 result);
2095 }
2096 }
2097
2098 static void visit_load_const(struct ac_nir_context *ctx,
2099 const nir_load_const_instr *instr)
2100 {
2101 LLVMValueRef values[4], value = NULL;
2102 LLVMTypeRef element_type =
2103 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2104
2105 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2106 switch (instr->def.bit_size) {
2107 case 32:
2108 values[i] = LLVMConstInt(element_type,
2109 instr->value.u32[i], false);
2110 break;
2111 case 64:
2112 values[i] = LLVMConstInt(element_type,
2113 instr->value.u64[i], false);
2114 break;
2115 default:
2116 fprintf(stderr,
2117 "unsupported nir load_const bit_size: %d\n",
2118 instr->def.bit_size);
2119 abort();
2120 }
2121 }
2122 if (instr->def.num_components > 1) {
2123 value = LLVMConstVector(values, instr->def.num_components);
2124 } else
2125 value = values[0];
2126
2127 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2128 }
2129
2130 static LLVMValueRef cast_ptr(struct ac_llvm_context *ctx, LLVMValueRef ptr,
2131 LLVMTypeRef type)
2132 {
2133 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2134 return LLVMBuildBitCast(ctx->builder, ptr,
2135 LLVMPointerType(type, addr_space), "");
2136 }
2137
2138 static LLVMValueRef
2139 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2140 {
2141 LLVMValueRef size =
2142 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2143 LLVMConstInt(ctx->ac.i32, 2, false), "");
2144
2145 /* VI only */
2146 if (ctx->ac.chip_class == VI && in_elements) {
2147 /* On VI, the descriptor contains the size in bytes,
2148 * but TXQ must return the size in elements.
2149 * The stride is always non-zero for resources using TXQ.
2150 */
2151 LLVMValueRef stride =
2152 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2153 ctx->ac.i32_1, "");
2154 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2155 LLVMConstInt(ctx->ac.i32, 16, false), "");
2156 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2157 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2158
2159 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2160 }
2161 return size;
2162 }
2163
2164 /**
2165 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2166 * intrinsic names).
2167 */
2168 static void build_int_type_name(
2169 LLVMTypeRef type,
2170 char *buf, unsigned bufsize)
2171 {
2172 assert(bufsize >= 6);
2173
2174 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2175 snprintf(buf, bufsize, "v%ui32",
2176 LLVMGetVectorSize(type));
2177 else
2178 strcpy(buf, "i32");
2179 }
2180
2181 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2182 struct ac_image_args *args,
2183 const nir_tex_instr *instr)
2184 {
2185 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2186 LLVMValueRef coord = args->addr;
2187 LLVMValueRef half_texel[2];
2188 LLVMValueRef compare_cube_wa = NULL;
2189 LLVMValueRef result;
2190 int c;
2191 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2192
2193 //TODO Rect
2194 {
2195 struct ac_image_args txq_args = { 0 };
2196
2197 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2198 txq_args.opcode = ac_image_get_resinfo;
2199 txq_args.dmask = 0xf;
2200 txq_args.addr = ctx->i32_0;
2201 txq_args.resource = args->resource;
2202 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2203
2204 for (c = 0; c < 2; c++) {
2205 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2206 LLVMConstInt(ctx->i32, c, false), "");
2207 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2208 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2209 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2210 LLVMConstReal(ctx->f32, -0.5), "");
2211 }
2212 }
2213
2214 LLVMValueRef orig_coords = args->addr;
2215
2216 for (c = 0; c < 2; c++) {
2217 LLVMValueRef tmp;
2218 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2219 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2220 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2221 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2222 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2223 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2224 }
2225
2226
2227 /*
2228 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2229 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2230 * workaround by sampling using a scaled type and converting.
2231 * This is taken from amdgpu-pro shaders.
2232 */
2233 /* NOTE this produces some ugly code compared to amdgpu-pro,
2234 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2235 * and then reads them back. -pro generates two selects,
2236 * one s_cmp for the descriptor rewriting
2237 * one v_cmp for the coordinate and result changes.
2238 */
2239 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2240 LLVMValueRef tmp, tmp2;
2241
2242 /* workaround 8/8/8/8 uint/sint cube gather bug */
2243 /* first detect it then change to a scaled read and f2i */
2244 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2245 tmp2 = tmp;
2246
2247 /* extract the DATA_FORMAT */
2248 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2249 LLVMConstInt(ctx->i32, 6, false), false);
2250
2251 /* is the DATA_FORMAT == 8_8_8_8 */
2252 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2253
2254 if (stype == GLSL_TYPE_UINT)
2255 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2256 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2257 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2258 else
2259 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2260 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2261 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2262
2263 /* replace the NUM FORMAT in the descriptor */
2264 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2265 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2266
2267 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2268
2269 /* don't modify the coordinates for this case */
2270 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2271 }
2272 args->addr = coord;
2273 result = ac_build_image_opcode(ctx, args);
2274
2275 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2276 LLVMValueRef tmp, tmp2;
2277
2278 /* if the cube workaround is in place, f2i the result. */
2279 for (c = 0; c < 4; c++) {
2280 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2281 if (stype == GLSL_TYPE_UINT)
2282 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2283 else
2284 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2285 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2286 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2287 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2288 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2289 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2290 }
2291 }
2292 return result;
2293 }
2294
2295 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2296 const nir_tex_instr *instr,
2297 bool lod_is_zero,
2298 struct ac_image_args *args)
2299 {
2300 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2301 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2302
2303 return ac_build_buffer_load_format(&ctx->ac,
2304 args->resource,
2305 args->addr,
2306 ctx->ac.i32_0,
2307 util_last_bit(mask),
2308 false, true);
2309 }
2310
2311 args->opcode = ac_image_sample;
2312 args->compare = instr->is_shadow;
2313
2314 switch (instr->op) {
2315 case nir_texop_txf:
2316 case nir_texop_txf_ms:
2317 case nir_texop_samples_identical:
2318 args->opcode = lod_is_zero ||
2319 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2320 ac_image_load : ac_image_load_mip;
2321 args->compare = false;
2322 args->offset = false;
2323 break;
2324 case nir_texop_txb:
2325 args->bias = true;
2326 break;
2327 case nir_texop_txl:
2328 if (lod_is_zero)
2329 args->level_zero = true;
2330 else
2331 args->lod = true;
2332 break;
2333 case nir_texop_txs:
2334 case nir_texop_query_levels:
2335 args->opcode = ac_image_get_resinfo;
2336 break;
2337 case nir_texop_tex:
2338 if (ctx->stage != MESA_SHADER_FRAGMENT)
2339 args->level_zero = true;
2340 break;
2341 case nir_texop_txd:
2342 args->deriv = true;
2343 break;
2344 case nir_texop_tg4:
2345 args->opcode = ac_image_gather4;
2346 args->level_zero = true;
2347 break;
2348 case nir_texop_lod:
2349 args->opcode = ac_image_get_lod;
2350 args->compare = false;
2351 args->offset = false;
2352 break;
2353 default:
2354 break;
2355 }
2356
2357 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2358 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2359 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2360 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2361 }
2362 }
2363 return ac_build_image_opcode(&ctx->ac, args);
2364 }
2365
2366 static LLVMValueRef
2367 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2368 unsigned desc_set, unsigned binding)
2369 {
2370 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2371 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2372 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2373 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2374 unsigned base_offset = layout->binding[binding].offset;
2375 LLVMValueRef offset, stride;
2376
2377 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2378 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2379 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2380 layout->binding[binding].dynamic_offset_offset;
2381 desc_ptr = ctx->abi.push_constants;
2382 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2383 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2384 } else
2385 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2386
2387 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2388 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
2389 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
2390
2391 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2392 desc_ptr = cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
2393 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2394
2395 return desc_ptr;
2396 }
2397
2398 static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
2399 nir_intrinsic_instr *instr)
2400 {
2401 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2402 LLVMValueRef index = get_src(ctx, instr->src[1]);
2403
2404 LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
2405 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2406 return result;
2407 }
2408
2409 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
2410 nir_intrinsic_instr *instr)
2411 {
2412 LLVMValueRef ptr, addr;
2413
2414 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2415 addr = LLVMBuildAdd(ctx->ac.builder, addr,
2416 get_src(ctx, instr->src[0]), "");
2417
2418 ptr = ac_build_gep0(&ctx->ac, ctx->abi->push_constants, addr);
2419 ptr = cast_ptr(&ctx->ac, ptr, get_def_type(ctx, &instr->dest.ssa));
2420
2421 return LLVMBuildLoad(ctx->ac.builder, ptr, "");
2422 }
2423
2424 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2425 const nir_intrinsic_instr *instr)
2426 {
2427 LLVMValueRef index = get_src(ctx, instr->src[0]);
2428
2429 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2430 }
2431
2432 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2433 {
2434 uint32_t new_mask = 0;
2435 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2436 if (mask & (1u << i))
2437 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2438 return new_mask;
2439 }
2440
2441 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2442 unsigned start, unsigned count)
2443 {
2444 LLVMTypeRef type = LLVMTypeOf(src);
2445
2446 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2447 assert(start == 0);
2448 assert(count == 1);
2449 return src;
2450 }
2451
2452 unsigned src_elements = LLVMGetVectorSize(type);
2453 assert(start < src_elements);
2454 assert(start + count <= src_elements);
2455
2456 if (start == 0 && count == src_elements)
2457 return src;
2458
2459 if (count == 1)
2460 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2461
2462 assert(count <= 8);
2463 LLVMValueRef indices[8];
2464 for (unsigned i = 0; i < count; ++i)
2465 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2466
2467 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2468 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2469 }
2470
2471 static void visit_store_ssbo(struct ac_nir_context *ctx,
2472 nir_intrinsic_instr *instr)
2473 {
2474 const char *store_name;
2475 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2476 LLVMTypeRef data_type = ctx->ac.f32;
2477 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2478 int components_32bit = elem_size_mult * instr->num_components;
2479 unsigned writemask = nir_intrinsic_write_mask(instr);
2480 LLVMValueRef base_data, base_offset;
2481 LLVMValueRef params[6];
2482
2483 params[1] = ctx->abi->load_ssbo(ctx->abi,
2484 get_src(ctx, instr->src[1]), true);
2485 params[2] = ctx->ac.i32_0; /* vindex */
2486 params[4] = ctx->ac.i1false; /* glc */
2487 params[5] = ctx->ac.i1false; /* slc */
2488
2489 if (components_32bit > 1)
2490 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2491
2492 writemask = widen_mask(writemask, elem_size_mult);
2493
2494 base_data = ac_to_float(&ctx->ac, src_data);
2495 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2496 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2497 data_type, "");
2498 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2499 while (writemask) {
2500 int start, count;
2501 LLVMValueRef data;
2502 LLVMValueRef offset;
2503
2504 u_bit_scan_consecutive_range(&writemask, &start, &count);
2505
2506 /* Due to an LLVM limitation, split 3-element writes
2507 * into a 2-element and a 1-element write. */
2508 if (count == 3) {
2509 writemask |= 1 << (start + 2);
2510 count = 2;
2511 }
2512
2513 if (count > 4) {
2514 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2515 count = 4;
2516 }
2517
2518 if (count == 4) {
2519 store_name = "llvm.amdgcn.buffer.store.v4f32";
2520 } else if (count == 2) {
2521 store_name = "llvm.amdgcn.buffer.store.v2f32";
2522
2523 } else {
2524 assert(count == 1);
2525 store_name = "llvm.amdgcn.buffer.store.f32";
2526 }
2527 data = extract_vector_range(&ctx->ac, base_data, start, count);
2528
2529 offset = base_offset;
2530 if (start != 0) {
2531 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2532 }
2533 params[0] = data;
2534 params[3] = offset;
2535 ac_build_intrinsic(&ctx->ac, store_name,
2536 ctx->ac.voidt, params, 6, 0);
2537 }
2538 }
2539
2540 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2541 const nir_intrinsic_instr *instr)
2542 {
2543 const char *name;
2544 LLVMValueRef params[6];
2545 int arg_count = 0;
2546
2547 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2548 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2549 }
2550 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2551 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2552 get_src(ctx, instr->src[0]),
2553 true);
2554 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2555 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2556 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2557
2558 switch (instr->intrinsic) {
2559 case nir_intrinsic_ssbo_atomic_add:
2560 name = "llvm.amdgcn.buffer.atomic.add";
2561 break;
2562 case nir_intrinsic_ssbo_atomic_imin:
2563 name = "llvm.amdgcn.buffer.atomic.smin";
2564 break;
2565 case nir_intrinsic_ssbo_atomic_umin:
2566 name = "llvm.amdgcn.buffer.atomic.umin";
2567 break;
2568 case nir_intrinsic_ssbo_atomic_imax:
2569 name = "llvm.amdgcn.buffer.atomic.smax";
2570 break;
2571 case nir_intrinsic_ssbo_atomic_umax:
2572 name = "llvm.amdgcn.buffer.atomic.umax";
2573 break;
2574 case nir_intrinsic_ssbo_atomic_and:
2575 name = "llvm.amdgcn.buffer.atomic.and";
2576 break;
2577 case nir_intrinsic_ssbo_atomic_or:
2578 name = "llvm.amdgcn.buffer.atomic.or";
2579 break;
2580 case nir_intrinsic_ssbo_atomic_xor:
2581 name = "llvm.amdgcn.buffer.atomic.xor";
2582 break;
2583 case nir_intrinsic_ssbo_atomic_exchange:
2584 name = "llvm.amdgcn.buffer.atomic.swap";
2585 break;
2586 case nir_intrinsic_ssbo_atomic_comp_swap:
2587 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2588 break;
2589 default:
2590 abort();
2591 }
2592
2593 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2594 }
2595
2596 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2597 const nir_intrinsic_instr *instr)
2598 {
2599 LLVMValueRef results[2];
2600 int load_components;
2601 int num_components = instr->num_components;
2602 if (instr->dest.ssa.bit_size == 64)
2603 num_components *= 2;
2604
2605 for (int i = 0; i < num_components; i += load_components) {
2606 load_components = MIN2(num_components - i, 4);
2607 const char *load_name;
2608 LLVMTypeRef data_type = ctx->ac.f32;
2609 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2610 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2611
2612 if (load_components == 3)
2613 data_type = LLVMVectorType(ctx->ac.f32, 4);
2614 else if (load_components > 1)
2615 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2616
2617 if (load_components >= 3)
2618 load_name = "llvm.amdgcn.buffer.load.v4f32";
2619 else if (load_components == 2)
2620 load_name = "llvm.amdgcn.buffer.load.v2f32";
2621 else if (load_components == 1)
2622 load_name = "llvm.amdgcn.buffer.load.f32";
2623 else
2624 unreachable("unhandled number of components");
2625
2626 LLVMValueRef params[] = {
2627 ctx->abi->load_ssbo(ctx->abi,
2628 get_src(ctx, instr->src[0]),
2629 false),
2630 ctx->ac.i32_0,
2631 offset,
2632 ctx->ac.i1false,
2633 ctx->ac.i1false,
2634 };
2635
2636 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2637 }
2638
2639 assume(results[0]);
2640 LLVMValueRef ret = results[0];
2641 if (num_components > 4 || num_components == 3) {
2642 LLVMValueRef masks[] = {
2643 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2644 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2645 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2646 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2647 };
2648
2649 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2650 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2651 results[num_components > 4 ? 1 : 0], swizzle, "");
2652 }
2653
2654 return LLVMBuildBitCast(ctx->ac.builder, ret,
2655 get_def_type(ctx, &instr->dest.ssa), "");
2656 }
2657
2658 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2659 const nir_intrinsic_instr *instr)
2660 {
2661 LLVMValueRef ret;
2662 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2663 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2664 int num_components = instr->num_components;
2665
2666 if (ctx->abi->load_ubo)
2667 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2668
2669 if (instr->dest.ssa.bit_size == 64)
2670 num_components *= 2;
2671
2672 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2673 NULL, 0, false, false, true, true);
2674 ret = trim_vector(&ctx->ac, ret, num_components);
2675 return LLVMBuildBitCast(ctx->ac.builder, ret,
2676 get_def_type(ctx, &instr->dest.ssa), "");
2677 }
2678
2679 static void
2680 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2681 bool vs_in, unsigned *vertex_index_out,
2682 LLVMValueRef *vertex_index_ref,
2683 unsigned *const_out, LLVMValueRef *indir_out)
2684 {
2685 unsigned const_offset = 0;
2686 nir_deref *tail = &deref->deref;
2687 LLVMValueRef offset = NULL;
2688
2689 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2690 tail = tail->child;
2691 nir_deref_array *deref_array = nir_deref_as_array(tail);
2692 if (vertex_index_out)
2693 *vertex_index_out = deref_array->base_offset;
2694
2695 if (vertex_index_ref) {
2696 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2697 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2698 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2699 }
2700 *vertex_index_ref = vtx;
2701 }
2702 }
2703
2704 if (deref->var->data.compact) {
2705 assert(tail->child->deref_type == nir_deref_type_array);
2706 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2707 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2708 /* We always lower indirect dereferences for "compact" array vars. */
2709 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2710
2711 const_offset = deref_array->base_offset;
2712 goto out;
2713 }
2714
2715 while (tail->child != NULL) {
2716 const struct glsl_type *parent_type = tail->type;
2717 tail = tail->child;
2718
2719 if (tail->deref_type == nir_deref_type_array) {
2720 nir_deref_array *deref_array = nir_deref_as_array(tail);
2721 LLVMValueRef index, stride, local_offset;
2722 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2723
2724 const_offset += size * deref_array->base_offset;
2725 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2726 continue;
2727
2728 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2729 index = get_src(ctx, deref_array->indirect);
2730 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2731 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2732
2733 if (offset)
2734 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2735 else
2736 offset = local_offset;
2737 } else if (tail->deref_type == nir_deref_type_struct) {
2738 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2739
2740 for (unsigned i = 0; i < deref_struct->index; i++) {
2741 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2742 const_offset += glsl_count_attribute_slots(ft, vs_in);
2743 }
2744 } else
2745 unreachable("unsupported deref type");
2746
2747 }
2748 out:
2749 if (const_offset && offset)
2750 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2751 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2752 "");
2753
2754 *const_out = const_offset;
2755 *indir_out = offset;
2756 }
2757
2758
2759 /* The offchip buffer layout for TCS->TES is
2760 *
2761 * - attribute 0 of patch 0 vertex 0
2762 * - attribute 0 of patch 0 vertex 1
2763 * - attribute 0 of patch 0 vertex 2
2764 * ...
2765 * - attribute 0 of patch 1 vertex 0
2766 * - attribute 0 of patch 1 vertex 1
2767 * ...
2768 * - attribute 1 of patch 0 vertex 0
2769 * - attribute 1 of patch 0 vertex 1
2770 * ...
2771 * - per patch attribute 0 of patch 0
2772 * - per patch attribute 0 of patch 1
2773 * ...
2774 *
2775 * Note that every attribute has 4 components.
2776 */
2777 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
2778 LLVMValueRef vertex_index,
2779 LLVMValueRef param_index)
2780 {
2781 LLVMValueRef base_addr, vertices_per_patch, num_patches;
2782 LLVMValueRef param_stride, constant16;
2783 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2784
2785 vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
2786 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2787
2788 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2789 if (vertex_index) {
2790 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2791 vertices_per_patch, "");
2792
2793 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2794 vertex_index, "");
2795
2796 param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
2797 num_patches, "");
2798 } else {
2799 base_addr = rel_patch_id;
2800 param_stride = num_patches;
2801 }
2802
2803 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2804 LLVMBuildMul(ctx->ac.builder, param_index,
2805 param_stride, ""), "");
2806
2807 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
2808
2809 if (!vertex_index) {
2810 LLVMValueRef patch_data_offset =
2811 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2812
2813 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2814 patch_data_offset, "");
2815 }
2816 return base_addr;
2817 }
2818
2819 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
2820 unsigned param,
2821 unsigned const_index,
2822 bool is_compact,
2823 LLVMValueRef vertex_index,
2824 LLVMValueRef indir_index)
2825 {
2826 LLVMValueRef param_index;
2827
2828 if (indir_index)
2829 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
2830 indir_index, "");
2831 else {
2832 if (const_index && !is_compact)
2833 param += const_index;
2834 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2835 }
2836 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2837 }
2838
2839 static void
2840 mark_tess_output(struct radv_shader_context *ctx,
2841 bool is_patch, uint32_t param)
2842
2843 {
2844 if (is_patch) {
2845 ctx->tess_patch_outputs_written |= (1ull << param);
2846 } else
2847 ctx->tess_outputs_written |= (1ull << param);
2848 }
2849
2850 static LLVMValueRef
2851 get_dw_address(struct radv_shader_context *ctx,
2852 LLVMValueRef dw_addr,
2853 unsigned param,
2854 unsigned const_index,
2855 bool compact_const_index,
2856 LLVMValueRef vertex_index,
2857 LLVMValueRef stride,
2858 LLVMValueRef indir_index)
2859
2860 {
2861
2862 if (vertex_index) {
2863 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2864 LLVMBuildMul(ctx->ac.builder,
2865 vertex_index,
2866 stride, ""), "");
2867 }
2868
2869 if (indir_index)
2870 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2871 LLVMBuildMul(ctx->ac.builder, indir_index,
2872 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2873 else if (const_index && !compact_const_index)
2874 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2875 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2876
2877 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2878 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2879
2880 if (const_index && compact_const_index)
2881 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2882 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2883 return dw_addr;
2884 }
2885
2886 static LLVMValueRef
2887 load_tcs_varyings(struct ac_shader_abi *abi,
2888 LLVMValueRef vertex_index,
2889 LLVMValueRef indir_index,
2890 unsigned const_index,
2891 unsigned location,
2892 unsigned driver_location,
2893 unsigned component,
2894 unsigned num_components,
2895 bool is_patch,
2896 bool is_compact,
2897 bool load_input)
2898 {
2899 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2900 LLVMValueRef dw_addr, stride;
2901 LLVMValueRef value[4], result;
2902 unsigned param = shader_io_get_unique_index(location);
2903
2904 if (load_input) {
2905 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2906 dw_addr = get_tcs_in_current_patch_offset(ctx);
2907 } else {
2908 if (!is_patch) {
2909 stride = get_tcs_out_vertex_stride(ctx);
2910 dw_addr = get_tcs_out_current_patch_offset(ctx);
2911 } else {
2912 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2913 stride = NULL;
2914 }
2915 }
2916
2917 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2918 indir_index);
2919
2920 for (unsigned i = 0; i < num_components + component; i++) {
2921 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2922 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2923 ctx->ac.i32_1, "");
2924 }
2925 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2926 return result;
2927 }
2928
2929 static void
2930 store_tcs_output(struct ac_shader_abi *abi,
2931 LLVMValueRef vertex_index,
2932 LLVMValueRef param_index,
2933 unsigned const_index,
2934 unsigned location,
2935 unsigned driver_location,
2936 LLVMValueRef src,
2937 unsigned component,
2938 bool is_patch,
2939 bool is_compact,
2940 unsigned writemask)
2941 {
2942 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2943 LLVMValueRef dw_addr;
2944 LLVMValueRef stride = NULL;
2945 LLVMValueRef buf_addr = NULL;
2946 unsigned param;
2947 bool store_lds = true;
2948
2949 if (is_patch) {
2950 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2951 store_lds = false;
2952 } else {
2953 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2954 store_lds = false;
2955 }
2956
2957 param = shader_io_get_unique_index(location);
2958 if (location == VARYING_SLOT_CLIP_DIST0 &&
2959 is_compact && const_index > 3) {
2960 const_index -= 3;
2961 param++;
2962 }
2963
2964 if (!is_patch) {
2965 stride = get_tcs_out_vertex_stride(ctx);
2966 dw_addr = get_tcs_out_current_patch_offset(ctx);
2967 } else {
2968 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2969 }
2970
2971 mark_tess_output(ctx, is_patch, param);
2972
2973 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2974 param_index);
2975 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2976 vertex_index, param_index);
2977
2978 bool is_tess_factor = false;
2979 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2980 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2981 is_tess_factor = true;
2982
2983 unsigned base = is_compact ? const_index : 0;
2984 for (unsigned chan = 0; chan < 8; chan++) {
2985 if (!(writemask & (1 << chan)))
2986 continue;
2987 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2988
2989 if (store_lds || is_tess_factor) {
2990 LLVMValueRef dw_addr_chan =
2991 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2992 LLVMConstInt(ctx->ac.i32, chan, false), "");
2993 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2994 }
2995
2996 if (!is_tess_factor && writemask != 0xF)
2997 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2998 buf_addr, ctx->oc_lds,
2999 4 * (base + chan), 1, 0, true, false);
3000 }
3001
3002 if (writemask == 0xF) {
3003 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
3004 buf_addr, ctx->oc_lds,
3005 (base * 4), 1, 0, true, false);
3006 }
3007 }
3008
3009 static LLVMValueRef
3010 load_tes_input(struct ac_shader_abi *abi,
3011 LLVMValueRef vertex_index,
3012 LLVMValueRef param_index,
3013 unsigned const_index,
3014 unsigned location,
3015 unsigned driver_location,
3016 unsigned component,
3017 unsigned num_components,
3018 bool is_patch,
3019 bool is_compact,
3020 bool load_input)
3021 {
3022 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3023 LLVMValueRef buf_addr;
3024 LLVMValueRef result;
3025 unsigned param = shader_io_get_unique_index(location);
3026
3027 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3028 const_index -= 3;
3029 param++;
3030 }
3031
3032 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3033 is_compact, vertex_index, param_index);
3034
3035 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3036 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
3037
3038 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3039 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3040 result = trim_vector(&ctx->ac, result, num_components);
3041 return result;
3042 }
3043
3044 static LLVMValueRef
3045 load_gs_input(struct ac_shader_abi *abi,
3046 unsigned location,
3047 unsigned driver_location,
3048 unsigned component,
3049 unsigned num_components,
3050 unsigned vertex_index,
3051 unsigned const_index,
3052 LLVMTypeRef type)
3053 {
3054 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3055 LLVMValueRef vtx_offset;
3056 unsigned param, vtx_offset_param;
3057 LLVMValueRef value[4], result;
3058
3059 vtx_offset_param = vertex_index;
3060 assert(vtx_offset_param < 6);
3061 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
3062 LLVMConstInt(ctx->ac.i32, 4, false), "");
3063
3064 param = shader_io_get_unique_index(location);
3065
3066 for (unsigned i = component; i < num_components + component; i++) {
3067 if (ctx->ac.chip_class >= GFX9) {
3068 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3069 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3070 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3071 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3072 } else {
3073 LLVMValueRef soffset =
3074 LLVMConstInt(ctx->ac.i32,
3075 (param * 4 + i + const_index) * 256,
3076 false);
3077
3078 value[i] = ac_build_buffer_load(&ctx->ac,
3079 ctx->esgs_ring, 1,
3080 ctx->ac.i32_0,
3081 vtx_offset, soffset,
3082 0, 1, 0, true, false);
3083
3084 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
3085 type, "");
3086 }
3087 }
3088 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3089 result = ac_to_integer(&ctx->ac, result);
3090 return result;
3091 }
3092
3093 static LLVMValueRef
3094 build_gep_for_deref(struct ac_nir_context *ctx,
3095 nir_deref_var *deref)
3096 {
3097 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3098 assert(entry->data);
3099 LLVMValueRef val = entry->data;
3100 nir_deref *tail = deref->deref.child;
3101 while (tail != NULL) {
3102 LLVMValueRef offset;
3103 switch (tail->deref_type) {
3104 case nir_deref_type_array: {
3105 nir_deref_array *array = nir_deref_as_array(tail);
3106 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3107 if (array->deref_array_type ==
3108 nir_deref_array_type_indirect) {
3109 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3110 get_src(ctx,
3111 array->indirect),
3112 "");
3113 }
3114 break;
3115 }
3116 case nir_deref_type_struct: {
3117 nir_deref_struct *deref_struct =
3118 nir_deref_as_struct(tail);
3119 offset = LLVMConstInt(ctx->ac.i32,
3120 deref_struct->index, 0);
3121 break;
3122 }
3123 default:
3124 unreachable("bad deref type");
3125 }
3126 val = ac_build_gep0(&ctx->ac, val, offset);
3127 tail = tail->child;
3128 }
3129 return val;
3130 }
3131
3132 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3133 nir_intrinsic_instr *instr,
3134 bool load_inputs)
3135 {
3136 LLVMValueRef result;
3137 LLVMValueRef vertex_index = NULL;
3138 LLVMValueRef indir_index = NULL;
3139 unsigned const_index = 0;
3140 unsigned location = instr->variables[0]->var->data.location;
3141 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3142 const bool is_patch = instr->variables[0]->var->data.patch;
3143 const bool is_compact = instr->variables[0]->var->data.compact;
3144
3145 get_deref_offset(ctx, instr->variables[0],
3146 false, NULL, is_patch ? NULL : &vertex_index,
3147 &const_index, &indir_index);
3148
3149 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3150 const_index, location, driver_location,
3151 instr->variables[0]->var->data.location_frac,
3152 instr->num_components,
3153 is_patch, is_compact, load_inputs);
3154 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3155 }
3156
3157 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3158 nir_intrinsic_instr *instr)
3159 {
3160 LLVMValueRef values[8];
3161 int idx = instr->variables[0]->var->data.driver_location;
3162 int ve = instr->dest.ssa.num_components;
3163 unsigned comp = instr->variables[0]->var->data.location_frac;
3164 LLVMValueRef indir_index;
3165 LLVMValueRef ret;
3166 unsigned const_index;
3167 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3168 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3169 instr->variables[0]->var->data.mode == nir_var_shader_in;
3170 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3171 &const_index, &indir_index);
3172
3173 if (instr->dest.ssa.bit_size == 64)
3174 ve *= 2;
3175
3176 switch (instr->variables[0]->var->data.mode) {
3177 case nir_var_shader_in:
3178 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3179 ctx->stage == MESA_SHADER_TESS_EVAL) {
3180 return load_tess_varyings(ctx, instr, true);
3181 }
3182
3183 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3184 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3185 LLVMValueRef indir_index;
3186 unsigned const_index, vertex_index;
3187 get_deref_offset(ctx, instr->variables[0],
3188 false, &vertex_index, NULL,
3189 &const_index, &indir_index);
3190
3191 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3192 instr->variables[0]->var->data.driver_location,
3193 instr->variables[0]->var->data.location_frac, ve,
3194 vertex_index, const_index, type);
3195 }
3196
3197 for (unsigned chan = comp; chan < ve + comp; chan++) {
3198 if (indir_index) {
3199 unsigned count = glsl_count_attribute_slots(
3200 instr->variables[0]->var->type,
3201 ctx->stage == MESA_SHADER_VERTEX);
3202 count -= chan / 4;
3203 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3204 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3205 stride, false, true);
3206
3207 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3208 tmp_vec,
3209 indir_index, "");
3210 } else
3211 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3212 }
3213 break;
3214 case nir_var_local:
3215 for (unsigned chan = 0; chan < ve; chan++) {
3216 if (indir_index) {
3217 unsigned count = glsl_count_attribute_slots(
3218 instr->variables[0]->var->type, false);
3219 count -= chan / 4;
3220 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3221 &ctx->ac, ctx->locals + idx + chan, count,
3222 stride, true, true);
3223
3224 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3225 tmp_vec,
3226 indir_index, "");
3227 } else {
3228 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3229 }
3230 }
3231 break;
3232 case nir_var_shared: {
3233 LLVMValueRef address = build_gep_for_deref(ctx,
3234 instr->variables[0]);
3235 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3236 return LLVMBuildBitCast(ctx->ac.builder, val,
3237 get_def_type(ctx, &instr->dest.ssa),
3238 "");
3239 }
3240 case nir_var_shader_out:
3241 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3242 return load_tess_varyings(ctx, instr, false);
3243 }
3244
3245 for (unsigned chan = comp; chan < ve + comp; chan++) {
3246 if (indir_index) {
3247 unsigned count = glsl_count_attribute_slots(
3248 instr->variables[0]->var->type, false);
3249 count -= chan / 4;
3250 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3251 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3252 stride, true, true);
3253
3254 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3255 tmp_vec,
3256 indir_index, "");
3257 } else {
3258 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3259 ctx->abi->outputs[idx + chan + const_index * stride],
3260 "");
3261 }
3262 }
3263 break;
3264 default:
3265 unreachable("unhandle variable mode");
3266 }
3267 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3268 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3269 }
3270
3271 static void
3272 visit_store_var(struct ac_nir_context *ctx,
3273 nir_intrinsic_instr *instr)
3274 {
3275 LLVMValueRef temp_ptr, value;
3276 int idx = instr->variables[0]->var->data.driver_location;
3277 unsigned comp = instr->variables[0]->var->data.location_frac;
3278 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3279 int writemask = instr->const_index[0] << comp;
3280 LLVMValueRef indir_index;
3281 unsigned const_index;
3282 get_deref_offset(ctx, instr->variables[0], false,
3283 NULL, NULL, &const_index, &indir_index);
3284
3285 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3286
3287 src = LLVMBuildBitCast(ctx->ac.builder, src,
3288 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3289 "");
3290
3291 writemask = widen_mask(writemask, 2);
3292 }
3293
3294 switch (instr->variables[0]->var->data.mode) {
3295 case nir_var_shader_out:
3296
3297 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3298 LLVMValueRef vertex_index = NULL;
3299 LLVMValueRef indir_index = NULL;
3300 unsigned const_index = 0;
3301 const unsigned location = instr->variables[0]->var->data.location;
3302 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3303 const unsigned comp = instr->variables[0]->var->data.location_frac;
3304 const bool is_patch = instr->variables[0]->var->data.patch;
3305 const bool is_compact = instr->variables[0]->var->data.compact;
3306
3307 get_deref_offset(ctx, instr->variables[0],
3308 false, NULL, is_patch ? NULL : &vertex_index,
3309 &const_index, &indir_index);
3310
3311 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3312 const_index, location, driver_location,
3313 src, comp, is_patch, is_compact, writemask);
3314 return;
3315 }
3316
3317 for (unsigned chan = 0; chan < 8; chan++) {
3318 int stride = 4;
3319 if (!(writemask & (1 << chan)))
3320 continue;
3321
3322 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3323
3324 if (instr->variables[0]->var->data.compact)
3325 stride = 1;
3326 if (indir_index) {
3327 unsigned count = glsl_count_attribute_slots(
3328 instr->variables[0]->var->type, false);
3329 count -= chan / 4;
3330 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3331 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3332 stride, true, true);
3333
3334 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3335 value, indir_index, "");
3336 build_store_values_extended(&ctx->ac, ctx->abi->outputs + idx + chan,
3337 count, stride, tmp_vec);
3338
3339 } else {
3340 temp_ptr = ctx->abi->outputs[idx + chan + const_index * stride];
3341
3342 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3343 }
3344 }
3345 break;
3346 case nir_var_local:
3347 for (unsigned chan = 0; chan < 8; chan++) {
3348 if (!(writemask & (1 << chan)))
3349 continue;
3350
3351 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3352 if (indir_index) {
3353 unsigned count = glsl_count_attribute_slots(
3354 instr->variables[0]->var->type, false);
3355 count -= chan / 4;
3356 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3357 &ctx->ac, ctx->locals + idx + chan, count,
3358 4, true, true);
3359
3360 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3361 value, indir_index, "");
3362 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3363 count, 4, tmp_vec);
3364 } else {
3365 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3366
3367 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3368 }
3369 }
3370 break;
3371 case nir_var_shared: {
3372 int writemask = instr->const_index[0];
3373 LLVMValueRef address = build_gep_for_deref(ctx,
3374 instr->variables[0]);
3375 LLVMValueRef val = get_src(ctx, instr->src[0]);
3376 unsigned components =
3377 glsl_get_vector_elements(
3378 nir_deref_tail(&instr->variables[0]->deref)->type);
3379 if (writemask == (1 << components) - 1) {
3380 val = LLVMBuildBitCast(
3381 ctx->ac.builder, val,
3382 LLVMGetElementType(LLVMTypeOf(address)), "");
3383 LLVMBuildStore(ctx->ac.builder, val, address);
3384 } else {
3385 for (unsigned chan = 0; chan < 4; chan++) {
3386 if (!(writemask & (1 << chan)))
3387 continue;
3388 LLVMValueRef ptr =
3389 LLVMBuildStructGEP(ctx->ac.builder,
3390 address, chan, "");
3391 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3392 chan);
3393 src = LLVMBuildBitCast(
3394 ctx->ac.builder, src,
3395 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3396 LLVMBuildStore(ctx->ac.builder, src, ptr);
3397 }
3398 }
3399 break;
3400 }
3401 default:
3402 break;
3403 }
3404 }
3405
3406 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3407 {
3408 switch (dim) {
3409 case GLSL_SAMPLER_DIM_BUF:
3410 return 1;
3411 case GLSL_SAMPLER_DIM_1D:
3412 return array ? 2 : 1;
3413 case GLSL_SAMPLER_DIM_2D:
3414 return array ? 3 : 2;
3415 case GLSL_SAMPLER_DIM_MS:
3416 return array ? 4 : 3;
3417 case GLSL_SAMPLER_DIM_3D:
3418 case GLSL_SAMPLER_DIM_CUBE:
3419 return 3;
3420 case GLSL_SAMPLER_DIM_RECT:
3421 case GLSL_SAMPLER_DIM_SUBPASS:
3422 return 2;
3423 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3424 return 3;
3425 default:
3426 break;
3427 }
3428 return 0;
3429 }
3430
3431
3432
3433 /* Adjust the sample index according to FMASK.
3434 *
3435 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3436 * which is the identity mapping. Each nibble says which physical sample
3437 * should be fetched to get that sample.
3438 *
3439 * For example, 0x11111100 means there are only 2 samples stored and
3440 * the second sample covers 3/4 of the pixel. When reading samples 0
3441 * and 1, return physical sample 0 (determined by the first two 0s
3442 * in FMASK), otherwise return physical sample 1.
3443 *
3444 * The sample index should be adjusted as follows:
3445 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3446 */
3447 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3448 LLVMValueRef coord_x, LLVMValueRef coord_y,
3449 LLVMValueRef coord_z,
3450 LLVMValueRef sample_index,
3451 LLVMValueRef fmask_desc_ptr)
3452 {
3453 LLVMValueRef fmask_load_address[4];
3454 LLVMValueRef res;
3455
3456 fmask_load_address[0] = coord_x;
3457 fmask_load_address[1] = coord_y;
3458 if (coord_z) {
3459 fmask_load_address[2] = coord_z;
3460 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3461 }
3462
3463 struct ac_image_args args = {0};
3464
3465 args.opcode = ac_image_load;
3466 args.da = coord_z ? true : false;
3467 args.resource = fmask_desc_ptr;
3468 args.dmask = 0xf;
3469 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3470
3471 res = ac_build_image_opcode(ctx, &args);
3472
3473 res = ac_to_integer(ctx, res);
3474 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3475 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3476
3477 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3478 res,
3479 ctx->i32_0, "");
3480
3481 LLVMValueRef sample_index4 =
3482 LLVMBuildMul(ctx->builder, sample_index, four, "");
3483 LLVMValueRef shifted_fmask =
3484 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3485 LLVMValueRef final_sample =
3486 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3487
3488 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3489 * resource descriptor is 0 (invalid),
3490 */
3491 LLVMValueRef fmask_desc =
3492 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3493 ctx->v8i32, "");
3494
3495 LLVMValueRef fmask_word1 =
3496 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3497 ctx->i32_1, "");
3498
3499 LLVMValueRef word1_is_nonzero =
3500 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3501 fmask_word1, ctx->i32_0, "");
3502
3503 /* Replace the MSAA sample index. */
3504 sample_index =
3505 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3506 final_sample, sample_index, "");
3507 return sample_index;
3508 }
3509
3510 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3511 const nir_intrinsic_instr *instr)
3512 {
3513 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3514
3515 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3516 LLVMValueRef coords[4];
3517 LLVMValueRef masks[] = {
3518 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3519 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3520 };
3521 LLVMValueRef res;
3522 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3523
3524 int count;
3525 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3526 bool is_array = glsl_sampler_type_is_array(type);
3527 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3528 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3529 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3530 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3531 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3532 count = image_type_to_components_count(dim, is_array);
3533
3534 if (is_ms) {
3535 LLVMValueRef fmask_load_address[3];
3536 int chan;
3537
3538 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3539 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3540 if (is_array)
3541 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3542 else
3543 fmask_load_address[2] = NULL;
3544 if (add_frag_pos) {
3545 for (chan = 0; chan < 2; ++chan)
3546 fmask_load_address[chan] =
3547 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3548 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3549 ctx->ac.i32, ""), "");
3550 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3551 }
3552 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3553 fmask_load_address[0],
3554 fmask_load_address[1],
3555 fmask_load_address[2],
3556 sample_index,
3557 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3558 }
3559 if (count == 1 && !gfx9_1d) {
3560 if (instr->src[0].ssa->num_components)
3561 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3562 else
3563 res = src0;
3564 } else {
3565 int chan;
3566 if (is_ms)
3567 count--;
3568 for (chan = 0; chan < count; ++chan) {
3569 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3570 }
3571 if (add_frag_pos) {
3572 for (chan = 0; chan < 2; ++chan)
3573 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3574 ctx->ac.i32, ""), "");
3575 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3576 count++;
3577 }
3578
3579 if (gfx9_1d) {
3580 if (is_array) {
3581 coords[2] = coords[1];
3582 coords[1] = ctx->ac.i32_0;
3583 } else
3584 coords[1] = ctx->ac.i32_0;
3585 count++;
3586 }
3587
3588 if (is_ms) {
3589 coords[count] = sample_index;
3590 count++;
3591 }
3592
3593 if (count == 3) {
3594 coords[3] = LLVMGetUndef(ctx->ac.i32);
3595 count = 4;
3596 }
3597 res = ac_build_gather_values(&ctx->ac, coords, count);
3598 }
3599 return res;
3600 }
3601
3602 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3603 const nir_intrinsic_instr *instr)
3604 {
3605 LLVMValueRef params[7];
3606 LLVMValueRef res;
3607 char intrinsic_name[64];
3608 const nir_variable *var = instr->variables[0]->var;
3609 const struct glsl_type *type = var->type;
3610
3611 if(instr->variables[0]->deref.child)
3612 type = instr->variables[0]->deref.child->type;
3613
3614 type = glsl_without_array(type);
3615
3616 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3617 if (dim == GLSL_SAMPLER_DIM_BUF) {
3618 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3619 unsigned num_channels = util_last_bit(mask);
3620 LLVMValueRef rsrc, vindex;
3621
3622 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3623 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3624 ctx->ac.i32_0, "");
3625
3626 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3627 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3628 ctx->ac.i32_0, num_channels,
3629 false, false);
3630 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3631
3632 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3633 res = ac_to_integer(&ctx->ac, res);
3634 } else {
3635 bool is_da = glsl_sampler_type_is_array(type) ||
3636 dim == GLSL_SAMPLER_DIM_CUBE ||
3637 dim == GLSL_SAMPLER_DIM_3D ||
3638 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3639 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3640 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3641 LLVMValueRef glc = ctx->ac.i1false;
3642 LLVMValueRef slc = ctx->ac.i1false;
3643
3644 params[0] = get_image_coords(ctx, instr);
3645 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3646 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3647 params[3] = glc;
3648 params[4] = slc;
3649 params[5] = ctx->ac.i1false;
3650 params[6] = da;
3651
3652 ac_get_image_intr_name("llvm.amdgcn.image.load",
3653 ctx->ac.v4f32, /* vdata */
3654 LLVMTypeOf(params[0]), /* coords */
3655 LLVMTypeOf(params[1]), /* rsrc */
3656 intrinsic_name, sizeof(intrinsic_name));
3657
3658 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3659 params, 7, AC_FUNC_ATTR_READONLY);
3660 }
3661 return ac_to_integer(&ctx->ac, res);
3662 }
3663
3664 static void visit_image_store(struct ac_nir_context *ctx,
3665 nir_intrinsic_instr *instr)
3666 {
3667 LLVMValueRef params[8];
3668 char intrinsic_name[64];
3669 const nir_variable *var = instr->variables[0]->var;
3670 const struct glsl_type *type = glsl_without_array(var->type);
3671 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3672 LLVMValueRef glc = ctx->ac.i1false;
3673 bool force_glc = ctx->ac.chip_class == SI;
3674 if (force_glc)
3675 glc = ctx->ac.i1true;
3676
3677 if (dim == GLSL_SAMPLER_DIM_BUF) {
3678 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3679 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3680 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3681 ctx->ac.i32_0, ""); /* vindex */
3682 params[3] = ctx->ac.i32_0; /* voffset */
3683 params[4] = glc; /* glc */
3684 params[5] = ctx->ac.i1false; /* slc */
3685 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3686 params, 6, 0);
3687 } else {
3688 bool is_da = glsl_sampler_type_is_array(type) ||
3689 dim == GLSL_SAMPLER_DIM_CUBE ||
3690 dim == GLSL_SAMPLER_DIM_3D;
3691 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3692 LLVMValueRef slc = ctx->ac.i1false;
3693
3694 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3695 params[1] = get_image_coords(ctx, instr); /* coords */
3696 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3697 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3698 params[4] = glc;
3699 params[5] = slc;
3700 params[6] = ctx->ac.i1false;
3701 params[7] = da;
3702
3703 ac_get_image_intr_name("llvm.amdgcn.image.store",
3704 LLVMTypeOf(params[0]), /* vdata */
3705 LLVMTypeOf(params[1]), /* coords */
3706 LLVMTypeOf(params[2]), /* rsrc */
3707 intrinsic_name, sizeof(intrinsic_name));
3708
3709 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3710 params, 8, 0);
3711 }
3712
3713 }
3714
3715 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3716 const nir_intrinsic_instr *instr)
3717 {
3718 LLVMValueRef params[7];
3719 int param_count = 0;
3720 const nir_variable *var = instr->variables[0]->var;
3721
3722 const char *atomic_name;
3723 char intrinsic_name[41];
3724 const struct glsl_type *type = glsl_without_array(var->type);
3725 MAYBE_UNUSED int length;
3726
3727 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3728
3729 switch (instr->intrinsic) {
3730 case nir_intrinsic_image_atomic_add:
3731 atomic_name = "add";
3732 break;
3733 case nir_intrinsic_image_atomic_min:
3734 atomic_name = is_unsigned ? "umin" : "smin";
3735 break;
3736 case nir_intrinsic_image_atomic_max:
3737 atomic_name = is_unsigned ? "umax" : "smax";
3738 break;
3739 case nir_intrinsic_image_atomic_and:
3740 atomic_name = "and";
3741 break;
3742 case nir_intrinsic_image_atomic_or:
3743 atomic_name = "or";
3744 break;
3745 case nir_intrinsic_image_atomic_xor:
3746 atomic_name = "xor";
3747 break;
3748 case nir_intrinsic_image_atomic_exchange:
3749 atomic_name = "swap";
3750 break;
3751 case nir_intrinsic_image_atomic_comp_swap:
3752 atomic_name = "cmpswap";
3753 break;
3754 default:
3755 abort();
3756 }
3757
3758 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3759 params[param_count++] = get_src(ctx, instr->src[3]);
3760 params[param_count++] = get_src(ctx, instr->src[2]);
3761
3762 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3763 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3764 NULL, true, true);
3765 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3766 ctx->ac.i32_0, ""); /* vindex */
3767 params[param_count++] = ctx->ac.i32_0; /* voffset */
3768 params[param_count++] = ctx->ac.i1false; /* slc */
3769
3770 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3771 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3772 } else {
3773 char coords_type[8];
3774
3775 bool da = glsl_sampler_type_is_array(type) ||
3776 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3777 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_3D;
3778
3779 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3780 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3781 NULL, true, true);
3782 params[param_count++] = ctx->ac.i1false; /* r128 */
3783 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3784 params[param_count++] = ctx->ac.i1false; /* slc */
3785
3786 build_int_type_name(LLVMTypeOf(coords),
3787 coords_type, sizeof(coords_type));
3788
3789 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3790 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3791 }
3792
3793 assert(length < sizeof(intrinsic_name));
3794 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3795 }
3796
3797 static LLVMValueRef visit_image_samples(struct ac_nir_context *ctx,
3798 const nir_intrinsic_instr *instr)
3799 {
3800 const nir_variable *var = instr->variables[0]->var;
3801 const struct glsl_type *type = glsl_without_array(var->type);
3802 bool da = glsl_sampler_type_is_array(type) ||
3803 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3804 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_3D;
3805
3806 struct ac_image_args args = { 0 };
3807 args.da = da;
3808 args.dmask = 0xf;
3809 args.resource = get_sampler_desc(ctx, instr->variables[0],
3810 AC_DESC_IMAGE, NULL, true, false);
3811 args.opcode = ac_image_get_resinfo;
3812 args.addr = ctx->ac.i32_0;
3813
3814 return ac_build_image_opcode(&ctx->ac, &args);
3815 }
3816
3817 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3818 const nir_intrinsic_instr *instr)
3819 {
3820 LLVMValueRef res;
3821 const nir_variable *var = instr->variables[0]->var;
3822 const struct glsl_type *type = glsl_without_array(var->type);
3823 bool da = glsl_sampler_type_is_array(type) ||
3824 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3825 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_3D;
3826
3827 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3828 return get_buffer_size(ctx,
3829 get_sampler_desc(ctx, instr->variables[0],
3830 AC_DESC_BUFFER, NULL, true, false), true);
3831
3832 struct ac_image_args args = { 0 };
3833
3834 args.da = da;
3835 args.dmask = 0xf;
3836 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3837 args.opcode = ac_image_get_resinfo;
3838 args.addr = ctx->ac.i32_0;
3839
3840 res = ac_build_image_opcode(&ctx->ac, &args);
3841
3842 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3843
3844 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3845 glsl_sampler_type_is_array(type)) {
3846 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3847 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3848 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3849 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3850 }
3851 if (ctx->ac.chip_class >= GFX9 &&
3852 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3853 glsl_sampler_type_is_array(type)) {
3854 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3855 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3856 ctx->ac.i32_1, "");
3857
3858 }
3859 return res;
3860 }
3861
3862 #define NOOP_WAITCNT 0xf7f
3863 #define LGKM_CNT 0x07f
3864 #define VM_CNT 0xf70
3865
3866 static void emit_membar(struct ac_llvm_context *ac,
3867 const nir_intrinsic_instr *instr)
3868 {
3869 unsigned waitcnt = NOOP_WAITCNT;
3870
3871 switch (instr->intrinsic) {
3872 case nir_intrinsic_memory_barrier:
3873 case nir_intrinsic_group_memory_barrier:
3874 waitcnt &= VM_CNT & LGKM_CNT;
3875 break;
3876 case nir_intrinsic_memory_barrier_atomic_counter:
3877 case nir_intrinsic_memory_barrier_buffer:
3878 case nir_intrinsic_memory_barrier_image:
3879 waitcnt &= VM_CNT;
3880 break;
3881 case nir_intrinsic_memory_barrier_shared:
3882 waitcnt &= LGKM_CNT;
3883 break;
3884 default:
3885 break;
3886 }
3887 if (waitcnt != NOOP_WAITCNT)
3888 ac_build_waitcnt(ac, waitcnt);
3889 }
3890
3891 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3892 {
3893 /* SI only (thanks to a hw bug workaround):
3894 * The real barrier instruction isn’t needed, because an entire patch
3895 * always fits into a single wave.
3896 */
3897 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3898 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3899 return;
3900 }
3901 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3902 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3903 }
3904
3905 static void emit_discard(struct ac_nir_context *ctx,
3906 const nir_intrinsic_instr *instr)
3907 {
3908 LLVMValueRef cond;
3909
3910 if (instr->intrinsic == nir_intrinsic_discard_if) {
3911 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3912 get_src(ctx, instr->src[0]),
3913 ctx->ac.i32_0, "");
3914 } else {
3915 assert(instr->intrinsic == nir_intrinsic_discard);
3916 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3917 }
3918
3919 ac_build_kill_if_false(&ctx->ac, cond);
3920 }
3921
3922 static LLVMValueRef
3923 visit_load_helper_invocation(struct ac_nir_context *ctx)
3924 {
3925 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3926 "llvm.amdgcn.ps.live",
3927 ctx->ac.i1, NULL, 0,
3928 AC_FUNC_ATTR_READNONE);
3929 result = LLVMBuildNot(ctx->ac.builder, result, "");
3930 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3931 }
3932
3933 static LLVMValueRef
3934 visit_load_local_invocation_index(struct ac_nir_context *ctx)
3935 {
3936 LLVMValueRef result;
3937 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3938 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3939 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3940
3941 return LLVMBuildAdd(ctx->ac.builder, result, thread_id, "");
3942 }
3943
3944 static LLVMValueRef
3945 visit_load_shared(struct ac_nir_context *ctx,
3946 const nir_intrinsic_instr *instr)
3947 {
3948 LLVMValueRef values[4], derived_ptr, index, ret;
3949
3950 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
3951
3952 for (int chan = 0; chan < instr->num_components; chan++) {
3953 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3954 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
3955 values[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
3956 }
3957
3958 ret = ac_build_gather_values(&ctx->ac, values, instr->num_components);
3959 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3960 }
3961
3962 static void
3963 visit_store_shared(struct ac_nir_context *ctx,
3964 const nir_intrinsic_instr *instr)
3965 {
3966 LLVMValueRef derived_ptr, data,index;
3967 LLVMBuilderRef builder = ctx->ac.builder;
3968
3969 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
3970 LLVMValueRef src = get_src(ctx, instr->src[0]);
3971
3972 int writemask = nir_intrinsic_write_mask(instr);
3973 for (int chan = 0; chan < 4; chan++) {
3974 if (!(writemask & (1 << chan))) {
3975 continue;
3976 }
3977 data = ac_llvm_extract_elem(&ctx->ac, src, chan);
3978 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3979 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3980 LLVMBuildStore(builder, data, derived_ptr);
3981 }
3982 }
3983
3984 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
3985 const nir_intrinsic_instr *instr,
3986 LLVMValueRef ptr)
3987 {
3988 LLVMValueRef result;
3989 LLVMValueRef src = get_src(ctx, instr->src[0]);
3990
3991 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
3992 instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
3993 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3994 result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
3995 ptr, src, src1,
3996 LLVMAtomicOrderingSequentiallyConsistent,
3997 LLVMAtomicOrderingSequentiallyConsistent,
3998 false);
3999 } else {
4000 LLVMAtomicRMWBinOp op;
4001 switch (instr->intrinsic) {
4002 case nir_intrinsic_var_atomic_add:
4003 case nir_intrinsic_shared_atomic_add:
4004 op = LLVMAtomicRMWBinOpAdd;
4005 break;
4006 case nir_intrinsic_var_atomic_umin:
4007 case nir_intrinsic_shared_atomic_umin:
4008 op = LLVMAtomicRMWBinOpUMin;
4009 break;
4010 case nir_intrinsic_var_atomic_umax:
4011 case nir_intrinsic_shared_atomic_umax:
4012 op = LLVMAtomicRMWBinOpUMax;
4013 break;
4014 case nir_intrinsic_var_atomic_imin:
4015 case nir_intrinsic_shared_atomic_imin:
4016 op = LLVMAtomicRMWBinOpMin;
4017 break;
4018 case nir_intrinsic_var_atomic_imax:
4019 case nir_intrinsic_shared_atomic_imax:
4020 op = LLVMAtomicRMWBinOpMax;
4021 break;
4022 case nir_intrinsic_var_atomic_and:
4023 case nir_intrinsic_shared_atomic_and:
4024 op = LLVMAtomicRMWBinOpAnd;
4025 break;
4026 case nir_intrinsic_var_atomic_or:
4027 case nir_intrinsic_shared_atomic_or:
4028 op = LLVMAtomicRMWBinOpOr;
4029 break;
4030 case nir_intrinsic_var_atomic_xor:
4031 case nir_intrinsic_shared_atomic_xor:
4032 op = LLVMAtomicRMWBinOpXor;
4033 break;
4034 case nir_intrinsic_var_atomic_exchange:
4035 case nir_intrinsic_shared_atomic_exchange:
4036 op = LLVMAtomicRMWBinOpXchg;
4037 break;
4038 default:
4039 return NULL;
4040 }
4041
4042 result = LLVMBuildAtomicRMW(ctx->ac.builder, op, ptr, ac_to_integer(&ctx->ac, src),
4043 LLVMAtomicOrderingSequentiallyConsistent,
4044 false);
4045 }
4046 return result;
4047 }
4048
4049 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
4050 enum glsl_interp_mode interp, unsigned location)
4051 {
4052 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4053
4054 switch (interp) {
4055 case INTERP_MODE_FLAT:
4056 default:
4057 return NULL;
4058 case INTERP_MODE_SMOOTH:
4059 case INTERP_MODE_NONE:
4060 if (location == INTERP_CENTER)
4061 return ctx->persp_center;
4062 else if (location == INTERP_CENTROID)
4063 return ctx->persp_centroid;
4064 else if (location == INTERP_SAMPLE)
4065 return ctx->persp_sample;
4066 break;
4067 case INTERP_MODE_NOPERSPECTIVE:
4068 if (location == INTERP_CENTER)
4069 return ctx->linear_center;
4070 else if (location == INTERP_CENTROID)
4071 return ctx->linear_centroid;
4072 else if (location == INTERP_SAMPLE)
4073 return ctx->linear_sample;
4074 break;
4075 }
4076 return NULL;
4077 }
4078
4079 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
4080 LLVMValueRef sample_id)
4081 {
4082 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4083
4084 LLVMValueRef result;
4085 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4086
4087 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
4088 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4089
4090 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
4091 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4092
4093 return result;
4094 }
4095
4096 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4097 {
4098 LLVMValueRef values[2];
4099
4100 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0], 32);
4101 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1], 32);
4102 return ac_build_gather_values(&ctx->ac, values, 2);
4103 }
4104
4105 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4106 {
4107 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4108 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4109 ctx->options->key.fs.log2_num_samples :
4110 ctx->options->key.fs.log2_ps_iter_samples;
4111
4112 /* The bit pattern matches that used by fixed function fragment
4113 * processing. */
4114 static const uint16_t ps_iter_masks[] = {
4115 0xffff, /* not used */
4116 0x5555,
4117 0x1111,
4118 0x0101,
4119 0x0001,
4120 };
4121 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4122
4123 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4124
4125 LLVMValueRef result, sample_id;
4126 sample_id = unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4127 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4128 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4129 return result;
4130 }
4131
4132 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4133 const nir_intrinsic_instr *instr)
4134 {
4135 LLVMValueRef result[4];
4136 LLVMValueRef interp_param, attr_number;
4137 unsigned location;
4138 unsigned chan;
4139 LLVMValueRef src_c0 = NULL;
4140 LLVMValueRef src_c1 = NULL;
4141 LLVMValueRef src0 = NULL;
4142 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4143 switch (instr->intrinsic) {
4144 case nir_intrinsic_interp_var_at_centroid:
4145 location = INTERP_CENTROID;
4146 break;
4147 case nir_intrinsic_interp_var_at_sample:
4148 case nir_intrinsic_interp_var_at_offset:
4149 location = INTERP_CENTER;
4150 src0 = get_src(ctx, instr->src[0]);
4151 break;
4152 default:
4153 break;
4154 }
4155
4156 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4157 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4158 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4159 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4160 LLVMValueRef sample_position;
4161 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4162
4163 /* fetch sample ID */
4164 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4165
4166 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4167 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4168 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4169 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4170 }
4171 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4172 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4173
4174 if (location == INTERP_CENTER) {
4175 LLVMValueRef ij_out[2];
4176 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4177
4178 /*
4179 * take the I then J parameters, and the DDX/Y for it, and
4180 * calculate the IJ inputs for the interpolator.
4181 * temp1 = ddx * offset/sample.x + I;
4182 * interp_param.I = ddy * offset/sample.y + temp1;
4183 * temp1 = ddx * offset/sample.x + J;
4184 * interp_param.J = ddy * offset/sample.y + temp1;
4185 */
4186 for (unsigned i = 0; i < 2; i++) {
4187 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4188 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4189 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4190 ddxy_out, ix_ll, "");
4191 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4192 ddxy_out, iy_ll, "");
4193 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4194 interp_param, ix_ll, "");
4195 LLVMValueRef temp1, temp2;
4196
4197 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4198 ctx->ac.f32, "");
4199
4200 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4201 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4202
4203 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4204 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4205
4206 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4207 temp2, ctx->ac.i32, "");
4208 }
4209 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4210
4211 }
4212
4213 for (chan = 0; chan < 4; chan++) {
4214 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4215
4216 if (interp_param) {
4217 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4218 interp_param, ctx->ac.v2f32, "");
4219 LLVMValueRef i = LLVMBuildExtractElement(
4220 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4221 LLVMValueRef j = LLVMBuildExtractElement(
4222 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4223
4224 result[chan] = ac_build_fs_interp(&ctx->ac,
4225 llvm_chan, attr_number,
4226 ctx->abi->prim_mask, i, j);
4227 } else {
4228 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4229 LLVMConstInt(ctx->ac.i32, 2, false),
4230 llvm_chan, attr_number,
4231 ctx->abi->prim_mask);
4232 }
4233 }
4234 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4235 instr->variables[0]->var->data.location_frac);
4236 }
4237
4238 static void
4239 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4240 {
4241 LLVMValueRef gs_next_vertex;
4242 LLVMValueRef can_emit;
4243 int idx;
4244 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4245
4246 assert(stream == 0);
4247
4248 /* Write vertex attribute values to GSVS ring */
4249 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4250 ctx->gs_next_vertex,
4251 "");
4252
4253 /* If this thread has already emitted the declared maximum number of
4254 * vertices, kill it: excessive vertex emissions are not supposed to
4255 * have any effect, and GS threads have no externally observable
4256 * effects other than emitting vertices.
4257 */
4258 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4259 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4260 ac_build_kill_if_false(&ctx->ac, can_emit);
4261
4262 /* loop num outputs */
4263 idx = 0;
4264 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4265 LLVMValueRef *out_ptr = &addrs[i * 4];
4266 int length = 4;
4267 int slot = idx;
4268 int slot_inc = 1;
4269
4270 if (!(ctx->output_mask & (1ull << i)))
4271 continue;
4272
4273 if (i == VARYING_SLOT_CLIP_DIST0) {
4274 /* pack clip and cull into a single set of slots */
4275 length = ctx->num_output_clips + ctx->num_output_culls;
4276 if (length > 4)
4277 slot_inc = 2;
4278 }
4279 for (unsigned j = 0; j < length; j++) {
4280 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4281 out_ptr[j], "");
4282 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4283 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4284 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4285
4286 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4287
4288 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4289 out_val, 1,
4290 voffset, ctx->gs2vs_offset, 0,
4291 1, 1, true, true);
4292 }
4293 idx += slot_inc;
4294 }
4295
4296 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
4297 ctx->ac.i32_1, "");
4298 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
4299
4300 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4301 }
4302
4303 static void
4304 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4305 {
4306 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4307 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4308 }
4309
4310 static LLVMValueRef
4311 load_tess_coord(struct ac_shader_abi *abi)
4312 {
4313 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4314
4315 LLVMValueRef coord[4] = {
4316 ctx->tes_u,
4317 ctx->tes_v,
4318 ctx->ac.f32_0,
4319 ctx->ac.f32_0,
4320 };
4321
4322 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4323 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
4324 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
4325
4326 return ac_build_gather_values(&ctx->ac, coord, 3);
4327 }
4328
4329 static LLVMValueRef
4330 load_patch_vertices_in(struct ac_shader_abi *abi)
4331 {
4332 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4333 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4334 }
4335
4336 static void visit_intrinsic(struct ac_nir_context *ctx,
4337 nir_intrinsic_instr *instr)
4338 {
4339 LLVMValueRef result = NULL;
4340
4341 switch (instr->intrinsic) {
4342 case nir_intrinsic_ballot:
4343 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4344 break;
4345 case nir_intrinsic_read_invocation:
4346 case nir_intrinsic_read_first_invocation: {
4347 LLVMValueRef args[2];
4348
4349 /* Value */
4350 args[0] = get_src(ctx, instr->src[0]);
4351
4352 unsigned num_args;
4353 const char *intr_name;
4354 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4355 num_args = 2;
4356 intr_name = "llvm.amdgcn.readlane";
4357
4358 /* Invocation */
4359 args[1] = get_src(ctx, instr->src[1]);
4360 } else {
4361 num_args = 1;
4362 intr_name = "llvm.amdgcn.readfirstlane";
4363 }
4364
4365 /* We currently have no other way to prevent LLVM from lifting the icmp
4366 * calls to a dominating basic block.
4367 */
4368 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4369
4370 result = ac_build_intrinsic(&ctx->ac, intr_name,
4371 ctx->ac.i32, args, num_args,
4372 AC_FUNC_ATTR_READNONE |
4373 AC_FUNC_ATTR_CONVERGENT);
4374 break;
4375 }
4376 case nir_intrinsic_load_subgroup_invocation:
4377 result = ac_get_thread_id(&ctx->ac);
4378 break;
4379 case nir_intrinsic_load_work_group_id: {
4380 LLVMValueRef values[3];
4381
4382 for (int i = 0; i < 3; i++) {
4383 values[i] = ctx->abi->workgroup_ids[i] ?
4384 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4385 }
4386
4387 result = ac_build_gather_values(&ctx->ac, values, 3);
4388 break;
4389 }
4390 case nir_intrinsic_load_base_vertex: {
4391 result = ctx->abi->base_vertex;
4392 break;
4393 }
4394 case nir_intrinsic_load_local_group_size:
4395 result = ctx->abi->load_local_group_size(ctx->abi);
4396 break;
4397 case nir_intrinsic_load_vertex_id_zero_base: {
4398 result = ctx->abi->vertex_id;
4399 break;
4400 }
4401 case nir_intrinsic_load_local_invocation_id: {
4402 result = ctx->abi->local_invocation_ids;
4403 break;
4404 }
4405 case nir_intrinsic_load_base_instance:
4406 result = ctx->abi->start_instance;
4407 break;
4408 case nir_intrinsic_load_draw_id:
4409 result = ctx->abi->draw_id;
4410 break;
4411 case nir_intrinsic_load_view_index:
4412 result = ctx->abi->view_index;
4413 break;
4414 case nir_intrinsic_load_invocation_id:
4415 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4416 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4417 else
4418 result = ctx->abi->gs_invocation_id;
4419 break;
4420 case nir_intrinsic_load_primitive_id:
4421 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4422 result = ctx->abi->gs_prim_id;
4423 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4424 result = ctx->abi->tcs_patch_id;
4425 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4426 result = ctx->abi->tes_patch_id;
4427 } else
4428 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4429 break;
4430 case nir_intrinsic_load_sample_id:
4431 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4432 break;
4433 case nir_intrinsic_load_sample_pos:
4434 result = load_sample_pos(ctx);
4435 break;
4436 case nir_intrinsic_load_sample_mask_in:
4437 result = ctx->abi->load_sample_mask_in(ctx->abi);
4438 break;
4439 case nir_intrinsic_load_frag_coord: {
4440 LLVMValueRef values[4] = {
4441 ctx->abi->frag_pos[0],
4442 ctx->abi->frag_pos[1],
4443 ctx->abi->frag_pos[2],
4444 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4445 };
4446 result = ac_build_gather_values(&ctx->ac, values, 4);
4447 break;
4448 }
4449 case nir_intrinsic_load_front_face:
4450 result = ctx->abi->front_face;
4451 break;
4452 case nir_intrinsic_load_helper_invocation:
4453 result = visit_load_helper_invocation(ctx);
4454 break;
4455 case nir_intrinsic_load_instance_id:
4456 result = ctx->abi->instance_id;
4457 break;
4458 case nir_intrinsic_load_num_work_groups:
4459 result = ctx->abi->num_work_groups;
4460 break;
4461 case nir_intrinsic_load_local_invocation_index:
4462 result = visit_load_local_invocation_index(ctx);
4463 break;
4464 case nir_intrinsic_load_push_constant:
4465 result = visit_load_push_constant(ctx, instr);
4466 break;
4467 case nir_intrinsic_vulkan_resource_index: {
4468 LLVMValueRef index = get_src(ctx, instr->src[0]);
4469 unsigned desc_set = nir_intrinsic_desc_set(instr);
4470 unsigned binding = nir_intrinsic_binding(instr);
4471
4472 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4473 binding);
4474 break;
4475 }
4476 case nir_intrinsic_vulkan_resource_reindex:
4477 result = visit_vulkan_resource_reindex(ctx, instr);
4478 break;
4479 case nir_intrinsic_store_ssbo:
4480 visit_store_ssbo(ctx, instr);
4481 break;
4482 case nir_intrinsic_load_ssbo:
4483 result = visit_load_buffer(ctx, instr);
4484 break;
4485 case nir_intrinsic_ssbo_atomic_add:
4486 case nir_intrinsic_ssbo_atomic_imin:
4487 case nir_intrinsic_ssbo_atomic_umin:
4488 case nir_intrinsic_ssbo_atomic_imax:
4489 case nir_intrinsic_ssbo_atomic_umax:
4490 case nir_intrinsic_ssbo_atomic_and:
4491 case nir_intrinsic_ssbo_atomic_or:
4492 case nir_intrinsic_ssbo_atomic_xor:
4493 case nir_intrinsic_ssbo_atomic_exchange:
4494 case nir_intrinsic_ssbo_atomic_comp_swap:
4495 result = visit_atomic_ssbo(ctx, instr);
4496 break;
4497 case nir_intrinsic_load_ubo:
4498 result = visit_load_ubo_buffer(ctx, instr);
4499 break;
4500 case nir_intrinsic_get_buffer_size:
4501 result = visit_get_buffer_size(ctx, instr);
4502 break;
4503 case nir_intrinsic_load_var:
4504 result = visit_load_var(ctx, instr);
4505 break;
4506 case nir_intrinsic_store_var:
4507 visit_store_var(ctx, instr);
4508 break;
4509 case nir_intrinsic_load_shared:
4510 result = visit_load_shared(ctx, instr);
4511 break;
4512 case nir_intrinsic_store_shared:
4513 visit_store_shared(ctx, instr);
4514 break;
4515 case nir_intrinsic_image_samples:
4516 result = visit_image_samples(ctx, instr);
4517 break;
4518 case nir_intrinsic_image_load:
4519 result = visit_image_load(ctx, instr);
4520 break;
4521 case nir_intrinsic_image_store:
4522 visit_image_store(ctx, instr);
4523 break;
4524 case nir_intrinsic_image_atomic_add:
4525 case nir_intrinsic_image_atomic_min:
4526 case nir_intrinsic_image_atomic_max:
4527 case nir_intrinsic_image_atomic_and:
4528 case nir_intrinsic_image_atomic_or:
4529 case nir_intrinsic_image_atomic_xor:
4530 case nir_intrinsic_image_atomic_exchange:
4531 case nir_intrinsic_image_atomic_comp_swap:
4532 result = visit_image_atomic(ctx, instr);
4533 break;
4534 case nir_intrinsic_image_size:
4535 result = visit_image_size(ctx, instr);
4536 break;
4537 case nir_intrinsic_shader_clock:
4538 result = ac_build_shader_clock(&ctx->ac);
4539 break;
4540 case nir_intrinsic_discard:
4541 case nir_intrinsic_discard_if:
4542 emit_discard(ctx, instr);
4543 break;
4544 case nir_intrinsic_memory_barrier:
4545 case nir_intrinsic_group_memory_barrier:
4546 case nir_intrinsic_memory_barrier_atomic_counter:
4547 case nir_intrinsic_memory_barrier_buffer:
4548 case nir_intrinsic_memory_barrier_image:
4549 case nir_intrinsic_memory_barrier_shared:
4550 emit_membar(&ctx->ac, instr);
4551 break;
4552 case nir_intrinsic_barrier:
4553 emit_barrier(&ctx->ac, ctx->stage);
4554 break;
4555 case nir_intrinsic_shared_atomic_add:
4556 case nir_intrinsic_shared_atomic_imin:
4557 case nir_intrinsic_shared_atomic_umin:
4558 case nir_intrinsic_shared_atomic_imax:
4559 case nir_intrinsic_shared_atomic_umax:
4560 case nir_intrinsic_shared_atomic_and:
4561 case nir_intrinsic_shared_atomic_or:
4562 case nir_intrinsic_shared_atomic_xor:
4563 case nir_intrinsic_shared_atomic_exchange:
4564 case nir_intrinsic_shared_atomic_comp_swap: {
4565 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
4566 result = visit_var_atomic(ctx, instr, ptr);
4567 break;
4568 }
4569 case nir_intrinsic_var_atomic_add:
4570 case nir_intrinsic_var_atomic_imin:
4571 case nir_intrinsic_var_atomic_umin:
4572 case nir_intrinsic_var_atomic_imax:
4573 case nir_intrinsic_var_atomic_umax:
4574 case nir_intrinsic_var_atomic_and:
4575 case nir_intrinsic_var_atomic_or:
4576 case nir_intrinsic_var_atomic_xor:
4577 case nir_intrinsic_var_atomic_exchange:
4578 case nir_intrinsic_var_atomic_comp_swap: {
4579 LLVMValueRef ptr = build_gep_for_deref(ctx, instr->variables[0]);
4580 result = visit_var_atomic(ctx, instr, ptr);
4581 break;
4582 }
4583 case nir_intrinsic_interp_var_at_centroid:
4584 case nir_intrinsic_interp_var_at_sample:
4585 case nir_intrinsic_interp_var_at_offset:
4586 result = visit_interp(ctx, instr);
4587 break;
4588 case nir_intrinsic_emit_vertex:
4589 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->abi->outputs);
4590 break;
4591 case nir_intrinsic_end_primitive:
4592 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4593 break;
4594 case nir_intrinsic_load_tess_coord:
4595 result = ctx->abi->load_tess_coord(ctx->abi);
4596 break;
4597 case nir_intrinsic_load_tess_level_outer:
4598 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4599 break;
4600 case nir_intrinsic_load_tess_level_inner:
4601 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4602 break;
4603 case nir_intrinsic_load_patch_vertices_in:
4604 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4605 break;
4606 case nir_intrinsic_vote_all: {
4607 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4608 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4609 break;
4610 }
4611 case nir_intrinsic_vote_any: {
4612 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4613 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4614 break;
4615 }
4616 case nir_intrinsic_vote_eq: {
4617 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4618 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4619 break;
4620 }
4621 default:
4622 fprintf(stderr, "Unknown intrinsic: ");
4623 nir_print_instr(&instr->instr, stderr);
4624 fprintf(stderr, "\n");
4625 break;
4626 }
4627 if (result) {
4628 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4629 }
4630 }
4631
4632 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4633 LLVMValueRef buffer_ptr, bool write)
4634 {
4635 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4636 LLVMValueRef result;
4637
4638 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4639
4640 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4641 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4642
4643 return result;
4644 }
4645
4646 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4647 {
4648 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4649 LLVMValueRef result;
4650
4651 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4652
4653 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4654 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4655
4656 return result;
4657 }
4658
4659 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4660 unsigned descriptor_set,
4661 unsigned base_index,
4662 unsigned constant_index,
4663 LLVMValueRef index,
4664 enum ac_descriptor_type desc_type,
4665 bool image, bool write)
4666 {
4667 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4668 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4669 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4670 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4671 unsigned offset = binding->offset;
4672 unsigned stride = binding->size;
4673 unsigned type_size;
4674 LLVMBuilderRef builder = ctx->ac.builder;
4675 LLVMTypeRef type;
4676
4677 assert(base_index < layout->binding_count);
4678
4679 switch (desc_type) {
4680 case AC_DESC_IMAGE:
4681 type = ctx->ac.v8i32;
4682 type_size = 32;
4683 break;
4684 case AC_DESC_FMASK:
4685 type = ctx->ac.v8i32;
4686 offset += 32;
4687 type_size = 32;
4688 break;
4689 case AC_DESC_SAMPLER:
4690 type = ctx->ac.v4i32;
4691 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4692 offset += 64;
4693
4694 type_size = 16;
4695 break;
4696 case AC_DESC_BUFFER:
4697 type = ctx->ac.v4i32;
4698 type_size = 16;
4699 break;
4700 default:
4701 unreachable("invalid desc_type\n");
4702 }
4703
4704 offset += constant_index * stride;
4705
4706 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4707 (!index || binding->immutable_samplers_equal)) {
4708 if (binding->immutable_samplers_equal)
4709 constant_index = 0;
4710
4711 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4712
4713 LLVMValueRef constants[] = {
4714 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4715 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4716 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4717 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4718 };
4719 return ac_build_gather_values(&ctx->ac, constants, 4);
4720 }
4721
4722 assert(stride % type_size == 0);
4723
4724 if (!index)
4725 index = ctx->ac.i32_0;
4726
4727 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4728
4729 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4730 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4731
4732 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4733 }
4734
4735 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4736 const nir_deref_var *deref,
4737 enum ac_descriptor_type desc_type,
4738 const nir_tex_instr *tex_instr,
4739 bool image, bool write)
4740 {
4741 LLVMValueRef index = NULL;
4742 unsigned constant_index = 0;
4743 unsigned descriptor_set;
4744 unsigned base_index;
4745
4746 if (!deref) {
4747 assert(tex_instr && !image);
4748 descriptor_set = 0;
4749 base_index = tex_instr->sampler_index;
4750 } else {
4751 const nir_deref *tail = &deref->deref;
4752 while (tail->child) {
4753 const nir_deref_array *child = nir_deref_as_array(tail->child);
4754 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4755
4756 if (!array_size)
4757 array_size = 1;
4758
4759 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4760
4761 if (child->deref_array_type == nir_deref_array_type_indirect) {
4762 LLVMValueRef indirect = get_src(ctx, child->indirect);
4763
4764 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4765 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4766
4767 if (!index)
4768 index = indirect;
4769 else
4770 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4771 }
4772
4773 constant_index += child->base_offset * array_size;
4774
4775 tail = &child->deref;
4776 }
4777 descriptor_set = deref->var->data.descriptor_set;
4778 base_index = deref->var->data.binding;
4779 }
4780
4781 return ctx->abi->load_sampler_desc(ctx->abi,
4782 descriptor_set,
4783 base_index,
4784 constant_index, index,
4785 desc_type, image, write);
4786 }
4787
4788 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4789 struct ac_image_args *args,
4790 const nir_tex_instr *instr,
4791 nir_texop op,
4792 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4793 LLVMValueRef *param, unsigned count,
4794 unsigned dmask)
4795 {
4796 unsigned is_rect = 0;
4797 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4798
4799 if (op == nir_texop_lod)
4800 da = false;
4801 /* Pad to power of two vector */
4802 while (count < util_next_power_of_two(count))
4803 param[count++] = LLVMGetUndef(ctx->i32);
4804
4805 if (count > 1)
4806 args->addr = ac_build_gather_values(ctx, param, count);
4807 else
4808 args->addr = param[0];
4809
4810 args->resource = res_ptr;
4811 args->sampler = samp_ptr;
4812
4813 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4814 args->addr = param[0];
4815 return;
4816 }
4817
4818 args->dmask = dmask;
4819 args->unorm = is_rect;
4820 args->da = da;
4821 }
4822
4823 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4824 *
4825 * SI-CI:
4826 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4827 * filtering manually. The driver sets img7 to a mask clearing
4828 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4829 * s_and_b32 samp0, samp0, img7
4830 *
4831 * VI:
4832 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4833 */
4834 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4835 LLVMValueRef res, LLVMValueRef samp)
4836 {
4837 LLVMBuilderRef builder = ctx->ac.builder;
4838 LLVMValueRef img7, samp0;
4839
4840 if (ctx->ac.chip_class >= VI)
4841 return samp;
4842
4843 img7 = LLVMBuildExtractElement(builder, res,
4844 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4845 samp0 = LLVMBuildExtractElement(builder, samp,
4846 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4847 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4848 return LLVMBuildInsertElement(builder, samp, samp0,
4849 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4850 }
4851
4852 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4853 nir_tex_instr *instr,
4854 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4855 LLVMValueRef *fmask_ptr)
4856 {
4857 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4858 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4859 else
4860 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4861 if (samp_ptr) {
4862 if (instr->sampler)
4863 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4864 else
4865 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4866 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4867 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4868 }
4869 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4870 instr->op == nir_texop_samples_identical))
4871 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4872 }
4873
4874 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4875 LLVMValueRef coord)
4876 {
4877 coord = ac_to_float(ctx, coord);
4878 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4879 coord = ac_to_integer(ctx, coord);
4880 return coord;
4881 }
4882
4883 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4884 {
4885 LLVMValueRef result = NULL;
4886 struct ac_image_args args = { 0 };
4887 unsigned dmask = 0xf;
4888 LLVMValueRef address[16];
4889 LLVMValueRef coords[5];
4890 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4891 LLVMValueRef bias = NULL, offsets = NULL;
4892 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4893 LLVMValueRef ddx = NULL, ddy = NULL;
4894 LLVMValueRef derivs[6];
4895 unsigned chan, count = 0;
4896 unsigned const_src = 0, num_deriv_comp = 0;
4897 bool lod_is_zero = false;
4898
4899 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4900
4901 for (unsigned i = 0; i < instr->num_srcs; i++) {
4902 switch (instr->src[i].src_type) {
4903 case nir_tex_src_coord:
4904 coord = get_src(ctx, instr->src[i].src);
4905 break;
4906 case nir_tex_src_projector:
4907 break;
4908 case nir_tex_src_comparator:
4909 comparator = get_src(ctx, instr->src[i].src);
4910 break;
4911 case nir_tex_src_offset:
4912 offsets = get_src(ctx, instr->src[i].src);
4913 const_src = i;
4914 break;
4915 case nir_tex_src_bias:
4916 bias = get_src(ctx, instr->src[i].src);
4917 break;
4918 case nir_tex_src_lod: {
4919 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4920
4921 if (val && val->i32[0] == 0)
4922 lod_is_zero = true;
4923 lod = get_src(ctx, instr->src[i].src);
4924 break;
4925 }
4926 case nir_tex_src_ms_index:
4927 sample_index = get_src(ctx, instr->src[i].src);
4928 break;
4929 case nir_tex_src_ms_mcs:
4930 break;
4931 case nir_tex_src_ddx:
4932 ddx = get_src(ctx, instr->src[i].src);
4933 num_deriv_comp = instr->src[i].src.ssa->num_components;
4934 break;
4935 case nir_tex_src_ddy:
4936 ddy = get_src(ctx, instr->src[i].src);
4937 break;
4938 case nir_tex_src_texture_offset:
4939 case nir_tex_src_sampler_offset:
4940 case nir_tex_src_plane:
4941 default:
4942 break;
4943 }
4944 }
4945
4946 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4947 result = get_buffer_size(ctx, res_ptr, true);
4948 goto write_result;
4949 }
4950
4951 if (instr->op == nir_texop_texture_samples) {
4952 LLVMValueRef res, samples, is_msaa;
4953 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4954 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4955 LLVMConstInt(ctx->ac.i32, 3, false), "");
4956 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4957 LLVMConstInt(ctx->ac.i32, 28, false), "");
4958 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4959 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4960 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4961 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4962
4963 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4964 LLVMConstInt(ctx->ac.i32, 16, false), "");
4965 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4966 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4967 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4968 samples, "");
4969 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4970 ctx->ac.i32_1, "");
4971 result = samples;
4972 goto write_result;
4973 }
4974
4975 if (coord)
4976 for (chan = 0; chan < instr->coord_components; chan++)
4977 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4978
4979 if (offsets && instr->op != nir_texop_txf) {
4980 LLVMValueRef offset[3], pack;
4981 for (chan = 0; chan < 3; ++chan)
4982 offset[chan] = ctx->ac.i32_0;
4983
4984 args.offset = true;
4985 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4986 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4987 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4988 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4989 if (chan)
4990 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4991 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4992 }
4993 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4994 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4995 address[count++] = pack;
4996
4997 }
4998 /* pack LOD bias value */
4999 if (instr->op == nir_texop_txb && bias) {
5000 address[count++] = bias;
5001 }
5002
5003 /* Pack depth comparison value */
5004 if (instr->is_shadow && comparator) {
5005 LLVMValueRef z = ac_to_float(&ctx->ac,
5006 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
5007
5008 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
5009 * so the depth comparison value isn't clamped for Z16 and
5010 * Z24 anymore. Do it manually here.
5011 *
5012 * It's unnecessary if the original texture format was
5013 * Z32_FLOAT, but we don't know that here.
5014 */
5015 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
5016 z = ac_build_clamp(&ctx->ac, z);
5017
5018 address[count++] = z;
5019 }
5020
5021 /* pack derivatives */
5022 if (ddx || ddy) {
5023 int num_src_deriv_channels, num_dest_deriv_channels;
5024 switch (instr->sampler_dim) {
5025 case GLSL_SAMPLER_DIM_3D:
5026 case GLSL_SAMPLER_DIM_CUBE:
5027 num_deriv_comp = 3;
5028 num_src_deriv_channels = 3;
5029 num_dest_deriv_channels = 3;
5030 break;
5031 case GLSL_SAMPLER_DIM_2D:
5032 default:
5033 num_src_deriv_channels = 2;
5034 num_dest_deriv_channels = 2;
5035 num_deriv_comp = 2;
5036 break;
5037 case GLSL_SAMPLER_DIM_1D:
5038 num_src_deriv_channels = 1;
5039 if (ctx->ac.chip_class >= GFX9) {
5040 num_dest_deriv_channels = 2;
5041 num_deriv_comp = 2;
5042 } else {
5043 num_dest_deriv_channels = 1;
5044 num_deriv_comp = 1;
5045 }
5046 break;
5047 }
5048
5049 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
5050 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
5051 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
5052 }
5053 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
5054 derivs[i] = ctx->ac.f32_0;
5055 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
5056 }
5057 }
5058
5059 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
5060 for (chan = 0; chan < instr->coord_components; chan++)
5061 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
5062 if (instr->coord_components == 3)
5063 coords[3] = LLVMGetUndef(ctx->ac.f32);
5064 ac_prepare_cube_coords(&ctx->ac,
5065 instr->op == nir_texop_txd, instr->is_array,
5066 instr->op == nir_texop_lod, coords, derivs);
5067 if (num_deriv_comp)
5068 num_deriv_comp--;
5069 }
5070
5071 if (ddx || ddy) {
5072 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
5073 address[count++] = derivs[i];
5074 }
5075
5076 /* Pack texture coordinates */
5077 if (coord) {
5078 address[count++] = coords[0];
5079 if (instr->coord_components > 1) {
5080 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
5081 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
5082 }
5083 address[count++] = coords[1];
5084 }
5085 if (instr->coord_components > 2) {
5086 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
5087 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
5088 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
5089 instr->op != nir_texop_txf) {
5090 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
5091 }
5092 address[count++] = coords[2];
5093 }
5094
5095 if (ctx->ac.chip_class >= GFX9) {
5096 LLVMValueRef filler;
5097 if (instr->op == nir_texop_txf)
5098 filler = ctx->ac.i32_0;
5099 else
5100 filler = LLVMConstReal(ctx->ac.f32, 0.5);
5101
5102 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
5103 /* No nir_texop_lod, because it does not take a slice
5104 * even with array textures. */
5105 if (instr->is_array && instr->op != nir_texop_lod ) {
5106 address[count] = address[count - 1];
5107 address[count - 1] = filler;
5108 count++;
5109 } else
5110 address[count++] = filler;
5111 }
5112 }
5113 }
5114
5115 /* Pack LOD */
5116 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5117 instr->op == nir_texop_txf)) {
5118 address[count++] = lod;
5119 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5120 address[count++] = sample_index;
5121 } else if(instr->op == nir_texop_txs) {
5122 count = 0;
5123 if (lod)
5124 address[count++] = lod;
5125 else
5126 address[count++] = ctx->ac.i32_0;
5127 }
5128
5129 for (chan = 0; chan < count; chan++) {
5130 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5131 address[chan], ctx->ac.i32, "");
5132 }
5133
5134 if (instr->op == nir_texop_samples_identical) {
5135 LLVMValueRef txf_address[4];
5136 struct ac_image_args txf_args = { 0 };
5137 unsigned txf_count = count;
5138 memcpy(txf_address, address, sizeof(txf_address));
5139
5140 if (!instr->is_array)
5141 txf_address[2] = ctx->ac.i32_0;
5142 txf_address[3] = ctx->ac.i32_0;
5143
5144 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5145 fmask_ptr, NULL,
5146 txf_address, txf_count, 0xf);
5147
5148 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5149
5150 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5151 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5152 goto write_result;
5153 }
5154
5155 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5156 instr->op != nir_texop_txs) {
5157 unsigned sample_chan = instr->is_array ? 3 : 2;
5158 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5159 address[0],
5160 address[1],
5161 instr->is_array ? address[2] : NULL,
5162 address[sample_chan],
5163 fmask_ptr);
5164 }
5165
5166 if (offsets && instr->op == nir_texop_txf) {
5167 nir_const_value *const_offset =
5168 nir_src_as_const_value(instr->src[const_src].src);
5169 int num_offsets = instr->src[const_src].src.ssa->num_components;
5170 assert(const_offset);
5171 num_offsets = MIN2(num_offsets, instr->coord_components);
5172 if (num_offsets > 2)
5173 address[2] = LLVMBuildAdd(ctx->ac.builder,
5174 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5175 if (num_offsets > 1)
5176 address[1] = LLVMBuildAdd(ctx->ac.builder,
5177 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5178 address[0] = LLVMBuildAdd(ctx->ac.builder,
5179 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5180
5181 }
5182
5183 /* TODO TG4 support */
5184 if (instr->op == nir_texop_tg4) {
5185 if (instr->is_shadow)
5186 dmask = 1;
5187 else
5188 dmask = 1 << instr->component;
5189 }
5190 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5191 res_ptr, samp_ptr, address, count, dmask);
5192
5193 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5194
5195 if (instr->op == nir_texop_query_levels)
5196 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5197 else if (instr->is_shadow && instr->is_new_style_shadow &&
5198 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5199 instr->op != nir_texop_tg4)
5200 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5201 else if (instr->op == nir_texop_txs &&
5202 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5203 instr->is_array) {
5204 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5205 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5206 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5207 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5208 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5209 } else if (ctx->ac.chip_class >= GFX9 &&
5210 instr->op == nir_texop_txs &&
5211 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5212 instr->is_array) {
5213 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5214 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5215 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5216 ctx->ac.i32_1, "");
5217 } else if (instr->dest.ssa.num_components != 4)
5218 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5219
5220 write_result:
5221 if (result) {
5222 assert(instr->dest.is_ssa);
5223 result = ac_to_integer(&ctx->ac, result);
5224 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5225 }
5226 }
5227
5228
5229 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5230 {
5231 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5232 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5233
5234 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5235 _mesa_hash_table_insert(ctx->phis, instr, result);
5236 }
5237
5238 static void visit_post_phi(struct ac_nir_context *ctx,
5239 nir_phi_instr *instr,
5240 LLVMValueRef llvm_phi)
5241 {
5242 nir_foreach_phi_src(src, instr) {
5243 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5244 LLVMValueRef llvm_src = get_src(ctx, src->src);
5245
5246 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5247 }
5248 }
5249
5250 static void phi_post_pass(struct ac_nir_context *ctx)
5251 {
5252 struct hash_entry *entry;
5253 hash_table_foreach(ctx->phis, entry) {
5254 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5255 (LLVMValueRef)entry->data);
5256 }
5257 }
5258
5259
5260 static void visit_ssa_undef(struct ac_nir_context *ctx,
5261 const nir_ssa_undef_instr *instr)
5262 {
5263 unsigned num_components = instr->def.num_components;
5264 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5265 LLVMValueRef undef;
5266
5267 if (num_components == 1)
5268 undef = LLVMGetUndef(type);
5269 else {
5270 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5271 }
5272 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5273 }
5274
5275 static void visit_jump(struct ac_nir_context *ctx,
5276 const nir_jump_instr *instr)
5277 {
5278 switch (instr->type) {
5279 case nir_jump_break:
5280 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5281 LLVMClearInsertionPosition(ctx->ac.builder);
5282 break;
5283 case nir_jump_continue:
5284 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5285 LLVMClearInsertionPosition(ctx->ac.builder);
5286 break;
5287 default:
5288 fprintf(stderr, "Unknown NIR jump instr: ");
5289 nir_print_instr(&instr->instr, stderr);
5290 fprintf(stderr, "\n");
5291 abort();
5292 }
5293 }
5294
5295 static void visit_cf_list(struct ac_nir_context *ctx,
5296 struct exec_list *list);
5297
5298 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5299 {
5300 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5301 nir_foreach_instr(instr, block)
5302 {
5303 switch (instr->type) {
5304 case nir_instr_type_alu:
5305 visit_alu(ctx, nir_instr_as_alu(instr));
5306 break;
5307 case nir_instr_type_load_const:
5308 visit_load_const(ctx, nir_instr_as_load_const(instr));
5309 break;
5310 case nir_instr_type_intrinsic:
5311 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5312 break;
5313 case nir_instr_type_tex:
5314 visit_tex(ctx, nir_instr_as_tex(instr));
5315 break;
5316 case nir_instr_type_phi:
5317 visit_phi(ctx, nir_instr_as_phi(instr));
5318 break;
5319 case nir_instr_type_ssa_undef:
5320 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5321 break;
5322 case nir_instr_type_jump:
5323 visit_jump(ctx, nir_instr_as_jump(instr));
5324 break;
5325 default:
5326 fprintf(stderr, "Unknown NIR instr type: ");
5327 nir_print_instr(instr, stderr);
5328 fprintf(stderr, "\n");
5329 abort();
5330 }
5331 }
5332
5333 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5334 }
5335
5336 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5337 {
5338 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5339
5340 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5341 LLVMBasicBlockRef merge_block =
5342 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5343 LLVMBasicBlockRef if_block =
5344 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5345 LLVMBasicBlockRef else_block = merge_block;
5346 if (!exec_list_is_empty(&if_stmt->else_list))
5347 else_block = LLVMAppendBasicBlockInContext(
5348 ctx->ac.context, fn, "");
5349
5350 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5351 ctx->ac.i32_0, "");
5352 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5353
5354 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5355 visit_cf_list(ctx, &if_stmt->then_list);
5356 if (LLVMGetInsertBlock(ctx->ac.builder))
5357 LLVMBuildBr(ctx->ac.builder, merge_block);
5358
5359 if (!exec_list_is_empty(&if_stmt->else_list)) {
5360 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5361 visit_cf_list(ctx, &if_stmt->else_list);
5362 if (LLVMGetInsertBlock(ctx->ac.builder))
5363 LLVMBuildBr(ctx->ac.builder, merge_block);
5364 }
5365
5366 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5367 }
5368
5369 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5370 {
5371 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5372 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5373 LLVMBasicBlockRef break_parent = ctx->break_block;
5374
5375 ctx->continue_block =
5376 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5377 ctx->break_block =
5378 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5379
5380 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5381 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5382 visit_cf_list(ctx, &loop->body);
5383
5384 if (LLVMGetInsertBlock(ctx->ac.builder))
5385 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5386 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5387
5388 ctx->continue_block = continue_parent;
5389 ctx->break_block = break_parent;
5390 }
5391
5392 static void visit_cf_list(struct ac_nir_context *ctx,
5393 struct exec_list *list)
5394 {
5395 foreach_list_typed(nir_cf_node, node, node, list)
5396 {
5397 switch (node->type) {
5398 case nir_cf_node_block:
5399 visit_block(ctx, nir_cf_node_as_block(node));
5400 break;
5401
5402 case nir_cf_node_if:
5403 visit_if(ctx, nir_cf_node_as_if(node));
5404 break;
5405
5406 case nir_cf_node_loop:
5407 visit_loop(ctx, nir_cf_node_as_loop(node));
5408 break;
5409
5410 default:
5411 assert(0);
5412 }
5413 }
5414 }
5415
5416 static void
5417 handle_vs_input_decl(struct radv_shader_context *ctx,
5418 struct nir_variable *variable)
5419 {
5420 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5421 LLVMValueRef t_offset;
5422 LLVMValueRef t_list;
5423 LLVMValueRef input;
5424 LLVMValueRef buffer_index;
5425 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5426 int idx = variable->data.location;
5427 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5428 uint8_t input_usage_mask =
5429 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5430 unsigned num_channels = util_last_bit(input_usage_mask);
5431
5432 variable->data.driver_location = idx * 4;
5433
5434 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5435 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5436 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
5437 ctx->abi.start_instance, "");
5438 if (ctx->options->key.vs.as_ls) {
5439 ctx->shader_info->vs.vgpr_comp_cnt =
5440 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5441 } else {
5442 ctx->shader_info->vs.vgpr_comp_cnt =
5443 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5444 }
5445 } else
5446 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
5447 ctx->abi.base_vertex, "");
5448 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5449
5450 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5451
5452 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5453 buffer_index,
5454 ctx->ac.i32_0,
5455 num_channels, false, true);
5456
5457 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5458
5459 for (unsigned chan = 0; chan < 4; chan++) {
5460 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5461 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5462 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
5463 input, llvm_chan, ""));
5464 }
5465 }
5466 }
5467
5468 static void interp_fs_input(struct radv_shader_context *ctx,
5469 unsigned attr,
5470 LLVMValueRef interp_param,
5471 LLVMValueRef prim_mask,
5472 LLVMValueRef result[4])
5473 {
5474 LLVMValueRef attr_number;
5475 unsigned chan;
5476 LLVMValueRef i, j;
5477 bool interp = interp_param != NULL;
5478
5479 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5480
5481 /* fs.constant returns the param from the middle vertex, so it's not
5482 * really useful for flat shading. It's meant to be used for custom
5483 * interpolation (but the intrinsic can't fetch from the other two
5484 * vertices).
5485 *
5486 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5487 * to do the right thing. The only reason we use fs.constant is that
5488 * fs.interp cannot be used on integers, because they can be equal
5489 * to NaN.
5490 */
5491 if (interp) {
5492 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
5493 ctx->ac.v2f32, "");
5494
5495 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5496 ctx->ac.i32_0, "");
5497 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5498 ctx->ac.i32_1, "");
5499 }
5500
5501 for (chan = 0; chan < 4; chan++) {
5502 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5503
5504 if (interp) {
5505 result[chan] = ac_build_fs_interp(&ctx->ac,
5506 llvm_chan,
5507 attr_number,
5508 prim_mask, i, j);
5509 } else {
5510 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5511 LLVMConstInt(ctx->ac.i32, 2, false),
5512 llvm_chan,
5513 attr_number,
5514 prim_mask);
5515 }
5516 }
5517 }
5518
5519 static void
5520 handle_fs_input_decl(struct radv_shader_context *ctx,
5521 struct nir_variable *variable)
5522 {
5523 int idx = variable->data.location;
5524 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5525 LLVMValueRef interp;
5526
5527 variable->data.driver_location = idx * 4;
5528 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5529
5530 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5531 unsigned interp_type;
5532 if (variable->data.sample)
5533 interp_type = INTERP_SAMPLE;
5534 else if (variable->data.centroid)
5535 interp_type = INTERP_CENTROID;
5536 else
5537 interp_type = INTERP_CENTER;
5538
5539 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5540 } else
5541 interp = NULL;
5542
5543 for (unsigned i = 0; i < attrib_count; ++i)
5544 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5545
5546 }
5547
5548 static void
5549 handle_vs_inputs(struct radv_shader_context *ctx,
5550 struct nir_shader *nir) {
5551 nir_foreach_variable(variable, &nir->inputs)
5552 handle_vs_input_decl(ctx, variable);
5553 }
5554
5555 static void
5556 prepare_interp_optimize(struct radv_shader_context *ctx,
5557 struct nir_shader *nir)
5558 {
5559 if (!ctx->options->key.fs.multisample)
5560 return;
5561
5562 bool uses_center = false;
5563 bool uses_centroid = false;
5564 nir_foreach_variable(variable, &nir->inputs) {
5565 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5566 variable->data.sample)
5567 continue;
5568
5569 if (variable->data.centroid)
5570 uses_centroid = true;
5571 else
5572 uses_center = true;
5573 }
5574
5575 if (uses_center && uses_centroid) {
5576 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5577 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5578 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5579 }
5580 }
5581
5582 static void
5583 handle_fs_inputs(struct radv_shader_context *ctx,
5584 struct nir_shader *nir)
5585 {
5586 prepare_interp_optimize(ctx, nir);
5587
5588 nir_foreach_variable(variable, &nir->inputs)
5589 handle_fs_input_decl(ctx, variable);
5590
5591 unsigned index = 0;
5592
5593 if (ctx->shader_info->info.ps.uses_input_attachments ||
5594 ctx->shader_info->info.needs_multiview_view_index)
5595 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5596
5597 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5598 LLVMValueRef interp_param;
5599 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5600
5601 if (!(ctx->input_mask & (1ull << i)))
5602 continue;
5603
5604 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5605 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5606 interp_param = *inputs;
5607 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5608 inputs);
5609
5610 if (!interp_param)
5611 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5612 ++index;
5613 } else if (i == VARYING_SLOT_POS) {
5614 for(int i = 0; i < 3; ++i)
5615 inputs[i] = ctx->abi.frag_pos[i];
5616
5617 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5618 ctx->abi.frag_pos[3]);
5619 }
5620 }
5621 ctx->shader_info->fs.num_interp = index;
5622 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5623 ctx->shader_info->fs.has_pcoord = true;
5624 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5625 ctx->shader_info->fs.prim_id_input = true;
5626 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5627 ctx->shader_info->fs.layer_input = true;
5628 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5629
5630 if (ctx->shader_info->info.needs_multiview_view_index)
5631 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5632 }
5633
5634 static LLVMValueRef
5635 ac_build_alloca(struct ac_llvm_context *ac,
5636 LLVMTypeRef type,
5637 const char *name)
5638 {
5639 LLVMBuilderRef builder = ac->builder;
5640 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5641 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5642 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5643 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5644 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5645 LLVMValueRef res;
5646
5647 if (first_instr) {
5648 LLVMPositionBuilderBefore(first_builder, first_instr);
5649 } else {
5650 LLVMPositionBuilderAtEnd(first_builder, first_block);
5651 }
5652
5653 res = LLVMBuildAlloca(first_builder, type, name);
5654 LLVMBuildStore(builder, LLVMConstNull(type), res);
5655
5656 LLVMDisposeBuilder(first_builder);
5657
5658 return res;
5659 }
5660
5661 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5662 LLVMTypeRef type,
5663 const char *name)
5664 {
5665 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5666 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5667 return ptr;
5668 }
5669
5670 static void
5671 scan_shader_output_decl(struct radv_shader_context *ctx,
5672 struct nir_variable *variable,
5673 struct nir_shader *shader,
5674 gl_shader_stage stage)
5675 {
5676 int idx = variable->data.location + variable->data.index;
5677 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5678 uint64_t mask_attribs;
5679
5680 variable->data.driver_location = idx * 4;
5681
5682 /* tess ctrl has it's own load/store paths for outputs */
5683 if (stage == MESA_SHADER_TESS_CTRL)
5684 return;
5685
5686 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5687 if (stage == MESA_SHADER_VERTEX ||
5688 stage == MESA_SHADER_TESS_EVAL ||
5689 stage == MESA_SHADER_GEOMETRY) {
5690 if (idx == VARYING_SLOT_CLIP_DIST0) {
5691 int length = shader->info.clip_distance_array_size +
5692 shader->info.cull_distance_array_size;
5693 if (stage == MESA_SHADER_VERTEX) {
5694 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5695 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5696 }
5697 if (stage == MESA_SHADER_TESS_EVAL) {
5698 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5699 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5700 }
5701
5702 if (length > 4)
5703 attrib_count = 2;
5704 else
5705 attrib_count = 1;
5706 mask_attribs = 1ull << idx;
5707 }
5708 }
5709
5710 ctx->output_mask |= mask_attribs;
5711 }
5712
5713 static void
5714 handle_shader_output_decl(struct ac_nir_context *ctx,
5715 struct nir_shader *nir,
5716 struct nir_variable *variable)
5717 {
5718 unsigned output_loc = variable->data.driver_location / 4;
5719 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5720
5721 /* tess ctrl has it's own load/store paths for outputs */
5722 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5723 return;
5724
5725 if (ctx->stage == MESA_SHADER_VERTEX ||
5726 ctx->stage == MESA_SHADER_TESS_EVAL ||
5727 ctx->stage == MESA_SHADER_GEOMETRY) {
5728 int idx = variable->data.location + variable->data.index;
5729 if (idx == VARYING_SLOT_CLIP_DIST0) {
5730 int length = nir->info.clip_distance_array_size +
5731 nir->info.cull_distance_array_size;
5732
5733 if (length > 4)
5734 attrib_count = 2;
5735 else
5736 attrib_count = 1;
5737 }
5738 }
5739
5740 for (unsigned i = 0; i < attrib_count; ++i) {
5741 for (unsigned chan = 0; chan < 4; chan++) {
5742 ctx->abi->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5743 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5744 }
5745 }
5746 }
5747
5748 static LLVMTypeRef
5749 glsl_base_to_llvm_type(struct ac_llvm_context *ac,
5750 enum glsl_base_type type)
5751 {
5752 switch (type) {
5753 case GLSL_TYPE_INT:
5754 case GLSL_TYPE_UINT:
5755 case GLSL_TYPE_BOOL:
5756 case GLSL_TYPE_SUBROUTINE:
5757 return ac->i32;
5758 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5759 return ac->f32;
5760 case GLSL_TYPE_INT64:
5761 case GLSL_TYPE_UINT64:
5762 return ac->i64;
5763 case GLSL_TYPE_DOUBLE:
5764 return ac->f64;
5765 default:
5766 unreachable("unknown GLSL type");
5767 }
5768 }
5769
5770 static LLVMTypeRef
5771 glsl_to_llvm_type(struct ac_llvm_context *ac,
5772 const struct glsl_type *type)
5773 {
5774 if (glsl_type_is_scalar(type)) {
5775 return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
5776 }
5777
5778 if (glsl_type_is_vector(type)) {
5779 return LLVMVectorType(
5780 glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
5781 glsl_get_vector_elements(type));
5782 }
5783
5784 if (glsl_type_is_matrix(type)) {
5785 return LLVMArrayType(
5786 glsl_to_llvm_type(ac, glsl_get_column_type(type)),
5787 glsl_get_matrix_columns(type));
5788 }
5789
5790 if (glsl_type_is_array(type)) {
5791 return LLVMArrayType(
5792 glsl_to_llvm_type(ac, glsl_get_array_element(type)),
5793 glsl_get_length(type));
5794 }
5795
5796 assert(glsl_type_is_struct(type));
5797
5798 LLVMTypeRef member_types[glsl_get_length(type)];
5799
5800 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5801 member_types[i] =
5802 glsl_to_llvm_type(ac,
5803 glsl_get_struct_field(type, i));
5804 }
5805
5806 return LLVMStructTypeInContext(ac->context, member_types,
5807 glsl_get_length(type), false);
5808 }
5809
5810 static void
5811 setup_locals(struct ac_nir_context *ctx,
5812 struct nir_function *func)
5813 {
5814 int i, j;
5815 ctx->num_locals = 0;
5816 nir_foreach_variable(variable, &func->impl->locals) {
5817 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5818 variable->data.driver_location = ctx->num_locals * 4;
5819 variable->data.location_frac = 0;
5820 ctx->num_locals += attrib_count;
5821 }
5822 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5823 if (!ctx->locals)
5824 return;
5825
5826 for (i = 0; i < ctx->num_locals; i++) {
5827 for (j = 0; j < 4; j++) {
5828 ctx->locals[i * 4 + j] =
5829 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5830 }
5831 }
5832 }
5833
5834 static void
5835 setup_shared(struct ac_nir_context *ctx,
5836 struct nir_shader *nir)
5837 {
5838 nir_foreach_variable(variable, &nir->shared) {
5839 LLVMValueRef shared =
5840 LLVMAddGlobalInAddressSpace(
5841 ctx->ac.module, glsl_to_llvm_type(&ctx->ac, variable->type),
5842 variable->name ? variable->name : "",
5843 AC_LOCAL_ADDR_SPACE);
5844 _mesa_hash_table_insert(ctx->vars, variable, shared);
5845 }
5846 }
5847
5848 /* Initialize arguments for the shader export intrinsic */
5849 static void
5850 si_llvm_init_export_args(struct radv_shader_context *ctx,
5851 LLVMValueRef *values,
5852 unsigned target,
5853 struct ac_export_args *args)
5854 {
5855 /* Default is 0xf. Adjusted below depending on the format. */
5856 args->enabled_channels = 0xf;
5857
5858 /* Specify whether the EXEC mask represents the valid mask */
5859 args->valid_mask = 0;
5860
5861 /* Specify whether this is the last export */
5862 args->done = 0;
5863
5864 /* Specify the target we are exporting */
5865 args->target = target;
5866
5867 args->compr = false;
5868 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5869 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5870 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5871 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5872
5873 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5874 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5875 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5876 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5877 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5878 unsigned chan;
5879
5880 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5881 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5882 unsigned bits, bool hi) = NULL;
5883
5884 switch(col_format) {
5885 case V_028714_SPI_SHADER_ZERO:
5886 args->enabled_channels = 0; /* writemask */
5887 args->target = V_008DFC_SQ_EXP_NULL;
5888 break;
5889
5890 case V_028714_SPI_SHADER_32_R:
5891 args->enabled_channels = 1;
5892 args->out[0] = values[0];
5893 break;
5894
5895 case V_028714_SPI_SHADER_32_GR:
5896 args->enabled_channels = 0x3;
5897 args->out[0] = values[0];
5898 args->out[1] = values[1];
5899 break;
5900
5901 case V_028714_SPI_SHADER_32_AR:
5902 args->enabled_channels = 0x9;
5903 args->out[0] = values[0];
5904 args->out[3] = values[3];
5905 break;
5906
5907 case V_028714_SPI_SHADER_FP16_ABGR:
5908 packf = ac_build_cvt_pkrtz_f16;
5909 break;
5910
5911 case V_028714_SPI_SHADER_UNORM16_ABGR:
5912 packf = ac_build_cvt_pknorm_u16;
5913 break;
5914
5915 case V_028714_SPI_SHADER_SNORM16_ABGR:
5916 packf = ac_build_cvt_pknorm_i16;
5917 break;
5918
5919 case V_028714_SPI_SHADER_UINT16_ABGR:
5920 packi = ac_build_cvt_pk_u16;
5921 break;
5922
5923 case V_028714_SPI_SHADER_SINT16_ABGR:
5924 packi = ac_build_cvt_pk_i16;
5925 break;
5926
5927 default:
5928 case V_028714_SPI_SHADER_32_ABGR:
5929 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5930 break;
5931 }
5932
5933 /* Pack f16 or norm_i16/u16. */
5934 if (packf) {
5935 for (chan = 0; chan < 2; chan++) {
5936 LLVMValueRef pack_args[2] = {
5937 values[2 * chan],
5938 values[2 * chan + 1]
5939 };
5940 LLVMValueRef packed;
5941
5942 packed = packf(&ctx->ac, pack_args);
5943 args->out[chan] = ac_to_float(&ctx->ac, packed);
5944 }
5945 args->compr = 1; /* COMPR flag */
5946 }
5947
5948 /* Pack i16/u16. */
5949 if (packi) {
5950 for (chan = 0; chan < 2; chan++) {
5951 LLVMValueRef pack_args[2] = {
5952 ac_to_integer(&ctx->ac, values[2 * chan]),
5953 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5954 };
5955 LLVMValueRef packed;
5956
5957 packed = packi(&ctx->ac, pack_args,
5958 is_int8 ? 8 : is_int10 ? 10 : 16,
5959 chan == 1);
5960 args->out[chan] = ac_to_float(&ctx->ac, packed);
5961 }
5962 args->compr = 1; /* COMPR flag */
5963 }
5964 return;
5965 }
5966
5967 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5968
5969 for (unsigned i = 0; i < 4; ++i)
5970 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5971 }
5972
5973 static void
5974 radv_export_param(struct radv_shader_context *ctx, unsigned index,
5975 LLVMValueRef *values)
5976 {
5977 struct ac_export_args args;
5978
5979 si_llvm_init_export_args(ctx, values,
5980 V_008DFC_SQ_EXP_PARAM + index, &args);
5981 ac_build_export(&ctx->ac, &args);
5982 }
5983
5984 static LLVMValueRef
5985 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
5986 {
5987 LLVMValueRef output =
5988 ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
5989
5990 return LLVMBuildLoad(ctx->ac.builder, output, "");
5991 }
5992
5993 static void
5994 handle_vs_outputs_post(struct radv_shader_context *ctx,
5995 bool export_prim_id,
5996 struct ac_vs_output_info *outinfo)
5997 {
5998 uint32_t param_count = 0;
5999 unsigned target;
6000 unsigned pos_idx, num_pos_exports = 0;
6001 struct ac_export_args args, pos_args[4] = {};
6002 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
6003 int i;
6004
6005 if (ctx->options->key.has_multiview_view_index) {
6006 LLVMValueRef* tmp_out = &ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
6007 if(!*tmp_out) {
6008 for(unsigned i = 0; i < 4; ++i)
6009 ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
6010 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
6011 }
6012
6013 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
6014 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
6015 }
6016
6017 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6018 sizeof(outinfo->vs_output_param_offset));
6019
6020 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
6021 LLVMValueRef slots[8];
6022 unsigned j;
6023
6024 if (outinfo->cull_dist_mask)
6025 outinfo->cull_dist_mask <<= ctx->num_output_clips;
6026
6027 i = VARYING_SLOT_CLIP_DIST0;
6028 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
6029 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6030
6031 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
6032 slots[i] = LLVMGetUndef(ctx->ac.f32);
6033
6034 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
6035 target = V_008DFC_SQ_EXP_POS + 3;
6036 si_llvm_init_export_args(ctx, &slots[4], target, &args);
6037 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6038 &args, sizeof(args));
6039 }
6040
6041 target = V_008DFC_SQ_EXP_POS + 2;
6042 si_llvm_init_export_args(ctx, &slots[0], target, &args);
6043 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6044 &args, sizeof(args));
6045
6046 }
6047
6048 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
6049 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
6050 for (unsigned j = 0; j < 4; j++)
6051 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
6052 }
6053 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
6054
6055 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
6056 outinfo->writes_pointsize = true;
6057 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
6058 }
6059
6060 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
6061 outinfo->writes_layer = true;
6062 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
6063 }
6064
6065 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
6066 outinfo->writes_viewport_index = true;
6067 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
6068 }
6069
6070 if (outinfo->writes_pointsize ||
6071 outinfo->writes_layer ||
6072 outinfo->writes_viewport_index) {
6073 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
6074 (outinfo->writes_layer == true ? 4 : 0));
6075 pos_args[1].valid_mask = 0;
6076 pos_args[1].done = 0;
6077 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6078 pos_args[1].compr = 0;
6079 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6080 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6081 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6082 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6083
6084 if (outinfo->writes_pointsize == true)
6085 pos_args[1].out[0] = psize_value;
6086 if (outinfo->writes_layer == true)
6087 pos_args[1].out[2] = layer_value;
6088 if (outinfo->writes_viewport_index == true) {
6089 if (ctx->options->chip_class >= GFX9) {
6090 /* GFX9 has the layer in out.z[10:0] and the viewport
6091 * index in out.z[19:16].
6092 */
6093 LLVMValueRef v = viewport_index_value;
6094 v = ac_to_integer(&ctx->ac, v);
6095 v = LLVMBuildShl(ctx->ac.builder, v,
6096 LLVMConstInt(ctx->ac.i32, 16, false),
6097 "");
6098 v = LLVMBuildOr(ctx->ac.builder, v,
6099 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6100
6101 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6102 pos_args[1].enabled_channels |= 1 << 2;
6103 } else {
6104 pos_args[1].out[3] = viewport_index_value;
6105 pos_args[1].enabled_channels |= 1 << 3;
6106 }
6107 }
6108 }
6109 for (i = 0; i < 4; i++) {
6110 if (pos_args[i].out[0])
6111 num_pos_exports++;
6112 }
6113
6114 pos_idx = 0;
6115 for (i = 0; i < 4; i++) {
6116 if (!pos_args[i].out[0])
6117 continue;
6118
6119 /* Specify the target we are exporting */
6120 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6121 if (pos_idx == num_pos_exports)
6122 pos_args[i].done = 1;
6123 ac_build_export(&ctx->ac, &pos_args[i]);
6124 }
6125
6126 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6127 LLVMValueRef values[4];
6128 if (!(ctx->output_mask & (1ull << i)))
6129 continue;
6130
6131 if (i != VARYING_SLOT_LAYER &&
6132 i != VARYING_SLOT_PRIMITIVE_ID &&
6133 i < VARYING_SLOT_VAR0)
6134 continue;
6135
6136 for (unsigned j = 0; j < 4; j++)
6137 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6138
6139 radv_export_param(ctx, param_count, values);
6140
6141 outinfo->vs_output_param_offset[i] = param_count++;
6142 }
6143
6144 if (export_prim_id) {
6145 LLVMValueRef values[4];
6146
6147 values[0] = ctx->vs_prim_id;
6148 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6149 ctx->shader_info->vs.vgpr_comp_cnt);
6150 for (unsigned j = 1; j < 4; j++)
6151 values[j] = ctx->ac.f32_0;
6152
6153 radv_export_param(ctx, param_count, values);
6154
6155 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6156 outinfo->export_prim_id = true;
6157 }
6158
6159 outinfo->pos_exports = num_pos_exports;
6160 outinfo->param_exports = param_count;
6161 }
6162
6163 static void
6164 handle_es_outputs_post(struct radv_shader_context *ctx,
6165 struct ac_es_output_info *outinfo)
6166 {
6167 int j;
6168 uint64_t max_output_written = 0;
6169 LLVMValueRef lds_base = NULL;
6170
6171 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6172 int param_index;
6173 int length = 4;
6174
6175 if (!(ctx->output_mask & (1ull << i)))
6176 continue;
6177
6178 if (i == VARYING_SLOT_CLIP_DIST0)
6179 length = ctx->num_output_clips + ctx->num_output_culls;
6180
6181 param_index = shader_io_get_unique_index(i);
6182
6183 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6184 }
6185
6186 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6187
6188 if (ctx->ac.chip_class >= GFX9) {
6189 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6190 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6191 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6192 LLVMConstInt(ctx->ac.i32, 24, false),
6193 LLVMConstInt(ctx->ac.i32, 4, false), false);
6194 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6195 LLVMBuildMul(ctx->ac.builder, wave_idx,
6196 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6197 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6198 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6199 }
6200
6201 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6202 LLVMValueRef dw_addr = NULL;
6203 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6204 int param_index;
6205 int length = 4;
6206
6207 if (!(ctx->output_mask & (1ull << i)))
6208 continue;
6209
6210 if (i == VARYING_SLOT_CLIP_DIST0)
6211 length = ctx->num_output_clips + ctx->num_output_culls;
6212
6213 param_index = shader_io_get_unique_index(i);
6214
6215 if (lds_base) {
6216 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
6217 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6218 "");
6219 }
6220 for (j = 0; j < length; j++) {
6221 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
6222 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
6223
6224 if (ctx->ac.chip_class >= GFX9) {
6225 ac_lds_store(&ctx->ac, dw_addr,
6226 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6227 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6228 } else {
6229 ac_build_buffer_store_dword(&ctx->ac,
6230 ctx->esgs_ring,
6231 out_val, 1,
6232 NULL, ctx->es2gs_offset,
6233 (4 * param_index + j) * 4,
6234 1, 1, true, true);
6235 }
6236 }
6237 }
6238 }
6239
6240 static void
6241 handle_ls_outputs_post(struct radv_shader_context *ctx)
6242 {
6243 LLVMValueRef vertex_id = ctx->rel_auto_id;
6244 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6245 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
6246 vertex_dw_stride, "");
6247
6248 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6249 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6250 int length = 4;
6251
6252 if (!(ctx->output_mask & (1ull << i)))
6253 continue;
6254
6255 if (i == VARYING_SLOT_CLIP_DIST0)
6256 length = ctx->num_output_clips + ctx->num_output_culls;
6257 int param = shader_io_get_unique_index(i);
6258 mark_tess_output(ctx, false, param);
6259 if (length > 4)
6260 mark_tess_output(ctx, false, param + 1);
6261 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
6262 LLVMConstInt(ctx->ac.i32, param * 4, false),
6263 "");
6264 for (unsigned j = 0; j < length; j++) {
6265 ac_lds_store(&ctx->ac, dw_addr,
6266 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6267 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6268 }
6269 }
6270 }
6271
6272 struct ac_build_if_state
6273 {
6274 struct radv_shader_context *ctx;
6275 LLVMValueRef condition;
6276 LLVMBasicBlockRef entry_block;
6277 LLVMBasicBlockRef true_block;
6278 LLVMBasicBlockRef false_block;
6279 LLVMBasicBlockRef merge_block;
6280 };
6281
6282 static LLVMBasicBlockRef
6283 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
6284 {
6285 LLVMBasicBlockRef current_block;
6286 LLVMBasicBlockRef next_block;
6287 LLVMBasicBlockRef new_block;
6288
6289 /* get current basic block */
6290 current_block = LLVMGetInsertBlock(ctx->ac.builder);
6291
6292 /* chqeck if there's another block after this one */
6293 next_block = LLVMGetNextBasicBlock(current_block);
6294 if (next_block) {
6295 /* insert the new block before the next block */
6296 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6297 }
6298 else {
6299 /* append new block after current block */
6300 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6301 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6302 }
6303 return new_block;
6304 }
6305
6306 static void
6307 ac_nir_build_if(struct ac_build_if_state *ifthen,
6308 struct radv_shader_context *ctx,
6309 LLVMValueRef condition)
6310 {
6311 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
6312
6313 memset(ifthen, 0, sizeof *ifthen);
6314 ifthen->ctx = ctx;
6315 ifthen->condition = condition;
6316 ifthen->entry_block = block;
6317
6318 /* create endif/merge basic block for the phi functions */
6319 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6320
6321 /* create/insert true_block before merge_block */
6322 ifthen->true_block =
6323 LLVMInsertBasicBlockInContext(ctx->context,
6324 ifthen->merge_block,
6325 "if-true-block");
6326
6327 /* successive code goes into the true block */
6328 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
6329 }
6330
6331 /**
6332 * End a conditional.
6333 */
6334 static void
6335 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6336 {
6337 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
6338
6339 /* Insert branch to the merge block from current block */
6340 LLVMBuildBr(builder, ifthen->merge_block);
6341
6342 /*
6343 * Now patch in the various branch instructions.
6344 */
6345
6346 /* Insert the conditional branch instruction at the end of entry_block */
6347 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6348 if (ifthen->false_block) {
6349 /* we have an else clause */
6350 LLVMBuildCondBr(builder, ifthen->condition,
6351 ifthen->true_block, ifthen->false_block);
6352 }
6353 else {
6354 /* no else clause */
6355 LLVMBuildCondBr(builder, ifthen->condition,
6356 ifthen->true_block, ifthen->merge_block);
6357 }
6358
6359 /* Resume building code at end of the ifthen->merge_block */
6360 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6361 }
6362
6363 static void
6364 write_tess_factors(struct radv_shader_context *ctx)
6365 {
6366 unsigned stride, outer_comps, inner_comps;
6367 struct ac_build_if_state if_ctx, inner_if_ctx;
6368 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6369 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6370 unsigned tess_inner_index = 0, tess_outer_index;
6371 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
6372 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6373 int i;
6374 emit_barrier(&ctx->ac, ctx->stage);
6375
6376 switch (ctx->options->key.tcs.primitive_mode) {
6377 case GL_ISOLINES:
6378 stride = 2;
6379 outer_comps = 2;
6380 inner_comps = 0;
6381 break;
6382 case GL_TRIANGLES:
6383 stride = 4;
6384 outer_comps = 3;
6385 inner_comps = 1;
6386 break;
6387 case GL_QUADS:
6388 stride = 6;
6389 outer_comps = 4;
6390 inner_comps = 2;
6391 break;
6392 default:
6393 return;
6394 }
6395
6396 ac_nir_build_if(&if_ctx, ctx,
6397 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6398 invocation_id, ctx->ac.i32_0, ""));
6399
6400 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6401
6402 if (inner_comps) {
6403 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6404 mark_tess_output(ctx, true, tess_inner_index);
6405 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
6406 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6407 }
6408
6409 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6410 mark_tess_output(ctx, true, tess_outer_index);
6411 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
6412 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6413
6414 for (i = 0; i < 4; i++) {
6415 inner[i] = LLVMGetUndef(ctx->ac.i32);
6416 outer[i] = LLVMGetUndef(ctx->ac.i32);
6417 }
6418
6419 // LINES reverseal
6420 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6421 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6422 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6423 ctx->ac.i32_1, "");
6424 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6425 } else {
6426 for (i = 0; i < outer_comps; i++) {
6427 outer[i] = out[i] =
6428 ac_lds_load(&ctx->ac, lds_outer);
6429 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6430 ctx->ac.i32_1, "");
6431 }
6432 for (i = 0; i < inner_comps; i++) {
6433 inner[i] = out[outer_comps+i] =
6434 ac_lds_load(&ctx->ac, lds_inner);
6435 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
6436 ctx->ac.i32_1, "");
6437 }
6438 }
6439
6440 /* Convert the outputs to vectors for stores. */
6441 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6442 vec1 = NULL;
6443
6444 if (stride > 4)
6445 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6446
6447
6448 buffer = ctx->hs_ring_tess_factor;
6449 tf_base = ctx->tess_factor_offset;
6450 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
6451 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6452 unsigned tf_offset = 0;
6453
6454 if (ctx->options->chip_class <= VI) {
6455 ac_nir_build_if(&inner_if_ctx, ctx,
6456 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6457 rel_patch_id, ctx->ac.i32_0, ""));
6458
6459 /* Store the dynamic HS control word. */
6460 ac_build_buffer_store_dword(&ctx->ac, buffer,
6461 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6462 1, ctx->ac.i32_0, tf_base,
6463 0, 1, 0, true, false);
6464 tf_offset += 4;
6465
6466 ac_nir_build_endif(&inner_if_ctx);
6467 }
6468
6469 /* Store the tessellation factors. */
6470 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6471 MIN2(stride, 4), byteoffset, tf_base,
6472 tf_offset, 1, 0, true, false);
6473 if (vec1)
6474 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6475 stride - 4, byteoffset, tf_base,
6476 16 + tf_offset, 1, 0, true, false);
6477
6478 //store to offchip for TES to read - only if TES reads them
6479 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6480 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6481 LLVMValueRef tf_inner_offset;
6482 unsigned param_outer, param_inner;
6483
6484 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6485 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6486 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6487
6488 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6489 util_next_power_of_two(outer_comps));
6490
6491 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6492 outer_comps, tf_outer_offset,
6493 ctx->oc_lds, 0, 1, 0, true, false);
6494 if (inner_comps) {
6495 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6496 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6497 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6498
6499 inner_vec = inner_comps == 1 ? inner[0] :
6500 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6501 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6502 inner_comps, tf_inner_offset,
6503 ctx->oc_lds, 0, 1, 0, true, false);
6504 }
6505 }
6506 ac_nir_build_endif(&if_ctx);
6507 }
6508
6509 static void
6510 handle_tcs_outputs_post(struct radv_shader_context *ctx)
6511 {
6512 write_tess_factors(ctx);
6513 }
6514
6515 static bool
6516 si_export_mrt_color(struct radv_shader_context *ctx,
6517 LLVMValueRef *color, unsigned index, bool is_last,
6518 struct ac_export_args *args)
6519 {
6520 /* Export */
6521 si_llvm_init_export_args(ctx, color,
6522 V_008DFC_SQ_EXP_MRT + index, args);
6523
6524 if (is_last) {
6525 args->valid_mask = 1; /* whether the EXEC mask is valid */
6526 args->done = 1; /* DONE bit */
6527 } else if (!args->enabled_channels)
6528 return false; /* unnecessary NULL export */
6529
6530 return true;
6531 }
6532
6533 static void
6534 radv_export_mrt_z(struct radv_shader_context *ctx,
6535 LLVMValueRef depth, LLVMValueRef stencil,
6536 LLVMValueRef samplemask)
6537 {
6538 struct ac_export_args args;
6539
6540 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6541
6542 ac_build_export(&ctx->ac, &args);
6543 }
6544
6545 static void
6546 handle_fs_outputs_post(struct radv_shader_context *ctx)
6547 {
6548 unsigned index = 0;
6549 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6550 struct ac_export_args color_args[8];
6551
6552 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6553 LLVMValueRef values[4];
6554 bool last = false;
6555
6556 if (!(ctx->output_mask & (1ull << i)))
6557 continue;
6558
6559 if (i < FRAG_RESULT_DATA0)
6560 continue;
6561
6562 for (unsigned j = 0; j < 4; j++)
6563 values[j] = ac_to_float(&ctx->ac,
6564 radv_load_output(ctx, i, j));
6565
6566 if (!ctx->shader_info->info.ps.writes_z &&
6567 !ctx->shader_info->info.ps.writes_stencil &&
6568 !ctx->shader_info->info.ps.writes_sample_mask)
6569 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6570
6571 bool ret = si_export_mrt_color(ctx, values,
6572 i - FRAG_RESULT_DATA0,
6573 last, &color_args[index]);
6574 if (ret)
6575 index++;
6576 }
6577
6578 /* Process depth, stencil, samplemask. */
6579 if (ctx->shader_info->info.ps.writes_z) {
6580 depth = ac_to_float(&ctx->ac,
6581 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6582 }
6583 if (ctx->shader_info->info.ps.writes_stencil) {
6584 stencil = ac_to_float(&ctx->ac,
6585 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6586 }
6587 if (ctx->shader_info->info.ps.writes_sample_mask) {
6588 samplemask = ac_to_float(&ctx->ac,
6589 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6590 }
6591
6592 /* Export PS outputs. */
6593 for (unsigned i = 0; i < index; i++)
6594 ac_build_export(&ctx->ac, &color_args[i]);
6595
6596 if (depth || stencil || samplemask)
6597 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6598 else if (!index)
6599 ac_build_export_null(&ctx->ac);
6600 }
6601
6602 static void
6603 emit_gs_epilogue(struct radv_shader_context *ctx)
6604 {
6605 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6606 }
6607
6608 static void
6609 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6610 LLVMValueRef *addrs)
6611 {
6612 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
6613
6614 switch (ctx->stage) {
6615 case MESA_SHADER_VERTEX:
6616 if (ctx->options->key.vs.as_ls)
6617 handle_ls_outputs_post(ctx);
6618 else if (ctx->options->key.vs.as_es)
6619 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6620 else
6621 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6622 &ctx->shader_info->vs.outinfo);
6623 break;
6624 case MESA_SHADER_FRAGMENT:
6625 handle_fs_outputs_post(ctx);
6626 break;
6627 case MESA_SHADER_GEOMETRY:
6628 emit_gs_epilogue(ctx);
6629 break;
6630 case MESA_SHADER_TESS_CTRL:
6631 handle_tcs_outputs_post(ctx);
6632 break;
6633 case MESA_SHADER_TESS_EVAL:
6634 if (ctx->options->key.tes.as_es)
6635 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6636 else
6637 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6638 &ctx->shader_info->tes.outinfo);
6639 break;
6640 default:
6641 break;
6642 }
6643 }
6644
6645 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
6646 {
6647 LLVMPassManagerRef passmgr;
6648 /* Create the pass manager */
6649 passmgr = LLVMCreateFunctionPassManagerForModule(
6650 ctx->ac.module);
6651
6652 /* This pass should eliminate all the load and store instructions */
6653 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6654
6655 /* Add some optimization passes */
6656 LLVMAddScalarReplAggregatesPass(passmgr);
6657 LLVMAddLICMPass(passmgr);
6658 LLVMAddAggressiveDCEPass(passmgr);
6659 LLVMAddCFGSimplificationPass(passmgr);
6660 LLVMAddInstructionCombiningPass(passmgr);
6661
6662 /* Run the pass */
6663 LLVMInitializeFunctionPassManager(passmgr);
6664 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6665 LLVMFinalizeFunctionPassManager(passmgr);
6666
6667 LLVMDisposeBuilder(ctx->ac.builder);
6668 LLVMDisposePassManager(passmgr);
6669 }
6670
6671 static void
6672 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
6673 {
6674 struct ac_vs_output_info *outinfo;
6675
6676 switch (ctx->stage) {
6677 case MESA_SHADER_FRAGMENT:
6678 case MESA_SHADER_COMPUTE:
6679 case MESA_SHADER_TESS_CTRL:
6680 case MESA_SHADER_GEOMETRY:
6681 return;
6682 case MESA_SHADER_VERTEX:
6683 if (ctx->options->key.vs.as_ls ||
6684 ctx->options->key.vs.as_es)
6685 return;
6686 outinfo = &ctx->shader_info->vs.outinfo;
6687 break;
6688 case MESA_SHADER_TESS_EVAL:
6689 if (ctx->options->key.vs.as_es)
6690 return;
6691 outinfo = &ctx->shader_info->tes.outinfo;
6692 break;
6693 default:
6694 unreachable("Unhandled shader type");
6695 }
6696
6697 ac_optimize_vs_outputs(&ctx->ac,
6698 ctx->main_function,
6699 outinfo->vs_output_param_offset,
6700 VARYING_SLOT_MAX,
6701 &outinfo->param_exports);
6702 }
6703
6704 static void
6705 ac_setup_rings(struct radv_shader_context *ctx)
6706 {
6707 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6708 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6709 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6710 }
6711
6712 if (ctx->is_gs_copy_shader) {
6713 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6714 }
6715 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6716 LLVMValueRef tmp;
6717 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6718 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6719
6720 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6721
6722 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6723 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6724 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
6725 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6726 }
6727
6728 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6729 ctx->stage == MESA_SHADER_TESS_EVAL) {
6730 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6731 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6732 }
6733 }
6734
6735 static unsigned
6736 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6737 const struct nir_shader *nir)
6738 {
6739 switch (nir->info.stage) {
6740 case MESA_SHADER_TESS_CTRL:
6741 return chip_class >= CIK ? 128 : 64;
6742 case MESA_SHADER_GEOMETRY:
6743 return chip_class >= GFX9 ? 128 : 64;
6744 case MESA_SHADER_COMPUTE:
6745 break;
6746 default:
6747 return 0;
6748 }
6749
6750 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6751 nir->info.cs.local_size[1] *
6752 nir->info.cs.local_size[2];
6753 return max_workgroup_size;
6754 }
6755
6756 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6757 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
6758 {
6759 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6760 LLVMConstInt(ctx->ac.i32, 8, false),
6761 LLVMConstInt(ctx->ac.i32, 8, false), false);
6762 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6763 ctx->ac.i32_0, "");
6764 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6765 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6766 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6767 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6768 }
6769
6770 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
6771 {
6772 for(int i = 5; i >= 0; --i) {
6773 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6774 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6775 LLVMConstInt(ctx->ac.i32, 16, false), false);
6776 }
6777
6778 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6779 LLVMConstInt(ctx->ac.i32, 16, false),
6780 LLVMConstInt(ctx->ac.i32, 8, false), false);
6781 }
6782
6783 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6784 struct nir_shader *nir)
6785 {
6786 struct ac_nir_context ctx = {};
6787 struct nir_function *func;
6788
6789 ctx.ac = *ac;
6790 ctx.abi = abi;
6791
6792 ctx.stage = nir->info.stage;
6793
6794 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6795
6796 nir_foreach_variable(variable, &nir->outputs)
6797 handle_shader_output_decl(&ctx, nir, variable);
6798
6799 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6800 _mesa_key_pointer_equal);
6801 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6802 _mesa_key_pointer_equal);
6803 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6804 _mesa_key_pointer_equal);
6805
6806 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6807
6808 setup_locals(&ctx, func);
6809
6810 if (nir->info.stage == MESA_SHADER_COMPUTE)
6811 setup_shared(&ctx, nir);
6812
6813 visit_cf_list(&ctx, &func->impl->body);
6814 phi_post_pass(&ctx);
6815
6816 if (nir->info.stage != MESA_SHADER_COMPUTE)
6817 ctx.abi->emit_outputs(ctx.abi, AC_LLVM_MAX_OUTPUTS,
6818 ctx.abi->outputs);
6819
6820 free(ctx.locals);
6821 ralloc_free(ctx.defs);
6822 ralloc_free(ctx.phis);
6823 ralloc_free(ctx.vars);
6824 }
6825
6826 static
6827 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6828 struct nir_shader *const *shaders,
6829 int shader_count,
6830 struct ac_shader_variant_info *shader_info,
6831 const struct ac_nir_compiler_options *options)
6832 {
6833 struct radv_shader_context ctx = {0};
6834 unsigned i;
6835 ctx.options = options;
6836 ctx.shader_info = shader_info;
6837 ctx.context = LLVMContextCreate();
6838
6839 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6840 options->family);
6841 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6842 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6843
6844 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6845 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6846 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
6847 LLVMDisposeTargetData(data_layout);
6848 LLVMDisposeMessage(data_layout_str);
6849
6850 enum ac_float_mode float_mode =
6851 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6852 AC_FLOAT_MODE_DEFAULT;
6853
6854 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
6855
6856 memset(shader_info, 0, sizeof(*shader_info));
6857
6858 for(int i = 0; i < shader_count; ++i)
6859 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6860
6861 for (i = 0; i < AC_UD_MAX_SETS; i++)
6862 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6863 for (i = 0; i < AC_UD_MAX_UD; i++)
6864 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6865
6866 ctx.max_workgroup_size = 0;
6867 for (int i = 0; i < shader_count; ++i) {
6868 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6869 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6870 shaders[i]));
6871 }
6872
6873 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6874 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6875
6876 ctx.abi.inputs = &ctx.inputs[0];
6877 ctx.abi.emit_outputs = handle_shader_outputs_post;
6878 ctx.abi.emit_vertex = visit_emit_vertex;
6879 ctx.abi.load_ubo = radv_load_ubo;
6880 ctx.abi.load_ssbo = radv_load_ssbo;
6881 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6882 ctx.abi.load_resource = radv_load_resource;
6883 ctx.abi.clamp_shadow_reference = false;
6884
6885 if (shader_count >= 2)
6886 ac_init_exec_full_mask(&ctx.ac);
6887
6888 if (ctx.ac.chip_class == GFX9 &&
6889 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6890 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6891
6892 for(int i = 0; i < shader_count; ++i) {
6893 ctx.stage = shaders[i]->info.stage;
6894 ctx.output_mask = 0;
6895 ctx.tess_outputs_written = 0;
6896 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6897 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6898
6899 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6900 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6901 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6902 ctx.abi.load_inputs = load_gs_input;
6903 ctx.abi.emit_primitive = visit_end_primitive;
6904 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6905 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6906 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6907 ctx.abi.load_tess_varyings = load_tcs_varyings;
6908 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6909 ctx.abi.store_tcs_outputs = store_tcs_output;
6910 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6911 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6912 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6913 ctx.abi.load_tess_varyings = load_tes_input;
6914 ctx.abi.load_tess_coord = load_tess_coord;
6915 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6916 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6917 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6918 if (shader_info->info.vs.needs_instance_id) {
6919 if (ctx.options->key.vs.as_ls) {
6920 ctx.shader_info->vs.vgpr_comp_cnt =
6921 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6922 } else {
6923 ctx.shader_info->vs.vgpr_comp_cnt =
6924 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6925 }
6926 }
6927 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6928 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6929 ctx.abi.lookup_interp_param = lookup_interp_param;
6930 ctx.abi.load_sample_position = load_sample_position;
6931 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6932 }
6933
6934 if (i)
6935 emit_barrier(&ctx.ac, ctx.stage);
6936
6937 ac_setup_rings(&ctx);
6938
6939 LLVMBasicBlockRef merge_block;
6940 if (shader_count >= 2) {
6941 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6942 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6943 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6944
6945 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6946 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6947 LLVMConstInt(ctx.ac.i32, 8, false), false);
6948 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6949 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6950 thread_id, count, "");
6951 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6952
6953 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6954 }
6955
6956 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6957 handle_fs_inputs(&ctx, shaders[i]);
6958 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6959 handle_vs_inputs(&ctx, shaders[i]);
6960 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6961 prepare_gs_input_vgprs(&ctx);
6962
6963 nir_foreach_variable(variable, &shaders[i]->outputs)
6964 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6965
6966 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
6967
6968 if (shader_count >= 2) {
6969 LLVMBuildBr(ctx.ac.builder, merge_block);
6970 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6971 }
6972
6973 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6974 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6975 shaders[i]->info.cull_distance_array_size > 4;
6976 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6977 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6978 shaders[i]->info.gs.vertices_out;
6979 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6980 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6981 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6982 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6983 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6984 }
6985 }
6986
6987 LLVMBuildRetVoid(ctx.ac.builder);
6988
6989 if (options->dump_preoptir)
6990 ac_dump_module(ctx.ac.module);
6991
6992 ac_llvm_finalize_module(&ctx);
6993
6994 if (shader_count == 1)
6995 ac_nir_eliminate_const_vs_outputs(&ctx);
6996
6997 return ctx.ac.module;
6998 }
6999
7000 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
7001 {
7002 unsigned *retval = (unsigned *)context;
7003 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
7004 char *description = LLVMGetDiagInfoDescription(di);
7005
7006 if (severity == LLVMDSError) {
7007 *retval = 1;
7008 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
7009 description);
7010 }
7011
7012 LLVMDisposeMessage(description);
7013 }
7014
7015 static unsigned ac_llvm_compile(LLVMModuleRef M,
7016 struct ac_shader_binary *binary,
7017 LLVMTargetMachineRef tm)
7018 {
7019 unsigned retval = 0;
7020 char *err;
7021 LLVMContextRef llvm_ctx;
7022 LLVMMemoryBufferRef out_buffer;
7023 unsigned buffer_size;
7024 const char *buffer_data;
7025 LLVMBool mem_err;
7026
7027 /* Setup Diagnostic Handler*/
7028 llvm_ctx = LLVMGetModuleContext(M);
7029
7030 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
7031 &retval);
7032
7033 /* Compile IR*/
7034 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
7035 &err, &out_buffer);
7036
7037 /* Process Errors/Warnings */
7038 if (mem_err) {
7039 fprintf(stderr, "%s: %s", __FUNCTION__, err);
7040 free(err);
7041 retval = 1;
7042 goto out;
7043 }
7044
7045 /* Extract Shader Code*/
7046 buffer_size = LLVMGetBufferSize(out_buffer);
7047 buffer_data = LLVMGetBufferStart(out_buffer);
7048
7049 ac_elf_read(buffer_data, buffer_size, binary);
7050
7051 /* Clean up */
7052 LLVMDisposeMemoryBuffer(out_buffer);
7053
7054 out:
7055 return retval;
7056 }
7057
7058 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
7059 LLVMModuleRef llvm_module,
7060 struct ac_shader_binary *binary,
7061 struct ac_shader_config *config,
7062 struct ac_shader_variant_info *shader_info,
7063 gl_shader_stage stage,
7064 bool dump_shader, bool supports_spill)
7065 {
7066 if (dump_shader)
7067 ac_dump_module(llvm_module);
7068
7069 memset(binary, 0, sizeof(*binary));
7070 int v = ac_llvm_compile(llvm_module, binary, tm);
7071 if (v) {
7072 fprintf(stderr, "compile failed\n");
7073 }
7074
7075 if (dump_shader)
7076 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7077
7078 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7079
7080 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7081 LLVMDisposeModule(llvm_module);
7082 LLVMContextDispose(ctx);
7083
7084 if (stage == MESA_SHADER_FRAGMENT) {
7085 shader_info->num_input_vgprs = 0;
7086 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7087 shader_info->num_input_vgprs += 2;
7088 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7089 shader_info->num_input_vgprs += 2;
7090 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7091 shader_info->num_input_vgprs += 2;
7092 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7093 shader_info->num_input_vgprs += 3;
7094 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7095 shader_info->num_input_vgprs += 2;
7096 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7097 shader_info->num_input_vgprs += 2;
7098 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7099 shader_info->num_input_vgprs += 2;
7100 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7101 shader_info->num_input_vgprs += 1;
7102 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7103 shader_info->num_input_vgprs += 1;
7104 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7105 shader_info->num_input_vgprs += 1;
7106 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7107 shader_info->num_input_vgprs += 1;
7108 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7109 shader_info->num_input_vgprs += 1;
7110 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7111 shader_info->num_input_vgprs += 1;
7112 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7113 shader_info->num_input_vgprs += 1;
7114 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7115 shader_info->num_input_vgprs += 1;
7116 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7117 shader_info->num_input_vgprs += 1;
7118 }
7119 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7120
7121 /* +3 for scratch wave offset and VCC */
7122 config->num_sgprs = MAX2(config->num_sgprs,
7123 shader_info->num_input_sgprs + 3);
7124
7125 /* Enable 64-bit and 16-bit denormals, because there is no performance
7126 * cost.
7127 *
7128 * If denormals are enabled, all floating-point output modifiers are
7129 * ignored.
7130 *
7131 * Don't enable denormals for 32-bit floats, because:
7132 * - Floating-point output modifiers would be ignored by the hw.
7133 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7134 * have to stop using those.
7135 * - SI & CI would be very slow.
7136 */
7137 config->float_mode |= V_00B028_FP_64_DENORMS;
7138 }
7139
7140 static void
7141 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7142 {
7143 switch (nir->info.stage) {
7144 case MESA_SHADER_COMPUTE:
7145 for (int i = 0; i < 3; ++i)
7146 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7147 break;
7148 case MESA_SHADER_FRAGMENT:
7149 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7150 break;
7151 case MESA_SHADER_GEOMETRY:
7152 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7153 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7154 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7155 shader_info->gs.invocations = nir->info.gs.invocations;
7156 break;
7157 case MESA_SHADER_TESS_EVAL:
7158 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7159 shader_info->tes.spacing = nir->info.tess.spacing;
7160 shader_info->tes.ccw = nir->info.tess.ccw;
7161 shader_info->tes.point_mode = nir->info.tess.point_mode;
7162 shader_info->tes.as_es = options->key.tes.as_es;
7163 break;
7164 case MESA_SHADER_TESS_CTRL:
7165 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7166 break;
7167 case MESA_SHADER_VERTEX:
7168 shader_info->vs.as_es = options->key.vs.as_es;
7169 shader_info->vs.as_ls = options->key.vs.as_ls;
7170 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7171 if (options->key.vs.as_ls)
7172 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7173 break;
7174 default:
7175 break;
7176 }
7177 }
7178
7179 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7180 struct ac_shader_binary *binary,
7181 struct ac_shader_config *config,
7182 struct ac_shader_variant_info *shader_info,
7183 struct nir_shader *const *nir,
7184 int nir_count,
7185 const struct ac_nir_compiler_options *options,
7186 bool dump_shader)
7187 {
7188
7189 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7190 options);
7191
7192 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7193 for (int i = 0; i < nir_count; ++i)
7194 ac_fill_shader_info(shader_info, nir[i], options);
7195
7196 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7197 if (options->chip_class == GFX9) {
7198 if (nir_count == 2 &&
7199 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7200 shader_info->gs.es_type = nir[0]->info.stage;
7201 }
7202 }
7203 }
7204
7205 static void
7206 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
7207 {
7208 LLVMValueRef vtx_offset =
7209 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
7210 LLVMConstInt(ctx->ac.i32, 4, false), "");
7211 int idx = 0;
7212
7213 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
7214 int length = 4;
7215 int slot = idx;
7216 int slot_inc = 1;
7217 if (!(ctx->output_mask & (1ull << i)))
7218 continue;
7219
7220 if (i == VARYING_SLOT_CLIP_DIST0) {
7221 /* unpack clip and cull from a single set of slots */
7222 length = ctx->num_output_clips + ctx->num_output_culls;
7223 if (length > 4)
7224 slot_inc = 2;
7225 }
7226
7227 for (unsigned j = 0; j < length; j++) {
7228 LLVMValueRef value, soffset;
7229
7230 soffset = LLVMConstInt(ctx->ac.i32,
7231 (slot * 4 + j) *
7232 ctx->gs_max_out_vertices * 16 * 4, false);
7233
7234 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7235 1, ctx->ac.i32_0,
7236 vtx_offset, soffset,
7237 0, 1, 1, true, false);
7238
7239 LLVMBuildStore(ctx->ac.builder,
7240 ac_to_float(&ctx->ac, value), ctx->abi.outputs[radeon_llvm_reg_index_soa(i, j)]);
7241 }
7242 idx += slot_inc;
7243 }
7244 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7245 }
7246
7247 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7248 struct nir_shader *geom_shader,
7249 struct ac_shader_binary *binary,
7250 struct ac_shader_config *config,
7251 struct ac_shader_variant_info *shader_info,
7252 const struct ac_nir_compiler_options *options,
7253 bool dump_shader)
7254 {
7255 struct radv_shader_context ctx = {0};
7256 ctx.context = LLVMContextCreate();
7257 ctx.options = options;
7258 ctx.shader_info = shader_info;
7259
7260 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7261 options->family);
7262 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7263
7264 ctx.is_gs_copy_shader = true;
7265 LLVMSetTarget(ctx.ac.module, "amdgcn--");
7266
7267 enum ac_float_mode float_mode =
7268 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7269 AC_FLOAT_MODE_DEFAULT;
7270
7271 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
7272 ctx.stage = MESA_SHADER_VERTEX;
7273
7274 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7275
7276 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7277 ac_setup_rings(&ctx);
7278
7279 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7280 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7281
7282 struct ac_nir_context nir_ctx = {};
7283 nir_ctx.ac = ctx.ac;
7284 nir_ctx.abi = &ctx.abi;
7285
7286 nir_foreach_variable(variable, &geom_shader->outputs) {
7287 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7288 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7289 }
7290
7291 ac_gs_copy_shader_emit(&ctx);
7292
7293 LLVMBuildRetVoid(ctx.ac.builder);
7294
7295 ac_llvm_finalize_module(&ctx);
7296
7297 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
7298 MESA_SHADER_VERTEX,
7299 dump_shader, options->supports_spill);
7300 }