projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: handle 10-bit format clamping workaround.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 };
43
44 #define CONST_ADDR_SPACE 2
45 #define LOCAL_ADDR_SPACE 3
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct nir_to_llvm_context;
51
52 struct ac_nir_context {
53 struct ac_llvm_context ac;
54 struct ac_shader_abi *abi;
55
56 gl_shader_stage stage;
57
58 struct hash_table *defs;
59 struct hash_table *phis;
60 struct hash_table *vars;
61
62 LLVMValueRef main_function;
63 LLVMBasicBlockRef continue_block;
64 LLVMBasicBlockRef break_block;
65
66 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
67
68 int num_locals;
69 LLVMValueRef *locals;
70
71 LLVMValueRef ddxy_lds;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef num_work_groups;
96 LLVMValueRef workgroup_ids;
97 LLVMValueRef local_invocation_ids;
98 LLVMValueRef tg_size;
99
100 LLVMValueRef vertex_buffers;
101 LLVMValueRef rel_auto_id;
102 LLVMValueRef vs_prim_id;
103 LLVMValueRef ls_out_layout;
104 LLVMValueRef es2gs_offset;
105
106 LLVMValueRef tcs_offchip_layout;
107 LLVMValueRef tcs_out_offsets;
108 LLVMValueRef tcs_out_layout;
109 LLVMValueRef tcs_in_layout;
110 LLVMValueRef oc_lds;
111 LLVMValueRef tess_factor_offset;
112 LLVMValueRef tcs_patch_id;
113 LLVMValueRef tcs_rel_ids;
114 LLVMValueRef tes_rel_patch_id;
115 LLVMValueRef tes_patch_id;
116 LLVMValueRef tes_u;
117 LLVMValueRef tes_v;
118
119 LLVMValueRef gsvs_ring_stride;
120 LLVMValueRef gsvs_num_entries;
121 LLVMValueRef gs2vs_offset;
122 LLVMValueRef gs_wave_id;
123 LLVMValueRef gs_vtx_offset[6];
124 LLVMValueRef gs_prim_id, gs_invocation_id;
125
126 LLVMValueRef esgs_ring;
127 LLVMValueRef gsvs_ring;
128 LLVMValueRef hs_ring_tess_offchip;
129 LLVMValueRef hs_ring_tess_factor;
130
131 LLVMValueRef prim_mask;
132 LLVMValueRef sample_pos_offset;
133 LLVMValueRef persp_sample, persp_center, persp_centroid;
134 LLVMValueRef linear_sample, linear_center, linear_centroid;
135
136 LLVMTypeRef i1;
137 LLVMTypeRef i8;
138 LLVMTypeRef i16;
139 LLVMTypeRef i32;
140 LLVMTypeRef i64;
141 LLVMTypeRef v2i32;
142 LLVMTypeRef v3i32;
143 LLVMTypeRef v4i32;
144 LLVMTypeRef v8i32;
145 LLVMTypeRef f64;
146 LLVMTypeRef f32;
147 LLVMTypeRef f16;
148 LLVMTypeRef v2f32;
149 LLVMTypeRef v4f32;
150 LLVMTypeRef voidt;
151
152 LLVMValueRef i1true;
153 LLVMValueRef i1false;
154 LLVMValueRef i32zero;
155 LLVMValueRef i32one;
156 LLVMValueRef f32zero;
157 LLVMValueRef f32one;
158 LLVMValueRef v4f32empty;
159
160 unsigned uniform_md_kind;
161 LLVMValueRef empty_md;
162 gl_shader_stage stage;
163
164 LLVMValueRef lds;
165 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
166
167 uint64_t input_mask;
168 uint64_t output_mask;
169 uint8_t num_output_clips;
170 uint8_t num_output_culls;
171
172 bool is_gs_copy_shader;
173 LLVMValueRef gs_next_vertex;
174 unsigned gs_max_out_vertices;
175
176 unsigned tes_primitive_mode;
177 uint64_t tess_outputs_written;
178 uint64_t tess_patch_outputs_written;
179 };
180
181 static inline struct nir_to_llvm_context *
182 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
183 {
184 struct nir_to_llvm_context *ctx = NULL;
185 return container_of(abi, ctx, abi);
186 }
187
188 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
189 const nir_deref_var *deref,
190 enum ac_descriptor_type desc_type,
191 bool image, bool write);
192
193 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
194 {
195 return (index * 4) + chan;
196 }
197
198 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
199 {
200 /* handle patch indices separate */
201 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
202 return 0;
203 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
204 return 1;
205 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
206 return 2 + (slot - VARYING_SLOT_PATCH0);
207
208 if (slot == VARYING_SLOT_POS)
209 return 0;
210 if (slot == VARYING_SLOT_PSIZ)
211 return 1;
212 if (slot == VARYING_SLOT_CLIP_DIST0)
213 return 2;
214 /* 3 is reserved for clip dist as well */
215 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
216 return 4 + (slot - VARYING_SLOT_VAR0);
217 unreachable("illegal slot in get unique index\n");
218 }
219
220 static unsigned llvm_get_type_size(LLVMTypeRef type)
221 {
222 LLVMTypeKind kind = LLVMGetTypeKind(type);
223
224 switch (kind) {
225 case LLVMIntegerTypeKind:
226 return LLVMGetIntTypeWidth(type) / 8;
227 case LLVMFloatTypeKind:
228 return 4;
229 case LLVMPointerTypeKind:
230 return 8;
231 case LLVMVectorTypeKind:
232 return LLVMGetVectorSize(type) *
233 llvm_get_type_size(LLVMGetElementType(type));
234 default:
235 assert(0);
236 return 0;
237 }
238 }
239
240 static void set_llvm_calling_convention(LLVMValueRef func,
241 gl_shader_stage stage)
242 {
243 enum radeon_llvm_calling_convention calling_conv;
244
245 switch (stage) {
246 case MESA_SHADER_VERTEX:
247 case MESA_SHADER_TESS_CTRL:
248 case MESA_SHADER_TESS_EVAL:
249 calling_conv = RADEON_LLVM_AMDGPU_VS;
250 break;
251 case MESA_SHADER_GEOMETRY:
252 calling_conv = RADEON_LLVM_AMDGPU_GS;
253 break;
254 case MESA_SHADER_FRAGMENT:
255 calling_conv = RADEON_LLVM_AMDGPU_PS;
256 break;
257 case MESA_SHADER_COMPUTE:
258 calling_conv = RADEON_LLVM_AMDGPU_CS;
259 break;
260 default:
261 unreachable("Unhandle shader type");
262 }
263
264 LLVMSetFunctionCallConv(func, calling_conv);
265 }
266
267 #define MAX_ARGS 23
268 struct arg_info {
269 LLVMTypeRef types[MAX_ARGS];
270 LLVMValueRef *assign[MAX_ARGS];
271 unsigned array_params_mask;
272 uint8_t count;
273 uint8_t user_sgpr_count;
274 uint8_t sgpr_count;
275 uint8_t num_user_sgprs_used;
276 uint8_t num_sgprs_used;
277 uint8_t num_vgprs_used;
278 };
279
280 static inline void
281 add_argument(struct arg_info *info,
282 LLVMTypeRef type, LLVMValueRef *param_ptr)
283 {
284 assert(info->count < MAX_ARGS);
285 info->assign[info->count] = param_ptr;
286 info->types[info->count] = type;
287 info->count++;
288 }
289
290 static inline void
291 add_sgpr_argument(struct arg_info *info,
292 LLVMTypeRef type, LLVMValueRef *param_ptr)
293 {
294 add_argument(info, type, param_ptr);
295 info->num_sgprs_used += llvm_get_type_size(type) / 4;
296 info->sgpr_count++;
297 }
298
299 static inline void
300 add_user_sgpr_argument(struct arg_info *info,
301 LLVMTypeRef type,
302 LLVMValueRef *param_ptr)
303 {
304 add_sgpr_argument(info, type, param_ptr);
305 info->num_user_sgprs_used += llvm_get_type_size(type) / 4;
306 info->user_sgpr_count++;
307 }
308
309 static inline void
310 add_vgpr_argument(struct arg_info *info,
311 LLVMTypeRef type,
312 LLVMValueRef *param_ptr)
313 {
314 add_argument(info, type, param_ptr);
315 info->num_vgprs_used += llvm_get_type_size(type) / 4;
316 }
317
318 static inline void
319 add_user_sgpr_array_argument(struct arg_info *info,
320 LLVMTypeRef type,
321 LLVMValueRef *param_ptr)
322 {
323 info->array_params_mask |= (1 << info->count);
324 add_user_sgpr_argument(info, type, param_ptr);
325 }
326
327 static void assign_arguments(LLVMValueRef main_function,
328 struct arg_info *info)
329 {
330 unsigned i;
331 for (i = 0; i < info->count; i++) {
332 if (info->assign[i])
333 *info->assign[i] = LLVMGetParam(main_function, i);
334 }
335 }
336
337 static LLVMValueRef
338 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
339 LLVMBuilderRef builder, LLVMTypeRef *return_types,
340 unsigned num_return_elems,
341 struct arg_info *args,
342 unsigned max_workgroup_size,
343 bool unsafe_math)
344 {
345 LLVMTypeRef main_function_type, ret_type;
346 LLVMBasicBlockRef main_function_body;
347
348 if (num_return_elems)
349 ret_type = LLVMStructTypeInContext(ctx, return_types,
350 num_return_elems, true);
351 else
352 ret_type = LLVMVoidTypeInContext(ctx);
353
354 /* Setup the function */
355 main_function_type =
356 LLVMFunctionType(ret_type, args->types, args->count, 0);
357 LLVMValueRef main_function =
358 LLVMAddFunction(module, "main", main_function_type);
359 main_function_body =
360 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
361 LLVMPositionBuilderAtEnd(builder, main_function_body);
362
363 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
364 for (unsigned i = 0; i < args->sgpr_count; ++i) {
365 if (args->array_params_mask & (1 << i)) {
366 LLVMValueRef P = LLVMGetParam(main_function, i);
367 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
368 ac_add_attr_dereferenceable(P, UINT64_MAX);
369 }
370 else {
371 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
372 }
373 }
374
375 if (max_workgroup_size) {
376 ac_llvm_add_target_dep_function_attr(main_function,
377 "amdgpu-max-work-group-size",
378 max_workgroup_size);
379 }
380 if (unsafe_math) {
381 /* These were copied from some LLVM test. */
382 LLVMAddTargetDependentFunctionAttr(main_function,
383 "less-precise-fpmad",
384 "true");
385 LLVMAddTargetDependentFunctionAttr(main_function,
386 "no-infs-fp-math",
387 "true");
388 LLVMAddTargetDependentFunctionAttr(main_function,
389 "no-nans-fp-math",
390 "true");
391 LLVMAddTargetDependentFunctionAttr(main_function,
392 "unsafe-fp-math",
393 "true");
394 }
395 return main_function;
396 }
397
398 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
399 {
400 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
401 CONST_ADDR_SPACE);
402 }
403
404 static LLVMTypeRef to_integer_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
405 {
406 if (t == ctx->f16 || t == ctx->i16)
407 return ctx->i16;
408 else if (t == ctx->f32 || t == ctx->i32)
409 return ctx->i32;
410 else if (t == ctx->f64 || t == ctx->i64)
411 return ctx->i64;
412 else
413 unreachable("Unhandled integer size");
414 }
415
416 static LLVMTypeRef to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
417 {
418 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
419 LLVMTypeRef elem_type = LLVMGetElementType(t);
420 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
421 LLVMGetVectorSize(t));
422 }
423 return to_integer_type_scalar(ctx, t);
424 }
425
426 static LLVMValueRef to_integer(struct ac_llvm_context *ctx, LLVMValueRef v)
427 {
428 LLVMTypeRef type = LLVMTypeOf(v);
429 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
430 }
431
432 static LLVMTypeRef to_float_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
433 {
434 if (t == ctx->i16 || t == ctx->f16)
435 return ctx->f16;
436 else if (t == ctx->i32 || t == ctx->f32)
437 return ctx->f32;
438 else if (t == ctx->i64 || t == ctx->f64)
439 return ctx->f64;
440 else
441 unreachable("Unhandled float size");
442 }
443
444 static LLVMTypeRef to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
445 {
446 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
447 LLVMTypeRef elem_type = LLVMGetElementType(t);
448 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
449 LLVMGetVectorSize(t));
450 }
451 return to_float_type_scalar(ctx, t);
452 }
453
454 static LLVMValueRef to_float(struct ac_llvm_context *ctx, LLVMValueRef v)
455 {
456 LLVMTypeRef type = LLVMTypeOf(v);
457 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
458 }
459
460 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
461 {
462 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
463 type = LLVMGetElementType(type);
464
465 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
466 return LLVMGetIntTypeWidth(type);
467
468 if (type == ctx->f16)
469 return 16;
470 if (type == ctx->f32)
471 return 32;
472 if (type == ctx->f64)
473 return 64;
474
475 unreachable("Unhandled type kind in get_elem_bits");
476 }
477
478 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
479 LLVMValueRef param, unsigned rshift,
480 unsigned bitwidth)
481 {
482 LLVMValueRef value = param;
483 if (rshift)
484 value = LLVMBuildLShr(ctx->builder, value,
485 LLVMConstInt(ctx->i32, rshift, false), "");
486
487 if (rshift + bitwidth < 32) {
488 unsigned mask = (1 << bitwidth) - 1;
489 value = LLVMBuildAnd(ctx->builder, value,
490 LLVMConstInt(ctx->i32, mask, false), "");
491 }
492 return value;
493 }
494
495 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
496 {
497 switch (ctx->stage) {
498 case MESA_SHADER_TESS_CTRL:
499 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
500 case MESA_SHADER_TESS_EVAL:
501 return ctx->tes_rel_patch_id;
502 break;
503 default:
504 unreachable("Illegal stage");
505 }
506 }
507
508 /* Tessellation shaders pass outputs to the next shader using LDS.
509 *
510 * LS outputs = TCS inputs
511 * TCS outputs = TES inputs
512 *
513 * The LDS layout is:
514 * - TCS inputs for patch 0
515 * - TCS inputs for patch 1
516 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
517 * - ...
518 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
519 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
520 * - TCS outputs for patch 1
521 * - Per-patch TCS outputs for patch 1
522 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
523 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
524 * - ...
525 *
526 * All three shaders VS(LS), TCS, TES share the same LDS space.
527 */
528 static LLVMValueRef
529 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
530 {
531 if (ctx->stage == MESA_SHADER_VERTEX)
532 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
533 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
534 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
535 else {
536 assert(0);
537 return NULL;
538 }
539 }
540
541 static LLVMValueRef
542 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
543 {
544 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
545 }
546
547 static LLVMValueRef
548 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
549 {
550 return LLVMBuildMul(ctx->builder,
551 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
552 LLVMConstInt(ctx->i32, 4, false), "");
553 }
554
555 static LLVMValueRef
556 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
557 {
558 return LLVMBuildMul(ctx->builder,
559 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
560 LLVMConstInt(ctx->i32, 4, false), "");
561 }
562
563 static LLVMValueRef
564 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
565 {
566 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
567 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
568
569 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
570 }
571
572 static LLVMValueRef
573 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
574 {
575 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
576 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
577 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
578
579 return LLVMBuildAdd(ctx->builder, patch0_offset,
580 LLVMBuildMul(ctx->builder, patch_stride,
581 rel_patch_id, ""),
582 "");
583 }
584
585 static LLVMValueRef
586 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
587 {
588 LLVMValueRef patch0_patch_data_offset =
589 get_tcs_out_patch0_patch_data_offset(ctx);
590 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
591 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
592
593 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
594 LLVMBuildMul(ctx->builder, patch_stride,
595 rel_patch_id, ""),
596 "");
597 }
598
599 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
600 {
601 ud_info->sgpr_idx = *sgpr_idx;
602 ud_info->num_sgprs = num_sgprs;
603 ud_info->indirect = false;
604 ud_info->indirect_offset = 0;
605 *sgpr_idx += num_sgprs;
606 }
607
608 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
609 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
610 {
611 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
612 }
613
614
615 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
616 uint32_t indirect_offset)
617 {
618 ud_info->sgpr_idx = sgpr_idx;
619 ud_info->num_sgprs = num_sgprs;
620 ud_info->indirect = true;
621 ud_info->indirect_offset = indirect_offset;
622 }
623
624 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
625 {
626 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
627 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
628 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
629 "tess_lds");
630 }
631
632 struct user_sgpr_info {
633 bool need_ring_offsets;
634 uint8_t sgpr_count;
635 bool indirect_all_descriptor_sets;
636 };
637
638 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
639 struct user_sgpr_info *user_sgpr_info)
640 {
641 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
642
643 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
644 if (ctx->stage == MESA_SHADER_GEOMETRY ||
645 ctx->stage == MESA_SHADER_VERTEX ||
646 ctx->stage == MESA_SHADER_TESS_CTRL ||
647 ctx->stage == MESA_SHADER_TESS_EVAL ||
648 ctx->is_gs_copy_shader)
649 user_sgpr_info->need_ring_offsets = true;
650
651 if (ctx->stage == MESA_SHADER_FRAGMENT &&
652 ctx->shader_info->info.ps.needs_sample_positions)
653 user_sgpr_info->need_ring_offsets = true;
654
655 /* 2 user sgprs will nearly always be allocated for scratch/rings */
656 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
657 user_sgpr_info->sgpr_count += 2;
658 }
659
660 switch (ctx->stage) {
661 case MESA_SHADER_COMPUTE:
662 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
663 break;
664 case MESA_SHADER_FRAGMENT:
665 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
666 break;
667 case MESA_SHADER_VERTEX:
668 if (!ctx->is_gs_copy_shader) {
669 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
670 if (ctx->shader_info->info.vs.needs_draw_id) {
671 user_sgpr_info->sgpr_count += 3;
672 } else {
673 user_sgpr_info->sgpr_count += 2;
674 }
675 }
676 if (ctx->options->key.vs.as_ls)
677 user_sgpr_info->sgpr_count++;
678 break;
679 case MESA_SHADER_TESS_CTRL:
680 user_sgpr_info->sgpr_count += 4;
681 break;
682 case MESA_SHADER_TESS_EVAL:
683 user_sgpr_info->sgpr_count += 1;
684 break;
685 case MESA_SHADER_GEOMETRY:
686 user_sgpr_info->sgpr_count += 2;
687 break;
688 default:
689 break;
690 }
691
692 if (ctx->shader_info->info.needs_push_constants)
693 user_sgpr_info->sgpr_count += 2;
694
695 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
696 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
697 user_sgpr_info->sgpr_count += 2;
698 user_sgpr_info->indirect_all_descriptor_sets = true;
699 } else {
700 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
701 }
702 }
703
704 static void create_function(struct nir_to_llvm_context *ctx)
705 {
706 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
707 uint8_t user_sgpr_idx;
708 struct user_sgpr_info user_sgpr_info;
709 struct arg_info args = {};
710 LLVMValueRef desc_sets;
711
712 allocate_user_sgprs(ctx, &user_sgpr_info);
713 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
714 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
715 }
716
717 /* 1 for each descriptor set */
718 if (!user_sgpr_info.indirect_all_descriptor_sets) {
719 for (unsigned i = 0; i < num_sets; ++i) {
720 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
721 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
722 }
723 }
724 } else
725 add_user_sgpr_array_argument(&args, const_array(const_array(ctx->i8, 1024 * 1024), 32), &desc_sets);
726
727 if (ctx->shader_info->info.needs_push_constants) {
728 /* 1 for push constants and dynamic descriptors */
729 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
730 }
731
732 switch (ctx->stage) {
733 case MESA_SHADER_COMPUTE:
734 if (ctx->shader_info->info.cs.grid_components_used)
735 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
736 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
737 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
738 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
739 break;
740 case MESA_SHADER_VERTEX:
741 if (!ctx->is_gs_copy_shader) {
742 if (ctx->shader_info->info.vs.has_vertex_buffers)
743 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
744 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.base_vertex); // base vertex
745 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.start_instance);// start instance
746 if (ctx->shader_info->info.vs.needs_draw_id)
747 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.draw_id); // draw id
748 }
749 if (ctx->options->key.vs.as_es)
750 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
751 else if (ctx->options->key.vs.as_ls)
752 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
753 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
754 if (!ctx->is_gs_copy_shader) {
755 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
756 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
757 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
758 }
759 break;
760 case MESA_SHADER_TESS_CTRL:
761 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
762 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
763 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
764 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
765 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
766 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
767 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
768 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
769 break;
770 case MESA_SHADER_TESS_EVAL:
771 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
772 if (ctx->options->key.tes.as_es) {
773 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
774 add_sgpr_argument(&args, ctx->i32, NULL); //
775 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
776 } else {
777 add_sgpr_argument(&args, ctx->i32, NULL); //
778 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
779 }
780 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
781 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
782 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
783 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
784 break;
785 case MESA_SHADER_GEOMETRY:
786 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
787 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
788 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
789 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
790 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
791 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
792 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
793 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
794 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
795 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
796 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
797 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
798 break;
799 case MESA_SHADER_FRAGMENT:
800 if (ctx->shader_info->info.ps.needs_sample_positions)
801 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
802 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
803 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
804 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
805 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
806 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
807 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
808 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
809 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
810 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
811 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[0]); /* pos x float */
812 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[1]); /* pos y float */
813 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[2]); /* pos z float */
814 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[3]); /* pos w float */
815 add_vgpr_argument(&args, ctx->i32, &ctx->abi.front_face); /* front face */
816 add_vgpr_argument(&args, ctx->i32, &ctx->abi.ancillary); /* ancillary */
817 add_vgpr_argument(&args, ctx->i32, &ctx->abi.sample_coverage); /* sample coverage */
818 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
819 break;
820 default:
821 unreachable("Shader stage not implemented");
822 }
823
824 ctx->main_function = create_llvm_function(
825 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
826 ctx->max_workgroup_size,
827 ctx->options->unsafe_math);
828 set_llvm_calling_convention(ctx->main_function, ctx->stage);
829
830
831 ctx->shader_info->num_input_vgprs = 0;
832 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs =
833 ctx->options->supports_spill ? 2 : 0;
834
835 ctx->shader_info->num_user_sgprs += args.num_user_sgprs_used;
836 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
837
838 if (ctx->stage != MESA_SHADER_FRAGMENT)
839 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
840
841 assign_arguments(ctx->main_function, &args);
842
843 user_sgpr_idx = 0;
844
845 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
846 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
847 if (ctx->options->supports_spill) {
848 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
849 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
850 NULL, 0, AC_FUNC_ATTR_READNONE);
851 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
852 const_array(ctx->v4i32, 16), "");
853 }
854 }
855
856 if (!user_sgpr_info.indirect_all_descriptor_sets) {
857 for (unsigned i = 0; i < num_sets; ++i) {
858 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
859 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
860 } else
861 ctx->descriptor_sets[i] = NULL;
862 }
863 } else {
864 uint32_t desc_sgpr_idx = user_sgpr_idx;
865 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
866
867 for (unsigned i = 0; i < num_sets; ++i) {
868 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
869 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
870 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
871
872 } else
873 ctx->descriptor_sets[i] = NULL;
874 }
875 ctx->shader_info->need_indirect_descriptor_sets = true;
876 }
877
878 if (ctx->shader_info->info.needs_push_constants) {
879 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
880 }
881
882 switch (ctx->stage) {
883 case MESA_SHADER_COMPUTE:
884 if (ctx->shader_info->info.cs.grid_components_used) {
885 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
886 }
887 break;
888 case MESA_SHADER_VERTEX:
889 if (!ctx->is_gs_copy_shader) {
890 if (ctx->shader_info->info.vs.has_vertex_buffers) {
891 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
892 }
893 unsigned vs_num = 2;
894 if (ctx->shader_info->info.vs.needs_draw_id)
895 vs_num++;
896
897 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
898 }
899 if (ctx->options->key.vs.as_ls) {
900 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
901 }
902 if (ctx->options->key.vs.as_ls)
903 declare_tess_lds(ctx);
904 break;
905 case MESA_SHADER_TESS_CTRL:
906 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
907 declare_tess_lds(ctx);
908 break;
909 case MESA_SHADER_TESS_EVAL:
910 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
911 break;
912 case MESA_SHADER_GEOMETRY:
913 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
914 break;
915 case MESA_SHADER_FRAGMENT:
916 if (ctx->shader_info->info.ps.needs_sample_positions) {
917 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
918 }
919 break;
920 default:
921 unreachable("Shader stage not implemented");
922 }
923 }
924
925 static void setup_types(struct nir_to_llvm_context *ctx)
926 {
927 LLVMValueRef args[4];
928
929 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
930 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
931 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
932 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
933 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
934 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
935 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
936 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
937 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
938 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
939 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
940 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
941 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
942 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
943 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
944
945 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
946 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
947 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
948 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
949 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
950 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
951
952 args[0] = ctx->f32zero;
953 args[1] = ctx->f32zero;
954 args[2] = ctx->f32zero;
955 args[3] = ctx->f32one;
956 ctx->v4f32empty = LLVMConstVector(args, 4);
957
958 ctx->uniform_md_kind =
959 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
960 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
961
962 args[0] = LLVMConstReal(ctx->f32, 2.5);
963 }
964
965 static int get_llvm_num_components(LLVMValueRef value)
966 {
967 LLVMTypeRef type = LLVMTypeOf(value);
968 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
969 ? LLVMGetVectorSize(type)
970 : 1;
971 return num_components;
972 }
973
974 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
975 LLVMValueRef value,
976 int index)
977 {
978 int count = get_llvm_num_components(value);
979
980 assert(index < count);
981 if (count == 1)
982 return value;
983
984 return LLVMBuildExtractElement(ac->builder, value,
985 LLVMConstInt(ac->i32, index, false), "");
986 }
987
988 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
989 LLVMValueRef value, unsigned count)
990 {
991 unsigned num_components = get_llvm_num_components(value);
992 if (count == num_components)
993 return value;
994
995 LLVMValueRef masks[] = {
996 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
997 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
998
999 if (count == 1)
1000 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1001 "");
1002
1003 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1004 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1005 }
1006
1007 static void
1008 build_store_values_extended(struct ac_llvm_context *ac,
1009 LLVMValueRef *values,
1010 unsigned value_count,
1011 unsigned value_stride,
1012 LLVMValueRef vec)
1013 {
1014 LLVMBuilderRef builder = ac->builder;
1015 unsigned i;
1016
1017 for (i = 0; i < value_count; i++) {
1018 LLVMValueRef ptr = values[i * value_stride];
1019 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1020 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1021 LLVMBuildStore(builder, value, ptr);
1022 }
1023 }
1024
1025 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1026 const nir_ssa_def *def)
1027 {
1028 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1029 if (def->num_components > 1) {
1030 type = LLVMVectorType(type, def->num_components);
1031 }
1032 return type;
1033 }
1034
1035 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1036 {
1037 assert(src.is_ssa);
1038 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1039 return (LLVMValueRef)entry->data;
1040 }
1041
1042
1043 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1044 const struct nir_block *b)
1045 {
1046 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1047 return (LLVMBasicBlockRef)entry->data;
1048 }
1049
1050 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1051 nir_alu_src src,
1052 unsigned num_components)
1053 {
1054 LLVMValueRef value = get_src(ctx, src.src);
1055 bool need_swizzle = false;
1056
1057 assert(value);
1058 LLVMTypeRef type = LLVMTypeOf(value);
1059 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1060 ? LLVMGetVectorSize(type)
1061 : 1;
1062
1063 for (unsigned i = 0; i < num_components; ++i) {
1064 assert(src.swizzle[i] < src_components);
1065 if (src.swizzle[i] != i)
1066 need_swizzle = true;
1067 }
1068
1069 if (need_swizzle || num_components != src_components) {
1070 LLVMValueRef masks[] = {
1071 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1072 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1073 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1074 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1075
1076 if (src_components > 1 && num_components == 1) {
1077 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1078 masks[0], "");
1079 } else if (src_components == 1 && num_components > 1) {
1080 LLVMValueRef values[] = {value, value, value, value};
1081 value = ac_build_gather_values(&ctx->ac, values, num_components);
1082 } else {
1083 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1084 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1085 swizzle, "");
1086 }
1087 }
1088 assert(!src.negate);
1089 assert(!src.abs);
1090 return value;
1091 }
1092
1093 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1094 LLVMIntPredicate pred, LLVMValueRef src0,
1095 LLVMValueRef src1)
1096 {
1097 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1098 return LLVMBuildSelect(ctx->builder, result,
1099 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1100 LLVMConstInt(ctx->i32, 0, false), "");
1101 }
1102
1103 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1104 LLVMRealPredicate pred, LLVMValueRef src0,
1105 LLVMValueRef src1)
1106 {
1107 LLVMValueRef result;
1108 src0 = to_float(ctx, src0);
1109 src1 = to_float(ctx, src1);
1110 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1111 return LLVMBuildSelect(ctx->builder, result,
1112 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1113 LLVMConstInt(ctx->i32, 0, false), "");
1114 }
1115
1116 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1117 const char *intrin,
1118 LLVMTypeRef result_type,
1119 LLVMValueRef src0)
1120 {
1121 char name[64];
1122 LLVMValueRef params[] = {
1123 to_float(ctx, src0),
1124 };
1125
1126 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1127 get_elem_bits(ctx, result_type));
1128 assert(length < sizeof(name));
1129 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1130 }
1131
1132 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1133 const char *intrin,
1134 LLVMTypeRef result_type,
1135 LLVMValueRef src0, LLVMValueRef src1)
1136 {
1137 char name[64];
1138 LLVMValueRef params[] = {
1139 to_float(ctx, src0),
1140 to_float(ctx, src1),
1141 };
1142
1143 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1144 get_elem_bits(ctx, result_type));
1145 assert(length < sizeof(name));
1146 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1147 }
1148
1149 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1150 const char *intrin,
1151 LLVMTypeRef result_type,
1152 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1153 {
1154 char name[64];
1155 LLVMValueRef params[] = {
1156 to_float(ctx, src0),
1157 to_float(ctx, src1),
1158 to_float(ctx, src2),
1159 };
1160
1161 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1162 get_elem_bits(ctx, result_type));
1163 assert(length < sizeof(name));
1164 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1165 }
1166
1167 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1168 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1169 {
1170 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1171 ctx->i32_0, "");
1172 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1173 }
1174
1175 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1176 LLVMValueRef src0)
1177 {
1178 LLVMValueRef params[2] = {
1179 src0,
1180
1181 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1182 * add special code to check for x=0. The reason is that
1183 * the LLVM behavior for x=0 is different from what we
1184 * need here.
1185 *
1186 * The hardware already implements the correct behavior.
1187 */
1188 LLVMConstInt(ctx->i1, 1, false),
1189 };
1190 return ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1191 }
1192
1193 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1194 LLVMValueRef src0)
1195 {
1196 return ac_build_imsb(ctx, src0, ctx->i32);
1197 }
1198
1199 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1200 LLVMValueRef src0)
1201 {
1202 return ac_build_umsb(ctx, src0, ctx->i32);
1203 }
1204
1205 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1206 LLVMIntPredicate pred,
1207 LLVMValueRef src0, LLVMValueRef src1)
1208 {
1209 return LLVMBuildSelect(ctx->builder,
1210 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1211 src0,
1212 src1, "");
1213
1214 }
1215 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1216 LLVMValueRef src0)
1217 {
1218 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1219 LLVMBuildNeg(ctx->builder, src0, ""));
1220 }
1221
1222 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1223 LLVMValueRef src0)
1224 {
1225 LLVMValueRef cmp, val;
1226
1227 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1228 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1229 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1230 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1231 return val;
1232 }
1233
1234 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1235 LLVMValueRef src0)
1236 {
1237 LLVMValueRef cmp, val;
1238
1239 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1240 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1241 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1242 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1243 return val;
1244 }
1245
1246 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1247 LLVMValueRef src0)
1248 {
1249 const char *intr = "llvm.floor.f32";
1250 LLVMValueRef fsrc0 = to_float(ctx, src0);
1251 LLVMValueRef params[] = {
1252 fsrc0,
1253 };
1254 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1255 ctx->f32, params, 1,
1256 AC_FUNC_ATTR_READNONE);
1257 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1258 }
1259
1260 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1261 const char *intrin,
1262 LLVMValueRef src0, LLVMValueRef src1)
1263 {
1264 LLVMTypeRef ret_type;
1265 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1266 LLVMValueRef res;
1267 LLVMValueRef params[] = { src0, src1 };
1268 ret_type = LLVMStructTypeInContext(ctx->context, types,
1269 2, true);
1270
1271 res = ac_build_intrinsic(ctx, intrin, ret_type,
1272 params, 2, AC_FUNC_ATTR_READNONE);
1273
1274 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1275 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1276 return res;
1277 }
1278
1279 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1280 LLVMValueRef src0)
1281 {
1282 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1283 }
1284
1285 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1286 LLVMValueRef src0)
1287 {
1288 src0 = to_float(ctx, src0);
1289 return LLVMBuildSExt(ctx->builder,
1290 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1291 ctx->i32, "");
1292 }
1293
1294 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1295 LLVMValueRef src0)
1296 {
1297 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1298 }
1299
1300 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1301 LLVMValueRef src0)
1302 {
1303 return LLVMBuildSExt(ctx->builder,
1304 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1305 ctx->i32, "");
1306 }
1307
1308 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1309 LLVMValueRef src0)
1310 {
1311 LLVMValueRef result;
1312 LLVMValueRef cond;
1313
1314 src0 = to_float(&ctx->ac, src0);
1315 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1316
1317 /* TODO SI/CIK options here */
1318 if (ctx->options->chip_class >= VI) {
1319 LLVMValueRef args[2];
1320 /* Check if the result is a denormal - and flush to 0 if so. */
1321 args[0] = result;
1322 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1323 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1324 }
1325
1326 /* need to convert back up to f32 */
1327 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1328
1329 if (ctx->options->chip_class >= VI)
1330 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1331
1332 return result;
1333 }
1334
1335 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1336 LLVMValueRef src0, LLVMValueRef src1)
1337 {
1338 LLVMValueRef dst64, result;
1339 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1340 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1341
1342 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1343 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1344 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1345 return result;
1346 }
1347
1348 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1349 LLVMValueRef src0, LLVMValueRef src1)
1350 {
1351 LLVMValueRef dst64, result;
1352 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1353 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1354
1355 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1356 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1357 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1358 return result;
1359 }
1360
1361 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1362 bool is_signed,
1363 const LLVMValueRef srcs[3])
1364 {
1365 LLVMValueRef result;
1366 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1367
1368 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1369 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1370 return result;
1371 }
1372
1373 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1374 LLVMValueRef src0, LLVMValueRef src1,
1375 LLVMValueRef src2, LLVMValueRef src3)
1376 {
1377 LLVMValueRef bfi_args[3], result;
1378
1379 bfi_args[0] = LLVMBuildShl(ctx->builder,
1380 LLVMBuildSub(ctx->builder,
1381 LLVMBuildShl(ctx->builder,
1382 ctx->i32_1,
1383 src3, ""),
1384 ctx->i32_1, ""),
1385 src2, "");
1386 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1387 bfi_args[2] = src0;
1388
1389 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1390
1391 /* Calculate:
1392 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1393 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1394 */
1395 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1396 LLVMBuildAnd(ctx->builder, bfi_args[0],
1397 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1398
1399 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1400 return result;
1401 }
1402
1403 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1404 LLVMValueRef src0)
1405 {
1406 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1407 int i;
1408 LLVMValueRef comp[2];
1409
1410 src0 = to_float(ctx, src0);
1411 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1412 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1413 for (i = 0; i < 2; i++) {
1414 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1415 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1416 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1417 }
1418
1419 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1420 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1421
1422 return comp[0];
1423 }
1424
1425 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1426 LLVMValueRef src0)
1427 {
1428 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1429 LLVMValueRef temps[2], result, val;
1430 int i;
1431
1432 for (i = 0; i < 2; i++) {
1433 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1434 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1435 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1436 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1437 }
1438
1439 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1440 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1441 ctx->i32_0, "");
1442 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1443 ctx->i32_1, "");
1444 return result;
1445 }
1446
1447 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1448 nir_op op,
1449 LLVMValueRef src0)
1450 {
1451 unsigned mask;
1452 int idx;
1453 LLVMValueRef result;
1454 bool has_ds_bpermute = ctx->abi->chip_class >= VI;
1455
1456 if (!ctx->ddxy_lds && !has_ds_bpermute)
1457 ctx->ddxy_lds = LLVMAddGlobalInAddressSpace(ctx->ac.module,
1458 LLVMArrayType(ctx->ac.i32, 64),
1459 "ddxy_lds", LOCAL_ADDR_SPACE);
1460
1461 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1462 mask = AC_TID_MASK_LEFT;
1463 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1464 mask = AC_TID_MASK_TOP;
1465 else
1466 mask = AC_TID_MASK_TOP_LEFT;
1467
1468 /* for DDX we want to next X pixel, DDY next Y pixel. */
1469 if (op == nir_op_fddx_fine ||
1470 op == nir_op_fddx_coarse ||
1471 op == nir_op_fddx)
1472 idx = 1;
1473 else
1474 idx = 2;
1475
1476 result = ac_build_ddxy(&ctx->ac, has_ds_bpermute,
1477 mask, idx, ctx->ddxy_lds,
1478 src0);
1479 return result;
1480 }
1481
1482 /*
1483 * this takes an I,J coordinate pair,
1484 * and works out the X and Y derivatives.
1485 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1486 */
1487 static LLVMValueRef emit_ddxy_interp(
1488 struct ac_nir_context *ctx,
1489 LLVMValueRef interp_ij)
1490 {
1491 LLVMValueRef result[4], a;
1492 unsigned i;
1493
1494 for (i = 0; i < 2; i++) {
1495 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1496 LLVMConstInt(ctx->ac.i32, i, false), "");
1497 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1498 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1499 }
1500 return ac_build_gather_values(&ctx->ac, result, 4);
1501 }
1502
1503 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1504 {
1505 LLVMValueRef src[4], result = NULL;
1506 unsigned num_components = instr->dest.dest.ssa.num_components;
1507 unsigned src_components;
1508 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1509
1510 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1511 switch (instr->op) {
1512 case nir_op_vec2:
1513 case nir_op_vec3:
1514 case nir_op_vec4:
1515 src_components = 1;
1516 break;
1517 case nir_op_pack_half_2x16:
1518 src_components = 2;
1519 break;
1520 case nir_op_unpack_half_2x16:
1521 src_components = 1;
1522 break;
1523 default:
1524 src_components = num_components;
1525 break;
1526 }
1527 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1528 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1529
1530 switch (instr->op) {
1531 case nir_op_fmov:
1532 case nir_op_imov:
1533 result = src[0];
1534 break;
1535 case nir_op_fneg:
1536 src[0] = to_float(&ctx->ac, src[0]);
1537 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1538 break;
1539 case nir_op_ineg:
1540 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1541 break;
1542 case nir_op_inot:
1543 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1544 break;
1545 case nir_op_iadd:
1546 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1547 break;
1548 case nir_op_fadd:
1549 src[0] = to_float(&ctx->ac, src[0]);
1550 src[1] = to_float(&ctx->ac, src[1]);
1551 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1552 break;
1553 case nir_op_fsub:
1554 src[0] = to_float(&ctx->ac, src[0]);
1555 src[1] = to_float(&ctx->ac, src[1]);
1556 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1557 break;
1558 case nir_op_isub:
1559 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1560 break;
1561 case nir_op_imul:
1562 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1563 break;
1564 case nir_op_imod:
1565 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1566 break;
1567 case nir_op_umod:
1568 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1569 break;
1570 case nir_op_fmod:
1571 src[0] = to_float(&ctx->ac, src[0]);
1572 src[1] = to_float(&ctx->ac, src[1]);
1573 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1574 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1575 to_float_type(&ctx->ac, def_type), result);
1576 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1577 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1578 break;
1579 case nir_op_frem:
1580 src[0] = to_float(&ctx->ac, src[0]);
1581 src[1] = to_float(&ctx->ac, src[1]);
1582 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1583 break;
1584 case nir_op_irem:
1585 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1586 break;
1587 case nir_op_idiv:
1588 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1589 break;
1590 case nir_op_udiv:
1591 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1592 break;
1593 case nir_op_fmul:
1594 src[0] = to_float(&ctx->ac, src[0]);
1595 src[1] = to_float(&ctx->ac, src[1]);
1596 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1597 break;
1598 case nir_op_fdiv:
1599 src[0] = to_float(&ctx->ac, src[0]);
1600 src[1] = to_float(&ctx->ac, src[1]);
1601 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1602 break;
1603 case nir_op_frcp:
1604 src[0] = to_float(&ctx->ac, src[0]);
1605 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1606 break;
1607 case nir_op_iand:
1608 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1609 break;
1610 case nir_op_ior:
1611 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1612 break;
1613 case nir_op_ixor:
1614 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1615 break;
1616 case nir_op_ishl:
1617 result = LLVMBuildShl(ctx->ac.builder, src[0],
1618 LLVMBuildZExt(ctx->ac.builder, src[1],
1619 LLVMTypeOf(src[0]), ""),
1620 "");
1621 break;
1622 case nir_op_ishr:
1623 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1624 LLVMBuildZExt(ctx->ac.builder, src[1],
1625 LLVMTypeOf(src[0]), ""),
1626 "");
1627 break;
1628 case nir_op_ushr:
1629 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1630 LLVMBuildZExt(ctx->ac.builder, src[1],
1631 LLVMTypeOf(src[0]), ""),
1632 "");
1633 break;
1634 case nir_op_ilt:
1635 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1636 break;
1637 case nir_op_ine:
1638 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1639 break;
1640 case nir_op_ieq:
1641 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1642 break;
1643 case nir_op_ige:
1644 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1645 break;
1646 case nir_op_ult:
1647 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1648 break;
1649 case nir_op_uge:
1650 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1651 break;
1652 case nir_op_feq:
1653 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1654 break;
1655 case nir_op_fne:
1656 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1657 break;
1658 case nir_op_flt:
1659 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1660 break;
1661 case nir_op_fge:
1662 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1663 break;
1664 case nir_op_fabs:
1665 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1666 to_float_type(&ctx->ac, def_type), src[0]);
1667 break;
1668 case nir_op_iabs:
1669 result = emit_iabs(&ctx->ac, src[0]);
1670 break;
1671 case nir_op_imax:
1672 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1673 break;
1674 case nir_op_imin:
1675 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1676 break;
1677 case nir_op_umax:
1678 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1679 break;
1680 case nir_op_umin:
1681 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1682 break;
1683 case nir_op_isign:
1684 result = emit_isign(&ctx->ac, src[0]);
1685 break;
1686 case nir_op_fsign:
1687 src[0] = to_float(&ctx->ac, src[0]);
1688 result = emit_fsign(&ctx->ac, src[0]);
1689 break;
1690 case nir_op_ffloor:
1691 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1692 to_float_type(&ctx->ac, def_type), src[0]);
1693 break;
1694 case nir_op_ftrunc:
1695 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1696 to_float_type(&ctx->ac, def_type), src[0]);
1697 break;
1698 case nir_op_fceil:
1699 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1700 to_float_type(&ctx->ac, def_type), src[0]);
1701 break;
1702 case nir_op_fround_even:
1703 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1704 to_float_type(&ctx->ac, def_type),src[0]);
1705 break;
1706 case nir_op_ffract:
1707 result = emit_ffract(&ctx->ac, src[0]);
1708 break;
1709 case nir_op_fsin:
1710 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1711 to_float_type(&ctx->ac, def_type), src[0]);
1712 break;
1713 case nir_op_fcos:
1714 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1715 to_float_type(&ctx->ac, def_type), src[0]);
1716 break;
1717 case nir_op_fsqrt:
1718 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1719 to_float_type(&ctx->ac, def_type), src[0]);
1720 break;
1721 case nir_op_fexp2:
1722 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1723 to_float_type(&ctx->ac, def_type), src[0]);
1724 break;
1725 case nir_op_flog2:
1726 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1727 to_float_type(&ctx->ac, def_type), src[0]);
1728 break;
1729 case nir_op_frsq:
1730 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1731 to_float_type(&ctx->ac, def_type), src[0]);
1732 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1733 break;
1734 case nir_op_fpow:
1735 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1736 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1737 break;
1738 case nir_op_fmax:
1739 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1740 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1741 if (instr->dest.dest.ssa.bit_size == 32)
1742 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1743 to_float_type(&ctx->ac, def_type),
1744 result);
1745 break;
1746 case nir_op_fmin:
1747 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1748 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1749 if (instr->dest.dest.ssa.bit_size == 32)
1750 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1751 to_float_type(&ctx->ac, def_type),
1752 result);
1753 break;
1754 case nir_op_ffma:
1755 result = emit_intrin_3f_param(&ctx->ac, "llvm.fma",
1756 to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1757 break;
1758 case nir_op_ibitfield_extract:
1759 result = emit_bitfield_extract(&ctx->ac, true, src);
1760 break;
1761 case nir_op_ubitfield_extract:
1762 result = emit_bitfield_extract(&ctx->ac, false, src);
1763 break;
1764 case nir_op_bitfield_insert:
1765 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1766 break;
1767 case nir_op_bitfield_reverse:
1768 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1769 break;
1770 case nir_op_bit_count:
1771 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1772 break;
1773 case nir_op_vec2:
1774 case nir_op_vec3:
1775 case nir_op_vec4:
1776 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1777 src[i] = to_integer(&ctx->ac, src[i]);
1778 result = ac_build_gather_values(&ctx->ac, src, num_components);
1779 break;
1780 case nir_op_f2i32:
1781 case nir_op_f2i64:
1782 src[0] = to_float(&ctx->ac, src[0]);
1783 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1784 break;
1785 case nir_op_f2u32:
1786 case nir_op_f2u64:
1787 src[0] = to_float(&ctx->ac, src[0]);
1788 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1789 break;
1790 case nir_op_i2f32:
1791 case nir_op_i2f64:
1792 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1793 break;
1794 case nir_op_u2f32:
1795 case nir_op_u2f64:
1796 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1797 break;
1798 case nir_op_f2f64:
1799 result = LLVMBuildFPExt(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1800 break;
1801 case nir_op_f2f32:
1802 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1803 break;
1804 case nir_op_u2u32:
1805 case nir_op_u2u64:
1806 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1807 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1808 else
1809 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1810 break;
1811 case nir_op_i2i32:
1812 case nir_op_i2i64:
1813 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1814 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1815 else
1816 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1817 break;
1818 case nir_op_bcsel:
1819 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1820 break;
1821 case nir_op_find_lsb:
1822 result = emit_find_lsb(&ctx->ac, src[0]);
1823 break;
1824 case nir_op_ufind_msb:
1825 result = emit_ufind_msb(&ctx->ac, src[0]);
1826 break;
1827 case nir_op_ifind_msb:
1828 result = emit_ifind_msb(&ctx->ac, src[0]);
1829 break;
1830 case nir_op_uadd_carry:
1831 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1832 break;
1833 case nir_op_usub_borrow:
1834 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1835 break;
1836 case nir_op_b2f:
1837 result = emit_b2f(&ctx->ac, src[0]);
1838 break;
1839 case nir_op_f2b:
1840 result = emit_f2b(&ctx->ac, src[0]);
1841 break;
1842 case nir_op_b2i:
1843 result = emit_b2i(&ctx->ac, src[0]);
1844 break;
1845 case nir_op_i2b:
1846 result = emit_i2b(&ctx->ac, src[0]);
1847 break;
1848 case nir_op_fquantize2f16:
1849 result = emit_f2f16(ctx->nctx, src[0]);
1850 break;
1851 case nir_op_umul_high:
1852 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1853 break;
1854 case nir_op_imul_high:
1855 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1856 break;
1857 case nir_op_pack_half_2x16:
1858 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1859 break;
1860 case nir_op_unpack_half_2x16:
1861 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1862 break;
1863 case nir_op_fddx:
1864 case nir_op_fddy:
1865 case nir_op_fddx_fine:
1866 case nir_op_fddy_fine:
1867 case nir_op_fddx_coarse:
1868 case nir_op_fddy_coarse:
1869 result = emit_ddxy(ctx, instr->op, src[0]);
1870 break;
1871
1872 case nir_op_unpack_64_2x32_split_x: {
1873 assert(instr->src[0].src.ssa->num_components == 1);
1874 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1875 LLVMVectorType(ctx->ac.i32, 2),
1876 "");
1877 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1878 ctx->ac.i32_0, "");
1879 break;
1880 }
1881
1882 case nir_op_unpack_64_2x32_split_y: {
1883 assert(instr->src[0].src.ssa->num_components == 1);
1884 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1885 LLVMVectorType(ctx->ac.i32, 2),
1886 "");
1887 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1888 ctx->ac.i32_0, "");
1889 break;
1890 }
1891
1892 case nir_op_pack_64_2x32_split: {
1893 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
1894 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1895 src[0], ctx->ac.i32_0, "");
1896 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1897 src[1], ctx->ac.i32_1, "");
1898 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1899 break;
1900 }
1901
1902 default:
1903 fprintf(stderr, "Unknown NIR alu instr: ");
1904 nir_print_instr(&instr->instr, stderr);
1905 fprintf(stderr, "\n");
1906 abort();
1907 }
1908
1909 if (result) {
1910 assert(instr->dest.dest.is_ssa);
1911 result = to_integer(&ctx->ac, result);
1912 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1913 result);
1914 }
1915 }
1916
1917 static void visit_load_const(struct ac_nir_context *ctx,
1918 const nir_load_const_instr *instr)
1919 {
1920 LLVMValueRef values[4], value = NULL;
1921 LLVMTypeRef element_type =
1922 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1923
1924 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1925 switch (instr->def.bit_size) {
1926 case 32:
1927 values[i] = LLVMConstInt(element_type,
1928 instr->value.u32[i], false);
1929 break;
1930 case 64:
1931 values[i] = LLVMConstInt(element_type,
1932 instr->value.u64[i], false);
1933 break;
1934 default:
1935 fprintf(stderr,
1936 "unsupported nir load_const bit_size: %d\n",
1937 instr->def.bit_size);
1938 abort();
1939 }
1940 }
1941 if (instr->def.num_components > 1) {
1942 value = LLVMConstVector(values, instr->def.num_components);
1943 } else
1944 value = values[0];
1945
1946 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1947 }
1948
1949 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1950 LLVMTypeRef type)
1951 {
1952 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1953 return LLVMBuildBitCast(ctx->builder, ptr,
1954 LLVMPointerType(type, addr_space), "");
1955 }
1956
1957 static LLVMValueRef
1958 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1959 {
1960 LLVMValueRef size =
1961 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1962 LLVMConstInt(ctx->ac.i32, 2, false), "");
1963
1964 /* VI only */
1965 if (ctx->abi->chip_class >= VI && in_elements) {
1966 /* On VI, the descriptor contains the size in bytes,
1967 * but TXQ must return the size in elements.
1968 * The stride is always non-zero for resources using TXQ.
1969 */
1970 LLVMValueRef stride =
1971 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1972 LLVMConstInt(ctx->ac.i32, 1, false), "");
1973 stride = LLVMBuildLShr(ctx->ac.builder, stride,
1974 LLVMConstInt(ctx->ac.i32, 16, false), "");
1975 stride = LLVMBuildAnd(ctx->ac.builder, stride,
1976 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
1977
1978 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
1979 }
1980 return size;
1981 }
1982
1983 /**
1984 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1985 * intrinsic names).
1986 */
1987 static void build_int_type_name(
1988 LLVMTypeRef type,
1989 char *buf, unsigned bufsize)
1990 {
1991 assert(bufsize >= 6);
1992
1993 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1994 snprintf(buf, bufsize, "v%ui32",
1995 LLVMGetVectorSize(type));
1996 else
1997 strcpy(buf, "i32");
1998 }
1999
2000 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2001 struct ac_image_args *args,
2002 const nir_tex_instr *instr)
2003 {
2004 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2005 LLVMValueRef coord = args->addr;
2006 LLVMValueRef half_texel[2];
2007 LLVMValueRef compare_cube_wa;
2008 LLVMValueRef result;
2009 int c;
2010 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2011
2012 //TODO Rect
2013 {
2014 struct ac_image_args txq_args = { 0 };
2015
2016 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2017 txq_args.opcode = ac_image_get_resinfo;
2018 txq_args.dmask = 0xf;
2019 txq_args.addr = ctx->i32_0;
2020 txq_args.resource = args->resource;
2021 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2022
2023 for (c = 0; c < 2; c++) {
2024 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2025 LLVMConstInt(ctx->i32, c, false), "");
2026 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2027 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2028 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2029 LLVMConstReal(ctx->f32, -0.5), "");
2030 }
2031 }
2032
2033 LLVMValueRef orig_coords = args->addr;
2034
2035 for (c = 0; c < 2; c++) {
2036 LLVMValueRef tmp;
2037 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2038 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2039 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2040 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2041 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2042 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2043 }
2044
2045
2046 /*
2047 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2048 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2049 * workaround by sampling using a scaled type and converting.
2050 * This is taken from amdgpu-pro shaders.
2051 */
2052 /* NOTE this produces some ugly code compared to amdgpu-pro,
2053 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2054 * and then reads them back. -pro generates two selects,
2055 * one s_cmp for the descriptor rewriting
2056 * one v_cmp for the coordinate and result changes.
2057 */
2058 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2059 LLVMValueRef tmp, tmp2;
2060
2061 /* workaround 8/8/8/8 uint/sint cube gather bug */
2062 /* first detect it then change to a scaled read and f2i */
2063 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2064 tmp2 = tmp;
2065
2066 /* extract the DATA_FORMAT */
2067 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2068 LLVMConstInt(ctx->i32, 6, false), false);
2069
2070 /* is the DATA_FORMAT == 8_8_8_8 */
2071 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2072
2073 if (stype == GLSL_TYPE_UINT)
2074 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2075 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2076 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2077 else
2078 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2079 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2080 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2081
2082 /* replace the NUM FORMAT in the descriptor */
2083 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2084 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2085
2086 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2087
2088 /* don't modify the coordinates for this case */
2089 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2090 }
2091 args->addr = coord;
2092 result = ac_build_image_opcode(ctx, args);
2093
2094 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2095 LLVMValueRef tmp, tmp2;
2096
2097 /* if the cube workaround is in place, f2i the result. */
2098 for (c = 0; c < 4; c++) {
2099 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2100 if (stype == GLSL_TYPE_UINT)
2101 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2102 else
2103 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2104 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2105 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2106 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2107 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2108 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2109 }
2110 }
2111 return result;
2112 }
2113
2114 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2115 const nir_tex_instr *instr,
2116 bool lod_is_zero,
2117 struct ac_image_args *args)
2118 {
2119 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2120 return ac_build_buffer_load_format(&ctx->ac,
2121 args->resource,
2122 args->addr,
2123 LLVMConstInt(ctx->ac.i32, 0, false),
2124 true);
2125 }
2126
2127 args->opcode = ac_image_sample;
2128 args->compare = instr->is_shadow;
2129
2130 switch (instr->op) {
2131 case nir_texop_txf:
2132 case nir_texop_txf_ms:
2133 case nir_texop_samples_identical:
2134 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2135 args->compare = false;
2136 args->offset = false;
2137 break;
2138 case nir_texop_txb:
2139 args->bias = true;
2140 break;
2141 case nir_texop_txl:
2142 if (lod_is_zero)
2143 args->level_zero = true;
2144 else
2145 args->lod = true;
2146 break;
2147 case nir_texop_txs:
2148 case nir_texop_query_levels:
2149 args->opcode = ac_image_get_resinfo;
2150 break;
2151 case nir_texop_tex:
2152 if (ctx->stage != MESA_SHADER_FRAGMENT)
2153 args->level_zero = true;
2154 break;
2155 case nir_texop_txd:
2156 args->deriv = true;
2157 break;
2158 case nir_texop_tg4:
2159 args->opcode = ac_image_gather4;
2160 args->level_zero = true;
2161 break;
2162 case nir_texop_lod:
2163 args->opcode = ac_image_get_lod;
2164 args->compare = false;
2165 args->offset = false;
2166 break;
2167 default:
2168 break;
2169 }
2170
2171 if (instr->op == nir_texop_tg4) {
2172 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2173 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2174 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2175 }
2176 }
2177 return ac_build_image_opcode(&ctx->ac, args);
2178 }
2179
2180 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2181 nir_intrinsic_instr *instr)
2182 {
2183 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2184 unsigned desc_set = nir_intrinsic_desc_set(instr);
2185 unsigned binding = nir_intrinsic_binding(instr);
2186 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2187 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2188 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2189 unsigned base_offset = layout->binding[binding].offset;
2190 LLVMValueRef offset, stride;
2191
2192 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2193 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2194 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2195 layout->binding[binding].dynamic_offset_offset;
2196 desc_ptr = ctx->push_constants;
2197 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2198 stride = LLVMConstInt(ctx->i32, 16, false);
2199 } else
2200 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2201
2202 offset = LLVMConstInt(ctx->i32, base_offset, false);
2203 index = LLVMBuildMul(ctx->builder, index, stride, "");
2204 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2205
2206 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2207 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2208 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2209
2210 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2211 }
2212
2213 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2214 nir_intrinsic_instr *instr)
2215 {
2216 LLVMValueRef ptr, addr;
2217
2218 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2219 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2220
2221 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2222 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2223
2224 return LLVMBuildLoad(ctx->builder, ptr, "");
2225 }
2226
2227 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2228 const nir_intrinsic_instr *instr)
2229 {
2230 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2231
2232 return get_buffer_size(ctx, desc, false);
2233 }
2234 static void visit_store_ssbo(struct ac_nir_context *ctx,
2235 nir_intrinsic_instr *instr)
2236 {
2237 const char *store_name;
2238 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2239 LLVMTypeRef data_type = ctx->ac.f32;
2240 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2241 int components_32bit = elem_size_mult * instr->num_components;
2242 unsigned writemask = nir_intrinsic_write_mask(instr);
2243 LLVMValueRef base_data, base_offset;
2244 LLVMValueRef params[6];
2245 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2246
2247 params[1] = ctx->abi->load_ssbo(ctx->abi,
2248 get_src(ctx, instr->src[1]), true);
2249 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2250 params[4] = i1false; /* glc */
2251 params[5] = i1false; /* slc */
2252
2253 if (components_32bit > 1)
2254 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2255
2256 base_data = to_float(&ctx->ac, src_data);
2257 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2258 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2259 data_type, "");
2260 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2261 while (writemask) {
2262 int start, count;
2263 LLVMValueRef data;
2264 LLVMValueRef offset;
2265 LLVMValueRef tmp;
2266 u_bit_scan_consecutive_range(&writemask, &start, &count);
2267
2268 /* Due to an LLVM limitation, split 3-element writes
2269 * into a 2-element and a 1-element write. */
2270 if (count == 3) {
2271 writemask |= 1 << (start + 2);
2272 count = 2;
2273 }
2274
2275 start *= elem_size_mult;
2276 count *= elem_size_mult;
2277
2278 if (count > 4) {
2279 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2280 count = 4;
2281 }
2282
2283 if (count == 4) {
2284 store_name = "llvm.amdgcn.buffer.store.v4f32";
2285 data = base_data;
2286 } else if (count == 2) {
2287 LLVMTypeRef v2f32 = LLVMVectorType(ctx->ac.f32, 2);
2288
2289 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2290 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2291 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(v2f32), tmp,
2292 ctx->ac.i32_0, "");
2293
2294 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2295 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2296 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2297 ctx->ac.i32_1, "");
2298 store_name = "llvm.amdgcn.buffer.store.v2f32";
2299
2300 } else {
2301 assert(count == 1);
2302 if (get_llvm_num_components(base_data) > 1)
2303 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2304 LLVMConstInt(ctx->ac.i32, start, false), "");
2305 else
2306 data = base_data;
2307 store_name = "llvm.amdgcn.buffer.store.f32";
2308 }
2309
2310 offset = base_offset;
2311 if (start != 0) {
2312 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2313 }
2314 params[0] = data;
2315 params[3] = offset;
2316 ac_build_intrinsic(&ctx->ac, store_name,
2317 ctx->ac.voidt, params, 6, 0);
2318 }
2319 }
2320
2321 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2322 const nir_intrinsic_instr *instr)
2323 {
2324 const char *name;
2325 LLVMValueRef params[6];
2326 int arg_count = 0;
2327
2328 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2329 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2330 }
2331 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2332 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2333 get_src(ctx, instr->src[0]),
2334 true);
2335 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2336 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2337 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2338
2339 switch (instr->intrinsic) {
2340 case nir_intrinsic_ssbo_atomic_add:
2341 name = "llvm.amdgcn.buffer.atomic.add";
2342 break;
2343 case nir_intrinsic_ssbo_atomic_imin:
2344 name = "llvm.amdgcn.buffer.atomic.smin";
2345 break;
2346 case nir_intrinsic_ssbo_atomic_umin:
2347 name = "llvm.amdgcn.buffer.atomic.umin";
2348 break;
2349 case nir_intrinsic_ssbo_atomic_imax:
2350 name = "llvm.amdgcn.buffer.atomic.smax";
2351 break;
2352 case nir_intrinsic_ssbo_atomic_umax:
2353 name = "llvm.amdgcn.buffer.atomic.umax";
2354 break;
2355 case nir_intrinsic_ssbo_atomic_and:
2356 name = "llvm.amdgcn.buffer.atomic.and";
2357 break;
2358 case nir_intrinsic_ssbo_atomic_or:
2359 name = "llvm.amdgcn.buffer.atomic.or";
2360 break;
2361 case nir_intrinsic_ssbo_atomic_xor:
2362 name = "llvm.amdgcn.buffer.atomic.xor";
2363 break;
2364 case nir_intrinsic_ssbo_atomic_exchange:
2365 name = "llvm.amdgcn.buffer.atomic.swap";
2366 break;
2367 case nir_intrinsic_ssbo_atomic_comp_swap:
2368 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2369 break;
2370 default:
2371 abort();
2372 }
2373
2374 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2375 }
2376
2377 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2378 const nir_intrinsic_instr *instr)
2379 {
2380 LLVMValueRef results[2];
2381 int load_components;
2382 int num_components = instr->num_components;
2383 if (instr->dest.ssa.bit_size == 64)
2384 num_components *= 2;
2385
2386 for (int i = 0; i < num_components; i += load_components) {
2387 load_components = MIN2(num_components - i, 4);
2388 const char *load_name;
2389 LLVMTypeRef data_type = ctx->ac.f32;
2390 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2391 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2392
2393 if (load_components == 3)
2394 data_type = LLVMVectorType(ctx->ac.f32, 4);
2395 else if (load_components > 1)
2396 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2397
2398 if (load_components >= 3)
2399 load_name = "llvm.amdgcn.buffer.load.v4f32";
2400 else if (load_components == 2)
2401 load_name = "llvm.amdgcn.buffer.load.v2f32";
2402 else if (load_components == 1)
2403 load_name = "llvm.amdgcn.buffer.load.f32";
2404 else
2405 unreachable("unhandled number of components");
2406
2407 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2408 LLVMValueRef params[] = {
2409 ctx->abi->load_ssbo(ctx->abi,
2410 get_src(ctx, instr->src[0]),
2411 false),
2412 LLVMConstInt(ctx->ac.i32, 0, false),
2413 offset,
2414 i1false,
2415 i1false,
2416 };
2417
2418 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2419
2420 }
2421
2422 LLVMValueRef ret = results[0];
2423 if (num_components > 4 || num_components == 3) {
2424 LLVMValueRef masks[] = {
2425 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2426 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2427 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2428 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2429 };
2430
2431 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2432 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2433 results[num_components > 4 ? 1 : 0], swizzle, "");
2434 }
2435
2436 return LLVMBuildBitCast(ctx->ac.builder, ret,
2437 get_def_type(ctx, &instr->dest.ssa), "");
2438 }
2439
2440 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2441 const nir_intrinsic_instr *instr)
2442 {
2443 LLVMValueRef results[8], ret;
2444 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2445 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2446 int num_components = instr->num_components;
2447
2448 if (ctx->abi->load_ubo)
2449 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2450
2451 if (instr->dest.ssa.bit_size == 64)
2452 num_components *= 2;
2453
2454 for (unsigned i = 0; i < num_components; ++i) {
2455 LLVMValueRef params[] = {
2456 rsrc,
2457 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2458 offset, "")
2459 };
2460 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2461 params, 2,
2462 AC_FUNC_ATTR_READNONE |
2463 AC_FUNC_ATTR_LEGACY);
2464 }
2465
2466
2467 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2468 return LLVMBuildBitCast(ctx->ac.builder, ret,
2469 get_def_type(ctx, &instr->dest.ssa), "");
2470 }
2471
2472 static void
2473 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2474 bool vs_in, unsigned *vertex_index_out,
2475 LLVMValueRef *vertex_index_ref,
2476 unsigned *const_out, LLVMValueRef *indir_out)
2477 {
2478 unsigned const_offset = 0;
2479 nir_deref *tail = &deref->deref;
2480 LLVMValueRef offset = NULL;
2481
2482 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2483 tail = tail->child;
2484 nir_deref_array *deref_array = nir_deref_as_array(tail);
2485 if (vertex_index_out)
2486 *vertex_index_out = deref_array->base_offset;
2487
2488 if (vertex_index_ref) {
2489 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2490 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2491 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2492 }
2493 *vertex_index_ref = vtx;
2494 }
2495 }
2496
2497 if (deref->var->data.compact) {
2498 assert(tail->child->deref_type == nir_deref_type_array);
2499 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2500 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2501 /* We always lower indirect dereferences for "compact" array vars. */
2502 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2503
2504 const_offset = deref_array->base_offset;
2505 goto out;
2506 }
2507
2508 while (tail->child != NULL) {
2509 const struct glsl_type *parent_type = tail->type;
2510 tail = tail->child;
2511
2512 if (tail->deref_type == nir_deref_type_array) {
2513 nir_deref_array *deref_array = nir_deref_as_array(tail);
2514 LLVMValueRef index, stride, local_offset;
2515 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2516
2517 const_offset += size * deref_array->base_offset;
2518 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2519 continue;
2520
2521 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2522 index = get_src(ctx, deref_array->indirect);
2523 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2524 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2525
2526 if (offset)
2527 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2528 else
2529 offset = local_offset;
2530 } else if (tail->deref_type == nir_deref_type_struct) {
2531 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2532
2533 for (unsigned i = 0; i < deref_struct->index; i++) {
2534 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2535 const_offset += glsl_count_attribute_slots(ft, vs_in);
2536 }
2537 } else
2538 unreachable("unsupported deref type");
2539
2540 }
2541 out:
2542 if (const_offset && offset)
2543 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2544 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2545 "");
2546
2547 *const_out = const_offset;
2548 *indir_out = offset;
2549 }
2550
2551 static LLVMValueRef
2552 lds_load(struct nir_to_llvm_context *ctx,
2553 LLVMValueRef dw_addr)
2554 {
2555 LLVMValueRef value;
2556 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2557 return value;
2558 }
2559
2560 static void
2561 lds_store(struct nir_to_llvm_context *ctx,
2562 LLVMValueRef dw_addr, LLVMValueRef value)
2563 {
2564 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2565 ac_build_indexed_store(&ctx->ac, ctx->lds,
2566 dw_addr, value);
2567 }
2568
2569 /* The offchip buffer layout for TCS->TES is
2570 *
2571 * - attribute 0 of patch 0 vertex 0
2572 * - attribute 0 of patch 0 vertex 1
2573 * - attribute 0 of patch 0 vertex 2
2574 * ...
2575 * - attribute 0 of patch 1 vertex 0
2576 * - attribute 0 of patch 1 vertex 1
2577 * ...
2578 * - attribute 1 of patch 0 vertex 0
2579 * - attribute 1 of patch 0 vertex 1
2580 * ...
2581 * - per patch attribute 0 of patch 0
2582 * - per patch attribute 0 of patch 1
2583 * ...
2584 *
2585 * Note that every attribute has 4 components.
2586 */
2587 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2588 LLVMValueRef vertex_index,
2589 LLVMValueRef param_index)
2590 {
2591 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2592 LLVMValueRef param_stride, constant16;
2593 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2594
2595 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2596 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2597 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2598 num_patches, "");
2599
2600 constant16 = LLVMConstInt(ctx->i32, 16, false);
2601 if (vertex_index) {
2602 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2603 vertices_per_patch, "");
2604
2605 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2606 vertex_index, "");
2607
2608 param_stride = total_vertices;
2609 } else {
2610 base_addr = rel_patch_id;
2611 param_stride = num_patches;
2612 }
2613
2614 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2615 LLVMBuildMul(ctx->builder, param_index,
2616 param_stride, ""), "");
2617
2618 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2619
2620 if (!vertex_index) {
2621 LLVMValueRef patch_data_offset =
2622 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2623
2624 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2625 patch_data_offset, "");
2626 }
2627 return base_addr;
2628 }
2629
2630 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2631 unsigned param,
2632 unsigned const_index,
2633 bool is_compact,
2634 LLVMValueRef vertex_index,
2635 LLVMValueRef indir_index)
2636 {
2637 LLVMValueRef param_index;
2638
2639 if (indir_index)
2640 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2641 indir_index, "");
2642 else {
2643 if (const_index && !is_compact)
2644 param += const_index;
2645 param_index = LLVMConstInt(ctx->i32, param, false);
2646 }
2647 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2648 }
2649
2650 static void
2651 mark_tess_output(struct nir_to_llvm_context *ctx,
2652 bool is_patch, uint32_t param)
2653
2654 {
2655 if (is_patch) {
2656 ctx->tess_patch_outputs_written |= (1ull << param);
2657 } else
2658 ctx->tess_outputs_written |= (1ull << param);
2659 }
2660
2661 static LLVMValueRef
2662 get_dw_address(struct nir_to_llvm_context *ctx,
2663 LLVMValueRef dw_addr,
2664 unsigned param,
2665 unsigned const_index,
2666 bool compact_const_index,
2667 LLVMValueRef vertex_index,
2668 LLVMValueRef stride,
2669 LLVMValueRef indir_index)
2670
2671 {
2672
2673 if (vertex_index) {
2674 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2675 LLVMBuildMul(ctx->builder,
2676 vertex_index,
2677 stride, ""), "");
2678 }
2679
2680 if (indir_index)
2681 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2682 LLVMBuildMul(ctx->builder, indir_index,
2683 LLVMConstInt(ctx->i32, 4, false), ""), "");
2684 else if (const_index && !compact_const_index)
2685 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2686 LLVMConstInt(ctx->i32, const_index, false), "");
2687
2688 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2689 LLVMConstInt(ctx->i32, param * 4, false), "");
2690
2691 if (const_index && compact_const_index)
2692 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2693 LLVMConstInt(ctx->i32, const_index, false), "");
2694 return dw_addr;
2695 }
2696
2697 static LLVMValueRef
2698 load_tcs_input(struct nir_to_llvm_context *ctx,
2699 nir_intrinsic_instr *instr)
2700 {
2701 LLVMValueRef dw_addr, stride;
2702 unsigned const_index;
2703 LLVMValueRef vertex_index;
2704 LLVMValueRef indir_index;
2705 unsigned param;
2706 LLVMValueRef value[4], result;
2707 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2708 const bool is_compact = instr->variables[0]->var->data.compact;
2709 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2710 get_deref_offset(ctx->nir, instr->variables[0],
2711 false, NULL, per_vertex ? &vertex_index : NULL,
2712 &const_index, &indir_index);
2713
2714 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2715 dw_addr = get_tcs_in_current_patch_offset(ctx);
2716 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2717 indir_index);
2718
2719 for (unsigned i = 0; i < instr->num_components; i++) {
2720 value[i] = lds_load(ctx, dw_addr);
2721 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2722 ctx->i32one, "");
2723 }
2724 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2725 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2726 return result;
2727 }
2728
2729 static LLVMValueRef
2730 load_tcs_output(struct nir_to_llvm_context *ctx,
2731 nir_intrinsic_instr *instr)
2732 {
2733 LLVMValueRef dw_addr, stride;
2734 LLVMValueRef value[4], result;
2735 LLVMValueRef vertex_index = NULL;
2736 LLVMValueRef indir_index = NULL;
2737 unsigned const_index = 0;
2738 unsigned param;
2739 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2740 const bool is_compact = instr->variables[0]->var->data.compact;
2741 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2742 get_deref_offset(ctx->nir, instr->variables[0],
2743 false, NULL, per_vertex ? &vertex_index : NULL,
2744 &const_index, &indir_index);
2745
2746 if (!instr->variables[0]->var->data.patch) {
2747 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2748 dw_addr = get_tcs_out_current_patch_offset(ctx);
2749 } else {
2750 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2751 }
2752
2753 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2754 indir_index);
2755
2756 for (unsigned i = 0; i < instr->num_components; i++) {
2757 value[i] = lds_load(ctx, dw_addr);
2758 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2759 ctx->i32one, "");
2760 }
2761 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2762 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2763 return result;
2764 }
2765
2766 static void
2767 store_tcs_output(struct nir_to_llvm_context *ctx,
2768 nir_intrinsic_instr *instr,
2769 LLVMValueRef src,
2770 unsigned writemask)
2771 {
2772 LLVMValueRef stride, dw_addr;
2773 LLVMValueRef buf_addr = NULL;
2774 LLVMValueRef vertex_index = NULL;
2775 LLVMValueRef indir_index = NULL;
2776 unsigned const_index = 0;
2777 unsigned param;
2778 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2779 const bool is_compact = instr->variables[0]->var->data.compact;
2780
2781 get_deref_offset(ctx->nir, instr->variables[0],
2782 false, NULL, per_vertex ? &vertex_index : NULL,
2783 &const_index, &indir_index);
2784
2785 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2786 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2787 is_compact && const_index > 3) {
2788 const_index -= 3;
2789 param++;
2790 }
2791
2792 if (!instr->variables[0]->var->data.patch) {
2793 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2794 dw_addr = get_tcs_out_current_patch_offset(ctx);
2795 } else {
2796 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2797 }
2798
2799 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2800
2801 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2802 indir_index);
2803 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2804 vertex_index, indir_index);
2805
2806 unsigned base = is_compact ? const_index : 0;
2807 for (unsigned chan = 0; chan < 8; chan++) {
2808 bool is_tess_factor = false;
2809 if (!(writemask & (1 << chan)))
2810 continue;
2811 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan);
2812
2813 lds_store(ctx, dw_addr, value);
2814
2815 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2816 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2817 is_tess_factor = true;
2818
2819 if (!is_tess_factor && writemask != 0xF)
2820 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2821 buf_addr, ctx->oc_lds,
2822 4 * (base + chan), 1, 0, true, false);
2823
2824 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2825 ctx->i32one, "");
2826 }
2827
2828 if (writemask == 0xF) {
2829 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2830 buf_addr, ctx->oc_lds,
2831 (base * 4), 1, 0, true, false);
2832 }
2833 }
2834
2835 static LLVMValueRef
2836 load_tes_input(struct nir_to_llvm_context *ctx,
2837 const nir_intrinsic_instr *instr)
2838 {
2839 LLVMValueRef buf_addr;
2840 LLVMValueRef result;
2841 LLVMValueRef vertex_index = NULL;
2842 LLVMValueRef indir_index = NULL;
2843 unsigned const_index = 0;
2844 unsigned param;
2845 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2846 const bool is_compact = instr->variables[0]->var->data.compact;
2847
2848 get_deref_offset(ctx->nir, instr->variables[0],
2849 false, NULL, per_vertex ? &vertex_index : NULL,
2850 &const_index, &indir_index);
2851 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2852 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2853 is_compact && const_index > 3) {
2854 const_index -= 3;
2855 param++;
2856 }
2857 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2858 is_compact, vertex_index, indir_index);
2859
2860 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2861 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2862 result = trim_vector(&ctx->ac, result, instr->num_components);
2863 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2864 return result;
2865 }
2866
2867 static LLVMValueRef
2868 load_gs_input(struct nir_to_llvm_context *ctx,
2869 nir_intrinsic_instr *instr)
2870 {
2871 LLVMValueRef indir_index, vtx_offset;
2872 unsigned const_index;
2873 LLVMValueRef args[9];
2874 unsigned param, vtx_offset_param;
2875 LLVMValueRef value[4], result;
2876 unsigned vertex_index;
2877 get_deref_offset(ctx->nir, instr->variables[0],
2878 false, &vertex_index, NULL,
2879 &const_index, &indir_index);
2880 vtx_offset_param = vertex_index;
2881 assert(vtx_offset_param < 6);
2882 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2883 LLVMConstInt(ctx->i32, 4, false), "");
2884
2885 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2886 for (unsigned i = 0; i < instr->num_components; i++) {
2887
2888 args[0] = ctx->esgs_ring;
2889 args[1] = vtx_offset;
2890 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2891 args[3] = ctx->i32zero;
2892 args[4] = ctx->i32one; /* OFFEN */
2893 args[5] = ctx->i32zero; /* IDXEN */
2894 args[6] = ctx->i32one; /* GLC */
2895 args[7] = ctx->i32zero; /* SLC */
2896 args[8] = ctx->i32zero; /* TFE */
2897
2898 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2899 ctx->i32, args, 9,
2900 AC_FUNC_ATTR_READONLY |
2901 AC_FUNC_ATTR_LEGACY);
2902 }
2903 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2904
2905 return result;
2906 }
2907
2908 static LLVMValueRef
2909 build_gep_for_deref(struct ac_nir_context *ctx,
2910 nir_deref_var *deref)
2911 {
2912 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2913 assert(entry->data);
2914 LLVMValueRef val = entry->data;
2915 nir_deref *tail = deref->deref.child;
2916 while (tail != NULL) {
2917 LLVMValueRef offset;
2918 switch (tail->deref_type) {
2919 case nir_deref_type_array: {
2920 nir_deref_array *array = nir_deref_as_array(tail);
2921 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2922 if (array->deref_array_type ==
2923 nir_deref_array_type_indirect) {
2924 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2925 get_src(ctx,
2926 array->indirect),
2927 "");
2928 }
2929 break;
2930 }
2931 case nir_deref_type_struct: {
2932 nir_deref_struct *deref_struct =
2933 nir_deref_as_struct(tail);
2934 offset = LLVMConstInt(ctx->ac.i32,
2935 deref_struct->index, 0);
2936 break;
2937 }
2938 default:
2939 unreachable("bad deref type");
2940 }
2941 val = ac_build_gep0(&ctx->ac, val, offset);
2942 tail = tail->child;
2943 }
2944 return val;
2945 }
2946
2947 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
2948 nir_intrinsic_instr *instr)
2949 {
2950 LLVMValueRef values[8];
2951 int idx = instr->variables[0]->var->data.driver_location;
2952 int ve = instr->dest.ssa.num_components;
2953 LLVMValueRef indir_index;
2954 LLVMValueRef ret;
2955 unsigned const_index;
2956 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2957 instr->variables[0]->var->data.mode == nir_var_shader_in;
2958 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2959 &const_index, &indir_index);
2960
2961 if (instr->dest.ssa.bit_size == 64)
2962 ve *= 2;
2963
2964 switch (instr->variables[0]->var->data.mode) {
2965 case nir_var_shader_in:
2966 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2967 return load_tcs_input(ctx->nctx, instr);
2968 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2969 return load_tes_input(ctx->nctx, instr);
2970 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2971 return load_gs_input(ctx->nctx, instr);
2972 }
2973 for (unsigned chan = 0; chan < ve; chan++) {
2974 if (indir_index) {
2975 unsigned count = glsl_count_attribute_slots(
2976 instr->variables[0]->var->type,
2977 ctx->stage == MESA_SHADER_VERTEX);
2978 count -= chan / 4;
2979 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2980 &ctx->ac, ctx->abi->inputs + idx + chan, count,
2981 4, false, true);
2982
2983 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
2984 tmp_vec,
2985 indir_index, "");
2986 } else
2987 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
2988 }
2989 break;
2990 case nir_var_local:
2991 for (unsigned chan = 0; chan < ve; chan++) {
2992 if (indir_index) {
2993 unsigned count = glsl_count_attribute_slots(
2994 instr->variables[0]->var->type, false);
2995 count -= chan / 4;
2996 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2997 &ctx->ac, ctx->locals + idx + chan, count,
2998 4, true, true);
2999
3000 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3001 tmp_vec,
3002 indir_index, "");
3003 } else {
3004 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3005 }
3006 }
3007 break;
3008 case nir_var_shared: {
3009 LLVMValueRef address = build_gep_for_deref(ctx,
3010 instr->variables[0]);
3011 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3012 return LLVMBuildBitCast(ctx->ac.builder, val,
3013 get_def_type(ctx, &instr->dest.ssa),
3014 "");
3015 }
3016 case nir_var_shader_out:
3017 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3018 return load_tcs_output(ctx->nctx, instr);
3019 for (unsigned chan = 0; chan < ve; chan++) {
3020 if (indir_index) {
3021 unsigned count = glsl_count_attribute_slots(
3022 instr->variables[0]->var->type, false);
3023 count -= chan / 4;
3024 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3025 &ctx->ac, ctx->outputs + idx + chan, count,
3026 4, true, true);
3027
3028 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3029 tmp_vec,
3030 indir_index, "");
3031 } else {
3032 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3033 ctx->outputs[idx + chan + const_index * 4],
3034 "");
3035 }
3036 }
3037 break;
3038 default:
3039 unreachable("unhandle variable mode");
3040 }
3041 ret = ac_build_gather_values(&ctx->ac, values, ve);
3042 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3043 }
3044
3045 static void
3046 visit_store_var(struct ac_nir_context *ctx,
3047 nir_intrinsic_instr *instr)
3048 {
3049 LLVMValueRef temp_ptr, value;
3050 int idx = instr->variables[0]->var->data.driver_location;
3051 LLVMValueRef src = to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3052 int writemask = instr->const_index[0];
3053 LLVMValueRef indir_index;
3054 unsigned const_index;
3055 get_deref_offset(ctx, instr->variables[0], false,
3056 NULL, NULL, &const_index, &indir_index);
3057
3058 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3059 int old_writemask = writemask;
3060
3061 src = LLVMBuildBitCast(ctx->ac.builder, src,
3062 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3063 "");
3064
3065 writemask = 0;
3066 for (unsigned chan = 0; chan < 4; chan++) {
3067 if (old_writemask & (1 << chan))
3068 writemask |= 3u << (2 * chan);
3069 }
3070 }
3071
3072 switch (instr->variables[0]->var->data.mode) {
3073 case nir_var_shader_out:
3074
3075 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3076 store_tcs_output(ctx->nctx, instr, src, writemask);
3077 return;
3078 }
3079
3080 for (unsigned chan = 0; chan < 8; chan++) {
3081 int stride = 4;
3082 if (!(writemask & (1 << chan)))
3083 continue;
3084
3085 value = llvm_extract_elem(&ctx->ac, src, chan);
3086
3087 if (instr->variables[0]->var->data.compact)
3088 stride = 1;
3089 if (indir_index) {
3090 unsigned count = glsl_count_attribute_slots(
3091 instr->variables[0]->var->type, false);
3092 count -= chan / 4;
3093 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3094 &ctx->ac, ctx->outputs + idx + chan, count,
3095 stride, true, true);
3096
3097 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3098 value, indir_index, "");
3099 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3100 count, stride, tmp_vec);
3101
3102 } else {
3103 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3104
3105 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3106 }
3107 }
3108 break;
3109 case nir_var_local:
3110 for (unsigned chan = 0; chan < 8; chan++) {
3111 if (!(writemask & (1 << chan)))
3112 continue;
3113
3114 value = llvm_extract_elem(&ctx->ac, src, chan);
3115 if (indir_index) {
3116 unsigned count = glsl_count_attribute_slots(
3117 instr->variables[0]->var->type, false);
3118 count -= chan / 4;
3119 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3120 &ctx->ac, ctx->locals + idx + chan, count,
3121 4, true, true);
3122
3123 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3124 value, indir_index, "");
3125 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3126 count, 4, tmp_vec);
3127 } else {
3128 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3129
3130 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3131 }
3132 }
3133 break;
3134 case nir_var_shared: {
3135 int writemask = instr->const_index[0];
3136 LLVMValueRef address = build_gep_for_deref(ctx,
3137 instr->variables[0]);
3138 LLVMValueRef val = get_src(ctx, instr->src[0]);
3139 unsigned components =
3140 glsl_get_vector_elements(
3141 nir_deref_tail(&instr->variables[0]->deref)->type);
3142 if (writemask == (1 << components) - 1) {
3143 val = LLVMBuildBitCast(
3144 ctx->ac.builder, val,
3145 LLVMGetElementType(LLVMTypeOf(address)), "");
3146 LLVMBuildStore(ctx->ac.builder, val, address);
3147 } else {
3148 for (unsigned chan = 0; chan < 4; chan++) {
3149 if (!(writemask & (1 << chan)))
3150 continue;
3151 LLVMValueRef ptr =
3152 LLVMBuildStructGEP(ctx->ac.builder,
3153 address, chan, "");
3154 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3155 chan);
3156 src = LLVMBuildBitCast(
3157 ctx->ac.builder, src,
3158 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3159 LLVMBuildStore(ctx->ac.builder, src, ptr);
3160 }
3161 }
3162 break;
3163 }
3164 default:
3165 break;
3166 }
3167 }
3168
3169 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3170 {
3171 switch (dim) {
3172 case GLSL_SAMPLER_DIM_BUF:
3173 return 1;
3174 case GLSL_SAMPLER_DIM_1D:
3175 return array ? 2 : 1;
3176 case GLSL_SAMPLER_DIM_2D:
3177 return array ? 3 : 2;
3178 case GLSL_SAMPLER_DIM_MS:
3179 return array ? 4 : 3;
3180 case GLSL_SAMPLER_DIM_3D:
3181 case GLSL_SAMPLER_DIM_CUBE:
3182 return 3;
3183 case GLSL_SAMPLER_DIM_RECT:
3184 case GLSL_SAMPLER_DIM_SUBPASS:
3185 return 2;
3186 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3187 return 3;
3188 default:
3189 break;
3190 }
3191 return 0;
3192 }
3193
3194
3195
3196 /* Adjust the sample index according to FMASK.
3197 *
3198 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3199 * which is the identity mapping. Each nibble says which physical sample
3200 * should be fetched to get that sample.
3201 *
3202 * For example, 0x11111100 means there are only 2 samples stored and
3203 * the second sample covers 3/4 of the pixel. When reading samples 0
3204 * and 1, return physical sample 0 (determined by the first two 0s
3205 * in FMASK), otherwise return physical sample 1.
3206 *
3207 * The sample index should be adjusted as follows:
3208 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3209 */
3210 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3211 LLVMValueRef coord_x, LLVMValueRef coord_y,
3212 LLVMValueRef coord_z,
3213 LLVMValueRef sample_index,
3214 LLVMValueRef fmask_desc_ptr)
3215 {
3216 LLVMValueRef fmask_load_address[4];
3217 LLVMValueRef res;
3218
3219 fmask_load_address[0] = coord_x;
3220 fmask_load_address[1] = coord_y;
3221 if (coord_z) {
3222 fmask_load_address[2] = coord_z;
3223 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3224 }
3225
3226 struct ac_image_args args = {0};
3227
3228 args.opcode = ac_image_load;
3229 args.da = coord_z ? true : false;
3230 args.resource = fmask_desc_ptr;
3231 args.dmask = 0xf;
3232 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3233
3234 res = ac_build_image_opcode(ctx, &args);
3235
3236 res = to_integer(ctx, res);
3237 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3238 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3239
3240 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3241 res,
3242 ctx->i32_0, "");
3243
3244 LLVMValueRef sample_index4 =
3245 LLVMBuildMul(ctx->builder, sample_index, four, "");
3246 LLVMValueRef shifted_fmask =
3247 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3248 LLVMValueRef final_sample =
3249 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3250
3251 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3252 * resource descriptor is 0 (invalid),
3253 */
3254 LLVMValueRef fmask_desc =
3255 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3256 ctx->v8i32, "");
3257
3258 LLVMValueRef fmask_word1 =
3259 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3260 ctx->i32_1, "");
3261
3262 LLVMValueRef word1_is_nonzero =
3263 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3264 fmask_word1, ctx->i32_0, "");
3265
3266 /* Replace the MSAA sample index. */
3267 sample_index =
3268 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3269 final_sample, sample_index, "");
3270 return sample_index;
3271 }
3272
3273 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3274 const nir_intrinsic_instr *instr)
3275 {
3276 const struct glsl_type *type = instr->variables[0]->var->type;
3277 if(instr->variables[0]->deref.child)
3278 type = instr->variables[0]->deref.child->type;
3279
3280 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3281 LLVMValueRef coords[4];
3282 LLVMValueRef masks[] = {
3283 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3284 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3285 };
3286 LLVMValueRef res;
3287 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3288
3289 int count;
3290 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3291 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3292 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3293 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3294 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3295
3296 count = image_type_to_components_count(dim,
3297 glsl_sampler_type_is_array(type));
3298
3299 if (is_ms) {
3300 LLVMValueRef fmask_load_address[3];
3301 int chan;
3302
3303 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3304 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3305 if (glsl_sampler_type_is_array(type))
3306 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3307 else
3308 fmask_load_address[2] = NULL;
3309 if (add_frag_pos) {
3310 for (chan = 0; chan < 2; ++chan)
3311 fmask_load_address[chan] =
3312 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3313 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3314 ctx->ac.i32, ""), "");
3315 }
3316 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3317 fmask_load_address[0],
3318 fmask_load_address[1],
3319 fmask_load_address[2],
3320 sample_index,
3321 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, true, false));
3322 }
3323 if (count == 1) {
3324 if (instr->src[0].ssa->num_components)
3325 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3326 else
3327 res = src0;
3328 } else {
3329 int chan;
3330 if (is_ms)
3331 count--;
3332 for (chan = 0; chan < count; ++chan) {
3333 coords[chan] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[chan], "");
3334 }
3335
3336 if (add_frag_pos) {
3337 for (chan = 0; chan < count; ++chan)
3338 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3339 ctx->ac.i32, ""), "");
3340 }
3341 if (is_ms) {
3342 coords[count] = sample_index;
3343 count++;
3344 }
3345
3346 if (count == 3) {
3347 coords[3] = LLVMGetUndef(ctx->ac.i32);
3348 count = 4;
3349 }
3350 res = ac_build_gather_values(&ctx->ac, coords, count);
3351 }
3352 return res;
3353 }
3354
3355 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3356 const nir_intrinsic_instr *instr)
3357 {
3358 LLVMValueRef params[7];
3359 LLVMValueRef res;
3360 char intrinsic_name[64];
3361 const nir_variable *var = instr->variables[0]->var;
3362 const struct glsl_type *type = var->type;
3363 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3364 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3365
3366 if(instr->variables[0]->deref.child)
3367 type = instr->variables[0]->deref.child->type;
3368
3369 type = glsl_without_array(type);
3370 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3371 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, false);
3372 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3373 ctx->ac.i32_0, ""); /* vindex */
3374 params[2] = ctx->ac.i32_0; /* voffset */
3375 params[3] = i1false; /* glc */
3376 params[4] = i1false; /* slc */
3377 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3378 params, 5, 0);
3379
3380 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3381 res = to_integer(&ctx->ac, res);
3382 } else {
3383 bool is_da = glsl_sampler_type_is_array(type) ||
3384 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3385 LLVMValueRef da = is_da ? i1true : i1false;
3386 LLVMValueRef glc = i1false;
3387 LLVMValueRef slc = i1false;
3388
3389 params[0] = get_image_coords(ctx, instr);
3390 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3391 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3392 if (HAVE_LLVM <= 0x0309) {
3393 params[3] = i1false; /* r128 */
3394 params[4] = da;
3395 params[5] = glc;
3396 params[6] = slc;
3397 } else {
3398 LLVMValueRef lwe = i1false;
3399 params[3] = glc;
3400 params[4] = slc;
3401 params[5] = lwe;
3402 params[6] = da;
3403 }
3404
3405 ac_get_image_intr_name("llvm.amdgcn.image.load",
3406 ctx->ac.v4f32, /* vdata */
3407 LLVMTypeOf(params[0]), /* coords */
3408 LLVMTypeOf(params[1]), /* rsrc */
3409 intrinsic_name, sizeof(intrinsic_name));
3410
3411 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3412 params, 7, AC_FUNC_ATTR_READONLY);
3413 }
3414 return to_integer(&ctx->ac, res);
3415 }
3416
3417 static void visit_image_store(struct ac_nir_context *ctx,
3418 nir_intrinsic_instr *instr)
3419 {
3420 LLVMValueRef params[8];
3421 char intrinsic_name[64];
3422 const nir_variable *var = instr->variables[0]->var;
3423 const struct glsl_type *type = glsl_without_array(var->type);
3424 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3425 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3426 LLVMValueRef glc = i1false;
3427 bool force_glc = ctx->abi->chip_class == SI;
3428 if (force_glc)
3429 glc = i1true;
3430
3431 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3432 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3433 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, true);
3434 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3435 ctx->ac.i32_0, ""); /* vindex */
3436 params[3] = ctx->ac.i32_0; /* voffset */
3437 params[4] = glc; /* glc */
3438 params[5] = i1false; /* slc */
3439 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3440 params, 6, 0);
3441 } else {
3442 bool is_da = glsl_sampler_type_is_array(type) ||
3443 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3444 LLVMValueRef da = is_da ? i1true : i1false;
3445 LLVMValueRef slc = i1false;
3446
3447 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3448 params[1] = get_image_coords(ctx, instr); /* coords */
3449 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, true);
3450 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3451 if (HAVE_LLVM <= 0x0309) {
3452 params[4] = i1false; /* r128 */
3453 params[5] = da;
3454 params[6] = glc;
3455 params[7] = slc;
3456 } else {
3457 LLVMValueRef lwe = i1false;
3458 params[4] = glc;
3459 params[5] = slc;
3460 params[6] = lwe;
3461 params[7] = da;
3462 }
3463
3464 ac_get_image_intr_name("llvm.amdgcn.image.store",
3465 LLVMTypeOf(params[0]), /* vdata */
3466 LLVMTypeOf(params[1]), /* coords */
3467 LLVMTypeOf(params[2]), /* rsrc */
3468 intrinsic_name, sizeof(intrinsic_name));
3469
3470 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3471 params, 8, 0);
3472 }
3473
3474 }
3475
3476 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3477 const nir_intrinsic_instr *instr)
3478 {
3479 LLVMValueRef params[6];
3480 int param_count = 0;
3481 const nir_variable *var = instr->variables[0]->var;
3482
3483 const char *atomic_name;
3484 char intrinsic_name[41];
3485 const struct glsl_type *type = glsl_without_array(var->type);
3486 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3487 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3488 MAYBE_UNUSED int length;
3489
3490 switch (instr->intrinsic) {
3491 case nir_intrinsic_image_atomic_add:
3492 atomic_name = "add";
3493 break;
3494 case nir_intrinsic_image_atomic_min:
3495 atomic_name = "smin";
3496 break;
3497 case nir_intrinsic_image_atomic_max:
3498 atomic_name = "smax";
3499 break;
3500 case nir_intrinsic_image_atomic_and:
3501 atomic_name = "and";
3502 break;
3503 case nir_intrinsic_image_atomic_or:
3504 atomic_name = "or";
3505 break;
3506 case nir_intrinsic_image_atomic_xor:
3507 atomic_name = "xor";
3508 break;
3509 case nir_intrinsic_image_atomic_exchange:
3510 atomic_name = "swap";
3511 break;
3512 case nir_intrinsic_image_atomic_comp_swap:
3513 atomic_name = "cmpswap";
3514 break;
3515 default:
3516 abort();
3517 }
3518
3519 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3520 params[param_count++] = get_src(ctx, instr->src[3]);
3521 params[param_count++] = get_src(ctx, instr->src[2]);
3522
3523 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3524 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3525 true, true);
3526 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3527 ctx->ac.i32_0, ""); /* vindex */
3528 params[param_count++] = ctx->ac.i32_0; /* voffset */
3529 params[param_count++] = i1false; /* slc */
3530
3531 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3532 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3533 } else {
3534 char coords_type[8];
3535
3536 bool da = glsl_sampler_type_is_array(type) ||
3537 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3538
3539 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3540 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3541 true, true);
3542 params[param_count++] = i1false; /* r128 */
3543 params[param_count++] = da ? i1true : i1false; /* da */
3544 params[param_count++] = i1false; /* slc */
3545
3546 build_int_type_name(LLVMTypeOf(coords),
3547 coords_type, sizeof(coords_type));
3548
3549 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3550 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3551 }
3552
3553 assert(length < sizeof(intrinsic_name));
3554 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3555 }
3556
3557 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3558 const nir_intrinsic_instr *instr)
3559 {
3560 LLVMValueRef res;
3561 const nir_variable *var = instr->variables[0]->var;
3562 const struct glsl_type *type = instr->variables[0]->var->type;
3563 bool da = glsl_sampler_type_is_array(var->type) ||
3564 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3565 if(instr->variables[0]->deref.child)
3566 type = instr->variables[0]->deref.child->type;
3567
3568 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3569 return get_buffer_size(ctx,
3570 get_sampler_desc(ctx, instr->variables[0],
3571 AC_DESC_BUFFER, true, false), true);
3572
3573 struct ac_image_args args = { 0 };
3574
3575 args.da = da;
3576 args.dmask = 0xf;
3577 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3578 args.opcode = ac_image_get_resinfo;
3579 args.addr = ctx->ac.i32_0;
3580
3581 res = ac_build_image_opcode(&ctx->ac, &args);
3582
3583 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3584 glsl_sampler_type_is_array(type)) {
3585 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3586 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3587 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3588 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3589 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3590 }
3591 return res;
3592 }
3593
3594 #define NOOP_WAITCNT 0xf7f
3595 #define LGKM_CNT 0x07f
3596 #define VM_CNT 0xf70
3597
3598 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3599 unsigned simm16)
3600 {
3601 LLVMValueRef args[1] = {
3602 LLVMConstInt(ctx->i32, simm16, false),
3603 };
3604 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3605 ctx->voidt, args, 1, 0);
3606 }
3607
3608 static void emit_barrier(struct nir_to_llvm_context *ctx)
3609 {
3610 /* SI only (thanks to a hw bug workaround):
3611 * The real barrier instruction isn’t needed, because an entire patch
3612 * always fits into a single wave.
3613 */
3614 if (ctx->options->chip_class == SI &&
3615 ctx->stage == MESA_SHADER_TESS_CTRL) {
3616 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3617 return;
3618 }
3619 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3620 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3621 }
3622
3623 static void emit_discard_if(struct ac_nir_context *ctx,
3624 const nir_intrinsic_instr *instr)
3625 {
3626 LLVMValueRef cond;
3627
3628 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
3629 get_src(ctx, instr->src[0]),
3630 ctx->ac.i32_0, "");
3631
3632 cond = LLVMBuildSelect(ctx->ac.builder, cond,
3633 LLVMConstReal(ctx->ac.f32, -1.0f),
3634 ctx->ac.f32_0, "");
3635 ac_build_kill(&ctx->ac, cond);
3636 }
3637
3638 static LLVMValueRef
3639 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3640 {
3641 LLVMValueRef result;
3642 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3643 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3644 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3645
3646 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3647 }
3648
3649 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3650 const nir_intrinsic_instr *instr)
3651 {
3652 LLVMValueRef ptr, result;
3653 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3654 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3655
3656 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3657 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3658 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3659 ptr, src, src1,
3660 LLVMAtomicOrderingSequentiallyConsistent,
3661 LLVMAtomicOrderingSequentiallyConsistent,
3662 false);
3663 } else {
3664 LLVMAtomicRMWBinOp op;
3665 switch (instr->intrinsic) {
3666 case nir_intrinsic_var_atomic_add:
3667 op = LLVMAtomicRMWBinOpAdd;
3668 break;
3669 case nir_intrinsic_var_atomic_umin:
3670 op = LLVMAtomicRMWBinOpUMin;
3671 break;
3672 case nir_intrinsic_var_atomic_umax:
3673 op = LLVMAtomicRMWBinOpUMax;
3674 break;
3675 case nir_intrinsic_var_atomic_imin:
3676 op = LLVMAtomicRMWBinOpMin;
3677 break;
3678 case nir_intrinsic_var_atomic_imax:
3679 op = LLVMAtomicRMWBinOpMax;
3680 break;
3681 case nir_intrinsic_var_atomic_and:
3682 op = LLVMAtomicRMWBinOpAnd;
3683 break;
3684 case nir_intrinsic_var_atomic_or:
3685 op = LLVMAtomicRMWBinOpOr;
3686 break;
3687 case nir_intrinsic_var_atomic_xor:
3688 op = LLVMAtomicRMWBinOpXor;
3689 break;
3690 case nir_intrinsic_var_atomic_exchange:
3691 op = LLVMAtomicRMWBinOpXchg;
3692 break;
3693 default:
3694 return NULL;
3695 }
3696
3697 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(&ctx->ac, src),
3698 LLVMAtomicOrderingSequentiallyConsistent,
3699 false);
3700 }
3701 return result;
3702 }
3703
3704 #define INTERP_CENTER 0
3705 #define INTERP_CENTROID 1
3706 #define INTERP_SAMPLE 2
3707
3708 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3709 enum glsl_interp_mode interp, unsigned location)
3710 {
3711 switch (interp) {
3712 case INTERP_MODE_FLAT:
3713 default:
3714 return NULL;
3715 case INTERP_MODE_SMOOTH:
3716 case INTERP_MODE_NONE:
3717 if (location == INTERP_CENTER)
3718 return ctx->persp_center;
3719 else if (location == INTERP_CENTROID)
3720 return ctx->persp_centroid;
3721 else if (location == INTERP_SAMPLE)
3722 return ctx->persp_sample;
3723 break;
3724 case INTERP_MODE_NOPERSPECTIVE:
3725 if (location == INTERP_CENTER)
3726 return ctx->linear_center;
3727 else if (location == INTERP_CENTROID)
3728 return ctx->linear_centroid;
3729 else if (location == INTERP_SAMPLE)
3730 return ctx->linear_sample;
3731 break;
3732 }
3733 return NULL;
3734 }
3735
3736 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3737 LLVMValueRef sample_id)
3738 {
3739 LLVMValueRef result;
3740 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3741
3742 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3743 const_array(ctx->v2f32, 64), "");
3744
3745 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3746 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3747
3748 return result;
3749 }
3750
3751 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3752 {
3753 LLVMValueRef values[2];
3754
3755 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3756 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3757 return ac_build_gather_values(&ctx->ac, values, 2);
3758 }
3759
3760 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3761 const nir_intrinsic_instr *instr)
3762 {
3763 LLVMValueRef result[2];
3764 LLVMValueRef interp_param, attr_number;
3765 unsigned location;
3766 unsigned chan;
3767 LLVMValueRef src_c0, src_c1;
3768 LLVMValueRef src0;
3769 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3770 switch (instr->intrinsic) {
3771 case nir_intrinsic_interp_var_at_centroid:
3772 location = INTERP_CENTROID;
3773 break;
3774 case nir_intrinsic_interp_var_at_sample:
3775 case nir_intrinsic_interp_var_at_offset:
3776 location = INTERP_CENTER;
3777 src0 = get_src(ctx->nir, instr->src[0]);
3778 break;
3779 default:
3780 break;
3781 }
3782
3783 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3784 src_c0 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3785 src_c1 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3786 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3787 LLVMValueRef sample_position;
3788 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3789
3790 /* fetch sample ID */
3791 sample_position = load_sample_position(ctx, src0);
3792
3793 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3794 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3795 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3796 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3797 }
3798 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3799 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3800
3801 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3802 LLVMValueRef ij_out[2];
3803 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3804
3805 /*
3806 * take the I then J parameters, and the DDX/Y for it, and
3807 * calculate the IJ inputs for the interpolator.
3808 * temp1 = ddx * offset/sample.x + I;
3809 * interp_param.I = ddy * offset/sample.y + temp1;
3810 * temp1 = ddx * offset/sample.x + J;
3811 * interp_param.J = ddy * offset/sample.y + temp1;
3812 */
3813 for (unsigned i = 0; i < 2; i++) {
3814 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3815 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3816 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3817 ddxy_out, ix_ll, "");
3818 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3819 ddxy_out, iy_ll, "");
3820 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3821 interp_param, ix_ll, "");
3822 LLVMValueRef temp1, temp2;
3823
3824 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3825 ctx->f32, "");
3826
3827 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3828 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3829
3830 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3831 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3832
3833 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3834 temp2, ctx->i32, "");
3835 }
3836 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3837
3838 }
3839
3840 for (chan = 0; chan < 2; chan++) {
3841 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3842
3843 if (interp_param) {
3844 interp_param = LLVMBuildBitCast(ctx->builder,
3845 interp_param, LLVMVectorType(ctx->f32, 2), "");
3846 LLVMValueRef i = LLVMBuildExtractElement(
3847 ctx->builder, interp_param, ctx->i32zero, "");
3848 LLVMValueRef j = LLVMBuildExtractElement(
3849 ctx->builder, interp_param, ctx->i32one, "");
3850
3851 result[chan] = ac_build_fs_interp(&ctx->ac,
3852 llvm_chan, attr_number,
3853 ctx->prim_mask, i, j);
3854 } else {
3855 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3856 LLVMConstInt(ctx->i32, 2, false),
3857 llvm_chan, attr_number,
3858 ctx->prim_mask);
3859 }
3860 }
3861 return ac_build_gather_values(&ctx->ac, result, 2);
3862 }
3863
3864 static void
3865 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3866 const nir_intrinsic_instr *instr)
3867 {
3868 LLVMValueRef gs_next_vertex;
3869 LLVMValueRef can_emit, kill;
3870 int idx;
3871
3872 assert(instr->const_index[0] == 0);
3873 /* Write vertex attribute values to GSVS ring */
3874 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3875 ctx->gs_next_vertex,
3876 "");
3877
3878 /* If this thread has already emitted the declared maximum number of
3879 * vertices, kill it: excessive vertex emissions are not supposed to
3880 * have any effect, and GS threads have no externally observable
3881 * effects other than emitting vertices.
3882 */
3883 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3884 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3885
3886 kill = LLVMBuildSelect(ctx->builder, can_emit,
3887 LLVMConstReal(ctx->f32, 1.0f),
3888 LLVMConstReal(ctx->f32, -1.0f), "");
3889 ac_build_kill(&ctx->ac, kill);
3890
3891 /* loop num outputs */
3892 idx = 0;
3893 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3894 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
3895 int length = 4;
3896 int slot = idx;
3897 int slot_inc = 1;
3898
3899 if (!(ctx->output_mask & (1ull << i)))
3900 continue;
3901
3902 if (i == VARYING_SLOT_CLIP_DIST0) {
3903 /* pack clip and cull into a single set of slots */
3904 length = ctx->num_output_clips + ctx->num_output_culls;
3905 if (length > 4)
3906 slot_inc = 2;
3907 }
3908 for (unsigned j = 0; j < length; j++) {
3909 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3910 out_ptr[j], "");
3911 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3912 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3913 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3914
3915 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3916
3917 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3918 out_val, 1,
3919 voffset, ctx->gs2vs_offset, 0,
3920 1, 1, true, true);
3921 }
3922 idx += slot_inc;
3923 }
3924
3925 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3926 ctx->i32one, "");
3927 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3928
3929 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3930 }
3931
3932 static void
3933 visit_end_primitive(struct nir_to_llvm_context *ctx,
3934 const nir_intrinsic_instr *instr)
3935 {
3936 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3937 }
3938
3939 static LLVMValueRef
3940 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3941 const nir_intrinsic_instr *instr)
3942 {
3943 LLVMValueRef coord[4] = {
3944 ctx->tes_u,
3945 ctx->tes_v,
3946 ctx->f32zero,
3947 ctx->f32zero,
3948 };
3949
3950 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3951 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3952 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3953
3954 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3955 return LLVMBuildBitCast(ctx->builder, result,
3956 get_def_type(ctx->nir, &instr->dest.ssa), "");
3957 }
3958
3959 static void visit_intrinsic(struct ac_nir_context *ctx,
3960 nir_intrinsic_instr *instr)
3961 {
3962 LLVMValueRef result = NULL;
3963
3964 switch (instr->intrinsic) {
3965 case nir_intrinsic_load_work_group_id: {
3966 result = ctx->nctx->workgroup_ids;
3967 break;
3968 }
3969 case nir_intrinsic_load_base_vertex: {
3970 result = ctx->abi->base_vertex;
3971 break;
3972 }
3973 case nir_intrinsic_load_vertex_id_zero_base: {
3974 result = ctx->abi->vertex_id;
3975 break;
3976 }
3977 case nir_intrinsic_load_local_invocation_id: {
3978 result = ctx->nctx->local_invocation_ids;
3979 break;
3980 }
3981 case nir_intrinsic_load_base_instance:
3982 result = ctx->abi->start_instance;
3983 break;
3984 case nir_intrinsic_load_draw_id:
3985 result = ctx->abi->draw_id;
3986 break;
3987 case nir_intrinsic_load_invocation_id:
3988 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3989 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
3990 else
3991 result = ctx->nctx->gs_invocation_id;
3992 break;
3993 case nir_intrinsic_load_primitive_id:
3994 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3995 ctx->nctx->shader_info->gs.uses_prim_id = true;
3996 result = ctx->nctx->gs_prim_id;
3997 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3998 ctx->nctx->shader_info->tcs.uses_prim_id = true;
3999 result = ctx->nctx->tcs_patch_id;
4000 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4001 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4002 result = ctx->nctx->tes_patch_id;
4003 } else
4004 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4005 break;
4006 case nir_intrinsic_load_sample_id:
4007 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4008 break;
4009 case nir_intrinsic_load_sample_pos:
4010 result = load_sample_pos(ctx);
4011 break;
4012 case nir_intrinsic_load_sample_mask_in:
4013 result = ctx->abi->sample_coverage;
4014 break;
4015 case nir_intrinsic_load_frag_coord: {
4016 LLVMValueRef values[4] = {
4017 ctx->abi->frag_pos[0],
4018 ctx->abi->frag_pos[1],
4019 ctx->abi->frag_pos[2],
4020 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4021 };
4022 result = ac_build_gather_values(&ctx->ac, values, 4);
4023 break;
4024 }
4025 case nir_intrinsic_load_front_face:
4026 result = ctx->abi->front_face;
4027 break;
4028 case nir_intrinsic_load_instance_id:
4029 result = ctx->abi->instance_id;
4030 break;
4031 case nir_intrinsic_load_num_work_groups:
4032 result = ctx->nctx->num_work_groups;
4033 break;
4034 case nir_intrinsic_load_local_invocation_index:
4035 result = visit_load_local_invocation_index(ctx->nctx);
4036 break;
4037 case nir_intrinsic_load_push_constant:
4038 result = visit_load_push_constant(ctx->nctx, instr);
4039 break;
4040 case nir_intrinsic_vulkan_resource_index:
4041 result = visit_vulkan_resource_index(ctx->nctx, instr);
4042 break;
4043 case nir_intrinsic_store_ssbo:
4044 visit_store_ssbo(ctx, instr);
4045 break;
4046 case nir_intrinsic_load_ssbo:
4047 result = visit_load_buffer(ctx, instr);
4048 break;
4049 case nir_intrinsic_ssbo_atomic_add:
4050 case nir_intrinsic_ssbo_atomic_imin:
4051 case nir_intrinsic_ssbo_atomic_umin:
4052 case nir_intrinsic_ssbo_atomic_imax:
4053 case nir_intrinsic_ssbo_atomic_umax:
4054 case nir_intrinsic_ssbo_atomic_and:
4055 case nir_intrinsic_ssbo_atomic_or:
4056 case nir_intrinsic_ssbo_atomic_xor:
4057 case nir_intrinsic_ssbo_atomic_exchange:
4058 case nir_intrinsic_ssbo_atomic_comp_swap:
4059 result = visit_atomic_ssbo(ctx, instr);
4060 break;
4061 case nir_intrinsic_load_ubo:
4062 result = visit_load_ubo_buffer(ctx, instr);
4063 break;
4064 case nir_intrinsic_get_buffer_size:
4065 result = visit_get_buffer_size(ctx, instr);
4066 break;
4067 case nir_intrinsic_load_var:
4068 result = visit_load_var(ctx, instr);
4069 break;
4070 case nir_intrinsic_store_var:
4071 visit_store_var(ctx, instr);
4072 break;
4073 case nir_intrinsic_image_load:
4074 result = visit_image_load(ctx, instr);
4075 break;
4076 case nir_intrinsic_image_store:
4077 visit_image_store(ctx, instr);
4078 break;
4079 case nir_intrinsic_image_atomic_add:
4080 case nir_intrinsic_image_atomic_min:
4081 case nir_intrinsic_image_atomic_max:
4082 case nir_intrinsic_image_atomic_and:
4083 case nir_intrinsic_image_atomic_or:
4084 case nir_intrinsic_image_atomic_xor:
4085 case nir_intrinsic_image_atomic_exchange:
4086 case nir_intrinsic_image_atomic_comp_swap:
4087 result = visit_image_atomic(ctx, instr);
4088 break;
4089 case nir_intrinsic_image_size:
4090 result = visit_image_size(ctx, instr);
4091 break;
4092 case nir_intrinsic_discard:
4093 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4094 LLVMVoidTypeInContext(ctx->ac.context),
4095 NULL, 0, AC_FUNC_ATTR_LEGACY);
4096 break;
4097 case nir_intrinsic_discard_if:
4098 emit_discard_if(ctx, instr);
4099 break;
4100 case nir_intrinsic_memory_barrier:
4101 emit_waitcnt(ctx->nctx, VM_CNT);
4102 break;
4103 case nir_intrinsic_barrier:
4104 emit_barrier(ctx->nctx);
4105 break;
4106 case nir_intrinsic_var_atomic_add:
4107 case nir_intrinsic_var_atomic_imin:
4108 case nir_intrinsic_var_atomic_umin:
4109 case nir_intrinsic_var_atomic_imax:
4110 case nir_intrinsic_var_atomic_umax:
4111 case nir_intrinsic_var_atomic_and:
4112 case nir_intrinsic_var_atomic_or:
4113 case nir_intrinsic_var_atomic_xor:
4114 case nir_intrinsic_var_atomic_exchange:
4115 case nir_intrinsic_var_atomic_comp_swap:
4116 result = visit_var_atomic(ctx->nctx, instr);
4117 break;
4118 case nir_intrinsic_interp_var_at_centroid:
4119 case nir_intrinsic_interp_var_at_sample:
4120 case nir_intrinsic_interp_var_at_offset:
4121 result = visit_interp(ctx->nctx, instr);
4122 break;
4123 case nir_intrinsic_emit_vertex:
4124 visit_emit_vertex(ctx->nctx, instr);
4125 break;
4126 case nir_intrinsic_end_primitive:
4127 visit_end_primitive(ctx->nctx, instr);
4128 break;
4129 case nir_intrinsic_load_tess_coord:
4130 result = visit_load_tess_coord(ctx->nctx, instr);
4131 break;
4132 case nir_intrinsic_load_patch_vertices_in:
4133 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4134 break;
4135 default:
4136 fprintf(stderr, "Unknown intrinsic: ");
4137 nir_print_instr(&instr->instr, stderr);
4138 fprintf(stderr, "\n");
4139 break;
4140 }
4141 if (result) {
4142 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4143 }
4144 }
4145
4146 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4147 LLVMValueRef buffer, bool write)
4148 {
4149 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4150
4151 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4152 ctx->shader_info->fs.writes_memory = true;
4153
4154 return buffer;
4155 }
4156
4157 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4158 unsigned descriptor_set,
4159 unsigned base_index,
4160 unsigned constant_index,
4161 LLVMValueRef index,
4162 enum ac_descriptor_type desc_type,
4163 bool image, bool write)
4164 {
4165 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4166 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4167 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4168 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4169 unsigned offset = binding->offset;
4170 unsigned stride = binding->size;
4171 unsigned type_size;
4172 LLVMBuilderRef builder = ctx->builder;
4173 LLVMTypeRef type;
4174
4175 assert(base_index < layout->binding_count);
4176
4177 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4178 ctx->shader_info->fs.writes_memory = true;
4179
4180 switch (desc_type) {
4181 case AC_DESC_IMAGE:
4182 type = ctx->v8i32;
4183 type_size = 32;
4184 break;
4185 case AC_DESC_FMASK:
4186 type = ctx->v8i32;
4187 offset += 32;
4188 type_size = 32;
4189 break;
4190 case AC_DESC_SAMPLER:
4191 type = ctx->v4i32;
4192 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4193 offset += 64;
4194
4195 type_size = 16;
4196 break;
4197 case AC_DESC_BUFFER:
4198 type = ctx->v4i32;
4199 type_size = 16;
4200 break;
4201 default:
4202 unreachable("invalid desc_type\n");
4203 }
4204
4205 offset += constant_index * stride;
4206
4207 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4208 (!index || binding->immutable_samplers_equal)) {
4209 if (binding->immutable_samplers_equal)
4210 constant_index = 0;
4211
4212 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4213
4214 LLVMValueRef constants[] = {
4215 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4216 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4217 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4218 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4219 };
4220 return ac_build_gather_values(&ctx->ac, constants, 4);
4221 }
4222
4223 assert(stride % type_size == 0);
4224
4225 if (!index)
4226 index = ctx->i32zero;
4227
4228 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4229
4230 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4231 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4232
4233 return ac_build_indexed_load_const(&ctx->ac, list, index);
4234 }
4235
4236 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4237 const nir_deref_var *deref,
4238 enum ac_descriptor_type desc_type,
4239 bool image, bool write)
4240 {
4241 LLVMValueRef index = NULL;
4242 unsigned constant_index = 0;
4243 const nir_deref *tail = &deref->deref;
4244
4245 while (tail->child) {
4246 const nir_deref_array *child = nir_deref_as_array(tail->child);
4247 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4248
4249 if (!array_size)
4250 array_size = 1;
4251
4252 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4253
4254 if (child->deref_array_type == nir_deref_array_type_indirect) {
4255 LLVMValueRef indirect = get_src(ctx, child->indirect);
4256
4257 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4258 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4259
4260 if (!index)
4261 index = indirect;
4262 else
4263 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4264 }
4265
4266 constant_index += child->base_offset * array_size;
4267
4268 tail = &child->deref;
4269 }
4270
4271 return ctx->abi->load_sampler_desc(ctx->abi,
4272 deref->var->data.descriptor_set,
4273 deref->var->data.binding,
4274 constant_index, index,
4275 desc_type, image, write);
4276 }
4277
4278 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4279 struct ac_image_args *args,
4280 const nir_tex_instr *instr,
4281 nir_texop op,
4282 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4283 LLVMValueRef *param, unsigned count,
4284 unsigned dmask)
4285 {
4286 unsigned is_rect = 0;
4287 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4288
4289 if (op == nir_texop_lod)
4290 da = false;
4291 /* Pad to power of two vector */
4292 while (count < util_next_power_of_two(count))
4293 param[count++] = LLVMGetUndef(ctx->i32);
4294
4295 if (count > 1)
4296 args->addr = ac_build_gather_values(ctx, param, count);
4297 else
4298 args->addr = param[0];
4299
4300 args->resource = res_ptr;
4301 args->sampler = samp_ptr;
4302
4303 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4304 args->addr = param[0];
4305 return;
4306 }
4307
4308 args->dmask = dmask;
4309 args->unorm = is_rect;
4310 args->da = da;
4311 }
4312
4313 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4314 *
4315 * SI-CI:
4316 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4317 * filtering manually. The driver sets img7 to a mask clearing
4318 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4319 * s_and_b32 samp0, samp0, img7
4320 *
4321 * VI:
4322 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4323 */
4324 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4325 LLVMValueRef res, LLVMValueRef samp)
4326 {
4327 LLVMBuilderRef builder = ctx->ac.builder;
4328 LLVMValueRef img7, samp0;
4329
4330 if (ctx->abi->chip_class >= VI)
4331 return samp;
4332
4333 img7 = LLVMBuildExtractElement(builder, res,
4334 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4335 samp0 = LLVMBuildExtractElement(builder, samp,
4336 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4337 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4338 return LLVMBuildInsertElement(builder, samp, samp0,
4339 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4340 }
4341
4342 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4343 nir_tex_instr *instr,
4344 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4345 LLVMValueRef *fmask_ptr)
4346 {
4347 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4348 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, false, false);
4349 else
4350 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, false, false);
4351 if (samp_ptr) {
4352 if (instr->sampler)
4353 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, false, false);
4354 else
4355 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, false, false);
4356 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4357 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4358 }
4359 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4360 instr->op == nir_texop_samples_identical))
4361 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, false, false);
4362 }
4363
4364 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4365 LLVMValueRef coord)
4366 {
4367 coord = to_float(ctx, coord);
4368 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4369 coord = to_integer(ctx, coord);
4370 return coord;
4371 }
4372
4373 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4374 {
4375 LLVMValueRef result = NULL;
4376 struct ac_image_args args = { 0 };
4377 unsigned dmask = 0xf;
4378 LLVMValueRef address[16];
4379 LLVMValueRef coords[5];
4380 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4381 LLVMValueRef bias = NULL, offsets = NULL;
4382 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4383 LLVMValueRef ddx = NULL, ddy = NULL;
4384 LLVMValueRef derivs[6];
4385 unsigned chan, count = 0;
4386 unsigned const_src = 0, num_deriv_comp = 0;
4387 bool lod_is_zero = false;
4388
4389 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4390
4391 for (unsigned i = 0; i < instr->num_srcs; i++) {
4392 switch (instr->src[i].src_type) {
4393 case nir_tex_src_coord:
4394 coord = get_src(ctx, instr->src[i].src);
4395 break;
4396 case nir_tex_src_projector:
4397 break;
4398 case nir_tex_src_comparator:
4399 comparator = get_src(ctx, instr->src[i].src);
4400 break;
4401 case nir_tex_src_offset:
4402 offsets = get_src(ctx, instr->src[i].src);
4403 const_src = i;
4404 break;
4405 case nir_tex_src_bias:
4406 bias = get_src(ctx, instr->src[i].src);
4407 break;
4408 case nir_tex_src_lod: {
4409 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4410
4411 if (val && val->i32[0] == 0)
4412 lod_is_zero = true;
4413 lod = get_src(ctx, instr->src[i].src);
4414 break;
4415 }
4416 case nir_tex_src_ms_index:
4417 sample_index = get_src(ctx, instr->src[i].src);
4418 break;
4419 case nir_tex_src_ms_mcs:
4420 break;
4421 case nir_tex_src_ddx:
4422 ddx = get_src(ctx, instr->src[i].src);
4423 num_deriv_comp = instr->src[i].src.ssa->num_components;
4424 break;
4425 case nir_tex_src_ddy:
4426 ddy = get_src(ctx, instr->src[i].src);
4427 break;
4428 case nir_tex_src_texture_offset:
4429 case nir_tex_src_sampler_offset:
4430 case nir_tex_src_plane:
4431 default:
4432 break;
4433 }
4434 }
4435
4436 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4437 result = get_buffer_size(ctx, res_ptr, true);
4438 goto write_result;
4439 }
4440
4441 if (instr->op == nir_texop_texture_samples) {
4442 LLVMValueRef res, samples, is_msaa;
4443 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4444 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4445 LLVMConstInt(ctx->ac.i32, 3, false), "");
4446 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4447 LLVMConstInt(ctx->ac.i32, 28, false), "");
4448 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4449 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4450 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4451 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4452
4453 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4454 LLVMConstInt(ctx->ac.i32, 16, false), "");
4455 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4456 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4457 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4458 samples, "");
4459 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4460 ctx->ac.i32_1, "");
4461 result = samples;
4462 goto write_result;
4463 }
4464
4465 if (coord)
4466 for (chan = 0; chan < instr->coord_components; chan++)
4467 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4468
4469 if (offsets && instr->op != nir_texop_txf) {
4470 LLVMValueRef offset[3], pack;
4471 for (chan = 0; chan < 3; ++chan)
4472 offset[chan] = ctx->ac.i32_0;
4473
4474 args.offset = true;
4475 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4476 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4477 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4478 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4479 if (chan)
4480 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4481 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4482 }
4483 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4484 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4485 address[count++] = pack;
4486
4487 }
4488 /* pack LOD bias value */
4489 if (instr->op == nir_texop_txb && bias) {
4490 address[count++] = bias;
4491 }
4492
4493 /* Pack depth comparison value */
4494 if (instr->is_shadow && comparator) {
4495 LLVMValueRef z = llvm_extract_elem(&ctx->ac, comparator, 0);
4496
4497 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4498 * so the depth comparison value isn't clamped for Z16 and
4499 * Z24 anymore. Do it manually here.
4500 *
4501 * It's unnecessary if the original texture format was
4502 * Z32_FLOAT, but we don't know that here.
4503 */
4504 if (ctx->abi->chip_class == VI)
4505 z = ac_build_clamp(&ctx->ac, z);
4506
4507 address[count++] = z;
4508 }
4509
4510 /* pack derivatives */
4511 if (ddx || ddy) {
4512 switch (instr->sampler_dim) {
4513 case GLSL_SAMPLER_DIM_3D:
4514 case GLSL_SAMPLER_DIM_CUBE:
4515 num_deriv_comp = 3;
4516 break;
4517 case GLSL_SAMPLER_DIM_2D:
4518 default:
4519 num_deriv_comp = 2;
4520 break;
4521 case GLSL_SAMPLER_DIM_1D:
4522 num_deriv_comp = 1;
4523 break;
4524 }
4525
4526 for (unsigned i = 0; i < num_deriv_comp; i++) {
4527 derivs[i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4528 derivs[num_deriv_comp + i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4529 }
4530 }
4531
4532 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4533 if (instr->is_array && instr->op != nir_texop_lod)
4534 coords[3] = apply_round_slice(&ctx->ac, coords[3]);
4535 for (chan = 0; chan < instr->coord_components; chan++)
4536 coords[chan] = to_float(&ctx->ac, coords[chan]);
4537 if (instr->coord_components == 3)
4538 coords[3] = LLVMGetUndef(ctx->ac.f32);
4539 ac_prepare_cube_coords(&ctx->ac,
4540 instr->op == nir_texop_txd, instr->is_array,
4541 coords, derivs);
4542 if (num_deriv_comp)
4543 num_deriv_comp--;
4544 }
4545
4546 if (ddx || ddy) {
4547 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4548 address[count++] = derivs[i];
4549 }
4550
4551 /* Pack texture coordinates */
4552 if (coord) {
4553 address[count++] = coords[0];
4554 if (instr->coord_components > 1) {
4555 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4556 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4557 }
4558 address[count++] = coords[1];
4559 }
4560 if (instr->coord_components > 2) {
4561 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4562 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4563 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4564 instr->op != nir_texop_txf) {
4565 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4566 }
4567 address[count++] = coords[2];
4568 }
4569 }
4570
4571 /* Pack LOD */
4572 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4573 instr->op == nir_texop_txf)) {
4574 address[count++] = lod;
4575 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4576 address[count++] = sample_index;
4577 } else if(instr->op == nir_texop_txs) {
4578 count = 0;
4579 if (lod)
4580 address[count++] = lod;
4581 else
4582 address[count++] = ctx->ac.i32_0;
4583 }
4584
4585 for (chan = 0; chan < count; chan++) {
4586 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4587 address[chan], ctx->ac.i32, "");
4588 }
4589
4590 if (instr->op == nir_texop_samples_identical) {
4591 LLVMValueRef txf_address[4];
4592 struct ac_image_args txf_args = { 0 };
4593 unsigned txf_count = count;
4594 memcpy(txf_address, address, sizeof(txf_address));
4595
4596 if (!instr->is_array)
4597 txf_address[2] = ctx->ac.i32_0;
4598 txf_address[3] = ctx->ac.i32_0;
4599
4600 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4601 fmask_ptr, NULL,
4602 txf_address, txf_count, 0xf);
4603
4604 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4605
4606 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4607 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4608 goto write_result;
4609 }
4610
4611 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4612 instr->op != nir_texop_txs) {
4613 unsigned sample_chan = instr->is_array ? 3 : 2;
4614 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4615 address[0],
4616 address[1],
4617 instr->is_array ? address[2] : NULL,
4618 address[sample_chan],
4619 fmask_ptr);
4620 }
4621
4622 if (offsets && instr->op == nir_texop_txf) {
4623 nir_const_value *const_offset =
4624 nir_src_as_const_value(instr->src[const_src].src);
4625 int num_offsets = instr->src[const_src].src.ssa->num_components;
4626 assert(const_offset);
4627 num_offsets = MIN2(num_offsets, instr->coord_components);
4628 if (num_offsets > 2)
4629 address[2] = LLVMBuildAdd(ctx->ac.builder,
4630 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4631 if (num_offsets > 1)
4632 address[1] = LLVMBuildAdd(ctx->ac.builder,
4633 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4634 address[0] = LLVMBuildAdd(ctx->ac.builder,
4635 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4636
4637 }
4638
4639 /* TODO TG4 support */
4640 if (instr->op == nir_texop_tg4) {
4641 if (instr->is_shadow)
4642 dmask = 1;
4643 else
4644 dmask = 1 << instr->component;
4645 }
4646 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4647 res_ptr, samp_ptr, address, count, dmask);
4648
4649 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4650
4651 if (instr->op == nir_texop_query_levels)
4652 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4653 else if (instr->is_shadow && instr->is_new_style_shadow &&
4654 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4655 instr->op != nir_texop_tg4)
4656 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4657 else if (instr->op == nir_texop_txs &&
4658 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4659 instr->is_array) {
4660 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4661 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4662 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4663 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4664 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4665 } else if (instr->dest.ssa.num_components != 4)
4666 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4667
4668 write_result:
4669 if (result) {
4670 assert(instr->dest.is_ssa);
4671 result = to_integer(&ctx->ac, result);
4672 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4673 }
4674 }
4675
4676
4677 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4678 {
4679 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4680 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4681
4682 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4683 _mesa_hash_table_insert(ctx->phis, instr, result);
4684 }
4685
4686 static void visit_post_phi(struct ac_nir_context *ctx,
4687 nir_phi_instr *instr,
4688 LLVMValueRef llvm_phi)
4689 {
4690 nir_foreach_phi_src(src, instr) {
4691 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4692 LLVMValueRef llvm_src = get_src(ctx, src->src);
4693
4694 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4695 }
4696 }
4697
4698 static void phi_post_pass(struct ac_nir_context *ctx)
4699 {
4700 struct hash_entry *entry;
4701 hash_table_foreach(ctx->phis, entry) {
4702 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4703 (LLVMValueRef)entry->data);
4704 }
4705 }
4706
4707
4708 static void visit_ssa_undef(struct ac_nir_context *ctx,
4709 const nir_ssa_undef_instr *instr)
4710 {
4711 unsigned num_components = instr->def.num_components;
4712 LLVMValueRef undef;
4713
4714 if (num_components == 1)
4715 undef = LLVMGetUndef(ctx->ac.i32);
4716 else {
4717 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4718 }
4719 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4720 }
4721
4722 static void visit_jump(struct ac_nir_context *ctx,
4723 const nir_jump_instr *instr)
4724 {
4725 switch (instr->type) {
4726 case nir_jump_break:
4727 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4728 LLVMClearInsertionPosition(ctx->ac.builder);
4729 break;
4730 case nir_jump_continue:
4731 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4732 LLVMClearInsertionPosition(ctx->ac.builder);
4733 break;
4734 default:
4735 fprintf(stderr, "Unknown NIR jump instr: ");
4736 nir_print_instr(&instr->instr, stderr);
4737 fprintf(stderr, "\n");
4738 abort();
4739 }
4740 }
4741
4742 static void visit_cf_list(struct ac_nir_context *ctx,
4743 struct exec_list *list);
4744
4745 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4746 {
4747 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4748 nir_foreach_instr(instr, block)
4749 {
4750 switch (instr->type) {
4751 case nir_instr_type_alu:
4752 visit_alu(ctx, nir_instr_as_alu(instr));
4753 break;
4754 case nir_instr_type_load_const:
4755 visit_load_const(ctx, nir_instr_as_load_const(instr));
4756 break;
4757 case nir_instr_type_intrinsic:
4758 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4759 break;
4760 case nir_instr_type_tex:
4761 visit_tex(ctx, nir_instr_as_tex(instr));
4762 break;
4763 case nir_instr_type_phi:
4764 visit_phi(ctx, nir_instr_as_phi(instr));
4765 break;
4766 case nir_instr_type_ssa_undef:
4767 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4768 break;
4769 case nir_instr_type_jump:
4770 visit_jump(ctx, nir_instr_as_jump(instr));
4771 break;
4772 default:
4773 fprintf(stderr, "Unknown NIR instr type: ");
4774 nir_print_instr(instr, stderr);
4775 fprintf(stderr, "\n");
4776 abort();
4777 }
4778 }
4779
4780 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4781 }
4782
4783 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4784 {
4785 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4786
4787 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4788 LLVMBasicBlockRef merge_block =
4789 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4790 LLVMBasicBlockRef if_block =
4791 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4792 LLVMBasicBlockRef else_block = merge_block;
4793 if (!exec_list_is_empty(&if_stmt->else_list))
4794 else_block = LLVMAppendBasicBlockInContext(
4795 ctx->ac.context, fn, "");
4796
4797 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4798 LLVMConstInt(ctx->ac.i32, 0, false), "");
4799 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4800
4801 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4802 visit_cf_list(ctx, &if_stmt->then_list);
4803 if (LLVMGetInsertBlock(ctx->ac.builder))
4804 LLVMBuildBr(ctx->ac.builder, merge_block);
4805
4806 if (!exec_list_is_empty(&if_stmt->else_list)) {
4807 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4808 visit_cf_list(ctx, &if_stmt->else_list);
4809 if (LLVMGetInsertBlock(ctx->ac.builder))
4810 LLVMBuildBr(ctx->ac.builder, merge_block);
4811 }
4812
4813 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4814 }
4815
4816 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4817 {
4818 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4819 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4820 LLVMBasicBlockRef break_parent = ctx->break_block;
4821
4822 ctx->continue_block =
4823 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4824 ctx->break_block =
4825 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4826
4827 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4828 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4829 visit_cf_list(ctx, &loop->body);
4830
4831 if (LLVMGetInsertBlock(ctx->ac.builder))
4832 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4833 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4834
4835 ctx->continue_block = continue_parent;
4836 ctx->break_block = break_parent;
4837 }
4838
4839 static void visit_cf_list(struct ac_nir_context *ctx,
4840 struct exec_list *list)
4841 {
4842 foreach_list_typed(nir_cf_node, node, node, list)
4843 {
4844 switch (node->type) {
4845 case nir_cf_node_block:
4846 visit_block(ctx, nir_cf_node_as_block(node));
4847 break;
4848
4849 case nir_cf_node_if:
4850 visit_if(ctx, nir_cf_node_as_if(node));
4851 break;
4852
4853 case nir_cf_node_loop:
4854 visit_loop(ctx, nir_cf_node_as_loop(node));
4855 break;
4856
4857 default:
4858 assert(0);
4859 }
4860 }
4861 }
4862
4863 static void
4864 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4865 struct nir_variable *variable)
4866 {
4867 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4868 LLVMValueRef t_offset;
4869 LLVMValueRef t_list;
4870 LLVMValueRef input;
4871 LLVMValueRef buffer_index;
4872 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4873 int idx = variable->data.location;
4874 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4875
4876 variable->data.driver_location = idx * 4;
4877
4878 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4879 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
4880 ctx->abi.start_instance, "");
4881 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4882 ctx->shader_info->vs.vgpr_comp_cnt);
4883 } else
4884 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
4885 ctx->abi.base_vertex, "");
4886
4887 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4888 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4889
4890 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4891
4892 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4893 buffer_index,
4894 LLVMConstInt(ctx->i32, 0, false),
4895 true);
4896
4897 for (unsigned chan = 0; chan < 4; chan++) {
4898 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4899 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4900 to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
4901 input, llvm_chan, ""));
4902 }
4903 }
4904 }
4905
4906 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4907 unsigned attr,
4908 LLVMValueRef interp_param,
4909 LLVMValueRef prim_mask,
4910 LLVMValueRef result[4])
4911 {
4912 LLVMValueRef attr_number;
4913 unsigned chan;
4914 LLVMValueRef i, j;
4915 bool interp = interp_param != NULL;
4916
4917 attr_number = LLVMConstInt(ctx->i32, attr, false);
4918
4919 /* fs.constant returns the param from the middle vertex, so it's not
4920 * really useful for flat shading. It's meant to be used for custom
4921 * interpolation (but the intrinsic can't fetch from the other two
4922 * vertices).
4923 *
4924 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4925 * to do the right thing. The only reason we use fs.constant is that
4926 * fs.interp cannot be used on integers, because they can be equal
4927 * to NaN.
4928 */
4929 if (interp) {
4930 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4931 LLVMVectorType(ctx->f32, 2), "");
4932
4933 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4934 ctx->i32zero, "");
4935 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4936 ctx->i32one, "");
4937 }
4938
4939 for (chan = 0; chan < 4; chan++) {
4940 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4941
4942 if (interp) {
4943 result[chan] = ac_build_fs_interp(&ctx->ac,
4944 llvm_chan,
4945 attr_number,
4946 prim_mask, i, j);
4947 } else {
4948 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4949 LLVMConstInt(ctx->i32, 2, false),
4950 llvm_chan,
4951 attr_number,
4952 prim_mask);
4953 }
4954 }
4955 }
4956
4957 static void
4958 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4959 struct nir_variable *variable)
4960 {
4961 int idx = variable->data.location;
4962 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4963 LLVMValueRef interp;
4964
4965 variable->data.driver_location = idx * 4;
4966 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4967
4968 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4969 unsigned interp_type;
4970 if (variable->data.sample) {
4971 interp_type = INTERP_SAMPLE;
4972 ctx->shader_info->info.ps.force_persample = true;
4973 } else if (variable->data.centroid)
4974 interp_type = INTERP_CENTROID;
4975 else
4976 interp_type = INTERP_CENTER;
4977
4978 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4979 } else
4980 interp = NULL;
4981
4982 for (unsigned i = 0; i < attrib_count; ++i)
4983 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4984
4985 }
4986
4987 static void
4988 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4989 struct nir_variable *variable)
4990 {
4991 switch (ctx->stage) {
4992 case MESA_SHADER_VERTEX:
4993 handle_vs_input_decl(ctx, variable);
4994 break;
4995 case MESA_SHADER_FRAGMENT:
4996 handle_fs_input_decl(ctx, variable);
4997 break;
4998 default:
4999 break;
5000 }
5001
5002 }
5003
5004 static void
5005 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
5006 struct nir_shader *nir)
5007 {
5008 unsigned index = 0;
5009 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5010 LLVMValueRef interp_param;
5011 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5012
5013 if (!(ctx->input_mask & (1ull << i)))
5014 continue;
5015
5016 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5017 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5018 interp_param = *inputs;
5019 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5020 inputs);
5021
5022 if (!interp_param)
5023 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5024 ++index;
5025 } else if (i == VARYING_SLOT_POS) {
5026 for(int i = 0; i < 3; ++i)
5027 inputs[i] = ctx->abi.frag_pos[i];
5028
5029 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one,
5030 ctx->abi.frag_pos[3]);
5031 }
5032 }
5033 ctx->shader_info->fs.num_interp = index;
5034 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5035 ctx->shader_info->fs.has_pcoord = true;
5036 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5037 ctx->shader_info->fs.prim_id_input = true;
5038 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5039 ctx->shader_info->fs.layer_input = true;
5040 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5041 }
5042
5043 static LLVMValueRef
5044 ac_build_alloca(struct ac_llvm_context *ac,
5045 LLVMTypeRef type,
5046 const char *name)
5047 {
5048 LLVMBuilderRef builder = ac->builder;
5049 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5050 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5051 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5052 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5053 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5054 LLVMValueRef res;
5055
5056 if (first_instr) {
5057 LLVMPositionBuilderBefore(first_builder, first_instr);
5058 } else {
5059 LLVMPositionBuilderAtEnd(first_builder, first_block);
5060 }
5061
5062 res = LLVMBuildAlloca(first_builder, type, name);
5063 LLVMBuildStore(builder, LLVMConstNull(type), res);
5064
5065 LLVMDisposeBuilder(first_builder);
5066
5067 return res;
5068 }
5069
5070 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5071 LLVMTypeRef type,
5072 const char *name)
5073 {
5074 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5075 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5076 return ptr;
5077 }
5078
5079 static void
5080 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5081 struct nir_variable *variable)
5082 {
5083 int idx = variable->data.location + variable->data.index;
5084 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5085 uint64_t mask_attribs;
5086
5087 variable->data.driver_location = idx * 4;
5088
5089 /* tess ctrl has it's own load/store paths for outputs */
5090 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5091 return;
5092
5093 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5094 if (ctx->stage == MESA_SHADER_VERTEX ||
5095 ctx->stage == MESA_SHADER_TESS_EVAL ||
5096 ctx->stage == MESA_SHADER_GEOMETRY) {
5097 if (idx == VARYING_SLOT_CLIP_DIST0) {
5098 int length = ctx->num_output_clips + ctx->num_output_culls;
5099 if (ctx->stage == MESA_SHADER_VERTEX) {
5100 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5101 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5102 }
5103 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5104 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5105 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5106 }
5107
5108 if (length > 4)
5109 attrib_count = 2;
5110 else
5111 attrib_count = 1;
5112 mask_attribs = 1ull << idx;
5113 }
5114 }
5115
5116 ctx->output_mask |= mask_attribs;
5117 }
5118
5119 static void
5120 handle_shader_output_decl(struct ac_nir_context *ctx,
5121 struct nir_shader *nir,
5122 struct nir_variable *variable)
5123 {
5124 unsigned output_loc = variable->data.driver_location / 4;
5125 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5126
5127 /* tess ctrl has it's own load/store paths for outputs */
5128 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5129 return;
5130
5131 if (ctx->stage == MESA_SHADER_VERTEX ||
5132 ctx->stage == MESA_SHADER_TESS_EVAL ||
5133 ctx->stage == MESA_SHADER_GEOMETRY) {
5134 int idx = variable->data.location + variable->data.index;
5135 if (idx == VARYING_SLOT_CLIP_DIST0) {
5136 int length = nir->info.clip_distance_array_size +
5137 nir->info.cull_distance_array_size;
5138
5139 if (length > 4)
5140 attrib_count = 2;
5141 else
5142 attrib_count = 1;
5143 }
5144 }
5145
5146 for (unsigned i = 0; i < attrib_count; ++i) {
5147 for (unsigned chan = 0; chan < 4; chan++) {
5148 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5149 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5150 }
5151 }
5152 }
5153
5154 static LLVMTypeRef
5155 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5156 enum glsl_base_type type)
5157 {
5158 switch (type) {
5159 case GLSL_TYPE_INT:
5160 case GLSL_TYPE_UINT:
5161 case GLSL_TYPE_BOOL:
5162 case GLSL_TYPE_SUBROUTINE:
5163 return ctx->i32;
5164 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5165 return ctx->f32;
5166 case GLSL_TYPE_INT64:
5167 case GLSL_TYPE_UINT64:
5168 return ctx->i64;
5169 case GLSL_TYPE_DOUBLE:
5170 return ctx->f64;
5171 default:
5172 unreachable("unknown GLSL type");
5173 }
5174 }
5175
5176 static LLVMTypeRef
5177 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5178 const struct glsl_type *type)
5179 {
5180 if (glsl_type_is_scalar(type)) {
5181 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5182 }
5183
5184 if (glsl_type_is_vector(type)) {
5185 return LLVMVectorType(
5186 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5187 glsl_get_vector_elements(type));
5188 }
5189
5190 if (glsl_type_is_matrix(type)) {
5191 return LLVMArrayType(
5192 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5193 glsl_get_matrix_columns(type));
5194 }
5195
5196 if (glsl_type_is_array(type)) {
5197 return LLVMArrayType(
5198 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5199 glsl_get_length(type));
5200 }
5201
5202 assert(glsl_type_is_struct(type));
5203
5204 LLVMTypeRef member_types[glsl_get_length(type)];
5205
5206 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5207 member_types[i] =
5208 glsl_to_llvm_type(ctx,
5209 glsl_get_struct_field(type, i));
5210 }
5211
5212 return LLVMStructTypeInContext(ctx->context, member_types,
5213 glsl_get_length(type), false);
5214 }
5215
5216 static void
5217 setup_locals(struct ac_nir_context *ctx,
5218 struct nir_function *func)
5219 {
5220 int i, j;
5221 ctx->num_locals = 0;
5222 nir_foreach_variable(variable, &func->impl->locals) {
5223 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5224 variable->data.driver_location = ctx->num_locals * 4;
5225 ctx->num_locals += attrib_count;
5226 }
5227 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5228 if (!ctx->locals)
5229 return;
5230
5231 for (i = 0; i < ctx->num_locals; i++) {
5232 for (j = 0; j < 4; j++) {
5233 ctx->locals[i * 4 + j] =
5234 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5235 }
5236 }
5237 }
5238
5239 static void
5240 setup_shared(struct ac_nir_context *ctx,
5241 struct nir_shader *nir)
5242 {
5243 nir_foreach_variable(variable, &nir->shared) {
5244 LLVMValueRef shared =
5245 LLVMAddGlobalInAddressSpace(
5246 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5247 variable->name ? variable->name : "",
5248 LOCAL_ADDR_SPACE);
5249 _mesa_hash_table_insert(ctx->vars, variable, shared);
5250 }
5251 }
5252
5253 static LLVMValueRef
5254 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5255 {
5256 v = to_float(ctx, v);
5257 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5258 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5259 }
5260
5261
5262 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5263 LLVMValueRef src0, LLVMValueRef src1)
5264 {
5265 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5266 LLVMValueRef comp[2];
5267
5268 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5269 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5270 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5271 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5272 }
5273
5274 /* Initialize arguments for the shader export intrinsic */
5275 static void
5276 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5277 LLVMValueRef *values,
5278 unsigned target,
5279 struct ac_export_args *args)
5280 {
5281 /* Default is 0xf. Adjusted below depending on the format. */
5282 args->enabled_channels = 0xf;
5283
5284 /* Specify whether the EXEC mask represents the valid mask */
5285 args->valid_mask = 0;
5286
5287 /* Specify whether this is the last export */
5288 args->done = 0;
5289
5290 /* Specify the target we are exporting */
5291 args->target = target;
5292
5293 args->compr = false;
5294 args->out[0] = LLVMGetUndef(ctx->f32);
5295 args->out[1] = LLVMGetUndef(ctx->f32);
5296 args->out[2] = LLVMGetUndef(ctx->f32);
5297 args->out[3] = LLVMGetUndef(ctx->f32);
5298
5299 if (!values)
5300 return;
5301
5302 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5303 LLVMValueRef val[4];
5304 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5305 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5306 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5307 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5308
5309 switch(col_format) {
5310 case V_028714_SPI_SHADER_ZERO:
5311 args->enabled_channels = 0; /* writemask */
5312 args->target = V_008DFC_SQ_EXP_NULL;
5313 break;
5314
5315 case V_028714_SPI_SHADER_32_R:
5316 args->enabled_channels = 1;
5317 args->out[0] = values[0];
5318 break;
5319
5320 case V_028714_SPI_SHADER_32_GR:
5321 args->enabled_channels = 0x3;
5322 args->out[0] = values[0];
5323 args->out[1] = values[1];
5324 break;
5325
5326 case V_028714_SPI_SHADER_32_AR:
5327 args->enabled_channels = 0x9;
5328 args->out[0] = values[0];
5329 args->out[3] = values[3];
5330 break;
5331
5332 case V_028714_SPI_SHADER_FP16_ABGR:
5333 args->compr = 1;
5334
5335 for (unsigned chan = 0; chan < 2; chan++) {
5336 LLVMValueRef pack_args[2] = {
5337 values[2 * chan],
5338 values[2 * chan + 1]
5339 };
5340 LLVMValueRef packed;
5341
5342 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5343 args->out[chan] = packed;
5344 }
5345 break;
5346
5347 case V_028714_SPI_SHADER_UNORM16_ABGR:
5348 for (unsigned chan = 0; chan < 4; chan++) {
5349 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5350 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5351 LLVMConstReal(ctx->f32, 65535), "");
5352 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5353 LLVMConstReal(ctx->f32, 0.5), "");
5354 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5355 ctx->i32, "");
5356 }
5357
5358 args->compr = 1;
5359 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5360 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5361 break;
5362
5363 case V_028714_SPI_SHADER_SNORM16_ABGR:
5364 for (unsigned chan = 0; chan < 4; chan++) {
5365 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5366 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5367 LLVMConstReal(ctx->f32, 32767), "");
5368
5369 /* If positive, add 0.5, else add -0.5. */
5370 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5371 LLVMBuildSelect(ctx->builder,
5372 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5373 val[chan], ctx->f32zero, ""),
5374 LLVMConstReal(ctx->f32, 0.5),
5375 LLVMConstReal(ctx->f32, -0.5), ""), "");
5376 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5377 }
5378
5379 args->compr = 1;
5380 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5381 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5382 break;
5383
5384 case V_028714_SPI_SHADER_UINT16_ABGR: {
5385 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5386 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5387 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
5388
5389 for (unsigned chan = 0; chan < 4; chan++) {
5390 val[chan] = to_integer(&ctx->ac, values[chan]);
5391 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5392 }
5393
5394 args->compr = 1;
5395 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5396 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5397 break;
5398 }
5399
5400 case V_028714_SPI_SHADER_SINT16_ABGR: {
5401 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5402 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5403 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
5404 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5405 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->i32one;
5406 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
5407
5408 /* Clamp. */
5409 for (unsigned chan = 0; chan < 4; chan++) {
5410 val[chan] = to_integer(&ctx->ac, values[chan]);
5411 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5412 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5413 }
5414
5415 args->compr = 1;
5416 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5417 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5418 break;
5419 }
5420
5421 default:
5422 case V_028714_SPI_SHADER_32_ABGR:
5423 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5424 break;
5425 }
5426 } else
5427 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5428
5429 for (unsigned i = 0; i < 4; ++i)
5430 args->out[i] = to_float(&ctx->ac, args->out[i]);
5431 }
5432
5433 static void
5434 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5435 bool export_prim_id,
5436 struct ac_vs_output_info *outinfo)
5437 {
5438 uint32_t param_count = 0;
5439 unsigned target;
5440 unsigned pos_idx, num_pos_exports = 0;
5441 struct ac_export_args args, pos_args[4] = {};
5442 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5443 int i;
5444
5445 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5446 sizeof(outinfo->vs_output_param_offset));
5447
5448 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5449 LLVMValueRef slots[8];
5450 unsigned j;
5451
5452 if (outinfo->cull_dist_mask)
5453 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5454
5455 i = VARYING_SLOT_CLIP_DIST0;
5456 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5457 slots[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5458 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5459
5460 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5461 slots[i] = LLVMGetUndef(ctx->f32);
5462
5463 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5464 target = V_008DFC_SQ_EXP_POS + 3;
5465 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5466 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5467 &args, sizeof(args));
5468 }
5469
5470 target = V_008DFC_SQ_EXP_POS + 2;
5471 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5472 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5473 &args, sizeof(args));
5474
5475 }
5476
5477 LLVMValueRef pos_values[4] = {ctx->f32zero, ctx->f32zero, ctx->f32zero, ctx->f32one};
5478 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5479 for (unsigned j = 0; j < 4; j++)
5480 pos_values[j] = LLVMBuildLoad(ctx->builder,
5481 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5482 }
5483 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5484
5485 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5486 outinfo->writes_pointsize = true;
5487 psize_value = LLVMBuildLoad(ctx->builder,
5488 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5489 }
5490
5491 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5492 outinfo->writes_layer = true;
5493 layer_value = LLVMBuildLoad(ctx->builder,
5494 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5495 }
5496
5497 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5498 outinfo->writes_viewport_index = true;
5499 viewport_index_value = LLVMBuildLoad(ctx->builder,
5500 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5501 }
5502
5503 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5504 (outinfo->writes_layer == true ? 4 : 0) |
5505 (outinfo->writes_viewport_index == true ? 8 : 0));
5506 if (mask) {
5507 pos_args[1].enabled_channels = mask;
5508 pos_args[1].valid_mask = 0;
5509 pos_args[1].done = 0;
5510 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5511 pos_args[1].compr = 0;
5512 pos_args[1].out[0] = ctx->f32zero; /* X */
5513 pos_args[1].out[1] = ctx->f32zero; /* Y */
5514 pos_args[1].out[2] = ctx->f32zero; /* Z */
5515 pos_args[1].out[3] = ctx->f32zero; /* W */
5516
5517 if (outinfo->writes_pointsize == true)
5518 pos_args[1].out[0] = psize_value;
5519 if (outinfo->writes_layer == true)
5520 pos_args[1].out[2] = layer_value;
5521 if (outinfo->writes_viewport_index == true)
5522 pos_args[1].out[3] = viewport_index_value;
5523 }
5524 for (i = 0; i < 4; i++) {
5525 if (pos_args[i].out[0])
5526 num_pos_exports++;
5527 }
5528
5529 pos_idx = 0;
5530 for (i = 0; i < 4; i++) {
5531 if (!pos_args[i].out[0])
5532 continue;
5533
5534 /* Specify the target we are exporting */
5535 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5536 if (pos_idx == num_pos_exports)
5537 pos_args[i].done = 1;
5538 ac_build_export(&ctx->ac, &pos_args[i]);
5539 }
5540
5541 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5542 LLVMValueRef values[4];
5543 if (!(ctx->output_mask & (1ull << i)))
5544 continue;
5545
5546 for (unsigned j = 0; j < 4; j++)
5547 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5548 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5549
5550 if (i == VARYING_SLOT_LAYER) {
5551 target = V_008DFC_SQ_EXP_PARAM + param_count;
5552 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5553 param_count++;
5554 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5555 target = V_008DFC_SQ_EXP_PARAM + param_count;
5556 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5557 param_count++;
5558 } else if (i >= VARYING_SLOT_VAR0) {
5559 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5560 target = V_008DFC_SQ_EXP_PARAM + param_count;
5561 outinfo->vs_output_param_offset[i] = param_count;
5562 param_count++;
5563 } else
5564 continue;
5565
5566 si_llvm_init_export_args(ctx, values, target, &args);
5567
5568 if (target >= V_008DFC_SQ_EXP_POS &&
5569 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5570 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5571 &args, sizeof(args));
5572 } else {
5573 ac_build_export(&ctx->ac, &args);
5574 }
5575 }
5576
5577 if (export_prim_id) {
5578 LLVMValueRef values[4];
5579 target = V_008DFC_SQ_EXP_PARAM + param_count;
5580 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5581 param_count++;
5582
5583 values[0] = ctx->vs_prim_id;
5584 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5585 ctx->shader_info->vs.vgpr_comp_cnt);
5586 for (unsigned j = 1; j < 4; j++)
5587 values[j] = ctx->f32zero;
5588 si_llvm_init_export_args(ctx, values, target, &args);
5589 ac_build_export(&ctx->ac, &args);
5590 outinfo->export_prim_id = true;
5591 }
5592
5593 outinfo->pos_exports = num_pos_exports;
5594 outinfo->param_exports = param_count;
5595 }
5596
5597 static void
5598 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5599 struct ac_es_output_info *outinfo)
5600 {
5601 int j;
5602 uint64_t max_output_written = 0;
5603 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5604 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5605 int param_index;
5606 int length = 4;
5607
5608 if (!(ctx->output_mask & (1ull << i)))
5609 continue;
5610
5611 if (i == VARYING_SLOT_CLIP_DIST0)
5612 length = ctx->num_output_clips + ctx->num_output_culls;
5613
5614 param_index = shader_io_get_unique_index(i);
5615
5616 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5617
5618 for (j = 0; j < length; j++) {
5619 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5620 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5621
5622 ac_build_buffer_store_dword(&ctx->ac,
5623 ctx->esgs_ring,
5624 out_val, 1,
5625 NULL, ctx->es2gs_offset,
5626 (4 * param_index + j) * 4,
5627 1, 1, true, true);
5628 }
5629 }
5630 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5631 }
5632
5633 static void
5634 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5635 {
5636 LLVMValueRef vertex_id = ctx->rel_auto_id;
5637 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5638 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5639 vertex_dw_stride, "");
5640
5641 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5642 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5643 int length = 4;
5644
5645 if (!(ctx->output_mask & (1ull << i)))
5646 continue;
5647
5648 if (i == VARYING_SLOT_CLIP_DIST0)
5649 length = ctx->num_output_clips + ctx->num_output_culls;
5650 int param = shader_io_get_unique_index(i);
5651 mark_tess_output(ctx, false, param);
5652 if (length > 4)
5653 mark_tess_output(ctx, false, param + 1);
5654 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5655 LLVMConstInt(ctx->i32, param * 4, false),
5656 "");
5657 for (unsigned j = 0; j < length; j++) {
5658 lds_store(ctx, dw_addr,
5659 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5660 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5661 }
5662 }
5663 }
5664
5665 struct ac_build_if_state
5666 {
5667 struct nir_to_llvm_context *ctx;
5668 LLVMValueRef condition;
5669 LLVMBasicBlockRef entry_block;
5670 LLVMBasicBlockRef true_block;
5671 LLVMBasicBlockRef false_block;
5672 LLVMBasicBlockRef merge_block;
5673 };
5674
5675 static LLVMBasicBlockRef
5676 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5677 {
5678 LLVMBasicBlockRef current_block;
5679 LLVMBasicBlockRef next_block;
5680 LLVMBasicBlockRef new_block;
5681
5682 /* get current basic block */
5683 current_block = LLVMGetInsertBlock(ctx->builder);
5684
5685 /* chqeck if there's another block after this one */
5686 next_block = LLVMGetNextBasicBlock(current_block);
5687 if (next_block) {
5688 /* insert the new block before the next block */
5689 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5690 }
5691 else {
5692 /* append new block after current block */
5693 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5694 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5695 }
5696 return new_block;
5697 }
5698
5699 static void
5700 ac_nir_build_if(struct ac_build_if_state *ifthen,
5701 struct nir_to_llvm_context *ctx,
5702 LLVMValueRef condition)
5703 {
5704 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5705
5706 memset(ifthen, 0, sizeof *ifthen);
5707 ifthen->ctx = ctx;
5708 ifthen->condition = condition;
5709 ifthen->entry_block = block;
5710
5711 /* create endif/merge basic block for the phi functions */
5712 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5713
5714 /* create/insert true_block before merge_block */
5715 ifthen->true_block =
5716 LLVMInsertBasicBlockInContext(ctx->context,
5717 ifthen->merge_block,
5718 "if-true-block");
5719
5720 /* successive code goes into the true block */
5721 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5722 }
5723
5724 /**
5725 * End a conditional.
5726 */
5727 static void
5728 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5729 {
5730 LLVMBuilderRef builder = ifthen->ctx->builder;
5731
5732 /* Insert branch to the merge block from current block */
5733 LLVMBuildBr(builder, ifthen->merge_block);
5734
5735 /*
5736 * Now patch in the various branch instructions.
5737 */
5738
5739 /* Insert the conditional branch instruction at the end of entry_block */
5740 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5741 if (ifthen->false_block) {
5742 /* we have an else clause */
5743 LLVMBuildCondBr(builder, ifthen->condition,
5744 ifthen->true_block, ifthen->false_block);
5745 }
5746 else {
5747 /* no else clause */
5748 LLVMBuildCondBr(builder, ifthen->condition,
5749 ifthen->true_block, ifthen->merge_block);
5750 }
5751
5752 /* Resume building code at end of the ifthen->merge_block */
5753 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5754 }
5755
5756 static void
5757 write_tess_factors(struct nir_to_llvm_context *ctx)
5758 {
5759 unsigned stride, outer_comps, inner_comps;
5760 struct ac_build_if_state if_ctx, inner_if_ctx;
5761 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
5762 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
5763 unsigned tess_inner_index, tess_outer_index;
5764 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5765 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5766 int i;
5767 emit_barrier(ctx);
5768
5769 switch (ctx->options->key.tcs.primitive_mode) {
5770 case GL_ISOLINES:
5771 stride = 2;
5772 outer_comps = 2;
5773 inner_comps = 0;
5774 break;
5775 case GL_TRIANGLES:
5776 stride = 4;
5777 outer_comps = 3;
5778 inner_comps = 1;
5779 break;
5780 case GL_QUADS:
5781 stride = 6;
5782 outer_comps = 4;
5783 inner_comps = 2;
5784 break;
5785 default:
5786 return;
5787 }
5788
5789 ac_nir_build_if(&if_ctx, ctx,
5790 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5791 invocation_id, ctx->i32zero, ""));
5792
5793 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5794 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5795
5796 mark_tess_output(ctx, true, tess_inner_index);
5797 mark_tess_output(ctx, true, tess_outer_index);
5798 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5799 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5800 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5801 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5802 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5803
5804 for (i = 0; i < 4; i++) {
5805 inner[i] = LLVMGetUndef(ctx->i32);
5806 outer[i] = LLVMGetUndef(ctx->i32);
5807 }
5808
5809 // LINES reverseal
5810 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5811 outer[0] = out[1] = lds_load(ctx, lds_outer);
5812 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5813 LLVMConstInt(ctx->i32, 1, false), "");
5814 outer[1] = out[0] = lds_load(ctx, lds_outer);
5815 } else {
5816 for (i = 0; i < outer_comps; i++) {
5817 outer[i] = out[i] =
5818 lds_load(ctx, lds_outer);
5819 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5820 LLVMConstInt(ctx->i32, 1, false), "");
5821 }
5822 for (i = 0; i < inner_comps; i++) {
5823 inner[i] = out[outer_comps+i] =
5824 lds_load(ctx, lds_inner);
5825 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5826 LLVMConstInt(ctx->i32, 1, false), "");
5827 }
5828 }
5829
5830 /* Convert the outputs to vectors for stores. */
5831 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5832 vec1 = NULL;
5833
5834 if (stride > 4)
5835 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5836
5837
5838 buffer = ctx->hs_ring_tess_factor;
5839 tf_base = ctx->tess_factor_offset;
5840 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5841 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5842
5843 ac_nir_build_if(&inner_if_ctx, ctx,
5844 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5845 rel_patch_id, ctx->i32zero, ""));
5846
5847 /* Store the dynamic HS control word. */
5848 ac_build_buffer_store_dword(&ctx->ac, buffer,
5849 LLVMConstInt(ctx->i32, 0x80000000, false),
5850 1, ctx->i32zero, tf_base,
5851 0, 1, 0, true, false);
5852 ac_nir_build_endif(&inner_if_ctx);
5853
5854 /* Store the tessellation factors. */
5855 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5856 MIN2(stride, 4), byteoffset, tf_base,
5857 4, 1, 0, true, false);
5858 if (vec1)
5859 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5860 stride - 4, byteoffset, tf_base,
5861 20, 1, 0, true, false);
5862
5863 //TODO store to offchip for TES to read - only if TES reads them
5864 if (1) {
5865 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5866 LLVMValueRef tf_inner_offset;
5867 unsigned param_outer, param_inner;
5868
5869 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5870 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5871 LLVMConstInt(ctx->i32, param_outer, 0));
5872
5873 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5874 util_next_power_of_two(outer_comps));
5875
5876 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5877 outer_comps, tf_outer_offset,
5878 ctx->oc_lds, 0, 1, 0, true, false);
5879 if (inner_comps) {
5880 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5881 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5882 LLVMConstInt(ctx->i32, param_inner, 0));
5883
5884 inner_vec = inner_comps == 1 ? inner[0] :
5885 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5886 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5887 inner_comps, tf_inner_offset,
5888 ctx->oc_lds, 0, 1, 0, true, false);
5889 }
5890 }
5891 ac_nir_build_endif(&if_ctx);
5892 }
5893
5894 static void
5895 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5896 {
5897 write_tess_factors(ctx);
5898 }
5899
5900 static bool
5901 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5902 LLVMValueRef *color, unsigned param, bool is_last,
5903 struct ac_export_args *args)
5904 {
5905 /* Export */
5906 si_llvm_init_export_args(ctx, color, param,
5907 args);
5908
5909 if (is_last) {
5910 args->valid_mask = 1; /* whether the EXEC mask is valid */
5911 args->done = 1; /* DONE bit */
5912 } else if (!args->enabled_channels)
5913 return false; /* unnecessary NULL export */
5914
5915 return true;
5916 }
5917
5918 static void
5919 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5920 LLVMValueRef depth, LLVMValueRef stencil,
5921 LLVMValueRef samplemask)
5922 {
5923 struct ac_export_args args;
5924
5925 args.enabled_channels = 0;
5926 args.valid_mask = 1;
5927 args.done = 1;
5928 args.target = V_008DFC_SQ_EXP_MRTZ;
5929 args.compr = false;
5930
5931 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5932 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5933 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5934 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5935
5936 if (depth) {
5937 args.out[0] = depth;
5938 args.enabled_channels |= 0x1;
5939 }
5940
5941 if (stencil) {
5942 args.out[1] = stencil;
5943 args.enabled_channels |= 0x2;
5944 }
5945
5946 if (samplemask) {
5947 args.out[2] = samplemask;
5948 args.enabled_channels |= 0x4;
5949 }
5950
5951 /* SI (except OLAND and HAINAN) has a bug that it only looks
5952 * at the X writemask component. */
5953 if (ctx->options->chip_class == SI &&
5954 ctx->options->family != CHIP_OLAND &&
5955 ctx->options->family != CHIP_HAINAN)
5956 args.enabled_channels |= 0x1;
5957
5958 ac_build_export(&ctx->ac, &args);
5959 }
5960
5961 static void
5962 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5963 {
5964 unsigned index = 0;
5965 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5966 struct ac_export_args color_args[8];
5967
5968 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5969 LLVMValueRef values[4];
5970
5971 if (!(ctx->output_mask & (1ull << i)))
5972 continue;
5973
5974 if (i == FRAG_RESULT_DEPTH) {
5975 ctx->shader_info->fs.writes_z = true;
5976 depth = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5977 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5978 } else if (i == FRAG_RESULT_STENCIL) {
5979 ctx->shader_info->fs.writes_stencil = true;
5980 stencil = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5981 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5982 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5983 ctx->shader_info->fs.writes_sample_mask = true;
5984 samplemask = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5985 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5986 } else {
5987 bool last = false;
5988 for (unsigned j = 0; j < 4; j++)
5989 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5990 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5991
5992 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5993 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5994
5995 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
5996 if (ret)
5997 index++;
5998 }
5999 }
6000
6001 for (unsigned i = 0; i < index; i++)
6002 ac_build_export(&ctx->ac, &color_args[i]);
6003 if (depth || stencil || samplemask)
6004 si_export_mrt_z(ctx, depth, stencil, samplemask);
6005 else if (!index) {
6006 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6007 ac_build_export(&ctx->ac, &color_args[0]);
6008 }
6009
6010 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6011 }
6012
6013 static void
6014 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6015 {
6016 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6017 }
6018
6019 static void
6020 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6021 LLVMValueRef *addrs)
6022 {
6023 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6024
6025 switch (ctx->stage) {
6026 case MESA_SHADER_VERTEX:
6027 if (ctx->options->key.vs.as_ls)
6028 handle_ls_outputs_post(ctx);
6029 else if (ctx->options->key.vs.as_es)
6030 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6031 else
6032 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6033 &ctx->shader_info->vs.outinfo);
6034 break;
6035 case MESA_SHADER_FRAGMENT:
6036 handle_fs_outputs_post(ctx);
6037 break;
6038 case MESA_SHADER_GEOMETRY:
6039 emit_gs_epilogue(ctx);
6040 break;
6041 case MESA_SHADER_TESS_CTRL:
6042 handle_tcs_outputs_post(ctx);
6043 break;
6044 case MESA_SHADER_TESS_EVAL:
6045 if (ctx->options->key.tes.as_es)
6046 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6047 else
6048 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6049 &ctx->shader_info->tes.outinfo);
6050 break;
6051 default:
6052 break;
6053 }
6054 }
6055
6056 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6057 {
6058 LLVMPassManagerRef passmgr;
6059 /* Create the pass manager */
6060 passmgr = LLVMCreateFunctionPassManagerForModule(
6061 ctx->module);
6062
6063 /* This pass should eliminate all the load and store instructions */
6064 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6065
6066 /* Add some optimization passes */
6067 LLVMAddScalarReplAggregatesPass(passmgr);
6068 LLVMAddLICMPass(passmgr);
6069 LLVMAddAggressiveDCEPass(passmgr);
6070 LLVMAddCFGSimplificationPass(passmgr);
6071 LLVMAddInstructionCombiningPass(passmgr);
6072
6073 /* Run the pass */
6074 LLVMInitializeFunctionPassManager(passmgr);
6075 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6076 LLVMFinalizeFunctionPassManager(passmgr);
6077
6078 LLVMDisposeBuilder(ctx->builder);
6079 LLVMDisposePassManager(passmgr);
6080 }
6081
6082 static void
6083 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6084 {
6085 struct ac_vs_output_info *outinfo;
6086
6087 switch (ctx->stage) {
6088 case MESA_SHADER_FRAGMENT:
6089 case MESA_SHADER_COMPUTE:
6090 case MESA_SHADER_TESS_CTRL:
6091 case MESA_SHADER_GEOMETRY:
6092 return;
6093 case MESA_SHADER_VERTEX:
6094 if (ctx->options->key.vs.as_ls ||
6095 ctx->options->key.vs.as_es)
6096 return;
6097 outinfo = &ctx->shader_info->vs.outinfo;
6098 break;
6099 case MESA_SHADER_TESS_EVAL:
6100 if (ctx->options->key.vs.as_es)
6101 return;
6102 outinfo = &ctx->shader_info->tes.outinfo;
6103 break;
6104 default:
6105 unreachable("Unhandled shader type");
6106 }
6107
6108 ac_optimize_vs_outputs(&ctx->ac,
6109 ctx->main_function,
6110 outinfo->vs_output_param_offset,
6111 VARYING_SLOT_MAX,
6112 &outinfo->param_exports);
6113 }
6114
6115 static void
6116 ac_setup_rings(struct nir_to_llvm_context *ctx)
6117 {
6118 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6119 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6120 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
6121 }
6122
6123 if (ctx->is_gs_copy_shader) {
6124 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
6125 }
6126 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6127 LLVMValueRef tmp;
6128 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
6129 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
6130
6131 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6132
6133 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
6134 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
6135 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6136 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
6137 }
6138
6139 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6140 ctx->stage == MESA_SHADER_TESS_EVAL) {
6141 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6142 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6143 }
6144 }
6145
6146 static unsigned
6147 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6148 const struct nir_shader *nir)
6149 {
6150 switch (nir->stage) {
6151 case MESA_SHADER_TESS_CTRL:
6152 return chip_class >= CIK ? 128 : 64;
6153 case MESA_SHADER_GEOMETRY:
6154 return 64;
6155 case MESA_SHADER_COMPUTE:
6156 break;
6157 default:
6158 return 0;
6159 }
6160
6161 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6162 nir->info.cs.local_size[1] *
6163 nir->info.cs.local_size[2];
6164 return max_workgroup_size;
6165 }
6166
6167 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6168 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6169 {
6170 struct ac_nir_context ctx = {};
6171 struct nir_function *func;
6172
6173 ctx.ac = *ac;
6174 ctx.abi = abi;
6175
6176 ctx.nctx = nctx;
6177 if (nctx)
6178 nctx->nir = &ctx;
6179
6180 ctx.stage = nir->stage;
6181
6182 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6183
6184 nir_foreach_variable(variable, &nir->outputs)
6185 handle_shader_output_decl(&ctx, nir, variable);
6186
6187 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6188 _mesa_key_pointer_equal);
6189 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6190 _mesa_key_pointer_equal);
6191 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6192 _mesa_key_pointer_equal);
6193
6194 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6195
6196 setup_locals(&ctx, func);
6197
6198 if (nir->stage == MESA_SHADER_COMPUTE)
6199 setup_shared(&ctx, nir);
6200
6201 visit_cf_list(&ctx, &func->impl->body);
6202 phi_post_pass(&ctx);
6203
6204 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6205 ctx.outputs);
6206
6207 free(ctx.locals);
6208 ralloc_free(ctx.defs);
6209 ralloc_free(ctx.phis);
6210 ralloc_free(ctx.vars);
6211
6212 if (nctx)
6213 nctx->nir = NULL;
6214 }
6215
6216 static
6217 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6218 struct nir_shader *nir,
6219 struct ac_shader_variant_info *shader_info,
6220 const struct ac_nir_compiler_options *options)
6221 {
6222 struct nir_to_llvm_context ctx = {0};
6223 unsigned i;
6224 ctx.options = options;
6225 ctx.shader_info = shader_info;
6226 ctx.context = LLVMContextCreate();
6227 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6228
6229 ac_llvm_context_init(&ctx.ac, ctx.context);
6230 ctx.ac.module = ctx.module;
6231
6232 memset(shader_info, 0, sizeof(*shader_info));
6233
6234 ac_nir_shader_info_pass(nir, options, &shader_info->info);
6235
6236 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6237
6238 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6239 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6240 LLVMSetDataLayout(ctx.module, data_layout_str);
6241 LLVMDisposeTargetData(data_layout);
6242 LLVMDisposeMessage(data_layout_str);
6243
6244 setup_types(&ctx);
6245
6246 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6247 ctx.ac.builder = ctx.builder;
6248 ctx.stage = nir->stage;
6249 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
6250
6251 for (i = 0; i < AC_UD_MAX_SETS; i++)
6252 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6253 for (i = 0; i < AC_UD_MAX_UD; i++)
6254 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6255
6256 create_function(&ctx);
6257
6258 if (nir->stage == MESA_SHADER_GEOMETRY) {
6259 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.i32, "gs_next_vertex");
6260
6261 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
6262 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
6263 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
6264 } else if (nir->stage == MESA_SHADER_VERTEX) {
6265 if (shader_info->info.vs.needs_instance_id) {
6266 ctx.shader_info->vs.vgpr_comp_cnt =
6267 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6268 }
6269 } else if (nir->stage == MESA_SHADER_FRAGMENT) {
6270 shader_info->fs.can_discard = nir->info.fs.uses_discard;
6271 }
6272
6273 ac_setup_rings(&ctx);
6274
6275 ctx.num_output_clips = nir->info.clip_distance_array_size;
6276 ctx.num_output_culls = nir->info.cull_distance_array_size;
6277
6278 nir_foreach_variable(variable, &nir->inputs)
6279 handle_shader_input_decl(&ctx, variable);
6280
6281 if (nir->stage == MESA_SHADER_FRAGMENT)
6282 handle_fs_inputs_pre(&ctx, nir);
6283
6284 ctx.abi.chip_class = options->chip_class;
6285 ctx.abi.inputs = &ctx.inputs[0];
6286 ctx.abi.emit_outputs = handle_shader_outputs_post;
6287 ctx.abi.load_ssbo = radv_load_ssbo;
6288 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6289
6290 nir_foreach_variable(variable, &nir->outputs)
6291 scan_shader_output_decl(&ctx, variable);
6292
6293 ac_nir_translate(&ctx.ac, &ctx.abi, nir, &ctx);
6294
6295 LLVMBuildRetVoid(ctx.builder);
6296
6297 ac_llvm_finalize_module(&ctx);
6298
6299 ac_nir_eliminate_const_vs_outputs(&ctx);
6300
6301 if (nir->stage == MESA_SHADER_GEOMETRY) {
6302 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
6303 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6304 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6305 nir->info.gs.vertices_out;
6306 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
6307 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6308 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6309 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6310 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6311 }
6312
6313 return ctx.module;
6314 }
6315
6316 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6317 {
6318 unsigned *retval = (unsigned *)context;
6319 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6320 char *description = LLVMGetDiagInfoDescription(di);
6321
6322 if (severity == LLVMDSError) {
6323 *retval = 1;
6324 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6325 description);
6326 }
6327
6328 LLVMDisposeMessage(description);
6329 }
6330
6331 static unsigned ac_llvm_compile(LLVMModuleRef M,
6332 struct ac_shader_binary *binary,
6333 LLVMTargetMachineRef tm)
6334 {
6335 unsigned retval = 0;
6336 char *err;
6337 LLVMContextRef llvm_ctx;
6338 LLVMMemoryBufferRef out_buffer;
6339 unsigned buffer_size;
6340 const char *buffer_data;
6341 LLVMBool mem_err;
6342
6343 /* Setup Diagnostic Handler*/
6344 llvm_ctx = LLVMGetModuleContext(M);
6345
6346 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6347 &retval);
6348
6349 /* Compile IR*/
6350 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6351 &err, &out_buffer);
6352
6353 /* Process Errors/Warnings */
6354 if (mem_err) {
6355 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6356 free(err);
6357 retval = 1;
6358 goto out;
6359 }
6360
6361 /* Extract Shader Code*/
6362 buffer_size = LLVMGetBufferSize(out_buffer);
6363 buffer_data = LLVMGetBufferStart(out_buffer);
6364
6365 ac_elf_read(buffer_data, buffer_size, binary);
6366
6367 /* Clean up */
6368 LLVMDisposeMemoryBuffer(out_buffer);
6369
6370 out:
6371 return retval;
6372 }
6373
6374 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6375 LLVMModuleRef llvm_module,
6376 struct ac_shader_binary *binary,
6377 struct ac_shader_config *config,
6378 struct ac_shader_variant_info *shader_info,
6379 gl_shader_stage stage,
6380 bool dump_shader, bool supports_spill)
6381 {
6382 if (dump_shader)
6383 ac_dump_module(llvm_module);
6384
6385 memset(binary, 0, sizeof(*binary));
6386 int v = ac_llvm_compile(llvm_module, binary, tm);
6387 if (v) {
6388 fprintf(stderr, "compile failed\n");
6389 }
6390
6391 if (dump_shader)
6392 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6393
6394 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6395
6396 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6397 LLVMDisposeModule(llvm_module);
6398 LLVMContextDispose(ctx);
6399
6400 if (stage == MESA_SHADER_FRAGMENT) {
6401 shader_info->num_input_vgprs = 0;
6402 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6403 shader_info->num_input_vgprs += 2;
6404 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6405 shader_info->num_input_vgprs += 2;
6406 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6407 shader_info->num_input_vgprs += 2;
6408 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6409 shader_info->num_input_vgprs += 3;
6410 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6411 shader_info->num_input_vgprs += 2;
6412 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6413 shader_info->num_input_vgprs += 2;
6414 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6415 shader_info->num_input_vgprs += 2;
6416 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6417 shader_info->num_input_vgprs += 1;
6418 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6419 shader_info->num_input_vgprs += 1;
6420 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6421 shader_info->num_input_vgprs += 1;
6422 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6423 shader_info->num_input_vgprs += 1;
6424 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6425 shader_info->num_input_vgprs += 1;
6426 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6427 shader_info->num_input_vgprs += 1;
6428 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6429 shader_info->num_input_vgprs += 1;
6430 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6431 shader_info->num_input_vgprs += 1;
6432 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6433 shader_info->num_input_vgprs += 1;
6434 }
6435 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6436
6437 /* +3 for scratch wave offset and VCC */
6438 config->num_sgprs = MAX2(config->num_sgprs,
6439 shader_info->num_input_sgprs + 3);
6440 }
6441
6442 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6443 struct ac_shader_binary *binary,
6444 struct ac_shader_config *config,
6445 struct ac_shader_variant_info *shader_info,
6446 struct nir_shader *nir,
6447 const struct ac_nir_compiler_options *options,
6448 bool dump_shader)
6449 {
6450
6451 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6452 options);
6453
6454 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6455 switch (nir->stage) {
6456 case MESA_SHADER_COMPUTE:
6457 for (int i = 0; i < 3; ++i)
6458 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6459 break;
6460 case MESA_SHADER_FRAGMENT:
6461 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6462 break;
6463 case MESA_SHADER_GEOMETRY:
6464 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6465 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6466 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6467 shader_info->gs.invocations = nir->info.gs.invocations;
6468 break;
6469 case MESA_SHADER_TESS_EVAL:
6470 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6471 shader_info->tes.spacing = nir->info.tess.spacing;
6472 shader_info->tes.ccw = nir->info.tess.ccw;
6473 shader_info->tes.point_mode = nir->info.tess.point_mode;
6474 shader_info->tes.as_es = options->key.tes.as_es;
6475 break;
6476 case MESA_SHADER_TESS_CTRL:
6477 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6478 break;
6479 case MESA_SHADER_VERTEX:
6480 shader_info->vs.as_es = options->key.vs.as_es;
6481 shader_info->vs.as_ls = options->key.vs.as_ls;
6482 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6483 if (options->key.vs.as_ls)
6484 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6485 break;
6486 default:
6487 break;
6488 }
6489 }
6490
6491 static void
6492 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6493 {
6494 LLVMValueRef args[9];
6495 args[0] = ctx->gsvs_ring;
6496 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6497 args[3] = ctx->i32zero;
6498 args[4] = ctx->i32one; /* OFFEN */
6499 args[5] = ctx->i32zero; /* IDXEN */
6500 args[6] = ctx->i32one; /* GLC */
6501 args[7] = ctx->i32one; /* SLC */
6502 args[8] = ctx->i32zero; /* TFE */
6503
6504 int idx = 0;
6505
6506 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6507 int length = 4;
6508 int slot = idx;
6509 int slot_inc = 1;
6510 if (!(ctx->output_mask & (1ull << i)))
6511 continue;
6512
6513 if (i == VARYING_SLOT_CLIP_DIST0) {
6514 /* unpack clip and cull from a single set of slots */
6515 length = ctx->num_output_clips + ctx->num_output_culls;
6516 if (length > 4)
6517 slot_inc = 2;
6518 }
6519
6520 for (unsigned j = 0; j < length; j++) {
6521 LLVMValueRef value;
6522 args[2] = LLVMConstInt(ctx->i32,
6523 (slot * 4 + j) *
6524 ctx->gs_max_out_vertices * 16 * 4, false);
6525
6526 value = ac_build_intrinsic(&ctx->ac,
6527 "llvm.SI.buffer.load.dword.i32.i32",
6528 ctx->i32, args, 9,
6529 AC_FUNC_ATTR_READONLY |
6530 AC_FUNC_ATTR_LEGACY);
6531
6532 LLVMBuildStore(ctx->builder,
6533 to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6534 }
6535 idx += slot_inc;
6536 }
6537 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6538 }
6539
6540 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6541 struct nir_shader *geom_shader,
6542 struct ac_shader_binary *binary,
6543 struct ac_shader_config *config,
6544 struct ac_shader_variant_info *shader_info,
6545 const struct ac_nir_compiler_options *options,
6546 bool dump_shader)
6547 {
6548 struct nir_to_llvm_context ctx = {0};
6549 ctx.context = LLVMContextCreate();
6550 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6551 ctx.options = options;
6552 ctx.shader_info = shader_info;
6553
6554 ac_llvm_context_init(&ctx.ac, ctx.context);
6555 ctx.ac.module = ctx.module;
6556
6557 ctx.is_gs_copy_shader = true;
6558 LLVMSetTarget(ctx.module, "amdgcn--");
6559 setup_types(&ctx);
6560
6561 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6562 ctx.ac.builder = ctx.builder;
6563 ctx.stage = MESA_SHADER_VERTEX;
6564
6565 create_function(&ctx);
6566
6567 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6568 ac_setup_rings(&ctx);
6569
6570 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6571 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6572
6573 struct ac_nir_context nir_ctx = {};
6574 nir_ctx.ac = ctx.ac;
6575 nir_ctx.abi = &ctx.abi;
6576
6577 nir_ctx.nctx = &ctx;
6578 ctx.nir = &nir_ctx;
6579
6580 nir_foreach_variable(variable, &geom_shader->outputs) {
6581 scan_shader_output_decl(&ctx, variable);
6582 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6583 }
6584
6585 ac_gs_copy_shader_emit(&ctx);
6586
6587 ctx.nir = NULL;
6588
6589 LLVMBuildRetVoid(ctx.builder);
6590
6591 ac_llvm_finalize_module(&ctx);
6592
6593 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6594 MESA_SHADER_VERTEX,
6595 dump_shader, options->supports_spill);
6596 }