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radv/ac: refactor our fmask sample index fixup.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef gsvs_ring_stride;
87 LLVMValueRef gsvs_num_entries;
88 LLVMValueRef gs2vs_offset;
89 LLVMValueRef gs_wave_id;
90 LLVMValueRef gs_vtx_offset[6];
91 LLVMValueRef gs_prim_id, gs_invocation_id;
92
93 LLVMValueRef esgs_ring;
94 LLVMValueRef gsvs_ring;
95
96 LLVMValueRef prim_mask;
97 LLVMValueRef sample_positions;
98 LLVMValueRef persp_sample, persp_center, persp_centroid;
99 LLVMValueRef linear_sample, linear_center, linear_centroid;
100 LLVMValueRef front_face;
101 LLVMValueRef ancillary;
102 LLVMValueRef sample_coverage;
103 LLVMValueRef frag_pos[4];
104
105 LLVMBasicBlockRef continue_block;
106 LLVMBasicBlockRef break_block;
107
108 LLVMTypeRef i1;
109 LLVMTypeRef i8;
110 LLVMTypeRef i16;
111 LLVMTypeRef i32;
112 LLVMTypeRef i64;
113 LLVMTypeRef v2i32;
114 LLVMTypeRef v3i32;
115 LLVMTypeRef v4i32;
116 LLVMTypeRef v8i32;
117 LLVMTypeRef f64;
118 LLVMTypeRef f32;
119 LLVMTypeRef f16;
120 LLVMTypeRef v2f32;
121 LLVMTypeRef v4f32;
122 LLVMTypeRef v16i8;
123 LLVMTypeRef voidt;
124
125 LLVMValueRef i32zero;
126 LLVMValueRef i32one;
127 LLVMValueRef f32zero;
128 LLVMValueRef f32one;
129 LLVMValueRef v4f32empty;
130
131 unsigned uniform_md_kind;
132 LLVMValueRef empty_md;
133 gl_shader_stage stage;
134
135 LLVMValueRef lds;
136 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
137 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
138
139 LLVMValueRef shared_memory;
140 uint64_t input_mask;
141 uint64_t output_mask;
142 int num_locals;
143 LLVMValueRef *locals;
144 bool has_ddxy;
145 uint8_t num_input_clips;
146 uint8_t num_input_culls;
147 uint8_t num_output_clips;
148 uint8_t num_output_culls;
149
150 bool has_ds_bpermute;
151
152 bool is_gs_copy_shader;
153 LLVMValueRef gs_next_vertex;
154 unsigned gs_max_out_vertices;
155 };
156
157 struct ac_tex_info {
158 LLVMValueRef args[12];
159 int arg_count;
160 LLVMTypeRef dst_type;
161 bool has_offset;
162 };
163
164 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
165 nir_deref_var *deref,
166 enum desc_type desc_type);
167 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
168 {
169 return (index * 4) + chan;
170 }
171
172 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
173 {
174 if (slot == VARYING_SLOT_POS)
175 return 0;
176 if (slot == VARYING_SLOT_PSIZ)
177 return 1;
178 if (slot == VARYING_SLOT_CLIP_DIST0 ||
179 slot == VARYING_SLOT_CULL_DIST0)
180 return 2;
181 if (slot == VARYING_SLOT_CLIP_DIST1 ||
182 slot == VARYING_SLOT_CULL_DIST1)
183 return 3;
184 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
185 return 4 + (slot - VARYING_SLOT_VAR0);
186 unreachable("illegal slot in get unique index\n");
187 }
188
189 static unsigned llvm_get_type_size(LLVMTypeRef type)
190 {
191 LLVMTypeKind kind = LLVMGetTypeKind(type);
192
193 switch (kind) {
194 case LLVMIntegerTypeKind:
195 return LLVMGetIntTypeWidth(type) / 8;
196 case LLVMFloatTypeKind:
197 return 4;
198 case LLVMPointerTypeKind:
199 return 8;
200 case LLVMVectorTypeKind:
201 return LLVMGetVectorSize(type) *
202 llvm_get_type_size(LLVMGetElementType(type));
203 default:
204 assert(0);
205 return 0;
206 }
207 }
208
209 static void set_llvm_calling_convention(LLVMValueRef func,
210 gl_shader_stage stage)
211 {
212 enum radeon_llvm_calling_convention calling_conv;
213
214 switch (stage) {
215 case MESA_SHADER_VERTEX:
216 case MESA_SHADER_TESS_CTRL:
217 case MESA_SHADER_TESS_EVAL:
218 calling_conv = RADEON_LLVM_AMDGPU_VS;
219 break;
220 case MESA_SHADER_GEOMETRY:
221 calling_conv = RADEON_LLVM_AMDGPU_GS;
222 break;
223 case MESA_SHADER_FRAGMENT:
224 calling_conv = RADEON_LLVM_AMDGPU_PS;
225 break;
226 case MESA_SHADER_COMPUTE:
227 calling_conv = RADEON_LLVM_AMDGPU_CS;
228 break;
229 default:
230 unreachable("Unhandle shader type");
231 }
232
233 LLVMSetFunctionCallConv(func, calling_conv);
234 }
235
236 static LLVMValueRef
237 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
238 LLVMBuilderRef builder, LLVMTypeRef *return_types,
239 unsigned num_return_elems, LLVMTypeRef *param_types,
240 unsigned param_count, unsigned array_params_mask,
241 unsigned sgpr_params, bool unsafe_math)
242 {
243 LLVMTypeRef main_function_type, ret_type;
244 LLVMBasicBlockRef main_function_body;
245
246 if (num_return_elems)
247 ret_type = LLVMStructTypeInContext(ctx, return_types,
248 num_return_elems, true);
249 else
250 ret_type = LLVMVoidTypeInContext(ctx);
251
252 /* Setup the function */
253 main_function_type =
254 LLVMFunctionType(ret_type, param_types, param_count, 0);
255 LLVMValueRef main_function =
256 LLVMAddFunction(module, "main", main_function_type);
257 main_function_body =
258 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
259 LLVMPositionBuilderAtEnd(builder, main_function_body);
260
261 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
262 for (unsigned i = 0; i < sgpr_params; ++i) {
263 if (array_params_mask & (1 << i)) {
264 LLVMValueRef P = LLVMGetParam(main_function, i);
265 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_BYVAL);
266 ac_add_attr_dereferenceable(P, UINT64_MAX);
267 }
268 else {
269 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_INREG);
270 }
271 }
272
273 if (unsafe_math) {
274 /* These were copied from some LLVM test. */
275 LLVMAddTargetDependentFunctionAttr(main_function,
276 "less-precise-fpmad",
277 "true");
278 LLVMAddTargetDependentFunctionAttr(main_function,
279 "no-infs-fp-math",
280 "true");
281 LLVMAddTargetDependentFunctionAttr(main_function,
282 "no-nans-fp-math",
283 "true");
284 LLVMAddTargetDependentFunctionAttr(main_function,
285 "unsafe-fp-math",
286 "true");
287 }
288 return main_function;
289 }
290
291 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
292 {
293 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
294 CONST_ADDR_SPACE);
295 }
296
297 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
298 int idx,
299 LLVMTypeRef type)
300 {
301 LLVMValueRef offset;
302 LLVMValueRef ptr;
303 int addr_space;
304
305 offset = LLVMConstInt(ctx->i32, idx, false);
306
307 ptr = ctx->shared_memory;
308 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
309 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
310 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
311 return ptr;
312 }
313
314 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
315 {
316 if (t == ctx->f16 || t == ctx->i16)
317 return ctx->i16;
318 else if (t == ctx->f32 || t == ctx->i32)
319 return ctx->i32;
320 else if (t == ctx->f64 || t == ctx->i64)
321 return ctx->i64;
322 else
323 unreachable("Unhandled integer size");
324 }
325
326 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
327 {
328 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
329 LLVMTypeRef elem_type = LLVMGetElementType(t);
330 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
331 LLVMGetVectorSize(t));
332 }
333 return to_integer_type_scalar(ctx, t);
334 }
335
336 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
337 {
338 LLVMTypeRef type = LLVMTypeOf(v);
339 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
340 }
341
342 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
343 {
344 if (t == ctx->i16 || t == ctx->f16)
345 return ctx->f16;
346 else if (t == ctx->i32 || t == ctx->f32)
347 return ctx->f32;
348 else if (t == ctx->i64 || t == ctx->f64)
349 return ctx->f64;
350 else
351 unreachable("Unhandled float size");
352 }
353
354 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
355 {
356 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
357 LLVMTypeRef elem_type = LLVMGetElementType(t);
358 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
359 LLVMGetVectorSize(t));
360 }
361 return to_float_type_scalar(ctx, t);
362 }
363
364 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
365 {
366 LLVMTypeRef type = LLVMTypeOf(v);
367 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
368 }
369
370 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
371 {
372 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
373 type = LLVMGetElementType(type);
374
375 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
376 return LLVMGetIntTypeWidth(type);
377
378 if (type == ctx->f16)
379 return 16;
380 if (type == ctx->f32)
381 return 32;
382 if (type == ctx->f64)
383 return 64;
384
385 unreachable("Unhandled type kind in get_elem_bits");
386 }
387
388 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
389 LLVMValueRef param, unsigned rshift,
390 unsigned bitwidth)
391 {
392 LLVMValueRef value = param;
393 if (rshift)
394 value = LLVMBuildLShr(ctx->builder, value,
395 LLVMConstInt(ctx->i32, rshift, false), "");
396
397 if (rshift + bitwidth < 32) {
398 unsigned mask = (1 << bitwidth) - 1;
399 value = LLVMBuildAnd(ctx->builder, value,
400 LLVMConstInt(ctx->i32, mask, false), "");
401 }
402 return value;
403 }
404
405 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
406 {
407 ud_info->sgpr_idx = sgpr_idx;
408 ud_info->num_sgprs = num_sgprs;
409 ud_info->indirect = false;
410 ud_info->indirect_offset = 0;
411 }
412
413 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
414 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
415 {
416 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
417 }
418
419 #if 0
420 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
421 uint32_t indirect_offset)
422 {
423 ud_info->sgpr_idx = sgpr_idx;
424 ud_info->num_sgprs = num_sgprs;
425 ud_info->indirect = true;
426 ud_info->indirect_offset = indirect_offset;
427 }
428 #endif
429
430 static void create_function(struct nir_to_llvm_context *ctx)
431 {
432 LLVMTypeRef arg_types[23];
433 unsigned arg_idx = 0;
434 unsigned array_params_mask = 0;
435 unsigned sgpr_count = 0, user_sgpr_count;
436 unsigned i;
437 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
438 unsigned user_sgpr_idx;
439 bool need_push_constants;
440 bool need_ring_offsets = false;
441
442 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
443 if (ctx->stage == MESA_SHADER_GEOMETRY ||
444 ctx->stage == MESA_SHADER_VERTEX ||
445 ctx->is_gs_copy_shader)
446 need_ring_offsets = true;
447
448 need_push_constants = true;
449 if (!ctx->options->layout)
450 need_push_constants = false;
451 else if (!ctx->options->layout->push_constant_size &&
452 !ctx->options->layout->dynamic_offset_count)
453 need_push_constants = false;
454
455 if (need_ring_offsets && !ctx->options->supports_spill) {
456 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
457 }
458
459 /* 1 for each descriptor set */
460 for (unsigned i = 0; i < num_sets; ++i) {
461 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
462 array_params_mask |= (1 << arg_idx);
463 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
464 }
465 }
466
467 if (need_push_constants) {
468 /* 1 for push constants and dynamic descriptors */
469 array_params_mask |= (1 << arg_idx);
470 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
471 }
472
473 switch (ctx->stage) {
474 case MESA_SHADER_COMPUTE:
475 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
476 user_sgpr_count = arg_idx;
477 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
478 arg_types[arg_idx++] = ctx->i32;
479 sgpr_count = arg_idx;
480
481 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
482 break;
483 case MESA_SHADER_VERTEX:
484 if (!ctx->is_gs_copy_shader) {
485 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
486 arg_types[arg_idx++] = ctx->i32; // base vertex
487 arg_types[arg_idx++] = ctx->i32; // start instance
488 arg_types[arg_idx++] = ctx->i32; // draw index
489 }
490 user_sgpr_count = arg_idx;
491 if (ctx->options->key.vs.as_es)
492 arg_types[arg_idx++] = ctx->i32; //es2gs offset
493 sgpr_count = arg_idx;
494 arg_types[arg_idx++] = ctx->i32; // vertex id
495 if (!ctx->is_gs_copy_shader) {
496 arg_types[arg_idx++] = ctx->i32; // rel auto id
497 arg_types[arg_idx++] = ctx->i32; // vs prim id
498 arg_types[arg_idx++] = ctx->i32; // instance id
499 }
500 break;
501 case MESA_SHADER_GEOMETRY:
502 arg_types[arg_idx++] = ctx->i32; // gsvs stride
503 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
504 user_sgpr_count = arg_idx;
505 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
506 arg_types[arg_idx++] = ctx->i32; // wave id
507 sgpr_count = arg_idx;
508 arg_types[arg_idx++] = ctx->i32; // vtx0
509 arg_types[arg_idx++] = ctx->i32; // vtx1
510 arg_types[arg_idx++] = ctx->i32; // prim id
511 arg_types[arg_idx++] = ctx->i32; // vtx2
512 arg_types[arg_idx++] = ctx->i32; // vtx3
513 arg_types[arg_idx++] = ctx->i32; // vtx4
514 arg_types[arg_idx++] = ctx->i32; // vtx5
515 arg_types[arg_idx++] = ctx->i32; // GS instance id
516 break;
517 case MESA_SHADER_FRAGMENT:
518 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
519 user_sgpr_count = arg_idx;
520 arg_types[arg_idx++] = ctx->i32; /* prim mask */
521 sgpr_count = arg_idx;
522 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
523 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
524 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
525 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
526 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
527 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
528 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
529 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
530 arg_types[arg_idx++] = ctx->f32; /* pos x float */
531 arg_types[arg_idx++] = ctx->f32; /* pos y float */
532 arg_types[arg_idx++] = ctx->f32; /* pos z float */
533 arg_types[arg_idx++] = ctx->f32; /* pos w float */
534 arg_types[arg_idx++] = ctx->i32; /* front face */
535 arg_types[arg_idx++] = ctx->i32; /* ancillary */
536 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
537 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
538 break;
539 default:
540 unreachable("Shader stage not implemented");
541 }
542
543 ctx->main_function = create_llvm_function(
544 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
545 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
546 set_llvm_calling_convention(ctx->main_function, ctx->stage);
547
548 ctx->shader_info->num_input_sgprs = 0;
549 ctx->shader_info->num_input_vgprs = 0;
550
551 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
552 for (i = 0; i < user_sgpr_count; i++)
553 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
554
555 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
556 for (; i < sgpr_count; i++)
557 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
558
559 if (ctx->stage != MESA_SHADER_FRAGMENT)
560 for (; i < arg_idx; ++i)
561 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
562
563 arg_idx = 0;
564 user_sgpr_idx = 0;
565
566 if (ctx->options->supports_spill || need_ring_offsets) {
567 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
568 user_sgpr_idx += 2;
569 if (ctx->options->supports_spill) {
570 ctx->ring_offsets = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
571 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
572 NULL, 0, AC_FUNC_ATTR_READNONE);
573 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
574 const_array(ctx->v16i8, 8), "");
575 } else
576 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
577 }
578
579 for (unsigned i = 0; i < num_sets; ++i) {
580 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
581 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
582 user_sgpr_idx += 2;
583 ctx->descriptor_sets[i] =
584 LLVMGetParam(ctx->main_function, arg_idx++);
585 } else
586 ctx->descriptor_sets[i] = NULL;
587 }
588
589 if (need_push_constants) {
590 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
591 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
592 user_sgpr_idx += 2;
593 }
594
595 switch (ctx->stage) {
596 case MESA_SHADER_COMPUTE:
597 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
598 user_sgpr_idx += 3;
599 ctx->num_work_groups =
600 LLVMGetParam(ctx->main_function, arg_idx++);
601 ctx->workgroup_ids =
602 LLVMGetParam(ctx->main_function, arg_idx++);
603 ctx->tg_size =
604 LLVMGetParam(ctx->main_function, arg_idx++);
605 ctx->local_invocation_ids =
606 LLVMGetParam(ctx->main_function, arg_idx++);
607 break;
608 case MESA_SHADER_VERTEX:
609 if (!ctx->is_gs_copy_shader) {
610 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
611 user_sgpr_idx += 2;
612 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
613 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
614 user_sgpr_idx += 3;
615 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
616 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
617 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
618 }
619 if (ctx->options->key.vs.as_es)
620 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
621 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
622 if (!ctx->is_gs_copy_shader) {
623 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
624 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
625 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
626 }
627 break;
628 case MESA_SHADER_GEOMETRY:
629 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
630 user_sgpr_idx += 2;
631 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
632 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
633 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
634 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
635 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
636 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
637 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
638 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
639 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
640 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
641 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
642 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
643 break;
644 case MESA_SHADER_FRAGMENT:
645 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
646 user_sgpr_idx += 2;
647 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
648 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
649 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
650 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
651 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
652 arg_idx++;
653 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
654 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
655 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
656 arg_idx++; /* line stipple */
657 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
658 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
659 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
660 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
661 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
662 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
663 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
664 break;
665 default:
666 unreachable("Shader stage not implemented");
667 }
668 }
669
670 static void setup_types(struct nir_to_llvm_context *ctx)
671 {
672 LLVMValueRef args[4];
673
674 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
675 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
676 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
677 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
678 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
679 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
680 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
681 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
682 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
683 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
684 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
685 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
686 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
687 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
688 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
689 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
690
691 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
692 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
693 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
694 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
695
696 args[0] = ctx->f32zero;
697 args[1] = ctx->f32zero;
698 args[2] = ctx->f32zero;
699 args[3] = ctx->f32one;
700 ctx->v4f32empty = LLVMConstVector(args, 4);
701
702 ctx->uniform_md_kind =
703 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
704 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
705
706 args[0] = LLVMConstReal(ctx->f32, 2.5);
707 }
708
709 static int get_llvm_num_components(LLVMValueRef value)
710 {
711 LLVMTypeRef type = LLVMTypeOf(value);
712 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
713 ? LLVMGetVectorSize(type)
714 : 1;
715 return num_components;
716 }
717
718 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
719 LLVMValueRef value,
720 int index)
721 {
722 int count = get_llvm_num_components(value);
723
724 assert(index < count);
725 if (count == 1)
726 return value;
727
728 return LLVMBuildExtractElement(ctx->builder, value,
729 LLVMConstInt(ctx->i32, index, false), "");
730 }
731
732 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
733 LLVMValueRef value, unsigned count)
734 {
735 unsigned num_components = get_llvm_num_components(value);
736 if (count == num_components)
737 return value;
738
739 LLVMValueRef masks[] = {
740 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
741 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
742
743 if (count == 1)
744 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
745 "");
746
747 LLVMValueRef swizzle = LLVMConstVector(masks, count);
748 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
749 }
750
751 static void
752 build_store_values_extended(struct nir_to_llvm_context *ctx,
753 LLVMValueRef *values,
754 unsigned value_count,
755 unsigned value_stride,
756 LLVMValueRef vec)
757 {
758 LLVMBuilderRef builder = ctx->builder;
759 unsigned i;
760
761 if (value_count == 1) {
762 LLVMBuildStore(builder, vec, values[0]);
763 return;
764 }
765
766 for (i = 0; i < value_count; i++) {
767 LLVMValueRef ptr = values[i * value_stride];
768 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
769 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
770 LLVMBuildStore(builder, value, ptr);
771 }
772 }
773
774 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
775 nir_ssa_def *def)
776 {
777 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
778 if (def->num_components > 1) {
779 type = LLVMVectorType(type, def->num_components);
780 }
781 return type;
782 }
783
784 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
785 {
786 assert(src.is_ssa);
787 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
788 return (LLVMValueRef)entry->data;
789 }
790
791
792 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
793 struct nir_block *b)
794 {
795 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
796 return (LLVMBasicBlockRef)entry->data;
797 }
798
799 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
800 nir_alu_src src,
801 unsigned num_components)
802 {
803 LLVMValueRef value = get_src(ctx, src.src);
804 bool need_swizzle = false;
805
806 assert(value);
807 LLVMTypeRef type = LLVMTypeOf(value);
808 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
809 ? LLVMGetVectorSize(type)
810 : 1;
811
812 for (unsigned i = 0; i < num_components; ++i) {
813 assert(src.swizzle[i] < src_components);
814 if (src.swizzle[i] != i)
815 need_swizzle = true;
816 }
817
818 if (need_swizzle || num_components != src_components) {
819 LLVMValueRef masks[] = {
820 LLVMConstInt(ctx->i32, src.swizzle[0], false),
821 LLVMConstInt(ctx->i32, src.swizzle[1], false),
822 LLVMConstInt(ctx->i32, src.swizzle[2], false),
823 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
824
825 if (src_components > 1 && num_components == 1) {
826 value = LLVMBuildExtractElement(ctx->builder, value,
827 masks[0], "");
828 } else if (src_components == 1 && num_components > 1) {
829 LLVMValueRef values[] = {value, value, value, value};
830 value = ac_build_gather_values(&ctx->ac, values, num_components);
831 } else {
832 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
833 value = LLVMBuildShuffleVector(ctx->builder, value, value,
834 swizzle, "");
835 }
836 }
837 assert(!src.negate);
838 assert(!src.abs);
839 return value;
840 }
841
842 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
843 LLVMIntPredicate pred, LLVMValueRef src0,
844 LLVMValueRef src1)
845 {
846 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
847 return LLVMBuildSelect(ctx->builder, result,
848 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
849 LLVMConstInt(ctx->i32, 0, false), "");
850 }
851
852 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
853 LLVMRealPredicate pred, LLVMValueRef src0,
854 LLVMValueRef src1)
855 {
856 LLVMValueRef result;
857 src0 = to_float(ctx, src0);
858 src1 = to_float(ctx, src1);
859 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
860 return LLVMBuildSelect(ctx->builder, result,
861 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
862 LLVMConstInt(ctx->i32, 0, false), "");
863 }
864
865 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
866 const char *intrin,
867 LLVMTypeRef result_type,
868 LLVMValueRef src0)
869 {
870 char name[64];
871 LLVMValueRef params[] = {
872 to_float(ctx, src0),
873 };
874
875 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
876 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
877 }
878
879 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
880 const char *intrin,
881 LLVMTypeRef result_type,
882 LLVMValueRef src0, LLVMValueRef src1)
883 {
884 char name[64];
885 LLVMValueRef params[] = {
886 to_float(ctx, src0),
887 to_float(ctx, src1),
888 };
889
890 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
891 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
892 }
893
894 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
895 const char *intrin,
896 LLVMTypeRef result_type,
897 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
898 {
899 char name[64];
900 LLVMValueRef params[] = {
901 to_float(ctx, src0),
902 to_float(ctx, src1),
903 to_float(ctx, src2),
904 };
905
906 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
907 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
908 }
909
910 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
911 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
912 {
913 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
914 ctx->i32zero, "");
915 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
916 }
917
918 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
919 LLVMValueRef src0)
920 {
921 LLVMValueRef params[2] = {
922 src0,
923
924 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
925 * add special code to check for x=0. The reason is that
926 * the LLVM behavior for x=0 is different from what we
927 * need here.
928 *
929 * The hardware already implements the correct behavior.
930 */
931 LLVMConstInt(ctx->i32, 1, false),
932 };
933 return ac_emit_llvm_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
934 }
935
936 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
937 LLVMValueRef src0)
938 {
939 return ac_emit_imsb(&ctx->ac, src0, ctx->i32);
940 }
941
942 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
943 LLVMValueRef src0)
944 {
945 return ac_emit_umsb(&ctx->ac, src0, ctx->i32);
946 }
947
948 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
949 LLVMIntPredicate pred,
950 LLVMValueRef src0, LLVMValueRef src1)
951 {
952 return LLVMBuildSelect(ctx->builder,
953 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
954 src0,
955 src1, "");
956
957 }
958 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
959 LLVMValueRef src0)
960 {
961 return emit_minmax_int(ctx, LLVMIntSGT, src0,
962 LLVMBuildNeg(ctx->builder, src0, ""));
963 }
964
965 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
966 LLVMValueRef src0)
967 {
968 LLVMValueRef cmp, val;
969
970 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
971 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
972 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
973 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
974 return val;
975 }
976
977 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
978 LLVMValueRef src0)
979 {
980 LLVMValueRef cmp, val;
981
982 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
983 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
984 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
985 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
986 return val;
987 }
988
989 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
990 LLVMValueRef src0)
991 {
992 const char *intr = "llvm.floor.f32";
993 LLVMValueRef fsrc0 = to_float(ctx, src0);
994 LLVMValueRef params[] = {
995 fsrc0,
996 };
997 LLVMValueRef floor = ac_emit_llvm_intrinsic(&ctx->ac, intr,
998 ctx->f32, params, 1,
999 AC_FUNC_ATTR_READNONE);
1000 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1001 }
1002
1003 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1004 const char *intrin,
1005 LLVMValueRef src0, LLVMValueRef src1)
1006 {
1007 LLVMTypeRef ret_type;
1008 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1009 LLVMValueRef res;
1010 LLVMValueRef params[] = { src0, src1 };
1011 ret_type = LLVMStructTypeInContext(ctx->context, types,
1012 2, true);
1013
1014 res = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ret_type,
1015 params, 2, AC_FUNC_ATTR_READNONE);
1016
1017 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1018 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1019 return res;
1020 }
1021
1022 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1023 LLVMValueRef src0)
1024 {
1025 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1026 }
1027
1028 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1029 LLVMValueRef src0, LLVMValueRef src1)
1030 {
1031 LLVMValueRef dst64, result;
1032 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1033 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1034
1035 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1036 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1037 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1038 return result;
1039 }
1040
1041 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1042 LLVMValueRef src0, LLVMValueRef src1)
1043 {
1044 LLVMValueRef dst64, result;
1045 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1046 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1047
1048 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1049 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1050 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1051 return result;
1052 }
1053
1054 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1055 const char *intrin,
1056 LLVMValueRef srcs[3])
1057 {
1058 LLVMValueRef result;
1059 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1060 result = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->i32, srcs, 3, AC_FUNC_ATTR_READNONE);
1061
1062 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1063 return result;
1064 }
1065
1066 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1067 LLVMValueRef src0, LLVMValueRef src1,
1068 LLVMValueRef src2, LLVMValueRef src3)
1069 {
1070 LLVMValueRef bfi_args[3], result;
1071
1072 bfi_args[0] = LLVMBuildShl(ctx->builder,
1073 LLVMBuildSub(ctx->builder,
1074 LLVMBuildShl(ctx->builder,
1075 ctx->i32one,
1076 src3, ""),
1077 ctx->i32one, ""),
1078 src2, "");
1079 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1080 bfi_args[2] = src0;
1081
1082 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1083
1084 /* Calculate:
1085 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1086 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1087 */
1088 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1089 LLVMBuildAnd(ctx->builder, bfi_args[0],
1090 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1091
1092 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1093 return result;
1094 }
1095
1096 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1097 LLVMValueRef src0)
1098 {
1099 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1100 int i;
1101 LLVMValueRef comp[2];
1102
1103 src0 = to_float(ctx, src0);
1104 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1105 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1106 for (i = 0; i < 2; i++) {
1107 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1108 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1109 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1110 }
1111
1112 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1113 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1114
1115 return comp[0];
1116 }
1117
1118 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1119 LLVMValueRef src0)
1120 {
1121 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1122 LLVMValueRef temps[2], result, val;
1123 int i;
1124
1125 for (i = 0; i < 2; i++) {
1126 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1127 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1128 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1129 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1130 }
1131
1132 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1133 ctx->i32zero, "");
1134 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1135 ctx->i32one, "");
1136 return result;
1137 }
1138
1139 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1140 nir_op op,
1141 LLVMValueRef src0)
1142 {
1143 unsigned mask;
1144 int idx;
1145 LLVMValueRef result;
1146 ctx->has_ddxy = true;
1147
1148 if (!ctx->lds && !ctx->has_ds_bpermute)
1149 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1150 LLVMArrayType(ctx->i32, 64),
1151 "ddxy_lds", LOCAL_ADDR_SPACE);
1152
1153 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1154 mask = AC_TID_MASK_LEFT;
1155 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1156 mask = AC_TID_MASK_TOP;
1157 else
1158 mask = AC_TID_MASK_TOP_LEFT;
1159
1160 /* for DDX we want to next X pixel, DDY next Y pixel. */
1161 if (op == nir_op_fddx_fine ||
1162 op == nir_op_fddx_coarse ||
1163 op == nir_op_fddx)
1164 idx = 1;
1165 else
1166 idx = 2;
1167
1168 result = ac_emit_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1169 mask, idx, ctx->lds,
1170 src0);
1171 return result;
1172 }
1173
1174 /*
1175 * this takes an I,J coordinate pair,
1176 * and works out the X and Y derivatives.
1177 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1178 */
1179 static LLVMValueRef emit_ddxy_interp(
1180 struct nir_to_llvm_context *ctx,
1181 LLVMValueRef interp_ij)
1182 {
1183 LLVMValueRef result[4], a;
1184 unsigned i;
1185
1186 for (i = 0; i < 2; i++) {
1187 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1188 LLVMConstInt(ctx->i32, i, false), "");
1189 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1190 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1191 }
1192 return ac_build_gather_values(&ctx->ac, result, 4);
1193 }
1194
1195 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1196 {
1197 LLVMValueRef src[4], result = NULL;
1198 unsigned num_components = instr->dest.dest.ssa.num_components;
1199 unsigned src_components;
1200 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1201
1202 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1203 switch (instr->op) {
1204 case nir_op_vec2:
1205 case nir_op_vec3:
1206 case nir_op_vec4:
1207 src_components = 1;
1208 break;
1209 case nir_op_pack_half_2x16:
1210 src_components = 2;
1211 break;
1212 case nir_op_unpack_half_2x16:
1213 src_components = 1;
1214 break;
1215 default:
1216 src_components = num_components;
1217 break;
1218 }
1219 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1220 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1221
1222 switch (instr->op) {
1223 case nir_op_fmov:
1224 case nir_op_imov:
1225 result = src[0];
1226 break;
1227 case nir_op_fneg:
1228 src[0] = to_float(ctx, src[0]);
1229 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1230 break;
1231 case nir_op_ineg:
1232 result = LLVMBuildNeg(ctx->builder, src[0], "");
1233 break;
1234 case nir_op_inot:
1235 result = LLVMBuildNot(ctx->builder, src[0], "");
1236 break;
1237 case nir_op_iadd:
1238 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1239 break;
1240 case nir_op_fadd:
1241 src[0] = to_float(ctx, src[0]);
1242 src[1] = to_float(ctx, src[1]);
1243 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1244 break;
1245 case nir_op_fsub:
1246 src[0] = to_float(ctx, src[0]);
1247 src[1] = to_float(ctx, src[1]);
1248 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1249 break;
1250 case nir_op_isub:
1251 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1252 break;
1253 case nir_op_imul:
1254 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1255 break;
1256 case nir_op_imod:
1257 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1258 break;
1259 case nir_op_umod:
1260 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1261 break;
1262 case nir_op_fmod:
1263 src[0] = to_float(ctx, src[0]);
1264 src[1] = to_float(ctx, src[1]);
1265 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1266 result = emit_intrin_1f_param(ctx, "llvm.floor",
1267 to_float_type(ctx, def_type), result);
1268 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1269 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1270 break;
1271 case nir_op_frem:
1272 src[0] = to_float(ctx, src[0]);
1273 src[1] = to_float(ctx, src[1]);
1274 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1275 break;
1276 case nir_op_irem:
1277 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1278 break;
1279 case nir_op_idiv:
1280 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1281 break;
1282 case nir_op_udiv:
1283 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1284 break;
1285 case nir_op_fmul:
1286 src[0] = to_float(ctx, src[0]);
1287 src[1] = to_float(ctx, src[1]);
1288 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1289 break;
1290 case nir_op_fdiv:
1291 src[0] = to_float(ctx, src[0]);
1292 src[1] = to_float(ctx, src[1]);
1293 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1294 break;
1295 case nir_op_frcp:
1296 src[0] = to_float(ctx, src[0]);
1297 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, src[0]);
1298 break;
1299 case nir_op_iand:
1300 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1301 break;
1302 case nir_op_ior:
1303 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1304 break;
1305 case nir_op_ixor:
1306 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1307 break;
1308 case nir_op_ishl:
1309 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1310 break;
1311 case nir_op_ishr:
1312 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1313 break;
1314 case nir_op_ushr:
1315 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1316 break;
1317 case nir_op_ilt:
1318 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1319 break;
1320 case nir_op_ine:
1321 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1322 break;
1323 case nir_op_ieq:
1324 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1325 break;
1326 case nir_op_ige:
1327 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1328 break;
1329 case nir_op_ult:
1330 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1331 break;
1332 case nir_op_uge:
1333 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1334 break;
1335 case nir_op_feq:
1336 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1337 break;
1338 case nir_op_fne:
1339 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1340 break;
1341 case nir_op_flt:
1342 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1343 break;
1344 case nir_op_fge:
1345 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1346 break;
1347 case nir_op_fabs:
1348 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1349 to_float_type(ctx, def_type), src[0]);
1350 break;
1351 case nir_op_iabs:
1352 result = emit_iabs(ctx, src[0]);
1353 break;
1354 case nir_op_imax:
1355 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1356 break;
1357 case nir_op_imin:
1358 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1359 break;
1360 case nir_op_umax:
1361 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1362 break;
1363 case nir_op_umin:
1364 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1365 break;
1366 case nir_op_isign:
1367 result = emit_isign(ctx, src[0]);
1368 break;
1369 case nir_op_fsign:
1370 src[0] = to_float(ctx, src[0]);
1371 result = emit_fsign(ctx, src[0]);
1372 break;
1373 case nir_op_ffloor:
1374 result = emit_intrin_1f_param(ctx, "llvm.floor",
1375 to_float_type(ctx, def_type), src[0]);
1376 break;
1377 case nir_op_ftrunc:
1378 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1379 to_float_type(ctx, def_type), src[0]);
1380 break;
1381 case nir_op_fceil:
1382 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1383 to_float_type(ctx, def_type), src[0]);
1384 break;
1385 case nir_op_fround_even:
1386 result = emit_intrin_1f_param(ctx, "llvm.rint",
1387 to_float_type(ctx, def_type),src[0]);
1388 break;
1389 case nir_op_ffract:
1390 result = emit_ffract(ctx, src[0]);
1391 break;
1392 case nir_op_fsin:
1393 result = emit_intrin_1f_param(ctx, "llvm.sin",
1394 to_float_type(ctx, def_type), src[0]);
1395 break;
1396 case nir_op_fcos:
1397 result = emit_intrin_1f_param(ctx, "llvm.cos",
1398 to_float_type(ctx, def_type), src[0]);
1399 break;
1400 case nir_op_fsqrt:
1401 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1402 to_float_type(ctx, def_type), src[0]);
1403 break;
1404 case nir_op_fexp2:
1405 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1406 to_float_type(ctx, def_type), src[0]);
1407 break;
1408 case nir_op_flog2:
1409 result = emit_intrin_1f_param(ctx, "llvm.log2",
1410 to_float_type(ctx, def_type), src[0]);
1411 break;
1412 case nir_op_frsq:
1413 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1414 to_float_type(ctx, def_type), src[0]);
1415 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, result);
1416 break;
1417 case nir_op_fpow:
1418 result = emit_intrin_2f_param(ctx, "llvm.pow",
1419 to_float_type(ctx, def_type), src[0], src[1]);
1420 break;
1421 case nir_op_fmax:
1422 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1423 to_float_type(ctx, def_type), src[0], src[1]);
1424 break;
1425 case nir_op_fmin:
1426 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1427 to_float_type(ctx, def_type), src[0], src[1]);
1428 break;
1429 case nir_op_ffma:
1430 result = emit_intrin_3f_param(ctx, "llvm.fma",
1431 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1432 break;
1433 case nir_op_ibitfield_extract:
1434 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.i32", src);
1435 break;
1436 case nir_op_ubitfield_extract:
1437 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.u32", src);
1438 break;
1439 case nir_op_bitfield_insert:
1440 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1441 break;
1442 case nir_op_bitfield_reverse:
1443 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1444 break;
1445 case nir_op_bit_count:
1446 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1447 break;
1448 case nir_op_vec2:
1449 case nir_op_vec3:
1450 case nir_op_vec4:
1451 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1452 src[i] = to_integer(ctx, src[i]);
1453 result = ac_build_gather_values(&ctx->ac, src, num_components);
1454 break;
1455 case nir_op_d2i:
1456 case nir_op_f2i:
1457 src[0] = to_float(ctx, src[0]);
1458 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1459 break;
1460 case nir_op_d2u:
1461 case nir_op_f2u:
1462 src[0] = to_float(ctx, src[0]);
1463 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1464 break;
1465 case nir_op_i2d:
1466 case nir_op_i2f:
1467 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1468 break;
1469 case nir_op_u2d:
1470 case nir_op_u2f:
1471 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1472 break;
1473 case nir_op_f2d:
1474 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1475 break;
1476 case nir_op_d2f:
1477 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1478 break;
1479 case nir_op_bcsel:
1480 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1481 break;
1482 case nir_op_find_lsb:
1483 result = emit_find_lsb(ctx, src[0]);
1484 break;
1485 case nir_op_ufind_msb:
1486 result = emit_ufind_msb(ctx, src[0]);
1487 break;
1488 case nir_op_ifind_msb:
1489 result = emit_ifind_msb(ctx, src[0]);
1490 break;
1491 case nir_op_uadd_carry:
1492 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1493 break;
1494 case nir_op_usub_borrow:
1495 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1496 break;
1497 case nir_op_b2f:
1498 result = emit_b2f(ctx, src[0]);
1499 break;
1500 case nir_op_fquantize2f16:
1501 src[0] = to_float(ctx, src[0]);
1502 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1503 /* need to convert back up to f32 */
1504 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1505 break;
1506 case nir_op_umul_high:
1507 result = emit_umul_high(ctx, src[0], src[1]);
1508 break;
1509 case nir_op_imul_high:
1510 result = emit_imul_high(ctx, src[0], src[1]);
1511 break;
1512 case nir_op_pack_half_2x16:
1513 result = emit_pack_half_2x16(ctx, src[0]);
1514 break;
1515 case nir_op_unpack_half_2x16:
1516 result = emit_unpack_half_2x16(ctx, src[0]);
1517 break;
1518 case nir_op_fddx:
1519 case nir_op_fddy:
1520 case nir_op_fddx_fine:
1521 case nir_op_fddy_fine:
1522 case nir_op_fddx_coarse:
1523 case nir_op_fddy_coarse:
1524 result = emit_ddxy(ctx, instr->op, src[0]);
1525 break;
1526 default:
1527 fprintf(stderr, "Unknown NIR alu instr: ");
1528 nir_print_instr(&instr->instr, stderr);
1529 fprintf(stderr, "\n");
1530 abort();
1531 }
1532
1533 if (result) {
1534 assert(instr->dest.dest.is_ssa);
1535 result = to_integer(ctx, result);
1536 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1537 result);
1538 }
1539 }
1540
1541 static void visit_load_const(struct nir_to_llvm_context *ctx,
1542 nir_load_const_instr *instr)
1543 {
1544 LLVMValueRef values[4], value = NULL;
1545 LLVMTypeRef element_type =
1546 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1547
1548 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1549 switch (instr->def.bit_size) {
1550 case 32:
1551 values[i] = LLVMConstInt(element_type,
1552 instr->value.u32[i], false);
1553 break;
1554 case 64:
1555 values[i] = LLVMConstInt(element_type,
1556 instr->value.u64[i], false);
1557 break;
1558 default:
1559 fprintf(stderr,
1560 "unsupported nir load_const bit_size: %d\n",
1561 instr->def.bit_size);
1562 abort();
1563 }
1564 }
1565 if (instr->def.num_components > 1) {
1566 value = LLVMConstVector(values, instr->def.num_components);
1567 } else
1568 value = values[0];
1569
1570 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1571 }
1572
1573 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1574 LLVMTypeRef type)
1575 {
1576 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1577 return LLVMBuildBitCast(ctx->builder, ptr,
1578 LLVMPointerType(type, addr_space), "");
1579 }
1580
1581 static LLVMValueRef
1582 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1583 {
1584 LLVMValueRef size =
1585 LLVMBuildExtractElement(ctx->builder, descriptor,
1586 LLVMConstInt(ctx->i32, 2, false), "");
1587
1588 /* VI only */
1589 if (ctx->options->chip_class >= VI && in_elements) {
1590 /* On VI, the descriptor contains the size in bytes,
1591 * but TXQ must return the size in elements.
1592 * The stride is always non-zero for resources using TXQ.
1593 */
1594 LLVMValueRef stride =
1595 LLVMBuildExtractElement(ctx->builder, descriptor,
1596 LLVMConstInt(ctx->i32, 1, false), "");
1597 stride = LLVMBuildLShr(ctx->builder, stride,
1598 LLVMConstInt(ctx->i32, 16, false), "");
1599 stride = LLVMBuildAnd(ctx->builder, stride,
1600 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1601
1602 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1603 }
1604 return size;
1605 }
1606
1607 /**
1608 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1609 * intrinsic names).
1610 */
1611 static void build_int_type_name(
1612 LLVMTypeRef type,
1613 char *buf, unsigned bufsize)
1614 {
1615 assert(bufsize >= 6);
1616
1617 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1618 snprintf(buf, bufsize, "v%ui32",
1619 LLVMGetVectorSize(type));
1620 else
1621 strcpy(buf, "i32");
1622 }
1623
1624 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1625 struct ac_tex_info *tinfo,
1626 nir_tex_instr *instr,
1627 const char *intr_name,
1628 unsigned coord_vgpr_index)
1629 {
1630 LLVMValueRef coord = tinfo->args[0];
1631 LLVMValueRef half_texel[2];
1632 int c;
1633
1634 //TODO Rect
1635 {
1636 LLVMValueRef txq_args[10];
1637 int txq_arg_count = 0;
1638 LLVMValueRef size;
1639 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1640 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, false);
1641 txq_args[txq_arg_count++] = tinfo->args[1];
1642 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0xf, 0); /* dmask */
1643 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* unorm */
1644 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
1645 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
1646 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
1647 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
1648 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
1649 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
1650 size = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
1651 txq_args, txq_arg_count,
1652 AC_FUNC_ATTR_READNONE);
1653
1654 for (c = 0; c < 2; c++) {
1655 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1656 LLVMConstInt(ctx->i32, c, false), "");
1657 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1658 half_texel[c] = ac_emit_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1659 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1660 LLVMConstReal(ctx->f32, -0.5), "");
1661 }
1662 }
1663
1664 for (c = 0; c < 2; c++) {
1665 LLVMValueRef tmp;
1666 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1667 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1668 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1669 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1670 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1671 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1672 }
1673
1674 tinfo->args[0] = coord;
1675 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1676 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1677
1678 }
1679
1680 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1681 nir_tex_instr *instr,
1682 struct ac_tex_info *tinfo)
1683 {
1684 const char *name = "llvm.SI.image.sample";
1685 const char *infix = "";
1686 char intr_name[127];
1687 char type[64];
1688 bool is_shadow = instr->is_shadow;
1689 bool has_offset = tinfo->has_offset;
1690 switch (instr->op) {
1691 case nir_texop_txf:
1692 case nir_texop_txf_ms:
1693 case nir_texop_samples_identical:
1694 name = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? "llvm.SI.image.load" :
1695 instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? "llvm.SI.vs.load.input" :
1696 "llvm.SI.image.load.mip";
1697 is_shadow = false;
1698 has_offset = false;
1699 break;
1700 case nir_texop_txb:
1701 infix = ".b";
1702 break;
1703 case nir_texop_txl:
1704 infix = ".l";
1705 break;
1706 case nir_texop_txs:
1707 name = "llvm.SI.getresinfo";
1708 break;
1709 case nir_texop_query_levels:
1710 name = "llvm.SI.getresinfo";
1711 break;
1712 case nir_texop_tex:
1713 if (ctx->stage != MESA_SHADER_FRAGMENT)
1714 infix = ".lz";
1715 break;
1716 case nir_texop_txd:
1717 infix = ".d";
1718 break;
1719 case nir_texop_tg4:
1720 name = "llvm.SI.gather4";
1721 infix = ".lz";
1722 break;
1723 case nir_texop_lod:
1724 name = "llvm.SI.getlod";
1725 is_shadow = false;
1726 has_offset = false;
1727 break;
1728 default:
1729 break;
1730 }
1731
1732 build_int_type_name(LLVMTypeOf(tinfo->args[0]), type, sizeof(type));
1733 sprintf(intr_name, "%s%s%s%s.%s", name, is_shadow ? ".c" : "", infix,
1734 has_offset ? ".o" : "", type);
1735
1736 if (instr->op == nir_texop_tg4) {
1737 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1738 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1739 return radv_lower_gather4_integer(ctx, tinfo, instr, intr_name,
1740 (int)has_offset + (int)is_shadow);
1741 }
1742 }
1743 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1744 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1745
1746 }
1747
1748 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1749 nir_intrinsic_instr *instr)
1750 {
1751 LLVMValueRef index = get_src(ctx, instr->src[0]);
1752 unsigned desc_set = nir_intrinsic_desc_set(instr);
1753 unsigned binding = nir_intrinsic_binding(instr);
1754 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1755 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
1756 unsigned base_offset = layout->binding[binding].offset;
1757 LLVMValueRef offset, stride;
1758
1759 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1760 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1761 desc_ptr = ctx->push_constants;
1762 base_offset = ctx->options->layout->push_constant_size;
1763 base_offset += 16 * layout->binding[binding].dynamic_offset_offset;
1764 stride = LLVMConstInt(ctx->i32, 16, false);
1765 } else
1766 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1767
1768 offset = LLVMConstInt(ctx->i32, base_offset, false);
1769 index = LLVMBuildMul(ctx->builder, index, stride, "");
1770 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1771
1772 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1773 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1774 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1775
1776 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1777 }
1778
1779 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1780 nir_intrinsic_instr *instr)
1781 {
1782 LLVMValueRef ptr, addr;
1783
1784 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1785 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1786
1787 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
1788 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1789
1790 return LLVMBuildLoad(ctx->builder, ptr, "");
1791 }
1792
1793 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1794 nir_intrinsic_instr *instr)
1795 {
1796 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1797
1798 return get_buffer_size(ctx, desc, false);
1799 }
1800 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1801 nir_intrinsic_instr *instr)
1802 {
1803 const char *store_name;
1804 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
1805 LLVMTypeRef data_type = ctx->f32;
1806 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
1807 int components_32bit = elem_size_mult * instr->num_components;
1808 unsigned writemask = nir_intrinsic_write_mask(instr);
1809 LLVMValueRef base_data, base_offset;
1810 LLVMValueRef params[6];
1811
1812 if (ctx->stage == MESA_SHADER_FRAGMENT)
1813 ctx->shader_info->fs.writes_memory = true;
1814
1815 params[1] = get_src(ctx, instr->src[1]);
1816 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1817 params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
1818 params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1819
1820 if (components_32bit > 1)
1821 data_type = LLVMVectorType(ctx->f32, components_32bit);
1822
1823 base_data = to_float(ctx, src_data);
1824 base_data = trim_vector(ctx, base_data, instr->num_components);
1825 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1826 data_type, "");
1827 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1828 while (writemask) {
1829 int start, count;
1830 LLVMValueRef data;
1831 LLVMValueRef offset;
1832 LLVMValueRef tmp;
1833 u_bit_scan_consecutive_range(&writemask, &start, &count);
1834
1835 /* Due to an LLVM limitation, split 3-element writes
1836 * into a 2-element and a 1-element write. */
1837 if (count == 3) {
1838 writemask |= 1 << (start + 2);
1839 count = 2;
1840 }
1841
1842 start *= elem_size_mult;
1843 count *= elem_size_mult;
1844
1845 if (count > 4) {
1846 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
1847 count = 4;
1848 }
1849
1850 if (count == 4) {
1851 store_name = "llvm.amdgcn.buffer.store.v4f32";
1852 data = base_data;
1853 } else if (count == 2) {
1854 tmp = LLVMBuildExtractElement(ctx->builder,
1855 base_data, LLVMConstInt(ctx->i32, start, false), "");
1856 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
1857 ctx->i32zero, "");
1858
1859 tmp = LLVMBuildExtractElement(ctx->builder,
1860 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
1861 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
1862 ctx->i32one, "");
1863 store_name = "llvm.amdgcn.buffer.store.v2f32";
1864
1865 } else {
1866 assert(count == 1);
1867 if (get_llvm_num_components(base_data) > 1)
1868 data = LLVMBuildExtractElement(ctx->builder, base_data,
1869 LLVMConstInt(ctx->i32, start, false), "");
1870 else
1871 data = base_data;
1872 store_name = "llvm.amdgcn.buffer.store.f32";
1873 }
1874
1875 offset = base_offset;
1876 if (start != 0) {
1877 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
1878 }
1879 params[0] = data;
1880 params[3] = offset;
1881 ac_emit_llvm_intrinsic(&ctx->ac, store_name,
1882 ctx->voidt, params, 6, 0);
1883 }
1884 }
1885
1886 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
1887 nir_intrinsic_instr *instr)
1888 {
1889 const char *name;
1890 LLVMValueRef params[6];
1891 int arg_count = 0;
1892 if (ctx->stage == MESA_SHADER_FRAGMENT)
1893 ctx->shader_info->fs.writes_memory = true;
1894
1895 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
1896 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
1897 }
1898 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
1899 params[arg_count++] = get_src(ctx, instr->src[0]);
1900 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1901 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
1902 params[arg_count++] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1903
1904 switch (instr->intrinsic) {
1905 case nir_intrinsic_ssbo_atomic_add:
1906 name = "llvm.amdgcn.buffer.atomic.add";
1907 break;
1908 case nir_intrinsic_ssbo_atomic_imin:
1909 name = "llvm.amdgcn.buffer.atomic.smin";
1910 break;
1911 case nir_intrinsic_ssbo_atomic_umin:
1912 name = "llvm.amdgcn.buffer.atomic.umin";
1913 break;
1914 case nir_intrinsic_ssbo_atomic_imax:
1915 name = "llvm.amdgcn.buffer.atomic.smax";
1916 break;
1917 case nir_intrinsic_ssbo_atomic_umax:
1918 name = "llvm.amdgcn.buffer.atomic.umax";
1919 break;
1920 case nir_intrinsic_ssbo_atomic_and:
1921 name = "llvm.amdgcn.buffer.atomic.and";
1922 break;
1923 case nir_intrinsic_ssbo_atomic_or:
1924 name = "llvm.amdgcn.buffer.atomic.or";
1925 break;
1926 case nir_intrinsic_ssbo_atomic_xor:
1927 name = "llvm.amdgcn.buffer.atomic.xor";
1928 break;
1929 case nir_intrinsic_ssbo_atomic_exchange:
1930 name = "llvm.amdgcn.buffer.atomic.swap";
1931 break;
1932 case nir_intrinsic_ssbo_atomic_comp_swap:
1933 name = "llvm.amdgcn.buffer.atomic.cmpswap";
1934 break;
1935 default:
1936 abort();
1937 }
1938
1939 return ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
1940 }
1941
1942 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
1943 nir_intrinsic_instr *instr)
1944 {
1945 LLVMValueRef results[2];
1946 int load_components;
1947 int num_components = instr->num_components;
1948 if (instr->dest.ssa.bit_size == 64)
1949 num_components *= 2;
1950
1951 for (int i = 0; i < num_components; i += load_components) {
1952 load_components = MIN2(num_components - i, 4);
1953 const char *load_name;
1954 LLVMTypeRef data_type = ctx->f32;
1955 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
1956 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
1957
1958 if (load_components == 3)
1959 data_type = LLVMVectorType(ctx->f32, 4);
1960 else if (load_components > 1)
1961 data_type = LLVMVectorType(ctx->f32, load_components);
1962
1963 if (load_components >= 3)
1964 load_name = "llvm.amdgcn.buffer.load.v4f32";
1965 else if (load_components == 2)
1966 load_name = "llvm.amdgcn.buffer.load.v2f32";
1967 else if (load_components == 1)
1968 load_name = "llvm.amdgcn.buffer.load.f32";
1969 else
1970 unreachable("unhandled number of components");
1971
1972 LLVMValueRef params[] = {
1973 get_src(ctx, instr->src[0]),
1974 LLVMConstInt(ctx->i32, 0, false),
1975 offset,
1976 LLVMConstInt(ctx->i1, 0, false),
1977 LLVMConstInt(ctx->i1, 0, false),
1978 };
1979
1980 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
1981
1982 }
1983
1984 LLVMValueRef ret = results[0];
1985 if (num_components > 4 || num_components == 3) {
1986 LLVMValueRef masks[] = {
1987 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1988 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
1989 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
1990 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
1991 };
1992
1993 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1994 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
1995 results[num_components > 4 ? 1 : 0], swizzle, "");
1996 }
1997
1998 return LLVMBuildBitCast(ctx->builder, ret,
1999 get_def_type(ctx, &instr->dest.ssa), "");
2000 }
2001
2002 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2003 nir_intrinsic_instr *instr)
2004 {
2005 LLVMValueRef results[8], ret;
2006 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2007 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2008 int num_components = instr->num_components;
2009
2010 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2011
2012 if (instr->dest.ssa.bit_size == 64)
2013 num_components *= 2;
2014
2015 for (unsigned i = 0; i < num_components; ++i) {
2016 LLVMValueRef params[] = {
2017 rsrc,
2018 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2019 offset, "")
2020 };
2021 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2022 params, 2, AC_FUNC_ATTR_READNONE);
2023 }
2024
2025
2026 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2027 return LLVMBuildBitCast(ctx->builder, ret,
2028 get_def_type(ctx, &instr->dest.ssa), "");
2029 }
2030
2031 static void
2032 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2033 bool vs_in, unsigned *vertex_index_out,
2034 unsigned *const_out, LLVMValueRef *indir_out)
2035 {
2036 unsigned const_offset = 0;
2037 LLVMValueRef offset = NULL;
2038
2039 if (vertex_index_out != NULL) {
2040 tail = tail->child;
2041 nir_deref_array *deref_array = nir_deref_as_array(tail);
2042 *vertex_index_out = deref_array->base_offset;
2043 }
2044
2045 while (tail->child != NULL) {
2046 const struct glsl_type *parent_type = tail->type;
2047 tail = tail->child;
2048
2049 if (tail->deref_type == nir_deref_type_array) {
2050 nir_deref_array *deref_array = nir_deref_as_array(tail);
2051 LLVMValueRef index, stride, local_offset;
2052 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2053
2054 const_offset += size * deref_array->base_offset;
2055 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2056 continue;
2057
2058 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2059 index = get_src(ctx, deref_array->indirect);
2060 stride = LLVMConstInt(ctx->i32, size, 0);
2061 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2062
2063 if (offset)
2064 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2065 else
2066 offset = local_offset;
2067 } else if (tail->deref_type == nir_deref_type_struct) {
2068 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2069
2070 for (unsigned i = 0; i < deref_struct->index; i++) {
2071 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2072 const_offset += glsl_count_attribute_slots(ft, vs_in);
2073 }
2074 } else
2075 unreachable("unsupported deref type");
2076
2077 }
2078
2079 if (const_offset && offset)
2080 offset = LLVMBuildAdd(ctx->builder, offset,
2081 LLVMConstInt(ctx->i32, const_offset, 0),
2082 "");
2083
2084 *const_out = const_offset;
2085 *indir_out = offset;
2086 }
2087
2088 static LLVMValueRef
2089 load_gs_input(struct nir_to_llvm_context *ctx,
2090 nir_intrinsic_instr *instr)
2091 {
2092 LLVMValueRef indir_index, vtx_offset;
2093 unsigned const_index;
2094 LLVMValueRef args[9];
2095 unsigned param, vtx_offset_param;
2096 LLVMValueRef value[4], result;
2097 unsigned vertex_index;
2098 unsigned cull_offset = 0;
2099 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2100 false, &vertex_index,
2101 &const_index, &indir_index);
2102 vtx_offset_param = vertex_index;
2103 assert(vtx_offset_param < 6);
2104 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2105 LLVMConstInt(ctx->i32, 4, false), "");
2106
2107 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2108 if (instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2109 cull_offset += ctx->num_input_clips;
2110 for (unsigned i = 0; i < instr->num_components; i++) {
2111
2112 args[0] = ctx->esgs_ring;
2113 args[1] = vtx_offset;
2114 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index + cull_offset) * 256, false);
2115 args[3] = ctx->i32zero;
2116 args[4] = ctx->i32one; /* OFFEN */
2117 args[5] = ctx->i32zero; /* IDXEN */
2118 args[6] = ctx->i32one; /* GLC */
2119 args[7] = ctx->i32zero; /* SLC */
2120 args[8] = ctx->i32zero; /* TFE */
2121
2122 value[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2123 ctx->i32, args, 9, AC_FUNC_ATTR_READONLY);
2124 }
2125 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2126
2127 return result;
2128 }
2129
2130 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2131 nir_intrinsic_instr *instr)
2132 {
2133 LLVMValueRef values[8];
2134 int idx = instr->variables[0]->var->data.driver_location;
2135 int ve = instr->dest.ssa.num_components;
2136 LLVMValueRef indir_index;
2137 LLVMValueRef ret;
2138 unsigned const_index;
2139 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2140 instr->variables[0]->var->data.mode == nir_var_shader_in;
2141 radv_get_deref_offset(ctx, &instr->variables[0]->deref, vs_in, NULL,
2142 &const_index, &indir_index);
2143
2144 if (instr->dest.ssa.bit_size == 64)
2145 ve *= 2;
2146
2147 switch (instr->variables[0]->var->data.mode) {
2148 case nir_var_shader_in:
2149 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2150 return load_gs_input(ctx, instr);
2151 }
2152 for (unsigned chan = 0; chan < ve; chan++) {
2153 if (indir_index) {
2154 unsigned count = glsl_count_attribute_slots(
2155 instr->variables[0]->var->type,
2156 ctx->stage == MESA_SHADER_VERTEX);
2157 count -= chan / 4;
2158 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2159 &ctx->ac, ctx->inputs + idx + chan, count,
2160 4, false);
2161
2162 values[chan] = LLVMBuildExtractElement(ctx->builder,
2163 tmp_vec,
2164 indir_index, "");
2165 } else
2166 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2167 }
2168 break;
2169 case nir_var_local:
2170 for (unsigned chan = 0; chan < ve; chan++) {
2171 if (indir_index) {
2172 unsigned count = glsl_count_attribute_slots(
2173 instr->variables[0]->var->type, false);
2174 count -= chan / 4;
2175 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2176 &ctx->ac, ctx->locals + idx + chan, count,
2177 4, true);
2178
2179 values[chan] = LLVMBuildExtractElement(ctx->builder,
2180 tmp_vec,
2181 indir_index, "");
2182 } else {
2183 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2184 }
2185 }
2186 break;
2187 case nir_var_shader_out:
2188 for (unsigned chan = 0; chan < ve; chan++) {
2189 if (indir_index) {
2190 unsigned count = glsl_count_attribute_slots(
2191 instr->variables[0]->var->type, false);
2192 count -= chan / 4;
2193 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2194 &ctx->ac, ctx->outputs + idx + chan, count,
2195 4, true);
2196
2197 values[chan] = LLVMBuildExtractElement(ctx->builder,
2198 tmp_vec,
2199 indir_index, "");
2200 } else {
2201 values[chan] = LLVMBuildLoad(ctx->builder,
2202 ctx->outputs[idx + chan + const_index * 4],
2203 "");
2204 }
2205 }
2206 break;
2207 case nir_var_shared: {
2208 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2209 LLVMValueRef derived_ptr;
2210
2211 if (indir_index)
2212 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2213
2214 for (unsigned chan = 0; chan < ve; chan++) {
2215 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2216 if (indir_index)
2217 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2218 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2219
2220 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2221 }
2222 break;
2223 }
2224 default:
2225 unreachable("unhandle variable mode");
2226 }
2227 ret = ac_build_gather_values(&ctx->ac, values, ve);
2228 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2229 }
2230
2231 static void
2232 visit_store_var(struct nir_to_llvm_context *ctx,
2233 nir_intrinsic_instr *instr)
2234 {
2235 LLVMValueRef temp_ptr, value;
2236 int idx = instr->variables[0]->var->data.driver_location;
2237 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2238 int writemask = instr->const_index[0];
2239 LLVMValueRef indir_index;
2240 unsigned const_index;
2241 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2242 NULL, &const_index, &indir_index);
2243
2244 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2245 int old_writemask = writemask;
2246
2247 src = LLVMBuildBitCast(ctx->builder, src,
2248 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2249 "");
2250
2251 writemask = 0;
2252 for (unsigned chan = 0; chan < 4; chan++) {
2253 if (old_writemask & (1 << chan))
2254 writemask |= 3u << (2 * chan);
2255 }
2256 }
2257
2258 switch (instr->variables[0]->var->data.mode) {
2259 case nir_var_shader_out:
2260 for (unsigned chan = 0; chan < 8; chan++) {
2261 int stride = 4;
2262 if (!(writemask & (1 << chan)))
2263 continue;
2264
2265 value = llvm_extract_elem(ctx, src, chan);
2266
2267 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2268 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2269 stride = 1;
2270 if (indir_index) {
2271 unsigned count = glsl_count_attribute_slots(
2272 instr->variables[0]->var->type, false);
2273 count -= chan / 4;
2274 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2275 &ctx->ac, ctx->outputs + idx + chan, count,
2276 stride, true);
2277
2278 if (get_llvm_num_components(tmp_vec) > 1) {
2279 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2280 value, indir_index, "");
2281 } else
2282 tmp_vec = value;
2283 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2284 count, stride, tmp_vec);
2285
2286 } else {
2287 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2288
2289 LLVMBuildStore(ctx->builder, value, temp_ptr);
2290 }
2291 }
2292 break;
2293 case nir_var_local:
2294 for (unsigned chan = 0; chan < 8; chan++) {
2295 if (!(writemask & (1 << chan)))
2296 continue;
2297
2298 value = llvm_extract_elem(ctx, src, chan);
2299 if (indir_index) {
2300 unsigned count = glsl_count_attribute_slots(
2301 instr->variables[0]->var->type, false);
2302 count -= chan / 4;
2303 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2304 &ctx->ac, ctx->locals + idx + chan, count,
2305 4, true);
2306
2307 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2308 value, indir_index, "");
2309 build_store_values_extended(ctx, ctx->locals + idx + chan,
2310 count, 4, tmp_vec);
2311 } else {
2312 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2313
2314 LLVMBuildStore(ctx->builder, value, temp_ptr);
2315 }
2316 }
2317 break;
2318 case nir_var_shared: {
2319 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2320
2321 if (indir_index)
2322 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2323
2324 for (unsigned chan = 0; chan < 8; chan++) {
2325 if (!(writemask & (1 << chan)))
2326 continue;
2327 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2328 LLVMValueRef derived_ptr;
2329
2330 if (indir_index)
2331 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2332
2333 value = llvm_extract_elem(ctx, src, chan);
2334 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2335 LLVMBuildStore(ctx->builder,
2336 to_integer(ctx, value), derived_ptr);
2337 }
2338 break;
2339 }
2340 default:
2341 break;
2342 }
2343 }
2344
2345 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2346 {
2347 switch (dim) {
2348 case GLSL_SAMPLER_DIM_BUF:
2349 return 1;
2350 case GLSL_SAMPLER_DIM_1D:
2351 return array ? 2 : 1;
2352 case GLSL_SAMPLER_DIM_2D:
2353 return array ? 3 : 2;
2354 case GLSL_SAMPLER_DIM_MS:
2355 return array ? 4 : 3;
2356 case GLSL_SAMPLER_DIM_3D:
2357 case GLSL_SAMPLER_DIM_CUBE:
2358 return 3;
2359 case GLSL_SAMPLER_DIM_RECT:
2360 case GLSL_SAMPLER_DIM_SUBPASS:
2361 return 2;
2362 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2363 return 3;
2364 default:
2365 break;
2366 }
2367 return 0;
2368 }
2369
2370
2371 static void build_type_name_for_intr(
2372 LLVMTypeRef type,
2373 char *buf, unsigned bufsize)
2374 {
2375 LLVMTypeRef elem_type = type;
2376
2377 assert(bufsize >= 8);
2378
2379 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
2380 int ret = snprintf(buf, bufsize, "v%u",
2381 LLVMGetVectorSize(type));
2382 if (ret < 0) {
2383 char *type_name = LLVMPrintTypeToString(type);
2384 fprintf(stderr, "Error building type name for: %s\n",
2385 type_name);
2386 return;
2387 }
2388 elem_type = LLVMGetElementType(type);
2389 buf += ret;
2390 bufsize -= ret;
2391 }
2392 switch (LLVMGetTypeKind(elem_type)) {
2393 default: break;
2394 case LLVMIntegerTypeKind:
2395 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
2396 break;
2397 case LLVMFloatTypeKind:
2398 snprintf(buf, bufsize, "f32");
2399 break;
2400 case LLVMDoubleTypeKind:
2401 snprintf(buf, bufsize, "f64");
2402 break;
2403 }
2404 }
2405
2406 static void get_image_intr_name(const char *base_name,
2407 LLVMTypeRef data_type,
2408 LLVMTypeRef coords_type,
2409 LLVMTypeRef rsrc_type,
2410 char *out_name, unsigned out_len)
2411 {
2412 char coords_type_name[8];
2413
2414 build_type_name_for_intr(coords_type, coords_type_name,
2415 sizeof(coords_type_name));
2416
2417 if (HAVE_LLVM <= 0x0309) {
2418 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
2419 } else {
2420 char data_type_name[8];
2421 char rsrc_type_name[8];
2422
2423 build_type_name_for_intr(data_type, data_type_name,
2424 sizeof(data_type_name));
2425 build_type_name_for_intr(rsrc_type, rsrc_type_name,
2426 sizeof(rsrc_type_name));
2427 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
2428 data_type_name, coords_type_name, rsrc_type_name);
2429 }
2430 }
2431
2432 /* Adjust the sample index according to FMASK.
2433 *
2434 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2435 * which is the identity mapping. Each nibble says which physical sample
2436 * should be fetched to get that sample.
2437 *
2438 * For example, 0x11111100 means there are only 2 samples stored and
2439 * the second sample covers 3/4 of the pixel. When reading samples 0
2440 * and 1, return physical sample 0 (determined by the first two 0s
2441 * in FMASK), otherwise return physical sample 1.
2442 *
2443 * The sample index should be adjusted as follows:
2444 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2445 */
2446 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
2447 LLVMValueRef coord_x, LLVMValueRef coord_y,
2448 LLVMValueRef coord_z,
2449 LLVMValueRef sample_index,
2450 LLVMValueRef fmask_desc_ptr)
2451 {
2452 LLVMValueRef fmask_load_address[4], params[7];
2453 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2454 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2455 LLVMValueRef da = coord_z ? ctx->i32one : ctx->i32zero;
2456 LLVMValueRef res;
2457 char intrinsic_name[64];
2458
2459 fmask_load_address[0] = coord_x;
2460 fmask_load_address[1] = coord_y;
2461 if (coord_z) {
2462 fmask_load_address[2] = coord_z;
2463 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
2464 }
2465
2466 params[0] = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
2467 params[1] = fmask_desc_ptr;
2468 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2469 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2470 params[3] = glc;
2471 params[4] = slc;
2472 params[5] = lwe;
2473 params[6] = da;
2474
2475 get_image_intr_name("llvm.amdgcn.image.load",
2476 ctx->v4f32, /* vdata */
2477 LLVMTypeOf(params[0]), /* coords */
2478 LLVMTypeOf(params[1]), /* rsrc */
2479 intrinsic_name, sizeof(intrinsic_name));
2480
2481 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2482 params, 7, AC_FUNC_ATTR_READONLY);
2483
2484 res = to_integer(ctx, res);
2485 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
2486 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
2487
2488 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
2489 res,
2490 ctx->i32zero, "");
2491
2492 LLVMValueRef sample_index4 =
2493 LLVMBuildMul(ctx->builder, sample_index, four, "");
2494 LLVMValueRef shifted_fmask =
2495 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
2496 LLVMValueRef final_sample =
2497 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
2498
2499 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2500 * resource descriptor is 0 (invalid),
2501 */
2502 LLVMValueRef fmask_desc =
2503 LLVMBuildBitCast(ctx->builder, params[1],
2504 ctx->v8i32, "");
2505
2506 LLVMValueRef fmask_word1 =
2507 LLVMBuildExtractElement(ctx->builder, fmask_desc,
2508 ctx->i32one, "");
2509
2510 LLVMValueRef word1_is_nonzero =
2511 LLVMBuildICmp(ctx->builder, LLVMIntNE,
2512 fmask_word1, ctx->i32zero, "");
2513
2514 /* Replace the MSAA sample index. */
2515 sample_index =
2516 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
2517 final_sample, sample_index, "");
2518 return sample_index;
2519 }
2520
2521 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2522 nir_intrinsic_instr *instr)
2523 {
2524 const struct glsl_type *type = instr->variables[0]->var->type;
2525 if(instr->variables[0]->deref.child)
2526 type = instr->variables[0]->deref.child->type;
2527
2528 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2529 LLVMValueRef coords[4];
2530 LLVMValueRef masks[] = {
2531 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2532 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2533 };
2534 LLVMValueRef res;
2535 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2536
2537 int count;
2538 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2539 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2540 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2541 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2542 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2543
2544 count = image_type_to_components_count(dim,
2545 glsl_sampler_type_is_array(type));
2546
2547 if (is_ms) {
2548 LLVMValueRef fmask_load_address[3];
2549 int chan;
2550
2551 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2552 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
2553 if (glsl_sampler_type_is_array(type))
2554 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
2555 else
2556 fmask_load_address[2] = NULL;
2557 if (add_frag_pos) {
2558 for (chan = 0; chan < 2; ++chan)
2559 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2560 }
2561 sample_index = adjust_sample_index_using_fmask(ctx,
2562 fmask_load_address[0],
2563 fmask_load_address[1],
2564 fmask_load_address[2],
2565 sample_index,
2566 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
2567 }
2568 if (count == 1) {
2569 if (instr->src[0].ssa->num_components)
2570 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2571 else
2572 res = src0;
2573 } else {
2574 int chan;
2575 if (is_ms)
2576 count--;
2577 for (chan = 0; chan < count; ++chan) {
2578 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2579 }
2580
2581 if (add_frag_pos) {
2582 for (chan = 0; chan < count; ++chan)
2583 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2584 }
2585 if (is_ms) {
2586 coords[count] = sample_index;
2587 count++;
2588 }
2589
2590 if (count == 3) {
2591 coords[3] = LLVMGetUndef(ctx->i32);
2592 count = 4;
2593 }
2594 res = ac_build_gather_values(&ctx->ac, coords, count);
2595 }
2596 return res;
2597 }
2598
2599 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2600 nir_intrinsic_instr *instr)
2601 {
2602 LLVMValueRef params[7];
2603 LLVMValueRef res;
2604 char intrinsic_name[64];
2605 const nir_variable *var = instr->variables[0]->var;
2606 const struct glsl_type *type = var->type;
2607 if(instr->variables[0]->deref.child)
2608 type = instr->variables[0]->deref.child->type;
2609
2610 type = glsl_without_array(type);
2611 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2612 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2613 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2614 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2615 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2616 params[3] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2617 params[4] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2618 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2619 params, 5, 0);
2620
2621 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2622 res = to_integer(ctx, res);
2623 } else {
2624 bool is_da = glsl_sampler_type_is_array(type) ||
2625 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2626 LLVMValueRef da = is_da ? ctx->i32one : ctx->i32zero;
2627 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2628 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2629
2630 params[0] = get_image_coords(ctx, instr);
2631 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2632 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2633 if (HAVE_LLVM <= 0x0309) {
2634 params[3] = LLVMConstInt(ctx->i1, 0, false); /* r128 */
2635 params[4] = da;
2636 params[5] = glc;
2637 params[6] = slc;
2638 } else {
2639 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2640 params[3] = glc;
2641 params[4] = slc;
2642 params[5] = lwe;
2643 params[6] = da;
2644 }
2645
2646 get_image_intr_name("llvm.amdgcn.image.load",
2647 ctx->v4f32, /* vdata */
2648 LLVMTypeOf(params[0]), /* coords */
2649 LLVMTypeOf(params[1]), /* rsrc */
2650 intrinsic_name, sizeof(intrinsic_name));
2651
2652 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2653 params, 7, AC_FUNC_ATTR_READONLY);
2654 }
2655 return to_integer(ctx, res);
2656 }
2657
2658 static void visit_image_store(struct nir_to_llvm_context *ctx,
2659 nir_intrinsic_instr *instr)
2660 {
2661 LLVMValueRef params[8];
2662 char intrinsic_name[64];
2663 const nir_variable *var = instr->variables[0]->var;
2664 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2665 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2666 const struct glsl_type *type = glsl_without_array(var->type);
2667
2668 if (ctx->stage == MESA_SHADER_FRAGMENT)
2669 ctx->shader_info->fs.writes_memory = true;
2670
2671 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2672 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2673 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2674 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2675 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2676 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2677 params[4] = i1false; /* glc */
2678 params[5] = i1false; /* slc */
2679 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2680 params, 6, 0);
2681 } else {
2682 bool is_da = glsl_sampler_type_is_array(type) ||
2683 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2684 LLVMValueRef da = is_da ? i1true : i1false;
2685 LLVMValueRef glc = i1false;
2686 LLVMValueRef slc = i1false;
2687
2688 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2689 params[1] = get_image_coords(ctx, instr); /* coords */
2690 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2691 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2692 if (HAVE_LLVM <= 0x0309) {
2693 params[4] = i1false; /* r128 */
2694 params[5] = da;
2695 params[6] = glc;
2696 params[7] = slc;
2697 } else {
2698 LLVMValueRef lwe = i1false;
2699 params[4] = glc;
2700 params[5] = slc;
2701 params[6] = lwe;
2702 params[7] = da;
2703 }
2704
2705 get_image_intr_name("llvm.amdgcn.image.store",
2706 LLVMTypeOf(params[0]), /* vdata */
2707 LLVMTypeOf(params[1]), /* coords */
2708 LLVMTypeOf(params[2]), /* rsrc */
2709 intrinsic_name, sizeof(intrinsic_name));
2710
2711 ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2712 params, 8, 0);
2713 }
2714
2715 }
2716
2717 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2718 nir_intrinsic_instr *instr)
2719 {
2720 LLVMValueRef params[6];
2721 int param_count = 0;
2722 const nir_variable *var = instr->variables[0]->var;
2723 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2724 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2725 const char *base_name = "llvm.amdgcn.image.atomic";
2726 const char *atomic_name;
2727 LLVMValueRef coords;
2728 char intrinsic_name[32], coords_type[8];
2729 const struct glsl_type *type = glsl_without_array(var->type);
2730
2731 if (ctx->stage == MESA_SHADER_FRAGMENT)
2732 ctx->shader_info->fs.writes_memory = true;
2733
2734 params[param_count++] = get_src(ctx, instr->src[2]);
2735 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2736 params[param_count++] = get_src(ctx, instr->src[3]);
2737
2738 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2739 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2740 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2741 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2742 params[param_count++] = ctx->i32zero; /* voffset */
2743 params[param_count++] = i1false; /* glc */
2744 params[param_count++] = i1false; /* slc */
2745 } else {
2746 bool da = glsl_sampler_type_is_array(type) ||
2747 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2748
2749 coords = params[param_count++] = get_image_coords(ctx, instr);
2750 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2751 params[param_count++] = i1false; /* r128 */
2752 params[param_count++] = da ? i1true : i1false; /* da */
2753 params[param_count++] = i1false; /* slc */
2754 }
2755
2756 switch (instr->intrinsic) {
2757 case nir_intrinsic_image_atomic_add:
2758 atomic_name = "add";
2759 break;
2760 case nir_intrinsic_image_atomic_min:
2761 atomic_name = "smin";
2762 break;
2763 case nir_intrinsic_image_atomic_max:
2764 atomic_name = "smax";
2765 break;
2766 case nir_intrinsic_image_atomic_and:
2767 atomic_name = "and";
2768 break;
2769 case nir_intrinsic_image_atomic_or:
2770 atomic_name = "or";
2771 break;
2772 case nir_intrinsic_image_atomic_xor:
2773 atomic_name = "xor";
2774 break;
2775 case nir_intrinsic_image_atomic_exchange:
2776 atomic_name = "swap";
2777 break;
2778 case nir_intrinsic_image_atomic_comp_swap:
2779 atomic_name = "cmpswap";
2780 break;
2781 default:
2782 abort();
2783 }
2784 build_int_type_name(LLVMTypeOf(coords),
2785 coords_type, sizeof(coords_type));
2786
2787 snprintf(intrinsic_name, sizeof(intrinsic_name),
2788 "%s.%s.%s", base_name, atomic_name, coords_type);
2789 return ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2790 }
2791
2792 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2793 nir_intrinsic_instr *instr)
2794 {
2795 LLVMValueRef res;
2796 LLVMValueRef params[10];
2797 const nir_variable *var = instr->variables[0]->var;
2798 const struct glsl_type *type = instr->variables[0]->var->type;
2799 bool da = glsl_sampler_type_is_array(var->type) ||
2800 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2801 if(instr->variables[0]->deref.child)
2802 type = instr->variables[0]->deref.child->type;
2803
2804 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2805 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2806 params[0] = ctx->i32zero;
2807 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2808 params[2] = LLVMConstInt(ctx->i32, 15, false);
2809 params[3] = ctx->i32zero;
2810 params[4] = ctx->i32zero;
2811 params[5] = da ? ctx->i32one : ctx->i32zero;
2812 params[6] = ctx->i32zero;
2813 params[7] = ctx->i32zero;
2814 params[8] = ctx->i32zero;
2815 params[9] = ctx->i32zero;
2816
2817 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
2818 params, 10, AC_FUNC_ATTR_READNONE);
2819
2820 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2821 glsl_sampler_type_is_array(type)) {
2822 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2823 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2824 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2825 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2826 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2827 }
2828 return res;
2829 }
2830
2831 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2832 {
2833 LLVMValueRef args[1] = {
2834 LLVMConstInt(ctx->i32, 0xf70, false),
2835 };
2836 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2837 ctx->voidt, args, 1, 0);
2838 }
2839
2840 static void emit_barrier(struct nir_to_llvm_context *ctx)
2841 {
2842 // TODO tess
2843 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2844 ctx->voidt, NULL, 0, 0);
2845 }
2846
2847 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2848 nir_intrinsic_instr *instr)
2849 {
2850 LLVMValueRef cond;
2851 ctx->shader_info->fs.can_discard = true;
2852
2853 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2854 get_src(ctx, instr->src[0]),
2855 ctx->i32zero, "");
2856
2857 cond = LLVMBuildSelect(ctx->builder, cond,
2858 LLVMConstReal(ctx->f32, -1.0f),
2859 ctx->f32zero, "");
2860 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
2861 ctx->voidt,
2862 &cond, 1, 0);
2863 }
2864
2865 static LLVMValueRef
2866 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2867 {
2868 LLVMValueRef result;
2869 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
2870 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2871 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2872
2873 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2874 }
2875
2876 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2877 nir_intrinsic_instr *instr)
2878 {
2879 LLVMValueRef ptr, result;
2880 int idx = instr->variables[0]->var->data.driver_location;
2881 LLVMValueRef src = get_src(ctx, instr->src[0]);
2882 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2883
2884 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2885 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2886 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2887 ptr, src, src1,
2888 LLVMAtomicOrderingSequentiallyConsistent,
2889 LLVMAtomicOrderingSequentiallyConsistent,
2890 false);
2891 } else {
2892 LLVMAtomicRMWBinOp op;
2893 switch (instr->intrinsic) {
2894 case nir_intrinsic_var_atomic_add:
2895 op = LLVMAtomicRMWBinOpAdd;
2896 break;
2897 case nir_intrinsic_var_atomic_umin:
2898 op = LLVMAtomicRMWBinOpUMin;
2899 break;
2900 case nir_intrinsic_var_atomic_umax:
2901 op = LLVMAtomicRMWBinOpUMax;
2902 break;
2903 case nir_intrinsic_var_atomic_imin:
2904 op = LLVMAtomicRMWBinOpMin;
2905 break;
2906 case nir_intrinsic_var_atomic_imax:
2907 op = LLVMAtomicRMWBinOpMax;
2908 break;
2909 case nir_intrinsic_var_atomic_and:
2910 op = LLVMAtomicRMWBinOpAnd;
2911 break;
2912 case nir_intrinsic_var_atomic_or:
2913 op = LLVMAtomicRMWBinOpOr;
2914 break;
2915 case nir_intrinsic_var_atomic_xor:
2916 op = LLVMAtomicRMWBinOpXor;
2917 break;
2918 case nir_intrinsic_var_atomic_exchange:
2919 op = LLVMAtomicRMWBinOpXchg;
2920 break;
2921 default:
2922 return NULL;
2923 }
2924
2925 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2926 LLVMAtomicOrderingSequentiallyConsistent,
2927 false);
2928 }
2929 return result;
2930 }
2931
2932 #define INTERP_CENTER 0
2933 #define INTERP_CENTROID 1
2934 #define INTERP_SAMPLE 2
2935
2936 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2937 enum glsl_interp_mode interp, unsigned location)
2938 {
2939 switch (interp) {
2940 case INTERP_MODE_FLAT:
2941 default:
2942 return NULL;
2943 case INTERP_MODE_SMOOTH:
2944 case INTERP_MODE_NONE:
2945 if (location == INTERP_CENTER)
2946 return ctx->persp_center;
2947 else if (location == INTERP_CENTROID)
2948 return ctx->persp_centroid;
2949 else if (location == INTERP_SAMPLE)
2950 return ctx->persp_sample;
2951 break;
2952 case INTERP_MODE_NOPERSPECTIVE:
2953 if (location == INTERP_CENTER)
2954 return ctx->linear_center;
2955 else if (location == INTERP_CENTROID)
2956 return ctx->linear_centroid;
2957 else if (location == INTERP_SAMPLE)
2958 return ctx->linear_sample;
2959 break;
2960 }
2961 return NULL;
2962 }
2963
2964 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
2965 LLVMValueRef sample_id)
2966 {
2967 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2968 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
2969 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
2970 LLVMValueRef result[2];
2971
2972 result[0] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset0);
2973 result[1] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset1);
2974
2975 return ac_build_gather_values(&ctx->ac, result, 2);
2976 }
2977
2978 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
2979 {
2980 LLVMValueRef values[2];
2981
2982 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
2983 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
2984 return ac_build_gather_values(&ctx->ac, values, 2);
2985 }
2986
2987 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
2988 nir_intrinsic_instr *instr)
2989 {
2990 LLVMValueRef result[2];
2991 LLVMValueRef interp_param, attr_number;
2992 unsigned location;
2993 unsigned chan;
2994 LLVMValueRef src_c0, src_c1;
2995 LLVMValueRef src0;
2996 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
2997 switch (instr->intrinsic) {
2998 case nir_intrinsic_interp_var_at_centroid:
2999 location = INTERP_CENTROID;
3000 break;
3001 case nir_intrinsic_interp_var_at_sample:
3002 location = INTERP_SAMPLE;
3003 src0 = get_src(ctx, instr->src[0]);
3004 break;
3005 case nir_intrinsic_interp_var_at_offset:
3006 location = INTERP_CENTER;
3007 src0 = get_src(ctx, instr->src[0]);
3008 default:
3009 break;
3010 }
3011
3012 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3013 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3014 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3015 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3016 LLVMValueRef sample_position;
3017 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3018
3019 /* fetch sample ID */
3020 sample_position = load_sample_position(ctx, src0);
3021
3022 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3023 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3024 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3025 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3026 }
3027 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3028 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3029
3030 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3031 LLVMValueRef ij_out[2];
3032 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3033
3034 /*
3035 * take the I then J parameters, and the DDX/Y for it, and
3036 * calculate the IJ inputs for the interpolator.
3037 * temp1 = ddx * offset/sample.x + I;
3038 * interp_param.I = ddy * offset/sample.y + temp1;
3039 * temp1 = ddx * offset/sample.x + J;
3040 * interp_param.J = ddy * offset/sample.y + temp1;
3041 */
3042 for (unsigned i = 0; i < 2; i++) {
3043 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3044 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3045 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3046 ddxy_out, ix_ll, "");
3047 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3048 ddxy_out, iy_ll, "");
3049 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3050 interp_param, ix_ll, "");
3051 LLVMValueRef temp1, temp2;
3052
3053 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3054 ctx->f32, "");
3055
3056 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3057 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3058
3059 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3060 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3061
3062 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3063 temp2, ctx->i32, "");
3064 }
3065 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3066
3067 }
3068
3069 for (chan = 0; chan < 2; chan++) {
3070 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3071
3072 if (interp_param) {
3073 interp_param = LLVMBuildBitCast(ctx->builder,
3074 interp_param, LLVMVectorType(ctx->f32, 2), "");
3075 LLVMValueRef i = LLVMBuildExtractElement(
3076 ctx->builder, interp_param, ctx->i32zero, "");
3077 LLVMValueRef j = LLVMBuildExtractElement(
3078 ctx->builder, interp_param, ctx->i32one, "");
3079
3080 result[chan] = ac_build_fs_interp(&ctx->ac,
3081 llvm_chan, attr_number,
3082 ctx->prim_mask, i, j);
3083 } else {
3084 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3085 LLVMConstInt(ctx->i32, 2, false),
3086 llvm_chan, attr_number,
3087 ctx->prim_mask);
3088 }
3089 }
3090 return ac_build_gather_values(&ctx->ac, result, 2);
3091 }
3092
3093 static void
3094 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3095 nir_intrinsic_instr *instr)
3096 {
3097 LLVMValueRef gs_next_vertex;
3098 LLVMValueRef can_emit, kill;
3099 int idx;
3100 int clip_cull_slot = -1;
3101 assert(instr->const_index[0] == 0);
3102 /* Write vertex attribute values to GSVS ring */
3103 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3104 ctx->gs_next_vertex,
3105 "");
3106
3107 /* If this thread has already emitted the declared maximum number of
3108 * vertices, kill it: excessive vertex emissions are not supposed to
3109 * have any effect, and GS threads have no externally observable
3110 * effects other than emitting vertices.
3111 */
3112 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3113 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3114
3115 kill = LLVMBuildSelect(ctx->builder, can_emit,
3116 LLVMConstReal(ctx->f32, 1.0f),
3117 LLVMConstReal(ctx->f32, -1.0f), "");
3118 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
3119 ctx->voidt, &kill, 1, 0);
3120
3121 /* loop num outputs */
3122 idx = 0;
3123 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3124 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3125 int length = 4;
3126 int start = 0;
3127 int slot = idx;
3128 int slot_inc = 1;
3129
3130 if (!(ctx->output_mask & (1ull << i)))
3131 continue;
3132
3133 if (i == VARYING_SLOT_CLIP_DIST1 ||
3134 i == VARYING_SLOT_CULL_DIST1)
3135 continue;
3136
3137 if (i == VARYING_SLOT_CLIP_DIST0 ||
3138 i == VARYING_SLOT_CULL_DIST0) {
3139 /* pack clip and cull into a single set of slots */
3140 if (clip_cull_slot == -1) {
3141 clip_cull_slot = idx;
3142 if (ctx->num_output_clips + ctx->num_output_culls > 4)
3143 slot_inc = 2;
3144 } else {
3145 slot = clip_cull_slot;
3146 slot_inc = 0;
3147 }
3148 if (i == VARYING_SLOT_CLIP_DIST0)
3149 length = ctx->num_output_clips;
3150 if (i == VARYING_SLOT_CULL_DIST0) {
3151 start = ctx->num_output_clips;
3152 length = ctx->num_output_culls;
3153 }
3154 }
3155 for (unsigned j = 0; j < length; j++) {
3156 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3157 out_ptr[j], "");
3158 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j + start) * ctx->gs_max_out_vertices, false);
3159 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3160 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3161
3162 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3163
3164 ac_build_tbuffer_store(&ctx->ac, ctx->gsvs_ring,
3165 out_val, 1,
3166 voffset, ctx->gs2vs_offset, 0,
3167 V_008F0C_BUF_DATA_FORMAT_32,
3168 V_008F0C_BUF_NUM_FORMAT_UINT,
3169 1, 0, 1, 1, 0);
3170 }
3171 idx += slot_inc;
3172 }
3173
3174 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3175 ctx->i32one, "");
3176 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3177
3178 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3179 }
3180
3181 static void
3182 visit_end_primitive(struct nir_to_llvm_context *ctx,
3183 nir_intrinsic_instr *instr)
3184 {
3185 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3186 }
3187
3188 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3189 nir_intrinsic_instr *instr)
3190 {
3191 LLVMValueRef result = NULL;
3192
3193 switch (instr->intrinsic) {
3194 case nir_intrinsic_load_work_group_id: {
3195 result = ctx->workgroup_ids;
3196 break;
3197 }
3198 case nir_intrinsic_load_base_vertex: {
3199 result = ctx->base_vertex;
3200 break;
3201 }
3202 case nir_intrinsic_load_vertex_id_zero_base: {
3203 result = ctx->vertex_id;
3204 break;
3205 }
3206 case nir_intrinsic_load_local_invocation_id: {
3207 result = ctx->local_invocation_ids;
3208 break;
3209 }
3210 case nir_intrinsic_load_base_instance:
3211 result = ctx->start_instance;
3212 break;
3213 case nir_intrinsic_load_draw_id:
3214 result = ctx->draw_index;
3215 break;
3216 case nir_intrinsic_load_invocation_id:
3217 result = ctx->gs_invocation_id;
3218 break;
3219 case nir_intrinsic_load_primitive_id:
3220 if (ctx->stage == MESA_SHADER_GEOMETRY)
3221 result = ctx->gs_prim_id;
3222 else
3223 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3224 break;
3225 case nir_intrinsic_load_sample_id:
3226 ctx->shader_info->fs.force_persample = true;
3227 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3228 break;
3229 case nir_intrinsic_load_sample_pos:
3230 ctx->shader_info->fs.force_persample = true;
3231 result = load_sample_pos(ctx);
3232 break;
3233 case nir_intrinsic_load_sample_mask_in:
3234 result = ctx->sample_coverage;
3235 break;
3236 case nir_intrinsic_load_front_face:
3237 result = ctx->front_face;
3238 break;
3239 case nir_intrinsic_load_instance_id:
3240 result = ctx->instance_id;
3241 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3242 ctx->shader_info->vs.vgpr_comp_cnt);
3243 break;
3244 case nir_intrinsic_load_num_work_groups:
3245 result = ctx->num_work_groups;
3246 break;
3247 case nir_intrinsic_load_local_invocation_index:
3248 result = visit_load_local_invocation_index(ctx);
3249 break;
3250 case nir_intrinsic_load_push_constant:
3251 result = visit_load_push_constant(ctx, instr);
3252 break;
3253 case nir_intrinsic_vulkan_resource_index:
3254 result = visit_vulkan_resource_index(ctx, instr);
3255 break;
3256 case nir_intrinsic_store_ssbo:
3257 visit_store_ssbo(ctx, instr);
3258 break;
3259 case nir_intrinsic_load_ssbo:
3260 result = visit_load_buffer(ctx, instr);
3261 break;
3262 case nir_intrinsic_ssbo_atomic_add:
3263 case nir_intrinsic_ssbo_atomic_imin:
3264 case nir_intrinsic_ssbo_atomic_umin:
3265 case nir_intrinsic_ssbo_atomic_imax:
3266 case nir_intrinsic_ssbo_atomic_umax:
3267 case nir_intrinsic_ssbo_atomic_and:
3268 case nir_intrinsic_ssbo_atomic_or:
3269 case nir_intrinsic_ssbo_atomic_xor:
3270 case nir_intrinsic_ssbo_atomic_exchange:
3271 case nir_intrinsic_ssbo_atomic_comp_swap:
3272 result = visit_atomic_ssbo(ctx, instr);
3273 break;
3274 case nir_intrinsic_load_ubo:
3275 result = visit_load_ubo_buffer(ctx, instr);
3276 break;
3277 case nir_intrinsic_get_buffer_size:
3278 result = visit_get_buffer_size(ctx, instr);
3279 break;
3280 case nir_intrinsic_load_var:
3281 result = visit_load_var(ctx, instr);
3282 break;
3283 case nir_intrinsic_store_var:
3284 visit_store_var(ctx, instr);
3285 break;
3286 case nir_intrinsic_image_load:
3287 result = visit_image_load(ctx, instr);
3288 break;
3289 case nir_intrinsic_image_store:
3290 visit_image_store(ctx, instr);
3291 break;
3292 case nir_intrinsic_image_atomic_add:
3293 case nir_intrinsic_image_atomic_min:
3294 case nir_intrinsic_image_atomic_max:
3295 case nir_intrinsic_image_atomic_and:
3296 case nir_intrinsic_image_atomic_or:
3297 case nir_intrinsic_image_atomic_xor:
3298 case nir_intrinsic_image_atomic_exchange:
3299 case nir_intrinsic_image_atomic_comp_swap:
3300 result = visit_image_atomic(ctx, instr);
3301 break;
3302 case nir_intrinsic_image_size:
3303 result = visit_image_size(ctx, instr);
3304 break;
3305 case nir_intrinsic_discard:
3306 ctx->shader_info->fs.can_discard = true;
3307 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3308 ctx->voidt,
3309 NULL, 0, 0);
3310 break;
3311 case nir_intrinsic_discard_if:
3312 emit_discard_if(ctx, instr);
3313 break;
3314 case nir_intrinsic_memory_barrier:
3315 emit_waitcnt(ctx);
3316 break;
3317 case nir_intrinsic_barrier:
3318 emit_barrier(ctx);
3319 break;
3320 case nir_intrinsic_var_atomic_add:
3321 case nir_intrinsic_var_atomic_imin:
3322 case nir_intrinsic_var_atomic_umin:
3323 case nir_intrinsic_var_atomic_imax:
3324 case nir_intrinsic_var_atomic_umax:
3325 case nir_intrinsic_var_atomic_and:
3326 case nir_intrinsic_var_atomic_or:
3327 case nir_intrinsic_var_atomic_xor:
3328 case nir_intrinsic_var_atomic_exchange:
3329 case nir_intrinsic_var_atomic_comp_swap:
3330 result = visit_var_atomic(ctx, instr);
3331 break;
3332 case nir_intrinsic_interp_var_at_centroid:
3333 case nir_intrinsic_interp_var_at_sample:
3334 case nir_intrinsic_interp_var_at_offset:
3335 result = visit_interp(ctx, instr);
3336 break;
3337 case nir_intrinsic_emit_vertex:
3338 visit_emit_vertex(ctx, instr);
3339 break;
3340 case nir_intrinsic_end_primitive:
3341 visit_end_primitive(ctx, instr);
3342 break;
3343 default:
3344 fprintf(stderr, "Unknown intrinsic: ");
3345 nir_print_instr(&instr->instr, stderr);
3346 fprintf(stderr, "\n");
3347 break;
3348 }
3349 if (result) {
3350 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3351 }
3352 }
3353
3354 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3355 nir_deref_var *deref,
3356 enum desc_type desc_type)
3357 {
3358 unsigned desc_set = deref->var->data.descriptor_set;
3359 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3360 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3361 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3362 unsigned offset = binding->offset;
3363 unsigned stride = binding->size;
3364 unsigned type_size;
3365 LLVMBuilderRef builder = ctx->builder;
3366 LLVMTypeRef type;
3367 LLVMValueRef index = NULL;
3368
3369 assert(deref->var->data.binding < layout->binding_count);
3370
3371 switch (desc_type) {
3372 case DESC_IMAGE:
3373 type = ctx->v8i32;
3374 type_size = 32;
3375 break;
3376 case DESC_FMASK:
3377 type = ctx->v8i32;
3378 offset += 32;
3379 type_size = 32;
3380 break;
3381 case DESC_SAMPLER:
3382 type = ctx->v4i32;
3383 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3384 offset += 64;
3385
3386 type_size = 16;
3387 break;
3388 case DESC_BUFFER:
3389 type = ctx->v4i32;
3390 type_size = 16;
3391 break;
3392 default:
3393 unreachable("invalid desc_type\n");
3394 }
3395
3396 if (deref->deref.child) {
3397 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3398
3399 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3400 offset += child->base_offset * stride;
3401 if (child->deref_array_type == nir_deref_array_type_indirect) {
3402 index = get_src(ctx, child->indirect);
3403 }
3404 }
3405
3406 assert(stride % type_size == 0);
3407
3408 if (!index)
3409 index = ctx->i32zero;
3410
3411 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3412
3413 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
3414 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3415
3416 return ac_build_indexed_load_const(&ctx->ac, list, index);
3417 }
3418
3419 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3420 struct ac_tex_info *tinfo,
3421 nir_tex_instr *instr,
3422 nir_texop op,
3423 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3424 LLVMValueRef *param, unsigned count,
3425 unsigned dmask)
3426 {
3427 int num_args;
3428 unsigned is_rect = 0;
3429 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3430
3431 if (op == nir_texop_lod)
3432 da = false;
3433 /* Pad to power of two vector */
3434 while (count < util_next_power_of_two(count))
3435 param[count++] = LLVMGetUndef(ctx->i32);
3436
3437 if (count > 1)
3438 tinfo->args[0] = ac_build_gather_values(&ctx->ac, param, count);
3439 else
3440 tinfo->args[0] = param[0];
3441
3442 tinfo->args[1] = res_ptr;
3443 num_args = 2;
3444
3445 if (op == nir_texop_txf ||
3446 op == nir_texop_txf_ms ||
3447 op == nir_texop_query_levels ||
3448 op == nir_texop_texture_samples ||
3449 op == nir_texop_txs)
3450 tinfo->dst_type = ctx->v4i32;
3451 else {
3452 tinfo->dst_type = ctx->v4f32;
3453 tinfo->args[num_args++] = samp_ptr;
3454 }
3455
3456 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3457 tinfo->args[0] = res_ptr;
3458 tinfo->args[1] = LLVMConstInt(ctx->i32, 0, false);
3459 tinfo->args[2] = param[0];
3460 tinfo->arg_count = 3;
3461 return;
3462 }
3463
3464 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, dmask, 0);
3465 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, is_rect, 0); /* unorm */
3466 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
3467 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
3468 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
3469 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
3470 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
3471 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
3472
3473 tinfo->arg_count = num_args;
3474 }
3475
3476 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3477 *
3478 * SI-CI:
3479 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3480 * filtering manually. The driver sets img7 to a mask clearing
3481 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3482 * s_and_b32 samp0, samp0, img7
3483 *
3484 * VI:
3485 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3486 */
3487 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3488 LLVMValueRef res, LLVMValueRef samp)
3489 {
3490 LLVMBuilderRef builder = ctx->builder;
3491 LLVMValueRef img7, samp0;
3492
3493 if (ctx->options->chip_class >= VI)
3494 return samp;
3495
3496 img7 = LLVMBuildExtractElement(builder, res,
3497 LLVMConstInt(ctx->i32, 7, 0), "");
3498 samp0 = LLVMBuildExtractElement(builder, samp,
3499 LLVMConstInt(ctx->i32, 0, 0), "");
3500 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3501 return LLVMBuildInsertElement(builder, samp, samp0,
3502 LLVMConstInt(ctx->i32, 0, 0), "");
3503 }
3504
3505 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3506 nir_tex_instr *instr,
3507 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3508 LLVMValueRef *fmask_ptr)
3509 {
3510 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3511 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3512 else
3513 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3514 if (samp_ptr) {
3515 if (instr->sampler)
3516 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3517 else
3518 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3519 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3520 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3521 }
3522 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3523 instr->op == nir_texop_samples_identical))
3524 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3525 }
3526
3527 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
3528 LLVMValueRef coord)
3529 {
3530 coord = to_float(ctx, coord);
3531 coord = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
3532 coord = to_integer(ctx, coord);
3533 return coord;
3534 }
3535
3536 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3537 {
3538 LLVMValueRef result = NULL;
3539 struct ac_tex_info tinfo = { 0 };
3540 unsigned dmask = 0xf;
3541 LLVMValueRef address[16];
3542 LLVMValueRef coords[5];
3543 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3544 LLVMValueRef bias = NULL, offsets = NULL;
3545 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3546 LLVMValueRef ddx = NULL, ddy = NULL;
3547 LLVMValueRef derivs[6];
3548 unsigned chan, count = 0;
3549 unsigned const_src = 0, num_deriv_comp = 0;
3550
3551 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3552
3553 for (unsigned i = 0; i < instr->num_srcs; i++) {
3554 switch (instr->src[i].src_type) {
3555 case nir_tex_src_coord:
3556 coord = get_src(ctx, instr->src[i].src);
3557 break;
3558 case nir_tex_src_projector:
3559 break;
3560 case nir_tex_src_comparator:
3561 comparator = get_src(ctx, instr->src[i].src);
3562 break;
3563 case nir_tex_src_offset:
3564 offsets = get_src(ctx, instr->src[i].src);
3565 const_src = i;
3566 break;
3567 case nir_tex_src_bias:
3568 bias = get_src(ctx, instr->src[i].src);
3569 break;
3570 case nir_tex_src_lod:
3571 lod = get_src(ctx, instr->src[i].src);
3572 break;
3573 case nir_tex_src_ms_index:
3574 sample_index = get_src(ctx, instr->src[i].src);
3575 break;
3576 case nir_tex_src_ms_mcs:
3577 break;
3578 case nir_tex_src_ddx:
3579 ddx = get_src(ctx, instr->src[i].src);
3580 num_deriv_comp = instr->src[i].src.ssa->num_components;
3581 break;
3582 case nir_tex_src_ddy:
3583 ddy = get_src(ctx, instr->src[i].src);
3584 break;
3585 case nir_tex_src_texture_offset:
3586 case nir_tex_src_sampler_offset:
3587 case nir_tex_src_plane:
3588 default:
3589 break;
3590 }
3591 }
3592
3593 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3594 result = get_buffer_size(ctx, res_ptr, false);
3595 goto write_result;
3596 }
3597
3598 if (instr->op == nir_texop_texture_samples) {
3599 LLVMValueRef res, samples, is_msaa;
3600 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3601 samples = LLVMBuildExtractElement(ctx->builder, res,
3602 LLVMConstInt(ctx->i32, 3, false), "");
3603 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3604 LLVMConstInt(ctx->i32, 28, false), "");
3605 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3606 LLVMConstInt(ctx->i32, 0xe, false), "");
3607 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3608 LLVMConstInt(ctx->i32, 0xe, false), "");
3609
3610 samples = LLVMBuildLShr(ctx->builder, samples,
3611 LLVMConstInt(ctx->i32, 16, false), "");
3612 samples = LLVMBuildAnd(ctx->builder, samples,
3613 LLVMConstInt(ctx->i32, 0xf, false), "");
3614 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3615 samples, "");
3616 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3617 ctx->i32one, "");
3618 result = samples;
3619 goto write_result;
3620 }
3621
3622 if (coord)
3623 for (chan = 0; chan < instr->coord_components; chan++)
3624 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3625
3626 if (offsets && instr->op != nir_texop_txf) {
3627 LLVMValueRef offset[3], pack;
3628 for (chan = 0; chan < 3; ++chan)
3629 offset[chan] = ctx->i32zero;
3630
3631 tinfo.has_offset = true;
3632 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3633 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3634 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3635 LLVMConstInt(ctx->i32, 0x3f, false), "");
3636 if (chan)
3637 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3638 LLVMConstInt(ctx->i32, chan * 8, false), "");
3639 }
3640 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3641 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3642 address[count++] = pack;
3643
3644 }
3645 /* pack LOD bias value */
3646 if (instr->op == nir_texop_txb && bias) {
3647 address[count++] = bias;
3648 }
3649
3650 /* Pack depth comparison value */
3651 if (instr->is_shadow && comparator) {
3652 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3653 }
3654
3655 /* pack derivatives */
3656 if (ddx || ddy) {
3657 switch (instr->sampler_dim) {
3658 case GLSL_SAMPLER_DIM_3D:
3659 case GLSL_SAMPLER_DIM_CUBE:
3660 num_deriv_comp = 3;
3661 break;
3662 case GLSL_SAMPLER_DIM_2D:
3663 default:
3664 num_deriv_comp = 2;
3665 break;
3666 case GLSL_SAMPLER_DIM_1D:
3667 num_deriv_comp = 1;
3668 break;
3669 }
3670
3671 for (unsigned i = 0; i < num_deriv_comp; i++) {
3672 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3673 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3674 }
3675 }
3676
3677 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3678 for (chan = 0; chan < instr->coord_components; chan++)
3679 coords[chan] = to_float(ctx, coords[chan]);
3680 if (instr->coord_components == 3)
3681 coords[3] = LLVMGetUndef(ctx->f32);
3682 ac_prepare_cube_coords(&ctx->ac,
3683 instr->op == nir_texop_txd, instr->is_array,
3684 coords, derivs);
3685 if (num_deriv_comp)
3686 num_deriv_comp--;
3687 }
3688
3689 if (ddx || ddy) {
3690 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3691 address[count++] = derivs[i];
3692 }
3693
3694 /* Pack texture coordinates */
3695 if (coord) {
3696 address[count++] = coords[0];
3697 if (instr->coord_components > 1) {
3698 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
3699 coords[1] = apply_round_slice(ctx, coords[1]);
3700 }
3701 address[count++] = coords[1];
3702 }
3703 if (instr->coord_components > 2) {
3704 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3705 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3706 coords[2] = apply_round_slice(ctx, coords[2]);
3707 }
3708 address[count++] = coords[2];
3709 }
3710 }
3711
3712 /* Pack LOD */
3713 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3714 address[count++] = lod;
3715 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3716 address[count++] = sample_index;
3717 } else if(instr->op == nir_texop_txs) {
3718 count = 0;
3719 if (lod)
3720 address[count++] = lod;
3721 else
3722 address[count++] = ctx->i32zero;
3723 }
3724
3725 for (chan = 0; chan < count; chan++) {
3726 address[chan] = LLVMBuildBitCast(ctx->builder,
3727 address[chan], ctx->i32, "");
3728 }
3729
3730 if (instr->op == nir_texop_samples_identical) {
3731 LLVMValueRef txf_address[4];
3732 struct ac_tex_info txf_info = { 0 };
3733 unsigned txf_count = count;
3734 memcpy(txf_address, address, sizeof(txf_address));
3735
3736 if (!instr->is_array)
3737 txf_address[2] = ctx->i32zero;
3738 txf_address[3] = ctx->i32zero;
3739
3740 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3741 fmask_ptr, NULL,
3742 txf_address, txf_count, 0xf);
3743
3744 result = build_tex_intrinsic(ctx, instr, &txf_info);
3745
3746 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3747 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3748 goto write_result;
3749 }
3750
3751 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
3752 instr->op != nir_texop_txs) {
3753 unsigned sample_chan = instr->is_array ? 3 : 2;
3754 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
3755 address[0],
3756 address[1],
3757 instr->is_array ? address[2] : NULL,
3758 address[sample_chan],
3759 fmask_ptr);
3760 }
3761
3762 if (offsets && instr->op == nir_texop_txf) {
3763 nir_const_value *const_offset =
3764 nir_src_as_const_value(instr->src[const_src].src);
3765 int num_offsets = instr->src[const_src].src.ssa->num_components;
3766 assert(const_offset);
3767 num_offsets = MIN2(num_offsets, instr->coord_components);
3768 if (num_offsets > 2)
3769 address[2] = LLVMBuildAdd(ctx->builder,
3770 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3771 if (num_offsets > 1)
3772 address[1] = LLVMBuildAdd(ctx->builder,
3773 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3774 address[0] = LLVMBuildAdd(ctx->builder,
3775 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3776
3777 }
3778
3779 /* TODO TG4 support */
3780 if (instr->op == nir_texop_tg4) {
3781 if (instr->is_shadow)
3782 dmask = 1;
3783 else
3784 dmask = 1 << instr->component;
3785 }
3786 set_tex_fetch_args(ctx, &tinfo, instr, instr->op,
3787 res_ptr, samp_ptr, address, count, dmask);
3788
3789 result = build_tex_intrinsic(ctx, instr, &tinfo);
3790
3791 if (instr->op == nir_texop_query_levels)
3792 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3793 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3794 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3795 else if (instr->op == nir_texop_txs &&
3796 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3797 instr->is_array) {
3798 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3799 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3800 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3801 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3802 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3803 } else if (instr->dest.ssa.num_components != 4)
3804 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3805
3806 write_result:
3807 if (result) {
3808 assert(instr->dest.is_ssa);
3809 result = to_integer(ctx, result);
3810 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3811 }
3812 }
3813
3814
3815 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3816 {
3817 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3818 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3819
3820 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3821 _mesa_hash_table_insert(ctx->phis, instr, result);
3822 }
3823
3824 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3825 nir_phi_instr *instr,
3826 LLVMValueRef llvm_phi)
3827 {
3828 nir_foreach_phi_src(src, instr) {
3829 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3830 LLVMValueRef llvm_src = get_src(ctx, src->src);
3831
3832 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3833 }
3834 }
3835
3836 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3837 {
3838 struct hash_entry *entry;
3839 hash_table_foreach(ctx->phis, entry) {
3840 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3841 (LLVMValueRef)entry->data);
3842 }
3843 }
3844
3845
3846 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3847 nir_ssa_undef_instr *instr)
3848 {
3849 unsigned num_components = instr->def.num_components;
3850 LLVMValueRef undef;
3851
3852 if (num_components == 1)
3853 undef = LLVMGetUndef(ctx->i32);
3854 else {
3855 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3856 }
3857 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3858 }
3859
3860 static void visit_jump(struct nir_to_llvm_context *ctx,
3861 nir_jump_instr *instr)
3862 {
3863 switch (instr->type) {
3864 case nir_jump_break:
3865 LLVMBuildBr(ctx->builder, ctx->break_block);
3866 LLVMClearInsertionPosition(ctx->builder);
3867 break;
3868 case nir_jump_continue:
3869 LLVMBuildBr(ctx->builder, ctx->continue_block);
3870 LLVMClearInsertionPosition(ctx->builder);
3871 break;
3872 default:
3873 fprintf(stderr, "Unknown NIR jump instr: ");
3874 nir_print_instr(&instr->instr, stderr);
3875 fprintf(stderr, "\n");
3876 abort();
3877 }
3878 }
3879
3880 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3881 struct exec_list *list);
3882
3883 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3884 {
3885 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3886 nir_foreach_instr(instr, block)
3887 {
3888 switch (instr->type) {
3889 case nir_instr_type_alu:
3890 visit_alu(ctx, nir_instr_as_alu(instr));
3891 break;
3892 case nir_instr_type_load_const:
3893 visit_load_const(ctx, nir_instr_as_load_const(instr));
3894 break;
3895 case nir_instr_type_intrinsic:
3896 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3897 break;
3898 case nir_instr_type_tex:
3899 visit_tex(ctx, nir_instr_as_tex(instr));
3900 break;
3901 case nir_instr_type_phi:
3902 visit_phi(ctx, nir_instr_as_phi(instr));
3903 break;
3904 case nir_instr_type_ssa_undef:
3905 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3906 break;
3907 case nir_instr_type_jump:
3908 visit_jump(ctx, nir_instr_as_jump(instr));
3909 break;
3910 default:
3911 fprintf(stderr, "Unknown NIR instr type: ");
3912 nir_print_instr(instr, stderr);
3913 fprintf(stderr, "\n");
3914 abort();
3915 }
3916 }
3917
3918 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3919 }
3920
3921 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3922 {
3923 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3924
3925 LLVMBasicBlockRef merge_block =
3926 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3927 LLVMBasicBlockRef if_block =
3928 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3929 LLVMBasicBlockRef else_block = merge_block;
3930 if (!exec_list_is_empty(&if_stmt->else_list))
3931 else_block = LLVMAppendBasicBlockInContext(
3932 ctx->context, ctx->main_function, "");
3933
3934 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3935 LLVMConstInt(ctx->i32, 0, false), "");
3936 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3937
3938 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3939 visit_cf_list(ctx, &if_stmt->then_list);
3940 if (LLVMGetInsertBlock(ctx->builder))
3941 LLVMBuildBr(ctx->builder, merge_block);
3942
3943 if (!exec_list_is_empty(&if_stmt->else_list)) {
3944 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3945 visit_cf_list(ctx, &if_stmt->else_list);
3946 if (LLVMGetInsertBlock(ctx->builder))
3947 LLVMBuildBr(ctx->builder, merge_block);
3948 }
3949
3950 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3951 }
3952
3953 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3954 {
3955 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3956 LLVMBasicBlockRef break_parent = ctx->break_block;
3957
3958 ctx->continue_block =
3959 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3960 ctx->break_block =
3961 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3962
3963 LLVMBuildBr(ctx->builder, ctx->continue_block);
3964 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
3965 visit_cf_list(ctx, &loop->body);
3966
3967 if (LLVMGetInsertBlock(ctx->builder))
3968 LLVMBuildBr(ctx->builder, ctx->continue_block);
3969 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
3970
3971 ctx->continue_block = continue_parent;
3972 ctx->break_block = break_parent;
3973 }
3974
3975 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3976 struct exec_list *list)
3977 {
3978 foreach_list_typed(nir_cf_node, node, node, list)
3979 {
3980 switch (node->type) {
3981 case nir_cf_node_block:
3982 visit_block(ctx, nir_cf_node_as_block(node));
3983 break;
3984
3985 case nir_cf_node_if:
3986 visit_if(ctx, nir_cf_node_as_if(node));
3987 break;
3988
3989 case nir_cf_node_loop:
3990 visit_loop(ctx, nir_cf_node_as_loop(node));
3991 break;
3992
3993 default:
3994 assert(0);
3995 }
3996 }
3997 }
3998
3999 static void
4000 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4001 struct nir_variable *variable)
4002 {
4003 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4004 LLVMValueRef t_offset;
4005 LLVMValueRef t_list;
4006 LLVMValueRef args[3];
4007 LLVMValueRef input;
4008 LLVMValueRef buffer_index;
4009 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4010 int idx = variable->data.location;
4011 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4012
4013 variable->data.driver_location = idx * 4;
4014
4015 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4016 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4017 ctx->start_instance, "");
4018 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4019 ctx->shader_info->vs.vgpr_comp_cnt);
4020 } else
4021 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4022 ctx->base_vertex, "");
4023
4024 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4025 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4026
4027 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4028 args[0] = t_list;
4029 args[1] = LLVMConstInt(ctx->i32, 0, false);
4030 args[2] = buffer_index;
4031 input = ac_emit_llvm_intrinsic(&ctx->ac,
4032 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
4033 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
4034
4035 for (unsigned chan = 0; chan < 4; chan++) {
4036 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4037 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4038 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4039 input, llvm_chan, ""));
4040 }
4041 }
4042 }
4043
4044 static void
4045 handle_gs_input_decl(struct nir_to_llvm_context *ctx,
4046 struct nir_variable *variable)
4047 {
4048 int idx = variable->data.location;
4049
4050 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4051 idx == VARYING_SLOT_CULL_DIST0) {
4052 int length = glsl_get_length(glsl_get_array_element(variable->type));
4053 if (idx == VARYING_SLOT_CLIP_DIST0)
4054 ctx->num_input_clips = length;
4055 else
4056 ctx->num_input_culls = length;
4057 }
4058 }
4059
4060 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4061 unsigned attr,
4062 LLVMValueRef interp_param,
4063 LLVMValueRef prim_mask,
4064 LLVMValueRef result[4])
4065 {
4066 LLVMValueRef attr_number;
4067 unsigned chan;
4068 LLVMValueRef i, j;
4069 bool interp = interp_param != NULL;
4070
4071 attr_number = LLVMConstInt(ctx->i32, attr, false);
4072
4073 /* fs.constant returns the param from the middle vertex, so it's not
4074 * really useful for flat shading. It's meant to be used for custom
4075 * interpolation (but the intrinsic can't fetch from the other two
4076 * vertices).
4077 *
4078 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4079 * to do the right thing. The only reason we use fs.constant is that
4080 * fs.interp cannot be used on integers, because they can be equal
4081 * to NaN.
4082 */
4083 if (interp) {
4084 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4085 LLVMVectorType(ctx->f32, 2), "");
4086
4087 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4088 ctx->i32zero, "");
4089 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4090 ctx->i32one, "");
4091 }
4092
4093 for (chan = 0; chan < 4; chan++) {
4094 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4095
4096 if (interp) {
4097 result[chan] = ac_build_fs_interp(&ctx->ac,
4098 llvm_chan,
4099 attr_number,
4100 prim_mask, i, j);
4101 } else {
4102 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4103 LLVMConstInt(ctx->i32, 2, false),
4104 llvm_chan,
4105 attr_number,
4106 prim_mask);
4107 }
4108 }
4109 }
4110
4111 static void
4112 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4113 struct nir_variable *variable)
4114 {
4115 int idx = variable->data.location;
4116 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4117 LLVMValueRef interp;
4118
4119 variable->data.driver_location = idx * 4;
4120 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4121
4122 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4123 unsigned interp_type;
4124 if (variable->data.sample) {
4125 interp_type = INTERP_SAMPLE;
4126 ctx->shader_info->fs.force_persample = true;
4127 } else if (variable->data.centroid)
4128 interp_type = INTERP_CENTROID;
4129 else
4130 interp_type = INTERP_CENTER;
4131
4132 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4133 } else
4134 interp = NULL;
4135
4136 for (unsigned i = 0; i < attrib_count; ++i)
4137 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4138
4139 }
4140
4141 static void
4142 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4143 struct nir_variable *variable)
4144 {
4145 switch (ctx->stage) {
4146 case MESA_SHADER_VERTEX:
4147 handle_vs_input_decl(ctx, variable);
4148 break;
4149 case MESA_SHADER_FRAGMENT:
4150 handle_fs_input_decl(ctx, variable);
4151 break;
4152 case MESA_SHADER_GEOMETRY:
4153 handle_gs_input_decl(ctx, variable);
4154 break;
4155 default:
4156 break;
4157 }
4158
4159 }
4160
4161 static void
4162 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4163 struct nir_shader *nir)
4164 {
4165 unsigned index = 0;
4166 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4167 LLVMValueRef interp_param;
4168 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4169
4170 if (!(ctx->input_mask & (1ull << i)))
4171 continue;
4172
4173 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4174 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4175 interp_param = *inputs;
4176 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4177 inputs);
4178
4179 if (!interp_param)
4180 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4181 ++index;
4182 } else if (i == VARYING_SLOT_POS) {
4183 for(int i = 0; i < 3; ++i)
4184 inputs[i] = ctx->frag_pos[i];
4185
4186 inputs[3] = ac_emit_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4187 }
4188 }
4189 ctx->shader_info->fs.num_interp = index;
4190 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4191 ctx->shader_info->fs.has_pcoord = true;
4192 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4193 ctx->shader_info->fs.prim_id_input = true;
4194 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4195 ctx->shader_info->fs.layer_input = true;
4196 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4197 }
4198
4199 static LLVMValueRef
4200 ac_build_alloca(struct nir_to_llvm_context *ctx,
4201 LLVMTypeRef type,
4202 const char *name)
4203 {
4204 LLVMBuilderRef builder = ctx->builder;
4205 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4206 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4207 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4208 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4209 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4210 LLVMValueRef res;
4211
4212 if (first_instr) {
4213 LLVMPositionBuilderBefore(first_builder, first_instr);
4214 } else {
4215 LLVMPositionBuilderAtEnd(first_builder, first_block);
4216 }
4217
4218 res = LLVMBuildAlloca(first_builder, type, name);
4219 LLVMBuildStore(builder, LLVMConstNull(type), res);
4220
4221 LLVMDisposeBuilder(first_builder);
4222
4223 return res;
4224 }
4225
4226 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4227 LLVMTypeRef type,
4228 const char *name)
4229 {
4230 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4231 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4232 return ptr;
4233 }
4234
4235 static void
4236 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4237 struct nir_variable *variable)
4238 {
4239 int idx = variable->data.location + variable->data.index;
4240 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4241
4242 variable->data.driver_location = idx * 4;
4243
4244 if (ctx->stage == MESA_SHADER_VERTEX ||
4245 ctx->stage == MESA_SHADER_GEOMETRY) {
4246 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4247 idx == VARYING_SLOT_CULL_DIST0) {
4248 int length = glsl_get_length(variable->type);
4249 if (idx == VARYING_SLOT_CLIP_DIST0) {
4250 if (ctx->stage == MESA_SHADER_VERTEX)
4251 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
4252 ctx->num_output_clips = length;
4253 } else if (idx == VARYING_SLOT_CULL_DIST0) {
4254 if (ctx->stage == MESA_SHADER_VERTEX)
4255 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
4256 ctx->num_output_culls = length;
4257 }
4258 if (length > 4)
4259 attrib_count = 2;
4260 else
4261 attrib_count = 1;
4262 }
4263 }
4264
4265 for (unsigned i = 0; i < attrib_count; ++i) {
4266 for (unsigned chan = 0; chan < 4; chan++) {
4267 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4268 si_build_alloca_undef(ctx, ctx->f32, "");
4269 }
4270 }
4271 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
4272 }
4273
4274 static void
4275 setup_locals(struct nir_to_llvm_context *ctx,
4276 struct nir_function *func)
4277 {
4278 int i, j;
4279 ctx->num_locals = 0;
4280 nir_foreach_variable(variable, &func->impl->locals) {
4281 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4282 variable->data.driver_location = ctx->num_locals * 4;
4283 ctx->num_locals += attrib_count;
4284 }
4285 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4286 if (!ctx->locals)
4287 return;
4288
4289 for (i = 0; i < ctx->num_locals; i++) {
4290 for (j = 0; j < 4; j++) {
4291 ctx->locals[i * 4 + j] =
4292 si_build_alloca_undef(ctx, ctx->f32, "temp");
4293 }
4294 }
4295 }
4296
4297 static LLVMValueRef
4298 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4299 {
4300 v = to_float(ctx, v);
4301 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4302 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4303 }
4304
4305
4306 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4307 LLVMValueRef src0, LLVMValueRef src1)
4308 {
4309 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4310 LLVMValueRef comp[2];
4311
4312 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4313 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4314 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4315 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4316 }
4317
4318 /* Initialize arguments for the shader export intrinsic */
4319 static void
4320 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4321 LLVMValueRef *values,
4322 unsigned target,
4323 LLVMValueRef *args)
4324 {
4325 /* Default is 0xf. Adjusted below depending on the format. */
4326 args[0] = LLVMConstInt(ctx->i32, target != V_008DFC_SQ_EXP_NULL ? 0xf : 0, false);
4327 /* Specify whether the EXEC mask represents the valid mask */
4328 args[1] = LLVMConstInt(ctx->i32, 0, false);
4329
4330 /* Specify whether this is the last export */
4331 args[2] = LLVMConstInt(ctx->i32, 0, false);
4332 /* Specify the target we are exporting */
4333 args[3] = LLVMConstInt(ctx->i32, target, false);
4334
4335 args[4] = LLVMConstInt(ctx->i32, 0, false); /* COMPR flag */
4336 args[5] = LLVMGetUndef(ctx->f32);
4337 args[6] = LLVMGetUndef(ctx->f32);
4338 args[7] = LLVMGetUndef(ctx->f32);
4339 args[8] = LLVMGetUndef(ctx->f32);
4340
4341 if (!values)
4342 return;
4343
4344 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4345 LLVMValueRef val[4];
4346 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4347 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4348 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4349
4350 switch(col_format) {
4351 case V_028714_SPI_SHADER_ZERO:
4352 args[0] = LLVMConstInt(ctx->i32, 0x0, 0);
4353 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_NULL, 0);
4354 break;
4355
4356 case V_028714_SPI_SHADER_32_R:
4357 args[0] = LLVMConstInt(ctx->i32, 0x1, 0);
4358 args[5] = values[0];
4359 break;
4360
4361 case V_028714_SPI_SHADER_32_GR:
4362 args[0] = LLVMConstInt(ctx->i32, 0x3, 0);
4363 args[5] = values[0];
4364 args[6] = values[1];
4365 break;
4366
4367 case V_028714_SPI_SHADER_32_AR:
4368 args[0] = LLVMConstInt(ctx->i32, 0x9, 0);
4369 args[5] = values[0];
4370 args[8] = values[3];
4371 break;
4372
4373 case V_028714_SPI_SHADER_FP16_ABGR:
4374 args[4] = ctx->i32one;
4375
4376 for (unsigned chan = 0; chan < 2; chan++) {
4377 LLVMValueRef pack_args[2] = {
4378 values[2 * chan],
4379 values[2 * chan + 1]
4380 };
4381 LLVMValueRef packed;
4382
4383 packed = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.packf16",
4384 ctx->i32, pack_args, 2,
4385 AC_FUNC_ATTR_READNONE);
4386 args[chan + 5] = packed;
4387 }
4388 break;
4389
4390 case V_028714_SPI_SHADER_UNORM16_ABGR:
4391 for (unsigned chan = 0; chan < 4; chan++) {
4392 val[chan] = emit_float_saturate(ctx, values[chan], 0, 1);
4393 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4394 LLVMConstReal(ctx->f32, 65535), "");
4395 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4396 LLVMConstReal(ctx->f32, 0.5), "");
4397 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4398 ctx->i32, "");
4399 }
4400
4401 args[4] = ctx->i32one;
4402 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4403 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4404 break;
4405
4406 case V_028714_SPI_SHADER_SNORM16_ABGR:
4407 for (unsigned chan = 0; chan < 4; chan++) {
4408 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4409 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4410 LLVMConstReal(ctx->f32, 32767), "");
4411
4412 /* If positive, add 0.5, else add -0.5. */
4413 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4414 LLVMBuildSelect(ctx->builder,
4415 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4416 val[chan], ctx->f32zero, ""),
4417 LLVMConstReal(ctx->f32, 0.5),
4418 LLVMConstReal(ctx->f32, -0.5), ""), "");
4419 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4420 }
4421
4422 args[4] = ctx->i32one;
4423 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4424 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4425 break;
4426
4427 case V_028714_SPI_SHADER_UINT16_ABGR: {
4428 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4429
4430 for (unsigned chan = 0; chan < 4; chan++) {
4431 val[chan] = to_integer(ctx, values[chan]);
4432 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4433 }
4434
4435 args[4] = ctx->i32one;
4436 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4437 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4438 break;
4439 }
4440
4441 case V_028714_SPI_SHADER_SINT16_ABGR: {
4442 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4443 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4444
4445 /* Clamp. */
4446 for (unsigned chan = 0; chan < 4; chan++) {
4447 val[chan] = to_integer(ctx, values[chan]);
4448 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4449 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4450 }
4451
4452 args[4] = ctx->i32one;
4453 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4454 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4455 break;
4456 }
4457
4458 default:
4459 case V_028714_SPI_SHADER_32_ABGR:
4460 memcpy(&args[5], values, sizeof(values[0]) * 4);
4461 break;
4462 }
4463 } else
4464 memcpy(&args[5], values, sizeof(values[0]) * 4);
4465
4466 for (unsigned i = 5; i < 9; ++i)
4467 args[i] = to_float(ctx, args[i]);
4468 }
4469
4470 static void
4471 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4472 {
4473 uint32_t param_count = 0;
4474 unsigned target;
4475 unsigned pos_idx, num_pos_exports = 0;
4476 LLVMValueRef args[9];
4477 LLVMValueRef pos_args[4][9] = { { 0 } };
4478 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4479 int i;
4480 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4481 (1ull << VARYING_SLOT_CLIP_DIST1) |
4482 (1ull << VARYING_SLOT_CULL_DIST0) |
4483 (1ull << VARYING_SLOT_CULL_DIST1));
4484
4485 ctx->shader_info->vs.prim_id_output = 0xffffffff;
4486 ctx->shader_info->vs.layer_output = 0xffffffff;
4487 if (clip_mask) {
4488 LLVMValueRef slots[8];
4489 unsigned j;
4490
4491 if (ctx->shader_info->vs.cull_dist_mask)
4492 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_output_clips;
4493
4494 i = VARYING_SLOT_CLIP_DIST0;
4495 for (j = 0; j < ctx->num_output_clips; j++)
4496 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4497 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4498 i = VARYING_SLOT_CULL_DIST0;
4499 for (j = 0; j < ctx->num_output_culls; j++)
4500 slots[ctx->num_output_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4501 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4502
4503 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
4504 slots[i] = LLVMGetUndef(ctx->f32);
4505
4506 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
4507 target = V_008DFC_SQ_EXP_POS + 3;
4508 si_llvm_init_export_args(ctx, &slots[4], target, args);
4509 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4510 args, sizeof(args));
4511 }
4512
4513 target = V_008DFC_SQ_EXP_POS + 2;
4514 si_llvm_init_export_args(ctx, &slots[0], target, args);
4515 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4516 args, sizeof(args));
4517
4518 }
4519
4520 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4521 LLVMValueRef values[4];
4522 if (!(ctx->output_mask & (1ull << i)))
4523 continue;
4524
4525 for (unsigned j = 0; j < 4; j++)
4526 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4527 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4528
4529 if (i == VARYING_SLOT_POS) {
4530 target = V_008DFC_SQ_EXP_POS;
4531 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4532 i == VARYING_SLOT_CLIP_DIST1 ||
4533 i == VARYING_SLOT_CULL_DIST0 ||
4534 i == VARYING_SLOT_CULL_DIST1) {
4535 continue;
4536 } else if (i == VARYING_SLOT_PSIZ) {
4537 ctx->shader_info->vs.writes_pointsize = true;
4538 psize_value = values[0];
4539 continue;
4540 } else if (i == VARYING_SLOT_LAYER) {
4541 ctx->shader_info->vs.writes_layer = true;
4542 layer_value = values[0];
4543 ctx->shader_info->vs.layer_output = param_count;
4544 target = V_008DFC_SQ_EXP_PARAM + param_count;
4545 param_count++;
4546 } else if (i == VARYING_SLOT_VIEWPORT) {
4547 ctx->shader_info->vs.writes_viewport_index = true;
4548 viewport_index_value = values[0];
4549 continue;
4550 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
4551 ctx->shader_info->vs.prim_id_output = param_count;
4552 target = V_008DFC_SQ_EXP_PARAM + param_count;
4553 param_count++;
4554 } else if (i >= VARYING_SLOT_VAR0) {
4555 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4556 target = V_008DFC_SQ_EXP_PARAM + param_count;
4557 param_count++;
4558 }
4559
4560 si_llvm_init_export_args(ctx, values, target, args);
4561
4562 if (target >= V_008DFC_SQ_EXP_POS &&
4563 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4564 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4565 args, sizeof(args));
4566 } else {
4567 ac_emit_llvm_intrinsic(&ctx->ac,
4568 "llvm.SI.export",
4569 ctx->voidt,
4570 args, 9, 0);
4571 }
4572 }
4573
4574 /* We need to add the position output manually if it's missing. */
4575 if (!pos_args[0][0]) {
4576 pos_args[0][0] = LLVMConstInt(ctx->i32, 0xf, false);
4577 pos_args[0][1] = ctx->i32zero; /* EXEC mask */
4578 pos_args[0][2] = ctx->i32zero; /* last export? */
4579 pos_args[0][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS, false);
4580 pos_args[0][4] = ctx->i32zero; /* COMPR flag */
4581 pos_args[0][5] = ctx->f32zero; /* X */
4582 pos_args[0][6] = ctx->f32zero; /* Y */
4583 pos_args[0][7] = ctx->f32zero; /* Z */
4584 pos_args[0][8] = ctx->f32one; /* W */
4585 }
4586
4587 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4588 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4589 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4590 if (mask) {
4591 pos_args[1][0] = LLVMConstInt(ctx->i32, mask, false); /* writemask */
4592 pos_args[1][1] = ctx->i32zero; /* EXEC mask */
4593 pos_args[1][2] = ctx->i32zero; /* last export? */
4594 pos_args[1][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + 1, false);
4595 pos_args[1][4] = ctx->i32zero; /* COMPR flag */
4596 pos_args[1][5] = ctx->f32zero; /* X */
4597 pos_args[1][6] = ctx->f32zero; /* Y */
4598 pos_args[1][7] = ctx->f32zero; /* Z */
4599 pos_args[1][8] = ctx->f32zero; /* W */
4600
4601 if (ctx->shader_info->vs.writes_pointsize == true)
4602 pos_args[1][5] = psize_value;
4603 if (ctx->shader_info->vs.writes_layer == true)
4604 pos_args[1][7] = layer_value;
4605 if (ctx->shader_info->vs.writes_viewport_index == true)
4606 pos_args[1][8] = viewport_index_value;
4607 }
4608 for (i = 0; i < 4; i++) {
4609 if (pos_args[i][0])
4610 num_pos_exports++;
4611 }
4612
4613 pos_idx = 0;
4614 for (i = 0; i < 4; i++) {
4615 if (!pos_args[i][0])
4616 continue;
4617
4618 /* Specify the target we are exporting */
4619 pos_args[i][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + pos_idx++, false);
4620 if (pos_idx == num_pos_exports)
4621 pos_args[i][2] = ctx->i32one;
4622 ac_emit_llvm_intrinsic(&ctx->ac,
4623 "llvm.SI.export",
4624 ctx->voidt,
4625 pos_args[i], 9, 0);
4626 }
4627
4628 ctx->shader_info->vs.pos_exports = num_pos_exports;
4629 ctx->shader_info->vs.param_exports = param_count;
4630 }
4631
4632 static void
4633 handle_es_outputs_post(struct nir_to_llvm_context *ctx)
4634 {
4635 int j;
4636 uint64_t max_output_written = 0;
4637 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4638 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
4639 int param_index;
4640 int length = 4;
4641 int start = 0;
4642 if (!(ctx->output_mask & (1ull << i)))
4643 continue;
4644
4645 if (i == VARYING_SLOT_CLIP_DIST0) {
4646 length = ctx->num_output_clips;
4647 } else if (i == VARYING_SLOT_CULL_DIST0) {
4648 start = ctx->num_output_clips;
4649 length = ctx->num_output_culls;
4650 }
4651 param_index = shader_io_get_unique_index(i);
4652
4653 if (param_index > max_output_written)
4654 max_output_written = param_index;
4655
4656 for (j = 0; j < length; j++) {
4657 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
4658 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4659
4660 ac_build_tbuffer_store(&ctx->ac,
4661 ctx->esgs_ring,
4662 out_val, 1,
4663 LLVMGetUndef(ctx->i32), ctx->es2gs_offset,
4664 (4 * param_index + j + start) * 4,
4665 V_008F0C_BUF_DATA_FORMAT_32,
4666 V_008F0C_BUF_NUM_FORMAT_UINT,
4667 0, 0, 1, 1, 0);
4668 }
4669 }
4670 ctx->shader_info->vs.esgs_itemsize = (max_output_written + 1) * 16;
4671 }
4672
4673 static void
4674 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4675 LLVMValueRef *color, unsigned param, bool is_last)
4676 {
4677 LLVMValueRef args[9];
4678 /* Export */
4679 si_llvm_init_export_args(ctx, color, param,
4680 args);
4681
4682 if (is_last) {
4683 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4684 args[2] = ctx->i32one; /* DONE bit */
4685 } else if (args[0] == ctx->i32zero)
4686 return; /* unnecessary NULL export */
4687
4688 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4689 ctx->voidt, args, 9, 0);
4690 }
4691
4692 static void
4693 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4694 LLVMValueRef depth, LLVMValueRef stencil,
4695 LLVMValueRef samplemask)
4696 {
4697 LLVMValueRef args[9];
4698 unsigned mask = 0;
4699 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4700 args[2] = ctx->i32one; /* DONE bit */
4701 /* Specify the target we are exporting */
4702 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_MRTZ, false);
4703
4704 args[4] = ctx->i32zero; /* COMP flag */
4705 args[5] = LLVMGetUndef(ctx->f32); /* R, depth */
4706 args[6] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4707 args[7] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4708 args[8] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4709
4710 if (depth) {
4711 args[5] = depth;
4712 mask |= 0x1;
4713 }
4714
4715 if (stencil) {
4716 args[6] = stencil;
4717 mask |= 0x2;
4718 }
4719
4720 if (samplemask) {
4721 args[7] = samplemask;
4722 mask |= 0x04;
4723 }
4724
4725 /* SI (except OLAND) has a bug that it only looks
4726 * at the X writemask component. */
4727 if (ctx->options->chip_class == SI &&
4728 ctx->options->family != CHIP_OLAND)
4729 mask |= 0x01;
4730
4731 args[0] = LLVMConstInt(ctx->i32, mask, false);
4732 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4733 ctx->voidt, args, 9, 0);
4734 }
4735
4736 static void
4737 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4738 {
4739 unsigned index = 0;
4740 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4741
4742 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4743 LLVMValueRef values[4];
4744
4745 if (!(ctx->output_mask & (1ull << i)))
4746 continue;
4747
4748 if (i == FRAG_RESULT_DEPTH) {
4749 ctx->shader_info->fs.writes_z = true;
4750 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4751 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4752 } else if (i == FRAG_RESULT_STENCIL) {
4753 ctx->shader_info->fs.writes_stencil = true;
4754 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4755 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4756 } else {
4757 bool last = false;
4758 for (unsigned j = 0; j < 4; j++)
4759 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4760 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4761
4762 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil)
4763 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4764
4765 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4766 index++;
4767 }
4768 }
4769
4770 if (depth || stencil)
4771 si_export_mrt_z(ctx, depth, stencil, samplemask);
4772 else if (!index)
4773 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4774
4775 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4776 }
4777
4778 static void
4779 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4780 {
4781 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
4782 }
4783
4784 static void
4785 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4786 {
4787 switch (ctx->stage) {
4788 case MESA_SHADER_VERTEX:
4789 if (ctx->options->key.vs.as_es)
4790 handle_es_outputs_post(ctx);
4791 else
4792 handle_vs_outputs_post(ctx);
4793 break;
4794 case MESA_SHADER_FRAGMENT:
4795 handle_fs_outputs_post(ctx);
4796 break;
4797 case MESA_SHADER_GEOMETRY:
4798 emit_gs_epilogue(ctx);
4799 break;
4800 default:
4801 break;
4802 }
4803 }
4804
4805 static void
4806 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4807 struct nir_variable *variable, uint32_t *offset, int idx)
4808 {
4809 unsigned size = glsl_count_attribute_slots(variable->type, false);
4810 variable->data.driver_location = *offset;
4811 *offset += size;
4812 }
4813
4814 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4815 {
4816 LLVMPassManagerRef passmgr;
4817 /* Create the pass manager */
4818 passmgr = LLVMCreateFunctionPassManagerForModule(
4819 ctx->module);
4820
4821 /* This pass should eliminate all the load and store instructions */
4822 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4823
4824 /* Add some optimization passes */
4825 LLVMAddScalarReplAggregatesPass(passmgr);
4826 LLVMAddLICMPass(passmgr);
4827 LLVMAddAggressiveDCEPass(passmgr);
4828 LLVMAddCFGSimplificationPass(passmgr);
4829 LLVMAddInstructionCombiningPass(passmgr);
4830
4831 /* Run the pass */
4832 LLVMInitializeFunctionPassManager(passmgr);
4833 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4834 LLVMFinalizeFunctionPassManager(passmgr);
4835
4836 LLVMDisposeBuilder(ctx->builder);
4837 LLVMDisposePassManager(passmgr);
4838 }
4839
4840 static void
4841 ac_setup_rings(struct nir_to_llvm_context *ctx)
4842 {
4843 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4844 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, ctx->i32one);
4845 }
4846
4847 if (ctx->is_gs_copy_shader) {
4848 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4849 }
4850 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4851 LLVMValueRef tmp;
4852 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4853 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4854
4855 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4856
4857 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4858 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4859 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4860 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4861
4862 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4863 }
4864 }
4865
4866 static
4867 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4868 struct nir_shader *nir,
4869 struct ac_shader_variant_info *shader_info,
4870 const struct ac_nir_compiler_options *options)
4871 {
4872 struct nir_to_llvm_context ctx = {0};
4873 struct nir_function *func;
4874 unsigned i;
4875 ctx.options = options;
4876 ctx.shader_info = shader_info;
4877 ctx.context = LLVMContextCreate();
4878 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4879
4880 ac_llvm_context_init(&ctx.ac, ctx.context);
4881 ctx.ac.module = ctx.module;
4882
4883 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4884
4885 memset(shader_info, 0, sizeof(*shader_info));
4886
4887 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4888 setup_types(&ctx);
4889
4890 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4891 ctx.ac.builder = ctx.builder;
4892 ctx.stage = nir->stage;
4893
4894 for (i = 0; i < AC_UD_MAX_SETS; i++)
4895 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4896 for (i = 0; i < AC_UD_MAX_UD; i++)
4897 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4898
4899 create_function(&ctx);
4900
4901 if (nir->stage == MESA_SHADER_COMPUTE) {
4902 int num_shared = 0;
4903 nir_foreach_variable(variable, &nir->shared)
4904 num_shared++;
4905 if (num_shared) {
4906 int idx = 0;
4907 uint32_t shared_size = 0;
4908 LLVMValueRef var;
4909 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4910 nir_foreach_variable(variable, &nir->shared) {
4911 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4912 idx++;
4913 }
4914
4915 shared_size *= 16;
4916 var = LLVMAddGlobalInAddressSpace(ctx.module,
4917 LLVMArrayType(ctx.i8, shared_size),
4918 "compute_lds",
4919 LOCAL_ADDR_SPACE);
4920 LLVMSetAlignment(var, 4);
4921 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4922 }
4923 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4924 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4925
4926 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4927 }
4928
4929 ac_setup_rings(&ctx);
4930
4931 nir_foreach_variable(variable, &nir->inputs)
4932 handle_shader_input_decl(&ctx, variable);
4933
4934 if (nir->stage == MESA_SHADER_FRAGMENT)
4935 handle_fs_inputs_pre(&ctx, nir);
4936
4937 nir_foreach_variable(variable, &nir->outputs)
4938 handle_shader_output_decl(&ctx, variable);
4939
4940 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4941 _mesa_key_pointer_equal);
4942 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4943 _mesa_key_pointer_equal);
4944
4945 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4946
4947 setup_locals(&ctx, func);
4948
4949 visit_cf_list(&ctx, &func->impl->body);
4950 phi_post_pass(&ctx);
4951
4952 handle_shader_outputs_post(&ctx);
4953 LLVMBuildRetVoid(ctx.builder);
4954
4955 ac_llvm_finalize_module(&ctx);
4956 free(ctx.locals);
4957 ralloc_free(ctx.defs);
4958 ralloc_free(ctx.phis);
4959
4960 if (nir->stage == MESA_SHADER_GEOMETRY) {
4961 shader_info->gs.gsvs_vertex_size = util_bitcount64(ctx.output_mask) * 16;
4962 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
4963 nir->info->gs.vertices_out;
4964 }
4965 return ctx.module;
4966 }
4967
4968 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4969 {
4970 unsigned *retval = (unsigned *)context;
4971 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4972 char *description = LLVMGetDiagInfoDescription(di);
4973
4974 if (severity == LLVMDSError) {
4975 *retval = 1;
4976 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4977 description);
4978 }
4979
4980 LLVMDisposeMessage(description);
4981 }
4982
4983 static unsigned ac_llvm_compile(LLVMModuleRef M,
4984 struct ac_shader_binary *binary,
4985 LLVMTargetMachineRef tm)
4986 {
4987 unsigned retval = 0;
4988 char *err;
4989 LLVMContextRef llvm_ctx;
4990 LLVMMemoryBufferRef out_buffer;
4991 unsigned buffer_size;
4992 const char *buffer_data;
4993 LLVMBool mem_err;
4994
4995 /* Setup Diagnostic Handler*/
4996 llvm_ctx = LLVMGetModuleContext(M);
4997
4998 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4999 &retval);
5000
5001 /* Compile IR*/
5002 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
5003 &err, &out_buffer);
5004
5005 /* Process Errors/Warnings */
5006 if (mem_err) {
5007 fprintf(stderr, "%s: %s", __FUNCTION__, err);
5008 free(err);
5009 retval = 1;
5010 goto out;
5011 }
5012
5013 /* Extract Shader Code*/
5014 buffer_size = LLVMGetBufferSize(out_buffer);
5015 buffer_data = LLVMGetBufferStart(out_buffer);
5016
5017 ac_elf_read(buffer_data, buffer_size, binary);
5018
5019 /* Clean up */
5020 LLVMDisposeMemoryBuffer(out_buffer);
5021
5022 out:
5023 return retval;
5024 }
5025
5026 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
5027 LLVMModuleRef llvm_module,
5028 struct ac_shader_binary *binary,
5029 struct ac_shader_config *config,
5030 struct ac_shader_variant_info *shader_info,
5031 gl_shader_stage stage,
5032 bool dump_shader, bool supports_spill)
5033 {
5034 if (dump_shader)
5035 ac_dump_module(llvm_module);
5036
5037 memset(binary, 0, sizeof(*binary));
5038 int v = ac_llvm_compile(llvm_module, binary, tm);
5039 if (v) {
5040 fprintf(stderr, "compile failed\n");
5041 }
5042
5043 if (dump_shader)
5044 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
5045
5046 ac_shader_binary_read_config(binary, config, 0, supports_spill);
5047
5048 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
5049 LLVMDisposeModule(llvm_module);
5050 LLVMContextDispose(ctx);
5051
5052 if (stage == MESA_SHADER_FRAGMENT) {
5053 shader_info->num_input_vgprs = 0;
5054 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
5055 shader_info->num_input_vgprs += 2;
5056 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
5057 shader_info->num_input_vgprs += 2;
5058 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
5059 shader_info->num_input_vgprs += 2;
5060 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
5061 shader_info->num_input_vgprs += 3;
5062 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
5063 shader_info->num_input_vgprs += 2;
5064 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
5065 shader_info->num_input_vgprs += 2;
5066 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
5067 shader_info->num_input_vgprs += 2;
5068 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
5069 shader_info->num_input_vgprs += 1;
5070 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
5071 shader_info->num_input_vgprs += 1;
5072 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
5073 shader_info->num_input_vgprs += 1;
5074 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5075 shader_info->num_input_vgprs += 1;
5076 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5077 shader_info->num_input_vgprs += 1;
5078 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5079 shader_info->num_input_vgprs += 1;
5080 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5081 shader_info->num_input_vgprs += 1;
5082 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5083 shader_info->num_input_vgprs += 1;
5084 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5085 shader_info->num_input_vgprs += 1;
5086 }
5087 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5088
5089 /* +3 for scratch wave offset and VCC */
5090 config->num_sgprs = MAX2(config->num_sgprs,
5091 shader_info->num_input_sgprs + 3);
5092 }
5093
5094 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5095 struct ac_shader_binary *binary,
5096 struct ac_shader_config *config,
5097 struct ac_shader_variant_info *shader_info,
5098 struct nir_shader *nir,
5099 const struct ac_nir_compiler_options *options,
5100 bool dump_shader)
5101 {
5102
5103 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5104 options);
5105
5106 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5107 switch (nir->stage) {
5108 case MESA_SHADER_COMPUTE:
5109 for (int i = 0; i < 3; ++i)
5110 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5111 break;
5112 case MESA_SHADER_FRAGMENT:
5113 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5114 break;
5115 case MESA_SHADER_GEOMETRY:
5116 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5117 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5118 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5119 shader_info->gs.invocations = nir->info->gs.invocations;
5120 break;
5121 case MESA_SHADER_VERTEX:
5122 shader_info->vs.as_es = options->key.vs.as_es;
5123 break;
5124 default:
5125 break;
5126 }
5127 }
5128
5129 static void
5130 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5131 {
5132 LLVMValueRef args[9];
5133 args[0] = ctx->gsvs_ring;
5134 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5135 args[3] = ctx->i32zero;
5136 args[4] = ctx->i32one; /* OFFEN */
5137 args[5] = ctx->i32zero; /* IDXEN */
5138 args[6] = ctx->i32one; /* GLC */
5139 args[7] = ctx->i32one; /* SLC */
5140 args[8] = ctx->i32zero; /* TFE */
5141
5142 int idx = 0;
5143 int clip_cull_slot = -1;
5144 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5145 int length = 4;
5146 int start = 0;
5147 int slot = idx;
5148 int slot_inc = 1;
5149 if (!(ctx->output_mask & (1ull << i)))
5150 continue;
5151
5152 if (i == VARYING_SLOT_CLIP_DIST1 ||
5153 i == VARYING_SLOT_CULL_DIST1)
5154 continue;
5155
5156 if (i == VARYING_SLOT_CLIP_DIST0 ||
5157 i == VARYING_SLOT_CULL_DIST0) {
5158 /* unpack clip and cull from a single set of slots */
5159 if (clip_cull_slot == -1) {
5160 clip_cull_slot = idx;
5161 if (ctx->num_output_clips + ctx->num_output_culls > 4)
5162 slot_inc = 2;
5163 } else {
5164 slot = clip_cull_slot;
5165 slot_inc = 0;
5166 }
5167 if (i == VARYING_SLOT_CLIP_DIST0)
5168 length = ctx->num_output_clips;
5169 if (i == VARYING_SLOT_CULL_DIST0) {
5170 start = ctx->num_output_clips;
5171 length = ctx->num_output_culls;
5172 }
5173 }
5174
5175 for (unsigned j = 0; j < length; j++) {
5176 LLVMValueRef value;
5177 args[2] = LLVMConstInt(ctx->i32,
5178 (slot * 4 + j + start) *
5179 ctx->gs_max_out_vertices * 16 * 4, false);
5180
5181 value = ac_emit_llvm_intrinsic(&ctx->ac,
5182 "llvm.SI.buffer.load.dword.i32.i32",
5183 ctx->i32, args, 9,
5184 AC_FUNC_ATTR_READONLY);
5185
5186 LLVMBuildStore(ctx->builder,
5187 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
5188 }
5189 idx += slot_inc;
5190 }
5191 handle_vs_outputs_post(ctx);
5192 }
5193
5194 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5195 struct nir_shader *geom_shader,
5196 struct ac_shader_binary *binary,
5197 struct ac_shader_config *config,
5198 struct ac_shader_variant_info *shader_info,
5199 const struct ac_nir_compiler_options *options,
5200 bool dump_shader)
5201 {
5202 struct nir_to_llvm_context ctx = {0};
5203 ctx.context = LLVMContextCreate();
5204 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5205 ctx.options = options;
5206 ctx.shader_info = shader_info;
5207
5208 ac_llvm_context_init(&ctx.ac, ctx.context);
5209 ctx.ac.module = ctx.module;
5210
5211 ctx.is_gs_copy_shader = true;
5212 LLVMSetTarget(ctx.module, "amdgcn--");
5213 setup_types(&ctx);
5214
5215 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5216 ctx.ac.builder = ctx.builder;
5217 ctx.stage = MESA_SHADER_VERTEX;
5218
5219 create_function(&ctx);
5220
5221 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5222 ac_setup_rings(&ctx);
5223
5224 nir_foreach_variable(variable, &geom_shader->outputs)
5225 handle_shader_output_decl(&ctx, variable);
5226
5227 ac_gs_copy_shader_emit(&ctx);
5228
5229 LLVMBuildRetVoid(ctx.builder);
5230
5231 ac_llvm_finalize_module(&ctx);
5232
5233 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5234 MESA_SHADER_VERTEX,
5235 dump_shader, options->supports_spill);
5236 }