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[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
48
49 struct nir_to_llvm_context;
50
51 struct ac_nir_context {
52 struct ac_llvm_context ac;
53 struct ac_shader_abi *abi;
54
55 gl_shader_stage stage;
56
57 struct hash_table *defs;
58 struct hash_table *phis;
59 struct hash_table *vars;
60
61 LLVMValueRef main_function;
62 LLVMBasicBlockRef continue_block;
63 LLVMBasicBlockRef break_block;
64
65 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
66
67 int num_locals;
68 LLVMValueRef *locals;
69
70 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
71 };
72
73 struct nir_to_llvm_context {
74 struct ac_llvm_context ac;
75 const struct ac_nir_compiler_options *options;
76 struct ac_shader_variant_info *shader_info;
77 struct ac_shader_abi abi;
78 struct ac_nir_context *nir;
79
80 unsigned max_workgroup_size;
81 LLVMContextRef context;
82 LLVMModuleRef module;
83 LLVMBuilderRef builder;
84 LLVMValueRef main_function;
85
86 struct hash_table *defs;
87 struct hash_table *phis;
88
89 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
90 LLVMValueRef ring_offsets;
91 LLVMValueRef push_constants;
92 LLVMValueRef view_index;
93 LLVMValueRef tg_size;
94
95 LLVMValueRef vertex_buffers;
96 LLVMValueRef rel_auto_id;
97 LLVMValueRef vs_prim_id;
98 LLVMValueRef ls_out_layout;
99 LLVMValueRef es2gs_offset;
100
101 LLVMValueRef tcs_offchip_layout;
102 LLVMValueRef tcs_out_offsets;
103 LLVMValueRef tcs_out_layout;
104 LLVMValueRef tcs_in_layout;
105 LLVMValueRef oc_lds;
106 LLVMValueRef merged_wave_info;
107 LLVMValueRef tess_factor_offset;
108 LLVMValueRef tes_rel_patch_id;
109 LLVMValueRef tes_u;
110 LLVMValueRef tes_v;
111
112 LLVMValueRef gsvs_ring_stride;
113 LLVMValueRef gsvs_num_entries;
114 LLVMValueRef gs2vs_offset;
115 LLVMValueRef gs_wave_id;
116 LLVMValueRef gs_vtx_offset[6];
117
118 LLVMValueRef esgs_ring;
119 LLVMValueRef gsvs_ring;
120 LLVMValueRef hs_ring_tess_offchip;
121 LLVMValueRef hs_ring_tess_factor;
122
123 LLVMValueRef sample_pos_offset;
124 LLVMValueRef persp_sample, persp_center, persp_centroid;
125 LLVMValueRef linear_sample, linear_center, linear_centroid;
126
127 gl_shader_stage stage;
128
129 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
130
131 uint64_t input_mask;
132 uint64_t output_mask;
133 uint8_t num_output_clips;
134 uint8_t num_output_culls;
135
136 bool is_gs_copy_shader;
137 LLVMValueRef gs_next_vertex;
138 unsigned gs_max_out_vertices;
139
140 unsigned tes_primitive_mode;
141 uint64_t tess_outputs_written;
142 uint64_t tess_patch_outputs_written;
143
144 uint32_t tcs_patch_outputs_read;
145 uint64_t tcs_outputs_read;
146 };
147
148 static inline struct nir_to_llvm_context *
149 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
150 {
151 struct nir_to_llvm_context *ctx = NULL;
152 return container_of(abi, ctx, abi);
153 }
154
155 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
156 const nir_deref_var *deref,
157 enum ac_descriptor_type desc_type,
158 const nir_tex_instr *instr,
159 bool image, bool write);
160
161 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
162 {
163 return (index * 4) + chan;
164 }
165
166 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
167 {
168 /* handle patch indices separate */
169 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
170 return 0;
171 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
172 return 1;
173 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
174 return 2 + (slot - VARYING_SLOT_PATCH0);
175
176 if (slot == VARYING_SLOT_POS)
177 return 0;
178 if (slot == VARYING_SLOT_PSIZ)
179 return 1;
180 if (slot == VARYING_SLOT_CLIP_DIST0)
181 return 2;
182 /* 3 is reserved for clip dist as well */
183 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
184 return 4 + (slot - VARYING_SLOT_VAR0);
185 unreachable("illegal slot in get unique index\n");
186 }
187
188 static void set_llvm_calling_convention(LLVMValueRef func,
189 gl_shader_stage stage)
190 {
191 enum radeon_llvm_calling_convention calling_conv;
192
193 switch (stage) {
194 case MESA_SHADER_VERTEX:
195 case MESA_SHADER_TESS_EVAL:
196 calling_conv = RADEON_LLVM_AMDGPU_VS;
197 break;
198 case MESA_SHADER_GEOMETRY:
199 calling_conv = RADEON_LLVM_AMDGPU_GS;
200 break;
201 case MESA_SHADER_TESS_CTRL:
202 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
203 break;
204 case MESA_SHADER_FRAGMENT:
205 calling_conv = RADEON_LLVM_AMDGPU_PS;
206 break;
207 case MESA_SHADER_COMPUTE:
208 calling_conv = RADEON_LLVM_AMDGPU_CS;
209 break;
210 default:
211 unreachable("Unhandle shader type");
212 }
213
214 LLVMSetFunctionCallConv(func, calling_conv);
215 }
216
217 #define MAX_ARGS 23
218 struct arg_info {
219 LLVMTypeRef types[MAX_ARGS];
220 LLVMValueRef *assign[MAX_ARGS];
221 unsigned array_params_mask;
222 uint8_t count;
223 uint8_t sgpr_count;
224 uint8_t num_sgprs_used;
225 uint8_t num_vgprs_used;
226 };
227
228 enum ac_arg_regfile {
229 ARG_SGPR,
230 ARG_VGPR,
231 };
232
233 static void
234 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
235 LLVMValueRef *param_ptr)
236 {
237 assert(info->count < MAX_ARGS);
238
239 info->assign[info->count] = param_ptr;
240 info->types[info->count] = type;
241 info->count++;
242
243 if (regfile == ARG_SGPR) {
244 info->num_sgprs_used += ac_get_type_size(type) / 4;
245 info->sgpr_count++;
246 } else {
247 assert(regfile == ARG_VGPR);
248 info->num_vgprs_used += ac_get_type_size(type) / 4;
249 }
250 }
251
252 static inline void
253 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
254 {
255 info->array_params_mask |= (1 << info->count);
256 add_arg(info, ARG_SGPR, type, param_ptr);
257 }
258
259 static void assign_arguments(LLVMValueRef main_function,
260 struct arg_info *info)
261 {
262 unsigned i;
263 for (i = 0; i < info->count; i++) {
264 if (info->assign[i])
265 *info->assign[i] = LLVMGetParam(main_function, i);
266 }
267 }
268
269 static LLVMValueRef
270 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
271 LLVMBuilderRef builder, LLVMTypeRef *return_types,
272 unsigned num_return_elems,
273 struct arg_info *args,
274 unsigned max_workgroup_size,
275 bool unsafe_math)
276 {
277 LLVMTypeRef main_function_type, ret_type;
278 LLVMBasicBlockRef main_function_body;
279
280 if (num_return_elems)
281 ret_type = LLVMStructTypeInContext(ctx, return_types,
282 num_return_elems, true);
283 else
284 ret_type = LLVMVoidTypeInContext(ctx);
285
286 /* Setup the function */
287 main_function_type =
288 LLVMFunctionType(ret_type, args->types, args->count, 0);
289 LLVMValueRef main_function =
290 LLVMAddFunction(module, "main", main_function_type);
291 main_function_body =
292 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
293 LLVMPositionBuilderAtEnd(builder, main_function_body);
294
295 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
296 for (unsigned i = 0; i < args->sgpr_count; ++i) {
297 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
298
299 if (args->array_params_mask & (1 << i)) {
300 LLVMValueRef P = LLVMGetParam(main_function, i);
301 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
302 ac_add_attr_dereferenceable(P, UINT64_MAX);
303 }
304 }
305
306 if (max_workgroup_size) {
307 ac_llvm_add_target_dep_function_attr(main_function,
308 "amdgpu-max-work-group-size",
309 max_workgroup_size);
310 }
311 if (unsafe_math) {
312 /* These were copied from some LLVM test. */
313 LLVMAddTargetDependentFunctionAttr(main_function,
314 "less-precise-fpmad",
315 "true");
316 LLVMAddTargetDependentFunctionAttr(main_function,
317 "no-infs-fp-math",
318 "true");
319 LLVMAddTargetDependentFunctionAttr(main_function,
320 "no-nans-fp-math",
321 "true");
322 LLVMAddTargetDependentFunctionAttr(main_function,
323 "unsafe-fp-math",
324 "true");
325 LLVMAddTargetDependentFunctionAttr(main_function,
326 "no-signed-zeros-fp-math",
327 "true");
328 }
329 return main_function;
330 }
331
332 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
333 LLVMValueRef param, unsigned rshift,
334 unsigned bitwidth)
335 {
336 LLVMValueRef value = param;
337 if (rshift)
338 value = LLVMBuildLShr(ctx->builder, value,
339 LLVMConstInt(ctx->i32, rshift, false), "");
340
341 if (rshift + bitwidth < 32) {
342 unsigned mask = (1 << bitwidth) - 1;
343 value = LLVMBuildAnd(ctx->builder, value,
344 LLVMConstInt(ctx->i32, mask, false), "");
345 }
346 return value;
347 }
348
349 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
350 {
351 switch (ctx->stage) {
352 case MESA_SHADER_TESS_CTRL:
353 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
354 case MESA_SHADER_TESS_EVAL:
355 return ctx->tes_rel_patch_id;
356 break;
357 default:
358 unreachable("Illegal stage");
359 }
360 }
361
362 /* Tessellation shaders pass outputs to the next shader using LDS.
363 *
364 * LS outputs = TCS inputs
365 * TCS outputs = TES inputs
366 *
367 * The LDS layout is:
368 * - TCS inputs for patch 0
369 * - TCS inputs for patch 1
370 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
371 * - ...
372 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
373 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
374 * - TCS outputs for patch 1
375 * - Per-patch TCS outputs for patch 1
376 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
377 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
378 * - ...
379 *
380 * All three shaders VS(LS), TCS, TES share the same LDS space.
381 */
382 static LLVMValueRef
383 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
384 {
385 if (ctx->stage == MESA_SHADER_VERTEX)
386 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
387 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
388 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
389 else {
390 assert(0);
391 return NULL;
392 }
393 }
394
395 static LLVMValueRef
396 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
397 {
398 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
399 }
400
401 static LLVMValueRef
402 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
403 {
404 return LLVMBuildMul(ctx->builder,
405 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
406 LLVMConstInt(ctx->ac.i32, 4, false), "");
407 }
408
409 static LLVMValueRef
410 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
411 {
412 return LLVMBuildMul(ctx->builder,
413 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
414 LLVMConstInt(ctx->ac.i32, 4, false), "");
415 }
416
417 static LLVMValueRef
418 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
419 {
420 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
421 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
422
423 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
424 }
425
426 static LLVMValueRef
427 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
428 {
429 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
430 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
431 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
432
433 return LLVMBuildAdd(ctx->builder, patch0_offset,
434 LLVMBuildMul(ctx->builder, patch_stride,
435 rel_patch_id, ""),
436 "");
437 }
438
439 static LLVMValueRef
440 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
441 {
442 LLVMValueRef patch0_patch_data_offset =
443 get_tcs_out_patch0_patch_data_offset(ctx);
444 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
445 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
446
447 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
448 LLVMBuildMul(ctx->builder, patch_stride,
449 rel_patch_id, ""),
450 "");
451 }
452
453 static void
454 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
455 uint32_t indirect_offset)
456 {
457 ud_info->sgpr_idx = *sgpr_idx;
458 ud_info->num_sgprs = num_sgprs;
459 ud_info->indirect = indirect_offset > 0;
460 ud_info->indirect_offset = indirect_offset;
461 *sgpr_idx += num_sgprs;
462 }
463
464 static void
465 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
466 uint8_t num_sgprs)
467 {
468 struct ac_userdata_info *ud_info =
469 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
470 assert(ud_info);
471
472 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
473 }
474
475 static void
476 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
477 uint32_t indirect_offset)
478 {
479 struct ac_userdata_info *ud_info =
480 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
481 assert(ud_info);
482
483 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
484 }
485
486 struct user_sgpr_info {
487 bool need_ring_offsets;
488 uint8_t sgpr_count;
489 bool indirect_all_descriptor_sets;
490 };
491
492 static bool needs_view_index_sgpr(struct nir_to_llvm_context *ctx,
493 gl_shader_stage stage)
494 {
495 switch (stage) {
496 case MESA_SHADER_VERTEX:
497 if (ctx->shader_info->info.needs_multiview_view_index ||
498 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
499 return true;
500 break;
501 case MESA_SHADER_TESS_EVAL:
502 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
503 return true;
504 break;
505 case MESA_SHADER_GEOMETRY:
506 case MESA_SHADER_TESS_CTRL:
507 if (ctx->shader_info->info.needs_multiview_view_index)
508 return true;
509 break;
510 default:
511 break;
512 }
513 return false;
514 }
515
516 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
517 gl_shader_stage stage,
518 bool needs_view_index,
519 struct user_sgpr_info *user_sgpr_info)
520 {
521 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
522
523 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
524 if (stage == MESA_SHADER_GEOMETRY ||
525 stage == MESA_SHADER_VERTEX ||
526 stage == MESA_SHADER_TESS_CTRL ||
527 stage == MESA_SHADER_TESS_EVAL ||
528 ctx->is_gs_copy_shader)
529 user_sgpr_info->need_ring_offsets = true;
530
531 if (stage == MESA_SHADER_FRAGMENT &&
532 ctx->shader_info->info.ps.needs_sample_positions)
533 user_sgpr_info->need_ring_offsets = true;
534
535 /* 2 user sgprs will nearly always be allocated for scratch/rings */
536 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
537 user_sgpr_info->sgpr_count += 2;
538 }
539
540 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
541 switch (stage) {
542 case MESA_SHADER_COMPUTE:
543 if (ctx->shader_info->info.cs.uses_grid_size)
544 user_sgpr_info->sgpr_count += 3;
545 break;
546 case MESA_SHADER_FRAGMENT:
547 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
548 break;
549 case MESA_SHADER_VERTEX:
550 if (!ctx->is_gs_copy_shader) {
551 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
552 if (ctx->shader_info->info.vs.needs_draw_id) {
553 user_sgpr_info->sgpr_count += 3;
554 } else {
555 user_sgpr_info->sgpr_count += 2;
556 }
557 }
558 if (ctx->options->key.vs.as_ls)
559 user_sgpr_info->sgpr_count++;
560 break;
561 case MESA_SHADER_TESS_CTRL:
562 user_sgpr_info->sgpr_count += 4;
563 break;
564 case MESA_SHADER_TESS_EVAL:
565 user_sgpr_info->sgpr_count += 1;
566 break;
567 case MESA_SHADER_GEOMETRY:
568 user_sgpr_info->sgpr_count += 2;
569 break;
570 default:
571 break;
572 }
573
574 if (needs_view_index)
575 user_sgpr_info->sgpr_count++;
576
577 if (ctx->shader_info->info.loads_push_constants)
578 user_sgpr_info->sgpr_count += 2;
579
580 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
581 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
582
583 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
584 user_sgpr_info->sgpr_count += 2;
585 user_sgpr_info->indirect_all_descriptor_sets = true;
586 } else {
587 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
588 }
589 }
590
591 static void
592 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
593 gl_shader_stage stage,
594 bool has_previous_stage,
595 gl_shader_stage previous_stage,
596 const struct user_sgpr_info *user_sgpr_info,
597 struct arg_info *args,
598 LLVMValueRef *desc_sets)
599 {
600 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
601 unsigned num_sets = ctx->options->layout ?
602 ctx->options->layout->num_sets : 0;
603 unsigned stage_mask = 1 << stage;
604
605 if (has_previous_stage)
606 stage_mask |= 1 << previous_stage;
607
608 /* 1 for each descriptor set */
609 if (!user_sgpr_info->indirect_all_descriptor_sets) {
610 for (unsigned i = 0; i < num_sets; ++i) {
611 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
612 add_array_arg(args, type,
613 &ctx->descriptor_sets[i]);
614 }
615 }
616 } else {
617 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
618 }
619
620 if (ctx->shader_info->info.loads_push_constants) {
621 /* 1 for push constants and dynamic descriptors */
622 add_array_arg(args, type, &ctx->push_constants);
623 }
624 }
625
626 static void
627 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
628 gl_shader_stage stage,
629 bool has_previous_stage,
630 gl_shader_stage previous_stage,
631 struct arg_info *args)
632 {
633 if (!ctx->is_gs_copy_shader &&
634 (stage == MESA_SHADER_VERTEX ||
635 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
636 if (ctx->shader_info->info.vs.has_vertex_buffers) {
637 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
638 &ctx->vertex_buffers);
639 }
640 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
641 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
642 if (ctx->shader_info->info.vs.needs_draw_id) {
643 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
644 }
645 }
646 }
647
648 static void
649 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
650 {
651 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
652 if (!ctx->is_gs_copy_shader) {
653 if (ctx->options->key.vs.as_ls) {
654 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
655 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
656 } else {
657 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
658 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
659 }
660 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
661 }
662 }
663
664 static void
665 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
666 {
667 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
668 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
669 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
670 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
671 }
672
673 static void
674 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
675 bool has_previous_stage, gl_shader_stage previous_stage,
676 const struct user_sgpr_info *user_sgpr_info,
677 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
678 {
679 unsigned num_sets = ctx->options->layout ?
680 ctx->options->layout->num_sets : 0;
681 unsigned stage_mask = 1 << stage;
682
683 if (has_previous_stage)
684 stage_mask |= 1 << previous_stage;
685
686 if (!user_sgpr_info->indirect_all_descriptor_sets) {
687 for (unsigned i = 0; i < num_sets; ++i) {
688 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
689 set_loc_desc(ctx, i, user_sgpr_idx, 0);
690 } else
691 ctx->descriptor_sets[i] = NULL;
692 }
693 } else {
694 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
695 user_sgpr_idx, 2);
696
697 for (unsigned i = 0; i < num_sets; ++i) {
698 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
699 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
700 ctx->descriptor_sets[i] =
701 ac_build_load_to_sgpr(&ctx->ac,
702 desc_sets,
703 LLVMConstInt(ctx->ac.i32, i, false));
704
705 } else
706 ctx->descriptor_sets[i] = NULL;
707 }
708 ctx->shader_info->need_indirect_descriptor_sets = true;
709 }
710
711 if (ctx->shader_info->info.loads_push_constants) {
712 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
713 }
714 }
715
716 static void
717 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
718 gl_shader_stage stage, bool has_previous_stage,
719 gl_shader_stage previous_stage,
720 uint8_t *user_sgpr_idx)
721 {
722 if (!ctx->is_gs_copy_shader &&
723 (stage == MESA_SHADER_VERTEX ||
724 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
725 if (ctx->shader_info->info.vs.has_vertex_buffers) {
726 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
727 user_sgpr_idx, 2);
728 }
729
730 unsigned vs_num = 2;
731 if (ctx->shader_info->info.vs.needs_draw_id)
732 vs_num++;
733
734 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
735 user_sgpr_idx, vs_num);
736 }
737 }
738
739 static void create_function(struct nir_to_llvm_context *ctx,
740 gl_shader_stage stage,
741 bool has_previous_stage,
742 gl_shader_stage previous_stage)
743 {
744 uint8_t user_sgpr_idx;
745 struct user_sgpr_info user_sgpr_info;
746 struct arg_info args = {};
747 LLVMValueRef desc_sets;
748 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
749 allocate_user_sgprs(ctx, stage, needs_view_index, &user_sgpr_info);
750
751 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
752 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
753 &ctx->ring_offsets);
754 }
755
756 switch (stage) {
757 case MESA_SHADER_COMPUTE:
758 declare_global_input_sgprs(ctx, stage, has_previous_stage,
759 previous_stage, &user_sgpr_info,
760 &args, &desc_sets);
761
762 if (ctx->shader_info->info.cs.uses_grid_size) {
763 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
764 &ctx->abi.num_work_groups);
765 }
766
767 for (int i = 0; i < 3; i++) {
768 ctx->abi.workgroup_ids[i] = NULL;
769 if (ctx->shader_info->info.cs.uses_block_id[i]) {
770 add_arg(&args, ARG_SGPR, ctx->ac.i32,
771 &ctx->abi.workgroup_ids[i]);
772 }
773 }
774
775 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
776 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
777 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
778 &ctx->abi.local_invocation_ids);
779 break;
780 case MESA_SHADER_VERTEX:
781 declare_global_input_sgprs(ctx, stage, has_previous_stage,
782 previous_stage, &user_sgpr_info,
783 &args, &desc_sets);
784 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
785 previous_stage, &args);
786
787 if (needs_view_index)
788 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
789 if (ctx->options->key.vs.as_es)
790 add_arg(&args, ARG_SGPR, ctx->ac.i32,
791 &ctx->es2gs_offset);
792 else if (ctx->options->key.vs.as_ls)
793 add_arg(&args, ARG_SGPR, ctx->ac.i32,
794 &ctx->ls_out_layout);
795
796 declare_vs_input_vgprs(ctx, &args);
797 break;
798 case MESA_SHADER_TESS_CTRL:
799 if (has_previous_stage) {
800 // First 6 system regs
801 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
802 add_arg(&args, ARG_SGPR, ctx->ac.i32,
803 &ctx->merged_wave_info);
804 add_arg(&args, ARG_SGPR, ctx->ac.i32,
805 &ctx->tess_factor_offset);
806
807 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
808 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
809 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
810
811 declare_global_input_sgprs(ctx, stage,
812 has_previous_stage,
813 previous_stage,
814 &user_sgpr_info, &args,
815 &desc_sets);
816 declare_vs_specific_input_sgprs(ctx, stage,
817 has_previous_stage,
818 previous_stage, &args);
819
820 add_arg(&args, ARG_SGPR, ctx->ac.i32,
821 &ctx->ls_out_layout);
822
823 add_arg(&args, ARG_SGPR, ctx->ac.i32,
824 &ctx->tcs_offchip_layout);
825 add_arg(&args, ARG_SGPR, ctx->ac.i32,
826 &ctx->tcs_out_offsets);
827 add_arg(&args, ARG_SGPR, ctx->ac.i32,
828 &ctx->tcs_out_layout);
829 add_arg(&args, ARG_SGPR, ctx->ac.i32,
830 &ctx->tcs_in_layout);
831 if (needs_view_index)
832 add_arg(&args, ARG_SGPR, ctx->ac.i32,
833 &ctx->view_index);
834
835 add_arg(&args, ARG_VGPR, ctx->ac.i32,
836 &ctx->abi.tcs_patch_id);
837 add_arg(&args, ARG_VGPR, ctx->ac.i32,
838 &ctx->abi.tcs_rel_ids);
839
840 declare_vs_input_vgprs(ctx, &args);
841 } else {
842 declare_global_input_sgprs(ctx, stage,
843 has_previous_stage,
844 previous_stage,
845 &user_sgpr_info, &args,
846 &desc_sets);
847
848 add_arg(&args, ARG_SGPR, ctx->ac.i32,
849 &ctx->tcs_offchip_layout);
850 add_arg(&args, ARG_SGPR, ctx->ac.i32,
851 &ctx->tcs_out_offsets);
852 add_arg(&args, ARG_SGPR, ctx->ac.i32,
853 &ctx->tcs_out_layout);
854 add_arg(&args, ARG_SGPR, ctx->ac.i32,
855 &ctx->tcs_in_layout);
856 if (needs_view_index)
857 add_arg(&args, ARG_SGPR, ctx->ac.i32,
858 &ctx->view_index);
859
860 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
861 add_arg(&args, ARG_SGPR, ctx->ac.i32,
862 &ctx->tess_factor_offset);
863 add_arg(&args, ARG_VGPR, ctx->ac.i32,
864 &ctx->abi.tcs_patch_id);
865 add_arg(&args, ARG_VGPR, ctx->ac.i32,
866 &ctx->abi.tcs_rel_ids);
867 }
868 break;
869 case MESA_SHADER_TESS_EVAL:
870 declare_global_input_sgprs(ctx, stage, has_previous_stage,
871 previous_stage, &user_sgpr_info,
872 &args, &desc_sets);
873
874 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
875 if (needs_view_index)
876 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
877
878 if (ctx->options->key.tes.as_es) {
879 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
880 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
881 add_arg(&args, ARG_SGPR, ctx->ac.i32,
882 &ctx->es2gs_offset);
883 } else {
884 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
885 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
886 }
887 declare_tes_input_vgprs(ctx, &args);
888 break;
889 case MESA_SHADER_GEOMETRY:
890 if (has_previous_stage) {
891 // First 6 system regs
892 add_arg(&args, ARG_SGPR, ctx->ac.i32,
893 &ctx->gs2vs_offset);
894 add_arg(&args, ARG_SGPR, ctx->ac.i32,
895 &ctx->merged_wave_info);
896 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
897
898 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
900 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
901
902 declare_global_input_sgprs(ctx, stage,
903 has_previous_stage,
904 previous_stage,
905 &user_sgpr_info, &args,
906 &desc_sets);
907
908 if (previous_stage == MESA_SHADER_TESS_EVAL) {
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->tcs_offchip_layout);
911 } else {
912 declare_vs_specific_input_sgprs(ctx, stage,
913 has_previous_stage,
914 previous_stage,
915 &args);
916 }
917
918 add_arg(&args, ARG_SGPR, ctx->ac.i32,
919 &ctx->gsvs_ring_stride);
920 add_arg(&args, ARG_SGPR, ctx->ac.i32,
921 &ctx->gsvs_num_entries);
922 if (needs_view_index)
923 add_arg(&args, ARG_SGPR, ctx->ac.i32,
924 &ctx->view_index);
925
926 add_arg(&args, ARG_VGPR, ctx->ac.i32,
927 &ctx->gs_vtx_offset[0]);
928 add_arg(&args, ARG_VGPR, ctx->ac.i32,
929 &ctx->gs_vtx_offset[2]);
930 add_arg(&args, ARG_VGPR, ctx->ac.i32,
931 &ctx->abi.gs_prim_id);
932 add_arg(&args, ARG_VGPR, ctx->ac.i32,
933 &ctx->abi.gs_invocation_id);
934 add_arg(&args, ARG_VGPR, ctx->ac.i32,
935 &ctx->gs_vtx_offset[4]);
936
937 if (previous_stage == MESA_SHADER_VERTEX) {
938 declare_vs_input_vgprs(ctx, &args);
939 } else {
940 declare_tes_input_vgprs(ctx, &args);
941 }
942 } else {
943 declare_global_input_sgprs(ctx, stage,
944 has_previous_stage,
945 previous_stage,
946 &user_sgpr_info, &args,
947 &desc_sets);
948
949 add_arg(&args, ARG_SGPR, ctx->ac.i32,
950 &ctx->gsvs_ring_stride);
951 add_arg(&args, ARG_SGPR, ctx->ac.i32,
952 &ctx->gsvs_num_entries);
953 if (needs_view_index)
954 add_arg(&args, ARG_SGPR, ctx->ac.i32,
955 &ctx->view_index);
956
957 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
958 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
959 add_arg(&args, ARG_VGPR, ctx->ac.i32,
960 &ctx->gs_vtx_offset[0]);
961 add_arg(&args, ARG_VGPR, ctx->ac.i32,
962 &ctx->gs_vtx_offset[1]);
963 add_arg(&args, ARG_VGPR, ctx->ac.i32,
964 &ctx->abi.gs_prim_id);
965 add_arg(&args, ARG_VGPR, ctx->ac.i32,
966 &ctx->gs_vtx_offset[2]);
967 add_arg(&args, ARG_VGPR, ctx->ac.i32,
968 &ctx->gs_vtx_offset[3]);
969 add_arg(&args, ARG_VGPR, ctx->ac.i32,
970 &ctx->gs_vtx_offset[4]);
971 add_arg(&args, ARG_VGPR, ctx->ac.i32,
972 &ctx->gs_vtx_offset[5]);
973 add_arg(&args, ARG_VGPR, ctx->ac.i32,
974 &ctx->abi.gs_invocation_id);
975 }
976 break;
977 case MESA_SHADER_FRAGMENT:
978 declare_global_input_sgprs(ctx, stage, has_previous_stage,
979 previous_stage, &user_sgpr_info,
980 &args, &desc_sets);
981
982 if (ctx->shader_info->info.ps.needs_sample_positions)
983 add_arg(&args, ARG_SGPR, ctx->ac.i32,
984 &ctx->sample_pos_offset);
985
986 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
987 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
988 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
989 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
990 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
991 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
992 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
993 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
994 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
995 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
996 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
997 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
998 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
999 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1000 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1001 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1002 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1003 break;
1004 default:
1005 unreachable("Shader stage not implemented");
1006 }
1007
1008 ctx->main_function = create_llvm_function(
1009 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1010 ctx->max_workgroup_size,
1011 ctx->options->unsafe_math);
1012 set_llvm_calling_convention(ctx->main_function, stage);
1013
1014
1015 ctx->shader_info->num_input_vgprs = 0;
1016 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1017
1018 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1019
1020 if (ctx->stage != MESA_SHADER_FRAGMENT)
1021 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1022
1023 assign_arguments(ctx->main_function, &args);
1024
1025 user_sgpr_idx = 0;
1026
1027 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1028 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1029 &user_sgpr_idx, 2);
1030 if (ctx->options->supports_spill) {
1031 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1032 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1033 NULL, 0, AC_FUNC_ATTR_READNONE);
1034 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1035 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1036 }
1037 }
1038
1039 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1040 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1041 if (has_previous_stage)
1042 user_sgpr_idx = 0;
1043
1044 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1045 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1046
1047 switch (stage) {
1048 case MESA_SHADER_COMPUTE:
1049 if (ctx->shader_info->info.cs.uses_grid_size) {
1050 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1051 &user_sgpr_idx, 3);
1052 }
1053 break;
1054 case MESA_SHADER_VERTEX:
1055 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1056 previous_stage, &user_sgpr_idx);
1057 if (ctx->view_index)
1058 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1059 if (ctx->options->key.vs.as_ls) {
1060 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1061 &user_sgpr_idx, 1);
1062 }
1063 if (ctx->options->key.vs.as_ls)
1064 ac_declare_lds_as_pointer(&ctx->ac);
1065 break;
1066 case MESA_SHADER_TESS_CTRL:
1067 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1068 previous_stage, &user_sgpr_idx);
1069 if (has_previous_stage)
1070 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1071 &user_sgpr_idx, 1);
1072 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1073 if (ctx->view_index)
1074 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1075 ac_declare_lds_as_pointer(&ctx->ac);
1076 break;
1077 case MESA_SHADER_TESS_EVAL:
1078 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1079 if (ctx->view_index)
1080 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1081 break;
1082 case MESA_SHADER_GEOMETRY:
1083 if (has_previous_stage) {
1084 if (previous_stage == MESA_SHADER_VERTEX)
1085 set_vs_specific_input_locs(ctx, stage,
1086 has_previous_stage,
1087 previous_stage,
1088 &user_sgpr_idx);
1089 else
1090 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1091 &user_sgpr_idx, 1);
1092 }
1093 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1094 &user_sgpr_idx, 2);
1095 if (ctx->view_index)
1096 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1097 if (has_previous_stage)
1098 ac_declare_lds_as_pointer(&ctx->ac);
1099 break;
1100 case MESA_SHADER_FRAGMENT:
1101 if (ctx->shader_info->info.ps.needs_sample_positions) {
1102 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1103 &user_sgpr_idx, 1);
1104 }
1105 break;
1106 default:
1107 unreachable("Shader stage not implemented");
1108 }
1109
1110 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1111 }
1112
1113 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1114 LLVMValueRef value, unsigned count)
1115 {
1116 unsigned num_components = ac_get_llvm_num_components(value);
1117 if (count == num_components)
1118 return value;
1119
1120 LLVMValueRef masks[] = {
1121 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1122 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1123
1124 if (count == 1)
1125 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1126 "");
1127
1128 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1129 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1130 }
1131
1132 static void
1133 build_store_values_extended(struct ac_llvm_context *ac,
1134 LLVMValueRef *values,
1135 unsigned value_count,
1136 unsigned value_stride,
1137 LLVMValueRef vec)
1138 {
1139 LLVMBuilderRef builder = ac->builder;
1140 unsigned i;
1141
1142 for (i = 0; i < value_count; i++) {
1143 LLVMValueRef ptr = values[i * value_stride];
1144 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1145 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1146 LLVMBuildStore(builder, value, ptr);
1147 }
1148 }
1149
1150 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1151 const nir_ssa_def *def)
1152 {
1153 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1154 if (def->num_components > 1) {
1155 type = LLVMVectorType(type, def->num_components);
1156 }
1157 return type;
1158 }
1159
1160 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1161 {
1162 assert(src.is_ssa);
1163 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1164 return (LLVMValueRef)entry->data;
1165 }
1166
1167
1168 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1169 const struct nir_block *b)
1170 {
1171 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1172 return (LLVMBasicBlockRef)entry->data;
1173 }
1174
1175 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1176 nir_alu_src src,
1177 unsigned num_components)
1178 {
1179 LLVMValueRef value = get_src(ctx, src.src);
1180 bool need_swizzle = false;
1181
1182 assert(value);
1183 LLVMTypeRef type = LLVMTypeOf(value);
1184 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1185 ? LLVMGetVectorSize(type)
1186 : 1;
1187
1188 for (unsigned i = 0; i < num_components; ++i) {
1189 assert(src.swizzle[i] < src_components);
1190 if (src.swizzle[i] != i)
1191 need_swizzle = true;
1192 }
1193
1194 if (need_swizzle || num_components != src_components) {
1195 LLVMValueRef masks[] = {
1196 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1197 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1198 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1199 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1200
1201 if (src_components > 1 && num_components == 1) {
1202 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1203 masks[0], "");
1204 } else if (src_components == 1 && num_components > 1) {
1205 LLVMValueRef values[] = {value, value, value, value};
1206 value = ac_build_gather_values(&ctx->ac, values, num_components);
1207 } else {
1208 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1209 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1210 swizzle, "");
1211 }
1212 }
1213 assert(!src.negate);
1214 assert(!src.abs);
1215 return value;
1216 }
1217
1218 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1219 LLVMIntPredicate pred, LLVMValueRef src0,
1220 LLVMValueRef src1)
1221 {
1222 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1223 return LLVMBuildSelect(ctx->builder, result,
1224 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1225 ctx->i32_0, "");
1226 }
1227
1228 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1229 LLVMRealPredicate pred, LLVMValueRef src0,
1230 LLVMValueRef src1)
1231 {
1232 LLVMValueRef result;
1233 src0 = ac_to_float(ctx, src0);
1234 src1 = ac_to_float(ctx, src1);
1235 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1236 return LLVMBuildSelect(ctx->builder, result,
1237 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1238 ctx->i32_0, "");
1239 }
1240
1241 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1242 const char *intrin,
1243 LLVMTypeRef result_type,
1244 LLVMValueRef src0)
1245 {
1246 char name[64];
1247 LLVMValueRef params[] = {
1248 ac_to_float(ctx, src0),
1249 };
1250
1251 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1252 ac_get_elem_bits(ctx, result_type));
1253 assert(length < sizeof(name));
1254 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1255 }
1256
1257 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1258 const char *intrin,
1259 LLVMTypeRef result_type,
1260 LLVMValueRef src0, LLVMValueRef src1)
1261 {
1262 char name[64];
1263 LLVMValueRef params[] = {
1264 ac_to_float(ctx, src0),
1265 ac_to_float(ctx, src1),
1266 };
1267
1268 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1269 ac_get_elem_bits(ctx, result_type));
1270 assert(length < sizeof(name));
1271 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1272 }
1273
1274 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1275 const char *intrin,
1276 LLVMTypeRef result_type,
1277 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1278 {
1279 char name[64];
1280 LLVMValueRef params[] = {
1281 ac_to_float(ctx, src0),
1282 ac_to_float(ctx, src1),
1283 ac_to_float(ctx, src2),
1284 };
1285
1286 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1287 ac_get_elem_bits(ctx, result_type));
1288 assert(length < sizeof(name));
1289 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1290 }
1291
1292 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1293 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1294 {
1295 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1296 ctx->i32_0, "");
1297 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1298 }
1299
1300 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1301 LLVMIntPredicate pred,
1302 LLVMValueRef src0, LLVMValueRef src1)
1303 {
1304 return LLVMBuildSelect(ctx->builder,
1305 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1306 src0,
1307 src1, "");
1308
1309 }
1310 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1311 LLVMValueRef src0)
1312 {
1313 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1314 LLVMBuildNeg(ctx->builder, src0, ""));
1315 }
1316
1317 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1318 LLVMValueRef src0,
1319 unsigned bitsize)
1320 {
1321 LLVMValueRef cmp, val, zero, one;
1322 LLVMTypeRef type;
1323
1324 if (bitsize == 32) {
1325 type = ctx->f32;
1326 zero = ctx->f32_0;
1327 one = ctx->f32_1;
1328 } else {
1329 type = ctx->f64;
1330 zero = ctx->f64_0;
1331 one = ctx->f64_1;
1332 }
1333
1334 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1335 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1336 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1337 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1338 return val;
1339 }
1340
1341 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1342 LLVMValueRef src0, unsigned bitsize)
1343 {
1344 LLVMValueRef cmp, val, zero, one;
1345 LLVMTypeRef type;
1346
1347 if (bitsize == 32) {
1348 type = ctx->i32;
1349 zero = ctx->i32_0;
1350 one = ctx->i32_1;
1351 } else {
1352 type = ctx->i64;
1353 zero = ctx->i64_0;
1354 one = ctx->i64_1;
1355 }
1356
1357 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1358 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1359 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1360 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1361 return val;
1362 }
1363
1364 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1365 LLVMValueRef src0, unsigned bitsize)
1366 {
1367 LLVMTypeRef type;
1368 char *intr;
1369
1370 if (bitsize == 32) {
1371 intr = "llvm.floor.f32";
1372 type = ctx->f32;
1373 } else {
1374 intr = "llvm.floor.f64";
1375 type = ctx->f64;
1376 }
1377
1378 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1379 LLVMValueRef params[] = {
1380 fsrc0,
1381 };
1382 LLVMValueRef floor = ac_build_intrinsic(ctx, intr, type, params, 1,
1383 AC_FUNC_ATTR_READNONE);
1384 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1385 }
1386
1387 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1388 const char *intrin,
1389 LLVMValueRef src0, LLVMValueRef src1)
1390 {
1391 LLVMTypeRef ret_type;
1392 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1393 LLVMValueRef res;
1394 LLVMValueRef params[] = { src0, src1 };
1395 ret_type = LLVMStructTypeInContext(ctx->context, types,
1396 2, true);
1397
1398 res = ac_build_intrinsic(ctx, intrin, ret_type,
1399 params, 2, AC_FUNC_ATTR_READNONE);
1400
1401 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1402 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1403 return res;
1404 }
1405
1406 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1407 LLVMValueRef src0)
1408 {
1409 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1410 }
1411
1412 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1413 LLVMValueRef src0)
1414 {
1415 src0 = ac_to_float(ctx, src0);
1416 return LLVMBuildSExt(ctx->builder,
1417 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1418 ctx->i32, "");
1419 }
1420
1421 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1422 LLVMValueRef src0,
1423 unsigned bitsize)
1424 {
1425 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1426
1427 if (bitsize == 32)
1428 return result;
1429
1430 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1431 }
1432
1433 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1434 LLVMValueRef src0)
1435 {
1436 return LLVMBuildSExt(ctx->builder,
1437 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1438 ctx->i32, "");
1439 }
1440
1441 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1442 LLVMValueRef src0)
1443 {
1444 LLVMValueRef result;
1445 LLVMValueRef cond = NULL;
1446
1447 src0 = ac_to_float(&ctx->ac, src0);
1448 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1449
1450 if (ctx->options->chip_class >= VI) {
1451 LLVMValueRef args[2];
1452 /* Check if the result is a denormal - and flush to 0 if so. */
1453 args[0] = result;
1454 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1455 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1456 }
1457
1458 /* need to convert back up to f32 */
1459 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1460
1461 if (ctx->options->chip_class >= VI)
1462 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1463 else {
1464 /* for SI/CIK */
1465 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1466 * so compare the result and flush to 0 if it's smaller.
1467 */
1468 LLVMValueRef temp, cond2;
1469 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1470 ctx->ac.f32, result);
1471 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1472 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1473 temp, "");
1474 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1475 temp, ctx->ac.f32_0, "");
1476 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1477 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1478 }
1479 return result;
1480 }
1481
1482 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1483 LLVMValueRef src0, LLVMValueRef src1)
1484 {
1485 LLVMValueRef dst64, result;
1486 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1487 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1488
1489 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1490 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1491 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1492 return result;
1493 }
1494
1495 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1496 LLVMValueRef src0, LLVMValueRef src1)
1497 {
1498 LLVMValueRef dst64, result;
1499 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1500 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1501
1502 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1503 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1504 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1505 return result;
1506 }
1507
1508 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1509 bool is_signed,
1510 const LLVMValueRef srcs[3])
1511 {
1512 LLVMValueRef result;
1513 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1514
1515 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1516 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1517 return result;
1518 }
1519
1520 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1521 LLVMValueRef src0, LLVMValueRef src1,
1522 LLVMValueRef src2, LLVMValueRef src3)
1523 {
1524 LLVMValueRef bfi_args[3], result;
1525
1526 bfi_args[0] = LLVMBuildShl(ctx->builder,
1527 LLVMBuildSub(ctx->builder,
1528 LLVMBuildShl(ctx->builder,
1529 ctx->i32_1,
1530 src3, ""),
1531 ctx->i32_1, ""),
1532 src2, "");
1533 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1534 bfi_args[2] = src0;
1535
1536 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1537
1538 /* Calculate:
1539 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1540 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1541 */
1542 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1543 LLVMBuildAnd(ctx->builder, bfi_args[0],
1544 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1545
1546 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1547 return result;
1548 }
1549
1550 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1551 LLVMValueRef src0)
1552 {
1553 LLVMValueRef comp[2];
1554
1555 src0 = ac_to_float(ctx, src0);
1556 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1557 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1558
1559 return ac_build_cvt_pkrtz_f16(ctx, comp);
1560 }
1561
1562 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1563 LLVMValueRef src0)
1564 {
1565 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1566 LLVMValueRef temps[2], result, val;
1567 int i;
1568
1569 for (i = 0; i < 2; i++) {
1570 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1571 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1572 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1573 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1574 }
1575
1576 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1577 ctx->i32_0, "");
1578 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1579 ctx->i32_1, "");
1580 return result;
1581 }
1582
1583 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1584 nir_op op,
1585 LLVMValueRef src0)
1586 {
1587 unsigned mask;
1588 int idx;
1589 LLVMValueRef result;
1590
1591 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1592 mask = AC_TID_MASK_LEFT;
1593 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1594 mask = AC_TID_MASK_TOP;
1595 else
1596 mask = AC_TID_MASK_TOP_LEFT;
1597
1598 /* for DDX we want to next X pixel, DDY next Y pixel. */
1599 if (op == nir_op_fddx_fine ||
1600 op == nir_op_fddx_coarse ||
1601 op == nir_op_fddx)
1602 idx = 1;
1603 else
1604 idx = 2;
1605
1606 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1607 return result;
1608 }
1609
1610 /*
1611 * this takes an I,J coordinate pair,
1612 * and works out the X and Y derivatives.
1613 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1614 */
1615 static LLVMValueRef emit_ddxy_interp(
1616 struct ac_nir_context *ctx,
1617 LLVMValueRef interp_ij)
1618 {
1619 LLVMValueRef result[4], a;
1620 unsigned i;
1621
1622 for (i = 0; i < 2; i++) {
1623 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1624 LLVMConstInt(ctx->ac.i32, i, false), "");
1625 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1626 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1627 }
1628 return ac_build_gather_values(&ctx->ac, result, 4);
1629 }
1630
1631 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1632 {
1633 LLVMValueRef src[4], result = NULL;
1634 unsigned num_components = instr->dest.dest.ssa.num_components;
1635 unsigned src_components;
1636 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1637
1638 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1639 switch (instr->op) {
1640 case nir_op_vec2:
1641 case nir_op_vec3:
1642 case nir_op_vec4:
1643 src_components = 1;
1644 break;
1645 case nir_op_pack_half_2x16:
1646 src_components = 2;
1647 break;
1648 case nir_op_unpack_half_2x16:
1649 src_components = 1;
1650 break;
1651 default:
1652 src_components = num_components;
1653 break;
1654 }
1655 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1656 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1657
1658 switch (instr->op) {
1659 case nir_op_fmov:
1660 case nir_op_imov:
1661 result = src[0];
1662 break;
1663 case nir_op_fneg:
1664 src[0] = ac_to_float(&ctx->ac, src[0]);
1665 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1666 break;
1667 case nir_op_ineg:
1668 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1669 break;
1670 case nir_op_inot:
1671 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1672 break;
1673 case nir_op_iadd:
1674 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1675 break;
1676 case nir_op_fadd:
1677 src[0] = ac_to_float(&ctx->ac, src[0]);
1678 src[1] = ac_to_float(&ctx->ac, src[1]);
1679 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1680 break;
1681 case nir_op_fsub:
1682 src[0] = ac_to_float(&ctx->ac, src[0]);
1683 src[1] = ac_to_float(&ctx->ac, src[1]);
1684 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1685 break;
1686 case nir_op_isub:
1687 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1688 break;
1689 case nir_op_imul:
1690 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1691 break;
1692 case nir_op_imod:
1693 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1694 break;
1695 case nir_op_umod:
1696 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1697 break;
1698 case nir_op_fmod:
1699 src[0] = ac_to_float(&ctx->ac, src[0]);
1700 src[1] = ac_to_float(&ctx->ac, src[1]);
1701 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1702 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1703 ac_to_float_type(&ctx->ac, def_type), result);
1704 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1705 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1706 break;
1707 case nir_op_frem:
1708 src[0] = ac_to_float(&ctx->ac, src[0]);
1709 src[1] = ac_to_float(&ctx->ac, src[1]);
1710 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1711 break;
1712 case nir_op_irem:
1713 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1714 break;
1715 case nir_op_idiv:
1716 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1717 break;
1718 case nir_op_udiv:
1719 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1720 break;
1721 case nir_op_fmul:
1722 src[0] = ac_to_float(&ctx->ac, src[0]);
1723 src[1] = ac_to_float(&ctx->ac, src[1]);
1724 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1725 break;
1726 case nir_op_frcp:
1727 src[0] = ac_to_float(&ctx->ac, src[0]);
1728 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1729 src[0]);
1730 break;
1731 case nir_op_iand:
1732 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1733 break;
1734 case nir_op_ior:
1735 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1736 break;
1737 case nir_op_ixor:
1738 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1739 break;
1740 case nir_op_ishl:
1741 result = LLVMBuildShl(ctx->ac.builder, src[0],
1742 LLVMBuildZExt(ctx->ac.builder, src[1],
1743 LLVMTypeOf(src[0]), ""),
1744 "");
1745 break;
1746 case nir_op_ishr:
1747 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1748 LLVMBuildZExt(ctx->ac.builder, src[1],
1749 LLVMTypeOf(src[0]), ""),
1750 "");
1751 break;
1752 case nir_op_ushr:
1753 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1754 LLVMBuildZExt(ctx->ac.builder, src[1],
1755 LLVMTypeOf(src[0]), ""),
1756 "");
1757 break;
1758 case nir_op_ilt:
1759 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1760 break;
1761 case nir_op_ine:
1762 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1763 break;
1764 case nir_op_ieq:
1765 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1766 break;
1767 case nir_op_ige:
1768 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1769 break;
1770 case nir_op_ult:
1771 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1772 break;
1773 case nir_op_uge:
1774 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1775 break;
1776 case nir_op_feq:
1777 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1778 break;
1779 case nir_op_fne:
1780 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1781 break;
1782 case nir_op_flt:
1783 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1784 break;
1785 case nir_op_fge:
1786 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1787 break;
1788 case nir_op_fabs:
1789 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1790 ac_to_float_type(&ctx->ac, def_type), src[0]);
1791 break;
1792 case nir_op_iabs:
1793 result = emit_iabs(&ctx->ac, src[0]);
1794 break;
1795 case nir_op_imax:
1796 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1797 break;
1798 case nir_op_imin:
1799 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1800 break;
1801 case nir_op_umax:
1802 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1803 break;
1804 case nir_op_umin:
1805 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1806 break;
1807 case nir_op_isign:
1808 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1809 break;
1810 case nir_op_fsign:
1811 src[0] = ac_to_float(&ctx->ac, src[0]);
1812 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1813 break;
1814 case nir_op_ffloor:
1815 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1816 ac_to_float_type(&ctx->ac, def_type), src[0]);
1817 break;
1818 case nir_op_ftrunc:
1819 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1820 ac_to_float_type(&ctx->ac, def_type), src[0]);
1821 break;
1822 case nir_op_fceil:
1823 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1824 ac_to_float_type(&ctx->ac, def_type), src[0]);
1825 break;
1826 case nir_op_fround_even:
1827 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1828 ac_to_float_type(&ctx->ac, def_type),src[0]);
1829 break;
1830 case nir_op_ffract:
1831 result = emit_ffract(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1832 break;
1833 case nir_op_fsin:
1834 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1835 ac_to_float_type(&ctx->ac, def_type), src[0]);
1836 break;
1837 case nir_op_fcos:
1838 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1839 ac_to_float_type(&ctx->ac, def_type), src[0]);
1840 break;
1841 case nir_op_fsqrt:
1842 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1843 ac_to_float_type(&ctx->ac, def_type), src[0]);
1844 break;
1845 case nir_op_fexp2:
1846 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1847 ac_to_float_type(&ctx->ac, def_type), src[0]);
1848 break;
1849 case nir_op_flog2:
1850 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1851 ac_to_float_type(&ctx->ac, def_type), src[0]);
1852 break;
1853 case nir_op_frsq:
1854 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1855 ac_to_float_type(&ctx->ac, def_type), src[0]);
1856 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1857 result);
1858 break;
1859 case nir_op_fpow:
1860 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1861 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1862 break;
1863 case nir_op_fmax:
1864 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1865 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1866 if (ctx->ac.chip_class < GFX9 &&
1867 instr->dest.dest.ssa.bit_size == 32) {
1868 /* Only pre-GFX9 chips do not flush denorms. */
1869 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1870 ac_to_float_type(&ctx->ac, def_type),
1871 result);
1872 }
1873 break;
1874 case nir_op_fmin:
1875 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1876 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1877 if (ctx->ac.chip_class < GFX9 &&
1878 instr->dest.dest.ssa.bit_size == 32) {
1879 /* Only pre-GFX9 chips do not flush denorms. */
1880 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1881 ac_to_float_type(&ctx->ac, def_type),
1882 result);
1883 }
1884 break;
1885 case nir_op_ffma:
1886 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1887 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1888 break;
1889 case nir_op_ibitfield_extract:
1890 result = emit_bitfield_extract(&ctx->ac, true, src);
1891 break;
1892 case nir_op_ubitfield_extract:
1893 result = emit_bitfield_extract(&ctx->ac, false, src);
1894 break;
1895 case nir_op_bitfield_insert:
1896 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1897 break;
1898 case nir_op_bitfield_reverse:
1899 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1900 break;
1901 case nir_op_bit_count:
1902 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1903 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1904 else {
1905 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1906 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1907 }
1908 break;
1909 case nir_op_vec2:
1910 case nir_op_vec3:
1911 case nir_op_vec4:
1912 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1913 src[i] = ac_to_integer(&ctx->ac, src[i]);
1914 result = ac_build_gather_values(&ctx->ac, src, num_components);
1915 break;
1916 case nir_op_f2i32:
1917 case nir_op_f2i64:
1918 src[0] = ac_to_float(&ctx->ac, src[0]);
1919 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1920 break;
1921 case nir_op_f2u32:
1922 case nir_op_f2u64:
1923 src[0] = ac_to_float(&ctx->ac, src[0]);
1924 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1925 break;
1926 case nir_op_i2f32:
1927 case nir_op_i2f64:
1928 src[0] = ac_to_integer(&ctx->ac, src[0]);
1929 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1930 break;
1931 case nir_op_u2f32:
1932 case nir_op_u2f64:
1933 src[0] = ac_to_integer(&ctx->ac, src[0]);
1934 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1935 break;
1936 case nir_op_f2f64:
1937 src[0] = ac_to_float(&ctx->ac, src[0]);
1938 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1939 break;
1940 case nir_op_f2f32:
1941 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1942 break;
1943 case nir_op_u2u32:
1944 case nir_op_u2u64:
1945 src[0] = ac_to_integer(&ctx->ac, src[0]);
1946 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1947 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1948 else
1949 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1950 break;
1951 case nir_op_i2i32:
1952 case nir_op_i2i64:
1953 src[0] = ac_to_integer(&ctx->ac, src[0]);
1954 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1955 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1956 else
1957 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1958 break;
1959 case nir_op_bcsel:
1960 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1961 break;
1962 case nir_op_find_lsb:
1963 src[0] = ac_to_integer(&ctx->ac, src[0]);
1964 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1965 break;
1966 case nir_op_ufind_msb:
1967 src[0] = ac_to_integer(&ctx->ac, src[0]);
1968 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1969 break;
1970 case nir_op_ifind_msb:
1971 src[0] = ac_to_integer(&ctx->ac, src[0]);
1972 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1973 break;
1974 case nir_op_uadd_carry:
1975 src[0] = ac_to_integer(&ctx->ac, src[0]);
1976 src[1] = ac_to_integer(&ctx->ac, src[1]);
1977 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1978 break;
1979 case nir_op_usub_borrow:
1980 src[0] = ac_to_integer(&ctx->ac, src[0]);
1981 src[1] = ac_to_integer(&ctx->ac, src[1]);
1982 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1983 break;
1984 case nir_op_b2f:
1985 result = emit_b2f(&ctx->ac, src[0]);
1986 break;
1987 case nir_op_f2b:
1988 result = emit_f2b(&ctx->ac, src[0]);
1989 break;
1990 case nir_op_b2i:
1991 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1992 break;
1993 case nir_op_i2b:
1994 src[0] = ac_to_integer(&ctx->ac, src[0]);
1995 result = emit_i2b(&ctx->ac, src[0]);
1996 break;
1997 case nir_op_fquantize2f16:
1998 result = emit_f2f16(ctx->nctx, src[0]);
1999 break;
2000 case nir_op_umul_high:
2001 src[0] = ac_to_integer(&ctx->ac, src[0]);
2002 src[1] = ac_to_integer(&ctx->ac, src[1]);
2003 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2004 break;
2005 case nir_op_imul_high:
2006 src[0] = ac_to_integer(&ctx->ac, src[0]);
2007 src[1] = ac_to_integer(&ctx->ac, src[1]);
2008 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2009 break;
2010 case nir_op_pack_half_2x16:
2011 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2012 break;
2013 case nir_op_unpack_half_2x16:
2014 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2015 break;
2016 case nir_op_fddx:
2017 case nir_op_fddy:
2018 case nir_op_fddx_fine:
2019 case nir_op_fddy_fine:
2020 case nir_op_fddx_coarse:
2021 case nir_op_fddy_coarse:
2022 result = emit_ddxy(ctx, instr->op, src[0]);
2023 break;
2024
2025 case nir_op_unpack_64_2x32_split_x: {
2026 assert(instr->src[0].src.ssa->num_components == 1);
2027 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2028 ctx->ac.v2i32,
2029 "");
2030 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2031 ctx->ac.i32_0, "");
2032 break;
2033 }
2034
2035 case nir_op_unpack_64_2x32_split_y: {
2036 assert(instr->src[0].src.ssa->num_components == 1);
2037 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2038 ctx->ac.v2i32,
2039 "");
2040 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2041 ctx->ac.i32_1, "");
2042 break;
2043 }
2044
2045 case nir_op_pack_64_2x32_split: {
2046 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2047 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2048 src[0], ctx->ac.i32_0, "");
2049 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2050 src[1], ctx->ac.i32_1, "");
2051 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2052 break;
2053 }
2054
2055 default:
2056 fprintf(stderr, "Unknown NIR alu instr: ");
2057 nir_print_instr(&instr->instr, stderr);
2058 fprintf(stderr, "\n");
2059 abort();
2060 }
2061
2062 if (result) {
2063 assert(instr->dest.dest.is_ssa);
2064 result = ac_to_integer(&ctx->ac, result);
2065 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2066 result);
2067 }
2068 }
2069
2070 static void visit_load_const(struct ac_nir_context *ctx,
2071 const nir_load_const_instr *instr)
2072 {
2073 LLVMValueRef values[4], value = NULL;
2074 LLVMTypeRef element_type =
2075 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2076
2077 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2078 switch (instr->def.bit_size) {
2079 case 32:
2080 values[i] = LLVMConstInt(element_type,
2081 instr->value.u32[i], false);
2082 break;
2083 case 64:
2084 values[i] = LLVMConstInt(element_type,
2085 instr->value.u64[i], false);
2086 break;
2087 default:
2088 fprintf(stderr,
2089 "unsupported nir load_const bit_size: %d\n",
2090 instr->def.bit_size);
2091 abort();
2092 }
2093 }
2094 if (instr->def.num_components > 1) {
2095 value = LLVMConstVector(values, instr->def.num_components);
2096 } else
2097 value = values[0];
2098
2099 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2100 }
2101
2102 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2103 LLVMTypeRef type)
2104 {
2105 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2106 return LLVMBuildBitCast(ctx->builder, ptr,
2107 LLVMPointerType(type, addr_space), "");
2108 }
2109
2110 static LLVMValueRef
2111 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2112 {
2113 LLVMValueRef size =
2114 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2115 LLVMConstInt(ctx->ac.i32, 2, false), "");
2116
2117 /* VI only */
2118 if (ctx->ac.chip_class == VI && in_elements) {
2119 /* On VI, the descriptor contains the size in bytes,
2120 * but TXQ must return the size in elements.
2121 * The stride is always non-zero for resources using TXQ.
2122 */
2123 LLVMValueRef stride =
2124 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2125 ctx->ac.i32_1, "");
2126 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2127 LLVMConstInt(ctx->ac.i32, 16, false), "");
2128 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2129 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2130
2131 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2132 }
2133 return size;
2134 }
2135
2136 /**
2137 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2138 * intrinsic names).
2139 */
2140 static void build_int_type_name(
2141 LLVMTypeRef type,
2142 char *buf, unsigned bufsize)
2143 {
2144 assert(bufsize >= 6);
2145
2146 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2147 snprintf(buf, bufsize, "v%ui32",
2148 LLVMGetVectorSize(type));
2149 else
2150 strcpy(buf, "i32");
2151 }
2152
2153 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2154 struct ac_image_args *args,
2155 const nir_tex_instr *instr)
2156 {
2157 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2158 LLVMValueRef coord = args->addr;
2159 LLVMValueRef half_texel[2];
2160 LLVMValueRef compare_cube_wa = NULL;
2161 LLVMValueRef result;
2162 int c;
2163 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2164
2165 //TODO Rect
2166 {
2167 struct ac_image_args txq_args = { 0 };
2168
2169 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2170 txq_args.opcode = ac_image_get_resinfo;
2171 txq_args.dmask = 0xf;
2172 txq_args.addr = ctx->i32_0;
2173 txq_args.resource = args->resource;
2174 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2175
2176 for (c = 0; c < 2; c++) {
2177 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2178 LLVMConstInt(ctx->i32, c, false), "");
2179 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2180 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2181 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2182 LLVMConstReal(ctx->f32, -0.5), "");
2183 }
2184 }
2185
2186 LLVMValueRef orig_coords = args->addr;
2187
2188 for (c = 0; c < 2; c++) {
2189 LLVMValueRef tmp;
2190 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2191 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2192 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2193 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2194 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2195 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2196 }
2197
2198
2199 /*
2200 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2201 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2202 * workaround by sampling using a scaled type and converting.
2203 * This is taken from amdgpu-pro shaders.
2204 */
2205 /* NOTE this produces some ugly code compared to amdgpu-pro,
2206 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2207 * and then reads them back. -pro generates two selects,
2208 * one s_cmp for the descriptor rewriting
2209 * one v_cmp for the coordinate and result changes.
2210 */
2211 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2212 LLVMValueRef tmp, tmp2;
2213
2214 /* workaround 8/8/8/8 uint/sint cube gather bug */
2215 /* first detect it then change to a scaled read and f2i */
2216 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2217 tmp2 = tmp;
2218
2219 /* extract the DATA_FORMAT */
2220 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2221 LLVMConstInt(ctx->i32, 6, false), false);
2222
2223 /* is the DATA_FORMAT == 8_8_8_8 */
2224 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2225
2226 if (stype == GLSL_TYPE_UINT)
2227 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2228 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2229 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2230 else
2231 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2232 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2233 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2234
2235 /* replace the NUM FORMAT in the descriptor */
2236 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2237 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2238
2239 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2240
2241 /* don't modify the coordinates for this case */
2242 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2243 }
2244 args->addr = coord;
2245 result = ac_build_image_opcode(ctx, args);
2246
2247 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2248 LLVMValueRef tmp, tmp2;
2249
2250 /* if the cube workaround is in place, f2i the result. */
2251 for (c = 0; c < 4; c++) {
2252 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2253 if (stype == GLSL_TYPE_UINT)
2254 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2255 else
2256 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2257 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2258 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2259 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2260 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2261 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2262 }
2263 }
2264 return result;
2265 }
2266
2267 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2268 const nir_tex_instr *instr,
2269 bool lod_is_zero,
2270 struct ac_image_args *args)
2271 {
2272 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2273 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2274
2275 return ac_build_buffer_load_format(&ctx->ac,
2276 args->resource,
2277 args->addr,
2278 ctx->ac.i32_0,
2279 util_last_bit(mask),
2280 false, true);
2281 }
2282
2283 args->opcode = ac_image_sample;
2284 args->compare = instr->is_shadow;
2285
2286 switch (instr->op) {
2287 case nir_texop_txf:
2288 case nir_texop_txf_ms:
2289 case nir_texop_samples_identical:
2290 args->opcode = lod_is_zero ||
2291 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2292 ac_image_load : ac_image_load_mip;
2293 args->compare = false;
2294 args->offset = false;
2295 break;
2296 case nir_texop_txb:
2297 args->bias = true;
2298 break;
2299 case nir_texop_txl:
2300 if (lod_is_zero)
2301 args->level_zero = true;
2302 else
2303 args->lod = true;
2304 break;
2305 case nir_texop_txs:
2306 case nir_texop_query_levels:
2307 args->opcode = ac_image_get_resinfo;
2308 break;
2309 case nir_texop_tex:
2310 if (ctx->stage != MESA_SHADER_FRAGMENT)
2311 args->level_zero = true;
2312 break;
2313 case nir_texop_txd:
2314 args->deriv = true;
2315 break;
2316 case nir_texop_tg4:
2317 args->opcode = ac_image_gather4;
2318 args->level_zero = true;
2319 break;
2320 case nir_texop_lod:
2321 args->opcode = ac_image_get_lod;
2322 args->compare = false;
2323 args->offset = false;
2324 break;
2325 default:
2326 break;
2327 }
2328
2329 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2330 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2331 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2332 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2333 }
2334 }
2335 return ac_build_image_opcode(&ctx->ac, args);
2336 }
2337
2338 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2339 nir_intrinsic_instr *instr)
2340 {
2341 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2342 unsigned desc_set = nir_intrinsic_desc_set(instr);
2343 unsigned binding = nir_intrinsic_binding(instr);
2344 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2345 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2346 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2347 unsigned base_offset = layout->binding[binding].offset;
2348 LLVMValueRef offset, stride;
2349
2350 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2351 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2352 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2353 layout->binding[binding].dynamic_offset_offset;
2354 desc_ptr = ctx->push_constants;
2355 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2356 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2357 } else
2358 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2359
2360 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2361 index = LLVMBuildMul(ctx->builder, index, stride, "");
2362 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2363
2364 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2365 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2366 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2367
2368 return desc_ptr;
2369 }
2370
2371 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2372 nir_intrinsic_instr *instr)
2373 {
2374 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2375 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2376
2377 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2378 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2379 return result;
2380 }
2381
2382 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2383 nir_intrinsic_instr *instr)
2384 {
2385 LLVMValueRef ptr, addr;
2386
2387 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2388 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2389
2390 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2391 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2392
2393 return LLVMBuildLoad(ctx->builder, ptr, "");
2394 }
2395
2396 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2397 const nir_intrinsic_instr *instr)
2398 {
2399 LLVMValueRef index = get_src(ctx, instr->src[0]);
2400
2401 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2402 }
2403
2404 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2405 {
2406 uint32_t new_mask = 0;
2407 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2408 if (mask & (1u << i))
2409 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2410 return new_mask;
2411 }
2412
2413 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2414 unsigned start, unsigned count)
2415 {
2416 LLVMTypeRef type = LLVMTypeOf(src);
2417
2418 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2419 assert(start == 0);
2420 assert(count == 1);
2421 return src;
2422 }
2423
2424 unsigned src_elements = LLVMGetVectorSize(type);
2425 assert(start < src_elements);
2426 assert(start + count <= src_elements);
2427
2428 if (start == 0 && count == src_elements)
2429 return src;
2430
2431 if (count == 1)
2432 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2433
2434 assert(count <= 8);
2435 LLVMValueRef indices[8];
2436 for (unsigned i = 0; i < count; ++i)
2437 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2438
2439 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2440 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2441 }
2442
2443 static void visit_store_ssbo(struct ac_nir_context *ctx,
2444 nir_intrinsic_instr *instr)
2445 {
2446 const char *store_name;
2447 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2448 LLVMTypeRef data_type = ctx->ac.f32;
2449 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2450 int components_32bit = elem_size_mult * instr->num_components;
2451 unsigned writemask = nir_intrinsic_write_mask(instr);
2452 LLVMValueRef base_data, base_offset;
2453 LLVMValueRef params[6];
2454
2455 params[1] = ctx->abi->load_ssbo(ctx->abi,
2456 get_src(ctx, instr->src[1]), true);
2457 params[2] = ctx->ac.i32_0; /* vindex */
2458 params[4] = ctx->ac.i1false; /* glc */
2459 params[5] = ctx->ac.i1false; /* slc */
2460
2461 if (components_32bit > 1)
2462 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2463
2464 writemask = widen_mask(writemask, elem_size_mult);
2465
2466 base_data = ac_to_float(&ctx->ac, src_data);
2467 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2468 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2469 data_type, "");
2470 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2471 while (writemask) {
2472 int start, count;
2473 LLVMValueRef data;
2474 LLVMValueRef offset;
2475
2476 u_bit_scan_consecutive_range(&writemask, &start, &count);
2477
2478 /* Due to an LLVM limitation, split 3-element writes
2479 * into a 2-element and a 1-element write. */
2480 if (count == 3) {
2481 writemask |= 1 << (start + 2);
2482 count = 2;
2483 }
2484
2485 if (count > 4) {
2486 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2487 count = 4;
2488 }
2489
2490 if (count == 4) {
2491 store_name = "llvm.amdgcn.buffer.store.v4f32";
2492 } else if (count == 2) {
2493 store_name = "llvm.amdgcn.buffer.store.v2f32";
2494
2495 } else {
2496 assert(count == 1);
2497 store_name = "llvm.amdgcn.buffer.store.f32";
2498 }
2499 data = extract_vector_range(&ctx->ac, base_data, start, count);
2500
2501 offset = base_offset;
2502 if (start != 0) {
2503 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2504 }
2505 params[0] = data;
2506 params[3] = offset;
2507 ac_build_intrinsic(&ctx->ac, store_name,
2508 ctx->ac.voidt, params, 6, 0);
2509 }
2510 }
2511
2512 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2513 const nir_intrinsic_instr *instr)
2514 {
2515 const char *name;
2516 LLVMValueRef params[6];
2517 int arg_count = 0;
2518
2519 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2520 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2521 }
2522 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2523 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2524 get_src(ctx, instr->src[0]),
2525 true);
2526 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2527 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2528 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2529
2530 switch (instr->intrinsic) {
2531 case nir_intrinsic_ssbo_atomic_add:
2532 name = "llvm.amdgcn.buffer.atomic.add";
2533 break;
2534 case nir_intrinsic_ssbo_atomic_imin:
2535 name = "llvm.amdgcn.buffer.atomic.smin";
2536 break;
2537 case nir_intrinsic_ssbo_atomic_umin:
2538 name = "llvm.amdgcn.buffer.atomic.umin";
2539 break;
2540 case nir_intrinsic_ssbo_atomic_imax:
2541 name = "llvm.amdgcn.buffer.atomic.smax";
2542 break;
2543 case nir_intrinsic_ssbo_atomic_umax:
2544 name = "llvm.amdgcn.buffer.atomic.umax";
2545 break;
2546 case nir_intrinsic_ssbo_atomic_and:
2547 name = "llvm.amdgcn.buffer.atomic.and";
2548 break;
2549 case nir_intrinsic_ssbo_atomic_or:
2550 name = "llvm.amdgcn.buffer.atomic.or";
2551 break;
2552 case nir_intrinsic_ssbo_atomic_xor:
2553 name = "llvm.amdgcn.buffer.atomic.xor";
2554 break;
2555 case nir_intrinsic_ssbo_atomic_exchange:
2556 name = "llvm.amdgcn.buffer.atomic.swap";
2557 break;
2558 case nir_intrinsic_ssbo_atomic_comp_swap:
2559 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2560 break;
2561 default:
2562 abort();
2563 }
2564
2565 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2566 }
2567
2568 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2569 const nir_intrinsic_instr *instr)
2570 {
2571 LLVMValueRef results[2];
2572 int load_components;
2573 int num_components = instr->num_components;
2574 if (instr->dest.ssa.bit_size == 64)
2575 num_components *= 2;
2576
2577 for (int i = 0; i < num_components; i += load_components) {
2578 load_components = MIN2(num_components - i, 4);
2579 const char *load_name;
2580 LLVMTypeRef data_type = ctx->ac.f32;
2581 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2582 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2583
2584 if (load_components == 3)
2585 data_type = LLVMVectorType(ctx->ac.f32, 4);
2586 else if (load_components > 1)
2587 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2588
2589 if (load_components >= 3)
2590 load_name = "llvm.amdgcn.buffer.load.v4f32";
2591 else if (load_components == 2)
2592 load_name = "llvm.amdgcn.buffer.load.v2f32";
2593 else if (load_components == 1)
2594 load_name = "llvm.amdgcn.buffer.load.f32";
2595 else
2596 unreachable("unhandled number of components");
2597
2598 LLVMValueRef params[] = {
2599 ctx->abi->load_ssbo(ctx->abi,
2600 get_src(ctx, instr->src[0]),
2601 false),
2602 ctx->ac.i32_0,
2603 offset,
2604 ctx->ac.i1false,
2605 ctx->ac.i1false,
2606 };
2607
2608 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2609 }
2610
2611 assume(results[0]);
2612 LLVMValueRef ret = results[0];
2613 if (num_components > 4 || num_components == 3) {
2614 LLVMValueRef masks[] = {
2615 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2616 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2617 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2618 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2619 };
2620
2621 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2622 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2623 results[num_components > 4 ? 1 : 0], swizzle, "");
2624 }
2625
2626 return LLVMBuildBitCast(ctx->ac.builder, ret,
2627 get_def_type(ctx, &instr->dest.ssa), "");
2628 }
2629
2630 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2631 const nir_intrinsic_instr *instr)
2632 {
2633 LLVMValueRef ret;
2634 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2635 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2636 int num_components = instr->num_components;
2637
2638 if (ctx->abi->load_ubo)
2639 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2640
2641 if (instr->dest.ssa.bit_size == 64)
2642 num_components *= 2;
2643
2644 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2645 NULL, 0, false, false, true, true);
2646 ret = trim_vector(&ctx->ac, ret, num_components);
2647 return LLVMBuildBitCast(ctx->ac.builder, ret,
2648 get_def_type(ctx, &instr->dest.ssa), "");
2649 }
2650
2651 static void
2652 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2653 bool vs_in, unsigned *vertex_index_out,
2654 LLVMValueRef *vertex_index_ref,
2655 unsigned *const_out, LLVMValueRef *indir_out)
2656 {
2657 unsigned const_offset = 0;
2658 nir_deref *tail = &deref->deref;
2659 LLVMValueRef offset = NULL;
2660
2661 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2662 tail = tail->child;
2663 nir_deref_array *deref_array = nir_deref_as_array(tail);
2664 if (vertex_index_out)
2665 *vertex_index_out = deref_array->base_offset;
2666
2667 if (vertex_index_ref) {
2668 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2669 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2670 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2671 }
2672 *vertex_index_ref = vtx;
2673 }
2674 }
2675
2676 if (deref->var->data.compact) {
2677 assert(tail->child->deref_type == nir_deref_type_array);
2678 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2679 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2680 /* We always lower indirect dereferences for "compact" array vars. */
2681 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2682
2683 const_offset = deref_array->base_offset;
2684 goto out;
2685 }
2686
2687 while (tail->child != NULL) {
2688 const struct glsl_type *parent_type = tail->type;
2689 tail = tail->child;
2690
2691 if (tail->deref_type == nir_deref_type_array) {
2692 nir_deref_array *deref_array = nir_deref_as_array(tail);
2693 LLVMValueRef index, stride, local_offset;
2694 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2695
2696 const_offset += size * deref_array->base_offset;
2697 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2698 continue;
2699
2700 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2701 index = get_src(ctx, deref_array->indirect);
2702 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2703 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2704
2705 if (offset)
2706 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2707 else
2708 offset = local_offset;
2709 } else if (tail->deref_type == nir_deref_type_struct) {
2710 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2711
2712 for (unsigned i = 0; i < deref_struct->index; i++) {
2713 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2714 const_offset += glsl_count_attribute_slots(ft, vs_in);
2715 }
2716 } else
2717 unreachable("unsupported deref type");
2718
2719 }
2720 out:
2721 if (const_offset && offset)
2722 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2723 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2724 "");
2725
2726 *const_out = const_offset;
2727 *indir_out = offset;
2728 }
2729
2730
2731 /* The offchip buffer layout for TCS->TES is
2732 *
2733 * - attribute 0 of patch 0 vertex 0
2734 * - attribute 0 of patch 0 vertex 1
2735 * - attribute 0 of patch 0 vertex 2
2736 * ...
2737 * - attribute 0 of patch 1 vertex 0
2738 * - attribute 0 of patch 1 vertex 1
2739 * ...
2740 * - attribute 1 of patch 0 vertex 0
2741 * - attribute 1 of patch 0 vertex 1
2742 * ...
2743 * - per patch attribute 0 of patch 0
2744 * - per patch attribute 0 of patch 1
2745 * ...
2746 *
2747 * Note that every attribute has 4 components.
2748 */
2749 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2750 LLVMValueRef vertex_index,
2751 LLVMValueRef param_index)
2752 {
2753 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2754 LLVMValueRef param_stride, constant16;
2755 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2756
2757 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2758 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2759 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2760 num_patches, "");
2761
2762 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2763 if (vertex_index) {
2764 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2765 vertices_per_patch, "");
2766
2767 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2768 vertex_index, "");
2769
2770 param_stride = total_vertices;
2771 } else {
2772 base_addr = rel_patch_id;
2773 param_stride = num_patches;
2774 }
2775
2776 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2777 LLVMBuildMul(ctx->builder, param_index,
2778 param_stride, ""), "");
2779
2780 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2781
2782 if (!vertex_index) {
2783 LLVMValueRef patch_data_offset =
2784 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2785
2786 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2787 patch_data_offset, "");
2788 }
2789 return base_addr;
2790 }
2791
2792 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2793 unsigned param,
2794 unsigned const_index,
2795 bool is_compact,
2796 LLVMValueRef vertex_index,
2797 LLVMValueRef indir_index)
2798 {
2799 LLVMValueRef param_index;
2800
2801 if (indir_index)
2802 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2803 indir_index, "");
2804 else {
2805 if (const_index && !is_compact)
2806 param += const_index;
2807 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2808 }
2809 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2810 }
2811
2812 static void
2813 mark_tess_output(struct nir_to_llvm_context *ctx,
2814 bool is_patch, uint32_t param)
2815
2816 {
2817 if (is_patch) {
2818 ctx->tess_patch_outputs_written |= (1ull << param);
2819 } else
2820 ctx->tess_outputs_written |= (1ull << param);
2821 }
2822
2823 static LLVMValueRef
2824 get_dw_address(struct nir_to_llvm_context *ctx,
2825 LLVMValueRef dw_addr,
2826 unsigned param,
2827 unsigned const_index,
2828 bool compact_const_index,
2829 LLVMValueRef vertex_index,
2830 LLVMValueRef stride,
2831 LLVMValueRef indir_index)
2832
2833 {
2834
2835 if (vertex_index) {
2836 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2837 LLVMBuildMul(ctx->builder,
2838 vertex_index,
2839 stride, ""), "");
2840 }
2841
2842 if (indir_index)
2843 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2844 LLVMBuildMul(ctx->builder, indir_index,
2845 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2846 else if (const_index && !compact_const_index)
2847 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2848 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2849
2850 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2851 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2852
2853 if (const_index && compact_const_index)
2854 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2855 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2856 return dw_addr;
2857 }
2858
2859 static LLVMValueRef
2860 load_tcs_varyings(struct ac_shader_abi *abi,
2861 LLVMValueRef vertex_index,
2862 LLVMValueRef indir_index,
2863 unsigned const_index,
2864 unsigned location,
2865 unsigned driver_location,
2866 unsigned component,
2867 unsigned num_components,
2868 bool is_patch,
2869 bool is_compact,
2870 bool load_input)
2871 {
2872 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2873 LLVMValueRef dw_addr, stride;
2874 LLVMValueRef value[4], result;
2875 unsigned param = shader_io_get_unique_index(location);
2876
2877 if (load_input) {
2878 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2879 dw_addr = get_tcs_in_current_patch_offset(ctx);
2880 } else {
2881 if (!is_patch) {
2882 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2883 dw_addr = get_tcs_out_current_patch_offset(ctx);
2884 } else {
2885 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2886 stride = NULL;
2887 }
2888 }
2889
2890 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2891 indir_index);
2892
2893 for (unsigned i = 0; i < num_components + component; i++) {
2894 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2895 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2896 ctx->ac.i32_1, "");
2897 }
2898 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2899 return result;
2900 }
2901
2902 static void
2903 store_tcs_output(struct ac_shader_abi *abi,
2904 LLVMValueRef vertex_index,
2905 LLVMValueRef param_index,
2906 unsigned const_index,
2907 unsigned location,
2908 unsigned driver_location,
2909 LLVMValueRef src,
2910 unsigned component,
2911 bool is_patch,
2912 bool is_compact,
2913 unsigned writemask)
2914 {
2915 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2916 LLVMValueRef dw_addr;
2917 LLVMValueRef stride = NULL;
2918 LLVMValueRef buf_addr = NULL;
2919 unsigned param;
2920 bool store_lds = true;
2921
2922 if (is_patch) {
2923 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2924 store_lds = false;
2925 } else {
2926 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2927 store_lds = false;
2928 }
2929
2930 param = shader_io_get_unique_index(location);
2931 if (location == VARYING_SLOT_CLIP_DIST0 &&
2932 is_compact && const_index > 3) {
2933 const_index -= 3;
2934 param++;
2935 }
2936
2937 if (!is_patch) {
2938 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2939 dw_addr = get_tcs_out_current_patch_offset(ctx);
2940 } else {
2941 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2942 }
2943
2944 mark_tess_output(ctx, is_patch, param);
2945
2946 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2947 param_index);
2948 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2949 vertex_index, param_index);
2950
2951 bool is_tess_factor = false;
2952 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2953 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2954 is_tess_factor = true;
2955
2956 unsigned base = is_compact ? const_index : 0;
2957 for (unsigned chan = 0; chan < 8; chan++) {
2958 if (!(writemask & (1 << chan)))
2959 continue;
2960 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2961
2962 if (store_lds || is_tess_factor) {
2963 LLVMValueRef dw_addr_chan =
2964 LLVMBuildAdd(ctx->builder, dw_addr,
2965 LLVMConstInt(ctx->ac.i32, chan, false), "");
2966 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2967 }
2968
2969 if (!is_tess_factor && writemask != 0xF)
2970 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2971 buf_addr, ctx->oc_lds,
2972 4 * (base + chan), 1, 0, true, false);
2973 }
2974
2975 if (writemask == 0xF) {
2976 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2977 buf_addr, ctx->oc_lds,
2978 (base * 4), 1, 0, true, false);
2979 }
2980 }
2981
2982 static LLVMValueRef
2983 load_tes_input(struct ac_shader_abi *abi,
2984 LLVMValueRef vertex_index,
2985 LLVMValueRef param_index,
2986 unsigned const_index,
2987 unsigned location,
2988 unsigned driver_location,
2989 unsigned component,
2990 unsigned num_components,
2991 bool is_patch,
2992 bool is_compact,
2993 bool load_input)
2994 {
2995 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2996 LLVMValueRef buf_addr;
2997 LLVMValueRef result;
2998 unsigned param = shader_io_get_unique_index(location);
2999
3000 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3001 const_index -= 3;
3002 param++;
3003 }
3004
3005 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3006 is_compact, vertex_index, param_index);
3007
3008 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3009 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3010
3011 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3012 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3013 result = trim_vector(&ctx->ac, result, num_components);
3014 return result;
3015 }
3016
3017 static LLVMValueRef
3018 load_gs_input(struct ac_shader_abi *abi,
3019 unsigned location,
3020 unsigned driver_location,
3021 unsigned component,
3022 unsigned num_components,
3023 unsigned vertex_index,
3024 unsigned const_index,
3025 LLVMTypeRef type)
3026 {
3027 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3028 LLVMValueRef vtx_offset;
3029 unsigned param, vtx_offset_param;
3030 LLVMValueRef value[4], result;
3031
3032 vtx_offset_param = vertex_index;
3033 assert(vtx_offset_param < 6);
3034 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3035 LLVMConstInt(ctx->ac.i32, 4, false), "");
3036
3037 param = shader_io_get_unique_index(location);
3038
3039 for (unsigned i = component; i < num_components + component; i++) {
3040 if (ctx->ac.chip_class >= GFX9) {
3041 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3042 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3043 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3044 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3045 } else {
3046 LLVMValueRef soffset =
3047 LLVMConstInt(ctx->ac.i32,
3048 (param * 4 + i + const_index) * 256,
3049 false);
3050
3051 value[i] = ac_build_buffer_load(&ctx->ac,
3052 ctx->esgs_ring, 1,
3053 ctx->ac.i32_0,
3054 vtx_offset, soffset,
3055 0, 1, 0, true, false);
3056
3057 value[i] = LLVMBuildBitCast(ctx->builder, value[i],
3058 type, "");
3059 }
3060 }
3061 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3062 result = ac_to_integer(&ctx->ac, result);
3063 return result;
3064 }
3065
3066 static LLVMValueRef
3067 build_gep_for_deref(struct ac_nir_context *ctx,
3068 nir_deref_var *deref)
3069 {
3070 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3071 assert(entry->data);
3072 LLVMValueRef val = entry->data;
3073 nir_deref *tail = deref->deref.child;
3074 while (tail != NULL) {
3075 LLVMValueRef offset;
3076 switch (tail->deref_type) {
3077 case nir_deref_type_array: {
3078 nir_deref_array *array = nir_deref_as_array(tail);
3079 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3080 if (array->deref_array_type ==
3081 nir_deref_array_type_indirect) {
3082 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3083 get_src(ctx,
3084 array->indirect),
3085 "");
3086 }
3087 break;
3088 }
3089 case nir_deref_type_struct: {
3090 nir_deref_struct *deref_struct =
3091 nir_deref_as_struct(tail);
3092 offset = LLVMConstInt(ctx->ac.i32,
3093 deref_struct->index, 0);
3094 break;
3095 }
3096 default:
3097 unreachable("bad deref type");
3098 }
3099 val = ac_build_gep0(&ctx->ac, val, offset);
3100 tail = tail->child;
3101 }
3102 return val;
3103 }
3104
3105 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3106 nir_intrinsic_instr *instr,
3107 bool load_inputs)
3108 {
3109 LLVMValueRef result;
3110 LLVMValueRef vertex_index = NULL;
3111 LLVMValueRef indir_index = NULL;
3112 unsigned const_index = 0;
3113 unsigned location = instr->variables[0]->var->data.location;
3114 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3115 const bool is_patch = instr->variables[0]->var->data.patch;
3116 const bool is_compact = instr->variables[0]->var->data.compact;
3117
3118 get_deref_offset(ctx, instr->variables[0],
3119 false, NULL, is_patch ? NULL : &vertex_index,
3120 &const_index, &indir_index);
3121
3122 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3123 const_index, location, driver_location,
3124 instr->variables[0]->var->data.location_frac,
3125 instr->num_components,
3126 is_patch, is_compact, load_inputs);
3127 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3128 }
3129
3130 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3131 nir_intrinsic_instr *instr)
3132 {
3133 LLVMValueRef values[8];
3134 int idx = instr->variables[0]->var->data.driver_location;
3135 int ve = instr->dest.ssa.num_components;
3136 unsigned comp = instr->variables[0]->var->data.location_frac;
3137 LLVMValueRef indir_index;
3138 LLVMValueRef ret;
3139 unsigned const_index;
3140 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3141 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3142 instr->variables[0]->var->data.mode == nir_var_shader_in;
3143 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3144 &const_index, &indir_index);
3145
3146 if (instr->dest.ssa.bit_size == 64)
3147 ve *= 2;
3148
3149 switch (instr->variables[0]->var->data.mode) {
3150 case nir_var_shader_in:
3151 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3152 ctx->stage == MESA_SHADER_TESS_EVAL) {
3153 return load_tess_varyings(ctx, instr, true);
3154 }
3155
3156 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3157 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3158 LLVMValueRef indir_index;
3159 unsigned const_index, vertex_index;
3160 get_deref_offset(ctx, instr->variables[0],
3161 false, &vertex_index, NULL,
3162 &const_index, &indir_index);
3163
3164 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3165 instr->variables[0]->var->data.driver_location,
3166 instr->variables[0]->var->data.location_frac, ve,
3167 vertex_index, const_index, type);
3168 }
3169
3170 for (unsigned chan = comp; chan < ve + comp; chan++) {
3171 if (indir_index) {
3172 unsigned count = glsl_count_attribute_slots(
3173 instr->variables[0]->var->type,
3174 ctx->stage == MESA_SHADER_VERTEX);
3175 count -= chan / 4;
3176 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3177 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3178 stride, false, true);
3179
3180 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3181 tmp_vec,
3182 indir_index, "");
3183 } else
3184 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3185 }
3186 break;
3187 case nir_var_local:
3188 for (unsigned chan = 0; chan < ve; chan++) {
3189 if (indir_index) {
3190 unsigned count = glsl_count_attribute_slots(
3191 instr->variables[0]->var->type, false);
3192 count -= chan / 4;
3193 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3194 &ctx->ac, ctx->locals + idx + chan, count,
3195 stride, true, true);
3196
3197 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3198 tmp_vec,
3199 indir_index, "");
3200 } else {
3201 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3202 }
3203 }
3204 break;
3205 case nir_var_shared: {
3206 LLVMValueRef address = build_gep_for_deref(ctx,
3207 instr->variables[0]);
3208 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3209 return LLVMBuildBitCast(ctx->ac.builder, val,
3210 get_def_type(ctx, &instr->dest.ssa),
3211 "");
3212 }
3213 case nir_var_shader_out:
3214 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3215 return load_tess_varyings(ctx, instr, false);
3216 }
3217
3218 for (unsigned chan = comp; chan < ve + comp; chan++) {
3219 if (indir_index) {
3220 unsigned count = glsl_count_attribute_slots(
3221 instr->variables[0]->var->type, false);
3222 count -= chan / 4;
3223 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3224 &ctx->ac, ctx->outputs + idx + chan, count,
3225 stride, true, true);
3226
3227 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3228 tmp_vec,
3229 indir_index, "");
3230 } else {
3231 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3232 ctx->outputs[idx + chan + const_index * stride],
3233 "");
3234 }
3235 }
3236 break;
3237 default:
3238 unreachable("unhandle variable mode");
3239 }
3240 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3241 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3242 }
3243
3244 static void
3245 visit_store_var(struct ac_nir_context *ctx,
3246 nir_intrinsic_instr *instr)
3247 {
3248 LLVMValueRef temp_ptr, value;
3249 int idx = instr->variables[0]->var->data.driver_location;
3250 unsigned comp = instr->variables[0]->var->data.location_frac;
3251 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3252 int writemask = instr->const_index[0] << comp;
3253 LLVMValueRef indir_index;
3254 unsigned const_index;
3255 get_deref_offset(ctx, instr->variables[0], false,
3256 NULL, NULL, &const_index, &indir_index);
3257
3258 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3259
3260 src = LLVMBuildBitCast(ctx->ac.builder, src,
3261 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3262 "");
3263
3264 writemask = widen_mask(writemask, 2);
3265 }
3266
3267 switch (instr->variables[0]->var->data.mode) {
3268 case nir_var_shader_out:
3269
3270 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3271 LLVMValueRef vertex_index = NULL;
3272 LLVMValueRef indir_index = NULL;
3273 unsigned const_index = 0;
3274 const unsigned location = instr->variables[0]->var->data.location;
3275 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3276 const unsigned comp = instr->variables[0]->var->data.location_frac;
3277 const bool is_patch = instr->variables[0]->var->data.patch;
3278 const bool is_compact = instr->variables[0]->var->data.compact;
3279
3280 get_deref_offset(ctx, instr->variables[0],
3281 false, NULL, is_patch ? NULL : &vertex_index,
3282 &const_index, &indir_index);
3283
3284 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3285 const_index, location, driver_location,
3286 src, comp, is_patch, is_compact, writemask);
3287 return;
3288 }
3289
3290 for (unsigned chan = 0; chan < 8; chan++) {
3291 int stride = 4;
3292 if (!(writemask & (1 << chan)))
3293 continue;
3294
3295 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3296
3297 if (instr->variables[0]->var->data.compact)
3298 stride = 1;
3299 if (indir_index) {
3300 unsigned count = glsl_count_attribute_slots(
3301 instr->variables[0]->var->type, false);
3302 count -= chan / 4;
3303 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3304 &ctx->ac, ctx->outputs + idx + chan, count,
3305 stride, true, true);
3306
3307 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3308 value, indir_index, "");
3309 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3310 count, stride, tmp_vec);
3311
3312 } else {
3313 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3314
3315 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3316 }
3317 }
3318 break;
3319 case nir_var_local:
3320 for (unsigned chan = 0; chan < 8; chan++) {
3321 if (!(writemask & (1 << chan)))
3322 continue;
3323
3324 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3325 if (indir_index) {
3326 unsigned count = glsl_count_attribute_slots(
3327 instr->variables[0]->var->type, false);
3328 count -= chan / 4;
3329 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3330 &ctx->ac, ctx->locals + idx + chan, count,
3331 4, true, true);
3332
3333 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3334 value, indir_index, "");
3335 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3336 count, 4, tmp_vec);
3337 } else {
3338 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3339
3340 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3341 }
3342 }
3343 break;
3344 case nir_var_shared: {
3345 int writemask = instr->const_index[0];
3346 LLVMValueRef address = build_gep_for_deref(ctx,
3347 instr->variables[0]);
3348 LLVMValueRef val = get_src(ctx, instr->src[0]);
3349 unsigned components =
3350 glsl_get_vector_elements(
3351 nir_deref_tail(&instr->variables[0]->deref)->type);
3352 if (writemask == (1 << components) - 1) {
3353 val = LLVMBuildBitCast(
3354 ctx->ac.builder, val,
3355 LLVMGetElementType(LLVMTypeOf(address)), "");
3356 LLVMBuildStore(ctx->ac.builder, val, address);
3357 } else {
3358 for (unsigned chan = 0; chan < 4; chan++) {
3359 if (!(writemask & (1 << chan)))
3360 continue;
3361 LLVMValueRef ptr =
3362 LLVMBuildStructGEP(ctx->ac.builder,
3363 address, chan, "");
3364 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3365 chan);
3366 src = LLVMBuildBitCast(
3367 ctx->ac.builder, src,
3368 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3369 LLVMBuildStore(ctx->ac.builder, src, ptr);
3370 }
3371 }
3372 break;
3373 }
3374 default:
3375 break;
3376 }
3377 }
3378
3379 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3380 {
3381 switch (dim) {
3382 case GLSL_SAMPLER_DIM_BUF:
3383 return 1;
3384 case GLSL_SAMPLER_DIM_1D:
3385 return array ? 2 : 1;
3386 case GLSL_SAMPLER_DIM_2D:
3387 return array ? 3 : 2;
3388 case GLSL_SAMPLER_DIM_MS:
3389 return array ? 4 : 3;
3390 case GLSL_SAMPLER_DIM_3D:
3391 case GLSL_SAMPLER_DIM_CUBE:
3392 return 3;
3393 case GLSL_SAMPLER_DIM_RECT:
3394 case GLSL_SAMPLER_DIM_SUBPASS:
3395 return 2;
3396 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3397 return 3;
3398 default:
3399 break;
3400 }
3401 return 0;
3402 }
3403
3404
3405
3406 /* Adjust the sample index according to FMASK.
3407 *
3408 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3409 * which is the identity mapping. Each nibble says which physical sample
3410 * should be fetched to get that sample.
3411 *
3412 * For example, 0x11111100 means there are only 2 samples stored and
3413 * the second sample covers 3/4 of the pixel. When reading samples 0
3414 * and 1, return physical sample 0 (determined by the first two 0s
3415 * in FMASK), otherwise return physical sample 1.
3416 *
3417 * The sample index should be adjusted as follows:
3418 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3419 */
3420 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3421 LLVMValueRef coord_x, LLVMValueRef coord_y,
3422 LLVMValueRef coord_z,
3423 LLVMValueRef sample_index,
3424 LLVMValueRef fmask_desc_ptr)
3425 {
3426 LLVMValueRef fmask_load_address[4];
3427 LLVMValueRef res;
3428
3429 fmask_load_address[0] = coord_x;
3430 fmask_load_address[1] = coord_y;
3431 if (coord_z) {
3432 fmask_load_address[2] = coord_z;
3433 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3434 }
3435
3436 struct ac_image_args args = {0};
3437
3438 args.opcode = ac_image_load;
3439 args.da = coord_z ? true : false;
3440 args.resource = fmask_desc_ptr;
3441 args.dmask = 0xf;
3442 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3443
3444 res = ac_build_image_opcode(ctx, &args);
3445
3446 res = ac_to_integer(ctx, res);
3447 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3448 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3449
3450 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3451 res,
3452 ctx->i32_0, "");
3453
3454 LLVMValueRef sample_index4 =
3455 LLVMBuildMul(ctx->builder, sample_index, four, "");
3456 LLVMValueRef shifted_fmask =
3457 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3458 LLVMValueRef final_sample =
3459 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3460
3461 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3462 * resource descriptor is 0 (invalid),
3463 */
3464 LLVMValueRef fmask_desc =
3465 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3466 ctx->v8i32, "");
3467
3468 LLVMValueRef fmask_word1 =
3469 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3470 ctx->i32_1, "");
3471
3472 LLVMValueRef word1_is_nonzero =
3473 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3474 fmask_word1, ctx->i32_0, "");
3475
3476 /* Replace the MSAA sample index. */
3477 sample_index =
3478 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3479 final_sample, sample_index, "");
3480 return sample_index;
3481 }
3482
3483 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3484 const nir_intrinsic_instr *instr)
3485 {
3486 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3487
3488 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3489 LLVMValueRef coords[4];
3490 LLVMValueRef masks[] = {
3491 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3492 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3493 };
3494 LLVMValueRef res;
3495 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3496
3497 int count;
3498 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3499 bool is_array = glsl_sampler_type_is_array(type);
3500 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3501 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3502 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3503 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3504 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3505 count = image_type_to_components_count(dim, is_array);
3506
3507 if (is_ms) {
3508 LLVMValueRef fmask_load_address[3];
3509 int chan;
3510
3511 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3512 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3513 if (is_array)
3514 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3515 else
3516 fmask_load_address[2] = NULL;
3517 if (add_frag_pos) {
3518 for (chan = 0; chan < 2; ++chan)
3519 fmask_load_address[chan] =
3520 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3521 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3522 ctx->ac.i32, ""), "");
3523 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3524 }
3525 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3526 fmask_load_address[0],
3527 fmask_load_address[1],
3528 fmask_load_address[2],
3529 sample_index,
3530 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3531 }
3532 if (count == 1 && !gfx9_1d) {
3533 if (instr->src[0].ssa->num_components)
3534 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3535 else
3536 res = src0;
3537 } else {
3538 int chan;
3539 if (is_ms)
3540 count--;
3541 for (chan = 0; chan < count; ++chan) {
3542 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3543 }
3544 if (add_frag_pos) {
3545 for (chan = 0; chan < 2; ++chan)
3546 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3547 ctx->ac.i32, ""), "");
3548 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3549 count++;
3550 }
3551
3552 if (gfx9_1d) {
3553 if (is_array) {
3554 coords[2] = coords[1];
3555 coords[1] = ctx->ac.i32_0;
3556 } else
3557 coords[1] = ctx->ac.i32_0;
3558 count++;
3559 }
3560
3561 if (is_ms) {
3562 coords[count] = sample_index;
3563 count++;
3564 }
3565
3566 if (count == 3) {
3567 coords[3] = LLVMGetUndef(ctx->ac.i32);
3568 count = 4;
3569 }
3570 res = ac_build_gather_values(&ctx->ac, coords, count);
3571 }
3572 return res;
3573 }
3574
3575 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3576 const nir_intrinsic_instr *instr)
3577 {
3578 LLVMValueRef params[7];
3579 LLVMValueRef res;
3580 char intrinsic_name[64];
3581 const nir_variable *var = instr->variables[0]->var;
3582 const struct glsl_type *type = var->type;
3583
3584 if(instr->variables[0]->deref.child)
3585 type = instr->variables[0]->deref.child->type;
3586
3587 type = glsl_without_array(type);
3588
3589 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3590 if (dim == GLSL_SAMPLER_DIM_BUF) {
3591 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3592 unsigned num_channels = util_last_bit(mask);
3593 LLVMValueRef rsrc, vindex;
3594
3595 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3596 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3597 ctx->ac.i32_0, "");
3598
3599 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3600 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3601 ctx->ac.i32_0, num_channels,
3602 false, false);
3603 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3604
3605 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3606 res = ac_to_integer(&ctx->ac, res);
3607 } else {
3608 bool is_da = glsl_sampler_type_is_array(type) ||
3609 dim == GLSL_SAMPLER_DIM_CUBE ||
3610 dim == GLSL_SAMPLER_DIM_3D ||
3611 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3612 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3613 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3614 LLVMValueRef glc = ctx->ac.i1false;
3615 LLVMValueRef slc = ctx->ac.i1false;
3616
3617 params[0] = get_image_coords(ctx, instr);
3618 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3619 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3620 params[3] = glc;
3621 params[4] = slc;
3622 params[5] = ctx->ac.i1false;
3623 params[6] = da;
3624
3625 ac_get_image_intr_name("llvm.amdgcn.image.load",
3626 ctx->ac.v4f32, /* vdata */
3627 LLVMTypeOf(params[0]), /* coords */
3628 LLVMTypeOf(params[1]), /* rsrc */
3629 intrinsic_name, sizeof(intrinsic_name));
3630
3631 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3632 params, 7, AC_FUNC_ATTR_READONLY);
3633 }
3634 return ac_to_integer(&ctx->ac, res);
3635 }
3636
3637 static void visit_image_store(struct ac_nir_context *ctx,
3638 nir_intrinsic_instr *instr)
3639 {
3640 LLVMValueRef params[8];
3641 char intrinsic_name[64];
3642 const nir_variable *var = instr->variables[0]->var;
3643 const struct glsl_type *type = glsl_without_array(var->type);
3644 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3645 LLVMValueRef glc = ctx->ac.i1false;
3646 bool force_glc = ctx->ac.chip_class == SI;
3647 if (force_glc)
3648 glc = ctx->ac.i1true;
3649
3650 if (dim == GLSL_SAMPLER_DIM_BUF) {
3651 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3652 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3653 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3654 ctx->ac.i32_0, ""); /* vindex */
3655 params[3] = ctx->ac.i32_0; /* voffset */
3656 params[4] = glc; /* glc */
3657 params[5] = ctx->ac.i1false; /* slc */
3658 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3659 params, 6, 0);
3660 } else {
3661 bool is_da = glsl_sampler_type_is_array(type) ||
3662 dim == GLSL_SAMPLER_DIM_CUBE ||
3663 dim == GLSL_SAMPLER_DIM_3D;
3664 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3665 LLVMValueRef slc = ctx->ac.i1false;
3666
3667 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3668 params[1] = get_image_coords(ctx, instr); /* coords */
3669 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3670 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3671 params[4] = glc;
3672 params[5] = slc;
3673 params[6] = ctx->ac.i1false;
3674 params[7] = da;
3675
3676 ac_get_image_intr_name("llvm.amdgcn.image.store",
3677 LLVMTypeOf(params[0]), /* vdata */
3678 LLVMTypeOf(params[1]), /* coords */
3679 LLVMTypeOf(params[2]), /* rsrc */
3680 intrinsic_name, sizeof(intrinsic_name));
3681
3682 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3683 params, 8, 0);
3684 }
3685
3686 }
3687
3688 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3689 const nir_intrinsic_instr *instr)
3690 {
3691 LLVMValueRef params[7];
3692 int param_count = 0;
3693 const nir_variable *var = instr->variables[0]->var;
3694
3695 const char *atomic_name;
3696 char intrinsic_name[41];
3697 const struct glsl_type *type = glsl_without_array(var->type);
3698 MAYBE_UNUSED int length;
3699
3700 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3701
3702 switch (instr->intrinsic) {
3703 case nir_intrinsic_image_atomic_add:
3704 atomic_name = "add";
3705 break;
3706 case nir_intrinsic_image_atomic_min:
3707 atomic_name = is_unsigned ? "umin" : "smin";
3708 break;
3709 case nir_intrinsic_image_atomic_max:
3710 atomic_name = is_unsigned ? "umax" : "smax";
3711 break;
3712 case nir_intrinsic_image_atomic_and:
3713 atomic_name = "and";
3714 break;
3715 case nir_intrinsic_image_atomic_or:
3716 atomic_name = "or";
3717 break;
3718 case nir_intrinsic_image_atomic_xor:
3719 atomic_name = "xor";
3720 break;
3721 case nir_intrinsic_image_atomic_exchange:
3722 atomic_name = "swap";
3723 break;
3724 case nir_intrinsic_image_atomic_comp_swap:
3725 atomic_name = "cmpswap";
3726 break;
3727 default:
3728 abort();
3729 }
3730
3731 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3732 params[param_count++] = get_src(ctx, instr->src[3]);
3733 params[param_count++] = get_src(ctx, instr->src[2]);
3734
3735 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3736 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3737 NULL, true, true);
3738 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3739 ctx->ac.i32_0, ""); /* vindex */
3740 params[param_count++] = ctx->ac.i32_0; /* voffset */
3741 params[param_count++] = ctx->ac.i1false; /* slc */
3742
3743 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3744 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3745 } else {
3746 char coords_type[8];
3747
3748 bool da = glsl_sampler_type_is_array(type) ||
3749 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3750
3751 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3752 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3753 NULL, true, true);
3754 params[param_count++] = ctx->ac.i1false; /* r128 */
3755 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3756 params[param_count++] = ctx->ac.i1false; /* slc */
3757
3758 build_int_type_name(LLVMTypeOf(coords),
3759 coords_type, sizeof(coords_type));
3760
3761 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3762 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3763 }
3764
3765 assert(length < sizeof(intrinsic_name));
3766 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3767 }
3768
3769 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3770 const nir_intrinsic_instr *instr)
3771 {
3772 LLVMValueRef res;
3773 const nir_variable *var = instr->variables[0]->var;
3774 const struct glsl_type *type = instr->variables[0]->var->type;
3775 bool da = glsl_sampler_type_is_array(var->type) ||
3776 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE ||
3777 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_3D;
3778 if(instr->variables[0]->deref.child)
3779 type = instr->variables[0]->deref.child->type;
3780
3781 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3782 return get_buffer_size(ctx,
3783 get_sampler_desc(ctx, instr->variables[0],
3784 AC_DESC_BUFFER, NULL, true, false), true);
3785
3786 struct ac_image_args args = { 0 };
3787
3788 args.da = da;
3789 args.dmask = 0xf;
3790 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3791 args.opcode = ac_image_get_resinfo;
3792 args.addr = ctx->ac.i32_0;
3793
3794 res = ac_build_image_opcode(&ctx->ac, &args);
3795
3796 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3797
3798 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3799 glsl_sampler_type_is_array(type)) {
3800 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3801 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3802 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3803 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3804 }
3805 if (ctx->ac.chip_class >= GFX9 &&
3806 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3807 glsl_sampler_type_is_array(type)) {
3808 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3809 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3810 ctx->ac.i32_1, "");
3811
3812 }
3813 return res;
3814 }
3815
3816 #define NOOP_WAITCNT 0xf7f
3817 #define LGKM_CNT 0x07f
3818 #define VM_CNT 0xf70
3819
3820 static void emit_membar(struct ac_llvm_context *ac,
3821 const nir_intrinsic_instr *instr)
3822 {
3823 unsigned waitcnt = NOOP_WAITCNT;
3824
3825 switch (instr->intrinsic) {
3826 case nir_intrinsic_memory_barrier:
3827 case nir_intrinsic_group_memory_barrier:
3828 waitcnt &= VM_CNT & LGKM_CNT;
3829 break;
3830 case nir_intrinsic_memory_barrier_atomic_counter:
3831 case nir_intrinsic_memory_barrier_buffer:
3832 case nir_intrinsic_memory_barrier_image:
3833 waitcnt &= VM_CNT;
3834 break;
3835 case nir_intrinsic_memory_barrier_shared:
3836 waitcnt &= LGKM_CNT;
3837 break;
3838 default:
3839 break;
3840 }
3841 if (waitcnt != NOOP_WAITCNT)
3842 ac_build_waitcnt(ac, waitcnt);
3843 }
3844
3845 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3846 {
3847 /* SI only (thanks to a hw bug workaround):
3848 * The real barrier instruction isn’t needed, because an entire patch
3849 * always fits into a single wave.
3850 */
3851 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3852 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3853 return;
3854 }
3855 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3856 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3857 }
3858
3859 static void emit_discard(struct ac_nir_context *ctx,
3860 const nir_intrinsic_instr *instr)
3861 {
3862 LLVMValueRef cond;
3863
3864 if (instr->intrinsic == nir_intrinsic_discard_if) {
3865 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3866 get_src(ctx, instr->src[0]),
3867 ctx->ac.i32_0, "");
3868 } else {
3869 assert(instr->intrinsic == nir_intrinsic_discard);
3870 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3871 }
3872
3873 ac_build_kill_if_false(&ctx->ac, cond);
3874 }
3875
3876 static LLVMValueRef
3877 visit_load_helper_invocation(struct ac_nir_context *ctx)
3878 {
3879 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3880 "llvm.amdgcn.ps.live",
3881 ctx->ac.i1, NULL, 0,
3882 AC_FUNC_ATTR_READNONE);
3883 result = LLVMBuildNot(ctx->ac.builder, result, "");
3884 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3885 }
3886
3887 static LLVMValueRef
3888 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3889 {
3890 LLVMValueRef result;
3891 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3892 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3893 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3894
3895 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3896 }
3897
3898 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3899 const nir_intrinsic_instr *instr)
3900 {
3901 LLVMValueRef ptr, result;
3902 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3903 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3904
3905 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3906 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3907 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3908 ptr, src, src1,
3909 LLVMAtomicOrderingSequentiallyConsistent,
3910 LLVMAtomicOrderingSequentiallyConsistent,
3911 false);
3912 } else {
3913 LLVMAtomicRMWBinOp op;
3914 switch (instr->intrinsic) {
3915 case nir_intrinsic_var_atomic_add:
3916 op = LLVMAtomicRMWBinOpAdd;
3917 break;
3918 case nir_intrinsic_var_atomic_umin:
3919 op = LLVMAtomicRMWBinOpUMin;
3920 break;
3921 case nir_intrinsic_var_atomic_umax:
3922 op = LLVMAtomicRMWBinOpUMax;
3923 break;
3924 case nir_intrinsic_var_atomic_imin:
3925 op = LLVMAtomicRMWBinOpMin;
3926 break;
3927 case nir_intrinsic_var_atomic_imax:
3928 op = LLVMAtomicRMWBinOpMax;
3929 break;
3930 case nir_intrinsic_var_atomic_and:
3931 op = LLVMAtomicRMWBinOpAnd;
3932 break;
3933 case nir_intrinsic_var_atomic_or:
3934 op = LLVMAtomicRMWBinOpOr;
3935 break;
3936 case nir_intrinsic_var_atomic_xor:
3937 op = LLVMAtomicRMWBinOpXor;
3938 break;
3939 case nir_intrinsic_var_atomic_exchange:
3940 op = LLVMAtomicRMWBinOpXchg;
3941 break;
3942 default:
3943 return NULL;
3944 }
3945
3946 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3947 LLVMAtomicOrderingSequentiallyConsistent,
3948 false);
3949 }
3950 return result;
3951 }
3952
3953 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
3954 enum glsl_interp_mode interp, unsigned location)
3955 {
3956 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3957
3958 switch (interp) {
3959 case INTERP_MODE_FLAT:
3960 default:
3961 return NULL;
3962 case INTERP_MODE_SMOOTH:
3963 case INTERP_MODE_NONE:
3964 if (location == INTERP_CENTER)
3965 return ctx->persp_center;
3966 else if (location == INTERP_CENTROID)
3967 return ctx->persp_centroid;
3968 else if (location == INTERP_SAMPLE)
3969 return ctx->persp_sample;
3970 break;
3971 case INTERP_MODE_NOPERSPECTIVE:
3972 if (location == INTERP_CENTER)
3973 return ctx->linear_center;
3974 else if (location == INTERP_CENTROID)
3975 return ctx->linear_centroid;
3976 else if (location == INTERP_SAMPLE)
3977 return ctx->linear_sample;
3978 break;
3979 }
3980 return NULL;
3981 }
3982
3983 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
3984 LLVMValueRef sample_id)
3985 {
3986 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3987
3988 LLVMValueRef result;
3989 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3990
3991 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3992 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
3993
3994 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3995 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3996
3997 return result;
3998 }
3999
4000 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4001 {
4002 LLVMValueRef values[2];
4003
4004 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0], 32);
4005 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1], 32);
4006 return ac_build_gather_values(&ctx->ac, values, 2);
4007 }
4008
4009 static LLVMValueRef load_sample_mask_in(struct ac_nir_context *ctx)
4010 {
4011 uint8_t log2_ps_iter_samples = ctx->nctx->shader_info->info.ps.force_persample ? ctx->nctx->options->key.fs.log2_num_samples : ctx->nctx->options->key.fs.log2_ps_iter_samples;
4012
4013 /* The bit pattern matches that used by fixed function fragment
4014 * processing. */
4015 static const uint16_t ps_iter_masks[] = {
4016 0xffff, /* not used */
4017 0x5555,
4018 0x1111,
4019 0x0101,
4020 0x0001,
4021 };
4022 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4023
4024 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4025
4026 LLVMValueRef result, sample_id;
4027 sample_id = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4028 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4029 result = LLVMBuildAnd(ctx->ac.builder, sample_id, ctx->abi->sample_coverage, "");
4030 return result;
4031 }
4032
4033 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4034 const nir_intrinsic_instr *instr)
4035 {
4036 LLVMValueRef result[4];
4037 LLVMValueRef interp_param, attr_number;
4038 unsigned location;
4039 unsigned chan;
4040 LLVMValueRef src_c0 = NULL;
4041 LLVMValueRef src_c1 = NULL;
4042 LLVMValueRef src0 = NULL;
4043 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4044 switch (instr->intrinsic) {
4045 case nir_intrinsic_interp_var_at_centroid:
4046 location = INTERP_CENTROID;
4047 break;
4048 case nir_intrinsic_interp_var_at_sample:
4049 case nir_intrinsic_interp_var_at_offset:
4050 location = INTERP_CENTER;
4051 src0 = get_src(ctx, instr->src[0]);
4052 break;
4053 default:
4054 break;
4055 }
4056
4057 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4058 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4059 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4060 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4061 LLVMValueRef sample_position;
4062 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4063
4064 /* fetch sample ID */
4065 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4066
4067 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4068 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4069 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4070 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4071 }
4072 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4073 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4074
4075 if (location == INTERP_CENTER) {
4076 LLVMValueRef ij_out[2];
4077 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4078
4079 /*
4080 * take the I then J parameters, and the DDX/Y for it, and
4081 * calculate the IJ inputs for the interpolator.
4082 * temp1 = ddx * offset/sample.x + I;
4083 * interp_param.I = ddy * offset/sample.y + temp1;
4084 * temp1 = ddx * offset/sample.x + J;
4085 * interp_param.J = ddy * offset/sample.y + temp1;
4086 */
4087 for (unsigned i = 0; i < 2; i++) {
4088 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4089 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4090 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4091 ddxy_out, ix_ll, "");
4092 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4093 ddxy_out, iy_ll, "");
4094 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4095 interp_param, ix_ll, "");
4096 LLVMValueRef temp1, temp2;
4097
4098 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4099 ctx->ac.f32, "");
4100
4101 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4102 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4103
4104 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4105 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4106
4107 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4108 temp2, ctx->ac.i32, "");
4109 }
4110 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4111
4112 }
4113
4114 for (chan = 0; chan < 4; chan++) {
4115 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4116
4117 if (interp_param) {
4118 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4119 interp_param, ctx->ac.v2f32, "");
4120 LLVMValueRef i = LLVMBuildExtractElement(
4121 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4122 LLVMValueRef j = LLVMBuildExtractElement(
4123 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4124
4125 result[chan] = ac_build_fs_interp(&ctx->ac,
4126 llvm_chan, attr_number,
4127 ctx->abi->prim_mask, i, j);
4128 } else {
4129 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4130 LLVMConstInt(ctx->ac.i32, 2, false),
4131 llvm_chan, attr_number,
4132 ctx->abi->prim_mask);
4133 }
4134 }
4135 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4136 instr->variables[0]->var->data.location_frac);
4137 }
4138
4139 static void
4140 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4141 {
4142 LLVMValueRef gs_next_vertex;
4143 LLVMValueRef can_emit;
4144 int idx;
4145 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4146
4147 assert(stream == 0);
4148
4149 /* Write vertex attribute values to GSVS ring */
4150 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4151 ctx->gs_next_vertex,
4152 "");
4153
4154 /* If this thread has already emitted the declared maximum number of
4155 * vertices, kill it: excessive vertex emissions are not supposed to
4156 * have any effect, and GS threads have no externally observable
4157 * effects other than emitting vertices.
4158 */
4159 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4160 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4161 ac_build_kill_if_false(&ctx->ac, can_emit);
4162
4163 /* loop num outputs */
4164 idx = 0;
4165 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4166 LLVMValueRef *out_ptr = &addrs[i * 4];
4167 int length = 4;
4168 int slot = idx;
4169 int slot_inc = 1;
4170
4171 if (!(ctx->output_mask & (1ull << i)))
4172 continue;
4173
4174 if (i == VARYING_SLOT_CLIP_DIST0) {
4175 /* pack clip and cull into a single set of slots */
4176 length = ctx->num_output_clips + ctx->num_output_culls;
4177 if (length > 4)
4178 slot_inc = 2;
4179 }
4180 for (unsigned j = 0; j < length; j++) {
4181 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4182 out_ptr[j], "");
4183 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4184 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4185 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4186
4187 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4188
4189 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4190 out_val, 1,
4191 voffset, ctx->gs2vs_offset, 0,
4192 1, 1, true, true);
4193 }
4194 idx += slot_inc;
4195 }
4196
4197 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4198 ctx->ac.i32_1, "");
4199 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4200
4201 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4202 }
4203
4204 static void
4205 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4206 {
4207 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4208 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4209 }
4210
4211 static LLVMValueRef
4212 load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
4213 unsigned num_components)
4214 {
4215 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4216
4217 LLVMValueRef coord[4] = {
4218 ctx->tes_u,
4219 ctx->tes_v,
4220 ctx->ac.f32_0,
4221 ctx->ac.f32_0,
4222 };
4223
4224 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4225 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4226 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4227
4228 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, num_components);
4229 return LLVMBuildBitCast(ctx->builder, result, type, "");
4230 }
4231
4232 static LLVMValueRef
4233 load_patch_vertices_in(struct ac_shader_abi *abi)
4234 {
4235 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4236 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4237 }
4238
4239 static void visit_intrinsic(struct ac_nir_context *ctx,
4240 nir_intrinsic_instr *instr)
4241 {
4242 LLVMValueRef result = NULL;
4243
4244 switch (instr->intrinsic) {
4245 case nir_intrinsic_ballot:
4246 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4247 break;
4248 case nir_intrinsic_read_invocation:
4249 case nir_intrinsic_read_first_invocation: {
4250 LLVMValueRef args[2];
4251
4252 /* Value */
4253 args[0] = get_src(ctx, instr->src[0]);
4254
4255 unsigned num_args;
4256 const char *intr_name;
4257 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4258 num_args = 2;
4259 intr_name = "llvm.amdgcn.readlane";
4260
4261 /* Invocation */
4262 args[1] = get_src(ctx, instr->src[1]);
4263 } else {
4264 num_args = 1;
4265 intr_name = "llvm.amdgcn.readfirstlane";
4266 }
4267
4268 /* We currently have no other way to prevent LLVM from lifting the icmp
4269 * calls to a dominating basic block.
4270 */
4271 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4272
4273 result = ac_build_intrinsic(&ctx->ac, intr_name,
4274 ctx->ac.i32, args, num_args,
4275 AC_FUNC_ATTR_READNONE |
4276 AC_FUNC_ATTR_CONVERGENT);
4277 break;
4278 }
4279 case nir_intrinsic_load_subgroup_invocation:
4280 result = ac_get_thread_id(&ctx->ac);
4281 break;
4282 case nir_intrinsic_load_work_group_id: {
4283 LLVMValueRef values[3];
4284
4285 for (int i = 0; i < 3; i++) {
4286 values[i] = ctx->abi->workgroup_ids[i] ?
4287 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4288 }
4289
4290 result = ac_build_gather_values(&ctx->ac, values, 3);
4291 break;
4292 }
4293 case nir_intrinsic_load_base_vertex: {
4294 result = ctx->abi->base_vertex;
4295 break;
4296 }
4297 case nir_intrinsic_load_local_group_size:
4298 result = ctx->abi->load_local_group_size(ctx->abi);
4299 break;
4300 case nir_intrinsic_load_vertex_id_zero_base: {
4301 result = ctx->abi->vertex_id;
4302 break;
4303 }
4304 case nir_intrinsic_load_local_invocation_id: {
4305 result = ctx->abi->local_invocation_ids;
4306 break;
4307 }
4308 case nir_intrinsic_load_base_instance:
4309 result = ctx->abi->start_instance;
4310 break;
4311 case nir_intrinsic_load_draw_id:
4312 result = ctx->abi->draw_id;
4313 break;
4314 case nir_intrinsic_load_view_index:
4315 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4316 break;
4317 case nir_intrinsic_load_invocation_id:
4318 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4319 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4320 else
4321 result = ctx->abi->gs_invocation_id;
4322 break;
4323 case nir_intrinsic_load_primitive_id:
4324 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4325 result = ctx->abi->gs_prim_id;
4326 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4327 result = ctx->abi->tcs_patch_id;
4328 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4329 result = ctx->abi->tes_patch_id;
4330 } else
4331 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4332 break;
4333 case nir_intrinsic_load_sample_id:
4334 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4335 break;
4336 case nir_intrinsic_load_sample_pos:
4337 result = load_sample_pos(ctx);
4338 break;
4339 case nir_intrinsic_load_sample_mask_in:
4340 if (ctx->nctx)
4341 result = load_sample_mask_in(ctx);
4342 else
4343 result = ctx->abi->sample_coverage;
4344 break;
4345 case nir_intrinsic_load_frag_coord: {
4346 LLVMValueRef values[4] = {
4347 ctx->abi->frag_pos[0],
4348 ctx->abi->frag_pos[1],
4349 ctx->abi->frag_pos[2],
4350 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4351 };
4352 result = ac_build_gather_values(&ctx->ac, values, 4);
4353 break;
4354 }
4355 case nir_intrinsic_load_front_face:
4356 result = ctx->abi->front_face;
4357 break;
4358 case nir_intrinsic_load_helper_invocation:
4359 result = visit_load_helper_invocation(ctx);
4360 break;
4361 case nir_intrinsic_load_instance_id:
4362 result = ctx->abi->instance_id;
4363 break;
4364 case nir_intrinsic_load_num_work_groups:
4365 result = ctx->abi->num_work_groups;
4366 break;
4367 case nir_intrinsic_load_local_invocation_index:
4368 result = visit_load_local_invocation_index(ctx->nctx);
4369 break;
4370 case nir_intrinsic_load_push_constant:
4371 result = visit_load_push_constant(ctx->nctx, instr);
4372 break;
4373 case nir_intrinsic_vulkan_resource_index:
4374 result = visit_vulkan_resource_index(ctx->nctx, instr);
4375 break;
4376 case nir_intrinsic_vulkan_resource_reindex:
4377 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4378 break;
4379 case nir_intrinsic_store_ssbo:
4380 visit_store_ssbo(ctx, instr);
4381 break;
4382 case nir_intrinsic_load_ssbo:
4383 result = visit_load_buffer(ctx, instr);
4384 break;
4385 case nir_intrinsic_ssbo_atomic_add:
4386 case nir_intrinsic_ssbo_atomic_imin:
4387 case nir_intrinsic_ssbo_atomic_umin:
4388 case nir_intrinsic_ssbo_atomic_imax:
4389 case nir_intrinsic_ssbo_atomic_umax:
4390 case nir_intrinsic_ssbo_atomic_and:
4391 case nir_intrinsic_ssbo_atomic_or:
4392 case nir_intrinsic_ssbo_atomic_xor:
4393 case nir_intrinsic_ssbo_atomic_exchange:
4394 case nir_intrinsic_ssbo_atomic_comp_swap:
4395 result = visit_atomic_ssbo(ctx, instr);
4396 break;
4397 case nir_intrinsic_load_ubo:
4398 result = visit_load_ubo_buffer(ctx, instr);
4399 break;
4400 case nir_intrinsic_get_buffer_size:
4401 result = visit_get_buffer_size(ctx, instr);
4402 break;
4403 case nir_intrinsic_load_var:
4404 result = visit_load_var(ctx, instr);
4405 break;
4406 case nir_intrinsic_store_var:
4407 visit_store_var(ctx, instr);
4408 break;
4409 case nir_intrinsic_image_load:
4410 result = visit_image_load(ctx, instr);
4411 break;
4412 case nir_intrinsic_image_store:
4413 visit_image_store(ctx, instr);
4414 break;
4415 case nir_intrinsic_image_atomic_add:
4416 case nir_intrinsic_image_atomic_min:
4417 case nir_intrinsic_image_atomic_max:
4418 case nir_intrinsic_image_atomic_and:
4419 case nir_intrinsic_image_atomic_or:
4420 case nir_intrinsic_image_atomic_xor:
4421 case nir_intrinsic_image_atomic_exchange:
4422 case nir_intrinsic_image_atomic_comp_swap:
4423 result = visit_image_atomic(ctx, instr);
4424 break;
4425 case nir_intrinsic_image_size:
4426 result = visit_image_size(ctx, instr);
4427 break;
4428 case nir_intrinsic_shader_clock:
4429 result = ac_build_shader_clock(&ctx->ac);
4430 break;
4431 case nir_intrinsic_discard:
4432 case nir_intrinsic_discard_if:
4433 emit_discard(ctx, instr);
4434 break;
4435 case nir_intrinsic_memory_barrier:
4436 case nir_intrinsic_group_memory_barrier:
4437 case nir_intrinsic_memory_barrier_atomic_counter:
4438 case nir_intrinsic_memory_barrier_buffer:
4439 case nir_intrinsic_memory_barrier_image:
4440 case nir_intrinsic_memory_barrier_shared:
4441 emit_membar(&ctx->ac, instr);
4442 break;
4443 case nir_intrinsic_barrier:
4444 emit_barrier(&ctx->ac, ctx->stage);
4445 break;
4446 case nir_intrinsic_var_atomic_add:
4447 case nir_intrinsic_var_atomic_imin:
4448 case nir_intrinsic_var_atomic_umin:
4449 case nir_intrinsic_var_atomic_imax:
4450 case nir_intrinsic_var_atomic_umax:
4451 case nir_intrinsic_var_atomic_and:
4452 case nir_intrinsic_var_atomic_or:
4453 case nir_intrinsic_var_atomic_xor:
4454 case nir_intrinsic_var_atomic_exchange:
4455 case nir_intrinsic_var_atomic_comp_swap:
4456 result = visit_var_atomic(ctx->nctx, instr);
4457 break;
4458 case nir_intrinsic_interp_var_at_centroid:
4459 case nir_intrinsic_interp_var_at_sample:
4460 case nir_intrinsic_interp_var_at_offset:
4461 result = visit_interp(ctx, instr);
4462 break;
4463 case nir_intrinsic_emit_vertex:
4464 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->outputs);
4465 break;
4466 case nir_intrinsic_end_primitive:
4467 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4468 break;
4469 case nir_intrinsic_load_tess_coord: {
4470 LLVMTypeRef type = ctx->nctx ?
4471 get_def_type(ctx->nctx->nir, &instr->dest.ssa) :
4472 NULL;
4473 result = ctx->abi->load_tess_coord(ctx->abi, type, instr->num_components);
4474 break;
4475 }
4476 case nir_intrinsic_load_tess_level_outer:
4477 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4478 break;
4479 case nir_intrinsic_load_tess_level_inner:
4480 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4481 break;
4482 case nir_intrinsic_load_patch_vertices_in:
4483 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4484 break;
4485 case nir_intrinsic_vote_all: {
4486 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4487 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4488 break;
4489 }
4490 case nir_intrinsic_vote_any: {
4491 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4492 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4493 break;
4494 }
4495 case nir_intrinsic_vote_eq: {
4496 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4497 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4498 break;
4499 }
4500 default:
4501 fprintf(stderr, "Unknown intrinsic: ");
4502 nir_print_instr(&instr->instr, stderr);
4503 fprintf(stderr, "\n");
4504 break;
4505 }
4506 if (result) {
4507 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4508 }
4509 }
4510
4511 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4512 LLVMValueRef buffer_ptr, bool write)
4513 {
4514 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4515 LLVMValueRef result;
4516
4517 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4518
4519 result = LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4520 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4521
4522 return result;
4523 }
4524
4525 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4526 {
4527 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4528 LLVMValueRef result;
4529
4530 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4531
4532 result = LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4533 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4534
4535 return result;
4536 }
4537
4538 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4539 unsigned descriptor_set,
4540 unsigned base_index,
4541 unsigned constant_index,
4542 LLVMValueRef index,
4543 enum ac_descriptor_type desc_type,
4544 bool image, bool write)
4545 {
4546 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4547 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4548 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4549 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4550 unsigned offset = binding->offset;
4551 unsigned stride = binding->size;
4552 unsigned type_size;
4553 LLVMBuilderRef builder = ctx->builder;
4554 LLVMTypeRef type;
4555
4556 assert(base_index < layout->binding_count);
4557
4558 switch (desc_type) {
4559 case AC_DESC_IMAGE:
4560 type = ctx->ac.v8i32;
4561 type_size = 32;
4562 break;
4563 case AC_DESC_FMASK:
4564 type = ctx->ac.v8i32;
4565 offset += 32;
4566 type_size = 32;
4567 break;
4568 case AC_DESC_SAMPLER:
4569 type = ctx->ac.v4i32;
4570 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4571 offset += 64;
4572
4573 type_size = 16;
4574 break;
4575 case AC_DESC_BUFFER:
4576 type = ctx->ac.v4i32;
4577 type_size = 16;
4578 break;
4579 default:
4580 unreachable("invalid desc_type\n");
4581 }
4582
4583 offset += constant_index * stride;
4584
4585 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4586 (!index || binding->immutable_samplers_equal)) {
4587 if (binding->immutable_samplers_equal)
4588 constant_index = 0;
4589
4590 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4591
4592 LLVMValueRef constants[] = {
4593 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4594 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4595 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4596 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4597 };
4598 return ac_build_gather_values(&ctx->ac, constants, 4);
4599 }
4600
4601 assert(stride % type_size == 0);
4602
4603 if (!index)
4604 index = ctx->ac.i32_0;
4605
4606 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4607
4608 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4609 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4610
4611 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4612 }
4613
4614 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4615 const nir_deref_var *deref,
4616 enum ac_descriptor_type desc_type,
4617 const nir_tex_instr *tex_instr,
4618 bool image, bool write)
4619 {
4620 LLVMValueRef index = NULL;
4621 unsigned constant_index = 0;
4622 unsigned descriptor_set;
4623 unsigned base_index;
4624
4625 if (!deref) {
4626 assert(tex_instr && !image);
4627 descriptor_set = 0;
4628 base_index = tex_instr->sampler_index;
4629 } else {
4630 const nir_deref *tail = &deref->deref;
4631 while (tail->child) {
4632 const nir_deref_array *child = nir_deref_as_array(tail->child);
4633 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4634
4635 if (!array_size)
4636 array_size = 1;
4637
4638 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4639
4640 if (child->deref_array_type == nir_deref_array_type_indirect) {
4641 LLVMValueRef indirect = get_src(ctx, child->indirect);
4642
4643 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4644 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4645
4646 if (!index)
4647 index = indirect;
4648 else
4649 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4650 }
4651
4652 constant_index += child->base_offset * array_size;
4653
4654 tail = &child->deref;
4655 }
4656 descriptor_set = deref->var->data.descriptor_set;
4657 base_index = deref->var->data.binding;
4658 }
4659
4660 return ctx->abi->load_sampler_desc(ctx->abi,
4661 descriptor_set,
4662 base_index,
4663 constant_index, index,
4664 desc_type, image, write);
4665 }
4666
4667 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4668 struct ac_image_args *args,
4669 const nir_tex_instr *instr,
4670 nir_texop op,
4671 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4672 LLVMValueRef *param, unsigned count,
4673 unsigned dmask)
4674 {
4675 unsigned is_rect = 0;
4676 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4677
4678 if (op == nir_texop_lod)
4679 da = false;
4680 /* Pad to power of two vector */
4681 while (count < util_next_power_of_two(count))
4682 param[count++] = LLVMGetUndef(ctx->i32);
4683
4684 if (count > 1)
4685 args->addr = ac_build_gather_values(ctx, param, count);
4686 else
4687 args->addr = param[0];
4688
4689 args->resource = res_ptr;
4690 args->sampler = samp_ptr;
4691
4692 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4693 args->addr = param[0];
4694 return;
4695 }
4696
4697 args->dmask = dmask;
4698 args->unorm = is_rect;
4699 args->da = da;
4700 }
4701
4702 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4703 *
4704 * SI-CI:
4705 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4706 * filtering manually. The driver sets img7 to a mask clearing
4707 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4708 * s_and_b32 samp0, samp0, img7
4709 *
4710 * VI:
4711 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4712 */
4713 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4714 LLVMValueRef res, LLVMValueRef samp)
4715 {
4716 LLVMBuilderRef builder = ctx->ac.builder;
4717 LLVMValueRef img7, samp0;
4718
4719 if (ctx->ac.chip_class >= VI)
4720 return samp;
4721
4722 img7 = LLVMBuildExtractElement(builder, res,
4723 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4724 samp0 = LLVMBuildExtractElement(builder, samp,
4725 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4726 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4727 return LLVMBuildInsertElement(builder, samp, samp0,
4728 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4729 }
4730
4731 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4732 nir_tex_instr *instr,
4733 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4734 LLVMValueRef *fmask_ptr)
4735 {
4736 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4737 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4738 else
4739 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4740 if (samp_ptr) {
4741 if (instr->sampler)
4742 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4743 else
4744 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4745 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4746 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4747 }
4748 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4749 instr->op == nir_texop_samples_identical))
4750 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4751 }
4752
4753 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4754 LLVMValueRef coord)
4755 {
4756 coord = ac_to_float(ctx, coord);
4757 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4758 coord = ac_to_integer(ctx, coord);
4759 return coord;
4760 }
4761
4762 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4763 {
4764 LLVMValueRef result = NULL;
4765 struct ac_image_args args = { 0 };
4766 unsigned dmask = 0xf;
4767 LLVMValueRef address[16];
4768 LLVMValueRef coords[5];
4769 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4770 LLVMValueRef bias = NULL, offsets = NULL;
4771 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4772 LLVMValueRef ddx = NULL, ddy = NULL;
4773 LLVMValueRef derivs[6];
4774 unsigned chan, count = 0;
4775 unsigned const_src = 0, num_deriv_comp = 0;
4776 bool lod_is_zero = false;
4777
4778 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4779
4780 for (unsigned i = 0; i < instr->num_srcs; i++) {
4781 switch (instr->src[i].src_type) {
4782 case nir_tex_src_coord:
4783 coord = get_src(ctx, instr->src[i].src);
4784 break;
4785 case nir_tex_src_projector:
4786 break;
4787 case nir_tex_src_comparator:
4788 comparator = get_src(ctx, instr->src[i].src);
4789 break;
4790 case nir_tex_src_offset:
4791 offsets = get_src(ctx, instr->src[i].src);
4792 const_src = i;
4793 break;
4794 case nir_tex_src_bias:
4795 bias = get_src(ctx, instr->src[i].src);
4796 break;
4797 case nir_tex_src_lod: {
4798 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4799
4800 if (val && val->i32[0] == 0)
4801 lod_is_zero = true;
4802 lod = get_src(ctx, instr->src[i].src);
4803 break;
4804 }
4805 case nir_tex_src_ms_index:
4806 sample_index = get_src(ctx, instr->src[i].src);
4807 break;
4808 case nir_tex_src_ms_mcs:
4809 break;
4810 case nir_tex_src_ddx:
4811 ddx = get_src(ctx, instr->src[i].src);
4812 num_deriv_comp = instr->src[i].src.ssa->num_components;
4813 break;
4814 case nir_tex_src_ddy:
4815 ddy = get_src(ctx, instr->src[i].src);
4816 break;
4817 case nir_tex_src_texture_offset:
4818 case nir_tex_src_sampler_offset:
4819 case nir_tex_src_plane:
4820 default:
4821 break;
4822 }
4823 }
4824
4825 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4826 result = get_buffer_size(ctx, res_ptr, true);
4827 goto write_result;
4828 }
4829
4830 if (instr->op == nir_texop_texture_samples) {
4831 LLVMValueRef res, samples, is_msaa;
4832 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4833 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4834 LLVMConstInt(ctx->ac.i32, 3, false), "");
4835 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4836 LLVMConstInt(ctx->ac.i32, 28, false), "");
4837 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4838 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4839 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4840 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4841
4842 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4843 LLVMConstInt(ctx->ac.i32, 16, false), "");
4844 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4845 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4846 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4847 samples, "");
4848 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4849 ctx->ac.i32_1, "");
4850 result = samples;
4851 goto write_result;
4852 }
4853
4854 if (coord)
4855 for (chan = 0; chan < instr->coord_components; chan++)
4856 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4857
4858 if (offsets && instr->op != nir_texop_txf) {
4859 LLVMValueRef offset[3], pack;
4860 for (chan = 0; chan < 3; ++chan)
4861 offset[chan] = ctx->ac.i32_0;
4862
4863 args.offset = true;
4864 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4865 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4866 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4867 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4868 if (chan)
4869 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4870 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4871 }
4872 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4873 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4874 address[count++] = pack;
4875
4876 }
4877 /* pack LOD bias value */
4878 if (instr->op == nir_texop_txb && bias) {
4879 address[count++] = bias;
4880 }
4881
4882 /* Pack depth comparison value */
4883 if (instr->is_shadow && comparator) {
4884 LLVMValueRef z = ac_to_float(&ctx->ac,
4885 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4886
4887 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4888 * so the depth comparison value isn't clamped for Z16 and
4889 * Z24 anymore. Do it manually here.
4890 *
4891 * It's unnecessary if the original texture format was
4892 * Z32_FLOAT, but we don't know that here.
4893 */
4894 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4895 z = ac_build_clamp(&ctx->ac, z);
4896
4897 address[count++] = z;
4898 }
4899
4900 /* pack derivatives */
4901 if (ddx || ddy) {
4902 int num_src_deriv_channels, num_dest_deriv_channels;
4903 switch (instr->sampler_dim) {
4904 case GLSL_SAMPLER_DIM_3D:
4905 case GLSL_SAMPLER_DIM_CUBE:
4906 num_deriv_comp = 3;
4907 num_src_deriv_channels = 3;
4908 num_dest_deriv_channels = 3;
4909 break;
4910 case GLSL_SAMPLER_DIM_2D:
4911 default:
4912 num_src_deriv_channels = 2;
4913 num_dest_deriv_channels = 2;
4914 num_deriv_comp = 2;
4915 break;
4916 case GLSL_SAMPLER_DIM_1D:
4917 num_src_deriv_channels = 1;
4918 if (ctx->ac.chip_class >= GFX9) {
4919 num_dest_deriv_channels = 2;
4920 num_deriv_comp = 2;
4921 } else {
4922 num_dest_deriv_channels = 1;
4923 num_deriv_comp = 1;
4924 }
4925 break;
4926 }
4927
4928 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4929 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4930 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4931 }
4932 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4933 derivs[i] = ctx->ac.f32_0;
4934 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4935 }
4936 }
4937
4938 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4939 for (chan = 0; chan < instr->coord_components; chan++)
4940 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4941 if (instr->coord_components == 3)
4942 coords[3] = LLVMGetUndef(ctx->ac.f32);
4943 ac_prepare_cube_coords(&ctx->ac,
4944 instr->op == nir_texop_txd, instr->is_array,
4945 instr->op == nir_texop_lod, coords, derivs);
4946 if (num_deriv_comp)
4947 num_deriv_comp--;
4948 }
4949
4950 if (ddx || ddy) {
4951 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4952 address[count++] = derivs[i];
4953 }
4954
4955 /* Pack texture coordinates */
4956 if (coord) {
4957 address[count++] = coords[0];
4958 if (instr->coord_components > 1) {
4959 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4960 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4961 }
4962 address[count++] = coords[1];
4963 }
4964 if (instr->coord_components > 2) {
4965 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4966 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4967 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4968 instr->op != nir_texop_txf) {
4969 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4970 }
4971 address[count++] = coords[2];
4972 }
4973
4974 if (ctx->ac.chip_class >= GFX9) {
4975 LLVMValueRef filler;
4976 if (instr->op == nir_texop_txf)
4977 filler = ctx->ac.i32_0;
4978 else
4979 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4980
4981 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4982 /* No nir_texop_lod, because it does not take a slice
4983 * even with array textures. */
4984 if (instr->is_array && instr->op != nir_texop_lod ) {
4985 address[count] = address[count - 1];
4986 address[count - 1] = filler;
4987 count++;
4988 } else
4989 address[count++] = filler;
4990 }
4991 }
4992 }
4993
4994 /* Pack LOD */
4995 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4996 instr->op == nir_texop_txf)) {
4997 address[count++] = lod;
4998 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4999 address[count++] = sample_index;
5000 } else if(instr->op == nir_texop_txs) {
5001 count = 0;
5002 if (lod)
5003 address[count++] = lod;
5004 else
5005 address[count++] = ctx->ac.i32_0;
5006 }
5007
5008 for (chan = 0; chan < count; chan++) {
5009 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5010 address[chan], ctx->ac.i32, "");
5011 }
5012
5013 if (instr->op == nir_texop_samples_identical) {
5014 LLVMValueRef txf_address[4];
5015 struct ac_image_args txf_args = { 0 };
5016 unsigned txf_count = count;
5017 memcpy(txf_address, address, sizeof(txf_address));
5018
5019 if (!instr->is_array)
5020 txf_address[2] = ctx->ac.i32_0;
5021 txf_address[3] = ctx->ac.i32_0;
5022
5023 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5024 fmask_ptr, NULL,
5025 txf_address, txf_count, 0xf);
5026
5027 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5028
5029 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5030 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5031 goto write_result;
5032 }
5033
5034 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5035 instr->op != nir_texop_txs) {
5036 unsigned sample_chan = instr->is_array ? 3 : 2;
5037 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5038 address[0],
5039 address[1],
5040 instr->is_array ? address[2] : NULL,
5041 address[sample_chan],
5042 fmask_ptr);
5043 }
5044
5045 if (offsets && instr->op == nir_texop_txf) {
5046 nir_const_value *const_offset =
5047 nir_src_as_const_value(instr->src[const_src].src);
5048 int num_offsets = instr->src[const_src].src.ssa->num_components;
5049 assert(const_offset);
5050 num_offsets = MIN2(num_offsets, instr->coord_components);
5051 if (num_offsets > 2)
5052 address[2] = LLVMBuildAdd(ctx->ac.builder,
5053 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5054 if (num_offsets > 1)
5055 address[1] = LLVMBuildAdd(ctx->ac.builder,
5056 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5057 address[0] = LLVMBuildAdd(ctx->ac.builder,
5058 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5059
5060 }
5061
5062 /* TODO TG4 support */
5063 if (instr->op == nir_texop_tg4) {
5064 if (instr->is_shadow)
5065 dmask = 1;
5066 else
5067 dmask = 1 << instr->component;
5068 }
5069 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5070 res_ptr, samp_ptr, address, count, dmask);
5071
5072 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5073
5074 if (instr->op == nir_texop_query_levels)
5075 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5076 else if (instr->is_shadow && instr->is_new_style_shadow &&
5077 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5078 instr->op != nir_texop_tg4)
5079 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5080 else if (instr->op == nir_texop_txs &&
5081 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5082 instr->is_array) {
5083 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5084 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5085 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5086 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5087 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5088 } else if (ctx->ac.chip_class >= GFX9 &&
5089 instr->op == nir_texop_txs &&
5090 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5091 instr->is_array) {
5092 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5093 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5094 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5095 ctx->ac.i32_1, "");
5096 } else if (instr->dest.ssa.num_components != 4)
5097 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5098
5099 write_result:
5100 if (result) {
5101 assert(instr->dest.is_ssa);
5102 result = ac_to_integer(&ctx->ac, result);
5103 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5104 }
5105 }
5106
5107
5108 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5109 {
5110 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5111 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5112
5113 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5114 _mesa_hash_table_insert(ctx->phis, instr, result);
5115 }
5116
5117 static void visit_post_phi(struct ac_nir_context *ctx,
5118 nir_phi_instr *instr,
5119 LLVMValueRef llvm_phi)
5120 {
5121 nir_foreach_phi_src(src, instr) {
5122 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5123 LLVMValueRef llvm_src = get_src(ctx, src->src);
5124
5125 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5126 }
5127 }
5128
5129 static void phi_post_pass(struct ac_nir_context *ctx)
5130 {
5131 struct hash_entry *entry;
5132 hash_table_foreach(ctx->phis, entry) {
5133 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5134 (LLVMValueRef)entry->data);
5135 }
5136 }
5137
5138
5139 static void visit_ssa_undef(struct ac_nir_context *ctx,
5140 const nir_ssa_undef_instr *instr)
5141 {
5142 unsigned num_components = instr->def.num_components;
5143 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5144 LLVMValueRef undef;
5145
5146 if (num_components == 1)
5147 undef = LLVMGetUndef(type);
5148 else {
5149 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5150 }
5151 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5152 }
5153
5154 static void visit_jump(struct ac_nir_context *ctx,
5155 const nir_jump_instr *instr)
5156 {
5157 switch (instr->type) {
5158 case nir_jump_break:
5159 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5160 LLVMClearInsertionPosition(ctx->ac.builder);
5161 break;
5162 case nir_jump_continue:
5163 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5164 LLVMClearInsertionPosition(ctx->ac.builder);
5165 break;
5166 default:
5167 fprintf(stderr, "Unknown NIR jump instr: ");
5168 nir_print_instr(&instr->instr, stderr);
5169 fprintf(stderr, "\n");
5170 abort();
5171 }
5172 }
5173
5174 static void visit_cf_list(struct ac_nir_context *ctx,
5175 struct exec_list *list);
5176
5177 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5178 {
5179 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5180 nir_foreach_instr(instr, block)
5181 {
5182 switch (instr->type) {
5183 case nir_instr_type_alu:
5184 visit_alu(ctx, nir_instr_as_alu(instr));
5185 break;
5186 case nir_instr_type_load_const:
5187 visit_load_const(ctx, nir_instr_as_load_const(instr));
5188 break;
5189 case nir_instr_type_intrinsic:
5190 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5191 break;
5192 case nir_instr_type_tex:
5193 visit_tex(ctx, nir_instr_as_tex(instr));
5194 break;
5195 case nir_instr_type_phi:
5196 visit_phi(ctx, nir_instr_as_phi(instr));
5197 break;
5198 case nir_instr_type_ssa_undef:
5199 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5200 break;
5201 case nir_instr_type_jump:
5202 visit_jump(ctx, nir_instr_as_jump(instr));
5203 break;
5204 default:
5205 fprintf(stderr, "Unknown NIR instr type: ");
5206 nir_print_instr(instr, stderr);
5207 fprintf(stderr, "\n");
5208 abort();
5209 }
5210 }
5211
5212 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5213 }
5214
5215 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5216 {
5217 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5218
5219 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5220 LLVMBasicBlockRef merge_block =
5221 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5222 LLVMBasicBlockRef if_block =
5223 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5224 LLVMBasicBlockRef else_block = merge_block;
5225 if (!exec_list_is_empty(&if_stmt->else_list))
5226 else_block = LLVMAppendBasicBlockInContext(
5227 ctx->ac.context, fn, "");
5228
5229 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5230 ctx->ac.i32_0, "");
5231 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5232
5233 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5234 visit_cf_list(ctx, &if_stmt->then_list);
5235 if (LLVMGetInsertBlock(ctx->ac.builder))
5236 LLVMBuildBr(ctx->ac.builder, merge_block);
5237
5238 if (!exec_list_is_empty(&if_stmt->else_list)) {
5239 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5240 visit_cf_list(ctx, &if_stmt->else_list);
5241 if (LLVMGetInsertBlock(ctx->ac.builder))
5242 LLVMBuildBr(ctx->ac.builder, merge_block);
5243 }
5244
5245 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5246 }
5247
5248 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5249 {
5250 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5251 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5252 LLVMBasicBlockRef break_parent = ctx->break_block;
5253
5254 ctx->continue_block =
5255 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5256 ctx->break_block =
5257 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5258
5259 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5260 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5261 visit_cf_list(ctx, &loop->body);
5262
5263 if (LLVMGetInsertBlock(ctx->ac.builder))
5264 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5265 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5266
5267 ctx->continue_block = continue_parent;
5268 ctx->break_block = break_parent;
5269 }
5270
5271 static void visit_cf_list(struct ac_nir_context *ctx,
5272 struct exec_list *list)
5273 {
5274 foreach_list_typed(nir_cf_node, node, node, list)
5275 {
5276 switch (node->type) {
5277 case nir_cf_node_block:
5278 visit_block(ctx, nir_cf_node_as_block(node));
5279 break;
5280
5281 case nir_cf_node_if:
5282 visit_if(ctx, nir_cf_node_as_if(node));
5283 break;
5284
5285 case nir_cf_node_loop:
5286 visit_loop(ctx, nir_cf_node_as_loop(node));
5287 break;
5288
5289 default:
5290 assert(0);
5291 }
5292 }
5293 }
5294
5295 static void
5296 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5297 struct nir_variable *variable)
5298 {
5299 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5300 LLVMValueRef t_offset;
5301 LLVMValueRef t_list;
5302 LLVMValueRef input;
5303 LLVMValueRef buffer_index;
5304 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5305 int idx = variable->data.location;
5306 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5307 uint8_t input_usage_mask =
5308 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5309 unsigned num_channels = util_last_bit(input_usage_mask);
5310
5311 variable->data.driver_location = idx * 4;
5312
5313 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5314 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5315 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5316 ctx->abi.start_instance, "");
5317 if (ctx->options->key.vs.as_ls) {
5318 ctx->shader_info->vs.vgpr_comp_cnt =
5319 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5320 } else {
5321 ctx->shader_info->vs.vgpr_comp_cnt =
5322 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5323 }
5324 } else
5325 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5326 ctx->abi.base_vertex, "");
5327 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5328
5329 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5330
5331 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5332 buffer_index,
5333 ctx->ac.i32_0,
5334 num_channels, false, true);
5335
5336 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5337
5338 for (unsigned chan = 0; chan < 4; chan++) {
5339 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5340 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5341 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5342 input, llvm_chan, ""));
5343 }
5344 }
5345 }
5346
5347 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5348 unsigned attr,
5349 LLVMValueRef interp_param,
5350 LLVMValueRef prim_mask,
5351 LLVMValueRef result[4])
5352 {
5353 LLVMValueRef attr_number;
5354 unsigned chan;
5355 LLVMValueRef i, j;
5356 bool interp = interp_param != NULL;
5357
5358 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5359
5360 /* fs.constant returns the param from the middle vertex, so it's not
5361 * really useful for flat shading. It's meant to be used for custom
5362 * interpolation (but the intrinsic can't fetch from the other two
5363 * vertices).
5364 *
5365 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5366 * to do the right thing. The only reason we use fs.constant is that
5367 * fs.interp cannot be used on integers, because they can be equal
5368 * to NaN.
5369 */
5370 if (interp) {
5371 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5372 ctx->ac.v2f32, "");
5373
5374 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5375 ctx->ac.i32_0, "");
5376 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5377 ctx->ac.i32_1, "");
5378 }
5379
5380 for (chan = 0; chan < 4; chan++) {
5381 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5382
5383 if (interp) {
5384 result[chan] = ac_build_fs_interp(&ctx->ac,
5385 llvm_chan,
5386 attr_number,
5387 prim_mask, i, j);
5388 } else {
5389 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5390 LLVMConstInt(ctx->ac.i32, 2, false),
5391 llvm_chan,
5392 attr_number,
5393 prim_mask);
5394 }
5395 }
5396 }
5397
5398 static void
5399 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5400 struct nir_variable *variable)
5401 {
5402 int idx = variable->data.location;
5403 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5404 LLVMValueRef interp;
5405
5406 variable->data.driver_location = idx * 4;
5407 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5408
5409 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5410 unsigned interp_type;
5411 if (variable->data.sample) {
5412 interp_type = INTERP_SAMPLE;
5413 ctx->shader_info->info.ps.force_persample = true;
5414 } else if (variable->data.centroid)
5415 interp_type = INTERP_CENTROID;
5416 else
5417 interp_type = INTERP_CENTER;
5418
5419 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5420 } else
5421 interp = NULL;
5422
5423 for (unsigned i = 0; i < attrib_count; ++i)
5424 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5425
5426 }
5427
5428 static void
5429 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5430 struct nir_shader *nir) {
5431 nir_foreach_variable(variable, &nir->inputs)
5432 handle_vs_input_decl(ctx, variable);
5433 }
5434
5435 static void
5436 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5437 struct nir_shader *nir)
5438 {
5439 if (!ctx->options->key.fs.multisample)
5440 return;
5441
5442 bool uses_center = false;
5443 bool uses_centroid = false;
5444 nir_foreach_variable(variable, &nir->inputs) {
5445 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5446 variable->data.sample)
5447 continue;
5448
5449 if (variable->data.centroid)
5450 uses_centroid = true;
5451 else
5452 uses_center = true;
5453 }
5454
5455 if (uses_center && uses_centroid) {
5456 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5457 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5458 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5459 }
5460 }
5461
5462 static void
5463 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5464 struct nir_shader *nir)
5465 {
5466 prepare_interp_optimize(ctx, nir);
5467
5468 nir_foreach_variable(variable, &nir->inputs)
5469 handle_fs_input_decl(ctx, variable);
5470
5471 unsigned index = 0;
5472
5473 if (ctx->shader_info->info.ps.uses_input_attachments ||
5474 ctx->shader_info->info.needs_multiview_view_index)
5475 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5476
5477 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5478 LLVMValueRef interp_param;
5479 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5480
5481 if (!(ctx->input_mask & (1ull << i)))
5482 continue;
5483
5484 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5485 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5486 interp_param = *inputs;
5487 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5488 inputs);
5489
5490 if (!interp_param)
5491 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5492 ++index;
5493 } else if (i == VARYING_SLOT_POS) {
5494 for(int i = 0; i < 3; ++i)
5495 inputs[i] = ctx->abi.frag_pos[i];
5496
5497 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5498 ctx->abi.frag_pos[3]);
5499 }
5500 }
5501 ctx->shader_info->fs.num_interp = index;
5502 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5503 ctx->shader_info->fs.has_pcoord = true;
5504 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5505 ctx->shader_info->fs.prim_id_input = true;
5506 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5507 ctx->shader_info->fs.layer_input = true;
5508 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5509
5510 if (ctx->shader_info->info.needs_multiview_view_index)
5511 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5512 }
5513
5514 static LLVMValueRef
5515 ac_build_alloca(struct ac_llvm_context *ac,
5516 LLVMTypeRef type,
5517 const char *name)
5518 {
5519 LLVMBuilderRef builder = ac->builder;
5520 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5521 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5522 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5523 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5524 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5525 LLVMValueRef res;
5526
5527 if (first_instr) {
5528 LLVMPositionBuilderBefore(first_builder, first_instr);
5529 } else {
5530 LLVMPositionBuilderAtEnd(first_builder, first_block);
5531 }
5532
5533 res = LLVMBuildAlloca(first_builder, type, name);
5534 LLVMBuildStore(builder, LLVMConstNull(type), res);
5535
5536 LLVMDisposeBuilder(first_builder);
5537
5538 return res;
5539 }
5540
5541 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5542 LLVMTypeRef type,
5543 const char *name)
5544 {
5545 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5546 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5547 return ptr;
5548 }
5549
5550 static void
5551 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5552 struct nir_variable *variable,
5553 struct nir_shader *shader,
5554 gl_shader_stage stage)
5555 {
5556 int idx = variable->data.location + variable->data.index;
5557 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5558 uint64_t mask_attribs;
5559
5560 variable->data.driver_location = idx * 4;
5561
5562 /* tess ctrl has it's own load/store paths for outputs */
5563 if (stage == MESA_SHADER_TESS_CTRL)
5564 return;
5565
5566 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5567 if (stage == MESA_SHADER_VERTEX ||
5568 stage == MESA_SHADER_TESS_EVAL ||
5569 stage == MESA_SHADER_GEOMETRY) {
5570 if (idx == VARYING_SLOT_CLIP_DIST0) {
5571 int length = shader->info.clip_distance_array_size +
5572 shader->info.cull_distance_array_size;
5573 if (stage == MESA_SHADER_VERTEX) {
5574 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5575 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5576 }
5577 if (stage == MESA_SHADER_TESS_EVAL) {
5578 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5579 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5580 }
5581
5582 if (length > 4)
5583 attrib_count = 2;
5584 else
5585 attrib_count = 1;
5586 mask_attribs = 1ull << idx;
5587 }
5588 }
5589
5590 ctx->output_mask |= mask_attribs;
5591 }
5592
5593 static void
5594 handle_shader_output_decl(struct ac_nir_context *ctx,
5595 struct nir_shader *nir,
5596 struct nir_variable *variable)
5597 {
5598 unsigned output_loc = variable->data.driver_location / 4;
5599 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5600
5601 /* tess ctrl has it's own load/store paths for outputs */
5602 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5603 return;
5604
5605 if (ctx->stage == MESA_SHADER_VERTEX ||
5606 ctx->stage == MESA_SHADER_TESS_EVAL ||
5607 ctx->stage == MESA_SHADER_GEOMETRY) {
5608 int idx = variable->data.location + variable->data.index;
5609 if (idx == VARYING_SLOT_CLIP_DIST0) {
5610 int length = nir->info.clip_distance_array_size +
5611 nir->info.cull_distance_array_size;
5612
5613 if (length > 4)
5614 attrib_count = 2;
5615 else
5616 attrib_count = 1;
5617 }
5618 }
5619
5620 for (unsigned i = 0; i < attrib_count; ++i) {
5621 for (unsigned chan = 0; chan < 4; chan++) {
5622 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5623 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5624 }
5625 }
5626 }
5627
5628 static LLVMTypeRef
5629 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5630 enum glsl_base_type type)
5631 {
5632 switch (type) {
5633 case GLSL_TYPE_INT:
5634 case GLSL_TYPE_UINT:
5635 case GLSL_TYPE_BOOL:
5636 case GLSL_TYPE_SUBROUTINE:
5637 return ctx->ac.i32;
5638 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5639 return ctx->ac.f32;
5640 case GLSL_TYPE_INT64:
5641 case GLSL_TYPE_UINT64:
5642 return ctx->ac.i64;
5643 case GLSL_TYPE_DOUBLE:
5644 return ctx->ac.f64;
5645 default:
5646 unreachable("unknown GLSL type");
5647 }
5648 }
5649
5650 static LLVMTypeRef
5651 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5652 const struct glsl_type *type)
5653 {
5654 if (glsl_type_is_scalar(type)) {
5655 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5656 }
5657
5658 if (glsl_type_is_vector(type)) {
5659 return LLVMVectorType(
5660 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5661 glsl_get_vector_elements(type));
5662 }
5663
5664 if (glsl_type_is_matrix(type)) {
5665 return LLVMArrayType(
5666 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5667 glsl_get_matrix_columns(type));
5668 }
5669
5670 if (glsl_type_is_array(type)) {
5671 return LLVMArrayType(
5672 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5673 glsl_get_length(type));
5674 }
5675
5676 assert(glsl_type_is_struct(type));
5677
5678 LLVMTypeRef member_types[glsl_get_length(type)];
5679
5680 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5681 member_types[i] =
5682 glsl_to_llvm_type(ctx,
5683 glsl_get_struct_field(type, i));
5684 }
5685
5686 return LLVMStructTypeInContext(ctx->context, member_types,
5687 glsl_get_length(type), false);
5688 }
5689
5690 static void
5691 setup_locals(struct ac_nir_context *ctx,
5692 struct nir_function *func)
5693 {
5694 int i, j;
5695 ctx->num_locals = 0;
5696 nir_foreach_variable(variable, &func->impl->locals) {
5697 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5698 variable->data.driver_location = ctx->num_locals * 4;
5699 variable->data.location_frac = 0;
5700 ctx->num_locals += attrib_count;
5701 }
5702 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5703 if (!ctx->locals)
5704 return;
5705
5706 for (i = 0; i < ctx->num_locals; i++) {
5707 for (j = 0; j < 4; j++) {
5708 ctx->locals[i * 4 + j] =
5709 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5710 }
5711 }
5712 }
5713
5714 static void
5715 setup_shared(struct ac_nir_context *ctx,
5716 struct nir_shader *nir)
5717 {
5718 nir_foreach_variable(variable, &nir->shared) {
5719 LLVMValueRef shared =
5720 LLVMAddGlobalInAddressSpace(
5721 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5722 variable->name ? variable->name : "",
5723 AC_LOCAL_ADDR_SPACE);
5724 _mesa_hash_table_insert(ctx->vars, variable, shared);
5725 }
5726 }
5727
5728 /* Initialize arguments for the shader export intrinsic */
5729 static void
5730 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5731 LLVMValueRef *values,
5732 unsigned target,
5733 struct ac_export_args *args)
5734 {
5735 /* Default is 0xf. Adjusted below depending on the format. */
5736 args->enabled_channels = 0xf;
5737
5738 /* Specify whether the EXEC mask represents the valid mask */
5739 args->valid_mask = 0;
5740
5741 /* Specify whether this is the last export */
5742 args->done = 0;
5743
5744 /* Specify the target we are exporting */
5745 args->target = target;
5746
5747 args->compr = false;
5748 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5749 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5750 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5751 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5752
5753 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5754 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5755 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5756 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5757 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5758 unsigned chan;
5759
5760 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5761 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5762 unsigned bits, bool hi) = NULL;
5763
5764 switch(col_format) {
5765 case V_028714_SPI_SHADER_ZERO:
5766 args->enabled_channels = 0; /* writemask */
5767 args->target = V_008DFC_SQ_EXP_NULL;
5768 break;
5769
5770 case V_028714_SPI_SHADER_32_R:
5771 args->enabled_channels = 1;
5772 args->out[0] = values[0];
5773 break;
5774
5775 case V_028714_SPI_SHADER_32_GR:
5776 args->enabled_channels = 0x3;
5777 args->out[0] = values[0];
5778 args->out[1] = values[1];
5779 break;
5780
5781 case V_028714_SPI_SHADER_32_AR:
5782 args->enabled_channels = 0x9;
5783 args->out[0] = values[0];
5784 args->out[3] = values[3];
5785 break;
5786
5787 case V_028714_SPI_SHADER_FP16_ABGR:
5788 packf = ac_build_cvt_pkrtz_f16;
5789 break;
5790
5791 case V_028714_SPI_SHADER_UNORM16_ABGR:
5792 packf = ac_build_cvt_pknorm_u16;
5793 break;
5794
5795 case V_028714_SPI_SHADER_SNORM16_ABGR:
5796 packf = ac_build_cvt_pknorm_i16;
5797 break;
5798
5799 case V_028714_SPI_SHADER_UINT16_ABGR:
5800 packi = ac_build_cvt_pk_u16;
5801 break;
5802
5803 case V_028714_SPI_SHADER_SINT16_ABGR:
5804 packi = ac_build_cvt_pk_i16;
5805 break;
5806
5807 default:
5808 case V_028714_SPI_SHADER_32_ABGR:
5809 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5810 break;
5811 }
5812
5813 /* Pack f16 or norm_i16/u16. */
5814 if (packf) {
5815 for (chan = 0; chan < 2; chan++) {
5816 LLVMValueRef pack_args[2] = {
5817 values[2 * chan],
5818 values[2 * chan + 1]
5819 };
5820 LLVMValueRef packed;
5821
5822 packed = packf(&ctx->ac, pack_args);
5823 args->out[chan] = ac_to_float(&ctx->ac, packed);
5824 }
5825 args->compr = 1; /* COMPR flag */
5826 }
5827
5828 /* Pack i16/u16. */
5829 if (packi) {
5830 for (chan = 0; chan < 2; chan++) {
5831 LLVMValueRef pack_args[2] = {
5832 ac_to_integer(&ctx->ac, values[2 * chan]),
5833 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5834 };
5835 LLVMValueRef packed;
5836
5837 packed = packi(&ctx->ac, pack_args,
5838 is_int8 ? 8 : is_int10 ? 10 : 16,
5839 chan == 1);
5840 args->out[chan] = ac_to_float(&ctx->ac, packed);
5841 }
5842 args->compr = 1; /* COMPR flag */
5843 }
5844 return;
5845 }
5846
5847 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5848
5849 for (unsigned i = 0; i < 4; ++i)
5850 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5851 }
5852
5853 static void
5854 radv_export_param(struct nir_to_llvm_context *ctx, unsigned index,
5855 LLVMValueRef *values)
5856 {
5857 struct ac_export_args args;
5858
5859 si_llvm_init_export_args(ctx, values,
5860 V_008DFC_SQ_EXP_PARAM + index, &args);
5861 ac_build_export(&ctx->ac, &args);
5862 }
5863
5864 static LLVMValueRef
5865 radv_load_output(struct nir_to_llvm_context *ctx, unsigned index, unsigned chan)
5866 {
5867 LLVMValueRef output =
5868 ctx->nir->outputs[radeon_llvm_reg_index_soa(index, chan)];
5869
5870 return LLVMBuildLoad(ctx->builder, output, "");
5871 }
5872
5873 static void
5874 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5875 bool export_prim_id,
5876 struct ac_vs_output_info *outinfo)
5877 {
5878 uint32_t param_count = 0;
5879 unsigned target;
5880 unsigned pos_idx, num_pos_exports = 0;
5881 struct ac_export_args args, pos_args[4] = {};
5882 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5883 int i;
5884
5885 if (ctx->options->key.has_multiview_view_index) {
5886 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5887 if(!*tmp_out) {
5888 for(unsigned i = 0; i < 4; ++i)
5889 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5890 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5891 }
5892
5893 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5894 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5895 }
5896
5897 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5898 sizeof(outinfo->vs_output_param_offset));
5899
5900 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5901 LLVMValueRef slots[8];
5902 unsigned j;
5903
5904 if (outinfo->cull_dist_mask)
5905 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5906
5907 i = VARYING_SLOT_CLIP_DIST0;
5908 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5909 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
5910
5911 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5912 slots[i] = LLVMGetUndef(ctx->ac.f32);
5913
5914 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5915 target = V_008DFC_SQ_EXP_POS + 3;
5916 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5917 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5918 &args, sizeof(args));
5919 }
5920
5921 target = V_008DFC_SQ_EXP_POS + 2;
5922 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5923 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5924 &args, sizeof(args));
5925
5926 }
5927
5928 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5929 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5930 for (unsigned j = 0; j < 4; j++)
5931 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
5932 }
5933 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5934
5935 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5936 outinfo->writes_pointsize = true;
5937 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
5938 }
5939
5940 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5941 outinfo->writes_layer = true;
5942 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
5943 }
5944
5945 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5946 outinfo->writes_viewport_index = true;
5947 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
5948 }
5949
5950 if (outinfo->writes_pointsize ||
5951 outinfo->writes_layer ||
5952 outinfo->writes_viewport_index) {
5953 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5954 (outinfo->writes_layer == true ? 4 : 0));
5955 pos_args[1].valid_mask = 0;
5956 pos_args[1].done = 0;
5957 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5958 pos_args[1].compr = 0;
5959 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5960 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5961 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5962 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5963
5964 if (outinfo->writes_pointsize == true)
5965 pos_args[1].out[0] = psize_value;
5966 if (outinfo->writes_layer == true)
5967 pos_args[1].out[2] = layer_value;
5968 if (outinfo->writes_viewport_index == true) {
5969 if (ctx->options->chip_class >= GFX9) {
5970 /* GFX9 has the layer in out.z[10:0] and the viewport
5971 * index in out.z[19:16].
5972 */
5973 LLVMValueRef v = viewport_index_value;
5974 v = ac_to_integer(&ctx->ac, v);
5975 v = LLVMBuildShl(ctx->builder, v,
5976 LLVMConstInt(ctx->ac.i32, 16, false),
5977 "");
5978 v = LLVMBuildOr(ctx->builder, v,
5979 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5980
5981 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5982 pos_args[1].enabled_channels |= 1 << 2;
5983 } else {
5984 pos_args[1].out[3] = viewport_index_value;
5985 pos_args[1].enabled_channels |= 1 << 3;
5986 }
5987 }
5988 }
5989 for (i = 0; i < 4; i++) {
5990 if (pos_args[i].out[0])
5991 num_pos_exports++;
5992 }
5993
5994 pos_idx = 0;
5995 for (i = 0; i < 4; i++) {
5996 if (!pos_args[i].out[0])
5997 continue;
5998
5999 /* Specify the target we are exporting */
6000 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6001 if (pos_idx == num_pos_exports)
6002 pos_args[i].done = 1;
6003 ac_build_export(&ctx->ac, &pos_args[i]);
6004 }
6005
6006 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6007 LLVMValueRef values[4];
6008 if (!(ctx->output_mask & (1ull << i)))
6009 continue;
6010
6011 if (i != VARYING_SLOT_LAYER &&
6012 i != VARYING_SLOT_PRIMITIVE_ID &&
6013 i < VARYING_SLOT_VAR0)
6014 continue;
6015
6016 for (unsigned j = 0; j < 4; j++)
6017 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6018
6019 radv_export_param(ctx, param_count, values);
6020
6021 outinfo->vs_output_param_offset[i] = param_count++;
6022 }
6023
6024 if (export_prim_id) {
6025 LLVMValueRef values[4];
6026
6027 values[0] = ctx->vs_prim_id;
6028 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6029 ctx->shader_info->vs.vgpr_comp_cnt);
6030 for (unsigned j = 1; j < 4; j++)
6031 values[j] = ctx->ac.f32_0;
6032
6033 radv_export_param(ctx, param_count, values);
6034
6035 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6036 outinfo->export_prim_id = true;
6037 }
6038
6039 outinfo->pos_exports = num_pos_exports;
6040 outinfo->param_exports = param_count;
6041 }
6042
6043 static void
6044 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
6045 struct ac_es_output_info *outinfo)
6046 {
6047 int j;
6048 uint64_t max_output_written = 0;
6049 LLVMValueRef lds_base = NULL;
6050
6051 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6052 int param_index;
6053 int length = 4;
6054
6055 if (!(ctx->output_mask & (1ull << i)))
6056 continue;
6057
6058 if (i == VARYING_SLOT_CLIP_DIST0)
6059 length = ctx->num_output_clips + ctx->num_output_culls;
6060
6061 param_index = shader_io_get_unique_index(i);
6062
6063 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6064 }
6065
6066 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6067
6068 if (ctx->ac.chip_class >= GFX9) {
6069 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6070 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6071 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6072 LLVMConstInt(ctx->ac.i32, 24, false),
6073 LLVMConstInt(ctx->ac.i32, 4, false), false);
6074 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6075 LLVMBuildMul(ctx->ac.builder, wave_idx,
6076 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6077 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6078 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6079 }
6080
6081 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6082 LLVMValueRef dw_addr;
6083 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6084 int param_index;
6085 int length = 4;
6086
6087 if (!(ctx->output_mask & (1ull << i)))
6088 continue;
6089
6090 if (i == VARYING_SLOT_CLIP_DIST0)
6091 length = ctx->num_output_clips + ctx->num_output_culls;
6092
6093 param_index = shader_io_get_unique_index(i);
6094
6095 if (lds_base) {
6096 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6097 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6098 "");
6099 }
6100 for (j = 0; j < length; j++) {
6101 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6102 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6103
6104 if (ctx->ac.chip_class >= GFX9) {
6105 ac_lds_store(&ctx->ac, dw_addr,
6106 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6107 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6108 } else {
6109 ac_build_buffer_store_dword(&ctx->ac,
6110 ctx->esgs_ring,
6111 out_val, 1,
6112 NULL, ctx->es2gs_offset,
6113 (4 * param_index + j) * 4,
6114 1, 1, true, true);
6115 }
6116 }
6117 }
6118 }
6119
6120 static void
6121 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6122 {
6123 LLVMValueRef vertex_id = ctx->rel_auto_id;
6124 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6125 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6126 vertex_dw_stride, "");
6127
6128 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6129 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6130 int length = 4;
6131
6132 if (!(ctx->output_mask & (1ull << i)))
6133 continue;
6134
6135 if (i == VARYING_SLOT_CLIP_DIST0)
6136 length = ctx->num_output_clips + ctx->num_output_culls;
6137 int param = shader_io_get_unique_index(i);
6138 mark_tess_output(ctx, false, param);
6139 if (length > 4)
6140 mark_tess_output(ctx, false, param + 1);
6141 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6142 LLVMConstInt(ctx->ac.i32, param * 4, false),
6143 "");
6144 for (unsigned j = 0; j < length; j++) {
6145 ac_lds_store(&ctx->ac, dw_addr,
6146 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6147 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6148 }
6149 }
6150 }
6151
6152 struct ac_build_if_state
6153 {
6154 struct nir_to_llvm_context *ctx;
6155 LLVMValueRef condition;
6156 LLVMBasicBlockRef entry_block;
6157 LLVMBasicBlockRef true_block;
6158 LLVMBasicBlockRef false_block;
6159 LLVMBasicBlockRef merge_block;
6160 };
6161
6162 static LLVMBasicBlockRef
6163 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6164 {
6165 LLVMBasicBlockRef current_block;
6166 LLVMBasicBlockRef next_block;
6167 LLVMBasicBlockRef new_block;
6168
6169 /* get current basic block */
6170 current_block = LLVMGetInsertBlock(ctx->builder);
6171
6172 /* chqeck if there's another block after this one */
6173 next_block = LLVMGetNextBasicBlock(current_block);
6174 if (next_block) {
6175 /* insert the new block before the next block */
6176 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6177 }
6178 else {
6179 /* append new block after current block */
6180 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6181 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6182 }
6183 return new_block;
6184 }
6185
6186 static void
6187 ac_nir_build_if(struct ac_build_if_state *ifthen,
6188 struct nir_to_llvm_context *ctx,
6189 LLVMValueRef condition)
6190 {
6191 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6192
6193 memset(ifthen, 0, sizeof *ifthen);
6194 ifthen->ctx = ctx;
6195 ifthen->condition = condition;
6196 ifthen->entry_block = block;
6197
6198 /* create endif/merge basic block for the phi functions */
6199 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6200
6201 /* create/insert true_block before merge_block */
6202 ifthen->true_block =
6203 LLVMInsertBasicBlockInContext(ctx->context,
6204 ifthen->merge_block,
6205 "if-true-block");
6206
6207 /* successive code goes into the true block */
6208 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6209 }
6210
6211 /**
6212 * End a conditional.
6213 */
6214 static void
6215 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6216 {
6217 LLVMBuilderRef builder = ifthen->ctx->builder;
6218
6219 /* Insert branch to the merge block from current block */
6220 LLVMBuildBr(builder, ifthen->merge_block);
6221
6222 /*
6223 * Now patch in the various branch instructions.
6224 */
6225
6226 /* Insert the conditional branch instruction at the end of entry_block */
6227 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6228 if (ifthen->false_block) {
6229 /* we have an else clause */
6230 LLVMBuildCondBr(builder, ifthen->condition,
6231 ifthen->true_block, ifthen->false_block);
6232 }
6233 else {
6234 /* no else clause */
6235 LLVMBuildCondBr(builder, ifthen->condition,
6236 ifthen->true_block, ifthen->merge_block);
6237 }
6238
6239 /* Resume building code at end of the ifthen->merge_block */
6240 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6241 }
6242
6243 static void
6244 write_tess_factors(struct nir_to_llvm_context *ctx)
6245 {
6246 unsigned stride, outer_comps, inner_comps;
6247 struct ac_build_if_state if_ctx, inner_if_ctx;
6248 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6249 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6250 unsigned tess_inner_index, tess_outer_index;
6251 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6252 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6253 int i;
6254 emit_barrier(&ctx->ac, ctx->stage);
6255
6256 switch (ctx->options->key.tcs.primitive_mode) {
6257 case GL_ISOLINES:
6258 stride = 2;
6259 outer_comps = 2;
6260 inner_comps = 0;
6261 break;
6262 case GL_TRIANGLES:
6263 stride = 4;
6264 outer_comps = 3;
6265 inner_comps = 1;
6266 break;
6267 case GL_QUADS:
6268 stride = 6;
6269 outer_comps = 4;
6270 inner_comps = 2;
6271 break;
6272 default:
6273 return;
6274 }
6275
6276 ac_nir_build_if(&if_ctx, ctx,
6277 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6278 invocation_id, ctx->ac.i32_0, ""));
6279
6280 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6281 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6282
6283 mark_tess_output(ctx, true, tess_inner_index);
6284 mark_tess_output(ctx, true, tess_outer_index);
6285 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6286 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6287 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6288 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6289 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6290
6291 for (i = 0; i < 4; i++) {
6292 inner[i] = LLVMGetUndef(ctx->ac.i32);
6293 outer[i] = LLVMGetUndef(ctx->ac.i32);
6294 }
6295
6296 // LINES reverseal
6297 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6298 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6299 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6300 ctx->ac.i32_1, "");
6301 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6302 } else {
6303 for (i = 0; i < outer_comps; i++) {
6304 outer[i] = out[i] =
6305 ac_lds_load(&ctx->ac, lds_outer);
6306 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6307 ctx->ac.i32_1, "");
6308 }
6309 for (i = 0; i < inner_comps; i++) {
6310 inner[i] = out[outer_comps+i] =
6311 ac_lds_load(&ctx->ac, lds_inner);
6312 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6313 ctx->ac.i32_1, "");
6314 }
6315 }
6316
6317 /* Convert the outputs to vectors for stores. */
6318 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6319 vec1 = NULL;
6320
6321 if (stride > 4)
6322 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6323
6324
6325 buffer = ctx->hs_ring_tess_factor;
6326 tf_base = ctx->tess_factor_offset;
6327 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6328 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6329 unsigned tf_offset = 0;
6330
6331 if (ctx->options->chip_class <= VI) {
6332 ac_nir_build_if(&inner_if_ctx, ctx,
6333 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6334 rel_patch_id, ctx->ac.i32_0, ""));
6335
6336 /* Store the dynamic HS control word. */
6337 ac_build_buffer_store_dword(&ctx->ac, buffer,
6338 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6339 1, ctx->ac.i32_0, tf_base,
6340 0, 1, 0, true, false);
6341 tf_offset += 4;
6342
6343 ac_nir_build_endif(&inner_if_ctx);
6344 }
6345
6346 /* Store the tessellation factors. */
6347 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6348 MIN2(stride, 4), byteoffset, tf_base,
6349 tf_offset, 1, 0, true, false);
6350 if (vec1)
6351 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6352 stride - 4, byteoffset, tf_base,
6353 16 + tf_offset, 1, 0, true, false);
6354
6355 //store to offchip for TES to read - only if TES reads them
6356 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6357 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6358 LLVMValueRef tf_inner_offset;
6359 unsigned param_outer, param_inner;
6360
6361 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6362 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6363 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6364
6365 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6366 util_next_power_of_two(outer_comps));
6367
6368 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6369 outer_comps, tf_outer_offset,
6370 ctx->oc_lds, 0, 1, 0, true, false);
6371 if (inner_comps) {
6372 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6373 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6374 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6375
6376 inner_vec = inner_comps == 1 ? inner[0] :
6377 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6378 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6379 inner_comps, tf_inner_offset,
6380 ctx->oc_lds, 0, 1, 0, true, false);
6381 }
6382 }
6383 ac_nir_build_endif(&if_ctx);
6384 }
6385
6386 static void
6387 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6388 {
6389 write_tess_factors(ctx);
6390 }
6391
6392 static bool
6393 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6394 LLVMValueRef *color, unsigned index, bool is_last,
6395 struct ac_export_args *args)
6396 {
6397 /* Export */
6398 si_llvm_init_export_args(ctx, color,
6399 V_008DFC_SQ_EXP_MRT + index, args);
6400
6401 if (is_last) {
6402 args->valid_mask = 1; /* whether the EXEC mask is valid */
6403 args->done = 1; /* DONE bit */
6404 } else if (!args->enabled_channels)
6405 return false; /* unnecessary NULL export */
6406
6407 return true;
6408 }
6409
6410 static void
6411 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6412 LLVMValueRef depth, LLVMValueRef stencil,
6413 LLVMValueRef samplemask)
6414 {
6415 struct ac_export_args args;
6416
6417 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6418
6419 ac_build_export(&ctx->ac, &args);
6420 }
6421
6422 static void
6423 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6424 {
6425 unsigned index = 0;
6426 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6427 struct ac_export_args color_args[8];
6428
6429 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6430 LLVMValueRef values[4];
6431 bool last = false;
6432
6433 if (!(ctx->output_mask & (1ull << i)))
6434 continue;
6435
6436 if (i < FRAG_RESULT_DATA0)
6437 continue;
6438
6439 for (unsigned j = 0; j < 4; j++)
6440 values[j] = ac_to_float(&ctx->ac,
6441 radv_load_output(ctx, i, j));
6442
6443 if (!ctx->shader_info->info.ps.writes_z &&
6444 !ctx->shader_info->info.ps.writes_stencil &&
6445 !ctx->shader_info->info.ps.writes_sample_mask)
6446 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6447
6448 bool ret = si_export_mrt_color(ctx, values,
6449 i - FRAG_RESULT_DATA0,
6450 last, &color_args[index]);
6451 if (ret)
6452 index++;
6453 }
6454
6455 /* Process depth, stencil, samplemask. */
6456 if (ctx->shader_info->info.ps.writes_z) {
6457 depth = ac_to_float(&ctx->ac,
6458 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6459 }
6460 if (ctx->shader_info->info.ps.writes_stencil) {
6461 stencil = ac_to_float(&ctx->ac,
6462 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6463 }
6464 if (ctx->shader_info->info.ps.writes_sample_mask) {
6465 samplemask = ac_to_float(&ctx->ac,
6466 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6467 }
6468
6469 /* Export PS outputs. */
6470 for (unsigned i = 0; i < index; i++)
6471 ac_build_export(&ctx->ac, &color_args[i]);
6472
6473 if (depth || stencil || samplemask)
6474 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6475 else if (!index)
6476 ac_build_export_null(&ctx->ac);
6477 }
6478
6479 static void
6480 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6481 {
6482 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6483 }
6484
6485 static void
6486 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6487 LLVMValueRef *addrs)
6488 {
6489 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6490
6491 switch (ctx->stage) {
6492 case MESA_SHADER_VERTEX:
6493 if (ctx->options->key.vs.as_ls)
6494 handle_ls_outputs_post(ctx);
6495 else if (ctx->options->key.vs.as_es)
6496 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6497 else
6498 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6499 &ctx->shader_info->vs.outinfo);
6500 break;
6501 case MESA_SHADER_FRAGMENT:
6502 handle_fs_outputs_post(ctx);
6503 break;
6504 case MESA_SHADER_GEOMETRY:
6505 emit_gs_epilogue(ctx);
6506 break;
6507 case MESA_SHADER_TESS_CTRL:
6508 handle_tcs_outputs_post(ctx);
6509 break;
6510 case MESA_SHADER_TESS_EVAL:
6511 if (ctx->options->key.tes.as_es)
6512 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6513 else
6514 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6515 &ctx->shader_info->tes.outinfo);
6516 break;
6517 default:
6518 break;
6519 }
6520 }
6521
6522 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6523 {
6524 LLVMPassManagerRef passmgr;
6525 /* Create the pass manager */
6526 passmgr = LLVMCreateFunctionPassManagerForModule(
6527 ctx->module);
6528
6529 /* This pass should eliminate all the load and store instructions */
6530 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6531
6532 /* Add some optimization passes */
6533 LLVMAddScalarReplAggregatesPass(passmgr);
6534 LLVMAddLICMPass(passmgr);
6535 LLVMAddAggressiveDCEPass(passmgr);
6536 LLVMAddCFGSimplificationPass(passmgr);
6537 LLVMAddInstructionCombiningPass(passmgr);
6538
6539 /* Run the pass */
6540 LLVMInitializeFunctionPassManager(passmgr);
6541 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6542 LLVMFinalizeFunctionPassManager(passmgr);
6543
6544 LLVMDisposeBuilder(ctx->builder);
6545 LLVMDisposePassManager(passmgr);
6546 }
6547
6548 static void
6549 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6550 {
6551 struct ac_vs_output_info *outinfo;
6552
6553 switch (ctx->stage) {
6554 case MESA_SHADER_FRAGMENT:
6555 case MESA_SHADER_COMPUTE:
6556 case MESA_SHADER_TESS_CTRL:
6557 case MESA_SHADER_GEOMETRY:
6558 return;
6559 case MESA_SHADER_VERTEX:
6560 if (ctx->options->key.vs.as_ls ||
6561 ctx->options->key.vs.as_es)
6562 return;
6563 outinfo = &ctx->shader_info->vs.outinfo;
6564 break;
6565 case MESA_SHADER_TESS_EVAL:
6566 if (ctx->options->key.vs.as_es)
6567 return;
6568 outinfo = &ctx->shader_info->tes.outinfo;
6569 break;
6570 default:
6571 unreachable("Unhandled shader type");
6572 }
6573
6574 ac_optimize_vs_outputs(&ctx->ac,
6575 ctx->main_function,
6576 outinfo->vs_output_param_offset,
6577 VARYING_SLOT_MAX,
6578 &outinfo->param_exports);
6579 }
6580
6581 static void
6582 ac_setup_rings(struct nir_to_llvm_context *ctx)
6583 {
6584 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6585 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6586 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6587 }
6588
6589 if (ctx->is_gs_copy_shader) {
6590 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6591 }
6592 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6593 LLVMValueRef tmp;
6594 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6595 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6596
6597 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6598
6599 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6600 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6601 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6602 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6603 }
6604
6605 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6606 ctx->stage == MESA_SHADER_TESS_EVAL) {
6607 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6608 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6609 }
6610 }
6611
6612 static unsigned
6613 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6614 const struct nir_shader *nir)
6615 {
6616 switch (nir->info.stage) {
6617 case MESA_SHADER_TESS_CTRL:
6618 return chip_class >= CIK ? 128 : 64;
6619 case MESA_SHADER_GEOMETRY:
6620 return chip_class >= GFX9 ? 128 : 64;
6621 case MESA_SHADER_COMPUTE:
6622 break;
6623 default:
6624 return 0;
6625 }
6626
6627 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6628 nir->info.cs.local_size[1] *
6629 nir->info.cs.local_size[2];
6630 return max_workgroup_size;
6631 }
6632
6633 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6634 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6635 {
6636 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6637 LLVMConstInt(ctx->ac.i32, 8, false),
6638 LLVMConstInt(ctx->ac.i32, 8, false), false);
6639 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6640 ctx->ac.i32_0, "");
6641 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6642 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6643 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6644 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6645 }
6646
6647 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6648 {
6649 for(int i = 5; i >= 0; --i) {
6650 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6651 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6652 LLVMConstInt(ctx->ac.i32, 16, false), false);
6653 }
6654
6655 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6656 LLVMConstInt(ctx->ac.i32, 16, false),
6657 LLVMConstInt(ctx->ac.i32, 8, false), false);
6658 }
6659
6660 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6661 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6662 {
6663 struct ac_nir_context ctx = {};
6664 struct nir_function *func;
6665
6666 ctx.ac = *ac;
6667 ctx.abi = abi;
6668
6669 ctx.nctx = nctx;
6670 if (nctx)
6671 nctx->nir = &ctx;
6672
6673 ctx.stage = nir->info.stage;
6674
6675 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6676
6677 nir_foreach_variable(variable, &nir->outputs)
6678 handle_shader_output_decl(&ctx, nir, variable);
6679
6680 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6681 _mesa_key_pointer_equal);
6682 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6683 _mesa_key_pointer_equal);
6684 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6685 _mesa_key_pointer_equal);
6686
6687 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6688
6689 setup_locals(&ctx, func);
6690
6691 if (nir->info.stage == MESA_SHADER_COMPUTE)
6692 setup_shared(&ctx, nir);
6693
6694 visit_cf_list(&ctx, &func->impl->body);
6695 phi_post_pass(&ctx);
6696
6697 if (nir->info.stage != MESA_SHADER_COMPUTE)
6698 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6699 ctx.outputs);
6700
6701 free(ctx.locals);
6702 ralloc_free(ctx.defs);
6703 ralloc_free(ctx.phis);
6704 ralloc_free(ctx.vars);
6705
6706 if (nctx)
6707 nctx->nir = NULL;
6708 }
6709
6710 static
6711 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6712 struct nir_shader *const *shaders,
6713 int shader_count,
6714 struct ac_shader_variant_info *shader_info,
6715 const struct ac_nir_compiler_options *options)
6716 {
6717 struct nir_to_llvm_context ctx = {0};
6718 unsigned i;
6719 ctx.options = options;
6720 ctx.shader_info = shader_info;
6721 ctx.context = LLVMContextCreate();
6722 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6723
6724 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6725 options->family);
6726 ctx.ac.module = ctx.module;
6727 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6728
6729 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6730 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6731 LLVMSetDataLayout(ctx.module, data_layout_str);
6732 LLVMDisposeTargetData(data_layout);
6733 LLVMDisposeMessage(data_layout_str);
6734
6735 enum ac_float_mode float_mode =
6736 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6737 AC_FLOAT_MODE_DEFAULT;
6738
6739 ctx.builder = ac_create_builder(ctx.context, float_mode);
6740 ctx.ac.builder = ctx.builder;
6741
6742 memset(shader_info, 0, sizeof(*shader_info));
6743
6744 for(int i = 0; i < shader_count; ++i)
6745 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6746
6747 for (i = 0; i < AC_UD_MAX_SETS; i++)
6748 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6749 for (i = 0; i < AC_UD_MAX_UD; i++)
6750 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6751
6752 ctx.max_workgroup_size = 0;
6753 for (int i = 0; i < shader_count; ++i) {
6754 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6755 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6756 shaders[i]));
6757 }
6758
6759 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6760 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6761
6762 ctx.abi.inputs = &ctx.inputs[0];
6763 ctx.abi.emit_outputs = handle_shader_outputs_post;
6764 ctx.abi.emit_vertex = visit_emit_vertex;
6765 ctx.abi.load_ubo = radv_load_ubo;
6766 ctx.abi.load_ssbo = radv_load_ssbo;
6767 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6768 ctx.abi.clamp_shadow_reference = false;
6769
6770 if (shader_count >= 2)
6771 ac_init_exec_full_mask(&ctx.ac);
6772
6773 if (ctx.ac.chip_class == GFX9 &&
6774 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6775 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6776
6777 for(int i = 0; i < shader_count; ++i) {
6778 ctx.stage = shaders[i]->info.stage;
6779 ctx.output_mask = 0;
6780 ctx.tess_outputs_written = 0;
6781 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6782 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6783
6784 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6785 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6786 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6787 ctx.abi.load_inputs = load_gs_input;
6788 ctx.abi.emit_primitive = visit_end_primitive;
6789 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6790 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6791 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6792 ctx.abi.load_tess_varyings = load_tcs_varyings;
6793 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6794 ctx.abi.store_tcs_outputs = store_tcs_output;
6795 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6796 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6797 ctx.abi.load_tess_varyings = load_tes_input;
6798 ctx.abi.load_tess_coord = load_tess_coord;
6799 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6800 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6801 if (shader_info->info.vs.needs_instance_id) {
6802 if (ctx.options->key.vs.as_ls) {
6803 ctx.shader_info->vs.vgpr_comp_cnt =
6804 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6805 } else {
6806 ctx.shader_info->vs.vgpr_comp_cnt =
6807 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6808 }
6809 }
6810 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6811 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6812 ctx.abi.lookup_interp_param = lookup_interp_param;
6813 ctx.abi.load_sample_position = load_sample_position;
6814 }
6815
6816 if (i)
6817 emit_barrier(&ctx.ac, ctx.stage);
6818
6819 ac_setup_rings(&ctx);
6820
6821 LLVMBasicBlockRef merge_block;
6822 if (shader_count >= 2) {
6823 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6824 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6825 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6826
6827 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6828 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6829 LLVMConstInt(ctx.ac.i32, 8, false), false);
6830 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6831 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6832 thread_id, count, "");
6833 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6834
6835 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6836 }
6837
6838 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6839 handle_fs_inputs(&ctx, shaders[i]);
6840 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6841 handle_vs_inputs(&ctx, shaders[i]);
6842 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6843 prepare_gs_input_vgprs(&ctx);
6844
6845 nir_foreach_variable(variable, &shaders[i]->outputs)
6846 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6847
6848 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6849
6850 if (shader_count >= 2) {
6851 LLVMBuildBr(ctx.ac.builder, merge_block);
6852 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6853 }
6854
6855 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6856 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6857 shaders[i]->info.cull_distance_array_size > 4;
6858 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6859 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6860 shaders[i]->info.gs.vertices_out;
6861 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6862 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6863 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6864 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6865 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6866 }
6867 }
6868
6869 LLVMBuildRetVoid(ctx.builder);
6870
6871 if (options->dump_preoptir)
6872 ac_dump_module(ctx.module);
6873
6874 ac_llvm_finalize_module(&ctx);
6875
6876 if (shader_count == 1)
6877 ac_nir_eliminate_const_vs_outputs(&ctx);
6878
6879 return ctx.module;
6880 }
6881
6882 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6883 {
6884 unsigned *retval = (unsigned *)context;
6885 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6886 char *description = LLVMGetDiagInfoDescription(di);
6887
6888 if (severity == LLVMDSError) {
6889 *retval = 1;
6890 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6891 description);
6892 }
6893
6894 LLVMDisposeMessage(description);
6895 }
6896
6897 static unsigned ac_llvm_compile(LLVMModuleRef M,
6898 struct ac_shader_binary *binary,
6899 LLVMTargetMachineRef tm)
6900 {
6901 unsigned retval = 0;
6902 char *err;
6903 LLVMContextRef llvm_ctx;
6904 LLVMMemoryBufferRef out_buffer;
6905 unsigned buffer_size;
6906 const char *buffer_data;
6907 LLVMBool mem_err;
6908
6909 /* Setup Diagnostic Handler*/
6910 llvm_ctx = LLVMGetModuleContext(M);
6911
6912 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6913 &retval);
6914
6915 /* Compile IR*/
6916 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6917 &err, &out_buffer);
6918
6919 /* Process Errors/Warnings */
6920 if (mem_err) {
6921 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6922 free(err);
6923 retval = 1;
6924 goto out;
6925 }
6926
6927 /* Extract Shader Code*/
6928 buffer_size = LLVMGetBufferSize(out_buffer);
6929 buffer_data = LLVMGetBufferStart(out_buffer);
6930
6931 ac_elf_read(buffer_data, buffer_size, binary);
6932
6933 /* Clean up */
6934 LLVMDisposeMemoryBuffer(out_buffer);
6935
6936 out:
6937 return retval;
6938 }
6939
6940 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6941 LLVMModuleRef llvm_module,
6942 struct ac_shader_binary *binary,
6943 struct ac_shader_config *config,
6944 struct ac_shader_variant_info *shader_info,
6945 gl_shader_stage stage,
6946 bool dump_shader, bool supports_spill)
6947 {
6948 if (dump_shader)
6949 ac_dump_module(llvm_module);
6950
6951 memset(binary, 0, sizeof(*binary));
6952 int v = ac_llvm_compile(llvm_module, binary, tm);
6953 if (v) {
6954 fprintf(stderr, "compile failed\n");
6955 }
6956
6957 if (dump_shader)
6958 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6959
6960 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6961
6962 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6963 LLVMDisposeModule(llvm_module);
6964 LLVMContextDispose(ctx);
6965
6966 if (stage == MESA_SHADER_FRAGMENT) {
6967 shader_info->num_input_vgprs = 0;
6968 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6969 shader_info->num_input_vgprs += 2;
6970 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6971 shader_info->num_input_vgprs += 2;
6972 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6973 shader_info->num_input_vgprs += 2;
6974 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6975 shader_info->num_input_vgprs += 3;
6976 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6977 shader_info->num_input_vgprs += 2;
6978 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6979 shader_info->num_input_vgprs += 2;
6980 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6981 shader_info->num_input_vgprs += 2;
6982 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6983 shader_info->num_input_vgprs += 1;
6984 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6985 shader_info->num_input_vgprs += 1;
6986 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6987 shader_info->num_input_vgprs += 1;
6988 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6989 shader_info->num_input_vgprs += 1;
6990 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6991 shader_info->num_input_vgprs += 1;
6992 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6993 shader_info->num_input_vgprs += 1;
6994 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6995 shader_info->num_input_vgprs += 1;
6996 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6997 shader_info->num_input_vgprs += 1;
6998 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6999 shader_info->num_input_vgprs += 1;
7000 }
7001 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7002
7003 /* +3 for scratch wave offset and VCC */
7004 config->num_sgprs = MAX2(config->num_sgprs,
7005 shader_info->num_input_sgprs + 3);
7006
7007 /* Enable 64-bit and 16-bit denormals, because there is no performance
7008 * cost.
7009 *
7010 * If denormals are enabled, all floating-point output modifiers are
7011 * ignored.
7012 *
7013 * Don't enable denormals for 32-bit floats, because:
7014 * - Floating-point output modifiers would be ignored by the hw.
7015 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7016 * have to stop using those.
7017 * - SI & CI would be very slow.
7018 */
7019 config->float_mode |= V_00B028_FP_64_DENORMS;
7020 }
7021
7022 static void
7023 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7024 {
7025 switch (nir->info.stage) {
7026 case MESA_SHADER_COMPUTE:
7027 for (int i = 0; i < 3; ++i)
7028 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7029 break;
7030 case MESA_SHADER_FRAGMENT:
7031 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7032 break;
7033 case MESA_SHADER_GEOMETRY:
7034 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7035 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7036 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7037 shader_info->gs.invocations = nir->info.gs.invocations;
7038 break;
7039 case MESA_SHADER_TESS_EVAL:
7040 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7041 shader_info->tes.spacing = nir->info.tess.spacing;
7042 shader_info->tes.ccw = nir->info.tess.ccw;
7043 shader_info->tes.point_mode = nir->info.tess.point_mode;
7044 shader_info->tes.as_es = options->key.tes.as_es;
7045 break;
7046 case MESA_SHADER_TESS_CTRL:
7047 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7048 break;
7049 case MESA_SHADER_VERTEX:
7050 shader_info->vs.as_es = options->key.vs.as_es;
7051 shader_info->vs.as_ls = options->key.vs.as_ls;
7052 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7053 if (options->key.vs.as_ls)
7054 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7055 break;
7056 default:
7057 break;
7058 }
7059 }
7060
7061 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7062 struct ac_shader_binary *binary,
7063 struct ac_shader_config *config,
7064 struct ac_shader_variant_info *shader_info,
7065 struct nir_shader *const *nir,
7066 int nir_count,
7067 const struct ac_nir_compiler_options *options,
7068 bool dump_shader)
7069 {
7070
7071 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7072 options);
7073
7074 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7075 for (int i = 0; i < nir_count; ++i)
7076 ac_fill_shader_info(shader_info, nir[i], options);
7077
7078 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7079 if (options->chip_class == GFX9) {
7080 if (nir_count == 2 &&
7081 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7082 shader_info->gs.es_type = nir[0]->info.stage;
7083 }
7084 }
7085 }
7086
7087 static void
7088 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
7089 {
7090 LLVMValueRef vtx_offset =
7091 LLVMBuildMul(ctx->builder, ctx->abi.vertex_id,
7092 LLVMConstInt(ctx->ac.i32, 4, false), "");
7093 int idx = 0;
7094
7095 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7096 int length = 4;
7097 int slot = idx;
7098 int slot_inc = 1;
7099 if (!(ctx->output_mask & (1ull << i)))
7100 continue;
7101
7102 if (i == VARYING_SLOT_CLIP_DIST0) {
7103 /* unpack clip and cull from a single set of slots */
7104 length = ctx->num_output_clips + ctx->num_output_culls;
7105 if (length > 4)
7106 slot_inc = 2;
7107 }
7108
7109 for (unsigned j = 0; j < length; j++) {
7110 LLVMValueRef value, soffset;
7111
7112 soffset = LLVMConstInt(ctx->ac.i32,
7113 (slot * 4 + j) *
7114 ctx->gs_max_out_vertices * 16 * 4, false);
7115
7116 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7117 1, ctx->ac.i32_0,
7118 vtx_offset, soffset,
7119 0, 1, 1, true, false);
7120
7121 LLVMBuildStore(ctx->builder,
7122 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7123 }
7124 idx += slot_inc;
7125 }
7126 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7127 }
7128
7129 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7130 struct nir_shader *geom_shader,
7131 struct ac_shader_binary *binary,
7132 struct ac_shader_config *config,
7133 struct ac_shader_variant_info *shader_info,
7134 const struct ac_nir_compiler_options *options,
7135 bool dump_shader)
7136 {
7137 struct nir_to_llvm_context ctx = {0};
7138 ctx.context = LLVMContextCreate();
7139 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7140 ctx.options = options;
7141 ctx.shader_info = shader_info;
7142
7143 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7144 options->family);
7145 ctx.ac.module = ctx.module;
7146
7147 ctx.is_gs_copy_shader = true;
7148 LLVMSetTarget(ctx.module, "amdgcn--");
7149
7150 enum ac_float_mode float_mode =
7151 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7152 AC_FLOAT_MODE_DEFAULT;
7153
7154 ctx.builder = ac_create_builder(ctx.context, float_mode);
7155 ctx.ac.builder = ctx.builder;
7156 ctx.stage = MESA_SHADER_VERTEX;
7157
7158 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7159
7160 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7161 ac_setup_rings(&ctx);
7162
7163 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7164 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7165
7166 struct ac_nir_context nir_ctx = {};
7167 nir_ctx.ac = ctx.ac;
7168 nir_ctx.abi = &ctx.abi;
7169
7170 nir_ctx.nctx = &ctx;
7171 ctx.nir = &nir_ctx;
7172
7173 nir_foreach_variable(variable, &geom_shader->outputs) {
7174 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7175 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7176 }
7177
7178 ac_gs_copy_shader_emit(&ctx);
7179
7180 ctx.nir = NULL;
7181
7182 LLVMBuildRetVoid(ctx.builder);
7183
7184 ac_llvm_finalize_module(&ctx);
7185
7186 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7187 MESA_SHADER_VERTEX,
7188 dump_shader, options->supports_spill);
7189 }