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radv: drop debugging leftovers code in descriptor set patches.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_info.h"
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83 LLVMValueRef ls_out_layout;
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef tcs_offchip_layout;
87 LLVMValueRef tcs_out_offsets;
88 LLVMValueRef tcs_out_layout;
89 LLVMValueRef tcs_in_layout;
90 LLVMValueRef oc_lds;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tcs_patch_id;
93 LLVMValueRef tcs_rel_ids;
94 LLVMValueRef tes_rel_patch_id;
95 LLVMValueRef tes_patch_id;
96 LLVMValueRef tes_u;
97 LLVMValueRef tes_v;
98
99 LLVMValueRef gsvs_ring_stride;
100 LLVMValueRef gsvs_num_entries;
101 LLVMValueRef gs2vs_offset;
102 LLVMValueRef gs_wave_id;
103 LLVMValueRef gs_vtx_offset[6];
104 LLVMValueRef gs_prim_id, gs_invocation_id;
105
106 LLVMValueRef esgs_ring;
107 LLVMValueRef gsvs_ring;
108 LLVMValueRef hs_ring_tess_offchip;
109 LLVMValueRef hs_ring_tess_factor;
110
111 LLVMValueRef prim_mask;
112 LLVMValueRef sample_pos_offset;
113 LLVMValueRef persp_sample, persp_center, persp_centroid;
114 LLVMValueRef linear_sample, linear_center, linear_centroid;
115 LLVMValueRef front_face;
116 LLVMValueRef ancillary;
117 LLVMValueRef sample_coverage;
118 LLVMValueRef frag_pos[4];
119
120 LLVMBasicBlockRef continue_block;
121 LLVMBasicBlockRef break_block;
122
123 LLVMTypeRef i1;
124 LLVMTypeRef i8;
125 LLVMTypeRef i16;
126 LLVMTypeRef i32;
127 LLVMTypeRef i64;
128 LLVMTypeRef v2i32;
129 LLVMTypeRef v3i32;
130 LLVMTypeRef v4i32;
131 LLVMTypeRef v8i32;
132 LLVMTypeRef f64;
133 LLVMTypeRef f32;
134 LLVMTypeRef f16;
135 LLVMTypeRef v2f32;
136 LLVMTypeRef v4f32;
137 LLVMTypeRef v16i8;
138 LLVMTypeRef voidt;
139
140 LLVMValueRef i1true;
141 LLVMValueRef i1false;
142 LLVMValueRef i32zero;
143 LLVMValueRef i32one;
144 LLVMValueRef f32zero;
145 LLVMValueRef f32one;
146 LLVMValueRef v4f32empty;
147
148 unsigned uniform_md_kind;
149 LLVMValueRef empty_md;
150 gl_shader_stage stage;
151
152 LLVMValueRef lds;
153 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
154 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
155
156 LLVMValueRef shared_memory;
157 uint64_t input_mask;
158 uint64_t output_mask;
159 int num_locals;
160 LLVMValueRef *locals;
161 bool has_ddxy;
162 uint8_t num_output_clips;
163 uint8_t num_output_culls;
164
165 bool has_ds_bpermute;
166
167 bool is_gs_copy_shader;
168 LLVMValueRef gs_next_vertex;
169 unsigned gs_max_out_vertices;
170
171 unsigned tes_primitive_mode;
172 uint64_t tess_outputs_written;
173 uint64_t tess_patch_outputs_written;
174 };
175
176 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
177 nir_deref_var *deref,
178 enum desc_type desc_type);
179 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
180 {
181 return (index * 4) + chan;
182 }
183
184 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
185 {
186 /* handle patch indices separate */
187 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
188 return 0;
189 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
190 return 1;
191 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
192 return 2 + (slot - VARYING_SLOT_PATCH0);
193
194 if (slot == VARYING_SLOT_POS)
195 return 0;
196 if (slot == VARYING_SLOT_PSIZ)
197 return 1;
198 if (slot == VARYING_SLOT_CLIP_DIST0)
199 return 2;
200 /* 3 is reserved for clip dist as well */
201 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
202 return 4 + (slot - VARYING_SLOT_VAR0);
203 unreachable("illegal slot in get unique index\n");
204 }
205
206 static unsigned llvm_get_type_size(LLVMTypeRef type)
207 {
208 LLVMTypeKind kind = LLVMGetTypeKind(type);
209
210 switch (kind) {
211 case LLVMIntegerTypeKind:
212 return LLVMGetIntTypeWidth(type) / 8;
213 case LLVMFloatTypeKind:
214 return 4;
215 case LLVMPointerTypeKind:
216 return 8;
217 case LLVMVectorTypeKind:
218 return LLVMGetVectorSize(type) *
219 llvm_get_type_size(LLVMGetElementType(type));
220 default:
221 assert(0);
222 return 0;
223 }
224 }
225
226 static void set_llvm_calling_convention(LLVMValueRef func,
227 gl_shader_stage stage)
228 {
229 enum radeon_llvm_calling_convention calling_conv;
230
231 switch (stage) {
232 case MESA_SHADER_VERTEX:
233 case MESA_SHADER_TESS_CTRL:
234 case MESA_SHADER_TESS_EVAL:
235 calling_conv = RADEON_LLVM_AMDGPU_VS;
236 break;
237 case MESA_SHADER_GEOMETRY:
238 calling_conv = RADEON_LLVM_AMDGPU_GS;
239 break;
240 case MESA_SHADER_FRAGMENT:
241 calling_conv = RADEON_LLVM_AMDGPU_PS;
242 break;
243 case MESA_SHADER_COMPUTE:
244 calling_conv = RADEON_LLVM_AMDGPU_CS;
245 break;
246 default:
247 unreachable("Unhandle shader type");
248 }
249
250 LLVMSetFunctionCallConv(func, calling_conv);
251 }
252
253 static LLVMValueRef
254 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
255 LLVMBuilderRef builder, LLVMTypeRef *return_types,
256 unsigned num_return_elems, LLVMTypeRef *param_types,
257 unsigned param_count, unsigned array_params_mask,
258 unsigned sgpr_params, bool unsafe_math)
259 {
260 LLVMTypeRef main_function_type, ret_type;
261 LLVMBasicBlockRef main_function_body;
262
263 if (num_return_elems)
264 ret_type = LLVMStructTypeInContext(ctx, return_types,
265 num_return_elems, true);
266 else
267 ret_type = LLVMVoidTypeInContext(ctx);
268
269 /* Setup the function */
270 main_function_type =
271 LLVMFunctionType(ret_type, param_types, param_count, 0);
272 LLVMValueRef main_function =
273 LLVMAddFunction(module, "main", main_function_type);
274 main_function_body =
275 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
276 LLVMPositionBuilderAtEnd(builder, main_function_body);
277
278 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
279 for (unsigned i = 0; i < sgpr_params; ++i) {
280 if (array_params_mask & (1 << i)) {
281 LLVMValueRef P = LLVMGetParam(main_function, i);
282 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
283 ac_add_attr_dereferenceable(P, UINT64_MAX);
284 }
285 else {
286 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
287 }
288 }
289
290 if (unsafe_math) {
291 /* These were copied from some LLVM test. */
292 LLVMAddTargetDependentFunctionAttr(main_function,
293 "less-precise-fpmad",
294 "true");
295 LLVMAddTargetDependentFunctionAttr(main_function,
296 "no-infs-fp-math",
297 "true");
298 LLVMAddTargetDependentFunctionAttr(main_function,
299 "no-nans-fp-math",
300 "true");
301 LLVMAddTargetDependentFunctionAttr(main_function,
302 "unsafe-fp-math",
303 "true");
304 }
305 return main_function;
306 }
307
308 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
309 {
310 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
311 CONST_ADDR_SPACE);
312 }
313
314 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
315 int idx,
316 LLVMTypeRef type)
317 {
318 LLVMValueRef offset;
319 LLVMValueRef ptr;
320 int addr_space;
321
322 offset = LLVMConstInt(ctx->i32, idx * 16, false);
323
324 ptr = ctx->shared_memory;
325 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
326 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
327 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
328 return ptr;
329 }
330
331 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
332 {
333 if (t == ctx->f16 || t == ctx->i16)
334 return ctx->i16;
335 else if (t == ctx->f32 || t == ctx->i32)
336 return ctx->i32;
337 else if (t == ctx->f64 || t == ctx->i64)
338 return ctx->i64;
339 else
340 unreachable("Unhandled integer size");
341 }
342
343 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
344 {
345 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
346 LLVMTypeRef elem_type = LLVMGetElementType(t);
347 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
348 LLVMGetVectorSize(t));
349 }
350 return to_integer_type_scalar(ctx, t);
351 }
352
353 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
354 {
355 LLVMTypeRef type = LLVMTypeOf(v);
356 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
357 }
358
359 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
360 {
361 if (t == ctx->i16 || t == ctx->f16)
362 return ctx->f16;
363 else if (t == ctx->i32 || t == ctx->f32)
364 return ctx->f32;
365 else if (t == ctx->i64 || t == ctx->f64)
366 return ctx->f64;
367 else
368 unreachable("Unhandled float size");
369 }
370
371 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
372 {
373 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
374 LLVMTypeRef elem_type = LLVMGetElementType(t);
375 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
376 LLVMGetVectorSize(t));
377 }
378 return to_float_type_scalar(ctx, t);
379 }
380
381 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
382 {
383 LLVMTypeRef type = LLVMTypeOf(v);
384 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
385 }
386
387 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
388 {
389 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
390 type = LLVMGetElementType(type);
391
392 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
393 return LLVMGetIntTypeWidth(type);
394
395 if (type == ctx->f16)
396 return 16;
397 if (type == ctx->f32)
398 return 32;
399 if (type == ctx->f64)
400 return 64;
401
402 unreachable("Unhandled type kind in get_elem_bits");
403 }
404
405 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
406 LLVMValueRef param, unsigned rshift,
407 unsigned bitwidth)
408 {
409 LLVMValueRef value = param;
410 if (rshift)
411 value = LLVMBuildLShr(ctx->builder, value,
412 LLVMConstInt(ctx->i32, rshift, false), "");
413
414 if (rshift + bitwidth < 32) {
415 unsigned mask = (1 << bitwidth) - 1;
416 value = LLVMBuildAnd(ctx->builder, value,
417 LLVMConstInt(ctx->i32, mask, false), "");
418 }
419 return value;
420 }
421
422 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
423 {
424 switch (ctx->stage) {
425 case MESA_SHADER_TESS_CTRL:
426 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
427 case MESA_SHADER_TESS_EVAL:
428 return ctx->tes_rel_patch_id;
429 break;
430 default:
431 unreachable("Illegal stage");
432 }
433 }
434
435 /* Tessellation shaders pass outputs to the next shader using LDS.
436 *
437 * LS outputs = TCS inputs
438 * TCS outputs = TES inputs
439 *
440 * The LDS layout is:
441 * - TCS inputs for patch 0
442 * - TCS inputs for patch 1
443 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
444 * - ...
445 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
446 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
447 * - TCS outputs for patch 1
448 * - Per-patch TCS outputs for patch 1
449 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
450 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
451 * - ...
452 *
453 * All three shaders VS(LS), TCS, TES share the same LDS space.
454 */
455 static LLVMValueRef
456 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
457 {
458 if (ctx->stage == MESA_SHADER_VERTEX)
459 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
460 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
461 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
462 else {
463 assert(0);
464 return NULL;
465 }
466 }
467
468 static LLVMValueRef
469 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
470 {
471 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
472 }
473
474 static LLVMValueRef
475 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
476 {
477 return LLVMBuildMul(ctx->builder,
478 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
479 LLVMConstInt(ctx->i32, 4, false), "");
480 }
481
482 static LLVMValueRef
483 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
484 {
485 return LLVMBuildMul(ctx->builder,
486 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
487 LLVMConstInt(ctx->i32, 4, false), "");
488 }
489
490 static LLVMValueRef
491 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
494 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
495
496 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
497 }
498
499 static LLVMValueRef
500 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
501 {
502 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
503 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
504 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
505
506 return LLVMBuildAdd(ctx->builder, patch0_offset,
507 LLVMBuildMul(ctx->builder, patch_stride,
508 rel_patch_id, ""),
509 "");
510 }
511
512 static LLVMValueRef
513 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
514 {
515 LLVMValueRef patch0_patch_data_offset =
516 get_tcs_out_patch0_patch_data_offset(ctx);
517 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
518 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
519
520 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
521 LLVMBuildMul(ctx->builder, patch_stride,
522 rel_patch_id, ""),
523 "");
524 }
525
526 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
527 {
528 ud_info->sgpr_idx = sgpr_idx;
529 ud_info->num_sgprs = num_sgprs;
530 ud_info->indirect = false;
531 ud_info->indirect_offset = 0;
532 }
533
534 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
535 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
536 {
537 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
538 }
539
540
541 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
542 uint32_t indirect_offset)
543 {
544 ud_info->sgpr_idx = sgpr_idx;
545 ud_info->num_sgprs = num_sgprs;
546 ud_info->indirect = true;
547 ud_info->indirect_offset = indirect_offset;
548 }
549
550 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
551 {
552 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
553 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
554 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
555 "tess_lds");
556 }
557
558 struct user_sgpr_info {
559 bool need_ring_offsets;
560 uint8_t sgpr_count;
561 bool indirect_all_descriptor_sets;
562 };
563
564 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
565 struct user_sgpr_info *user_sgpr_info)
566 {
567 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
568
569 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
570 if (ctx->stage == MESA_SHADER_GEOMETRY ||
571 ctx->stage == MESA_SHADER_VERTEX ||
572 ctx->stage == MESA_SHADER_TESS_CTRL ||
573 ctx->stage == MESA_SHADER_TESS_EVAL ||
574 ctx->is_gs_copy_shader)
575 user_sgpr_info->need_ring_offsets = true;
576
577 if (ctx->stage == MESA_SHADER_FRAGMENT &&
578 ctx->shader_info->info.ps.needs_sample_positions)
579 user_sgpr_info->need_ring_offsets = true;
580
581 /* 2 user sgprs will nearly always be allocated for scratch/rings */
582 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
583 user_sgpr_info->sgpr_count += 2;
584 }
585
586 switch (ctx->stage) {
587 case MESA_SHADER_COMPUTE:
588 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
589 break;
590 case MESA_SHADER_FRAGMENT:
591 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
592 break;
593 case MESA_SHADER_VERTEX:
594 if (!ctx->is_gs_copy_shader) {
595 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
596 if (ctx->shader_info->info.vs.needs_draw_id) {
597 user_sgpr_info->sgpr_count += 3;
598 } else {
599 user_sgpr_info->sgpr_count += 2;
600 }
601 }
602 if (ctx->options->key.vs.as_ls)
603 user_sgpr_info->sgpr_count++;
604 break;
605 case MESA_SHADER_TESS_CTRL:
606 user_sgpr_info->sgpr_count += 4;
607 break;
608 case MESA_SHADER_TESS_EVAL:
609 user_sgpr_info->sgpr_count += 1;
610 break;
611 case MESA_SHADER_GEOMETRY:
612 user_sgpr_info->sgpr_count += 2;
613 break;
614 default:
615 break;
616 }
617
618 if (ctx->shader_info->info.needs_push_constants)
619 user_sgpr_info->sgpr_count += 2;
620
621 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
622 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
623 user_sgpr_info->sgpr_count += 2;
624 user_sgpr_info->indirect_all_descriptor_sets = true;
625 } else {
626 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
627 }
628 }
629
630 static void create_function(struct nir_to_llvm_context *ctx)
631 {
632 LLVMTypeRef arg_types[23];
633 unsigned arg_idx = 0;
634 unsigned array_params_mask = 0;
635 unsigned sgpr_count = 0, user_sgpr_count;
636 unsigned i;
637 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
638 unsigned user_sgpr_idx;
639 struct user_sgpr_info user_sgpr_info;
640
641 allocate_user_sgprs(ctx, &user_sgpr_info);
642 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
643 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* address of rings */
644 }
645
646 /* 1 for each descriptor set */
647 if (!user_sgpr_info.indirect_all_descriptor_sets) {
648 for (unsigned i = 0; i < num_sets; ++i) {
649 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
650 array_params_mask |= (1 << arg_idx);
651 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
652 }
653 }
654 } else {
655 array_params_mask |= (1 << arg_idx);
656 arg_types[arg_idx++] = const_array(const_array(ctx->i8, 1024 * 1024), 32);
657 }
658
659 if (ctx->shader_info->info.needs_push_constants) {
660 /* 1 for push constants and dynamic descriptors */
661 array_params_mask |= (1 << arg_idx);
662 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
663 }
664
665 switch (ctx->stage) {
666 case MESA_SHADER_COMPUTE:
667 if (ctx->shader_info->info.cs.grid_components_used)
668 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used); /* grid size */
669 user_sgpr_count = arg_idx;
670 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
671 arg_types[arg_idx++] = ctx->i32;
672 sgpr_count = arg_idx;
673
674 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
675 break;
676 case MESA_SHADER_VERTEX:
677 if (!ctx->is_gs_copy_shader) {
678 if (ctx->shader_info->info.vs.has_vertex_buffers)
679 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
680 arg_types[arg_idx++] = ctx->i32; // base vertex
681 arg_types[arg_idx++] = ctx->i32; // start instance
682 if (ctx->shader_info->info.vs.needs_draw_id)
683 arg_types[arg_idx++] = ctx->i32; // draw index
684 }
685 user_sgpr_count = arg_idx;
686 if (ctx->options->key.vs.as_es)
687 arg_types[arg_idx++] = ctx->i32; //es2gs offset
688 else if (ctx->options->key.vs.as_ls) {
689 arg_types[arg_idx++] = ctx->i32; //ls out layout
690 user_sgpr_count++;
691 }
692 sgpr_count = arg_idx;
693 arg_types[arg_idx++] = ctx->i32; // vertex id
694 if (!ctx->is_gs_copy_shader) {
695 arg_types[arg_idx++] = ctx->i32; // rel auto id
696 arg_types[arg_idx++] = ctx->i32; // vs prim id
697 arg_types[arg_idx++] = ctx->i32; // instance id
698 }
699 break;
700 case MESA_SHADER_TESS_CTRL:
701 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
702 arg_types[arg_idx++] = ctx->i32; // tcs out offsets
703 arg_types[arg_idx++] = ctx->i32; // tcs out layout
704 arg_types[arg_idx++] = ctx->i32; // tcs in layout
705 user_sgpr_count = arg_idx;
706 arg_types[arg_idx++] = ctx->i32; // param oc lds
707 arg_types[arg_idx++] = ctx->i32; // tess factor offset
708 sgpr_count = arg_idx;
709 arg_types[arg_idx++] = ctx->i32; // patch id
710 arg_types[arg_idx++] = ctx->i32; // rel ids;
711 break;
712 case MESA_SHADER_TESS_EVAL:
713 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
714 user_sgpr_count = arg_idx;
715 if (ctx->options->key.tes.as_es) {
716 arg_types[arg_idx++] = ctx->i32; // OC LDS
717 arg_types[arg_idx++] = ctx->i32; //
718 arg_types[arg_idx++] = ctx->i32; // es2gs offset
719 } else {
720 arg_types[arg_idx++] = ctx->i32; //
721 arg_types[arg_idx++] = ctx->i32; // OC LDS
722 }
723 sgpr_count = arg_idx;
724 arg_types[arg_idx++] = ctx->f32; // tes_u
725 arg_types[arg_idx++] = ctx->f32; // tes_v
726 arg_types[arg_idx++] = ctx->i32; // tes rel patch id
727 arg_types[arg_idx++] = ctx->i32; // tes patch id
728 break;
729 case MESA_SHADER_GEOMETRY:
730 arg_types[arg_idx++] = ctx->i32; // gsvs stride
731 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
732 user_sgpr_count = arg_idx;
733 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
734 arg_types[arg_idx++] = ctx->i32; // wave id
735 sgpr_count = arg_idx;
736 arg_types[arg_idx++] = ctx->i32; // vtx0
737 arg_types[arg_idx++] = ctx->i32; // vtx1
738 arg_types[arg_idx++] = ctx->i32; // prim id
739 arg_types[arg_idx++] = ctx->i32; // vtx2
740 arg_types[arg_idx++] = ctx->i32; // vtx3
741 arg_types[arg_idx++] = ctx->i32; // vtx4
742 arg_types[arg_idx++] = ctx->i32; // vtx5
743 arg_types[arg_idx++] = ctx->i32; // GS instance id
744 break;
745 case MESA_SHADER_FRAGMENT:
746 if (ctx->shader_info->info.ps.needs_sample_positions)
747 arg_types[arg_idx++] = ctx->i32; /* sample position offset */
748 user_sgpr_count = arg_idx;
749 arg_types[arg_idx++] = ctx->i32; /* prim mask */
750 sgpr_count = arg_idx;
751 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
752 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
753 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
754 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
755 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
756 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
757 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
758 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
759 arg_types[arg_idx++] = ctx->f32; /* pos x float */
760 arg_types[arg_idx++] = ctx->f32; /* pos y float */
761 arg_types[arg_idx++] = ctx->f32; /* pos z float */
762 arg_types[arg_idx++] = ctx->f32; /* pos w float */
763 arg_types[arg_idx++] = ctx->i32; /* front face */
764 arg_types[arg_idx++] = ctx->i32; /* ancillary */
765 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
766 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
767 break;
768 default:
769 unreachable("Shader stage not implemented");
770 }
771
772 ctx->main_function = create_llvm_function(
773 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
774 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
775 set_llvm_calling_convention(ctx->main_function, ctx->stage);
776
777 ctx->shader_info->num_input_sgprs = 0;
778 ctx->shader_info->num_input_vgprs = 0;
779
780 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
781 for (i = 0; i < user_sgpr_count; i++)
782 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
783
784 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
785 for (; i < sgpr_count; i++)
786 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
787
788 if (ctx->stage != MESA_SHADER_FRAGMENT)
789 for (; i < arg_idx; ++i)
790 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
791
792 arg_idx = 0;
793 user_sgpr_idx = 0;
794
795 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
796 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
797 user_sgpr_idx += 2;
798 if (ctx->options->supports_spill) {
799 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
800 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
801 NULL, 0, AC_FUNC_ATTR_READNONE);
802 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
803 const_array(ctx->v16i8, 16), "");
804 } else
805 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
806 }
807
808 if (!user_sgpr_info.indirect_all_descriptor_sets) {
809 for (unsigned i = 0; i < num_sets; ++i) {
810 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
811 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
812 user_sgpr_idx += 2;
813 ctx->descriptor_sets[i] =
814 LLVMGetParam(ctx->main_function, arg_idx++);
815 } else
816 ctx->descriptor_sets[i] = NULL;
817 }
818 } else {
819 uint32_t desc_sgpr_idx = user_sgpr_idx;
820 LLVMValueRef desc_sets = LLVMGetParam(ctx->main_function, arg_idx++);
821 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
822 user_sgpr_idx += 2;
823
824 for (unsigned i = 0; i < num_sets; ++i) {
825 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
826 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
827 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
828
829 } else
830 ctx->descriptor_sets[i] = NULL;
831 }
832 ctx->shader_info->need_indirect_descriptor_sets = true;
833 }
834
835 if (ctx->shader_info->info.needs_push_constants) {
836 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
837 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
838 user_sgpr_idx += 2;
839 }
840
841 switch (ctx->stage) {
842 case MESA_SHADER_COMPUTE:
843 if (ctx->shader_info->info.cs.grid_components_used) {
844 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
845 user_sgpr_idx += ctx->shader_info->info.cs.grid_components_used;
846 ctx->num_work_groups =
847 LLVMGetParam(ctx->main_function, arg_idx++);
848 }
849 ctx->workgroup_ids =
850 LLVMGetParam(ctx->main_function, arg_idx++);
851 ctx->tg_size =
852 LLVMGetParam(ctx->main_function, arg_idx++);
853 ctx->local_invocation_ids =
854 LLVMGetParam(ctx->main_function, arg_idx++);
855 break;
856 case MESA_SHADER_VERTEX:
857 if (!ctx->is_gs_copy_shader) {
858 if (ctx->shader_info->info.vs.has_vertex_buffers) {
859 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
860 user_sgpr_idx += 2;
861 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
862 }
863 unsigned vs_num = 2;
864 if (ctx->shader_info->info.vs.needs_draw_id)
865 vs_num++;
866
867 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
868 user_sgpr_idx += vs_num;
869
870 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
871 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
872 if (ctx->shader_info->info.vs.needs_draw_id)
873 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
874 }
875 if (ctx->options->key.vs.as_es)
876 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
877 else if (ctx->options->key.vs.as_ls) {
878 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, user_sgpr_idx, 1);
879 user_sgpr_idx += 1;
880 ctx->ls_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
881 }
882 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
883 if (!ctx->is_gs_copy_shader) {
884 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
885 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
886 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
887 }
888 if (ctx->options->key.vs.as_ls)
889 declare_tess_lds(ctx);
890 break;
891 case MESA_SHADER_TESS_CTRL:
892 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, user_sgpr_idx, 4);
893 user_sgpr_idx += 4;
894 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
895 ctx->tcs_out_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
896 ctx->tcs_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
897 ctx->tcs_in_layout = LLVMGetParam(ctx->main_function, arg_idx++);
898 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
899 ctx->tess_factor_offset = LLVMGetParam(ctx->main_function, arg_idx++);
900 ctx->tcs_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
901 ctx->tcs_rel_ids = LLVMGetParam(ctx->main_function, arg_idx++);
902
903 declare_tess_lds(ctx);
904 break;
905 case MESA_SHADER_TESS_EVAL:
906 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, user_sgpr_idx, 1);
907 user_sgpr_idx += 1;
908 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
909 if (ctx->options->key.tes.as_es) {
910 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
911 arg_idx++;
912 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
913 } else {
914 arg_idx++;
915 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
916 }
917 ctx->tes_u = LLVMGetParam(ctx->main_function, arg_idx++);
918 ctx->tes_v = LLVMGetParam(ctx->main_function, arg_idx++);
919 ctx->tes_rel_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
920 ctx->tes_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
921 break;
922 case MESA_SHADER_GEOMETRY:
923 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
924 user_sgpr_idx += 2;
925 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
926 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
927 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
928 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
929 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
930 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
931 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
932 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
933 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
934 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
935 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
936 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
937 break;
938 case MESA_SHADER_FRAGMENT:
939 if (ctx->shader_info->info.ps.needs_sample_positions) {
940 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, user_sgpr_idx, 1);
941 user_sgpr_idx += 1;
942 ctx->sample_pos_offset = LLVMGetParam(ctx->main_function, arg_idx++);
943 }
944 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
945 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
946 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
947 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
948 arg_idx++;
949 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
950 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
951 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
952 arg_idx++; /* line stipple */
953 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
954 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
955 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
956 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
957 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
958 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
959 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
960 break;
961 default:
962 unreachable("Shader stage not implemented");
963 }
964 }
965
966 static void setup_types(struct nir_to_llvm_context *ctx)
967 {
968 LLVMValueRef args[4];
969
970 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
971 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
972 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
973 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
974 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
975 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
976 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
977 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
978 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
979 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
980 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
981 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
982 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
983 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
984 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
985 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
986
987 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
988 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
989 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
990 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
991 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
992 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
993
994 args[0] = ctx->f32zero;
995 args[1] = ctx->f32zero;
996 args[2] = ctx->f32zero;
997 args[3] = ctx->f32one;
998 ctx->v4f32empty = LLVMConstVector(args, 4);
999
1000 ctx->uniform_md_kind =
1001 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
1002 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
1003
1004 args[0] = LLVMConstReal(ctx->f32, 2.5);
1005 }
1006
1007 static int get_llvm_num_components(LLVMValueRef value)
1008 {
1009 LLVMTypeRef type = LLVMTypeOf(value);
1010 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1011 ? LLVMGetVectorSize(type)
1012 : 1;
1013 return num_components;
1014 }
1015
1016 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
1017 LLVMValueRef value,
1018 int index)
1019 {
1020 int count = get_llvm_num_components(value);
1021
1022 assert(index < count);
1023 if (count == 1)
1024 return value;
1025
1026 return LLVMBuildExtractElement(ctx->builder, value,
1027 LLVMConstInt(ctx->i32, index, false), "");
1028 }
1029
1030 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
1031 LLVMValueRef value, unsigned count)
1032 {
1033 unsigned num_components = get_llvm_num_components(value);
1034 if (count == num_components)
1035 return value;
1036
1037 LLVMValueRef masks[] = {
1038 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1039 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1040
1041 if (count == 1)
1042 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1043 "");
1044
1045 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1046 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1047 }
1048
1049 static void
1050 build_store_values_extended(struct nir_to_llvm_context *ctx,
1051 LLVMValueRef *values,
1052 unsigned value_count,
1053 unsigned value_stride,
1054 LLVMValueRef vec)
1055 {
1056 LLVMBuilderRef builder = ctx->builder;
1057 unsigned i;
1058
1059 if (value_count == 1) {
1060 LLVMBuildStore(builder, vec, values[0]);
1061 return;
1062 }
1063
1064 for (i = 0; i < value_count; i++) {
1065 LLVMValueRef ptr = values[i * value_stride];
1066 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
1067 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1068 LLVMBuildStore(builder, value, ptr);
1069 }
1070 }
1071
1072 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
1073 nir_ssa_def *def)
1074 {
1075 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
1076 if (def->num_components > 1) {
1077 type = LLVMVectorType(type, def->num_components);
1078 }
1079 return type;
1080 }
1081
1082 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
1083 {
1084 assert(src.is_ssa);
1085 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
1086 return (LLVMValueRef)entry->data;
1087 }
1088
1089
1090 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
1091 struct nir_block *b)
1092 {
1093 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
1094 return (LLVMBasicBlockRef)entry->data;
1095 }
1096
1097 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
1098 nir_alu_src src,
1099 unsigned num_components)
1100 {
1101 LLVMValueRef value = get_src(ctx, src.src);
1102 bool need_swizzle = false;
1103
1104 assert(value);
1105 LLVMTypeRef type = LLVMTypeOf(value);
1106 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1107 ? LLVMGetVectorSize(type)
1108 : 1;
1109
1110 for (unsigned i = 0; i < num_components; ++i) {
1111 assert(src.swizzle[i] < src_components);
1112 if (src.swizzle[i] != i)
1113 need_swizzle = true;
1114 }
1115
1116 if (need_swizzle || num_components != src_components) {
1117 LLVMValueRef masks[] = {
1118 LLVMConstInt(ctx->i32, src.swizzle[0], false),
1119 LLVMConstInt(ctx->i32, src.swizzle[1], false),
1120 LLVMConstInt(ctx->i32, src.swizzle[2], false),
1121 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
1122
1123 if (src_components > 1 && num_components == 1) {
1124 value = LLVMBuildExtractElement(ctx->builder, value,
1125 masks[0], "");
1126 } else if (src_components == 1 && num_components > 1) {
1127 LLVMValueRef values[] = {value, value, value, value};
1128 value = ac_build_gather_values(&ctx->ac, values, num_components);
1129 } else {
1130 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1131 value = LLVMBuildShuffleVector(ctx->builder, value, value,
1132 swizzle, "");
1133 }
1134 }
1135 assert(!src.negate);
1136 assert(!src.abs);
1137 return value;
1138 }
1139
1140 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
1141 LLVMIntPredicate pred, LLVMValueRef src0,
1142 LLVMValueRef src1)
1143 {
1144 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1145 return LLVMBuildSelect(ctx->builder, result,
1146 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1147 LLVMConstInt(ctx->i32, 0, false), "");
1148 }
1149
1150 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
1151 LLVMRealPredicate pred, LLVMValueRef src0,
1152 LLVMValueRef src1)
1153 {
1154 LLVMValueRef result;
1155 src0 = to_float(ctx, src0);
1156 src1 = to_float(ctx, src1);
1157 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1158 return LLVMBuildSelect(ctx->builder, result,
1159 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1160 LLVMConstInt(ctx->i32, 0, false), "");
1161 }
1162
1163 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
1164 const char *intrin,
1165 LLVMTypeRef result_type,
1166 LLVMValueRef src0)
1167 {
1168 char name[64];
1169 LLVMValueRef params[] = {
1170 to_float(ctx, src0),
1171 };
1172
1173 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1174 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1175 }
1176
1177 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
1178 const char *intrin,
1179 LLVMTypeRef result_type,
1180 LLVMValueRef src0, LLVMValueRef src1)
1181 {
1182 char name[64];
1183 LLVMValueRef params[] = {
1184 to_float(ctx, src0),
1185 to_float(ctx, src1),
1186 };
1187
1188 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1189 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1190 }
1191
1192 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
1193 const char *intrin,
1194 LLVMTypeRef result_type,
1195 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1196 {
1197 char name[64];
1198 LLVMValueRef params[] = {
1199 to_float(ctx, src0),
1200 to_float(ctx, src1),
1201 to_float(ctx, src2),
1202 };
1203
1204 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1205 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1206 }
1207
1208 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
1209 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1210 {
1211 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1212 ctx->i32zero, "");
1213 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1214 }
1215
1216 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
1217 LLVMValueRef src0)
1218 {
1219 LLVMValueRef params[2] = {
1220 src0,
1221
1222 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1223 * add special code to check for x=0. The reason is that
1224 * the LLVM behavior for x=0 is different from what we
1225 * need here.
1226 *
1227 * The hardware already implements the correct behavior.
1228 */
1229 LLVMConstInt(ctx->i32, 1, false),
1230 };
1231 return ac_build_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1232 }
1233
1234 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
1235 LLVMValueRef src0)
1236 {
1237 return ac_build_imsb(&ctx->ac, src0, ctx->i32);
1238 }
1239
1240 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
1241 LLVMValueRef src0)
1242 {
1243 return ac_build_umsb(&ctx->ac, src0, ctx->i32);
1244 }
1245
1246 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
1247 LLVMIntPredicate pred,
1248 LLVMValueRef src0, LLVMValueRef src1)
1249 {
1250 return LLVMBuildSelect(ctx->builder,
1251 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1252 src0,
1253 src1, "");
1254
1255 }
1256 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
1257 LLVMValueRef src0)
1258 {
1259 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1260 LLVMBuildNeg(ctx->builder, src0, ""));
1261 }
1262
1263 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1264 LLVMValueRef src0)
1265 {
1266 LLVMValueRef cmp, val;
1267
1268 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1269 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1270 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1271 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1272 return val;
1273 }
1274
1275 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1276 LLVMValueRef src0)
1277 {
1278 LLVMValueRef cmp, val;
1279
1280 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1281 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1282 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1283 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1284 return val;
1285 }
1286
1287 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1288 LLVMValueRef src0)
1289 {
1290 const char *intr = "llvm.floor.f32";
1291 LLVMValueRef fsrc0 = to_float(ctx, src0);
1292 LLVMValueRef params[] = {
1293 fsrc0,
1294 };
1295 LLVMValueRef floor = ac_build_intrinsic(&ctx->ac, intr,
1296 ctx->f32, params, 1,
1297 AC_FUNC_ATTR_READNONE);
1298 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1299 }
1300
1301 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1302 const char *intrin,
1303 LLVMValueRef src0, LLVMValueRef src1)
1304 {
1305 LLVMTypeRef ret_type;
1306 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1307 LLVMValueRef res;
1308 LLVMValueRef params[] = { src0, src1 };
1309 ret_type = LLVMStructTypeInContext(ctx->context, types,
1310 2, true);
1311
1312 res = ac_build_intrinsic(&ctx->ac, intrin, ret_type,
1313 params, 2, AC_FUNC_ATTR_READNONE);
1314
1315 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1316 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1317 return res;
1318 }
1319
1320 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1321 LLVMValueRef src0)
1322 {
1323 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1324 }
1325
1326 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1327 LLVMValueRef src0, LLVMValueRef src1)
1328 {
1329 LLVMValueRef dst64, result;
1330 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1331 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1332
1333 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1334 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1335 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1336 return result;
1337 }
1338
1339 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1340 LLVMValueRef src0, LLVMValueRef src1)
1341 {
1342 LLVMValueRef dst64, result;
1343 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1344 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1345
1346 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1347 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1348 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1349 return result;
1350 }
1351
1352 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1353 bool is_signed,
1354 LLVMValueRef srcs[3])
1355 {
1356 LLVMValueRef result;
1357 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1358
1359 result = ac_build_bfe(&ctx->ac, srcs[0], srcs[1], srcs[2], is_signed);
1360 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1361 return result;
1362 }
1363
1364 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1365 LLVMValueRef src0, LLVMValueRef src1,
1366 LLVMValueRef src2, LLVMValueRef src3)
1367 {
1368 LLVMValueRef bfi_args[3], result;
1369
1370 bfi_args[0] = LLVMBuildShl(ctx->builder,
1371 LLVMBuildSub(ctx->builder,
1372 LLVMBuildShl(ctx->builder,
1373 ctx->i32one,
1374 src3, ""),
1375 ctx->i32one, ""),
1376 src2, "");
1377 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1378 bfi_args[2] = src0;
1379
1380 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1381
1382 /* Calculate:
1383 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1384 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1385 */
1386 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1387 LLVMBuildAnd(ctx->builder, bfi_args[0],
1388 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1389
1390 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1391 return result;
1392 }
1393
1394 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1395 LLVMValueRef src0)
1396 {
1397 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1398 int i;
1399 LLVMValueRef comp[2];
1400
1401 src0 = to_float(ctx, src0);
1402 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1403 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1404 for (i = 0; i < 2; i++) {
1405 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1406 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1407 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1408 }
1409
1410 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1411 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1412
1413 return comp[0];
1414 }
1415
1416 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1417 LLVMValueRef src0)
1418 {
1419 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1420 LLVMValueRef temps[2], result, val;
1421 int i;
1422
1423 for (i = 0; i < 2; i++) {
1424 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1425 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1426 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1427 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1428 }
1429
1430 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1431 ctx->i32zero, "");
1432 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1433 ctx->i32one, "");
1434 return result;
1435 }
1436
1437 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1438 nir_op op,
1439 LLVMValueRef src0)
1440 {
1441 unsigned mask;
1442 int idx;
1443 LLVMValueRef result;
1444 ctx->has_ddxy = true;
1445
1446 if (!ctx->lds && !ctx->has_ds_bpermute)
1447 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1448 LLVMArrayType(ctx->i32, 64),
1449 "ddxy_lds", LOCAL_ADDR_SPACE);
1450
1451 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1452 mask = AC_TID_MASK_LEFT;
1453 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1454 mask = AC_TID_MASK_TOP;
1455 else
1456 mask = AC_TID_MASK_TOP_LEFT;
1457
1458 /* for DDX we want to next X pixel, DDY next Y pixel. */
1459 if (op == nir_op_fddx_fine ||
1460 op == nir_op_fddx_coarse ||
1461 op == nir_op_fddx)
1462 idx = 1;
1463 else
1464 idx = 2;
1465
1466 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1467 mask, idx, ctx->lds,
1468 src0);
1469 return result;
1470 }
1471
1472 /*
1473 * this takes an I,J coordinate pair,
1474 * and works out the X and Y derivatives.
1475 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1476 */
1477 static LLVMValueRef emit_ddxy_interp(
1478 struct nir_to_llvm_context *ctx,
1479 LLVMValueRef interp_ij)
1480 {
1481 LLVMValueRef result[4], a;
1482 unsigned i;
1483
1484 for (i = 0; i < 2; i++) {
1485 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1486 LLVMConstInt(ctx->i32, i, false), "");
1487 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1488 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1489 }
1490 return ac_build_gather_values(&ctx->ac, result, 4);
1491 }
1492
1493 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1494 {
1495 LLVMValueRef src[4], result = NULL;
1496 unsigned num_components = instr->dest.dest.ssa.num_components;
1497 unsigned src_components;
1498 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1499
1500 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1501 switch (instr->op) {
1502 case nir_op_vec2:
1503 case nir_op_vec3:
1504 case nir_op_vec4:
1505 src_components = 1;
1506 break;
1507 case nir_op_pack_half_2x16:
1508 src_components = 2;
1509 break;
1510 case nir_op_unpack_half_2x16:
1511 src_components = 1;
1512 break;
1513 default:
1514 src_components = num_components;
1515 break;
1516 }
1517 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1518 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1519
1520 switch (instr->op) {
1521 case nir_op_fmov:
1522 case nir_op_imov:
1523 result = src[0];
1524 break;
1525 case nir_op_fneg:
1526 src[0] = to_float(ctx, src[0]);
1527 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1528 break;
1529 case nir_op_ineg:
1530 result = LLVMBuildNeg(ctx->builder, src[0], "");
1531 break;
1532 case nir_op_inot:
1533 result = LLVMBuildNot(ctx->builder, src[0], "");
1534 break;
1535 case nir_op_iadd:
1536 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1537 break;
1538 case nir_op_fadd:
1539 src[0] = to_float(ctx, src[0]);
1540 src[1] = to_float(ctx, src[1]);
1541 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1542 break;
1543 case nir_op_fsub:
1544 src[0] = to_float(ctx, src[0]);
1545 src[1] = to_float(ctx, src[1]);
1546 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1547 break;
1548 case nir_op_isub:
1549 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1550 break;
1551 case nir_op_imul:
1552 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1553 break;
1554 case nir_op_imod:
1555 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1556 break;
1557 case nir_op_umod:
1558 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1559 break;
1560 case nir_op_fmod:
1561 src[0] = to_float(ctx, src[0]);
1562 src[1] = to_float(ctx, src[1]);
1563 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1564 result = emit_intrin_1f_param(ctx, "llvm.floor",
1565 to_float_type(ctx, def_type), result);
1566 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1567 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1568 break;
1569 case nir_op_frem:
1570 src[0] = to_float(ctx, src[0]);
1571 src[1] = to_float(ctx, src[1]);
1572 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1573 break;
1574 case nir_op_irem:
1575 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1576 break;
1577 case nir_op_idiv:
1578 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1579 break;
1580 case nir_op_udiv:
1581 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1582 break;
1583 case nir_op_fmul:
1584 src[0] = to_float(ctx, src[0]);
1585 src[1] = to_float(ctx, src[1]);
1586 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1587 break;
1588 case nir_op_fdiv:
1589 src[0] = to_float(ctx, src[0]);
1590 src[1] = to_float(ctx, src[1]);
1591 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1592 break;
1593 case nir_op_frcp:
1594 src[0] = to_float(ctx, src[0]);
1595 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1596 break;
1597 case nir_op_iand:
1598 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1599 break;
1600 case nir_op_ior:
1601 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1602 break;
1603 case nir_op_ixor:
1604 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1605 break;
1606 case nir_op_ishl:
1607 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1608 break;
1609 case nir_op_ishr:
1610 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1611 break;
1612 case nir_op_ushr:
1613 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1614 break;
1615 case nir_op_ilt:
1616 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1617 break;
1618 case nir_op_ine:
1619 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1620 break;
1621 case nir_op_ieq:
1622 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1623 break;
1624 case nir_op_ige:
1625 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1626 break;
1627 case nir_op_ult:
1628 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1629 break;
1630 case nir_op_uge:
1631 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1632 break;
1633 case nir_op_feq:
1634 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1635 break;
1636 case nir_op_fne:
1637 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1638 break;
1639 case nir_op_flt:
1640 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1641 break;
1642 case nir_op_fge:
1643 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1644 break;
1645 case nir_op_fabs:
1646 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1647 to_float_type(ctx, def_type), src[0]);
1648 break;
1649 case nir_op_iabs:
1650 result = emit_iabs(ctx, src[0]);
1651 break;
1652 case nir_op_imax:
1653 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1654 break;
1655 case nir_op_imin:
1656 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1657 break;
1658 case nir_op_umax:
1659 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1660 break;
1661 case nir_op_umin:
1662 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1663 break;
1664 case nir_op_isign:
1665 result = emit_isign(ctx, src[0]);
1666 break;
1667 case nir_op_fsign:
1668 src[0] = to_float(ctx, src[0]);
1669 result = emit_fsign(ctx, src[0]);
1670 break;
1671 case nir_op_ffloor:
1672 result = emit_intrin_1f_param(ctx, "llvm.floor",
1673 to_float_type(ctx, def_type), src[0]);
1674 break;
1675 case nir_op_ftrunc:
1676 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1677 to_float_type(ctx, def_type), src[0]);
1678 break;
1679 case nir_op_fceil:
1680 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1681 to_float_type(ctx, def_type), src[0]);
1682 break;
1683 case nir_op_fround_even:
1684 result = emit_intrin_1f_param(ctx, "llvm.rint",
1685 to_float_type(ctx, def_type),src[0]);
1686 break;
1687 case nir_op_ffract:
1688 result = emit_ffract(ctx, src[0]);
1689 break;
1690 case nir_op_fsin:
1691 result = emit_intrin_1f_param(ctx, "llvm.sin",
1692 to_float_type(ctx, def_type), src[0]);
1693 break;
1694 case nir_op_fcos:
1695 result = emit_intrin_1f_param(ctx, "llvm.cos",
1696 to_float_type(ctx, def_type), src[0]);
1697 break;
1698 case nir_op_fsqrt:
1699 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1700 to_float_type(ctx, def_type), src[0]);
1701 break;
1702 case nir_op_fexp2:
1703 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1704 to_float_type(ctx, def_type), src[0]);
1705 break;
1706 case nir_op_flog2:
1707 result = emit_intrin_1f_param(ctx, "llvm.log2",
1708 to_float_type(ctx, def_type), src[0]);
1709 break;
1710 case nir_op_frsq:
1711 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1712 to_float_type(ctx, def_type), src[0]);
1713 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1714 break;
1715 case nir_op_fpow:
1716 result = emit_intrin_2f_param(ctx, "llvm.pow",
1717 to_float_type(ctx, def_type), src[0], src[1]);
1718 break;
1719 case nir_op_fmax:
1720 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1721 to_float_type(ctx, def_type), src[0], src[1]);
1722 break;
1723 case nir_op_fmin:
1724 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1725 to_float_type(ctx, def_type), src[0], src[1]);
1726 break;
1727 case nir_op_ffma:
1728 result = emit_intrin_3f_param(ctx, "llvm.fma",
1729 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1730 break;
1731 case nir_op_ibitfield_extract:
1732 result = emit_bitfield_extract(ctx, true, src);
1733 break;
1734 case nir_op_ubitfield_extract:
1735 result = emit_bitfield_extract(ctx, false, src);
1736 break;
1737 case nir_op_bitfield_insert:
1738 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1739 break;
1740 case nir_op_bitfield_reverse:
1741 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1742 break;
1743 case nir_op_bit_count:
1744 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1745 break;
1746 case nir_op_vec2:
1747 case nir_op_vec3:
1748 case nir_op_vec4:
1749 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1750 src[i] = to_integer(ctx, src[i]);
1751 result = ac_build_gather_values(&ctx->ac, src, num_components);
1752 break;
1753 case nir_op_f2i32:
1754 case nir_op_f2i64:
1755 src[0] = to_float(ctx, src[0]);
1756 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1757 break;
1758 case nir_op_f2u32:
1759 case nir_op_f2u64:
1760 src[0] = to_float(ctx, src[0]);
1761 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1762 break;
1763 case nir_op_i2f32:
1764 case nir_op_i2f64:
1765 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1766 break;
1767 case nir_op_u2f32:
1768 case nir_op_u2f64:
1769 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1770 break;
1771 case nir_op_f2f64:
1772 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1773 break;
1774 case nir_op_f2f32:
1775 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1776 break;
1777 case nir_op_u2u32:
1778 case nir_op_u2u64:
1779 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1780 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1781 else
1782 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1783 break;
1784 case nir_op_i2i32:
1785 case nir_op_i2i64:
1786 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1787 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1788 else
1789 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1790 break;
1791 case nir_op_bcsel:
1792 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1793 break;
1794 case nir_op_find_lsb:
1795 result = emit_find_lsb(ctx, src[0]);
1796 break;
1797 case nir_op_ufind_msb:
1798 result = emit_ufind_msb(ctx, src[0]);
1799 break;
1800 case nir_op_ifind_msb:
1801 result = emit_ifind_msb(ctx, src[0]);
1802 break;
1803 case nir_op_uadd_carry:
1804 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1805 break;
1806 case nir_op_usub_borrow:
1807 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1808 break;
1809 case nir_op_b2f:
1810 result = emit_b2f(ctx, src[0]);
1811 break;
1812 case nir_op_fquantize2f16:
1813 src[0] = to_float(ctx, src[0]);
1814 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1815 /* need to convert back up to f32 */
1816 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1817 break;
1818 case nir_op_umul_high:
1819 result = emit_umul_high(ctx, src[0], src[1]);
1820 break;
1821 case nir_op_imul_high:
1822 result = emit_imul_high(ctx, src[0], src[1]);
1823 break;
1824 case nir_op_pack_half_2x16:
1825 result = emit_pack_half_2x16(ctx, src[0]);
1826 break;
1827 case nir_op_unpack_half_2x16:
1828 result = emit_unpack_half_2x16(ctx, src[0]);
1829 break;
1830 case nir_op_fddx:
1831 case nir_op_fddy:
1832 case nir_op_fddx_fine:
1833 case nir_op_fddy_fine:
1834 case nir_op_fddx_coarse:
1835 case nir_op_fddy_coarse:
1836 result = emit_ddxy(ctx, instr->op, src[0]);
1837 break;
1838 default:
1839 fprintf(stderr, "Unknown NIR alu instr: ");
1840 nir_print_instr(&instr->instr, stderr);
1841 fprintf(stderr, "\n");
1842 abort();
1843 }
1844
1845 if (result) {
1846 assert(instr->dest.dest.is_ssa);
1847 result = to_integer(ctx, result);
1848 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1849 result);
1850 }
1851 }
1852
1853 static void visit_load_const(struct nir_to_llvm_context *ctx,
1854 nir_load_const_instr *instr)
1855 {
1856 LLVMValueRef values[4], value = NULL;
1857 LLVMTypeRef element_type =
1858 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1859
1860 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1861 switch (instr->def.bit_size) {
1862 case 32:
1863 values[i] = LLVMConstInt(element_type,
1864 instr->value.u32[i], false);
1865 break;
1866 case 64:
1867 values[i] = LLVMConstInt(element_type,
1868 instr->value.u64[i], false);
1869 break;
1870 default:
1871 fprintf(stderr,
1872 "unsupported nir load_const bit_size: %d\n",
1873 instr->def.bit_size);
1874 abort();
1875 }
1876 }
1877 if (instr->def.num_components > 1) {
1878 value = LLVMConstVector(values, instr->def.num_components);
1879 } else
1880 value = values[0];
1881
1882 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1883 }
1884
1885 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1886 LLVMTypeRef type)
1887 {
1888 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1889 return LLVMBuildBitCast(ctx->builder, ptr,
1890 LLVMPointerType(type, addr_space), "");
1891 }
1892
1893 static LLVMValueRef
1894 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1895 {
1896 LLVMValueRef size =
1897 LLVMBuildExtractElement(ctx->builder, descriptor,
1898 LLVMConstInt(ctx->i32, 2, false), "");
1899
1900 /* VI only */
1901 if (ctx->options->chip_class >= VI && in_elements) {
1902 /* On VI, the descriptor contains the size in bytes,
1903 * but TXQ must return the size in elements.
1904 * The stride is always non-zero for resources using TXQ.
1905 */
1906 LLVMValueRef stride =
1907 LLVMBuildExtractElement(ctx->builder, descriptor,
1908 LLVMConstInt(ctx->i32, 1, false), "");
1909 stride = LLVMBuildLShr(ctx->builder, stride,
1910 LLVMConstInt(ctx->i32, 16, false), "");
1911 stride = LLVMBuildAnd(ctx->builder, stride,
1912 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1913
1914 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1915 }
1916 return size;
1917 }
1918
1919 /**
1920 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1921 * intrinsic names).
1922 */
1923 static void build_int_type_name(
1924 LLVMTypeRef type,
1925 char *buf, unsigned bufsize)
1926 {
1927 assert(bufsize >= 6);
1928
1929 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1930 snprintf(buf, bufsize, "v%ui32",
1931 LLVMGetVectorSize(type));
1932 else
1933 strcpy(buf, "i32");
1934 }
1935
1936 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1937 struct ac_image_args *args,
1938 nir_tex_instr *instr)
1939 {
1940 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1941 LLVMValueRef coord = args->addr;
1942 LLVMValueRef half_texel[2];
1943 LLVMValueRef compare_cube_wa;
1944 LLVMValueRef result;
1945 int c;
1946 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1947
1948 //TODO Rect
1949 {
1950 struct ac_image_args txq_args = { 0 };
1951
1952 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1953 txq_args.opcode = ac_image_get_resinfo;
1954 txq_args.dmask = 0xf;
1955 txq_args.addr = ctx->i32zero;
1956 txq_args.resource = args->resource;
1957 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
1958
1959 for (c = 0; c < 2; c++) {
1960 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1961 LLVMConstInt(ctx->i32, c, false), "");
1962 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1963 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1964 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1965 LLVMConstReal(ctx->f32, -0.5), "");
1966 }
1967 }
1968
1969 LLVMValueRef orig_coords = args->addr;
1970
1971 for (c = 0; c < 2; c++) {
1972 LLVMValueRef tmp;
1973 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1974 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1975 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1976 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1977 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1978 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1979 }
1980
1981
1982 /*
1983 * Apparantly cube has issue with integer types that the workaround doesn't solve,
1984 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
1985 * workaround by sampling using a scaled type and converting.
1986 * This is taken from amdgpu-pro shaders.
1987 */
1988 /* NOTE this produces some ugly code compared to amdgpu-pro,
1989 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
1990 * and then reads them back. -pro generates two selects,
1991 * one s_cmp for the descriptor rewriting
1992 * one v_cmp for the coordinate and result changes.
1993 */
1994 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1995 LLVMValueRef tmp, tmp2;
1996
1997 /* workaround 8/8/8/8 uint/sint cube gather bug */
1998 /* first detect it then change to a scaled read and f2i */
1999 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
2000 tmp2 = tmp;
2001
2002 /* extract the DATA_FORMAT */
2003 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
2004 LLVMConstInt(ctx->i32, 6, false), false);
2005
2006 /* is the DATA_FORMAT == 8_8_8_8 */
2007 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2008
2009 if (stype == GLSL_TYPE_UINT)
2010 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2011 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2012 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2013 else
2014 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2015 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2016 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2017
2018 /* replace the NUM FORMAT in the descriptor */
2019 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2020 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2021
2022 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
2023
2024 /* don't modify the coordinates for this case */
2025 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2026 }
2027 args->addr = coord;
2028 result = ac_build_image_opcode(&ctx->ac, args);
2029
2030 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2031 LLVMValueRef tmp, tmp2;
2032
2033 /* if the cube workaround is in place, f2i the result. */
2034 for (c = 0; c < 4; c++) {
2035 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2036 if (stype == GLSL_TYPE_UINT)
2037 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2038 else
2039 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2040 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2041 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2042 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2043 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2044 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2045 }
2046 }
2047 return result;
2048 }
2049
2050 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
2051 nir_tex_instr *instr,
2052 struct ac_image_args *args)
2053 {
2054 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2055 return ac_build_buffer_load_format(&ctx->ac,
2056 args->resource,
2057 args->addr,
2058 LLVMConstInt(ctx->i32, 0, false),
2059 true);
2060 }
2061
2062 args->opcode = ac_image_sample;
2063 args->compare = instr->is_shadow;
2064
2065 switch (instr->op) {
2066 case nir_texop_txf:
2067 case nir_texop_txf_ms:
2068 case nir_texop_samples_identical:
2069 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2070 args->compare = false;
2071 args->offset = false;
2072 break;
2073 case nir_texop_txb:
2074 args->bias = true;
2075 break;
2076 case nir_texop_txl:
2077 args->lod = true;
2078 break;
2079 case nir_texop_txs:
2080 case nir_texop_query_levels:
2081 args->opcode = ac_image_get_resinfo;
2082 break;
2083 case nir_texop_tex:
2084 if (ctx->stage != MESA_SHADER_FRAGMENT)
2085 args->level_zero = true;
2086 break;
2087 case nir_texop_txd:
2088 args->deriv = true;
2089 break;
2090 case nir_texop_tg4:
2091 args->opcode = ac_image_gather4;
2092 args->level_zero = true;
2093 break;
2094 case nir_texop_lod:
2095 args->opcode = ac_image_get_lod;
2096 args->compare = false;
2097 args->offset = false;
2098 break;
2099 default:
2100 break;
2101 }
2102
2103 if (instr->op == nir_texop_tg4) {
2104 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2105 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2106 return radv_lower_gather4_integer(ctx, args, instr);
2107 }
2108 }
2109 return ac_build_image_opcode(&ctx->ac, args);
2110 }
2111
2112 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2113 nir_intrinsic_instr *instr)
2114 {
2115 LLVMValueRef index = get_src(ctx, instr->src[0]);
2116 unsigned desc_set = nir_intrinsic_desc_set(instr);
2117 unsigned binding = nir_intrinsic_binding(instr);
2118 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2119 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2120 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2121 unsigned base_offset = layout->binding[binding].offset;
2122 LLVMValueRef offset, stride;
2123
2124 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2125 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2126 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2127 layout->binding[binding].dynamic_offset_offset;
2128 desc_ptr = ctx->push_constants;
2129 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2130 stride = LLVMConstInt(ctx->i32, 16, false);
2131 } else
2132 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2133
2134 offset = LLVMConstInt(ctx->i32, base_offset, false);
2135 index = LLVMBuildMul(ctx->builder, index, stride, "");
2136 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2137
2138 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2139 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2140 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2141
2142 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2143 }
2144
2145 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2146 nir_intrinsic_instr *instr)
2147 {
2148 LLVMValueRef ptr, addr;
2149
2150 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2151 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
2152
2153 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2154 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
2155
2156 return LLVMBuildLoad(ctx->builder, ptr, "");
2157 }
2158
2159 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2160 nir_intrinsic_instr *instr)
2161 {
2162 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2163
2164 return get_buffer_size(ctx, desc, false);
2165 }
2166 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2167 nir_intrinsic_instr *instr)
2168 {
2169 const char *store_name;
2170 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2171 LLVMTypeRef data_type = ctx->f32;
2172 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
2173 int components_32bit = elem_size_mult * instr->num_components;
2174 unsigned writemask = nir_intrinsic_write_mask(instr);
2175 LLVMValueRef base_data, base_offset;
2176 LLVMValueRef params[6];
2177
2178 if (ctx->stage == MESA_SHADER_FRAGMENT)
2179 ctx->shader_info->fs.writes_memory = true;
2180
2181 params[1] = get_src(ctx, instr->src[1]);
2182 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2183 params[4] = ctx->i1false; /* glc */
2184 params[5] = ctx->i1false; /* slc */
2185
2186 if (components_32bit > 1)
2187 data_type = LLVMVectorType(ctx->f32, components_32bit);
2188
2189 base_data = to_float(ctx, src_data);
2190 base_data = trim_vector(ctx, base_data, instr->num_components);
2191 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2192 data_type, "");
2193 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2194 while (writemask) {
2195 int start, count;
2196 LLVMValueRef data;
2197 LLVMValueRef offset;
2198 LLVMValueRef tmp;
2199 u_bit_scan_consecutive_range(&writemask, &start, &count);
2200
2201 /* Due to an LLVM limitation, split 3-element writes
2202 * into a 2-element and a 1-element write. */
2203 if (count == 3) {
2204 writemask |= 1 << (start + 2);
2205 count = 2;
2206 }
2207
2208 start *= elem_size_mult;
2209 count *= elem_size_mult;
2210
2211 if (count > 4) {
2212 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2213 count = 4;
2214 }
2215
2216 if (count == 4) {
2217 store_name = "llvm.amdgcn.buffer.store.v4f32";
2218 data = base_data;
2219 } else if (count == 2) {
2220 tmp = LLVMBuildExtractElement(ctx->builder,
2221 base_data, LLVMConstInt(ctx->i32, start, false), "");
2222 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2223 ctx->i32zero, "");
2224
2225 tmp = LLVMBuildExtractElement(ctx->builder,
2226 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2227 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2228 ctx->i32one, "");
2229 store_name = "llvm.amdgcn.buffer.store.v2f32";
2230
2231 } else {
2232 assert(count == 1);
2233 if (get_llvm_num_components(base_data) > 1)
2234 data = LLVMBuildExtractElement(ctx->builder, base_data,
2235 LLVMConstInt(ctx->i32, start, false), "");
2236 else
2237 data = base_data;
2238 store_name = "llvm.amdgcn.buffer.store.f32";
2239 }
2240
2241 offset = base_offset;
2242 if (start != 0) {
2243 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2244 }
2245 params[0] = data;
2246 params[3] = offset;
2247 ac_build_intrinsic(&ctx->ac, store_name,
2248 ctx->voidt, params, 6, 0);
2249 }
2250 }
2251
2252 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2253 nir_intrinsic_instr *instr)
2254 {
2255 const char *name;
2256 LLVMValueRef params[6];
2257 int arg_count = 0;
2258 if (ctx->stage == MESA_SHADER_FRAGMENT)
2259 ctx->shader_info->fs.writes_memory = true;
2260
2261 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2262 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2263 }
2264 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2265 params[arg_count++] = get_src(ctx, instr->src[0]);
2266 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2267 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2268 params[arg_count++] = ctx->i1false; /* slc */
2269
2270 switch (instr->intrinsic) {
2271 case nir_intrinsic_ssbo_atomic_add:
2272 name = "llvm.amdgcn.buffer.atomic.add";
2273 break;
2274 case nir_intrinsic_ssbo_atomic_imin:
2275 name = "llvm.amdgcn.buffer.atomic.smin";
2276 break;
2277 case nir_intrinsic_ssbo_atomic_umin:
2278 name = "llvm.amdgcn.buffer.atomic.umin";
2279 break;
2280 case nir_intrinsic_ssbo_atomic_imax:
2281 name = "llvm.amdgcn.buffer.atomic.smax";
2282 break;
2283 case nir_intrinsic_ssbo_atomic_umax:
2284 name = "llvm.amdgcn.buffer.atomic.umax";
2285 break;
2286 case nir_intrinsic_ssbo_atomic_and:
2287 name = "llvm.amdgcn.buffer.atomic.and";
2288 break;
2289 case nir_intrinsic_ssbo_atomic_or:
2290 name = "llvm.amdgcn.buffer.atomic.or";
2291 break;
2292 case nir_intrinsic_ssbo_atomic_xor:
2293 name = "llvm.amdgcn.buffer.atomic.xor";
2294 break;
2295 case nir_intrinsic_ssbo_atomic_exchange:
2296 name = "llvm.amdgcn.buffer.atomic.swap";
2297 break;
2298 case nir_intrinsic_ssbo_atomic_comp_swap:
2299 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2300 break;
2301 default:
2302 abort();
2303 }
2304
2305 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2306 }
2307
2308 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2309 nir_intrinsic_instr *instr)
2310 {
2311 LLVMValueRef results[2];
2312 int load_components;
2313 int num_components = instr->num_components;
2314 if (instr->dest.ssa.bit_size == 64)
2315 num_components *= 2;
2316
2317 for (int i = 0; i < num_components; i += load_components) {
2318 load_components = MIN2(num_components - i, 4);
2319 const char *load_name;
2320 LLVMTypeRef data_type = ctx->f32;
2321 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2322 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2323
2324 if (load_components == 3)
2325 data_type = LLVMVectorType(ctx->f32, 4);
2326 else if (load_components > 1)
2327 data_type = LLVMVectorType(ctx->f32, load_components);
2328
2329 if (load_components >= 3)
2330 load_name = "llvm.amdgcn.buffer.load.v4f32";
2331 else if (load_components == 2)
2332 load_name = "llvm.amdgcn.buffer.load.v2f32";
2333 else if (load_components == 1)
2334 load_name = "llvm.amdgcn.buffer.load.f32";
2335 else
2336 unreachable("unhandled number of components");
2337
2338 LLVMValueRef params[] = {
2339 get_src(ctx, instr->src[0]),
2340 LLVMConstInt(ctx->i32, 0, false),
2341 offset,
2342 ctx->i1false,
2343 ctx->i1false,
2344 };
2345
2346 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2347
2348 }
2349
2350 LLVMValueRef ret = results[0];
2351 if (num_components > 4 || num_components == 3) {
2352 LLVMValueRef masks[] = {
2353 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2354 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2355 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2356 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2357 };
2358
2359 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2360 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2361 results[num_components > 4 ? 1 : 0], swizzle, "");
2362 }
2363
2364 return LLVMBuildBitCast(ctx->builder, ret,
2365 get_def_type(ctx, &instr->dest.ssa), "");
2366 }
2367
2368 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2369 nir_intrinsic_instr *instr)
2370 {
2371 LLVMValueRef results[8], ret;
2372 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2373 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2374 int num_components = instr->num_components;
2375
2376 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2377
2378 if (instr->dest.ssa.bit_size == 64)
2379 num_components *= 2;
2380
2381 for (unsigned i = 0; i < num_components; ++i) {
2382 LLVMValueRef params[] = {
2383 rsrc,
2384 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2385 offset, "")
2386 };
2387 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2388 params, 2,
2389 AC_FUNC_ATTR_READNONE |
2390 AC_FUNC_ATTR_LEGACY);
2391 }
2392
2393
2394 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2395 return LLVMBuildBitCast(ctx->builder, ret,
2396 get_def_type(ctx, &instr->dest.ssa), "");
2397 }
2398
2399 static void
2400 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref_var *deref,
2401 bool vs_in, unsigned *vertex_index_out,
2402 LLVMValueRef *vertex_index_ref,
2403 unsigned *const_out, LLVMValueRef *indir_out)
2404 {
2405 unsigned const_offset = 0;
2406 nir_deref *tail = &deref->deref;
2407 LLVMValueRef offset = NULL;
2408
2409 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2410 tail = tail->child;
2411 nir_deref_array *deref_array = nir_deref_as_array(tail);
2412 if (vertex_index_out)
2413 *vertex_index_out = deref_array->base_offset;
2414
2415 if (vertex_index_ref) {
2416 LLVMValueRef vtx = LLVMConstInt(ctx->i32, deref_array->base_offset, false);
2417 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2418 vtx = LLVMBuildAdd(ctx->builder, vtx, get_src(ctx, deref_array->indirect), "");
2419 }
2420 *vertex_index_ref = vtx;
2421 }
2422 }
2423
2424 if (deref->var->data.compact) {
2425 assert(tail->child->deref_type == nir_deref_type_array);
2426 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2427 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2428 /* We always lower indirect dereferences for "compact" array vars. */
2429 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2430
2431 const_offset = deref_array->base_offset;
2432 goto out;
2433 }
2434
2435 while (tail->child != NULL) {
2436 const struct glsl_type *parent_type = tail->type;
2437 tail = tail->child;
2438
2439 if (tail->deref_type == nir_deref_type_array) {
2440 nir_deref_array *deref_array = nir_deref_as_array(tail);
2441 LLVMValueRef index, stride, local_offset;
2442 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2443
2444 const_offset += size * deref_array->base_offset;
2445 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2446 continue;
2447
2448 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2449 index = get_src(ctx, deref_array->indirect);
2450 stride = LLVMConstInt(ctx->i32, size, 0);
2451 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2452
2453 if (offset)
2454 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2455 else
2456 offset = local_offset;
2457 } else if (tail->deref_type == nir_deref_type_struct) {
2458 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2459
2460 for (unsigned i = 0; i < deref_struct->index; i++) {
2461 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2462 const_offset += glsl_count_attribute_slots(ft, vs_in);
2463 }
2464 } else
2465 unreachable("unsupported deref type");
2466
2467 }
2468 out:
2469 if (const_offset && offset)
2470 offset = LLVMBuildAdd(ctx->builder, offset,
2471 LLVMConstInt(ctx->i32, const_offset, 0),
2472 "");
2473
2474 *const_out = const_offset;
2475 *indir_out = offset;
2476 }
2477
2478 static LLVMValueRef
2479 lds_load(struct nir_to_llvm_context *ctx,
2480 LLVMValueRef dw_addr)
2481 {
2482 LLVMValueRef value;
2483 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2484 return value;
2485 }
2486
2487 static void
2488 lds_store(struct nir_to_llvm_context *ctx,
2489 LLVMValueRef dw_addr, LLVMValueRef value)
2490 {
2491 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2492 ac_build_indexed_store(&ctx->ac, ctx->lds,
2493 dw_addr, value);
2494 }
2495
2496 /* The offchip buffer layout for TCS->TES is
2497 *
2498 * - attribute 0 of patch 0 vertex 0
2499 * - attribute 0 of patch 0 vertex 1
2500 * - attribute 0 of patch 0 vertex 2
2501 * ...
2502 * - attribute 0 of patch 1 vertex 0
2503 * - attribute 0 of patch 1 vertex 1
2504 * ...
2505 * - attribute 1 of patch 0 vertex 0
2506 * - attribute 1 of patch 0 vertex 1
2507 * ...
2508 * - per patch attribute 0 of patch 0
2509 * - per patch attribute 0 of patch 1
2510 * ...
2511 *
2512 * Note that every attribute has 4 components.
2513 */
2514 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2515 LLVMValueRef vertex_index,
2516 LLVMValueRef param_index)
2517 {
2518 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2519 LLVMValueRef param_stride, constant16;
2520 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2521
2522 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2523 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2524 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2525 num_patches, "");
2526
2527 constant16 = LLVMConstInt(ctx->i32, 16, false);
2528 if (vertex_index) {
2529 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2530 vertices_per_patch, "");
2531
2532 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2533 vertex_index, "");
2534
2535 param_stride = total_vertices;
2536 } else {
2537 base_addr = rel_patch_id;
2538 param_stride = num_patches;
2539 }
2540
2541 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2542 LLVMBuildMul(ctx->builder, param_index,
2543 param_stride, ""), "");
2544
2545 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2546
2547 if (!vertex_index) {
2548 LLVMValueRef patch_data_offset =
2549 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2550
2551 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2552 patch_data_offset, "");
2553 }
2554 return base_addr;
2555 }
2556
2557 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2558 unsigned param,
2559 unsigned const_index,
2560 bool is_compact,
2561 LLVMValueRef vertex_index,
2562 LLVMValueRef indir_index)
2563 {
2564 LLVMValueRef param_index;
2565
2566 if (indir_index)
2567 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2568 indir_index, "");
2569 else {
2570 if (const_index && !is_compact)
2571 param += const_index;
2572 param_index = LLVMConstInt(ctx->i32, param, false);
2573 }
2574 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2575 }
2576
2577 static void
2578 mark_tess_output(struct nir_to_llvm_context *ctx,
2579 bool is_patch, uint32_t param)
2580
2581 {
2582 if (is_patch) {
2583 ctx->tess_patch_outputs_written |= (1ull << param);
2584 } else
2585 ctx->tess_outputs_written |= (1ull << param);
2586 }
2587
2588 static LLVMValueRef
2589 get_dw_address(struct nir_to_llvm_context *ctx,
2590 LLVMValueRef dw_addr,
2591 unsigned param,
2592 unsigned const_index,
2593 bool compact_const_index,
2594 LLVMValueRef vertex_index,
2595 LLVMValueRef stride,
2596 LLVMValueRef indir_index)
2597
2598 {
2599
2600 if (vertex_index) {
2601 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2602 LLVMBuildMul(ctx->builder,
2603 vertex_index,
2604 stride, ""), "");
2605 }
2606
2607 if (indir_index)
2608 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2609 LLVMBuildMul(ctx->builder, indir_index,
2610 LLVMConstInt(ctx->i32, 4, false), ""), "");
2611 else if (const_index && !compact_const_index)
2612 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2613 LLVMConstInt(ctx->i32, const_index, false), "");
2614
2615 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2616 LLVMConstInt(ctx->i32, param * 4, false), "");
2617
2618 if (const_index && compact_const_index)
2619 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2620 LLVMConstInt(ctx->i32, const_index, false), "");
2621 return dw_addr;
2622 }
2623
2624 static LLVMValueRef
2625 load_tcs_input(struct nir_to_llvm_context *ctx,
2626 nir_intrinsic_instr *instr)
2627 {
2628 LLVMValueRef dw_addr, stride;
2629 unsigned const_index;
2630 LLVMValueRef vertex_index;
2631 LLVMValueRef indir_index;
2632 unsigned param;
2633 LLVMValueRef value[4], result;
2634 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2635 const bool is_compact = instr->variables[0]->var->data.compact;
2636 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2637 radv_get_deref_offset(ctx, instr->variables[0],
2638 false, NULL, per_vertex ? &vertex_index : NULL,
2639 &const_index, &indir_index);
2640
2641 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2642 dw_addr = get_tcs_in_current_patch_offset(ctx);
2643 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2644 indir_index);
2645
2646 for (unsigned i = 0; i < instr->num_components; i++) {
2647 value[i] = lds_load(ctx, dw_addr);
2648 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2649 ctx->i32one, "");
2650 }
2651 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2652 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2653 return result;
2654 }
2655
2656 static LLVMValueRef
2657 load_tcs_output(struct nir_to_llvm_context *ctx,
2658 nir_intrinsic_instr *instr)
2659 {
2660 LLVMValueRef dw_addr, stride;
2661 LLVMValueRef value[4], result;
2662 LLVMValueRef vertex_index = NULL;
2663 LLVMValueRef indir_index = NULL;
2664 unsigned const_index = 0;
2665 unsigned param;
2666 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2667 const bool is_compact = instr->variables[0]->var->data.compact;
2668 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2669 radv_get_deref_offset(ctx, instr->variables[0],
2670 false, NULL, per_vertex ? &vertex_index : NULL,
2671 &const_index, &indir_index);
2672
2673 if (!instr->variables[0]->var->data.patch) {
2674 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2675 dw_addr = get_tcs_out_current_patch_offset(ctx);
2676 } else {
2677 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2678 }
2679
2680 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2681 indir_index);
2682
2683 for (unsigned i = 0; i < instr->num_components; i++) {
2684 value[i] = lds_load(ctx, dw_addr);
2685 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2686 ctx->i32one, "");
2687 }
2688 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2689 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2690 return result;
2691 }
2692
2693 static void
2694 store_tcs_output(struct nir_to_llvm_context *ctx,
2695 nir_intrinsic_instr *instr,
2696 LLVMValueRef src,
2697 unsigned writemask)
2698 {
2699 LLVMValueRef stride, dw_addr;
2700 LLVMValueRef buf_addr = NULL;
2701 LLVMValueRef vertex_index = NULL;
2702 LLVMValueRef indir_index = NULL;
2703 unsigned const_index = 0;
2704 unsigned param;
2705 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2706 const bool is_compact = instr->variables[0]->var->data.compact;
2707
2708 radv_get_deref_offset(ctx, instr->variables[0],
2709 false, NULL, per_vertex ? &vertex_index : NULL,
2710 &const_index, &indir_index);
2711
2712 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2713 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2714 is_compact && const_index > 3) {
2715 const_index -= 3;
2716 param++;
2717 }
2718
2719 if (!instr->variables[0]->var->data.patch) {
2720 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2721 dw_addr = get_tcs_out_current_patch_offset(ctx);
2722 } else {
2723 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2724 }
2725
2726 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2727
2728 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2729 indir_index);
2730 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2731 vertex_index, indir_index);
2732
2733 unsigned base = is_compact ? const_index : 0;
2734 for (unsigned chan = 0; chan < 8; chan++) {
2735 bool is_tess_factor = false;
2736 if (!(writemask & (1 << chan)))
2737 continue;
2738 LLVMValueRef value = llvm_extract_elem(ctx, src, chan);
2739
2740 lds_store(ctx, dw_addr, value);
2741
2742 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2743 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2744 is_tess_factor = true;
2745
2746 if (!is_tess_factor && writemask != 0xF)
2747 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2748 buf_addr, ctx->oc_lds,
2749 4 * (base + chan), 1, 0, true, false);
2750
2751 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2752 ctx->i32one, "");
2753 }
2754
2755 if (writemask == 0xF) {
2756 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2757 buf_addr, ctx->oc_lds,
2758 (base * 4), 1, 0, true, false);
2759 }
2760 }
2761
2762 static LLVMValueRef
2763 load_tes_input(struct nir_to_llvm_context *ctx,
2764 nir_intrinsic_instr *instr)
2765 {
2766 LLVMValueRef buf_addr;
2767 LLVMValueRef result;
2768 LLVMValueRef vertex_index = NULL;
2769 LLVMValueRef indir_index = NULL;
2770 unsigned const_index = 0;
2771 unsigned param;
2772 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2773 const bool is_compact = instr->variables[0]->var->data.compact;
2774
2775 radv_get_deref_offset(ctx, instr->variables[0],
2776 false, NULL, per_vertex ? &vertex_index : NULL,
2777 &const_index, &indir_index);
2778 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2779 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2780 is_compact && const_index > 3) {
2781 const_index -= 3;
2782 param++;
2783 }
2784 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2785 is_compact, vertex_index, indir_index);
2786
2787 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2788 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true);
2789 result = trim_vector(ctx, result, instr->num_components);
2790 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2791 return result;
2792 }
2793
2794 static LLVMValueRef
2795 load_gs_input(struct nir_to_llvm_context *ctx,
2796 nir_intrinsic_instr *instr)
2797 {
2798 LLVMValueRef indir_index, vtx_offset;
2799 unsigned const_index;
2800 LLVMValueRef args[9];
2801 unsigned param, vtx_offset_param;
2802 LLVMValueRef value[4], result;
2803 unsigned vertex_index;
2804 radv_get_deref_offset(ctx, instr->variables[0],
2805 false, &vertex_index, NULL,
2806 &const_index, &indir_index);
2807 vtx_offset_param = vertex_index;
2808 assert(vtx_offset_param < 6);
2809 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2810 LLVMConstInt(ctx->i32, 4, false), "");
2811
2812 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2813 for (unsigned i = 0; i < instr->num_components; i++) {
2814
2815 args[0] = ctx->esgs_ring;
2816 args[1] = vtx_offset;
2817 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2818 args[3] = ctx->i32zero;
2819 args[4] = ctx->i32one; /* OFFEN */
2820 args[5] = ctx->i32zero; /* IDXEN */
2821 args[6] = ctx->i32one; /* GLC */
2822 args[7] = ctx->i32zero; /* SLC */
2823 args[8] = ctx->i32zero; /* TFE */
2824
2825 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2826 ctx->i32, args, 9,
2827 AC_FUNC_ATTR_READONLY |
2828 AC_FUNC_ATTR_LEGACY);
2829 }
2830 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2831
2832 return result;
2833 }
2834
2835 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2836 nir_intrinsic_instr *instr)
2837 {
2838 LLVMValueRef values[8];
2839 int idx = instr->variables[0]->var->data.driver_location;
2840 int ve = instr->dest.ssa.num_components;
2841 LLVMValueRef indir_index;
2842 LLVMValueRef ret;
2843 unsigned const_index;
2844 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2845 instr->variables[0]->var->data.mode == nir_var_shader_in;
2846 radv_get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2847 &const_index, &indir_index);
2848
2849 if (instr->dest.ssa.bit_size == 64)
2850 ve *= 2;
2851
2852 switch (instr->variables[0]->var->data.mode) {
2853 case nir_var_shader_in:
2854 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2855 return load_tcs_input(ctx, instr);
2856 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2857 return load_tes_input(ctx, instr);
2858 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2859 return load_gs_input(ctx, instr);
2860 }
2861 for (unsigned chan = 0; chan < ve; chan++) {
2862 if (indir_index) {
2863 unsigned count = glsl_count_attribute_slots(
2864 instr->variables[0]->var->type,
2865 ctx->stage == MESA_SHADER_VERTEX);
2866 count -= chan / 4;
2867 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2868 &ctx->ac, ctx->inputs + idx + chan, count,
2869 4, false);
2870
2871 values[chan] = LLVMBuildExtractElement(ctx->builder,
2872 tmp_vec,
2873 indir_index, "");
2874 } else
2875 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2876 }
2877 break;
2878 case nir_var_local:
2879 for (unsigned chan = 0; chan < ve; chan++) {
2880 if (indir_index) {
2881 unsigned count = glsl_count_attribute_slots(
2882 instr->variables[0]->var->type, false);
2883 count -= chan / 4;
2884 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2885 &ctx->ac, ctx->locals + idx + chan, count,
2886 4, true);
2887
2888 values[chan] = LLVMBuildExtractElement(ctx->builder,
2889 tmp_vec,
2890 indir_index, "");
2891 } else {
2892 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2893 }
2894 }
2895 break;
2896 case nir_var_shader_out:
2897 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2898 return load_tcs_output(ctx, instr);
2899 for (unsigned chan = 0; chan < ve; chan++) {
2900 if (indir_index) {
2901 unsigned count = glsl_count_attribute_slots(
2902 instr->variables[0]->var->type, false);
2903 count -= chan / 4;
2904 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2905 &ctx->ac, ctx->outputs + idx + chan, count,
2906 4, true);
2907
2908 values[chan] = LLVMBuildExtractElement(ctx->builder,
2909 tmp_vec,
2910 indir_index, "");
2911 } else {
2912 values[chan] = LLVMBuildLoad(ctx->builder,
2913 ctx->outputs[idx + chan + const_index * 4],
2914 "");
2915 }
2916 }
2917 break;
2918 case nir_var_shared: {
2919 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2920 LLVMValueRef derived_ptr;
2921
2922 if (indir_index)
2923 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2924
2925 for (unsigned chan = 0; chan < ve; chan++) {
2926 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2927 if (indir_index)
2928 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2929 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2930
2931 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2932 }
2933 break;
2934 }
2935 default:
2936 unreachable("unhandle variable mode");
2937 }
2938 ret = ac_build_gather_values(&ctx->ac, values, ve);
2939 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2940 }
2941
2942 static void
2943 visit_store_var(struct nir_to_llvm_context *ctx,
2944 nir_intrinsic_instr *instr)
2945 {
2946 LLVMValueRef temp_ptr, value;
2947 int idx = instr->variables[0]->var->data.driver_location;
2948 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2949 int writemask = instr->const_index[0];
2950 LLVMValueRef indir_index;
2951 unsigned const_index;
2952 radv_get_deref_offset(ctx, instr->variables[0], false,
2953 NULL, NULL, &const_index, &indir_index);
2954
2955 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2956 int old_writemask = writemask;
2957
2958 src = LLVMBuildBitCast(ctx->builder, src,
2959 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2960 "");
2961
2962 writemask = 0;
2963 for (unsigned chan = 0; chan < 4; chan++) {
2964 if (old_writemask & (1 << chan))
2965 writemask |= 3u << (2 * chan);
2966 }
2967 }
2968
2969 switch (instr->variables[0]->var->data.mode) {
2970 case nir_var_shader_out:
2971
2972 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
2973 store_tcs_output(ctx, instr, src, writemask);
2974 return;
2975 }
2976
2977 for (unsigned chan = 0; chan < 8; chan++) {
2978 int stride = 4;
2979 if (!(writemask & (1 << chan)))
2980 continue;
2981
2982 value = llvm_extract_elem(ctx, src, chan);
2983
2984 if (instr->variables[0]->var->data.compact)
2985 stride = 1;
2986 if (indir_index) {
2987 unsigned count = glsl_count_attribute_slots(
2988 instr->variables[0]->var->type, false);
2989 count -= chan / 4;
2990 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2991 &ctx->ac, ctx->outputs + idx + chan, count,
2992 stride, true);
2993
2994 if (get_llvm_num_components(tmp_vec) > 1) {
2995 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2996 value, indir_index, "");
2997 } else
2998 tmp_vec = value;
2999 build_store_values_extended(ctx, ctx->outputs + idx + chan,
3000 count, stride, tmp_vec);
3001
3002 } else {
3003 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3004
3005 LLVMBuildStore(ctx->builder, value, temp_ptr);
3006 }
3007 }
3008 break;
3009 case nir_var_local:
3010 for (unsigned chan = 0; chan < 8; chan++) {
3011 if (!(writemask & (1 << chan)))
3012 continue;
3013
3014 value = llvm_extract_elem(ctx, src, chan);
3015 if (indir_index) {
3016 unsigned count = glsl_count_attribute_slots(
3017 instr->variables[0]->var->type, false);
3018 count -= chan / 4;
3019 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3020 &ctx->ac, ctx->locals + idx + chan, count,
3021 4, true);
3022
3023 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3024 value, indir_index, "");
3025 build_store_values_extended(ctx, ctx->locals + idx + chan,
3026 count, 4, tmp_vec);
3027 } else {
3028 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3029
3030 LLVMBuildStore(ctx->builder, value, temp_ptr);
3031 }
3032 }
3033 break;
3034 case nir_var_shared: {
3035 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3036
3037 if (indir_index)
3038 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
3039
3040 for (unsigned chan = 0; chan < 8; chan++) {
3041 if (!(writemask & (1 << chan)))
3042 continue;
3043 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
3044 LLVMValueRef derived_ptr;
3045
3046 if (indir_index)
3047 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
3048
3049 value = llvm_extract_elem(ctx, src, chan);
3050 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
3051 LLVMBuildStore(ctx->builder,
3052 to_integer(ctx, value), derived_ptr);
3053 }
3054 break;
3055 }
3056 default:
3057 break;
3058 }
3059 }
3060
3061 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3062 {
3063 switch (dim) {
3064 case GLSL_SAMPLER_DIM_BUF:
3065 return 1;
3066 case GLSL_SAMPLER_DIM_1D:
3067 return array ? 2 : 1;
3068 case GLSL_SAMPLER_DIM_2D:
3069 return array ? 3 : 2;
3070 case GLSL_SAMPLER_DIM_MS:
3071 return array ? 4 : 3;
3072 case GLSL_SAMPLER_DIM_3D:
3073 case GLSL_SAMPLER_DIM_CUBE:
3074 return 3;
3075 case GLSL_SAMPLER_DIM_RECT:
3076 case GLSL_SAMPLER_DIM_SUBPASS:
3077 return 2;
3078 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3079 return 3;
3080 default:
3081 break;
3082 }
3083 return 0;
3084 }
3085
3086
3087
3088 /* Adjust the sample index according to FMASK.
3089 *
3090 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3091 * which is the identity mapping. Each nibble says which physical sample
3092 * should be fetched to get that sample.
3093 *
3094 * For example, 0x11111100 means there are only 2 samples stored and
3095 * the second sample covers 3/4 of the pixel. When reading samples 0
3096 * and 1, return physical sample 0 (determined by the first two 0s
3097 * in FMASK), otherwise return physical sample 1.
3098 *
3099 * The sample index should be adjusted as follows:
3100 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3101 */
3102 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
3103 LLVMValueRef coord_x, LLVMValueRef coord_y,
3104 LLVMValueRef coord_z,
3105 LLVMValueRef sample_index,
3106 LLVMValueRef fmask_desc_ptr)
3107 {
3108 LLVMValueRef fmask_load_address[4];
3109 LLVMValueRef res;
3110
3111 fmask_load_address[0] = coord_x;
3112 fmask_load_address[1] = coord_y;
3113 if (coord_z) {
3114 fmask_load_address[2] = coord_z;
3115 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3116 }
3117
3118 struct ac_image_args args = {0};
3119
3120 args.opcode = ac_image_load;
3121 args.da = coord_z ? true : false;
3122 args.resource = fmask_desc_ptr;
3123 args.dmask = 0xf;
3124 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
3125
3126 res = ac_build_image_opcode(&ctx->ac, &args);
3127
3128 res = to_integer(ctx, res);
3129 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3130 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3131
3132 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3133 res,
3134 ctx->i32zero, "");
3135
3136 LLVMValueRef sample_index4 =
3137 LLVMBuildMul(ctx->builder, sample_index, four, "");
3138 LLVMValueRef shifted_fmask =
3139 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3140 LLVMValueRef final_sample =
3141 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3142
3143 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3144 * resource descriptor is 0 (invalid),
3145 */
3146 LLVMValueRef fmask_desc =
3147 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3148 ctx->v8i32, "");
3149
3150 LLVMValueRef fmask_word1 =
3151 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3152 ctx->i32one, "");
3153
3154 LLVMValueRef word1_is_nonzero =
3155 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3156 fmask_word1, ctx->i32zero, "");
3157
3158 /* Replace the MSAA sample index. */
3159 sample_index =
3160 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3161 final_sample, sample_index, "");
3162 return sample_index;
3163 }
3164
3165 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
3166 nir_intrinsic_instr *instr)
3167 {
3168 const struct glsl_type *type = instr->variables[0]->var->type;
3169 if(instr->variables[0]->deref.child)
3170 type = instr->variables[0]->deref.child->type;
3171
3172 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3173 LLVMValueRef coords[4];
3174 LLVMValueRef masks[] = {
3175 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
3176 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
3177 };
3178 LLVMValueRef res;
3179 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
3180
3181 int count;
3182 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3183 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3184 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3185 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3186 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3187
3188 count = image_type_to_components_count(dim,
3189 glsl_sampler_type_is_array(type));
3190
3191 if (is_ms) {
3192 LLVMValueRef fmask_load_address[3];
3193 int chan;
3194
3195 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3196 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
3197 if (glsl_sampler_type_is_array(type))
3198 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
3199 else
3200 fmask_load_address[2] = NULL;
3201 if (add_frag_pos) {
3202 for (chan = 0; chan < 2; ++chan)
3203 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3204 }
3205 sample_index = adjust_sample_index_using_fmask(ctx,
3206 fmask_load_address[0],
3207 fmask_load_address[1],
3208 fmask_load_address[2],
3209 sample_index,
3210 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
3211 }
3212 if (count == 1) {
3213 if (instr->src[0].ssa->num_components)
3214 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3215 else
3216 res = src0;
3217 } else {
3218 int chan;
3219 if (is_ms)
3220 count--;
3221 for (chan = 0; chan < count; ++chan) {
3222 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
3223 }
3224
3225 if (add_frag_pos) {
3226 for (chan = 0; chan < count; ++chan)
3227 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3228 }
3229 if (is_ms) {
3230 coords[count] = sample_index;
3231 count++;
3232 }
3233
3234 if (count == 3) {
3235 coords[3] = LLVMGetUndef(ctx->i32);
3236 count = 4;
3237 }
3238 res = ac_build_gather_values(&ctx->ac, coords, count);
3239 }
3240 return res;
3241 }
3242
3243 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
3244 nir_intrinsic_instr *instr)
3245 {
3246 LLVMValueRef params[7];
3247 LLVMValueRef res;
3248 char intrinsic_name[64];
3249 const nir_variable *var = instr->variables[0]->var;
3250 const struct glsl_type *type = var->type;
3251 if(instr->variables[0]->deref.child)
3252 type = instr->variables[0]->deref.child->type;
3253
3254 type = glsl_without_array(type);
3255 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3256 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3257 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3258 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3259 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3260 params[3] = ctx->i1false; /* glc */
3261 params[4] = ctx->i1false; /* slc */
3262 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
3263 params, 5, 0);
3264
3265 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
3266 res = to_integer(ctx, res);
3267 } else {
3268 bool is_da = glsl_sampler_type_is_array(type) ||
3269 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3270 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3271 LLVMValueRef glc = ctx->i1false;
3272 LLVMValueRef slc = ctx->i1false;
3273
3274 params[0] = get_image_coords(ctx, instr);
3275 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3276 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3277 if (HAVE_LLVM <= 0x0309) {
3278 params[3] = ctx->i1false; /* r128 */
3279 params[4] = da;
3280 params[5] = glc;
3281 params[6] = slc;
3282 } else {
3283 LLVMValueRef lwe = ctx->i1false;
3284 params[3] = glc;
3285 params[4] = slc;
3286 params[5] = lwe;
3287 params[6] = da;
3288 }
3289
3290 ac_get_image_intr_name("llvm.amdgcn.image.load",
3291 ctx->v4f32, /* vdata */
3292 LLVMTypeOf(params[0]), /* coords */
3293 LLVMTypeOf(params[1]), /* rsrc */
3294 intrinsic_name, sizeof(intrinsic_name));
3295
3296 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
3297 params, 7, AC_FUNC_ATTR_READONLY);
3298 }
3299 return to_integer(ctx, res);
3300 }
3301
3302 static void visit_image_store(struct nir_to_llvm_context *ctx,
3303 nir_intrinsic_instr *instr)
3304 {
3305 LLVMValueRef params[8];
3306 char intrinsic_name[64];
3307 const nir_variable *var = instr->variables[0]->var;
3308 const struct glsl_type *type = glsl_without_array(var->type);
3309
3310 if (ctx->stage == MESA_SHADER_FRAGMENT)
3311 ctx->shader_info->fs.writes_memory = true;
3312
3313 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3314 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
3315 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3316 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3317 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3318 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3319 params[4] = ctx->i1false; /* glc */
3320 params[5] = ctx->i1false; /* slc */
3321 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
3322 params, 6, 0);
3323 } else {
3324 bool is_da = glsl_sampler_type_is_array(type) ||
3325 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3326 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3327 LLVMValueRef glc = ctx->i1false;
3328 LLVMValueRef slc = ctx->i1false;
3329
3330 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
3331 params[1] = get_image_coords(ctx, instr); /* coords */
3332 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3333 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3334 if (HAVE_LLVM <= 0x0309) {
3335 params[4] = ctx->i1false; /* r128 */
3336 params[5] = da;
3337 params[6] = glc;
3338 params[7] = slc;
3339 } else {
3340 LLVMValueRef lwe = ctx->i1false;
3341 params[4] = glc;
3342 params[5] = slc;
3343 params[6] = lwe;
3344 params[7] = da;
3345 }
3346
3347 ac_get_image_intr_name("llvm.amdgcn.image.store",
3348 LLVMTypeOf(params[0]), /* vdata */
3349 LLVMTypeOf(params[1]), /* coords */
3350 LLVMTypeOf(params[2]), /* rsrc */
3351 intrinsic_name, sizeof(intrinsic_name));
3352
3353 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
3354 params, 8, 0);
3355 }
3356
3357 }
3358
3359 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
3360 nir_intrinsic_instr *instr)
3361 {
3362 LLVMValueRef params[6];
3363 int param_count = 0;
3364 const nir_variable *var = instr->variables[0]->var;
3365
3366 const char *base_name = "llvm.amdgcn.image.atomic";
3367 const char *atomic_name;
3368 LLVMValueRef coords;
3369 char intrinsic_name[32], coords_type[8];
3370 const struct glsl_type *type = glsl_without_array(var->type);
3371
3372 if (ctx->stage == MESA_SHADER_FRAGMENT)
3373 ctx->shader_info->fs.writes_memory = true;
3374
3375 params[param_count++] = get_src(ctx, instr->src[2]);
3376 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3377 params[param_count++] = get_src(ctx, instr->src[3]);
3378
3379 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3380 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3381 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3382 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3383 params[param_count++] = ctx->i32zero; /* voffset */
3384 params[param_count++] = ctx->i1false; /* glc */
3385 params[param_count++] = ctx->i1false; /* slc */
3386 } else {
3387 bool da = glsl_sampler_type_is_array(type) ||
3388 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3389
3390 coords = params[param_count++] = get_image_coords(ctx, instr);
3391 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3392 params[param_count++] = ctx->i1false; /* r128 */
3393 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
3394 params[param_count++] = ctx->i1false; /* slc */
3395 }
3396
3397 switch (instr->intrinsic) {
3398 case nir_intrinsic_image_atomic_add:
3399 atomic_name = "add";
3400 break;
3401 case nir_intrinsic_image_atomic_min:
3402 atomic_name = "smin";
3403 break;
3404 case nir_intrinsic_image_atomic_max:
3405 atomic_name = "smax";
3406 break;
3407 case nir_intrinsic_image_atomic_and:
3408 atomic_name = "and";
3409 break;
3410 case nir_intrinsic_image_atomic_or:
3411 atomic_name = "or";
3412 break;
3413 case nir_intrinsic_image_atomic_xor:
3414 atomic_name = "xor";
3415 break;
3416 case nir_intrinsic_image_atomic_exchange:
3417 atomic_name = "swap";
3418 break;
3419 case nir_intrinsic_image_atomic_comp_swap:
3420 atomic_name = "cmpswap";
3421 break;
3422 default:
3423 abort();
3424 }
3425 build_int_type_name(LLVMTypeOf(coords),
3426 coords_type, sizeof(coords_type));
3427
3428 snprintf(intrinsic_name, sizeof(intrinsic_name),
3429 "%s.%s.%s", base_name, atomic_name, coords_type);
3430 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
3431 }
3432
3433 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
3434 nir_intrinsic_instr *instr)
3435 {
3436 LLVMValueRef res;
3437 const nir_variable *var = instr->variables[0]->var;
3438 const struct glsl_type *type = instr->variables[0]->var->type;
3439 bool da = glsl_sampler_type_is_array(var->type) ||
3440 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3441 if(instr->variables[0]->deref.child)
3442 type = instr->variables[0]->deref.child->type;
3443
3444 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3445 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
3446
3447 struct ac_image_args args = { 0 };
3448
3449 args.da = da;
3450 args.dmask = 0xf;
3451 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3452 args.opcode = ac_image_get_resinfo;
3453 args.addr = ctx->i32zero;
3454
3455 res = ac_build_image_opcode(&ctx->ac, &args);
3456
3457 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3458 glsl_sampler_type_is_array(type)) {
3459 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3460 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3461 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
3462 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3463 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
3464 }
3465 return res;
3466 }
3467
3468 #define NOOP_WAITCNT 0xf7f
3469 #define LGKM_CNT 0x07f
3470 #define VM_CNT 0xf70
3471
3472 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3473 unsigned simm16)
3474 {
3475 LLVMValueRef args[1] = {
3476 LLVMConstInt(ctx->i32, simm16, false),
3477 };
3478 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3479 ctx->voidt, args, 1, 0);
3480 }
3481
3482 static void emit_barrier(struct nir_to_llvm_context *ctx)
3483 {
3484 /* SI only (thanks to a hw bug workaround):
3485 * The real barrier instruction isn’t needed, because an entire patch
3486 * always fits into a single wave.
3487 */
3488 if (ctx->options->chip_class == SI &&
3489 ctx->stage == MESA_SHADER_TESS_CTRL) {
3490 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3491 return;
3492 }
3493 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3494 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3495 }
3496
3497 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3498 nir_intrinsic_instr *instr)
3499 {
3500 LLVMValueRef cond;
3501 ctx->shader_info->fs.can_discard = true;
3502
3503 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3504 get_src(ctx, instr->src[0]),
3505 ctx->i32zero, "");
3506
3507 cond = LLVMBuildSelect(ctx->builder, cond,
3508 LLVMConstReal(ctx->f32, -1.0f),
3509 ctx->f32zero, "");
3510 ac_build_kill(&ctx->ac, cond);
3511 }
3512
3513 static LLVMValueRef
3514 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3515 {
3516 LLVMValueRef result;
3517 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3518 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3519 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3520
3521 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3522 }
3523
3524 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3525 nir_intrinsic_instr *instr)
3526 {
3527 LLVMValueRef ptr, result;
3528 int idx = instr->variables[0]->var->data.driver_location;
3529 LLVMValueRef src = get_src(ctx, instr->src[0]);
3530 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3531
3532 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3533 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3534 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3535 ptr, src, src1,
3536 LLVMAtomicOrderingSequentiallyConsistent,
3537 LLVMAtomicOrderingSequentiallyConsistent,
3538 false);
3539 } else {
3540 LLVMAtomicRMWBinOp op;
3541 switch (instr->intrinsic) {
3542 case nir_intrinsic_var_atomic_add:
3543 op = LLVMAtomicRMWBinOpAdd;
3544 break;
3545 case nir_intrinsic_var_atomic_umin:
3546 op = LLVMAtomicRMWBinOpUMin;
3547 break;
3548 case nir_intrinsic_var_atomic_umax:
3549 op = LLVMAtomicRMWBinOpUMax;
3550 break;
3551 case nir_intrinsic_var_atomic_imin:
3552 op = LLVMAtomicRMWBinOpMin;
3553 break;
3554 case nir_intrinsic_var_atomic_imax:
3555 op = LLVMAtomicRMWBinOpMax;
3556 break;
3557 case nir_intrinsic_var_atomic_and:
3558 op = LLVMAtomicRMWBinOpAnd;
3559 break;
3560 case nir_intrinsic_var_atomic_or:
3561 op = LLVMAtomicRMWBinOpOr;
3562 break;
3563 case nir_intrinsic_var_atomic_xor:
3564 op = LLVMAtomicRMWBinOpXor;
3565 break;
3566 case nir_intrinsic_var_atomic_exchange:
3567 op = LLVMAtomicRMWBinOpXchg;
3568 break;
3569 default:
3570 return NULL;
3571 }
3572
3573 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
3574 LLVMAtomicOrderingSequentiallyConsistent,
3575 false);
3576 }
3577 return result;
3578 }
3579
3580 #define INTERP_CENTER 0
3581 #define INTERP_CENTROID 1
3582 #define INTERP_SAMPLE 2
3583
3584 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3585 enum glsl_interp_mode interp, unsigned location)
3586 {
3587 switch (interp) {
3588 case INTERP_MODE_FLAT:
3589 default:
3590 return NULL;
3591 case INTERP_MODE_SMOOTH:
3592 case INTERP_MODE_NONE:
3593 if (location == INTERP_CENTER)
3594 return ctx->persp_center;
3595 else if (location == INTERP_CENTROID)
3596 return ctx->persp_centroid;
3597 else if (location == INTERP_SAMPLE)
3598 return ctx->persp_sample;
3599 break;
3600 case INTERP_MODE_NOPERSPECTIVE:
3601 if (location == INTERP_CENTER)
3602 return ctx->linear_center;
3603 else if (location == INTERP_CENTROID)
3604 return ctx->linear_centroid;
3605 else if (location == INTERP_SAMPLE)
3606 return ctx->linear_sample;
3607 break;
3608 }
3609 return NULL;
3610 }
3611
3612 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3613 LLVMValueRef sample_id)
3614 {
3615 LLVMValueRef result;
3616 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3617
3618 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3619 const_array(ctx->v2f32, 64), "");
3620
3621 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3622 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3623
3624 return result;
3625 }
3626
3627 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3628 {
3629 LLVMValueRef values[2];
3630
3631 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
3632 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
3633 return ac_build_gather_values(&ctx->ac, values, 2);
3634 }
3635
3636 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3637 nir_intrinsic_instr *instr)
3638 {
3639 LLVMValueRef result[2];
3640 LLVMValueRef interp_param, attr_number;
3641 unsigned location;
3642 unsigned chan;
3643 LLVMValueRef src_c0, src_c1;
3644 LLVMValueRef src0;
3645 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3646 switch (instr->intrinsic) {
3647 case nir_intrinsic_interp_var_at_centroid:
3648 location = INTERP_CENTROID;
3649 break;
3650 case nir_intrinsic_interp_var_at_sample:
3651 case nir_intrinsic_interp_var_at_offset:
3652 location = INTERP_CENTER;
3653 src0 = get_src(ctx, instr->src[0]);
3654 break;
3655 default:
3656 break;
3657 }
3658
3659 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3660 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3661 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3662 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3663 LLVMValueRef sample_position;
3664 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3665
3666 /* fetch sample ID */
3667 sample_position = load_sample_position(ctx, src0);
3668
3669 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3670 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3671 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3672 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3673 }
3674 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3675 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3676
3677 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3678 LLVMValueRef ij_out[2];
3679 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3680
3681 /*
3682 * take the I then J parameters, and the DDX/Y for it, and
3683 * calculate the IJ inputs for the interpolator.
3684 * temp1 = ddx * offset/sample.x + I;
3685 * interp_param.I = ddy * offset/sample.y + temp1;
3686 * temp1 = ddx * offset/sample.x + J;
3687 * interp_param.J = ddy * offset/sample.y + temp1;
3688 */
3689 for (unsigned i = 0; i < 2; i++) {
3690 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3691 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3692 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3693 ddxy_out, ix_ll, "");
3694 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3695 ddxy_out, iy_ll, "");
3696 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3697 interp_param, ix_ll, "");
3698 LLVMValueRef temp1, temp2;
3699
3700 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3701 ctx->f32, "");
3702
3703 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3704 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3705
3706 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3707 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3708
3709 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3710 temp2, ctx->i32, "");
3711 }
3712 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3713
3714 }
3715
3716 for (chan = 0; chan < 2; chan++) {
3717 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3718
3719 if (interp_param) {
3720 interp_param = LLVMBuildBitCast(ctx->builder,
3721 interp_param, LLVMVectorType(ctx->f32, 2), "");
3722 LLVMValueRef i = LLVMBuildExtractElement(
3723 ctx->builder, interp_param, ctx->i32zero, "");
3724 LLVMValueRef j = LLVMBuildExtractElement(
3725 ctx->builder, interp_param, ctx->i32one, "");
3726
3727 result[chan] = ac_build_fs_interp(&ctx->ac,
3728 llvm_chan, attr_number,
3729 ctx->prim_mask, i, j);
3730 } else {
3731 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3732 LLVMConstInt(ctx->i32, 2, false),
3733 llvm_chan, attr_number,
3734 ctx->prim_mask);
3735 }
3736 }
3737 return ac_build_gather_values(&ctx->ac, result, 2);
3738 }
3739
3740 static void
3741 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3742 nir_intrinsic_instr *instr)
3743 {
3744 LLVMValueRef gs_next_vertex;
3745 LLVMValueRef can_emit, kill;
3746 int idx;
3747
3748 assert(instr->const_index[0] == 0);
3749 /* Write vertex attribute values to GSVS ring */
3750 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3751 ctx->gs_next_vertex,
3752 "");
3753
3754 /* If this thread has already emitted the declared maximum number of
3755 * vertices, kill it: excessive vertex emissions are not supposed to
3756 * have any effect, and GS threads have no externally observable
3757 * effects other than emitting vertices.
3758 */
3759 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3760 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3761
3762 kill = LLVMBuildSelect(ctx->builder, can_emit,
3763 LLVMConstReal(ctx->f32, 1.0f),
3764 LLVMConstReal(ctx->f32, -1.0f), "");
3765 ac_build_kill(&ctx->ac, kill);
3766
3767 /* loop num outputs */
3768 idx = 0;
3769 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3770 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3771 int length = 4;
3772 int slot = idx;
3773 int slot_inc = 1;
3774
3775 if (!(ctx->output_mask & (1ull << i)))
3776 continue;
3777
3778 if (i == VARYING_SLOT_CLIP_DIST0) {
3779 /* pack clip and cull into a single set of slots */
3780 length = ctx->num_output_clips + ctx->num_output_culls;
3781 if (length > 4)
3782 slot_inc = 2;
3783 }
3784 for (unsigned j = 0; j < length; j++) {
3785 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3786 out_ptr[j], "");
3787 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3788 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3789 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3790
3791 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3792
3793 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3794 out_val, 1,
3795 voffset, ctx->gs2vs_offset, 0,
3796 1, 1, true, true);
3797 }
3798 idx += slot_inc;
3799 }
3800
3801 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3802 ctx->i32one, "");
3803 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3804
3805 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3806 }
3807
3808 static void
3809 visit_end_primitive(struct nir_to_llvm_context *ctx,
3810 nir_intrinsic_instr *instr)
3811 {
3812 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3813 }
3814
3815 static LLVMValueRef
3816 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3817 nir_intrinsic_instr *instr)
3818 {
3819 LLVMValueRef coord[4] = {
3820 ctx->tes_u,
3821 ctx->tes_v,
3822 ctx->f32zero,
3823 ctx->f32zero,
3824 };
3825
3826 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3827 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3828 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3829
3830 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3831 return LLVMBuildBitCast(ctx->builder, result,
3832 get_def_type(ctx, &instr->dest.ssa), "");
3833 }
3834
3835 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3836 nir_intrinsic_instr *instr)
3837 {
3838 LLVMValueRef result = NULL;
3839
3840 switch (instr->intrinsic) {
3841 case nir_intrinsic_load_work_group_id: {
3842 result = ctx->workgroup_ids;
3843 break;
3844 }
3845 case nir_intrinsic_load_base_vertex: {
3846 result = ctx->base_vertex;
3847 break;
3848 }
3849 case nir_intrinsic_load_vertex_id_zero_base: {
3850 result = ctx->vertex_id;
3851 break;
3852 }
3853 case nir_intrinsic_load_local_invocation_id: {
3854 result = ctx->local_invocation_ids;
3855 break;
3856 }
3857 case nir_intrinsic_load_base_instance:
3858 result = ctx->start_instance;
3859 break;
3860 case nir_intrinsic_load_draw_id:
3861 result = ctx->draw_index;
3862 break;
3863 case nir_intrinsic_load_invocation_id:
3864 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3865 result = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
3866 else
3867 result = ctx->gs_invocation_id;
3868 break;
3869 case nir_intrinsic_load_primitive_id:
3870 if (ctx->stage == MESA_SHADER_GEOMETRY)
3871 result = ctx->gs_prim_id;
3872 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
3873 result = ctx->tcs_patch_id;
3874 else if (ctx->stage == MESA_SHADER_TESS_EVAL)
3875 result = ctx->tes_patch_id;
3876 else
3877 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3878 break;
3879 case nir_intrinsic_load_sample_id:
3880 ctx->shader_info->fs.force_persample = true;
3881 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3882 break;
3883 case nir_intrinsic_load_sample_pos:
3884 ctx->shader_info->fs.force_persample = true;
3885 result = load_sample_pos(ctx);
3886 break;
3887 case nir_intrinsic_load_sample_mask_in:
3888 result = ctx->sample_coverage;
3889 break;
3890 case nir_intrinsic_load_front_face:
3891 result = ctx->front_face;
3892 break;
3893 case nir_intrinsic_load_instance_id:
3894 result = ctx->instance_id;
3895 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3896 ctx->shader_info->vs.vgpr_comp_cnt);
3897 break;
3898 case nir_intrinsic_load_num_work_groups:
3899 result = ctx->num_work_groups;
3900 break;
3901 case nir_intrinsic_load_local_invocation_index:
3902 result = visit_load_local_invocation_index(ctx);
3903 break;
3904 case nir_intrinsic_load_push_constant:
3905 result = visit_load_push_constant(ctx, instr);
3906 break;
3907 case nir_intrinsic_vulkan_resource_index:
3908 result = visit_vulkan_resource_index(ctx, instr);
3909 break;
3910 case nir_intrinsic_store_ssbo:
3911 visit_store_ssbo(ctx, instr);
3912 break;
3913 case nir_intrinsic_load_ssbo:
3914 result = visit_load_buffer(ctx, instr);
3915 break;
3916 case nir_intrinsic_ssbo_atomic_add:
3917 case nir_intrinsic_ssbo_atomic_imin:
3918 case nir_intrinsic_ssbo_atomic_umin:
3919 case nir_intrinsic_ssbo_atomic_imax:
3920 case nir_intrinsic_ssbo_atomic_umax:
3921 case nir_intrinsic_ssbo_atomic_and:
3922 case nir_intrinsic_ssbo_atomic_or:
3923 case nir_intrinsic_ssbo_atomic_xor:
3924 case nir_intrinsic_ssbo_atomic_exchange:
3925 case nir_intrinsic_ssbo_atomic_comp_swap:
3926 result = visit_atomic_ssbo(ctx, instr);
3927 break;
3928 case nir_intrinsic_load_ubo:
3929 result = visit_load_ubo_buffer(ctx, instr);
3930 break;
3931 case nir_intrinsic_get_buffer_size:
3932 result = visit_get_buffer_size(ctx, instr);
3933 break;
3934 case nir_intrinsic_load_var:
3935 result = visit_load_var(ctx, instr);
3936 break;
3937 case nir_intrinsic_store_var:
3938 visit_store_var(ctx, instr);
3939 break;
3940 case nir_intrinsic_image_load:
3941 result = visit_image_load(ctx, instr);
3942 break;
3943 case nir_intrinsic_image_store:
3944 visit_image_store(ctx, instr);
3945 break;
3946 case nir_intrinsic_image_atomic_add:
3947 case nir_intrinsic_image_atomic_min:
3948 case nir_intrinsic_image_atomic_max:
3949 case nir_intrinsic_image_atomic_and:
3950 case nir_intrinsic_image_atomic_or:
3951 case nir_intrinsic_image_atomic_xor:
3952 case nir_intrinsic_image_atomic_exchange:
3953 case nir_intrinsic_image_atomic_comp_swap:
3954 result = visit_image_atomic(ctx, instr);
3955 break;
3956 case nir_intrinsic_image_size:
3957 result = visit_image_size(ctx, instr);
3958 break;
3959 case nir_intrinsic_discard:
3960 ctx->shader_info->fs.can_discard = true;
3961 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3962 ctx->voidt,
3963 NULL, 0, AC_FUNC_ATTR_LEGACY);
3964 break;
3965 case nir_intrinsic_discard_if:
3966 emit_discard_if(ctx, instr);
3967 break;
3968 case nir_intrinsic_memory_barrier:
3969 emit_waitcnt(ctx, VM_CNT);
3970 break;
3971 case nir_intrinsic_barrier:
3972 emit_barrier(ctx);
3973 break;
3974 case nir_intrinsic_var_atomic_add:
3975 case nir_intrinsic_var_atomic_imin:
3976 case nir_intrinsic_var_atomic_umin:
3977 case nir_intrinsic_var_atomic_imax:
3978 case nir_intrinsic_var_atomic_umax:
3979 case nir_intrinsic_var_atomic_and:
3980 case nir_intrinsic_var_atomic_or:
3981 case nir_intrinsic_var_atomic_xor:
3982 case nir_intrinsic_var_atomic_exchange:
3983 case nir_intrinsic_var_atomic_comp_swap:
3984 result = visit_var_atomic(ctx, instr);
3985 break;
3986 case nir_intrinsic_interp_var_at_centroid:
3987 case nir_intrinsic_interp_var_at_sample:
3988 case nir_intrinsic_interp_var_at_offset:
3989 result = visit_interp(ctx, instr);
3990 break;
3991 case nir_intrinsic_emit_vertex:
3992 visit_emit_vertex(ctx, instr);
3993 break;
3994 case nir_intrinsic_end_primitive:
3995 visit_end_primitive(ctx, instr);
3996 break;
3997 case nir_intrinsic_load_tess_coord:
3998 result = visit_load_tess_coord(ctx, instr);
3999 break;
4000 case nir_intrinsic_load_patch_vertices_in:
4001 result = LLVMConstInt(ctx->i32, ctx->options->key.tcs.input_vertices, false);
4002 break;
4003 default:
4004 fprintf(stderr, "Unknown intrinsic: ");
4005 nir_print_instr(&instr->instr, stderr);
4006 fprintf(stderr, "\n");
4007 break;
4008 }
4009 if (result) {
4010 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4011 }
4012 }
4013
4014 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
4015 nir_deref_var *deref,
4016 enum desc_type desc_type)
4017 {
4018 unsigned desc_set = deref->var->data.descriptor_set;
4019 LLVMValueRef list = ctx->descriptor_sets[desc_set];
4020 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4021 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
4022 unsigned offset = binding->offset;
4023 unsigned stride = binding->size;
4024 unsigned type_size;
4025 LLVMBuilderRef builder = ctx->builder;
4026 LLVMTypeRef type;
4027 LLVMValueRef index = NULL;
4028 unsigned constant_index = 0;
4029
4030 assert(deref->var->data.binding < layout->binding_count);
4031
4032 switch (desc_type) {
4033 case DESC_IMAGE:
4034 type = ctx->v8i32;
4035 type_size = 32;
4036 break;
4037 case DESC_FMASK:
4038 type = ctx->v8i32;
4039 offset += 32;
4040 type_size = 32;
4041 break;
4042 case DESC_SAMPLER:
4043 type = ctx->v4i32;
4044 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4045 offset += 64;
4046
4047 type_size = 16;
4048 break;
4049 case DESC_BUFFER:
4050 type = ctx->v4i32;
4051 type_size = 16;
4052 break;
4053 default:
4054 unreachable("invalid desc_type\n");
4055 }
4056
4057 if (deref->deref.child) {
4058 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
4059
4060 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4061 offset += child->base_offset * stride;
4062 if (child->deref_array_type == nir_deref_array_type_indirect) {
4063 index = get_src(ctx, child->indirect);
4064 }
4065
4066 constant_index = child->base_offset;
4067 }
4068 if (desc_type == DESC_SAMPLER && binding->immutable_samplers_offset &&
4069 (!index || binding->immutable_samplers_equal)) {
4070 if (binding->immutable_samplers_equal)
4071 constant_index = 0;
4072
4073 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4074
4075 LLVMValueRef constants[] = {
4076 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4077 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4078 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4079 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4080 };
4081 return ac_build_gather_values(&ctx->ac, constants, 4);
4082 }
4083
4084 assert(stride % type_size == 0);
4085
4086 if (!index)
4087 index = ctx->i32zero;
4088
4089 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4090
4091 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4092 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4093
4094 return ac_build_indexed_load_const(&ctx->ac, list, index);
4095 }
4096
4097 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
4098 struct ac_image_args *args,
4099 nir_tex_instr *instr,
4100 nir_texop op,
4101 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4102 LLVMValueRef *param, unsigned count,
4103 unsigned dmask)
4104 {
4105 unsigned is_rect = 0;
4106 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4107
4108 if (op == nir_texop_lod)
4109 da = false;
4110 /* Pad to power of two vector */
4111 while (count < util_next_power_of_two(count))
4112 param[count++] = LLVMGetUndef(ctx->i32);
4113
4114 if (count > 1)
4115 args->addr = ac_build_gather_values(&ctx->ac, param, count);
4116 else
4117 args->addr = param[0];
4118
4119 args->resource = res_ptr;
4120 args->sampler = samp_ptr;
4121
4122 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4123 args->addr = param[0];
4124 return;
4125 }
4126
4127 args->dmask = dmask;
4128 args->unorm = is_rect;
4129 args->da = da;
4130 }
4131
4132 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4133 *
4134 * SI-CI:
4135 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4136 * filtering manually. The driver sets img7 to a mask clearing
4137 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4138 * s_and_b32 samp0, samp0, img7
4139 *
4140 * VI:
4141 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4142 */
4143 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
4144 LLVMValueRef res, LLVMValueRef samp)
4145 {
4146 LLVMBuilderRef builder = ctx->builder;
4147 LLVMValueRef img7, samp0;
4148
4149 if (ctx->options->chip_class >= VI)
4150 return samp;
4151
4152 img7 = LLVMBuildExtractElement(builder, res,
4153 LLVMConstInt(ctx->i32, 7, 0), "");
4154 samp0 = LLVMBuildExtractElement(builder, samp,
4155 LLVMConstInt(ctx->i32, 0, 0), "");
4156 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4157 return LLVMBuildInsertElement(builder, samp, samp0,
4158 LLVMConstInt(ctx->i32, 0, 0), "");
4159 }
4160
4161 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
4162 nir_tex_instr *instr,
4163 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4164 LLVMValueRef *fmask_ptr)
4165 {
4166 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4167 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
4168 else
4169 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
4170 if (samp_ptr) {
4171 if (instr->sampler)
4172 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
4173 else
4174 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
4175 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4176 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4177 }
4178 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4179 instr->op == nir_texop_samples_identical))
4180 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
4181 }
4182
4183 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
4184 LLVMValueRef coord)
4185 {
4186 coord = to_float(ctx, coord);
4187 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4188 coord = to_integer(ctx, coord);
4189 return coord;
4190 }
4191
4192 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
4193 {
4194 LLVMValueRef result = NULL;
4195 struct ac_image_args args = { 0 };
4196 unsigned dmask = 0xf;
4197 LLVMValueRef address[16];
4198 LLVMValueRef coords[5];
4199 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4200 LLVMValueRef bias = NULL, offsets = NULL;
4201 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4202 LLVMValueRef ddx = NULL, ddy = NULL;
4203 LLVMValueRef derivs[6];
4204 unsigned chan, count = 0;
4205 unsigned const_src = 0, num_deriv_comp = 0;
4206
4207 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4208
4209 for (unsigned i = 0; i < instr->num_srcs; i++) {
4210 switch (instr->src[i].src_type) {
4211 case nir_tex_src_coord:
4212 coord = get_src(ctx, instr->src[i].src);
4213 break;
4214 case nir_tex_src_projector:
4215 break;
4216 case nir_tex_src_comparator:
4217 comparator = get_src(ctx, instr->src[i].src);
4218 break;
4219 case nir_tex_src_offset:
4220 offsets = get_src(ctx, instr->src[i].src);
4221 const_src = i;
4222 break;
4223 case nir_tex_src_bias:
4224 bias = get_src(ctx, instr->src[i].src);
4225 break;
4226 case nir_tex_src_lod:
4227 lod = get_src(ctx, instr->src[i].src);
4228 break;
4229 case nir_tex_src_ms_index:
4230 sample_index = get_src(ctx, instr->src[i].src);
4231 break;
4232 case nir_tex_src_ms_mcs:
4233 break;
4234 case nir_tex_src_ddx:
4235 ddx = get_src(ctx, instr->src[i].src);
4236 num_deriv_comp = instr->src[i].src.ssa->num_components;
4237 break;
4238 case nir_tex_src_ddy:
4239 ddy = get_src(ctx, instr->src[i].src);
4240 break;
4241 case nir_tex_src_texture_offset:
4242 case nir_tex_src_sampler_offset:
4243 case nir_tex_src_plane:
4244 default:
4245 break;
4246 }
4247 }
4248
4249 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4250 result = get_buffer_size(ctx, res_ptr, true);
4251 goto write_result;
4252 }
4253
4254 if (instr->op == nir_texop_texture_samples) {
4255 LLVMValueRef res, samples, is_msaa;
4256 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
4257 samples = LLVMBuildExtractElement(ctx->builder, res,
4258 LLVMConstInt(ctx->i32, 3, false), "");
4259 is_msaa = LLVMBuildLShr(ctx->builder, samples,
4260 LLVMConstInt(ctx->i32, 28, false), "");
4261 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
4262 LLVMConstInt(ctx->i32, 0xe, false), "");
4263 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
4264 LLVMConstInt(ctx->i32, 0xe, false), "");
4265
4266 samples = LLVMBuildLShr(ctx->builder, samples,
4267 LLVMConstInt(ctx->i32, 16, false), "");
4268 samples = LLVMBuildAnd(ctx->builder, samples,
4269 LLVMConstInt(ctx->i32, 0xf, false), "");
4270 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
4271 samples, "");
4272 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
4273 ctx->i32one, "");
4274 result = samples;
4275 goto write_result;
4276 }
4277
4278 if (coord)
4279 for (chan = 0; chan < instr->coord_components; chan++)
4280 coords[chan] = llvm_extract_elem(ctx, coord, chan);
4281
4282 if (offsets && instr->op != nir_texop_txf) {
4283 LLVMValueRef offset[3], pack;
4284 for (chan = 0; chan < 3; ++chan)
4285 offset[chan] = ctx->i32zero;
4286
4287 args.offset = true;
4288 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4289 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
4290 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
4291 LLVMConstInt(ctx->i32, 0x3f, false), "");
4292 if (chan)
4293 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
4294 LLVMConstInt(ctx->i32, chan * 8, false), "");
4295 }
4296 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
4297 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
4298 address[count++] = pack;
4299
4300 }
4301 /* pack LOD bias value */
4302 if (instr->op == nir_texop_txb && bias) {
4303 address[count++] = bias;
4304 }
4305
4306 /* Pack depth comparison value */
4307 if (instr->is_shadow && comparator) {
4308 address[count++] = llvm_extract_elem(ctx, comparator, 0);
4309 }
4310
4311 /* pack derivatives */
4312 if (ddx || ddy) {
4313 switch (instr->sampler_dim) {
4314 case GLSL_SAMPLER_DIM_3D:
4315 case GLSL_SAMPLER_DIM_CUBE:
4316 num_deriv_comp = 3;
4317 break;
4318 case GLSL_SAMPLER_DIM_2D:
4319 default:
4320 num_deriv_comp = 2;
4321 break;
4322 case GLSL_SAMPLER_DIM_1D:
4323 num_deriv_comp = 1;
4324 break;
4325 }
4326
4327 for (unsigned i = 0; i < num_deriv_comp; i++) {
4328 derivs[i] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
4329 derivs[num_deriv_comp + i] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
4330 }
4331 }
4332
4333 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4334 if (instr->is_array && instr->op != nir_texop_lod)
4335 coords[3] = apply_round_slice(ctx, coords[3]);
4336 for (chan = 0; chan < instr->coord_components; chan++)
4337 coords[chan] = to_float(ctx, coords[chan]);
4338 if (instr->coord_components == 3)
4339 coords[3] = LLVMGetUndef(ctx->f32);
4340 ac_prepare_cube_coords(&ctx->ac,
4341 instr->op == nir_texop_txd, instr->is_array,
4342 coords, derivs);
4343 if (num_deriv_comp)
4344 num_deriv_comp--;
4345 }
4346
4347 if (ddx || ddy) {
4348 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4349 address[count++] = derivs[i];
4350 }
4351
4352 /* Pack texture coordinates */
4353 if (coord) {
4354 address[count++] = coords[0];
4355 if (instr->coord_components > 1) {
4356 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4357 coords[1] = apply_round_slice(ctx, coords[1]);
4358 }
4359 address[count++] = coords[1];
4360 }
4361 if (instr->coord_components > 2) {
4362 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4363 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4364 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4365 instr->op != nir_texop_txf) {
4366 coords[2] = apply_round_slice(ctx, coords[2]);
4367 }
4368 address[count++] = coords[2];
4369 }
4370 }
4371
4372 /* Pack LOD */
4373 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
4374 address[count++] = lod;
4375 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4376 address[count++] = sample_index;
4377 } else if(instr->op == nir_texop_txs) {
4378 count = 0;
4379 if (lod)
4380 address[count++] = lod;
4381 else
4382 address[count++] = ctx->i32zero;
4383 }
4384
4385 for (chan = 0; chan < count; chan++) {
4386 address[chan] = LLVMBuildBitCast(ctx->builder,
4387 address[chan], ctx->i32, "");
4388 }
4389
4390 if (instr->op == nir_texop_samples_identical) {
4391 LLVMValueRef txf_address[4];
4392 struct ac_image_args txf_args = { 0 };
4393 unsigned txf_count = count;
4394 memcpy(txf_address, address, sizeof(txf_address));
4395
4396 if (!instr->is_array)
4397 txf_address[2] = ctx->i32zero;
4398 txf_address[3] = ctx->i32zero;
4399
4400 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
4401 fmask_ptr, NULL,
4402 txf_address, txf_count, 0xf);
4403
4404 result = build_tex_intrinsic(ctx, instr, &txf_args);
4405
4406 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4407 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
4408 goto write_result;
4409 }
4410
4411 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4412 instr->op != nir_texop_txs) {
4413 unsigned sample_chan = instr->is_array ? 3 : 2;
4414 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
4415 address[0],
4416 address[1],
4417 instr->is_array ? address[2] : NULL,
4418 address[sample_chan],
4419 fmask_ptr);
4420 }
4421
4422 if (offsets && instr->op == nir_texop_txf) {
4423 nir_const_value *const_offset =
4424 nir_src_as_const_value(instr->src[const_src].src);
4425 int num_offsets = instr->src[const_src].src.ssa->num_components;
4426 assert(const_offset);
4427 num_offsets = MIN2(num_offsets, instr->coord_components);
4428 if (num_offsets > 2)
4429 address[2] = LLVMBuildAdd(ctx->builder,
4430 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
4431 if (num_offsets > 1)
4432 address[1] = LLVMBuildAdd(ctx->builder,
4433 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
4434 address[0] = LLVMBuildAdd(ctx->builder,
4435 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
4436
4437 }
4438
4439 /* TODO TG4 support */
4440 if (instr->op == nir_texop_tg4) {
4441 if (instr->is_shadow)
4442 dmask = 1;
4443 else
4444 dmask = 1 << instr->component;
4445 }
4446 set_tex_fetch_args(ctx, &args, instr, instr->op,
4447 res_ptr, samp_ptr, address, count, dmask);
4448
4449 result = build_tex_intrinsic(ctx, instr, &args);
4450
4451 if (instr->op == nir_texop_query_levels)
4452 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
4453 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4454 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4455 else if (instr->op == nir_texop_txs &&
4456 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4457 instr->is_array) {
4458 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
4459 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
4460 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
4461 z = LLVMBuildSDiv(ctx->builder, z, six, "");
4462 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
4463 } else if (instr->dest.ssa.num_components != 4)
4464 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
4465
4466 write_result:
4467 if (result) {
4468 assert(instr->dest.is_ssa);
4469 result = to_integer(ctx, result);
4470 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4471 }
4472 }
4473
4474
4475 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
4476 {
4477 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4478 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
4479
4480 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4481 _mesa_hash_table_insert(ctx->phis, instr, result);
4482 }
4483
4484 static void visit_post_phi(struct nir_to_llvm_context *ctx,
4485 nir_phi_instr *instr,
4486 LLVMValueRef llvm_phi)
4487 {
4488 nir_foreach_phi_src(src, instr) {
4489 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4490 LLVMValueRef llvm_src = get_src(ctx, src->src);
4491
4492 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4493 }
4494 }
4495
4496 static void phi_post_pass(struct nir_to_llvm_context *ctx)
4497 {
4498 struct hash_entry *entry;
4499 hash_table_foreach(ctx->phis, entry) {
4500 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4501 (LLVMValueRef)entry->data);
4502 }
4503 }
4504
4505
4506 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
4507 nir_ssa_undef_instr *instr)
4508 {
4509 unsigned num_components = instr->def.num_components;
4510 LLVMValueRef undef;
4511
4512 if (num_components == 1)
4513 undef = LLVMGetUndef(ctx->i32);
4514 else {
4515 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
4516 }
4517 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4518 }
4519
4520 static void visit_jump(struct nir_to_llvm_context *ctx,
4521 nir_jump_instr *instr)
4522 {
4523 switch (instr->type) {
4524 case nir_jump_break:
4525 LLVMBuildBr(ctx->builder, ctx->break_block);
4526 LLVMClearInsertionPosition(ctx->builder);
4527 break;
4528 case nir_jump_continue:
4529 LLVMBuildBr(ctx->builder, ctx->continue_block);
4530 LLVMClearInsertionPosition(ctx->builder);
4531 break;
4532 default:
4533 fprintf(stderr, "Unknown NIR jump instr: ");
4534 nir_print_instr(&instr->instr, stderr);
4535 fprintf(stderr, "\n");
4536 abort();
4537 }
4538 }
4539
4540 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4541 struct exec_list *list);
4542
4543 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
4544 {
4545 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
4546 nir_foreach_instr(instr, block)
4547 {
4548 switch (instr->type) {
4549 case nir_instr_type_alu:
4550 visit_alu(ctx, nir_instr_as_alu(instr));
4551 break;
4552 case nir_instr_type_load_const:
4553 visit_load_const(ctx, nir_instr_as_load_const(instr));
4554 break;
4555 case nir_instr_type_intrinsic:
4556 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4557 break;
4558 case nir_instr_type_tex:
4559 visit_tex(ctx, nir_instr_as_tex(instr));
4560 break;
4561 case nir_instr_type_phi:
4562 visit_phi(ctx, nir_instr_as_phi(instr));
4563 break;
4564 case nir_instr_type_ssa_undef:
4565 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4566 break;
4567 case nir_instr_type_jump:
4568 visit_jump(ctx, nir_instr_as_jump(instr));
4569 break;
4570 default:
4571 fprintf(stderr, "Unknown NIR instr type: ");
4572 nir_print_instr(instr, stderr);
4573 fprintf(stderr, "\n");
4574 abort();
4575 }
4576 }
4577
4578 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4579 }
4580
4581 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
4582 {
4583 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4584
4585 LLVMBasicBlockRef merge_block =
4586 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4587 LLVMBasicBlockRef if_block =
4588 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4589 LLVMBasicBlockRef else_block = merge_block;
4590 if (!exec_list_is_empty(&if_stmt->else_list))
4591 else_block = LLVMAppendBasicBlockInContext(
4592 ctx->context, ctx->main_function, "");
4593
4594 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
4595 LLVMConstInt(ctx->i32, 0, false), "");
4596 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
4597
4598 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
4599 visit_cf_list(ctx, &if_stmt->then_list);
4600 if (LLVMGetInsertBlock(ctx->builder))
4601 LLVMBuildBr(ctx->builder, merge_block);
4602
4603 if (!exec_list_is_empty(&if_stmt->else_list)) {
4604 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
4605 visit_cf_list(ctx, &if_stmt->else_list);
4606 if (LLVMGetInsertBlock(ctx->builder))
4607 LLVMBuildBr(ctx->builder, merge_block);
4608 }
4609
4610 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
4611 }
4612
4613 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
4614 {
4615 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4616 LLVMBasicBlockRef break_parent = ctx->break_block;
4617
4618 ctx->continue_block =
4619 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4620 ctx->break_block =
4621 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4622
4623 LLVMBuildBr(ctx->builder, ctx->continue_block);
4624 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4625 visit_cf_list(ctx, &loop->body);
4626
4627 if (LLVMGetInsertBlock(ctx->builder))
4628 LLVMBuildBr(ctx->builder, ctx->continue_block);
4629 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4630
4631 ctx->continue_block = continue_parent;
4632 ctx->break_block = break_parent;
4633 }
4634
4635 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4636 struct exec_list *list)
4637 {
4638 foreach_list_typed(nir_cf_node, node, node, list)
4639 {
4640 switch (node->type) {
4641 case nir_cf_node_block:
4642 visit_block(ctx, nir_cf_node_as_block(node));
4643 break;
4644
4645 case nir_cf_node_if:
4646 visit_if(ctx, nir_cf_node_as_if(node));
4647 break;
4648
4649 case nir_cf_node_loop:
4650 visit_loop(ctx, nir_cf_node_as_loop(node));
4651 break;
4652
4653 default:
4654 assert(0);
4655 }
4656 }
4657 }
4658
4659 static void
4660 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4661 struct nir_variable *variable)
4662 {
4663 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4664 LLVMValueRef t_offset;
4665 LLVMValueRef t_list;
4666 LLVMValueRef input;
4667 LLVMValueRef buffer_index;
4668 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4669 int idx = variable->data.location;
4670 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4671
4672 variable->data.driver_location = idx * 4;
4673
4674 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4675 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4676 ctx->start_instance, "");
4677 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4678 ctx->shader_info->vs.vgpr_comp_cnt);
4679 } else
4680 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4681 ctx->base_vertex, "");
4682
4683 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4684 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4685
4686 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4687
4688 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4689 buffer_index,
4690 LLVMConstInt(ctx->i32, 0, false),
4691 true);
4692
4693 for (unsigned chan = 0; chan < 4; chan++) {
4694 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4695 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4696 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4697 input, llvm_chan, ""));
4698 }
4699 }
4700 }
4701
4702 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4703 unsigned attr,
4704 LLVMValueRef interp_param,
4705 LLVMValueRef prim_mask,
4706 LLVMValueRef result[4])
4707 {
4708 LLVMValueRef attr_number;
4709 unsigned chan;
4710 LLVMValueRef i, j;
4711 bool interp = interp_param != NULL;
4712
4713 attr_number = LLVMConstInt(ctx->i32, attr, false);
4714
4715 /* fs.constant returns the param from the middle vertex, so it's not
4716 * really useful for flat shading. It's meant to be used for custom
4717 * interpolation (but the intrinsic can't fetch from the other two
4718 * vertices).
4719 *
4720 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4721 * to do the right thing. The only reason we use fs.constant is that
4722 * fs.interp cannot be used on integers, because they can be equal
4723 * to NaN.
4724 */
4725 if (interp) {
4726 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4727 LLVMVectorType(ctx->f32, 2), "");
4728
4729 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4730 ctx->i32zero, "");
4731 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4732 ctx->i32one, "");
4733 }
4734
4735 for (chan = 0; chan < 4; chan++) {
4736 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4737
4738 if (interp) {
4739 result[chan] = ac_build_fs_interp(&ctx->ac,
4740 llvm_chan,
4741 attr_number,
4742 prim_mask, i, j);
4743 } else {
4744 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4745 LLVMConstInt(ctx->i32, 2, false),
4746 llvm_chan,
4747 attr_number,
4748 prim_mask);
4749 }
4750 }
4751 }
4752
4753 static void
4754 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4755 struct nir_variable *variable)
4756 {
4757 int idx = variable->data.location;
4758 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4759 LLVMValueRef interp;
4760
4761 variable->data.driver_location = idx * 4;
4762 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4763
4764 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4765 unsigned interp_type;
4766 if (variable->data.sample) {
4767 interp_type = INTERP_SAMPLE;
4768 ctx->shader_info->fs.force_persample = true;
4769 } else if (variable->data.centroid)
4770 interp_type = INTERP_CENTROID;
4771 else
4772 interp_type = INTERP_CENTER;
4773
4774 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4775 } else
4776 interp = NULL;
4777
4778 for (unsigned i = 0; i < attrib_count; ++i)
4779 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4780
4781 }
4782
4783 static void
4784 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4785 struct nir_variable *variable)
4786 {
4787 switch (ctx->stage) {
4788 case MESA_SHADER_VERTEX:
4789 handle_vs_input_decl(ctx, variable);
4790 break;
4791 case MESA_SHADER_FRAGMENT:
4792 handle_fs_input_decl(ctx, variable);
4793 break;
4794 default:
4795 break;
4796 }
4797
4798 }
4799
4800 static void
4801 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4802 struct nir_shader *nir)
4803 {
4804 unsigned index = 0;
4805 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4806 LLVMValueRef interp_param;
4807 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4808
4809 if (!(ctx->input_mask & (1ull << i)))
4810 continue;
4811
4812 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4813 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4814 interp_param = *inputs;
4815 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4816 inputs);
4817
4818 if (!interp_param)
4819 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4820 ++index;
4821 } else if (i == VARYING_SLOT_POS) {
4822 for(int i = 0; i < 3; ++i)
4823 inputs[i] = ctx->frag_pos[i];
4824
4825 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4826 }
4827 }
4828 ctx->shader_info->fs.num_interp = index;
4829 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4830 ctx->shader_info->fs.has_pcoord = true;
4831 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4832 ctx->shader_info->fs.prim_id_input = true;
4833 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4834 ctx->shader_info->fs.layer_input = true;
4835 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4836 }
4837
4838 static LLVMValueRef
4839 ac_build_alloca(struct nir_to_llvm_context *ctx,
4840 LLVMTypeRef type,
4841 const char *name)
4842 {
4843 LLVMBuilderRef builder = ctx->builder;
4844 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4845 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4846 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4847 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4848 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4849 LLVMValueRef res;
4850
4851 if (first_instr) {
4852 LLVMPositionBuilderBefore(first_builder, first_instr);
4853 } else {
4854 LLVMPositionBuilderAtEnd(first_builder, first_block);
4855 }
4856
4857 res = LLVMBuildAlloca(first_builder, type, name);
4858 LLVMBuildStore(builder, LLVMConstNull(type), res);
4859
4860 LLVMDisposeBuilder(first_builder);
4861
4862 return res;
4863 }
4864
4865 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4866 LLVMTypeRef type,
4867 const char *name)
4868 {
4869 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4870 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4871 return ptr;
4872 }
4873
4874 static void
4875 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4876 struct nir_variable *variable)
4877 {
4878 int idx = variable->data.location + variable->data.index;
4879 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4880 uint64_t mask_attribs;
4881 variable->data.driver_location = idx * 4;
4882
4883 /* tess ctrl has it's own load/store paths for outputs */
4884 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4885 return;
4886
4887 mask_attribs = ((1ull << attrib_count) - 1) << idx;
4888 if (ctx->stage == MESA_SHADER_VERTEX ||
4889 ctx->stage == MESA_SHADER_TESS_EVAL ||
4890 ctx->stage == MESA_SHADER_GEOMETRY) {
4891 if (idx == VARYING_SLOT_CLIP_DIST0) {
4892 int length = ctx->num_output_clips + ctx->num_output_culls;
4893 if (ctx->stage == MESA_SHADER_VERTEX) {
4894 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4895 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4896 }
4897 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4898 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4899 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4900 }
4901
4902 if (length > 4)
4903 attrib_count = 2;
4904 else
4905 attrib_count = 1;
4906 mask_attribs = 1ull << idx;
4907 }
4908 }
4909
4910 for (unsigned i = 0; i < attrib_count; ++i) {
4911 for (unsigned chan = 0; chan < 4; chan++) {
4912 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4913 si_build_alloca_undef(ctx, ctx->f32, "");
4914 }
4915 }
4916 ctx->output_mask |= mask_attribs;
4917 }
4918
4919 static void
4920 setup_locals(struct nir_to_llvm_context *ctx,
4921 struct nir_function *func)
4922 {
4923 int i, j;
4924 ctx->num_locals = 0;
4925 nir_foreach_variable(variable, &func->impl->locals) {
4926 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4927 variable->data.driver_location = ctx->num_locals * 4;
4928 ctx->num_locals += attrib_count;
4929 }
4930 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4931 if (!ctx->locals)
4932 return;
4933
4934 for (i = 0; i < ctx->num_locals; i++) {
4935 for (j = 0; j < 4; j++) {
4936 ctx->locals[i * 4 + j] =
4937 si_build_alloca_undef(ctx, ctx->f32, "temp");
4938 }
4939 }
4940 }
4941
4942 static LLVMValueRef
4943 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4944 {
4945 v = to_float(ctx, v);
4946 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4947 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4948 }
4949
4950
4951 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4952 LLVMValueRef src0, LLVMValueRef src1)
4953 {
4954 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4955 LLVMValueRef comp[2];
4956
4957 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4958 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4959 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4960 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4961 }
4962
4963 /* Initialize arguments for the shader export intrinsic */
4964 static void
4965 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4966 LLVMValueRef *values,
4967 unsigned target,
4968 struct ac_export_args *args)
4969 {
4970 /* Default is 0xf. Adjusted below depending on the format. */
4971 args->enabled_channels = 0xf;
4972
4973 /* Specify whether the EXEC mask represents the valid mask */
4974 args->valid_mask = 0;
4975
4976 /* Specify whether this is the last export */
4977 args->done = 0;
4978
4979 /* Specify the target we are exporting */
4980 args->target = target;
4981
4982 args->compr = false;
4983 args->out[0] = LLVMGetUndef(ctx->f32);
4984 args->out[1] = LLVMGetUndef(ctx->f32);
4985 args->out[2] = LLVMGetUndef(ctx->f32);
4986 args->out[3] = LLVMGetUndef(ctx->f32);
4987
4988 if (!values)
4989 return;
4990
4991 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4992 LLVMValueRef val[4];
4993 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4994 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4995 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4996
4997 switch(col_format) {
4998 case V_028714_SPI_SHADER_ZERO:
4999 args->enabled_channels = 0; /* writemask */
5000 args->target = V_008DFC_SQ_EXP_NULL;
5001 break;
5002
5003 case V_028714_SPI_SHADER_32_R:
5004 args->enabled_channels = 1;
5005 args->out[0] = values[0];
5006 break;
5007
5008 case V_028714_SPI_SHADER_32_GR:
5009 args->enabled_channels = 0x3;
5010 args->out[0] = values[0];
5011 args->out[1] = values[1];
5012 break;
5013
5014 case V_028714_SPI_SHADER_32_AR:
5015 args->enabled_channels = 0x9;
5016 args->out[0] = values[0];
5017 args->out[3] = values[3];
5018 break;
5019
5020 case V_028714_SPI_SHADER_FP16_ABGR:
5021 args->compr = 1;
5022
5023 for (unsigned chan = 0; chan < 2; chan++) {
5024 LLVMValueRef pack_args[2] = {
5025 values[2 * chan],
5026 values[2 * chan + 1]
5027 };
5028 LLVMValueRef packed;
5029
5030 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5031 args->out[chan] = packed;
5032 }
5033 break;
5034
5035 case V_028714_SPI_SHADER_UNORM16_ABGR:
5036 for (unsigned chan = 0; chan < 4; chan++) {
5037 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5038 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5039 LLVMConstReal(ctx->f32, 65535), "");
5040 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5041 LLVMConstReal(ctx->f32, 0.5), "");
5042 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5043 ctx->i32, "");
5044 }
5045
5046 args->compr = 1;
5047 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5048 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5049 break;
5050
5051 case V_028714_SPI_SHADER_SNORM16_ABGR:
5052 for (unsigned chan = 0; chan < 4; chan++) {
5053 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
5054 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5055 LLVMConstReal(ctx->f32, 32767), "");
5056
5057 /* If positive, add 0.5, else add -0.5. */
5058 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5059 LLVMBuildSelect(ctx->builder,
5060 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5061 val[chan], ctx->f32zero, ""),
5062 LLVMConstReal(ctx->f32, 0.5),
5063 LLVMConstReal(ctx->f32, -0.5), ""), "");
5064 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5065 }
5066
5067 args->compr = 1;
5068 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5069 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5070 break;
5071
5072 case V_028714_SPI_SHADER_UINT16_ABGR: {
5073 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
5074
5075 for (unsigned chan = 0; chan < 4; chan++) {
5076 val[chan] = to_integer(ctx, values[chan]);
5077 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
5078 }
5079
5080 args->compr = 1;
5081 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5082 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5083 break;
5084 }
5085
5086 case V_028714_SPI_SHADER_SINT16_ABGR: {
5087 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5088 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5089
5090 /* Clamp. */
5091 for (unsigned chan = 0; chan < 4; chan++) {
5092 val[chan] = to_integer(ctx, values[chan]);
5093 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
5094 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
5095 }
5096
5097 args->compr = 1;
5098 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5099 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5100 break;
5101 }
5102
5103 default:
5104 case V_028714_SPI_SHADER_32_ABGR:
5105 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5106 break;
5107 }
5108 } else
5109 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5110
5111 for (unsigned i = 0; i < 4; ++i)
5112 args->out[i] = to_float(ctx, args->out[i]);
5113 }
5114
5115 static void
5116 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5117 struct ac_vs_output_info *outinfo)
5118 {
5119 uint32_t param_count = 0;
5120 unsigned target;
5121 unsigned pos_idx, num_pos_exports = 0;
5122 struct ac_export_args args, pos_args[4] = {};
5123 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5124 int i;
5125
5126 outinfo->prim_id_output = 0xffffffff;
5127 outinfo->layer_output = 0xffffffff;
5128 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5129 LLVMValueRef slots[8];
5130 unsigned j;
5131
5132 if (outinfo->cull_dist_mask)
5133 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5134
5135 i = VARYING_SLOT_CLIP_DIST0;
5136 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5137 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5138 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5139
5140 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5141 slots[i] = LLVMGetUndef(ctx->f32);
5142
5143 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5144 target = V_008DFC_SQ_EXP_POS + 3;
5145 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5146 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5147 &args, sizeof(args));
5148 }
5149
5150 target = V_008DFC_SQ_EXP_POS + 2;
5151 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5152 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5153 &args, sizeof(args));
5154
5155 }
5156
5157 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5158 LLVMValueRef values[4];
5159 if (!(ctx->output_mask & (1ull << i)))
5160 continue;
5161
5162 for (unsigned j = 0; j < 4; j++)
5163 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5164 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5165
5166 if (i == VARYING_SLOT_POS) {
5167 target = V_008DFC_SQ_EXP_POS;
5168 } else if (i == VARYING_SLOT_CLIP_DIST0) {
5169 continue;
5170 } else if (i == VARYING_SLOT_PSIZ) {
5171 outinfo->writes_pointsize = true;
5172 psize_value = values[0];
5173 continue;
5174 } else if (i == VARYING_SLOT_LAYER) {
5175 outinfo->writes_layer = true;
5176 layer_value = values[0];
5177 outinfo->layer_output = param_count;
5178 target = V_008DFC_SQ_EXP_PARAM + param_count;
5179 param_count++;
5180 } else if (i == VARYING_SLOT_VIEWPORT) {
5181 outinfo->writes_viewport_index = true;
5182 viewport_index_value = values[0];
5183 continue;
5184 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5185 outinfo->prim_id_output = param_count;
5186 target = V_008DFC_SQ_EXP_PARAM + param_count;
5187 param_count++;
5188 } else if (i >= VARYING_SLOT_VAR0) {
5189 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5190 target = V_008DFC_SQ_EXP_PARAM + param_count;
5191 param_count++;
5192 }
5193
5194 si_llvm_init_export_args(ctx, values, target, &args);
5195
5196 if (target >= V_008DFC_SQ_EXP_POS &&
5197 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5198 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5199 &args, sizeof(args));
5200 } else {
5201 ac_build_export(&ctx->ac, &args);
5202 }
5203 }
5204
5205 /* We need to add the position output manually if it's missing. */
5206 if (!pos_args[0].out[0]) {
5207 pos_args[0].enabled_channels = 0xf;
5208 pos_args[0].valid_mask = 0;
5209 pos_args[0].done = 0;
5210 pos_args[0].target = V_008DFC_SQ_EXP_POS;
5211 pos_args[0].compr = 0;
5212 pos_args[0].out[0] = ctx->f32zero; /* X */
5213 pos_args[0].out[1] = ctx->f32zero; /* Y */
5214 pos_args[0].out[2] = ctx->f32zero; /* Z */
5215 pos_args[0].out[3] = ctx->f32one; /* W */
5216 }
5217
5218 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5219 (outinfo->writes_layer == true ? 4 : 0) |
5220 (outinfo->writes_viewport_index == true ? 8 : 0));
5221 if (mask) {
5222 pos_args[1].enabled_channels = mask;
5223 pos_args[1].valid_mask = 0;
5224 pos_args[1].done = 0;
5225 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5226 pos_args[1].compr = 0;
5227 pos_args[1].out[0] = ctx->f32zero; /* X */
5228 pos_args[1].out[1] = ctx->f32zero; /* Y */
5229 pos_args[1].out[2] = ctx->f32zero; /* Z */
5230 pos_args[1].out[3] = ctx->f32zero; /* W */
5231
5232 if (outinfo->writes_pointsize == true)
5233 pos_args[1].out[0] = psize_value;
5234 if (outinfo->writes_layer == true)
5235 pos_args[1].out[2] = layer_value;
5236 if (outinfo->writes_viewport_index == true)
5237 pos_args[1].out[3] = viewport_index_value;
5238 }
5239 for (i = 0; i < 4; i++) {
5240 if (pos_args[i].out[0])
5241 num_pos_exports++;
5242 }
5243
5244 pos_idx = 0;
5245 for (i = 0; i < 4; i++) {
5246 if (!pos_args[i].out[0])
5247 continue;
5248
5249 /* Specify the target we are exporting */
5250 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5251 if (pos_idx == num_pos_exports)
5252 pos_args[i].done = 1;
5253 ac_build_export(&ctx->ac, &pos_args[i]);
5254 }
5255
5256 outinfo->pos_exports = num_pos_exports;
5257 outinfo->param_exports = param_count;
5258 }
5259
5260 static void
5261 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5262 struct ac_es_output_info *outinfo)
5263 {
5264 int j;
5265 uint64_t max_output_written = 0;
5266 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5267 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5268 int param_index;
5269 int length = 4;
5270
5271 if (!(ctx->output_mask & (1ull << i)))
5272 continue;
5273
5274 if (i == VARYING_SLOT_CLIP_DIST0)
5275 length = ctx->num_output_clips + ctx->num_output_culls;
5276
5277 param_index = shader_io_get_unique_index(i);
5278
5279 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5280
5281 for (j = 0; j < length; j++) {
5282 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5283 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5284
5285 ac_build_buffer_store_dword(&ctx->ac,
5286 ctx->esgs_ring,
5287 out_val, 1,
5288 NULL, ctx->es2gs_offset,
5289 (4 * param_index + j) * 4,
5290 1, 1, true, true);
5291 }
5292 }
5293 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5294 }
5295
5296 static void
5297 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5298 {
5299 LLVMValueRef vertex_id = ctx->rel_auto_id;
5300 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5301 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5302 vertex_dw_stride, "");
5303
5304 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5305 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5306 int length = 4;
5307
5308 if (!(ctx->output_mask & (1ull << i)))
5309 continue;
5310
5311 if (i == VARYING_SLOT_CLIP_DIST0)
5312 length = ctx->num_output_clips + ctx->num_output_culls;
5313 int param = shader_io_get_unique_index(i);
5314 mark_tess_output(ctx, false, param);
5315 if (length > 4)
5316 mark_tess_output(ctx, false, param + 1);
5317 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5318 LLVMConstInt(ctx->i32, param * 4, false),
5319 "");
5320 for (unsigned j = 0; j < length; j++) {
5321 lds_store(ctx, dw_addr,
5322 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5323 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5324 }
5325 }
5326 }
5327
5328 struct ac_build_if_state
5329 {
5330 struct nir_to_llvm_context *ctx;
5331 LLVMValueRef condition;
5332 LLVMBasicBlockRef entry_block;
5333 LLVMBasicBlockRef true_block;
5334 LLVMBasicBlockRef false_block;
5335 LLVMBasicBlockRef merge_block;
5336 };
5337
5338 static LLVMBasicBlockRef
5339 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5340 {
5341 LLVMBasicBlockRef current_block;
5342 LLVMBasicBlockRef next_block;
5343 LLVMBasicBlockRef new_block;
5344
5345 /* get current basic block */
5346 current_block = LLVMGetInsertBlock(ctx->builder);
5347
5348 /* chqeck if there's another block after this one */
5349 next_block = LLVMGetNextBasicBlock(current_block);
5350 if (next_block) {
5351 /* insert the new block before the next block */
5352 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5353 }
5354 else {
5355 /* append new block after current block */
5356 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5357 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5358 }
5359 return new_block;
5360 }
5361
5362 static void
5363 ac_nir_build_if(struct ac_build_if_state *ifthen,
5364 struct nir_to_llvm_context *ctx,
5365 LLVMValueRef condition)
5366 {
5367 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5368
5369 memset(ifthen, 0, sizeof *ifthen);
5370 ifthen->ctx = ctx;
5371 ifthen->condition = condition;
5372 ifthen->entry_block = block;
5373
5374 /* create endif/merge basic block for the phi functions */
5375 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5376
5377 /* create/insert true_block before merge_block */
5378 ifthen->true_block =
5379 LLVMInsertBasicBlockInContext(ctx->context,
5380 ifthen->merge_block,
5381 "if-true-block");
5382
5383 /* successive code goes into the true block */
5384 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5385 }
5386
5387 /**
5388 * End a conditional.
5389 */
5390 static void
5391 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5392 {
5393 LLVMBuilderRef builder = ifthen->ctx->builder;
5394
5395 /* Insert branch to the merge block from current block */
5396 LLVMBuildBr(builder, ifthen->merge_block);
5397
5398 /*
5399 * Now patch in the various branch instructions.
5400 */
5401
5402 /* Insert the conditional branch instruction at the end of entry_block */
5403 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5404 if (ifthen->false_block) {
5405 /* we have an else clause */
5406 LLVMBuildCondBr(builder, ifthen->condition,
5407 ifthen->true_block, ifthen->false_block);
5408 }
5409 else {
5410 /* no else clause */
5411 LLVMBuildCondBr(builder, ifthen->condition,
5412 ifthen->true_block, ifthen->merge_block);
5413 }
5414
5415 /* Resume building code at end of the ifthen->merge_block */
5416 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5417 }
5418
5419 static void
5420 write_tess_factors(struct nir_to_llvm_context *ctx)
5421 {
5422 unsigned stride, outer_comps, inner_comps;
5423 struct ac_build_if_state if_ctx, inner_if_ctx;
5424 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5425 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5426 unsigned tess_inner_index, tess_outer_index;
5427 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5428 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5429 int i;
5430 emit_barrier(ctx);
5431
5432 switch (ctx->options->key.tcs.primitive_mode) {
5433 case GL_ISOLINES:
5434 stride = 2;
5435 outer_comps = 2;
5436 inner_comps = 0;
5437 break;
5438 case GL_TRIANGLES:
5439 stride = 4;
5440 outer_comps = 3;
5441 inner_comps = 1;
5442 break;
5443 case GL_QUADS:
5444 stride = 6;
5445 outer_comps = 4;
5446 inner_comps = 2;
5447 break;
5448 default:
5449 return;
5450 }
5451
5452 ac_nir_build_if(&if_ctx, ctx,
5453 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5454 invocation_id, ctx->i32zero, ""));
5455
5456 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5457 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5458
5459 mark_tess_output(ctx, true, tess_inner_index);
5460 mark_tess_output(ctx, true, tess_outer_index);
5461 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5462 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5463 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5464 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5465 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5466
5467 for (i = 0; i < 4; i++) {
5468 inner[i] = LLVMGetUndef(ctx->i32);
5469 outer[i] = LLVMGetUndef(ctx->i32);
5470 }
5471
5472 // LINES reverseal
5473 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5474 outer[0] = out[1] = lds_load(ctx, lds_outer);
5475 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5476 LLVMConstInt(ctx->i32, 1, false), "");
5477 outer[1] = out[0] = lds_load(ctx, lds_outer);
5478 } else {
5479 for (i = 0; i < outer_comps; i++) {
5480 outer[i] = out[i] =
5481 lds_load(ctx, lds_outer);
5482 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5483 LLVMConstInt(ctx->i32, 1, false), "");
5484 }
5485 for (i = 0; i < inner_comps; i++) {
5486 inner[i] = out[outer_comps+i] =
5487 lds_load(ctx, lds_inner);
5488 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5489 LLVMConstInt(ctx->i32, 1, false), "");
5490 }
5491 }
5492
5493 /* Convert the outputs to vectors for stores. */
5494 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5495 vec1 = NULL;
5496
5497 if (stride > 4)
5498 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5499
5500
5501 buffer = ctx->hs_ring_tess_factor;
5502 tf_base = ctx->tess_factor_offset;
5503 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5504 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5505
5506 ac_nir_build_if(&inner_if_ctx, ctx,
5507 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5508 rel_patch_id, ctx->i32zero, ""));
5509
5510 /* Store the dynamic HS control word. */
5511 ac_build_buffer_store_dword(&ctx->ac, buffer,
5512 LLVMConstInt(ctx->i32, 0x80000000, false),
5513 1, ctx->i32zero, tf_base,
5514 0, 1, 0, true, false);
5515 ac_nir_build_endif(&inner_if_ctx);
5516
5517 /* Store the tessellation factors. */
5518 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5519 MIN2(stride, 4), byteoffset, tf_base,
5520 4, 1, 0, true, false);
5521 if (vec1)
5522 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5523 stride - 4, byteoffset, tf_base,
5524 20, 1, 0, true, false);
5525
5526 //TODO store to offchip for TES to read - only if TES reads them
5527 if (1) {
5528 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5529 LLVMValueRef tf_inner_offset;
5530 unsigned param_outer, param_inner;
5531
5532 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5533 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5534 LLVMConstInt(ctx->i32, param_outer, 0));
5535
5536 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5537 util_next_power_of_two(outer_comps));
5538
5539 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5540 outer_comps, tf_outer_offset,
5541 ctx->oc_lds, 0, 1, 0, true, false);
5542 if (inner_comps) {
5543 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5544 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5545 LLVMConstInt(ctx->i32, param_inner, 0));
5546
5547 inner_vec = inner_comps == 1 ? inner[0] :
5548 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5549 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5550 inner_comps, tf_inner_offset,
5551 ctx->oc_lds, 0, 1, 0, true, false);
5552 }
5553 }
5554 ac_nir_build_endif(&if_ctx);
5555 }
5556
5557 static void
5558 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5559 {
5560 write_tess_factors(ctx);
5561 }
5562
5563 static void
5564 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5565 LLVMValueRef *color, unsigned param, bool is_last)
5566 {
5567
5568 struct ac_export_args args;
5569
5570 /* Export */
5571 si_llvm_init_export_args(ctx, color, param,
5572 &args);
5573
5574 if (is_last) {
5575 args.valid_mask = 1; /* whether the EXEC mask is valid */
5576 args.done = 1; /* DONE bit */
5577 } else if (!args.enabled_channels)
5578 return; /* unnecessary NULL export */
5579
5580 ac_build_export(&ctx->ac, &args);
5581 }
5582
5583 static void
5584 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5585 LLVMValueRef depth, LLVMValueRef stencil,
5586 LLVMValueRef samplemask)
5587 {
5588 struct ac_export_args args;
5589
5590 args.enabled_channels = 0;
5591 args.valid_mask = 1;
5592 args.done = 1;
5593 args.target = V_008DFC_SQ_EXP_MRTZ;
5594 args.compr = false;
5595
5596 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5597 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5598 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5599 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5600
5601 if (depth) {
5602 args.out[0] = depth;
5603 args.enabled_channels |= 0x1;
5604 }
5605
5606 if (stencil) {
5607 args.out[1] = stencil;
5608 args.enabled_channels |= 0x2;
5609 }
5610
5611 if (samplemask) {
5612 args.out[2] = samplemask;
5613 args.enabled_channels |= 0x4;
5614 }
5615
5616 /* SI (except OLAND) has a bug that it only looks
5617 * at the X writemask component. */
5618 if (ctx->options->chip_class == SI &&
5619 ctx->options->family != CHIP_OLAND)
5620 args.enabled_channels |= 0x1;
5621
5622 ac_build_export(&ctx->ac, &args);
5623 }
5624
5625 static void
5626 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5627 {
5628 unsigned index = 0;
5629 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5630
5631 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5632 LLVMValueRef values[4];
5633
5634 if (!(ctx->output_mask & (1ull << i)))
5635 continue;
5636
5637 if (i == FRAG_RESULT_DEPTH) {
5638 ctx->shader_info->fs.writes_z = true;
5639 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
5640 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5641 } else if (i == FRAG_RESULT_STENCIL) {
5642 ctx->shader_info->fs.writes_stencil = true;
5643 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
5644 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5645 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5646 ctx->shader_info->fs.writes_sample_mask = true;
5647 samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
5648 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5649 } else {
5650 bool last = false;
5651 for (unsigned j = 0; j < 4; j++)
5652 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5653 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5654
5655 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5656 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5657
5658 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
5659 index++;
5660 }
5661 }
5662
5663 if (depth || stencil || samplemask)
5664 si_export_mrt_z(ctx, depth, stencil, samplemask);
5665 else if (!index)
5666 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
5667
5668 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5669 }
5670
5671 static void
5672 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5673 {
5674 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5675 }
5676
5677 static void
5678 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
5679 {
5680 switch (ctx->stage) {
5681 case MESA_SHADER_VERTEX:
5682 if (ctx->options->key.vs.as_ls)
5683 handle_ls_outputs_post(ctx);
5684 else if (ctx->options->key.vs.as_es)
5685 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5686 else
5687 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
5688 break;
5689 case MESA_SHADER_FRAGMENT:
5690 handle_fs_outputs_post(ctx);
5691 break;
5692 case MESA_SHADER_GEOMETRY:
5693 emit_gs_epilogue(ctx);
5694 break;
5695 case MESA_SHADER_TESS_CTRL:
5696 handle_tcs_outputs_post(ctx);
5697 break;
5698 case MESA_SHADER_TESS_EVAL:
5699 if (ctx->options->key.tes.as_es)
5700 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
5701 else
5702 handle_vs_outputs_post(ctx, &ctx->shader_info->tes.outinfo);
5703 break;
5704 default:
5705 break;
5706 }
5707 }
5708
5709 static void
5710 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
5711 struct nir_variable *variable, uint32_t *offset, int idx)
5712 {
5713 unsigned size = glsl_count_attribute_slots(variable->type, false);
5714 variable->data.driver_location = *offset;
5715 *offset += size;
5716 }
5717
5718 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
5719 {
5720 LLVMPassManagerRef passmgr;
5721 /* Create the pass manager */
5722 passmgr = LLVMCreateFunctionPassManagerForModule(
5723 ctx->module);
5724
5725 /* This pass should eliminate all the load and store instructions */
5726 LLVMAddPromoteMemoryToRegisterPass(passmgr);
5727
5728 /* Add some optimization passes */
5729 LLVMAddScalarReplAggregatesPass(passmgr);
5730 LLVMAddLICMPass(passmgr);
5731 LLVMAddAggressiveDCEPass(passmgr);
5732 LLVMAddCFGSimplificationPass(passmgr);
5733 LLVMAddInstructionCombiningPass(passmgr);
5734
5735 /* Run the pass */
5736 LLVMInitializeFunctionPassManager(passmgr);
5737 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
5738 LLVMFinalizeFunctionPassManager(passmgr);
5739
5740 LLVMDisposeBuilder(ctx->builder);
5741 LLVMDisposePassManager(passmgr);
5742 }
5743
5744 static void
5745 ac_setup_rings(struct nir_to_llvm_context *ctx)
5746 {
5747 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
5748 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
5749 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
5750 }
5751
5752 if (ctx->is_gs_copy_shader) {
5753 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
5754 }
5755 if (ctx->stage == MESA_SHADER_GEOMETRY) {
5756 LLVMValueRef tmp;
5757 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
5758 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
5759
5760 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
5761
5762 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
5763 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
5764 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
5765 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
5766
5767 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
5768 }
5769
5770 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
5771 ctx->stage == MESA_SHADER_TESS_EVAL) {
5772 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
5773 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
5774 }
5775 }
5776
5777 static
5778 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
5779 struct nir_shader *nir,
5780 struct ac_shader_variant_info *shader_info,
5781 const struct ac_nir_compiler_options *options)
5782 {
5783 struct nir_to_llvm_context ctx = {0};
5784 struct nir_function *func;
5785 unsigned i;
5786 ctx.options = options;
5787 ctx.shader_info = shader_info;
5788 ctx.context = LLVMContextCreate();
5789 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5790
5791 ac_llvm_context_init(&ctx.ac, ctx.context);
5792 ctx.ac.module = ctx.module;
5793
5794 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
5795
5796 memset(shader_info, 0, sizeof(*shader_info));
5797
5798 ac_nir_shader_info_pass(nir, options, &shader_info->info);
5799
5800 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
5801
5802 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
5803 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
5804 LLVMSetDataLayout(ctx.module, data_layout_str);
5805 LLVMDisposeTargetData(data_layout);
5806 LLVMDisposeMessage(data_layout_str);
5807
5808 setup_types(&ctx);
5809
5810 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5811 ctx.ac.builder = ctx.builder;
5812 ctx.stage = nir->stage;
5813
5814 for (i = 0; i < AC_UD_MAX_SETS; i++)
5815 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
5816 for (i = 0; i < AC_UD_MAX_UD; i++)
5817 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
5818
5819 create_function(&ctx);
5820
5821 if (nir->stage == MESA_SHADER_COMPUTE) {
5822 int num_shared = 0;
5823 nir_foreach_variable(variable, &nir->shared)
5824 num_shared++;
5825 if (num_shared) {
5826 int idx = 0;
5827 uint32_t shared_size = 0;
5828 LLVMValueRef var;
5829 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
5830 nir_foreach_variable(variable, &nir->shared) {
5831 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
5832 idx++;
5833 }
5834
5835 shared_size *= 16;
5836 var = LLVMAddGlobalInAddressSpace(ctx.module,
5837 LLVMArrayType(ctx.i8, shared_size),
5838 "compute_lds",
5839 LOCAL_ADDR_SPACE);
5840 LLVMSetAlignment(var, 4);
5841 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
5842 }
5843 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
5844 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
5845
5846 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
5847 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
5848 ctx.tes_primitive_mode = nir->info->tess.primitive_mode;
5849 }
5850
5851 ac_setup_rings(&ctx);
5852
5853 nir_foreach_variable(variable, &nir->inputs)
5854 handle_shader_input_decl(&ctx, variable);
5855
5856 if (nir->stage == MESA_SHADER_FRAGMENT)
5857 handle_fs_inputs_pre(&ctx, nir);
5858
5859 ctx.num_output_clips = nir->info->clip_distance_array_size;
5860 ctx.num_output_culls = nir->info->cull_distance_array_size;
5861
5862 nir_foreach_variable(variable, &nir->outputs)
5863 handle_shader_output_decl(&ctx, variable);
5864
5865 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5866 _mesa_key_pointer_equal);
5867 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5868 _mesa_key_pointer_equal);
5869
5870 func = (struct nir_function *)exec_list_get_head(&nir->functions);
5871
5872 setup_locals(&ctx, func);
5873
5874 visit_cf_list(&ctx, &func->impl->body);
5875 phi_post_pass(&ctx);
5876
5877 handle_shader_outputs_post(&ctx);
5878 LLVMBuildRetVoid(ctx.builder);
5879
5880 ac_llvm_finalize_module(&ctx);
5881 free(ctx.locals);
5882 ralloc_free(ctx.defs);
5883 ralloc_free(ctx.phis);
5884
5885 if (nir->stage == MESA_SHADER_GEOMETRY) {
5886 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
5887 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
5888 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
5889 nir->info->gs.vertices_out;
5890 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
5891 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
5892 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
5893 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
5894 shader_info->vs.outputs_written = ctx.tess_outputs_written;
5895 }
5896
5897 return ctx.module;
5898 }
5899
5900 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
5901 {
5902 unsigned *retval = (unsigned *)context;
5903 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
5904 char *description = LLVMGetDiagInfoDescription(di);
5905
5906 if (severity == LLVMDSError) {
5907 *retval = 1;
5908 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
5909 description);
5910 }
5911
5912 LLVMDisposeMessage(description);
5913 }
5914
5915 static unsigned ac_llvm_compile(LLVMModuleRef M,
5916 struct ac_shader_binary *binary,
5917 LLVMTargetMachineRef tm)
5918 {
5919 unsigned retval = 0;
5920 char *err;
5921 LLVMContextRef llvm_ctx;
5922 LLVMMemoryBufferRef out_buffer;
5923 unsigned buffer_size;
5924 const char *buffer_data;
5925 LLVMBool mem_err;
5926
5927 /* Setup Diagnostic Handler*/
5928 llvm_ctx = LLVMGetModuleContext(M);
5929
5930 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
5931 &retval);
5932
5933 /* Compile IR*/
5934 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
5935 &err, &out_buffer);
5936
5937 /* Process Errors/Warnings */
5938 if (mem_err) {
5939 fprintf(stderr, "%s: %s", __FUNCTION__, err);
5940 free(err);
5941 retval = 1;
5942 goto out;
5943 }
5944
5945 /* Extract Shader Code*/
5946 buffer_size = LLVMGetBufferSize(out_buffer);
5947 buffer_data = LLVMGetBufferStart(out_buffer);
5948
5949 ac_elf_read(buffer_data, buffer_size, binary);
5950
5951 /* Clean up */
5952 LLVMDisposeMemoryBuffer(out_buffer);
5953
5954 out:
5955 return retval;
5956 }
5957
5958 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
5959 LLVMModuleRef llvm_module,
5960 struct ac_shader_binary *binary,
5961 struct ac_shader_config *config,
5962 struct ac_shader_variant_info *shader_info,
5963 gl_shader_stage stage,
5964 bool dump_shader, bool supports_spill)
5965 {
5966 if (dump_shader)
5967 ac_dump_module(llvm_module);
5968
5969 memset(binary, 0, sizeof(*binary));
5970 int v = ac_llvm_compile(llvm_module, binary, tm);
5971 if (v) {
5972 fprintf(stderr, "compile failed\n");
5973 }
5974
5975 if (dump_shader)
5976 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
5977
5978 ac_shader_binary_read_config(binary, config, 0, supports_spill);
5979
5980 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
5981 LLVMDisposeModule(llvm_module);
5982 LLVMContextDispose(ctx);
5983
5984 if (stage == MESA_SHADER_FRAGMENT) {
5985 shader_info->num_input_vgprs = 0;
5986 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
5987 shader_info->num_input_vgprs += 2;
5988 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
5989 shader_info->num_input_vgprs += 2;
5990 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
5991 shader_info->num_input_vgprs += 2;
5992 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
5993 shader_info->num_input_vgprs += 3;
5994 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
5995 shader_info->num_input_vgprs += 2;
5996 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
5997 shader_info->num_input_vgprs += 2;
5998 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
5999 shader_info->num_input_vgprs += 2;
6000 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6001 shader_info->num_input_vgprs += 1;
6002 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6003 shader_info->num_input_vgprs += 1;
6004 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6005 shader_info->num_input_vgprs += 1;
6006 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6007 shader_info->num_input_vgprs += 1;
6008 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6009 shader_info->num_input_vgprs += 1;
6010 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6011 shader_info->num_input_vgprs += 1;
6012 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6013 shader_info->num_input_vgprs += 1;
6014 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6015 shader_info->num_input_vgprs += 1;
6016 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6017 shader_info->num_input_vgprs += 1;
6018 }
6019 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6020
6021 /* +3 for scratch wave offset and VCC */
6022 config->num_sgprs = MAX2(config->num_sgprs,
6023 shader_info->num_input_sgprs + 3);
6024 }
6025
6026 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6027 struct ac_shader_binary *binary,
6028 struct ac_shader_config *config,
6029 struct ac_shader_variant_info *shader_info,
6030 struct nir_shader *nir,
6031 const struct ac_nir_compiler_options *options,
6032 bool dump_shader)
6033 {
6034
6035 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6036 options);
6037
6038 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6039 switch (nir->stage) {
6040 case MESA_SHADER_COMPUTE:
6041 for (int i = 0; i < 3; ++i)
6042 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
6043 break;
6044 case MESA_SHADER_FRAGMENT:
6045 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
6046 break;
6047 case MESA_SHADER_GEOMETRY:
6048 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
6049 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
6050 shader_info->gs.output_prim = nir->info->gs.output_primitive;
6051 shader_info->gs.invocations = nir->info->gs.invocations;
6052 break;
6053 case MESA_SHADER_TESS_EVAL:
6054 shader_info->tes.primitive_mode = nir->info->tess.primitive_mode;
6055 shader_info->tes.spacing = nir->info->tess.spacing;
6056 shader_info->tes.ccw = nir->info->tess.ccw;
6057 shader_info->tes.point_mode = nir->info->tess.point_mode;
6058 shader_info->tes.as_es = options->key.tes.as_es;
6059 break;
6060 case MESA_SHADER_TESS_CTRL:
6061 shader_info->tcs.tcs_vertices_out = nir->info->tess.tcs_vertices_out;
6062 break;
6063 case MESA_SHADER_VERTEX:
6064 shader_info->vs.as_es = options->key.vs.as_es;
6065 shader_info->vs.as_ls = options->key.vs.as_ls;
6066 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6067 if (options->key.vs.as_ls)
6068 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6069 break;
6070 default:
6071 break;
6072 }
6073 }
6074
6075 static void
6076 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6077 {
6078 LLVMValueRef args[9];
6079 args[0] = ctx->gsvs_ring;
6080 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6081 args[3] = ctx->i32zero;
6082 args[4] = ctx->i32one; /* OFFEN */
6083 args[5] = ctx->i32zero; /* IDXEN */
6084 args[6] = ctx->i32one; /* GLC */
6085 args[7] = ctx->i32one; /* SLC */
6086 args[8] = ctx->i32zero; /* TFE */
6087
6088 int idx = 0;
6089
6090 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6091 int length = 4;
6092 int slot = idx;
6093 int slot_inc = 1;
6094 if (!(ctx->output_mask & (1ull << i)))
6095 continue;
6096
6097 if (i == VARYING_SLOT_CLIP_DIST0) {
6098 /* unpack clip and cull from a single set of slots */
6099 length = ctx->num_output_clips + ctx->num_output_culls;
6100 if (length > 4)
6101 slot_inc = 2;
6102 }
6103
6104 for (unsigned j = 0; j < length; j++) {
6105 LLVMValueRef value;
6106 args[2] = LLVMConstInt(ctx->i32,
6107 (slot * 4 + j) *
6108 ctx->gs_max_out_vertices * 16 * 4, false);
6109
6110 value = ac_build_intrinsic(&ctx->ac,
6111 "llvm.SI.buffer.load.dword.i32.i32",
6112 ctx->i32, args, 9,
6113 AC_FUNC_ATTR_READONLY |
6114 AC_FUNC_ATTR_LEGACY);
6115
6116 LLVMBuildStore(ctx->builder,
6117 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
6118 }
6119 idx += slot_inc;
6120 }
6121 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
6122 }
6123
6124 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6125 struct nir_shader *geom_shader,
6126 struct ac_shader_binary *binary,
6127 struct ac_shader_config *config,
6128 struct ac_shader_variant_info *shader_info,
6129 const struct ac_nir_compiler_options *options,
6130 bool dump_shader)
6131 {
6132 struct nir_to_llvm_context ctx = {0};
6133 ctx.context = LLVMContextCreate();
6134 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6135 ctx.options = options;
6136 ctx.shader_info = shader_info;
6137
6138 ac_llvm_context_init(&ctx.ac, ctx.context);
6139 ctx.ac.module = ctx.module;
6140
6141 ctx.is_gs_copy_shader = true;
6142 LLVMSetTarget(ctx.module, "amdgcn--");
6143 setup_types(&ctx);
6144
6145 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6146 ctx.ac.builder = ctx.builder;
6147 ctx.stage = MESA_SHADER_VERTEX;
6148
6149 create_function(&ctx);
6150
6151 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
6152 ac_setup_rings(&ctx);
6153
6154 ctx.num_output_clips = geom_shader->info->clip_distance_array_size;
6155 ctx.num_output_culls = geom_shader->info->cull_distance_array_size;
6156
6157 nir_foreach_variable(variable, &geom_shader->outputs)
6158 handle_shader_output_decl(&ctx, variable);
6159
6160 ac_gs_copy_shader_emit(&ctx);
6161
6162 LLVMBuildRetVoid(ctx.builder);
6163
6164 ac_llvm_finalize_module(&ctx);
6165
6166 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6167 MESA_SHADER_VERTEX,
6168 dump_shader, options->supports_spill);
6169 }