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radv: fetch sample index via fmask for image coord as well.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef gsvs_ring_stride;
87 LLVMValueRef gsvs_num_entries;
88 LLVMValueRef gs2vs_offset;
89 LLVMValueRef gs_wave_id;
90 LLVMValueRef gs_vtx_offset[6];
91 LLVMValueRef gs_prim_id, gs_invocation_id;
92
93 LLVMValueRef esgs_ring;
94 LLVMValueRef gsvs_ring;
95
96 LLVMValueRef prim_mask;
97 LLVMValueRef sample_positions;
98 LLVMValueRef persp_sample, persp_center, persp_centroid;
99 LLVMValueRef linear_sample, linear_center, linear_centroid;
100 LLVMValueRef front_face;
101 LLVMValueRef ancillary;
102 LLVMValueRef sample_coverage;
103 LLVMValueRef frag_pos[4];
104
105 LLVMBasicBlockRef continue_block;
106 LLVMBasicBlockRef break_block;
107
108 LLVMTypeRef i1;
109 LLVMTypeRef i8;
110 LLVMTypeRef i16;
111 LLVMTypeRef i32;
112 LLVMTypeRef i64;
113 LLVMTypeRef v2i32;
114 LLVMTypeRef v3i32;
115 LLVMTypeRef v4i32;
116 LLVMTypeRef v8i32;
117 LLVMTypeRef f64;
118 LLVMTypeRef f32;
119 LLVMTypeRef f16;
120 LLVMTypeRef v2f32;
121 LLVMTypeRef v4f32;
122 LLVMTypeRef v16i8;
123 LLVMTypeRef voidt;
124
125 LLVMValueRef i32zero;
126 LLVMValueRef i32one;
127 LLVMValueRef f32zero;
128 LLVMValueRef f32one;
129 LLVMValueRef v4f32empty;
130
131 unsigned uniform_md_kind;
132 LLVMValueRef empty_md;
133 gl_shader_stage stage;
134
135 LLVMValueRef lds;
136 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
137 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
138
139 LLVMValueRef shared_memory;
140 uint64_t input_mask;
141 uint64_t output_mask;
142 int num_locals;
143 LLVMValueRef *locals;
144 bool has_ddxy;
145 uint8_t num_input_clips;
146 uint8_t num_input_culls;
147 uint8_t num_output_clips;
148 uint8_t num_output_culls;
149
150 bool has_ds_bpermute;
151
152 bool is_gs_copy_shader;
153 LLVMValueRef gs_next_vertex;
154 unsigned gs_max_out_vertices;
155 };
156
157 struct ac_tex_info {
158 LLVMValueRef args[12];
159 int arg_count;
160 LLVMTypeRef dst_type;
161 bool has_offset;
162 };
163
164 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
165 nir_deref_var *deref,
166 enum desc_type desc_type);
167 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
168 {
169 return (index * 4) + chan;
170 }
171
172 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
173 {
174 if (slot == VARYING_SLOT_POS)
175 return 0;
176 if (slot == VARYING_SLOT_PSIZ)
177 return 1;
178 if (slot == VARYING_SLOT_CLIP_DIST0 ||
179 slot == VARYING_SLOT_CULL_DIST0)
180 return 2;
181 if (slot == VARYING_SLOT_CLIP_DIST1 ||
182 slot == VARYING_SLOT_CULL_DIST1)
183 return 3;
184 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
185 return 4 + (slot - VARYING_SLOT_VAR0);
186 unreachable("illegal slot in get unique index\n");
187 }
188
189 static unsigned llvm_get_type_size(LLVMTypeRef type)
190 {
191 LLVMTypeKind kind = LLVMGetTypeKind(type);
192
193 switch (kind) {
194 case LLVMIntegerTypeKind:
195 return LLVMGetIntTypeWidth(type) / 8;
196 case LLVMFloatTypeKind:
197 return 4;
198 case LLVMPointerTypeKind:
199 return 8;
200 case LLVMVectorTypeKind:
201 return LLVMGetVectorSize(type) *
202 llvm_get_type_size(LLVMGetElementType(type));
203 default:
204 assert(0);
205 return 0;
206 }
207 }
208
209 static void set_llvm_calling_convention(LLVMValueRef func,
210 gl_shader_stage stage)
211 {
212 enum radeon_llvm_calling_convention calling_conv;
213
214 switch (stage) {
215 case MESA_SHADER_VERTEX:
216 case MESA_SHADER_TESS_CTRL:
217 case MESA_SHADER_TESS_EVAL:
218 calling_conv = RADEON_LLVM_AMDGPU_VS;
219 break;
220 case MESA_SHADER_GEOMETRY:
221 calling_conv = RADEON_LLVM_AMDGPU_GS;
222 break;
223 case MESA_SHADER_FRAGMENT:
224 calling_conv = RADEON_LLVM_AMDGPU_PS;
225 break;
226 case MESA_SHADER_COMPUTE:
227 calling_conv = RADEON_LLVM_AMDGPU_CS;
228 break;
229 default:
230 unreachable("Unhandle shader type");
231 }
232
233 LLVMSetFunctionCallConv(func, calling_conv);
234 }
235
236 static LLVMValueRef
237 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
238 LLVMBuilderRef builder, LLVMTypeRef *return_types,
239 unsigned num_return_elems, LLVMTypeRef *param_types,
240 unsigned param_count, unsigned array_params_mask,
241 unsigned sgpr_params, bool unsafe_math)
242 {
243 LLVMTypeRef main_function_type, ret_type;
244 LLVMBasicBlockRef main_function_body;
245
246 if (num_return_elems)
247 ret_type = LLVMStructTypeInContext(ctx, return_types,
248 num_return_elems, true);
249 else
250 ret_type = LLVMVoidTypeInContext(ctx);
251
252 /* Setup the function */
253 main_function_type =
254 LLVMFunctionType(ret_type, param_types, param_count, 0);
255 LLVMValueRef main_function =
256 LLVMAddFunction(module, "main", main_function_type);
257 main_function_body =
258 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
259 LLVMPositionBuilderAtEnd(builder, main_function_body);
260
261 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
262 for (unsigned i = 0; i < sgpr_params; ++i) {
263 if (array_params_mask & (1 << i)) {
264 LLVMValueRef P = LLVMGetParam(main_function, i);
265 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_BYVAL);
266 ac_add_attr_dereferenceable(P, UINT64_MAX);
267 }
268 else {
269 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_INREG);
270 }
271 }
272
273 if (unsafe_math) {
274 /* These were copied from some LLVM test. */
275 LLVMAddTargetDependentFunctionAttr(main_function,
276 "less-precise-fpmad",
277 "true");
278 LLVMAddTargetDependentFunctionAttr(main_function,
279 "no-infs-fp-math",
280 "true");
281 LLVMAddTargetDependentFunctionAttr(main_function,
282 "no-nans-fp-math",
283 "true");
284 LLVMAddTargetDependentFunctionAttr(main_function,
285 "unsafe-fp-math",
286 "true");
287 }
288 return main_function;
289 }
290
291 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
292 {
293 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
294 CONST_ADDR_SPACE);
295 }
296
297 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
298 int idx,
299 LLVMTypeRef type)
300 {
301 LLVMValueRef offset;
302 LLVMValueRef ptr;
303 int addr_space;
304
305 offset = LLVMConstInt(ctx->i32, idx, false);
306
307 ptr = ctx->shared_memory;
308 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
309 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
310 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
311 return ptr;
312 }
313
314 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
315 {
316 if (t == ctx->f16 || t == ctx->i16)
317 return ctx->i16;
318 else if (t == ctx->f32 || t == ctx->i32)
319 return ctx->i32;
320 else if (t == ctx->f64 || t == ctx->i64)
321 return ctx->i64;
322 else
323 unreachable("Unhandled integer size");
324 }
325
326 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
327 {
328 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
329 LLVMTypeRef elem_type = LLVMGetElementType(t);
330 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
331 LLVMGetVectorSize(t));
332 }
333 return to_integer_type_scalar(ctx, t);
334 }
335
336 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
337 {
338 LLVMTypeRef type = LLVMTypeOf(v);
339 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
340 }
341
342 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
343 {
344 if (t == ctx->i16 || t == ctx->f16)
345 return ctx->f16;
346 else if (t == ctx->i32 || t == ctx->f32)
347 return ctx->f32;
348 else if (t == ctx->i64 || t == ctx->f64)
349 return ctx->f64;
350 else
351 unreachable("Unhandled float size");
352 }
353
354 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
355 {
356 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
357 LLVMTypeRef elem_type = LLVMGetElementType(t);
358 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
359 LLVMGetVectorSize(t));
360 }
361 return to_float_type_scalar(ctx, t);
362 }
363
364 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
365 {
366 LLVMTypeRef type = LLVMTypeOf(v);
367 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
368 }
369
370 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
371 {
372 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
373 type = LLVMGetElementType(type);
374
375 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
376 return LLVMGetIntTypeWidth(type);
377
378 if (type == ctx->f16)
379 return 16;
380 if (type == ctx->f32)
381 return 32;
382 if (type == ctx->f64)
383 return 64;
384
385 unreachable("Unhandled type kind in get_elem_bits");
386 }
387
388 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
389 LLVMValueRef param, unsigned rshift,
390 unsigned bitwidth)
391 {
392 LLVMValueRef value = param;
393 if (rshift)
394 value = LLVMBuildLShr(ctx->builder, value,
395 LLVMConstInt(ctx->i32, rshift, false), "");
396
397 if (rshift + bitwidth < 32) {
398 unsigned mask = (1 << bitwidth) - 1;
399 value = LLVMBuildAnd(ctx->builder, value,
400 LLVMConstInt(ctx->i32, mask, false), "");
401 }
402 return value;
403 }
404
405 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
406 {
407 ud_info->sgpr_idx = sgpr_idx;
408 ud_info->num_sgprs = num_sgprs;
409 ud_info->indirect = false;
410 ud_info->indirect_offset = 0;
411 }
412
413 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
414 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
415 {
416 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
417 }
418
419 #if 0
420 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
421 uint32_t indirect_offset)
422 {
423 ud_info->sgpr_idx = sgpr_idx;
424 ud_info->num_sgprs = num_sgprs;
425 ud_info->indirect = true;
426 ud_info->indirect_offset = indirect_offset;
427 }
428 #endif
429
430 static void create_function(struct nir_to_llvm_context *ctx)
431 {
432 LLVMTypeRef arg_types[23];
433 unsigned arg_idx = 0;
434 unsigned array_params_mask = 0;
435 unsigned sgpr_count = 0, user_sgpr_count;
436 unsigned i;
437 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
438 unsigned user_sgpr_idx;
439 bool need_push_constants;
440 bool need_ring_offsets = false;
441
442 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
443 if (ctx->stage == MESA_SHADER_GEOMETRY ||
444 ctx->stage == MESA_SHADER_VERTEX ||
445 ctx->is_gs_copy_shader)
446 need_ring_offsets = true;
447
448 need_push_constants = true;
449 if (!ctx->options->layout)
450 need_push_constants = false;
451 else if (!ctx->options->layout->push_constant_size &&
452 !ctx->options->layout->dynamic_offset_count)
453 need_push_constants = false;
454
455 if (need_ring_offsets && !ctx->options->supports_spill) {
456 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
457 }
458
459 /* 1 for each descriptor set */
460 for (unsigned i = 0; i < num_sets; ++i) {
461 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
462 array_params_mask |= (1 << arg_idx);
463 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
464 }
465 }
466
467 if (need_push_constants) {
468 /* 1 for push constants and dynamic descriptors */
469 array_params_mask |= (1 << arg_idx);
470 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
471 }
472
473 switch (ctx->stage) {
474 case MESA_SHADER_COMPUTE:
475 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
476 user_sgpr_count = arg_idx;
477 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
478 arg_types[arg_idx++] = ctx->i32;
479 sgpr_count = arg_idx;
480
481 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
482 break;
483 case MESA_SHADER_VERTEX:
484 if (!ctx->is_gs_copy_shader) {
485 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
486 arg_types[arg_idx++] = ctx->i32; // base vertex
487 arg_types[arg_idx++] = ctx->i32; // start instance
488 arg_types[arg_idx++] = ctx->i32; // draw index
489 }
490 user_sgpr_count = arg_idx;
491 if (ctx->options->key.vs.as_es)
492 arg_types[arg_idx++] = ctx->i32; //es2gs offset
493 sgpr_count = arg_idx;
494 arg_types[arg_idx++] = ctx->i32; // vertex id
495 if (!ctx->is_gs_copy_shader) {
496 arg_types[arg_idx++] = ctx->i32; // rel auto id
497 arg_types[arg_idx++] = ctx->i32; // vs prim id
498 arg_types[arg_idx++] = ctx->i32; // instance id
499 }
500 break;
501 case MESA_SHADER_GEOMETRY:
502 arg_types[arg_idx++] = ctx->i32; // gsvs stride
503 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
504 user_sgpr_count = arg_idx;
505 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
506 arg_types[arg_idx++] = ctx->i32; // wave id
507 sgpr_count = arg_idx;
508 arg_types[arg_idx++] = ctx->i32; // vtx0
509 arg_types[arg_idx++] = ctx->i32; // vtx1
510 arg_types[arg_idx++] = ctx->i32; // prim id
511 arg_types[arg_idx++] = ctx->i32; // vtx2
512 arg_types[arg_idx++] = ctx->i32; // vtx3
513 arg_types[arg_idx++] = ctx->i32; // vtx4
514 arg_types[arg_idx++] = ctx->i32; // vtx5
515 arg_types[arg_idx++] = ctx->i32; // GS instance id
516 break;
517 case MESA_SHADER_FRAGMENT:
518 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
519 user_sgpr_count = arg_idx;
520 arg_types[arg_idx++] = ctx->i32; /* prim mask */
521 sgpr_count = arg_idx;
522 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
523 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
524 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
525 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
526 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
527 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
528 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
529 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
530 arg_types[arg_idx++] = ctx->f32; /* pos x float */
531 arg_types[arg_idx++] = ctx->f32; /* pos y float */
532 arg_types[arg_idx++] = ctx->f32; /* pos z float */
533 arg_types[arg_idx++] = ctx->f32; /* pos w float */
534 arg_types[arg_idx++] = ctx->i32; /* front face */
535 arg_types[arg_idx++] = ctx->i32; /* ancillary */
536 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
537 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
538 break;
539 default:
540 unreachable("Shader stage not implemented");
541 }
542
543 ctx->main_function = create_llvm_function(
544 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
545 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
546 set_llvm_calling_convention(ctx->main_function, ctx->stage);
547
548 ctx->shader_info->num_input_sgprs = 0;
549 ctx->shader_info->num_input_vgprs = 0;
550
551 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
552 for (i = 0; i < user_sgpr_count; i++)
553 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
554
555 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
556 for (; i < sgpr_count; i++)
557 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
558
559 if (ctx->stage != MESA_SHADER_FRAGMENT)
560 for (; i < arg_idx; ++i)
561 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
562
563 arg_idx = 0;
564 user_sgpr_idx = 0;
565
566 if (ctx->options->supports_spill || need_ring_offsets) {
567 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
568 user_sgpr_idx += 2;
569 if (ctx->options->supports_spill) {
570 ctx->ring_offsets = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
571 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
572 NULL, 0, AC_FUNC_ATTR_READNONE);
573 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
574 const_array(ctx->v16i8, 8), "");
575 } else
576 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
577 }
578
579 for (unsigned i = 0; i < num_sets; ++i) {
580 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
581 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
582 user_sgpr_idx += 2;
583 ctx->descriptor_sets[i] =
584 LLVMGetParam(ctx->main_function, arg_idx++);
585 } else
586 ctx->descriptor_sets[i] = NULL;
587 }
588
589 if (need_push_constants) {
590 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
591 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
592 user_sgpr_idx += 2;
593 }
594
595 switch (ctx->stage) {
596 case MESA_SHADER_COMPUTE:
597 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
598 user_sgpr_idx += 3;
599 ctx->num_work_groups =
600 LLVMGetParam(ctx->main_function, arg_idx++);
601 ctx->workgroup_ids =
602 LLVMGetParam(ctx->main_function, arg_idx++);
603 ctx->tg_size =
604 LLVMGetParam(ctx->main_function, arg_idx++);
605 ctx->local_invocation_ids =
606 LLVMGetParam(ctx->main_function, arg_idx++);
607 break;
608 case MESA_SHADER_VERTEX:
609 if (!ctx->is_gs_copy_shader) {
610 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
611 user_sgpr_idx += 2;
612 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
613 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
614 user_sgpr_idx += 3;
615 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
616 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
617 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
618 }
619 if (ctx->options->key.vs.as_es)
620 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
621 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
622 if (!ctx->is_gs_copy_shader) {
623 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
624 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
625 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
626 }
627 break;
628 case MESA_SHADER_GEOMETRY:
629 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
630 user_sgpr_idx += 2;
631 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
632 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
633 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
634 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
635 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
636 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
637 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
638 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
639 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
640 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
641 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
642 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
643 break;
644 case MESA_SHADER_FRAGMENT:
645 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
646 user_sgpr_idx += 2;
647 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
648 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
649 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
650 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
651 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
652 arg_idx++;
653 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
654 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
655 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
656 arg_idx++; /* line stipple */
657 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
658 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
659 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
660 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
661 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
662 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
663 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
664 break;
665 default:
666 unreachable("Shader stage not implemented");
667 }
668 }
669
670 static void setup_types(struct nir_to_llvm_context *ctx)
671 {
672 LLVMValueRef args[4];
673
674 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
675 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
676 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
677 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
678 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
679 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
680 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
681 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
682 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
683 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
684 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
685 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
686 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
687 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
688 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
689 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
690
691 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
692 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
693 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
694 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
695
696 args[0] = ctx->f32zero;
697 args[1] = ctx->f32zero;
698 args[2] = ctx->f32zero;
699 args[3] = ctx->f32one;
700 ctx->v4f32empty = LLVMConstVector(args, 4);
701
702 ctx->uniform_md_kind =
703 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
704 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
705
706 args[0] = LLVMConstReal(ctx->f32, 2.5);
707 }
708
709 static int get_llvm_num_components(LLVMValueRef value)
710 {
711 LLVMTypeRef type = LLVMTypeOf(value);
712 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
713 ? LLVMGetVectorSize(type)
714 : 1;
715 return num_components;
716 }
717
718 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
719 LLVMValueRef value,
720 int index)
721 {
722 int count = get_llvm_num_components(value);
723
724 assert(index < count);
725 if (count == 1)
726 return value;
727
728 return LLVMBuildExtractElement(ctx->builder, value,
729 LLVMConstInt(ctx->i32, index, false), "");
730 }
731
732 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
733 LLVMValueRef value, unsigned count)
734 {
735 unsigned num_components = get_llvm_num_components(value);
736 if (count == num_components)
737 return value;
738
739 LLVMValueRef masks[] = {
740 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
741 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
742
743 if (count == 1)
744 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
745 "");
746
747 LLVMValueRef swizzle = LLVMConstVector(masks, count);
748 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
749 }
750
751 static void
752 build_store_values_extended(struct nir_to_llvm_context *ctx,
753 LLVMValueRef *values,
754 unsigned value_count,
755 unsigned value_stride,
756 LLVMValueRef vec)
757 {
758 LLVMBuilderRef builder = ctx->builder;
759 unsigned i;
760
761 if (value_count == 1) {
762 LLVMBuildStore(builder, vec, values[0]);
763 return;
764 }
765
766 for (i = 0; i < value_count; i++) {
767 LLVMValueRef ptr = values[i * value_stride];
768 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
769 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
770 LLVMBuildStore(builder, value, ptr);
771 }
772 }
773
774 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
775 nir_ssa_def *def)
776 {
777 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
778 if (def->num_components > 1) {
779 type = LLVMVectorType(type, def->num_components);
780 }
781 return type;
782 }
783
784 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
785 {
786 assert(src.is_ssa);
787 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
788 return (LLVMValueRef)entry->data;
789 }
790
791
792 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
793 struct nir_block *b)
794 {
795 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
796 return (LLVMBasicBlockRef)entry->data;
797 }
798
799 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
800 nir_alu_src src,
801 unsigned num_components)
802 {
803 LLVMValueRef value = get_src(ctx, src.src);
804 bool need_swizzle = false;
805
806 assert(value);
807 LLVMTypeRef type = LLVMTypeOf(value);
808 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
809 ? LLVMGetVectorSize(type)
810 : 1;
811
812 for (unsigned i = 0; i < num_components; ++i) {
813 assert(src.swizzle[i] < src_components);
814 if (src.swizzle[i] != i)
815 need_swizzle = true;
816 }
817
818 if (need_swizzle || num_components != src_components) {
819 LLVMValueRef masks[] = {
820 LLVMConstInt(ctx->i32, src.swizzle[0], false),
821 LLVMConstInt(ctx->i32, src.swizzle[1], false),
822 LLVMConstInt(ctx->i32, src.swizzle[2], false),
823 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
824
825 if (src_components > 1 && num_components == 1) {
826 value = LLVMBuildExtractElement(ctx->builder, value,
827 masks[0], "");
828 } else if (src_components == 1 && num_components > 1) {
829 LLVMValueRef values[] = {value, value, value, value};
830 value = ac_build_gather_values(&ctx->ac, values, num_components);
831 } else {
832 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
833 value = LLVMBuildShuffleVector(ctx->builder, value, value,
834 swizzle, "");
835 }
836 }
837 assert(!src.negate);
838 assert(!src.abs);
839 return value;
840 }
841
842 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
843 LLVMIntPredicate pred, LLVMValueRef src0,
844 LLVMValueRef src1)
845 {
846 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
847 return LLVMBuildSelect(ctx->builder, result,
848 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
849 LLVMConstInt(ctx->i32, 0, false), "");
850 }
851
852 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
853 LLVMRealPredicate pred, LLVMValueRef src0,
854 LLVMValueRef src1)
855 {
856 LLVMValueRef result;
857 src0 = to_float(ctx, src0);
858 src1 = to_float(ctx, src1);
859 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
860 return LLVMBuildSelect(ctx->builder, result,
861 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
862 LLVMConstInt(ctx->i32, 0, false), "");
863 }
864
865 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
866 const char *intrin,
867 LLVMTypeRef result_type,
868 LLVMValueRef src0)
869 {
870 char name[64];
871 LLVMValueRef params[] = {
872 to_float(ctx, src0),
873 };
874
875 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
876 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
877 }
878
879 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
880 const char *intrin,
881 LLVMTypeRef result_type,
882 LLVMValueRef src0, LLVMValueRef src1)
883 {
884 char name[64];
885 LLVMValueRef params[] = {
886 to_float(ctx, src0),
887 to_float(ctx, src1),
888 };
889
890 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
891 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
892 }
893
894 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
895 const char *intrin,
896 LLVMTypeRef result_type,
897 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
898 {
899 char name[64];
900 LLVMValueRef params[] = {
901 to_float(ctx, src0),
902 to_float(ctx, src1),
903 to_float(ctx, src2),
904 };
905
906 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
907 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
908 }
909
910 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
911 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
912 {
913 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
914 ctx->i32zero, "");
915 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
916 }
917
918 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
919 LLVMValueRef src0)
920 {
921 LLVMValueRef params[2] = {
922 src0,
923
924 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
925 * add special code to check for x=0. The reason is that
926 * the LLVM behavior for x=0 is different from what we
927 * need here.
928 *
929 * The hardware already implements the correct behavior.
930 */
931 LLVMConstInt(ctx->i32, 1, false),
932 };
933 return ac_emit_llvm_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
934 }
935
936 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
937 LLVMValueRef src0)
938 {
939 return ac_emit_imsb(&ctx->ac, src0, ctx->i32);
940 }
941
942 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
943 LLVMValueRef src0)
944 {
945 return ac_emit_umsb(&ctx->ac, src0, ctx->i32);
946 }
947
948 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
949 LLVMIntPredicate pred,
950 LLVMValueRef src0, LLVMValueRef src1)
951 {
952 return LLVMBuildSelect(ctx->builder,
953 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
954 src0,
955 src1, "");
956
957 }
958 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
959 LLVMValueRef src0)
960 {
961 return emit_minmax_int(ctx, LLVMIntSGT, src0,
962 LLVMBuildNeg(ctx->builder, src0, ""));
963 }
964
965 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
966 LLVMValueRef src0)
967 {
968 LLVMValueRef cmp, val;
969
970 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
971 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
972 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
973 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
974 return val;
975 }
976
977 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
978 LLVMValueRef src0)
979 {
980 LLVMValueRef cmp, val;
981
982 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
983 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
984 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
985 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
986 return val;
987 }
988
989 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
990 LLVMValueRef src0)
991 {
992 const char *intr = "llvm.floor.f32";
993 LLVMValueRef fsrc0 = to_float(ctx, src0);
994 LLVMValueRef params[] = {
995 fsrc0,
996 };
997 LLVMValueRef floor = ac_emit_llvm_intrinsic(&ctx->ac, intr,
998 ctx->f32, params, 1,
999 AC_FUNC_ATTR_READNONE);
1000 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1001 }
1002
1003 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1004 const char *intrin,
1005 LLVMValueRef src0, LLVMValueRef src1)
1006 {
1007 LLVMTypeRef ret_type;
1008 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1009 LLVMValueRef res;
1010 LLVMValueRef params[] = { src0, src1 };
1011 ret_type = LLVMStructTypeInContext(ctx->context, types,
1012 2, true);
1013
1014 res = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ret_type,
1015 params, 2, AC_FUNC_ATTR_READNONE);
1016
1017 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1018 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1019 return res;
1020 }
1021
1022 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1023 LLVMValueRef src0)
1024 {
1025 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1026 }
1027
1028 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1029 LLVMValueRef src0, LLVMValueRef src1)
1030 {
1031 LLVMValueRef dst64, result;
1032 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1033 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1034
1035 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1036 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1037 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1038 return result;
1039 }
1040
1041 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1042 LLVMValueRef src0, LLVMValueRef src1)
1043 {
1044 LLVMValueRef dst64, result;
1045 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1046 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1047
1048 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1049 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1050 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1051 return result;
1052 }
1053
1054 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1055 const char *intrin,
1056 LLVMValueRef srcs[3])
1057 {
1058 LLVMValueRef result;
1059 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1060 result = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->i32, srcs, 3, AC_FUNC_ATTR_READNONE);
1061
1062 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1063 return result;
1064 }
1065
1066 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1067 LLVMValueRef src0, LLVMValueRef src1,
1068 LLVMValueRef src2, LLVMValueRef src3)
1069 {
1070 LLVMValueRef bfi_args[3], result;
1071
1072 bfi_args[0] = LLVMBuildShl(ctx->builder,
1073 LLVMBuildSub(ctx->builder,
1074 LLVMBuildShl(ctx->builder,
1075 ctx->i32one,
1076 src3, ""),
1077 ctx->i32one, ""),
1078 src2, "");
1079 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1080 bfi_args[2] = src0;
1081
1082 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1083
1084 /* Calculate:
1085 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1086 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1087 */
1088 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1089 LLVMBuildAnd(ctx->builder, bfi_args[0],
1090 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1091
1092 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1093 return result;
1094 }
1095
1096 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1097 LLVMValueRef src0)
1098 {
1099 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1100 int i;
1101 LLVMValueRef comp[2];
1102
1103 src0 = to_float(ctx, src0);
1104 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1105 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1106 for (i = 0; i < 2; i++) {
1107 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1108 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1109 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1110 }
1111
1112 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1113 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1114
1115 return comp[0];
1116 }
1117
1118 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1119 LLVMValueRef src0)
1120 {
1121 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1122 LLVMValueRef temps[2], result, val;
1123 int i;
1124
1125 for (i = 0; i < 2; i++) {
1126 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1127 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1128 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1129 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1130 }
1131
1132 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1133 ctx->i32zero, "");
1134 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1135 ctx->i32one, "");
1136 return result;
1137 }
1138
1139 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1140 nir_op op,
1141 LLVMValueRef src0)
1142 {
1143 unsigned mask;
1144 int idx;
1145 LLVMValueRef result;
1146 ctx->has_ddxy = true;
1147
1148 if (!ctx->lds && !ctx->has_ds_bpermute)
1149 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1150 LLVMArrayType(ctx->i32, 64),
1151 "ddxy_lds", LOCAL_ADDR_SPACE);
1152
1153 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1154 mask = AC_TID_MASK_LEFT;
1155 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1156 mask = AC_TID_MASK_TOP;
1157 else
1158 mask = AC_TID_MASK_TOP_LEFT;
1159
1160 /* for DDX we want to next X pixel, DDY next Y pixel. */
1161 if (op == nir_op_fddx_fine ||
1162 op == nir_op_fddx_coarse ||
1163 op == nir_op_fddx)
1164 idx = 1;
1165 else
1166 idx = 2;
1167
1168 result = ac_emit_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1169 mask, idx, ctx->lds,
1170 src0);
1171 return result;
1172 }
1173
1174 /*
1175 * this takes an I,J coordinate pair,
1176 * and works out the X and Y derivatives.
1177 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1178 */
1179 static LLVMValueRef emit_ddxy_interp(
1180 struct nir_to_llvm_context *ctx,
1181 LLVMValueRef interp_ij)
1182 {
1183 LLVMValueRef result[4], a;
1184 unsigned i;
1185
1186 for (i = 0; i < 2; i++) {
1187 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1188 LLVMConstInt(ctx->i32, i, false), "");
1189 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1190 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1191 }
1192 return ac_build_gather_values(&ctx->ac, result, 4);
1193 }
1194
1195 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1196 {
1197 LLVMValueRef src[4], result = NULL;
1198 unsigned num_components = instr->dest.dest.ssa.num_components;
1199 unsigned src_components;
1200 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1201
1202 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1203 switch (instr->op) {
1204 case nir_op_vec2:
1205 case nir_op_vec3:
1206 case nir_op_vec4:
1207 src_components = 1;
1208 break;
1209 case nir_op_pack_half_2x16:
1210 src_components = 2;
1211 break;
1212 case nir_op_unpack_half_2x16:
1213 src_components = 1;
1214 break;
1215 default:
1216 src_components = num_components;
1217 break;
1218 }
1219 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1220 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1221
1222 switch (instr->op) {
1223 case nir_op_fmov:
1224 case nir_op_imov:
1225 result = src[0];
1226 break;
1227 case nir_op_fneg:
1228 src[0] = to_float(ctx, src[0]);
1229 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1230 break;
1231 case nir_op_ineg:
1232 result = LLVMBuildNeg(ctx->builder, src[0], "");
1233 break;
1234 case nir_op_inot:
1235 result = LLVMBuildNot(ctx->builder, src[0], "");
1236 break;
1237 case nir_op_iadd:
1238 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1239 break;
1240 case nir_op_fadd:
1241 src[0] = to_float(ctx, src[0]);
1242 src[1] = to_float(ctx, src[1]);
1243 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1244 break;
1245 case nir_op_fsub:
1246 src[0] = to_float(ctx, src[0]);
1247 src[1] = to_float(ctx, src[1]);
1248 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1249 break;
1250 case nir_op_isub:
1251 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1252 break;
1253 case nir_op_imul:
1254 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1255 break;
1256 case nir_op_imod:
1257 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1258 break;
1259 case nir_op_umod:
1260 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1261 break;
1262 case nir_op_fmod:
1263 src[0] = to_float(ctx, src[0]);
1264 src[1] = to_float(ctx, src[1]);
1265 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1266 result = emit_intrin_1f_param(ctx, "llvm.floor",
1267 to_float_type(ctx, def_type), result);
1268 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1269 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1270 break;
1271 case nir_op_frem:
1272 src[0] = to_float(ctx, src[0]);
1273 src[1] = to_float(ctx, src[1]);
1274 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1275 break;
1276 case nir_op_irem:
1277 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1278 break;
1279 case nir_op_idiv:
1280 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1281 break;
1282 case nir_op_udiv:
1283 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1284 break;
1285 case nir_op_fmul:
1286 src[0] = to_float(ctx, src[0]);
1287 src[1] = to_float(ctx, src[1]);
1288 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1289 break;
1290 case nir_op_fdiv:
1291 src[0] = to_float(ctx, src[0]);
1292 src[1] = to_float(ctx, src[1]);
1293 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1294 break;
1295 case nir_op_frcp:
1296 src[0] = to_float(ctx, src[0]);
1297 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, src[0]);
1298 break;
1299 case nir_op_iand:
1300 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1301 break;
1302 case nir_op_ior:
1303 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1304 break;
1305 case nir_op_ixor:
1306 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1307 break;
1308 case nir_op_ishl:
1309 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1310 break;
1311 case nir_op_ishr:
1312 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1313 break;
1314 case nir_op_ushr:
1315 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1316 break;
1317 case nir_op_ilt:
1318 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1319 break;
1320 case nir_op_ine:
1321 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1322 break;
1323 case nir_op_ieq:
1324 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1325 break;
1326 case nir_op_ige:
1327 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1328 break;
1329 case nir_op_ult:
1330 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1331 break;
1332 case nir_op_uge:
1333 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1334 break;
1335 case nir_op_feq:
1336 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1337 break;
1338 case nir_op_fne:
1339 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1340 break;
1341 case nir_op_flt:
1342 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1343 break;
1344 case nir_op_fge:
1345 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1346 break;
1347 case nir_op_fabs:
1348 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1349 to_float_type(ctx, def_type), src[0]);
1350 break;
1351 case nir_op_iabs:
1352 result = emit_iabs(ctx, src[0]);
1353 break;
1354 case nir_op_imax:
1355 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1356 break;
1357 case nir_op_imin:
1358 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1359 break;
1360 case nir_op_umax:
1361 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1362 break;
1363 case nir_op_umin:
1364 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1365 break;
1366 case nir_op_isign:
1367 result = emit_isign(ctx, src[0]);
1368 break;
1369 case nir_op_fsign:
1370 src[0] = to_float(ctx, src[0]);
1371 result = emit_fsign(ctx, src[0]);
1372 break;
1373 case nir_op_ffloor:
1374 result = emit_intrin_1f_param(ctx, "llvm.floor",
1375 to_float_type(ctx, def_type), src[0]);
1376 break;
1377 case nir_op_ftrunc:
1378 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1379 to_float_type(ctx, def_type), src[0]);
1380 break;
1381 case nir_op_fceil:
1382 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1383 to_float_type(ctx, def_type), src[0]);
1384 break;
1385 case nir_op_fround_even:
1386 result = emit_intrin_1f_param(ctx, "llvm.rint",
1387 to_float_type(ctx, def_type),src[0]);
1388 break;
1389 case nir_op_ffract:
1390 result = emit_ffract(ctx, src[0]);
1391 break;
1392 case nir_op_fsin:
1393 result = emit_intrin_1f_param(ctx, "llvm.sin",
1394 to_float_type(ctx, def_type), src[0]);
1395 break;
1396 case nir_op_fcos:
1397 result = emit_intrin_1f_param(ctx, "llvm.cos",
1398 to_float_type(ctx, def_type), src[0]);
1399 break;
1400 case nir_op_fsqrt:
1401 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1402 to_float_type(ctx, def_type), src[0]);
1403 break;
1404 case nir_op_fexp2:
1405 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1406 to_float_type(ctx, def_type), src[0]);
1407 break;
1408 case nir_op_flog2:
1409 result = emit_intrin_1f_param(ctx, "llvm.log2",
1410 to_float_type(ctx, def_type), src[0]);
1411 break;
1412 case nir_op_frsq:
1413 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1414 to_float_type(ctx, def_type), src[0]);
1415 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, result);
1416 break;
1417 case nir_op_fpow:
1418 result = emit_intrin_2f_param(ctx, "llvm.pow",
1419 to_float_type(ctx, def_type), src[0], src[1]);
1420 break;
1421 case nir_op_fmax:
1422 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1423 to_float_type(ctx, def_type), src[0], src[1]);
1424 break;
1425 case nir_op_fmin:
1426 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1427 to_float_type(ctx, def_type), src[0], src[1]);
1428 break;
1429 case nir_op_ffma:
1430 result = emit_intrin_3f_param(ctx, "llvm.fma",
1431 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1432 break;
1433 case nir_op_ibitfield_extract:
1434 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.i32", src);
1435 break;
1436 case nir_op_ubitfield_extract:
1437 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.u32", src);
1438 break;
1439 case nir_op_bitfield_insert:
1440 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1441 break;
1442 case nir_op_bitfield_reverse:
1443 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1444 break;
1445 case nir_op_bit_count:
1446 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1447 break;
1448 case nir_op_vec2:
1449 case nir_op_vec3:
1450 case nir_op_vec4:
1451 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1452 src[i] = to_integer(ctx, src[i]);
1453 result = ac_build_gather_values(&ctx->ac, src, num_components);
1454 break;
1455 case nir_op_d2i:
1456 case nir_op_f2i:
1457 src[0] = to_float(ctx, src[0]);
1458 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1459 break;
1460 case nir_op_d2u:
1461 case nir_op_f2u:
1462 src[0] = to_float(ctx, src[0]);
1463 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1464 break;
1465 case nir_op_i2d:
1466 case nir_op_i2f:
1467 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1468 break;
1469 case nir_op_u2d:
1470 case nir_op_u2f:
1471 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1472 break;
1473 case nir_op_f2d:
1474 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1475 break;
1476 case nir_op_d2f:
1477 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1478 break;
1479 case nir_op_bcsel:
1480 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1481 break;
1482 case nir_op_find_lsb:
1483 result = emit_find_lsb(ctx, src[0]);
1484 break;
1485 case nir_op_ufind_msb:
1486 result = emit_ufind_msb(ctx, src[0]);
1487 break;
1488 case nir_op_ifind_msb:
1489 result = emit_ifind_msb(ctx, src[0]);
1490 break;
1491 case nir_op_uadd_carry:
1492 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1493 break;
1494 case nir_op_usub_borrow:
1495 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1496 break;
1497 case nir_op_b2f:
1498 result = emit_b2f(ctx, src[0]);
1499 break;
1500 case nir_op_fquantize2f16:
1501 src[0] = to_float(ctx, src[0]);
1502 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1503 /* need to convert back up to f32 */
1504 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1505 break;
1506 case nir_op_umul_high:
1507 result = emit_umul_high(ctx, src[0], src[1]);
1508 break;
1509 case nir_op_imul_high:
1510 result = emit_imul_high(ctx, src[0], src[1]);
1511 break;
1512 case nir_op_pack_half_2x16:
1513 result = emit_pack_half_2x16(ctx, src[0]);
1514 break;
1515 case nir_op_unpack_half_2x16:
1516 result = emit_unpack_half_2x16(ctx, src[0]);
1517 break;
1518 case nir_op_fddx:
1519 case nir_op_fddy:
1520 case nir_op_fddx_fine:
1521 case nir_op_fddy_fine:
1522 case nir_op_fddx_coarse:
1523 case nir_op_fddy_coarse:
1524 result = emit_ddxy(ctx, instr->op, src[0]);
1525 break;
1526 default:
1527 fprintf(stderr, "Unknown NIR alu instr: ");
1528 nir_print_instr(&instr->instr, stderr);
1529 fprintf(stderr, "\n");
1530 abort();
1531 }
1532
1533 if (result) {
1534 assert(instr->dest.dest.is_ssa);
1535 result = to_integer(ctx, result);
1536 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1537 result);
1538 }
1539 }
1540
1541 static void visit_load_const(struct nir_to_llvm_context *ctx,
1542 nir_load_const_instr *instr)
1543 {
1544 LLVMValueRef values[4], value = NULL;
1545 LLVMTypeRef element_type =
1546 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1547
1548 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1549 switch (instr->def.bit_size) {
1550 case 32:
1551 values[i] = LLVMConstInt(element_type,
1552 instr->value.u32[i], false);
1553 break;
1554 case 64:
1555 values[i] = LLVMConstInt(element_type,
1556 instr->value.u64[i], false);
1557 break;
1558 default:
1559 fprintf(stderr,
1560 "unsupported nir load_const bit_size: %d\n",
1561 instr->def.bit_size);
1562 abort();
1563 }
1564 }
1565 if (instr->def.num_components > 1) {
1566 value = LLVMConstVector(values, instr->def.num_components);
1567 } else
1568 value = values[0];
1569
1570 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1571 }
1572
1573 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1574 LLVMTypeRef type)
1575 {
1576 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1577 return LLVMBuildBitCast(ctx->builder, ptr,
1578 LLVMPointerType(type, addr_space), "");
1579 }
1580
1581 static LLVMValueRef
1582 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1583 {
1584 LLVMValueRef size =
1585 LLVMBuildExtractElement(ctx->builder, descriptor,
1586 LLVMConstInt(ctx->i32, 2, false), "");
1587
1588 /* VI only */
1589 if (ctx->options->chip_class >= VI && in_elements) {
1590 /* On VI, the descriptor contains the size in bytes,
1591 * but TXQ must return the size in elements.
1592 * The stride is always non-zero for resources using TXQ.
1593 */
1594 LLVMValueRef stride =
1595 LLVMBuildExtractElement(ctx->builder, descriptor,
1596 LLVMConstInt(ctx->i32, 1, false), "");
1597 stride = LLVMBuildLShr(ctx->builder, stride,
1598 LLVMConstInt(ctx->i32, 16, false), "");
1599 stride = LLVMBuildAnd(ctx->builder, stride,
1600 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1601
1602 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1603 }
1604 return size;
1605 }
1606
1607 /**
1608 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1609 * intrinsic names).
1610 */
1611 static void build_int_type_name(
1612 LLVMTypeRef type,
1613 char *buf, unsigned bufsize)
1614 {
1615 assert(bufsize >= 6);
1616
1617 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1618 snprintf(buf, bufsize, "v%ui32",
1619 LLVMGetVectorSize(type));
1620 else
1621 strcpy(buf, "i32");
1622 }
1623
1624 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1625 struct ac_tex_info *tinfo,
1626 nir_tex_instr *instr,
1627 const char *intr_name,
1628 unsigned coord_vgpr_index)
1629 {
1630 LLVMValueRef coord = tinfo->args[0];
1631 LLVMValueRef half_texel[2];
1632 int c;
1633
1634 //TODO Rect
1635 {
1636 LLVMValueRef txq_args[10];
1637 int txq_arg_count = 0;
1638 LLVMValueRef size;
1639 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1640 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, false);
1641 txq_args[txq_arg_count++] = tinfo->args[1];
1642 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0xf, 0); /* dmask */
1643 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* unorm */
1644 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
1645 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
1646 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
1647 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
1648 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
1649 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
1650 size = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
1651 txq_args, txq_arg_count,
1652 AC_FUNC_ATTR_READNONE);
1653
1654 for (c = 0; c < 2; c++) {
1655 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1656 LLVMConstInt(ctx->i32, c, false), "");
1657 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1658 half_texel[c] = ac_emit_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1659 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1660 LLVMConstReal(ctx->f32, -0.5), "");
1661 }
1662 }
1663
1664 for (c = 0; c < 2; c++) {
1665 LLVMValueRef tmp;
1666 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1667 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1668 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1669 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1670 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1671 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1672 }
1673
1674 tinfo->args[0] = coord;
1675 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1676 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1677
1678 }
1679
1680 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1681 nir_tex_instr *instr,
1682 struct ac_tex_info *tinfo)
1683 {
1684 const char *name = "llvm.SI.image.sample";
1685 const char *infix = "";
1686 char intr_name[127];
1687 char type[64];
1688 bool is_shadow = instr->is_shadow;
1689 bool has_offset = tinfo->has_offset;
1690 switch (instr->op) {
1691 case nir_texop_txf:
1692 case nir_texop_txf_ms:
1693 case nir_texop_samples_identical:
1694 name = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? "llvm.SI.image.load" :
1695 instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? "llvm.SI.vs.load.input" :
1696 "llvm.SI.image.load.mip";
1697 is_shadow = false;
1698 has_offset = false;
1699 break;
1700 case nir_texop_txb:
1701 infix = ".b";
1702 break;
1703 case nir_texop_txl:
1704 infix = ".l";
1705 break;
1706 case nir_texop_txs:
1707 name = "llvm.SI.getresinfo";
1708 break;
1709 case nir_texop_query_levels:
1710 name = "llvm.SI.getresinfo";
1711 break;
1712 case nir_texop_tex:
1713 if (ctx->stage != MESA_SHADER_FRAGMENT)
1714 infix = ".lz";
1715 break;
1716 case nir_texop_txd:
1717 infix = ".d";
1718 break;
1719 case nir_texop_tg4:
1720 name = "llvm.SI.gather4";
1721 infix = ".lz";
1722 break;
1723 case nir_texop_lod:
1724 name = "llvm.SI.getlod";
1725 is_shadow = false;
1726 has_offset = false;
1727 break;
1728 default:
1729 break;
1730 }
1731
1732 build_int_type_name(LLVMTypeOf(tinfo->args[0]), type, sizeof(type));
1733 sprintf(intr_name, "%s%s%s%s.%s", name, is_shadow ? ".c" : "", infix,
1734 has_offset ? ".o" : "", type);
1735
1736 if (instr->op == nir_texop_tg4) {
1737 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1738 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1739 return radv_lower_gather4_integer(ctx, tinfo, instr, intr_name,
1740 (int)has_offset + (int)is_shadow);
1741 }
1742 }
1743 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1744 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1745
1746 }
1747
1748 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1749 nir_intrinsic_instr *instr)
1750 {
1751 LLVMValueRef index = get_src(ctx, instr->src[0]);
1752 unsigned desc_set = nir_intrinsic_desc_set(instr);
1753 unsigned binding = nir_intrinsic_binding(instr);
1754 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1755 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
1756 unsigned base_offset = layout->binding[binding].offset;
1757 LLVMValueRef offset, stride;
1758
1759 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1760 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1761 desc_ptr = ctx->push_constants;
1762 base_offset = ctx->options->layout->push_constant_size;
1763 base_offset += 16 * layout->binding[binding].dynamic_offset_offset;
1764 stride = LLVMConstInt(ctx->i32, 16, false);
1765 } else
1766 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1767
1768 offset = LLVMConstInt(ctx->i32, base_offset, false);
1769 index = LLVMBuildMul(ctx->builder, index, stride, "");
1770 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1771
1772 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1773 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1774 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1775
1776 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1777 }
1778
1779 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1780 nir_intrinsic_instr *instr)
1781 {
1782 LLVMValueRef ptr, addr;
1783
1784 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1785 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1786
1787 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
1788 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1789
1790 return LLVMBuildLoad(ctx->builder, ptr, "");
1791 }
1792
1793 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1794 nir_intrinsic_instr *instr)
1795 {
1796 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1797
1798 return get_buffer_size(ctx, desc, false);
1799 }
1800 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1801 nir_intrinsic_instr *instr)
1802 {
1803 const char *store_name;
1804 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
1805 LLVMTypeRef data_type = ctx->f32;
1806 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
1807 int components_32bit = elem_size_mult * instr->num_components;
1808 unsigned writemask = nir_intrinsic_write_mask(instr);
1809 LLVMValueRef base_data, base_offset;
1810 LLVMValueRef params[6];
1811
1812 if (ctx->stage == MESA_SHADER_FRAGMENT)
1813 ctx->shader_info->fs.writes_memory = true;
1814
1815 params[1] = get_src(ctx, instr->src[1]);
1816 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1817 params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
1818 params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1819
1820 if (components_32bit > 1)
1821 data_type = LLVMVectorType(ctx->f32, components_32bit);
1822
1823 base_data = to_float(ctx, src_data);
1824 base_data = trim_vector(ctx, base_data, instr->num_components);
1825 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1826 data_type, "");
1827 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1828 while (writemask) {
1829 int start, count;
1830 LLVMValueRef data;
1831 LLVMValueRef offset;
1832 LLVMValueRef tmp;
1833 u_bit_scan_consecutive_range(&writemask, &start, &count);
1834
1835 /* Due to an LLVM limitation, split 3-element writes
1836 * into a 2-element and a 1-element write. */
1837 if (count == 3) {
1838 writemask |= 1 << (start + 2);
1839 count = 2;
1840 }
1841
1842 start *= elem_size_mult;
1843 count *= elem_size_mult;
1844
1845 if (count > 4) {
1846 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
1847 count = 4;
1848 }
1849
1850 if (count == 4) {
1851 store_name = "llvm.amdgcn.buffer.store.v4f32";
1852 data = base_data;
1853 } else if (count == 2) {
1854 tmp = LLVMBuildExtractElement(ctx->builder,
1855 base_data, LLVMConstInt(ctx->i32, start, false), "");
1856 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
1857 ctx->i32zero, "");
1858
1859 tmp = LLVMBuildExtractElement(ctx->builder,
1860 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
1861 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
1862 ctx->i32one, "");
1863 store_name = "llvm.amdgcn.buffer.store.v2f32";
1864
1865 } else {
1866 assert(count == 1);
1867 if (get_llvm_num_components(base_data) > 1)
1868 data = LLVMBuildExtractElement(ctx->builder, base_data,
1869 LLVMConstInt(ctx->i32, start, false), "");
1870 else
1871 data = base_data;
1872 store_name = "llvm.amdgcn.buffer.store.f32";
1873 }
1874
1875 offset = base_offset;
1876 if (start != 0) {
1877 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
1878 }
1879 params[0] = data;
1880 params[3] = offset;
1881 ac_emit_llvm_intrinsic(&ctx->ac, store_name,
1882 ctx->voidt, params, 6, 0);
1883 }
1884 }
1885
1886 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
1887 nir_intrinsic_instr *instr)
1888 {
1889 const char *name;
1890 LLVMValueRef params[6];
1891 int arg_count = 0;
1892 if (ctx->stage == MESA_SHADER_FRAGMENT)
1893 ctx->shader_info->fs.writes_memory = true;
1894
1895 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
1896 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
1897 }
1898 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
1899 params[arg_count++] = get_src(ctx, instr->src[0]);
1900 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1901 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
1902 params[arg_count++] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1903
1904 switch (instr->intrinsic) {
1905 case nir_intrinsic_ssbo_atomic_add:
1906 name = "llvm.amdgcn.buffer.atomic.add";
1907 break;
1908 case nir_intrinsic_ssbo_atomic_imin:
1909 name = "llvm.amdgcn.buffer.atomic.smin";
1910 break;
1911 case nir_intrinsic_ssbo_atomic_umin:
1912 name = "llvm.amdgcn.buffer.atomic.umin";
1913 break;
1914 case nir_intrinsic_ssbo_atomic_imax:
1915 name = "llvm.amdgcn.buffer.atomic.smax";
1916 break;
1917 case nir_intrinsic_ssbo_atomic_umax:
1918 name = "llvm.amdgcn.buffer.atomic.umax";
1919 break;
1920 case nir_intrinsic_ssbo_atomic_and:
1921 name = "llvm.amdgcn.buffer.atomic.and";
1922 break;
1923 case nir_intrinsic_ssbo_atomic_or:
1924 name = "llvm.amdgcn.buffer.atomic.or";
1925 break;
1926 case nir_intrinsic_ssbo_atomic_xor:
1927 name = "llvm.amdgcn.buffer.atomic.xor";
1928 break;
1929 case nir_intrinsic_ssbo_atomic_exchange:
1930 name = "llvm.amdgcn.buffer.atomic.swap";
1931 break;
1932 case nir_intrinsic_ssbo_atomic_comp_swap:
1933 name = "llvm.amdgcn.buffer.atomic.cmpswap";
1934 break;
1935 default:
1936 abort();
1937 }
1938
1939 return ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
1940 }
1941
1942 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
1943 nir_intrinsic_instr *instr)
1944 {
1945 LLVMValueRef results[2];
1946 int load_components;
1947 int num_components = instr->num_components;
1948 if (instr->dest.ssa.bit_size == 64)
1949 num_components *= 2;
1950
1951 for (int i = 0; i < num_components; i += load_components) {
1952 load_components = MIN2(num_components - i, 4);
1953 const char *load_name;
1954 LLVMTypeRef data_type = ctx->f32;
1955 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
1956 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
1957
1958 if (load_components == 3)
1959 data_type = LLVMVectorType(ctx->f32, 4);
1960 else if (load_components > 1)
1961 data_type = LLVMVectorType(ctx->f32, load_components);
1962
1963 if (load_components >= 3)
1964 load_name = "llvm.amdgcn.buffer.load.v4f32";
1965 else if (load_components == 2)
1966 load_name = "llvm.amdgcn.buffer.load.v2f32";
1967 else if (load_components == 1)
1968 load_name = "llvm.amdgcn.buffer.load.f32";
1969 else
1970 unreachable("unhandled number of components");
1971
1972 LLVMValueRef params[] = {
1973 get_src(ctx, instr->src[0]),
1974 LLVMConstInt(ctx->i32, 0, false),
1975 offset,
1976 LLVMConstInt(ctx->i1, 0, false),
1977 LLVMConstInt(ctx->i1, 0, false),
1978 };
1979
1980 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
1981
1982 }
1983
1984 LLVMValueRef ret = results[0];
1985 if (num_components > 4 || num_components == 3) {
1986 LLVMValueRef masks[] = {
1987 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1988 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
1989 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
1990 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
1991 };
1992
1993 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1994 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
1995 results[num_components > 4 ? 1 : 0], swizzle, "");
1996 }
1997
1998 return LLVMBuildBitCast(ctx->builder, ret,
1999 get_def_type(ctx, &instr->dest.ssa), "");
2000 }
2001
2002 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2003 nir_intrinsic_instr *instr)
2004 {
2005 LLVMValueRef results[8], ret;
2006 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2007 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2008 int num_components = instr->num_components;
2009
2010 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2011
2012 if (instr->dest.ssa.bit_size == 64)
2013 num_components *= 2;
2014
2015 for (unsigned i = 0; i < num_components; ++i) {
2016 LLVMValueRef params[] = {
2017 rsrc,
2018 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2019 offset, "")
2020 };
2021 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2022 params, 2, AC_FUNC_ATTR_READNONE);
2023 }
2024
2025
2026 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2027 return LLVMBuildBitCast(ctx->builder, ret,
2028 get_def_type(ctx, &instr->dest.ssa), "");
2029 }
2030
2031 static void
2032 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2033 bool vs_in, unsigned *vertex_index_out,
2034 unsigned *const_out, LLVMValueRef *indir_out)
2035 {
2036 unsigned const_offset = 0;
2037 LLVMValueRef offset = NULL;
2038
2039 if (vertex_index_out != NULL) {
2040 tail = tail->child;
2041 nir_deref_array *deref_array = nir_deref_as_array(tail);
2042 *vertex_index_out = deref_array->base_offset;
2043 }
2044
2045 while (tail->child != NULL) {
2046 const struct glsl_type *parent_type = tail->type;
2047 tail = tail->child;
2048
2049 if (tail->deref_type == nir_deref_type_array) {
2050 nir_deref_array *deref_array = nir_deref_as_array(tail);
2051 LLVMValueRef index, stride, local_offset;
2052 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2053
2054 const_offset += size * deref_array->base_offset;
2055 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2056 continue;
2057
2058 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2059 index = get_src(ctx, deref_array->indirect);
2060 stride = LLVMConstInt(ctx->i32, size, 0);
2061 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2062
2063 if (offset)
2064 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2065 else
2066 offset = local_offset;
2067 } else if (tail->deref_type == nir_deref_type_struct) {
2068 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2069
2070 for (unsigned i = 0; i < deref_struct->index; i++) {
2071 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2072 const_offset += glsl_count_attribute_slots(ft, vs_in);
2073 }
2074 } else
2075 unreachable("unsupported deref type");
2076
2077 }
2078
2079 if (const_offset && offset)
2080 offset = LLVMBuildAdd(ctx->builder, offset,
2081 LLVMConstInt(ctx->i32, const_offset, 0),
2082 "");
2083
2084 *const_out = const_offset;
2085 *indir_out = offset;
2086 }
2087
2088 static LLVMValueRef
2089 load_gs_input(struct nir_to_llvm_context *ctx,
2090 nir_intrinsic_instr *instr)
2091 {
2092 LLVMValueRef indir_index, vtx_offset;
2093 unsigned const_index;
2094 LLVMValueRef args[9];
2095 unsigned param, vtx_offset_param;
2096 LLVMValueRef value[4], result;
2097 unsigned vertex_index;
2098 unsigned cull_offset = 0;
2099 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2100 false, &vertex_index,
2101 &const_index, &indir_index);
2102 vtx_offset_param = vertex_index;
2103 assert(vtx_offset_param < 6);
2104 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2105 LLVMConstInt(ctx->i32, 4, false), "");
2106
2107 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2108 if (instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2109 cull_offset += ctx->num_input_clips;
2110 for (unsigned i = 0; i < instr->num_components; i++) {
2111
2112 args[0] = ctx->esgs_ring;
2113 args[1] = vtx_offset;
2114 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index + cull_offset) * 256, false);
2115 args[3] = ctx->i32zero;
2116 args[4] = ctx->i32one; /* OFFEN */
2117 args[5] = ctx->i32zero; /* IDXEN */
2118 args[6] = ctx->i32one; /* GLC */
2119 args[7] = ctx->i32zero; /* SLC */
2120 args[8] = ctx->i32zero; /* TFE */
2121
2122 value[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2123 ctx->i32, args, 9, AC_FUNC_ATTR_READONLY);
2124 }
2125 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2126
2127 return result;
2128 }
2129
2130 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2131 nir_intrinsic_instr *instr)
2132 {
2133 LLVMValueRef values[8];
2134 int idx = instr->variables[0]->var->data.driver_location;
2135 int ve = instr->dest.ssa.num_components;
2136 LLVMValueRef indir_index;
2137 LLVMValueRef ret;
2138 unsigned const_index;
2139 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2140 instr->variables[0]->var->data.mode == nir_var_shader_in;
2141 radv_get_deref_offset(ctx, &instr->variables[0]->deref, vs_in, NULL,
2142 &const_index, &indir_index);
2143
2144 if (instr->dest.ssa.bit_size == 64)
2145 ve *= 2;
2146
2147 switch (instr->variables[0]->var->data.mode) {
2148 case nir_var_shader_in:
2149 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2150 return load_gs_input(ctx, instr);
2151 }
2152 for (unsigned chan = 0; chan < ve; chan++) {
2153 if (indir_index) {
2154 unsigned count = glsl_count_attribute_slots(
2155 instr->variables[0]->var->type,
2156 ctx->stage == MESA_SHADER_VERTEX);
2157 count -= chan / 4;
2158 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2159 &ctx->ac, ctx->inputs + idx + chan, count,
2160 4, false);
2161
2162 values[chan] = LLVMBuildExtractElement(ctx->builder,
2163 tmp_vec,
2164 indir_index, "");
2165 } else
2166 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2167 }
2168 break;
2169 case nir_var_local:
2170 for (unsigned chan = 0; chan < ve; chan++) {
2171 if (indir_index) {
2172 unsigned count = glsl_count_attribute_slots(
2173 instr->variables[0]->var->type, false);
2174 count -= chan / 4;
2175 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2176 &ctx->ac, ctx->locals + idx + chan, count,
2177 4, true);
2178
2179 values[chan] = LLVMBuildExtractElement(ctx->builder,
2180 tmp_vec,
2181 indir_index, "");
2182 } else {
2183 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2184 }
2185 }
2186 break;
2187 case nir_var_shader_out:
2188 for (unsigned chan = 0; chan < ve; chan++) {
2189 if (indir_index) {
2190 unsigned count = glsl_count_attribute_slots(
2191 instr->variables[0]->var->type, false);
2192 count -= chan / 4;
2193 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2194 &ctx->ac, ctx->outputs + idx + chan, count,
2195 4, true);
2196
2197 values[chan] = LLVMBuildExtractElement(ctx->builder,
2198 tmp_vec,
2199 indir_index, "");
2200 } else {
2201 values[chan] = LLVMBuildLoad(ctx->builder,
2202 ctx->outputs[idx + chan + const_index * 4],
2203 "");
2204 }
2205 }
2206 break;
2207 case nir_var_shared: {
2208 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2209 LLVMValueRef derived_ptr;
2210
2211 if (indir_index)
2212 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2213
2214 for (unsigned chan = 0; chan < ve; chan++) {
2215 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2216 if (indir_index)
2217 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2218 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2219
2220 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2221 }
2222 break;
2223 }
2224 default:
2225 unreachable("unhandle variable mode");
2226 }
2227 ret = ac_build_gather_values(&ctx->ac, values, ve);
2228 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2229 }
2230
2231 static void
2232 visit_store_var(struct nir_to_llvm_context *ctx,
2233 nir_intrinsic_instr *instr)
2234 {
2235 LLVMValueRef temp_ptr, value;
2236 int idx = instr->variables[0]->var->data.driver_location;
2237 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2238 int writemask = instr->const_index[0];
2239 LLVMValueRef indir_index;
2240 unsigned const_index;
2241 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2242 NULL, &const_index, &indir_index);
2243
2244 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2245 int old_writemask = writemask;
2246
2247 src = LLVMBuildBitCast(ctx->builder, src,
2248 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2249 "");
2250
2251 writemask = 0;
2252 for (unsigned chan = 0; chan < 4; chan++) {
2253 if (old_writemask & (1 << chan))
2254 writemask |= 3u << (2 * chan);
2255 }
2256 }
2257
2258 switch (instr->variables[0]->var->data.mode) {
2259 case nir_var_shader_out:
2260 for (unsigned chan = 0; chan < 8; chan++) {
2261 int stride = 4;
2262 if (!(writemask & (1 << chan)))
2263 continue;
2264
2265 value = llvm_extract_elem(ctx, src, chan);
2266
2267 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2268 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2269 stride = 1;
2270 if (indir_index) {
2271 unsigned count = glsl_count_attribute_slots(
2272 instr->variables[0]->var->type, false);
2273 count -= chan / 4;
2274 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2275 &ctx->ac, ctx->outputs + idx + chan, count,
2276 stride, true);
2277
2278 if (get_llvm_num_components(tmp_vec) > 1) {
2279 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2280 value, indir_index, "");
2281 } else
2282 tmp_vec = value;
2283 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2284 count, stride, tmp_vec);
2285
2286 } else {
2287 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2288
2289 LLVMBuildStore(ctx->builder, value, temp_ptr);
2290 }
2291 }
2292 break;
2293 case nir_var_local:
2294 for (unsigned chan = 0; chan < 8; chan++) {
2295 if (!(writemask & (1 << chan)))
2296 continue;
2297
2298 value = llvm_extract_elem(ctx, src, chan);
2299 if (indir_index) {
2300 unsigned count = glsl_count_attribute_slots(
2301 instr->variables[0]->var->type, false);
2302 count -= chan / 4;
2303 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2304 &ctx->ac, ctx->locals + idx + chan, count,
2305 4, true);
2306
2307 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2308 value, indir_index, "");
2309 build_store_values_extended(ctx, ctx->locals + idx + chan,
2310 count, 4, tmp_vec);
2311 } else {
2312 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2313
2314 LLVMBuildStore(ctx->builder, value, temp_ptr);
2315 }
2316 }
2317 break;
2318 case nir_var_shared: {
2319 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2320
2321 if (indir_index)
2322 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2323
2324 for (unsigned chan = 0; chan < 8; chan++) {
2325 if (!(writemask & (1 << chan)))
2326 continue;
2327 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2328 LLVMValueRef derived_ptr;
2329
2330 if (indir_index)
2331 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2332
2333 value = llvm_extract_elem(ctx, src, chan);
2334 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2335 LLVMBuildStore(ctx->builder,
2336 to_integer(ctx, value), derived_ptr);
2337 }
2338 break;
2339 }
2340 default:
2341 break;
2342 }
2343 }
2344
2345 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2346 {
2347 switch (dim) {
2348 case GLSL_SAMPLER_DIM_BUF:
2349 return 1;
2350 case GLSL_SAMPLER_DIM_1D:
2351 return array ? 2 : 1;
2352 case GLSL_SAMPLER_DIM_2D:
2353 return array ? 3 : 2;
2354 case GLSL_SAMPLER_DIM_MS:
2355 return array ? 4 : 3;
2356 case GLSL_SAMPLER_DIM_3D:
2357 case GLSL_SAMPLER_DIM_CUBE:
2358 return 3;
2359 case GLSL_SAMPLER_DIM_RECT:
2360 case GLSL_SAMPLER_DIM_SUBPASS:
2361 return 2;
2362 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2363 return 3;
2364 default:
2365 break;
2366 }
2367 return 0;
2368 }
2369
2370
2371 static void build_type_name_for_intr(
2372 LLVMTypeRef type,
2373 char *buf, unsigned bufsize)
2374 {
2375 LLVMTypeRef elem_type = type;
2376
2377 assert(bufsize >= 8);
2378
2379 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
2380 int ret = snprintf(buf, bufsize, "v%u",
2381 LLVMGetVectorSize(type));
2382 if (ret < 0) {
2383 char *type_name = LLVMPrintTypeToString(type);
2384 fprintf(stderr, "Error building type name for: %s\n",
2385 type_name);
2386 return;
2387 }
2388 elem_type = LLVMGetElementType(type);
2389 buf += ret;
2390 bufsize -= ret;
2391 }
2392 switch (LLVMGetTypeKind(elem_type)) {
2393 default: break;
2394 case LLVMIntegerTypeKind:
2395 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
2396 break;
2397 case LLVMFloatTypeKind:
2398 snprintf(buf, bufsize, "f32");
2399 break;
2400 case LLVMDoubleTypeKind:
2401 snprintf(buf, bufsize, "f64");
2402 break;
2403 }
2404 }
2405
2406 static void get_image_intr_name(const char *base_name,
2407 LLVMTypeRef data_type,
2408 LLVMTypeRef coords_type,
2409 LLVMTypeRef rsrc_type,
2410 char *out_name, unsigned out_len)
2411 {
2412 char coords_type_name[8];
2413
2414 build_type_name_for_intr(coords_type, coords_type_name,
2415 sizeof(coords_type_name));
2416
2417 if (HAVE_LLVM <= 0x0309) {
2418 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
2419 } else {
2420 char data_type_name[8];
2421 char rsrc_type_name[8];
2422
2423 build_type_name_for_intr(data_type, data_type_name,
2424 sizeof(data_type_name));
2425 build_type_name_for_intr(rsrc_type, rsrc_type_name,
2426 sizeof(rsrc_type_name));
2427 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
2428 data_type_name, coords_type_name, rsrc_type_name);
2429 }
2430 }
2431
2432 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2433 nir_intrinsic_instr *instr)
2434 {
2435 const struct glsl_type *type = instr->variables[0]->var->type;
2436 if(instr->variables[0]->deref.child)
2437 type = instr->variables[0]->deref.child->type;
2438
2439 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2440 LLVMValueRef coords[4];
2441 LLVMValueRef masks[] = {
2442 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2443 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2444 };
2445 LLVMValueRef res;
2446 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2447
2448 int count;
2449 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2450 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2451 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2452 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2453 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2454
2455 count = image_type_to_components_count(dim,
2456 glsl_sampler_type_is_array(type));
2457
2458 if (is_ms) {
2459 LLVMValueRef fmask_load_address[4];
2460 LLVMValueRef params[7];
2461 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2462 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2463 LLVMValueRef da = ctx->i32zero;
2464 char intrinsic_name[64];
2465 int chan;
2466 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2467 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
2468 fmask_load_address[2] = LLVMGetUndef(ctx->i32);
2469 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
2470 if (add_frag_pos) {
2471 for (chan = 0; chan < 2; ++chan)
2472 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2473 }
2474 params[0] = ac_build_gather_values(&ctx->ac, fmask_load_address, 4);
2475 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_FMASK);
2476 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2477 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2478 params[3] = glc;
2479 params[4] = slc;
2480 params[5] = lwe;
2481 params[6] = da;
2482
2483 get_image_intr_name("llvm.amdgcn.image.load",
2484 ctx->v4f32, /* vdata */
2485 LLVMTypeOf(params[0]), /* coords */
2486 LLVMTypeOf(params[1]), /* rsrc */
2487 intrinsic_name, sizeof(intrinsic_name));
2488
2489 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2490 params, 7, AC_FUNC_ATTR_READONLY);
2491
2492 res = to_integer(ctx, res);
2493 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
2494 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
2495
2496 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
2497 res,
2498 ctx->i32zero, "");
2499
2500 LLVMValueRef sample_index4 =
2501 LLVMBuildMul(ctx->builder, sample_index, four, "");
2502 LLVMValueRef shifted_fmask =
2503 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
2504 LLVMValueRef final_sample =
2505 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
2506
2507 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2508 * resource descriptor is 0 (invalid),
2509 */
2510 LLVMValueRef fmask_desc =
2511 LLVMBuildBitCast(ctx->builder, params[1],
2512 ctx->v8i32, "");
2513
2514 LLVMValueRef fmask_word1 =
2515 LLVMBuildExtractElement(ctx->builder, fmask_desc,
2516 ctx->i32one, "");
2517
2518 LLVMValueRef word1_is_nonzero =
2519 LLVMBuildICmp(ctx->builder, LLVMIntNE,
2520 fmask_word1, ctx->i32zero, "");
2521
2522 /* Replace the MSAA sample index. */
2523 sample_index =
2524 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
2525 final_sample, sample_index, "");
2526 }
2527 if (count == 1) {
2528 if (instr->src[0].ssa->num_components)
2529 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2530 else
2531 res = src0;
2532 } else {
2533 int chan;
2534 if (is_ms)
2535 count--;
2536 for (chan = 0; chan < count; ++chan) {
2537 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2538 }
2539
2540 if (add_frag_pos) {
2541 for (chan = 0; chan < count; ++chan)
2542 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2543 }
2544 if (is_ms) {
2545 coords[count] = sample_index;
2546 count++;
2547 }
2548
2549 if (count == 3) {
2550 coords[3] = LLVMGetUndef(ctx->i32);
2551 count = 4;
2552 }
2553 res = ac_build_gather_values(&ctx->ac, coords, count);
2554 }
2555 return res;
2556 }
2557
2558 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2559 nir_intrinsic_instr *instr)
2560 {
2561 LLVMValueRef params[7];
2562 LLVMValueRef res;
2563 char intrinsic_name[64];
2564 const nir_variable *var = instr->variables[0]->var;
2565 const struct glsl_type *type = var->type;
2566 if(instr->variables[0]->deref.child)
2567 type = instr->variables[0]->deref.child->type;
2568
2569 type = glsl_without_array(type);
2570 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2571 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2572 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2573 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2574 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2575 params[3] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2576 params[4] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2577 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2578 params, 5, 0);
2579
2580 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2581 res = to_integer(ctx, res);
2582 } else {
2583 bool is_da = glsl_sampler_type_is_array(type) ||
2584 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2585 LLVMValueRef da = is_da ? ctx->i32one : ctx->i32zero;
2586 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2587 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2588
2589 params[0] = get_image_coords(ctx, instr);
2590 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2591 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2592 if (HAVE_LLVM <= 0x0309) {
2593 params[3] = LLVMConstInt(ctx->i1, 0, false); /* r128 */
2594 params[4] = da;
2595 params[5] = glc;
2596 params[6] = slc;
2597 } else {
2598 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2599 params[3] = glc;
2600 params[4] = slc;
2601 params[5] = lwe;
2602 params[6] = da;
2603 }
2604
2605 get_image_intr_name("llvm.amdgcn.image.load",
2606 ctx->v4f32, /* vdata */
2607 LLVMTypeOf(params[0]), /* coords */
2608 LLVMTypeOf(params[1]), /* rsrc */
2609 intrinsic_name, sizeof(intrinsic_name));
2610
2611 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2612 params, 7, AC_FUNC_ATTR_READONLY);
2613 }
2614 return to_integer(ctx, res);
2615 }
2616
2617 static void visit_image_store(struct nir_to_llvm_context *ctx,
2618 nir_intrinsic_instr *instr)
2619 {
2620 LLVMValueRef params[8];
2621 char intrinsic_name[64];
2622 const nir_variable *var = instr->variables[0]->var;
2623 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2624 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2625 const struct glsl_type *type = glsl_without_array(var->type);
2626
2627 if (ctx->stage == MESA_SHADER_FRAGMENT)
2628 ctx->shader_info->fs.writes_memory = true;
2629
2630 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2631 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2632 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2633 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2634 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2635 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2636 params[4] = i1false; /* glc */
2637 params[5] = i1false; /* slc */
2638 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2639 params, 6, 0);
2640 } else {
2641 bool is_da = glsl_sampler_type_is_array(type) ||
2642 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2643 LLVMValueRef da = is_da ? i1true : i1false;
2644 LLVMValueRef glc = i1false;
2645 LLVMValueRef slc = i1false;
2646
2647 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2648 params[1] = get_image_coords(ctx, instr); /* coords */
2649 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2650 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2651 if (HAVE_LLVM <= 0x0309) {
2652 params[4] = i1false; /* r128 */
2653 params[5] = da;
2654 params[6] = glc;
2655 params[7] = slc;
2656 } else {
2657 LLVMValueRef lwe = i1false;
2658 params[4] = glc;
2659 params[5] = slc;
2660 params[6] = lwe;
2661 params[7] = da;
2662 }
2663
2664 get_image_intr_name("llvm.amdgcn.image.store",
2665 LLVMTypeOf(params[0]), /* vdata */
2666 LLVMTypeOf(params[1]), /* coords */
2667 LLVMTypeOf(params[2]), /* rsrc */
2668 intrinsic_name, sizeof(intrinsic_name));
2669
2670 ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2671 params, 8, 0);
2672 }
2673
2674 }
2675
2676 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2677 nir_intrinsic_instr *instr)
2678 {
2679 LLVMValueRef params[6];
2680 int param_count = 0;
2681 const nir_variable *var = instr->variables[0]->var;
2682 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2683 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2684 const char *base_name = "llvm.amdgcn.image.atomic";
2685 const char *atomic_name;
2686 LLVMValueRef coords;
2687 char intrinsic_name[32], coords_type[8];
2688 const struct glsl_type *type = glsl_without_array(var->type);
2689
2690 if (ctx->stage == MESA_SHADER_FRAGMENT)
2691 ctx->shader_info->fs.writes_memory = true;
2692
2693 params[param_count++] = get_src(ctx, instr->src[2]);
2694 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2695 params[param_count++] = get_src(ctx, instr->src[3]);
2696
2697 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2698 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2699 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2700 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2701 params[param_count++] = ctx->i32zero; /* voffset */
2702 params[param_count++] = i1false; /* glc */
2703 params[param_count++] = i1false; /* slc */
2704 } else {
2705 bool da = glsl_sampler_type_is_array(type) ||
2706 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2707
2708 coords = params[param_count++] = get_image_coords(ctx, instr);
2709 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2710 params[param_count++] = i1false; /* r128 */
2711 params[param_count++] = da ? i1true : i1false; /* da */
2712 params[param_count++] = i1false; /* slc */
2713 }
2714
2715 switch (instr->intrinsic) {
2716 case nir_intrinsic_image_atomic_add:
2717 atomic_name = "add";
2718 break;
2719 case nir_intrinsic_image_atomic_min:
2720 atomic_name = "smin";
2721 break;
2722 case nir_intrinsic_image_atomic_max:
2723 atomic_name = "smax";
2724 break;
2725 case nir_intrinsic_image_atomic_and:
2726 atomic_name = "and";
2727 break;
2728 case nir_intrinsic_image_atomic_or:
2729 atomic_name = "or";
2730 break;
2731 case nir_intrinsic_image_atomic_xor:
2732 atomic_name = "xor";
2733 break;
2734 case nir_intrinsic_image_atomic_exchange:
2735 atomic_name = "swap";
2736 break;
2737 case nir_intrinsic_image_atomic_comp_swap:
2738 atomic_name = "cmpswap";
2739 break;
2740 default:
2741 abort();
2742 }
2743 build_int_type_name(LLVMTypeOf(coords),
2744 coords_type, sizeof(coords_type));
2745
2746 snprintf(intrinsic_name, sizeof(intrinsic_name),
2747 "%s.%s.%s", base_name, atomic_name, coords_type);
2748 return ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2749 }
2750
2751 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2752 nir_intrinsic_instr *instr)
2753 {
2754 LLVMValueRef res;
2755 LLVMValueRef params[10];
2756 const nir_variable *var = instr->variables[0]->var;
2757 const struct glsl_type *type = instr->variables[0]->var->type;
2758 bool da = glsl_sampler_type_is_array(var->type) ||
2759 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2760 if(instr->variables[0]->deref.child)
2761 type = instr->variables[0]->deref.child->type;
2762
2763 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2764 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2765 params[0] = ctx->i32zero;
2766 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2767 params[2] = LLVMConstInt(ctx->i32, 15, false);
2768 params[3] = ctx->i32zero;
2769 params[4] = ctx->i32zero;
2770 params[5] = da ? ctx->i32one : ctx->i32zero;
2771 params[6] = ctx->i32zero;
2772 params[7] = ctx->i32zero;
2773 params[8] = ctx->i32zero;
2774 params[9] = ctx->i32zero;
2775
2776 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
2777 params, 10, AC_FUNC_ATTR_READNONE);
2778
2779 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2780 glsl_sampler_type_is_array(type)) {
2781 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2782 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2783 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2784 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2785 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2786 }
2787 return res;
2788 }
2789
2790 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2791 {
2792 LLVMValueRef args[1] = {
2793 LLVMConstInt(ctx->i32, 0xf70, false),
2794 };
2795 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2796 ctx->voidt, args, 1, 0);
2797 }
2798
2799 static void emit_barrier(struct nir_to_llvm_context *ctx)
2800 {
2801 // TODO tess
2802 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2803 ctx->voidt, NULL, 0, 0);
2804 }
2805
2806 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2807 nir_intrinsic_instr *instr)
2808 {
2809 LLVMValueRef cond;
2810 ctx->shader_info->fs.can_discard = true;
2811
2812 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2813 get_src(ctx, instr->src[0]),
2814 ctx->i32zero, "");
2815
2816 cond = LLVMBuildSelect(ctx->builder, cond,
2817 LLVMConstReal(ctx->f32, -1.0f),
2818 ctx->f32zero, "");
2819 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
2820 ctx->voidt,
2821 &cond, 1, 0);
2822 }
2823
2824 static LLVMValueRef
2825 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2826 {
2827 LLVMValueRef result;
2828 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
2829 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2830 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2831
2832 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2833 }
2834
2835 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2836 nir_intrinsic_instr *instr)
2837 {
2838 LLVMValueRef ptr, result;
2839 int idx = instr->variables[0]->var->data.driver_location;
2840 LLVMValueRef src = get_src(ctx, instr->src[0]);
2841 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2842
2843 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2844 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2845 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2846 ptr, src, src1,
2847 LLVMAtomicOrderingSequentiallyConsistent,
2848 LLVMAtomicOrderingSequentiallyConsistent,
2849 false);
2850 } else {
2851 LLVMAtomicRMWBinOp op;
2852 switch (instr->intrinsic) {
2853 case nir_intrinsic_var_atomic_add:
2854 op = LLVMAtomicRMWBinOpAdd;
2855 break;
2856 case nir_intrinsic_var_atomic_umin:
2857 op = LLVMAtomicRMWBinOpUMin;
2858 break;
2859 case nir_intrinsic_var_atomic_umax:
2860 op = LLVMAtomicRMWBinOpUMax;
2861 break;
2862 case nir_intrinsic_var_atomic_imin:
2863 op = LLVMAtomicRMWBinOpMin;
2864 break;
2865 case nir_intrinsic_var_atomic_imax:
2866 op = LLVMAtomicRMWBinOpMax;
2867 break;
2868 case nir_intrinsic_var_atomic_and:
2869 op = LLVMAtomicRMWBinOpAnd;
2870 break;
2871 case nir_intrinsic_var_atomic_or:
2872 op = LLVMAtomicRMWBinOpOr;
2873 break;
2874 case nir_intrinsic_var_atomic_xor:
2875 op = LLVMAtomicRMWBinOpXor;
2876 break;
2877 case nir_intrinsic_var_atomic_exchange:
2878 op = LLVMAtomicRMWBinOpXchg;
2879 break;
2880 default:
2881 return NULL;
2882 }
2883
2884 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2885 LLVMAtomicOrderingSequentiallyConsistent,
2886 false);
2887 }
2888 return result;
2889 }
2890
2891 #define INTERP_CENTER 0
2892 #define INTERP_CENTROID 1
2893 #define INTERP_SAMPLE 2
2894
2895 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2896 enum glsl_interp_mode interp, unsigned location)
2897 {
2898 switch (interp) {
2899 case INTERP_MODE_FLAT:
2900 default:
2901 return NULL;
2902 case INTERP_MODE_SMOOTH:
2903 case INTERP_MODE_NONE:
2904 if (location == INTERP_CENTER)
2905 return ctx->persp_center;
2906 else if (location == INTERP_CENTROID)
2907 return ctx->persp_centroid;
2908 else if (location == INTERP_SAMPLE)
2909 return ctx->persp_sample;
2910 break;
2911 case INTERP_MODE_NOPERSPECTIVE:
2912 if (location == INTERP_CENTER)
2913 return ctx->linear_center;
2914 else if (location == INTERP_CENTROID)
2915 return ctx->linear_centroid;
2916 else if (location == INTERP_SAMPLE)
2917 return ctx->linear_sample;
2918 break;
2919 }
2920 return NULL;
2921 }
2922
2923 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
2924 LLVMValueRef sample_id)
2925 {
2926 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2927 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
2928 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
2929 LLVMValueRef result[2];
2930
2931 result[0] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset0);
2932 result[1] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset1);
2933
2934 return ac_build_gather_values(&ctx->ac, result, 2);
2935 }
2936
2937 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
2938 {
2939 LLVMValueRef values[2];
2940
2941 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
2942 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
2943 return ac_build_gather_values(&ctx->ac, values, 2);
2944 }
2945
2946 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
2947 nir_intrinsic_instr *instr)
2948 {
2949 LLVMValueRef result[2];
2950 LLVMValueRef interp_param, attr_number;
2951 unsigned location;
2952 unsigned chan;
2953 LLVMValueRef src_c0, src_c1;
2954 LLVMValueRef src0;
2955 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
2956 switch (instr->intrinsic) {
2957 case nir_intrinsic_interp_var_at_centroid:
2958 location = INTERP_CENTROID;
2959 break;
2960 case nir_intrinsic_interp_var_at_sample:
2961 location = INTERP_SAMPLE;
2962 src0 = get_src(ctx, instr->src[0]);
2963 break;
2964 case nir_intrinsic_interp_var_at_offset:
2965 location = INTERP_CENTER;
2966 src0 = get_src(ctx, instr->src[0]);
2967 default:
2968 break;
2969 }
2970
2971 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
2972 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
2973 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
2974 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
2975 LLVMValueRef sample_position;
2976 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
2977
2978 /* fetch sample ID */
2979 sample_position = load_sample_position(ctx, src0);
2980
2981 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
2982 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
2983 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
2984 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
2985 }
2986 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
2987 attr_number = LLVMConstInt(ctx->i32, input_index, false);
2988
2989 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
2990 LLVMValueRef ij_out[2];
2991 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
2992
2993 /*
2994 * take the I then J parameters, and the DDX/Y for it, and
2995 * calculate the IJ inputs for the interpolator.
2996 * temp1 = ddx * offset/sample.x + I;
2997 * interp_param.I = ddy * offset/sample.y + temp1;
2998 * temp1 = ddx * offset/sample.x + J;
2999 * interp_param.J = ddy * offset/sample.y + temp1;
3000 */
3001 for (unsigned i = 0; i < 2; i++) {
3002 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3003 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3004 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3005 ddxy_out, ix_ll, "");
3006 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3007 ddxy_out, iy_ll, "");
3008 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3009 interp_param, ix_ll, "");
3010 LLVMValueRef temp1, temp2;
3011
3012 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3013 ctx->f32, "");
3014
3015 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3016 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3017
3018 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3019 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3020
3021 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3022 temp2, ctx->i32, "");
3023 }
3024 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3025
3026 }
3027
3028 for (chan = 0; chan < 2; chan++) {
3029 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3030
3031 if (interp_param) {
3032 interp_param = LLVMBuildBitCast(ctx->builder,
3033 interp_param, LLVMVectorType(ctx->f32, 2), "");
3034 LLVMValueRef i = LLVMBuildExtractElement(
3035 ctx->builder, interp_param, ctx->i32zero, "");
3036 LLVMValueRef j = LLVMBuildExtractElement(
3037 ctx->builder, interp_param, ctx->i32one, "");
3038
3039 result[chan] = ac_build_fs_interp(&ctx->ac,
3040 llvm_chan, attr_number,
3041 ctx->prim_mask, i, j);
3042 } else {
3043 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3044 LLVMConstInt(ctx->i32, 2, false),
3045 llvm_chan, attr_number,
3046 ctx->prim_mask);
3047 }
3048 }
3049 return ac_build_gather_values(&ctx->ac, result, 2);
3050 }
3051
3052 static void
3053 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3054 nir_intrinsic_instr *instr)
3055 {
3056 LLVMValueRef gs_next_vertex;
3057 LLVMValueRef can_emit, kill;
3058 int idx;
3059 int clip_cull_slot = -1;
3060 assert(instr->const_index[0] == 0);
3061 /* Write vertex attribute values to GSVS ring */
3062 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3063 ctx->gs_next_vertex,
3064 "");
3065
3066 /* If this thread has already emitted the declared maximum number of
3067 * vertices, kill it: excessive vertex emissions are not supposed to
3068 * have any effect, and GS threads have no externally observable
3069 * effects other than emitting vertices.
3070 */
3071 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3072 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3073
3074 kill = LLVMBuildSelect(ctx->builder, can_emit,
3075 LLVMConstReal(ctx->f32, 1.0f),
3076 LLVMConstReal(ctx->f32, -1.0f), "");
3077 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
3078 ctx->voidt, &kill, 1, 0);
3079
3080 /* loop num outputs */
3081 idx = 0;
3082 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3083 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3084 int length = 4;
3085 int start = 0;
3086 int slot = idx;
3087 int slot_inc = 1;
3088
3089 if (!(ctx->output_mask & (1ull << i)))
3090 continue;
3091
3092 if (i == VARYING_SLOT_CLIP_DIST1 ||
3093 i == VARYING_SLOT_CULL_DIST1)
3094 continue;
3095
3096 if (i == VARYING_SLOT_CLIP_DIST0 ||
3097 i == VARYING_SLOT_CULL_DIST0) {
3098 /* pack clip and cull into a single set of slots */
3099 if (clip_cull_slot == -1) {
3100 clip_cull_slot = idx;
3101 if (ctx->num_output_clips + ctx->num_output_culls > 4)
3102 slot_inc = 2;
3103 } else {
3104 slot = clip_cull_slot;
3105 slot_inc = 0;
3106 }
3107 if (i == VARYING_SLOT_CLIP_DIST0)
3108 length = ctx->num_output_clips;
3109 if (i == VARYING_SLOT_CULL_DIST0) {
3110 start = ctx->num_output_clips;
3111 length = ctx->num_output_culls;
3112 }
3113 }
3114 for (unsigned j = 0; j < length; j++) {
3115 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3116 out_ptr[j], "");
3117 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j + start) * ctx->gs_max_out_vertices, false);
3118 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3119 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3120
3121 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3122
3123 ac_build_tbuffer_store(&ctx->ac, ctx->gsvs_ring,
3124 out_val, 1,
3125 voffset, ctx->gs2vs_offset, 0,
3126 V_008F0C_BUF_DATA_FORMAT_32,
3127 V_008F0C_BUF_NUM_FORMAT_UINT,
3128 1, 0, 1, 1, 0);
3129 }
3130 idx += slot_inc;
3131 }
3132
3133 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3134 ctx->i32one, "");
3135 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3136
3137 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3138 }
3139
3140 static void
3141 visit_end_primitive(struct nir_to_llvm_context *ctx,
3142 nir_intrinsic_instr *instr)
3143 {
3144 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3145 }
3146
3147 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3148 nir_intrinsic_instr *instr)
3149 {
3150 LLVMValueRef result = NULL;
3151
3152 switch (instr->intrinsic) {
3153 case nir_intrinsic_load_work_group_id: {
3154 result = ctx->workgroup_ids;
3155 break;
3156 }
3157 case nir_intrinsic_load_base_vertex: {
3158 result = ctx->base_vertex;
3159 break;
3160 }
3161 case nir_intrinsic_load_vertex_id_zero_base: {
3162 result = ctx->vertex_id;
3163 break;
3164 }
3165 case nir_intrinsic_load_local_invocation_id: {
3166 result = ctx->local_invocation_ids;
3167 break;
3168 }
3169 case nir_intrinsic_load_base_instance:
3170 result = ctx->start_instance;
3171 break;
3172 case nir_intrinsic_load_draw_id:
3173 result = ctx->draw_index;
3174 break;
3175 case nir_intrinsic_load_invocation_id:
3176 result = ctx->gs_invocation_id;
3177 break;
3178 case nir_intrinsic_load_primitive_id:
3179 if (ctx->stage == MESA_SHADER_GEOMETRY)
3180 result = ctx->gs_prim_id;
3181 else
3182 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3183 break;
3184 case nir_intrinsic_load_sample_id:
3185 ctx->shader_info->fs.force_persample = true;
3186 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3187 break;
3188 case nir_intrinsic_load_sample_pos:
3189 ctx->shader_info->fs.force_persample = true;
3190 result = load_sample_pos(ctx);
3191 break;
3192 case nir_intrinsic_load_sample_mask_in:
3193 result = ctx->sample_coverage;
3194 break;
3195 case nir_intrinsic_load_front_face:
3196 result = ctx->front_face;
3197 break;
3198 case nir_intrinsic_load_instance_id:
3199 result = ctx->instance_id;
3200 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3201 ctx->shader_info->vs.vgpr_comp_cnt);
3202 break;
3203 case nir_intrinsic_load_num_work_groups:
3204 result = ctx->num_work_groups;
3205 break;
3206 case nir_intrinsic_load_local_invocation_index:
3207 result = visit_load_local_invocation_index(ctx);
3208 break;
3209 case nir_intrinsic_load_push_constant:
3210 result = visit_load_push_constant(ctx, instr);
3211 break;
3212 case nir_intrinsic_vulkan_resource_index:
3213 result = visit_vulkan_resource_index(ctx, instr);
3214 break;
3215 case nir_intrinsic_store_ssbo:
3216 visit_store_ssbo(ctx, instr);
3217 break;
3218 case nir_intrinsic_load_ssbo:
3219 result = visit_load_buffer(ctx, instr);
3220 break;
3221 case nir_intrinsic_ssbo_atomic_add:
3222 case nir_intrinsic_ssbo_atomic_imin:
3223 case nir_intrinsic_ssbo_atomic_umin:
3224 case nir_intrinsic_ssbo_atomic_imax:
3225 case nir_intrinsic_ssbo_atomic_umax:
3226 case nir_intrinsic_ssbo_atomic_and:
3227 case nir_intrinsic_ssbo_atomic_or:
3228 case nir_intrinsic_ssbo_atomic_xor:
3229 case nir_intrinsic_ssbo_atomic_exchange:
3230 case nir_intrinsic_ssbo_atomic_comp_swap:
3231 result = visit_atomic_ssbo(ctx, instr);
3232 break;
3233 case nir_intrinsic_load_ubo:
3234 result = visit_load_ubo_buffer(ctx, instr);
3235 break;
3236 case nir_intrinsic_get_buffer_size:
3237 result = visit_get_buffer_size(ctx, instr);
3238 break;
3239 case nir_intrinsic_load_var:
3240 result = visit_load_var(ctx, instr);
3241 break;
3242 case nir_intrinsic_store_var:
3243 visit_store_var(ctx, instr);
3244 break;
3245 case nir_intrinsic_image_load:
3246 result = visit_image_load(ctx, instr);
3247 break;
3248 case nir_intrinsic_image_store:
3249 visit_image_store(ctx, instr);
3250 break;
3251 case nir_intrinsic_image_atomic_add:
3252 case nir_intrinsic_image_atomic_min:
3253 case nir_intrinsic_image_atomic_max:
3254 case nir_intrinsic_image_atomic_and:
3255 case nir_intrinsic_image_atomic_or:
3256 case nir_intrinsic_image_atomic_xor:
3257 case nir_intrinsic_image_atomic_exchange:
3258 case nir_intrinsic_image_atomic_comp_swap:
3259 result = visit_image_atomic(ctx, instr);
3260 break;
3261 case nir_intrinsic_image_size:
3262 result = visit_image_size(ctx, instr);
3263 break;
3264 case nir_intrinsic_discard:
3265 ctx->shader_info->fs.can_discard = true;
3266 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3267 ctx->voidt,
3268 NULL, 0, 0);
3269 break;
3270 case nir_intrinsic_discard_if:
3271 emit_discard_if(ctx, instr);
3272 break;
3273 case nir_intrinsic_memory_barrier:
3274 emit_waitcnt(ctx);
3275 break;
3276 case nir_intrinsic_barrier:
3277 emit_barrier(ctx);
3278 break;
3279 case nir_intrinsic_var_atomic_add:
3280 case nir_intrinsic_var_atomic_imin:
3281 case nir_intrinsic_var_atomic_umin:
3282 case nir_intrinsic_var_atomic_imax:
3283 case nir_intrinsic_var_atomic_umax:
3284 case nir_intrinsic_var_atomic_and:
3285 case nir_intrinsic_var_atomic_or:
3286 case nir_intrinsic_var_atomic_xor:
3287 case nir_intrinsic_var_atomic_exchange:
3288 case nir_intrinsic_var_atomic_comp_swap:
3289 result = visit_var_atomic(ctx, instr);
3290 break;
3291 case nir_intrinsic_interp_var_at_centroid:
3292 case nir_intrinsic_interp_var_at_sample:
3293 case nir_intrinsic_interp_var_at_offset:
3294 result = visit_interp(ctx, instr);
3295 break;
3296 case nir_intrinsic_emit_vertex:
3297 visit_emit_vertex(ctx, instr);
3298 break;
3299 case nir_intrinsic_end_primitive:
3300 visit_end_primitive(ctx, instr);
3301 break;
3302 default:
3303 fprintf(stderr, "Unknown intrinsic: ");
3304 nir_print_instr(&instr->instr, stderr);
3305 fprintf(stderr, "\n");
3306 break;
3307 }
3308 if (result) {
3309 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3310 }
3311 }
3312
3313 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3314 nir_deref_var *deref,
3315 enum desc_type desc_type)
3316 {
3317 unsigned desc_set = deref->var->data.descriptor_set;
3318 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3319 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3320 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3321 unsigned offset = binding->offset;
3322 unsigned stride = binding->size;
3323 unsigned type_size;
3324 LLVMBuilderRef builder = ctx->builder;
3325 LLVMTypeRef type;
3326 LLVMValueRef index = NULL;
3327
3328 assert(deref->var->data.binding < layout->binding_count);
3329
3330 switch (desc_type) {
3331 case DESC_IMAGE:
3332 type = ctx->v8i32;
3333 type_size = 32;
3334 break;
3335 case DESC_FMASK:
3336 type = ctx->v8i32;
3337 offset += 32;
3338 type_size = 32;
3339 break;
3340 case DESC_SAMPLER:
3341 type = ctx->v4i32;
3342 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3343 offset += 64;
3344
3345 type_size = 16;
3346 break;
3347 case DESC_BUFFER:
3348 type = ctx->v4i32;
3349 type_size = 16;
3350 break;
3351 default:
3352 unreachable("invalid desc_type\n");
3353 }
3354
3355 if (deref->deref.child) {
3356 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3357
3358 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3359 offset += child->base_offset * stride;
3360 if (child->deref_array_type == nir_deref_array_type_indirect) {
3361 index = get_src(ctx, child->indirect);
3362 }
3363 }
3364
3365 assert(stride % type_size == 0);
3366
3367 if (!index)
3368 index = ctx->i32zero;
3369
3370 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3371
3372 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
3373 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3374
3375 return ac_build_indexed_load_const(&ctx->ac, list, index);
3376 }
3377
3378 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3379 struct ac_tex_info *tinfo,
3380 nir_tex_instr *instr,
3381 nir_texop op,
3382 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3383 LLVMValueRef *param, unsigned count,
3384 unsigned dmask)
3385 {
3386 int num_args;
3387 unsigned is_rect = 0;
3388 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3389
3390 if (op == nir_texop_lod)
3391 da = false;
3392 /* Pad to power of two vector */
3393 while (count < util_next_power_of_two(count))
3394 param[count++] = LLVMGetUndef(ctx->i32);
3395
3396 if (count > 1)
3397 tinfo->args[0] = ac_build_gather_values(&ctx->ac, param, count);
3398 else
3399 tinfo->args[0] = param[0];
3400
3401 tinfo->args[1] = res_ptr;
3402 num_args = 2;
3403
3404 if (op == nir_texop_txf ||
3405 op == nir_texop_txf_ms ||
3406 op == nir_texop_query_levels ||
3407 op == nir_texop_texture_samples ||
3408 op == nir_texop_txs)
3409 tinfo->dst_type = ctx->v4i32;
3410 else {
3411 tinfo->dst_type = ctx->v4f32;
3412 tinfo->args[num_args++] = samp_ptr;
3413 }
3414
3415 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3416 tinfo->args[0] = res_ptr;
3417 tinfo->args[1] = LLVMConstInt(ctx->i32, 0, false);
3418 tinfo->args[2] = param[0];
3419 tinfo->arg_count = 3;
3420 return;
3421 }
3422
3423 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, dmask, 0);
3424 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, is_rect, 0); /* unorm */
3425 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
3426 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
3427 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
3428 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
3429 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
3430 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
3431
3432 tinfo->arg_count = num_args;
3433 }
3434
3435 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3436 *
3437 * SI-CI:
3438 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3439 * filtering manually. The driver sets img7 to a mask clearing
3440 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3441 * s_and_b32 samp0, samp0, img7
3442 *
3443 * VI:
3444 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3445 */
3446 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3447 LLVMValueRef res, LLVMValueRef samp)
3448 {
3449 LLVMBuilderRef builder = ctx->builder;
3450 LLVMValueRef img7, samp0;
3451
3452 if (ctx->options->chip_class >= VI)
3453 return samp;
3454
3455 img7 = LLVMBuildExtractElement(builder, res,
3456 LLVMConstInt(ctx->i32, 7, 0), "");
3457 samp0 = LLVMBuildExtractElement(builder, samp,
3458 LLVMConstInt(ctx->i32, 0, 0), "");
3459 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3460 return LLVMBuildInsertElement(builder, samp, samp0,
3461 LLVMConstInt(ctx->i32, 0, 0), "");
3462 }
3463
3464 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3465 nir_tex_instr *instr,
3466 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3467 LLVMValueRef *fmask_ptr)
3468 {
3469 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3470 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3471 else
3472 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3473 if (samp_ptr) {
3474 if (instr->sampler)
3475 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3476 else
3477 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3478 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3479 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3480 }
3481 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3482 instr->op == nir_texop_samples_identical))
3483 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3484 }
3485
3486 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
3487 LLVMValueRef coord)
3488 {
3489 coord = to_float(ctx, coord);
3490 coord = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
3491 coord = to_integer(ctx, coord);
3492 return coord;
3493 }
3494
3495 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3496 {
3497 LLVMValueRef result = NULL;
3498 struct ac_tex_info tinfo = { 0 };
3499 unsigned dmask = 0xf;
3500 LLVMValueRef address[16];
3501 LLVMValueRef coords[5];
3502 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3503 LLVMValueRef bias = NULL, offsets = NULL;
3504 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3505 LLVMValueRef ddx = NULL, ddy = NULL;
3506 LLVMValueRef derivs[6];
3507 unsigned chan, count = 0;
3508 unsigned const_src = 0, num_deriv_comp = 0;
3509
3510 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3511
3512 for (unsigned i = 0; i < instr->num_srcs; i++) {
3513 switch (instr->src[i].src_type) {
3514 case nir_tex_src_coord:
3515 coord = get_src(ctx, instr->src[i].src);
3516 break;
3517 case nir_tex_src_projector:
3518 break;
3519 case nir_tex_src_comparator:
3520 comparator = get_src(ctx, instr->src[i].src);
3521 break;
3522 case nir_tex_src_offset:
3523 offsets = get_src(ctx, instr->src[i].src);
3524 const_src = i;
3525 break;
3526 case nir_tex_src_bias:
3527 bias = get_src(ctx, instr->src[i].src);
3528 break;
3529 case nir_tex_src_lod:
3530 lod = get_src(ctx, instr->src[i].src);
3531 break;
3532 case nir_tex_src_ms_index:
3533 sample_index = get_src(ctx, instr->src[i].src);
3534 break;
3535 case nir_tex_src_ms_mcs:
3536 break;
3537 case nir_tex_src_ddx:
3538 ddx = get_src(ctx, instr->src[i].src);
3539 num_deriv_comp = instr->src[i].src.ssa->num_components;
3540 break;
3541 case nir_tex_src_ddy:
3542 ddy = get_src(ctx, instr->src[i].src);
3543 break;
3544 case nir_tex_src_texture_offset:
3545 case nir_tex_src_sampler_offset:
3546 case nir_tex_src_plane:
3547 default:
3548 break;
3549 }
3550 }
3551
3552 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3553 result = get_buffer_size(ctx, res_ptr, false);
3554 goto write_result;
3555 }
3556
3557 if (instr->op == nir_texop_texture_samples) {
3558 LLVMValueRef res, samples, is_msaa;
3559 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3560 samples = LLVMBuildExtractElement(ctx->builder, res,
3561 LLVMConstInt(ctx->i32, 3, false), "");
3562 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3563 LLVMConstInt(ctx->i32, 28, false), "");
3564 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3565 LLVMConstInt(ctx->i32, 0xe, false), "");
3566 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3567 LLVMConstInt(ctx->i32, 0xe, false), "");
3568
3569 samples = LLVMBuildLShr(ctx->builder, samples,
3570 LLVMConstInt(ctx->i32, 16, false), "");
3571 samples = LLVMBuildAnd(ctx->builder, samples,
3572 LLVMConstInt(ctx->i32, 0xf, false), "");
3573 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3574 samples, "");
3575 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3576 ctx->i32one, "");
3577 result = samples;
3578 goto write_result;
3579 }
3580
3581 if (coord)
3582 for (chan = 0; chan < instr->coord_components; chan++)
3583 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3584
3585 if (offsets && instr->op != nir_texop_txf) {
3586 LLVMValueRef offset[3], pack;
3587 for (chan = 0; chan < 3; ++chan)
3588 offset[chan] = ctx->i32zero;
3589
3590 tinfo.has_offset = true;
3591 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3592 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3593 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3594 LLVMConstInt(ctx->i32, 0x3f, false), "");
3595 if (chan)
3596 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3597 LLVMConstInt(ctx->i32, chan * 8, false), "");
3598 }
3599 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3600 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3601 address[count++] = pack;
3602
3603 }
3604 /* pack LOD bias value */
3605 if (instr->op == nir_texop_txb && bias) {
3606 address[count++] = bias;
3607 }
3608
3609 /* Pack depth comparison value */
3610 if (instr->is_shadow && comparator) {
3611 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3612 }
3613
3614 /* pack derivatives */
3615 if (ddx || ddy) {
3616 switch (instr->sampler_dim) {
3617 case GLSL_SAMPLER_DIM_3D:
3618 case GLSL_SAMPLER_DIM_CUBE:
3619 num_deriv_comp = 3;
3620 break;
3621 case GLSL_SAMPLER_DIM_2D:
3622 default:
3623 num_deriv_comp = 2;
3624 break;
3625 case GLSL_SAMPLER_DIM_1D:
3626 num_deriv_comp = 1;
3627 break;
3628 }
3629
3630 for (unsigned i = 0; i < num_deriv_comp; i++) {
3631 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3632 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3633 }
3634 }
3635
3636 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3637 for (chan = 0; chan < instr->coord_components; chan++)
3638 coords[chan] = to_float(ctx, coords[chan]);
3639 if (instr->coord_components == 3)
3640 coords[3] = LLVMGetUndef(ctx->f32);
3641 ac_prepare_cube_coords(&ctx->ac,
3642 instr->op == nir_texop_txd, instr->is_array,
3643 coords, derivs);
3644 if (num_deriv_comp)
3645 num_deriv_comp--;
3646 }
3647
3648 if (ddx || ddy) {
3649 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3650 address[count++] = derivs[i];
3651 }
3652
3653 /* Pack texture coordinates */
3654 if (coord) {
3655 address[count++] = coords[0];
3656 if (instr->coord_components > 1) {
3657 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
3658 coords[1] = apply_round_slice(ctx, coords[1]);
3659 }
3660 address[count++] = coords[1];
3661 }
3662 if (instr->coord_components > 2) {
3663 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3664 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3665 coords[2] = apply_round_slice(ctx, coords[2]);
3666 }
3667 address[count++] = coords[2];
3668 }
3669 }
3670
3671 /* Pack LOD */
3672 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3673 address[count++] = lod;
3674 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3675 address[count++] = sample_index;
3676 } else if(instr->op == nir_texop_txs) {
3677 count = 0;
3678 if (lod)
3679 address[count++] = lod;
3680 else
3681 address[count++] = ctx->i32zero;
3682 }
3683
3684 for (chan = 0; chan < count; chan++) {
3685 address[chan] = LLVMBuildBitCast(ctx->builder,
3686 address[chan], ctx->i32, "");
3687 }
3688
3689 if (instr->op == nir_texop_samples_identical) {
3690 LLVMValueRef txf_address[4];
3691 struct ac_tex_info txf_info = { 0 };
3692 unsigned txf_count = count;
3693 memcpy(txf_address, address, sizeof(txf_address));
3694
3695 if (!instr->is_array)
3696 txf_address[2] = ctx->i32zero;
3697 txf_address[3] = ctx->i32zero;
3698
3699 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3700 fmask_ptr, NULL,
3701 txf_address, txf_count, 0xf);
3702
3703 result = build_tex_intrinsic(ctx, instr, &txf_info);
3704
3705 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3706 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3707 goto write_result;
3708 }
3709
3710 /* Adjust the sample index according to FMASK.
3711 *
3712 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3713 * which is the identity mapping. Each nibble says which physical sample
3714 * should be fetched to get that sample.
3715 *
3716 * For example, 0x11111100 means there are only 2 samples stored and
3717 * the second sample covers 3/4 of the pixel. When reading samples 0
3718 * and 1, return physical sample 0 (determined by the first two 0s
3719 * in FMASK), otherwise return physical sample 1.
3720 *
3721 * The sample index should be adjusted as follows:
3722 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3723 */
3724 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
3725 instr->op != nir_texop_txs) {
3726 LLVMValueRef txf_address[4];
3727 struct ac_tex_info txf_info = { 0 };
3728 unsigned txf_count = count;
3729 memcpy(txf_address, address, sizeof(txf_address));
3730
3731 if (!instr->is_array)
3732 txf_address[2] = ctx->i32zero;
3733 txf_address[3] = ctx->i32zero;
3734
3735 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3736 fmask_ptr, NULL,
3737 txf_address, txf_count, 0xf);
3738
3739 result = build_tex_intrinsic(ctx, instr, &txf_info);
3740 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3741 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3742
3743 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3744 result,
3745 ctx->i32zero, "");
3746
3747 unsigned sample_chan = instr->is_array ? 3 : 2;
3748
3749 LLVMValueRef sample_index4 =
3750 LLVMBuildMul(ctx->builder, address[sample_chan], four, "");
3751 LLVMValueRef shifted_fmask =
3752 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3753 LLVMValueRef final_sample =
3754 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3755
3756 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3757 * resource descriptor is 0 (invalid),
3758 */
3759 LLVMValueRef fmask_desc =
3760 LLVMBuildBitCast(ctx->builder, fmask_ptr,
3761 ctx->v8i32, "");
3762
3763 LLVMValueRef fmask_word1 =
3764 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3765 ctx->i32one, "");
3766
3767 LLVMValueRef word1_is_nonzero =
3768 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3769 fmask_word1, ctx->i32zero, "");
3770
3771 /* Replace the MSAA sample index. */
3772 address[sample_chan] =
3773 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3774 final_sample, address[sample_chan], "");
3775 }
3776
3777 if (offsets && instr->op == nir_texop_txf) {
3778 nir_const_value *const_offset =
3779 nir_src_as_const_value(instr->src[const_src].src);
3780 int num_offsets = instr->src[const_src].src.ssa->num_components;
3781 assert(const_offset);
3782 num_offsets = MIN2(num_offsets, instr->coord_components);
3783 if (num_offsets > 2)
3784 address[2] = LLVMBuildAdd(ctx->builder,
3785 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3786 if (num_offsets > 1)
3787 address[1] = LLVMBuildAdd(ctx->builder,
3788 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3789 address[0] = LLVMBuildAdd(ctx->builder,
3790 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3791
3792 }
3793
3794 /* TODO TG4 support */
3795 if (instr->op == nir_texop_tg4) {
3796 if (instr->is_shadow)
3797 dmask = 1;
3798 else
3799 dmask = 1 << instr->component;
3800 }
3801 set_tex_fetch_args(ctx, &tinfo, instr, instr->op,
3802 res_ptr, samp_ptr, address, count, dmask);
3803
3804 result = build_tex_intrinsic(ctx, instr, &tinfo);
3805
3806 if (instr->op == nir_texop_query_levels)
3807 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3808 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3809 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3810 else if (instr->op == nir_texop_txs &&
3811 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3812 instr->is_array) {
3813 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3814 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3815 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3816 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3817 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3818 } else if (instr->dest.ssa.num_components != 4)
3819 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3820
3821 write_result:
3822 if (result) {
3823 assert(instr->dest.is_ssa);
3824 result = to_integer(ctx, result);
3825 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3826 }
3827 }
3828
3829
3830 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3831 {
3832 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3833 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3834
3835 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3836 _mesa_hash_table_insert(ctx->phis, instr, result);
3837 }
3838
3839 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3840 nir_phi_instr *instr,
3841 LLVMValueRef llvm_phi)
3842 {
3843 nir_foreach_phi_src(src, instr) {
3844 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3845 LLVMValueRef llvm_src = get_src(ctx, src->src);
3846
3847 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3848 }
3849 }
3850
3851 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3852 {
3853 struct hash_entry *entry;
3854 hash_table_foreach(ctx->phis, entry) {
3855 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3856 (LLVMValueRef)entry->data);
3857 }
3858 }
3859
3860
3861 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3862 nir_ssa_undef_instr *instr)
3863 {
3864 unsigned num_components = instr->def.num_components;
3865 LLVMValueRef undef;
3866
3867 if (num_components == 1)
3868 undef = LLVMGetUndef(ctx->i32);
3869 else {
3870 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3871 }
3872 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3873 }
3874
3875 static void visit_jump(struct nir_to_llvm_context *ctx,
3876 nir_jump_instr *instr)
3877 {
3878 switch (instr->type) {
3879 case nir_jump_break:
3880 LLVMBuildBr(ctx->builder, ctx->break_block);
3881 LLVMClearInsertionPosition(ctx->builder);
3882 break;
3883 case nir_jump_continue:
3884 LLVMBuildBr(ctx->builder, ctx->continue_block);
3885 LLVMClearInsertionPosition(ctx->builder);
3886 break;
3887 default:
3888 fprintf(stderr, "Unknown NIR jump instr: ");
3889 nir_print_instr(&instr->instr, stderr);
3890 fprintf(stderr, "\n");
3891 abort();
3892 }
3893 }
3894
3895 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3896 struct exec_list *list);
3897
3898 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3899 {
3900 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3901 nir_foreach_instr(instr, block)
3902 {
3903 switch (instr->type) {
3904 case nir_instr_type_alu:
3905 visit_alu(ctx, nir_instr_as_alu(instr));
3906 break;
3907 case nir_instr_type_load_const:
3908 visit_load_const(ctx, nir_instr_as_load_const(instr));
3909 break;
3910 case nir_instr_type_intrinsic:
3911 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3912 break;
3913 case nir_instr_type_tex:
3914 visit_tex(ctx, nir_instr_as_tex(instr));
3915 break;
3916 case nir_instr_type_phi:
3917 visit_phi(ctx, nir_instr_as_phi(instr));
3918 break;
3919 case nir_instr_type_ssa_undef:
3920 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3921 break;
3922 case nir_instr_type_jump:
3923 visit_jump(ctx, nir_instr_as_jump(instr));
3924 break;
3925 default:
3926 fprintf(stderr, "Unknown NIR instr type: ");
3927 nir_print_instr(instr, stderr);
3928 fprintf(stderr, "\n");
3929 abort();
3930 }
3931 }
3932
3933 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3934 }
3935
3936 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3937 {
3938 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3939
3940 LLVMBasicBlockRef merge_block =
3941 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3942 LLVMBasicBlockRef if_block =
3943 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3944 LLVMBasicBlockRef else_block = merge_block;
3945 if (!exec_list_is_empty(&if_stmt->else_list))
3946 else_block = LLVMAppendBasicBlockInContext(
3947 ctx->context, ctx->main_function, "");
3948
3949 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3950 LLVMConstInt(ctx->i32, 0, false), "");
3951 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3952
3953 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3954 visit_cf_list(ctx, &if_stmt->then_list);
3955 if (LLVMGetInsertBlock(ctx->builder))
3956 LLVMBuildBr(ctx->builder, merge_block);
3957
3958 if (!exec_list_is_empty(&if_stmt->else_list)) {
3959 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3960 visit_cf_list(ctx, &if_stmt->else_list);
3961 if (LLVMGetInsertBlock(ctx->builder))
3962 LLVMBuildBr(ctx->builder, merge_block);
3963 }
3964
3965 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3966 }
3967
3968 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3969 {
3970 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3971 LLVMBasicBlockRef break_parent = ctx->break_block;
3972
3973 ctx->continue_block =
3974 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3975 ctx->break_block =
3976 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3977
3978 LLVMBuildBr(ctx->builder, ctx->continue_block);
3979 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
3980 visit_cf_list(ctx, &loop->body);
3981
3982 if (LLVMGetInsertBlock(ctx->builder))
3983 LLVMBuildBr(ctx->builder, ctx->continue_block);
3984 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
3985
3986 ctx->continue_block = continue_parent;
3987 ctx->break_block = break_parent;
3988 }
3989
3990 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3991 struct exec_list *list)
3992 {
3993 foreach_list_typed(nir_cf_node, node, node, list)
3994 {
3995 switch (node->type) {
3996 case nir_cf_node_block:
3997 visit_block(ctx, nir_cf_node_as_block(node));
3998 break;
3999
4000 case nir_cf_node_if:
4001 visit_if(ctx, nir_cf_node_as_if(node));
4002 break;
4003
4004 case nir_cf_node_loop:
4005 visit_loop(ctx, nir_cf_node_as_loop(node));
4006 break;
4007
4008 default:
4009 assert(0);
4010 }
4011 }
4012 }
4013
4014 static void
4015 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4016 struct nir_variable *variable)
4017 {
4018 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4019 LLVMValueRef t_offset;
4020 LLVMValueRef t_list;
4021 LLVMValueRef args[3];
4022 LLVMValueRef input;
4023 LLVMValueRef buffer_index;
4024 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4025 int idx = variable->data.location;
4026 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4027
4028 variable->data.driver_location = idx * 4;
4029
4030 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4031 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4032 ctx->start_instance, "");
4033 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4034 ctx->shader_info->vs.vgpr_comp_cnt);
4035 } else
4036 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4037 ctx->base_vertex, "");
4038
4039 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4040 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4041
4042 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4043 args[0] = t_list;
4044 args[1] = LLVMConstInt(ctx->i32, 0, false);
4045 args[2] = buffer_index;
4046 input = ac_emit_llvm_intrinsic(&ctx->ac,
4047 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
4048 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
4049
4050 for (unsigned chan = 0; chan < 4; chan++) {
4051 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4052 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4053 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4054 input, llvm_chan, ""));
4055 }
4056 }
4057 }
4058
4059 static void
4060 handle_gs_input_decl(struct nir_to_llvm_context *ctx,
4061 struct nir_variable *variable)
4062 {
4063 int idx = variable->data.location;
4064
4065 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4066 idx == VARYING_SLOT_CULL_DIST0) {
4067 int length = glsl_get_length(glsl_get_array_element(variable->type));
4068 if (idx == VARYING_SLOT_CLIP_DIST0)
4069 ctx->num_input_clips = length;
4070 else
4071 ctx->num_input_culls = length;
4072 }
4073 }
4074
4075 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4076 unsigned attr,
4077 LLVMValueRef interp_param,
4078 LLVMValueRef prim_mask,
4079 LLVMValueRef result[4])
4080 {
4081 LLVMValueRef attr_number;
4082 unsigned chan;
4083 LLVMValueRef i, j;
4084 bool interp = interp_param != NULL;
4085
4086 attr_number = LLVMConstInt(ctx->i32, attr, false);
4087
4088 /* fs.constant returns the param from the middle vertex, so it's not
4089 * really useful for flat shading. It's meant to be used for custom
4090 * interpolation (but the intrinsic can't fetch from the other two
4091 * vertices).
4092 *
4093 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4094 * to do the right thing. The only reason we use fs.constant is that
4095 * fs.interp cannot be used on integers, because they can be equal
4096 * to NaN.
4097 */
4098 if (interp) {
4099 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4100 LLVMVectorType(ctx->f32, 2), "");
4101
4102 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4103 ctx->i32zero, "");
4104 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4105 ctx->i32one, "");
4106 }
4107
4108 for (chan = 0; chan < 4; chan++) {
4109 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4110
4111 if (interp) {
4112 result[chan] = ac_build_fs_interp(&ctx->ac,
4113 llvm_chan,
4114 attr_number,
4115 prim_mask, i, j);
4116 } else {
4117 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4118 LLVMConstInt(ctx->i32, 2, false),
4119 llvm_chan,
4120 attr_number,
4121 prim_mask);
4122 }
4123 }
4124 }
4125
4126 static void
4127 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4128 struct nir_variable *variable)
4129 {
4130 int idx = variable->data.location;
4131 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4132 LLVMValueRef interp;
4133
4134 variable->data.driver_location = idx * 4;
4135 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4136
4137 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4138 unsigned interp_type;
4139 if (variable->data.sample) {
4140 interp_type = INTERP_SAMPLE;
4141 ctx->shader_info->fs.force_persample = true;
4142 } else if (variable->data.centroid)
4143 interp_type = INTERP_CENTROID;
4144 else
4145 interp_type = INTERP_CENTER;
4146
4147 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4148 } else
4149 interp = NULL;
4150
4151 for (unsigned i = 0; i < attrib_count; ++i)
4152 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4153
4154 }
4155
4156 static void
4157 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4158 struct nir_variable *variable)
4159 {
4160 switch (ctx->stage) {
4161 case MESA_SHADER_VERTEX:
4162 handle_vs_input_decl(ctx, variable);
4163 break;
4164 case MESA_SHADER_FRAGMENT:
4165 handle_fs_input_decl(ctx, variable);
4166 break;
4167 case MESA_SHADER_GEOMETRY:
4168 handle_gs_input_decl(ctx, variable);
4169 break;
4170 default:
4171 break;
4172 }
4173
4174 }
4175
4176 static void
4177 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4178 struct nir_shader *nir)
4179 {
4180 unsigned index = 0;
4181 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4182 LLVMValueRef interp_param;
4183 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4184
4185 if (!(ctx->input_mask & (1ull << i)))
4186 continue;
4187
4188 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4189 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4190 interp_param = *inputs;
4191 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4192 inputs);
4193
4194 if (!interp_param)
4195 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4196 ++index;
4197 } else if (i == VARYING_SLOT_POS) {
4198 for(int i = 0; i < 3; ++i)
4199 inputs[i] = ctx->frag_pos[i];
4200
4201 inputs[3] = ac_emit_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4202 }
4203 }
4204 ctx->shader_info->fs.num_interp = index;
4205 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4206 ctx->shader_info->fs.has_pcoord = true;
4207 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4208 ctx->shader_info->fs.prim_id_input = true;
4209 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4210 ctx->shader_info->fs.layer_input = true;
4211 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4212 }
4213
4214 static LLVMValueRef
4215 ac_build_alloca(struct nir_to_llvm_context *ctx,
4216 LLVMTypeRef type,
4217 const char *name)
4218 {
4219 LLVMBuilderRef builder = ctx->builder;
4220 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4221 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4222 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4223 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4224 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4225 LLVMValueRef res;
4226
4227 if (first_instr) {
4228 LLVMPositionBuilderBefore(first_builder, first_instr);
4229 } else {
4230 LLVMPositionBuilderAtEnd(first_builder, first_block);
4231 }
4232
4233 res = LLVMBuildAlloca(first_builder, type, name);
4234 LLVMBuildStore(builder, LLVMConstNull(type), res);
4235
4236 LLVMDisposeBuilder(first_builder);
4237
4238 return res;
4239 }
4240
4241 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4242 LLVMTypeRef type,
4243 const char *name)
4244 {
4245 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4246 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4247 return ptr;
4248 }
4249
4250 static void
4251 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4252 struct nir_variable *variable)
4253 {
4254 int idx = variable->data.location + variable->data.index;
4255 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4256
4257 variable->data.driver_location = idx * 4;
4258
4259 if (ctx->stage == MESA_SHADER_VERTEX ||
4260 ctx->stage == MESA_SHADER_GEOMETRY) {
4261 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4262 idx == VARYING_SLOT_CULL_DIST0) {
4263 int length = glsl_get_length(variable->type);
4264 if (idx == VARYING_SLOT_CLIP_DIST0) {
4265 if (ctx->stage == MESA_SHADER_VERTEX)
4266 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
4267 ctx->num_output_clips = length;
4268 } else if (idx == VARYING_SLOT_CULL_DIST0) {
4269 if (ctx->stage == MESA_SHADER_VERTEX)
4270 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
4271 ctx->num_output_culls = length;
4272 }
4273 if (length > 4)
4274 attrib_count = 2;
4275 else
4276 attrib_count = 1;
4277 }
4278 }
4279
4280 for (unsigned i = 0; i < attrib_count; ++i) {
4281 for (unsigned chan = 0; chan < 4; chan++) {
4282 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4283 si_build_alloca_undef(ctx, ctx->f32, "");
4284 }
4285 }
4286 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
4287 }
4288
4289 static void
4290 setup_locals(struct nir_to_llvm_context *ctx,
4291 struct nir_function *func)
4292 {
4293 int i, j;
4294 ctx->num_locals = 0;
4295 nir_foreach_variable(variable, &func->impl->locals) {
4296 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4297 variable->data.driver_location = ctx->num_locals * 4;
4298 ctx->num_locals += attrib_count;
4299 }
4300 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4301 if (!ctx->locals)
4302 return;
4303
4304 for (i = 0; i < ctx->num_locals; i++) {
4305 for (j = 0; j < 4; j++) {
4306 ctx->locals[i * 4 + j] =
4307 si_build_alloca_undef(ctx, ctx->f32, "temp");
4308 }
4309 }
4310 }
4311
4312 static LLVMValueRef
4313 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4314 {
4315 v = to_float(ctx, v);
4316 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4317 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4318 }
4319
4320
4321 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4322 LLVMValueRef src0, LLVMValueRef src1)
4323 {
4324 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4325 LLVMValueRef comp[2];
4326
4327 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4328 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4329 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4330 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4331 }
4332
4333 /* Initialize arguments for the shader export intrinsic */
4334 static void
4335 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4336 LLVMValueRef *values,
4337 unsigned target,
4338 LLVMValueRef *args)
4339 {
4340 /* Default is 0xf. Adjusted below depending on the format. */
4341 args[0] = LLVMConstInt(ctx->i32, target != V_008DFC_SQ_EXP_NULL ? 0xf : 0, false);
4342 /* Specify whether the EXEC mask represents the valid mask */
4343 args[1] = LLVMConstInt(ctx->i32, 0, false);
4344
4345 /* Specify whether this is the last export */
4346 args[2] = LLVMConstInt(ctx->i32, 0, false);
4347 /* Specify the target we are exporting */
4348 args[3] = LLVMConstInt(ctx->i32, target, false);
4349
4350 args[4] = LLVMConstInt(ctx->i32, 0, false); /* COMPR flag */
4351 args[5] = LLVMGetUndef(ctx->f32);
4352 args[6] = LLVMGetUndef(ctx->f32);
4353 args[7] = LLVMGetUndef(ctx->f32);
4354 args[8] = LLVMGetUndef(ctx->f32);
4355
4356 if (!values)
4357 return;
4358
4359 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4360 LLVMValueRef val[4];
4361 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4362 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4363 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4364
4365 switch(col_format) {
4366 case V_028714_SPI_SHADER_ZERO:
4367 args[0] = LLVMConstInt(ctx->i32, 0x0, 0);
4368 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_NULL, 0);
4369 break;
4370
4371 case V_028714_SPI_SHADER_32_R:
4372 args[0] = LLVMConstInt(ctx->i32, 0x1, 0);
4373 args[5] = values[0];
4374 break;
4375
4376 case V_028714_SPI_SHADER_32_GR:
4377 args[0] = LLVMConstInt(ctx->i32, 0x3, 0);
4378 args[5] = values[0];
4379 args[6] = values[1];
4380 break;
4381
4382 case V_028714_SPI_SHADER_32_AR:
4383 args[0] = LLVMConstInt(ctx->i32, 0x9, 0);
4384 args[5] = values[0];
4385 args[8] = values[3];
4386 break;
4387
4388 case V_028714_SPI_SHADER_FP16_ABGR:
4389 args[4] = ctx->i32one;
4390
4391 for (unsigned chan = 0; chan < 2; chan++) {
4392 LLVMValueRef pack_args[2] = {
4393 values[2 * chan],
4394 values[2 * chan + 1]
4395 };
4396 LLVMValueRef packed;
4397
4398 packed = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.packf16",
4399 ctx->i32, pack_args, 2,
4400 AC_FUNC_ATTR_READNONE);
4401 args[chan + 5] = packed;
4402 }
4403 break;
4404
4405 case V_028714_SPI_SHADER_UNORM16_ABGR:
4406 for (unsigned chan = 0; chan < 4; chan++) {
4407 val[chan] = emit_float_saturate(ctx, values[chan], 0, 1);
4408 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4409 LLVMConstReal(ctx->f32, 65535), "");
4410 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4411 LLVMConstReal(ctx->f32, 0.5), "");
4412 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4413 ctx->i32, "");
4414 }
4415
4416 args[4] = ctx->i32one;
4417 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4418 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4419 break;
4420
4421 case V_028714_SPI_SHADER_SNORM16_ABGR:
4422 for (unsigned chan = 0; chan < 4; chan++) {
4423 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4424 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4425 LLVMConstReal(ctx->f32, 32767), "");
4426
4427 /* If positive, add 0.5, else add -0.5. */
4428 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4429 LLVMBuildSelect(ctx->builder,
4430 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4431 val[chan], ctx->f32zero, ""),
4432 LLVMConstReal(ctx->f32, 0.5),
4433 LLVMConstReal(ctx->f32, -0.5), ""), "");
4434 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4435 }
4436
4437 args[4] = ctx->i32one;
4438 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4439 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4440 break;
4441
4442 case V_028714_SPI_SHADER_UINT16_ABGR: {
4443 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4444
4445 for (unsigned chan = 0; chan < 4; chan++) {
4446 val[chan] = to_integer(ctx, values[chan]);
4447 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4448 }
4449
4450 args[4] = ctx->i32one;
4451 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4452 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4453 break;
4454 }
4455
4456 case V_028714_SPI_SHADER_SINT16_ABGR: {
4457 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4458 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4459
4460 /* Clamp. */
4461 for (unsigned chan = 0; chan < 4; chan++) {
4462 val[chan] = to_integer(ctx, values[chan]);
4463 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4464 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4465 }
4466
4467 args[4] = ctx->i32one;
4468 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4469 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4470 break;
4471 }
4472
4473 default:
4474 case V_028714_SPI_SHADER_32_ABGR:
4475 memcpy(&args[5], values, sizeof(values[0]) * 4);
4476 break;
4477 }
4478 } else
4479 memcpy(&args[5], values, sizeof(values[0]) * 4);
4480
4481 for (unsigned i = 5; i < 9; ++i)
4482 args[i] = to_float(ctx, args[i]);
4483 }
4484
4485 static void
4486 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4487 {
4488 uint32_t param_count = 0;
4489 unsigned target;
4490 unsigned pos_idx, num_pos_exports = 0;
4491 LLVMValueRef args[9];
4492 LLVMValueRef pos_args[4][9] = { { 0 } };
4493 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4494 int i;
4495 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4496 (1ull << VARYING_SLOT_CLIP_DIST1) |
4497 (1ull << VARYING_SLOT_CULL_DIST0) |
4498 (1ull << VARYING_SLOT_CULL_DIST1));
4499
4500 ctx->shader_info->vs.prim_id_output = 0xffffffff;
4501 ctx->shader_info->vs.layer_output = 0xffffffff;
4502 if (clip_mask) {
4503 LLVMValueRef slots[8];
4504 unsigned j;
4505
4506 if (ctx->shader_info->vs.cull_dist_mask)
4507 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_output_clips;
4508
4509 i = VARYING_SLOT_CLIP_DIST0;
4510 for (j = 0; j < ctx->num_output_clips; j++)
4511 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4512 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4513 i = VARYING_SLOT_CULL_DIST0;
4514 for (j = 0; j < ctx->num_output_culls; j++)
4515 slots[ctx->num_output_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4516 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4517
4518 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
4519 slots[i] = LLVMGetUndef(ctx->f32);
4520
4521 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
4522 target = V_008DFC_SQ_EXP_POS + 3;
4523 si_llvm_init_export_args(ctx, &slots[4], target, args);
4524 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4525 args, sizeof(args));
4526 }
4527
4528 target = V_008DFC_SQ_EXP_POS + 2;
4529 si_llvm_init_export_args(ctx, &slots[0], target, args);
4530 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4531 args, sizeof(args));
4532
4533 }
4534
4535 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4536 LLVMValueRef values[4];
4537 if (!(ctx->output_mask & (1ull << i)))
4538 continue;
4539
4540 for (unsigned j = 0; j < 4; j++)
4541 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4542 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4543
4544 if (i == VARYING_SLOT_POS) {
4545 target = V_008DFC_SQ_EXP_POS;
4546 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4547 i == VARYING_SLOT_CLIP_DIST1 ||
4548 i == VARYING_SLOT_CULL_DIST0 ||
4549 i == VARYING_SLOT_CULL_DIST1) {
4550 continue;
4551 } else if (i == VARYING_SLOT_PSIZ) {
4552 ctx->shader_info->vs.writes_pointsize = true;
4553 psize_value = values[0];
4554 continue;
4555 } else if (i == VARYING_SLOT_LAYER) {
4556 ctx->shader_info->vs.writes_layer = true;
4557 layer_value = values[0];
4558 ctx->shader_info->vs.layer_output = param_count;
4559 target = V_008DFC_SQ_EXP_PARAM + param_count;
4560 param_count++;
4561 } else if (i == VARYING_SLOT_VIEWPORT) {
4562 ctx->shader_info->vs.writes_viewport_index = true;
4563 viewport_index_value = values[0];
4564 continue;
4565 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
4566 ctx->shader_info->vs.prim_id_output = param_count;
4567 target = V_008DFC_SQ_EXP_PARAM + param_count;
4568 param_count++;
4569 } else if (i >= VARYING_SLOT_VAR0) {
4570 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4571 target = V_008DFC_SQ_EXP_PARAM + param_count;
4572 param_count++;
4573 }
4574
4575 si_llvm_init_export_args(ctx, values, target, args);
4576
4577 if (target >= V_008DFC_SQ_EXP_POS &&
4578 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4579 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4580 args, sizeof(args));
4581 } else {
4582 ac_emit_llvm_intrinsic(&ctx->ac,
4583 "llvm.SI.export",
4584 ctx->voidt,
4585 args, 9, 0);
4586 }
4587 }
4588
4589 /* We need to add the position output manually if it's missing. */
4590 if (!pos_args[0][0]) {
4591 pos_args[0][0] = LLVMConstInt(ctx->i32, 0xf, false);
4592 pos_args[0][1] = ctx->i32zero; /* EXEC mask */
4593 pos_args[0][2] = ctx->i32zero; /* last export? */
4594 pos_args[0][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS, false);
4595 pos_args[0][4] = ctx->i32zero; /* COMPR flag */
4596 pos_args[0][5] = ctx->f32zero; /* X */
4597 pos_args[0][6] = ctx->f32zero; /* Y */
4598 pos_args[0][7] = ctx->f32zero; /* Z */
4599 pos_args[0][8] = ctx->f32one; /* W */
4600 }
4601
4602 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4603 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4604 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4605 if (mask) {
4606 pos_args[1][0] = LLVMConstInt(ctx->i32, mask, false); /* writemask */
4607 pos_args[1][1] = ctx->i32zero; /* EXEC mask */
4608 pos_args[1][2] = ctx->i32zero; /* last export? */
4609 pos_args[1][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + 1, false);
4610 pos_args[1][4] = ctx->i32zero; /* COMPR flag */
4611 pos_args[1][5] = ctx->f32zero; /* X */
4612 pos_args[1][6] = ctx->f32zero; /* Y */
4613 pos_args[1][7] = ctx->f32zero; /* Z */
4614 pos_args[1][8] = ctx->f32zero; /* W */
4615
4616 if (ctx->shader_info->vs.writes_pointsize == true)
4617 pos_args[1][5] = psize_value;
4618 if (ctx->shader_info->vs.writes_layer == true)
4619 pos_args[1][7] = layer_value;
4620 if (ctx->shader_info->vs.writes_viewport_index == true)
4621 pos_args[1][8] = viewport_index_value;
4622 }
4623 for (i = 0; i < 4; i++) {
4624 if (pos_args[i][0])
4625 num_pos_exports++;
4626 }
4627
4628 pos_idx = 0;
4629 for (i = 0; i < 4; i++) {
4630 if (!pos_args[i][0])
4631 continue;
4632
4633 /* Specify the target we are exporting */
4634 pos_args[i][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + pos_idx++, false);
4635 if (pos_idx == num_pos_exports)
4636 pos_args[i][2] = ctx->i32one;
4637 ac_emit_llvm_intrinsic(&ctx->ac,
4638 "llvm.SI.export",
4639 ctx->voidt,
4640 pos_args[i], 9, 0);
4641 }
4642
4643 ctx->shader_info->vs.pos_exports = num_pos_exports;
4644 ctx->shader_info->vs.param_exports = param_count;
4645 }
4646
4647 static void
4648 handle_es_outputs_post(struct nir_to_llvm_context *ctx)
4649 {
4650 int j;
4651 uint64_t max_output_written = 0;
4652 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4653 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
4654 int param_index;
4655 int length = 4;
4656 int start = 0;
4657 if (!(ctx->output_mask & (1ull << i)))
4658 continue;
4659
4660 if (i == VARYING_SLOT_CLIP_DIST0) {
4661 length = ctx->num_output_clips;
4662 } else if (i == VARYING_SLOT_CULL_DIST0) {
4663 start = ctx->num_output_clips;
4664 length = ctx->num_output_culls;
4665 }
4666 param_index = shader_io_get_unique_index(i);
4667
4668 if (param_index > max_output_written)
4669 max_output_written = param_index;
4670
4671 for (j = 0; j < length; j++) {
4672 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
4673 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4674
4675 ac_build_tbuffer_store(&ctx->ac,
4676 ctx->esgs_ring,
4677 out_val, 1,
4678 LLVMGetUndef(ctx->i32), ctx->es2gs_offset,
4679 (4 * param_index + j + start) * 4,
4680 V_008F0C_BUF_DATA_FORMAT_32,
4681 V_008F0C_BUF_NUM_FORMAT_UINT,
4682 0, 0, 1, 1, 0);
4683 }
4684 }
4685 ctx->shader_info->vs.esgs_itemsize = (max_output_written + 1) * 16;
4686 }
4687
4688 static void
4689 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4690 LLVMValueRef *color, unsigned param, bool is_last)
4691 {
4692 LLVMValueRef args[9];
4693 /* Export */
4694 si_llvm_init_export_args(ctx, color, param,
4695 args);
4696
4697 if (is_last) {
4698 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4699 args[2] = ctx->i32one; /* DONE bit */
4700 } else if (args[0] == ctx->i32zero)
4701 return; /* unnecessary NULL export */
4702
4703 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4704 ctx->voidt, args, 9, 0);
4705 }
4706
4707 static void
4708 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4709 LLVMValueRef depth, LLVMValueRef stencil,
4710 LLVMValueRef samplemask)
4711 {
4712 LLVMValueRef args[9];
4713 unsigned mask = 0;
4714 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4715 args[2] = ctx->i32one; /* DONE bit */
4716 /* Specify the target we are exporting */
4717 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_MRTZ, false);
4718
4719 args[4] = ctx->i32zero; /* COMP flag */
4720 args[5] = LLVMGetUndef(ctx->f32); /* R, depth */
4721 args[6] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4722 args[7] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4723 args[8] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4724
4725 if (depth) {
4726 args[5] = depth;
4727 mask |= 0x1;
4728 }
4729
4730 if (stencil) {
4731 args[6] = stencil;
4732 mask |= 0x2;
4733 }
4734
4735 if (samplemask) {
4736 args[7] = samplemask;
4737 mask |= 0x04;
4738 }
4739
4740 /* SI (except OLAND) has a bug that it only looks
4741 * at the X writemask component. */
4742 if (ctx->options->chip_class == SI &&
4743 ctx->options->family != CHIP_OLAND)
4744 mask |= 0x01;
4745
4746 args[0] = LLVMConstInt(ctx->i32, mask, false);
4747 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4748 ctx->voidt, args, 9, 0);
4749 }
4750
4751 static void
4752 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4753 {
4754 unsigned index = 0;
4755 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4756
4757 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4758 LLVMValueRef values[4];
4759
4760 if (!(ctx->output_mask & (1ull << i)))
4761 continue;
4762
4763 if (i == FRAG_RESULT_DEPTH) {
4764 ctx->shader_info->fs.writes_z = true;
4765 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4766 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4767 } else if (i == FRAG_RESULT_STENCIL) {
4768 ctx->shader_info->fs.writes_stencil = true;
4769 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4770 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4771 } else {
4772 bool last = false;
4773 for (unsigned j = 0; j < 4; j++)
4774 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4775 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4776
4777 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil)
4778 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4779
4780 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4781 index++;
4782 }
4783 }
4784
4785 if (depth || stencil)
4786 si_export_mrt_z(ctx, depth, stencil, samplemask);
4787 else if (!index)
4788 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4789
4790 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4791 }
4792
4793 static void
4794 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4795 {
4796 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
4797 }
4798
4799 static void
4800 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4801 {
4802 switch (ctx->stage) {
4803 case MESA_SHADER_VERTEX:
4804 if (ctx->options->key.vs.as_es)
4805 handle_es_outputs_post(ctx);
4806 else
4807 handle_vs_outputs_post(ctx);
4808 break;
4809 case MESA_SHADER_FRAGMENT:
4810 handle_fs_outputs_post(ctx);
4811 break;
4812 case MESA_SHADER_GEOMETRY:
4813 emit_gs_epilogue(ctx);
4814 break;
4815 default:
4816 break;
4817 }
4818 }
4819
4820 static void
4821 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4822 struct nir_variable *variable, uint32_t *offset, int idx)
4823 {
4824 unsigned size = glsl_count_attribute_slots(variable->type, false);
4825 variable->data.driver_location = *offset;
4826 *offset += size;
4827 }
4828
4829 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4830 {
4831 LLVMPassManagerRef passmgr;
4832 /* Create the pass manager */
4833 passmgr = LLVMCreateFunctionPassManagerForModule(
4834 ctx->module);
4835
4836 /* This pass should eliminate all the load and store instructions */
4837 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4838
4839 /* Add some optimization passes */
4840 LLVMAddScalarReplAggregatesPass(passmgr);
4841 LLVMAddLICMPass(passmgr);
4842 LLVMAddAggressiveDCEPass(passmgr);
4843 LLVMAddCFGSimplificationPass(passmgr);
4844 LLVMAddInstructionCombiningPass(passmgr);
4845
4846 /* Run the pass */
4847 LLVMInitializeFunctionPassManager(passmgr);
4848 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4849 LLVMFinalizeFunctionPassManager(passmgr);
4850
4851 LLVMDisposeBuilder(ctx->builder);
4852 LLVMDisposePassManager(passmgr);
4853 }
4854
4855 static void
4856 ac_setup_rings(struct nir_to_llvm_context *ctx)
4857 {
4858 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4859 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, ctx->i32one);
4860 }
4861
4862 if (ctx->is_gs_copy_shader) {
4863 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4864 }
4865 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4866 LLVMValueRef tmp;
4867 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4868 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4869
4870 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4871
4872 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4873 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4874 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4875 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4876
4877 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4878 }
4879 }
4880
4881 static
4882 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4883 struct nir_shader *nir,
4884 struct ac_shader_variant_info *shader_info,
4885 const struct ac_nir_compiler_options *options)
4886 {
4887 struct nir_to_llvm_context ctx = {0};
4888 struct nir_function *func;
4889 unsigned i;
4890 ctx.options = options;
4891 ctx.shader_info = shader_info;
4892 ctx.context = LLVMContextCreate();
4893 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4894
4895 ac_llvm_context_init(&ctx.ac, ctx.context);
4896 ctx.ac.module = ctx.module;
4897
4898 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4899
4900 memset(shader_info, 0, sizeof(*shader_info));
4901
4902 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4903 setup_types(&ctx);
4904
4905 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4906 ctx.ac.builder = ctx.builder;
4907 ctx.stage = nir->stage;
4908
4909 for (i = 0; i < AC_UD_MAX_SETS; i++)
4910 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4911 for (i = 0; i < AC_UD_MAX_UD; i++)
4912 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4913
4914 create_function(&ctx);
4915
4916 if (nir->stage == MESA_SHADER_COMPUTE) {
4917 int num_shared = 0;
4918 nir_foreach_variable(variable, &nir->shared)
4919 num_shared++;
4920 if (num_shared) {
4921 int idx = 0;
4922 uint32_t shared_size = 0;
4923 LLVMValueRef var;
4924 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4925 nir_foreach_variable(variable, &nir->shared) {
4926 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4927 idx++;
4928 }
4929
4930 shared_size *= 16;
4931 var = LLVMAddGlobalInAddressSpace(ctx.module,
4932 LLVMArrayType(ctx.i8, shared_size),
4933 "compute_lds",
4934 LOCAL_ADDR_SPACE);
4935 LLVMSetAlignment(var, 4);
4936 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4937 }
4938 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4939 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4940
4941 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4942 }
4943
4944 ac_setup_rings(&ctx);
4945
4946 nir_foreach_variable(variable, &nir->inputs)
4947 handle_shader_input_decl(&ctx, variable);
4948
4949 if (nir->stage == MESA_SHADER_FRAGMENT)
4950 handle_fs_inputs_pre(&ctx, nir);
4951
4952 nir_foreach_variable(variable, &nir->outputs)
4953 handle_shader_output_decl(&ctx, variable);
4954
4955 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4956 _mesa_key_pointer_equal);
4957 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4958 _mesa_key_pointer_equal);
4959
4960 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4961
4962 setup_locals(&ctx, func);
4963
4964 visit_cf_list(&ctx, &func->impl->body);
4965 phi_post_pass(&ctx);
4966
4967 handle_shader_outputs_post(&ctx);
4968 LLVMBuildRetVoid(ctx.builder);
4969
4970 ac_llvm_finalize_module(&ctx);
4971 free(ctx.locals);
4972 ralloc_free(ctx.defs);
4973 ralloc_free(ctx.phis);
4974
4975 if (nir->stage == MESA_SHADER_GEOMETRY) {
4976 shader_info->gs.gsvs_vertex_size = util_bitcount64(ctx.output_mask) * 16;
4977 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
4978 nir->info->gs.vertices_out;
4979 }
4980 return ctx.module;
4981 }
4982
4983 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4984 {
4985 unsigned *retval = (unsigned *)context;
4986 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4987 char *description = LLVMGetDiagInfoDescription(di);
4988
4989 if (severity == LLVMDSError) {
4990 *retval = 1;
4991 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4992 description);
4993 }
4994
4995 LLVMDisposeMessage(description);
4996 }
4997
4998 static unsigned ac_llvm_compile(LLVMModuleRef M,
4999 struct ac_shader_binary *binary,
5000 LLVMTargetMachineRef tm)
5001 {
5002 unsigned retval = 0;
5003 char *err;
5004 LLVMContextRef llvm_ctx;
5005 LLVMMemoryBufferRef out_buffer;
5006 unsigned buffer_size;
5007 const char *buffer_data;
5008 LLVMBool mem_err;
5009
5010 /* Setup Diagnostic Handler*/
5011 llvm_ctx = LLVMGetModuleContext(M);
5012
5013 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
5014 &retval);
5015
5016 /* Compile IR*/
5017 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
5018 &err, &out_buffer);
5019
5020 /* Process Errors/Warnings */
5021 if (mem_err) {
5022 fprintf(stderr, "%s: %s", __FUNCTION__, err);
5023 free(err);
5024 retval = 1;
5025 goto out;
5026 }
5027
5028 /* Extract Shader Code*/
5029 buffer_size = LLVMGetBufferSize(out_buffer);
5030 buffer_data = LLVMGetBufferStart(out_buffer);
5031
5032 ac_elf_read(buffer_data, buffer_size, binary);
5033
5034 /* Clean up */
5035 LLVMDisposeMemoryBuffer(out_buffer);
5036
5037 out:
5038 return retval;
5039 }
5040
5041 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
5042 LLVMModuleRef llvm_module,
5043 struct ac_shader_binary *binary,
5044 struct ac_shader_config *config,
5045 struct ac_shader_variant_info *shader_info,
5046 gl_shader_stage stage,
5047 bool dump_shader, bool supports_spill)
5048 {
5049 if (dump_shader)
5050 ac_dump_module(llvm_module);
5051
5052 memset(binary, 0, sizeof(*binary));
5053 int v = ac_llvm_compile(llvm_module, binary, tm);
5054 if (v) {
5055 fprintf(stderr, "compile failed\n");
5056 }
5057
5058 if (dump_shader)
5059 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
5060
5061 ac_shader_binary_read_config(binary, config, 0, supports_spill);
5062
5063 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
5064 LLVMDisposeModule(llvm_module);
5065 LLVMContextDispose(ctx);
5066
5067 if (stage == MESA_SHADER_FRAGMENT) {
5068 shader_info->num_input_vgprs = 0;
5069 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
5070 shader_info->num_input_vgprs += 2;
5071 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
5072 shader_info->num_input_vgprs += 2;
5073 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
5074 shader_info->num_input_vgprs += 2;
5075 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
5076 shader_info->num_input_vgprs += 3;
5077 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
5078 shader_info->num_input_vgprs += 2;
5079 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
5080 shader_info->num_input_vgprs += 2;
5081 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
5082 shader_info->num_input_vgprs += 2;
5083 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
5084 shader_info->num_input_vgprs += 1;
5085 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
5086 shader_info->num_input_vgprs += 1;
5087 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
5088 shader_info->num_input_vgprs += 1;
5089 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5090 shader_info->num_input_vgprs += 1;
5091 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5092 shader_info->num_input_vgprs += 1;
5093 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5094 shader_info->num_input_vgprs += 1;
5095 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5096 shader_info->num_input_vgprs += 1;
5097 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5098 shader_info->num_input_vgprs += 1;
5099 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5100 shader_info->num_input_vgprs += 1;
5101 }
5102 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5103
5104 /* +3 for scratch wave offset and VCC */
5105 config->num_sgprs = MAX2(config->num_sgprs,
5106 shader_info->num_input_sgprs + 3);
5107 }
5108
5109 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5110 struct ac_shader_binary *binary,
5111 struct ac_shader_config *config,
5112 struct ac_shader_variant_info *shader_info,
5113 struct nir_shader *nir,
5114 const struct ac_nir_compiler_options *options,
5115 bool dump_shader)
5116 {
5117
5118 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5119 options);
5120
5121 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5122 switch (nir->stage) {
5123 case MESA_SHADER_COMPUTE:
5124 for (int i = 0; i < 3; ++i)
5125 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5126 break;
5127 case MESA_SHADER_FRAGMENT:
5128 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5129 break;
5130 case MESA_SHADER_GEOMETRY:
5131 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5132 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5133 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5134 shader_info->gs.invocations = nir->info->gs.invocations;
5135 break;
5136 case MESA_SHADER_VERTEX:
5137 shader_info->vs.as_es = options->key.vs.as_es;
5138 break;
5139 default:
5140 break;
5141 }
5142 }
5143
5144 static void
5145 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5146 {
5147 LLVMValueRef args[9];
5148 args[0] = ctx->gsvs_ring;
5149 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5150 args[3] = ctx->i32zero;
5151 args[4] = ctx->i32one; /* OFFEN */
5152 args[5] = ctx->i32zero; /* IDXEN */
5153 args[6] = ctx->i32one; /* GLC */
5154 args[7] = ctx->i32one; /* SLC */
5155 args[8] = ctx->i32zero; /* TFE */
5156
5157 int idx = 0;
5158 int clip_cull_slot = -1;
5159 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5160 int length = 4;
5161 int start = 0;
5162 int slot = idx;
5163 int slot_inc = 1;
5164 if (!(ctx->output_mask & (1ull << i)))
5165 continue;
5166
5167 if (i == VARYING_SLOT_CLIP_DIST1 ||
5168 i == VARYING_SLOT_CULL_DIST1)
5169 continue;
5170
5171 if (i == VARYING_SLOT_CLIP_DIST0 ||
5172 i == VARYING_SLOT_CULL_DIST0) {
5173 /* unpack clip and cull from a single set of slots */
5174 if (clip_cull_slot == -1) {
5175 clip_cull_slot = idx;
5176 if (ctx->num_output_clips + ctx->num_output_culls > 4)
5177 slot_inc = 2;
5178 } else {
5179 slot = clip_cull_slot;
5180 slot_inc = 0;
5181 }
5182 if (i == VARYING_SLOT_CLIP_DIST0)
5183 length = ctx->num_output_clips;
5184 if (i == VARYING_SLOT_CULL_DIST0) {
5185 start = ctx->num_output_clips;
5186 length = ctx->num_output_culls;
5187 }
5188 }
5189
5190 for (unsigned j = 0; j < length; j++) {
5191 LLVMValueRef value;
5192 args[2] = LLVMConstInt(ctx->i32,
5193 (slot * 4 + j + start) *
5194 ctx->gs_max_out_vertices * 16 * 4, false);
5195
5196 value = ac_emit_llvm_intrinsic(&ctx->ac,
5197 "llvm.SI.buffer.load.dword.i32.i32",
5198 ctx->i32, args, 9,
5199 AC_FUNC_ATTR_READONLY);
5200
5201 LLVMBuildStore(ctx->builder,
5202 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
5203 }
5204 idx += slot_inc;
5205 }
5206 handle_vs_outputs_post(ctx);
5207 }
5208
5209 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5210 struct nir_shader *geom_shader,
5211 struct ac_shader_binary *binary,
5212 struct ac_shader_config *config,
5213 struct ac_shader_variant_info *shader_info,
5214 const struct ac_nir_compiler_options *options,
5215 bool dump_shader)
5216 {
5217 struct nir_to_llvm_context ctx = {0};
5218 ctx.context = LLVMContextCreate();
5219 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5220 ctx.options = options;
5221 ctx.shader_info = shader_info;
5222
5223 ac_llvm_context_init(&ctx.ac, ctx.context);
5224 ctx.ac.module = ctx.module;
5225
5226 ctx.is_gs_copy_shader = true;
5227 LLVMSetTarget(ctx.module, "amdgcn--");
5228 setup_types(&ctx);
5229
5230 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5231 ctx.ac.builder = ctx.builder;
5232 ctx.stage = MESA_SHADER_VERTEX;
5233
5234 create_function(&ctx);
5235
5236 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5237 ac_setup_rings(&ctx);
5238
5239 nir_foreach_variable(variable, &geom_shader->outputs)
5240 handle_shader_output_decl(&ctx, variable);
5241
5242 ac_gs_copy_shader_emit(&ctx);
5243
5244 LLVMBuildRetVoid(ctx.builder);
5245
5246 ac_llvm_finalize_module(&ctx);
5247
5248 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5249 MESA_SHADER_VERTEX,
5250 dump_shader, options->supports_spill);
5251 }