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radv/ac: rename num clips/cull to output clips/culls
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef gsvs_ring_stride;
87 LLVMValueRef gsvs_num_entries;
88 LLVMValueRef gs2vs_offset;
89 LLVMValueRef gs_wave_id;
90 LLVMValueRef gs_vtx_offset[6];
91 LLVMValueRef gs_prim_id, gs_invocation_id;
92
93 LLVMValueRef esgs_ring;
94 LLVMValueRef gsvs_ring;
95
96 LLVMValueRef prim_mask;
97 LLVMValueRef sample_positions;
98 LLVMValueRef persp_sample, persp_center, persp_centroid;
99 LLVMValueRef linear_sample, linear_center, linear_centroid;
100 LLVMValueRef front_face;
101 LLVMValueRef ancillary;
102 LLVMValueRef frag_pos[4];
103
104 LLVMBasicBlockRef continue_block;
105 LLVMBasicBlockRef break_block;
106
107 LLVMTypeRef i1;
108 LLVMTypeRef i8;
109 LLVMTypeRef i16;
110 LLVMTypeRef i32;
111 LLVMTypeRef i64;
112 LLVMTypeRef v2i32;
113 LLVMTypeRef v3i32;
114 LLVMTypeRef v4i32;
115 LLVMTypeRef v8i32;
116 LLVMTypeRef f64;
117 LLVMTypeRef f32;
118 LLVMTypeRef f16;
119 LLVMTypeRef v2f32;
120 LLVMTypeRef v4f32;
121 LLVMTypeRef v16i8;
122 LLVMTypeRef voidt;
123
124 LLVMValueRef i32zero;
125 LLVMValueRef i32one;
126 LLVMValueRef f32zero;
127 LLVMValueRef f32one;
128 LLVMValueRef v4f32empty;
129
130 unsigned uniform_md_kind;
131 LLVMValueRef empty_md;
132 gl_shader_stage stage;
133
134 LLVMValueRef lds;
135 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
136 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
137
138 LLVMValueRef shared_memory;
139 uint64_t input_mask;
140 uint64_t output_mask;
141 int num_locals;
142 LLVMValueRef *locals;
143 bool has_ddxy;
144 uint8_t num_output_clips;
145 uint8_t num_output_culls;
146
147 bool has_ds_bpermute;
148
149 bool is_gs_copy_shader;
150 LLVMValueRef gs_next_vertex;
151 unsigned gs_max_out_vertices;
152 };
153
154 struct ac_tex_info {
155 LLVMValueRef args[12];
156 int arg_count;
157 LLVMTypeRef dst_type;
158 bool has_offset;
159 };
160
161 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
162 nir_deref_var *deref,
163 enum desc_type desc_type);
164 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
165 {
166 return (index * 4) + chan;
167 }
168
169 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
170 {
171 if (slot == VARYING_SLOT_POS)
172 return 0;
173 if (slot == VARYING_SLOT_PSIZ)
174 return 1;
175 if (slot == VARYING_SLOT_CLIP_DIST0)
176 return 2;
177 if (slot == VARYING_SLOT_CLIP_DIST1)
178 return 3;
179 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
180 return 4 + (slot - VARYING_SLOT_VAR0);
181 unreachable("illegal slot in get unique index\n");
182 }
183
184 static unsigned llvm_get_type_size(LLVMTypeRef type)
185 {
186 LLVMTypeKind kind = LLVMGetTypeKind(type);
187
188 switch (kind) {
189 case LLVMIntegerTypeKind:
190 return LLVMGetIntTypeWidth(type) / 8;
191 case LLVMFloatTypeKind:
192 return 4;
193 case LLVMPointerTypeKind:
194 return 8;
195 case LLVMVectorTypeKind:
196 return LLVMGetVectorSize(type) *
197 llvm_get_type_size(LLVMGetElementType(type));
198 default:
199 assert(0);
200 return 0;
201 }
202 }
203
204 static void set_llvm_calling_convention(LLVMValueRef func,
205 gl_shader_stage stage)
206 {
207 enum radeon_llvm_calling_convention calling_conv;
208
209 switch (stage) {
210 case MESA_SHADER_VERTEX:
211 case MESA_SHADER_TESS_CTRL:
212 case MESA_SHADER_TESS_EVAL:
213 calling_conv = RADEON_LLVM_AMDGPU_VS;
214 break;
215 case MESA_SHADER_GEOMETRY:
216 calling_conv = RADEON_LLVM_AMDGPU_GS;
217 break;
218 case MESA_SHADER_FRAGMENT:
219 calling_conv = RADEON_LLVM_AMDGPU_PS;
220 break;
221 case MESA_SHADER_COMPUTE:
222 calling_conv = RADEON_LLVM_AMDGPU_CS;
223 break;
224 default:
225 unreachable("Unhandle shader type");
226 }
227
228 LLVMSetFunctionCallConv(func, calling_conv);
229 }
230
231 static LLVMValueRef
232 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
233 LLVMBuilderRef builder, LLVMTypeRef *return_types,
234 unsigned num_return_elems, LLVMTypeRef *param_types,
235 unsigned param_count, unsigned array_params_mask,
236 unsigned sgpr_params, bool unsafe_math)
237 {
238 LLVMTypeRef main_function_type, ret_type;
239 LLVMBasicBlockRef main_function_body;
240
241 if (num_return_elems)
242 ret_type = LLVMStructTypeInContext(ctx, return_types,
243 num_return_elems, true);
244 else
245 ret_type = LLVMVoidTypeInContext(ctx);
246
247 /* Setup the function */
248 main_function_type =
249 LLVMFunctionType(ret_type, param_types, param_count, 0);
250 LLVMValueRef main_function =
251 LLVMAddFunction(module, "main", main_function_type);
252 main_function_body =
253 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
254 LLVMPositionBuilderAtEnd(builder, main_function_body);
255
256 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
257 for (unsigned i = 0; i < sgpr_params; ++i) {
258 if (array_params_mask & (1 << i)) {
259 LLVMValueRef P = LLVMGetParam(main_function, i);
260 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_BYVAL);
261 ac_add_attr_dereferenceable(P, UINT64_MAX);
262 }
263 else {
264 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_INREG);
265 }
266 }
267
268 if (unsafe_math) {
269 /* These were copied from some LLVM test. */
270 LLVMAddTargetDependentFunctionAttr(main_function,
271 "less-precise-fpmad",
272 "true");
273 LLVMAddTargetDependentFunctionAttr(main_function,
274 "no-infs-fp-math",
275 "true");
276 LLVMAddTargetDependentFunctionAttr(main_function,
277 "no-nans-fp-math",
278 "true");
279 LLVMAddTargetDependentFunctionAttr(main_function,
280 "unsafe-fp-math",
281 "true");
282 }
283 return main_function;
284 }
285
286 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
287 {
288 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
289 CONST_ADDR_SPACE);
290 }
291
292 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
293 int idx,
294 LLVMTypeRef type)
295 {
296 LLVMValueRef offset;
297 LLVMValueRef ptr;
298 int addr_space;
299
300 offset = LLVMConstInt(ctx->i32, idx, false);
301
302 ptr = ctx->shared_memory;
303 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
304 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
305 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
306 return ptr;
307 }
308
309 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
310 {
311 if (t == ctx->f16 || t == ctx->i16)
312 return ctx->i16;
313 else if (t == ctx->f32 || t == ctx->i32)
314 return ctx->i32;
315 else if (t == ctx->f64 || t == ctx->i64)
316 return ctx->i64;
317 else
318 unreachable("Unhandled integer size");
319 }
320
321 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
322 {
323 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
324 LLVMTypeRef elem_type = LLVMGetElementType(t);
325 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
326 LLVMGetVectorSize(t));
327 }
328 return to_integer_type_scalar(ctx, t);
329 }
330
331 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
332 {
333 LLVMTypeRef type = LLVMTypeOf(v);
334 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
335 }
336
337 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
338 {
339 if (t == ctx->i16 || t == ctx->f16)
340 return ctx->f16;
341 else if (t == ctx->i32 || t == ctx->f32)
342 return ctx->f32;
343 else if (t == ctx->i64 || t == ctx->f64)
344 return ctx->f64;
345 else
346 unreachable("Unhandled float size");
347 }
348
349 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
350 {
351 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
352 LLVMTypeRef elem_type = LLVMGetElementType(t);
353 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
354 LLVMGetVectorSize(t));
355 }
356 return to_float_type_scalar(ctx, t);
357 }
358
359 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
360 {
361 LLVMTypeRef type = LLVMTypeOf(v);
362 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
363 }
364
365 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
366 {
367 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
368 type = LLVMGetElementType(type);
369
370 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
371 return LLVMGetIntTypeWidth(type);
372
373 if (type == ctx->f16)
374 return 16;
375 if (type == ctx->f32)
376 return 32;
377 if (type == ctx->f64)
378 return 64;
379
380 unreachable("Unhandled type kind in get_elem_bits");
381 }
382
383 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
384 LLVMValueRef param, unsigned rshift,
385 unsigned bitwidth)
386 {
387 LLVMValueRef value = param;
388 if (rshift)
389 value = LLVMBuildLShr(ctx->builder, value,
390 LLVMConstInt(ctx->i32, rshift, false), "");
391
392 if (rshift + bitwidth < 32) {
393 unsigned mask = (1 << bitwidth) - 1;
394 value = LLVMBuildAnd(ctx->builder, value,
395 LLVMConstInt(ctx->i32, mask, false), "");
396 }
397 return value;
398 }
399
400 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
401 {
402 ud_info->sgpr_idx = sgpr_idx;
403 ud_info->num_sgprs = num_sgprs;
404 ud_info->indirect = false;
405 ud_info->indirect_offset = 0;
406 }
407
408 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
409 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
410 {
411 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
412 }
413
414 #if 0
415 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
416 uint32_t indirect_offset)
417 {
418 ud_info->sgpr_idx = sgpr_idx;
419 ud_info->num_sgprs = num_sgprs;
420 ud_info->indirect = true;
421 ud_info->indirect_offset = indirect_offset;
422 }
423 #endif
424
425 static void create_function(struct nir_to_llvm_context *ctx)
426 {
427 LLVMTypeRef arg_types[23];
428 unsigned arg_idx = 0;
429 unsigned array_params_mask = 0;
430 unsigned sgpr_count = 0, user_sgpr_count;
431 unsigned i;
432 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
433 unsigned user_sgpr_idx;
434 bool need_push_constants;
435 bool need_ring_offsets = false;
436
437 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
438 if (ctx->stage == MESA_SHADER_GEOMETRY ||
439 ctx->stage == MESA_SHADER_VERTEX ||
440 ctx->is_gs_copy_shader)
441 need_ring_offsets = true;
442
443 need_push_constants = true;
444 if (!ctx->options->layout)
445 need_push_constants = false;
446 else if (!ctx->options->layout->push_constant_size &&
447 !ctx->options->layout->dynamic_offset_count)
448 need_push_constants = false;
449
450 if (need_ring_offsets && !ctx->options->supports_spill) {
451 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
452 }
453
454 /* 1 for each descriptor set */
455 for (unsigned i = 0; i < num_sets; ++i) {
456 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
457 array_params_mask |= (1 << arg_idx);
458 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
459 }
460 }
461
462 if (need_push_constants) {
463 /* 1 for push constants and dynamic descriptors */
464 array_params_mask |= (1 << arg_idx);
465 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
466 }
467
468 switch (ctx->stage) {
469 case MESA_SHADER_COMPUTE:
470 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
471 user_sgpr_count = arg_idx;
472 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
473 arg_types[arg_idx++] = ctx->i32;
474 sgpr_count = arg_idx;
475
476 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
477 break;
478 case MESA_SHADER_VERTEX:
479 if (!ctx->is_gs_copy_shader) {
480 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
481 arg_types[arg_idx++] = ctx->i32; // base vertex
482 arg_types[arg_idx++] = ctx->i32; // start instance
483 arg_types[arg_idx++] = ctx->i32; // draw index
484 }
485 user_sgpr_count = arg_idx;
486 if (ctx->options->key.vs.as_es)
487 arg_types[arg_idx++] = ctx->i32; //es2gs offset
488 sgpr_count = arg_idx;
489 arg_types[arg_idx++] = ctx->i32; // vertex id
490 if (!ctx->is_gs_copy_shader) {
491 arg_types[arg_idx++] = ctx->i32; // rel auto id
492 arg_types[arg_idx++] = ctx->i32; // vs prim id
493 arg_types[arg_idx++] = ctx->i32; // instance id
494 }
495 break;
496 case MESA_SHADER_GEOMETRY:
497 arg_types[arg_idx++] = ctx->i32; // gsvs stride
498 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
499 user_sgpr_count = arg_idx;
500 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
501 arg_types[arg_idx++] = ctx->i32; // wave id
502 sgpr_count = arg_idx;
503 arg_types[arg_idx++] = ctx->i32; // vtx0
504 arg_types[arg_idx++] = ctx->i32; // vtx1
505 arg_types[arg_idx++] = ctx->i32; // prim id
506 arg_types[arg_idx++] = ctx->i32; // vtx2
507 arg_types[arg_idx++] = ctx->i32; // vtx3
508 arg_types[arg_idx++] = ctx->i32; // vtx4
509 arg_types[arg_idx++] = ctx->i32; // vtx5
510 arg_types[arg_idx++] = ctx->i32; // GS instance id
511 break;
512 case MESA_SHADER_FRAGMENT:
513 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
514 user_sgpr_count = arg_idx;
515 arg_types[arg_idx++] = ctx->i32; /* prim mask */
516 sgpr_count = arg_idx;
517 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
518 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
519 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
520 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
521 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
522 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
523 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
524 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
525 arg_types[arg_idx++] = ctx->f32; /* pos x float */
526 arg_types[arg_idx++] = ctx->f32; /* pos y float */
527 arg_types[arg_idx++] = ctx->f32; /* pos z float */
528 arg_types[arg_idx++] = ctx->f32; /* pos w float */
529 arg_types[arg_idx++] = ctx->i32; /* front face */
530 arg_types[arg_idx++] = ctx->i32; /* ancillary */
531 arg_types[arg_idx++] = ctx->f32; /* sample coverage */
532 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
533 break;
534 default:
535 unreachable("Shader stage not implemented");
536 }
537
538 ctx->main_function = create_llvm_function(
539 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
540 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
541 set_llvm_calling_convention(ctx->main_function, ctx->stage);
542
543 ctx->shader_info->num_input_sgprs = 0;
544 ctx->shader_info->num_input_vgprs = 0;
545
546 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
547 for (i = 0; i < user_sgpr_count; i++)
548 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
549
550 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
551 for (; i < sgpr_count; i++)
552 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
553
554 if (ctx->stage != MESA_SHADER_FRAGMENT)
555 for (; i < arg_idx; ++i)
556 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
557
558 arg_idx = 0;
559 user_sgpr_idx = 0;
560
561 if (ctx->options->supports_spill || need_ring_offsets) {
562 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
563 user_sgpr_idx += 2;
564 if (ctx->options->supports_spill) {
565 ctx->ring_offsets = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
566 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
567 NULL, 0, AC_FUNC_ATTR_READNONE);
568 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
569 const_array(ctx->v16i8, 8), "");
570 } else
571 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
572 }
573
574 for (unsigned i = 0; i < num_sets; ++i) {
575 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
576 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
577 user_sgpr_idx += 2;
578 ctx->descriptor_sets[i] =
579 LLVMGetParam(ctx->main_function, arg_idx++);
580 } else
581 ctx->descriptor_sets[i] = NULL;
582 }
583
584 if (need_push_constants) {
585 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
586 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
587 user_sgpr_idx += 2;
588 }
589
590 switch (ctx->stage) {
591 case MESA_SHADER_COMPUTE:
592 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
593 user_sgpr_idx += 3;
594 ctx->num_work_groups =
595 LLVMGetParam(ctx->main_function, arg_idx++);
596 ctx->workgroup_ids =
597 LLVMGetParam(ctx->main_function, arg_idx++);
598 ctx->tg_size =
599 LLVMGetParam(ctx->main_function, arg_idx++);
600 ctx->local_invocation_ids =
601 LLVMGetParam(ctx->main_function, arg_idx++);
602 break;
603 case MESA_SHADER_VERTEX:
604 if (!ctx->is_gs_copy_shader) {
605 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
606 user_sgpr_idx += 2;
607 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
608 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
609 user_sgpr_idx += 3;
610 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
611 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
612 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
613 }
614 if (ctx->options->key.vs.as_es)
615 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
616 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
617 if (!ctx->is_gs_copy_shader) {
618 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
619 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
620 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
621 }
622 break;
623 case MESA_SHADER_GEOMETRY:
624 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
625 user_sgpr_idx += 2;
626 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
627 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
628 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
629 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
630 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
631 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
632 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
633 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
634 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
635 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
636 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
637 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
638 break;
639 case MESA_SHADER_FRAGMENT:
640 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
641 user_sgpr_idx += 2;
642 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
643 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
644 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
645 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
646 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
647 arg_idx++;
648 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
649 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
650 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
651 arg_idx++; /* line stipple */
652 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
653 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
654 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
655 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
656 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
657 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
658 break;
659 default:
660 unreachable("Shader stage not implemented");
661 }
662 }
663
664 static void setup_types(struct nir_to_llvm_context *ctx)
665 {
666 LLVMValueRef args[4];
667
668 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
669 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
670 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
671 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
672 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
673 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
674 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
675 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
676 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
677 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
678 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
679 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
680 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
681 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
682 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
683 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
684
685 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
686 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
687 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
688 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
689
690 args[0] = ctx->f32zero;
691 args[1] = ctx->f32zero;
692 args[2] = ctx->f32zero;
693 args[3] = ctx->f32one;
694 ctx->v4f32empty = LLVMConstVector(args, 4);
695
696 ctx->uniform_md_kind =
697 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
698 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
699
700 args[0] = LLVMConstReal(ctx->f32, 2.5);
701 }
702
703 static int get_llvm_num_components(LLVMValueRef value)
704 {
705 LLVMTypeRef type = LLVMTypeOf(value);
706 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
707 ? LLVMGetVectorSize(type)
708 : 1;
709 return num_components;
710 }
711
712 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
713 LLVMValueRef value,
714 int index)
715 {
716 int count = get_llvm_num_components(value);
717
718 assert(index < count);
719 if (count == 1)
720 return value;
721
722 return LLVMBuildExtractElement(ctx->builder, value,
723 LLVMConstInt(ctx->i32, index, false), "");
724 }
725
726 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
727 LLVMValueRef value, unsigned count)
728 {
729 unsigned num_components = get_llvm_num_components(value);
730 if (count == num_components)
731 return value;
732
733 LLVMValueRef masks[] = {
734 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
735 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
736
737 if (count == 1)
738 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
739 "");
740
741 LLVMValueRef swizzle = LLVMConstVector(masks, count);
742 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
743 }
744
745 static void
746 build_store_values_extended(struct nir_to_llvm_context *ctx,
747 LLVMValueRef *values,
748 unsigned value_count,
749 unsigned value_stride,
750 LLVMValueRef vec)
751 {
752 LLVMBuilderRef builder = ctx->builder;
753 unsigned i;
754
755 if (value_count == 1) {
756 LLVMBuildStore(builder, vec, values[0]);
757 return;
758 }
759
760 for (i = 0; i < value_count; i++) {
761 LLVMValueRef ptr = values[i * value_stride];
762 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
763 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
764 LLVMBuildStore(builder, value, ptr);
765 }
766 }
767
768 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
769 nir_ssa_def *def)
770 {
771 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
772 if (def->num_components > 1) {
773 type = LLVMVectorType(type, def->num_components);
774 }
775 return type;
776 }
777
778 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
779 {
780 assert(src.is_ssa);
781 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
782 return (LLVMValueRef)entry->data;
783 }
784
785
786 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
787 struct nir_block *b)
788 {
789 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
790 return (LLVMBasicBlockRef)entry->data;
791 }
792
793 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
794 nir_alu_src src,
795 unsigned num_components)
796 {
797 LLVMValueRef value = get_src(ctx, src.src);
798 bool need_swizzle = false;
799
800 assert(value);
801 LLVMTypeRef type = LLVMTypeOf(value);
802 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
803 ? LLVMGetVectorSize(type)
804 : 1;
805
806 for (unsigned i = 0; i < num_components; ++i) {
807 assert(src.swizzle[i] < src_components);
808 if (src.swizzle[i] != i)
809 need_swizzle = true;
810 }
811
812 if (need_swizzle || num_components != src_components) {
813 LLVMValueRef masks[] = {
814 LLVMConstInt(ctx->i32, src.swizzle[0], false),
815 LLVMConstInt(ctx->i32, src.swizzle[1], false),
816 LLVMConstInt(ctx->i32, src.swizzle[2], false),
817 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
818
819 if (src_components > 1 && num_components == 1) {
820 value = LLVMBuildExtractElement(ctx->builder, value,
821 masks[0], "");
822 } else if (src_components == 1 && num_components > 1) {
823 LLVMValueRef values[] = {value, value, value, value};
824 value = ac_build_gather_values(&ctx->ac, values, num_components);
825 } else {
826 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
827 value = LLVMBuildShuffleVector(ctx->builder, value, value,
828 swizzle, "");
829 }
830 }
831 assert(!src.negate);
832 assert(!src.abs);
833 return value;
834 }
835
836 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
837 LLVMIntPredicate pred, LLVMValueRef src0,
838 LLVMValueRef src1)
839 {
840 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
841 return LLVMBuildSelect(ctx->builder, result,
842 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
843 LLVMConstInt(ctx->i32, 0, false), "");
844 }
845
846 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
847 LLVMRealPredicate pred, LLVMValueRef src0,
848 LLVMValueRef src1)
849 {
850 LLVMValueRef result;
851 src0 = to_float(ctx, src0);
852 src1 = to_float(ctx, src1);
853 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
854 return LLVMBuildSelect(ctx->builder, result,
855 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
856 LLVMConstInt(ctx->i32, 0, false), "");
857 }
858
859 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
860 const char *intrin,
861 LLVMTypeRef result_type,
862 LLVMValueRef src0)
863 {
864 char name[64];
865 LLVMValueRef params[] = {
866 to_float(ctx, src0),
867 };
868
869 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
870 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
871 }
872
873 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
874 const char *intrin,
875 LLVMTypeRef result_type,
876 LLVMValueRef src0, LLVMValueRef src1)
877 {
878 char name[64];
879 LLVMValueRef params[] = {
880 to_float(ctx, src0),
881 to_float(ctx, src1),
882 };
883
884 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
885 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
886 }
887
888 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
889 const char *intrin,
890 LLVMTypeRef result_type,
891 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
892 {
893 char name[64];
894 LLVMValueRef params[] = {
895 to_float(ctx, src0),
896 to_float(ctx, src1),
897 to_float(ctx, src2),
898 };
899
900 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
901 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
902 }
903
904 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
905 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
906 {
907 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
908 ctx->i32zero, "");
909 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
910 }
911
912 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
913 LLVMValueRef src0)
914 {
915 LLVMValueRef params[2] = {
916 src0,
917
918 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
919 * add special code to check for x=0. The reason is that
920 * the LLVM behavior for x=0 is different from what we
921 * need here.
922 *
923 * The hardware already implements the correct behavior.
924 */
925 LLVMConstInt(ctx->i32, 1, false),
926 };
927 return ac_emit_llvm_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
928 }
929
930 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
931 LLVMValueRef src0)
932 {
933 return ac_emit_imsb(&ctx->ac, src0, ctx->i32);
934 }
935
936 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
937 LLVMValueRef src0)
938 {
939 return ac_emit_umsb(&ctx->ac, src0, ctx->i32);
940 }
941
942 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
943 LLVMIntPredicate pred,
944 LLVMValueRef src0, LLVMValueRef src1)
945 {
946 return LLVMBuildSelect(ctx->builder,
947 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
948 src0,
949 src1, "");
950
951 }
952 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
953 LLVMValueRef src0)
954 {
955 return emit_minmax_int(ctx, LLVMIntSGT, src0,
956 LLVMBuildNeg(ctx->builder, src0, ""));
957 }
958
959 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
960 LLVMValueRef src0)
961 {
962 LLVMValueRef cmp, val;
963
964 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
965 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
966 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
967 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
968 return val;
969 }
970
971 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
972 LLVMValueRef src0)
973 {
974 LLVMValueRef cmp, val;
975
976 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
977 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
978 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
979 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
980 return val;
981 }
982
983 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
984 LLVMValueRef src0)
985 {
986 const char *intr = "llvm.floor.f32";
987 LLVMValueRef fsrc0 = to_float(ctx, src0);
988 LLVMValueRef params[] = {
989 fsrc0,
990 };
991 LLVMValueRef floor = ac_emit_llvm_intrinsic(&ctx->ac, intr,
992 ctx->f32, params, 1,
993 AC_FUNC_ATTR_READNONE);
994 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
995 }
996
997 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
998 const char *intrin,
999 LLVMValueRef src0, LLVMValueRef src1)
1000 {
1001 LLVMTypeRef ret_type;
1002 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1003 LLVMValueRef res;
1004 LLVMValueRef params[] = { src0, src1 };
1005 ret_type = LLVMStructTypeInContext(ctx->context, types,
1006 2, true);
1007
1008 res = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ret_type,
1009 params, 2, AC_FUNC_ATTR_READNONE);
1010
1011 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1012 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1013 return res;
1014 }
1015
1016 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1017 LLVMValueRef src0)
1018 {
1019 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1020 }
1021
1022 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1023 LLVMValueRef src0, LLVMValueRef src1)
1024 {
1025 LLVMValueRef dst64, result;
1026 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1027 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1028
1029 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1030 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1031 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1032 return result;
1033 }
1034
1035 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1036 LLVMValueRef src0, LLVMValueRef src1)
1037 {
1038 LLVMValueRef dst64, result;
1039 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1040 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1041
1042 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1043 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1044 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1045 return result;
1046 }
1047
1048 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1049 const char *intrin,
1050 LLVMValueRef srcs[3])
1051 {
1052 LLVMValueRef result;
1053 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1054 result = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->i32, srcs, 3, AC_FUNC_ATTR_READNONE);
1055
1056 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1057 return result;
1058 }
1059
1060 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1061 LLVMValueRef src0, LLVMValueRef src1,
1062 LLVMValueRef src2, LLVMValueRef src3)
1063 {
1064 LLVMValueRef bfi_args[3], result;
1065
1066 bfi_args[0] = LLVMBuildShl(ctx->builder,
1067 LLVMBuildSub(ctx->builder,
1068 LLVMBuildShl(ctx->builder,
1069 ctx->i32one,
1070 src3, ""),
1071 ctx->i32one, ""),
1072 src2, "");
1073 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1074 bfi_args[2] = src0;
1075
1076 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1077
1078 /* Calculate:
1079 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1080 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1081 */
1082 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1083 LLVMBuildAnd(ctx->builder, bfi_args[0],
1084 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1085
1086 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1087 return result;
1088 }
1089
1090 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1091 LLVMValueRef src0)
1092 {
1093 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1094 int i;
1095 LLVMValueRef comp[2];
1096
1097 src0 = to_float(ctx, src0);
1098 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1099 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1100 for (i = 0; i < 2; i++) {
1101 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1102 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1103 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1104 }
1105
1106 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1107 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1108
1109 return comp[0];
1110 }
1111
1112 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1113 LLVMValueRef src0)
1114 {
1115 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1116 LLVMValueRef temps[2], result, val;
1117 int i;
1118
1119 for (i = 0; i < 2; i++) {
1120 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1121 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1122 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1123 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1124 }
1125
1126 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1127 ctx->i32zero, "");
1128 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1129 ctx->i32one, "");
1130 return result;
1131 }
1132
1133 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1134 nir_op op,
1135 LLVMValueRef src0)
1136 {
1137 unsigned mask;
1138 int idx;
1139 LLVMValueRef result;
1140 ctx->has_ddxy = true;
1141
1142 if (!ctx->lds && !ctx->has_ds_bpermute)
1143 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1144 LLVMArrayType(ctx->i32, 64),
1145 "ddxy_lds", LOCAL_ADDR_SPACE);
1146
1147 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1148 mask = AC_TID_MASK_LEFT;
1149 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1150 mask = AC_TID_MASK_TOP;
1151 else
1152 mask = AC_TID_MASK_TOP_LEFT;
1153
1154 /* for DDX we want to next X pixel, DDY next Y pixel. */
1155 if (op == nir_op_fddx_fine ||
1156 op == nir_op_fddx_coarse ||
1157 op == nir_op_fddx)
1158 idx = 1;
1159 else
1160 idx = 2;
1161
1162 result = ac_emit_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1163 mask, idx, ctx->lds,
1164 src0);
1165 return result;
1166 }
1167
1168 /*
1169 * this takes an I,J coordinate pair,
1170 * and works out the X and Y derivatives.
1171 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1172 */
1173 static LLVMValueRef emit_ddxy_interp(
1174 struct nir_to_llvm_context *ctx,
1175 LLVMValueRef interp_ij)
1176 {
1177 LLVMValueRef result[4], a;
1178 unsigned i;
1179
1180 for (i = 0; i < 2; i++) {
1181 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1182 LLVMConstInt(ctx->i32, i, false), "");
1183 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1184 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1185 }
1186 return ac_build_gather_values(&ctx->ac, result, 4);
1187 }
1188
1189 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1190 {
1191 LLVMValueRef src[4], result = NULL;
1192 unsigned num_components = instr->dest.dest.ssa.num_components;
1193 unsigned src_components;
1194 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1195
1196 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1197 switch (instr->op) {
1198 case nir_op_vec2:
1199 case nir_op_vec3:
1200 case nir_op_vec4:
1201 src_components = 1;
1202 break;
1203 case nir_op_pack_half_2x16:
1204 src_components = 2;
1205 break;
1206 case nir_op_unpack_half_2x16:
1207 src_components = 1;
1208 break;
1209 default:
1210 src_components = num_components;
1211 break;
1212 }
1213 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1214 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1215
1216 switch (instr->op) {
1217 case nir_op_fmov:
1218 case nir_op_imov:
1219 result = src[0];
1220 break;
1221 case nir_op_fneg:
1222 src[0] = to_float(ctx, src[0]);
1223 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1224 break;
1225 case nir_op_ineg:
1226 result = LLVMBuildNeg(ctx->builder, src[0], "");
1227 break;
1228 case nir_op_inot:
1229 result = LLVMBuildNot(ctx->builder, src[0], "");
1230 break;
1231 case nir_op_iadd:
1232 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1233 break;
1234 case nir_op_fadd:
1235 src[0] = to_float(ctx, src[0]);
1236 src[1] = to_float(ctx, src[1]);
1237 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1238 break;
1239 case nir_op_fsub:
1240 src[0] = to_float(ctx, src[0]);
1241 src[1] = to_float(ctx, src[1]);
1242 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1243 break;
1244 case nir_op_isub:
1245 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1246 break;
1247 case nir_op_imul:
1248 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1249 break;
1250 case nir_op_imod:
1251 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1252 break;
1253 case nir_op_umod:
1254 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1255 break;
1256 case nir_op_fmod:
1257 src[0] = to_float(ctx, src[0]);
1258 src[1] = to_float(ctx, src[1]);
1259 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1260 result = emit_intrin_1f_param(ctx, "llvm.floor",
1261 to_float_type(ctx, def_type), result);
1262 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1263 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1264 break;
1265 case nir_op_frem:
1266 src[0] = to_float(ctx, src[0]);
1267 src[1] = to_float(ctx, src[1]);
1268 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1269 break;
1270 case nir_op_irem:
1271 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1272 break;
1273 case nir_op_idiv:
1274 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1275 break;
1276 case nir_op_udiv:
1277 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1278 break;
1279 case nir_op_fmul:
1280 src[0] = to_float(ctx, src[0]);
1281 src[1] = to_float(ctx, src[1]);
1282 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1283 break;
1284 case nir_op_fdiv:
1285 src[0] = to_float(ctx, src[0]);
1286 src[1] = to_float(ctx, src[1]);
1287 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1288 break;
1289 case nir_op_frcp:
1290 src[0] = to_float(ctx, src[0]);
1291 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, src[0]);
1292 break;
1293 case nir_op_iand:
1294 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1295 break;
1296 case nir_op_ior:
1297 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1298 break;
1299 case nir_op_ixor:
1300 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1301 break;
1302 case nir_op_ishl:
1303 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1304 break;
1305 case nir_op_ishr:
1306 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1307 break;
1308 case nir_op_ushr:
1309 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1310 break;
1311 case nir_op_ilt:
1312 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1313 break;
1314 case nir_op_ine:
1315 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1316 break;
1317 case nir_op_ieq:
1318 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1319 break;
1320 case nir_op_ige:
1321 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1322 break;
1323 case nir_op_ult:
1324 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1325 break;
1326 case nir_op_uge:
1327 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1328 break;
1329 case nir_op_feq:
1330 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1331 break;
1332 case nir_op_fne:
1333 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1334 break;
1335 case nir_op_flt:
1336 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1337 break;
1338 case nir_op_fge:
1339 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1340 break;
1341 case nir_op_fabs:
1342 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1343 to_float_type(ctx, def_type), src[0]);
1344 break;
1345 case nir_op_iabs:
1346 result = emit_iabs(ctx, src[0]);
1347 break;
1348 case nir_op_imax:
1349 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1350 break;
1351 case nir_op_imin:
1352 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1353 break;
1354 case nir_op_umax:
1355 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1356 break;
1357 case nir_op_umin:
1358 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1359 break;
1360 case nir_op_isign:
1361 result = emit_isign(ctx, src[0]);
1362 break;
1363 case nir_op_fsign:
1364 src[0] = to_float(ctx, src[0]);
1365 result = emit_fsign(ctx, src[0]);
1366 break;
1367 case nir_op_ffloor:
1368 result = emit_intrin_1f_param(ctx, "llvm.floor",
1369 to_float_type(ctx, def_type), src[0]);
1370 break;
1371 case nir_op_ftrunc:
1372 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1373 to_float_type(ctx, def_type), src[0]);
1374 break;
1375 case nir_op_fceil:
1376 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1377 to_float_type(ctx, def_type), src[0]);
1378 break;
1379 case nir_op_fround_even:
1380 result = emit_intrin_1f_param(ctx, "llvm.rint",
1381 to_float_type(ctx, def_type),src[0]);
1382 break;
1383 case nir_op_ffract:
1384 result = emit_ffract(ctx, src[0]);
1385 break;
1386 case nir_op_fsin:
1387 result = emit_intrin_1f_param(ctx, "llvm.sin",
1388 to_float_type(ctx, def_type), src[0]);
1389 break;
1390 case nir_op_fcos:
1391 result = emit_intrin_1f_param(ctx, "llvm.cos",
1392 to_float_type(ctx, def_type), src[0]);
1393 break;
1394 case nir_op_fsqrt:
1395 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1396 to_float_type(ctx, def_type), src[0]);
1397 break;
1398 case nir_op_fexp2:
1399 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1400 to_float_type(ctx, def_type), src[0]);
1401 break;
1402 case nir_op_flog2:
1403 result = emit_intrin_1f_param(ctx, "llvm.log2",
1404 to_float_type(ctx, def_type), src[0]);
1405 break;
1406 case nir_op_frsq:
1407 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1408 to_float_type(ctx, def_type), src[0]);
1409 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, result);
1410 break;
1411 case nir_op_fpow:
1412 result = emit_intrin_2f_param(ctx, "llvm.pow",
1413 to_float_type(ctx, def_type), src[0], src[1]);
1414 break;
1415 case nir_op_fmax:
1416 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1417 to_float_type(ctx, def_type), src[0], src[1]);
1418 break;
1419 case nir_op_fmin:
1420 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1421 to_float_type(ctx, def_type), src[0], src[1]);
1422 break;
1423 case nir_op_ffma:
1424 result = emit_intrin_3f_param(ctx, "llvm.fma",
1425 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1426 break;
1427 case nir_op_ibitfield_extract:
1428 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.i32", src);
1429 break;
1430 case nir_op_ubitfield_extract:
1431 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.u32", src);
1432 break;
1433 case nir_op_bitfield_insert:
1434 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1435 break;
1436 case nir_op_bitfield_reverse:
1437 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1438 break;
1439 case nir_op_bit_count:
1440 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1441 break;
1442 case nir_op_vec2:
1443 case nir_op_vec3:
1444 case nir_op_vec4:
1445 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1446 src[i] = to_integer(ctx, src[i]);
1447 result = ac_build_gather_values(&ctx->ac, src, num_components);
1448 break;
1449 case nir_op_d2i:
1450 case nir_op_f2i:
1451 src[0] = to_float(ctx, src[0]);
1452 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1453 break;
1454 case nir_op_d2u:
1455 case nir_op_f2u:
1456 src[0] = to_float(ctx, src[0]);
1457 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1458 break;
1459 case nir_op_i2d:
1460 case nir_op_i2f:
1461 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1462 break;
1463 case nir_op_u2d:
1464 case nir_op_u2f:
1465 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1466 break;
1467 case nir_op_f2d:
1468 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1469 break;
1470 case nir_op_d2f:
1471 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1472 break;
1473 case nir_op_bcsel:
1474 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1475 break;
1476 case nir_op_find_lsb:
1477 result = emit_find_lsb(ctx, src[0]);
1478 break;
1479 case nir_op_ufind_msb:
1480 result = emit_ufind_msb(ctx, src[0]);
1481 break;
1482 case nir_op_ifind_msb:
1483 result = emit_ifind_msb(ctx, src[0]);
1484 break;
1485 case nir_op_uadd_carry:
1486 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1487 break;
1488 case nir_op_usub_borrow:
1489 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1490 break;
1491 case nir_op_b2f:
1492 result = emit_b2f(ctx, src[0]);
1493 break;
1494 case nir_op_fquantize2f16:
1495 src[0] = to_float(ctx, src[0]);
1496 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1497 /* need to convert back up to f32 */
1498 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1499 break;
1500 case nir_op_umul_high:
1501 result = emit_umul_high(ctx, src[0], src[1]);
1502 break;
1503 case nir_op_imul_high:
1504 result = emit_imul_high(ctx, src[0], src[1]);
1505 break;
1506 case nir_op_pack_half_2x16:
1507 result = emit_pack_half_2x16(ctx, src[0]);
1508 break;
1509 case nir_op_unpack_half_2x16:
1510 result = emit_unpack_half_2x16(ctx, src[0]);
1511 break;
1512 case nir_op_fddx:
1513 case nir_op_fddy:
1514 case nir_op_fddx_fine:
1515 case nir_op_fddy_fine:
1516 case nir_op_fddx_coarse:
1517 case nir_op_fddy_coarse:
1518 result = emit_ddxy(ctx, instr->op, src[0]);
1519 break;
1520 default:
1521 fprintf(stderr, "Unknown NIR alu instr: ");
1522 nir_print_instr(&instr->instr, stderr);
1523 fprintf(stderr, "\n");
1524 abort();
1525 }
1526
1527 if (result) {
1528 assert(instr->dest.dest.is_ssa);
1529 result = to_integer(ctx, result);
1530 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1531 result);
1532 }
1533 }
1534
1535 static void visit_load_const(struct nir_to_llvm_context *ctx,
1536 nir_load_const_instr *instr)
1537 {
1538 LLVMValueRef values[4], value = NULL;
1539 LLVMTypeRef element_type =
1540 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1541
1542 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1543 switch (instr->def.bit_size) {
1544 case 32:
1545 values[i] = LLVMConstInt(element_type,
1546 instr->value.u32[i], false);
1547 break;
1548 case 64:
1549 values[i] = LLVMConstInt(element_type,
1550 instr->value.u64[i], false);
1551 break;
1552 default:
1553 fprintf(stderr,
1554 "unsupported nir load_const bit_size: %d\n",
1555 instr->def.bit_size);
1556 abort();
1557 }
1558 }
1559 if (instr->def.num_components > 1) {
1560 value = LLVMConstVector(values, instr->def.num_components);
1561 } else
1562 value = values[0];
1563
1564 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1565 }
1566
1567 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1568 LLVMTypeRef type)
1569 {
1570 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1571 return LLVMBuildBitCast(ctx->builder, ptr,
1572 LLVMPointerType(type, addr_space), "");
1573 }
1574
1575 static LLVMValueRef
1576 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1577 {
1578 LLVMValueRef size =
1579 LLVMBuildExtractElement(ctx->builder, descriptor,
1580 LLVMConstInt(ctx->i32, 2, false), "");
1581
1582 /* VI only */
1583 if (ctx->options->chip_class >= VI && in_elements) {
1584 /* On VI, the descriptor contains the size in bytes,
1585 * but TXQ must return the size in elements.
1586 * The stride is always non-zero for resources using TXQ.
1587 */
1588 LLVMValueRef stride =
1589 LLVMBuildExtractElement(ctx->builder, descriptor,
1590 LLVMConstInt(ctx->i32, 1, false), "");
1591 stride = LLVMBuildLShr(ctx->builder, stride,
1592 LLVMConstInt(ctx->i32, 16, false), "");
1593 stride = LLVMBuildAnd(ctx->builder, stride,
1594 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1595
1596 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1597 }
1598 return size;
1599 }
1600
1601 /**
1602 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1603 * intrinsic names).
1604 */
1605 static void build_int_type_name(
1606 LLVMTypeRef type,
1607 char *buf, unsigned bufsize)
1608 {
1609 assert(bufsize >= 6);
1610
1611 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1612 snprintf(buf, bufsize, "v%ui32",
1613 LLVMGetVectorSize(type));
1614 else
1615 strcpy(buf, "i32");
1616 }
1617
1618 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1619 struct ac_tex_info *tinfo,
1620 nir_tex_instr *instr,
1621 const char *intr_name,
1622 unsigned coord_vgpr_index)
1623 {
1624 LLVMValueRef coord = tinfo->args[0];
1625 LLVMValueRef half_texel[2];
1626 int c;
1627
1628 //TODO Rect
1629 {
1630 LLVMValueRef txq_args[10];
1631 int txq_arg_count = 0;
1632 LLVMValueRef size;
1633 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1634 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, false);
1635 txq_args[txq_arg_count++] = tinfo->args[1];
1636 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0xf, 0); /* dmask */
1637 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* unorm */
1638 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
1639 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
1640 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
1641 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
1642 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
1643 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
1644 size = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
1645 txq_args, txq_arg_count,
1646 AC_FUNC_ATTR_READNONE);
1647
1648 for (c = 0; c < 2; c++) {
1649 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1650 LLVMConstInt(ctx->i32, c, false), "");
1651 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1652 half_texel[c] = ac_emit_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1653 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1654 LLVMConstReal(ctx->f32, -0.5), "");
1655 }
1656 }
1657
1658 for (c = 0; c < 2; c++) {
1659 LLVMValueRef tmp;
1660 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1661 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1662 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1663 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1664 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1665 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1666 }
1667
1668 tinfo->args[0] = coord;
1669 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1670 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1671
1672 }
1673
1674 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1675 nir_tex_instr *instr,
1676 struct ac_tex_info *tinfo)
1677 {
1678 const char *name = "llvm.SI.image.sample";
1679 const char *infix = "";
1680 char intr_name[127];
1681 char type[64];
1682 bool is_shadow = instr->is_shadow;
1683 bool has_offset = tinfo->has_offset;
1684 switch (instr->op) {
1685 case nir_texop_txf:
1686 case nir_texop_txf_ms:
1687 case nir_texop_samples_identical:
1688 name = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? "llvm.SI.image.load" :
1689 instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? "llvm.SI.vs.load.input" :
1690 "llvm.SI.image.load.mip";
1691 is_shadow = false;
1692 has_offset = false;
1693 break;
1694 case nir_texop_txb:
1695 infix = ".b";
1696 break;
1697 case nir_texop_txl:
1698 infix = ".l";
1699 break;
1700 case nir_texop_txs:
1701 name = "llvm.SI.getresinfo";
1702 break;
1703 case nir_texop_query_levels:
1704 name = "llvm.SI.getresinfo";
1705 break;
1706 case nir_texop_tex:
1707 if (ctx->stage != MESA_SHADER_FRAGMENT)
1708 infix = ".lz";
1709 break;
1710 case nir_texop_txd:
1711 infix = ".d";
1712 break;
1713 case nir_texop_tg4:
1714 name = "llvm.SI.gather4";
1715 infix = ".lz";
1716 break;
1717 case nir_texop_lod:
1718 name = "llvm.SI.getlod";
1719 is_shadow = false;
1720 has_offset = false;
1721 break;
1722 default:
1723 break;
1724 }
1725
1726 build_int_type_name(LLVMTypeOf(tinfo->args[0]), type, sizeof(type));
1727 sprintf(intr_name, "%s%s%s%s.%s", name, is_shadow ? ".c" : "", infix,
1728 has_offset ? ".o" : "", type);
1729
1730 if (instr->op == nir_texop_tg4) {
1731 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1732 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1733 return radv_lower_gather4_integer(ctx, tinfo, instr, intr_name,
1734 (int)has_offset + (int)is_shadow);
1735 }
1736 }
1737 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1738 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1739
1740 }
1741
1742 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1743 nir_intrinsic_instr *instr)
1744 {
1745 LLVMValueRef index = get_src(ctx, instr->src[0]);
1746 unsigned desc_set = nir_intrinsic_desc_set(instr);
1747 unsigned binding = nir_intrinsic_binding(instr);
1748 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1749 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
1750 unsigned base_offset = layout->binding[binding].offset;
1751 LLVMValueRef offset, stride;
1752
1753 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1754 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1755 desc_ptr = ctx->push_constants;
1756 base_offset = ctx->options->layout->push_constant_size;
1757 base_offset += 16 * layout->binding[binding].dynamic_offset_offset;
1758 stride = LLVMConstInt(ctx->i32, 16, false);
1759 } else
1760 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1761
1762 offset = LLVMConstInt(ctx->i32, base_offset, false);
1763 index = LLVMBuildMul(ctx->builder, index, stride, "");
1764 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1765
1766 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1767 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1768 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1769
1770 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1771 }
1772
1773 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1774 nir_intrinsic_instr *instr)
1775 {
1776 LLVMValueRef ptr, addr;
1777
1778 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1779 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1780
1781 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
1782 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1783
1784 return LLVMBuildLoad(ctx->builder, ptr, "");
1785 }
1786
1787 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1788 nir_intrinsic_instr *instr)
1789 {
1790 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1791
1792 return get_buffer_size(ctx, desc, false);
1793 }
1794 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1795 nir_intrinsic_instr *instr)
1796 {
1797 const char *store_name;
1798 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
1799 LLVMTypeRef data_type = ctx->f32;
1800 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
1801 int components_32bit = elem_size_mult * instr->num_components;
1802 unsigned writemask = nir_intrinsic_write_mask(instr);
1803 LLVMValueRef base_data, base_offset;
1804 LLVMValueRef params[6];
1805
1806 if (ctx->stage == MESA_SHADER_FRAGMENT)
1807 ctx->shader_info->fs.writes_memory = true;
1808
1809 params[1] = get_src(ctx, instr->src[1]);
1810 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1811 params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
1812 params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1813
1814 if (components_32bit > 1)
1815 data_type = LLVMVectorType(ctx->f32, components_32bit);
1816
1817 base_data = to_float(ctx, src_data);
1818 base_data = trim_vector(ctx, base_data, instr->num_components);
1819 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1820 data_type, "");
1821 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1822 while (writemask) {
1823 int start, count;
1824 LLVMValueRef data;
1825 LLVMValueRef offset;
1826 LLVMValueRef tmp;
1827 u_bit_scan_consecutive_range(&writemask, &start, &count);
1828
1829 /* Due to an LLVM limitation, split 3-element writes
1830 * into a 2-element and a 1-element write. */
1831 if (count == 3) {
1832 writemask |= 1 << (start + 2);
1833 count = 2;
1834 }
1835
1836 start *= elem_size_mult;
1837 count *= elem_size_mult;
1838
1839 if (count > 4) {
1840 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
1841 count = 4;
1842 }
1843
1844 if (count == 4) {
1845 store_name = "llvm.amdgcn.buffer.store.v4f32";
1846 data = base_data;
1847 } else if (count == 2) {
1848 tmp = LLVMBuildExtractElement(ctx->builder,
1849 base_data, LLVMConstInt(ctx->i32, start, false), "");
1850 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
1851 ctx->i32zero, "");
1852
1853 tmp = LLVMBuildExtractElement(ctx->builder,
1854 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
1855 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
1856 ctx->i32one, "");
1857 store_name = "llvm.amdgcn.buffer.store.v2f32";
1858
1859 } else {
1860 assert(count == 1);
1861 if (get_llvm_num_components(base_data) > 1)
1862 data = LLVMBuildExtractElement(ctx->builder, base_data,
1863 LLVMConstInt(ctx->i32, start, false), "");
1864 else
1865 data = base_data;
1866 store_name = "llvm.amdgcn.buffer.store.f32";
1867 }
1868
1869 offset = base_offset;
1870 if (start != 0) {
1871 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
1872 }
1873 params[0] = data;
1874 params[3] = offset;
1875 ac_emit_llvm_intrinsic(&ctx->ac, store_name,
1876 ctx->voidt, params, 6, 0);
1877 }
1878 }
1879
1880 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
1881 nir_intrinsic_instr *instr)
1882 {
1883 const char *name;
1884 LLVMValueRef params[6];
1885 int arg_count = 0;
1886 if (ctx->stage == MESA_SHADER_FRAGMENT)
1887 ctx->shader_info->fs.writes_memory = true;
1888
1889 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
1890 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
1891 }
1892 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
1893 params[arg_count++] = get_src(ctx, instr->src[0]);
1894 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1895 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
1896 params[arg_count++] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1897
1898 switch (instr->intrinsic) {
1899 case nir_intrinsic_ssbo_atomic_add:
1900 name = "llvm.amdgcn.buffer.atomic.add";
1901 break;
1902 case nir_intrinsic_ssbo_atomic_imin:
1903 name = "llvm.amdgcn.buffer.atomic.smin";
1904 break;
1905 case nir_intrinsic_ssbo_atomic_umin:
1906 name = "llvm.amdgcn.buffer.atomic.umin";
1907 break;
1908 case nir_intrinsic_ssbo_atomic_imax:
1909 name = "llvm.amdgcn.buffer.atomic.smax";
1910 break;
1911 case nir_intrinsic_ssbo_atomic_umax:
1912 name = "llvm.amdgcn.buffer.atomic.umax";
1913 break;
1914 case nir_intrinsic_ssbo_atomic_and:
1915 name = "llvm.amdgcn.buffer.atomic.and";
1916 break;
1917 case nir_intrinsic_ssbo_atomic_or:
1918 name = "llvm.amdgcn.buffer.atomic.or";
1919 break;
1920 case nir_intrinsic_ssbo_atomic_xor:
1921 name = "llvm.amdgcn.buffer.atomic.xor";
1922 break;
1923 case nir_intrinsic_ssbo_atomic_exchange:
1924 name = "llvm.amdgcn.buffer.atomic.swap";
1925 break;
1926 case nir_intrinsic_ssbo_atomic_comp_swap:
1927 name = "llvm.amdgcn.buffer.atomic.cmpswap";
1928 break;
1929 default:
1930 abort();
1931 }
1932
1933 return ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
1934 }
1935
1936 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
1937 nir_intrinsic_instr *instr)
1938 {
1939 LLVMValueRef results[2];
1940 int load_components;
1941 int num_components = instr->num_components;
1942 if (instr->dest.ssa.bit_size == 64)
1943 num_components *= 2;
1944
1945 for (int i = 0; i < num_components; i += load_components) {
1946 load_components = MIN2(num_components - i, 4);
1947 const char *load_name;
1948 LLVMTypeRef data_type = ctx->f32;
1949 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
1950 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
1951
1952 if (load_components == 3)
1953 data_type = LLVMVectorType(ctx->f32, 4);
1954 else if (load_components > 1)
1955 data_type = LLVMVectorType(ctx->f32, load_components);
1956
1957 if (load_components >= 3)
1958 load_name = "llvm.amdgcn.buffer.load.v4f32";
1959 else if (load_components == 2)
1960 load_name = "llvm.amdgcn.buffer.load.v2f32";
1961 else if (load_components == 1)
1962 load_name = "llvm.amdgcn.buffer.load.f32";
1963 else
1964 unreachable("unhandled number of components");
1965
1966 LLVMValueRef params[] = {
1967 get_src(ctx, instr->src[0]),
1968 LLVMConstInt(ctx->i32, 0, false),
1969 offset,
1970 LLVMConstInt(ctx->i1, 0, false),
1971 LLVMConstInt(ctx->i1, 0, false),
1972 };
1973
1974 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
1975
1976 }
1977
1978 LLVMValueRef ret = results[0];
1979 if (num_components > 4 || num_components == 3) {
1980 LLVMValueRef masks[] = {
1981 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1982 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
1983 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
1984 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
1985 };
1986
1987 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1988 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
1989 results[num_components > 4 ? 1 : 0], swizzle, "");
1990 }
1991
1992 return LLVMBuildBitCast(ctx->builder, ret,
1993 get_def_type(ctx, &instr->dest.ssa), "");
1994 }
1995
1996 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
1997 nir_intrinsic_instr *instr)
1998 {
1999 LLVMValueRef results[8], ret;
2000 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2001 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2002 int num_components = instr->num_components;
2003
2004 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2005
2006 if (instr->dest.ssa.bit_size == 64)
2007 num_components *= 2;
2008
2009 for (unsigned i = 0; i < num_components; ++i) {
2010 LLVMValueRef params[] = {
2011 rsrc,
2012 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2013 offset, "")
2014 };
2015 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2016 params, 2, AC_FUNC_ATTR_READNONE);
2017 }
2018
2019
2020 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2021 return LLVMBuildBitCast(ctx->builder, ret,
2022 get_def_type(ctx, &instr->dest.ssa), "");
2023 }
2024
2025 static void
2026 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2027 bool vs_in, unsigned *vertex_index_out,
2028 unsigned *const_out, LLVMValueRef *indir_out)
2029 {
2030 unsigned const_offset = 0;
2031 LLVMValueRef offset = NULL;
2032
2033 if (vertex_index_out != NULL) {
2034 tail = tail->child;
2035 nir_deref_array *deref_array = nir_deref_as_array(tail);
2036 *vertex_index_out = deref_array->base_offset;
2037 }
2038
2039 while (tail->child != NULL) {
2040 const struct glsl_type *parent_type = tail->type;
2041 tail = tail->child;
2042
2043 if (tail->deref_type == nir_deref_type_array) {
2044 nir_deref_array *deref_array = nir_deref_as_array(tail);
2045 LLVMValueRef index, stride, local_offset;
2046 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2047
2048 const_offset += size * deref_array->base_offset;
2049 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2050 continue;
2051
2052 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2053 index = get_src(ctx, deref_array->indirect);
2054 stride = LLVMConstInt(ctx->i32, size, 0);
2055 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2056
2057 if (offset)
2058 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2059 else
2060 offset = local_offset;
2061 } else if (tail->deref_type == nir_deref_type_struct) {
2062 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2063
2064 for (unsigned i = 0; i < deref_struct->index; i++) {
2065 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2066 const_offset += glsl_count_attribute_slots(ft, vs_in);
2067 }
2068 } else
2069 unreachable("unsupported deref type");
2070
2071 }
2072
2073 if (const_offset && offset)
2074 offset = LLVMBuildAdd(ctx->builder, offset,
2075 LLVMConstInt(ctx->i32, const_offset, 0),
2076 "");
2077
2078 *const_out = const_offset;
2079 *indir_out = offset;
2080 }
2081
2082 static LLVMValueRef
2083 load_gs_input(struct nir_to_llvm_context *ctx,
2084 nir_intrinsic_instr *instr)
2085 {
2086 LLVMValueRef indir_index, vtx_offset;
2087 unsigned const_index;
2088 LLVMValueRef args[9];
2089 unsigned param, vtx_offset_param;
2090 LLVMValueRef value[4], result;
2091 unsigned vertex_index;
2092 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2093 false, &vertex_index,
2094 &const_index, &indir_index);
2095 vtx_offset_param = vertex_index;
2096 assert(vtx_offset_param < 6);
2097 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2098 LLVMConstInt(ctx->i32, 4, false), "");
2099
2100 for (unsigned i = 0; i < instr->num_components; i++) {
2101 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2102 args[0] = ctx->esgs_ring;
2103 args[1] = vtx_offset;
2104 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2105 args[3] = ctx->i32zero;
2106 args[4] = ctx->i32one; /* OFFEN */
2107 args[5] = ctx->i32zero; /* IDXEN */
2108 args[6] = ctx->i32one; /* GLC */
2109 args[7] = ctx->i32zero; /* SLC */
2110 args[8] = ctx->i32zero; /* TFE */
2111
2112 value[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2113 ctx->i32, args, 9, AC_FUNC_ATTR_READONLY);
2114 }
2115 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2116
2117 return result;
2118 }
2119
2120 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2121 nir_intrinsic_instr *instr)
2122 {
2123 LLVMValueRef values[8];
2124 int idx = instr->variables[0]->var->data.driver_location;
2125 int ve = instr->dest.ssa.num_components;
2126 LLVMValueRef indir_index;
2127 LLVMValueRef ret;
2128 unsigned const_index;
2129 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2130 instr->variables[0]->var->data.mode == nir_var_shader_in;
2131 radv_get_deref_offset(ctx, &instr->variables[0]->deref, vs_in, NULL,
2132 &const_index, &indir_index);
2133
2134 if (instr->dest.ssa.bit_size == 64)
2135 ve *= 2;
2136
2137 switch (instr->variables[0]->var->data.mode) {
2138 case nir_var_shader_in:
2139 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2140 return load_gs_input(ctx, instr);
2141 }
2142 for (unsigned chan = 0; chan < ve; chan++) {
2143 if (indir_index) {
2144 unsigned count = glsl_count_attribute_slots(
2145 instr->variables[0]->var->type,
2146 ctx->stage == MESA_SHADER_VERTEX);
2147 count -= chan / 4;
2148 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2149 &ctx->ac, ctx->inputs + idx + chan, count,
2150 4, false);
2151
2152 values[chan] = LLVMBuildExtractElement(ctx->builder,
2153 tmp_vec,
2154 indir_index, "");
2155 } else
2156 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2157 }
2158 break;
2159 case nir_var_local:
2160 for (unsigned chan = 0; chan < ve; chan++) {
2161 if (indir_index) {
2162 unsigned count = glsl_count_attribute_slots(
2163 instr->variables[0]->var->type, false);
2164 count -= chan / 4;
2165 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2166 &ctx->ac, ctx->locals + idx + chan, count,
2167 4, true);
2168
2169 values[chan] = LLVMBuildExtractElement(ctx->builder,
2170 tmp_vec,
2171 indir_index, "");
2172 } else {
2173 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2174 }
2175 }
2176 break;
2177 case nir_var_shader_out:
2178 for (unsigned chan = 0; chan < ve; chan++) {
2179 if (indir_index) {
2180 unsigned count = glsl_count_attribute_slots(
2181 instr->variables[0]->var->type, false);
2182 count -= chan / 4;
2183 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2184 &ctx->ac, ctx->outputs + idx + chan, count,
2185 4, true);
2186
2187 values[chan] = LLVMBuildExtractElement(ctx->builder,
2188 tmp_vec,
2189 indir_index, "");
2190 } else {
2191 values[chan] = LLVMBuildLoad(ctx->builder,
2192 ctx->outputs[idx + chan + const_index * 4],
2193 "");
2194 }
2195 }
2196 break;
2197 case nir_var_shared: {
2198 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2199 LLVMValueRef derived_ptr;
2200
2201 if (indir_index)
2202 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2203
2204 for (unsigned chan = 0; chan < ve; chan++) {
2205 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2206 if (indir_index)
2207 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2208 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2209
2210 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2211 }
2212 break;
2213 }
2214 default:
2215 unreachable("unhandle variable mode");
2216 }
2217 ret = ac_build_gather_values(&ctx->ac, values, ve);
2218 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2219 }
2220
2221 static void
2222 visit_store_var(struct nir_to_llvm_context *ctx,
2223 nir_intrinsic_instr *instr)
2224 {
2225 LLVMValueRef temp_ptr, value;
2226 int idx = instr->variables[0]->var->data.driver_location;
2227 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2228 int writemask = instr->const_index[0];
2229 LLVMValueRef indir_index;
2230 unsigned const_index;
2231 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2232 NULL, &const_index, &indir_index);
2233
2234 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2235 int old_writemask = writemask;
2236
2237 src = LLVMBuildBitCast(ctx->builder, src,
2238 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2239 "");
2240
2241 writemask = 0;
2242 for (unsigned chan = 0; chan < 4; chan++) {
2243 if (old_writemask & (1 << chan))
2244 writemask |= 3u << (2 * chan);
2245 }
2246 }
2247
2248 switch (instr->variables[0]->var->data.mode) {
2249 case nir_var_shader_out:
2250 for (unsigned chan = 0; chan < 8; chan++) {
2251 int stride = 4;
2252 if (!(writemask & (1 << chan)))
2253 continue;
2254
2255 value = llvm_extract_elem(ctx, src, chan);
2256
2257 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2258 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2259 stride = 1;
2260 if (indir_index) {
2261 unsigned count = glsl_count_attribute_slots(
2262 instr->variables[0]->var->type, false);
2263 count -= chan / 4;
2264 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2265 &ctx->ac, ctx->outputs + idx + chan, count,
2266 stride, true);
2267
2268 if (get_llvm_num_components(tmp_vec) > 1) {
2269 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2270 value, indir_index, "");
2271 } else
2272 tmp_vec = value;
2273 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2274 count, stride, tmp_vec);
2275
2276 } else {
2277 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2278
2279 LLVMBuildStore(ctx->builder, value, temp_ptr);
2280 }
2281 }
2282 break;
2283 case nir_var_local:
2284 for (unsigned chan = 0; chan < 8; chan++) {
2285 if (!(writemask & (1 << chan)))
2286 continue;
2287
2288 value = llvm_extract_elem(ctx, src, chan);
2289 if (indir_index) {
2290 unsigned count = glsl_count_attribute_slots(
2291 instr->variables[0]->var->type, false);
2292 count -= chan / 4;
2293 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2294 &ctx->ac, ctx->locals + idx + chan, count,
2295 4, true);
2296
2297 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2298 value, indir_index, "");
2299 build_store_values_extended(ctx, ctx->locals + idx + chan,
2300 count, 4, tmp_vec);
2301 } else {
2302 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2303
2304 LLVMBuildStore(ctx->builder, value, temp_ptr);
2305 }
2306 }
2307 break;
2308 case nir_var_shared: {
2309 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2310
2311 if (indir_index)
2312 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2313
2314 for (unsigned chan = 0; chan < 8; chan++) {
2315 if (!(writemask & (1 << chan)))
2316 continue;
2317 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2318 LLVMValueRef derived_ptr;
2319
2320 if (indir_index)
2321 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2322
2323 value = llvm_extract_elem(ctx, src, chan);
2324 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2325 LLVMBuildStore(ctx->builder,
2326 to_integer(ctx, value), derived_ptr);
2327 }
2328 break;
2329 }
2330 default:
2331 break;
2332 }
2333 }
2334
2335 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2336 {
2337 switch (dim) {
2338 case GLSL_SAMPLER_DIM_BUF:
2339 return 1;
2340 case GLSL_SAMPLER_DIM_1D:
2341 return array ? 2 : 1;
2342 case GLSL_SAMPLER_DIM_2D:
2343 return array ? 3 : 2;
2344 case GLSL_SAMPLER_DIM_MS:
2345 return array ? 4 : 3;
2346 case GLSL_SAMPLER_DIM_3D:
2347 case GLSL_SAMPLER_DIM_CUBE:
2348 return 3;
2349 case GLSL_SAMPLER_DIM_RECT:
2350 case GLSL_SAMPLER_DIM_SUBPASS:
2351 return 2;
2352 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2353 return 3;
2354 default:
2355 break;
2356 }
2357 return 0;
2358 }
2359
2360 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2361 nir_intrinsic_instr *instr)
2362 {
2363 const struct glsl_type *type = instr->variables[0]->var->type;
2364 if(instr->variables[0]->deref.child)
2365 type = instr->variables[0]->deref.child->type;
2366
2367 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2368 LLVMValueRef coords[4];
2369 LLVMValueRef masks[] = {
2370 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2371 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2372 };
2373 LLVMValueRef res;
2374 int count;
2375 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2376 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2377 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2378 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2379 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2380
2381 count = image_type_to_components_count(dim,
2382 glsl_sampler_type_is_array(type));
2383
2384 if (count == 1) {
2385 if (instr->src[0].ssa->num_components)
2386 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2387 else
2388 res = src0;
2389 } else {
2390 int chan;
2391 if (is_ms)
2392 count--;
2393 for (chan = 0; chan < count; ++chan) {
2394 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2395 }
2396
2397 if (add_frag_pos) {
2398 for (chan = 0; chan < count; ++chan)
2399 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2400 }
2401 if (is_ms) {
2402 coords[count] = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2403 count++;
2404 }
2405
2406 if (count == 3) {
2407 coords[3] = LLVMGetUndef(ctx->i32);
2408 count = 4;
2409 }
2410 res = ac_build_gather_values(&ctx->ac, coords, count);
2411 }
2412 return res;
2413 }
2414
2415 static void build_type_name_for_intr(
2416 LLVMTypeRef type,
2417 char *buf, unsigned bufsize)
2418 {
2419 LLVMTypeRef elem_type = type;
2420
2421 assert(bufsize >= 8);
2422
2423 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
2424 int ret = snprintf(buf, bufsize, "v%u",
2425 LLVMGetVectorSize(type));
2426 if (ret < 0) {
2427 char *type_name = LLVMPrintTypeToString(type);
2428 fprintf(stderr, "Error building type name for: %s\n",
2429 type_name);
2430 return;
2431 }
2432 elem_type = LLVMGetElementType(type);
2433 buf += ret;
2434 bufsize -= ret;
2435 }
2436 switch (LLVMGetTypeKind(elem_type)) {
2437 default: break;
2438 case LLVMIntegerTypeKind:
2439 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
2440 break;
2441 case LLVMFloatTypeKind:
2442 snprintf(buf, bufsize, "f32");
2443 break;
2444 case LLVMDoubleTypeKind:
2445 snprintf(buf, bufsize, "f64");
2446 break;
2447 }
2448 }
2449
2450 static void get_image_intr_name(const char *base_name,
2451 LLVMTypeRef data_type,
2452 LLVMTypeRef coords_type,
2453 LLVMTypeRef rsrc_type,
2454 char *out_name, unsigned out_len)
2455 {
2456 char coords_type_name[8];
2457
2458 build_type_name_for_intr(coords_type, coords_type_name,
2459 sizeof(coords_type_name));
2460
2461 if (HAVE_LLVM <= 0x0309) {
2462 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
2463 } else {
2464 char data_type_name[8];
2465 char rsrc_type_name[8];
2466
2467 build_type_name_for_intr(data_type, data_type_name,
2468 sizeof(data_type_name));
2469 build_type_name_for_intr(rsrc_type, rsrc_type_name,
2470 sizeof(rsrc_type_name));
2471 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
2472 data_type_name, coords_type_name, rsrc_type_name);
2473 }
2474 }
2475
2476 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2477 nir_intrinsic_instr *instr)
2478 {
2479 LLVMValueRef params[7];
2480 LLVMValueRef res;
2481 char intrinsic_name[64];
2482 const nir_variable *var = instr->variables[0]->var;
2483 const struct glsl_type *type = var->type;
2484 if(instr->variables[0]->deref.child)
2485 type = instr->variables[0]->deref.child->type;
2486
2487 type = glsl_without_array(type);
2488 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2489 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2490 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2491 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2492 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2493 params[3] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2494 params[4] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2495 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2496 params, 5, 0);
2497
2498 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2499 res = to_integer(ctx, res);
2500 } else {
2501 bool is_da = glsl_sampler_type_is_array(type) ||
2502 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2503 LLVMValueRef da = is_da ? ctx->i32one : ctx->i32zero;
2504 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2505 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2506
2507 params[0] = get_image_coords(ctx, instr);
2508 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2509 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2510 if (HAVE_LLVM <= 0x0309) {
2511 params[3] = LLVMConstInt(ctx->i1, 0, false); /* r128 */
2512 params[4] = da;
2513 params[5] = glc;
2514 params[6] = slc;
2515 } else {
2516 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2517 params[3] = glc;
2518 params[4] = slc;
2519 params[5] = lwe;
2520 params[6] = da;
2521 }
2522
2523 get_image_intr_name("llvm.amdgcn.image.load",
2524 ctx->v4f32, /* vdata */
2525 LLVMTypeOf(params[0]), /* coords */
2526 LLVMTypeOf(params[1]), /* rsrc */
2527 intrinsic_name, sizeof(intrinsic_name));
2528
2529 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2530 params, 7, AC_FUNC_ATTR_READONLY);
2531 }
2532 return to_integer(ctx, res);
2533 }
2534
2535 static void visit_image_store(struct nir_to_llvm_context *ctx,
2536 nir_intrinsic_instr *instr)
2537 {
2538 LLVMValueRef params[8];
2539 char intrinsic_name[64];
2540 const nir_variable *var = instr->variables[0]->var;
2541 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2542 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2543 const struct glsl_type *type = glsl_without_array(var->type);
2544
2545 if (ctx->stage == MESA_SHADER_FRAGMENT)
2546 ctx->shader_info->fs.writes_memory = true;
2547
2548 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2549 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2550 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2551 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2552 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2553 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2554 params[4] = i1false; /* glc */
2555 params[5] = i1false; /* slc */
2556 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2557 params, 6, 0);
2558 } else {
2559 bool is_da = glsl_sampler_type_is_array(type) ||
2560 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2561 LLVMValueRef da = is_da ? i1true : i1false;
2562 LLVMValueRef glc = i1false;
2563 LLVMValueRef slc = i1false;
2564
2565 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2566 params[1] = get_image_coords(ctx, instr); /* coords */
2567 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2568 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2569 if (HAVE_LLVM <= 0x0309) {
2570 params[4] = i1false; /* r128 */
2571 params[5] = da;
2572 params[6] = glc;
2573 params[7] = slc;
2574 } else {
2575 LLVMValueRef lwe = i1false;
2576 params[4] = glc;
2577 params[5] = slc;
2578 params[6] = lwe;
2579 params[7] = da;
2580 }
2581
2582 get_image_intr_name("llvm.amdgcn.image.store",
2583 LLVMTypeOf(params[0]), /* vdata */
2584 LLVMTypeOf(params[1]), /* coords */
2585 LLVMTypeOf(params[2]), /* rsrc */
2586 intrinsic_name, sizeof(intrinsic_name));
2587
2588 ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2589 params, 8, 0);
2590 }
2591
2592 }
2593
2594 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2595 nir_intrinsic_instr *instr)
2596 {
2597 LLVMValueRef params[6];
2598 int param_count = 0;
2599 const nir_variable *var = instr->variables[0]->var;
2600 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2601 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2602 const char *base_name = "llvm.amdgcn.image.atomic";
2603 const char *atomic_name;
2604 LLVMValueRef coords;
2605 char intrinsic_name[32], coords_type[8];
2606 const struct glsl_type *type = glsl_without_array(var->type);
2607
2608 if (ctx->stage == MESA_SHADER_FRAGMENT)
2609 ctx->shader_info->fs.writes_memory = true;
2610
2611 params[param_count++] = get_src(ctx, instr->src[2]);
2612 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2613 params[param_count++] = get_src(ctx, instr->src[3]);
2614
2615 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2616 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2617 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2618 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2619 params[param_count++] = ctx->i32zero; /* voffset */
2620 params[param_count++] = i1false; /* glc */
2621 params[param_count++] = i1false; /* slc */
2622 } else {
2623 bool da = glsl_sampler_type_is_array(type) ||
2624 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2625
2626 coords = params[param_count++] = get_image_coords(ctx, instr);
2627 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2628 params[param_count++] = i1false; /* r128 */
2629 params[param_count++] = da ? i1true : i1false; /* da */
2630 params[param_count++] = i1false; /* slc */
2631 }
2632
2633 switch (instr->intrinsic) {
2634 case nir_intrinsic_image_atomic_add:
2635 atomic_name = "add";
2636 break;
2637 case nir_intrinsic_image_atomic_min:
2638 atomic_name = "smin";
2639 break;
2640 case nir_intrinsic_image_atomic_max:
2641 atomic_name = "smax";
2642 break;
2643 case nir_intrinsic_image_atomic_and:
2644 atomic_name = "and";
2645 break;
2646 case nir_intrinsic_image_atomic_or:
2647 atomic_name = "or";
2648 break;
2649 case nir_intrinsic_image_atomic_xor:
2650 atomic_name = "xor";
2651 break;
2652 case nir_intrinsic_image_atomic_exchange:
2653 atomic_name = "swap";
2654 break;
2655 case nir_intrinsic_image_atomic_comp_swap:
2656 atomic_name = "cmpswap";
2657 break;
2658 default:
2659 abort();
2660 }
2661 build_int_type_name(LLVMTypeOf(coords),
2662 coords_type, sizeof(coords_type));
2663
2664 snprintf(intrinsic_name, sizeof(intrinsic_name),
2665 "%s.%s.%s", base_name, atomic_name, coords_type);
2666 return ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2667 }
2668
2669 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2670 nir_intrinsic_instr *instr)
2671 {
2672 LLVMValueRef res;
2673 LLVMValueRef params[10];
2674 const nir_variable *var = instr->variables[0]->var;
2675 const struct glsl_type *type = instr->variables[0]->var->type;
2676 bool da = glsl_sampler_type_is_array(var->type) ||
2677 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2678 if(instr->variables[0]->deref.child)
2679 type = instr->variables[0]->deref.child->type;
2680
2681 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2682 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2683 params[0] = ctx->i32zero;
2684 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2685 params[2] = LLVMConstInt(ctx->i32, 15, false);
2686 params[3] = ctx->i32zero;
2687 params[4] = ctx->i32zero;
2688 params[5] = da ? ctx->i32one : ctx->i32zero;
2689 params[6] = ctx->i32zero;
2690 params[7] = ctx->i32zero;
2691 params[8] = ctx->i32zero;
2692 params[9] = ctx->i32zero;
2693
2694 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
2695 params, 10, AC_FUNC_ATTR_READNONE);
2696
2697 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2698 glsl_sampler_type_is_array(type)) {
2699 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2700 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2701 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2702 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2703 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2704 }
2705 return res;
2706 }
2707
2708 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2709 {
2710 LLVMValueRef args[1] = {
2711 LLVMConstInt(ctx->i32, 0xf70, false),
2712 };
2713 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2714 ctx->voidt, args, 1, 0);
2715 }
2716
2717 static void emit_barrier(struct nir_to_llvm_context *ctx)
2718 {
2719 // TODO tess
2720 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2721 ctx->voidt, NULL, 0, 0);
2722 }
2723
2724 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2725 nir_intrinsic_instr *instr)
2726 {
2727 LLVMValueRef cond;
2728 ctx->shader_info->fs.can_discard = true;
2729
2730 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2731 get_src(ctx, instr->src[0]),
2732 ctx->i32zero, "");
2733
2734 cond = LLVMBuildSelect(ctx->builder, cond,
2735 LLVMConstReal(ctx->f32, -1.0f),
2736 ctx->f32zero, "");
2737 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
2738 ctx->voidt,
2739 &cond, 1, 0);
2740 }
2741
2742 static LLVMValueRef
2743 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2744 {
2745 LLVMValueRef result;
2746 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
2747 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2748 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2749
2750 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2751 }
2752
2753 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2754 nir_intrinsic_instr *instr)
2755 {
2756 LLVMValueRef ptr, result;
2757 int idx = instr->variables[0]->var->data.driver_location;
2758 LLVMValueRef src = get_src(ctx, instr->src[0]);
2759 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2760
2761 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2762 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2763 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2764 ptr, src, src1,
2765 LLVMAtomicOrderingSequentiallyConsistent,
2766 LLVMAtomicOrderingSequentiallyConsistent,
2767 false);
2768 } else {
2769 LLVMAtomicRMWBinOp op;
2770 switch (instr->intrinsic) {
2771 case nir_intrinsic_var_atomic_add:
2772 op = LLVMAtomicRMWBinOpAdd;
2773 break;
2774 case nir_intrinsic_var_atomic_umin:
2775 op = LLVMAtomicRMWBinOpUMin;
2776 break;
2777 case nir_intrinsic_var_atomic_umax:
2778 op = LLVMAtomicRMWBinOpUMax;
2779 break;
2780 case nir_intrinsic_var_atomic_imin:
2781 op = LLVMAtomicRMWBinOpMin;
2782 break;
2783 case nir_intrinsic_var_atomic_imax:
2784 op = LLVMAtomicRMWBinOpMax;
2785 break;
2786 case nir_intrinsic_var_atomic_and:
2787 op = LLVMAtomicRMWBinOpAnd;
2788 break;
2789 case nir_intrinsic_var_atomic_or:
2790 op = LLVMAtomicRMWBinOpOr;
2791 break;
2792 case nir_intrinsic_var_atomic_xor:
2793 op = LLVMAtomicRMWBinOpXor;
2794 break;
2795 case nir_intrinsic_var_atomic_exchange:
2796 op = LLVMAtomicRMWBinOpXchg;
2797 break;
2798 default:
2799 return NULL;
2800 }
2801
2802 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2803 LLVMAtomicOrderingSequentiallyConsistent,
2804 false);
2805 }
2806 return result;
2807 }
2808
2809 #define INTERP_CENTER 0
2810 #define INTERP_CENTROID 1
2811 #define INTERP_SAMPLE 2
2812
2813 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2814 enum glsl_interp_mode interp, unsigned location)
2815 {
2816 switch (interp) {
2817 case INTERP_MODE_FLAT:
2818 default:
2819 return NULL;
2820 case INTERP_MODE_SMOOTH:
2821 case INTERP_MODE_NONE:
2822 if (location == INTERP_CENTER)
2823 return ctx->persp_center;
2824 else if (location == INTERP_CENTROID)
2825 return ctx->persp_centroid;
2826 else if (location == INTERP_SAMPLE)
2827 return ctx->persp_sample;
2828 break;
2829 case INTERP_MODE_NOPERSPECTIVE:
2830 if (location == INTERP_CENTER)
2831 return ctx->linear_center;
2832 else if (location == INTERP_CENTROID)
2833 return ctx->linear_centroid;
2834 else if (location == INTERP_SAMPLE)
2835 return ctx->linear_sample;
2836 break;
2837 }
2838 return NULL;
2839 }
2840
2841 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
2842 LLVMValueRef sample_id)
2843 {
2844 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2845 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
2846 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
2847 LLVMValueRef result[2];
2848
2849 result[0] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset0);
2850 result[1] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset1);
2851
2852 return ac_build_gather_values(&ctx->ac, result, 2);
2853 }
2854
2855 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
2856 {
2857 LLVMValueRef values[2];
2858
2859 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
2860 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
2861 return ac_build_gather_values(&ctx->ac, values, 2);
2862 }
2863
2864 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
2865 nir_intrinsic_instr *instr)
2866 {
2867 LLVMValueRef result[2];
2868 LLVMValueRef interp_param, attr_number;
2869 unsigned location;
2870 unsigned chan;
2871 LLVMValueRef src_c0, src_c1;
2872 LLVMValueRef src0;
2873 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
2874 switch (instr->intrinsic) {
2875 case nir_intrinsic_interp_var_at_centroid:
2876 location = INTERP_CENTROID;
2877 break;
2878 case nir_intrinsic_interp_var_at_sample:
2879 case nir_intrinsic_interp_var_at_offset:
2880 location = INTERP_SAMPLE;
2881 src0 = get_src(ctx, instr->src[0]);
2882 break;
2883 default:
2884 break;
2885 }
2886
2887 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
2888 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
2889 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
2890 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
2891 LLVMValueRef sample_position;
2892 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
2893
2894 /* fetch sample ID */
2895 sample_position = load_sample_position(ctx, src0);
2896
2897 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
2898 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
2899 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
2900 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
2901 }
2902 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
2903 attr_number = LLVMConstInt(ctx->i32, input_index, false);
2904
2905 if (location == INTERP_SAMPLE) {
2906 LLVMValueRef ij_out[2];
2907 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
2908
2909 /*
2910 * take the I then J parameters, and the DDX/Y for it, and
2911 * calculate the IJ inputs for the interpolator.
2912 * temp1 = ddx * offset/sample.x + I;
2913 * interp_param.I = ddy * offset/sample.y + temp1;
2914 * temp1 = ddx * offset/sample.x + J;
2915 * interp_param.J = ddy * offset/sample.y + temp1;
2916 */
2917 for (unsigned i = 0; i < 2; i++) {
2918 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
2919 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
2920 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
2921 ddxy_out, ix_ll, "");
2922 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
2923 ddxy_out, iy_ll, "");
2924 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
2925 interp_param, ix_ll, "");
2926 LLVMValueRef temp1, temp2;
2927
2928 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
2929 ctx->f32, "");
2930
2931 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
2932 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
2933
2934 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
2935 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
2936
2937 ij_out[i] = LLVMBuildBitCast(ctx->builder,
2938 temp2, ctx->i32, "");
2939 }
2940 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
2941
2942 }
2943
2944 for (chan = 0; chan < 2; chan++) {
2945 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
2946
2947 if (interp_param) {
2948 interp_param = LLVMBuildBitCast(ctx->builder,
2949 interp_param, LLVMVectorType(ctx->f32, 2), "");
2950 LLVMValueRef i = LLVMBuildExtractElement(
2951 ctx->builder, interp_param, ctx->i32zero, "");
2952 LLVMValueRef j = LLVMBuildExtractElement(
2953 ctx->builder, interp_param, ctx->i32one, "");
2954
2955 result[chan] = ac_build_fs_interp(&ctx->ac,
2956 llvm_chan, attr_number,
2957 ctx->prim_mask, i, j);
2958 } else {
2959 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
2960 LLVMConstInt(ctx->i32, 2, false),
2961 llvm_chan, attr_number,
2962 ctx->prim_mask);
2963 }
2964 }
2965 return ac_build_gather_values(&ctx->ac, result, 2);
2966 }
2967
2968 static void
2969 visit_emit_vertex(struct nir_to_llvm_context *ctx,
2970 nir_intrinsic_instr *instr)
2971 {
2972 LLVMValueRef gs_next_vertex;
2973 LLVMValueRef can_emit, kill;
2974 int idx;
2975
2976 assert(instr->const_index[0] == 0);
2977 /* Write vertex attribute values to GSVS ring */
2978 gs_next_vertex = LLVMBuildLoad(ctx->builder,
2979 ctx->gs_next_vertex,
2980 "");
2981
2982 /* If this thread has already emitted the declared maximum number of
2983 * vertices, kill it: excessive vertex emissions are not supposed to
2984 * have any effect, and GS threads have no externally observable
2985 * effects other than emitting vertices.
2986 */
2987 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
2988 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
2989
2990 kill = LLVMBuildSelect(ctx->builder, can_emit,
2991 LLVMConstReal(ctx->f32, 1.0f),
2992 LLVMConstReal(ctx->f32, -1.0f), "");
2993 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
2994 ctx->voidt, &kill, 1, 0);
2995
2996 /* loop num outputs */
2997 idx = 0;
2998 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
2999 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3000 if (!(ctx->output_mask & (1ull << i)))
3001 continue;
3002
3003 for (unsigned j = 0; j < 4; j++) {
3004 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3005 out_ptr[j], "");
3006 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (idx * 4 + j) * ctx->gs_max_out_vertices, false);
3007 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3008 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3009
3010 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3011
3012 ac_build_tbuffer_store(&ctx->ac, ctx->gsvs_ring,
3013 out_val, 1,
3014 voffset, ctx->gs2vs_offset, 0,
3015 V_008F0C_BUF_DATA_FORMAT_32,
3016 V_008F0C_BUF_NUM_FORMAT_UINT,
3017 1, 0, 1, 1, 0);
3018 }
3019 idx++;
3020 }
3021
3022 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3023 ctx->i32one, "");
3024 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3025
3026 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3027 }
3028
3029 static void
3030 visit_end_primitive(struct nir_to_llvm_context *ctx,
3031 nir_intrinsic_instr *instr)
3032 {
3033 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3034 }
3035
3036 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3037 nir_intrinsic_instr *instr)
3038 {
3039 LLVMValueRef result = NULL;
3040
3041 switch (instr->intrinsic) {
3042 case nir_intrinsic_load_work_group_id: {
3043 result = ctx->workgroup_ids;
3044 break;
3045 }
3046 case nir_intrinsic_load_base_vertex: {
3047 result = ctx->base_vertex;
3048 break;
3049 }
3050 case nir_intrinsic_load_vertex_id_zero_base: {
3051 result = ctx->vertex_id;
3052 break;
3053 }
3054 case nir_intrinsic_load_local_invocation_id: {
3055 result = ctx->local_invocation_ids;
3056 break;
3057 }
3058 case nir_intrinsic_load_base_instance:
3059 result = ctx->start_instance;
3060 break;
3061 case nir_intrinsic_load_draw_id:
3062 result = ctx->draw_index;
3063 break;
3064 case nir_intrinsic_load_invocation_id:
3065 result = ctx->gs_invocation_id;
3066 break;
3067 case nir_intrinsic_load_primitive_id:
3068 if (ctx->stage == MESA_SHADER_GEOMETRY)
3069 result = ctx->gs_prim_id;
3070 else
3071 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3072 break;
3073 case nir_intrinsic_load_sample_id:
3074 ctx->shader_info->fs.force_persample = true;
3075 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3076 break;
3077 case nir_intrinsic_load_sample_pos:
3078 ctx->shader_info->fs.force_persample = true;
3079 result = load_sample_pos(ctx);
3080 break;
3081 case nir_intrinsic_load_front_face:
3082 result = ctx->front_face;
3083 break;
3084 case nir_intrinsic_load_instance_id:
3085 result = ctx->instance_id;
3086 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3087 ctx->shader_info->vs.vgpr_comp_cnt);
3088 break;
3089 case nir_intrinsic_load_num_work_groups:
3090 result = ctx->num_work_groups;
3091 break;
3092 case nir_intrinsic_load_local_invocation_index:
3093 result = visit_load_local_invocation_index(ctx);
3094 break;
3095 case nir_intrinsic_load_push_constant:
3096 result = visit_load_push_constant(ctx, instr);
3097 break;
3098 case nir_intrinsic_vulkan_resource_index:
3099 result = visit_vulkan_resource_index(ctx, instr);
3100 break;
3101 case nir_intrinsic_store_ssbo:
3102 visit_store_ssbo(ctx, instr);
3103 break;
3104 case nir_intrinsic_load_ssbo:
3105 result = visit_load_buffer(ctx, instr);
3106 break;
3107 case nir_intrinsic_ssbo_atomic_add:
3108 case nir_intrinsic_ssbo_atomic_imin:
3109 case nir_intrinsic_ssbo_atomic_umin:
3110 case nir_intrinsic_ssbo_atomic_imax:
3111 case nir_intrinsic_ssbo_atomic_umax:
3112 case nir_intrinsic_ssbo_atomic_and:
3113 case nir_intrinsic_ssbo_atomic_or:
3114 case nir_intrinsic_ssbo_atomic_xor:
3115 case nir_intrinsic_ssbo_atomic_exchange:
3116 case nir_intrinsic_ssbo_atomic_comp_swap:
3117 result = visit_atomic_ssbo(ctx, instr);
3118 break;
3119 case nir_intrinsic_load_ubo:
3120 result = visit_load_ubo_buffer(ctx, instr);
3121 break;
3122 case nir_intrinsic_get_buffer_size:
3123 result = visit_get_buffer_size(ctx, instr);
3124 break;
3125 case nir_intrinsic_load_var:
3126 result = visit_load_var(ctx, instr);
3127 break;
3128 case nir_intrinsic_store_var:
3129 visit_store_var(ctx, instr);
3130 break;
3131 case nir_intrinsic_image_load:
3132 result = visit_image_load(ctx, instr);
3133 break;
3134 case nir_intrinsic_image_store:
3135 visit_image_store(ctx, instr);
3136 break;
3137 case nir_intrinsic_image_atomic_add:
3138 case nir_intrinsic_image_atomic_min:
3139 case nir_intrinsic_image_atomic_max:
3140 case nir_intrinsic_image_atomic_and:
3141 case nir_intrinsic_image_atomic_or:
3142 case nir_intrinsic_image_atomic_xor:
3143 case nir_intrinsic_image_atomic_exchange:
3144 case nir_intrinsic_image_atomic_comp_swap:
3145 result = visit_image_atomic(ctx, instr);
3146 break;
3147 case nir_intrinsic_image_size:
3148 result = visit_image_size(ctx, instr);
3149 break;
3150 case nir_intrinsic_discard:
3151 ctx->shader_info->fs.can_discard = true;
3152 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3153 ctx->voidt,
3154 NULL, 0, 0);
3155 break;
3156 case nir_intrinsic_discard_if:
3157 emit_discard_if(ctx, instr);
3158 break;
3159 case nir_intrinsic_memory_barrier:
3160 emit_waitcnt(ctx);
3161 break;
3162 case nir_intrinsic_barrier:
3163 emit_barrier(ctx);
3164 break;
3165 case nir_intrinsic_var_atomic_add:
3166 case nir_intrinsic_var_atomic_imin:
3167 case nir_intrinsic_var_atomic_umin:
3168 case nir_intrinsic_var_atomic_imax:
3169 case nir_intrinsic_var_atomic_umax:
3170 case nir_intrinsic_var_atomic_and:
3171 case nir_intrinsic_var_atomic_or:
3172 case nir_intrinsic_var_atomic_xor:
3173 case nir_intrinsic_var_atomic_exchange:
3174 case nir_intrinsic_var_atomic_comp_swap:
3175 result = visit_var_atomic(ctx, instr);
3176 break;
3177 case nir_intrinsic_interp_var_at_centroid:
3178 case nir_intrinsic_interp_var_at_sample:
3179 case nir_intrinsic_interp_var_at_offset:
3180 result = visit_interp(ctx, instr);
3181 break;
3182 case nir_intrinsic_emit_vertex:
3183 visit_emit_vertex(ctx, instr);
3184 break;
3185 case nir_intrinsic_end_primitive:
3186 visit_end_primitive(ctx, instr);
3187 break;
3188 default:
3189 fprintf(stderr, "Unknown intrinsic: ");
3190 nir_print_instr(&instr->instr, stderr);
3191 fprintf(stderr, "\n");
3192 break;
3193 }
3194 if (result) {
3195 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3196 }
3197 }
3198
3199 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3200 nir_deref_var *deref,
3201 enum desc_type desc_type)
3202 {
3203 unsigned desc_set = deref->var->data.descriptor_set;
3204 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3205 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3206 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3207 unsigned offset = binding->offset;
3208 unsigned stride = binding->size;
3209 unsigned type_size;
3210 LLVMBuilderRef builder = ctx->builder;
3211 LLVMTypeRef type;
3212 LLVMValueRef index = NULL;
3213
3214 assert(deref->var->data.binding < layout->binding_count);
3215
3216 switch (desc_type) {
3217 case DESC_IMAGE:
3218 type = ctx->v8i32;
3219 type_size = 32;
3220 break;
3221 case DESC_FMASK:
3222 type = ctx->v8i32;
3223 offset += 32;
3224 type_size = 32;
3225 break;
3226 case DESC_SAMPLER:
3227 type = ctx->v4i32;
3228 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3229 offset += 64;
3230
3231 type_size = 16;
3232 break;
3233 case DESC_BUFFER:
3234 type = ctx->v4i32;
3235 type_size = 16;
3236 break;
3237 default:
3238 unreachable("invalid desc_type\n");
3239 }
3240
3241 if (deref->deref.child) {
3242 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3243
3244 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3245 offset += child->base_offset * stride;
3246 if (child->deref_array_type == nir_deref_array_type_indirect) {
3247 index = get_src(ctx, child->indirect);
3248 }
3249 }
3250
3251 assert(stride % type_size == 0);
3252
3253 if (!index)
3254 index = ctx->i32zero;
3255
3256 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3257
3258 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
3259 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3260
3261 return ac_build_indexed_load_const(&ctx->ac, list, index);
3262 }
3263
3264 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3265 struct ac_tex_info *tinfo,
3266 nir_tex_instr *instr,
3267 nir_texop op,
3268 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3269 LLVMValueRef *param, unsigned count,
3270 unsigned dmask)
3271 {
3272 int num_args;
3273 unsigned is_rect = 0;
3274 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3275
3276 if (op == nir_texop_lod)
3277 da = false;
3278 /* Pad to power of two vector */
3279 while (count < util_next_power_of_two(count))
3280 param[count++] = LLVMGetUndef(ctx->i32);
3281
3282 if (count > 1)
3283 tinfo->args[0] = ac_build_gather_values(&ctx->ac, param, count);
3284 else
3285 tinfo->args[0] = param[0];
3286
3287 tinfo->args[1] = res_ptr;
3288 num_args = 2;
3289
3290 if (op == nir_texop_txf ||
3291 op == nir_texop_txf_ms ||
3292 op == nir_texop_query_levels ||
3293 op == nir_texop_texture_samples ||
3294 op == nir_texop_txs)
3295 tinfo->dst_type = ctx->v4i32;
3296 else {
3297 tinfo->dst_type = ctx->v4f32;
3298 tinfo->args[num_args++] = samp_ptr;
3299 }
3300
3301 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3302 tinfo->args[0] = res_ptr;
3303 tinfo->args[1] = LLVMConstInt(ctx->i32, 0, false);
3304 tinfo->args[2] = param[0];
3305 tinfo->arg_count = 3;
3306 return;
3307 }
3308
3309 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, dmask, 0);
3310 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, is_rect, 0); /* unorm */
3311 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
3312 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
3313 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
3314 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
3315 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
3316 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
3317
3318 tinfo->arg_count = num_args;
3319 }
3320
3321 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3322 *
3323 * SI-CI:
3324 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3325 * filtering manually. The driver sets img7 to a mask clearing
3326 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3327 * s_and_b32 samp0, samp0, img7
3328 *
3329 * VI:
3330 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3331 */
3332 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3333 LLVMValueRef res, LLVMValueRef samp)
3334 {
3335 LLVMBuilderRef builder = ctx->builder;
3336 LLVMValueRef img7, samp0;
3337
3338 if (ctx->options->chip_class >= VI)
3339 return samp;
3340
3341 img7 = LLVMBuildExtractElement(builder, res,
3342 LLVMConstInt(ctx->i32, 7, 0), "");
3343 samp0 = LLVMBuildExtractElement(builder, samp,
3344 LLVMConstInt(ctx->i32, 0, 0), "");
3345 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3346 return LLVMBuildInsertElement(builder, samp, samp0,
3347 LLVMConstInt(ctx->i32, 0, 0), "");
3348 }
3349
3350 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3351 nir_tex_instr *instr,
3352 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3353 LLVMValueRef *fmask_ptr)
3354 {
3355 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3356 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3357 else
3358 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3359 if (samp_ptr) {
3360 if (instr->sampler)
3361 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3362 else
3363 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3364 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3365 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3366 }
3367 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3368 instr->op == nir_texop_samples_identical))
3369 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3370 }
3371
3372 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
3373 LLVMValueRef coord)
3374 {
3375 coord = to_float(ctx, coord);
3376 coord = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
3377 coord = to_integer(ctx, coord);
3378 return coord;
3379 }
3380
3381 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3382 {
3383 LLVMValueRef result = NULL;
3384 struct ac_tex_info tinfo = { 0 };
3385 unsigned dmask = 0xf;
3386 LLVMValueRef address[16];
3387 LLVMValueRef coords[5];
3388 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3389 LLVMValueRef bias = NULL, offsets = NULL;
3390 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3391 LLVMValueRef ddx = NULL, ddy = NULL;
3392 LLVMValueRef derivs[6];
3393 unsigned chan, count = 0;
3394 unsigned const_src = 0, num_deriv_comp = 0;
3395
3396 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3397
3398 for (unsigned i = 0; i < instr->num_srcs; i++) {
3399 switch (instr->src[i].src_type) {
3400 case nir_tex_src_coord:
3401 coord = get_src(ctx, instr->src[i].src);
3402 break;
3403 case nir_tex_src_projector:
3404 break;
3405 case nir_tex_src_comparator:
3406 comparator = get_src(ctx, instr->src[i].src);
3407 break;
3408 case nir_tex_src_offset:
3409 offsets = get_src(ctx, instr->src[i].src);
3410 const_src = i;
3411 break;
3412 case nir_tex_src_bias:
3413 bias = get_src(ctx, instr->src[i].src);
3414 break;
3415 case nir_tex_src_lod:
3416 lod = get_src(ctx, instr->src[i].src);
3417 break;
3418 case nir_tex_src_ms_index:
3419 sample_index = get_src(ctx, instr->src[i].src);
3420 break;
3421 case nir_tex_src_ms_mcs:
3422 break;
3423 case nir_tex_src_ddx:
3424 ddx = get_src(ctx, instr->src[i].src);
3425 num_deriv_comp = instr->src[i].src.ssa->num_components;
3426 break;
3427 case nir_tex_src_ddy:
3428 ddy = get_src(ctx, instr->src[i].src);
3429 break;
3430 case nir_tex_src_texture_offset:
3431 case nir_tex_src_sampler_offset:
3432 case nir_tex_src_plane:
3433 default:
3434 break;
3435 }
3436 }
3437
3438 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3439 result = get_buffer_size(ctx, res_ptr, false);
3440 goto write_result;
3441 }
3442
3443 if (instr->op == nir_texop_texture_samples) {
3444 LLVMValueRef res, samples, is_msaa;
3445 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3446 samples = LLVMBuildExtractElement(ctx->builder, res,
3447 LLVMConstInt(ctx->i32, 3, false), "");
3448 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3449 LLVMConstInt(ctx->i32, 28, false), "");
3450 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3451 LLVMConstInt(ctx->i32, 0xe, false), "");
3452 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3453 LLVMConstInt(ctx->i32, 0xe, false), "");
3454
3455 samples = LLVMBuildLShr(ctx->builder, samples,
3456 LLVMConstInt(ctx->i32, 16, false), "");
3457 samples = LLVMBuildAnd(ctx->builder, samples,
3458 LLVMConstInt(ctx->i32, 0xf, false), "");
3459 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3460 samples, "");
3461 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3462 ctx->i32one, "");
3463 result = samples;
3464 goto write_result;
3465 }
3466
3467 if (coord)
3468 for (chan = 0; chan < instr->coord_components; chan++)
3469 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3470
3471 if (offsets && instr->op != nir_texop_txf) {
3472 LLVMValueRef offset[3], pack;
3473 for (chan = 0; chan < 3; ++chan)
3474 offset[chan] = ctx->i32zero;
3475
3476 tinfo.has_offset = true;
3477 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3478 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3479 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3480 LLVMConstInt(ctx->i32, 0x3f, false), "");
3481 if (chan)
3482 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3483 LLVMConstInt(ctx->i32, chan * 8, false), "");
3484 }
3485 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3486 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3487 address[count++] = pack;
3488
3489 }
3490 /* pack LOD bias value */
3491 if (instr->op == nir_texop_txb && bias) {
3492 address[count++] = bias;
3493 }
3494
3495 /* Pack depth comparison value */
3496 if (instr->is_shadow && comparator) {
3497 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3498 }
3499
3500 /* pack derivatives */
3501 if (ddx || ddy) {
3502 switch (instr->sampler_dim) {
3503 case GLSL_SAMPLER_DIM_3D:
3504 case GLSL_SAMPLER_DIM_CUBE:
3505 num_deriv_comp = 3;
3506 break;
3507 case GLSL_SAMPLER_DIM_2D:
3508 default:
3509 num_deriv_comp = 2;
3510 break;
3511 case GLSL_SAMPLER_DIM_1D:
3512 num_deriv_comp = 1;
3513 break;
3514 }
3515
3516 for (unsigned i = 0; i < num_deriv_comp; i++) {
3517 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3518 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3519 }
3520 }
3521
3522 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3523 for (chan = 0; chan < instr->coord_components; chan++)
3524 coords[chan] = to_float(ctx, coords[chan]);
3525 if (instr->coord_components == 3)
3526 coords[3] = LLVMGetUndef(ctx->f32);
3527 ac_prepare_cube_coords(&ctx->ac,
3528 instr->op == nir_texop_txd, instr->is_array,
3529 coords, derivs);
3530 if (num_deriv_comp)
3531 num_deriv_comp--;
3532 }
3533
3534 if (ddx || ddy) {
3535 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3536 address[count++] = derivs[i];
3537 }
3538
3539 /* Pack texture coordinates */
3540 if (coord) {
3541 address[count++] = coords[0];
3542 if (instr->coord_components > 1) {
3543 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
3544 coords[1] = apply_round_slice(ctx, coords[1]);
3545 }
3546 address[count++] = coords[1];
3547 }
3548 if (instr->coord_components > 2) {
3549 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3550 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3551 coords[2] = apply_round_slice(ctx, coords[2]);
3552 }
3553 address[count++] = coords[2];
3554 }
3555 }
3556
3557 /* Pack LOD */
3558 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3559 address[count++] = lod;
3560 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3561 address[count++] = sample_index;
3562 } else if(instr->op == nir_texop_txs) {
3563 count = 0;
3564 if (lod)
3565 address[count++] = lod;
3566 else
3567 address[count++] = ctx->i32zero;
3568 }
3569
3570 for (chan = 0; chan < count; chan++) {
3571 address[chan] = LLVMBuildBitCast(ctx->builder,
3572 address[chan], ctx->i32, "");
3573 }
3574
3575 if (instr->op == nir_texop_samples_identical) {
3576 LLVMValueRef txf_address[4];
3577 struct ac_tex_info txf_info = { 0 };
3578 unsigned txf_count = count;
3579 memcpy(txf_address, address, sizeof(txf_address));
3580
3581 if (!instr->is_array)
3582 txf_address[2] = ctx->i32zero;
3583 txf_address[3] = ctx->i32zero;
3584
3585 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3586 fmask_ptr, NULL,
3587 txf_address, txf_count, 0xf);
3588
3589 result = build_tex_intrinsic(ctx, instr, &txf_info);
3590
3591 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3592 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3593 goto write_result;
3594 }
3595
3596 /* Adjust the sample index according to FMASK.
3597 *
3598 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3599 * which is the identity mapping. Each nibble says which physical sample
3600 * should be fetched to get that sample.
3601 *
3602 * For example, 0x11111100 means there are only 2 samples stored and
3603 * the second sample covers 3/4 of the pixel. When reading samples 0
3604 * and 1, return physical sample 0 (determined by the first two 0s
3605 * in FMASK), otherwise return physical sample 1.
3606 *
3607 * The sample index should be adjusted as follows:
3608 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3609 */
3610 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
3611 instr->op != nir_texop_txs) {
3612 LLVMValueRef txf_address[4];
3613 struct ac_tex_info txf_info = { 0 };
3614 unsigned txf_count = count;
3615 memcpy(txf_address, address, sizeof(txf_address));
3616
3617 if (!instr->is_array)
3618 txf_address[2] = ctx->i32zero;
3619 txf_address[3] = ctx->i32zero;
3620
3621 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3622 fmask_ptr, NULL,
3623 txf_address, txf_count, 0xf);
3624
3625 result = build_tex_intrinsic(ctx, instr, &txf_info);
3626 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3627 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3628
3629 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3630 result,
3631 ctx->i32zero, "");
3632
3633 unsigned sample_chan = instr->is_array ? 3 : 2;
3634
3635 LLVMValueRef sample_index4 =
3636 LLVMBuildMul(ctx->builder, address[sample_chan], four, "");
3637 LLVMValueRef shifted_fmask =
3638 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3639 LLVMValueRef final_sample =
3640 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3641
3642 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3643 * resource descriptor is 0 (invalid),
3644 */
3645 LLVMValueRef fmask_desc =
3646 LLVMBuildBitCast(ctx->builder, fmask_ptr,
3647 ctx->v8i32, "");
3648
3649 LLVMValueRef fmask_word1 =
3650 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3651 ctx->i32one, "");
3652
3653 LLVMValueRef word1_is_nonzero =
3654 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3655 fmask_word1, ctx->i32zero, "");
3656
3657 /* Replace the MSAA sample index. */
3658 address[sample_chan] =
3659 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3660 final_sample, address[sample_chan], "");
3661 }
3662
3663 if (offsets && instr->op == nir_texop_txf) {
3664 nir_const_value *const_offset =
3665 nir_src_as_const_value(instr->src[const_src].src);
3666 int num_offsets = instr->src[const_src].src.ssa->num_components;
3667 assert(const_offset);
3668 num_offsets = MIN2(num_offsets, instr->coord_components);
3669 if (num_offsets > 2)
3670 address[2] = LLVMBuildAdd(ctx->builder,
3671 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3672 if (num_offsets > 1)
3673 address[1] = LLVMBuildAdd(ctx->builder,
3674 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3675 address[0] = LLVMBuildAdd(ctx->builder,
3676 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3677
3678 }
3679
3680 /* TODO TG4 support */
3681 if (instr->op == nir_texop_tg4) {
3682 if (instr->is_shadow)
3683 dmask = 1;
3684 else
3685 dmask = 1 << instr->component;
3686 }
3687 set_tex_fetch_args(ctx, &tinfo, instr, instr->op,
3688 res_ptr, samp_ptr, address, count, dmask);
3689
3690 result = build_tex_intrinsic(ctx, instr, &tinfo);
3691
3692 if (instr->op == nir_texop_query_levels)
3693 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3694 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3695 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3696 else if (instr->op == nir_texop_txs &&
3697 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3698 instr->is_array) {
3699 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3700 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3701 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3702 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3703 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3704 } else if (instr->dest.ssa.num_components != 4)
3705 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3706
3707 write_result:
3708 if (result) {
3709 assert(instr->dest.is_ssa);
3710 result = to_integer(ctx, result);
3711 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3712 }
3713 }
3714
3715
3716 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3717 {
3718 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3719 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3720
3721 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3722 _mesa_hash_table_insert(ctx->phis, instr, result);
3723 }
3724
3725 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3726 nir_phi_instr *instr,
3727 LLVMValueRef llvm_phi)
3728 {
3729 nir_foreach_phi_src(src, instr) {
3730 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3731 LLVMValueRef llvm_src = get_src(ctx, src->src);
3732
3733 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3734 }
3735 }
3736
3737 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3738 {
3739 struct hash_entry *entry;
3740 hash_table_foreach(ctx->phis, entry) {
3741 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3742 (LLVMValueRef)entry->data);
3743 }
3744 }
3745
3746
3747 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3748 nir_ssa_undef_instr *instr)
3749 {
3750 unsigned num_components = instr->def.num_components;
3751 LLVMValueRef undef;
3752
3753 if (num_components == 1)
3754 undef = LLVMGetUndef(ctx->i32);
3755 else {
3756 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3757 }
3758 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3759 }
3760
3761 static void visit_jump(struct nir_to_llvm_context *ctx,
3762 nir_jump_instr *instr)
3763 {
3764 switch (instr->type) {
3765 case nir_jump_break:
3766 LLVMBuildBr(ctx->builder, ctx->break_block);
3767 LLVMClearInsertionPosition(ctx->builder);
3768 break;
3769 case nir_jump_continue:
3770 LLVMBuildBr(ctx->builder, ctx->continue_block);
3771 LLVMClearInsertionPosition(ctx->builder);
3772 break;
3773 default:
3774 fprintf(stderr, "Unknown NIR jump instr: ");
3775 nir_print_instr(&instr->instr, stderr);
3776 fprintf(stderr, "\n");
3777 abort();
3778 }
3779 }
3780
3781 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3782 struct exec_list *list);
3783
3784 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3785 {
3786 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3787 nir_foreach_instr(instr, block)
3788 {
3789 switch (instr->type) {
3790 case nir_instr_type_alu:
3791 visit_alu(ctx, nir_instr_as_alu(instr));
3792 break;
3793 case nir_instr_type_load_const:
3794 visit_load_const(ctx, nir_instr_as_load_const(instr));
3795 break;
3796 case nir_instr_type_intrinsic:
3797 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3798 break;
3799 case nir_instr_type_tex:
3800 visit_tex(ctx, nir_instr_as_tex(instr));
3801 break;
3802 case nir_instr_type_phi:
3803 visit_phi(ctx, nir_instr_as_phi(instr));
3804 break;
3805 case nir_instr_type_ssa_undef:
3806 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3807 break;
3808 case nir_instr_type_jump:
3809 visit_jump(ctx, nir_instr_as_jump(instr));
3810 break;
3811 default:
3812 fprintf(stderr, "Unknown NIR instr type: ");
3813 nir_print_instr(instr, stderr);
3814 fprintf(stderr, "\n");
3815 abort();
3816 }
3817 }
3818
3819 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3820 }
3821
3822 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3823 {
3824 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3825
3826 LLVMBasicBlockRef merge_block =
3827 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3828 LLVMBasicBlockRef if_block =
3829 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3830 LLVMBasicBlockRef else_block = merge_block;
3831 if (!exec_list_is_empty(&if_stmt->else_list))
3832 else_block = LLVMAppendBasicBlockInContext(
3833 ctx->context, ctx->main_function, "");
3834
3835 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3836 LLVMConstInt(ctx->i32, 0, false), "");
3837 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3838
3839 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3840 visit_cf_list(ctx, &if_stmt->then_list);
3841 if (LLVMGetInsertBlock(ctx->builder))
3842 LLVMBuildBr(ctx->builder, merge_block);
3843
3844 if (!exec_list_is_empty(&if_stmt->else_list)) {
3845 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3846 visit_cf_list(ctx, &if_stmt->else_list);
3847 if (LLVMGetInsertBlock(ctx->builder))
3848 LLVMBuildBr(ctx->builder, merge_block);
3849 }
3850
3851 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3852 }
3853
3854 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3855 {
3856 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3857 LLVMBasicBlockRef break_parent = ctx->break_block;
3858
3859 ctx->continue_block =
3860 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3861 ctx->break_block =
3862 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3863
3864 LLVMBuildBr(ctx->builder, ctx->continue_block);
3865 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
3866 visit_cf_list(ctx, &loop->body);
3867
3868 if (LLVMGetInsertBlock(ctx->builder))
3869 LLVMBuildBr(ctx->builder, ctx->continue_block);
3870 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
3871
3872 ctx->continue_block = continue_parent;
3873 ctx->break_block = break_parent;
3874 }
3875
3876 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3877 struct exec_list *list)
3878 {
3879 foreach_list_typed(nir_cf_node, node, node, list)
3880 {
3881 switch (node->type) {
3882 case nir_cf_node_block:
3883 visit_block(ctx, nir_cf_node_as_block(node));
3884 break;
3885
3886 case nir_cf_node_if:
3887 visit_if(ctx, nir_cf_node_as_if(node));
3888 break;
3889
3890 case nir_cf_node_loop:
3891 visit_loop(ctx, nir_cf_node_as_loop(node));
3892 break;
3893
3894 default:
3895 assert(0);
3896 }
3897 }
3898 }
3899
3900 static void
3901 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
3902 struct nir_variable *variable)
3903 {
3904 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
3905 LLVMValueRef t_offset;
3906 LLVMValueRef t_list;
3907 LLVMValueRef args[3];
3908 LLVMValueRef input;
3909 LLVMValueRef buffer_index;
3910 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
3911 int idx = variable->data.location;
3912 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
3913
3914 variable->data.driver_location = idx * 4;
3915
3916 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
3917 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
3918 ctx->start_instance, "");
3919 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3920 ctx->shader_info->vs.vgpr_comp_cnt);
3921 } else
3922 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
3923 ctx->base_vertex, "");
3924
3925 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
3926 t_offset = LLVMConstInt(ctx->i32, index + i, false);
3927
3928 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
3929 args[0] = t_list;
3930 args[1] = LLVMConstInt(ctx->i32, 0, false);
3931 args[2] = buffer_index;
3932 input = ac_emit_llvm_intrinsic(&ctx->ac,
3933 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
3934 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
3935
3936 for (unsigned chan = 0; chan < 4; chan++) {
3937 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3938 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
3939 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
3940 input, llvm_chan, ""));
3941 }
3942 }
3943 }
3944
3945
3946 static void interp_fs_input(struct nir_to_llvm_context *ctx,
3947 unsigned attr,
3948 LLVMValueRef interp_param,
3949 LLVMValueRef prim_mask,
3950 LLVMValueRef result[4])
3951 {
3952 LLVMValueRef attr_number;
3953 unsigned chan;
3954 LLVMValueRef i, j;
3955 bool interp = interp_param != NULL;
3956
3957 attr_number = LLVMConstInt(ctx->i32, attr, false);
3958
3959 /* fs.constant returns the param from the middle vertex, so it's not
3960 * really useful for flat shading. It's meant to be used for custom
3961 * interpolation (but the intrinsic can't fetch from the other two
3962 * vertices).
3963 *
3964 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
3965 * to do the right thing. The only reason we use fs.constant is that
3966 * fs.interp cannot be used on integers, because they can be equal
3967 * to NaN.
3968 */
3969 if (interp) {
3970 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
3971 LLVMVectorType(ctx->f32, 2), "");
3972
3973 i = LLVMBuildExtractElement(ctx->builder, interp_param,
3974 ctx->i32zero, "");
3975 j = LLVMBuildExtractElement(ctx->builder, interp_param,
3976 ctx->i32one, "");
3977 }
3978
3979 for (chan = 0; chan < 4; chan++) {
3980 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3981
3982 if (interp) {
3983 result[chan] = ac_build_fs_interp(&ctx->ac,
3984 llvm_chan,
3985 attr_number,
3986 prim_mask, i, j);
3987 } else {
3988 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3989 LLVMConstInt(ctx->i32, 2, false),
3990 llvm_chan,
3991 attr_number,
3992 prim_mask);
3993 }
3994 }
3995 }
3996
3997 static void
3998 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
3999 struct nir_variable *variable)
4000 {
4001 int idx = variable->data.location;
4002 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4003 LLVMValueRef interp;
4004
4005 variable->data.driver_location = idx * 4;
4006 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4007
4008 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4009 unsigned interp_type;
4010 if (variable->data.sample) {
4011 interp_type = INTERP_SAMPLE;
4012 ctx->shader_info->fs.force_persample = true;
4013 } else if (variable->data.centroid)
4014 interp_type = INTERP_CENTROID;
4015 else
4016 interp_type = INTERP_CENTER;
4017
4018 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4019 } else
4020 interp = NULL;
4021
4022 for (unsigned i = 0; i < attrib_count; ++i)
4023 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4024
4025 }
4026
4027 static void
4028 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4029 struct nir_variable *variable)
4030 {
4031 switch (ctx->stage) {
4032 case MESA_SHADER_VERTEX:
4033 handle_vs_input_decl(ctx, variable);
4034 break;
4035 case MESA_SHADER_FRAGMENT:
4036 handle_fs_input_decl(ctx, variable);
4037 break;
4038 default:
4039 break;
4040 }
4041
4042 }
4043
4044 static void
4045 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4046 struct nir_shader *nir)
4047 {
4048 unsigned index = 0;
4049 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4050 LLVMValueRef interp_param;
4051 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4052
4053 if (!(ctx->input_mask & (1ull << i)))
4054 continue;
4055
4056 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4057 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4058 interp_param = *inputs;
4059 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4060 inputs);
4061
4062 if (!interp_param)
4063 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4064 ++index;
4065 } else if (i == VARYING_SLOT_POS) {
4066 for(int i = 0; i < 3; ++i)
4067 inputs[i] = ctx->frag_pos[i];
4068
4069 inputs[3] = ac_emit_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4070 }
4071 }
4072 ctx->shader_info->fs.num_interp = index;
4073 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4074 ctx->shader_info->fs.has_pcoord = true;
4075 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4076 ctx->shader_info->fs.prim_id_input = true;
4077 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4078 ctx->shader_info->fs.layer_input = true;
4079 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4080 }
4081
4082 static LLVMValueRef
4083 ac_build_alloca(struct nir_to_llvm_context *ctx,
4084 LLVMTypeRef type,
4085 const char *name)
4086 {
4087 LLVMBuilderRef builder = ctx->builder;
4088 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4089 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4090 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4091 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4092 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4093 LLVMValueRef res;
4094
4095 if (first_instr) {
4096 LLVMPositionBuilderBefore(first_builder, first_instr);
4097 } else {
4098 LLVMPositionBuilderAtEnd(first_builder, first_block);
4099 }
4100
4101 res = LLVMBuildAlloca(first_builder, type, name);
4102 LLVMBuildStore(builder, LLVMConstNull(type), res);
4103
4104 LLVMDisposeBuilder(first_builder);
4105
4106 return res;
4107 }
4108
4109 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4110 LLVMTypeRef type,
4111 const char *name)
4112 {
4113 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4114 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4115 return ptr;
4116 }
4117
4118 static void
4119 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4120 struct nir_variable *variable)
4121 {
4122 int idx = variable->data.location + variable->data.index;
4123 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4124
4125 variable->data.driver_location = idx * 4;
4126
4127 if (ctx->stage == MESA_SHADER_VERTEX ||
4128 ctx->stage == MESA_SHADER_GEOMETRY) {
4129 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4130 idx == VARYING_SLOT_CULL_DIST0) {
4131 int length = glsl_get_length(variable->type);
4132 if (ctx->stage == MESA_SHADER_VERTEX) {
4133 if (idx == VARYING_SLOT_CLIP_DIST0) {
4134 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
4135 ctx->num_output_clips = length;
4136 } else if (idx == VARYING_SLOT_CULL_DIST0) {
4137 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
4138 ctx->num_output_culls = length;
4139 }
4140 }
4141 if (length > 4)
4142 attrib_count = 2;
4143 else
4144 attrib_count = 1;
4145 }
4146 }
4147
4148 for (unsigned i = 0; i < attrib_count; ++i) {
4149 for (unsigned chan = 0; chan < 4; chan++) {
4150 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4151 si_build_alloca_undef(ctx, ctx->f32, "");
4152 }
4153 }
4154 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
4155 }
4156
4157 static void
4158 setup_locals(struct nir_to_llvm_context *ctx,
4159 struct nir_function *func)
4160 {
4161 int i, j;
4162 ctx->num_locals = 0;
4163 nir_foreach_variable(variable, &func->impl->locals) {
4164 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4165 variable->data.driver_location = ctx->num_locals * 4;
4166 ctx->num_locals += attrib_count;
4167 }
4168 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4169 if (!ctx->locals)
4170 return;
4171
4172 for (i = 0; i < ctx->num_locals; i++) {
4173 for (j = 0; j < 4; j++) {
4174 ctx->locals[i * 4 + j] =
4175 si_build_alloca_undef(ctx, ctx->f32, "temp");
4176 }
4177 }
4178 }
4179
4180 static LLVMValueRef
4181 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4182 {
4183 v = to_float(ctx, v);
4184 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4185 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4186 }
4187
4188
4189 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4190 LLVMValueRef src0, LLVMValueRef src1)
4191 {
4192 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4193 LLVMValueRef comp[2];
4194
4195 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4196 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4197 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4198 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4199 }
4200
4201 /* Initialize arguments for the shader export intrinsic */
4202 static void
4203 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4204 LLVMValueRef *values,
4205 unsigned target,
4206 LLVMValueRef *args)
4207 {
4208 /* Default is 0xf. Adjusted below depending on the format. */
4209 args[0] = LLVMConstInt(ctx->i32, target != V_008DFC_SQ_EXP_NULL ? 0xf : 0, false);
4210 /* Specify whether the EXEC mask represents the valid mask */
4211 args[1] = LLVMConstInt(ctx->i32, 0, false);
4212
4213 /* Specify whether this is the last export */
4214 args[2] = LLVMConstInt(ctx->i32, 0, false);
4215 /* Specify the target we are exporting */
4216 args[3] = LLVMConstInt(ctx->i32, target, false);
4217
4218 args[4] = LLVMConstInt(ctx->i32, 0, false); /* COMPR flag */
4219 args[5] = LLVMGetUndef(ctx->f32);
4220 args[6] = LLVMGetUndef(ctx->f32);
4221 args[7] = LLVMGetUndef(ctx->f32);
4222 args[8] = LLVMGetUndef(ctx->f32);
4223
4224 if (!values)
4225 return;
4226
4227 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4228 LLVMValueRef val[4];
4229 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4230 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4231 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4232
4233 switch(col_format) {
4234 case V_028714_SPI_SHADER_ZERO:
4235 args[0] = LLVMConstInt(ctx->i32, 0x0, 0);
4236 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_NULL, 0);
4237 break;
4238
4239 case V_028714_SPI_SHADER_32_R:
4240 args[0] = LLVMConstInt(ctx->i32, 0x1, 0);
4241 args[5] = values[0];
4242 break;
4243
4244 case V_028714_SPI_SHADER_32_GR:
4245 args[0] = LLVMConstInt(ctx->i32, 0x3, 0);
4246 args[5] = values[0];
4247 args[6] = values[1];
4248 break;
4249
4250 case V_028714_SPI_SHADER_32_AR:
4251 args[0] = LLVMConstInt(ctx->i32, 0x9, 0);
4252 args[5] = values[0];
4253 args[8] = values[3];
4254 break;
4255
4256 case V_028714_SPI_SHADER_FP16_ABGR:
4257 args[4] = ctx->i32one;
4258
4259 for (unsigned chan = 0; chan < 2; chan++) {
4260 LLVMValueRef pack_args[2] = {
4261 values[2 * chan],
4262 values[2 * chan + 1]
4263 };
4264 LLVMValueRef packed;
4265
4266 packed = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.packf16",
4267 ctx->i32, pack_args, 2,
4268 AC_FUNC_ATTR_READNONE);
4269 args[chan + 5] = packed;
4270 }
4271 break;
4272
4273 case V_028714_SPI_SHADER_UNORM16_ABGR:
4274 for (unsigned chan = 0; chan < 4; chan++) {
4275 val[chan] = emit_float_saturate(ctx, values[chan], 0, 1);
4276 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4277 LLVMConstReal(ctx->f32, 65535), "");
4278 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4279 LLVMConstReal(ctx->f32, 0.5), "");
4280 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4281 ctx->i32, "");
4282 }
4283
4284 args[4] = ctx->i32one;
4285 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4286 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4287 break;
4288
4289 case V_028714_SPI_SHADER_SNORM16_ABGR:
4290 for (unsigned chan = 0; chan < 4; chan++) {
4291 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4292 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4293 LLVMConstReal(ctx->f32, 32767), "");
4294
4295 /* If positive, add 0.5, else add -0.5. */
4296 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4297 LLVMBuildSelect(ctx->builder,
4298 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4299 val[chan], ctx->f32zero, ""),
4300 LLVMConstReal(ctx->f32, 0.5),
4301 LLVMConstReal(ctx->f32, -0.5), ""), "");
4302 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4303 }
4304
4305 args[4] = ctx->i32one;
4306 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4307 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4308 break;
4309
4310 case V_028714_SPI_SHADER_UINT16_ABGR: {
4311 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4312
4313 for (unsigned chan = 0; chan < 4; chan++) {
4314 val[chan] = to_integer(ctx, values[chan]);
4315 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4316 }
4317
4318 args[4] = ctx->i32one;
4319 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4320 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4321 break;
4322 }
4323
4324 case V_028714_SPI_SHADER_SINT16_ABGR: {
4325 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4326 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4327
4328 /* Clamp. */
4329 for (unsigned chan = 0; chan < 4; chan++) {
4330 val[chan] = to_integer(ctx, values[chan]);
4331 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4332 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4333 }
4334
4335 args[4] = ctx->i32one;
4336 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4337 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4338 break;
4339 }
4340
4341 default:
4342 case V_028714_SPI_SHADER_32_ABGR:
4343 memcpy(&args[5], values, sizeof(values[0]) * 4);
4344 break;
4345 }
4346 } else
4347 memcpy(&args[5], values, sizeof(values[0]) * 4);
4348
4349 for (unsigned i = 5; i < 9; ++i)
4350 args[i] = to_float(ctx, args[i]);
4351 }
4352
4353 static void
4354 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4355 {
4356 uint32_t param_count = 0;
4357 unsigned target;
4358 unsigned pos_idx, num_pos_exports = 0;
4359 LLVMValueRef args[9];
4360 LLVMValueRef pos_args[4][9] = { { 0 } };
4361 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4362 int i;
4363 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4364 (1ull << VARYING_SLOT_CLIP_DIST1) |
4365 (1ull << VARYING_SLOT_CULL_DIST0) |
4366 (1ull << VARYING_SLOT_CULL_DIST1));
4367
4368 ctx->shader_info->vs.prim_id_output = 0xffffffff;
4369 ctx->shader_info->vs.layer_output = 0xffffffff;
4370 if (clip_mask) {
4371 LLVMValueRef slots[8];
4372 unsigned j;
4373
4374 if (ctx->shader_info->vs.cull_dist_mask)
4375 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_output_clips;
4376
4377 i = VARYING_SLOT_CLIP_DIST0;
4378 for (j = 0; j < ctx->num_output_clips; j++)
4379 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4380 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4381 i = VARYING_SLOT_CULL_DIST0;
4382 for (j = 0; j < ctx->num_output_culls; j++)
4383 slots[ctx->num_output_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4384 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4385
4386 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
4387 slots[i] = LLVMGetUndef(ctx->f32);
4388
4389 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
4390 target = V_008DFC_SQ_EXP_POS + 3;
4391 si_llvm_init_export_args(ctx, &slots[4], target, args);
4392 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4393 args, sizeof(args));
4394 }
4395
4396 target = V_008DFC_SQ_EXP_POS + 2;
4397 si_llvm_init_export_args(ctx, &slots[0], target, args);
4398 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4399 args, sizeof(args));
4400
4401 }
4402
4403 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4404 LLVMValueRef values[4];
4405 if (!(ctx->output_mask & (1ull << i)))
4406 continue;
4407
4408 for (unsigned j = 0; j < 4; j++)
4409 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4410 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4411
4412 if (i == VARYING_SLOT_POS) {
4413 target = V_008DFC_SQ_EXP_POS;
4414 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4415 i == VARYING_SLOT_CLIP_DIST1 ||
4416 i == VARYING_SLOT_CULL_DIST0 ||
4417 i == VARYING_SLOT_CULL_DIST1) {
4418 continue;
4419 } else if (i == VARYING_SLOT_PSIZ) {
4420 ctx->shader_info->vs.writes_pointsize = true;
4421 psize_value = values[0];
4422 continue;
4423 } else if (i == VARYING_SLOT_LAYER) {
4424 ctx->shader_info->vs.writes_layer = true;
4425 layer_value = values[0];
4426 ctx->shader_info->vs.layer_output = param_count;
4427 target = V_008DFC_SQ_EXP_PARAM + param_count;
4428 param_count++;
4429 } else if (i == VARYING_SLOT_VIEWPORT) {
4430 ctx->shader_info->vs.writes_viewport_index = true;
4431 viewport_index_value = values[0];
4432 continue;
4433 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
4434 ctx->shader_info->vs.prim_id_output = param_count;
4435 target = V_008DFC_SQ_EXP_PARAM + param_count;
4436 param_count++;
4437 } else if (i >= VARYING_SLOT_VAR0) {
4438 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4439 target = V_008DFC_SQ_EXP_PARAM + param_count;
4440 param_count++;
4441 }
4442
4443 si_llvm_init_export_args(ctx, values, target, args);
4444
4445 if (target >= V_008DFC_SQ_EXP_POS &&
4446 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4447 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4448 args, sizeof(args));
4449 } else {
4450 ac_emit_llvm_intrinsic(&ctx->ac,
4451 "llvm.SI.export",
4452 ctx->voidt,
4453 args, 9, 0);
4454 }
4455 }
4456
4457 /* We need to add the position output manually if it's missing. */
4458 if (!pos_args[0][0]) {
4459 pos_args[0][0] = LLVMConstInt(ctx->i32, 0xf, false);
4460 pos_args[0][1] = ctx->i32zero; /* EXEC mask */
4461 pos_args[0][2] = ctx->i32zero; /* last export? */
4462 pos_args[0][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS, false);
4463 pos_args[0][4] = ctx->i32zero; /* COMPR flag */
4464 pos_args[0][5] = ctx->f32zero; /* X */
4465 pos_args[0][6] = ctx->f32zero; /* Y */
4466 pos_args[0][7] = ctx->f32zero; /* Z */
4467 pos_args[0][8] = ctx->f32one; /* W */
4468 }
4469
4470 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4471 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4472 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4473 if (mask) {
4474 pos_args[1][0] = LLVMConstInt(ctx->i32, mask, false); /* writemask */
4475 pos_args[1][1] = ctx->i32zero; /* EXEC mask */
4476 pos_args[1][2] = ctx->i32zero; /* last export? */
4477 pos_args[1][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + 1, false);
4478 pos_args[1][4] = ctx->i32zero; /* COMPR flag */
4479 pos_args[1][5] = ctx->f32zero; /* X */
4480 pos_args[1][6] = ctx->f32zero; /* Y */
4481 pos_args[1][7] = ctx->f32zero; /* Z */
4482 pos_args[1][8] = ctx->f32zero; /* W */
4483
4484 if (ctx->shader_info->vs.writes_pointsize == true)
4485 pos_args[1][5] = psize_value;
4486 if (ctx->shader_info->vs.writes_layer == true)
4487 pos_args[1][7] = layer_value;
4488 if (ctx->shader_info->vs.writes_viewport_index == true)
4489 pos_args[1][8] = viewport_index_value;
4490 }
4491 for (i = 0; i < 4; i++) {
4492 if (pos_args[i][0])
4493 num_pos_exports++;
4494 }
4495
4496 pos_idx = 0;
4497 for (i = 0; i < 4; i++) {
4498 if (!pos_args[i][0])
4499 continue;
4500
4501 /* Specify the target we are exporting */
4502 pos_args[i][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + pos_idx++, false);
4503 if (pos_idx == num_pos_exports)
4504 pos_args[i][2] = ctx->i32one;
4505 ac_emit_llvm_intrinsic(&ctx->ac,
4506 "llvm.SI.export",
4507 ctx->voidt,
4508 pos_args[i], 9, 0);
4509 }
4510
4511 ctx->shader_info->vs.pos_exports = num_pos_exports;
4512 ctx->shader_info->vs.param_exports = param_count;
4513 }
4514
4515 static void
4516 handle_es_outputs_post(struct nir_to_llvm_context *ctx)
4517 {
4518 int j;
4519 uint64_t max_output_written = 0;
4520 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4521 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
4522 int param_index;
4523 if (!(ctx->output_mask & (1ull << i)))
4524 continue;
4525
4526 param_index = shader_io_get_unique_index(i);
4527
4528 if (param_index > max_output_written)
4529 max_output_written = param_index;
4530
4531 for (j = 0; j < 4; j++) {
4532 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
4533 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4534
4535 ac_build_tbuffer_store(&ctx->ac,
4536 ctx->esgs_ring,
4537 out_val, 1,
4538 LLVMGetUndef(ctx->i32), ctx->es2gs_offset,
4539 (4 * param_index + j) * 4,
4540 V_008F0C_BUF_DATA_FORMAT_32,
4541 V_008F0C_BUF_NUM_FORMAT_UINT,
4542 0, 0, 1, 1, 0);
4543 }
4544 }
4545 ctx->shader_info->vs.esgs_itemsize = (max_output_written + 1) * 16;
4546 }
4547
4548 static void
4549 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4550 LLVMValueRef *color, unsigned param, bool is_last)
4551 {
4552 LLVMValueRef args[9];
4553 /* Export */
4554 si_llvm_init_export_args(ctx, color, param,
4555 args);
4556
4557 if (is_last) {
4558 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4559 args[2] = ctx->i32one; /* DONE bit */
4560 } else if (args[0] == ctx->i32zero)
4561 return; /* unnecessary NULL export */
4562
4563 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4564 ctx->voidt, args, 9, 0);
4565 }
4566
4567 static void
4568 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4569 LLVMValueRef depth, LLVMValueRef stencil,
4570 LLVMValueRef samplemask)
4571 {
4572 LLVMValueRef args[9];
4573 unsigned mask = 0;
4574 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4575 args[2] = ctx->i32one; /* DONE bit */
4576 /* Specify the target we are exporting */
4577 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_MRTZ, false);
4578
4579 args[4] = ctx->i32zero; /* COMP flag */
4580 args[5] = LLVMGetUndef(ctx->f32); /* R, depth */
4581 args[6] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4582 args[7] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4583 args[8] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4584
4585 if (depth) {
4586 args[5] = depth;
4587 mask |= 0x1;
4588 }
4589
4590 if (stencil) {
4591 args[6] = stencil;
4592 mask |= 0x2;
4593 }
4594
4595 if (samplemask) {
4596 args[7] = samplemask;
4597 mask |= 0x04;
4598 }
4599
4600 /* SI (except OLAND) has a bug that it only looks
4601 * at the X writemask component. */
4602 if (ctx->options->chip_class == SI &&
4603 ctx->options->family != CHIP_OLAND)
4604 mask |= 0x01;
4605
4606 args[0] = LLVMConstInt(ctx->i32, mask, false);
4607 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4608 ctx->voidt, args, 9, 0);
4609 }
4610
4611 static void
4612 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4613 {
4614 unsigned index = 0;
4615 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4616
4617 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4618 LLVMValueRef values[4];
4619
4620 if (!(ctx->output_mask & (1ull << i)))
4621 continue;
4622
4623 if (i == FRAG_RESULT_DEPTH) {
4624 ctx->shader_info->fs.writes_z = true;
4625 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4626 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4627 } else if (i == FRAG_RESULT_STENCIL) {
4628 ctx->shader_info->fs.writes_stencil = true;
4629 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4630 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4631 } else {
4632 bool last = false;
4633 for (unsigned j = 0; j < 4; j++)
4634 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4635 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4636
4637 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil)
4638 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4639
4640 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4641 index++;
4642 }
4643 }
4644
4645 if (depth || stencil)
4646 si_export_mrt_z(ctx, depth, stencil, samplemask);
4647 else if (!index)
4648 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4649
4650 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4651 }
4652
4653 static void
4654 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4655 {
4656 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
4657 }
4658
4659 static void
4660 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4661 {
4662 switch (ctx->stage) {
4663 case MESA_SHADER_VERTEX:
4664 if (ctx->options->key.vs.as_es)
4665 handle_es_outputs_post(ctx);
4666 else
4667 handle_vs_outputs_post(ctx);
4668 break;
4669 case MESA_SHADER_FRAGMENT:
4670 handle_fs_outputs_post(ctx);
4671 break;
4672 case MESA_SHADER_GEOMETRY:
4673 emit_gs_epilogue(ctx);
4674 break;
4675 default:
4676 break;
4677 }
4678 }
4679
4680 static void
4681 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4682 struct nir_variable *variable, uint32_t *offset, int idx)
4683 {
4684 unsigned size = glsl_count_attribute_slots(variable->type, false);
4685 variable->data.driver_location = *offset;
4686 *offset += size;
4687 }
4688
4689 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4690 {
4691 LLVMPassManagerRef passmgr;
4692 /* Create the pass manager */
4693 passmgr = LLVMCreateFunctionPassManagerForModule(
4694 ctx->module);
4695
4696 /* This pass should eliminate all the load and store instructions */
4697 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4698
4699 /* Add some optimization passes */
4700 LLVMAddScalarReplAggregatesPass(passmgr);
4701 LLVMAddLICMPass(passmgr);
4702 LLVMAddAggressiveDCEPass(passmgr);
4703 LLVMAddCFGSimplificationPass(passmgr);
4704 LLVMAddInstructionCombiningPass(passmgr);
4705
4706 /* Run the pass */
4707 LLVMInitializeFunctionPassManager(passmgr);
4708 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4709 LLVMFinalizeFunctionPassManager(passmgr);
4710
4711 LLVMDisposeBuilder(ctx->builder);
4712 LLVMDisposePassManager(passmgr);
4713 }
4714
4715 static void
4716 ac_setup_rings(struct nir_to_llvm_context *ctx)
4717 {
4718 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4719 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, ctx->i32one);
4720 }
4721
4722 if (ctx->is_gs_copy_shader) {
4723 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4724 }
4725 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4726 LLVMValueRef tmp;
4727 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4728 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4729
4730 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4731
4732 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4733 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4734 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4735 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4736
4737 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4738 }
4739 }
4740
4741 static
4742 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4743 struct nir_shader *nir,
4744 struct ac_shader_variant_info *shader_info,
4745 const struct ac_nir_compiler_options *options)
4746 {
4747 struct nir_to_llvm_context ctx = {0};
4748 struct nir_function *func;
4749 unsigned i;
4750 ctx.options = options;
4751 ctx.shader_info = shader_info;
4752 ctx.context = LLVMContextCreate();
4753 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4754
4755 ac_llvm_context_init(&ctx.ac, ctx.context);
4756 ctx.ac.module = ctx.module;
4757
4758 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4759
4760 memset(shader_info, 0, sizeof(*shader_info));
4761
4762 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4763 setup_types(&ctx);
4764
4765 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4766 ctx.ac.builder = ctx.builder;
4767 ctx.stage = nir->stage;
4768
4769 for (i = 0; i < AC_UD_MAX_SETS; i++)
4770 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4771 for (i = 0; i < AC_UD_MAX_UD; i++)
4772 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4773
4774 create_function(&ctx);
4775
4776 if (nir->stage == MESA_SHADER_COMPUTE) {
4777 int num_shared = 0;
4778 nir_foreach_variable(variable, &nir->shared)
4779 num_shared++;
4780 if (num_shared) {
4781 int idx = 0;
4782 uint32_t shared_size = 0;
4783 LLVMValueRef var;
4784 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4785 nir_foreach_variable(variable, &nir->shared) {
4786 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4787 idx++;
4788 }
4789
4790 shared_size *= 16;
4791 var = LLVMAddGlobalInAddressSpace(ctx.module,
4792 LLVMArrayType(ctx.i8, shared_size),
4793 "compute_lds",
4794 LOCAL_ADDR_SPACE);
4795 LLVMSetAlignment(var, 4);
4796 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4797 }
4798 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4799 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4800
4801 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4802 }
4803
4804 ac_setup_rings(&ctx);
4805
4806 nir_foreach_variable(variable, &nir->inputs)
4807 handle_shader_input_decl(&ctx, variable);
4808
4809 if (nir->stage == MESA_SHADER_FRAGMENT)
4810 handle_fs_inputs_pre(&ctx, nir);
4811
4812 nir_foreach_variable(variable, &nir->outputs)
4813 handle_shader_output_decl(&ctx, variable);
4814
4815 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4816 _mesa_key_pointer_equal);
4817 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4818 _mesa_key_pointer_equal);
4819
4820 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4821
4822 setup_locals(&ctx, func);
4823
4824 visit_cf_list(&ctx, &func->impl->body);
4825 phi_post_pass(&ctx);
4826
4827 handle_shader_outputs_post(&ctx);
4828 LLVMBuildRetVoid(ctx.builder);
4829
4830 ac_llvm_finalize_module(&ctx);
4831 free(ctx.locals);
4832 ralloc_free(ctx.defs);
4833 ralloc_free(ctx.phis);
4834
4835 if (nir->stage == MESA_SHADER_GEOMETRY) {
4836 shader_info->gs.gsvs_vertex_size = util_bitcount64(ctx.output_mask) * 16;
4837 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
4838 nir->info->gs.vertices_out;
4839 }
4840 return ctx.module;
4841 }
4842
4843 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4844 {
4845 unsigned *retval = (unsigned *)context;
4846 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4847 char *description = LLVMGetDiagInfoDescription(di);
4848
4849 if (severity == LLVMDSError) {
4850 *retval = 1;
4851 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4852 description);
4853 }
4854
4855 LLVMDisposeMessage(description);
4856 }
4857
4858 static unsigned ac_llvm_compile(LLVMModuleRef M,
4859 struct ac_shader_binary *binary,
4860 LLVMTargetMachineRef tm)
4861 {
4862 unsigned retval = 0;
4863 char *err;
4864 LLVMContextRef llvm_ctx;
4865 LLVMMemoryBufferRef out_buffer;
4866 unsigned buffer_size;
4867 const char *buffer_data;
4868 LLVMBool mem_err;
4869
4870 /* Setup Diagnostic Handler*/
4871 llvm_ctx = LLVMGetModuleContext(M);
4872
4873 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4874 &retval);
4875
4876 /* Compile IR*/
4877 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
4878 &err, &out_buffer);
4879
4880 /* Process Errors/Warnings */
4881 if (mem_err) {
4882 fprintf(stderr, "%s: %s", __FUNCTION__, err);
4883 free(err);
4884 retval = 1;
4885 goto out;
4886 }
4887
4888 /* Extract Shader Code*/
4889 buffer_size = LLVMGetBufferSize(out_buffer);
4890 buffer_data = LLVMGetBufferStart(out_buffer);
4891
4892 ac_elf_read(buffer_data, buffer_size, binary);
4893
4894 /* Clean up */
4895 LLVMDisposeMemoryBuffer(out_buffer);
4896
4897 out:
4898 return retval;
4899 }
4900
4901 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
4902 LLVMModuleRef llvm_module,
4903 struct ac_shader_binary *binary,
4904 struct ac_shader_config *config,
4905 struct ac_shader_variant_info *shader_info,
4906 gl_shader_stage stage,
4907 bool dump_shader, bool supports_spill)
4908 {
4909 if (dump_shader)
4910 ac_dump_module(llvm_module);
4911
4912 memset(binary, 0, sizeof(*binary));
4913 int v = ac_llvm_compile(llvm_module, binary, tm);
4914 if (v) {
4915 fprintf(stderr, "compile failed\n");
4916 }
4917
4918 if (dump_shader)
4919 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
4920
4921 ac_shader_binary_read_config(binary, config, 0, supports_spill);
4922
4923 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4924 LLVMDisposeModule(llvm_module);
4925 LLVMContextDispose(ctx);
4926
4927 if (stage == MESA_SHADER_FRAGMENT) {
4928 shader_info->num_input_vgprs = 0;
4929 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
4930 shader_info->num_input_vgprs += 2;
4931 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
4932 shader_info->num_input_vgprs += 2;
4933 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
4934 shader_info->num_input_vgprs += 2;
4935 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
4936 shader_info->num_input_vgprs += 3;
4937 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
4938 shader_info->num_input_vgprs += 2;
4939 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
4940 shader_info->num_input_vgprs += 2;
4941 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
4942 shader_info->num_input_vgprs += 2;
4943 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
4944 shader_info->num_input_vgprs += 1;
4945 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
4946 shader_info->num_input_vgprs += 1;
4947 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
4948 shader_info->num_input_vgprs += 1;
4949 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
4950 shader_info->num_input_vgprs += 1;
4951 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
4952 shader_info->num_input_vgprs += 1;
4953 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
4954 shader_info->num_input_vgprs += 1;
4955 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
4956 shader_info->num_input_vgprs += 1;
4957 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
4958 shader_info->num_input_vgprs += 1;
4959 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
4960 shader_info->num_input_vgprs += 1;
4961 }
4962 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
4963
4964 /* +3 for scratch wave offset and VCC */
4965 config->num_sgprs = MAX2(config->num_sgprs,
4966 shader_info->num_input_sgprs + 3);
4967 }
4968
4969 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
4970 struct ac_shader_binary *binary,
4971 struct ac_shader_config *config,
4972 struct ac_shader_variant_info *shader_info,
4973 struct nir_shader *nir,
4974 const struct ac_nir_compiler_options *options,
4975 bool dump_shader)
4976 {
4977
4978 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
4979 options);
4980
4981 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
4982 switch (nir->stage) {
4983 case MESA_SHADER_COMPUTE:
4984 for (int i = 0; i < 3; ++i)
4985 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
4986 break;
4987 case MESA_SHADER_FRAGMENT:
4988 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
4989 break;
4990 case MESA_SHADER_GEOMETRY:
4991 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
4992 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
4993 shader_info->gs.output_prim = nir->info->gs.output_primitive;
4994 shader_info->gs.invocations = nir->info->gs.invocations;
4995 break;
4996 case MESA_SHADER_VERTEX:
4997 shader_info->vs.as_es = options->key.vs.as_es;
4998 break;
4999 default:
5000 break;
5001 }
5002 }
5003
5004 static void
5005 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5006 {
5007 LLVMValueRef args[9];
5008 args[0] = ctx->gsvs_ring;
5009 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5010 args[3] = ctx->i32zero;
5011 args[4] = ctx->i32one; /* OFFEN */
5012 args[5] = ctx->i32zero; /* IDXEN */
5013 args[6] = ctx->i32one; /* GLC */
5014 args[7] = ctx->i32one; /* SLC */
5015 args[8] = ctx->i32zero; /* TFE */
5016
5017 int idx = 0;
5018 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5019 if (!(ctx->output_mask & (1ull << i)))
5020 continue;
5021
5022 for (unsigned j = 0; j < 4; j++) {
5023 LLVMValueRef value;
5024 args[2] = LLVMConstInt(ctx->i32,
5025 (idx * 4 + j) *
5026 ctx->gs_max_out_vertices * 16 * 4, false);
5027
5028 value = ac_emit_llvm_intrinsic(&ctx->ac,
5029 "llvm.SI.buffer.load.dword.i32.i32",
5030 ctx->i32, args, 9,
5031 AC_FUNC_ATTR_READONLY);
5032
5033 LLVMBuildStore(ctx->builder,
5034 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
5035 }
5036 idx++;
5037 }
5038 handle_vs_outputs_post(ctx);
5039 }
5040
5041 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5042 struct nir_shader *geom_shader,
5043 struct ac_shader_binary *binary,
5044 struct ac_shader_config *config,
5045 struct ac_shader_variant_info *shader_info,
5046 const struct ac_nir_compiler_options *options,
5047 bool dump_shader)
5048 {
5049 struct nir_to_llvm_context ctx = {0};
5050 ctx.context = LLVMContextCreate();
5051 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5052 ctx.options = options;
5053 ctx.shader_info = shader_info;
5054
5055 ac_llvm_context_init(&ctx.ac, ctx.context);
5056 ctx.ac.module = ctx.module;
5057
5058 ctx.is_gs_copy_shader = true;
5059 LLVMSetTarget(ctx.module, "amdgcn--");
5060 setup_types(&ctx);
5061
5062 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5063 ctx.ac.builder = ctx.builder;
5064 ctx.stage = MESA_SHADER_VERTEX;
5065
5066 create_function(&ctx);
5067
5068 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5069 ac_setup_rings(&ctx);
5070
5071 nir_foreach_variable(variable, &geom_shader->outputs)
5072 handle_shader_output_decl(&ctx, variable);
5073
5074 ac_gs_copy_shader_emit(&ctx);
5075
5076 LLVMBuildRetVoid(ctx.builder);
5077
5078 ac_llvm_finalize_module(&ctx);
5079
5080 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5081 MESA_SHADER_VERTEX,
5082 dump_shader, options->supports_spill);
5083 }