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ac/nir: silence maybe-uninitialized warnings
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 };
43
44 #define CONST_ADDR_SPACE 2
45 #define LOCAL_ADDR_SPACE 3
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct nir_to_llvm_context;
51
52 struct ac_nir_context {
53 struct ac_llvm_context ac;
54 struct ac_shader_abi *abi;
55
56 gl_shader_stage stage;
57
58 struct hash_table *defs;
59 struct hash_table *phis;
60 struct hash_table *vars;
61
62 LLVMValueRef main_function;
63 LLVMBasicBlockRef continue_block;
64 LLVMBasicBlockRef break_block;
65
66 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
67
68 int num_locals;
69 LLVMValueRef *locals;
70
71 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
72 };
73
74 struct nir_to_llvm_context {
75 struct ac_llvm_context ac;
76 const struct ac_nir_compiler_options *options;
77 struct ac_shader_variant_info *shader_info;
78 struct ac_shader_abi abi;
79 struct ac_nir_context *nir;
80
81 unsigned max_workgroup_size;
82 LLVMContextRef context;
83 LLVMModuleRef module;
84 LLVMBuilderRef builder;
85 LLVMValueRef main_function;
86
87 struct hash_table *defs;
88 struct hash_table *phis;
89
90 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
91 LLVMValueRef ring_offsets;
92 LLVMValueRef push_constants;
93 LLVMValueRef view_index;
94 LLVMValueRef num_work_groups;
95 LLVMValueRef workgroup_ids;
96 LLVMValueRef local_invocation_ids;
97 LLVMValueRef tg_size;
98
99 LLVMValueRef vertex_buffers;
100 LLVMValueRef rel_auto_id;
101 LLVMValueRef vs_prim_id;
102 LLVMValueRef ls_out_layout;
103 LLVMValueRef es2gs_offset;
104
105 LLVMValueRef tcs_offchip_layout;
106 LLVMValueRef tcs_out_offsets;
107 LLVMValueRef tcs_out_layout;
108 LLVMValueRef tcs_in_layout;
109 LLVMValueRef oc_lds;
110 LLVMValueRef tess_factor_offset;
111 LLVMValueRef tcs_patch_id;
112 LLVMValueRef tcs_rel_ids;
113 LLVMValueRef tes_rel_patch_id;
114 LLVMValueRef tes_patch_id;
115 LLVMValueRef tes_u;
116 LLVMValueRef tes_v;
117
118 LLVMValueRef gsvs_ring_stride;
119 LLVMValueRef gsvs_num_entries;
120 LLVMValueRef gs2vs_offset;
121 LLVMValueRef gs_wave_id;
122 LLVMValueRef gs_vtx_offset[6];
123 LLVMValueRef gs_prim_id, gs_invocation_id;
124
125 LLVMValueRef esgs_ring;
126 LLVMValueRef gsvs_ring;
127 LLVMValueRef hs_ring_tess_offchip;
128 LLVMValueRef hs_ring_tess_factor;
129
130 LLVMValueRef prim_mask;
131 LLVMValueRef sample_pos_offset;
132 LLVMValueRef persp_sample, persp_center, persp_centroid;
133 LLVMValueRef linear_sample, linear_center, linear_centroid;
134
135 LLVMTypeRef i1;
136 LLVMTypeRef i8;
137 LLVMTypeRef i16;
138 LLVMTypeRef i32;
139 LLVMTypeRef i64;
140 LLVMTypeRef v2i32;
141 LLVMTypeRef v3i32;
142 LLVMTypeRef v4i32;
143 LLVMTypeRef v8i32;
144 LLVMTypeRef f64;
145 LLVMTypeRef f32;
146 LLVMTypeRef f16;
147 LLVMTypeRef v2f32;
148 LLVMTypeRef v4f32;
149 LLVMTypeRef voidt;
150
151 LLVMValueRef i1true;
152 LLVMValueRef i1false;
153 LLVMValueRef i32zero;
154 LLVMValueRef i32one;
155 LLVMValueRef f32zero;
156 LLVMValueRef f32one;
157 LLVMValueRef v4f32empty;
158
159 unsigned uniform_md_kind;
160 LLVMValueRef empty_md;
161 gl_shader_stage stage;
162
163 LLVMValueRef lds;
164 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
165
166 uint64_t input_mask;
167 uint64_t output_mask;
168 uint8_t num_output_clips;
169 uint8_t num_output_culls;
170
171 bool is_gs_copy_shader;
172 LLVMValueRef gs_next_vertex;
173 unsigned gs_max_out_vertices;
174
175 unsigned tes_primitive_mode;
176 uint64_t tess_outputs_written;
177 uint64_t tess_patch_outputs_written;
178 };
179
180 static inline struct nir_to_llvm_context *
181 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
182 {
183 struct nir_to_llvm_context *ctx = NULL;
184 return container_of(abi, ctx, abi);
185 }
186
187 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
188 const nir_deref_var *deref,
189 enum ac_descriptor_type desc_type,
190 bool image, bool write);
191
192 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
193 {
194 return (index * 4) + chan;
195 }
196
197 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
198 {
199 /* handle patch indices separate */
200 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
201 return 0;
202 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
203 return 1;
204 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
205 return 2 + (slot - VARYING_SLOT_PATCH0);
206
207 if (slot == VARYING_SLOT_POS)
208 return 0;
209 if (slot == VARYING_SLOT_PSIZ)
210 return 1;
211 if (slot == VARYING_SLOT_CLIP_DIST0)
212 return 2;
213 /* 3 is reserved for clip dist as well */
214 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
215 return 4 + (slot - VARYING_SLOT_VAR0);
216 unreachable("illegal slot in get unique index\n");
217 }
218
219 static unsigned llvm_get_type_size(LLVMTypeRef type)
220 {
221 LLVMTypeKind kind = LLVMGetTypeKind(type);
222
223 switch (kind) {
224 case LLVMIntegerTypeKind:
225 return LLVMGetIntTypeWidth(type) / 8;
226 case LLVMFloatTypeKind:
227 return 4;
228 case LLVMPointerTypeKind:
229 return 8;
230 case LLVMVectorTypeKind:
231 return LLVMGetVectorSize(type) *
232 llvm_get_type_size(LLVMGetElementType(type));
233 default:
234 assert(0);
235 return 0;
236 }
237 }
238
239 static void set_llvm_calling_convention(LLVMValueRef func,
240 gl_shader_stage stage)
241 {
242 enum radeon_llvm_calling_convention calling_conv;
243
244 switch (stage) {
245 case MESA_SHADER_VERTEX:
246 case MESA_SHADER_TESS_CTRL:
247 case MESA_SHADER_TESS_EVAL:
248 calling_conv = RADEON_LLVM_AMDGPU_VS;
249 break;
250 case MESA_SHADER_GEOMETRY:
251 calling_conv = RADEON_LLVM_AMDGPU_GS;
252 break;
253 case MESA_SHADER_FRAGMENT:
254 calling_conv = RADEON_LLVM_AMDGPU_PS;
255 break;
256 case MESA_SHADER_COMPUTE:
257 calling_conv = RADEON_LLVM_AMDGPU_CS;
258 break;
259 default:
260 unreachable("Unhandle shader type");
261 }
262
263 LLVMSetFunctionCallConv(func, calling_conv);
264 }
265
266 #define MAX_ARGS 23
267 struct arg_info {
268 LLVMTypeRef types[MAX_ARGS];
269 LLVMValueRef *assign[MAX_ARGS];
270 unsigned array_params_mask;
271 uint8_t count;
272 uint8_t user_sgpr_count;
273 uint8_t sgpr_count;
274 uint8_t num_user_sgprs_used;
275 uint8_t num_sgprs_used;
276 uint8_t num_vgprs_used;
277 };
278
279 static inline void
280 add_argument(struct arg_info *info,
281 LLVMTypeRef type, LLVMValueRef *param_ptr)
282 {
283 assert(info->count < MAX_ARGS);
284 info->assign[info->count] = param_ptr;
285 info->types[info->count] = type;
286 info->count++;
287 }
288
289 static inline void
290 add_sgpr_argument(struct arg_info *info,
291 LLVMTypeRef type, LLVMValueRef *param_ptr)
292 {
293 add_argument(info, type, param_ptr);
294 info->num_sgprs_used += llvm_get_type_size(type) / 4;
295 info->sgpr_count++;
296 }
297
298 static inline void
299 add_user_sgpr_argument(struct arg_info *info,
300 LLVMTypeRef type,
301 LLVMValueRef *param_ptr)
302 {
303 add_sgpr_argument(info, type, param_ptr);
304 info->num_user_sgprs_used += llvm_get_type_size(type) / 4;
305 info->user_sgpr_count++;
306 }
307
308 static inline void
309 add_vgpr_argument(struct arg_info *info,
310 LLVMTypeRef type,
311 LLVMValueRef *param_ptr)
312 {
313 add_argument(info, type, param_ptr);
314 info->num_vgprs_used += llvm_get_type_size(type) / 4;
315 }
316
317 static inline void
318 add_user_sgpr_array_argument(struct arg_info *info,
319 LLVMTypeRef type,
320 LLVMValueRef *param_ptr)
321 {
322 info->array_params_mask |= (1 << info->count);
323 add_user_sgpr_argument(info, type, param_ptr);
324 }
325
326 static void assign_arguments(LLVMValueRef main_function,
327 struct arg_info *info)
328 {
329 unsigned i;
330 for (i = 0; i < info->count; i++) {
331 if (info->assign[i])
332 *info->assign[i] = LLVMGetParam(main_function, i);
333 }
334 }
335
336 static LLVMValueRef
337 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
338 LLVMBuilderRef builder, LLVMTypeRef *return_types,
339 unsigned num_return_elems,
340 struct arg_info *args,
341 unsigned max_workgroup_size,
342 bool unsafe_math)
343 {
344 LLVMTypeRef main_function_type, ret_type;
345 LLVMBasicBlockRef main_function_body;
346
347 if (num_return_elems)
348 ret_type = LLVMStructTypeInContext(ctx, return_types,
349 num_return_elems, true);
350 else
351 ret_type = LLVMVoidTypeInContext(ctx);
352
353 /* Setup the function */
354 main_function_type =
355 LLVMFunctionType(ret_type, args->types, args->count, 0);
356 LLVMValueRef main_function =
357 LLVMAddFunction(module, "main", main_function_type);
358 main_function_body =
359 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
360 LLVMPositionBuilderAtEnd(builder, main_function_body);
361
362 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
363 for (unsigned i = 0; i < args->sgpr_count; ++i) {
364 if (args->array_params_mask & (1 << i)) {
365 LLVMValueRef P = LLVMGetParam(main_function, i);
366 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
367 ac_add_attr_dereferenceable(P, UINT64_MAX);
368 }
369 else {
370 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
371 }
372 }
373
374 if (max_workgroup_size) {
375 ac_llvm_add_target_dep_function_attr(main_function,
376 "amdgpu-max-work-group-size",
377 max_workgroup_size);
378 }
379 if (unsafe_math) {
380 /* These were copied from some LLVM test. */
381 LLVMAddTargetDependentFunctionAttr(main_function,
382 "less-precise-fpmad",
383 "true");
384 LLVMAddTargetDependentFunctionAttr(main_function,
385 "no-infs-fp-math",
386 "true");
387 LLVMAddTargetDependentFunctionAttr(main_function,
388 "no-nans-fp-math",
389 "true");
390 LLVMAddTargetDependentFunctionAttr(main_function,
391 "unsafe-fp-math",
392 "true");
393 }
394 return main_function;
395 }
396
397 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
398 {
399 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
400 CONST_ADDR_SPACE);
401 }
402
403 static LLVMTypeRef to_integer_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
404 {
405 if (t == ctx->f16 || t == ctx->i16)
406 return ctx->i16;
407 else if (t == ctx->f32 || t == ctx->i32)
408 return ctx->i32;
409 else if (t == ctx->f64 || t == ctx->i64)
410 return ctx->i64;
411 else
412 unreachable("Unhandled integer size");
413 }
414
415 static LLVMTypeRef to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
416 {
417 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
418 LLVMTypeRef elem_type = LLVMGetElementType(t);
419 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
420 LLVMGetVectorSize(t));
421 }
422 return to_integer_type_scalar(ctx, t);
423 }
424
425 static LLVMValueRef to_integer(struct ac_llvm_context *ctx, LLVMValueRef v)
426 {
427 LLVMTypeRef type = LLVMTypeOf(v);
428 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
429 }
430
431 static LLVMTypeRef to_float_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
432 {
433 if (t == ctx->i16 || t == ctx->f16)
434 return ctx->f16;
435 else if (t == ctx->i32 || t == ctx->f32)
436 return ctx->f32;
437 else if (t == ctx->i64 || t == ctx->f64)
438 return ctx->f64;
439 else
440 unreachable("Unhandled float size");
441 }
442
443 static LLVMTypeRef to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
444 {
445 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
446 LLVMTypeRef elem_type = LLVMGetElementType(t);
447 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
448 LLVMGetVectorSize(t));
449 }
450 return to_float_type_scalar(ctx, t);
451 }
452
453 static LLVMValueRef to_float(struct ac_llvm_context *ctx, LLVMValueRef v)
454 {
455 LLVMTypeRef type = LLVMTypeOf(v);
456 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
457 }
458
459 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
460 {
461 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
462 type = LLVMGetElementType(type);
463
464 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
465 return LLVMGetIntTypeWidth(type);
466
467 if (type == ctx->f16)
468 return 16;
469 if (type == ctx->f32)
470 return 32;
471 if (type == ctx->f64)
472 return 64;
473
474 unreachable("Unhandled type kind in get_elem_bits");
475 }
476
477 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
478 LLVMValueRef param, unsigned rshift,
479 unsigned bitwidth)
480 {
481 LLVMValueRef value = param;
482 if (rshift)
483 value = LLVMBuildLShr(ctx->builder, value,
484 LLVMConstInt(ctx->i32, rshift, false), "");
485
486 if (rshift + bitwidth < 32) {
487 unsigned mask = (1 << bitwidth) - 1;
488 value = LLVMBuildAnd(ctx->builder, value,
489 LLVMConstInt(ctx->i32, mask, false), "");
490 }
491 return value;
492 }
493
494 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
495 {
496 switch (ctx->stage) {
497 case MESA_SHADER_TESS_CTRL:
498 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
499 case MESA_SHADER_TESS_EVAL:
500 return ctx->tes_rel_patch_id;
501 break;
502 default:
503 unreachable("Illegal stage");
504 }
505 }
506
507 /* Tessellation shaders pass outputs to the next shader using LDS.
508 *
509 * LS outputs = TCS inputs
510 * TCS outputs = TES inputs
511 *
512 * The LDS layout is:
513 * - TCS inputs for patch 0
514 * - TCS inputs for patch 1
515 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
516 * - ...
517 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
518 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
519 * - TCS outputs for patch 1
520 * - Per-patch TCS outputs for patch 1
521 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
522 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
523 * - ...
524 *
525 * All three shaders VS(LS), TCS, TES share the same LDS space.
526 */
527 static LLVMValueRef
528 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
529 {
530 if (ctx->stage == MESA_SHADER_VERTEX)
531 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
532 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
533 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
534 else {
535 assert(0);
536 return NULL;
537 }
538 }
539
540 static LLVMValueRef
541 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
542 {
543 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
544 }
545
546 static LLVMValueRef
547 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
548 {
549 return LLVMBuildMul(ctx->builder,
550 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
551 LLVMConstInt(ctx->i32, 4, false), "");
552 }
553
554 static LLVMValueRef
555 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
556 {
557 return LLVMBuildMul(ctx->builder,
558 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
559 LLVMConstInt(ctx->i32, 4, false), "");
560 }
561
562 static LLVMValueRef
563 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
564 {
565 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
566 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
567
568 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
569 }
570
571 static LLVMValueRef
572 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
573 {
574 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
575 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
576 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
577
578 return LLVMBuildAdd(ctx->builder, patch0_offset,
579 LLVMBuildMul(ctx->builder, patch_stride,
580 rel_patch_id, ""),
581 "");
582 }
583
584 static LLVMValueRef
585 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
586 {
587 LLVMValueRef patch0_patch_data_offset =
588 get_tcs_out_patch0_patch_data_offset(ctx);
589 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
590 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
591
592 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
593 LLVMBuildMul(ctx->builder, patch_stride,
594 rel_patch_id, ""),
595 "");
596 }
597
598 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
599 {
600 ud_info->sgpr_idx = *sgpr_idx;
601 ud_info->num_sgprs = num_sgprs;
602 ud_info->indirect = false;
603 ud_info->indirect_offset = 0;
604 *sgpr_idx += num_sgprs;
605 }
606
607 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
608 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
609 {
610 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
611 }
612
613
614 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
615 uint32_t indirect_offset)
616 {
617 ud_info->sgpr_idx = sgpr_idx;
618 ud_info->num_sgprs = num_sgprs;
619 ud_info->indirect = true;
620 ud_info->indirect_offset = indirect_offset;
621 }
622
623 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
624 {
625 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
626 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
627 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
628 "tess_lds");
629 }
630
631 struct user_sgpr_info {
632 bool need_ring_offsets;
633 uint8_t sgpr_count;
634 bool indirect_all_descriptor_sets;
635 };
636
637 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
638 struct user_sgpr_info *user_sgpr_info)
639 {
640 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
641
642 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
643 if (ctx->stage == MESA_SHADER_GEOMETRY ||
644 ctx->stage == MESA_SHADER_VERTEX ||
645 ctx->stage == MESA_SHADER_TESS_CTRL ||
646 ctx->stage == MESA_SHADER_TESS_EVAL ||
647 ctx->is_gs_copy_shader)
648 user_sgpr_info->need_ring_offsets = true;
649
650 if (ctx->stage == MESA_SHADER_FRAGMENT &&
651 ctx->shader_info->info.ps.needs_sample_positions)
652 user_sgpr_info->need_ring_offsets = true;
653
654 /* 2 user sgprs will nearly always be allocated for scratch/rings */
655 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
656 user_sgpr_info->sgpr_count += 2;
657 }
658
659 switch (ctx->stage) {
660 case MESA_SHADER_COMPUTE:
661 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
662 break;
663 case MESA_SHADER_FRAGMENT:
664 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
665 break;
666 case MESA_SHADER_VERTEX:
667 if (!ctx->is_gs_copy_shader) {
668 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
669 if (ctx->shader_info->info.vs.needs_draw_id) {
670 user_sgpr_info->sgpr_count += 3;
671 } else {
672 user_sgpr_info->sgpr_count += 2;
673 }
674 }
675 if (ctx->options->key.vs.as_ls)
676 user_sgpr_info->sgpr_count++;
677 break;
678 case MESA_SHADER_TESS_CTRL:
679 user_sgpr_info->sgpr_count += 4;
680 break;
681 case MESA_SHADER_TESS_EVAL:
682 user_sgpr_info->sgpr_count += 1;
683 break;
684 case MESA_SHADER_GEOMETRY:
685 user_sgpr_info->sgpr_count += 2;
686 break;
687 default:
688 break;
689 }
690
691 if (ctx->shader_info->info.needs_push_constants)
692 user_sgpr_info->sgpr_count += 2;
693
694 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
695 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
696 user_sgpr_info->sgpr_count += 2;
697 user_sgpr_info->indirect_all_descriptor_sets = true;
698 } else {
699 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
700 }
701 }
702
703 static void create_function(struct nir_to_llvm_context *ctx)
704 {
705 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
706 uint8_t user_sgpr_idx;
707 struct user_sgpr_info user_sgpr_info;
708 struct arg_info args = {};
709 LLVMValueRef desc_sets;
710
711 allocate_user_sgprs(ctx, &user_sgpr_info);
712 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
713 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
714 }
715
716 /* 1 for each descriptor set */
717 if (!user_sgpr_info.indirect_all_descriptor_sets) {
718 for (unsigned i = 0; i < num_sets; ++i) {
719 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
720 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
721 }
722 }
723 } else
724 add_user_sgpr_array_argument(&args, const_array(const_array(ctx->i8, 1024 * 1024), 32), &desc_sets);
725
726 if (ctx->shader_info->info.needs_push_constants) {
727 /* 1 for push constants and dynamic descriptors */
728 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
729 }
730
731 switch (ctx->stage) {
732 case MESA_SHADER_COMPUTE:
733 if (ctx->shader_info->info.cs.grid_components_used)
734 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
735 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
736 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
737 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
738 break;
739 case MESA_SHADER_VERTEX:
740 if (!ctx->is_gs_copy_shader) {
741 if (ctx->shader_info->info.vs.has_vertex_buffers)
742 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
743 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.base_vertex); // base vertex
744 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.start_instance);// start instance
745 if (ctx->shader_info->info.vs.needs_draw_id)
746 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.draw_id); // draw id
747 }
748 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
749 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
750 if (ctx->options->key.vs.as_es)
751 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
752 else if (ctx->options->key.vs.as_ls)
753 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
754 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
755 if (!ctx->is_gs_copy_shader) {
756 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
757 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
758 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
759 }
760 break;
761 case MESA_SHADER_TESS_CTRL:
762 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
763 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
764 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
765 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
766 if (ctx->shader_info->info.needs_multiview_view_index)
767 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
768 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
769 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
770 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
771 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
772 break;
773 case MESA_SHADER_TESS_EVAL:
774 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
775 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
776 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
777 if (ctx->options->key.tes.as_es) {
778 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
779 add_sgpr_argument(&args, ctx->i32, NULL); //
780 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
781 } else {
782 add_sgpr_argument(&args, ctx->i32, NULL); //
783 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
784 }
785 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
786 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
787 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
788 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
789 break;
790 case MESA_SHADER_GEOMETRY:
791 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
792 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
793 if (ctx->shader_info->info.needs_multiview_view_index)
794 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
795 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
796 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
797 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
798 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
799 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
800 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
801 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
802 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
803 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
804 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
805 break;
806 case MESA_SHADER_FRAGMENT:
807 if (ctx->shader_info->info.ps.needs_sample_positions)
808 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
809 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
810 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
811 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
812 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
813 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
814 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
815 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
816 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
817 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
818 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[0]); /* pos x float */
819 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[1]); /* pos y float */
820 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[2]); /* pos z float */
821 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[3]); /* pos w float */
822 add_vgpr_argument(&args, ctx->i32, &ctx->abi.front_face); /* front face */
823 add_vgpr_argument(&args, ctx->i32, &ctx->abi.ancillary); /* ancillary */
824 add_vgpr_argument(&args, ctx->i32, &ctx->abi.sample_coverage); /* sample coverage */
825 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
826 break;
827 default:
828 unreachable("Shader stage not implemented");
829 }
830
831 ctx->main_function = create_llvm_function(
832 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
833 ctx->max_workgroup_size,
834 ctx->options->unsafe_math);
835 set_llvm_calling_convention(ctx->main_function, ctx->stage);
836
837
838 ctx->shader_info->num_input_vgprs = 0;
839 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs =
840 ctx->options->supports_spill ? 2 : 0;
841
842 ctx->shader_info->num_user_sgprs += args.num_user_sgprs_used;
843 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
844
845 if (ctx->stage != MESA_SHADER_FRAGMENT)
846 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
847
848 assign_arguments(ctx->main_function, &args);
849
850 user_sgpr_idx = 0;
851
852 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
853 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
854 if (ctx->options->supports_spill) {
855 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
856 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
857 NULL, 0, AC_FUNC_ATTR_READNONE);
858 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
859 const_array(ctx->v4i32, 16), "");
860 }
861 }
862
863 if (!user_sgpr_info.indirect_all_descriptor_sets) {
864 for (unsigned i = 0; i < num_sets; ++i) {
865 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
866 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
867 } else
868 ctx->descriptor_sets[i] = NULL;
869 }
870 } else {
871 uint32_t desc_sgpr_idx = user_sgpr_idx;
872 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
873
874 for (unsigned i = 0; i < num_sets; ++i) {
875 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
876 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
877 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
878
879 } else
880 ctx->descriptor_sets[i] = NULL;
881 }
882 ctx->shader_info->need_indirect_descriptor_sets = true;
883 }
884
885 if (ctx->shader_info->info.needs_push_constants) {
886 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
887 }
888
889 switch (ctx->stage) {
890 case MESA_SHADER_COMPUTE:
891 if (ctx->shader_info->info.cs.grid_components_used) {
892 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
893 }
894 break;
895 case MESA_SHADER_VERTEX:
896 if (!ctx->is_gs_copy_shader) {
897 if (ctx->shader_info->info.vs.has_vertex_buffers) {
898 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
899 }
900 unsigned vs_num = 2;
901 if (ctx->shader_info->info.vs.needs_draw_id)
902 vs_num++;
903
904 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
905 }
906 if (ctx->view_index)
907 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
908 if (ctx->options->key.vs.as_ls) {
909 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
910 }
911 if (ctx->options->key.vs.as_ls)
912 declare_tess_lds(ctx);
913 break;
914 case MESA_SHADER_TESS_CTRL:
915 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
916 if (ctx->view_index)
917 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
918 declare_tess_lds(ctx);
919 break;
920 case MESA_SHADER_TESS_EVAL:
921 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
922 if (ctx->view_index)
923 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
924 break;
925 case MESA_SHADER_GEOMETRY:
926 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
927 if (ctx->view_index)
928 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
929 break;
930 case MESA_SHADER_FRAGMENT:
931 if (ctx->shader_info->info.ps.needs_sample_positions) {
932 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
933 }
934 break;
935 default:
936 unreachable("Shader stage not implemented");
937 }
938 }
939
940 static void setup_types(struct nir_to_llvm_context *ctx)
941 {
942 LLVMValueRef args[4];
943
944 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
945 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
946 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
947 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
948 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
949 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
950 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
951 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
952 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
953 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
954 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
955 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
956 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
957 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
958 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
959
960 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
961 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
962 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
963 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
964 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
965 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
966
967 args[0] = ctx->f32zero;
968 args[1] = ctx->f32zero;
969 args[2] = ctx->f32zero;
970 args[3] = ctx->f32one;
971 ctx->v4f32empty = LLVMConstVector(args, 4);
972
973 ctx->uniform_md_kind =
974 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
975 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
976
977 args[0] = LLVMConstReal(ctx->f32, 2.5);
978 }
979
980 static int get_llvm_num_components(LLVMValueRef value)
981 {
982 LLVMTypeRef type = LLVMTypeOf(value);
983 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
984 ? LLVMGetVectorSize(type)
985 : 1;
986 return num_components;
987 }
988
989 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
990 LLVMValueRef value,
991 int index)
992 {
993 int count = get_llvm_num_components(value);
994
995 assert(index < count);
996 if (count == 1)
997 return value;
998
999 return LLVMBuildExtractElement(ac->builder, value,
1000 LLVMConstInt(ac->i32, index, false), "");
1001 }
1002
1003 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1004 LLVMValueRef value, unsigned count)
1005 {
1006 unsigned num_components = get_llvm_num_components(value);
1007 if (count == num_components)
1008 return value;
1009
1010 LLVMValueRef masks[] = {
1011 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1012 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1013
1014 if (count == 1)
1015 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1016 "");
1017
1018 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1019 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1020 }
1021
1022 static void
1023 build_store_values_extended(struct ac_llvm_context *ac,
1024 LLVMValueRef *values,
1025 unsigned value_count,
1026 unsigned value_stride,
1027 LLVMValueRef vec)
1028 {
1029 LLVMBuilderRef builder = ac->builder;
1030 unsigned i;
1031
1032 for (i = 0; i < value_count; i++) {
1033 LLVMValueRef ptr = values[i * value_stride];
1034 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1035 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1036 LLVMBuildStore(builder, value, ptr);
1037 }
1038 }
1039
1040 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1041 const nir_ssa_def *def)
1042 {
1043 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1044 if (def->num_components > 1) {
1045 type = LLVMVectorType(type, def->num_components);
1046 }
1047 return type;
1048 }
1049
1050 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1051 {
1052 assert(src.is_ssa);
1053 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1054 return (LLVMValueRef)entry->data;
1055 }
1056
1057
1058 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1059 const struct nir_block *b)
1060 {
1061 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1062 return (LLVMBasicBlockRef)entry->data;
1063 }
1064
1065 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1066 nir_alu_src src,
1067 unsigned num_components)
1068 {
1069 LLVMValueRef value = get_src(ctx, src.src);
1070 bool need_swizzle = false;
1071
1072 assert(value);
1073 LLVMTypeRef type = LLVMTypeOf(value);
1074 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1075 ? LLVMGetVectorSize(type)
1076 : 1;
1077
1078 for (unsigned i = 0; i < num_components; ++i) {
1079 assert(src.swizzle[i] < src_components);
1080 if (src.swizzle[i] != i)
1081 need_swizzle = true;
1082 }
1083
1084 if (need_swizzle || num_components != src_components) {
1085 LLVMValueRef masks[] = {
1086 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1087 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1088 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1089 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1090
1091 if (src_components > 1 && num_components == 1) {
1092 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1093 masks[0], "");
1094 } else if (src_components == 1 && num_components > 1) {
1095 LLVMValueRef values[] = {value, value, value, value};
1096 value = ac_build_gather_values(&ctx->ac, values, num_components);
1097 } else {
1098 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1099 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1100 swizzle, "");
1101 }
1102 }
1103 assert(!src.negate);
1104 assert(!src.abs);
1105 return value;
1106 }
1107
1108 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1109 LLVMIntPredicate pred, LLVMValueRef src0,
1110 LLVMValueRef src1)
1111 {
1112 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1113 return LLVMBuildSelect(ctx->builder, result,
1114 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1115 LLVMConstInt(ctx->i32, 0, false), "");
1116 }
1117
1118 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1119 LLVMRealPredicate pred, LLVMValueRef src0,
1120 LLVMValueRef src1)
1121 {
1122 LLVMValueRef result;
1123 src0 = to_float(ctx, src0);
1124 src1 = to_float(ctx, src1);
1125 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1126 return LLVMBuildSelect(ctx->builder, result,
1127 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1128 LLVMConstInt(ctx->i32, 0, false), "");
1129 }
1130
1131 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1132 const char *intrin,
1133 LLVMTypeRef result_type,
1134 LLVMValueRef src0)
1135 {
1136 char name[64];
1137 LLVMValueRef params[] = {
1138 to_float(ctx, src0),
1139 };
1140
1141 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1142 get_elem_bits(ctx, result_type));
1143 assert(length < sizeof(name));
1144 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1145 }
1146
1147 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1148 const char *intrin,
1149 LLVMTypeRef result_type,
1150 LLVMValueRef src0, LLVMValueRef src1)
1151 {
1152 char name[64];
1153 LLVMValueRef params[] = {
1154 to_float(ctx, src0),
1155 to_float(ctx, src1),
1156 };
1157
1158 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1159 get_elem_bits(ctx, result_type));
1160 assert(length < sizeof(name));
1161 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1162 }
1163
1164 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1165 const char *intrin,
1166 LLVMTypeRef result_type,
1167 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1168 {
1169 char name[64];
1170 LLVMValueRef params[] = {
1171 to_float(ctx, src0),
1172 to_float(ctx, src1),
1173 to_float(ctx, src2),
1174 };
1175
1176 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1177 get_elem_bits(ctx, result_type));
1178 assert(length < sizeof(name));
1179 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1180 }
1181
1182 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1183 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1184 {
1185 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1186 ctx->i32_0, "");
1187 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1188 }
1189
1190 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1191 LLVMValueRef src0)
1192 {
1193 LLVMValueRef params[2] = {
1194 src0,
1195
1196 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1197 * add special code to check for x=0. The reason is that
1198 * the LLVM behavior for x=0 is different from what we
1199 * need here.
1200 *
1201 * The hardware already implements the correct behavior.
1202 */
1203 LLVMConstInt(ctx->i1, 1, false),
1204 };
1205
1206 LLVMValueRef lsb = ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32,
1207 params, 2,
1208 AC_FUNC_ATTR_READNONE);
1209
1210 /* TODO: We need an intrinsic to skip this conditional. */
1211 /* Check for zero: */
1212 return LLVMBuildSelect(ctx->builder, LLVMBuildICmp(ctx->builder,
1213 LLVMIntEQ, src0,
1214 ctx->i32_0, ""),
1215 LLVMConstInt(ctx->i32, -1, 0), lsb, "");
1216 }
1217
1218 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1219 LLVMValueRef src0)
1220 {
1221 return ac_build_imsb(ctx, src0, ctx->i32);
1222 }
1223
1224 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1225 LLVMValueRef src0)
1226 {
1227 return ac_build_umsb(ctx, src0, ctx->i32);
1228 }
1229
1230 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1231 LLVMIntPredicate pred,
1232 LLVMValueRef src0, LLVMValueRef src1)
1233 {
1234 return LLVMBuildSelect(ctx->builder,
1235 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1236 src0,
1237 src1, "");
1238
1239 }
1240 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1241 LLVMValueRef src0)
1242 {
1243 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1244 LLVMBuildNeg(ctx->builder, src0, ""));
1245 }
1246
1247 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1248 LLVMValueRef src0)
1249 {
1250 LLVMValueRef cmp, val;
1251
1252 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1253 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1254 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1255 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1256 return val;
1257 }
1258
1259 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1260 LLVMValueRef src0)
1261 {
1262 LLVMValueRef cmp, val;
1263
1264 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1265 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1266 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1267 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1268 return val;
1269 }
1270
1271 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1272 LLVMValueRef src0)
1273 {
1274 const char *intr = "llvm.floor.f32";
1275 LLVMValueRef fsrc0 = to_float(ctx, src0);
1276 LLVMValueRef params[] = {
1277 fsrc0,
1278 };
1279 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1280 ctx->f32, params, 1,
1281 AC_FUNC_ATTR_READNONE);
1282 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1283 }
1284
1285 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1286 const char *intrin,
1287 LLVMValueRef src0, LLVMValueRef src1)
1288 {
1289 LLVMTypeRef ret_type;
1290 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1291 LLVMValueRef res;
1292 LLVMValueRef params[] = { src0, src1 };
1293 ret_type = LLVMStructTypeInContext(ctx->context, types,
1294 2, true);
1295
1296 res = ac_build_intrinsic(ctx, intrin, ret_type,
1297 params, 2, AC_FUNC_ATTR_READNONE);
1298
1299 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1300 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1301 return res;
1302 }
1303
1304 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1305 LLVMValueRef src0)
1306 {
1307 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1308 }
1309
1310 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1311 LLVMValueRef src0)
1312 {
1313 src0 = to_float(ctx, src0);
1314 return LLVMBuildSExt(ctx->builder,
1315 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1316 ctx->i32, "");
1317 }
1318
1319 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1320 LLVMValueRef src0)
1321 {
1322 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1323 }
1324
1325 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1326 LLVMValueRef src0)
1327 {
1328 return LLVMBuildSExt(ctx->builder,
1329 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1330 ctx->i32, "");
1331 }
1332
1333 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1334 LLVMValueRef src0)
1335 {
1336 LLVMValueRef result;
1337 LLVMValueRef cond = NULL;
1338
1339 src0 = to_float(&ctx->ac, src0);
1340 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1341
1342 if (ctx->options->chip_class >= VI) {
1343 LLVMValueRef args[2];
1344 /* Check if the result is a denormal - and flush to 0 if so. */
1345 args[0] = result;
1346 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1347 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1348 }
1349
1350 /* need to convert back up to f32 */
1351 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1352
1353 if (ctx->options->chip_class >= VI)
1354 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1355 else {
1356 /* for SI/CIK */
1357 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1358 * so compare the result and flush to 0 if it's smaller.
1359 */
1360 LLVMValueRef temp, cond2;
1361 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1362 ctx->f32, result);
1363 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1364 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1365 temp, "");
1366 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1367 temp, ctx->f32zero, "");
1368 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1369 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1370 }
1371 return result;
1372 }
1373
1374 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1375 LLVMValueRef src0, LLVMValueRef src1)
1376 {
1377 LLVMValueRef dst64, result;
1378 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1379 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1380
1381 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1382 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1383 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1384 return result;
1385 }
1386
1387 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1388 LLVMValueRef src0, LLVMValueRef src1)
1389 {
1390 LLVMValueRef dst64, result;
1391 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1392 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1393
1394 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1395 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1396 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1397 return result;
1398 }
1399
1400 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1401 bool is_signed,
1402 const LLVMValueRef srcs[3])
1403 {
1404 LLVMValueRef result;
1405 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1406
1407 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1408 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1409 return result;
1410 }
1411
1412 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1413 LLVMValueRef src0, LLVMValueRef src1,
1414 LLVMValueRef src2, LLVMValueRef src3)
1415 {
1416 LLVMValueRef bfi_args[3], result;
1417
1418 bfi_args[0] = LLVMBuildShl(ctx->builder,
1419 LLVMBuildSub(ctx->builder,
1420 LLVMBuildShl(ctx->builder,
1421 ctx->i32_1,
1422 src3, ""),
1423 ctx->i32_1, ""),
1424 src2, "");
1425 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1426 bfi_args[2] = src0;
1427
1428 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1429
1430 /* Calculate:
1431 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1432 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1433 */
1434 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1435 LLVMBuildAnd(ctx->builder, bfi_args[0],
1436 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1437
1438 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1439 return result;
1440 }
1441
1442 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1443 LLVMValueRef src0)
1444 {
1445 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1446 int i;
1447 LLVMValueRef comp[2];
1448
1449 src0 = to_float(ctx, src0);
1450 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1451 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1452 for (i = 0; i < 2; i++) {
1453 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1454 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1455 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1456 }
1457
1458 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1459 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1460
1461 return comp[0];
1462 }
1463
1464 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1465 LLVMValueRef src0)
1466 {
1467 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1468 LLVMValueRef temps[2], result, val;
1469 int i;
1470
1471 for (i = 0; i < 2; i++) {
1472 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1473 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1474 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1475 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1476 }
1477
1478 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1479 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1480 ctx->i32_0, "");
1481 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1482 ctx->i32_1, "");
1483 return result;
1484 }
1485
1486 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1487 nir_op op,
1488 LLVMValueRef src0)
1489 {
1490 unsigned mask;
1491 int idx;
1492 LLVMValueRef result;
1493 bool has_ds_bpermute = ctx->abi->chip_class >= VI;
1494
1495 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1496 mask = AC_TID_MASK_LEFT;
1497 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1498 mask = AC_TID_MASK_TOP;
1499 else
1500 mask = AC_TID_MASK_TOP_LEFT;
1501
1502 /* for DDX we want to next X pixel, DDY next Y pixel. */
1503 if (op == nir_op_fddx_fine ||
1504 op == nir_op_fddx_coarse ||
1505 op == nir_op_fddx)
1506 idx = 1;
1507 else
1508 idx = 2;
1509
1510 result = ac_build_ddxy(&ctx->ac, has_ds_bpermute,
1511 mask, idx,
1512 src0);
1513 return result;
1514 }
1515
1516 /*
1517 * this takes an I,J coordinate pair,
1518 * and works out the X and Y derivatives.
1519 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1520 */
1521 static LLVMValueRef emit_ddxy_interp(
1522 struct ac_nir_context *ctx,
1523 LLVMValueRef interp_ij)
1524 {
1525 LLVMValueRef result[4], a;
1526 unsigned i;
1527
1528 for (i = 0; i < 2; i++) {
1529 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1530 LLVMConstInt(ctx->ac.i32, i, false), "");
1531 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1532 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1533 }
1534 return ac_build_gather_values(&ctx->ac, result, 4);
1535 }
1536
1537 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1538 {
1539 LLVMValueRef src[4], result = NULL;
1540 unsigned num_components = instr->dest.dest.ssa.num_components;
1541 unsigned src_components;
1542 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1543
1544 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1545 switch (instr->op) {
1546 case nir_op_vec2:
1547 case nir_op_vec3:
1548 case nir_op_vec4:
1549 src_components = 1;
1550 break;
1551 case nir_op_pack_half_2x16:
1552 src_components = 2;
1553 break;
1554 case nir_op_unpack_half_2x16:
1555 src_components = 1;
1556 break;
1557 default:
1558 src_components = num_components;
1559 break;
1560 }
1561 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1562 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1563
1564 switch (instr->op) {
1565 case nir_op_fmov:
1566 case nir_op_imov:
1567 result = src[0];
1568 break;
1569 case nir_op_fneg:
1570 src[0] = to_float(&ctx->ac, src[0]);
1571 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1572 break;
1573 case nir_op_ineg:
1574 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1575 break;
1576 case nir_op_inot:
1577 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1578 break;
1579 case nir_op_iadd:
1580 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1581 break;
1582 case nir_op_fadd:
1583 src[0] = to_float(&ctx->ac, src[0]);
1584 src[1] = to_float(&ctx->ac, src[1]);
1585 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1586 break;
1587 case nir_op_fsub:
1588 src[0] = to_float(&ctx->ac, src[0]);
1589 src[1] = to_float(&ctx->ac, src[1]);
1590 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1591 break;
1592 case nir_op_isub:
1593 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1594 break;
1595 case nir_op_imul:
1596 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1597 break;
1598 case nir_op_imod:
1599 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1600 break;
1601 case nir_op_umod:
1602 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1603 break;
1604 case nir_op_fmod:
1605 src[0] = to_float(&ctx->ac, src[0]);
1606 src[1] = to_float(&ctx->ac, src[1]);
1607 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1608 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1609 to_float_type(&ctx->ac, def_type), result);
1610 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1611 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1612 break;
1613 case nir_op_frem:
1614 src[0] = to_float(&ctx->ac, src[0]);
1615 src[1] = to_float(&ctx->ac, src[1]);
1616 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1617 break;
1618 case nir_op_irem:
1619 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1620 break;
1621 case nir_op_idiv:
1622 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1623 break;
1624 case nir_op_udiv:
1625 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1626 break;
1627 case nir_op_fmul:
1628 src[0] = to_float(&ctx->ac, src[0]);
1629 src[1] = to_float(&ctx->ac, src[1]);
1630 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1631 break;
1632 case nir_op_fdiv:
1633 src[0] = to_float(&ctx->ac, src[0]);
1634 src[1] = to_float(&ctx->ac, src[1]);
1635 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1636 break;
1637 case nir_op_frcp:
1638 src[0] = to_float(&ctx->ac, src[0]);
1639 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1640 break;
1641 case nir_op_iand:
1642 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1643 break;
1644 case nir_op_ior:
1645 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1646 break;
1647 case nir_op_ixor:
1648 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1649 break;
1650 case nir_op_ishl:
1651 result = LLVMBuildShl(ctx->ac.builder, src[0],
1652 LLVMBuildZExt(ctx->ac.builder, src[1],
1653 LLVMTypeOf(src[0]), ""),
1654 "");
1655 break;
1656 case nir_op_ishr:
1657 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1658 LLVMBuildZExt(ctx->ac.builder, src[1],
1659 LLVMTypeOf(src[0]), ""),
1660 "");
1661 break;
1662 case nir_op_ushr:
1663 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1664 LLVMBuildZExt(ctx->ac.builder, src[1],
1665 LLVMTypeOf(src[0]), ""),
1666 "");
1667 break;
1668 case nir_op_ilt:
1669 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1670 break;
1671 case nir_op_ine:
1672 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1673 break;
1674 case nir_op_ieq:
1675 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1676 break;
1677 case nir_op_ige:
1678 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1679 break;
1680 case nir_op_ult:
1681 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1682 break;
1683 case nir_op_uge:
1684 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1685 break;
1686 case nir_op_feq:
1687 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1688 break;
1689 case nir_op_fne:
1690 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1691 break;
1692 case nir_op_flt:
1693 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1694 break;
1695 case nir_op_fge:
1696 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1697 break;
1698 case nir_op_fabs:
1699 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1700 to_float_type(&ctx->ac, def_type), src[0]);
1701 break;
1702 case nir_op_iabs:
1703 result = emit_iabs(&ctx->ac, src[0]);
1704 break;
1705 case nir_op_imax:
1706 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1707 break;
1708 case nir_op_imin:
1709 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1710 break;
1711 case nir_op_umax:
1712 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1713 break;
1714 case nir_op_umin:
1715 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1716 break;
1717 case nir_op_isign:
1718 result = emit_isign(&ctx->ac, src[0]);
1719 break;
1720 case nir_op_fsign:
1721 src[0] = to_float(&ctx->ac, src[0]);
1722 result = emit_fsign(&ctx->ac, src[0]);
1723 break;
1724 case nir_op_ffloor:
1725 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1726 to_float_type(&ctx->ac, def_type), src[0]);
1727 break;
1728 case nir_op_ftrunc:
1729 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1730 to_float_type(&ctx->ac, def_type), src[0]);
1731 break;
1732 case nir_op_fceil:
1733 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1734 to_float_type(&ctx->ac, def_type), src[0]);
1735 break;
1736 case nir_op_fround_even:
1737 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1738 to_float_type(&ctx->ac, def_type),src[0]);
1739 break;
1740 case nir_op_ffract:
1741 result = emit_ffract(&ctx->ac, src[0]);
1742 break;
1743 case nir_op_fsin:
1744 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1745 to_float_type(&ctx->ac, def_type), src[0]);
1746 break;
1747 case nir_op_fcos:
1748 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1749 to_float_type(&ctx->ac, def_type), src[0]);
1750 break;
1751 case nir_op_fsqrt:
1752 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1753 to_float_type(&ctx->ac, def_type), src[0]);
1754 break;
1755 case nir_op_fexp2:
1756 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1757 to_float_type(&ctx->ac, def_type), src[0]);
1758 break;
1759 case nir_op_flog2:
1760 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1761 to_float_type(&ctx->ac, def_type), src[0]);
1762 break;
1763 case nir_op_frsq:
1764 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1765 to_float_type(&ctx->ac, def_type), src[0]);
1766 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1767 break;
1768 case nir_op_fpow:
1769 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1770 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1771 break;
1772 case nir_op_fmax:
1773 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1774 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1775 if (instr->dest.dest.ssa.bit_size == 32)
1776 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1777 to_float_type(&ctx->ac, def_type),
1778 result);
1779 break;
1780 case nir_op_fmin:
1781 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1782 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1783 if (instr->dest.dest.ssa.bit_size == 32)
1784 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1785 to_float_type(&ctx->ac, def_type),
1786 result);
1787 break;
1788 case nir_op_ffma:
1789 result = emit_intrin_3f_param(&ctx->ac, "llvm.fma",
1790 to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1791 break;
1792 case nir_op_ibitfield_extract:
1793 result = emit_bitfield_extract(&ctx->ac, true, src);
1794 break;
1795 case nir_op_ubitfield_extract:
1796 result = emit_bitfield_extract(&ctx->ac, false, src);
1797 break;
1798 case nir_op_bitfield_insert:
1799 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1800 break;
1801 case nir_op_bitfield_reverse:
1802 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1803 break;
1804 case nir_op_bit_count:
1805 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1806 break;
1807 case nir_op_vec2:
1808 case nir_op_vec3:
1809 case nir_op_vec4:
1810 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1811 src[i] = to_integer(&ctx->ac, src[i]);
1812 result = ac_build_gather_values(&ctx->ac, src, num_components);
1813 break;
1814 case nir_op_f2i32:
1815 case nir_op_f2i64:
1816 src[0] = to_float(&ctx->ac, src[0]);
1817 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1818 break;
1819 case nir_op_f2u32:
1820 case nir_op_f2u64:
1821 src[0] = to_float(&ctx->ac, src[0]);
1822 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1823 break;
1824 case nir_op_i2f32:
1825 case nir_op_i2f64:
1826 src[0] = to_integer(&ctx->ac, src[0]);
1827 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1828 break;
1829 case nir_op_u2f32:
1830 case nir_op_u2f64:
1831 src[0] = to_integer(&ctx->ac, src[0]);
1832 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1833 break;
1834 case nir_op_f2f64:
1835 result = LLVMBuildFPExt(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1836 break;
1837 case nir_op_f2f32:
1838 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1839 break;
1840 case nir_op_u2u32:
1841 case nir_op_u2u64:
1842 src[0] = to_integer(&ctx->ac, src[0]);
1843 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1844 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1845 else
1846 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1847 break;
1848 case nir_op_i2i32:
1849 case nir_op_i2i64:
1850 src[0] = to_integer(&ctx->ac, src[0]);
1851 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1852 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1853 else
1854 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1855 break;
1856 case nir_op_bcsel:
1857 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1858 break;
1859 case nir_op_find_lsb:
1860 src[0] = to_integer(&ctx->ac, src[0]);
1861 result = emit_find_lsb(&ctx->ac, src[0]);
1862 break;
1863 case nir_op_ufind_msb:
1864 src[0] = to_integer(&ctx->ac, src[0]);
1865 result = emit_ufind_msb(&ctx->ac, src[0]);
1866 break;
1867 case nir_op_ifind_msb:
1868 src[0] = to_integer(&ctx->ac, src[0]);
1869 result = emit_ifind_msb(&ctx->ac, src[0]);
1870 break;
1871 case nir_op_uadd_carry:
1872 src[0] = to_integer(&ctx->ac, src[0]);
1873 src[1] = to_integer(&ctx->ac, src[1]);
1874 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1875 break;
1876 case nir_op_usub_borrow:
1877 src[0] = to_integer(&ctx->ac, src[0]);
1878 src[1] = to_integer(&ctx->ac, src[1]);
1879 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1880 break;
1881 case nir_op_b2f:
1882 result = emit_b2f(&ctx->ac, src[0]);
1883 break;
1884 case nir_op_f2b:
1885 result = emit_f2b(&ctx->ac, src[0]);
1886 break;
1887 case nir_op_b2i:
1888 result = emit_b2i(&ctx->ac, src[0]);
1889 break;
1890 case nir_op_i2b:
1891 src[0] = to_integer(&ctx->ac, src[0]);
1892 result = emit_i2b(&ctx->ac, src[0]);
1893 break;
1894 case nir_op_fquantize2f16:
1895 result = emit_f2f16(ctx->nctx, src[0]);
1896 break;
1897 case nir_op_umul_high:
1898 src[0] = to_integer(&ctx->ac, src[0]);
1899 src[1] = to_integer(&ctx->ac, src[1]);
1900 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1901 break;
1902 case nir_op_imul_high:
1903 src[0] = to_integer(&ctx->ac, src[0]);
1904 src[1] = to_integer(&ctx->ac, src[1]);
1905 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1906 break;
1907 case nir_op_pack_half_2x16:
1908 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1909 break;
1910 case nir_op_unpack_half_2x16:
1911 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1912 break;
1913 case nir_op_fddx:
1914 case nir_op_fddy:
1915 case nir_op_fddx_fine:
1916 case nir_op_fddy_fine:
1917 case nir_op_fddx_coarse:
1918 case nir_op_fddy_coarse:
1919 result = emit_ddxy(ctx, instr->op, src[0]);
1920 break;
1921
1922 case nir_op_unpack_64_2x32_split_x: {
1923 assert(instr->src[0].src.ssa->num_components == 1);
1924 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1925 LLVMVectorType(ctx->ac.i32, 2),
1926 "");
1927 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1928 ctx->ac.i32_0, "");
1929 break;
1930 }
1931
1932 case nir_op_unpack_64_2x32_split_y: {
1933 assert(instr->src[0].src.ssa->num_components == 1);
1934 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1935 LLVMVectorType(ctx->ac.i32, 2),
1936 "");
1937 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1938 ctx->ac.i32_1, "");
1939 break;
1940 }
1941
1942 case nir_op_pack_64_2x32_split: {
1943 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
1944 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1945 src[0], ctx->ac.i32_0, "");
1946 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1947 src[1], ctx->ac.i32_1, "");
1948 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1949 break;
1950 }
1951
1952 default:
1953 fprintf(stderr, "Unknown NIR alu instr: ");
1954 nir_print_instr(&instr->instr, stderr);
1955 fprintf(stderr, "\n");
1956 abort();
1957 }
1958
1959 if (result) {
1960 assert(instr->dest.dest.is_ssa);
1961 result = to_integer(&ctx->ac, result);
1962 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1963 result);
1964 }
1965 }
1966
1967 static void visit_load_const(struct ac_nir_context *ctx,
1968 const nir_load_const_instr *instr)
1969 {
1970 LLVMValueRef values[4], value = NULL;
1971 LLVMTypeRef element_type =
1972 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1973
1974 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1975 switch (instr->def.bit_size) {
1976 case 32:
1977 values[i] = LLVMConstInt(element_type,
1978 instr->value.u32[i], false);
1979 break;
1980 case 64:
1981 values[i] = LLVMConstInt(element_type,
1982 instr->value.u64[i], false);
1983 break;
1984 default:
1985 fprintf(stderr,
1986 "unsupported nir load_const bit_size: %d\n",
1987 instr->def.bit_size);
1988 abort();
1989 }
1990 }
1991 if (instr->def.num_components > 1) {
1992 value = LLVMConstVector(values, instr->def.num_components);
1993 } else
1994 value = values[0];
1995
1996 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1997 }
1998
1999 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2000 LLVMTypeRef type)
2001 {
2002 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2003 return LLVMBuildBitCast(ctx->builder, ptr,
2004 LLVMPointerType(type, addr_space), "");
2005 }
2006
2007 static LLVMValueRef
2008 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2009 {
2010 LLVMValueRef size =
2011 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2012 LLVMConstInt(ctx->ac.i32, 2, false), "");
2013
2014 /* VI only */
2015 if (ctx->abi->chip_class >= VI && in_elements) {
2016 /* On VI, the descriptor contains the size in bytes,
2017 * but TXQ must return the size in elements.
2018 * The stride is always non-zero for resources using TXQ.
2019 */
2020 LLVMValueRef stride =
2021 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2022 LLVMConstInt(ctx->ac.i32, 1, false), "");
2023 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2024 LLVMConstInt(ctx->ac.i32, 16, false), "");
2025 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2026 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2027
2028 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2029 }
2030 return size;
2031 }
2032
2033 /**
2034 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2035 * intrinsic names).
2036 */
2037 static void build_int_type_name(
2038 LLVMTypeRef type,
2039 char *buf, unsigned bufsize)
2040 {
2041 assert(bufsize >= 6);
2042
2043 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2044 snprintf(buf, bufsize, "v%ui32",
2045 LLVMGetVectorSize(type));
2046 else
2047 strcpy(buf, "i32");
2048 }
2049
2050 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2051 struct ac_image_args *args,
2052 const nir_tex_instr *instr)
2053 {
2054 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2055 LLVMValueRef coord = args->addr;
2056 LLVMValueRef half_texel[2];
2057 LLVMValueRef compare_cube_wa = NULL;
2058 LLVMValueRef result;
2059 int c;
2060 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2061
2062 //TODO Rect
2063 {
2064 struct ac_image_args txq_args = { 0 };
2065
2066 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2067 txq_args.opcode = ac_image_get_resinfo;
2068 txq_args.dmask = 0xf;
2069 txq_args.addr = ctx->i32_0;
2070 txq_args.resource = args->resource;
2071 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2072
2073 for (c = 0; c < 2; c++) {
2074 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2075 LLVMConstInt(ctx->i32, c, false), "");
2076 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2077 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2078 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2079 LLVMConstReal(ctx->f32, -0.5), "");
2080 }
2081 }
2082
2083 LLVMValueRef orig_coords = args->addr;
2084
2085 for (c = 0; c < 2; c++) {
2086 LLVMValueRef tmp;
2087 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2088 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2089 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2090 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2091 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2092 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2093 }
2094
2095
2096 /*
2097 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2098 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2099 * workaround by sampling using a scaled type and converting.
2100 * This is taken from amdgpu-pro shaders.
2101 */
2102 /* NOTE this produces some ugly code compared to amdgpu-pro,
2103 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2104 * and then reads them back. -pro generates two selects,
2105 * one s_cmp for the descriptor rewriting
2106 * one v_cmp for the coordinate and result changes.
2107 */
2108 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2109 LLVMValueRef tmp, tmp2;
2110
2111 /* workaround 8/8/8/8 uint/sint cube gather bug */
2112 /* first detect it then change to a scaled read and f2i */
2113 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2114 tmp2 = tmp;
2115
2116 /* extract the DATA_FORMAT */
2117 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2118 LLVMConstInt(ctx->i32, 6, false), false);
2119
2120 /* is the DATA_FORMAT == 8_8_8_8 */
2121 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2122
2123 if (stype == GLSL_TYPE_UINT)
2124 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2125 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2126 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2127 else
2128 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2129 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2130 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2131
2132 /* replace the NUM FORMAT in the descriptor */
2133 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2134 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2135
2136 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2137
2138 /* don't modify the coordinates for this case */
2139 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2140 }
2141 args->addr = coord;
2142 result = ac_build_image_opcode(ctx, args);
2143
2144 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2145 LLVMValueRef tmp, tmp2;
2146
2147 /* if the cube workaround is in place, f2i the result. */
2148 for (c = 0; c < 4; c++) {
2149 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2150 if (stype == GLSL_TYPE_UINT)
2151 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2152 else
2153 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2154 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2155 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2156 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2157 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2158 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2159 }
2160 }
2161 return result;
2162 }
2163
2164 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2165 const nir_tex_instr *instr,
2166 bool lod_is_zero,
2167 struct ac_image_args *args)
2168 {
2169 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2170 return ac_build_buffer_load_format(&ctx->ac,
2171 args->resource,
2172 args->addr,
2173 LLVMConstInt(ctx->ac.i32, 0, false),
2174 true);
2175 }
2176
2177 args->opcode = ac_image_sample;
2178 args->compare = instr->is_shadow;
2179
2180 switch (instr->op) {
2181 case nir_texop_txf:
2182 case nir_texop_txf_ms:
2183 case nir_texop_samples_identical:
2184 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2185 args->compare = false;
2186 args->offset = false;
2187 break;
2188 case nir_texop_txb:
2189 args->bias = true;
2190 break;
2191 case nir_texop_txl:
2192 if (lod_is_zero)
2193 args->level_zero = true;
2194 else
2195 args->lod = true;
2196 break;
2197 case nir_texop_txs:
2198 case nir_texop_query_levels:
2199 args->opcode = ac_image_get_resinfo;
2200 break;
2201 case nir_texop_tex:
2202 if (ctx->stage != MESA_SHADER_FRAGMENT)
2203 args->level_zero = true;
2204 break;
2205 case nir_texop_txd:
2206 args->deriv = true;
2207 break;
2208 case nir_texop_tg4:
2209 args->opcode = ac_image_gather4;
2210 args->level_zero = true;
2211 break;
2212 case nir_texop_lod:
2213 args->opcode = ac_image_get_lod;
2214 args->compare = false;
2215 args->offset = false;
2216 break;
2217 default:
2218 break;
2219 }
2220
2221 if (instr->op == nir_texop_tg4 && ctx->abi->chip_class <= VI) {
2222 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2223 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2224 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2225 }
2226 }
2227 return ac_build_image_opcode(&ctx->ac, args);
2228 }
2229
2230 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2231 nir_intrinsic_instr *instr)
2232 {
2233 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2234 unsigned desc_set = nir_intrinsic_desc_set(instr);
2235 unsigned binding = nir_intrinsic_binding(instr);
2236 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2237 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2238 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2239 unsigned base_offset = layout->binding[binding].offset;
2240 LLVMValueRef offset, stride;
2241
2242 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2243 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2244 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2245 layout->binding[binding].dynamic_offset_offset;
2246 desc_ptr = ctx->push_constants;
2247 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2248 stride = LLVMConstInt(ctx->i32, 16, false);
2249 } else
2250 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2251
2252 offset = LLVMConstInt(ctx->i32, base_offset, false);
2253 index = LLVMBuildMul(ctx->builder, index, stride, "");
2254 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2255
2256 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2257 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2258 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2259
2260 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2261 }
2262
2263 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2264 nir_intrinsic_instr *instr)
2265 {
2266 LLVMValueRef ptr, addr;
2267
2268 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2269 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2270
2271 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2272 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2273
2274 return LLVMBuildLoad(ctx->builder, ptr, "");
2275 }
2276
2277 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2278 const nir_intrinsic_instr *instr)
2279 {
2280 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2281
2282 return get_buffer_size(ctx, desc, false);
2283 }
2284 static void visit_store_ssbo(struct ac_nir_context *ctx,
2285 nir_intrinsic_instr *instr)
2286 {
2287 const char *store_name;
2288 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2289 LLVMTypeRef data_type = ctx->ac.f32;
2290 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2291 int components_32bit = elem_size_mult * instr->num_components;
2292 unsigned writemask = nir_intrinsic_write_mask(instr);
2293 LLVMValueRef base_data, base_offset;
2294 LLVMValueRef params[6];
2295 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2296
2297 params[1] = ctx->abi->load_ssbo(ctx->abi,
2298 get_src(ctx, instr->src[1]), true);
2299 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2300 params[4] = i1false; /* glc */
2301 params[5] = i1false; /* slc */
2302
2303 if (components_32bit > 1)
2304 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2305
2306 base_data = to_float(&ctx->ac, src_data);
2307 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2308 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2309 data_type, "");
2310 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2311 while (writemask) {
2312 int start, count;
2313 LLVMValueRef data;
2314 LLVMValueRef offset;
2315 LLVMValueRef tmp;
2316 u_bit_scan_consecutive_range(&writemask, &start, &count);
2317
2318 /* Due to an LLVM limitation, split 3-element writes
2319 * into a 2-element and a 1-element write. */
2320 if (count == 3) {
2321 writemask |= 1 << (start + 2);
2322 count = 2;
2323 }
2324
2325 start *= elem_size_mult;
2326 count *= elem_size_mult;
2327
2328 if (count > 4) {
2329 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2330 count = 4;
2331 }
2332
2333 if (count == 4) {
2334 store_name = "llvm.amdgcn.buffer.store.v4f32";
2335 data = base_data;
2336 } else if (count == 2) {
2337 LLVMTypeRef v2f32 = LLVMVectorType(ctx->ac.f32, 2);
2338
2339 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2340 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2341 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(v2f32), tmp,
2342 ctx->ac.i32_0, "");
2343
2344 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2345 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2346 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2347 ctx->ac.i32_1, "");
2348 store_name = "llvm.amdgcn.buffer.store.v2f32";
2349
2350 } else {
2351 assert(count == 1);
2352 if (get_llvm_num_components(base_data) > 1)
2353 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2354 LLVMConstInt(ctx->ac.i32, start, false), "");
2355 else
2356 data = base_data;
2357 store_name = "llvm.amdgcn.buffer.store.f32";
2358 }
2359
2360 offset = base_offset;
2361 if (start != 0) {
2362 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2363 }
2364 params[0] = data;
2365 params[3] = offset;
2366 ac_build_intrinsic(&ctx->ac, store_name,
2367 ctx->ac.voidt, params, 6, 0);
2368 }
2369 }
2370
2371 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2372 const nir_intrinsic_instr *instr)
2373 {
2374 const char *name;
2375 LLVMValueRef params[6];
2376 int arg_count = 0;
2377
2378 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2379 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2380 }
2381 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2382 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2383 get_src(ctx, instr->src[0]),
2384 true);
2385 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2386 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2387 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2388
2389 switch (instr->intrinsic) {
2390 case nir_intrinsic_ssbo_atomic_add:
2391 name = "llvm.amdgcn.buffer.atomic.add";
2392 break;
2393 case nir_intrinsic_ssbo_atomic_imin:
2394 name = "llvm.amdgcn.buffer.atomic.smin";
2395 break;
2396 case nir_intrinsic_ssbo_atomic_umin:
2397 name = "llvm.amdgcn.buffer.atomic.umin";
2398 break;
2399 case nir_intrinsic_ssbo_atomic_imax:
2400 name = "llvm.amdgcn.buffer.atomic.smax";
2401 break;
2402 case nir_intrinsic_ssbo_atomic_umax:
2403 name = "llvm.amdgcn.buffer.atomic.umax";
2404 break;
2405 case nir_intrinsic_ssbo_atomic_and:
2406 name = "llvm.amdgcn.buffer.atomic.and";
2407 break;
2408 case nir_intrinsic_ssbo_atomic_or:
2409 name = "llvm.amdgcn.buffer.atomic.or";
2410 break;
2411 case nir_intrinsic_ssbo_atomic_xor:
2412 name = "llvm.amdgcn.buffer.atomic.xor";
2413 break;
2414 case nir_intrinsic_ssbo_atomic_exchange:
2415 name = "llvm.amdgcn.buffer.atomic.swap";
2416 break;
2417 case nir_intrinsic_ssbo_atomic_comp_swap:
2418 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2419 break;
2420 default:
2421 abort();
2422 }
2423
2424 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2425 }
2426
2427 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2428 const nir_intrinsic_instr *instr)
2429 {
2430 LLVMValueRef results[2];
2431 int load_components;
2432 int num_components = instr->num_components;
2433 if (instr->dest.ssa.bit_size == 64)
2434 num_components *= 2;
2435
2436 for (int i = 0; i < num_components; i += load_components) {
2437 load_components = MIN2(num_components - i, 4);
2438 const char *load_name;
2439 LLVMTypeRef data_type = ctx->ac.f32;
2440 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2441 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2442
2443 if (load_components == 3)
2444 data_type = LLVMVectorType(ctx->ac.f32, 4);
2445 else if (load_components > 1)
2446 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2447
2448 if (load_components >= 3)
2449 load_name = "llvm.amdgcn.buffer.load.v4f32";
2450 else if (load_components == 2)
2451 load_name = "llvm.amdgcn.buffer.load.v2f32";
2452 else if (load_components == 1)
2453 load_name = "llvm.amdgcn.buffer.load.f32";
2454 else
2455 unreachable("unhandled number of components");
2456
2457 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2458 LLVMValueRef params[] = {
2459 ctx->abi->load_ssbo(ctx->abi,
2460 get_src(ctx, instr->src[0]),
2461 false),
2462 LLVMConstInt(ctx->ac.i32, 0, false),
2463 offset,
2464 i1false,
2465 i1false,
2466 };
2467
2468 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2469
2470 }
2471
2472 LLVMValueRef ret = results[0];
2473 if (num_components > 4 || num_components == 3) {
2474 LLVMValueRef masks[] = {
2475 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2476 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2477 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2478 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2479 };
2480
2481 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2482 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2483 results[num_components > 4 ? 1 : 0], swizzle, "");
2484 }
2485
2486 return LLVMBuildBitCast(ctx->ac.builder, ret,
2487 get_def_type(ctx, &instr->dest.ssa), "");
2488 }
2489
2490 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2491 const nir_intrinsic_instr *instr)
2492 {
2493 LLVMValueRef results[8], ret;
2494 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2495 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2496 int num_components = instr->num_components;
2497
2498 if (ctx->abi->load_ubo)
2499 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2500
2501 if (instr->dest.ssa.bit_size == 64)
2502 num_components *= 2;
2503
2504 for (unsigned i = 0; i < num_components; ++i) {
2505 LLVMValueRef params[] = {
2506 rsrc,
2507 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2508 offset, "")
2509 };
2510 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2511 params, 2,
2512 AC_FUNC_ATTR_READNONE |
2513 AC_FUNC_ATTR_LEGACY);
2514 }
2515
2516
2517 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2518 return LLVMBuildBitCast(ctx->ac.builder, ret,
2519 get_def_type(ctx, &instr->dest.ssa), "");
2520 }
2521
2522 static void
2523 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2524 bool vs_in, unsigned *vertex_index_out,
2525 LLVMValueRef *vertex_index_ref,
2526 unsigned *const_out, LLVMValueRef *indir_out)
2527 {
2528 unsigned const_offset = 0;
2529 nir_deref *tail = &deref->deref;
2530 LLVMValueRef offset = NULL;
2531
2532 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2533 tail = tail->child;
2534 nir_deref_array *deref_array = nir_deref_as_array(tail);
2535 if (vertex_index_out)
2536 *vertex_index_out = deref_array->base_offset;
2537
2538 if (vertex_index_ref) {
2539 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2540 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2541 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2542 }
2543 *vertex_index_ref = vtx;
2544 }
2545 }
2546
2547 if (deref->var->data.compact) {
2548 assert(tail->child->deref_type == nir_deref_type_array);
2549 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2550 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2551 /* We always lower indirect dereferences for "compact" array vars. */
2552 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2553
2554 const_offset = deref_array->base_offset;
2555 goto out;
2556 }
2557
2558 while (tail->child != NULL) {
2559 const struct glsl_type *parent_type = tail->type;
2560 tail = tail->child;
2561
2562 if (tail->deref_type == nir_deref_type_array) {
2563 nir_deref_array *deref_array = nir_deref_as_array(tail);
2564 LLVMValueRef index, stride, local_offset;
2565 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2566
2567 const_offset += size * deref_array->base_offset;
2568 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2569 continue;
2570
2571 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2572 index = get_src(ctx, deref_array->indirect);
2573 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2574 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2575
2576 if (offset)
2577 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2578 else
2579 offset = local_offset;
2580 } else if (tail->deref_type == nir_deref_type_struct) {
2581 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2582
2583 for (unsigned i = 0; i < deref_struct->index; i++) {
2584 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2585 const_offset += glsl_count_attribute_slots(ft, vs_in);
2586 }
2587 } else
2588 unreachable("unsupported deref type");
2589
2590 }
2591 out:
2592 if (const_offset && offset)
2593 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2594 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2595 "");
2596
2597 *const_out = const_offset;
2598 *indir_out = offset;
2599 }
2600
2601 static LLVMValueRef
2602 lds_load(struct nir_to_llvm_context *ctx,
2603 LLVMValueRef dw_addr)
2604 {
2605 LLVMValueRef value;
2606 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2607 return value;
2608 }
2609
2610 static void
2611 lds_store(struct nir_to_llvm_context *ctx,
2612 LLVMValueRef dw_addr, LLVMValueRef value)
2613 {
2614 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2615 ac_build_indexed_store(&ctx->ac, ctx->lds,
2616 dw_addr, value);
2617 }
2618
2619 /* The offchip buffer layout for TCS->TES is
2620 *
2621 * - attribute 0 of patch 0 vertex 0
2622 * - attribute 0 of patch 0 vertex 1
2623 * - attribute 0 of patch 0 vertex 2
2624 * ...
2625 * - attribute 0 of patch 1 vertex 0
2626 * - attribute 0 of patch 1 vertex 1
2627 * ...
2628 * - attribute 1 of patch 0 vertex 0
2629 * - attribute 1 of patch 0 vertex 1
2630 * ...
2631 * - per patch attribute 0 of patch 0
2632 * - per patch attribute 0 of patch 1
2633 * ...
2634 *
2635 * Note that every attribute has 4 components.
2636 */
2637 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2638 LLVMValueRef vertex_index,
2639 LLVMValueRef param_index)
2640 {
2641 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2642 LLVMValueRef param_stride, constant16;
2643 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2644
2645 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2646 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2647 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2648 num_patches, "");
2649
2650 constant16 = LLVMConstInt(ctx->i32, 16, false);
2651 if (vertex_index) {
2652 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2653 vertices_per_patch, "");
2654
2655 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2656 vertex_index, "");
2657
2658 param_stride = total_vertices;
2659 } else {
2660 base_addr = rel_patch_id;
2661 param_stride = num_patches;
2662 }
2663
2664 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2665 LLVMBuildMul(ctx->builder, param_index,
2666 param_stride, ""), "");
2667
2668 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2669
2670 if (!vertex_index) {
2671 LLVMValueRef patch_data_offset =
2672 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2673
2674 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2675 patch_data_offset, "");
2676 }
2677 return base_addr;
2678 }
2679
2680 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2681 unsigned param,
2682 unsigned const_index,
2683 bool is_compact,
2684 LLVMValueRef vertex_index,
2685 LLVMValueRef indir_index)
2686 {
2687 LLVMValueRef param_index;
2688
2689 if (indir_index)
2690 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2691 indir_index, "");
2692 else {
2693 if (const_index && !is_compact)
2694 param += const_index;
2695 param_index = LLVMConstInt(ctx->i32, param, false);
2696 }
2697 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2698 }
2699
2700 static void
2701 mark_tess_output(struct nir_to_llvm_context *ctx,
2702 bool is_patch, uint32_t param)
2703
2704 {
2705 if (is_patch) {
2706 ctx->tess_patch_outputs_written |= (1ull << param);
2707 } else
2708 ctx->tess_outputs_written |= (1ull << param);
2709 }
2710
2711 static LLVMValueRef
2712 get_dw_address(struct nir_to_llvm_context *ctx,
2713 LLVMValueRef dw_addr,
2714 unsigned param,
2715 unsigned const_index,
2716 bool compact_const_index,
2717 LLVMValueRef vertex_index,
2718 LLVMValueRef stride,
2719 LLVMValueRef indir_index)
2720
2721 {
2722
2723 if (vertex_index) {
2724 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2725 LLVMBuildMul(ctx->builder,
2726 vertex_index,
2727 stride, ""), "");
2728 }
2729
2730 if (indir_index)
2731 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2732 LLVMBuildMul(ctx->builder, indir_index,
2733 LLVMConstInt(ctx->i32, 4, false), ""), "");
2734 else if (const_index && !compact_const_index)
2735 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2736 LLVMConstInt(ctx->i32, const_index, false), "");
2737
2738 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2739 LLVMConstInt(ctx->i32, param * 4, false), "");
2740
2741 if (const_index && compact_const_index)
2742 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2743 LLVMConstInt(ctx->i32, const_index, false), "");
2744 return dw_addr;
2745 }
2746
2747 static LLVMValueRef
2748 load_tcs_input(struct nir_to_llvm_context *ctx,
2749 nir_intrinsic_instr *instr)
2750 {
2751 LLVMValueRef dw_addr, stride;
2752 unsigned const_index;
2753 LLVMValueRef vertex_index;
2754 LLVMValueRef indir_index;
2755 unsigned param;
2756 LLVMValueRef value[4], result;
2757 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2758 const bool is_compact = instr->variables[0]->var->data.compact;
2759 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2760 get_deref_offset(ctx->nir, instr->variables[0],
2761 false, NULL, per_vertex ? &vertex_index : NULL,
2762 &const_index, &indir_index);
2763
2764 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2765 dw_addr = get_tcs_in_current_patch_offset(ctx);
2766 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2767 indir_index);
2768
2769 for (unsigned i = 0; i < instr->num_components; i++) {
2770 value[i] = lds_load(ctx, dw_addr);
2771 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2772 ctx->i32one, "");
2773 }
2774 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2775 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2776 return result;
2777 }
2778
2779 static LLVMValueRef
2780 load_tcs_output(struct nir_to_llvm_context *ctx,
2781 nir_intrinsic_instr *instr)
2782 {
2783 LLVMValueRef dw_addr;
2784 LLVMValueRef stride = NULL;
2785 LLVMValueRef value[4], result;
2786 LLVMValueRef vertex_index = NULL;
2787 LLVMValueRef indir_index = NULL;
2788 unsigned const_index = 0;
2789 unsigned param;
2790 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2791 const bool is_compact = instr->variables[0]->var->data.compact;
2792 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2793 get_deref_offset(ctx->nir, instr->variables[0],
2794 false, NULL, per_vertex ? &vertex_index : NULL,
2795 &const_index, &indir_index);
2796
2797 if (!instr->variables[0]->var->data.patch) {
2798 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2799 dw_addr = get_tcs_out_current_patch_offset(ctx);
2800 } else {
2801 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2802 }
2803
2804 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2805 indir_index);
2806
2807 for (unsigned i = 0; i < instr->num_components; i++) {
2808 value[i] = lds_load(ctx, dw_addr);
2809 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2810 ctx->i32one, "");
2811 }
2812 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2813 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2814 return result;
2815 }
2816
2817 static void
2818 store_tcs_output(struct nir_to_llvm_context *ctx,
2819 nir_intrinsic_instr *instr,
2820 LLVMValueRef src,
2821 unsigned writemask)
2822 {
2823 LLVMValueRef dw_addr;
2824 LLVMValueRef stride = NULL;
2825 LLVMValueRef buf_addr = NULL;
2826 LLVMValueRef vertex_index = NULL;
2827 LLVMValueRef indir_index = NULL;
2828 unsigned const_index = 0;
2829 unsigned param;
2830 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2831 const bool is_compact = instr->variables[0]->var->data.compact;
2832
2833 get_deref_offset(ctx->nir, instr->variables[0],
2834 false, NULL, per_vertex ? &vertex_index : NULL,
2835 &const_index, &indir_index);
2836
2837 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2838 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2839 is_compact && const_index > 3) {
2840 const_index -= 3;
2841 param++;
2842 }
2843
2844 if (!instr->variables[0]->var->data.patch) {
2845 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2846 dw_addr = get_tcs_out_current_patch_offset(ctx);
2847 } else {
2848 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2849 }
2850
2851 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2852
2853 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2854 indir_index);
2855 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2856 vertex_index, indir_index);
2857
2858 unsigned base = is_compact ? const_index : 0;
2859 for (unsigned chan = 0; chan < 8; chan++) {
2860 bool is_tess_factor = false;
2861 if (!(writemask & (1 << chan)))
2862 continue;
2863 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan);
2864
2865 lds_store(ctx, dw_addr, value);
2866
2867 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2868 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2869 is_tess_factor = true;
2870
2871 if (!is_tess_factor && writemask != 0xF)
2872 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2873 buf_addr, ctx->oc_lds,
2874 4 * (base + chan), 1, 0, true, false);
2875
2876 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2877 ctx->i32one, "");
2878 }
2879
2880 if (writemask == 0xF) {
2881 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2882 buf_addr, ctx->oc_lds,
2883 (base * 4), 1, 0, true, false);
2884 }
2885 }
2886
2887 static LLVMValueRef
2888 load_tes_input(struct nir_to_llvm_context *ctx,
2889 const nir_intrinsic_instr *instr)
2890 {
2891 LLVMValueRef buf_addr;
2892 LLVMValueRef result;
2893 LLVMValueRef vertex_index = NULL;
2894 LLVMValueRef indir_index = NULL;
2895 unsigned const_index = 0;
2896 unsigned param;
2897 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2898 const bool is_compact = instr->variables[0]->var->data.compact;
2899
2900 get_deref_offset(ctx->nir, instr->variables[0],
2901 false, NULL, per_vertex ? &vertex_index : NULL,
2902 &const_index, &indir_index);
2903 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2904 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2905 is_compact && const_index > 3) {
2906 const_index -= 3;
2907 param++;
2908 }
2909 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2910 is_compact, vertex_index, indir_index);
2911
2912 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2913 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2914 result = trim_vector(&ctx->ac, result, instr->num_components);
2915 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2916 return result;
2917 }
2918
2919 static LLVMValueRef
2920 load_gs_input(struct nir_to_llvm_context *ctx,
2921 nir_intrinsic_instr *instr)
2922 {
2923 LLVMValueRef indir_index, vtx_offset;
2924 unsigned const_index;
2925 LLVMValueRef args[9];
2926 unsigned param, vtx_offset_param;
2927 LLVMValueRef value[4], result;
2928 unsigned vertex_index;
2929 get_deref_offset(ctx->nir, instr->variables[0],
2930 false, &vertex_index, NULL,
2931 &const_index, &indir_index);
2932 vtx_offset_param = vertex_index;
2933 assert(vtx_offset_param < 6);
2934 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2935 LLVMConstInt(ctx->i32, 4, false), "");
2936
2937 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2938 for (unsigned i = 0; i < instr->num_components; i++) {
2939
2940 args[0] = ctx->esgs_ring;
2941 args[1] = vtx_offset;
2942 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2943 args[3] = ctx->i32zero;
2944 args[4] = ctx->i32one; /* OFFEN */
2945 args[5] = ctx->i32zero; /* IDXEN */
2946 args[6] = ctx->i32one; /* GLC */
2947 args[7] = ctx->i32zero; /* SLC */
2948 args[8] = ctx->i32zero; /* TFE */
2949
2950 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2951 ctx->i32, args, 9,
2952 AC_FUNC_ATTR_READONLY |
2953 AC_FUNC_ATTR_LEGACY);
2954 }
2955 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2956
2957 return result;
2958 }
2959
2960 static LLVMValueRef
2961 build_gep_for_deref(struct ac_nir_context *ctx,
2962 nir_deref_var *deref)
2963 {
2964 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2965 assert(entry->data);
2966 LLVMValueRef val = entry->data;
2967 nir_deref *tail = deref->deref.child;
2968 while (tail != NULL) {
2969 LLVMValueRef offset;
2970 switch (tail->deref_type) {
2971 case nir_deref_type_array: {
2972 nir_deref_array *array = nir_deref_as_array(tail);
2973 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2974 if (array->deref_array_type ==
2975 nir_deref_array_type_indirect) {
2976 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2977 get_src(ctx,
2978 array->indirect),
2979 "");
2980 }
2981 break;
2982 }
2983 case nir_deref_type_struct: {
2984 nir_deref_struct *deref_struct =
2985 nir_deref_as_struct(tail);
2986 offset = LLVMConstInt(ctx->ac.i32,
2987 deref_struct->index, 0);
2988 break;
2989 }
2990 default:
2991 unreachable("bad deref type");
2992 }
2993 val = ac_build_gep0(&ctx->ac, val, offset);
2994 tail = tail->child;
2995 }
2996 return val;
2997 }
2998
2999 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3000 nir_intrinsic_instr *instr)
3001 {
3002 LLVMValueRef values[8];
3003 int idx = instr->variables[0]->var->data.driver_location;
3004 int ve = instr->dest.ssa.num_components;
3005 LLVMValueRef indir_index;
3006 LLVMValueRef ret;
3007 unsigned const_index;
3008 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3009 instr->variables[0]->var->data.mode == nir_var_shader_in;
3010 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3011 &const_index, &indir_index);
3012
3013 if (instr->dest.ssa.bit_size == 64)
3014 ve *= 2;
3015
3016 switch (instr->variables[0]->var->data.mode) {
3017 case nir_var_shader_in:
3018 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3019 return load_tcs_input(ctx->nctx, instr);
3020 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3021 return load_tes_input(ctx->nctx, instr);
3022 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3023 return load_gs_input(ctx->nctx, instr);
3024 }
3025 for (unsigned chan = 0; chan < ve; chan++) {
3026 if (indir_index) {
3027 unsigned count = glsl_count_attribute_slots(
3028 instr->variables[0]->var->type,
3029 ctx->stage == MESA_SHADER_VERTEX);
3030 count -= chan / 4;
3031 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3032 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3033 4, false, true);
3034
3035 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3036 tmp_vec,
3037 indir_index, "");
3038 } else
3039 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3040 }
3041 break;
3042 case nir_var_local:
3043 for (unsigned chan = 0; chan < ve; chan++) {
3044 if (indir_index) {
3045 unsigned count = glsl_count_attribute_slots(
3046 instr->variables[0]->var->type, false);
3047 count -= chan / 4;
3048 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3049 &ctx->ac, ctx->locals + idx + chan, count,
3050 4, true, true);
3051
3052 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3053 tmp_vec,
3054 indir_index, "");
3055 } else {
3056 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3057 }
3058 }
3059 break;
3060 case nir_var_shared: {
3061 LLVMValueRef address = build_gep_for_deref(ctx,
3062 instr->variables[0]);
3063 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3064 return LLVMBuildBitCast(ctx->ac.builder, val,
3065 get_def_type(ctx, &instr->dest.ssa),
3066 "");
3067 }
3068 case nir_var_shader_out:
3069 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3070 return load_tcs_output(ctx->nctx, instr);
3071 for (unsigned chan = 0; chan < ve; chan++) {
3072 if (indir_index) {
3073 unsigned count = glsl_count_attribute_slots(
3074 instr->variables[0]->var->type, false);
3075 count -= chan / 4;
3076 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3077 &ctx->ac, ctx->outputs + idx + chan, count,
3078 4, true, true);
3079
3080 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3081 tmp_vec,
3082 indir_index, "");
3083 } else {
3084 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3085 ctx->outputs[idx + chan + const_index * 4],
3086 "");
3087 }
3088 }
3089 break;
3090 default:
3091 unreachable("unhandle variable mode");
3092 }
3093 ret = ac_build_gather_values(&ctx->ac, values, ve);
3094 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3095 }
3096
3097 static void
3098 visit_store_var(struct ac_nir_context *ctx,
3099 nir_intrinsic_instr *instr)
3100 {
3101 LLVMValueRef temp_ptr, value;
3102 int idx = instr->variables[0]->var->data.driver_location;
3103 LLVMValueRef src = to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3104 int writemask = instr->const_index[0];
3105 LLVMValueRef indir_index;
3106 unsigned const_index;
3107 get_deref_offset(ctx, instr->variables[0], false,
3108 NULL, NULL, &const_index, &indir_index);
3109
3110 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3111 int old_writemask = writemask;
3112
3113 src = LLVMBuildBitCast(ctx->ac.builder, src,
3114 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3115 "");
3116
3117 writemask = 0;
3118 for (unsigned chan = 0; chan < 4; chan++) {
3119 if (old_writemask & (1 << chan))
3120 writemask |= 3u << (2 * chan);
3121 }
3122 }
3123
3124 switch (instr->variables[0]->var->data.mode) {
3125 case nir_var_shader_out:
3126
3127 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3128 store_tcs_output(ctx->nctx, instr, src, writemask);
3129 return;
3130 }
3131
3132 for (unsigned chan = 0; chan < 8; chan++) {
3133 int stride = 4;
3134 if (!(writemask & (1 << chan)))
3135 continue;
3136
3137 value = llvm_extract_elem(&ctx->ac, src, chan);
3138
3139 if (instr->variables[0]->var->data.compact)
3140 stride = 1;
3141 if (indir_index) {
3142 unsigned count = glsl_count_attribute_slots(
3143 instr->variables[0]->var->type, false);
3144 count -= chan / 4;
3145 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3146 &ctx->ac, ctx->outputs + idx + chan, count,
3147 stride, true, true);
3148
3149 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3150 value, indir_index, "");
3151 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3152 count, stride, tmp_vec);
3153
3154 } else {
3155 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3156
3157 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3158 }
3159 }
3160 break;
3161 case nir_var_local:
3162 for (unsigned chan = 0; chan < 8; chan++) {
3163 if (!(writemask & (1 << chan)))
3164 continue;
3165
3166 value = llvm_extract_elem(&ctx->ac, src, chan);
3167 if (indir_index) {
3168 unsigned count = glsl_count_attribute_slots(
3169 instr->variables[0]->var->type, false);
3170 count -= chan / 4;
3171 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3172 &ctx->ac, ctx->locals + idx + chan, count,
3173 4, true, true);
3174
3175 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3176 value, indir_index, "");
3177 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3178 count, 4, tmp_vec);
3179 } else {
3180 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3181
3182 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3183 }
3184 }
3185 break;
3186 case nir_var_shared: {
3187 int writemask = instr->const_index[0];
3188 LLVMValueRef address = build_gep_for_deref(ctx,
3189 instr->variables[0]);
3190 LLVMValueRef val = get_src(ctx, instr->src[0]);
3191 unsigned components =
3192 glsl_get_vector_elements(
3193 nir_deref_tail(&instr->variables[0]->deref)->type);
3194 if (writemask == (1 << components) - 1) {
3195 val = LLVMBuildBitCast(
3196 ctx->ac.builder, val,
3197 LLVMGetElementType(LLVMTypeOf(address)), "");
3198 LLVMBuildStore(ctx->ac.builder, val, address);
3199 } else {
3200 for (unsigned chan = 0; chan < 4; chan++) {
3201 if (!(writemask & (1 << chan)))
3202 continue;
3203 LLVMValueRef ptr =
3204 LLVMBuildStructGEP(ctx->ac.builder,
3205 address, chan, "");
3206 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3207 chan);
3208 src = LLVMBuildBitCast(
3209 ctx->ac.builder, src,
3210 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3211 LLVMBuildStore(ctx->ac.builder, src, ptr);
3212 }
3213 }
3214 break;
3215 }
3216 default:
3217 break;
3218 }
3219 }
3220
3221 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3222 {
3223 switch (dim) {
3224 case GLSL_SAMPLER_DIM_BUF:
3225 return 1;
3226 case GLSL_SAMPLER_DIM_1D:
3227 return array ? 2 : 1;
3228 case GLSL_SAMPLER_DIM_2D:
3229 return array ? 3 : 2;
3230 case GLSL_SAMPLER_DIM_MS:
3231 return array ? 4 : 3;
3232 case GLSL_SAMPLER_DIM_3D:
3233 case GLSL_SAMPLER_DIM_CUBE:
3234 return 3;
3235 case GLSL_SAMPLER_DIM_RECT:
3236 case GLSL_SAMPLER_DIM_SUBPASS:
3237 return 2;
3238 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3239 return 3;
3240 default:
3241 break;
3242 }
3243 return 0;
3244 }
3245
3246
3247
3248 /* Adjust the sample index according to FMASK.
3249 *
3250 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3251 * which is the identity mapping. Each nibble says which physical sample
3252 * should be fetched to get that sample.
3253 *
3254 * For example, 0x11111100 means there are only 2 samples stored and
3255 * the second sample covers 3/4 of the pixel. When reading samples 0
3256 * and 1, return physical sample 0 (determined by the first two 0s
3257 * in FMASK), otherwise return physical sample 1.
3258 *
3259 * The sample index should be adjusted as follows:
3260 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3261 */
3262 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3263 LLVMValueRef coord_x, LLVMValueRef coord_y,
3264 LLVMValueRef coord_z,
3265 LLVMValueRef sample_index,
3266 LLVMValueRef fmask_desc_ptr)
3267 {
3268 LLVMValueRef fmask_load_address[4];
3269 LLVMValueRef res;
3270
3271 fmask_load_address[0] = coord_x;
3272 fmask_load_address[1] = coord_y;
3273 if (coord_z) {
3274 fmask_load_address[2] = coord_z;
3275 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3276 }
3277
3278 struct ac_image_args args = {0};
3279
3280 args.opcode = ac_image_load;
3281 args.da = coord_z ? true : false;
3282 args.resource = fmask_desc_ptr;
3283 args.dmask = 0xf;
3284 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3285
3286 res = ac_build_image_opcode(ctx, &args);
3287
3288 res = to_integer(ctx, res);
3289 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3290 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3291
3292 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3293 res,
3294 ctx->i32_0, "");
3295
3296 LLVMValueRef sample_index4 =
3297 LLVMBuildMul(ctx->builder, sample_index, four, "");
3298 LLVMValueRef shifted_fmask =
3299 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3300 LLVMValueRef final_sample =
3301 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3302
3303 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3304 * resource descriptor is 0 (invalid),
3305 */
3306 LLVMValueRef fmask_desc =
3307 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3308 ctx->v8i32, "");
3309
3310 LLVMValueRef fmask_word1 =
3311 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3312 ctx->i32_1, "");
3313
3314 LLVMValueRef word1_is_nonzero =
3315 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3316 fmask_word1, ctx->i32_0, "");
3317
3318 /* Replace the MSAA sample index. */
3319 sample_index =
3320 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3321 final_sample, sample_index, "");
3322 return sample_index;
3323 }
3324
3325 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3326 const nir_intrinsic_instr *instr)
3327 {
3328 const struct glsl_type *type = instr->variables[0]->var->type;
3329 if(instr->variables[0]->deref.child)
3330 type = instr->variables[0]->deref.child->type;
3331
3332 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3333 LLVMValueRef coords[4];
3334 LLVMValueRef masks[] = {
3335 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3336 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3337 };
3338 LLVMValueRef res;
3339 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3340
3341 int count;
3342 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3343 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3344 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3345 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3346 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3347
3348 count = image_type_to_components_count(dim,
3349 glsl_sampler_type_is_array(type));
3350
3351 if (is_ms) {
3352 LLVMValueRef fmask_load_address[3];
3353 int chan;
3354
3355 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3356 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3357 if (glsl_sampler_type_is_array(type))
3358 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3359 else
3360 fmask_load_address[2] = NULL;
3361 if (add_frag_pos) {
3362 for (chan = 0; chan < 2; ++chan)
3363 fmask_load_address[chan] =
3364 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3365 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3366 ctx->ac.i32, ""), "");
3367 fmask_load_address[2] = to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3368 }
3369 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3370 fmask_load_address[0],
3371 fmask_load_address[1],
3372 fmask_load_address[2],
3373 sample_index,
3374 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, true, false));
3375 }
3376 if (count == 1) {
3377 if (instr->src[0].ssa->num_components)
3378 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3379 else
3380 res = src0;
3381 } else {
3382 int chan;
3383 if (is_ms)
3384 count--;
3385 for (chan = 0; chan < count; ++chan) {
3386 coords[chan] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[chan], "");
3387 }
3388
3389 if (add_frag_pos) {
3390 for (chan = 0; chan < 2; ++chan)
3391 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3392 ctx->ac.i32, ""), "");
3393 coords[2] = to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3394 count++;
3395 }
3396 if (is_ms) {
3397 coords[count] = sample_index;
3398 count++;
3399 }
3400
3401 if (count == 3) {
3402 coords[3] = LLVMGetUndef(ctx->ac.i32);
3403 count = 4;
3404 }
3405 res = ac_build_gather_values(&ctx->ac, coords, count);
3406 }
3407 return res;
3408 }
3409
3410 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3411 const nir_intrinsic_instr *instr)
3412 {
3413 LLVMValueRef params[7];
3414 LLVMValueRef res;
3415 char intrinsic_name[64];
3416 const nir_variable *var = instr->variables[0]->var;
3417 const struct glsl_type *type = var->type;
3418 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3419 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3420
3421 if(instr->variables[0]->deref.child)
3422 type = instr->variables[0]->deref.child->type;
3423
3424 type = glsl_without_array(type);
3425 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3426 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, false);
3427 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3428 ctx->ac.i32_0, ""); /* vindex */
3429 params[2] = ctx->ac.i32_0; /* voffset */
3430 params[3] = i1false; /* glc */
3431 params[4] = i1false; /* slc */
3432 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3433 params, 5, 0);
3434
3435 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3436 res = to_integer(&ctx->ac, res);
3437 } else {
3438 bool is_da = glsl_sampler_type_is_array(type) ||
3439 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3440 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3441 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3442 LLVMValueRef da = is_da ? i1true : i1false;
3443 LLVMValueRef glc = i1false;
3444 LLVMValueRef slc = i1false;
3445
3446 params[0] = get_image_coords(ctx, instr);
3447 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3448 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3449 if (HAVE_LLVM <= 0x0309) {
3450 params[3] = i1false; /* r128 */
3451 params[4] = da;
3452 params[5] = glc;
3453 params[6] = slc;
3454 } else {
3455 LLVMValueRef lwe = i1false;
3456 params[3] = glc;
3457 params[4] = slc;
3458 params[5] = lwe;
3459 params[6] = da;
3460 }
3461
3462 ac_get_image_intr_name("llvm.amdgcn.image.load",
3463 ctx->ac.v4f32, /* vdata */
3464 LLVMTypeOf(params[0]), /* coords */
3465 LLVMTypeOf(params[1]), /* rsrc */
3466 intrinsic_name, sizeof(intrinsic_name));
3467
3468 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3469 params, 7, AC_FUNC_ATTR_READONLY);
3470 }
3471 return to_integer(&ctx->ac, res);
3472 }
3473
3474 static void visit_image_store(struct ac_nir_context *ctx,
3475 nir_intrinsic_instr *instr)
3476 {
3477 LLVMValueRef params[8];
3478 char intrinsic_name[64];
3479 const nir_variable *var = instr->variables[0]->var;
3480 const struct glsl_type *type = glsl_without_array(var->type);
3481 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3482 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3483 LLVMValueRef glc = i1false;
3484 bool force_glc = ctx->abi->chip_class == SI;
3485 if (force_glc)
3486 glc = i1true;
3487
3488 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3489 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3490 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, true);
3491 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3492 ctx->ac.i32_0, ""); /* vindex */
3493 params[3] = ctx->ac.i32_0; /* voffset */
3494 params[4] = glc; /* glc */
3495 params[5] = i1false; /* slc */
3496 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3497 params, 6, 0);
3498 } else {
3499 bool is_da = glsl_sampler_type_is_array(type) ||
3500 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3501 LLVMValueRef da = is_da ? i1true : i1false;
3502 LLVMValueRef slc = i1false;
3503
3504 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3505 params[1] = get_image_coords(ctx, instr); /* coords */
3506 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, true);
3507 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3508 if (HAVE_LLVM <= 0x0309) {
3509 params[4] = i1false; /* r128 */
3510 params[5] = da;
3511 params[6] = glc;
3512 params[7] = slc;
3513 } else {
3514 LLVMValueRef lwe = i1false;
3515 params[4] = glc;
3516 params[5] = slc;
3517 params[6] = lwe;
3518 params[7] = da;
3519 }
3520
3521 ac_get_image_intr_name("llvm.amdgcn.image.store",
3522 LLVMTypeOf(params[0]), /* vdata */
3523 LLVMTypeOf(params[1]), /* coords */
3524 LLVMTypeOf(params[2]), /* rsrc */
3525 intrinsic_name, sizeof(intrinsic_name));
3526
3527 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3528 params, 8, 0);
3529 }
3530
3531 }
3532
3533 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3534 const nir_intrinsic_instr *instr)
3535 {
3536 LLVMValueRef params[6];
3537 int param_count = 0;
3538 const nir_variable *var = instr->variables[0]->var;
3539
3540 const char *atomic_name;
3541 char intrinsic_name[41];
3542 const struct glsl_type *type = glsl_without_array(var->type);
3543 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3544 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3545 MAYBE_UNUSED int length;
3546
3547 switch (instr->intrinsic) {
3548 case nir_intrinsic_image_atomic_add:
3549 atomic_name = "add";
3550 break;
3551 case nir_intrinsic_image_atomic_min:
3552 atomic_name = "smin";
3553 break;
3554 case nir_intrinsic_image_atomic_max:
3555 atomic_name = "smax";
3556 break;
3557 case nir_intrinsic_image_atomic_and:
3558 atomic_name = "and";
3559 break;
3560 case nir_intrinsic_image_atomic_or:
3561 atomic_name = "or";
3562 break;
3563 case nir_intrinsic_image_atomic_xor:
3564 atomic_name = "xor";
3565 break;
3566 case nir_intrinsic_image_atomic_exchange:
3567 atomic_name = "swap";
3568 break;
3569 case nir_intrinsic_image_atomic_comp_swap:
3570 atomic_name = "cmpswap";
3571 break;
3572 default:
3573 abort();
3574 }
3575
3576 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3577 params[param_count++] = get_src(ctx, instr->src[3]);
3578 params[param_count++] = get_src(ctx, instr->src[2]);
3579
3580 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3581 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3582 true, true);
3583 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3584 ctx->ac.i32_0, ""); /* vindex */
3585 params[param_count++] = ctx->ac.i32_0; /* voffset */
3586 params[param_count++] = i1false; /* slc */
3587
3588 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3589 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3590 } else {
3591 char coords_type[8];
3592
3593 bool da = glsl_sampler_type_is_array(type) ||
3594 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3595
3596 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3597 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3598 true, true);
3599 params[param_count++] = i1false; /* r128 */
3600 params[param_count++] = da ? i1true : i1false; /* da */
3601 params[param_count++] = i1false; /* slc */
3602
3603 build_int_type_name(LLVMTypeOf(coords),
3604 coords_type, sizeof(coords_type));
3605
3606 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3607 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3608 }
3609
3610 assert(length < sizeof(intrinsic_name));
3611 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3612 }
3613
3614 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3615 const nir_intrinsic_instr *instr)
3616 {
3617 LLVMValueRef res;
3618 const nir_variable *var = instr->variables[0]->var;
3619 const struct glsl_type *type = instr->variables[0]->var->type;
3620 bool da = glsl_sampler_type_is_array(var->type) ||
3621 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3622 if(instr->variables[0]->deref.child)
3623 type = instr->variables[0]->deref.child->type;
3624
3625 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3626 return get_buffer_size(ctx,
3627 get_sampler_desc(ctx, instr->variables[0],
3628 AC_DESC_BUFFER, true, false), true);
3629
3630 struct ac_image_args args = { 0 };
3631
3632 args.da = da;
3633 args.dmask = 0xf;
3634 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3635 args.opcode = ac_image_get_resinfo;
3636 args.addr = ctx->ac.i32_0;
3637
3638 res = ac_build_image_opcode(&ctx->ac, &args);
3639
3640 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3641 glsl_sampler_type_is_array(type)) {
3642 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3643 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3644 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3645 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3646 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3647 }
3648 return res;
3649 }
3650
3651 #define NOOP_WAITCNT 0xf7f
3652 #define LGKM_CNT 0x07f
3653 #define VM_CNT 0xf70
3654
3655 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3656 unsigned simm16)
3657 {
3658 LLVMValueRef args[1] = {
3659 LLVMConstInt(ctx->i32, simm16, false),
3660 };
3661 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3662 ctx->voidt, args, 1, 0);
3663 }
3664
3665 static void emit_barrier(struct nir_to_llvm_context *ctx)
3666 {
3667 /* SI only (thanks to a hw bug workaround):
3668 * The real barrier instruction isn’t needed, because an entire patch
3669 * always fits into a single wave.
3670 */
3671 if (ctx->options->chip_class == SI &&
3672 ctx->stage == MESA_SHADER_TESS_CTRL) {
3673 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3674 return;
3675 }
3676 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3677 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3678 }
3679
3680 static void emit_discard_if(struct ac_nir_context *ctx,
3681 const nir_intrinsic_instr *instr)
3682 {
3683 LLVMValueRef cond;
3684
3685 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
3686 get_src(ctx, instr->src[0]),
3687 ctx->ac.i32_0, "");
3688
3689 cond = LLVMBuildSelect(ctx->ac.builder, cond,
3690 LLVMConstReal(ctx->ac.f32, -1.0f),
3691 ctx->ac.f32_0, "");
3692 ac_build_kill(&ctx->ac, cond);
3693 }
3694
3695 static LLVMValueRef
3696 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3697 {
3698 LLVMValueRef result;
3699 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3700 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3701 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3702
3703 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3704 }
3705
3706 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3707 const nir_intrinsic_instr *instr)
3708 {
3709 LLVMValueRef ptr, result;
3710 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3711 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3712
3713 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3714 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3715 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3716 ptr, src, src1,
3717 LLVMAtomicOrderingSequentiallyConsistent,
3718 LLVMAtomicOrderingSequentiallyConsistent,
3719 false);
3720 } else {
3721 LLVMAtomicRMWBinOp op;
3722 switch (instr->intrinsic) {
3723 case nir_intrinsic_var_atomic_add:
3724 op = LLVMAtomicRMWBinOpAdd;
3725 break;
3726 case nir_intrinsic_var_atomic_umin:
3727 op = LLVMAtomicRMWBinOpUMin;
3728 break;
3729 case nir_intrinsic_var_atomic_umax:
3730 op = LLVMAtomicRMWBinOpUMax;
3731 break;
3732 case nir_intrinsic_var_atomic_imin:
3733 op = LLVMAtomicRMWBinOpMin;
3734 break;
3735 case nir_intrinsic_var_atomic_imax:
3736 op = LLVMAtomicRMWBinOpMax;
3737 break;
3738 case nir_intrinsic_var_atomic_and:
3739 op = LLVMAtomicRMWBinOpAnd;
3740 break;
3741 case nir_intrinsic_var_atomic_or:
3742 op = LLVMAtomicRMWBinOpOr;
3743 break;
3744 case nir_intrinsic_var_atomic_xor:
3745 op = LLVMAtomicRMWBinOpXor;
3746 break;
3747 case nir_intrinsic_var_atomic_exchange:
3748 op = LLVMAtomicRMWBinOpXchg;
3749 break;
3750 default:
3751 return NULL;
3752 }
3753
3754 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(&ctx->ac, src),
3755 LLVMAtomicOrderingSequentiallyConsistent,
3756 false);
3757 }
3758 return result;
3759 }
3760
3761 #define INTERP_CENTER 0
3762 #define INTERP_CENTROID 1
3763 #define INTERP_SAMPLE 2
3764
3765 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3766 enum glsl_interp_mode interp, unsigned location)
3767 {
3768 switch (interp) {
3769 case INTERP_MODE_FLAT:
3770 default:
3771 return NULL;
3772 case INTERP_MODE_SMOOTH:
3773 case INTERP_MODE_NONE:
3774 if (location == INTERP_CENTER)
3775 return ctx->persp_center;
3776 else if (location == INTERP_CENTROID)
3777 return ctx->persp_centroid;
3778 else if (location == INTERP_SAMPLE)
3779 return ctx->persp_sample;
3780 break;
3781 case INTERP_MODE_NOPERSPECTIVE:
3782 if (location == INTERP_CENTER)
3783 return ctx->linear_center;
3784 else if (location == INTERP_CENTROID)
3785 return ctx->linear_centroid;
3786 else if (location == INTERP_SAMPLE)
3787 return ctx->linear_sample;
3788 break;
3789 }
3790 return NULL;
3791 }
3792
3793 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3794 LLVMValueRef sample_id)
3795 {
3796 LLVMValueRef result;
3797 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3798
3799 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3800 const_array(ctx->v2f32, 64), "");
3801
3802 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3803 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3804
3805 return result;
3806 }
3807
3808 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3809 {
3810 LLVMValueRef values[2];
3811
3812 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3813 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3814 return ac_build_gather_values(&ctx->ac, values, 2);
3815 }
3816
3817 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3818 const nir_intrinsic_instr *instr)
3819 {
3820 LLVMValueRef result[2];
3821 LLVMValueRef interp_param, attr_number;
3822 unsigned location;
3823 unsigned chan;
3824 LLVMValueRef src_c0 = NULL;
3825 LLVMValueRef src_c1 = NULL;
3826 LLVMValueRef src0 = NULL;
3827 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3828 switch (instr->intrinsic) {
3829 case nir_intrinsic_interp_var_at_centroid:
3830 location = INTERP_CENTROID;
3831 break;
3832 case nir_intrinsic_interp_var_at_sample:
3833 case nir_intrinsic_interp_var_at_offset:
3834 location = INTERP_CENTER;
3835 src0 = get_src(ctx->nir, instr->src[0]);
3836 break;
3837 default:
3838 break;
3839 }
3840
3841 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3842 src_c0 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3843 src_c1 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3844 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3845 LLVMValueRef sample_position;
3846 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3847
3848 /* fetch sample ID */
3849 sample_position = load_sample_position(ctx, src0);
3850
3851 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3852 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3853 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3854 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3855 }
3856 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3857 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3858
3859 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3860 LLVMValueRef ij_out[2];
3861 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3862
3863 /*
3864 * take the I then J parameters, and the DDX/Y for it, and
3865 * calculate the IJ inputs for the interpolator.
3866 * temp1 = ddx * offset/sample.x + I;
3867 * interp_param.I = ddy * offset/sample.y + temp1;
3868 * temp1 = ddx * offset/sample.x + J;
3869 * interp_param.J = ddy * offset/sample.y + temp1;
3870 */
3871 for (unsigned i = 0; i < 2; i++) {
3872 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3873 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3874 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3875 ddxy_out, ix_ll, "");
3876 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3877 ddxy_out, iy_ll, "");
3878 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3879 interp_param, ix_ll, "");
3880 LLVMValueRef temp1, temp2;
3881
3882 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3883 ctx->f32, "");
3884
3885 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3886 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3887
3888 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3889 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3890
3891 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3892 temp2, ctx->i32, "");
3893 }
3894 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3895
3896 }
3897
3898 for (chan = 0; chan < 2; chan++) {
3899 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3900
3901 if (interp_param) {
3902 interp_param = LLVMBuildBitCast(ctx->builder,
3903 interp_param, LLVMVectorType(ctx->f32, 2), "");
3904 LLVMValueRef i = LLVMBuildExtractElement(
3905 ctx->builder, interp_param, ctx->i32zero, "");
3906 LLVMValueRef j = LLVMBuildExtractElement(
3907 ctx->builder, interp_param, ctx->i32one, "");
3908
3909 result[chan] = ac_build_fs_interp(&ctx->ac,
3910 llvm_chan, attr_number,
3911 ctx->prim_mask, i, j);
3912 } else {
3913 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3914 LLVMConstInt(ctx->i32, 2, false),
3915 llvm_chan, attr_number,
3916 ctx->prim_mask);
3917 }
3918 }
3919 return ac_build_gather_values(&ctx->ac, result, 2);
3920 }
3921
3922 static void
3923 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3924 const nir_intrinsic_instr *instr)
3925 {
3926 LLVMValueRef gs_next_vertex;
3927 LLVMValueRef can_emit, kill;
3928 int idx;
3929
3930 assert(instr->const_index[0] == 0);
3931 /* Write vertex attribute values to GSVS ring */
3932 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3933 ctx->gs_next_vertex,
3934 "");
3935
3936 /* If this thread has already emitted the declared maximum number of
3937 * vertices, kill it: excessive vertex emissions are not supposed to
3938 * have any effect, and GS threads have no externally observable
3939 * effects other than emitting vertices.
3940 */
3941 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3942 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3943
3944 kill = LLVMBuildSelect(ctx->builder, can_emit,
3945 LLVMConstReal(ctx->f32, 1.0f),
3946 LLVMConstReal(ctx->f32, -1.0f), "");
3947 ac_build_kill(&ctx->ac, kill);
3948
3949 /* loop num outputs */
3950 idx = 0;
3951 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3952 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
3953 int length = 4;
3954 int slot = idx;
3955 int slot_inc = 1;
3956
3957 if (!(ctx->output_mask & (1ull << i)))
3958 continue;
3959
3960 if (i == VARYING_SLOT_CLIP_DIST0) {
3961 /* pack clip and cull into a single set of slots */
3962 length = ctx->num_output_clips + ctx->num_output_culls;
3963 if (length > 4)
3964 slot_inc = 2;
3965 }
3966 for (unsigned j = 0; j < length; j++) {
3967 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3968 out_ptr[j], "");
3969 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3970 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3971 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3972
3973 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3974
3975 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3976 out_val, 1,
3977 voffset, ctx->gs2vs_offset, 0,
3978 1, 1, true, true);
3979 }
3980 idx += slot_inc;
3981 }
3982
3983 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3984 ctx->i32one, "");
3985 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3986
3987 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3988 }
3989
3990 static void
3991 visit_end_primitive(struct nir_to_llvm_context *ctx,
3992 const nir_intrinsic_instr *instr)
3993 {
3994 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3995 }
3996
3997 static LLVMValueRef
3998 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3999 const nir_intrinsic_instr *instr)
4000 {
4001 LLVMValueRef coord[4] = {
4002 ctx->tes_u,
4003 ctx->tes_v,
4004 ctx->f32zero,
4005 ctx->f32zero,
4006 };
4007
4008 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4009 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
4010 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4011
4012 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4013 return LLVMBuildBitCast(ctx->builder, result,
4014 get_def_type(ctx->nir, &instr->dest.ssa), "");
4015 }
4016
4017 static void visit_intrinsic(struct ac_nir_context *ctx,
4018 nir_intrinsic_instr *instr)
4019 {
4020 LLVMValueRef result = NULL;
4021
4022 switch (instr->intrinsic) {
4023 case nir_intrinsic_load_work_group_id: {
4024 result = ctx->nctx->workgroup_ids;
4025 break;
4026 }
4027 case nir_intrinsic_load_base_vertex: {
4028 result = ctx->abi->base_vertex;
4029 break;
4030 }
4031 case nir_intrinsic_load_vertex_id_zero_base: {
4032 result = ctx->abi->vertex_id;
4033 break;
4034 }
4035 case nir_intrinsic_load_local_invocation_id: {
4036 result = ctx->nctx->local_invocation_ids;
4037 break;
4038 }
4039 case nir_intrinsic_load_base_instance:
4040 result = ctx->abi->start_instance;
4041 break;
4042 case nir_intrinsic_load_draw_id:
4043 result = ctx->abi->draw_id;
4044 break;
4045 case nir_intrinsic_load_view_index:
4046 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4047 break;
4048 case nir_intrinsic_load_invocation_id:
4049 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4050 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4051 else
4052 result = ctx->nctx->gs_invocation_id;
4053 break;
4054 case nir_intrinsic_load_primitive_id:
4055 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4056 ctx->nctx->shader_info->gs.uses_prim_id = true;
4057 result = ctx->nctx->gs_prim_id;
4058 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4059 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4060 result = ctx->nctx->tcs_patch_id;
4061 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4062 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4063 result = ctx->nctx->tes_patch_id;
4064 } else
4065 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4066 break;
4067 case nir_intrinsic_load_sample_id:
4068 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4069 break;
4070 case nir_intrinsic_load_sample_pos:
4071 result = load_sample_pos(ctx);
4072 break;
4073 case nir_intrinsic_load_sample_mask_in:
4074 result = ctx->abi->sample_coverage;
4075 break;
4076 case nir_intrinsic_load_frag_coord: {
4077 LLVMValueRef values[4] = {
4078 ctx->abi->frag_pos[0],
4079 ctx->abi->frag_pos[1],
4080 ctx->abi->frag_pos[2],
4081 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4082 };
4083 result = ac_build_gather_values(&ctx->ac, values, 4);
4084 break;
4085 }
4086 case nir_intrinsic_load_front_face:
4087 result = ctx->abi->front_face;
4088 break;
4089 case nir_intrinsic_load_instance_id:
4090 result = ctx->abi->instance_id;
4091 break;
4092 case nir_intrinsic_load_num_work_groups:
4093 result = ctx->nctx->num_work_groups;
4094 break;
4095 case nir_intrinsic_load_local_invocation_index:
4096 result = visit_load_local_invocation_index(ctx->nctx);
4097 break;
4098 case nir_intrinsic_load_push_constant:
4099 result = visit_load_push_constant(ctx->nctx, instr);
4100 break;
4101 case nir_intrinsic_vulkan_resource_index:
4102 result = visit_vulkan_resource_index(ctx->nctx, instr);
4103 break;
4104 case nir_intrinsic_store_ssbo:
4105 visit_store_ssbo(ctx, instr);
4106 break;
4107 case nir_intrinsic_load_ssbo:
4108 result = visit_load_buffer(ctx, instr);
4109 break;
4110 case nir_intrinsic_ssbo_atomic_add:
4111 case nir_intrinsic_ssbo_atomic_imin:
4112 case nir_intrinsic_ssbo_atomic_umin:
4113 case nir_intrinsic_ssbo_atomic_imax:
4114 case nir_intrinsic_ssbo_atomic_umax:
4115 case nir_intrinsic_ssbo_atomic_and:
4116 case nir_intrinsic_ssbo_atomic_or:
4117 case nir_intrinsic_ssbo_atomic_xor:
4118 case nir_intrinsic_ssbo_atomic_exchange:
4119 case nir_intrinsic_ssbo_atomic_comp_swap:
4120 result = visit_atomic_ssbo(ctx, instr);
4121 break;
4122 case nir_intrinsic_load_ubo:
4123 result = visit_load_ubo_buffer(ctx, instr);
4124 break;
4125 case nir_intrinsic_get_buffer_size:
4126 result = visit_get_buffer_size(ctx, instr);
4127 break;
4128 case nir_intrinsic_load_var:
4129 result = visit_load_var(ctx, instr);
4130 break;
4131 case nir_intrinsic_store_var:
4132 visit_store_var(ctx, instr);
4133 break;
4134 case nir_intrinsic_image_load:
4135 result = visit_image_load(ctx, instr);
4136 break;
4137 case nir_intrinsic_image_store:
4138 visit_image_store(ctx, instr);
4139 break;
4140 case nir_intrinsic_image_atomic_add:
4141 case nir_intrinsic_image_atomic_min:
4142 case nir_intrinsic_image_atomic_max:
4143 case nir_intrinsic_image_atomic_and:
4144 case nir_intrinsic_image_atomic_or:
4145 case nir_intrinsic_image_atomic_xor:
4146 case nir_intrinsic_image_atomic_exchange:
4147 case nir_intrinsic_image_atomic_comp_swap:
4148 result = visit_image_atomic(ctx, instr);
4149 break;
4150 case nir_intrinsic_image_size:
4151 result = visit_image_size(ctx, instr);
4152 break;
4153 case nir_intrinsic_discard:
4154 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4155 LLVMVoidTypeInContext(ctx->ac.context),
4156 NULL, 0, AC_FUNC_ATTR_LEGACY);
4157 break;
4158 case nir_intrinsic_discard_if:
4159 emit_discard_if(ctx, instr);
4160 break;
4161 case nir_intrinsic_memory_barrier:
4162 emit_waitcnt(ctx->nctx, VM_CNT);
4163 break;
4164 case nir_intrinsic_barrier:
4165 emit_barrier(ctx->nctx);
4166 break;
4167 case nir_intrinsic_var_atomic_add:
4168 case nir_intrinsic_var_atomic_imin:
4169 case nir_intrinsic_var_atomic_umin:
4170 case nir_intrinsic_var_atomic_imax:
4171 case nir_intrinsic_var_atomic_umax:
4172 case nir_intrinsic_var_atomic_and:
4173 case nir_intrinsic_var_atomic_or:
4174 case nir_intrinsic_var_atomic_xor:
4175 case nir_intrinsic_var_atomic_exchange:
4176 case nir_intrinsic_var_atomic_comp_swap:
4177 result = visit_var_atomic(ctx->nctx, instr);
4178 break;
4179 case nir_intrinsic_interp_var_at_centroid:
4180 case nir_intrinsic_interp_var_at_sample:
4181 case nir_intrinsic_interp_var_at_offset:
4182 result = visit_interp(ctx->nctx, instr);
4183 break;
4184 case nir_intrinsic_emit_vertex:
4185 visit_emit_vertex(ctx->nctx, instr);
4186 break;
4187 case nir_intrinsic_end_primitive:
4188 visit_end_primitive(ctx->nctx, instr);
4189 break;
4190 case nir_intrinsic_load_tess_coord:
4191 result = visit_load_tess_coord(ctx->nctx, instr);
4192 break;
4193 case nir_intrinsic_load_patch_vertices_in:
4194 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4195 break;
4196 default:
4197 fprintf(stderr, "Unknown intrinsic: ");
4198 nir_print_instr(&instr->instr, stderr);
4199 fprintf(stderr, "\n");
4200 break;
4201 }
4202 if (result) {
4203 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4204 }
4205 }
4206
4207 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4208 LLVMValueRef buffer, bool write)
4209 {
4210 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4211
4212 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4213 ctx->shader_info->fs.writes_memory = true;
4214
4215 return buffer;
4216 }
4217
4218 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4219 unsigned descriptor_set,
4220 unsigned base_index,
4221 unsigned constant_index,
4222 LLVMValueRef index,
4223 enum ac_descriptor_type desc_type,
4224 bool image, bool write)
4225 {
4226 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4227 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4228 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4229 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4230 unsigned offset = binding->offset;
4231 unsigned stride = binding->size;
4232 unsigned type_size;
4233 LLVMBuilderRef builder = ctx->builder;
4234 LLVMTypeRef type;
4235
4236 assert(base_index < layout->binding_count);
4237
4238 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4239 ctx->shader_info->fs.writes_memory = true;
4240
4241 switch (desc_type) {
4242 case AC_DESC_IMAGE:
4243 type = ctx->v8i32;
4244 type_size = 32;
4245 break;
4246 case AC_DESC_FMASK:
4247 type = ctx->v8i32;
4248 offset += 32;
4249 type_size = 32;
4250 break;
4251 case AC_DESC_SAMPLER:
4252 type = ctx->v4i32;
4253 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4254 offset += 64;
4255
4256 type_size = 16;
4257 break;
4258 case AC_DESC_BUFFER:
4259 type = ctx->v4i32;
4260 type_size = 16;
4261 break;
4262 default:
4263 unreachable("invalid desc_type\n");
4264 }
4265
4266 offset += constant_index * stride;
4267
4268 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4269 (!index || binding->immutable_samplers_equal)) {
4270 if (binding->immutable_samplers_equal)
4271 constant_index = 0;
4272
4273 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4274
4275 LLVMValueRef constants[] = {
4276 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4277 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4278 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4279 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4280 };
4281 return ac_build_gather_values(&ctx->ac, constants, 4);
4282 }
4283
4284 assert(stride % type_size == 0);
4285
4286 if (!index)
4287 index = ctx->i32zero;
4288
4289 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4290
4291 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4292 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4293
4294 return ac_build_indexed_load_const(&ctx->ac, list, index);
4295 }
4296
4297 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4298 const nir_deref_var *deref,
4299 enum ac_descriptor_type desc_type,
4300 bool image, bool write)
4301 {
4302 LLVMValueRef index = NULL;
4303 unsigned constant_index = 0;
4304 const nir_deref *tail = &deref->deref;
4305
4306 while (tail->child) {
4307 const nir_deref_array *child = nir_deref_as_array(tail->child);
4308 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4309
4310 if (!array_size)
4311 array_size = 1;
4312
4313 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4314
4315 if (child->deref_array_type == nir_deref_array_type_indirect) {
4316 LLVMValueRef indirect = get_src(ctx, child->indirect);
4317
4318 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4319 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4320
4321 if (!index)
4322 index = indirect;
4323 else
4324 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4325 }
4326
4327 constant_index += child->base_offset * array_size;
4328
4329 tail = &child->deref;
4330 }
4331
4332 return ctx->abi->load_sampler_desc(ctx->abi,
4333 deref->var->data.descriptor_set,
4334 deref->var->data.binding,
4335 constant_index, index,
4336 desc_type, image, write);
4337 }
4338
4339 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4340 struct ac_image_args *args,
4341 const nir_tex_instr *instr,
4342 nir_texop op,
4343 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4344 LLVMValueRef *param, unsigned count,
4345 unsigned dmask)
4346 {
4347 unsigned is_rect = 0;
4348 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4349
4350 if (op == nir_texop_lod)
4351 da = false;
4352 /* Pad to power of two vector */
4353 while (count < util_next_power_of_two(count))
4354 param[count++] = LLVMGetUndef(ctx->i32);
4355
4356 if (count > 1)
4357 args->addr = ac_build_gather_values(ctx, param, count);
4358 else
4359 args->addr = param[0];
4360
4361 args->resource = res_ptr;
4362 args->sampler = samp_ptr;
4363
4364 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4365 args->addr = param[0];
4366 return;
4367 }
4368
4369 args->dmask = dmask;
4370 args->unorm = is_rect;
4371 args->da = da;
4372 }
4373
4374 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4375 *
4376 * SI-CI:
4377 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4378 * filtering manually. The driver sets img7 to a mask clearing
4379 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4380 * s_and_b32 samp0, samp0, img7
4381 *
4382 * VI:
4383 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4384 */
4385 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4386 LLVMValueRef res, LLVMValueRef samp)
4387 {
4388 LLVMBuilderRef builder = ctx->ac.builder;
4389 LLVMValueRef img7, samp0;
4390
4391 if (ctx->abi->chip_class >= VI)
4392 return samp;
4393
4394 img7 = LLVMBuildExtractElement(builder, res,
4395 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4396 samp0 = LLVMBuildExtractElement(builder, samp,
4397 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4398 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4399 return LLVMBuildInsertElement(builder, samp, samp0,
4400 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4401 }
4402
4403 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4404 nir_tex_instr *instr,
4405 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4406 LLVMValueRef *fmask_ptr)
4407 {
4408 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4409 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, false, false);
4410 else
4411 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, false, false);
4412 if (samp_ptr) {
4413 if (instr->sampler)
4414 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, false, false);
4415 else
4416 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, false, false);
4417 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4418 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4419 }
4420 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4421 instr->op == nir_texop_samples_identical))
4422 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, false, false);
4423 }
4424
4425 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4426 LLVMValueRef coord)
4427 {
4428 coord = to_float(ctx, coord);
4429 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4430 coord = to_integer(ctx, coord);
4431 return coord;
4432 }
4433
4434 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4435 {
4436 LLVMValueRef result = NULL;
4437 struct ac_image_args args = { 0 };
4438 unsigned dmask = 0xf;
4439 LLVMValueRef address[16];
4440 LLVMValueRef coords[5];
4441 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4442 LLVMValueRef bias = NULL, offsets = NULL;
4443 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4444 LLVMValueRef ddx = NULL, ddy = NULL;
4445 LLVMValueRef derivs[6];
4446 unsigned chan, count = 0;
4447 unsigned const_src = 0, num_deriv_comp = 0;
4448 bool lod_is_zero = false;
4449
4450 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4451
4452 for (unsigned i = 0; i < instr->num_srcs; i++) {
4453 switch (instr->src[i].src_type) {
4454 case nir_tex_src_coord:
4455 coord = get_src(ctx, instr->src[i].src);
4456 break;
4457 case nir_tex_src_projector:
4458 break;
4459 case nir_tex_src_comparator:
4460 comparator = get_src(ctx, instr->src[i].src);
4461 break;
4462 case nir_tex_src_offset:
4463 offsets = get_src(ctx, instr->src[i].src);
4464 const_src = i;
4465 break;
4466 case nir_tex_src_bias:
4467 bias = get_src(ctx, instr->src[i].src);
4468 break;
4469 case nir_tex_src_lod: {
4470 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4471
4472 if (val && val->i32[0] == 0)
4473 lod_is_zero = true;
4474 lod = get_src(ctx, instr->src[i].src);
4475 break;
4476 }
4477 case nir_tex_src_ms_index:
4478 sample_index = get_src(ctx, instr->src[i].src);
4479 break;
4480 case nir_tex_src_ms_mcs:
4481 break;
4482 case nir_tex_src_ddx:
4483 ddx = get_src(ctx, instr->src[i].src);
4484 num_deriv_comp = instr->src[i].src.ssa->num_components;
4485 break;
4486 case nir_tex_src_ddy:
4487 ddy = get_src(ctx, instr->src[i].src);
4488 break;
4489 case nir_tex_src_texture_offset:
4490 case nir_tex_src_sampler_offset:
4491 case nir_tex_src_plane:
4492 default:
4493 break;
4494 }
4495 }
4496
4497 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4498 result = get_buffer_size(ctx, res_ptr, true);
4499 goto write_result;
4500 }
4501
4502 if (instr->op == nir_texop_texture_samples) {
4503 LLVMValueRef res, samples, is_msaa;
4504 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4505 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4506 LLVMConstInt(ctx->ac.i32, 3, false), "");
4507 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4508 LLVMConstInt(ctx->ac.i32, 28, false), "");
4509 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4510 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4511 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4512 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4513
4514 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4515 LLVMConstInt(ctx->ac.i32, 16, false), "");
4516 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4517 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4518 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4519 samples, "");
4520 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4521 ctx->ac.i32_1, "");
4522 result = samples;
4523 goto write_result;
4524 }
4525
4526 if (coord)
4527 for (chan = 0; chan < instr->coord_components; chan++)
4528 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4529
4530 if (offsets && instr->op != nir_texop_txf) {
4531 LLVMValueRef offset[3], pack;
4532 for (chan = 0; chan < 3; ++chan)
4533 offset[chan] = ctx->ac.i32_0;
4534
4535 args.offset = true;
4536 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4537 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4538 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4539 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4540 if (chan)
4541 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4542 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4543 }
4544 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4545 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4546 address[count++] = pack;
4547
4548 }
4549 /* pack LOD bias value */
4550 if (instr->op == nir_texop_txb && bias) {
4551 address[count++] = bias;
4552 }
4553
4554 /* Pack depth comparison value */
4555 if (instr->is_shadow && comparator) {
4556 LLVMValueRef z = to_float(&ctx->ac,
4557 llvm_extract_elem(&ctx->ac, comparator, 0));
4558
4559 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4560 * so the depth comparison value isn't clamped for Z16 and
4561 * Z24 anymore. Do it manually here.
4562 *
4563 * It's unnecessary if the original texture format was
4564 * Z32_FLOAT, but we don't know that here.
4565 */
4566 if (ctx->abi->chip_class == VI)
4567 z = ac_build_clamp(&ctx->ac, z);
4568
4569 address[count++] = z;
4570 }
4571
4572 /* pack derivatives */
4573 if (ddx || ddy) {
4574 switch (instr->sampler_dim) {
4575 case GLSL_SAMPLER_DIM_3D:
4576 case GLSL_SAMPLER_DIM_CUBE:
4577 num_deriv_comp = 3;
4578 break;
4579 case GLSL_SAMPLER_DIM_2D:
4580 default:
4581 num_deriv_comp = 2;
4582 break;
4583 case GLSL_SAMPLER_DIM_1D:
4584 num_deriv_comp = 1;
4585 break;
4586 }
4587
4588 for (unsigned i = 0; i < num_deriv_comp; i++) {
4589 derivs[i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4590 derivs[num_deriv_comp + i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4591 }
4592 }
4593
4594 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4595 if (instr->is_array && instr->op != nir_texop_lod)
4596 coords[3] = apply_round_slice(&ctx->ac, coords[3]);
4597 for (chan = 0; chan < instr->coord_components; chan++)
4598 coords[chan] = to_float(&ctx->ac, coords[chan]);
4599 if (instr->coord_components == 3)
4600 coords[3] = LLVMGetUndef(ctx->ac.f32);
4601 ac_prepare_cube_coords(&ctx->ac,
4602 instr->op == nir_texop_txd, instr->is_array,
4603 coords, derivs);
4604 if (num_deriv_comp)
4605 num_deriv_comp--;
4606 }
4607
4608 if (ddx || ddy) {
4609 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4610 address[count++] = derivs[i];
4611 }
4612
4613 /* Pack texture coordinates */
4614 if (coord) {
4615 address[count++] = coords[0];
4616 if (instr->coord_components > 1) {
4617 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4618 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4619 }
4620 address[count++] = coords[1];
4621 }
4622 if (instr->coord_components > 2) {
4623 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4624 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4625 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4626 instr->op != nir_texop_txf) {
4627 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4628 }
4629 address[count++] = coords[2];
4630 }
4631 }
4632
4633 /* Pack LOD */
4634 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4635 instr->op == nir_texop_txf)) {
4636 address[count++] = lod;
4637 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4638 address[count++] = sample_index;
4639 } else if(instr->op == nir_texop_txs) {
4640 count = 0;
4641 if (lod)
4642 address[count++] = lod;
4643 else
4644 address[count++] = ctx->ac.i32_0;
4645 }
4646
4647 for (chan = 0; chan < count; chan++) {
4648 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4649 address[chan], ctx->ac.i32, "");
4650 }
4651
4652 if (instr->op == nir_texop_samples_identical) {
4653 LLVMValueRef txf_address[4];
4654 struct ac_image_args txf_args = { 0 };
4655 unsigned txf_count = count;
4656 memcpy(txf_address, address, sizeof(txf_address));
4657
4658 if (!instr->is_array)
4659 txf_address[2] = ctx->ac.i32_0;
4660 txf_address[3] = ctx->ac.i32_0;
4661
4662 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4663 fmask_ptr, NULL,
4664 txf_address, txf_count, 0xf);
4665
4666 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4667
4668 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4669 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4670 goto write_result;
4671 }
4672
4673 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4674 instr->op != nir_texop_txs) {
4675 unsigned sample_chan = instr->is_array ? 3 : 2;
4676 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4677 address[0],
4678 address[1],
4679 instr->is_array ? address[2] : NULL,
4680 address[sample_chan],
4681 fmask_ptr);
4682 }
4683
4684 if (offsets && instr->op == nir_texop_txf) {
4685 nir_const_value *const_offset =
4686 nir_src_as_const_value(instr->src[const_src].src);
4687 int num_offsets = instr->src[const_src].src.ssa->num_components;
4688 assert(const_offset);
4689 num_offsets = MIN2(num_offsets, instr->coord_components);
4690 if (num_offsets > 2)
4691 address[2] = LLVMBuildAdd(ctx->ac.builder,
4692 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4693 if (num_offsets > 1)
4694 address[1] = LLVMBuildAdd(ctx->ac.builder,
4695 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4696 address[0] = LLVMBuildAdd(ctx->ac.builder,
4697 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4698
4699 }
4700
4701 /* TODO TG4 support */
4702 if (instr->op == nir_texop_tg4) {
4703 if (instr->is_shadow)
4704 dmask = 1;
4705 else
4706 dmask = 1 << instr->component;
4707 }
4708 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4709 res_ptr, samp_ptr, address, count, dmask);
4710
4711 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4712
4713 if (instr->op == nir_texop_query_levels)
4714 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4715 else if (instr->is_shadow && instr->is_new_style_shadow &&
4716 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4717 instr->op != nir_texop_tg4)
4718 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4719 else if (instr->op == nir_texop_txs &&
4720 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4721 instr->is_array) {
4722 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4723 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4724 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4725 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4726 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4727 } else if (instr->dest.ssa.num_components != 4)
4728 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4729
4730 write_result:
4731 if (result) {
4732 assert(instr->dest.is_ssa);
4733 result = to_integer(&ctx->ac, result);
4734 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4735 }
4736 }
4737
4738
4739 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4740 {
4741 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4742 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4743
4744 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4745 _mesa_hash_table_insert(ctx->phis, instr, result);
4746 }
4747
4748 static void visit_post_phi(struct ac_nir_context *ctx,
4749 nir_phi_instr *instr,
4750 LLVMValueRef llvm_phi)
4751 {
4752 nir_foreach_phi_src(src, instr) {
4753 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4754 LLVMValueRef llvm_src = get_src(ctx, src->src);
4755
4756 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4757 }
4758 }
4759
4760 static void phi_post_pass(struct ac_nir_context *ctx)
4761 {
4762 struct hash_entry *entry;
4763 hash_table_foreach(ctx->phis, entry) {
4764 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4765 (LLVMValueRef)entry->data);
4766 }
4767 }
4768
4769
4770 static void visit_ssa_undef(struct ac_nir_context *ctx,
4771 const nir_ssa_undef_instr *instr)
4772 {
4773 unsigned num_components = instr->def.num_components;
4774 LLVMValueRef undef;
4775
4776 if (num_components == 1)
4777 undef = LLVMGetUndef(ctx->ac.i32);
4778 else {
4779 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4780 }
4781 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4782 }
4783
4784 static void visit_jump(struct ac_nir_context *ctx,
4785 const nir_jump_instr *instr)
4786 {
4787 switch (instr->type) {
4788 case nir_jump_break:
4789 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4790 LLVMClearInsertionPosition(ctx->ac.builder);
4791 break;
4792 case nir_jump_continue:
4793 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4794 LLVMClearInsertionPosition(ctx->ac.builder);
4795 break;
4796 default:
4797 fprintf(stderr, "Unknown NIR jump instr: ");
4798 nir_print_instr(&instr->instr, stderr);
4799 fprintf(stderr, "\n");
4800 abort();
4801 }
4802 }
4803
4804 static void visit_cf_list(struct ac_nir_context *ctx,
4805 struct exec_list *list);
4806
4807 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4808 {
4809 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4810 nir_foreach_instr(instr, block)
4811 {
4812 switch (instr->type) {
4813 case nir_instr_type_alu:
4814 visit_alu(ctx, nir_instr_as_alu(instr));
4815 break;
4816 case nir_instr_type_load_const:
4817 visit_load_const(ctx, nir_instr_as_load_const(instr));
4818 break;
4819 case nir_instr_type_intrinsic:
4820 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4821 break;
4822 case nir_instr_type_tex:
4823 visit_tex(ctx, nir_instr_as_tex(instr));
4824 break;
4825 case nir_instr_type_phi:
4826 visit_phi(ctx, nir_instr_as_phi(instr));
4827 break;
4828 case nir_instr_type_ssa_undef:
4829 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4830 break;
4831 case nir_instr_type_jump:
4832 visit_jump(ctx, nir_instr_as_jump(instr));
4833 break;
4834 default:
4835 fprintf(stderr, "Unknown NIR instr type: ");
4836 nir_print_instr(instr, stderr);
4837 fprintf(stderr, "\n");
4838 abort();
4839 }
4840 }
4841
4842 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4843 }
4844
4845 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4846 {
4847 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4848
4849 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4850 LLVMBasicBlockRef merge_block =
4851 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4852 LLVMBasicBlockRef if_block =
4853 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4854 LLVMBasicBlockRef else_block = merge_block;
4855 if (!exec_list_is_empty(&if_stmt->else_list))
4856 else_block = LLVMAppendBasicBlockInContext(
4857 ctx->ac.context, fn, "");
4858
4859 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4860 LLVMConstInt(ctx->ac.i32, 0, false), "");
4861 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4862
4863 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4864 visit_cf_list(ctx, &if_stmt->then_list);
4865 if (LLVMGetInsertBlock(ctx->ac.builder))
4866 LLVMBuildBr(ctx->ac.builder, merge_block);
4867
4868 if (!exec_list_is_empty(&if_stmt->else_list)) {
4869 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4870 visit_cf_list(ctx, &if_stmt->else_list);
4871 if (LLVMGetInsertBlock(ctx->ac.builder))
4872 LLVMBuildBr(ctx->ac.builder, merge_block);
4873 }
4874
4875 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4876 }
4877
4878 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4879 {
4880 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4881 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4882 LLVMBasicBlockRef break_parent = ctx->break_block;
4883
4884 ctx->continue_block =
4885 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4886 ctx->break_block =
4887 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4888
4889 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4890 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4891 visit_cf_list(ctx, &loop->body);
4892
4893 if (LLVMGetInsertBlock(ctx->ac.builder))
4894 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4895 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4896
4897 ctx->continue_block = continue_parent;
4898 ctx->break_block = break_parent;
4899 }
4900
4901 static void visit_cf_list(struct ac_nir_context *ctx,
4902 struct exec_list *list)
4903 {
4904 foreach_list_typed(nir_cf_node, node, node, list)
4905 {
4906 switch (node->type) {
4907 case nir_cf_node_block:
4908 visit_block(ctx, nir_cf_node_as_block(node));
4909 break;
4910
4911 case nir_cf_node_if:
4912 visit_if(ctx, nir_cf_node_as_if(node));
4913 break;
4914
4915 case nir_cf_node_loop:
4916 visit_loop(ctx, nir_cf_node_as_loop(node));
4917 break;
4918
4919 default:
4920 assert(0);
4921 }
4922 }
4923 }
4924
4925 static void
4926 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4927 struct nir_variable *variable)
4928 {
4929 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4930 LLVMValueRef t_offset;
4931 LLVMValueRef t_list;
4932 LLVMValueRef input;
4933 LLVMValueRef buffer_index;
4934 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4935 int idx = variable->data.location;
4936 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4937
4938 variable->data.driver_location = idx * 4;
4939
4940 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4941 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
4942 ctx->abi.start_instance, "");
4943 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4944 ctx->shader_info->vs.vgpr_comp_cnt);
4945 } else
4946 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
4947 ctx->abi.base_vertex, "");
4948
4949 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4950 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4951
4952 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4953
4954 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4955 buffer_index,
4956 LLVMConstInt(ctx->i32, 0, false),
4957 true);
4958
4959 for (unsigned chan = 0; chan < 4; chan++) {
4960 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4961 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4962 to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
4963 input, llvm_chan, ""));
4964 }
4965 }
4966 }
4967
4968 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4969 unsigned attr,
4970 LLVMValueRef interp_param,
4971 LLVMValueRef prim_mask,
4972 LLVMValueRef result[4])
4973 {
4974 LLVMValueRef attr_number;
4975 unsigned chan;
4976 LLVMValueRef i, j;
4977 bool interp = interp_param != NULL;
4978
4979 attr_number = LLVMConstInt(ctx->i32, attr, false);
4980
4981 /* fs.constant returns the param from the middle vertex, so it's not
4982 * really useful for flat shading. It's meant to be used for custom
4983 * interpolation (but the intrinsic can't fetch from the other two
4984 * vertices).
4985 *
4986 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4987 * to do the right thing. The only reason we use fs.constant is that
4988 * fs.interp cannot be used on integers, because they can be equal
4989 * to NaN.
4990 */
4991 if (interp) {
4992 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4993 LLVMVectorType(ctx->f32, 2), "");
4994
4995 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4996 ctx->i32zero, "");
4997 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4998 ctx->i32one, "");
4999 }
5000
5001 for (chan = 0; chan < 4; chan++) {
5002 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
5003
5004 if (interp) {
5005 result[chan] = ac_build_fs_interp(&ctx->ac,
5006 llvm_chan,
5007 attr_number,
5008 prim_mask, i, j);
5009 } else {
5010 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5011 LLVMConstInt(ctx->i32, 2, false),
5012 llvm_chan,
5013 attr_number,
5014 prim_mask);
5015 }
5016 }
5017 }
5018
5019 static void
5020 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5021 struct nir_variable *variable)
5022 {
5023 int idx = variable->data.location;
5024 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5025 LLVMValueRef interp;
5026
5027 variable->data.driver_location = idx * 4;
5028 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5029
5030 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5031 unsigned interp_type;
5032 if (variable->data.sample) {
5033 interp_type = INTERP_SAMPLE;
5034 ctx->shader_info->info.ps.force_persample = true;
5035 } else if (variable->data.centroid)
5036 interp_type = INTERP_CENTROID;
5037 else
5038 interp_type = INTERP_CENTER;
5039
5040 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5041 } else
5042 interp = NULL;
5043
5044 for (unsigned i = 0; i < attrib_count; ++i)
5045 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5046
5047 }
5048
5049 static void
5050 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5051 struct nir_shader *nir) {
5052 nir_foreach_variable(variable, &nir->inputs)
5053 handle_vs_input_decl(ctx, variable);
5054 }
5055
5056 static void
5057 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5058 struct nir_shader *nir)
5059 {
5060 if (!ctx->options->key.fs.multisample)
5061 return;
5062
5063 bool uses_center = false;
5064 bool uses_centroid = false;
5065 nir_foreach_variable(variable, &nir->inputs) {
5066 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5067 variable->data.sample)
5068 continue;
5069
5070 if (variable->data.centroid)
5071 uses_centroid = true;
5072 else
5073 uses_center = true;
5074 }
5075
5076 if (uses_center && uses_centroid) {
5077 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5078 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5079 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5080 }
5081 }
5082
5083 static void
5084 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5085 struct nir_shader *nir)
5086 {
5087 prepare_interp_optimize(ctx, nir);
5088
5089 nir_foreach_variable(variable, &nir->inputs)
5090 handle_fs_input_decl(ctx, variable);
5091
5092 unsigned index = 0;
5093
5094 if (ctx->shader_info->info.ps.uses_input_attachments ||
5095 ctx->shader_info->info.needs_multiview_view_index)
5096 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5097
5098 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5099 LLVMValueRef interp_param;
5100 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5101
5102 if (!(ctx->input_mask & (1ull << i)))
5103 continue;
5104
5105 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5106 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5107 interp_param = *inputs;
5108 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5109 inputs);
5110
5111 if (!interp_param)
5112 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5113 ++index;
5114 } else if (i == VARYING_SLOT_POS) {
5115 for(int i = 0; i < 3; ++i)
5116 inputs[i] = ctx->abi.frag_pos[i];
5117
5118 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one,
5119 ctx->abi.frag_pos[3]);
5120 }
5121 }
5122 ctx->shader_info->fs.num_interp = index;
5123 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5124 ctx->shader_info->fs.has_pcoord = true;
5125 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5126 ctx->shader_info->fs.prim_id_input = true;
5127 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5128 ctx->shader_info->fs.layer_input = true;
5129 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5130
5131 if (ctx->shader_info->info.needs_multiview_view_index)
5132 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5133 }
5134
5135 static LLVMValueRef
5136 ac_build_alloca(struct ac_llvm_context *ac,
5137 LLVMTypeRef type,
5138 const char *name)
5139 {
5140 LLVMBuilderRef builder = ac->builder;
5141 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5142 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5143 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5144 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5145 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5146 LLVMValueRef res;
5147
5148 if (first_instr) {
5149 LLVMPositionBuilderBefore(first_builder, first_instr);
5150 } else {
5151 LLVMPositionBuilderAtEnd(first_builder, first_block);
5152 }
5153
5154 res = LLVMBuildAlloca(first_builder, type, name);
5155 LLVMBuildStore(builder, LLVMConstNull(type), res);
5156
5157 LLVMDisposeBuilder(first_builder);
5158
5159 return res;
5160 }
5161
5162 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5163 LLVMTypeRef type,
5164 const char *name)
5165 {
5166 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5167 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5168 return ptr;
5169 }
5170
5171 static void
5172 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5173 struct nir_variable *variable)
5174 {
5175 int idx = variable->data.location + variable->data.index;
5176 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5177 uint64_t mask_attribs;
5178
5179 variable->data.driver_location = idx * 4;
5180
5181 /* tess ctrl has it's own load/store paths for outputs */
5182 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5183 return;
5184
5185 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5186 if (ctx->stage == MESA_SHADER_VERTEX ||
5187 ctx->stage == MESA_SHADER_TESS_EVAL ||
5188 ctx->stage == MESA_SHADER_GEOMETRY) {
5189 if (idx == VARYING_SLOT_CLIP_DIST0) {
5190 int length = ctx->num_output_clips + ctx->num_output_culls;
5191 if (ctx->stage == MESA_SHADER_VERTEX) {
5192 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5193 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5194 }
5195 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5196 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5197 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5198 }
5199
5200 if (length > 4)
5201 attrib_count = 2;
5202 else
5203 attrib_count = 1;
5204 mask_attribs = 1ull << idx;
5205 }
5206 }
5207
5208 ctx->output_mask |= mask_attribs;
5209 }
5210
5211 static void
5212 handle_shader_output_decl(struct ac_nir_context *ctx,
5213 struct nir_shader *nir,
5214 struct nir_variable *variable)
5215 {
5216 unsigned output_loc = variable->data.driver_location / 4;
5217 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5218
5219 /* tess ctrl has it's own load/store paths for outputs */
5220 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5221 return;
5222
5223 if (ctx->stage == MESA_SHADER_VERTEX ||
5224 ctx->stage == MESA_SHADER_TESS_EVAL ||
5225 ctx->stage == MESA_SHADER_GEOMETRY) {
5226 int idx = variable->data.location + variable->data.index;
5227 if (idx == VARYING_SLOT_CLIP_DIST0) {
5228 int length = nir->info.clip_distance_array_size +
5229 nir->info.cull_distance_array_size;
5230
5231 if (length > 4)
5232 attrib_count = 2;
5233 else
5234 attrib_count = 1;
5235 }
5236 }
5237
5238 for (unsigned i = 0; i < attrib_count; ++i) {
5239 for (unsigned chan = 0; chan < 4; chan++) {
5240 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5241 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5242 }
5243 }
5244 }
5245
5246 static LLVMTypeRef
5247 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5248 enum glsl_base_type type)
5249 {
5250 switch (type) {
5251 case GLSL_TYPE_INT:
5252 case GLSL_TYPE_UINT:
5253 case GLSL_TYPE_BOOL:
5254 case GLSL_TYPE_SUBROUTINE:
5255 return ctx->i32;
5256 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5257 return ctx->f32;
5258 case GLSL_TYPE_INT64:
5259 case GLSL_TYPE_UINT64:
5260 return ctx->i64;
5261 case GLSL_TYPE_DOUBLE:
5262 return ctx->f64;
5263 default:
5264 unreachable("unknown GLSL type");
5265 }
5266 }
5267
5268 static LLVMTypeRef
5269 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5270 const struct glsl_type *type)
5271 {
5272 if (glsl_type_is_scalar(type)) {
5273 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5274 }
5275
5276 if (glsl_type_is_vector(type)) {
5277 return LLVMVectorType(
5278 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5279 glsl_get_vector_elements(type));
5280 }
5281
5282 if (glsl_type_is_matrix(type)) {
5283 return LLVMArrayType(
5284 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5285 glsl_get_matrix_columns(type));
5286 }
5287
5288 if (glsl_type_is_array(type)) {
5289 return LLVMArrayType(
5290 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5291 glsl_get_length(type));
5292 }
5293
5294 assert(glsl_type_is_struct(type));
5295
5296 LLVMTypeRef member_types[glsl_get_length(type)];
5297
5298 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5299 member_types[i] =
5300 glsl_to_llvm_type(ctx,
5301 glsl_get_struct_field(type, i));
5302 }
5303
5304 return LLVMStructTypeInContext(ctx->context, member_types,
5305 glsl_get_length(type), false);
5306 }
5307
5308 static void
5309 setup_locals(struct ac_nir_context *ctx,
5310 struct nir_function *func)
5311 {
5312 int i, j;
5313 ctx->num_locals = 0;
5314 nir_foreach_variable(variable, &func->impl->locals) {
5315 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5316 variable->data.driver_location = ctx->num_locals * 4;
5317 ctx->num_locals += attrib_count;
5318 }
5319 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5320 if (!ctx->locals)
5321 return;
5322
5323 for (i = 0; i < ctx->num_locals; i++) {
5324 for (j = 0; j < 4; j++) {
5325 ctx->locals[i * 4 + j] =
5326 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5327 }
5328 }
5329 }
5330
5331 static void
5332 setup_shared(struct ac_nir_context *ctx,
5333 struct nir_shader *nir)
5334 {
5335 nir_foreach_variable(variable, &nir->shared) {
5336 LLVMValueRef shared =
5337 LLVMAddGlobalInAddressSpace(
5338 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5339 variable->name ? variable->name : "",
5340 LOCAL_ADDR_SPACE);
5341 _mesa_hash_table_insert(ctx->vars, variable, shared);
5342 }
5343 }
5344
5345 static LLVMValueRef
5346 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5347 {
5348 v = to_float(ctx, v);
5349 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5350 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5351 }
5352
5353
5354 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5355 LLVMValueRef src0, LLVMValueRef src1)
5356 {
5357 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5358 LLVMValueRef comp[2];
5359
5360 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5361 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5362 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5363 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5364 }
5365
5366 /* Initialize arguments for the shader export intrinsic */
5367 static void
5368 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5369 LLVMValueRef *values,
5370 unsigned target,
5371 struct ac_export_args *args)
5372 {
5373 /* Default is 0xf. Adjusted below depending on the format. */
5374 args->enabled_channels = 0xf;
5375
5376 /* Specify whether the EXEC mask represents the valid mask */
5377 args->valid_mask = 0;
5378
5379 /* Specify whether this is the last export */
5380 args->done = 0;
5381
5382 /* Specify the target we are exporting */
5383 args->target = target;
5384
5385 args->compr = false;
5386 args->out[0] = LLVMGetUndef(ctx->f32);
5387 args->out[1] = LLVMGetUndef(ctx->f32);
5388 args->out[2] = LLVMGetUndef(ctx->f32);
5389 args->out[3] = LLVMGetUndef(ctx->f32);
5390
5391 if (!values)
5392 return;
5393
5394 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5395 LLVMValueRef val[4];
5396 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5397 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5398 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5399 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5400
5401 switch(col_format) {
5402 case V_028714_SPI_SHADER_ZERO:
5403 args->enabled_channels = 0; /* writemask */
5404 args->target = V_008DFC_SQ_EXP_NULL;
5405 break;
5406
5407 case V_028714_SPI_SHADER_32_R:
5408 args->enabled_channels = 1;
5409 args->out[0] = values[0];
5410 break;
5411
5412 case V_028714_SPI_SHADER_32_GR:
5413 args->enabled_channels = 0x3;
5414 args->out[0] = values[0];
5415 args->out[1] = values[1];
5416 break;
5417
5418 case V_028714_SPI_SHADER_32_AR:
5419 args->enabled_channels = 0x9;
5420 args->out[0] = values[0];
5421 args->out[3] = values[3];
5422 break;
5423
5424 case V_028714_SPI_SHADER_FP16_ABGR:
5425 args->compr = 1;
5426
5427 for (unsigned chan = 0; chan < 2; chan++) {
5428 LLVMValueRef pack_args[2] = {
5429 values[2 * chan],
5430 values[2 * chan + 1]
5431 };
5432 LLVMValueRef packed;
5433
5434 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5435 args->out[chan] = packed;
5436 }
5437 break;
5438
5439 case V_028714_SPI_SHADER_UNORM16_ABGR:
5440 for (unsigned chan = 0; chan < 4; chan++) {
5441 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5442 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5443 LLVMConstReal(ctx->f32, 65535), "");
5444 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5445 LLVMConstReal(ctx->f32, 0.5), "");
5446 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5447 ctx->i32, "");
5448 }
5449
5450 args->compr = 1;
5451 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5452 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5453 break;
5454
5455 case V_028714_SPI_SHADER_SNORM16_ABGR:
5456 for (unsigned chan = 0; chan < 4; chan++) {
5457 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5458 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5459 LLVMConstReal(ctx->f32, 32767), "");
5460
5461 /* If positive, add 0.5, else add -0.5. */
5462 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5463 LLVMBuildSelect(ctx->builder,
5464 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5465 val[chan], ctx->f32zero, ""),
5466 LLVMConstReal(ctx->f32, 0.5),
5467 LLVMConstReal(ctx->f32, -0.5), ""), "");
5468 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5469 }
5470
5471 args->compr = 1;
5472 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5473 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5474 break;
5475
5476 case V_028714_SPI_SHADER_UINT16_ABGR: {
5477 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5478 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5479 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
5480
5481 for (unsigned chan = 0; chan < 4; chan++) {
5482 val[chan] = to_integer(&ctx->ac, values[chan]);
5483 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5484 }
5485
5486 args->compr = 1;
5487 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5488 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5489 break;
5490 }
5491
5492 case V_028714_SPI_SHADER_SINT16_ABGR: {
5493 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5494 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5495 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
5496 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5497 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->i32one;
5498 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
5499
5500 /* Clamp. */
5501 for (unsigned chan = 0; chan < 4; chan++) {
5502 val[chan] = to_integer(&ctx->ac, values[chan]);
5503 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5504 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5505 }
5506
5507 args->compr = 1;
5508 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5509 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5510 break;
5511 }
5512
5513 default:
5514 case V_028714_SPI_SHADER_32_ABGR:
5515 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5516 break;
5517 }
5518 } else
5519 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5520
5521 for (unsigned i = 0; i < 4; ++i)
5522 args->out[i] = to_float(&ctx->ac, args->out[i]);
5523 }
5524
5525 static void
5526 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5527 bool export_prim_id,
5528 struct ac_vs_output_info *outinfo)
5529 {
5530 uint32_t param_count = 0;
5531 unsigned target;
5532 unsigned pos_idx, num_pos_exports = 0;
5533 struct ac_export_args args, pos_args[4] = {};
5534 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5535 int i;
5536
5537 if (ctx->options->key.has_multiview_view_index) {
5538 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5539 if(!*tmp_out) {
5540 for(unsigned i = 0; i < 4; ++i)
5541 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5542 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5543 }
5544
5545 LLVMBuildStore(ctx->builder, to_float(&ctx->ac, ctx->view_index), *tmp_out);
5546 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5547 }
5548
5549 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5550 sizeof(outinfo->vs_output_param_offset));
5551
5552 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5553 LLVMValueRef slots[8];
5554 unsigned j;
5555
5556 if (outinfo->cull_dist_mask)
5557 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5558
5559 i = VARYING_SLOT_CLIP_DIST0;
5560 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5561 slots[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5562 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5563
5564 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5565 slots[i] = LLVMGetUndef(ctx->f32);
5566
5567 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5568 target = V_008DFC_SQ_EXP_POS + 3;
5569 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5570 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5571 &args, sizeof(args));
5572 }
5573
5574 target = V_008DFC_SQ_EXP_POS + 2;
5575 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5576 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5577 &args, sizeof(args));
5578
5579 }
5580
5581 LLVMValueRef pos_values[4] = {ctx->f32zero, ctx->f32zero, ctx->f32zero, ctx->f32one};
5582 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5583 for (unsigned j = 0; j < 4; j++)
5584 pos_values[j] = LLVMBuildLoad(ctx->builder,
5585 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5586 }
5587 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5588
5589 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5590 outinfo->writes_pointsize = true;
5591 psize_value = LLVMBuildLoad(ctx->builder,
5592 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5593 }
5594
5595 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5596 outinfo->writes_layer = true;
5597 layer_value = LLVMBuildLoad(ctx->builder,
5598 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5599 }
5600
5601 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5602 outinfo->writes_viewport_index = true;
5603 viewport_index_value = LLVMBuildLoad(ctx->builder,
5604 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5605 }
5606
5607 if (outinfo->writes_pointsize ||
5608 outinfo->writes_layer ||
5609 outinfo->writes_viewport_index) {
5610 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5611 (outinfo->writes_layer == true ? 4 : 0));
5612 pos_args[1].valid_mask = 0;
5613 pos_args[1].done = 0;
5614 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5615 pos_args[1].compr = 0;
5616 pos_args[1].out[0] = ctx->f32zero; /* X */
5617 pos_args[1].out[1] = ctx->f32zero; /* Y */
5618 pos_args[1].out[2] = ctx->f32zero; /* Z */
5619 pos_args[1].out[3] = ctx->f32zero; /* W */
5620
5621 if (outinfo->writes_pointsize == true)
5622 pos_args[1].out[0] = psize_value;
5623 if (outinfo->writes_layer == true)
5624 pos_args[1].out[2] = layer_value;
5625 if (outinfo->writes_viewport_index == true) {
5626 if (ctx->options->chip_class >= GFX9) {
5627 /* GFX9 has the layer in out.z[10:0] and the viewport
5628 * index in out.z[19:16].
5629 */
5630 LLVMValueRef v = viewport_index_value;
5631 v = to_integer(&ctx->ac, v);
5632 v = LLVMBuildShl(ctx->builder, v,
5633 LLVMConstInt(ctx->i32, 16, false),
5634 "");
5635 v = LLVMBuildOr(ctx->builder, v,
5636 to_integer(&ctx->ac, pos_args[1].out[2]), "");
5637
5638 pos_args[1].out[2] = to_float(&ctx->ac, v);
5639 pos_args[1].enabled_channels |= 1 << 2;
5640 } else {
5641 pos_args[1].out[3] = viewport_index_value;
5642 pos_args[1].enabled_channels |= 1 << 3;
5643 }
5644 }
5645 }
5646 for (i = 0; i < 4; i++) {
5647 if (pos_args[i].out[0])
5648 num_pos_exports++;
5649 }
5650
5651 pos_idx = 0;
5652 for (i = 0; i < 4; i++) {
5653 if (!pos_args[i].out[0])
5654 continue;
5655
5656 /* Specify the target we are exporting */
5657 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5658 if (pos_idx == num_pos_exports)
5659 pos_args[i].done = 1;
5660 ac_build_export(&ctx->ac, &pos_args[i]);
5661 }
5662
5663 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5664 LLVMValueRef values[4];
5665 if (!(ctx->output_mask & (1ull << i)))
5666 continue;
5667
5668 for (unsigned j = 0; j < 4; j++)
5669 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5670 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5671
5672 if (i == VARYING_SLOT_LAYER) {
5673 target = V_008DFC_SQ_EXP_PARAM + param_count;
5674 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5675 param_count++;
5676 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5677 target = V_008DFC_SQ_EXP_PARAM + param_count;
5678 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5679 param_count++;
5680 } else if (i >= VARYING_SLOT_VAR0) {
5681 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5682 target = V_008DFC_SQ_EXP_PARAM + param_count;
5683 outinfo->vs_output_param_offset[i] = param_count;
5684 param_count++;
5685 } else
5686 continue;
5687
5688 si_llvm_init_export_args(ctx, values, target, &args);
5689
5690 if (target >= V_008DFC_SQ_EXP_POS &&
5691 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5692 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5693 &args, sizeof(args));
5694 } else {
5695 ac_build_export(&ctx->ac, &args);
5696 }
5697 }
5698
5699 if (export_prim_id) {
5700 LLVMValueRef values[4];
5701 target = V_008DFC_SQ_EXP_PARAM + param_count;
5702 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5703 param_count++;
5704
5705 values[0] = ctx->vs_prim_id;
5706 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5707 ctx->shader_info->vs.vgpr_comp_cnt);
5708 for (unsigned j = 1; j < 4; j++)
5709 values[j] = ctx->f32zero;
5710 si_llvm_init_export_args(ctx, values, target, &args);
5711 ac_build_export(&ctx->ac, &args);
5712 outinfo->export_prim_id = true;
5713 }
5714
5715 outinfo->pos_exports = num_pos_exports;
5716 outinfo->param_exports = param_count;
5717 }
5718
5719 static void
5720 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5721 struct ac_es_output_info *outinfo)
5722 {
5723 int j;
5724 uint64_t max_output_written = 0;
5725 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5726 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5727 int param_index;
5728 int length = 4;
5729
5730 if (!(ctx->output_mask & (1ull << i)))
5731 continue;
5732
5733 if (i == VARYING_SLOT_CLIP_DIST0)
5734 length = ctx->num_output_clips + ctx->num_output_culls;
5735
5736 param_index = shader_io_get_unique_index(i);
5737
5738 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5739
5740 for (j = 0; j < length; j++) {
5741 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5742 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5743
5744 ac_build_buffer_store_dword(&ctx->ac,
5745 ctx->esgs_ring,
5746 out_val, 1,
5747 NULL, ctx->es2gs_offset,
5748 (4 * param_index + j) * 4,
5749 1, 1, true, true);
5750 }
5751 }
5752 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5753 }
5754
5755 static void
5756 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5757 {
5758 LLVMValueRef vertex_id = ctx->rel_auto_id;
5759 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5760 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5761 vertex_dw_stride, "");
5762
5763 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5764 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5765 int length = 4;
5766
5767 if (!(ctx->output_mask & (1ull << i)))
5768 continue;
5769
5770 if (i == VARYING_SLOT_CLIP_DIST0)
5771 length = ctx->num_output_clips + ctx->num_output_culls;
5772 int param = shader_io_get_unique_index(i);
5773 mark_tess_output(ctx, false, param);
5774 if (length > 4)
5775 mark_tess_output(ctx, false, param + 1);
5776 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5777 LLVMConstInt(ctx->i32, param * 4, false),
5778 "");
5779 for (unsigned j = 0; j < length; j++) {
5780 lds_store(ctx, dw_addr,
5781 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5782 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5783 }
5784 }
5785 }
5786
5787 struct ac_build_if_state
5788 {
5789 struct nir_to_llvm_context *ctx;
5790 LLVMValueRef condition;
5791 LLVMBasicBlockRef entry_block;
5792 LLVMBasicBlockRef true_block;
5793 LLVMBasicBlockRef false_block;
5794 LLVMBasicBlockRef merge_block;
5795 };
5796
5797 static LLVMBasicBlockRef
5798 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5799 {
5800 LLVMBasicBlockRef current_block;
5801 LLVMBasicBlockRef next_block;
5802 LLVMBasicBlockRef new_block;
5803
5804 /* get current basic block */
5805 current_block = LLVMGetInsertBlock(ctx->builder);
5806
5807 /* chqeck if there's another block after this one */
5808 next_block = LLVMGetNextBasicBlock(current_block);
5809 if (next_block) {
5810 /* insert the new block before the next block */
5811 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5812 }
5813 else {
5814 /* append new block after current block */
5815 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5816 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5817 }
5818 return new_block;
5819 }
5820
5821 static void
5822 ac_nir_build_if(struct ac_build_if_state *ifthen,
5823 struct nir_to_llvm_context *ctx,
5824 LLVMValueRef condition)
5825 {
5826 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5827
5828 memset(ifthen, 0, sizeof *ifthen);
5829 ifthen->ctx = ctx;
5830 ifthen->condition = condition;
5831 ifthen->entry_block = block;
5832
5833 /* create endif/merge basic block for the phi functions */
5834 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5835
5836 /* create/insert true_block before merge_block */
5837 ifthen->true_block =
5838 LLVMInsertBasicBlockInContext(ctx->context,
5839 ifthen->merge_block,
5840 "if-true-block");
5841
5842 /* successive code goes into the true block */
5843 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5844 }
5845
5846 /**
5847 * End a conditional.
5848 */
5849 static void
5850 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5851 {
5852 LLVMBuilderRef builder = ifthen->ctx->builder;
5853
5854 /* Insert branch to the merge block from current block */
5855 LLVMBuildBr(builder, ifthen->merge_block);
5856
5857 /*
5858 * Now patch in the various branch instructions.
5859 */
5860
5861 /* Insert the conditional branch instruction at the end of entry_block */
5862 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5863 if (ifthen->false_block) {
5864 /* we have an else clause */
5865 LLVMBuildCondBr(builder, ifthen->condition,
5866 ifthen->true_block, ifthen->false_block);
5867 }
5868 else {
5869 /* no else clause */
5870 LLVMBuildCondBr(builder, ifthen->condition,
5871 ifthen->true_block, ifthen->merge_block);
5872 }
5873
5874 /* Resume building code at end of the ifthen->merge_block */
5875 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5876 }
5877
5878 static void
5879 write_tess_factors(struct nir_to_llvm_context *ctx)
5880 {
5881 unsigned stride, outer_comps, inner_comps;
5882 struct ac_build_if_state if_ctx, inner_if_ctx;
5883 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
5884 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
5885 unsigned tess_inner_index, tess_outer_index;
5886 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5887 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5888 int i;
5889 emit_barrier(ctx);
5890
5891 switch (ctx->options->key.tcs.primitive_mode) {
5892 case GL_ISOLINES:
5893 stride = 2;
5894 outer_comps = 2;
5895 inner_comps = 0;
5896 break;
5897 case GL_TRIANGLES:
5898 stride = 4;
5899 outer_comps = 3;
5900 inner_comps = 1;
5901 break;
5902 case GL_QUADS:
5903 stride = 6;
5904 outer_comps = 4;
5905 inner_comps = 2;
5906 break;
5907 default:
5908 return;
5909 }
5910
5911 ac_nir_build_if(&if_ctx, ctx,
5912 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5913 invocation_id, ctx->i32zero, ""));
5914
5915 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5916 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5917
5918 mark_tess_output(ctx, true, tess_inner_index);
5919 mark_tess_output(ctx, true, tess_outer_index);
5920 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5921 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5922 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5923 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5924 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5925
5926 for (i = 0; i < 4; i++) {
5927 inner[i] = LLVMGetUndef(ctx->i32);
5928 outer[i] = LLVMGetUndef(ctx->i32);
5929 }
5930
5931 // LINES reverseal
5932 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5933 outer[0] = out[1] = lds_load(ctx, lds_outer);
5934 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5935 LLVMConstInt(ctx->i32, 1, false), "");
5936 outer[1] = out[0] = lds_load(ctx, lds_outer);
5937 } else {
5938 for (i = 0; i < outer_comps; i++) {
5939 outer[i] = out[i] =
5940 lds_load(ctx, lds_outer);
5941 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5942 LLVMConstInt(ctx->i32, 1, false), "");
5943 }
5944 for (i = 0; i < inner_comps; i++) {
5945 inner[i] = out[outer_comps+i] =
5946 lds_load(ctx, lds_inner);
5947 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5948 LLVMConstInt(ctx->i32, 1, false), "");
5949 }
5950 }
5951
5952 /* Convert the outputs to vectors for stores. */
5953 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5954 vec1 = NULL;
5955
5956 if (stride > 4)
5957 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5958
5959
5960 buffer = ctx->hs_ring_tess_factor;
5961 tf_base = ctx->tess_factor_offset;
5962 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5963 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5964
5965 ac_nir_build_if(&inner_if_ctx, ctx,
5966 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5967 rel_patch_id, ctx->i32zero, ""));
5968
5969 /* Store the dynamic HS control word. */
5970 ac_build_buffer_store_dword(&ctx->ac, buffer,
5971 LLVMConstInt(ctx->i32, 0x80000000, false),
5972 1, ctx->i32zero, tf_base,
5973 0, 1, 0, true, false);
5974 ac_nir_build_endif(&inner_if_ctx);
5975
5976 /* Store the tessellation factors. */
5977 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5978 MIN2(stride, 4), byteoffset, tf_base,
5979 4, 1, 0, true, false);
5980 if (vec1)
5981 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5982 stride - 4, byteoffset, tf_base,
5983 20, 1, 0, true, false);
5984
5985 //TODO store to offchip for TES to read - only if TES reads them
5986 if (1) {
5987 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5988 LLVMValueRef tf_inner_offset;
5989 unsigned param_outer, param_inner;
5990
5991 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5992 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5993 LLVMConstInt(ctx->i32, param_outer, 0));
5994
5995 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5996 util_next_power_of_two(outer_comps));
5997
5998 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5999 outer_comps, tf_outer_offset,
6000 ctx->oc_lds, 0, 1, 0, true, false);
6001 if (inner_comps) {
6002 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6003 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6004 LLVMConstInt(ctx->i32, param_inner, 0));
6005
6006 inner_vec = inner_comps == 1 ? inner[0] :
6007 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6008 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6009 inner_comps, tf_inner_offset,
6010 ctx->oc_lds, 0, 1, 0, true, false);
6011 }
6012 }
6013 ac_nir_build_endif(&if_ctx);
6014 }
6015
6016 static void
6017 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6018 {
6019 write_tess_factors(ctx);
6020 }
6021
6022 static bool
6023 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6024 LLVMValueRef *color, unsigned param, bool is_last,
6025 struct ac_export_args *args)
6026 {
6027 /* Export */
6028 si_llvm_init_export_args(ctx, color, param,
6029 args);
6030
6031 if (is_last) {
6032 args->valid_mask = 1; /* whether the EXEC mask is valid */
6033 args->done = 1; /* DONE bit */
6034 } else if (!args->enabled_channels)
6035 return false; /* unnecessary NULL export */
6036
6037 return true;
6038 }
6039
6040 static void
6041 si_export_mrt_z(struct nir_to_llvm_context *ctx,
6042 LLVMValueRef depth, LLVMValueRef stencil,
6043 LLVMValueRef samplemask)
6044 {
6045 struct ac_export_args args;
6046
6047 args.enabled_channels = 0;
6048 args.valid_mask = 1;
6049 args.done = 1;
6050 args.target = V_008DFC_SQ_EXP_MRTZ;
6051 args.compr = false;
6052
6053 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
6054 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
6055 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
6056 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
6057
6058 if (depth) {
6059 args.out[0] = depth;
6060 args.enabled_channels |= 0x1;
6061 }
6062
6063 if (stencil) {
6064 args.out[1] = stencil;
6065 args.enabled_channels |= 0x2;
6066 }
6067
6068 if (samplemask) {
6069 args.out[2] = samplemask;
6070 args.enabled_channels |= 0x4;
6071 }
6072
6073 /* SI (except OLAND and HAINAN) has a bug that it only looks
6074 * at the X writemask component. */
6075 if (ctx->options->chip_class == SI &&
6076 ctx->options->family != CHIP_OLAND &&
6077 ctx->options->family != CHIP_HAINAN)
6078 args.enabled_channels |= 0x1;
6079
6080 ac_build_export(&ctx->ac, &args);
6081 }
6082
6083 static void
6084 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6085 {
6086 unsigned index = 0;
6087 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6088 struct ac_export_args color_args[8];
6089
6090 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6091 LLVMValueRef values[4];
6092
6093 if (!(ctx->output_mask & (1ull << i)))
6094 continue;
6095
6096 if (i == FRAG_RESULT_DEPTH) {
6097 ctx->shader_info->fs.writes_z = true;
6098 depth = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6099 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6100 } else if (i == FRAG_RESULT_STENCIL) {
6101 ctx->shader_info->fs.writes_stencil = true;
6102 stencil = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6103 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6104 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6105 ctx->shader_info->fs.writes_sample_mask = true;
6106 samplemask = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6107 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6108 } else {
6109 bool last = false;
6110 for (unsigned j = 0; j < 4; j++)
6111 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6112 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6113
6114 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6115 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6116
6117 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6118 if (ret)
6119 index++;
6120 }
6121 }
6122
6123 for (unsigned i = 0; i < index; i++)
6124 ac_build_export(&ctx->ac, &color_args[i]);
6125 if (depth || stencil || samplemask)
6126 si_export_mrt_z(ctx, depth, stencil, samplemask);
6127 else if (!index) {
6128 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6129 ac_build_export(&ctx->ac, &color_args[0]);
6130 }
6131
6132 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6133 }
6134
6135 static void
6136 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6137 {
6138 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6139 }
6140
6141 static void
6142 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6143 LLVMValueRef *addrs)
6144 {
6145 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6146
6147 switch (ctx->stage) {
6148 case MESA_SHADER_VERTEX:
6149 if (ctx->options->key.vs.as_ls)
6150 handle_ls_outputs_post(ctx);
6151 else if (ctx->options->key.vs.as_es)
6152 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6153 else
6154 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6155 &ctx->shader_info->vs.outinfo);
6156 break;
6157 case MESA_SHADER_FRAGMENT:
6158 handle_fs_outputs_post(ctx);
6159 break;
6160 case MESA_SHADER_GEOMETRY:
6161 emit_gs_epilogue(ctx);
6162 break;
6163 case MESA_SHADER_TESS_CTRL:
6164 handle_tcs_outputs_post(ctx);
6165 break;
6166 case MESA_SHADER_TESS_EVAL:
6167 if (ctx->options->key.tes.as_es)
6168 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6169 else
6170 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6171 &ctx->shader_info->tes.outinfo);
6172 break;
6173 default:
6174 break;
6175 }
6176 }
6177
6178 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6179 {
6180 LLVMPassManagerRef passmgr;
6181 /* Create the pass manager */
6182 passmgr = LLVMCreateFunctionPassManagerForModule(
6183 ctx->module);
6184
6185 /* This pass should eliminate all the load and store instructions */
6186 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6187
6188 /* Add some optimization passes */
6189 LLVMAddScalarReplAggregatesPass(passmgr);
6190 LLVMAddLICMPass(passmgr);
6191 LLVMAddAggressiveDCEPass(passmgr);
6192 LLVMAddCFGSimplificationPass(passmgr);
6193 LLVMAddInstructionCombiningPass(passmgr);
6194
6195 /* Run the pass */
6196 LLVMInitializeFunctionPassManager(passmgr);
6197 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6198 LLVMFinalizeFunctionPassManager(passmgr);
6199
6200 LLVMDisposeBuilder(ctx->builder);
6201 LLVMDisposePassManager(passmgr);
6202 }
6203
6204 static void
6205 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6206 {
6207 struct ac_vs_output_info *outinfo;
6208
6209 switch (ctx->stage) {
6210 case MESA_SHADER_FRAGMENT:
6211 case MESA_SHADER_COMPUTE:
6212 case MESA_SHADER_TESS_CTRL:
6213 case MESA_SHADER_GEOMETRY:
6214 return;
6215 case MESA_SHADER_VERTEX:
6216 if (ctx->options->key.vs.as_ls ||
6217 ctx->options->key.vs.as_es)
6218 return;
6219 outinfo = &ctx->shader_info->vs.outinfo;
6220 break;
6221 case MESA_SHADER_TESS_EVAL:
6222 if (ctx->options->key.vs.as_es)
6223 return;
6224 outinfo = &ctx->shader_info->tes.outinfo;
6225 break;
6226 default:
6227 unreachable("Unhandled shader type");
6228 }
6229
6230 ac_optimize_vs_outputs(&ctx->ac,
6231 ctx->main_function,
6232 outinfo->vs_output_param_offset,
6233 VARYING_SLOT_MAX,
6234 &outinfo->param_exports);
6235 }
6236
6237 static void
6238 ac_setup_rings(struct nir_to_llvm_context *ctx)
6239 {
6240 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6241 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6242 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
6243 }
6244
6245 if (ctx->is_gs_copy_shader) {
6246 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
6247 }
6248 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6249 LLVMValueRef tmp;
6250 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
6251 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
6252
6253 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6254
6255 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
6256 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
6257 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6258 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
6259 }
6260
6261 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6262 ctx->stage == MESA_SHADER_TESS_EVAL) {
6263 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6264 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6265 }
6266 }
6267
6268 static unsigned
6269 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6270 const struct nir_shader *nir)
6271 {
6272 switch (nir->stage) {
6273 case MESA_SHADER_TESS_CTRL:
6274 return chip_class >= CIK ? 128 : 64;
6275 case MESA_SHADER_GEOMETRY:
6276 return 64;
6277 case MESA_SHADER_COMPUTE:
6278 break;
6279 default:
6280 return 0;
6281 }
6282
6283 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6284 nir->info.cs.local_size[1] *
6285 nir->info.cs.local_size[2];
6286 return max_workgroup_size;
6287 }
6288
6289 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6290 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6291 {
6292 struct ac_nir_context ctx = {};
6293 struct nir_function *func;
6294
6295 ctx.ac = *ac;
6296 ctx.abi = abi;
6297
6298 ctx.nctx = nctx;
6299 if (nctx)
6300 nctx->nir = &ctx;
6301
6302 ctx.stage = nir->stage;
6303
6304 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6305
6306 nir_foreach_variable(variable, &nir->outputs)
6307 handle_shader_output_decl(&ctx, nir, variable);
6308
6309 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6310 _mesa_key_pointer_equal);
6311 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6312 _mesa_key_pointer_equal);
6313 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6314 _mesa_key_pointer_equal);
6315
6316 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6317
6318 setup_locals(&ctx, func);
6319
6320 if (nir->stage == MESA_SHADER_COMPUTE)
6321 setup_shared(&ctx, nir);
6322
6323 visit_cf_list(&ctx, &func->impl->body);
6324 phi_post_pass(&ctx);
6325
6326 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6327 ctx.outputs);
6328
6329 free(ctx.locals);
6330 ralloc_free(ctx.defs);
6331 ralloc_free(ctx.phis);
6332 ralloc_free(ctx.vars);
6333
6334 if (nctx)
6335 nctx->nir = NULL;
6336 }
6337
6338 static
6339 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6340 struct nir_shader *nir,
6341 struct ac_shader_variant_info *shader_info,
6342 const struct ac_nir_compiler_options *options)
6343 {
6344 struct nir_to_llvm_context ctx = {0};
6345 unsigned i;
6346 ctx.options = options;
6347 ctx.shader_info = shader_info;
6348 ctx.context = LLVMContextCreate();
6349 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6350
6351 ac_llvm_context_init(&ctx.ac, ctx.context);
6352 ctx.ac.module = ctx.module;
6353
6354 memset(shader_info, 0, sizeof(*shader_info));
6355
6356 ac_nir_shader_info_pass(nir, options, &shader_info->info);
6357
6358 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6359
6360 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6361 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6362 LLVMSetDataLayout(ctx.module, data_layout_str);
6363 LLVMDisposeTargetData(data_layout);
6364 LLVMDisposeMessage(data_layout_str);
6365
6366 setup_types(&ctx);
6367
6368 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6369 ctx.ac.builder = ctx.builder;
6370 ctx.stage = nir->stage;
6371 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
6372
6373 for (i = 0; i < AC_UD_MAX_SETS; i++)
6374 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6375 for (i = 0; i < AC_UD_MAX_UD; i++)
6376 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6377
6378 create_function(&ctx);
6379
6380 if (nir->stage == MESA_SHADER_GEOMETRY) {
6381 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.i32, "gs_next_vertex");
6382
6383 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
6384 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
6385 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
6386 } else if (nir->stage == MESA_SHADER_VERTEX) {
6387 if (shader_info->info.vs.needs_instance_id) {
6388 ctx.shader_info->vs.vgpr_comp_cnt =
6389 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6390 }
6391 } else if (nir->stage == MESA_SHADER_FRAGMENT) {
6392 shader_info->fs.can_discard = nir->info.fs.uses_discard;
6393 }
6394
6395 ac_setup_rings(&ctx);
6396
6397 ctx.num_output_clips = nir->info.clip_distance_array_size;
6398 ctx.num_output_culls = nir->info.cull_distance_array_size;
6399
6400 if (nir->stage == MESA_SHADER_FRAGMENT)
6401 handle_fs_inputs(&ctx, nir);
6402 else if(nir->stage == MESA_SHADER_VERTEX)
6403 handle_vs_inputs(&ctx, nir);
6404
6405 ctx.abi.chip_class = options->chip_class;
6406 ctx.abi.inputs = &ctx.inputs[0];
6407 ctx.abi.emit_outputs = handle_shader_outputs_post;
6408 ctx.abi.load_ssbo = radv_load_ssbo;
6409 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6410
6411 nir_foreach_variable(variable, &nir->outputs)
6412 scan_shader_output_decl(&ctx, variable);
6413
6414 ac_nir_translate(&ctx.ac, &ctx.abi, nir, &ctx);
6415
6416 LLVMBuildRetVoid(ctx.builder);
6417
6418 ac_llvm_finalize_module(&ctx);
6419
6420 ac_nir_eliminate_const_vs_outputs(&ctx);
6421
6422 if (nir->stage == MESA_SHADER_GEOMETRY) {
6423 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
6424 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6425 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6426 nir->info.gs.vertices_out;
6427 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
6428 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6429 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6430 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6431 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6432 }
6433
6434 return ctx.module;
6435 }
6436
6437 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6438 {
6439 unsigned *retval = (unsigned *)context;
6440 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6441 char *description = LLVMGetDiagInfoDescription(di);
6442
6443 if (severity == LLVMDSError) {
6444 *retval = 1;
6445 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6446 description);
6447 }
6448
6449 LLVMDisposeMessage(description);
6450 }
6451
6452 static unsigned ac_llvm_compile(LLVMModuleRef M,
6453 struct ac_shader_binary *binary,
6454 LLVMTargetMachineRef tm)
6455 {
6456 unsigned retval = 0;
6457 char *err;
6458 LLVMContextRef llvm_ctx;
6459 LLVMMemoryBufferRef out_buffer;
6460 unsigned buffer_size;
6461 const char *buffer_data;
6462 LLVMBool mem_err;
6463
6464 /* Setup Diagnostic Handler*/
6465 llvm_ctx = LLVMGetModuleContext(M);
6466
6467 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6468 &retval);
6469
6470 /* Compile IR*/
6471 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6472 &err, &out_buffer);
6473
6474 /* Process Errors/Warnings */
6475 if (mem_err) {
6476 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6477 free(err);
6478 retval = 1;
6479 goto out;
6480 }
6481
6482 /* Extract Shader Code*/
6483 buffer_size = LLVMGetBufferSize(out_buffer);
6484 buffer_data = LLVMGetBufferStart(out_buffer);
6485
6486 ac_elf_read(buffer_data, buffer_size, binary);
6487
6488 /* Clean up */
6489 LLVMDisposeMemoryBuffer(out_buffer);
6490
6491 out:
6492 return retval;
6493 }
6494
6495 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6496 LLVMModuleRef llvm_module,
6497 struct ac_shader_binary *binary,
6498 struct ac_shader_config *config,
6499 struct ac_shader_variant_info *shader_info,
6500 gl_shader_stage stage,
6501 bool dump_shader, bool supports_spill)
6502 {
6503 if (dump_shader)
6504 ac_dump_module(llvm_module);
6505
6506 memset(binary, 0, sizeof(*binary));
6507 int v = ac_llvm_compile(llvm_module, binary, tm);
6508 if (v) {
6509 fprintf(stderr, "compile failed\n");
6510 }
6511
6512 if (dump_shader)
6513 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6514
6515 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6516
6517 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6518 LLVMDisposeModule(llvm_module);
6519 LLVMContextDispose(ctx);
6520
6521 if (stage == MESA_SHADER_FRAGMENT) {
6522 shader_info->num_input_vgprs = 0;
6523 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6524 shader_info->num_input_vgprs += 2;
6525 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6526 shader_info->num_input_vgprs += 2;
6527 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6528 shader_info->num_input_vgprs += 2;
6529 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6530 shader_info->num_input_vgprs += 3;
6531 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6532 shader_info->num_input_vgprs += 2;
6533 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6534 shader_info->num_input_vgprs += 2;
6535 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6536 shader_info->num_input_vgprs += 2;
6537 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6538 shader_info->num_input_vgprs += 1;
6539 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6540 shader_info->num_input_vgprs += 1;
6541 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6542 shader_info->num_input_vgprs += 1;
6543 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6544 shader_info->num_input_vgprs += 1;
6545 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6546 shader_info->num_input_vgprs += 1;
6547 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6548 shader_info->num_input_vgprs += 1;
6549 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6550 shader_info->num_input_vgprs += 1;
6551 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6552 shader_info->num_input_vgprs += 1;
6553 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6554 shader_info->num_input_vgprs += 1;
6555 }
6556 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6557
6558 /* +3 for scratch wave offset and VCC */
6559 config->num_sgprs = MAX2(config->num_sgprs,
6560 shader_info->num_input_sgprs + 3);
6561 }
6562
6563 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6564 struct ac_shader_binary *binary,
6565 struct ac_shader_config *config,
6566 struct ac_shader_variant_info *shader_info,
6567 struct nir_shader *nir,
6568 const struct ac_nir_compiler_options *options,
6569 bool dump_shader)
6570 {
6571
6572 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6573 options);
6574
6575 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6576 switch (nir->stage) {
6577 case MESA_SHADER_COMPUTE:
6578 for (int i = 0; i < 3; ++i)
6579 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6580 break;
6581 case MESA_SHADER_FRAGMENT:
6582 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6583 break;
6584 case MESA_SHADER_GEOMETRY:
6585 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6586 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6587 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6588 shader_info->gs.invocations = nir->info.gs.invocations;
6589 break;
6590 case MESA_SHADER_TESS_EVAL:
6591 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6592 shader_info->tes.spacing = nir->info.tess.spacing;
6593 shader_info->tes.ccw = nir->info.tess.ccw;
6594 shader_info->tes.point_mode = nir->info.tess.point_mode;
6595 shader_info->tes.as_es = options->key.tes.as_es;
6596 break;
6597 case MESA_SHADER_TESS_CTRL:
6598 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6599 break;
6600 case MESA_SHADER_VERTEX:
6601 shader_info->vs.as_es = options->key.vs.as_es;
6602 shader_info->vs.as_ls = options->key.vs.as_ls;
6603 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6604 if (options->key.vs.as_ls)
6605 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6606 break;
6607 default:
6608 break;
6609 }
6610 }
6611
6612 static void
6613 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6614 {
6615 LLVMValueRef args[9];
6616 args[0] = ctx->gsvs_ring;
6617 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6618 args[3] = ctx->i32zero;
6619 args[4] = ctx->i32one; /* OFFEN */
6620 args[5] = ctx->i32zero; /* IDXEN */
6621 args[6] = ctx->i32one; /* GLC */
6622 args[7] = ctx->i32one; /* SLC */
6623 args[8] = ctx->i32zero; /* TFE */
6624
6625 int idx = 0;
6626
6627 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6628 int length = 4;
6629 int slot = idx;
6630 int slot_inc = 1;
6631 if (!(ctx->output_mask & (1ull << i)))
6632 continue;
6633
6634 if (i == VARYING_SLOT_CLIP_DIST0) {
6635 /* unpack clip and cull from a single set of slots */
6636 length = ctx->num_output_clips + ctx->num_output_culls;
6637 if (length > 4)
6638 slot_inc = 2;
6639 }
6640
6641 for (unsigned j = 0; j < length; j++) {
6642 LLVMValueRef value;
6643 args[2] = LLVMConstInt(ctx->i32,
6644 (slot * 4 + j) *
6645 ctx->gs_max_out_vertices * 16 * 4, false);
6646
6647 value = ac_build_intrinsic(&ctx->ac,
6648 "llvm.SI.buffer.load.dword.i32.i32",
6649 ctx->i32, args, 9,
6650 AC_FUNC_ATTR_READONLY |
6651 AC_FUNC_ATTR_LEGACY);
6652
6653 LLVMBuildStore(ctx->builder,
6654 to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6655 }
6656 idx += slot_inc;
6657 }
6658 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6659 }
6660
6661 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6662 struct nir_shader *geom_shader,
6663 struct ac_shader_binary *binary,
6664 struct ac_shader_config *config,
6665 struct ac_shader_variant_info *shader_info,
6666 const struct ac_nir_compiler_options *options,
6667 bool dump_shader)
6668 {
6669 struct nir_to_llvm_context ctx = {0};
6670 ctx.context = LLVMContextCreate();
6671 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6672 ctx.options = options;
6673 ctx.shader_info = shader_info;
6674
6675 ac_llvm_context_init(&ctx.ac, ctx.context);
6676 ctx.ac.module = ctx.module;
6677
6678 ctx.is_gs_copy_shader = true;
6679 LLVMSetTarget(ctx.module, "amdgcn--");
6680 setup_types(&ctx);
6681
6682 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6683 ctx.ac.builder = ctx.builder;
6684 ctx.stage = MESA_SHADER_VERTEX;
6685
6686 create_function(&ctx);
6687
6688 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6689 ac_setup_rings(&ctx);
6690
6691 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6692 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6693
6694 struct ac_nir_context nir_ctx = {};
6695 nir_ctx.ac = ctx.ac;
6696 nir_ctx.abi = &ctx.abi;
6697
6698 nir_ctx.nctx = &ctx;
6699 ctx.nir = &nir_ctx;
6700
6701 nir_foreach_variable(variable, &geom_shader->outputs) {
6702 scan_shader_output_decl(&ctx, variable);
6703 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6704 }
6705
6706 ac_gs_copy_shader_emit(&ctx);
6707
6708 ctx.nir = NULL;
6709
6710 LLVMBuildRetVoid(ctx.builder);
6711
6712 ac_llvm_finalize_module(&ctx);
6713
6714 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6715 MESA_SHADER_VERTEX,
6716 dump_shader, options->supports_spill);
6717 }