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ac: add basic nir -> llvm type helper
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 RADEON_LLVM_AMDGPU_HS = 93,
43 };
44
45 #define CONST_ADDR_SPACE 2
46 #define LOCAL_ADDR_SPACE 3
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
50
51 struct nir_to_llvm_context;
52
53 struct ac_nir_context {
54 struct ac_llvm_context ac;
55 struct ac_shader_abi *abi;
56
57 gl_shader_stage stage;
58
59 struct hash_table *defs;
60 struct hash_table *phis;
61 struct hash_table *vars;
62
63 LLVMValueRef main_function;
64 LLVMBasicBlockRef continue_block;
65 LLVMBasicBlockRef break_block;
66
67 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
68
69 int num_locals;
70 LLVMValueRef *locals;
71
72 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
73 };
74
75 struct nir_to_llvm_context {
76 struct ac_llvm_context ac;
77 const struct ac_nir_compiler_options *options;
78 struct ac_shader_variant_info *shader_info;
79 struct ac_shader_abi abi;
80 struct ac_nir_context *nir;
81
82 unsigned max_workgroup_size;
83 LLVMContextRef context;
84 LLVMModuleRef module;
85 LLVMBuilderRef builder;
86 LLVMValueRef main_function;
87
88 struct hash_table *defs;
89 struct hash_table *phis;
90
91 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
92 LLVMValueRef ring_offsets;
93 LLVMValueRef push_constants;
94 LLVMValueRef view_index;
95 LLVMValueRef num_work_groups;
96 LLVMValueRef workgroup_ids;
97 LLVMValueRef local_invocation_ids;
98 LLVMValueRef tg_size;
99
100 LLVMValueRef vertex_buffers;
101 LLVMValueRef rel_auto_id;
102 LLVMValueRef vs_prim_id;
103 LLVMValueRef ls_out_layout;
104 LLVMValueRef es2gs_offset;
105
106 LLVMValueRef tcs_offchip_layout;
107 LLVMValueRef tcs_out_offsets;
108 LLVMValueRef tcs_out_layout;
109 LLVMValueRef tcs_in_layout;
110 LLVMValueRef oc_lds;
111 LLVMValueRef merged_wave_info;
112 LLVMValueRef tess_factor_offset;
113 LLVMValueRef tcs_patch_id;
114 LLVMValueRef tcs_rel_ids;
115 LLVMValueRef tes_rel_patch_id;
116 LLVMValueRef tes_patch_id;
117 LLVMValueRef tes_u;
118 LLVMValueRef tes_v;
119
120 LLVMValueRef gsvs_ring_stride;
121 LLVMValueRef gsvs_num_entries;
122 LLVMValueRef gs2vs_offset;
123 LLVMValueRef gs_wave_id;
124 LLVMValueRef gs_vtx_offset[6];
125
126 LLVMValueRef esgs_ring;
127 LLVMValueRef gsvs_ring;
128 LLVMValueRef hs_ring_tess_offchip;
129 LLVMValueRef hs_ring_tess_factor;
130
131 LLVMValueRef prim_mask;
132 LLVMValueRef sample_pos_offset;
133 LLVMValueRef persp_sample, persp_center, persp_centroid;
134 LLVMValueRef linear_sample, linear_center, linear_centroid;
135
136 gl_shader_stage stage;
137
138 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
139
140 uint64_t input_mask;
141 uint64_t output_mask;
142 uint8_t num_output_clips;
143 uint8_t num_output_culls;
144
145 bool is_gs_copy_shader;
146 LLVMValueRef gs_next_vertex;
147 unsigned gs_max_out_vertices;
148
149 unsigned tes_primitive_mode;
150 uint64_t tess_outputs_written;
151 uint64_t tess_patch_outputs_written;
152
153 uint32_t tcs_patch_outputs_read;
154 uint64_t tcs_outputs_read;
155 };
156
157 static inline struct nir_to_llvm_context *
158 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
159 {
160 struct nir_to_llvm_context *ctx = NULL;
161 return container_of(abi, ctx, abi);
162 }
163
164 static LLVMTypeRef
165 nir2llvmtype(struct ac_nir_context *ctx,
166 const struct glsl_type *type)
167 {
168 switch (glsl_get_base_type(glsl_without_array(type))) {
169 case GLSL_TYPE_UINT:
170 case GLSL_TYPE_INT:
171 return ctx->ac.i32;
172 case GLSL_TYPE_UINT64:
173 case GLSL_TYPE_INT64:
174 return ctx->ac.i64;
175 case GLSL_TYPE_DOUBLE:
176 return ctx->ac.f64;
177 case GLSL_TYPE_FLOAT:
178 return ctx->ac.f32;
179 default:
180 assert(!"Unsupported type in nir2llvmtype()");
181 break;
182 }
183 return 0;
184 }
185
186 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
187 const nir_deref_var *deref,
188 enum ac_descriptor_type desc_type,
189 const nir_tex_instr *instr,
190 bool image, bool write);
191
192 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
193 {
194 return (index * 4) + chan;
195 }
196
197 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
198 {
199 /* handle patch indices separate */
200 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
201 return 0;
202 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
203 return 1;
204 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
205 return 2 + (slot - VARYING_SLOT_PATCH0);
206
207 if (slot == VARYING_SLOT_POS)
208 return 0;
209 if (slot == VARYING_SLOT_PSIZ)
210 return 1;
211 if (slot == VARYING_SLOT_CLIP_DIST0)
212 return 2;
213 /* 3 is reserved for clip dist as well */
214 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
215 return 4 + (slot - VARYING_SLOT_VAR0);
216 unreachable("illegal slot in get unique index\n");
217 }
218
219 static void set_llvm_calling_convention(LLVMValueRef func,
220 gl_shader_stage stage)
221 {
222 enum radeon_llvm_calling_convention calling_conv;
223
224 switch (stage) {
225 case MESA_SHADER_VERTEX:
226 case MESA_SHADER_TESS_EVAL:
227 calling_conv = RADEON_LLVM_AMDGPU_VS;
228 break;
229 case MESA_SHADER_GEOMETRY:
230 calling_conv = RADEON_LLVM_AMDGPU_GS;
231 break;
232 case MESA_SHADER_TESS_CTRL:
233 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
234 break;
235 case MESA_SHADER_FRAGMENT:
236 calling_conv = RADEON_LLVM_AMDGPU_PS;
237 break;
238 case MESA_SHADER_COMPUTE:
239 calling_conv = RADEON_LLVM_AMDGPU_CS;
240 break;
241 default:
242 unreachable("Unhandle shader type");
243 }
244
245 LLVMSetFunctionCallConv(func, calling_conv);
246 }
247
248 #define MAX_ARGS 23
249 struct arg_info {
250 LLVMTypeRef types[MAX_ARGS];
251 LLVMValueRef *assign[MAX_ARGS];
252 unsigned array_params_mask;
253 uint8_t count;
254 uint8_t user_sgpr_count;
255 uint8_t sgpr_count;
256 uint8_t num_user_sgprs_used;
257 uint8_t num_sgprs_used;
258 uint8_t num_vgprs_used;
259 };
260
261 static inline void
262 add_argument(struct arg_info *info,
263 LLVMTypeRef type, LLVMValueRef *param_ptr)
264 {
265 assert(info->count < MAX_ARGS);
266 info->assign[info->count] = param_ptr;
267 info->types[info->count] = type;
268 info->count++;
269 }
270
271 static inline void
272 add_sgpr_argument(struct arg_info *info,
273 LLVMTypeRef type, LLVMValueRef *param_ptr)
274 {
275 add_argument(info, type, param_ptr);
276 info->num_sgprs_used += ac_get_type_size(type) / 4;
277 info->sgpr_count++;
278 }
279
280 static inline void
281 add_user_sgpr_argument(struct arg_info *info,
282 LLVMTypeRef type,
283 LLVMValueRef *param_ptr)
284 {
285 add_sgpr_argument(info, type, param_ptr);
286 info->num_user_sgprs_used += ac_get_type_size(type) / 4;
287 info->user_sgpr_count++;
288 }
289
290 static inline void
291 add_vgpr_argument(struct arg_info *info,
292 LLVMTypeRef type,
293 LLVMValueRef *param_ptr)
294 {
295 add_argument(info, type, param_ptr);
296 info->num_vgprs_used += ac_get_type_size(type) / 4;
297 }
298
299 static inline void
300 add_user_sgpr_array_argument(struct arg_info *info,
301 LLVMTypeRef type,
302 LLVMValueRef *param_ptr)
303 {
304 info->array_params_mask |= (1 << info->count);
305 add_user_sgpr_argument(info, type, param_ptr);
306 }
307
308 static void assign_arguments(LLVMValueRef main_function,
309 struct arg_info *info)
310 {
311 unsigned i;
312 for (i = 0; i < info->count; i++) {
313 if (info->assign[i])
314 *info->assign[i] = LLVMGetParam(main_function, i);
315 }
316 }
317
318 static LLVMValueRef
319 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
320 LLVMBuilderRef builder, LLVMTypeRef *return_types,
321 unsigned num_return_elems,
322 struct arg_info *args,
323 unsigned max_workgroup_size,
324 bool unsafe_math)
325 {
326 LLVMTypeRef main_function_type, ret_type;
327 LLVMBasicBlockRef main_function_body;
328
329 if (num_return_elems)
330 ret_type = LLVMStructTypeInContext(ctx, return_types,
331 num_return_elems, true);
332 else
333 ret_type = LLVMVoidTypeInContext(ctx);
334
335 /* Setup the function */
336 main_function_type =
337 LLVMFunctionType(ret_type, args->types, args->count, 0);
338 LLVMValueRef main_function =
339 LLVMAddFunction(module, "main", main_function_type);
340 main_function_body =
341 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
342 LLVMPositionBuilderAtEnd(builder, main_function_body);
343
344 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
345 for (unsigned i = 0; i < args->sgpr_count; ++i) {
346 if (args->array_params_mask & (1 << i)) {
347 LLVMValueRef P = LLVMGetParam(main_function, i);
348 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
349 ac_add_attr_dereferenceable(P, UINT64_MAX);
350 }
351 else {
352 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
353 }
354 }
355
356 if (max_workgroup_size) {
357 ac_llvm_add_target_dep_function_attr(main_function,
358 "amdgpu-max-work-group-size",
359 max_workgroup_size);
360 }
361 if (unsafe_math) {
362 /* These were copied from some LLVM test. */
363 LLVMAddTargetDependentFunctionAttr(main_function,
364 "less-precise-fpmad",
365 "true");
366 LLVMAddTargetDependentFunctionAttr(main_function,
367 "no-infs-fp-math",
368 "true");
369 LLVMAddTargetDependentFunctionAttr(main_function,
370 "no-nans-fp-math",
371 "true");
372 LLVMAddTargetDependentFunctionAttr(main_function,
373 "unsafe-fp-math",
374 "true");
375 }
376 return main_function;
377 }
378
379 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
380 {
381 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
382 CONST_ADDR_SPACE);
383 }
384
385 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
386 {
387 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
388 type = LLVMGetElementType(type);
389
390 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
391 return LLVMGetIntTypeWidth(type);
392
393 if (type == ctx->f16)
394 return 16;
395 if (type == ctx->f32)
396 return 32;
397 if (type == ctx->f64)
398 return 64;
399
400 unreachable("Unhandled type kind in get_elem_bits");
401 }
402
403 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
404 LLVMValueRef param, unsigned rshift,
405 unsigned bitwidth)
406 {
407 LLVMValueRef value = param;
408 if (rshift)
409 value = LLVMBuildLShr(ctx->builder, value,
410 LLVMConstInt(ctx->i32, rshift, false), "");
411
412 if (rshift + bitwidth < 32) {
413 unsigned mask = (1 << bitwidth) - 1;
414 value = LLVMBuildAnd(ctx->builder, value,
415 LLVMConstInt(ctx->i32, mask, false), "");
416 }
417 return value;
418 }
419
420 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
421 {
422 switch (ctx->stage) {
423 case MESA_SHADER_TESS_CTRL:
424 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
425 case MESA_SHADER_TESS_EVAL:
426 return ctx->tes_rel_patch_id;
427 break;
428 default:
429 unreachable("Illegal stage");
430 }
431 }
432
433 /* Tessellation shaders pass outputs to the next shader using LDS.
434 *
435 * LS outputs = TCS inputs
436 * TCS outputs = TES inputs
437 *
438 * The LDS layout is:
439 * - TCS inputs for patch 0
440 * - TCS inputs for patch 1
441 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
442 * - ...
443 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
444 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
445 * - TCS outputs for patch 1
446 * - Per-patch TCS outputs for patch 1
447 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
448 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
449 * - ...
450 *
451 * All three shaders VS(LS), TCS, TES share the same LDS space.
452 */
453 static LLVMValueRef
454 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
455 {
456 if (ctx->stage == MESA_SHADER_VERTEX)
457 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
458 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
459 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
460 else {
461 assert(0);
462 return NULL;
463 }
464 }
465
466 static LLVMValueRef
467 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
468 {
469 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
470 }
471
472 static LLVMValueRef
473 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
474 {
475 return LLVMBuildMul(ctx->builder,
476 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
477 LLVMConstInt(ctx->ac.i32, 4, false), "");
478 }
479
480 static LLVMValueRef
481 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
482 {
483 return LLVMBuildMul(ctx->builder,
484 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
485 LLVMConstInt(ctx->ac.i32, 4, false), "");
486 }
487
488 static LLVMValueRef
489 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
490 {
491 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
492 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
493
494 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
495 }
496
497 static LLVMValueRef
498 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
499 {
500 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
501 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
502 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
503
504 return LLVMBuildAdd(ctx->builder, patch0_offset,
505 LLVMBuildMul(ctx->builder, patch_stride,
506 rel_patch_id, ""),
507 "");
508 }
509
510 static LLVMValueRef
511 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
512 {
513 LLVMValueRef patch0_patch_data_offset =
514 get_tcs_out_patch0_patch_data_offset(ctx);
515 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
516 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
517
518 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
519 LLVMBuildMul(ctx->builder, patch_stride,
520 rel_patch_id, ""),
521 "");
522 }
523
524 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
525 {
526 ud_info->sgpr_idx = *sgpr_idx;
527 ud_info->num_sgprs = num_sgprs;
528 ud_info->indirect = false;
529 ud_info->indirect_offset = 0;
530 *sgpr_idx += num_sgprs;
531 }
532
533 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
534 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
535 {
536 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
537 }
538
539
540 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
541 uint32_t indirect_offset)
542 {
543 ud_info->sgpr_idx = sgpr_idx;
544 ud_info->num_sgprs = num_sgprs;
545 ud_info->indirect = true;
546 ud_info->indirect_offset = indirect_offset;
547 }
548
549 struct user_sgpr_info {
550 bool need_ring_offsets;
551 uint8_t sgpr_count;
552 bool indirect_all_descriptor_sets;
553 };
554
555 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
556 struct user_sgpr_info *user_sgpr_info)
557 {
558 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
559
560 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
561 if (ctx->stage == MESA_SHADER_GEOMETRY ||
562 ctx->stage == MESA_SHADER_VERTEX ||
563 ctx->stage == MESA_SHADER_TESS_CTRL ||
564 ctx->stage == MESA_SHADER_TESS_EVAL ||
565 ctx->is_gs_copy_shader)
566 user_sgpr_info->need_ring_offsets = true;
567
568 if (ctx->stage == MESA_SHADER_FRAGMENT &&
569 ctx->shader_info->info.ps.needs_sample_positions)
570 user_sgpr_info->need_ring_offsets = true;
571
572 /* 2 user sgprs will nearly always be allocated for scratch/rings */
573 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
574 user_sgpr_info->sgpr_count += 2;
575 }
576
577 switch (ctx->stage) {
578 case MESA_SHADER_COMPUTE:
579 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
580 break;
581 case MESA_SHADER_FRAGMENT:
582 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
583 break;
584 case MESA_SHADER_VERTEX:
585 if (!ctx->is_gs_copy_shader) {
586 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
587 if (ctx->shader_info->info.vs.needs_draw_id) {
588 user_sgpr_info->sgpr_count += 3;
589 } else {
590 user_sgpr_info->sgpr_count += 2;
591 }
592 }
593 if (ctx->options->key.vs.as_ls)
594 user_sgpr_info->sgpr_count++;
595 break;
596 case MESA_SHADER_TESS_CTRL:
597 user_sgpr_info->sgpr_count += 4;
598 break;
599 case MESA_SHADER_TESS_EVAL:
600 user_sgpr_info->sgpr_count += 1;
601 break;
602 case MESA_SHADER_GEOMETRY:
603 user_sgpr_info->sgpr_count += 2;
604 break;
605 default:
606 break;
607 }
608
609 if (ctx->shader_info->info.needs_push_constants)
610 user_sgpr_info->sgpr_count += 2;
611
612 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
613 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
614 user_sgpr_info->sgpr_count += 2;
615 user_sgpr_info->indirect_all_descriptor_sets = true;
616 } else {
617 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
618 }
619 }
620
621 static void
622 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
623 gl_shader_stage stage,
624 bool has_previous_stage,
625 gl_shader_stage previous_stage,
626 const struct user_sgpr_info *user_sgpr_info,
627 struct arg_info *args,
628 LLVMValueRef *desc_sets)
629 {
630 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
631 unsigned stage_mask = 1 << stage;
632 if (has_previous_stage)
633 stage_mask |= 1 << previous_stage;
634
635 /* 1 for each descriptor set */
636 if (!user_sgpr_info->indirect_all_descriptor_sets) {
637 for (unsigned i = 0; i < num_sets; ++i) {
638 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
639 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->descriptor_sets[i]);
640 }
641 }
642 } else
643 add_user_sgpr_array_argument(args, const_array(const_array(ctx->ac.i8, 1024 * 1024), 32), desc_sets);
644
645 if (ctx->shader_info->info.needs_push_constants) {
646 /* 1 for push constants and dynamic descriptors */
647 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->push_constants);
648 }
649 }
650
651 static void
652 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
653 gl_shader_stage stage,
654 bool has_previous_stage,
655 gl_shader_stage previous_stage,
656 const struct user_sgpr_info *user_sgpr_info,
657 LLVMValueRef desc_sets,
658 uint8_t *user_sgpr_idx)
659 {
660 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
661 unsigned stage_mask = 1 << stage;
662 if (has_previous_stage)
663 stage_mask |= 1 << previous_stage;
664
665 if (!user_sgpr_info->indirect_all_descriptor_sets) {
666 for (unsigned i = 0; i < num_sets; ++i) {
667 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
668 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
669 } else
670 ctx->descriptor_sets[i] = NULL;
671 }
672 } else {
673 uint32_t desc_sgpr_idx = *user_sgpr_idx;
674 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
675
676 for (unsigned i = 0; i < num_sets; ++i) {
677 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
678 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
679 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->ac.i32, i, false));
680
681 } else
682 ctx->descriptor_sets[i] = NULL;
683 }
684 ctx->shader_info->need_indirect_descriptor_sets = true;
685 }
686
687 if (ctx->shader_info->info.needs_push_constants) {
688 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
689 }
690 }
691
692 static void
693 radv_define_vs_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
694 gl_shader_stage stage,
695 bool has_previous_stage,
696 gl_shader_stage previous_stage,
697 struct arg_info *args)
698 {
699 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
700 if (ctx->shader_info->info.vs.has_vertex_buffers)
701 add_user_sgpr_argument(args, const_array(ctx->ac.v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
702 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.base_vertex); // base vertex
703 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.start_instance);// start instance
704 if (ctx->shader_info->info.vs.needs_draw_id)
705 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.draw_id); // draw id
706 }
707 }
708
709 static void
710 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
711 gl_shader_stage stage,
712 bool has_previous_stage,
713 gl_shader_stage previous_stage,
714 uint8_t *user_sgpr_idx)
715 {
716 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
717 if (ctx->shader_info->info.vs.has_vertex_buffers) {
718 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
719 }
720 unsigned vs_num = 2;
721 if (ctx->shader_info->info.vs.needs_draw_id)
722 vs_num++;
723
724 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
725 }
726 }
727
728
729 static void create_function(struct nir_to_llvm_context *ctx,
730 gl_shader_stage stage,
731 bool has_previous_stage,
732 gl_shader_stage previous_stage)
733 {
734 uint8_t user_sgpr_idx;
735 struct user_sgpr_info user_sgpr_info;
736 struct arg_info args = {};
737 LLVMValueRef desc_sets;
738
739 allocate_user_sgprs(ctx, &user_sgpr_info);
740
741 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
742 add_user_sgpr_argument(&args, const_array(ctx->ac.v4i32, 16), &ctx->ring_offsets); /* address of rings */
743 }
744
745 switch (stage) {
746 case MESA_SHADER_COMPUTE:
747 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
748 if (ctx->shader_info->info.cs.grid_components_used)
749 add_user_sgpr_argument(&args, LLVMVectorType(ctx->ac.i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
750 add_sgpr_argument(&args, ctx->ac.v3i32, &ctx->workgroup_ids);
751 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tg_size);
752 add_vgpr_argument(&args, ctx->ac.v3i32, &ctx->local_invocation_ids);
753 break;
754 case MESA_SHADER_VERTEX:
755 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
756 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
757 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
758 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
759 if (ctx->options->key.vs.as_es)
760 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
761 else if (ctx->options->key.vs.as_ls)
762 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
763 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
764 if (!ctx->is_gs_copy_shader) {
765 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
766 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
767 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
768 }
769 break;
770 case MESA_SHADER_TESS_CTRL:
771 if (has_previous_stage) {
772 // First 6 system regs
773 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
774 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
775 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
776
777 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
778 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
779 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
780
781 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
782 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
783 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
784
785 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
786 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
787 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
788 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
789 if (ctx->shader_info->info.needs_multiview_view_index)
790 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
791
792 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
793 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
794 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
795 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
796 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
797 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
798 } else {
799 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
800 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
801 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
802 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
803 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
804 if (ctx->shader_info->info.needs_multiview_view_index)
805 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
806 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
807 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
808 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
809 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
810 }
811 break;
812 case MESA_SHADER_TESS_EVAL:
813 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
814 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
815 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
816 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
817 if (ctx->options->key.tes.as_es) {
818 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
819 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
820 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
821 } else {
822 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
823 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
824 }
825 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
826 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
827 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
828 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
829 break;
830 case MESA_SHADER_GEOMETRY:
831 if (has_previous_stage) {
832 // First 6 system regs
833 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // tess factor offset
834 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
835 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
836
837 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
838 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
839 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
840
841 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
842 if (previous_stage == MESA_SHADER_TESS_EVAL)
843 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
844 else
845 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
846 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
847 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
848 if (ctx->shader_info->info.needs_multiview_view_index)
849 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
850
851 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx01
852 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]); // vtx23
853 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_prim_id); // prim id
854 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_invocation_id);
855 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
856
857 if (previous_stage == MESA_SHADER_VERTEX) {
858 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
859 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
860 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
861 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
862 } else {
863 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
864 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
865 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
866 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
867 }
868 } else {
869 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
870 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
871 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
872 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
873 if (ctx->shader_info->info.needs_multiview_view_index)
874 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
875 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // gs2vs offset
876 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs_wave_id); // wave id
877 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx0
878 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[1]); // vtx1
879 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_prim_id); // prim id
880 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]);
881 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[3]);
882 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
883 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[5]);
884 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_invocation_id);
885 }
886 break;
887 case MESA_SHADER_FRAGMENT:
888 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
889 if (ctx->shader_info->info.ps.needs_sample_positions)
890 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->sample_pos_offset); /* sample position offset */
891 add_sgpr_argument(&args, ctx->ac.i32, &ctx->prim_mask); /* prim mask */
892 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_sample); /* persp sample */
893 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_center); /* persp center */
894 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_centroid); /* persp centroid */
895 add_vgpr_argument(&args, ctx->ac.v3i32, NULL); /* persp pull model */
896 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_sample); /* linear sample */
897 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_center); /* linear center */
898 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_centroid); /* linear centroid */
899 add_vgpr_argument(&args, ctx->ac.f32, NULL); /* line stipple tex */
900 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[0]); /* pos x float */
901 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[1]); /* pos y float */
902 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[2]); /* pos z float */
903 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[3]); /* pos w float */
904 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.front_face); /* front face */
905 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.ancillary); /* ancillary */
906 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.sample_coverage); /* sample coverage */
907 add_vgpr_argument(&args, ctx->ac.i32, NULL); /* fixed pt */
908 break;
909 default:
910 unreachable("Shader stage not implemented");
911 }
912
913 ctx->main_function = create_llvm_function(
914 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
915 ctx->max_workgroup_size,
916 ctx->options->unsafe_math);
917 set_llvm_calling_convention(ctx->main_function, stage);
918
919
920 ctx->shader_info->num_input_vgprs = 0;
921 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
922
923 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
924
925 if (ctx->stage != MESA_SHADER_FRAGMENT)
926 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
927
928 assign_arguments(ctx->main_function, &args);
929
930 user_sgpr_idx = 0;
931
932 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
933 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
934 if (ctx->options->supports_spill) {
935 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
936 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
937 NULL, 0, AC_FUNC_ATTR_READNONE);
938 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
939 const_array(ctx->ac.v4i32, 16), "");
940 }
941 }
942
943 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
944 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
945 if (has_previous_stage)
946 user_sgpr_idx = 0;
947
948 radv_define_common_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, desc_sets, &user_sgpr_idx);
949
950 switch (stage) {
951 case MESA_SHADER_COMPUTE:
952 if (ctx->shader_info->info.cs.grid_components_used) {
953 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
954 }
955 break;
956 case MESA_SHADER_VERTEX:
957 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
958 if (ctx->view_index)
959 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
960 if (ctx->options->key.vs.as_ls) {
961 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
962 }
963 if (ctx->options->key.vs.as_ls)
964 ac_declare_lds_as_pointer(&ctx->ac);
965 break;
966 case MESA_SHADER_TESS_CTRL:
967 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
968 if (has_previous_stage)
969 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
970 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
971 if (ctx->view_index)
972 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
973 ac_declare_lds_as_pointer(&ctx->ac);
974 break;
975 case MESA_SHADER_TESS_EVAL:
976 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
977 if (ctx->view_index)
978 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
979 break;
980 case MESA_SHADER_GEOMETRY:
981 if (has_previous_stage) {
982 if (previous_stage == MESA_SHADER_VERTEX)
983 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
984 else
985 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
986 }
987 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
988 if (ctx->view_index)
989 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
990 if (has_previous_stage)
991 ac_declare_lds_as_pointer(&ctx->ac);
992 break;
993 case MESA_SHADER_FRAGMENT:
994 if (ctx->shader_info->info.ps.needs_sample_positions) {
995 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
996 }
997 break;
998 default:
999 unreachable("Shader stage not implemented");
1000 }
1001
1002 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1003 }
1004
1005 static int get_llvm_num_components(LLVMValueRef value)
1006 {
1007 LLVMTypeRef type = LLVMTypeOf(value);
1008 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1009 ? LLVMGetVectorSize(type)
1010 : 1;
1011 return num_components;
1012 }
1013
1014 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1015 LLVMValueRef value,
1016 int index)
1017 {
1018 int count = get_llvm_num_components(value);
1019
1020 if (count == 1)
1021 return value;
1022
1023 return LLVMBuildExtractElement(ac->builder, value,
1024 LLVMConstInt(ac->i32, index, false), "");
1025 }
1026
1027 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1028 LLVMValueRef value, unsigned count)
1029 {
1030 unsigned num_components = get_llvm_num_components(value);
1031 if (count == num_components)
1032 return value;
1033
1034 LLVMValueRef masks[] = {
1035 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1036 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1037
1038 if (count == 1)
1039 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1040 "");
1041
1042 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1043 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1044 }
1045
1046 static void
1047 build_store_values_extended(struct ac_llvm_context *ac,
1048 LLVMValueRef *values,
1049 unsigned value_count,
1050 unsigned value_stride,
1051 LLVMValueRef vec)
1052 {
1053 LLVMBuilderRef builder = ac->builder;
1054 unsigned i;
1055
1056 for (i = 0; i < value_count; i++) {
1057 LLVMValueRef ptr = values[i * value_stride];
1058 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1059 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1060 LLVMBuildStore(builder, value, ptr);
1061 }
1062 }
1063
1064 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1065 const nir_ssa_def *def)
1066 {
1067 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1068 if (def->num_components > 1) {
1069 type = LLVMVectorType(type, def->num_components);
1070 }
1071 return type;
1072 }
1073
1074 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1075 {
1076 assert(src.is_ssa);
1077 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1078 return (LLVMValueRef)entry->data;
1079 }
1080
1081
1082 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1083 const struct nir_block *b)
1084 {
1085 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1086 return (LLVMBasicBlockRef)entry->data;
1087 }
1088
1089 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1090 nir_alu_src src,
1091 unsigned num_components)
1092 {
1093 LLVMValueRef value = get_src(ctx, src.src);
1094 bool need_swizzle = false;
1095
1096 assert(value);
1097 LLVMTypeRef type = LLVMTypeOf(value);
1098 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1099 ? LLVMGetVectorSize(type)
1100 : 1;
1101
1102 for (unsigned i = 0; i < num_components; ++i) {
1103 assert(src.swizzle[i] < src_components);
1104 if (src.swizzle[i] != i)
1105 need_swizzle = true;
1106 }
1107
1108 if (need_swizzle || num_components != src_components) {
1109 LLVMValueRef masks[] = {
1110 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1111 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1112 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1113 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1114
1115 if (src_components > 1 && num_components == 1) {
1116 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1117 masks[0], "");
1118 } else if (src_components == 1 && num_components > 1) {
1119 LLVMValueRef values[] = {value, value, value, value};
1120 value = ac_build_gather_values(&ctx->ac, values, num_components);
1121 } else {
1122 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1123 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1124 swizzle, "");
1125 }
1126 }
1127 assert(!src.negate);
1128 assert(!src.abs);
1129 return value;
1130 }
1131
1132 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1133 LLVMIntPredicate pred, LLVMValueRef src0,
1134 LLVMValueRef src1)
1135 {
1136 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1137 return LLVMBuildSelect(ctx->builder, result,
1138 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1139 LLVMConstInt(ctx->i32, 0, false), "");
1140 }
1141
1142 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1143 LLVMRealPredicate pred, LLVMValueRef src0,
1144 LLVMValueRef src1)
1145 {
1146 LLVMValueRef result;
1147 src0 = ac_to_float(ctx, src0);
1148 src1 = ac_to_float(ctx, src1);
1149 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1150 return LLVMBuildSelect(ctx->builder, result,
1151 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1152 LLVMConstInt(ctx->i32, 0, false), "");
1153 }
1154
1155 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1156 const char *intrin,
1157 LLVMTypeRef result_type,
1158 LLVMValueRef src0)
1159 {
1160 char name[64];
1161 LLVMValueRef params[] = {
1162 ac_to_float(ctx, src0),
1163 };
1164
1165 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1166 get_elem_bits(ctx, result_type));
1167 assert(length < sizeof(name));
1168 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1169 }
1170
1171 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1172 const char *intrin,
1173 LLVMTypeRef result_type,
1174 LLVMValueRef src0, LLVMValueRef src1)
1175 {
1176 char name[64];
1177 LLVMValueRef params[] = {
1178 ac_to_float(ctx, src0),
1179 ac_to_float(ctx, src1),
1180 };
1181
1182 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1183 get_elem_bits(ctx, result_type));
1184 assert(length < sizeof(name));
1185 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1186 }
1187
1188 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1189 const char *intrin,
1190 LLVMTypeRef result_type,
1191 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1192 {
1193 char name[64];
1194 LLVMValueRef params[] = {
1195 ac_to_float(ctx, src0),
1196 ac_to_float(ctx, src1),
1197 ac_to_float(ctx, src2),
1198 };
1199
1200 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1201 get_elem_bits(ctx, result_type));
1202 assert(length < sizeof(name));
1203 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1204 }
1205
1206 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1207 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1208 {
1209 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1210 ctx->i32_0, "");
1211 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1212 }
1213
1214 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1215 LLVMIntPredicate pred,
1216 LLVMValueRef src0, LLVMValueRef src1)
1217 {
1218 return LLVMBuildSelect(ctx->builder,
1219 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1220 src0,
1221 src1, "");
1222
1223 }
1224 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1225 LLVMValueRef src0)
1226 {
1227 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1228 LLVMBuildNeg(ctx->builder, src0, ""));
1229 }
1230
1231 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1232 LLVMValueRef src0)
1233 {
1234 LLVMValueRef cmp, val;
1235
1236 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1237 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1238 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1239 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1240 return val;
1241 }
1242
1243 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1244 LLVMValueRef src0)
1245 {
1246 LLVMValueRef cmp, val;
1247
1248 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1249 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1250 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1251 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1252 return val;
1253 }
1254
1255 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1256 LLVMValueRef src0)
1257 {
1258 const char *intr = "llvm.floor.f32";
1259 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1260 LLVMValueRef params[] = {
1261 fsrc0,
1262 };
1263 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1264 ctx->f32, params, 1,
1265 AC_FUNC_ATTR_READNONE);
1266 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1267 }
1268
1269 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1270 const char *intrin,
1271 LLVMValueRef src0, LLVMValueRef src1)
1272 {
1273 LLVMTypeRef ret_type;
1274 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1275 LLVMValueRef res;
1276 LLVMValueRef params[] = { src0, src1 };
1277 ret_type = LLVMStructTypeInContext(ctx->context, types,
1278 2, true);
1279
1280 res = ac_build_intrinsic(ctx, intrin, ret_type,
1281 params, 2, AC_FUNC_ATTR_READNONE);
1282
1283 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1284 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1285 return res;
1286 }
1287
1288 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1289 LLVMValueRef src0)
1290 {
1291 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1292 }
1293
1294 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1295 LLVMValueRef src0)
1296 {
1297 src0 = ac_to_float(ctx, src0);
1298 return LLVMBuildSExt(ctx->builder,
1299 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1300 ctx->i32, "");
1301 }
1302
1303 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1304 LLVMValueRef src0)
1305 {
1306 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1307 }
1308
1309 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1310 LLVMValueRef src0)
1311 {
1312 return LLVMBuildSExt(ctx->builder,
1313 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1314 ctx->i32, "");
1315 }
1316
1317 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1318 LLVMValueRef src0)
1319 {
1320 LLVMValueRef result;
1321 LLVMValueRef cond = NULL;
1322
1323 src0 = ac_to_float(&ctx->ac, src0);
1324 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1325
1326 if (ctx->options->chip_class >= VI) {
1327 LLVMValueRef args[2];
1328 /* Check if the result is a denormal - and flush to 0 if so. */
1329 args[0] = result;
1330 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1331 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1332 }
1333
1334 /* need to convert back up to f32 */
1335 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1336
1337 if (ctx->options->chip_class >= VI)
1338 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1339 else {
1340 /* for SI/CIK */
1341 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1342 * so compare the result and flush to 0 if it's smaller.
1343 */
1344 LLVMValueRef temp, cond2;
1345 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1346 ctx->ac.f32, result);
1347 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1348 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1349 temp, "");
1350 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1351 temp, ctx->ac.f32_0, "");
1352 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1353 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1354 }
1355 return result;
1356 }
1357
1358 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1359 LLVMValueRef src0, LLVMValueRef src1)
1360 {
1361 LLVMValueRef dst64, result;
1362 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1363 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1364
1365 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1366 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1367 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1368 return result;
1369 }
1370
1371 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1372 LLVMValueRef src0, LLVMValueRef src1)
1373 {
1374 LLVMValueRef dst64, result;
1375 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1376 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1377
1378 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1379 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1380 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1381 return result;
1382 }
1383
1384 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1385 bool is_signed,
1386 const LLVMValueRef srcs[3])
1387 {
1388 LLVMValueRef result;
1389 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1390
1391 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1392 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1393 return result;
1394 }
1395
1396 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1397 LLVMValueRef src0, LLVMValueRef src1,
1398 LLVMValueRef src2, LLVMValueRef src3)
1399 {
1400 LLVMValueRef bfi_args[3], result;
1401
1402 bfi_args[0] = LLVMBuildShl(ctx->builder,
1403 LLVMBuildSub(ctx->builder,
1404 LLVMBuildShl(ctx->builder,
1405 ctx->i32_1,
1406 src3, ""),
1407 ctx->i32_1, ""),
1408 src2, "");
1409 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1410 bfi_args[2] = src0;
1411
1412 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1413
1414 /* Calculate:
1415 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1416 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1417 */
1418 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1419 LLVMBuildAnd(ctx->builder, bfi_args[0],
1420 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1421
1422 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1423 return result;
1424 }
1425
1426 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1427 LLVMValueRef src0)
1428 {
1429 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1430 int i;
1431 LLVMValueRef comp[2];
1432
1433 src0 = ac_to_float(ctx, src0);
1434 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1435 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1436 for (i = 0; i < 2; i++) {
1437 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1438 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1439 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1440 }
1441
1442 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1443 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1444
1445 return comp[0];
1446 }
1447
1448 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1449 LLVMValueRef src0)
1450 {
1451 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1452 LLVMValueRef temps[2], result, val;
1453 int i;
1454
1455 for (i = 0; i < 2; i++) {
1456 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1457 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1458 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1459 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1460 }
1461
1462 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1463 ctx->i32_0, "");
1464 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1465 ctx->i32_1, "");
1466 return result;
1467 }
1468
1469 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1470 nir_op op,
1471 LLVMValueRef src0)
1472 {
1473 unsigned mask;
1474 int idx;
1475 LLVMValueRef result;
1476
1477 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1478 mask = AC_TID_MASK_LEFT;
1479 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1480 mask = AC_TID_MASK_TOP;
1481 else
1482 mask = AC_TID_MASK_TOP_LEFT;
1483
1484 /* for DDX we want to next X pixel, DDY next Y pixel. */
1485 if (op == nir_op_fddx_fine ||
1486 op == nir_op_fddx_coarse ||
1487 op == nir_op_fddx)
1488 idx = 1;
1489 else
1490 idx = 2;
1491
1492 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1493 return result;
1494 }
1495
1496 /*
1497 * this takes an I,J coordinate pair,
1498 * and works out the X and Y derivatives.
1499 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1500 */
1501 static LLVMValueRef emit_ddxy_interp(
1502 struct ac_nir_context *ctx,
1503 LLVMValueRef interp_ij)
1504 {
1505 LLVMValueRef result[4], a;
1506 unsigned i;
1507
1508 for (i = 0; i < 2; i++) {
1509 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1510 LLVMConstInt(ctx->ac.i32, i, false), "");
1511 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1512 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1513 }
1514 return ac_build_gather_values(&ctx->ac, result, 4);
1515 }
1516
1517 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1518 {
1519 LLVMValueRef src[4], result = NULL;
1520 unsigned num_components = instr->dest.dest.ssa.num_components;
1521 unsigned src_components;
1522 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1523
1524 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1525 switch (instr->op) {
1526 case nir_op_vec2:
1527 case nir_op_vec3:
1528 case nir_op_vec4:
1529 src_components = 1;
1530 break;
1531 case nir_op_pack_half_2x16:
1532 src_components = 2;
1533 break;
1534 case nir_op_unpack_half_2x16:
1535 src_components = 1;
1536 break;
1537 default:
1538 src_components = num_components;
1539 break;
1540 }
1541 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1542 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1543
1544 switch (instr->op) {
1545 case nir_op_fmov:
1546 case nir_op_imov:
1547 result = src[0];
1548 break;
1549 case nir_op_fneg:
1550 src[0] = ac_to_float(&ctx->ac, src[0]);
1551 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1552 break;
1553 case nir_op_ineg:
1554 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1555 break;
1556 case nir_op_inot:
1557 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1558 break;
1559 case nir_op_iadd:
1560 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1561 break;
1562 case nir_op_fadd:
1563 src[0] = ac_to_float(&ctx->ac, src[0]);
1564 src[1] = ac_to_float(&ctx->ac, src[1]);
1565 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1566 break;
1567 case nir_op_fsub:
1568 src[0] = ac_to_float(&ctx->ac, src[0]);
1569 src[1] = ac_to_float(&ctx->ac, src[1]);
1570 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1571 break;
1572 case nir_op_isub:
1573 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1574 break;
1575 case nir_op_imul:
1576 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1577 break;
1578 case nir_op_imod:
1579 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1580 break;
1581 case nir_op_umod:
1582 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1583 break;
1584 case nir_op_fmod:
1585 src[0] = ac_to_float(&ctx->ac, src[0]);
1586 src[1] = ac_to_float(&ctx->ac, src[1]);
1587 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1588 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1589 ac_to_float_type(&ctx->ac, def_type), result);
1590 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1591 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1592 break;
1593 case nir_op_frem:
1594 src[0] = ac_to_float(&ctx->ac, src[0]);
1595 src[1] = ac_to_float(&ctx->ac, src[1]);
1596 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1597 break;
1598 case nir_op_irem:
1599 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1600 break;
1601 case nir_op_idiv:
1602 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1603 break;
1604 case nir_op_udiv:
1605 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1606 break;
1607 case nir_op_fmul:
1608 src[0] = ac_to_float(&ctx->ac, src[0]);
1609 src[1] = ac_to_float(&ctx->ac, src[1]);
1610 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1611 break;
1612 case nir_op_fdiv:
1613 src[0] = ac_to_float(&ctx->ac, src[0]);
1614 src[1] = ac_to_float(&ctx->ac, src[1]);
1615 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1616 break;
1617 case nir_op_frcp:
1618 src[0] = ac_to_float(&ctx->ac, src[0]);
1619 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1620 break;
1621 case nir_op_iand:
1622 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1623 break;
1624 case nir_op_ior:
1625 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1626 break;
1627 case nir_op_ixor:
1628 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1629 break;
1630 case nir_op_ishl:
1631 result = LLVMBuildShl(ctx->ac.builder, src[0],
1632 LLVMBuildZExt(ctx->ac.builder, src[1],
1633 LLVMTypeOf(src[0]), ""),
1634 "");
1635 break;
1636 case nir_op_ishr:
1637 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1638 LLVMBuildZExt(ctx->ac.builder, src[1],
1639 LLVMTypeOf(src[0]), ""),
1640 "");
1641 break;
1642 case nir_op_ushr:
1643 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1644 LLVMBuildZExt(ctx->ac.builder, src[1],
1645 LLVMTypeOf(src[0]), ""),
1646 "");
1647 break;
1648 case nir_op_ilt:
1649 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1650 break;
1651 case nir_op_ine:
1652 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1653 break;
1654 case nir_op_ieq:
1655 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1656 break;
1657 case nir_op_ige:
1658 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1659 break;
1660 case nir_op_ult:
1661 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1662 break;
1663 case nir_op_uge:
1664 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1665 break;
1666 case nir_op_feq:
1667 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1668 break;
1669 case nir_op_fne:
1670 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1671 break;
1672 case nir_op_flt:
1673 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1674 break;
1675 case nir_op_fge:
1676 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1677 break;
1678 case nir_op_fabs:
1679 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1680 ac_to_float_type(&ctx->ac, def_type), src[0]);
1681 break;
1682 case nir_op_iabs:
1683 result = emit_iabs(&ctx->ac, src[0]);
1684 break;
1685 case nir_op_imax:
1686 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1687 break;
1688 case nir_op_imin:
1689 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1690 break;
1691 case nir_op_umax:
1692 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1693 break;
1694 case nir_op_umin:
1695 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1696 break;
1697 case nir_op_isign:
1698 result = emit_isign(&ctx->ac, src[0]);
1699 break;
1700 case nir_op_fsign:
1701 src[0] = ac_to_float(&ctx->ac, src[0]);
1702 result = emit_fsign(&ctx->ac, src[0]);
1703 break;
1704 case nir_op_ffloor:
1705 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1706 ac_to_float_type(&ctx->ac, def_type), src[0]);
1707 break;
1708 case nir_op_ftrunc:
1709 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1710 ac_to_float_type(&ctx->ac, def_type), src[0]);
1711 break;
1712 case nir_op_fceil:
1713 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1714 ac_to_float_type(&ctx->ac, def_type), src[0]);
1715 break;
1716 case nir_op_fround_even:
1717 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1718 ac_to_float_type(&ctx->ac, def_type),src[0]);
1719 break;
1720 case nir_op_ffract:
1721 result = emit_ffract(&ctx->ac, src[0]);
1722 break;
1723 case nir_op_fsin:
1724 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1725 ac_to_float_type(&ctx->ac, def_type), src[0]);
1726 break;
1727 case nir_op_fcos:
1728 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1729 ac_to_float_type(&ctx->ac, def_type), src[0]);
1730 break;
1731 case nir_op_fsqrt:
1732 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1733 ac_to_float_type(&ctx->ac, def_type), src[0]);
1734 break;
1735 case nir_op_fexp2:
1736 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1737 ac_to_float_type(&ctx->ac, def_type), src[0]);
1738 break;
1739 case nir_op_flog2:
1740 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1741 ac_to_float_type(&ctx->ac, def_type), src[0]);
1742 break;
1743 case nir_op_frsq:
1744 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1745 ac_to_float_type(&ctx->ac, def_type), src[0]);
1746 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1747 break;
1748 case nir_op_fpow:
1749 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1750 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1751 break;
1752 case nir_op_fmax:
1753 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1754 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1755 if (instr->dest.dest.ssa.bit_size == 32)
1756 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1757 ac_to_float_type(&ctx->ac, def_type),
1758 result);
1759 break;
1760 case nir_op_fmin:
1761 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1762 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1763 if (instr->dest.dest.ssa.bit_size == 32)
1764 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1765 ac_to_float_type(&ctx->ac, def_type),
1766 result);
1767 break;
1768 case nir_op_ffma:
1769 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1770 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1771 break;
1772 case nir_op_ibitfield_extract:
1773 result = emit_bitfield_extract(&ctx->ac, true, src);
1774 break;
1775 case nir_op_ubitfield_extract:
1776 result = emit_bitfield_extract(&ctx->ac, false, src);
1777 break;
1778 case nir_op_bitfield_insert:
1779 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1780 break;
1781 case nir_op_bitfield_reverse:
1782 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1783 break;
1784 case nir_op_bit_count:
1785 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1786 break;
1787 case nir_op_vec2:
1788 case nir_op_vec3:
1789 case nir_op_vec4:
1790 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1791 src[i] = ac_to_integer(&ctx->ac, src[i]);
1792 result = ac_build_gather_values(&ctx->ac, src, num_components);
1793 break;
1794 case nir_op_f2i32:
1795 case nir_op_f2i64:
1796 src[0] = ac_to_float(&ctx->ac, src[0]);
1797 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1798 break;
1799 case nir_op_f2u32:
1800 case nir_op_f2u64:
1801 src[0] = ac_to_float(&ctx->ac, src[0]);
1802 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1803 break;
1804 case nir_op_i2f32:
1805 case nir_op_i2f64:
1806 src[0] = ac_to_integer(&ctx->ac, src[0]);
1807 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1808 break;
1809 case nir_op_u2f32:
1810 case nir_op_u2f64:
1811 src[0] = ac_to_integer(&ctx->ac, src[0]);
1812 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1813 break;
1814 case nir_op_f2f64:
1815 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1816 break;
1817 case nir_op_f2f32:
1818 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1819 break;
1820 case nir_op_u2u32:
1821 case nir_op_u2u64:
1822 src[0] = ac_to_integer(&ctx->ac, src[0]);
1823 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1824 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1825 else
1826 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1827 break;
1828 case nir_op_i2i32:
1829 case nir_op_i2i64:
1830 src[0] = ac_to_integer(&ctx->ac, src[0]);
1831 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1832 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1833 else
1834 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1835 break;
1836 case nir_op_bcsel:
1837 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1838 break;
1839 case nir_op_find_lsb:
1840 src[0] = ac_to_integer(&ctx->ac, src[0]);
1841 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1842 break;
1843 case nir_op_ufind_msb:
1844 src[0] = ac_to_integer(&ctx->ac, src[0]);
1845 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1846 break;
1847 case nir_op_ifind_msb:
1848 src[0] = ac_to_integer(&ctx->ac, src[0]);
1849 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1850 break;
1851 case nir_op_uadd_carry:
1852 src[0] = ac_to_integer(&ctx->ac, src[0]);
1853 src[1] = ac_to_integer(&ctx->ac, src[1]);
1854 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1855 break;
1856 case nir_op_usub_borrow:
1857 src[0] = ac_to_integer(&ctx->ac, src[0]);
1858 src[1] = ac_to_integer(&ctx->ac, src[1]);
1859 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1860 break;
1861 case nir_op_b2f:
1862 result = emit_b2f(&ctx->ac, src[0]);
1863 break;
1864 case nir_op_f2b:
1865 result = emit_f2b(&ctx->ac, src[0]);
1866 break;
1867 case nir_op_b2i:
1868 result = emit_b2i(&ctx->ac, src[0]);
1869 break;
1870 case nir_op_i2b:
1871 src[0] = ac_to_integer(&ctx->ac, src[0]);
1872 result = emit_i2b(&ctx->ac, src[0]);
1873 break;
1874 case nir_op_fquantize2f16:
1875 result = emit_f2f16(ctx->nctx, src[0]);
1876 break;
1877 case nir_op_umul_high:
1878 src[0] = ac_to_integer(&ctx->ac, src[0]);
1879 src[1] = ac_to_integer(&ctx->ac, src[1]);
1880 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1881 break;
1882 case nir_op_imul_high:
1883 src[0] = ac_to_integer(&ctx->ac, src[0]);
1884 src[1] = ac_to_integer(&ctx->ac, src[1]);
1885 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1886 break;
1887 case nir_op_pack_half_2x16:
1888 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1889 break;
1890 case nir_op_unpack_half_2x16:
1891 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1892 break;
1893 case nir_op_fddx:
1894 case nir_op_fddy:
1895 case nir_op_fddx_fine:
1896 case nir_op_fddy_fine:
1897 case nir_op_fddx_coarse:
1898 case nir_op_fddy_coarse:
1899 result = emit_ddxy(ctx, instr->op, src[0]);
1900 break;
1901
1902 case nir_op_unpack_64_2x32_split_x: {
1903 assert(instr->src[0].src.ssa->num_components == 1);
1904 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1905 ctx->ac.v2i32,
1906 "");
1907 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1908 ctx->ac.i32_0, "");
1909 break;
1910 }
1911
1912 case nir_op_unpack_64_2x32_split_y: {
1913 assert(instr->src[0].src.ssa->num_components == 1);
1914 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1915 ctx->ac.v2i32,
1916 "");
1917 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1918 ctx->ac.i32_1, "");
1919 break;
1920 }
1921
1922 case nir_op_pack_64_2x32_split: {
1923 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
1924 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1925 src[0], ctx->ac.i32_0, "");
1926 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1927 src[1], ctx->ac.i32_1, "");
1928 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1929 break;
1930 }
1931
1932 default:
1933 fprintf(stderr, "Unknown NIR alu instr: ");
1934 nir_print_instr(&instr->instr, stderr);
1935 fprintf(stderr, "\n");
1936 abort();
1937 }
1938
1939 if (result) {
1940 assert(instr->dest.dest.is_ssa);
1941 result = ac_to_integer(&ctx->ac, result);
1942 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1943 result);
1944 }
1945 }
1946
1947 static void visit_load_const(struct ac_nir_context *ctx,
1948 const nir_load_const_instr *instr)
1949 {
1950 LLVMValueRef values[4], value = NULL;
1951 LLVMTypeRef element_type =
1952 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1953
1954 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1955 switch (instr->def.bit_size) {
1956 case 32:
1957 values[i] = LLVMConstInt(element_type,
1958 instr->value.u32[i], false);
1959 break;
1960 case 64:
1961 values[i] = LLVMConstInt(element_type,
1962 instr->value.u64[i], false);
1963 break;
1964 default:
1965 fprintf(stderr,
1966 "unsupported nir load_const bit_size: %d\n",
1967 instr->def.bit_size);
1968 abort();
1969 }
1970 }
1971 if (instr->def.num_components > 1) {
1972 value = LLVMConstVector(values, instr->def.num_components);
1973 } else
1974 value = values[0];
1975
1976 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1977 }
1978
1979 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1980 LLVMTypeRef type)
1981 {
1982 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1983 return LLVMBuildBitCast(ctx->builder, ptr,
1984 LLVMPointerType(type, addr_space), "");
1985 }
1986
1987 static LLVMValueRef
1988 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1989 {
1990 LLVMValueRef size =
1991 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1992 LLVMConstInt(ctx->ac.i32, 2, false), "");
1993
1994 /* VI only */
1995 if (ctx->ac.chip_class == VI && in_elements) {
1996 /* On VI, the descriptor contains the size in bytes,
1997 * but TXQ must return the size in elements.
1998 * The stride is always non-zero for resources using TXQ.
1999 */
2000 LLVMValueRef stride =
2001 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2002 LLVMConstInt(ctx->ac.i32, 1, false), "");
2003 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2004 LLVMConstInt(ctx->ac.i32, 16, false), "");
2005 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2006 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2007
2008 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2009 }
2010 return size;
2011 }
2012
2013 /**
2014 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2015 * intrinsic names).
2016 */
2017 static void build_int_type_name(
2018 LLVMTypeRef type,
2019 char *buf, unsigned bufsize)
2020 {
2021 assert(bufsize >= 6);
2022
2023 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2024 snprintf(buf, bufsize, "v%ui32",
2025 LLVMGetVectorSize(type));
2026 else
2027 strcpy(buf, "i32");
2028 }
2029
2030 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2031 struct ac_image_args *args,
2032 const nir_tex_instr *instr)
2033 {
2034 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2035 LLVMValueRef coord = args->addr;
2036 LLVMValueRef half_texel[2];
2037 LLVMValueRef compare_cube_wa = NULL;
2038 LLVMValueRef result;
2039 int c;
2040 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2041
2042 //TODO Rect
2043 {
2044 struct ac_image_args txq_args = { 0 };
2045
2046 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2047 txq_args.opcode = ac_image_get_resinfo;
2048 txq_args.dmask = 0xf;
2049 txq_args.addr = ctx->i32_0;
2050 txq_args.resource = args->resource;
2051 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2052
2053 for (c = 0; c < 2; c++) {
2054 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2055 LLVMConstInt(ctx->i32, c, false), "");
2056 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2057 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2058 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2059 LLVMConstReal(ctx->f32, -0.5), "");
2060 }
2061 }
2062
2063 LLVMValueRef orig_coords = args->addr;
2064
2065 for (c = 0; c < 2; c++) {
2066 LLVMValueRef tmp;
2067 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2068 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2069 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2070 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2071 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2072 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2073 }
2074
2075
2076 /*
2077 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2078 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2079 * workaround by sampling using a scaled type and converting.
2080 * This is taken from amdgpu-pro shaders.
2081 */
2082 /* NOTE this produces some ugly code compared to amdgpu-pro,
2083 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2084 * and then reads them back. -pro generates two selects,
2085 * one s_cmp for the descriptor rewriting
2086 * one v_cmp for the coordinate and result changes.
2087 */
2088 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2089 LLVMValueRef tmp, tmp2;
2090
2091 /* workaround 8/8/8/8 uint/sint cube gather bug */
2092 /* first detect it then change to a scaled read and f2i */
2093 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2094 tmp2 = tmp;
2095
2096 /* extract the DATA_FORMAT */
2097 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2098 LLVMConstInt(ctx->i32, 6, false), false);
2099
2100 /* is the DATA_FORMAT == 8_8_8_8 */
2101 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2102
2103 if (stype == GLSL_TYPE_UINT)
2104 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2105 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2106 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2107 else
2108 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2109 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2110 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2111
2112 /* replace the NUM FORMAT in the descriptor */
2113 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2114 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2115
2116 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2117
2118 /* don't modify the coordinates for this case */
2119 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2120 }
2121 args->addr = coord;
2122 result = ac_build_image_opcode(ctx, args);
2123
2124 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2125 LLVMValueRef tmp, tmp2;
2126
2127 /* if the cube workaround is in place, f2i the result. */
2128 for (c = 0; c < 4; c++) {
2129 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2130 if (stype == GLSL_TYPE_UINT)
2131 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2132 else
2133 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2134 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2135 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2136 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2137 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2138 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2139 }
2140 }
2141 return result;
2142 }
2143
2144 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2145 const nir_tex_instr *instr,
2146 bool lod_is_zero,
2147 struct ac_image_args *args)
2148 {
2149 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2150 return ac_build_buffer_load_format(&ctx->ac,
2151 args->resource,
2152 args->addr,
2153 LLVMConstInt(ctx->ac.i32, 0, false),
2154 true);
2155 }
2156
2157 args->opcode = ac_image_sample;
2158 args->compare = instr->is_shadow;
2159
2160 switch (instr->op) {
2161 case nir_texop_txf:
2162 case nir_texop_txf_ms:
2163 case nir_texop_samples_identical:
2164 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2165 args->compare = false;
2166 args->offset = false;
2167 break;
2168 case nir_texop_txb:
2169 args->bias = true;
2170 break;
2171 case nir_texop_txl:
2172 if (lod_is_zero)
2173 args->level_zero = true;
2174 else
2175 args->lod = true;
2176 break;
2177 case nir_texop_txs:
2178 case nir_texop_query_levels:
2179 args->opcode = ac_image_get_resinfo;
2180 break;
2181 case nir_texop_tex:
2182 if (ctx->stage != MESA_SHADER_FRAGMENT)
2183 args->level_zero = true;
2184 break;
2185 case nir_texop_txd:
2186 args->deriv = true;
2187 break;
2188 case nir_texop_tg4:
2189 args->opcode = ac_image_gather4;
2190 args->level_zero = true;
2191 break;
2192 case nir_texop_lod:
2193 args->opcode = ac_image_get_lod;
2194 args->compare = false;
2195 args->offset = false;
2196 break;
2197 default:
2198 break;
2199 }
2200
2201 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2202 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2203 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2204 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2205 }
2206 }
2207 return ac_build_image_opcode(&ctx->ac, args);
2208 }
2209
2210 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2211 nir_intrinsic_instr *instr)
2212 {
2213 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2214 unsigned desc_set = nir_intrinsic_desc_set(instr);
2215 unsigned binding = nir_intrinsic_binding(instr);
2216 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2217 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2218 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2219 unsigned base_offset = layout->binding[binding].offset;
2220 LLVMValueRef offset, stride;
2221
2222 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2223 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2224 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2225 layout->binding[binding].dynamic_offset_offset;
2226 desc_ptr = ctx->push_constants;
2227 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2228 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2229 } else
2230 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2231
2232 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2233 index = LLVMBuildMul(ctx->builder, index, stride, "");
2234 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2235
2236 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2237 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2238 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2239
2240 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2241 }
2242
2243 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2244 nir_intrinsic_instr *instr)
2245 {
2246 LLVMValueRef ptr, addr;
2247
2248 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2249 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2250
2251 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2252 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2253
2254 return LLVMBuildLoad(ctx->builder, ptr, "");
2255 }
2256
2257 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2258 const nir_intrinsic_instr *instr)
2259 {
2260 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2261
2262 return get_buffer_size(ctx, desc, false);
2263 }
2264 static void visit_store_ssbo(struct ac_nir_context *ctx,
2265 nir_intrinsic_instr *instr)
2266 {
2267 const char *store_name;
2268 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2269 LLVMTypeRef data_type = ctx->ac.f32;
2270 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2271 int components_32bit = elem_size_mult * instr->num_components;
2272 unsigned writemask = nir_intrinsic_write_mask(instr);
2273 LLVMValueRef base_data, base_offset;
2274 LLVMValueRef params[6];
2275
2276 params[1] = ctx->abi->load_ssbo(ctx->abi,
2277 get_src(ctx, instr->src[1]), true);
2278 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2279 params[4] = ctx->ac.i1false; /* glc */
2280 params[5] = ctx->ac.i1false; /* slc */
2281
2282 if (components_32bit > 1)
2283 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2284
2285 base_data = ac_to_float(&ctx->ac, src_data);
2286 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2287 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2288 data_type, "");
2289 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2290 while (writemask) {
2291 int start, count;
2292 LLVMValueRef data;
2293 LLVMValueRef offset;
2294 LLVMValueRef tmp;
2295 u_bit_scan_consecutive_range(&writemask, &start, &count);
2296
2297 /* Due to an LLVM limitation, split 3-element writes
2298 * into a 2-element and a 1-element write. */
2299 if (count == 3) {
2300 writemask |= 1 << (start + 2);
2301 count = 2;
2302 }
2303
2304 start *= elem_size_mult;
2305 count *= elem_size_mult;
2306
2307 if (count > 4) {
2308 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2309 count = 4;
2310 }
2311
2312 if (count == 4) {
2313 store_name = "llvm.amdgcn.buffer.store.v4f32";
2314 data = base_data;
2315 } else if (count == 2) {
2316 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2317 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2318 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2319 ctx->ac.i32_0, "");
2320
2321 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2322 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2323 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2324 ctx->ac.i32_1, "");
2325 store_name = "llvm.amdgcn.buffer.store.v2f32";
2326
2327 } else {
2328 assert(count == 1);
2329 if (get_llvm_num_components(base_data) > 1)
2330 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2331 LLVMConstInt(ctx->ac.i32, start, false), "");
2332 else
2333 data = base_data;
2334 store_name = "llvm.amdgcn.buffer.store.f32";
2335 }
2336
2337 offset = base_offset;
2338 if (start != 0) {
2339 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2340 }
2341 params[0] = data;
2342 params[3] = offset;
2343 ac_build_intrinsic(&ctx->ac, store_name,
2344 ctx->ac.voidt, params, 6, 0);
2345 }
2346 }
2347
2348 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2349 const nir_intrinsic_instr *instr)
2350 {
2351 const char *name;
2352 LLVMValueRef params[6];
2353 int arg_count = 0;
2354
2355 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2356 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2357 }
2358 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2359 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2360 get_src(ctx, instr->src[0]),
2361 true);
2362 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2363 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2364 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2365
2366 switch (instr->intrinsic) {
2367 case nir_intrinsic_ssbo_atomic_add:
2368 name = "llvm.amdgcn.buffer.atomic.add";
2369 break;
2370 case nir_intrinsic_ssbo_atomic_imin:
2371 name = "llvm.amdgcn.buffer.atomic.smin";
2372 break;
2373 case nir_intrinsic_ssbo_atomic_umin:
2374 name = "llvm.amdgcn.buffer.atomic.umin";
2375 break;
2376 case nir_intrinsic_ssbo_atomic_imax:
2377 name = "llvm.amdgcn.buffer.atomic.smax";
2378 break;
2379 case nir_intrinsic_ssbo_atomic_umax:
2380 name = "llvm.amdgcn.buffer.atomic.umax";
2381 break;
2382 case nir_intrinsic_ssbo_atomic_and:
2383 name = "llvm.amdgcn.buffer.atomic.and";
2384 break;
2385 case nir_intrinsic_ssbo_atomic_or:
2386 name = "llvm.amdgcn.buffer.atomic.or";
2387 break;
2388 case nir_intrinsic_ssbo_atomic_xor:
2389 name = "llvm.amdgcn.buffer.atomic.xor";
2390 break;
2391 case nir_intrinsic_ssbo_atomic_exchange:
2392 name = "llvm.amdgcn.buffer.atomic.swap";
2393 break;
2394 case nir_intrinsic_ssbo_atomic_comp_swap:
2395 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2396 break;
2397 default:
2398 abort();
2399 }
2400
2401 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2402 }
2403
2404 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2405 const nir_intrinsic_instr *instr)
2406 {
2407 LLVMValueRef results[2];
2408 int load_components;
2409 int num_components = instr->num_components;
2410 if (instr->dest.ssa.bit_size == 64)
2411 num_components *= 2;
2412
2413 for (int i = 0; i < num_components; i += load_components) {
2414 load_components = MIN2(num_components - i, 4);
2415 const char *load_name;
2416 LLVMTypeRef data_type = ctx->ac.f32;
2417 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2418 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2419
2420 if (load_components == 3)
2421 data_type = LLVMVectorType(ctx->ac.f32, 4);
2422 else if (load_components > 1)
2423 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2424
2425 if (load_components >= 3)
2426 load_name = "llvm.amdgcn.buffer.load.v4f32";
2427 else if (load_components == 2)
2428 load_name = "llvm.amdgcn.buffer.load.v2f32";
2429 else if (load_components == 1)
2430 load_name = "llvm.amdgcn.buffer.load.f32";
2431 else
2432 unreachable("unhandled number of components");
2433
2434 LLVMValueRef params[] = {
2435 ctx->abi->load_ssbo(ctx->abi,
2436 get_src(ctx, instr->src[0]),
2437 false),
2438 LLVMConstInt(ctx->ac.i32, 0, false),
2439 offset,
2440 ctx->ac.i1false,
2441 ctx->ac.i1false,
2442 };
2443
2444 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2445
2446 }
2447
2448 assume(results[0]);
2449 LLVMValueRef ret = results[0];
2450 if (num_components > 4 || num_components == 3) {
2451 LLVMValueRef masks[] = {
2452 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2453 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2454 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2455 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2456 };
2457
2458 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2459 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2460 results[num_components > 4 ? 1 : 0], swizzle, "");
2461 }
2462
2463 return LLVMBuildBitCast(ctx->ac.builder, ret,
2464 get_def_type(ctx, &instr->dest.ssa), "");
2465 }
2466
2467 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2468 const nir_intrinsic_instr *instr)
2469 {
2470 LLVMValueRef results[8], ret;
2471 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2472 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2473 int num_components = instr->num_components;
2474
2475 if (ctx->abi->load_ubo)
2476 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2477
2478 if (instr->dest.ssa.bit_size == 64)
2479 num_components *= 2;
2480
2481 for (unsigned i = 0; i < num_components; ++i) {
2482 LLVMValueRef params[] = {
2483 rsrc,
2484 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2485 offset, "")
2486 };
2487 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2488 params, 2,
2489 AC_FUNC_ATTR_READNONE |
2490 AC_FUNC_ATTR_LEGACY);
2491 }
2492
2493
2494 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2495 return LLVMBuildBitCast(ctx->ac.builder, ret,
2496 get_def_type(ctx, &instr->dest.ssa), "");
2497 }
2498
2499 static void
2500 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2501 bool vs_in, unsigned *vertex_index_out,
2502 LLVMValueRef *vertex_index_ref,
2503 unsigned *const_out, LLVMValueRef *indir_out)
2504 {
2505 unsigned const_offset = 0;
2506 nir_deref *tail = &deref->deref;
2507 LLVMValueRef offset = NULL;
2508
2509 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2510 tail = tail->child;
2511 nir_deref_array *deref_array = nir_deref_as_array(tail);
2512 if (vertex_index_out)
2513 *vertex_index_out = deref_array->base_offset;
2514
2515 if (vertex_index_ref) {
2516 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2517 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2518 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2519 }
2520 *vertex_index_ref = vtx;
2521 }
2522 }
2523
2524 if (deref->var->data.compact) {
2525 assert(tail->child->deref_type == nir_deref_type_array);
2526 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2527 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2528 /* We always lower indirect dereferences for "compact" array vars. */
2529 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2530
2531 const_offset = deref_array->base_offset;
2532 goto out;
2533 }
2534
2535 while (tail->child != NULL) {
2536 const struct glsl_type *parent_type = tail->type;
2537 tail = tail->child;
2538
2539 if (tail->deref_type == nir_deref_type_array) {
2540 nir_deref_array *deref_array = nir_deref_as_array(tail);
2541 LLVMValueRef index, stride, local_offset;
2542 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2543
2544 const_offset += size * deref_array->base_offset;
2545 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2546 continue;
2547
2548 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2549 index = get_src(ctx, deref_array->indirect);
2550 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2551 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2552
2553 if (offset)
2554 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2555 else
2556 offset = local_offset;
2557 } else if (tail->deref_type == nir_deref_type_struct) {
2558 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2559
2560 for (unsigned i = 0; i < deref_struct->index; i++) {
2561 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2562 const_offset += glsl_count_attribute_slots(ft, vs_in);
2563 }
2564 } else
2565 unreachable("unsupported deref type");
2566
2567 }
2568 out:
2569 if (const_offset && offset)
2570 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2571 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2572 "");
2573
2574 *const_out = const_offset;
2575 *indir_out = offset;
2576 }
2577
2578
2579 /* The offchip buffer layout for TCS->TES is
2580 *
2581 * - attribute 0 of patch 0 vertex 0
2582 * - attribute 0 of patch 0 vertex 1
2583 * - attribute 0 of patch 0 vertex 2
2584 * ...
2585 * - attribute 0 of patch 1 vertex 0
2586 * - attribute 0 of patch 1 vertex 1
2587 * ...
2588 * - attribute 1 of patch 0 vertex 0
2589 * - attribute 1 of patch 0 vertex 1
2590 * ...
2591 * - per patch attribute 0 of patch 0
2592 * - per patch attribute 0 of patch 1
2593 * ...
2594 *
2595 * Note that every attribute has 4 components.
2596 */
2597 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2598 LLVMValueRef vertex_index,
2599 LLVMValueRef param_index)
2600 {
2601 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2602 LLVMValueRef param_stride, constant16;
2603 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2604
2605 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2606 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2607 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2608 num_patches, "");
2609
2610 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2611 if (vertex_index) {
2612 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2613 vertices_per_patch, "");
2614
2615 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2616 vertex_index, "");
2617
2618 param_stride = total_vertices;
2619 } else {
2620 base_addr = rel_patch_id;
2621 param_stride = num_patches;
2622 }
2623
2624 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2625 LLVMBuildMul(ctx->builder, param_index,
2626 param_stride, ""), "");
2627
2628 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2629
2630 if (!vertex_index) {
2631 LLVMValueRef patch_data_offset =
2632 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2633
2634 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2635 patch_data_offset, "");
2636 }
2637 return base_addr;
2638 }
2639
2640 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2641 unsigned param,
2642 unsigned const_index,
2643 bool is_compact,
2644 LLVMValueRef vertex_index,
2645 LLVMValueRef indir_index)
2646 {
2647 LLVMValueRef param_index;
2648
2649 if (indir_index)
2650 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2651 indir_index, "");
2652 else {
2653 if (const_index && !is_compact)
2654 param += const_index;
2655 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2656 }
2657 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2658 }
2659
2660 static void
2661 mark_tess_output(struct nir_to_llvm_context *ctx,
2662 bool is_patch, uint32_t param)
2663
2664 {
2665 if (is_patch) {
2666 ctx->tess_patch_outputs_written |= (1ull << param);
2667 } else
2668 ctx->tess_outputs_written |= (1ull << param);
2669 }
2670
2671 static LLVMValueRef
2672 get_dw_address(struct nir_to_llvm_context *ctx,
2673 LLVMValueRef dw_addr,
2674 unsigned param,
2675 unsigned const_index,
2676 bool compact_const_index,
2677 LLVMValueRef vertex_index,
2678 LLVMValueRef stride,
2679 LLVMValueRef indir_index)
2680
2681 {
2682
2683 if (vertex_index) {
2684 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2685 LLVMBuildMul(ctx->builder,
2686 vertex_index,
2687 stride, ""), "");
2688 }
2689
2690 if (indir_index)
2691 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2692 LLVMBuildMul(ctx->builder, indir_index,
2693 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2694 else if (const_index && !compact_const_index)
2695 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2696 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2697
2698 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2699 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2700
2701 if (const_index && compact_const_index)
2702 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2703 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2704 return dw_addr;
2705 }
2706
2707 static LLVMValueRef
2708 build_varying_gather_values(struct ac_llvm_context *ctx, LLVMValueRef *values,
2709 unsigned value_count, unsigned component)
2710 {
2711 LLVMValueRef vec = NULL;
2712
2713 if (value_count == 1) {
2714 return values[component];
2715 } else if (!value_count)
2716 unreachable("value_count is 0");
2717
2718 for (unsigned i = component; i < value_count + component; i++) {
2719 LLVMValueRef value = values[i];
2720
2721 if (!i)
2722 vec = LLVMGetUndef( LLVMVectorType(LLVMTypeOf(value), value_count));
2723 LLVMValueRef index = LLVMConstInt(ctx->i32, i - component, false);
2724 vec = LLVMBuildInsertElement(ctx->builder, vec, value, index, "");
2725 }
2726 return vec;
2727 }
2728
2729 static LLVMValueRef
2730 load_tcs_input(struct nir_to_llvm_context *ctx,
2731 nir_intrinsic_instr *instr)
2732 {
2733 LLVMValueRef dw_addr, stride;
2734 unsigned const_index;
2735 LLVMValueRef vertex_index;
2736 LLVMValueRef indir_index;
2737 unsigned param;
2738 LLVMValueRef value[4], result;
2739 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2740 const bool is_compact = instr->variables[0]->var->data.compact;
2741 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2742 get_deref_offset(ctx->nir, instr->variables[0],
2743 false, NULL, per_vertex ? &vertex_index : NULL,
2744 &const_index, &indir_index);
2745
2746 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2747 dw_addr = get_tcs_in_current_patch_offset(ctx);
2748 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2749 indir_index);
2750
2751 unsigned comp = instr->variables[0]->var->data.location_frac;
2752 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2753 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2754 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2755 ctx->ac.i32_1, "");
2756 }
2757 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2758 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2759 return result;
2760 }
2761
2762 static LLVMValueRef
2763 load_tcs_output(struct nir_to_llvm_context *ctx,
2764 nir_intrinsic_instr *instr)
2765 {
2766 LLVMValueRef dw_addr;
2767 LLVMValueRef stride = NULL;
2768 LLVMValueRef value[4], result;
2769 LLVMValueRef vertex_index = NULL;
2770 LLVMValueRef indir_index = NULL;
2771 unsigned const_index = 0;
2772 unsigned param;
2773 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2774 const bool is_compact = instr->variables[0]->var->data.compact;
2775 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2776 get_deref_offset(ctx->nir, instr->variables[0],
2777 false, NULL, per_vertex ? &vertex_index : NULL,
2778 &const_index, &indir_index);
2779
2780 if (!instr->variables[0]->var->data.patch) {
2781 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2782 dw_addr = get_tcs_out_current_patch_offset(ctx);
2783 } else {
2784 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2785 }
2786
2787 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2788 indir_index);
2789
2790 unsigned comp = instr->variables[0]->var->data.location_frac;
2791 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2792 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2793 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2794 ctx->ac.i32_1, "");
2795 }
2796 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2797 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2798 return result;
2799 }
2800
2801 static void
2802 store_tcs_output(struct nir_to_llvm_context *ctx,
2803 nir_intrinsic_instr *instr,
2804 LLVMValueRef src,
2805 unsigned writemask)
2806 {
2807 LLVMValueRef dw_addr;
2808 LLVMValueRef stride = NULL;
2809 LLVMValueRef buf_addr = NULL;
2810 LLVMValueRef vertex_index = NULL;
2811 LLVMValueRef indir_index = NULL;
2812 unsigned const_index = 0;
2813 unsigned param;
2814 const unsigned comp = instr->variables[0]->var->data.location_frac;
2815 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2816 const bool is_compact = instr->variables[0]->var->data.compact;
2817 bool store_lds = true;
2818
2819 if (instr->variables[0]->var->data.patch) {
2820 if (!(ctx->tcs_patch_outputs_read & (1U << instr->variables[0]->var->data.location)))
2821 store_lds = false;
2822 } else {
2823 if (!(ctx->tcs_outputs_read & (1ULL << instr->variables[0]->var->data.location)))
2824 store_lds = false;
2825 }
2826 get_deref_offset(ctx->nir, instr->variables[0],
2827 false, NULL, per_vertex ? &vertex_index : NULL,
2828 &const_index, &indir_index);
2829
2830 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2831 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2832 is_compact && const_index > 3) {
2833 const_index -= 3;
2834 param++;
2835 }
2836
2837 if (!instr->variables[0]->var->data.patch) {
2838 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2839 dw_addr = get_tcs_out_current_patch_offset(ctx);
2840 } else {
2841 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2842 }
2843
2844 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2845
2846 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2847 indir_index);
2848 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2849 vertex_index, indir_index);
2850
2851 bool is_tess_factor = false;
2852 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2853 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2854 is_tess_factor = true;
2855
2856 unsigned base = is_compact ? const_index : 0;
2857 for (unsigned chan = 0; chan < 8; chan++) {
2858 if (!(writemask & (1 << chan)))
2859 continue;
2860 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2861
2862 if (store_lds || is_tess_factor)
2863 ac_lds_store(&ctx->ac, dw_addr, value);
2864
2865 if (!is_tess_factor && writemask != 0xF)
2866 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2867 buf_addr, ctx->oc_lds,
2868 4 * (base + chan), 1, 0, true, false);
2869
2870 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2871 ctx->ac.i32_1, "");
2872 }
2873
2874 if (writemask == 0xF) {
2875 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2876 buf_addr, ctx->oc_lds,
2877 (base * 4), 1, 0, true, false);
2878 }
2879 }
2880
2881 static LLVMValueRef
2882 load_tes_input(struct nir_to_llvm_context *ctx,
2883 const nir_intrinsic_instr *instr)
2884 {
2885 LLVMValueRef buf_addr;
2886 LLVMValueRef result;
2887 LLVMValueRef vertex_index = NULL;
2888 LLVMValueRef indir_index = NULL;
2889 unsigned const_index = 0;
2890 unsigned param;
2891 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2892 const bool is_compact = instr->variables[0]->var->data.compact;
2893
2894 get_deref_offset(ctx->nir, instr->variables[0],
2895 false, NULL, per_vertex ? &vertex_index : NULL,
2896 &const_index, &indir_index);
2897 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2898 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2899 is_compact && const_index > 3) {
2900 const_index -= 3;
2901 param++;
2902 }
2903
2904 unsigned comp = instr->variables[0]->var->data.location_frac;
2905 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2906 is_compact, vertex_index, indir_index);
2907
2908 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, comp * 4, false);
2909 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2910
2911 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2912 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2913 result = trim_vector(&ctx->ac, result, instr->num_components);
2914 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2915 return result;
2916 }
2917
2918 static LLVMValueRef
2919 load_gs_input(struct nir_to_llvm_context *ctx,
2920 nir_intrinsic_instr *instr)
2921 {
2922 LLVMValueRef indir_index, vtx_offset;
2923 unsigned const_index;
2924 LLVMValueRef args[9];
2925 unsigned param, vtx_offset_param;
2926 LLVMValueRef value[4], result;
2927 unsigned vertex_index;
2928 get_deref_offset(ctx->nir, instr->variables[0],
2929 false, &vertex_index, NULL,
2930 &const_index, &indir_index);
2931 vtx_offset_param = vertex_index;
2932 assert(vtx_offset_param < 6);
2933 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2934 LLVMConstInt(ctx->ac.i32, 4, false), "");
2935
2936 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2937
2938 unsigned comp = instr->variables[0]->var->data.location_frac;
2939 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2940 if (ctx->ac.chip_class >= GFX9) {
2941 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
2942 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2943 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
2944 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2945 } else {
2946 args[0] = ctx->esgs_ring;
2947 args[1] = vtx_offset;
2948 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
2949 args[3] = ctx->ac.i32_0;
2950 args[4] = ctx->ac.i32_1; /* OFFEN */
2951 args[5] = ctx->ac.i32_0; /* IDXEN */
2952 args[6] = ctx->ac.i32_1; /* GLC */
2953 args[7] = ctx->ac.i32_0; /* SLC */
2954 args[8] = ctx->ac.i32_0; /* TFE */
2955
2956 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2957 ctx->ac.i32, args, 9,
2958 AC_FUNC_ATTR_READONLY |
2959 AC_FUNC_ATTR_LEGACY);
2960 }
2961 }
2962 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2963
2964 return result;
2965 }
2966
2967 static LLVMValueRef
2968 build_gep_for_deref(struct ac_nir_context *ctx,
2969 nir_deref_var *deref)
2970 {
2971 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2972 assert(entry->data);
2973 LLVMValueRef val = entry->data;
2974 nir_deref *tail = deref->deref.child;
2975 while (tail != NULL) {
2976 LLVMValueRef offset;
2977 switch (tail->deref_type) {
2978 case nir_deref_type_array: {
2979 nir_deref_array *array = nir_deref_as_array(tail);
2980 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2981 if (array->deref_array_type ==
2982 nir_deref_array_type_indirect) {
2983 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2984 get_src(ctx,
2985 array->indirect),
2986 "");
2987 }
2988 break;
2989 }
2990 case nir_deref_type_struct: {
2991 nir_deref_struct *deref_struct =
2992 nir_deref_as_struct(tail);
2993 offset = LLVMConstInt(ctx->ac.i32,
2994 deref_struct->index, 0);
2995 break;
2996 }
2997 default:
2998 unreachable("bad deref type");
2999 }
3000 val = ac_build_gep0(&ctx->ac, val, offset);
3001 tail = tail->child;
3002 }
3003 return val;
3004 }
3005
3006 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3007 nir_intrinsic_instr *instr)
3008 {
3009 LLVMValueRef values[8];
3010 int idx = instr->variables[0]->var->data.driver_location;
3011 int ve = instr->dest.ssa.num_components;
3012 unsigned comp = instr->variables[0]->var->data.location_frac;
3013 LLVMValueRef indir_index;
3014 LLVMValueRef ret;
3015 unsigned const_index;
3016 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3017 instr->variables[0]->var->data.mode == nir_var_shader_in;
3018 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3019 &const_index, &indir_index);
3020
3021 if (instr->dest.ssa.bit_size == 64)
3022 ve *= 2;
3023
3024 switch (instr->variables[0]->var->data.mode) {
3025 case nir_var_shader_in:
3026 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3027 return load_tcs_input(ctx->nctx, instr);
3028 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3029 return load_tes_input(ctx->nctx, instr);
3030 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3031 return load_gs_input(ctx->nctx, instr);
3032 }
3033
3034 for (unsigned chan = comp; chan < ve + comp; chan++) {
3035 if (indir_index) {
3036 unsigned count = glsl_count_attribute_slots(
3037 instr->variables[0]->var->type,
3038 ctx->stage == MESA_SHADER_VERTEX);
3039 count -= chan / 4;
3040 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3041 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3042 4, false, true);
3043
3044 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3045 tmp_vec,
3046 indir_index, "");
3047 } else
3048 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3049 }
3050 break;
3051 case nir_var_local:
3052 for (unsigned chan = 0; chan < ve; chan++) {
3053 if (indir_index) {
3054 unsigned count = glsl_count_attribute_slots(
3055 instr->variables[0]->var->type, false);
3056 count -= chan / 4;
3057 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3058 &ctx->ac, ctx->locals + idx + chan, count,
3059 4, true, true);
3060
3061 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3062 tmp_vec,
3063 indir_index, "");
3064 } else {
3065 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3066 }
3067 }
3068 break;
3069 case nir_var_shared: {
3070 LLVMValueRef address = build_gep_for_deref(ctx,
3071 instr->variables[0]);
3072 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3073 return LLVMBuildBitCast(ctx->ac.builder, val,
3074 get_def_type(ctx, &instr->dest.ssa),
3075 "");
3076 }
3077 case nir_var_shader_out:
3078 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3079 return load_tcs_output(ctx->nctx, instr);
3080
3081 for (unsigned chan = comp; chan < ve + comp; chan++) {
3082 if (indir_index) {
3083 unsigned count = glsl_count_attribute_slots(
3084 instr->variables[0]->var->type, false);
3085 count -= chan / 4;
3086 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3087 &ctx->ac, ctx->outputs + idx + chan, count,
3088 4, true, true);
3089
3090 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3091 tmp_vec,
3092 indir_index, "");
3093 } else {
3094 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3095 ctx->outputs[idx + chan + const_index * 4],
3096 "");
3097 }
3098 }
3099 break;
3100 default:
3101 unreachable("unhandle variable mode");
3102 }
3103 ret = build_varying_gather_values(&ctx->ac, values, ve, comp);
3104 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3105 }
3106
3107 static void
3108 visit_store_var(struct ac_nir_context *ctx,
3109 nir_intrinsic_instr *instr)
3110 {
3111 LLVMValueRef temp_ptr, value;
3112 int idx = instr->variables[0]->var->data.driver_location;
3113 unsigned comp = instr->variables[0]->var->data.location_frac;
3114 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3115 int writemask = instr->const_index[0] << comp;
3116 LLVMValueRef indir_index;
3117 unsigned const_index;
3118 get_deref_offset(ctx, instr->variables[0], false,
3119 NULL, NULL, &const_index, &indir_index);
3120
3121 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3122 int old_writemask = writemask;
3123
3124 src = LLVMBuildBitCast(ctx->ac.builder, src,
3125 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3126 "");
3127
3128 writemask = 0;
3129 for (unsigned chan = 0; chan < 4; chan++) {
3130 if (old_writemask & (1 << chan))
3131 writemask |= 3u << (2 * chan);
3132 }
3133 }
3134
3135 switch (instr->variables[0]->var->data.mode) {
3136 case nir_var_shader_out:
3137
3138 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3139 store_tcs_output(ctx->nctx, instr, src, writemask);
3140 return;
3141 }
3142
3143 for (unsigned chan = 0; chan < 8; chan++) {
3144 int stride = 4;
3145 if (!(writemask & (1 << chan)))
3146 continue;
3147
3148 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3149
3150 if (instr->variables[0]->var->data.compact)
3151 stride = 1;
3152 if (indir_index) {
3153 unsigned count = glsl_count_attribute_slots(
3154 instr->variables[0]->var->type, false);
3155 count -= chan / 4;
3156 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3157 &ctx->ac, ctx->outputs + idx + chan, count,
3158 stride, true, true);
3159
3160 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3161 value, indir_index, "");
3162 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3163 count, stride, tmp_vec);
3164
3165 } else {
3166 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3167
3168 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3169 }
3170 }
3171 break;
3172 case nir_var_local:
3173 for (unsigned chan = 0; chan < 8; chan++) {
3174 if (!(writemask & (1 << chan)))
3175 continue;
3176
3177 value = llvm_extract_elem(&ctx->ac, src, chan);
3178 if (indir_index) {
3179 unsigned count = glsl_count_attribute_slots(
3180 instr->variables[0]->var->type, false);
3181 count -= chan / 4;
3182 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3183 &ctx->ac, ctx->locals + idx + chan, count,
3184 4, true, true);
3185
3186 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3187 value, indir_index, "");
3188 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3189 count, 4, tmp_vec);
3190 } else {
3191 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3192
3193 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3194 }
3195 }
3196 break;
3197 case nir_var_shared: {
3198 int writemask = instr->const_index[0];
3199 LLVMValueRef address = build_gep_for_deref(ctx,
3200 instr->variables[0]);
3201 LLVMValueRef val = get_src(ctx, instr->src[0]);
3202 unsigned components =
3203 glsl_get_vector_elements(
3204 nir_deref_tail(&instr->variables[0]->deref)->type);
3205 if (writemask == (1 << components) - 1) {
3206 val = LLVMBuildBitCast(
3207 ctx->ac.builder, val,
3208 LLVMGetElementType(LLVMTypeOf(address)), "");
3209 LLVMBuildStore(ctx->ac.builder, val, address);
3210 } else {
3211 for (unsigned chan = 0; chan < 4; chan++) {
3212 if (!(writemask & (1 << chan)))
3213 continue;
3214 LLVMValueRef ptr =
3215 LLVMBuildStructGEP(ctx->ac.builder,
3216 address, chan, "");
3217 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3218 chan);
3219 src = LLVMBuildBitCast(
3220 ctx->ac.builder, src,
3221 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3222 LLVMBuildStore(ctx->ac.builder, src, ptr);
3223 }
3224 }
3225 break;
3226 }
3227 default:
3228 break;
3229 }
3230 }
3231
3232 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3233 {
3234 switch (dim) {
3235 case GLSL_SAMPLER_DIM_BUF:
3236 return 1;
3237 case GLSL_SAMPLER_DIM_1D:
3238 return array ? 2 : 1;
3239 case GLSL_SAMPLER_DIM_2D:
3240 return array ? 3 : 2;
3241 case GLSL_SAMPLER_DIM_MS:
3242 return array ? 4 : 3;
3243 case GLSL_SAMPLER_DIM_3D:
3244 case GLSL_SAMPLER_DIM_CUBE:
3245 return 3;
3246 case GLSL_SAMPLER_DIM_RECT:
3247 case GLSL_SAMPLER_DIM_SUBPASS:
3248 return 2;
3249 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3250 return 3;
3251 default:
3252 break;
3253 }
3254 return 0;
3255 }
3256
3257
3258
3259 /* Adjust the sample index according to FMASK.
3260 *
3261 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3262 * which is the identity mapping. Each nibble says which physical sample
3263 * should be fetched to get that sample.
3264 *
3265 * For example, 0x11111100 means there are only 2 samples stored and
3266 * the second sample covers 3/4 of the pixel. When reading samples 0
3267 * and 1, return physical sample 0 (determined by the first two 0s
3268 * in FMASK), otherwise return physical sample 1.
3269 *
3270 * The sample index should be adjusted as follows:
3271 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3272 */
3273 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3274 LLVMValueRef coord_x, LLVMValueRef coord_y,
3275 LLVMValueRef coord_z,
3276 LLVMValueRef sample_index,
3277 LLVMValueRef fmask_desc_ptr)
3278 {
3279 LLVMValueRef fmask_load_address[4];
3280 LLVMValueRef res;
3281
3282 fmask_load_address[0] = coord_x;
3283 fmask_load_address[1] = coord_y;
3284 if (coord_z) {
3285 fmask_load_address[2] = coord_z;
3286 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3287 }
3288
3289 struct ac_image_args args = {0};
3290
3291 args.opcode = ac_image_load;
3292 args.da = coord_z ? true : false;
3293 args.resource = fmask_desc_ptr;
3294 args.dmask = 0xf;
3295 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3296
3297 res = ac_build_image_opcode(ctx, &args);
3298
3299 res = ac_to_integer(ctx, res);
3300 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3301 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3302
3303 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3304 res,
3305 ctx->i32_0, "");
3306
3307 LLVMValueRef sample_index4 =
3308 LLVMBuildMul(ctx->builder, sample_index, four, "");
3309 LLVMValueRef shifted_fmask =
3310 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3311 LLVMValueRef final_sample =
3312 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3313
3314 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3315 * resource descriptor is 0 (invalid),
3316 */
3317 LLVMValueRef fmask_desc =
3318 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3319 ctx->v8i32, "");
3320
3321 LLVMValueRef fmask_word1 =
3322 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3323 ctx->i32_1, "");
3324
3325 LLVMValueRef word1_is_nonzero =
3326 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3327 fmask_word1, ctx->i32_0, "");
3328
3329 /* Replace the MSAA sample index. */
3330 sample_index =
3331 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3332 final_sample, sample_index, "");
3333 return sample_index;
3334 }
3335
3336 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3337 const nir_intrinsic_instr *instr)
3338 {
3339 const struct glsl_type *type = instr->variables[0]->var->type;
3340 if(instr->variables[0]->deref.child)
3341 type = instr->variables[0]->deref.child->type;
3342
3343 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3344 LLVMValueRef coords[4];
3345 LLVMValueRef masks[] = {
3346 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3347 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3348 };
3349 LLVMValueRef res;
3350 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3351
3352 int count;
3353 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3354 bool is_array = glsl_sampler_type_is_array(type);
3355 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3356 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3357 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3358 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3359 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3360 count = image_type_to_components_count(dim, is_array);
3361
3362 if (is_ms) {
3363 LLVMValueRef fmask_load_address[3];
3364 int chan;
3365
3366 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3367 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3368 if (is_array)
3369 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3370 else
3371 fmask_load_address[2] = NULL;
3372 if (add_frag_pos) {
3373 for (chan = 0; chan < 2; ++chan)
3374 fmask_load_address[chan] =
3375 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3376 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3377 ctx->ac.i32, ""), "");
3378 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3379 }
3380 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3381 fmask_load_address[0],
3382 fmask_load_address[1],
3383 fmask_load_address[2],
3384 sample_index,
3385 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3386 }
3387 if (count == 1 && !gfx9_1d) {
3388 if (instr->src[0].ssa->num_components)
3389 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3390 else
3391 res = src0;
3392 } else {
3393 int chan;
3394 if (is_ms)
3395 count--;
3396 for (chan = 0; chan < count; ++chan) {
3397 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3398 }
3399 if (add_frag_pos) {
3400 for (chan = 0; chan < 2; ++chan)
3401 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3402 ctx->ac.i32, ""), "");
3403 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3404 count++;
3405 }
3406
3407 if (gfx9_1d) {
3408 if (is_array) {
3409 coords[2] = coords[1];
3410 coords[1] = ctx->ac.i32_0;
3411 } else
3412 coords[1] = ctx->ac.i32_0;
3413 count++;
3414 }
3415
3416 if (is_ms) {
3417 coords[count] = sample_index;
3418 count++;
3419 }
3420
3421 if (count == 3) {
3422 coords[3] = LLVMGetUndef(ctx->ac.i32);
3423 count = 4;
3424 }
3425 res = ac_build_gather_values(&ctx->ac, coords, count);
3426 }
3427 return res;
3428 }
3429
3430 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3431 const nir_intrinsic_instr *instr)
3432 {
3433 LLVMValueRef params[7];
3434 LLVMValueRef res;
3435 char intrinsic_name[64];
3436 const nir_variable *var = instr->variables[0]->var;
3437 const struct glsl_type *type = var->type;
3438
3439 if(instr->variables[0]->deref.child)
3440 type = instr->variables[0]->deref.child->type;
3441
3442 type = glsl_without_array(type);
3443 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3444 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3445 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3446 ctx->ac.i32_0, ""); /* vindex */
3447 params[2] = ctx->ac.i32_0; /* voffset */
3448 params[3] = ctx->ac.i1false; /* glc */
3449 params[4] = ctx->ac.i1false; /* slc */
3450 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3451 params, 5, 0);
3452
3453 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3454 res = ac_to_integer(&ctx->ac, res);
3455 } else {
3456 bool is_da = glsl_sampler_type_is_array(type) ||
3457 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3458 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3459 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3460 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3461 LLVMValueRef glc = ctx->ac.i1false;
3462 LLVMValueRef slc = ctx->ac.i1false;
3463
3464 params[0] = get_image_coords(ctx, instr);
3465 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3466 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3467 if (HAVE_LLVM <= 0x0309) {
3468 params[3] = ctx->ac.i1false; /* r128 */
3469 params[4] = da;
3470 params[5] = glc;
3471 params[6] = slc;
3472 } else {
3473 LLVMValueRef lwe = ctx->ac.i1false;
3474 params[3] = glc;
3475 params[4] = slc;
3476 params[5] = lwe;
3477 params[6] = da;
3478 }
3479
3480 ac_get_image_intr_name("llvm.amdgcn.image.load",
3481 ctx->ac.v4f32, /* vdata */
3482 LLVMTypeOf(params[0]), /* coords */
3483 LLVMTypeOf(params[1]), /* rsrc */
3484 intrinsic_name, sizeof(intrinsic_name));
3485
3486 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3487 params, 7, AC_FUNC_ATTR_READONLY);
3488 }
3489 return ac_to_integer(&ctx->ac, res);
3490 }
3491
3492 static void visit_image_store(struct ac_nir_context *ctx,
3493 nir_intrinsic_instr *instr)
3494 {
3495 LLVMValueRef params[8];
3496 char intrinsic_name[64];
3497 const nir_variable *var = instr->variables[0]->var;
3498 const struct glsl_type *type = glsl_without_array(var->type);
3499 LLVMValueRef glc = ctx->ac.i1false;
3500 bool force_glc = ctx->ac.chip_class == SI;
3501 if (force_glc)
3502 glc = ctx->ac.i1true;
3503
3504 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3505 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3506 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3507 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3508 ctx->ac.i32_0, ""); /* vindex */
3509 params[3] = ctx->ac.i32_0; /* voffset */
3510 params[4] = glc; /* glc */
3511 params[5] = ctx->ac.i1false; /* slc */
3512 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3513 params, 6, 0);
3514 } else {
3515 bool is_da = glsl_sampler_type_is_array(type) ||
3516 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3517 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3518 LLVMValueRef slc = ctx->ac.i1false;
3519
3520 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3521 params[1] = get_image_coords(ctx, instr); /* coords */
3522 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3523 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3524 if (HAVE_LLVM <= 0x0309) {
3525 params[4] = ctx->ac.i1false; /* r128 */
3526 params[5] = da;
3527 params[6] = glc;
3528 params[7] = slc;
3529 } else {
3530 LLVMValueRef lwe = ctx->ac.i1false;
3531 params[4] = glc;
3532 params[5] = slc;
3533 params[6] = lwe;
3534 params[7] = da;
3535 }
3536
3537 ac_get_image_intr_name("llvm.amdgcn.image.store",
3538 LLVMTypeOf(params[0]), /* vdata */
3539 LLVMTypeOf(params[1]), /* coords */
3540 LLVMTypeOf(params[2]), /* rsrc */
3541 intrinsic_name, sizeof(intrinsic_name));
3542
3543 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3544 params, 8, 0);
3545 }
3546
3547 }
3548
3549 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3550 const nir_intrinsic_instr *instr)
3551 {
3552 LLVMValueRef params[7];
3553 int param_count = 0;
3554 const nir_variable *var = instr->variables[0]->var;
3555
3556 const char *atomic_name;
3557 char intrinsic_name[41];
3558 const struct glsl_type *type = glsl_without_array(var->type);
3559 MAYBE_UNUSED int length;
3560
3561 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3562
3563 switch (instr->intrinsic) {
3564 case nir_intrinsic_image_atomic_add:
3565 atomic_name = "add";
3566 break;
3567 case nir_intrinsic_image_atomic_min:
3568 atomic_name = is_unsigned ? "umin" : "smin";
3569 break;
3570 case nir_intrinsic_image_atomic_max:
3571 atomic_name = is_unsigned ? "umax" : "smax";
3572 break;
3573 case nir_intrinsic_image_atomic_and:
3574 atomic_name = "and";
3575 break;
3576 case nir_intrinsic_image_atomic_or:
3577 atomic_name = "or";
3578 break;
3579 case nir_intrinsic_image_atomic_xor:
3580 atomic_name = "xor";
3581 break;
3582 case nir_intrinsic_image_atomic_exchange:
3583 atomic_name = "swap";
3584 break;
3585 case nir_intrinsic_image_atomic_comp_swap:
3586 atomic_name = "cmpswap";
3587 break;
3588 default:
3589 abort();
3590 }
3591
3592 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3593 params[param_count++] = get_src(ctx, instr->src[3]);
3594 params[param_count++] = get_src(ctx, instr->src[2]);
3595
3596 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3597 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3598 NULL, true, true);
3599 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3600 ctx->ac.i32_0, ""); /* vindex */
3601 params[param_count++] = ctx->ac.i32_0; /* voffset */
3602 params[param_count++] = ctx->ac.i1false; /* slc */
3603
3604 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3605 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3606 } else {
3607 char coords_type[8];
3608
3609 bool da = glsl_sampler_type_is_array(type) ||
3610 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3611
3612 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3613 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3614 NULL, true, true);
3615 params[param_count++] = ctx->ac.i1false; /* r128 */
3616 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3617 params[param_count++] = ctx->ac.i1false; /* slc */
3618
3619 build_int_type_name(LLVMTypeOf(coords),
3620 coords_type, sizeof(coords_type));
3621
3622 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3623 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3624 }
3625
3626 assert(length < sizeof(intrinsic_name));
3627 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3628 }
3629
3630 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3631 const nir_intrinsic_instr *instr)
3632 {
3633 LLVMValueRef res;
3634 const nir_variable *var = instr->variables[0]->var;
3635 const struct glsl_type *type = instr->variables[0]->var->type;
3636 bool da = glsl_sampler_type_is_array(var->type) ||
3637 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3638 if(instr->variables[0]->deref.child)
3639 type = instr->variables[0]->deref.child->type;
3640
3641 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3642 return get_buffer_size(ctx,
3643 get_sampler_desc(ctx, instr->variables[0],
3644 AC_DESC_BUFFER, NULL, true, false), true);
3645
3646 struct ac_image_args args = { 0 };
3647
3648 args.da = da;
3649 args.dmask = 0xf;
3650 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3651 args.opcode = ac_image_get_resinfo;
3652 args.addr = ctx->ac.i32_0;
3653
3654 res = ac_build_image_opcode(&ctx->ac, &args);
3655
3656 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3657
3658 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3659 glsl_sampler_type_is_array(type)) {
3660 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3661 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3662 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3663 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3664 }
3665 if (ctx->ac.chip_class >= GFX9 &&
3666 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3667 glsl_sampler_type_is_array(type)) {
3668 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3669 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3670 ctx->ac.i32_1, "");
3671
3672 }
3673 return res;
3674 }
3675
3676 #define NOOP_WAITCNT 0xf7f
3677 #define LGKM_CNT 0x07f
3678 #define VM_CNT 0xf70
3679
3680 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3681 unsigned simm16)
3682 {
3683 LLVMValueRef args[1] = {
3684 LLVMConstInt(ctx->ac.i32, simm16, false),
3685 };
3686 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3687 ctx->ac.voidt, args, 1, 0);
3688 }
3689
3690 static void emit_membar(struct nir_to_llvm_context *ctx,
3691 const nir_intrinsic_instr *instr)
3692 {
3693 unsigned waitcnt = NOOP_WAITCNT;
3694
3695 switch (instr->intrinsic) {
3696 case nir_intrinsic_memory_barrier:
3697 case nir_intrinsic_group_memory_barrier:
3698 waitcnt &= VM_CNT & LGKM_CNT;
3699 break;
3700 case nir_intrinsic_memory_barrier_atomic_counter:
3701 case nir_intrinsic_memory_barrier_buffer:
3702 case nir_intrinsic_memory_barrier_image:
3703 waitcnt &= VM_CNT;
3704 break;
3705 case nir_intrinsic_memory_barrier_shared:
3706 waitcnt &= LGKM_CNT;
3707 break;
3708 default:
3709 break;
3710 }
3711 if (waitcnt != NOOP_WAITCNT)
3712 emit_waitcnt(ctx, waitcnt);
3713 }
3714
3715 static void emit_barrier(struct nir_to_llvm_context *ctx)
3716 {
3717 /* SI only (thanks to a hw bug workaround):
3718 * The real barrier instruction isn’t needed, because an entire patch
3719 * always fits into a single wave.
3720 */
3721 if (ctx->options->chip_class == SI &&
3722 ctx->stage == MESA_SHADER_TESS_CTRL) {
3723 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3724 return;
3725 }
3726 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3727 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3728 }
3729
3730 static void emit_discard_if(struct ac_nir_context *ctx,
3731 const nir_intrinsic_instr *instr)
3732 {
3733 LLVMValueRef cond;
3734
3735 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3736 get_src(ctx, instr->src[0]),
3737 ctx->ac.i32_0, "");
3738 ac_build_kill_if_false(&ctx->ac, cond);
3739 }
3740
3741 static LLVMValueRef
3742 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3743 {
3744 LLVMValueRef result;
3745 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3746 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3747 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3748
3749 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3750 }
3751
3752 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3753 const nir_intrinsic_instr *instr)
3754 {
3755 LLVMValueRef ptr, result;
3756 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3757 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3758
3759 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3760 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3761 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3762 ptr, src, src1,
3763 LLVMAtomicOrderingSequentiallyConsistent,
3764 LLVMAtomicOrderingSequentiallyConsistent,
3765 false);
3766 } else {
3767 LLVMAtomicRMWBinOp op;
3768 switch (instr->intrinsic) {
3769 case nir_intrinsic_var_atomic_add:
3770 op = LLVMAtomicRMWBinOpAdd;
3771 break;
3772 case nir_intrinsic_var_atomic_umin:
3773 op = LLVMAtomicRMWBinOpUMin;
3774 break;
3775 case nir_intrinsic_var_atomic_umax:
3776 op = LLVMAtomicRMWBinOpUMax;
3777 break;
3778 case nir_intrinsic_var_atomic_imin:
3779 op = LLVMAtomicRMWBinOpMin;
3780 break;
3781 case nir_intrinsic_var_atomic_imax:
3782 op = LLVMAtomicRMWBinOpMax;
3783 break;
3784 case nir_intrinsic_var_atomic_and:
3785 op = LLVMAtomicRMWBinOpAnd;
3786 break;
3787 case nir_intrinsic_var_atomic_or:
3788 op = LLVMAtomicRMWBinOpOr;
3789 break;
3790 case nir_intrinsic_var_atomic_xor:
3791 op = LLVMAtomicRMWBinOpXor;
3792 break;
3793 case nir_intrinsic_var_atomic_exchange:
3794 op = LLVMAtomicRMWBinOpXchg;
3795 break;
3796 default:
3797 return NULL;
3798 }
3799
3800 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3801 LLVMAtomicOrderingSequentiallyConsistent,
3802 false);
3803 }
3804 return result;
3805 }
3806
3807 #define INTERP_CENTER 0
3808 #define INTERP_CENTROID 1
3809 #define INTERP_SAMPLE 2
3810
3811 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3812 enum glsl_interp_mode interp, unsigned location)
3813 {
3814 switch (interp) {
3815 case INTERP_MODE_FLAT:
3816 default:
3817 return NULL;
3818 case INTERP_MODE_SMOOTH:
3819 case INTERP_MODE_NONE:
3820 if (location == INTERP_CENTER)
3821 return ctx->persp_center;
3822 else if (location == INTERP_CENTROID)
3823 return ctx->persp_centroid;
3824 else if (location == INTERP_SAMPLE)
3825 return ctx->persp_sample;
3826 break;
3827 case INTERP_MODE_NOPERSPECTIVE:
3828 if (location == INTERP_CENTER)
3829 return ctx->linear_center;
3830 else if (location == INTERP_CENTROID)
3831 return ctx->linear_centroid;
3832 else if (location == INTERP_SAMPLE)
3833 return ctx->linear_sample;
3834 break;
3835 }
3836 return NULL;
3837 }
3838
3839 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3840 LLVMValueRef sample_id)
3841 {
3842 LLVMValueRef result;
3843 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3844
3845 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3846 const_array(ctx->ac.v2f32, 64), "");
3847
3848 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3849 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3850
3851 return result;
3852 }
3853
3854 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3855 {
3856 LLVMValueRef values[2];
3857
3858 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3859 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3860 return ac_build_gather_values(&ctx->ac, values, 2);
3861 }
3862
3863 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3864 const nir_intrinsic_instr *instr)
3865 {
3866 LLVMValueRef result[4];
3867 LLVMValueRef interp_param, attr_number;
3868 unsigned location;
3869 unsigned chan;
3870 LLVMValueRef src_c0 = NULL;
3871 LLVMValueRef src_c1 = NULL;
3872 LLVMValueRef src0 = NULL;
3873 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3874 switch (instr->intrinsic) {
3875 case nir_intrinsic_interp_var_at_centroid:
3876 location = INTERP_CENTROID;
3877 break;
3878 case nir_intrinsic_interp_var_at_sample:
3879 case nir_intrinsic_interp_var_at_offset:
3880 location = INTERP_CENTER;
3881 src0 = get_src(ctx->nir, instr->src[0]);
3882 break;
3883 default:
3884 break;
3885 }
3886
3887 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3888 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3889 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3890 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3891 LLVMValueRef sample_position;
3892 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
3893
3894 /* fetch sample ID */
3895 sample_position = load_sample_position(ctx, src0);
3896
3897 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
3898 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3899 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
3900 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3901 }
3902 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3903 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
3904
3905 if (location == INTERP_CENTER) {
3906 LLVMValueRef ij_out[2];
3907 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3908
3909 /*
3910 * take the I then J parameters, and the DDX/Y for it, and
3911 * calculate the IJ inputs for the interpolator.
3912 * temp1 = ddx * offset/sample.x + I;
3913 * interp_param.I = ddy * offset/sample.y + temp1;
3914 * temp1 = ddx * offset/sample.x + J;
3915 * interp_param.J = ddy * offset/sample.y + temp1;
3916 */
3917 for (unsigned i = 0; i < 2; i++) {
3918 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
3919 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
3920 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3921 ddxy_out, ix_ll, "");
3922 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3923 ddxy_out, iy_ll, "");
3924 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3925 interp_param, ix_ll, "");
3926 LLVMValueRef temp1, temp2;
3927
3928 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3929 ctx->ac.f32, "");
3930
3931 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3932 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3933
3934 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3935 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3936
3937 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3938 temp2, ctx->ac.i32, "");
3939 }
3940 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3941
3942 }
3943
3944 for (chan = 0; chan < 4; chan++) {
3945 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
3946
3947 if (interp_param) {
3948 interp_param = LLVMBuildBitCast(ctx->builder,
3949 interp_param, ctx->ac.v2f32, "");
3950 LLVMValueRef i = LLVMBuildExtractElement(
3951 ctx->builder, interp_param, ctx->ac.i32_0, "");
3952 LLVMValueRef j = LLVMBuildExtractElement(
3953 ctx->builder, interp_param, ctx->ac.i32_1, "");
3954
3955 result[chan] = ac_build_fs_interp(&ctx->ac,
3956 llvm_chan, attr_number,
3957 ctx->prim_mask, i, j);
3958 } else {
3959 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3960 LLVMConstInt(ctx->ac.i32, 2, false),
3961 llvm_chan, attr_number,
3962 ctx->prim_mask);
3963 }
3964 }
3965 return build_varying_gather_values(&ctx->ac, result, instr->num_components,
3966 instr->variables[0]->var->data.location_frac);
3967 }
3968
3969 static void
3970 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
3971 {
3972 LLVMValueRef gs_next_vertex;
3973 LLVMValueRef can_emit;
3974 int idx;
3975 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3976
3977 /* Write vertex attribute values to GSVS ring */
3978 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3979 ctx->gs_next_vertex,
3980 "");
3981
3982 /* If this thread has already emitted the declared maximum number of
3983 * vertices, kill it: excessive vertex emissions are not supposed to
3984 * have any effect, and GS threads have no externally observable
3985 * effects other than emitting vertices.
3986 */
3987 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3988 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
3989 ac_build_kill_if_false(&ctx->ac, can_emit);
3990
3991 /* loop num outputs */
3992 idx = 0;
3993 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3994 LLVMValueRef *out_ptr = &addrs[i * 4];
3995 int length = 4;
3996 int slot = idx;
3997 int slot_inc = 1;
3998
3999 if (!(ctx->output_mask & (1ull << i)))
4000 continue;
4001
4002 if (i == VARYING_SLOT_CLIP_DIST0) {
4003 /* pack clip and cull into a single set of slots */
4004 length = ctx->num_output_clips + ctx->num_output_culls;
4005 if (length > 4)
4006 slot_inc = 2;
4007 }
4008 for (unsigned j = 0; j < length; j++) {
4009 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4010 out_ptr[j], "");
4011 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4012 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4013 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4014
4015 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4016
4017 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4018 out_val, 1,
4019 voffset, ctx->gs2vs_offset, 0,
4020 1, 1, true, true);
4021 }
4022 idx += slot_inc;
4023 }
4024
4025 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4026 ctx->ac.i32_1, "");
4027 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4028
4029 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4030 }
4031
4032 static void
4033 visit_end_primitive(struct nir_to_llvm_context *ctx,
4034 const nir_intrinsic_instr *instr)
4035 {
4036 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4037 }
4038
4039 static LLVMValueRef
4040 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4041 const nir_intrinsic_instr *instr)
4042 {
4043 LLVMValueRef coord[4] = {
4044 ctx->tes_u,
4045 ctx->tes_v,
4046 ctx->ac.f32_0,
4047 ctx->ac.f32_0,
4048 };
4049
4050 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4051 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4052 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4053
4054 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4055 return LLVMBuildBitCast(ctx->builder, result,
4056 get_def_type(ctx->nir, &instr->dest.ssa), "");
4057 }
4058
4059 static void visit_intrinsic(struct ac_nir_context *ctx,
4060 nir_intrinsic_instr *instr)
4061 {
4062 LLVMValueRef result = NULL;
4063
4064 switch (instr->intrinsic) {
4065 case nir_intrinsic_load_work_group_id: {
4066 result = ctx->nctx->workgroup_ids;
4067 break;
4068 }
4069 case nir_intrinsic_load_base_vertex: {
4070 result = ctx->abi->base_vertex;
4071 break;
4072 }
4073 case nir_intrinsic_load_vertex_id_zero_base: {
4074 result = ctx->abi->vertex_id;
4075 break;
4076 }
4077 case nir_intrinsic_load_local_invocation_id: {
4078 result = ctx->nctx->local_invocation_ids;
4079 break;
4080 }
4081 case nir_intrinsic_load_base_instance:
4082 result = ctx->abi->start_instance;
4083 break;
4084 case nir_intrinsic_load_draw_id:
4085 result = ctx->abi->draw_id;
4086 break;
4087 case nir_intrinsic_load_view_index:
4088 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4089 break;
4090 case nir_intrinsic_load_invocation_id:
4091 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4092 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4093 else
4094 result = ctx->abi->gs_invocation_id;
4095 break;
4096 case nir_intrinsic_load_primitive_id:
4097 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4098 if (ctx->nctx)
4099 ctx->nctx->shader_info->gs.uses_prim_id = true;
4100 result = ctx->abi->gs_prim_id;
4101 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4102 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4103 result = ctx->nctx->tcs_patch_id;
4104 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4105 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4106 result = ctx->nctx->tes_patch_id;
4107 } else
4108 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4109 break;
4110 case nir_intrinsic_load_sample_id:
4111 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4112 break;
4113 case nir_intrinsic_load_sample_pos:
4114 result = load_sample_pos(ctx);
4115 break;
4116 case nir_intrinsic_load_sample_mask_in:
4117 result = ctx->abi->sample_coverage;
4118 break;
4119 case nir_intrinsic_load_frag_coord: {
4120 LLVMValueRef values[4] = {
4121 ctx->abi->frag_pos[0],
4122 ctx->abi->frag_pos[1],
4123 ctx->abi->frag_pos[2],
4124 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4125 };
4126 result = ac_build_gather_values(&ctx->ac, values, 4);
4127 break;
4128 }
4129 case nir_intrinsic_load_front_face:
4130 result = ctx->abi->front_face;
4131 break;
4132 case nir_intrinsic_load_instance_id:
4133 result = ctx->abi->instance_id;
4134 break;
4135 case nir_intrinsic_load_num_work_groups:
4136 result = ctx->nctx->num_work_groups;
4137 break;
4138 case nir_intrinsic_load_local_invocation_index:
4139 result = visit_load_local_invocation_index(ctx->nctx);
4140 break;
4141 case nir_intrinsic_load_push_constant:
4142 result = visit_load_push_constant(ctx->nctx, instr);
4143 break;
4144 case nir_intrinsic_vulkan_resource_index:
4145 result = visit_vulkan_resource_index(ctx->nctx, instr);
4146 break;
4147 case nir_intrinsic_store_ssbo:
4148 visit_store_ssbo(ctx, instr);
4149 break;
4150 case nir_intrinsic_load_ssbo:
4151 result = visit_load_buffer(ctx, instr);
4152 break;
4153 case nir_intrinsic_ssbo_atomic_add:
4154 case nir_intrinsic_ssbo_atomic_imin:
4155 case nir_intrinsic_ssbo_atomic_umin:
4156 case nir_intrinsic_ssbo_atomic_imax:
4157 case nir_intrinsic_ssbo_atomic_umax:
4158 case nir_intrinsic_ssbo_atomic_and:
4159 case nir_intrinsic_ssbo_atomic_or:
4160 case nir_intrinsic_ssbo_atomic_xor:
4161 case nir_intrinsic_ssbo_atomic_exchange:
4162 case nir_intrinsic_ssbo_atomic_comp_swap:
4163 result = visit_atomic_ssbo(ctx, instr);
4164 break;
4165 case nir_intrinsic_load_ubo:
4166 result = visit_load_ubo_buffer(ctx, instr);
4167 break;
4168 case nir_intrinsic_get_buffer_size:
4169 result = visit_get_buffer_size(ctx, instr);
4170 break;
4171 case nir_intrinsic_load_var:
4172 result = visit_load_var(ctx, instr);
4173 break;
4174 case nir_intrinsic_store_var:
4175 visit_store_var(ctx, instr);
4176 break;
4177 case nir_intrinsic_image_load:
4178 result = visit_image_load(ctx, instr);
4179 break;
4180 case nir_intrinsic_image_store:
4181 visit_image_store(ctx, instr);
4182 break;
4183 case nir_intrinsic_image_atomic_add:
4184 case nir_intrinsic_image_atomic_min:
4185 case nir_intrinsic_image_atomic_max:
4186 case nir_intrinsic_image_atomic_and:
4187 case nir_intrinsic_image_atomic_or:
4188 case nir_intrinsic_image_atomic_xor:
4189 case nir_intrinsic_image_atomic_exchange:
4190 case nir_intrinsic_image_atomic_comp_swap:
4191 result = visit_image_atomic(ctx, instr);
4192 break;
4193 case nir_intrinsic_image_size:
4194 result = visit_image_size(ctx, instr);
4195 break;
4196 case nir_intrinsic_discard:
4197 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4198 LLVMVoidTypeInContext(ctx->ac.context),
4199 NULL, 0, AC_FUNC_ATTR_LEGACY);
4200 break;
4201 case nir_intrinsic_discard_if:
4202 emit_discard_if(ctx, instr);
4203 break;
4204 case nir_intrinsic_memory_barrier:
4205 case nir_intrinsic_group_memory_barrier:
4206 case nir_intrinsic_memory_barrier_atomic_counter:
4207 case nir_intrinsic_memory_barrier_buffer:
4208 case nir_intrinsic_memory_barrier_image:
4209 case nir_intrinsic_memory_barrier_shared:
4210 emit_membar(ctx->nctx, instr);
4211 break;
4212 case nir_intrinsic_barrier:
4213 emit_barrier(ctx->nctx);
4214 break;
4215 case nir_intrinsic_var_atomic_add:
4216 case nir_intrinsic_var_atomic_imin:
4217 case nir_intrinsic_var_atomic_umin:
4218 case nir_intrinsic_var_atomic_imax:
4219 case nir_intrinsic_var_atomic_umax:
4220 case nir_intrinsic_var_atomic_and:
4221 case nir_intrinsic_var_atomic_or:
4222 case nir_intrinsic_var_atomic_xor:
4223 case nir_intrinsic_var_atomic_exchange:
4224 case nir_intrinsic_var_atomic_comp_swap:
4225 result = visit_var_atomic(ctx->nctx, instr);
4226 break;
4227 case nir_intrinsic_interp_var_at_centroid:
4228 case nir_intrinsic_interp_var_at_sample:
4229 case nir_intrinsic_interp_var_at_offset:
4230 result = visit_interp(ctx->nctx, instr);
4231 break;
4232 case nir_intrinsic_emit_vertex:
4233 assert(instr->const_index[0] == 0);
4234 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4235 break;
4236 case nir_intrinsic_end_primitive:
4237 visit_end_primitive(ctx->nctx, instr);
4238 break;
4239 case nir_intrinsic_load_tess_coord:
4240 result = visit_load_tess_coord(ctx->nctx, instr);
4241 break;
4242 case nir_intrinsic_load_patch_vertices_in:
4243 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4244 break;
4245 default:
4246 fprintf(stderr, "Unknown intrinsic: ");
4247 nir_print_instr(&instr->instr, stderr);
4248 fprintf(stderr, "\n");
4249 break;
4250 }
4251 if (result) {
4252 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4253 }
4254 }
4255
4256 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4257 LLVMValueRef buffer, bool write)
4258 {
4259 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4260
4261 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4262 ctx->shader_info->fs.writes_memory = true;
4263
4264 return buffer;
4265 }
4266
4267 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4268 unsigned descriptor_set,
4269 unsigned base_index,
4270 unsigned constant_index,
4271 LLVMValueRef index,
4272 enum ac_descriptor_type desc_type,
4273 bool image, bool write)
4274 {
4275 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4276 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4277 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4278 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4279 unsigned offset = binding->offset;
4280 unsigned stride = binding->size;
4281 unsigned type_size;
4282 LLVMBuilderRef builder = ctx->builder;
4283 LLVMTypeRef type;
4284
4285 assert(base_index < layout->binding_count);
4286
4287 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4288 ctx->shader_info->fs.writes_memory = true;
4289
4290 switch (desc_type) {
4291 case AC_DESC_IMAGE:
4292 type = ctx->ac.v8i32;
4293 type_size = 32;
4294 break;
4295 case AC_DESC_FMASK:
4296 type = ctx->ac.v8i32;
4297 offset += 32;
4298 type_size = 32;
4299 break;
4300 case AC_DESC_SAMPLER:
4301 type = ctx->ac.v4i32;
4302 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4303 offset += 64;
4304
4305 type_size = 16;
4306 break;
4307 case AC_DESC_BUFFER:
4308 type = ctx->ac.v4i32;
4309 type_size = 16;
4310 break;
4311 default:
4312 unreachable("invalid desc_type\n");
4313 }
4314
4315 offset += constant_index * stride;
4316
4317 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4318 (!index || binding->immutable_samplers_equal)) {
4319 if (binding->immutable_samplers_equal)
4320 constant_index = 0;
4321
4322 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4323
4324 LLVMValueRef constants[] = {
4325 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4326 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4327 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4328 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4329 };
4330 return ac_build_gather_values(&ctx->ac, constants, 4);
4331 }
4332
4333 assert(stride % type_size == 0);
4334
4335 if (!index)
4336 index = ctx->ac.i32_0;
4337
4338 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4339
4340 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4341 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4342
4343 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4344 }
4345
4346 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4347 const nir_deref_var *deref,
4348 enum ac_descriptor_type desc_type,
4349 const nir_tex_instr *tex_instr,
4350 bool image, bool write)
4351 {
4352 LLVMValueRef index = NULL;
4353 unsigned constant_index = 0;
4354 unsigned descriptor_set;
4355 unsigned base_index;
4356
4357 if (!deref) {
4358 assert(tex_instr && !image);
4359 descriptor_set = 0;
4360 base_index = tex_instr->sampler_index;
4361 } else {
4362 const nir_deref *tail = &deref->deref;
4363 while (tail->child) {
4364 const nir_deref_array *child = nir_deref_as_array(tail->child);
4365 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4366
4367 if (!array_size)
4368 array_size = 1;
4369
4370 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4371
4372 if (child->deref_array_type == nir_deref_array_type_indirect) {
4373 LLVMValueRef indirect = get_src(ctx, child->indirect);
4374
4375 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4376 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4377
4378 if (!index)
4379 index = indirect;
4380 else
4381 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4382 }
4383
4384 constant_index += child->base_offset * array_size;
4385
4386 tail = &child->deref;
4387 }
4388 descriptor_set = deref->var->data.descriptor_set;
4389 base_index = deref->var->data.binding;
4390 }
4391
4392 return ctx->abi->load_sampler_desc(ctx->abi,
4393 descriptor_set,
4394 base_index,
4395 constant_index, index,
4396 desc_type, image, write);
4397 }
4398
4399 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4400 struct ac_image_args *args,
4401 const nir_tex_instr *instr,
4402 nir_texop op,
4403 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4404 LLVMValueRef *param, unsigned count,
4405 unsigned dmask)
4406 {
4407 unsigned is_rect = 0;
4408 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4409
4410 if (op == nir_texop_lod)
4411 da = false;
4412 /* Pad to power of two vector */
4413 while (count < util_next_power_of_two(count))
4414 param[count++] = LLVMGetUndef(ctx->i32);
4415
4416 if (count > 1)
4417 args->addr = ac_build_gather_values(ctx, param, count);
4418 else
4419 args->addr = param[0];
4420
4421 args->resource = res_ptr;
4422 args->sampler = samp_ptr;
4423
4424 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4425 args->addr = param[0];
4426 return;
4427 }
4428
4429 args->dmask = dmask;
4430 args->unorm = is_rect;
4431 args->da = da;
4432 }
4433
4434 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4435 *
4436 * SI-CI:
4437 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4438 * filtering manually. The driver sets img7 to a mask clearing
4439 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4440 * s_and_b32 samp0, samp0, img7
4441 *
4442 * VI:
4443 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4444 */
4445 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4446 LLVMValueRef res, LLVMValueRef samp)
4447 {
4448 LLVMBuilderRef builder = ctx->ac.builder;
4449 LLVMValueRef img7, samp0;
4450
4451 if (ctx->ac.chip_class >= VI)
4452 return samp;
4453
4454 img7 = LLVMBuildExtractElement(builder, res,
4455 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4456 samp0 = LLVMBuildExtractElement(builder, samp,
4457 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4458 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4459 return LLVMBuildInsertElement(builder, samp, samp0,
4460 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4461 }
4462
4463 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4464 nir_tex_instr *instr,
4465 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4466 LLVMValueRef *fmask_ptr)
4467 {
4468 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4469 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4470 else
4471 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4472 if (samp_ptr) {
4473 if (instr->sampler)
4474 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4475 else
4476 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4477 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4478 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4479 }
4480 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4481 instr->op == nir_texop_samples_identical))
4482 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4483 }
4484
4485 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4486 LLVMValueRef coord)
4487 {
4488 coord = ac_to_float(ctx, coord);
4489 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4490 coord = ac_to_integer(ctx, coord);
4491 return coord;
4492 }
4493
4494 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4495 {
4496 LLVMValueRef result = NULL;
4497 struct ac_image_args args = { 0 };
4498 unsigned dmask = 0xf;
4499 LLVMValueRef address[16];
4500 LLVMValueRef coords[5];
4501 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4502 LLVMValueRef bias = NULL, offsets = NULL;
4503 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4504 LLVMValueRef ddx = NULL, ddy = NULL;
4505 LLVMValueRef derivs[6];
4506 unsigned chan, count = 0;
4507 unsigned const_src = 0, num_deriv_comp = 0;
4508 bool lod_is_zero = false;
4509
4510 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4511
4512 for (unsigned i = 0; i < instr->num_srcs; i++) {
4513 switch (instr->src[i].src_type) {
4514 case nir_tex_src_coord:
4515 coord = get_src(ctx, instr->src[i].src);
4516 break;
4517 case nir_tex_src_projector:
4518 break;
4519 case nir_tex_src_comparator:
4520 comparator = get_src(ctx, instr->src[i].src);
4521 break;
4522 case nir_tex_src_offset:
4523 offsets = get_src(ctx, instr->src[i].src);
4524 const_src = i;
4525 break;
4526 case nir_tex_src_bias:
4527 bias = get_src(ctx, instr->src[i].src);
4528 break;
4529 case nir_tex_src_lod: {
4530 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4531
4532 if (val && val->i32[0] == 0)
4533 lod_is_zero = true;
4534 lod = get_src(ctx, instr->src[i].src);
4535 break;
4536 }
4537 case nir_tex_src_ms_index:
4538 sample_index = get_src(ctx, instr->src[i].src);
4539 break;
4540 case nir_tex_src_ms_mcs:
4541 break;
4542 case nir_tex_src_ddx:
4543 ddx = get_src(ctx, instr->src[i].src);
4544 num_deriv_comp = instr->src[i].src.ssa->num_components;
4545 break;
4546 case nir_tex_src_ddy:
4547 ddy = get_src(ctx, instr->src[i].src);
4548 break;
4549 case nir_tex_src_texture_offset:
4550 case nir_tex_src_sampler_offset:
4551 case nir_tex_src_plane:
4552 default:
4553 break;
4554 }
4555 }
4556
4557 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4558 result = get_buffer_size(ctx, res_ptr, true);
4559 goto write_result;
4560 }
4561
4562 if (instr->op == nir_texop_texture_samples) {
4563 LLVMValueRef res, samples, is_msaa;
4564 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4565 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4566 LLVMConstInt(ctx->ac.i32, 3, false), "");
4567 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4568 LLVMConstInt(ctx->ac.i32, 28, false), "");
4569 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4570 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4571 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4572 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4573
4574 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4575 LLVMConstInt(ctx->ac.i32, 16, false), "");
4576 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4577 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4578 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4579 samples, "");
4580 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4581 ctx->ac.i32_1, "");
4582 result = samples;
4583 goto write_result;
4584 }
4585
4586 if (coord)
4587 for (chan = 0; chan < instr->coord_components; chan++)
4588 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4589
4590 if (offsets && instr->op != nir_texop_txf) {
4591 LLVMValueRef offset[3], pack;
4592 for (chan = 0; chan < 3; ++chan)
4593 offset[chan] = ctx->ac.i32_0;
4594
4595 args.offset = true;
4596 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4597 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4598 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4599 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4600 if (chan)
4601 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4602 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4603 }
4604 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4605 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4606 address[count++] = pack;
4607
4608 }
4609 /* pack LOD bias value */
4610 if (instr->op == nir_texop_txb && bias) {
4611 address[count++] = bias;
4612 }
4613
4614 /* Pack depth comparison value */
4615 if (instr->is_shadow && comparator) {
4616 LLVMValueRef z = ac_to_float(&ctx->ac,
4617 llvm_extract_elem(&ctx->ac, comparator, 0));
4618
4619 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4620 * so the depth comparison value isn't clamped for Z16 and
4621 * Z24 anymore. Do it manually here.
4622 *
4623 * It's unnecessary if the original texture format was
4624 * Z32_FLOAT, but we don't know that here.
4625 */
4626 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4627 z = ac_build_clamp(&ctx->ac, z);
4628
4629 address[count++] = z;
4630 }
4631
4632 /* pack derivatives */
4633 if (ddx || ddy) {
4634 int num_src_deriv_channels, num_dest_deriv_channels;
4635 switch (instr->sampler_dim) {
4636 case GLSL_SAMPLER_DIM_3D:
4637 case GLSL_SAMPLER_DIM_CUBE:
4638 num_deriv_comp = 3;
4639 num_src_deriv_channels = 3;
4640 num_dest_deriv_channels = 3;
4641 break;
4642 case GLSL_SAMPLER_DIM_2D:
4643 default:
4644 num_src_deriv_channels = 2;
4645 num_dest_deriv_channels = 2;
4646 num_deriv_comp = 2;
4647 break;
4648 case GLSL_SAMPLER_DIM_1D:
4649 num_src_deriv_channels = 1;
4650 if (ctx->ac.chip_class >= GFX9) {
4651 num_dest_deriv_channels = 2;
4652 num_deriv_comp = 2;
4653 } else {
4654 num_dest_deriv_channels = 1;
4655 num_deriv_comp = 1;
4656 }
4657 break;
4658 }
4659
4660 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4661 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4662 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4663 }
4664 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4665 derivs[i] = ctx->ac.f32_0;
4666 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4667 }
4668 }
4669
4670 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4671 for (chan = 0; chan < instr->coord_components; chan++)
4672 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4673 if (instr->coord_components == 3)
4674 coords[3] = LLVMGetUndef(ctx->ac.f32);
4675 ac_prepare_cube_coords(&ctx->ac,
4676 instr->op == nir_texop_txd, instr->is_array,
4677 instr->op == nir_texop_lod, coords, derivs);
4678 if (num_deriv_comp)
4679 num_deriv_comp--;
4680 }
4681
4682 if (ddx || ddy) {
4683 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4684 address[count++] = derivs[i];
4685 }
4686
4687 /* Pack texture coordinates */
4688 if (coord) {
4689 address[count++] = coords[0];
4690 if (instr->coord_components > 1) {
4691 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4692 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4693 }
4694 address[count++] = coords[1];
4695 }
4696 if (instr->coord_components > 2) {
4697 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4698 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4699 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4700 instr->op != nir_texop_txf) {
4701 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4702 }
4703 address[count++] = coords[2];
4704 }
4705
4706 if (ctx->ac.chip_class >= GFX9) {
4707 LLVMValueRef filler;
4708 if (instr->op == nir_texop_txf)
4709 filler = ctx->ac.i32_0;
4710 else
4711 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4712
4713 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4714 /* No nir_texop_lod, because it does not take a slice
4715 * even with array textures. */
4716 if (instr->is_array && instr->op != nir_texop_lod ) {
4717 address[count] = address[count - 1];
4718 address[count - 1] = filler;
4719 count++;
4720 } else
4721 address[count++] = filler;
4722 }
4723 }
4724 }
4725
4726 /* Pack LOD */
4727 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4728 instr->op == nir_texop_txf)) {
4729 address[count++] = lod;
4730 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4731 address[count++] = sample_index;
4732 } else if(instr->op == nir_texop_txs) {
4733 count = 0;
4734 if (lod)
4735 address[count++] = lod;
4736 else
4737 address[count++] = ctx->ac.i32_0;
4738 }
4739
4740 for (chan = 0; chan < count; chan++) {
4741 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4742 address[chan], ctx->ac.i32, "");
4743 }
4744
4745 if (instr->op == nir_texop_samples_identical) {
4746 LLVMValueRef txf_address[4];
4747 struct ac_image_args txf_args = { 0 };
4748 unsigned txf_count = count;
4749 memcpy(txf_address, address, sizeof(txf_address));
4750
4751 if (!instr->is_array)
4752 txf_address[2] = ctx->ac.i32_0;
4753 txf_address[3] = ctx->ac.i32_0;
4754
4755 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4756 fmask_ptr, NULL,
4757 txf_address, txf_count, 0xf);
4758
4759 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4760
4761 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4762 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4763 goto write_result;
4764 }
4765
4766 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4767 instr->op != nir_texop_txs) {
4768 unsigned sample_chan = instr->is_array ? 3 : 2;
4769 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4770 address[0],
4771 address[1],
4772 instr->is_array ? address[2] : NULL,
4773 address[sample_chan],
4774 fmask_ptr);
4775 }
4776
4777 if (offsets && instr->op == nir_texop_txf) {
4778 nir_const_value *const_offset =
4779 nir_src_as_const_value(instr->src[const_src].src);
4780 int num_offsets = instr->src[const_src].src.ssa->num_components;
4781 assert(const_offset);
4782 num_offsets = MIN2(num_offsets, instr->coord_components);
4783 if (num_offsets > 2)
4784 address[2] = LLVMBuildAdd(ctx->ac.builder,
4785 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4786 if (num_offsets > 1)
4787 address[1] = LLVMBuildAdd(ctx->ac.builder,
4788 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4789 address[0] = LLVMBuildAdd(ctx->ac.builder,
4790 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4791
4792 }
4793
4794 /* TODO TG4 support */
4795 if (instr->op == nir_texop_tg4) {
4796 if (instr->is_shadow)
4797 dmask = 1;
4798 else
4799 dmask = 1 << instr->component;
4800 }
4801 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4802 res_ptr, samp_ptr, address, count, dmask);
4803
4804 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4805
4806 if (instr->op == nir_texop_query_levels)
4807 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4808 else if (instr->is_shadow && instr->is_new_style_shadow &&
4809 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4810 instr->op != nir_texop_tg4)
4811 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4812 else if (instr->op == nir_texop_txs &&
4813 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4814 instr->is_array) {
4815 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4816 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4817 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4818 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4819 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4820 } else if (ctx->ac.chip_class >= GFX9 &&
4821 instr->op == nir_texop_txs &&
4822 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4823 instr->is_array) {
4824 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4825 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4826 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4827 ctx->ac.i32_1, "");
4828 } else if (instr->dest.ssa.num_components != 4)
4829 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4830
4831 write_result:
4832 if (result) {
4833 assert(instr->dest.is_ssa);
4834 result = ac_to_integer(&ctx->ac, result);
4835 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4836 }
4837 }
4838
4839
4840 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4841 {
4842 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4843 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4844
4845 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4846 _mesa_hash_table_insert(ctx->phis, instr, result);
4847 }
4848
4849 static void visit_post_phi(struct ac_nir_context *ctx,
4850 nir_phi_instr *instr,
4851 LLVMValueRef llvm_phi)
4852 {
4853 nir_foreach_phi_src(src, instr) {
4854 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4855 LLVMValueRef llvm_src = get_src(ctx, src->src);
4856
4857 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4858 }
4859 }
4860
4861 static void phi_post_pass(struct ac_nir_context *ctx)
4862 {
4863 struct hash_entry *entry;
4864 hash_table_foreach(ctx->phis, entry) {
4865 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4866 (LLVMValueRef)entry->data);
4867 }
4868 }
4869
4870
4871 static void visit_ssa_undef(struct ac_nir_context *ctx,
4872 const nir_ssa_undef_instr *instr)
4873 {
4874 unsigned num_components = instr->def.num_components;
4875 LLVMValueRef undef;
4876
4877 if (num_components == 1)
4878 undef = LLVMGetUndef(ctx->ac.i32);
4879 else {
4880 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4881 }
4882 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4883 }
4884
4885 static void visit_jump(struct ac_nir_context *ctx,
4886 const nir_jump_instr *instr)
4887 {
4888 switch (instr->type) {
4889 case nir_jump_break:
4890 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4891 LLVMClearInsertionPosition(ctx->ac.builder);
4892 break;
4893 case nir_jump_continue:
4894 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4895 LLVMClearInsertionPosition(ctx->ac.builder);
4896 break;
4897 default:
4898 fprintf(stderr, "Unknown NIR jump instr: ");
4899 nir_print_instr(&instr->instr, stderr);
4900 fprintf(stderr, "\n");
4901 abort();
4902 }
4903 }
4904
4905 static void visit_cf_list(struct ac_nir_context *ctx,
4906 struct exec_list *list);
4907
4908 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4909 {
4910 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4911 nir_foreach_instr(instr, block)
4912 {
4913 switch (instr->type) {
4914 case nir_instr_type_alu:
4915 visit_alu(ctx, nir_instr_as_alu(instr));
4916 break;
4917 case nir_instr_type_load_const:
4918 visit_load_const(ctx, nir_instr_as_load_const(instr));
4919 break;
4920 case nir_instr_type_intrinsic:
4921 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4922 break;
4923 case nir_instr_type_tex:
4924 visit_tex(ctx, nir_instr_as_tex(instr));
4925 break;
4926 case nir_instr_type_phi:
4927 visit_phi(ctx, nir_instr_as_phi(instr));
4928 break;
4929 case nir_instr_type_ssa_undef:
4930 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4931 break;
4932 case nir_instr_type_jump:
4933 visit_jump(ctx, nir_instr_as_jump(instr));
4934 break;
4935 default:
4936 fprintf(stderr, "Unknown NIR instr type: ");
4937 nir_print_instr(instr, stderr);
4938 fprintf(stderr, "\n");
4939 abort();
4940 }
4941 }
4942
4943 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4944 }
4945
4946 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4947 {
4948 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4949
4950 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4951 LLVMBasicBlockRef merge_block =
4952 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4953 LLVMBasicBlockRef if_block =
4954 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4955 LLVMBasicBlockRef else_block = merge_block;
4956 if (!exec_list_is_empty(&if_stmt->else_list))
4957 else_block = LLVMAppendBasicBlockInContext(
4958 ctx->ac.context, fn, "");
4959
4960 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4961 LLVMConstInt(ctx->ac.i32, 0, false), "");
4962 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4963
4964 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4965 visit_cf_list(ctx, &if_stmt->then_list);
4966 if (LLVMGetInsertBlock(ctx->ac.builder))
4967 LLVMBuildBr(ctx->ac.builder, merge_block);
4968
4969 if (!exec_list_is_empty(&if_stmt->else_list)) {
4970 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4971 visit_cf_list(ctx, &if_stmt->else_list);
4972 if (LLVMGetInsertBlock(ctx->ac.builder))
4973 LLVMBuildBr(ctx->ac.builder, merge_block);
4974 }
4975
4976 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4977 }
4978
4979 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4980 {
4981 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4982 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4983 LLVMBasicBlockRef break_parent = ctx->break_block;
4984
4985 ctx->continue_block =
4986 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4987 ctx->break_block =
4988 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4989
4990 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4991 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4992 visit_cf_list(ctx, &loop->body);
4993
4994 if (LLVMGetInsertBlock(ctx->ac.builder))
4995 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4996 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4997
4998 ctx->continue_block = continue_parent;
4999 ctx->break_block = break_parent;
5000 }
5001
5002 static void visit_cf_list(struct ac_nir_context *ctx,
5003 struct exec_list *list)
5004 {
5005 foreach_list_typed(nir_cf_node, node, node, list)
5006 {
5007 switch (node->type) {
5008 case nir_cf_node_block:
5009 visit_block(ctx, nir_cf_node_as_block(node));
5010 break;
5011
5012 case nir_cf_node_if:
5013 visit_if(ctx, nir_cf_node_as_if(node));
5014 break;
5015
5016 case nir_cf_node_loop:
5017 visit_loop(ctx, nir_cf_node_as_loop(node));
5018 break;
5019
5020 default:
5021 assert(0);
5022 }
5023 }
5024 }
5025
5026 static void
5027 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5028 struct nir_variable *variable)
5029 {
5030 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5031 LLVMValueRef t_offset;
5032 LLVMValueRef t_list;
5033 LLVMValueRef input;
5034 LLVMValueRef buffer_index;
5035 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5036 int idx = variable->data.location;
5037 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5038
5039 variable->data.driver_location = idx * 4;
5040
5041 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5042 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5043 ctx->abi.start_instance, "");
5044 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5045 ctx->shader_info->vs.vgpr_comp_cnt);
5046 } else
5047 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5048 ctx->abi.base_vertex, "");
5049
5050 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5051 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5052
5053 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5054
5055 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5056 buffer_index,
5057 LLVMConstInt(ctx->ac.i32, 0, false),
5058 true);
5059
5060 for (unsigned chan = 0; chan < 4; chan++) {
5061 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5062 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5063 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5064 input, llvm_chan, ""));
5065 }
5066 }
5067 }
5068
5069 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5070 unsigned attr,
5071 LLVMValueRef interp_param,
5072 LLVMValueRef prim_mask,
5073 LLVMValueRef result[4])
5074 {
5075 LLVMValueRef attr_number;
5076 unsigned chan;
5077 LLVMValueRef i, j;
5078 bool interp = interp_param != NULL;
5079
5080 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5081
5082 /* fs.constant returns the param from the middle vertex, so it's not
5083 * really useful for flat shading. It's meant to be used for custom
5084 * interpolation (but the intrinsic can't fetch from the other two
5085 * vertices).
5086 *
5087 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5088 * to do the right thing. The only reason we use fs.constant is that
5089 * fs.interp cannot be used on integers, because they can be equal
5090 * to NaN.
5091 */
5092 if (interp) {
5093 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5094 ctx->ac.v2f32, "");
5095
5096 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5097 ctx->ac.i32_0, "");
5098 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5099 ctx->ac.i32_1, "");
5100 }
5101
5102 for (chan = 0; chan < 4; chan++) {
5103 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5104
5105 if (interp) {
5106 result[chan] = ac_build_fs_interp(&ctx->ac,
5107 llvm_chan,
5108 attr_number,
5109 prim_mask, i, j);
5110 } else {
5111 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5112 LLVMConstInt(ctx->ac.i32, 2, false),
5113 llvm_chan,
5114 attr_number,
5115 prim_mask);
5116 }
5117 }
5118 }
5119
5120 static void
5121 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5122 struct nir_variable *variable)
5123 {
5124 int idx = variable->data.location;
5125 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5126 LLVMValueRef interp;
5127
5128 variable->data.driver_location = idx * 4;
5129 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5130
5131 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5132 unsigned interp_type;
5133 if (variable->data.sample) {
5134 interp_type = INTERP_SAMPLE;
5135 ctx->shader_info->info.ps.force_persample = true;
5136 } else if (variable->data.centroid)
5137 interp_type = INTERP_CENTROID;
5138 else
5139 interp_type = INTERP_CENTER;
5140
5141 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5142 } else
5143 interp = NULL;
5144
5145 for (unsigned i = 0; i < attrib_count; ++i)
5146 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5147
5148 }
5149
5150 static void
5151 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5152 struct nir_shader *nir) {
5153 nir_foreach_variable(variable, &nir->inputs)
5154 handle_vs_input_decl(ctx, variable);
5155 }
5156
5157 static void
5158 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5159 struct nir_shader *nir)
5160 {
5161 if (!ctx->options->key.fs.multisample)
5162 return;
5163
5164 bool uses_center = false;
5165 bool uses_centroid = false;
5166 nir_foreach_variable(variable, &nir->inputs) {
5167 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5168 variable->data.sample)
5169 continue;
5170
5171 if (variable->data.centroid)
5172 uses_centroid = true;
5173 else
5174 uses_center = true;
5175 }
5176
5177 if (uses_center && uses_centroid) {
5178 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5179 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5180 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5181 }
5182 }
5183
5184 static void
5185 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5186 struct nir_shader *nir)
5187 {
5188 prepare_interp_optimize(ctx, nir);
5189
5190 nir_foreach_variable(variable, &nir->inputs)
5191 handle_fs_input_decl(ctx, variable);
5192
5193 unsigned index = 0;
5194
5195 if (ctx->shader_info->info.ps.uses_input_attachments ||
5196 ctx->shader_info->info.needs_multiview_view_index)
5197 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5198
5199 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5200 LLVMValueRef interp_param;
5201 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5202
5203 if (!(ctx->input_mask & (1ull << i)))
5204 continue;
5205
5206 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5207 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5208 interp_param = *inputs;
5209 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5210 inputs);
5211
5212 if (!interp_param)
5213 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5214 ++index;
5215 } else if (i == VARYING_SLOT_POS) {
5216 for(int i = 0; i < 3; ++i)
5217 inputs[i] = ctx->abi.frag_pos[i];
5218
5219 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5220 ctx->abi.frag_pos[3]);
5221 }
5222 }
5223 ctx->shader_info->fs.num_interp = index;
5224 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5225 ctx->shader_info->fs.has_pcoord = true;
5226 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5227 ctx->shader_info->fs.prim_id_input = true;
5228 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5229 ctx->shader_info->fs.layer_input = true;
5230 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5231
5232 if (ctx->shader_info->info.needs_multiview_view_index)
5233 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5234 }
5235
5236 static LLVMValueRef
5237 ac_build_alloca(struct ac_llvm_context *ac,
5238 LLVMTypeRef type,
5239 const char *name)
5240 {
5241 LLVMBuilderRef builder = ac->builder;
5242 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5243 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5244 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5245 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5246 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5247 LLVMValueRef res;
5248
5249 if (first_instr) {
5250 LLVMPositionBuilderBefore(first_builder, first_instr);
5251 } else {
5252 LLVMPositionBuilderAtEnd(first_builder, first_block);
5253 }
5254
5255 res = LLVMBuildAlloca(first_builder, type, name);
5256 LLVMBuildStore(builder, LLVMConstNull(type), res);
5257
5258 LLVMDisposeBuilder(first_builder);
5259
5260 return res;
5261 }
5262
5263 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5264 LLVMTypeRef type,
5265 const char *name)
5266 {
5267 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5268 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5269 return ptr;
5270 }
5271
5272 static void
5273 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5274 struct nir_variable *variable,
5275 struct nir_shader *shader,
5276 gl_shader_stage stage)
5277 {
5278 int idx = variable->data.location + variable->data.index;
5279 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5280 uint64_t mask_attribs;
5281
5282 variable->data.driver_location = idx * 4;
5283
5284 /* tess ctrl has it's own load/store paths for outputs */
5285 if (stage == MESA_SHADER_TESS_CTRL)
5286 return;
5287
5288 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5289 if (stage == MESA_SHADER_VERTEX ||
5290 stage == MESA_SHADER_TESS_EVAL ||
5291 stage == MESA_SHADER_GEOMETRY) {
5292 if (idx == VARYING_SLOT_CLIP_DIST0) {
5293 int length = shader->info.clip_distance_array_size +
5294 shader->info.cull_distance_array_size;
5295 if (stage == MESA_SHADER_VERTEX) {
5296 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5297 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5298 }
5299 if (stage == MESA_SHADER_TESS_EVAL) {
5300 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5301 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5302 }
5303
5304 if (length > 4)
5305 attrib_count = 2;
5306 else
5307 attrib_count = 1;
5308 mask_attribs = 1ull << idx;
5309 }
5310 }
5311
5312 ctx->output_mask |= mask_attribs;
5313 }
5314
5315 static void
5316 handle_shader_output_decl(struct ac_nir_context *ctx,
5317 struct nir_shader *nir,
5318 struct nir_variable *variable)
5319 {
5320 unsigned output_loc = variable->data.driver_location / 4;
5321 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5322
5323 /* tess ctrl has it's own load/store paths for outputs */
5324 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5325 return;
5326
5327 if (ctx->stage == MESA_SHADER_VERTEX ||
5328 ctx->stage == MESA_SHADER_TESS_EVAL ||
5329 ctx->stage == MESA_SHADER_GEOMETRY) {
5330 int idx = variable->data.location + variable->data.index;
5331 if (idx == VARYING_SLOT_CLIP_DIST0) {
5332 int length = nir->info.clip_distance_array_size +
5333 nir->info.cull_distance_array_size;
5334
5335 if (length > 4)
5336 attrib_count = 2;
5337 else
5338 attrib_count = 1;
5339 }
5340 }
5341
5342 for (unsigned i = 0; i < attrib_count; ++i) {
5343 for (unsigned chan = 0; chan < 4; chan++) {
5344 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5345 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5346 }
5347 }
5348 }
5349
5350 static LLVMTypeRef
5351 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5352 enum glsl_base_type type)
5353 {
5354 switch (type) {
5355 case GLSL_TYPE_INT:
5356 case GLSL_TYPE_UINT:
5357 case GLSL_TYPE_BOOL:
5358 case GLSL_TYPE_SUBROUTINE:
5359 return ctx->ac.i32;
5360 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5361 return ctx->ac.f32;
5362 case GLSL_TYPE_INT64:
5363 case GLSL_TYPE_UINT64:
5364 return ctx->ac.i64;
5365 case GLSL_TYPE_DOUBLE:
5366 return ctx->ac.f64;
5367 default:
5368 unreachable("unknown GLSL type");
5369 }
5370 }
5371
5372 static LLVMTypeRef
5373 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5374 const struct glsl_type *type)
5375 {
5376 if (glsl_type_is_scalar(type)) {
5377 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5378 }
5379
5380 if (glsl_type_is_vector(type)) {
5381 return LLVMVectorType(
5382 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5383 glsl_get_vector_elements(type));
5384 }
5385
5386 if (glsl_type_is_matrix(type)) {
5387 return LLVMArrayType(
5388 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5389 glsl_get_matrix_columns(type));
5390 }
5391
5392 if (glsl_type_is_array(type)) {
5393 return LLVMArrayType(
5394 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5395 glsl_get_length(type));
5396 }
5397
5398 assert(glsl_type_is_struct(type));
5399
5400 LLVMTypeRef member_types[glsl_get_length(type)];
5401
5402 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5403 member_types[i] =
5404 glsl_to_llvm_type(ctx,
5405 glsl_get_struct_field(type, i));
5406 }
5407
5408 return LLVMStructTypeInContext(ctx->context, member_types,
5409 glsl_get_length(type), false);
5410 }
5411
5412 static void
5413 setup_locals(struct ac_nir_context *ctx,
5414 struct nir_function *func)
5415 {
5416 int i, j;
5417 ctx->num_locals = 0;
5418 nir_foreach_variable(variable, &func->impl->locals) {
5419 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5420 variable->data.driver_location = ctx->num_locals * 4;
5421 ctx->num_locals += attrib_count;
5422 }
5423 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5424 if (!ctx->locals)
5425 return;
5426
5427 for (i = 0; i < ctx->num_locals; i++) {
5428 for (j = 0; j < 4; j++) {
5429 ctx->locals[i * 4 + j] =
5430 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5431 }
5432 }
5433 }
5434
5435 static void
5436 setup_shared(struct ac_nir_context *ctx,
5437 struct nir_shader *nir)
5438 {
5439 nir_foreach_variable(variable, &nir->shared) {
5440 LLVMValueRef shared =
5441 LLVMAddGlobalInAddressSpace(
5442 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5443 variable->name ? variable->name : "",
5444 LOCAL_ADDR_SPACE);
5445 _mesa_hash_table_insert(ctx->vars, variable, shared);
5446 }
5447 }
5448
5449 static LLVMValueRef
5450 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5451 {
5452 v = ac_to_float(ctx, v);
5453 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5454 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5455 }
5456
5457
5458 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5459 LLVMValueRef src0, LLVMValueRef src1)
5460 {
5461 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5462 LLVMValueRef comp[2];
5463
5464 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5465 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5466 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5467 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5468 }
5469
5470 /* Initialize arguments for the shader export intrinsic */
5471 static void
5472 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5473 LLVMValueRef *values,
5474 unsigned target,
5475 struct ac_export_args *args)
5476 {
5477 /* Default is 0xf. Adjusted below depending on the format. */
5478 args->enabled_channels = 0xf;
5479
5480 /* Specify whether the EXEC mask represents the valid mask */
5481 args->valid_mask = 0;
5482
5483 /* Specify whether this is the last export */
5484 args->done = 0;
5485
5486 /* Specify the target we are exporting */
5487 args->target = target;
5488
5489 args->compr = false;
5490 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5491 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5492 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5493 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5494
5495 if (!values)
5496 return;
5497
5498 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5499 LLVMValueRef val[4];
5500 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5501 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5502 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5503 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5504
5505 switch(col_format) {
5506 case V_028714_SPI_SHADER_ZERO:
5507 args->enabled_channels = 0; /* writemask */
5508 args->target = V_008DFC_SQ_EXP_NULL;
5509 break;
5510
5511 case V_028714_SPI_SHADER_32_R:
5512 args->enabled_channels = 1;
5513 args->out[0] = values[0];
5514 break;
5515
5516 case V_028714_SPI_SHADER_32_GR:
5517 args->enabled_channels = 0x3;
5518 args->out[0] = values[0];
5519 args->out[1] = values[1];
5520 break;
5521
5522 case V_028714_SPI_SHADER_32_AR:
5523 args->enabled_channels = 0x9;
5524 args->out[0] = values[0];
5525 args->out[3] = values[3];
5526 break;
5527
5528 case V_028714_SPI_SHADER_FP16_ABGR:
5529 args->compr = 1;
5530
5531 for (unsigned chan = 0; chan < 2; chan++) {
5532 LLVMValueRef pack_args[2] = {
5533 values[2 * chan],
5534 values[2 * chan + 1]
5535 };
5536 LLVMValueRef packed;
5537
5538 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5539 args->out[chan] = packed;
5540 }
5541 break;
5542
5543 case V_028714_SPI_SHADER_UNORM16_ABGR:
5544 for (unsigned chan = 0; chan < 4; chan++) {
5545 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5546 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5547 LLVMConstReal(ctx->ac.f32, 65535), "");
5548 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5549 LLVMConstReal(ctx->ac.f32, 0.5), "");
5550 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5551 ctx->ac.i32, "");
5552 }
5553
5554 args->compr = 1;
5555 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5556 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5557 break;
5558
5559 case V_028714_SPI_SHADER_SNORM16_ABGR:
5560 for (unsigned chan = 0; chan < 4; chan++) {
5561 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5562 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5563 LLVMConstReal(ctx->ac.f32, 32767), "");
5564
5565 /* If positive, add 0.5, else add -0.5. */
5566 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5567 LLVMBuildSelect(ctx->builder,
5568 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5569 val[chan], ctx->ac.f32_0, ""),
5570 LLVMConstReal(ctx->ac.f32, 0.5),
5571 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5572 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5573 }
5574
5575 args->compr = 1;
5576 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5577 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5578 break;
5579
5580 case V_028714_SPI_SHADER_UINT16_ABGR: {
5581 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5582 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5583 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5584
5585 for (unsigned chan = 0; chan < 4; chan++) {
5586 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5587 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5588 }
5589
5590 args->compr = 1;
5591 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5592 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5593 break;
5594 }
5595
5596 case V_028714_SPI_SHADER_SINT16_ABGR: {
5597 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5598 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5599 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5600 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5601 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5602 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5603
5604 /* Clamp. */
5605 for (unsigned chan = 0; chan < 4; chan++) {
5606 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5607 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5608 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5609 }
5610
5611 args->compr = 1;
5612 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5613 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5614 break;
5615 }
5616
5617 default:
5618 case V_028714_SPI_SHADER_32_ABGR:
5619 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5620 break;
5621 }
5622 } else
5623 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5624
5625 for (unsigned i = 0; i < 4; ++i)
5626 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5627 }
5628
5629 static void
5630 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5631 bool export_prim_id,
5632 struct ac_vs_output_info *outinfo)
5633 {
5634 uint32_t param_count = 0;
5635 unsigned target;
5636 unsigned pos_idx, num_pos_exports = 0;
5637 struct ac_export_args args, pos_args[4] = {};
5638 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5639 int i;
5640
5641 if (ctx->options->key.has_multiview_view_index) {
5642 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5643 if(!*tmp_out) {
5644 for(unsigned i = 0; i < 4; ++i)
5645 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5646 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5647 }
5648
5649 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5650 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5651 }
5652
5653 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5654 sizeof(outinfo->vs_output_param_offset));
5655
5656 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5657 LLVMValueRef slots[8];
5658 unsigned j;
5659
5660 if (outinfo->cull_dist_mask)
5661 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5662
5663 i = VARYING_SLOT_CLIP_DIST0;
5664 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5665 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5666 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5667
5668 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5669 slots[i] = LLVMGetUndef(ctx->ac.f32);
5670
5671 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5672 target = V_008DFC_SQ_EXP_POS + 3;
5673 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5674 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5675 &args, sizeof(args));
5676 }
5677
5678 target = V_008DFC_SQ_EXP_POS + 2;
5679 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5680 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5681 &args, sizeof(args));
5682
5683 }
5684
5685 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5686 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5687 for (unsigned j = 0; j < 4; j++)
5688 pos_values[j] = LLVMBuildLoad(ctx->builder,
5689 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5690 }
5691 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5692
5693 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5694 outinfo->writes_pointsize = true;
5695 psize_value = LLVMBuildLoad(ctx->builder,
5696 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5697 }
5698
5699 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5700 outinfo->writes_layer = true;
5701 layer_value = LLVMBuildLoad(ctx->builder,
5702 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5703 }
5704
5705 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5706 outinfo->writes_viewport_index = true;
5707 viewport_index_value = LLVMBuildLoad(ctx->builder,
5708 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5709 }
5710
5711 if (outinfo->writes_pointsize ||
5712 outinfo->writes_layer ||
5713 outinfo->writes_viewport_index) {
5714 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5715 (outinfo->writes_layer == true ? 4 : 0));
5716 pos_args[1].valid_mask = 0;
5717 pos_args[1].done = 0;
5718 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5719 pos_args[1].compr = 0;
5720 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5721 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5722 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5723 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5724
5725 if (outinfo->writes_pointsize == true)
5726 pos_args[1].out[0] = psize_value;
5727 if (outinfo->writes_layer == true)
5728 pos_args[1].out[2] = layer_value;
5729 if (outinfo->writes_viewport_index == true) {
5730 if (ctx->options->chip_class >= GFX9) {
5731 /* GFX9 has the layer in out.z[10:0] and the viewport
5732 * index in out.z[19:16].
5733 */
5734 LLVMValueRef v = viewport_index_value;
5735 v = ac_to_integer(&ctx->ac, v);
5736 v = LLVMBuildShl(ctx->builder, v,
5737 LLVMConstInt(ctx->ac.i32, 16, false),
5738 "");
5739 v = LLVMBuildOr(ctx->builder, v,
5740 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5741
5742 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5743 pos_args[1].enabled_channels |= 1 << 2;
5744 } else {
5745 pos_args[1].out[3] = viewport_index_value;
5746 pos_args[1].enabled_channels |= 1 << 3;
5747 }
5748 }
5749 }
5750 for (i = 0; i < 4; i++) {
5751 if (pos_args[i].out[0])
5752 num_pos_exports++;
5753 }
5754
5755 pos_idx = 0;
5756 for (i = 0; i < 4; i++) {
5757 if (!pos_args[i].out[0])
5758 continue;
5759
5760 /* Specify the target we are exporting */
5761 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5762 if (pos_idx == num_pos_exports)
5763 pos_args[i].done = 1;
5764 ac_build_export(&ctx->ac, &pos_args[i]);
5765 }
5766
5767 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5768 LLVMValueRef values[4];
5769 if (!(ctx->output_mask & (1ull << i)))
5770 continue;
5771
5772 for (unsigned j = 0; j < 4; j++)
5773 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5774 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5775
5776 if (i == VARYING_SLOT_LAYER) {
5777 target = V_008DFC_SQ_EXP_PARAM + param_count;
5778 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5779 param_count++;
5780 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5781 target = V_008DFC_SQ_EXP_PARAM + param_count;
5782 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5783 param_count++;
5784 } else if (i >= VARYING_SLOT_VAR0) {
5785 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5786 target = V_008DFC_SQ_EXP_PARAM + param_count;
5787 outinfo->vs_output_param_offset[i] = param_count;
5788 param_count++;
5789 } else
5790 continue;
5791
5792 si_llvm_init_export_args(ctx, values, target, &args);
5793
5794 if (target >= V_008DFC_SQ_EXP_POS &&
5795 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5796 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5797 &args, sizeof(args));
5798 } else {
5799 ac_build_export(&ctx->ac, &args);
5800 }
5801 }
5802
5803 if (export_prim_id) {
5804 LLVMValueRef values[4];
5805 target = V_008DFC_SQ_EXP_PARAM + param_count;
5806 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5807 param_count++;
5808
5809 values[0] = ctx->vs_prim_id;
5810 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5811 ctx->shader_info->vs.vgpr_comp_cnt);
5812 for (unsigned j = 1; j < 4; j++)
5813 values[j] = ctx->ac.f32_0;
5814 si_llvm_init_export_args(ctx, values, target, &args);
5815 ac_build_export(&ctx->ac, &args);
5816 outinfo->export_prim_id = true;
5817 }
5818
5819 outinfo->pos_exports = num_pos_exports;
5820 outinfo->param_exports = param_count;
5821 }
5822
5823 static void
5824 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5825 struct ac_es_output_info *outinfo)
5826 {
5827 int j;
5828 uint64_t max_output_written = 0;
5829 LLVMValueRef lds_base = NULL;
5830
5831 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5832 int param_index;
5833 int length = 4;
5834
5835 if (!(ctx->output_mask & (1ull << i)))
5836 continue;
5837
5838 if (i == VARYING_SLOT_CLIP_DIST0)
5839 length = ctx->num_output_clips + ctx->num_output_culls;
5840
5841 param_index = shader_io_get_unique_index(i);
5842
5843 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5844 }
5845
5846 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5847
5848 if (ctx->ac.chip_class >= GFX9) {
5849 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5850 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5851 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5852 LLVMConstInt(ctx->ac.i32, 24, false),
5853 LLVMConstInt(ctx->ac.i32, 4, false), false);
5854 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5855 LLVMBuildMul(ctx->ac.builder, wave_idx,
5856 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5857 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5858 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5859 }
5860
5861 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5862 LLVMValueRef dw_addr;
5863 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5864 int param_index;
5865 int length = 4;
5866
5867 if (!(ctx->output_mask & (1ull << i)))
5868 continue;
5869
5870 if (i == VARYING_SLOT_CLIP_DIST0)
5871 length = ctx->num_output_clips + ctx->num_output_culls;
5872
5873 param_index = shader_io_get_unique_index(i);
5874
5875 if (lds_base) {
5876 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5877 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
5878 "");
5879 }
5880 for (j = 0; j < length; j++) {
5881 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5882 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
5883
5884 if (ctx->ac.chip_class >= GFX9) {
5885 ac_lds_store(&ctx->ac, dw_addr,
5886 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5887 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5888 } else {
5889 ac_build_buffer_store_dword(&ctx->ac,
5890 ctx->esgs_ring,
5891 out_val, 1,
5892 NULL, ctx->es2gs_offset,
5893 (4 * param_index + j) * 4,
5894 1, 1, true, true);
5895 }
5896 }
5897 }
5898 }
5899
5900 static void
5901 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5902 {
5903 LLVMValueRef vertex_id = ctx->rel_auto_id;
5904 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5905 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5906 vertex_dw_stride, "");
5907
5908 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5909 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5910 int length = 4;
5911
5912 if (!(ctx->output_mask & (1ull << i)))
5913 continue;
5914
5915 if (i == VARYING_SLOT_CLIP_DIST0)
5916 length = ctx->num_output_clips + ctx->num_output_culls;
5917 int param = shader_io_get_unique_index(i);
5918 mark_tess_output(ctx, false, param);
5919 if (length > 4)
5920 mark_tess_output(ctx, false, param + 1);
5921 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5922 LLVMConstInt(ctx->ac.i32, param * 4, false),
5923 "");
5924 for (unsigned j = 0; j < length; j++) {
5925 ac_lds_store(&ctx->ac, dw_addr,
5926 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5927 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5928 }
5929 }
5930 }
5931
5932 struct ac_build_if_state
5933 {
5934 struct nir_to_llvm_context *ctx;
5935 LLVMValueRef condition;
5936 LLVMBasicBlockRef entry_block;
5937 LLVMBasicBlockRef true_block;
5938 LLVMBasicBlockRef false_block;
5939 LLVMBasicBlockRef merge_block;
5940 };
5941
5942 static LLVMBasicBlockRef
5943 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5944 {
5945 LLVMBasicBlockRef current_block;
5946 LLVMBasicBlockRef next_block;
5947 LLVMBasicBlockRef new_block;
5948
5949 /* get current basic block */
5950 current_block = LLVMGetInsertBlock(ctx->builder);
5951
5952 /* chqeck if there's another block after this one */
5953 next_block = LLVMGetNextBasicBlock(current_block);
5954 if (next_block) {
5955 /* insert the new block before the next block */
5956 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5957 }
5958 else {
5959 /* append new block after current block */
5960 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5961 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5962 }
5963 return new_block;
5964 }
5965
5966 static void
5967 ac_nir_build_if(struct ac_build_if_state *ifthen,
5968 struct nir_to_llvm_context *ctx,
5969 LLVMValueRef condition)
5970 {
5971 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5972
5973 memset(ifthen, 0, sizeof *ifthen);
5974 ifthen->ctx = ctx;
5975 ifthen->condition = condition;
5976 ifthen->entry_block = block;
5977
5978 /* create endif/merge basic block for the phi functions */
5979 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5980
5981 /* create/insert true_block before merge_block */
5982 ifthen->true_block =
5983 LLVMInsertBasicBlockInContext(ctx->context,
5984 ifthen->merge_block,
5985 "if-true-block");
5986
5987 /* successive code goes into the true block */
5988 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5989 }
5990
5991 /**
5992 * End a conditional.
5993 */
5994 static void
5995 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5996 {
5997 LLVMBuilderRef builder = ifthen->ctx->builder;
5998
5999 /* Insert branch to the merge block from current block */
6000 LLVMBuildBr(builder, ifthen->merge_block);
6001
6002 /*
6003 * Now patch in the various branch instructions.
6004 */
6005
6006 /* Insert the conditional branch instruction at the end of entry_block */
6007 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6008 if (ifthen->false_block) {
6009 /* we have an else clause */
6010 LLVMBuildCondBr(builder, ifthen->condition,
6011 ifthen->true_block, ifthen->false_block);
6012 }
6013 else {
6014 /* no else clause */
6015 LLVMBuildCondBr(builder, ifthen->condition,
6016 ifthen->true_block, ifthen->merge_block);
6017 }
6018
6019 /* Resume building code at end of the ifthen->merge_block */
6020 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6021 }
6022
6023 static void
6024 write_tess_factors(struct nir_to_llvm_context *ctx)
6025 {
6026 unsigned stride, outer_comps, inner_comps;
6027 struct ac_build_if_state if_ctx, inner_if_ctx;
6028 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6029 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6030 unsigned tess_inner_index, tess_outer_index;
6031 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6032 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6033 int i;
6034 emit_barrier(ctx);
6035
6036 switch (ctx->options->key.tcs.primitive_mode) {
6037 case GL_ISOLINES:
6038 stride = 2;
6039 outer_comps = 2;
6040 inner_comps = 0;
6041 break;
6042 case GL_TRIANGLES:
6043 stride = 4;
6044 outer_comps = 3;
6045 inner_comps = 1;
6046 break;
6047 case GL_QUADS:
6048 stride = 6;
6049 outer_comps = 4;
6050 inner_comps = 2;
6051 break;
6052 default:
6053 return;
6054 }
6055
6056 ac_nir_build_if(&if_ctx, ctx,
6057 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6058 invocation_id, ctx->ac.i32_0, ""));
6059
6060 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6061 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6062
6063 mark_tess_output(ctx, true, tess_inner_index);
6064 mark_tess_output(ctx, true, tess_outer_index);
6065 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6066 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6067 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6068 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6069 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6070
6071 for (i = 0; i < 4; i++) {
6072 inner[i] = LLVMGetUndef(ctx->ac.i32);
6073 outer[i] = LLVMGetUndef(ctx->ac.i32);
6074 }
6075
6076 // LINES reverseal
6077 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6078 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6079 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6080 LLVMConstInt(ctx->ac.i32, 1, false), "");
6081 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6082 } else {
6083 for (i = 0; i < outer_comps; i++) {
6084 outer[i] = out[i] =
6085 ac_lds_load(&ctx->ac, lds_outer);
6086 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6087 LLVMConstInt(ctx->ac.i32, 1, false), "");
6088 }
6089 for (i = 0; i < inner_comps; i++) {
6090 inner[i] = out[outer_comps+i] =
6091 ac_lds_load(&ctx->ac, lds_inner);
6092 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6093 LLVMConstInt(ctx->ac.i32, 1, false), "");
6094 }
6095 }
6096
6097 /* Convert the outputs to vectors for stores. */
6098 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6099 vec1 = NULL;
6100
6101 if (stride > 4)
6102 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6103
6104
6105 buffer = ctx->hs_ring_tess_factor;
6106 tf_base = ctx->tess_factor_offset;
6107 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6108 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6109 unsigned tf_offset = 0;
6110
6111 if (ctx->options->chip_class <= VI) {
6112 ac_nir_build_if(&inner_if_ctx, ctx,
6113 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6114 rel_patch_id, ctx->ac.i32_0, ""));
6115
6116 /* Store the dynamic HS control word. */
6117 ac_build_buffer_store_dword(&ctx->ac, buffer,
6118 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6119 1, ctx->ac.i32_0, tf_base,
6120 0, 1, 0, true, false);
6121 tf_offset += 4;
6122
6123 ac_nir_build_endif(&inner_if_ctx);
6124 }
6125
6126 /* Store the tessellation factors. */
6127 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6128 MIN2(stride, 4), byteoffset, tf_base,
6129 tf_offset, 1, 0, true, false);
6130 if (vec1)
6131 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6132 stride - 4, byteoffset, tf_base,
6133 16 + tf_offset, 1, 0, true, false);
6134
6135 //store to offchip for TES to read - only if TES reads them
6136 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6137 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6138 LLVMValueRef tf_inner_offset;
6139 unsigned param_outer, param_inner;
6140
6141 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6142 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6143 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6144
6145 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6146 util_next_power_of_two(outer_comps));
6147
6148 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6149 outer_comps, tf_outer_offset,
6150 ctx->oc_lds, 0, 1, 0, true, false);
6151 if (inner_comps) {
6152 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6153 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6154 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6155
6156 inner_vec = inner_comps == 1 ? inner[0] :
6157 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6158 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6159 inner_comps, tf_inner_offset,
6160 ctx->oc_lds, 0, 1, 0, true, false);
6161 }
6162 }
6163 ac_nir_build_endif(&if_ctx);
6164 }
6165
6166 static void
6167 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6168 {
6169 write_tess_factors(ctx);
6170 }
6171
6172 static bool
6173 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6174 LLVMValueRef *color, unsigned param, bool is_last,
6175 struct ac_export_args *args)
6176 {
6177 /* Export */
6178 si_llvm_init_export_args(ctx, color, param,
6179 args);
6180
6181 if (is_last) {
6182 args->valid_mask = 1; /* whether the EXEC mask is valid */
6183 args->done = 1; /* DONE bit */
6184 } else if (!args->enabled_channels)
6185 return false; /* unnecessary NULL export */
6186
6187 return true;
6188 }
6189
6190 static void
6191 si_export_mrt_z(struct nir_to_llvm_context *ctx,
6192 LLVMValueRef depth, LLVMValueRef stencil,
6193 LLVMValueRef samplemask)
6194 {
6195 struct ac_export_args args;
6196
6197 args.enabled_channels = 0;
6198 args.valid_mask = 1;
6199 args.done = 1;
6200 args.target = V_008DFC_SQ_EXP_MRTZ;
6201 args.compr = false;
6202
6203 args.out[0] = LLVMGetUndef(ctx->ac.f32); /* R, depth */
6204 args.out[1] = LLVMGetUndef(ctx->ac.f32); /* G, stencil test val[0:7], stencil op val[8:15] */
6205 args.out[2] = LLVMGetUndef(ctx->ac.f32); /* B, sample mask */
6206 args.out[3] = LLVMGetUndef(ctx->ac.f32); /* A, alpha to mask */
6207
6208 if (depth) {
6209 args.out[0] = depth;
6210 args.enabled_channels |= 0x1;
6211 }
6212
6213 if (stencil) {
6214 args.out[1] = stencil;
6215 args.enabled_channels |= 0x2;
6216 }
6217
6218 if (samplemask) {
6219 args.out[2] = samplemask;
6220 args.enabled_channels |= 0x4;
6221 }
6222
6223 /* SI (except OLAND and HAINAN) has a bug that it only looks
6224 * at the X writemask component. */
6225 if (ctx->options->chip_class == SI &&
6226 ctx->options->family != CHIP_OLAND &&
6227 ctx->options->family != CHIP_HAINAN)
6228 args.enabled_channels |= 0x1;
6229
6230 ac_build_export(&ctx->ac, &args);
6231 }
6232
6233 static void
6234 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6235 {
6236 unsigned index = 0;
6237 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6238 struct ac_export_args color_args[8];
6239
6240 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6241 LLVMValueRef values[4];
6242
6243 if (!(ctx->output_mask & (1ull << i)))
6244 continue;
6245
6246 if (i == FRAG_RESULT_DEPTH) {
6247 ctx->shader_info->fs.writes_z = true;
6248 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6249 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6250 } else if (i == FRAG_RESULT_STENCIL) {
6251 ctx->shader_info->fs.writes_stencil = true;
6252 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6253 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6254 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6255 ctx->shader_info->fs.writes_sample_mask = true;
6256 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6257 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6258 } else {
6259 bool last = false;
6260 for (unsigned j = 0; j < 4; j++)
6261 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6262 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6263
6264 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6265 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6266
6267 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6268 if (ret)
6269 index++;
6270 }
6271 }
6272
6273 for (unsigned i = 0; i < index; i++)
6274 ac_build_export(&ctx->ac, &color_args[i]);
6275 if (depth || stencil || samplemask)
6276 si_export_mrt_z(ctx, depth, stencil, samplemask);
6277 else if (!index) {
6278 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6279 ac_build_export(&ctx->ac, &color_args[0]);
6280 }
6281
6282 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6283 }
6284
6285 static void
6286 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6287 {
6288 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6289 }
6290
6291 static void
6292 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6293 LLVMValueRef *addrs)
6294 {
6295 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6296
6297 switch (ctx->stage) {
6298 case MESA_SHADER_VERTEX:
6299 if (ctx->options->key.vs.as_ls)
6300 handle_ls_outputs_post(ctx);
6301 else if (ctx->options->key.vs.as_es)
6302 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6303 else
6304 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6305 &ctx->shader_info->vs.outinfo);
6306 break;
6307 case MESA_SHADER_FRAGMENT:
6308 handle_fs_outputs_post(ctx);
6309 break;
6310 case MESA_SHADER_GEOMETRY:
6311 emit_gs_epilogue(ctx);
6312 break;
6313 case MESA_SHADER_TESS_CTRL:
6314 handle_tcs_outputs_post(ctx);
6315 break;
6316 case MESA_SHADER_TESS_EVAL:
6317 if (ctx->options->key.tes.as_es)
6318 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6319 else
6320 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6321 &ctx->shader_info->tes.outinfo);
6322 break;
6323 default:
6324 break;
6325 }
6326 }
6327
6328 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6329 {
6330 LLVMPassManagerRef passmgr;
6331 /* Create the pass manager */
6332 passmgr = LLVMCreateFunctionPassManagerForModule(
6333 ctx->module);
6334
6335 /* This pass should eliminate all the load and store instructions */
6336 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6337
6338 /* Add some optimization passes */
6339 LLVMAddScalarReplAggregatesPass(passmgr);
6340 LLVMAddLICMPass(passmgr);
6341 LLVMAddAggressiveDCEPass(passmgr);
6342 LLVMAddCFGSimplificationPass(passmgr);
6343 LLVMAddInstructionCombiningPass(passmgr);
6344
6345 /* Run the pass */
6346 LLVMInitializeFunctionPassManager(passmgr);
6347 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6348 LLVMFinalizeFunctionPassManager(passmgr);
6349
6350 LLVMDisposeBuilder(ctx->builder);
6351 LLVMDisposePassManager(passmgr);
6352 }
6353
6354 static void
6355 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6356 {
6357 struct ac_vs_output_info *outinfo;
6358
6359 switch (ctx->stage) {
6360 case MESA_SHADER_FRAGMENT:
6361 case MESA_SHADER_COMPUTE:
6362 case MESA_SHADER_TESS_CTRL:
6363 case MESA_SHADER_GEOMETRY:
6364 return;
6365 case MESA_SHADER_VERTEX:
6366 if (ctx->options->key.vs.as_ls ||
6367 ctx->options->key.vs.as_es)
6368 return;
6369 outinfo = &ctx->shader_info->vs.outinfo;
6370 break;
6371 case MESA_SHADER_TESS_EVAL:
6372 if (ctx->options->key.vs.as_es)
6373 return;
6374 outinfo = &ctx->shader_info->tes.outinfo;
6375 break;
6376 default:
6377 unreachable("Unhandled shader type");
6378 }
6379
6380 ac_optimize_vs_outputs(&ctx->ac,
6381 ctx->main_function,
6382 outinfo->vs_output_param_offset,
6383 VARYING_SLOT_MAX,
6384 &outinfo->param_exports);
6385 }
6386
6387 static void
6388 ac_setup_rings(struct nir_to_llvm_context *ctx)
6389 {
6390 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6391 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6392 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6393 }
6394
6395 if (ctx->is_gs_copy_shader) {
6396 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6397 }
6398 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6399 LLVMValueRef tmp;
6400 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6401 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6402
6403 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6404
6405 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6406 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6407 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6408 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6409 }
6410
6411 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6412 ctx->stage == MESA_SHADER_TESS_EVAL) {
6413 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6414 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6415 }
6416 }
6417
6418 static unsigned
6419 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6420 const struct nir_shader *nir)
6421 {
6422 switch (nir->info.stage) {
6423 case MESA_SHADER_TESS_CTRL:
6424 return chip_class >= CIK ? 128 : 64;
6425 case MESA_SHADER_GEOMETRY:
6426 return chip_class >= GFX9 ? 128 : 64;
6427 case MESA_SHADER_COMPUTE:
6428 break;
6429 default:
6430 return 0;
6431 }
6432
6433 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6434 nir->info.cs.local_size[1] *
6435 nir->info.cs.local_size[2];
6436 return max_workgroup_size;
6437 }
6438
6439 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6440 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6441 {
6442 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6443 LLVMConstInt(ctx->ac.i32, 8, false),
6444 LLVMConstInt(ctx->ac.i32, 8, false), false);
6445 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6446 LLVMConstInt(ctx->ac.i32, 0, false), "");
6447 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6448 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6449 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6450 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6451 }
6452
6453 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6454 {
6455 for(int i = 5; i >= 0; --i) {
6456 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6457 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6458 LLVMConstInt(ctx->ac.i32, 16, false), false);
6459 }
6460
6461 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6462 LLVMConstInt(ctx->ac.i32, 16, false),
6463 LLVMConstInt(ctx->ac.i32, 8, false), false);
6464 }
6465
6466 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6467 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6468 {
6469 struct ac_nir_context ctx = {};
6470 struct nir_function *func;
6471
6472 ctx.ac = *ac;
6473 ctx.abi = abi;
6474
6475 ctx.nctx = nctx;
6476 if (nctx)
6477 nctx->nir = &ctx;
6478
6479 ctx.stage = nir->info.stage;
6480
6481 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6482
6483 nir_foreach_variable(variable, &nir->outputs)
6484 handle_shader_output_decl(&ctx, nir, variable);
6485
6486 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6487 _mesa_key_pointer_equal);
6488 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6489 _mesa_key_pointer_equal);
6490 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6491 _mesa_key_pointer_equal);
6492
6493 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6494
6495 setup_locals(&ctx, func);
6496
6497 if (nir->info.stage == MESA_SHADER_COMPUTE)
6498 setup_shared(&ctx, nir);
6499
6500 visit_cf_list(&ctx, &func->impl->body);
6501 phi_post_pass(&ctx);
6502
6503 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6504 ctx.outputs);
6505
6506 free(ctx.locals);
6507 ralloc_free(ctx.defs);
6508 ralloc_free(ctx.phis);
6509 ralloc_free(ctx.vars);
6510
6511 if (nctx)
6512 nctx->nir = NULL;
6513 }
6514
6515 static
6516 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6517 struct nir_shader *const *shaders,
6518 int shader_count,
6519 struct ac_shader_variant_info *shader_info,
6520 const struct ac_nir_compiler_options *options)
6521 {
6522 struct nir_to_llvm_context ctx = {0};
6523 unsigned i;
6524 ctx.options = options;
6525 ctx.shader_info = shader_info;
6526 ctx.context = LLVMContextCreate();
6527 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6528
6529 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6530 ctx.ac.module = ctx.module;
6531 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6532
6533 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6534 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6535 LLVMSetDataLayout(ctx.module, data_layout_str);
6536 LLVMDisposeTargetData(data_layout);
6537 LLVMDisposeMessage(data_layout_str);
6538
6539 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6540 ctx.ac.builder = ctx.builder;
6541
6542 memset(shader_info, 0, sizeof(*shader_info));
6543
6544 for(int i = 0; i < shader_count; ++i)
6545 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6546
6547 for (i = 0; i < AC_UD_MAX_SETS; i++)
6548 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6549 for (i = 0; i < AC_UD_MAX_UD; i++)
6550 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6551
6552 ctx.max_workgroup_size = 0;
6553 for (int i = 0; i < shader_count; ++i) {
6554 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6555 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6556 shaders[i]));
6557 }
6558
6559 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6560 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6561
6562 ctx.abi.inputs = &ctx.inputs[0];
6563 ctx.abi.emit_outputs = handle_shader_outputs_post;
6564 ctx.abi.emit_vertex = visit_emit_vertex;
6565 ctx.abi.load_ssbo = radv_load_ssbo;
6566 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6567 ctx.abi.clamp_shadow_reference = false;
6568
6569 if (shader_count >= 2)
6570 ac_init_exec_full_mask(&ctx.ac);
6571
6572 if (ctx.ac.chip_class == GFX9 &&
6573 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6574 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6575
6576 for(int i = 0; i < shader_count; ++i) {
6577 ctx.stage = shaders[i]->info.stage;
6578 ctx.output_mask = 0;
6579 ctx.tess_outputs_written = 0;
6580 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6581 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6582
6583 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6584 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6585
6586 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6587 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6588 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6589 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6590 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6591 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6592 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6593 if (shader_info->info.vs.needs_instance_id) {
6594 ctx.shader_info->vs.vgpr_comp_cnt =
6595 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6596 }
6597 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6598 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6599 }
6600
6601 if (i)
6602 emit_barrier(&ctx);
6603
6604 ac_setup_rings(&ctx);
6605
6606 LLVMBasicBlockRef merge_block;
6607 if (shader_count >= 2) {
6608 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6609 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6610 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6611
6612 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6613 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6614 LLVMConstInt(ctx.ac.i32, 8, false), false);
6615 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6616 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6617 thread_id, count, "");
6618 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6619
6620 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6621 }
6622
6623 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6624 handle_fs_inputs(&ctx, shaders[i]);
6625 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6626 handle_vs_inputs(&ctx, shaders[i]);
6627 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6628 prepare_gs_input_vgprs(&ctx);
6629
6630 nir_foreach_variable(variable, &shaders[i]->outputs)
6631 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6632
6633 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6634
6635 if (shader_count >= 2) {
6636 LLVMBuildBr(ctx.ac.builder, merge_block);
6637 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6638 }
6639
6640 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6641 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6642 shaders[i]->info.cull_distance_array_size > 4;
6643 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6644 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6645 shaders[i]->info.gs.vertices_out;
6646 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6647 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6648 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6649 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6650 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6651 }
6652 }
6653
6654 LLVMBuildRetVoid(ctx.builder);
6655
6656 ac_llvm_finalize_module(&ctx);
6657
6658 if (shader_count == 1)
6659 ac_nir_eliminate_const_vs_outputs(&ctx);
6660
6661 return ctx.module;
6662 }
6663
6664 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6665 {
6666 unsigned *retval = (unsigned *)context;
6667 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6668 char *description = LLVMGetDiagInfoDescription(di);
6669
6670 if (severity == LLVMDSError) {
6671 *retval = 1;
6672 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6673 description);
6674 }
6675
6676 LLVMDisposeMessage(description);
6677 }
6678
6679 static unsigned ac_llvm_compile(LLVMModuleRef M,
6680 struct ac_shader_binary *binary,
6681 LLVMTargetMachineRef tm)
6682 {
6683 unsigned retval = 0;
6684 char *err;
6685 LLVMContextRef llvm_ctx;
6686 LLVMMemoryBufferRef out_buffer;
6687 unsigned buffer_size;
6688 const char *buffer_data;
6689 LLVMBool mem_err;
6690
6691 /* Setup Diagnostic Handler*/
6692 llvm_ctx = LLVMGetModuleContext(M);
6693
6694 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6695 &retval);
6696
6697 /* Compile IR*/
6698 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6699 &err, &out_buffer);
6700
6701 /* Process Errors/Warnings */
6702 if (mem_err) {
6703 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6704 free(err);
6705 retval = 1;
6706 goto out;
6707 }
6708
6709 /* Extract Shader Code*/
6710 buffer_size = LLVMGetBufferSize(out_buffer);
6711 buffer_data = LLVMGetBufferStart(out_buffer);
6712
6713 ac_elf_read(buffer_data, buffer_size, binary);
6714
6715 /* Clean up */
6716 LLVMDisposeMemoryBuffer(out_buffer);
6717
6718 out:
6719 return retval;
6720 }
6721
6722 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6723 LLVMModuleRef llvm_module,
6724 struct ac_shader_binary *binary,
6725 struct ac_shader_config *config,
6726 struct ac_shader_variant_info *shader_info,
6727 gl_shader_stage stage,
6728 bool dump_shader, bool supports_spill)
6729 {
6730 if (dump_shader)
6731 ac_dump_module(llvm_module);
6732
6733 memset(binary, 0, sizeof(*binary));
6734 int v = ac_llvm_compile(llvm_module, binary, tm);
6735 if (v) {
6736 fprintf(stderr, "compile failed\n");
6737 }
6738
6739 if (dump_shader)
6740 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6741
6742 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6743
6744 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6745 LLVMDisposeModule(llvm_module);
6746 LLVMContextDispose(ctx);
6747
6748 if (stage == MESA_SHADER_FRAGMENT) {
6749 shader_info->num_input_vgprs = 0;
6750 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6751 shader_info->num_input_vgprs += 2;
6752 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6753 shader_info->num_input_vgprs += 2;
6754 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6755 shader_info->num_input_vgprs += 2;
6756 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6757 shader_info->num_input_vgprs += 3;
6758 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6759 shader_info->num_input_vgprs += 2;
6760 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6761 shader_info->num_input_vgprs += 2;
6762 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6763 shader_info->num_input_vgprs += 2;
6764 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6765 shader_info->num_input_vgprs += 1;
6766 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6767 shader_info->num_input_vgprs += 1;
6768 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6769 shader_info->num_input_vgprs += 1;
6770 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6771 shader_info->num_input_vgprs += 1;
6772 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6773 shader_info->num_input_vgprs += 1;
6774 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6775 shader_info->num_input_vgprs += 1;
6776 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6777 shader_info->num_input_vgprs += 1;
6778 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6779 shader_info->num_input_vgprs += 1;
6780 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6781 shader_info->num_input_vgprs += 1;
6782 }
6783 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6784
6785 /* +3 for scratch wave offset and VCC */
6786 config->num_sgprs = MAX2(config->num_sgprs,
6787 shader_info->num_input_sgprs + 3);
6788 }
6789
6790 static void
6791 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6792 {
6793 switch (nir->info.stage) {
6794 case MESA_SHADER_COMPUTE:
6795 for (int i = 0; i < 3; ++i)
6796 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6797 break;
6798 case MESA_SHADER_FRAGMENT:
6799 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6800 break;
6801 case MESA_SHADER_GEOMETRY:
6802 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6803 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6804 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6805 shader_info->gs.invocations = nir->info.gs.invocations;
6806 break;
6807 case MESA_SHADER_TESS_EVAL:
6808 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6809 shader_info->tes.spacing = nir->info.tess.spacing;
6810 shader_info->tes.ccw = nir->info.tess.ccw;
6811 shader_info->tes.point_mode = nir->info.tess.point_mode;
6812 shader_info->tes.as_es = options->key.tes.as_es;
6813 break;
6814 case MESA_SHADER_TESS_CTRL:
6815 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6816 break;
6817 case MESA_SHADER_VERTEX:
6818 shader_info->vs.as_es = options->key.vs.as_es;
6819 shader_info->vs.as_ls = options->key.vs.as_ls;
6820 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6821 if (options->key.vs.as_ls)
6822 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6823 break;
6824 default:
6825 break;
6826 }
6827 }
6828
6829 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6830 struct ac_shader_binary *binary,
6831 struct ac_shader_config *config,
6832 struct ac_shader_variant_info *shader_info,
6833 struct nir_shader *const *nir,
6834 int nir_count,
6835 const struct ac_nir_compiler_options *options,
6836 bool dump_shader)
6837 {
6838
6839 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6840 options);
6841
6842 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6843 for (int i = 0; i < nir_count; ++i)
6844 ac_fill_shader_info(shader_info, nir[i], options);
6845 }
6846
6847 static void
6848 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6849 {
6850 LLVMValueRef args[9];
6851 args[0] = ctx->gsvs_ring;
6852 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6853 args[3] = ctx->ac.i32_0;
6854 args[4] = ctx->ac.i32_1; /* OFFEN */
6855 args[5] = ctx->ac.i32_0; /* IDXEN */
6856 args[6] = ctx->ac.i32_1; /* GLC */
6857 args[7] = ctx->ac.i32_1; /* SLC */
6858 args[8] = ctx->ac.i32_0; /* TFE */
6859
6860 int idx = 0;
6861
6862 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6863 int length = 4;
6864 int slot = idx;
6865 int slot_inc = 1;
6866 if (!(ctx->output_mask & (1ull << i)))
6867 continue;
6868
6869 if (i == VARYING_SLOT_CLIP_DIST0) {
6870 /* unpack clip and cull from a single set of slots */
6871 length = ctx->num_output_clips + ctx->num_output_culls;
6872 if (length > 4)
6873 slot_inc = 2;
6874 }
6875
6876 for (unsigned j = 0; j < length; j++) {
6877 LLVMValueRef value;
6878 args[2] = LLVMConstInt(ctx->ac.i32,
6879 (slot * 4 + j) *
6880 ctx->gs_max_out_vertices * 16 * 4, false);
6881
6882 value = ac_build_intrinsic(&ctx->ac,
6883 "llvm.SI.buffer.load.dword.i32.i32",
6884 ctx->ac.i32, args, 9,
6885 AC_FUNC_ATTR_READONLY |
6886 AC_FUNC_ATTR_LEGACY);
6887
6888 LLVMBuildStore(ctx->builder,
6889 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6890 }
6891 idx += slot_inc;
6892 }
6893 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6894 }
6895
6896 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6897 struct nir_shader *geom_shader,
6898 struct ac_shader_binary *binary,
6899 struct ac_shader_config *config,
6900 struct ac_shader_variant_info *shader_info,
6901 const struct ac_nir_compiler_options *options,
6902 bool dump_shader)
6903 {
6904 struct nir_to_llvm_context ctx = {0};
6905 ctx.context = LLVMContextCreate();
6906 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6907 ctx.options = options;
6908 ctx.shader_info = shader_info;
6909
6910 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6911 ctx.ac.module = ctx.module;
6912
6913 ctx.is_gs_copy_shader = true;
6914 LLVMSetTarget(ctx.module, "amdgcn--");
6915
6916 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6917 ctx.ac.builder = ctx.builder;
6918 ctx.stage = MESA_SHADER_VERTEX;
6919
6920 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
6921
6922 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6923 ac_setup_rings(&ctx);
6924
6925 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6926 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6927
6928 struct ac_nir_context nir_ctx = {};
6929 nir_ctx.ac = ctx.ac;
6930 nir_ctx.abi = &ctx.abi;
6931
6932 nir_ctx.nctx = &ctx;
6933 ctx.nir = &nir_ctx;
6934
6935 nir_foreach_variable(variable, &geom_shader->outputs) {
6936 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
6937 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6938 }
6939
6940 ac_gs_copy_shader_emit(&ctx);
6941
6942 ctx.nir = NULL;
6943
6944 LLVMBuildRetVoid(ctx.builder);
6945
6946 ac_llvm_finalize_module(&ctx);
6947
6948 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6949 MESA_SHADER_VERTEX,
6950 dump_shader, options->supports_spill);
6951 }