2 * Copyright © 2016 Bas Nieuwenhuizen
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
38 enum radeon_llvm_calling_convention
{
39 RADEON_LLVM_AMDGPU_VS
= 87,
40 RADEON_LLVM_AMDGPU_GS
= 88,
41 RADEON_LLVM_AMDGPU_PS
= 89,
42 RADEON_LLVM_AMDGPU_CS
= 90,
43 RADEON_LLVM_AMDGPU_HS
= 93,
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
52 struct nir_to_llvm_context
;
54 struct ac_nir_context
{
55 struct ac_llvm_context ac
;
56 struct ac_shader_abi
*abi
;
58 gl_shader_stage stage
;
60 struct hash_table
*defs
;
61 struct hash_table
*phis
;
62 struct hash_table
*vars
;
64 LLVMValueRef main_function
;
65 LLVMBasicBlockRef continue_block
;
66 LLVMBasicBlockRef break_block
;
68 LLVMValueRef outputs
[RADEON_LLVM_MAX_OUTPUTS
* 4];
73 struct nir_to_llvm_context
*nctx
; /* TODO get rid of this */
76 struct nir_to_llvm_context
{
77 struct ac_llvm_context ac
;
78 const struct ac_nir_compiler_options
*options
;
79 struct ac_shader_variant_info
*shader_info
;
80 struct ac_shader_abi abi
;
81 struct ac_nir_context
*nir
;
83 unsigned max_workgroup_size
;
84 LLVMContextRef context
;
86 LLVMBuilderRef builder
;
87 LLVMValueRef main_function
;
89 struct hash_table
*defs
;
90 struct hash_table
*phis
;
92 LLVMValueRef descriptor_sets
[AC_UD_MAX_SETS
];
93 LLVMValueRef ring_offsets
;
94 LLVMValueRef push_constants
;
95 LLVMValueRef view_index
;
96 LLVMValueRef num_work_groups
;
97 LLVMValueRef workgroup_ids
[3];
98 LLVMValueRef local_invocation_ids
;
101 LLVMValueRef vertex_buffers
;
102 LLVMValueRef rel_auto_id
;
103 LLVMValueRef vs_prim_id
;
104 LLVMValueRef ls_out_layout
;
105 LLVMValueRef es2gs_offset
;
107 LLVMValueRef tcs_offchip_layout
;
108 LLVMValueRef tcs_out_offsets
;
109 LLVMValueRef tcs_out_layout
;
110 LLVMValueRef tcs_in_layout
;
112 LLVMValueRef merged_wave_info
;
113 LLVMValueRef tess_factor_offset
;
114 LLVMValueRef tcs_patch_id
;
115 LLVMValueRef tcs_rel_ids
;
116 LLVMValueRef tes_rel_patch_id
;
117 LLVMValueRef tes_patch_id
;
121 LLVMValueRef gsvs_ring_stride
;
122 LLVMValueRef gsvs_num_entries
;
123 LLVMValueRef gs2vs_offset
;
124 LLVMValueRef gs_wave_id
;
125 LLVMValueRef gs_vtx_offset
[6];
127 LLVMValueRef esgs_ring
;
128 LLVMValueRef gsvs_ring
;
129 LLVMValueRef hs_ring_tess_offchip
;
130 LLVMValueRef hs_ring_tess_factor
;
132 LLVMValueRef prim_mask
;
133 LLVMValueRef sample_pos_offset
;
134 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
135 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
137 gl_shader_stage stage
;
139 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
142 uint64_t output_mask
;
143 uint8_t num_output_clips
;
144 uint8_t num_output_culls
;
146 bool is_gs_copy_shader
;
147 LLVMValueRef gs_next_vertex
;
148 unsigned gs_max_out_vertices
;
150 unsigned tes_primitive_mode
;
151 uint64_t tess_outputs_written
;
152 uint64_t tess_patch_outputs_written
;
154 uint32_t tcs_patch_outputs_read
;
155 uint64_t tcs_outputs_read
;
158 static inline struct nir_to_llvm_context
*
159 nir_to_llvm_context_from_abi(struct ac_shader_abi
*abi
)
161 struct nir_to_llvm_context
*ctx
= NULL
;
162 return container_of(abi
, ctx
, abi
);
166 nir2llvmtype(struct ac_nir_context
*ctx
,
167 const struct glsl_type
*type
)
169 switch (glsl_get_base_type(glsl_without_array(type
))) {
173 case GLSL_TYPE_UINT64
:
174 case GLSL_TYPE_INT64
:
176 case GLSL_TYPE_DOUBLE
:
178 case GLSL_TYPE_FLOAT
:
181 assert(!"Unsupported type in nir2llvmtype()");
187 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
188 const nir_deref_var
*deref
,
189 enum ac_descriptor_type desc_type
,
190 const nir_tex_instr
*instr
,
191 bool image
, bool write
);
193 static unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
)
195 return (index
* 4) + chan
;
198 static unsigned shader_io_get_unique_index(gl_varying_slot slot
)
200 /* handle patch indices separate */
201 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
203 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
205 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
206 return 2 + (slot
- VARYING_SLOT_PATCH0
);
208 if (slot
== VARYING_SLOT_POS
)
210 if (slot
== VARYING_SLOT_PSIZ
)
212 if (slot
== VARYING_SLOT_CLIP_DIST0
)
214 /* 3 is reserved for clip dist as well */
215 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
216 return 4 + (slot
- VARYING_SLOT_VAR0
);
217 unreachable("illegal slot in get unique index\n");
220 static void set_llvm_calling_convention(LLVMValueRef func
,
221 gl_shader_stage stage
)
223 enum radeon_llvm_calling_convention calling_conv
;
226 case MESA_SHADER_VERTEX
:
227 case MESA_SHADER_TESS_EVAL
:
228 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
230 case MESA_SHADER_GEOMETRY
:
231 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
233 case MESA_SHADER_TESS_CTRL
:
234 calling_conv
= HAVE_LLVM
>= 0x0500 ? RADEON_LLVM_AMDGPU_HS
: RADEON_LLVM_AMDGPU_VS
;
236 case MESA_SHADER_FRAGMENT
:
237 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
239 case MESA_SHADER_COMPUTE
:
240 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
243 unreachable("Unhandle shader type");
246 LLVMSetFunctionCallConv(func
, calling_conv
);
251 LLVMTypeRef types
[MAX_ARGS
];
252 LLVMValueRef
*assign
[MAX_ARGS
];
253 unsigned array_params_mask
;
255 uint8_t user_sgpr_count
;
257 uint8_t num_user_sgprs_used
;
258 uint8_t num_sgprs_used
;
259 uint8_t num_vgprs_used
;
263 add_argument(struct arg_info
*info
,
264 LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
266 assert(info
->count
< MAX_ARGS
);
267 info
->assign
[info
->count
] = param_ptr
;
268 info
->types
[info
->count
] = type
;
273 add_sgpr_argument(struct arg_info
*info
,
274 LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
276 add_argument(info
, type
, param_ptr
);
277 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
282 add_user_sgpr_argument(struct arg_info
*info
,
284 LLVMValueRef
*param_ptr
)
286 add_sgpr_argument(info
, type
, param_ptr
);
287 info
->num_user_sgprs_used
+= ac_get_type_size(type
) / 4;
288 info
->user_sgpr_count
++;
292 add_vgpr_argument(struct arg_info
*info
,
294 LLVMValueRef
*param_ptr
)
296 add_argument(info
, type
, param_ptr
);
297 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
301 add_user_sgpr_array_argument(struct arg_info
*info
,
303 LLVMValueRef
*param_ptr
)
305 info
->array_params_mask
|= (1 << info
->count
);
306 add_user_sgpr_argument(info
, type
, param_ptr
);
309 static void assign_arguments(LLVMValueRef main_function
,
310 struct arg_info
*info
)
313 for (i
= 0; i
< info
->count
; i
++) {
315 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
320 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
321 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
322 unsigned num_return_elems
,
323 struct arg_info
*args
,
324 unsigned max_workgroup_size
,
327 LLVMTypeRef main_function_type
, ret_type
;
328 LLVMBasicBlockRef main_function_body
;
330 if (num_return_elems
)
331 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
332 num_return_elems
, true);
334 ret_type
= LLVMVoidTypeInContext(ctx
);
336 /* Setup the function */
338 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
339 LLVMValueRef main_function
=
340 LLVMAddFunction(module
, "main", main_function_type
);
342 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
343 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
345 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
346 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
347 if (args
->array_params_mask
& (1 << i
)) {
348 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
349 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_BYVAL
);
350 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
353 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
357 if (max_workgroup_size
) {
358 ac_llvm_add_target_dep_function_attr(main_function
,
359 "amdgpu-max-work-group-size",
363 /* These were copied from some LLVM test. */
364 LLVMAddTargetDependentFunctionAttr(main_function
,
365 "less-precise-fpmad",
367 LLVMAddTargetDependentFunctionAttr(main_function
,
370 LLVMAddTargetDependentFunctionAttr(main_function
,
373 LLVMAddTargetDependentFunctionAttr(main_function
,
377 return main_function
;
380 static LLVMTypeRef
const_array(LLVMTypeRef elem_type
, int num_elements
)
382 return LLVMPointerType(LLVMArrayType(elem_type
, num_elements
),
386 static int get_elem_bits(struct ac_llvm_context
*ctx
, LLVMTypeRef type
)
388 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
389 type
= LLVMGetElementType(type
);
391 if (LLVMGetTypeKind(type
) == LLVMIntegerTypeKind
)
392 return LLVMGetIntTypeWidth(type
);
394 if (type
== ctx
->f16
)
396 if (type
== ctx
->f32
)
398 if (type
== ctx
->f64
)
401 unreachable("Unhandled type kind in get_elem_bits");
404 static LLVMValueRef
unpack_param(struct ac_llvm_context
*ctx
,
405 LLVMValueRef param
, unsigned rshift
,
408 LLVMValueRef value
= param
;
410 value
= LLVMBuildLShr(ctx
->builder
, value
,
411 LLVMConstInt(ctx
->i32
, rshift
, false), "");
413 if (rshift
+ bitwidth
< 32) {
414 unsigned mask
= (1 << bitwidth
) - 1;
415 value
= LLVMBuildAnd(ctx
->builder
, value
,
416 LLVMConstInt(ctx
->i32
, mask
, false), "");
421 static LLVMValueRef
get_rel_patch_id(struct nir_to_llvm_context
*ctx
)
423 switch (ctx
->stage
) {
424 case MESA_SHADER_TESS_CTRL
:
425 return unpack_param(&ctx
->ac
, ctx
->tcs_rel_ids
, 0, 8);
426 case MESA_SHADER_TESS_EVAL
:
427 return ctx
->tes_rel_patch_id
;
430 unreachable("Illegal stage");
434 /* Tessellation shaders pass outputs to the next shader using LDS.
436 * LS outputs = TCS inputs
437 * TCS outputs = TES inputs
440 * - TCS inputs for patch 0
441 * - TCS inputs for patch 1
442 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
444 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
445 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
446 * - TCS outputs for patch 1
447 * - Per-patch TCS outputs for patch 1
448 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
449 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
452 * All three shaders VS(LS), TCS, TES share the same LDS space.
455 get_tcs_in_patch_stride(struct nir_to_llvm_context
*ctx
)
457 if (ctx
->stage
== MESA_SHADER_VERTEX
)
458 return unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 0, 13);
459 else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
460 return unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 0, 13);
468 get_tcs_out_patch_stride(struct nir_to_llvm_context
*ctx
)
470 return unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 0, 13);
474 get_tcs_out_patch0_offset(struct nir_to_llvm_context
*ctx
)
476 return LLVMBuildMul(ctx
->builder
,
477 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 0, 16),
478 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
482 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context
*ctx
)
484 return LLVMBuildMul(ctx
->builder
,
485 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 16, 16),
486 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
490 get_tcs_in_current_patch_offset(struct nir_to_llvm_context
*ctx
)
492 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
493 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
495 return LLVMBuildMul(ctx
->builder
, patch_stride
, rel_patch_id
, "");
499 get_tcs_out_current_patch_offset(struct nir_to_llvm_context
*ctx
)
501 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
502 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
503 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
505 return LLVMBuildAdd(ctx
->builder
, patch0_offset
,
506 LLVMBuildMul(ctx
->builder
, patch_stride
,
512 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context
*ctx
)
514 LLVMValueRef patch0_patch_data_offset
=
515 get_tcs_out_patch0_patch_data_offset(ctx
);
516 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
517 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
519 return LLVMBuildAdd(ctx
->builder
, patch0_patch_data_offset
,
520 LLVMBuildMul(ctx
->builder
, patch_stride
,
525 static void set_userdata_location(struct ac_userdata_info
*ud_info
, uint8_t *sgpr_idx
, uint8_t num_sgprs
)
527 ud_info
->sgpr_idx
= *sgpr_idx
;
528 ud_info
->num_sgprs
= num_sgprs
;
529 ud_info
->indirect
= false;
530 ud_info
->indirect_offset
= 0;
531 *sgpr_idx
+= num_sgprs
;
534 static void set_userdata_location_shader(struct nir_to_llvm_context
*ctx
,
535 int idx
, uint8_t *sgpr_idx
, uint8_t num_sgprs
)
537 set_userdata_location(&ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
], sgpr_idx
, num_sgprs
);
541 static void set_userdata_location_indirect(struct ac_userdata_info
*ud_info
, uint8_t sgpr_idx
, uint8_t num_sgprs
,
542 uint32_t indirect_offset
)
544 ud_info
->sgpr_idx
= sgpr_idx
;
545 ud_info
->num_sgprs
= num_sgprs
;
546 ud_info
->indirect
= true;
547 ud_info
->indirect_offset
= indirect_offset
;
550 struct user_sgpr_info
{
551 bool need_ring_offsets
;
553 bool indirect_all_descriptor_sets
;
556 static void allocate_user_sgprs(struct nir_to_llvm_context
*ctx
,
557 struct user_sgpr_info
*user_sgpr_info
)
559 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
561 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
562 if (ctx
->stage
== MESA_SHADER_GEOMETRY
||
563 ctx
->stage
== MESA_SHADER_VERTEX
||
564 ctx
->stage
== MESA_SHADER_TESS_CTRL
||
565 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
566 ctx
->is_gs_copy_shader
)
567 user_sgpr_info
->need_ring_offsets
= true;
569 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&&
570 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
571 user_sgpr_info
->need_ring_offsets
= true;
573 /* 2 user sgprs will nearly always be allocated for scratch/rings */
574 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
575 user_sgpr_info
->sgpr_count
+= 2;
578 switch (ctx
->stage
) {
579 case MESA_SHADER_COMPUTE
:
580 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
581 user_sgpr_info
->sgpr_count
+= 3;
583 case MESA_SHADER_FRAGMENT
:
584 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
586 case MESA_SHADER_VERTEX
:
587 if (!ctx
->is_gs_copy_shader
) {
588 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.vs
.has_vertex_buffers
? 2 : 0;
589 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
590 user_sgpr_info
->sgpr_count
+= 3;
592 user_sgpr_info
->sgpr_count
+= 2;
595 if (ctx
->options
->key
.vs
.as_ls
)
596 user_sgpr_info
->sgpr_count
++;
598 case MESA_SHADER_TESS_CTRL
:
599 user_sgpr_info
->sgpr_count
+= 4;
601 case MESA_SHADER_TESS_EVAL
:
602 user_sgpr_info
->sgpr_count
+= 1;
604 case MESA_SHADER_GEOMETRY
:
605 user_sgpr_info
->sgpr_count
+= 2;
611 if (ctx
->shader_info
->info
.needs_push_constants
)
612 user_sgpr_info
->sgpr_count
+= 2;
614 uint32_t remaining_sgprs
= 16 - user_sgpr_info
->sgpr_count
;
615 if (remaining_sgprs
/ 2 < util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
)) {
616 user_sgpr_info
->sgpr_count
+= 2;
617 user_sgpr_info
->indirect_all_descriptor_sets
= true;
619 user_sgpr_info
->sgpr_count
+= util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
) * 2;
624 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context
*ctx
,
625 gl_shader_stage stage
,
626 bool has_previous_stage
,
627 gl_shader_stage previous_stage
,
628 const struct user_sgpr_info
*user_sgpr_info
,
629 struct arg_info
*args
,
630 LLVMValueRef
*desc_sets
)
632 unsigned num_sets
= ctx
->options
->layout
? ctx
->options
->layout
->num_sets
: 0;
633 unsigned stage_mask
= 1 << stage
;
634 if (has_previous_stage
)
635 stage_mask
|= 1 << previous_stage
;
637 /* 1 for each descriptor set */
638 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
639 for (unsigned i
= 0; i
< num_sets
; ++i
) {
640 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
641 add_user_sgpr_array_argument(args
, const_array(ctx
->ac
.i8
, 1024 * 1024), &ctx
->descriptor_sets
[i
]);
645 add_user_sgpr_array_argument(args
, const_array(const_array(ctx
->ac
.i8
, 1024 * 1024), 32), desc_sets
);
647 if (ctx
->shader_info
->info
.needs_push_constants
) {
648 /* 1 for push constants and dynamic descriptors */
649 add_user_sgpr_array_argument(args
, const_array(ctx
->ac
.i8
, 1024 * 1024), &ctx
->push_constants
);
654 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context
*ctx
,
655 gl_shader_stage stage
,
656 bool has_previous_stage
,
657 gl_shader_stage previous_stage
,
658 const struct user_sgpr_info
*user_sgpr_info
,
659 LLVMValueRef desc_sets
,
660 uint8_t *user_sgpr_idx
)
662 unsigned num_sets
= ctx
->options
->layout
? ctx
->options
->layout
->num_sets
: 0;
663 unsigned stage_mask
= 1 << stage
;
664 if (has_previous_stage
)
665 stage_mask
|= 1 << previous_stage
;
667 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
668 for (unsigned i
= 0; i
< num_sets
; ++i
) {
669 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
670 set_userdata_location(&ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[i
], user_sgpr_idx
, 2);
672 ctx
->descriptor_sets
[i
] = NULL
;
675 uint32_t desc_sgpr_idx
= *user_sgpr_idx
;
676 set_userdata_location_shader(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
, user_sgpr_idx
, 2);
678 for (unsigned i
= 0; i
< num_sets
; ++i
) {
679 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
680 set_userdata_location_indirect(&ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[i
], desc_sgpr_idx
, 2, i
* 8);
681 ctx
->descriptor_sets
[i
] = ac_build_load_to_sgpr(&ctx
->ac
, desc_sets
, LLVMConstInt(ctx
->ac
.i32
, i
, false));
684 ctx
->descriptor_sets
[i
] = NULL
;
686 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
689 if (ctx
->shader_info
->info
.needs_push_constants
) {
690 set_userdata_location_shader(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
, 2);
695 radv_define_vs_user_sgprs_phase1(struct nir_to_llvm_context
*ctx
,
696 gl_shader_stage stage
,
697 bool has_previous_stage
,
698 gl_shader_stage previous_stage
,
699 struct arg_info
*args
)
701 if (!ctx
->is_gs_copy_shader
&& (stage
== MESA_SHADER_VERTEX
|| (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
702 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
)
703 add_user_sgpr_argument(args
, const_array(ctx
->ac
.v4i32
, 16), &ctx
->vertex_buffers
); /* vertex buffers */
704 add_user_sgpr_argument(args
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
); // base vertex
705 add_user_sgpr_argument(args
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);// start instance
706 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
707 add_user_sgpr_argument(args
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
); // draw id
712 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context
*ctx
,
713 gl_shader_stage stage
,
714 bool has_previous_stage
,
715 gl_shader_stage previous_stage
,
716 uint8_t *user_sgpr_idx
)
718 if (!ctx
->is_gs_copy_shader
&& (stage
== MESA_SHADER_VERTEX
|| (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
719 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
720 set_userdata_location_shader(ctx
, AC_UD_VS_VERTEX_BUFFERS
, user_sgpr_idx
, 2);
723 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
726 set_userdata_location_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
, user_sgpr_idx
, vs_num
);
731 static void create_function(struct nir_to_llvm_context
*ctx
,
732 gl_shader_stage stage
,
733 bool has_previous_stage
,
734 gl_shader_stage previous_stage
)
736 uint8_t user_sgpr_idx
;
737 struct user_sgpr_info user_sgpr_info
;
738 struct arg_info args
= {};
739 LLVMValueRef desc_sets
;
741 allocate_user_sgprs(ctx
, &user_sgpr_info
);
743 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
744 add_user_sgpr_argument(&args
, const_array(ctx
->ac
.v4i32
, 16), &ctx
->ring_offsets
); /* address of rings */
748 case MESA_SHADER_COMPUTE
:
749 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
750 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
751 add_user_sgpr_argument(&args
, ctx
->ac
.v3i32
,
752 &ctx
->num_work_groups
);
755 for (int i
= 0; i
< 3; i
++) {
756 ctx
->workgroup_ids
[i
] = NULL
;
757 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
758 add_sgpr_argument(&args
, ctx
->ac
.i32
,
759 &ctx
->workgroup_ids
[i
]);
763 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
764 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tg_size
);
765 add_vgpr_argument(&args
, ctx
->ac
.v3i32
, &ctx
->local_invocation_ids
);
767 case MESA_SHADER_VERTEX
:
768 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
769 radv_define_vs_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &args
);
770 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
771 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->view_index
);
772 if (ctx
->options
->key
.vs
.as_es
)
773 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->es2gs_offset
); // es2gs offset
774 else if (ctx
->options
->key
.vs
.as_ls
)
775 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->ls_out_layout
); // ls out layout
776 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
); // vertex id
777 if (!ctx
->is_gs_copy_shader
) {
778 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->rel_auto_id
); // rel auto id
779 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->vs_prim_id
); // vs prim id
780 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
); // instance id
783 case MESA_SHADER_TESS_CTRL
:
784 if (has_previous_stage
) {
785 // First 6 system regs
786 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->oc_lds
); // param oc lds
787 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->merged_wave_info
); // merged wave info
788 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tess_factor_offset
); // tess factor offset
790 add_sgpr_argument(&args
, ctx
->ac
.i32
, NULL
); // scratch offset
791 add_sgpr_argument(&args
, ctx
->ac
.i32
, NULL
); // unknown
792 add_sgpr_argument(&args
, ctx
->ac
.i32
, NULL
); // unknown
794 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
795 radv_define_vs_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &args
);
796 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->ls_out_layout
); // ls out layout
798 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_offchip_layout
); // tcs offchip layout
799 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_out_offsets
); // tcs out offsets
800 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_out_layout
); // tcs out layout
801 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_in_layout
); // tcs in layout
802 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
803 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->view_index
);
805 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_patch_id
); // patch id
806 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_rel_ids
); // rel ids;
807 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
); // vertex id
808 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->rel_auto_id
); // rel auto id
809 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->vs_prim_id
); // vs prim id
810 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
); // instance id
812 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
813 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_offchip_layout
); // tcs offchip layout
814 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_out_offsets
); // tcs out offsets
815 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_out_layout
); // tcs out layout
816 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_in_layout
); // tcs in layout
817 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
818 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->view_index
);
819 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->oc_lds
); // param oc lds
820 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tess_factor_offset
); // tess factor offset
821 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_patch_id
); // patch id
822 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_rel_ids
); // rel ids;
825 case MESA_SHADER_TESS_EVAL
:
826 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
827 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_offchip_layout
); // tcs offchip layout
828 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
829 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->view_index
);
830 if (ctx
->options
->key
.tes
.as_es
) {
831 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->oc_lds
); // OC LDS
832 add_sgpr_argument(&args
, ctx
->ac
.i32
, NULL
); //
833 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->es2gs_offset
); // es2gs offset
835 add_sgpr_argument(&args
, ctx
->ac
.i32
, NULL
); //
836 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->oc_lds
); // OC LDS
838 add_vgpr_argument(&args
, ctx
->ac
.f32
, &ctx
->tes_u
); // tes_u
839 add_vgpr_argument(&args
, ctx
->ac
.f32
, &ctx
->tes_v
); // tes_v
840 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
); // tes rel patch id
841 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tes_patch_id
); // tes patch id
843 case MESA_SHADER_GEOMETRY
:
844 if (has_previous_stage
) {
845 // First 6 system regs
846 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
); // tess factor offset
847 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->merged_wave_info
); // merged wave info
848 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->oc_lds
); // param oc lds
850 add_sgpr_argument(&args
, ctx
->ac
.i32
, NULL
); // scratch offset
851 add_sgpr_argument(&args
, ctx
->ac
.i32
, NULL
); // unknown
852 add_sgpr_argument(&args
, ctx
->ac
.i32
, NULL
); // unknown
854 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
855 if (previous_stage
== MESA_SHADER_TESS_EVAL
)
856 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_offchip_layout
); // tcs offchip layout
858 radv_define_vs_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &args
);
859 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gsvs_ring_stride
); // gsvs stride
860 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gsvs_num_entries
); // gsvs num entires
861 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
862 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->view_index
);
864 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_vtx_offset
[0]); // vtx01
865 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_vtx_offset
[2]); // vtx23
866 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.gs_prim_id
); // prim id
867 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.gs_invocation_id
);
868 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_vtx_offset
[4]);
870 if (previous_stage
== MESA_SHADER_VERTEX
) {
871 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
); // vertex id
872 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->rel_auto_id
); // rel auto id
873 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->vs_prim_id
); // vs prim id
874 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
); // instance id
876 add_vgpr_argument(&args
, ctx
->ac
.f32
, &ctx
->tes_u
); // tes_u
877 add_vgpr_argument(&args
, ctx
->ac
.f32
, &ctx
->tes_v
); // tes_v
878 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
); // tes rel patch id
879 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tes_patch_id
); // tes patch id
882 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
883 radv_define_vs_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &args
);
884 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gsvs_ring_stride
); // gsvs stride
885 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gsvs_num_entries
); // gsvs num entires
886 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
887 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->view_index
);
888 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
); // gs2vs offset
889 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_wave_id
); // wave id
890 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_vtx_offset
[0]); // vtx0
891 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_vtx_offset
[1]); // vtx1
892 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.gs_prim_id
); // prim id
893 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_vtx_offset
[2]);
894 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_vtx_offset
[3]);
895 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_vtx_offset
[4]);
896 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_vtx_offset
[5]);
897 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.gs_invocation_id
);
900 case MESA_SHADER_FRAGMENT
:
901 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
902 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
)
903 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->sample_pos_offset
); /* sample position offset */
904 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->prim_mask
); /* prim mask */
905 add_vgpr_argument(&args
, ctx
->ac
.v2i32
, &ctx
->persp_sample
); /* persp sample */
906 add_vgpr_argument(&args
, ctx
->ac
.v2i32
, &ctx
->persp_center
); /* persp center */
907 add_vgpr_argument(&args
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
); /* persp centroid */
908 add_vgpr_argument(&args
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
909 add_vgpr_argument(&args
, ctx
->ac
.v2i32
, &ctx
->linear_sample
); /* linear sample */
910 add_vgpr_argument(&args
, ctx
->ac
.v2i32
, &ctx
->linear_center
); /* linear center */
911 add_vgpr_argument(&args
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
); /* linear centroid */
912 add_vgpr_argument(&args
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
913 add_vgpr_argument(&args
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]); /* pos x float */
914 add_vgpr_argument(&args
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]); /* pos y float */
915 add_vgpr_argument(&args
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]); /* pos z float */
916 add_vgpr_argument(&args
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]); /* pos w float */
917 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.front_face
); /* front face */
918 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
); /* ancillary */
919 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
); /* sample coverage */
920 add_vgpr_argument(&args
, ctx
->ac
.i32
, NULL
); /* fixed pt */
923 unreachable("Shader stage not implemented");
926 ctx
->main_function
= create_llvm_function(
927 ctx
->context
, ctx
->module
, ctx
->builder
, NULL
, 0, &args
,
928 ctx
->max_workgroup_size
,
929 ctx
->options
->unsafe_math
);
930 set_llvm_calling_convention(ctx
->main_function
, stage
);
933 ctx
->shader_info
->num_input_vgprs
= 0;
934 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
936 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
938 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
939 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
941 assign_arguments(ctx
->main_function
, &args
);
945 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
946 set_userdata_location_shader(ctx
, AC_UD_SCRATCH_RING_OFFSETS
, &user_sgpr_idx
, 2);
947 if (ctx
->options
->supports_spill
) {
948 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
949 LLVMPointerType(ctx
->ac
.i8
, CONST_ADDR_SPACE
),
950 NULL
, 0, AC_FUNC_ATTR_READNONE
);
951 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->builder
, ctx
->ring_offsets
,
952 const_array(ctx
->ac
.v4i32
, 16), "");
956 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
957 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
958 if (has_previous_stage
)
961 radv_define_common_user_sgprs_phase2(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
964 case MESA_SHADER_COMPUTE
:
965 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
966 set_userdata_location_shader(ctx
, AC_UD_CS_GRID_SIZE
,
970 case MESA_SHADER_VERTEX
:
971 radv_define_vs_user_sgprs_phase2(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_idx
);
973 set_userdata_location_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
974 if (ctx
->options
->key
.vs
.as_ls
) {
975 set_userdata_location_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
, &user_sgpr_idx
, 1);
977 if (ctx
->options
->key
.vs
.as_ls
)
978 ac_declare_lds_as_pointer(&ctx
->ac
);
980 case MESA_SHADER_TESS_CTRL
:
981 radv_define_vs_user_sgprs_phase2(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_idx
);
982 if (has_previous_stage
)
983 set_userdata_location_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
, &user_sgpr_idx
, 1);
984 set_userdata_location_shader(ctx
, AC_UD_TCS_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 4);
986 set_userdata_location_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
987 ac_declare_lds_as_pointer(&ctx
->ac
);
989 case MESA_SHADER_TESS_EVAL
:
990 set_userdata_location_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 1);
992 set_userdata_location_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
994 case MESA_SHADER_GEOMETRY
:
995 if (has_previous_stage
) {
996 if (previous_stage
== MESA_SHADER_VERTEX
)
997 radv_define_vs_user_sgprs_phase2(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_idx
);
999 set_userdata_location_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 1);
1001 set_userdata_location_shader(ctx
, AC_UD_GS_VS_RING_STRIDE_ENTRIES
, &user_sgpr_idx
, 2);
1002 if (ctx
->view_index
)
1003 set_userdata_location_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1004 if (has_previous_stage
)
1005 ac_declare_lds_as_pointer(&ctx
->ac
);
1007 case MESA_SHADER_FRAGMENT
:
1008 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
) {
1009 set_userdata_location_shader(ctx
, AC_UD_PS_SAMPLE_POS_OFFSET
, &user_sgpr_idx
, 1);
1013 unreachable("Shader stage not implemented");
1016 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1019 static int get_llvm_num_components(LLVMValueRef value
)
1021 LLVMTypeRef type
= LLVMTypeOf(value
);
1022 unsigned num_components
= LLVMGetTypeKind(type
) == LLVMVectorTypeKind
1023 ? LLVMGetVectorSize(type
)
1025 return num_components
;
1028 static LLVMValueRef
llvm_extract_elem(struct ac_llvm_context
*ac
,
1032 int count
= get_llvm_num_components(value
);
1037 return LLVMBuildExtractElement(ac
->builder
, value
,
1038 LLVMConstInt(ac
->i32
, index
, false), "");
1041 static LLVMValueRef
trim_vector(struct ac_llvm_context
*ctx
,
1042 LLVMValueRef value
, unsigned count
)
1044 unsigned num_components
= get_llvm_num_components(value
);
1045 if (count
== num_components
)
1048 LLVMValueRef masks
[] = {
1049 LLVMConstInt(ctx
->i32
, 0, false), LLVMConstInt(ctx
->i32
, 1, false),
1050 LLVMConstInt(ctx
->i32
, 2, false), LLVMConstInt(ctx
->i32
, 3, false)};
1053 return LLVMBuildExtractElement(ctx
->builder
, value
, masks
[0],
1056 LLVMValueRef swizzle
= LLVMConstVector(masks
, count
);
1057 return LLVMBuildShuffleVector(ctx
->builder
, value
, value
, swizzle
, "");
1061 build_store_values_extended(struct ac_llvm_context
*ac
,
1062 LLVMValueRef
*values
,
1063 unsigned value_count
,
1064 unsigned value_stride
,
1067 LLVMBuilderRef builder
= ac
->builder
;
1070 for (i
= 0; i
< value_count
; i
++) {
1071 LLVMValueRef ptr
= values
[i
* value_stride
];
1072 LLVMValueRef index
= LLVMConstInt(ac
->i32
, i
, false);
1073 LLVMValueRef value
= LLVMBuildExtractElement(builder
, vec
, index
, "");
1074 LLVMBuildStore(builder
, value
, ptr
);
1078 static LLVMTypeRef
get_def_type(struct ac_nir_context
*ctx
,
1079 const nir_ssa_def
*def
)
1081 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, def
->bit_size
);
1082 if (def
->num_components
> 1) {
1083 type
= LLVMVectorType(type
, def
->num_components
);
1088 static LLVMValueRef
get_src(struct ac_nir_context
*nir
, nir_src src
)
1091 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, src
.ssa
);
1092 return (LLVMValueRef
)entry
->data
;
1096 static LLVMBasicBlockRef
get_block(struct ac_nir_context
*nir
,
1097 const struct nir_block
*b
)
1099 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, b
);
1100 return (LLVMBasicBlockRef
)entry
->data
;
1103 static LLVMValueRef
get_alu_src(struct ac_nir_context
*ctx
,
1105 unsigned num_components
)
1107 LLVMValueRef value
= get_src(ctx
, src
.src
);
1108 bool need_swizzle
= false;
1111 LLVMTypeRef type
= LLVMTypeOf(value
);
1112 unsigned src_components
= LLVMGetTypeKind(type
) == LLVMVectorTypeKind
1113 ? LLVMGetVectorSize(type
)
1116 for (unsigned i
= 0; i
< num_components
; ++i
) {
1117 assert(src
.swizzle
[i
] < src_components
);
1118 if (src
.swizzle
[i
] != i
)
1119 need_swizzle
= true;
1122 if (need_swizzle
|| num_components
!= src_components
) {
1123 LLVMValueRef masks
[] = {
1124 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[0], false),
1125 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[1], false),
1126 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[2], false),
1127 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[3], false)};
1129 if (src_components
> 1 && num_components
== 1) {
1130 value
= LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
1132 } else if (src_components
== 1 && num_components
> 1) {
1133 LLVMValueRef values
[] = {value
, value
, value
, value
};
1134 value
= ac_build_gather_values(&ctx
->ac
, values
, num_components
);
1136 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
1137 value
= LLVMBuildShuffleVector(ctx
->ac
.builder
, value
, value
,
1141 assert(!src
.negate
);
1146 static LLVMValueRef
emit_int_cmp(struct ac_llvm_context
*ctx
,
1147 LLVMIntPredicate pred
, LLVMValueRef src0
,
1150 LLVMValueRef result
= LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, "");
1151 return LLVMBuildSelect(ctx
->builder
, result
,
1152 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1156 static LLVMValueRef
emit_float_cmp(struct ac_llvm_context
*ctx
,
1157 LLVMRealPredicate pred
, LLVMValueRef src0
,
1160 LLVMValueRef result
;
1161 src0
= ac_to_float(ctx
, src0
);
1162 src1
= ac_to_float(ctx
, src1
);
1163 result
= LLVMBuildFCmp(ctx
->builder
, pred
, src0
, src1
, "");
1164 return LLVMBuildSelect(ctx
->builder
, result
,
1165 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1169 static LLVMValueRef
emit_intrin_1f_param(struct ac_llvm_context
*ctx
,
1171 LLVMTypeRef result_type
,
1175 LLVMValueRef params
[] = {
1176 ac_to_float(ctx
, src0
),
1179 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1180 get_elem_bits(ctx
, result_type
));
1181 assert(length
< sizeof(name
));
1182 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 1, AC_FUNC_ATTR_READNONE
);
1185 static LLVMValueRef
emit_intrin_2f_param(struct ac_llvm_context
*ctx
,
1187 LLVMTypeRef result_type
,
1188 LLVMValueRef src0
, LLVMValueRef src1
)
1191 LLVMValueRef params
[] = {
1192 ac_to_float(ctx
, src0
),
1193 ac_to_float(ctx
, src1
),
1196 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1197 get_elem_bits(ctx
, result_type
));
1198 assert(length
< sizeof(name
));
1199 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 2, AC_FUNC_ATTR_READNONE
);
1202 static LLVMValueRef
emit_intrin_3f_param(struct ac_llvm_context
*ctx
,
1204 LLVMTypeRef result_type
,
1205 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1208 LLVMValueRef params
[] = {
1209 ac_to_float(ctx
, src0
),
1210 ac_to_float(ctx
, src1
),
1211 ac_to_float(ctx
, src2
),
1214 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1215 get_elem_bits(ctx
, result_type
));
1216 assert(length
< sizeof(name
));
1217 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 3, AC_FUNC_ATTR_READNONE
);
1220 static LLVMValueRef
emit_bcsel(struct ac_llvm_context
*ctx
,
1221 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1223 LLVMValueRef v
= LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
,
1225 return LLVMBuildSelect(ctx
->builder
, v
, src1
, src2
, "");
1228 static LLVMValueRef
emit_minmax_int(struct ac_llvm_context
*ctx
,
1229 LLVMIntPredicate pred
,
1230 LLVMValueRef src0
, LLVMValueRef src1
)
1232 return LLVMBuildSelect(ctx
->builder
,
1233 LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, ""),
1238 static LLVMValueRef
emit_iabs(struct ac_llvm_context
*ctx
,
1241 return emit_minmax_int(ctx
, LLVMIntSGT
, src0
,
1242 LLVMBuildNeg(ctx
->builder
, src0
, ""));
1245 static LLVMValueRef
emit_fsign(struct ac_llvm_context
*ctx
,
1248 LLVMValueRef cmp
, val
;
1250 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGT
, src0
, ctx
->f32_0
, "");
1251 val
= LLVMBuildSelect(ctx
->builder
, cmp
, ctx
->f32_1
, src0
, "");
1252 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
, val
, ctx
->f32_0
, "");
1253 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstReal(ctx
->f32
, -1.0), "");
1257 static LLVMValueRef
emit_isign(struct ac_llvm_context
*ctx
,
1260 LLVMValueRef cmp
, val
;
1262 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGT
, src0
, ctx
->i32_0
, "");
1263 val
= LLVMBuildSelect(ctx
->builder
, cmp
, ctx
->i32_1
, src0
, "");
1264 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGE
, val
, ctx
->i32_0
, "");
1265 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstInt(ctx
->i32
, -1, true), "");
1269 static LLVMValueRef
emit_ffract(struct ac_llvm_context
*ctx
,
1272 const char *intr
= "llvm.floor.f32";
1273 LLVMValueRef fsrc0
= ac_to_float(ctx
, src0
);
1274 LLVMValueRef params
[] = {
1277 LLVMValueRef floor
= ac_build_intrinsic(ctx
, intr
,
1278 ctx
->f32
, params
, 1,
1279 AC_FUNC_ATTR_READNONE
);
1280 return LLVMBuildFSub(ctx
->builder
, fsrc0
, floor
, "");
1283 static LLVMValueRef
emit_uint_carry(struct ac_llvm_context
*ctx
,
1285 LLVMValueRef src0
, LLVMValueRef src1
)
1287 LLVMTypeRef ret_type
;
1288 LLVMTypeRef types
[] = { ctx
->i32
, ctx
->i1
};
1290 LLVMValueRef params
[] = { src0
, src1
};
1291 ret_type
= LLVMStructTypeInContext(ctx
->context
, types
,
1294 res
= ac_build_intrinsic(ctx
, intrin
, ret_type
,
1295 params
, 2, AC_FUNC_ATTR_READNONE
);
1297 res
= LLVMBuildExtractValue(ctx
->builder
, res
, 1, "");
1298 res
= LLVMBuildZExt(ctx
->builder
, res
, ctx
->i32
, "");
1302 static LLVMValueRef
emit_b2f(struct ac_llvm_context
*ctx
,
1305 return LLVMBuildAnd(ctx
->builder
, src0
, LLVMBuildBitCast(ctx
->builder
, LLVMConstReal(ctx
->f32
, 1.0), ctx
->i32
, ""), "");
1308 static LLVMValueRef
emit_f2b(struct ac_llvm_context
*ctx
,
1311 src0
= ac_to_float(ctx
, src0
);
1312 return LLVMBuildSExt(ctx
->builder
,
1313 LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
, src0
, ctx
->f32_0
, ""),
1317 static LLVMValueRef
emit_b2i(struct ac_llvm_context
*ctx
,
1320 return LLVMBuildAnd(ctx
->builder
, src0
, ctx
->i32_1
, "");
1323 static LLVMValueRef
emit_i2b(struct ac_llvm_context
*ctx
,
1326 return LLVMBuildSExt(ctx
->builder
,
1327 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
, ctx
->i32_0
, ""),
1331 static LLVMValueRef
emit_f2f16(struct nir_to_llvm_context
*ctx
,
1334 LLVMValueRef result
;
1335 LLVMValueRef cond
= NULL
;
1337 src0
= ac_to_float(&ctx
->ac
, src0
);
1338 result
= LLVMBuildFPTrunc(ctx
->builder
, src0
, ctx
->ac
.f16
, "");
1340 if (ctx
->options
->chip_class
>= VI
) {
1341 LLVMValueRef args
[2];
1342 /* Check if the result is a denormal - and flush to 0 if so. */
1344 args
[1] = LLVMConstInt(ctx
->ac
.i32
, N_SUBNORMAL
| P_SUBNORMAL
, false);
1345 cond
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.class.f16", ctx
->ac
.i1
, args
, 2, AC_FUNC_ATTR_READNONE
);
1348 /* need to convert back up to f32 */
1349 result
= LLVMBuildFPExt(ctx
->builder
, result
, ctx
->ac
.f32
, "");
1351 if (ctx
->options
->chip_class
>= VI
)
1352 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->ac
.f32_0
, result
, "");
1355 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1356 * so compare the result and flush to 0 if it's smaller.
1358 LLVMValueRef temp
, cond2
;
1359 temp
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1360 ctx
->ac
.f32
, result
);
1361 cond
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUGT
,
1362 LLVMBuildBitCast(ctx
->builder
, LLVMConstInt(ctx
->ac
.i32
, 0x38800000, false), ctx
->ac
.f32
, ""),
1364 cond2
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
,
1365 temp
, ctx
->ac
.f32_0
, "");
1366 cond
= LLVMBuildAnd(ctx
->builder
, cond
, cond2
, "");
1367 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->ac
.f32_0
, result
, "");
1372 static LLVMValueRef
emit_umul_high(struct ac_llvm_context
*ctx
,
1373 LLVMValueRef src0
, LLVMValueRef src1
)
1375 LLVMValueRef dst64
, result
;
1376 src0
= LLVMBuildZExt(ctx
->builder
, src0
, ctx
->i64
, "");
1377 src1
= LLVMBuildZExt(ctx
->builder
, src1
, ctx
->i64
, "");
1379 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1380 dst64
= LLVMBuildLShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1381 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1385 static LLVMValueRef
emit_imul_high(struct ac_llvm_context
*ctx
,
1386 LLVMValueRef src0
, LLVMValueRef src1
)
1388 LLVMValueRef dst64
, result
;
1389 src0
= LLVMBuildSExt(ctx
->builder
, src0
, ctx
->i64
, "");
1390 src1
= LLVMBuildSExt(ctx
->builder
, src1
, ctx
->i64
, "");
1392 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1393 dst64
= LLVMBuildAShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1394 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1398 static LLVMValueRef
emit_bitfield_extract(struct ac_llvm_context
*ctx
,
1400 const LLVMValueRef srcs
[3])
1402 LLVMValueRef result
;
1403 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, srcs
[2], LLVMConstInt(ctx
->i32
, 32, false), "");
1405 result
= ac_build_bfe(ctx
, srcs
[0], srcs
[1], srcs
[2], is_signed
);
1406 result
= LLVMBuildSelect(ctx
->builder
, icond
, srcs
[0], result
, "");
1410 static LLVMValueRef
emit_bitfield_insert(struct ac_llvm_context
*ctx
,
1411 LLVMValueRef src0
, LLVMValueRef src1
,
1412 LLVMValueRef src2
, LLVMValueRef src3
)
1414 LLVMValueRef bfi_args
[3], result
;
1416 bfi_args
[0] = LLVMBuildShl(ctx
->builder
,
1417 LLVMBuildSub(ctx
->builder
,
1418 LLVMBuildShl(ctx
->builder
,
1423 bfi_args
[1] = LLVMBuildShl(ctx
->builder
, src1
, src2
, "");
1426 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, src3
, LLVMConstInt(ctx
->i32
, 32, false), "");
1429 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1430 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1432 result
= LLVMBuildXor(ctx
->builder
, bfi_args
[2],
1433 LLVMBuildAnd(ctx
->builder
, bfi_args
[0],
1434 LLVMBuildXor(ctx
->builder
, bfi_args
[1], bfi_args
[2], ""), ""), "");
1436 result
= LLVMBuildSelect(ctx
->builder
, icond
, src1
, result
, "");
1440 static LLVMValueRef
emit_pack_half_2x16(struct ac_llvm_context
*ctx
,
1443 LLVMValueRef comp
[2];
1445 src0
= ac_to_float(ctx
, src0
);
1446 comp
[0] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_0
, "");
1447 comp
[1] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_1
, "");
1449 return ac_build_cvt_pkrtz_f16(ctx
, comp
);
1452 static LLVMValueRef
emit_unpack_half_2x16(struct ac_llvm_context
*ctx
,
1455 LLVMValueRef const16
= LLVMConstInt(ctx
->i32
, 16, false);
1456 LLVMValueRef temps
[2], result
, val
;
1459 for (i
= 0; i
< 2; i
++) {
1460 val
= i
== 1 ? LLVMBuildLShr(ctx
->builder
, src0
, const16
, "") : src0
;
1461 val
= LLVMBuildTrunc(ctx
->builder
, val
, ctx
->i16
, "");
1462 val
= LLVMBuildBitCast(ctx
->builder
, val
, ctx
->f16
, "");
1463 temps
[i
] = LLVMBuildFPExt(ctx
->builder
, val
, ctx
->f32
, "");
1466 result
= LLVMBuildInsertElement(ctx
->builder
, LLVMGetUndef(ctx
->v2f32
), temps
[0],
1468 result
= LLVMBuildInsertElement(ctx
->builder
, result
, temps
[1],
1473 static LLVMValueRef
emit_ddxy(struct ac_nir_context
*ctx
,
1479 LLVMValueRef result
;
1481 if (op
== nir_op_fddx_fine
|| op
== nir_op_fddx
)
1482 mask
= AC_TID_MASK_LEFT
;
1483 else if (op
== nir_op_fddy_fine
|| op
== nir_op_fddy
)
1484 mask
= AC_TID_MASK_TOP
;
1486 mask
= AC_TID_MASK_TOP_LEFT
;
1488 /* for DDX we want to next X pixel, DDY next Y pixel. */
1489 if (op
== nir_op_fddx_fine
||
1490 op
== nir_op_fddx_coarse
||
1496 result
= ac_build_ddxy(&ctx
->ac
, mask
, idx
, src0
);
1501 * this takes an I,J coordinate pair,
1502 * and works out the X and Y derivatives.
1503 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1505 static LLVMValueRef
emit_ddxy_interp(
1506 struct ac_nir_context
*ctx
,
1507 LLVMValueRef interp_ij
)
1509 LLVMValueRef result
[4], a
;
1512 for (i
= 0; i
< 2; i
++) {
1513 a
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_ij
,
1514 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
1515 result
[i
] = emit_ddxy(ctx
, nir_op_fddx
, a
);
1516 result
[2+i
] = emit_ddxy(ctx
, nir_op_fddy
, a
);
1518 return ac_build_gather_values(&ctx
->ac
, result
, 4);
1521 static void visit_alu(struct ac_nir_context
*ctx
, const nir_alu_instr
*instr
)
1523 LLVMValueRef src
[4], result
= NULL
;
1524 unsigned num_components
= instr
->dest
.dest
.ssa
.num_components
;
1525 unsigned src_components
;
1526 LLVMTypeRef def_type
= get_def_type(ctx
, &instr
->dest
.dest
.ssa
);
1528 assert(nir_op_infos
[instr
->op
].num_inputs
<= ARRAY_SIZE(src
));
1529 switch (instr
->op
) {
1535 case nir_op_pack_half_2x16
:
1538 case nir_op_unpack_half_2x16
:
1542 src_components
= num_components
;
1545 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1546 src
[i
] = get_alu_src(ctx
, instr
->src
[i
], src_components
);
1548 switch (instr
->op
) {
1554 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1555 result
= LLVMBuildFNeg(ctx
->ac
.builder
, src
[0], "");
1558 result
= LLVMBuildNeg(ctx
->ac
.builder
, src
[0], "");
1561 result
= LLVMBuildNot(ctx
->ac
.builder
, src
[0], "");
1564 result
= LLVMBuildAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1567 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1568 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1569 result
= LLVMBuildFAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1572 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1573 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1574 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1577 result
= LLVMBuildSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1580 result
= LLVMBuildMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1583 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1586 result
= LLVMBuildURem(ctx
->ac
.builder
, src
[0], src
[1], "");
1589 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1590 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1591 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1592 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1593 ac_to_float_type(&ctx
->ac
, def_type
), result
);
1594 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[1] , result
, "");
1595 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], result
, "");
1598 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1599 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1600 result
= LLVMBuildFRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1603 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1606 result
= LLVMBuildSDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1609 result
= LLVMBuildUDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1612 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1613 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1614 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1617 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1618 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1619 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1622 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1623 result
= ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, src
[0]);
1626 result
= LLVMBuildAnd(ctx
->ac
.builder
, src
[0], src
[1], "");
1629 result
= LLVMBuildOr(ctx
->ac
.builder
, src
[0], src
[1], "");
1632 result
= LLVMBuildXor(ctx
->ac
.builder
, src
[0], src
[1], "");
1635 result
= LLVMBuildShl(ctx
->ac
.builder
, src
[0],
1636 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1637 LLVMTypeOf(src
[0]), ""),
1641 result
= LLVMBuildAShr(ctx
->ac
.builder
, src
[0],
1642 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1643 LLVMTypeOf(src
[0]), ""),
1647 result
= LLVMBuildLShr(ctx
->ac
.builder
, src
[0],
1648 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1649 LLVMTypeOf(src
[0]), ""),
1653 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1656 result
= emit_int_cmp(&ctx
->ac
, LLVMIntNE
, src
[0], src
[1]);
1659 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, src
[0], src
[1]);
1662 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSGE
, src
[0], src
[1]);
1665 result
= emit_int_cmp(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1668 result
= emit_int_cmp(&ctx
->ac
, LLVMIntUGE
, src
[0], src
[1]);
1671 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUEQ
, src
[0], src
[1]);
1674 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUNE
, src
[0], src
[1]);
1677 result
= emit_float_cmp(&ctx
->ac
, LLVMRealULT
, src
[0], src
[1]);
1680 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUGE
, src
[0], src
[1]);
1683 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1684 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1687 result
= emit_iabs(&ctx
->ac
, src
[0]);
1690 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, src
[0], src
[1]);
1693 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1696 result
= emit_minmax_int(&ctx
->ac
, LLVMIntUGT
, src
[0], src
[1]);
1699 result
= emit_minmax_int(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1702 result
= emit_isign(&ctx
->ac
, src
[0]);
1705 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1706 result
= emit_fsign(&ctx
->ac
, src
[0]);
1709 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1710 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1713 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.trunc",
1714 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1717 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.ceil",
1718 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1720 case nir_op_fround_even
:
1721 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.rint",
1722 ac_to_float_type(&ctx
->ac
, def_type
),src
[0]);
1725 result
= emit_ffract(&ctx
->ac
, src
[0]);
1728 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sin",
1729 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1732 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.cos",
1733 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1736 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1737 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1740 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.exp2",
1741 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1744 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.log2",
1745 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1748 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1749 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1750 result
= ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, result
);
1753 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.pow",
1754 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1757 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.maxnum",
1758 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1759 if (instr
->dest
.dest
.ssa
.bit_size
== 32)
1760 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1761 ac_to_float_type(&ctx
->ac
, def_type
),
1765 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.minnum",
1766 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1767 if (instr
->dest
.dest
.ssa
.bit_size
== 32)
1768 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1769 ac_to_float_type(&ctx
->ac
, def_type
),
1773 result
= emit_intrin_3f_param(&ctx
->ac
, "llvm.fmuladd",
1774 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1], src
[2]);
1776 case nir_op_ibitfield_extract
:
1777 result
= emit_bitfield_extract(&ctx
->ac
, true, src
);
1779 case nir_op_ubitfield_extract
:
1780 result
= emit_bitfield_extract(&ctx
->ac
, false, src
);
1782 case nir_op_bitfield_insert
:
1783 result
= emit_bitfield_insert(&ctx
->ac
, src
[0], src
[1], src
[2], src
[3]);
1785 case nir_op_bitfield_reverse
:
1786 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.bitreverse.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1788 case nir_op_bit_count
:
1789 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1794 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1795 src
[i
] = ac_to_integer(&ctx
->ac
, src
[i
]);
1796 result
= ac_build_gather_values(&ctx
->ac
, src
, num_components
);
1800 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1801 result
= LLVMBuildFPToSI(ctx
->ac
.builder
, src
[0], def_type
, "");
1805 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1806 result
= LLVMBuildFPToUI(ctx
->ac
.builder
, src
[0], def_type
, "");
1810 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1811 result
= LLVMBuildSIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1815 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1816 result
= LLVMBuildUIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1819 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1820 result
= LLVMBuildFPExt(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1823 result
= LLVMBuildFPTrunc(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1827 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1828 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1829 result
= LLVMBuildZExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1831 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1835 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1836 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1837 result
= LLVMBuildSExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1839 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1842 result
= emit_bcsel(&ctx
->ac
, src
[0], src
[1], src
[2]);
1844 case nir_op_find_lsb
:
1845 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1846 result
= ac_find_lsb(&ctx
->ac
, ctx
->ac
.i32
, src
[0]);
1848 case nir_op_ufind_msb
:
1849 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1850 result
= ac_build_umsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1852 case nir_op_ifind_msb
:
1853 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1854 result
= ac_build_imsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1856 case nir_op_uadd_carry
:
1857 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1858 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1859 result
= emit_uint_carry(&ctx
->ac
, "llvm.uadd.with.overflow.i32", src
[0], src
[1]);
1861 case nir_op_usub_borrow
:
1862 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1863 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1864 result
= emit_uint_carry(&ctx
->ac
, "llvm.usub.with.overflow.i32", src
[0], src
[1]);
1867 result
= emit_b2f(&ctx
->ac
, src
[0]);
1870 result
= emit_f2b(&ctx
->ac
, src
[0]);
1873 result
= emit_b2i(&ctx
->ac
, src
[0]);
1876 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1877 result
= emit_i2b(&ctx
->ac
, src
[0]);
1879 case nir_op_fquantize2f16
:
1880 result
= emit_f2f16(ctx
->nctx
, src
[0]);
1882 case nir_op_umul_high
:
1883 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1884 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1885 result
= emit_umul_high(&ctx
->ac
, src
[0], src
[1]);
1887 case nir_op_imul_high
:
1888 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1889 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1890 result
= emit_imul_high(&ctx
->ac
, src
[0], src
[1]);
1892 case nir_op_pack_half_2x16
:
1893 result
= emit_pack_half_2x16(&ctx
->ac
, src
[0]);
1895 case nir_op_unpack_half_2x16
:
1896 result
= emit_unpack_half_2x16(&ctx
->ac
, src
[0]);
1900 case nir_op_fddx_fine
:
1901 case nir_op_fddy_fine
:
1902 case nir_op_fddx_coarse
:
1903 case nir_op_fddy_coarse
:
1904 result
= emit_ddxy(ctx
, instr
->op
, src
[0]);
1907 case nir_op_unpack_64_2x32_split_x
: {
1908 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
1909 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
1912 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
1917 case nir_op_unpack_64_2x32_split_y
: {
1918 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
1919 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
1922 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
1927 case nir_op_pack_64_2x32_split
: {
1928 LLVMValueRef tmp
= LLVMGetUndef(ctx
->ac
.v2i32
);
1929 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
1930 src
[0], ctx
->ac
.i32_0
, "");
1931 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
1932 src
[1], ctx
->ac
.i32_1
, "");
1933 result
= LLVMBuildBitCast(ctx
->ac
.builder
, tmp
, ctx
->ac
.i64
, "");
1938 fprintf(stderr
, "Unknown NIR alu instr: ");
1939 nir_print_instr(&instr
->instr
, stderr
);
1940 fprintf(stderr
, "\n");
1945 assert(instr
->dest
.dest
.is_ssa
);
1946 result
= ac_to_integer(&ctx
->ac
, result
);
1947 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.dest
.ssa
,
1952 static void visit_load_const(struct ac_nir_context
*ctx
,
1953 const nir_load_const_instr
*instr
)
1955 LLVMValueRef values
[4], value
= NULL
;
1956 LLVMTypeRef element_type
=
1957 LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
1959 for (unsigned i
= 0; i
< instr
->def
.num_components
; ++i
) {
1960 switch (instr
->def
.bit_size
) {
1962 values
[i
] = LLVMConstInt(element_type
,
1963 instr
->value
.u32
[i
], false);
1966 values
[i
] = LLVMConstInt(element_type
,
1967 instr
->value
.u64
[i
], false);
1971 "unsupported nir load_const bit_size: %d\n",
1972 instr
->def
.bit_size
);
1976 if (instr
->def
.num_components
> 1) {
1977 value
= LLVMConstVector(values
, instr
->def
.num_components
);
1981 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, value
);
1984 static LLVMValueRef
cast_ptr(struct nir_to_llvm_context
*ctx
, LLVMValueRef ptr
,
1987 int addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
1988 return LLVMBuildBitCast(ctx
->builder
, ptr
,
1989 LLVMPointerType(type
, addr_space
), "");
1993 get_buffer_size(struct ac_nir_context
*ctx
, LLVMValueRef descriptor
, bool in_elements
)
1996 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
1997 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
2000 if (ctx
->ac
.chip_class
== VI
&& in_elements
) {
2001 /* On VI, the descriptor contains the size in bytes,
2002 * but TXQ must return the size in elements.
2003 * The stride is always non-zero for resources using TXQ.
2005 LLVMValueRef stride
=
2006 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2008 stride
= LLVMBuildLShr(ctx
->ac
.builder
, stride
,
2009 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
2010 stride
= LLVMBuildAnd(ctx
->ac
.builder
, stride
,
2011 LLVMConstInt(ctx
->ac
.i32
, 0x3fff, false), "");
2013 size
= LLVMBuildUDiv(ctx
->ac
.builder
, size
, stride
, "");
2019 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2022 static void build_int_type_name(
2024 char *buf
, unsigned bufsize
)
2026 assert(bufsize
>= 6);
2028 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
2029 snprintf(buf
, bufsize
, "v%ui32",
2030 LLVMGetVectorSize(type
));
2035 static LLVMValueRef
radv_lower_gather4_integer(struct ac_llvm_context
*ctx
,
2036 struct ac_image_args
*args
,
2037 const nir_tex_instr
*instr
)
2039 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2040 LLVMValueRef coord
= args
->addr
;
2041 LLVMValueRef half_texel
[2];
2042 LLVMValueRef compare_cube_wa
= NULL
;
2043 LLVMValueRef result
;
2045 unsigned coord_vgpr_index
= (unsigned)args
->offset
+ (unsigned)args
->compare
;
2049 struct ac_image_args txq_args
= { 0 };
2051 txq_args
.da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
2052 txq_args
.opcode
= ac_image_get_resinfo
;
2053 txq_args
.dmask
= 0xf;
2054 txq_args
.addr
= ctx
->i32_0
;
2055 txq_args
.resource
= args
->resource
;
2056 LLVMValueRef size
= ac_build_image_opcode(ctx
, &txq_args
);
2058 for (c
= 0; c
< 2; c
++) {
2059 half_texel
[c
] = LLVMBuildExtractElement(ctx
->builder
, size
,
2060 LLVMConstInt(ctx
->i32
, c
, false), "");
2061 half_texel
[c
] = LLVMBuildUIToFP(ctx
->builder
, half_texel
[c
], ctx
->f32
, "");
2062 half_texel
[c
] = ac_build_fdiv(ctx
, ctx
->f32_1
, half_texel
[c
]);
2063 half_texel
[c
] = LLVMBuildFMul(ctx
->builder
, half_texel
[c
],
2064 LLVMConstReal(ctx
->f32
, -0.5), "");
2068 LLVMValueRef orig_coords
= args
->addr
;
2070 for (c
= 0; c
< 2; c
++) {
2072 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, coord_vgpr_index
+ c
, 0);
2073 tmp
= LLVMBuildExtractElement(ctx
->builder
, coord
, index
, "");
2074 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2075 tmp
= LLVMBuildFAdd(ctx
->builder
, tmp
, half_texel
[c
], "");
2076 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2077 coord
= LLVMBuildInsertElement(ctx
->builder
, coord
, tmp
, index
, "");
2082 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2083 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2084 * workaround by sampling using a scaled type and converting.
2085 * This is taken from amdgpu-pro shaders.
2087 /* NOTE this produces some ugly code compared to amdgpu-pro,
2088 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2089 * and then reads them back. -pro generates two selects,
2090 * one s_cmp for the descriptor rewriting
2091 * one v_cmp for the coordinate and result changes.
2093 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2094 LLVMValueRef tmp
, tmp2
;
2096 /* workaround 8/8/8/8 uint/sint cube gather bug */
2097 /* first detect it then change to a scaled read and f2i */
2098 tmp
= LLVMBuildExtractElement(ctx
->builder
, args
->resource
, ctx
->i32_1
, "");
2101 /* extract the DATA_FORMAT */
2102 tmp
= ac_build_bfe(ctx
, tmp
, LLVMConstInt(ctx
->i32
, 20, false),
2103 LLVMConstInt(ctx
->i32
, 6, false), false);
2105 /* is the DATA_FORMAT == 8_8_8_8 */
2106 compare_cube_wa
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, tmp
, LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false), "");
2108 if (stype
== GLSL_TYPE_UINT
)
2109 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2110 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0x8000000, false),
2111 LLVMConstInt(ctx
->i32
, 0x10000000, false), "");
2113 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2114 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0xc000000, false),
2115 LLVMConstInt(ctx
->i32
, 0x14000000, false), "");
2117 /* replace the NUM FORMAT in the descriptor */
2118 tmp2
= LLVMBuildAnd(ctx
->builder
, tmp2
, LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false), "");
2119 tmp2
= LLVMBuildOr(ctx
->builder
, tmp2
, tmp
, "");
2121 args
->resource
= LLVMBuildInsertElement(ctx
->builder
, args
->resource
, tmp2
, ctx
->i32_1
, "");
2123 /* don't modify the coordinates for this case */
2124 coord
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, orig_coords
, coord
, "");
2127 result
= ac_build_image_opcode(ctx
, args
);
2129 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2130 LLVMValueRef tmp
, tmp2
;
2132 /* if the cube workaround is in place, f2i the result. */
2133 for (c
= 0; c
< 4; c
++) {
2134 tmp
= LLVMBuildExtractElement(ctx
->builder
, result
, LLVMConstInt(ctx
->i32
, c
, false), "");
2135 if (stype
== GLSL_TYPE_UINT
)
2136 tmp2
= LLVMBuildFPToUI(ctx
->builder
, tmp
, ctx
->i32
, "");
2138 tmp2
= LLVMBuildFPToSI(ctx
->builder
, tmp
, ctx
->i32
, "");
2139 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2140 tmp2
= LLVMBuildBitCast(ctx
->builder
, tmp2
, ctx
->i32
, "");
2141 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, tmp2
, tmp
, "");
2142 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2143 result
= LLVMBuildInsertElement(ctx
->builder
, result
, tmp
, LLVMConstInt(ctx
->i32
, c
, false), "");
2149 static LLVMValueRef
build_tex_intrinsic(struct ac_nir_context
*ctx
,
2150 const nir_tex_instr
*instr
,
2152 struct ac_image_args
*args
)
2154 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
2155 return ac_build_buffer_load_format(&ctx
->ac
,
2162 args
->opcode
= ac_image_sample
;
2163 args
->compare
= instr
->is_shadow
;
2165 switch (instr
->op
) {
2167 case nir_texop_txf_ms
:
2168 case nir_texop_samples_identical
:
2169 args
->opcode
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
? ac_image_load
: ac_image_load_mip
;
2170 args
->compare
= false;
2171 args
->offset
= false;
2178 args
->level_zero
= true;
2183 case nir_texop_query_levels
:
2184 args
->opcode
= ac_image_get_resinfo
;
2187 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
2188 args
->level_zero
= true;
2194 args
->opcode
= ac_image_gather4
;
2195 args
->level_zero
= true;
2198 args
->opcode
= ac_image_get_lod
;
2199 args
->compare
= false;
2200 args
->offset
= false;
2206 if (instr
->op
== nir_texop_tg4
&& ctx
->ac
.chip_class
<= VI
) {
2207 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2208 if (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
) {
2209 return radv_lower_gather4_integer(&ctx
->ac
, args
, instr
);
2212 return ac_build_image_opcode(&ctx
->ac
, args
);
2215 static LLVMValueRef
visit_vulkan_resource_index(struct nir_to_llvm_context
*ctx
,
2216 nir_intrinsic_instr
*instr
)
2218 LLVMValueRef index
= get_src(ctx
->nir
, instr
->src
[0]);
2219 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
2220 unsigned binding
= nir_intrinsic_binding(instr
);
2221 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
2222 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
2223 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
2224 unsigned base_offset
= layout
->binding
[binding
].offset
;
2225 LLVMValueRef offset
, stride
;
2227 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
2228 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
2229 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
2230 layout
->binding
[binding
].dynamic_offset_offset
;
2231 desc_ptr
= ctx
->push_constants
;
2232 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
2233 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2235 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
2237 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
2238 index
= LLVMBuildMul(ctx
->builder
, index
, stride
, "");
2239 offset
= LLVMBuildAdd(ctx
->builder
, offset
, index
, "");
2241 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
2242 desc_ptr
= cast_ptr(ctx
, desc_ptr
, ctx
->ac
.v4i32
);
2243 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2248 static LLVMValueRef
visit_vulkan_resource_reindex(struct nir_to_llvm_context
*ctx
,
2249 nir_intrinsic_instr
*instr
)
2251 LLVMValueRef ptr
= get_src(ctx
->nir
, instr
->src
[0]);
2252 LLVMValueRef index
= get_src(ctx
->nir
, instr
->src
[1]);
2254 LLVMValueRef result
= LLVMBuildGEP(ctx
->builder
, ptr
, &index
, 1, "");
2255 LLVMSetMetadata(result
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2259 static LLVMValueRef
visit_load_push_constant(struct nir_to_llvm_context
*ctx
,
2260 nir_intrinsic_instr
*instr
)
2262 LLVMValueRef ptr
, addr
;
2264 addr
= LLVMConstInt(ctx
->ac
.i32
, nir_intrinsic_base(instr
), 0);
2265 addr
= LLVMBuildAdd(ctx
->builder
, addr
, get_src(ctx
->nir
, instr
->src
[0]), "");
2267 ptr
= ac_build_gep0(&ctx
->ac
, ctx
->push_constants
, addr
);
2268 ptr
= cast_ptr(ctx
, ptr
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
));
2270 return LLVMBuildLoad(ctx
->builder
, ptr
, "");
2273 static LLVMValueRef
visit_get_buffer_size(struct ac_nir_context
*ctx
,
2274 const nir_intrinsic_instr
*instr
)
2276 LLVMValueRef ptr
= get_src(ctx
, instr
->src
[0]);
2278 return get_buffer_size(ctx
, LLVMBuildLoad(ctx
->ac
.builder
, ptr
, ""), false);
2280 static void visit_store_ssbo(struct ac_nir_context
*ctx
,
2281 nir_intrinsic_instr
*instr
)
2283 const char *store_name
;
2284 LLVMValueRef src_data
= get_src(ctx
, instr
->src
[0]);
2285 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2286 int elem_size_mult
= get_elem_bits(&ctx
->ac
, LLVMTypeOf(src_data
)) / 32;
2287 int components_32bit
= elem_size_mult
* instr
->num_components
;
2288 unsigned writemask
= nir_intrinsic_write_mask(instr
);
2289 LLVMValueRef base_data
, base_offset
;
2290 LLVMValueRef params
[6];
2292 params
[1] = ctx
->abi
->load_ssbo(ctx
->abi
,
2293 get_src(ctx
, instr
->src
[1]), true);
2294 params
[2] = ctx
->ac
.i32_0
; /* vindex */
2295 params
[4] = ctx
->ac
.i1false
; /* glc */
2296 params
[5] = ctx
->ac
.i1false
; /* slc */
2298 if (components_32bit
> 1)
2299 data_type
= LLVMVectorType(ctx
->ac
.f32
, components_32bit
);
2301 base_data
= ac_to_float(&ctx
->ac
, src_data
);
2302 base_data
= trim_vector(&ctx
->ac
, base_data
, instr
->num_components
);
2303 base_data
= LLVMBuildBitCast(ctx
->ac
.builder
, base_data
,
2305 base_offset
= get_src(ctx
, instr
->src
[2]); /* voffset */
2309 LLVMValueRef offset
;
2311 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
2313 /* Due to an LLVM limitation, split 3-element writes
2314 * into a 2-element and a 1-element write. */
2316 writemask
|= 1 << (start
+ 2);
2320 start
*= elem_size_mult
;
2321 count
*= elem_size_mult
;
2324 writemask
|= ((1u << (count
- 4)) - 1u) << (start
+ 4);
2329 store_name
= "llvm.amdgcn.buffer.store.v4f32";
2331 } else if (count
== 2) {
2332 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
2333 base_data
, LLVMConstInt(ctx
->ac
.i32
, start
, false), "");
2334 data
= LLVMBuildInsertElement(ctx
->ac
.builder
, LLVMGetUndef(ctx
->ac
.v2f32
), tmp
,
2337 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
2338 base_data
, LLVMConstInt(ctx
->ac
.i32
, start
+ 1, false), "");
2339 data
= LLVMBuildInsertElement(ctx
->ac
.builder
, data
, tmp
,
2341 store_name
= "llvm.amdgcn.buffer.store.v2f32";
2345 if (get_llvm_num_components(base_data
) > 1)
2346 data
= LLVMBuildExtractElement(ctx
->ac
.builder
, base_data
,
2347 LLVMConstInt(ctx
->ac
.i32
, start
, false), "");
2350 store_name
= "llvm.amdgcn.buffer.store.f32";
2353 offset
= base_offset
;
2355 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, LLVMConstInt(ctx
->ac
.i32
, start
* 4, false), "");
2359 ac_build_intrinsic(&ctx
->ac
, store_name
,
2360 ctx
->ac
.voidt
, params
, 6, 0);
2364 static LLVMValueRef
visit_atomic_ssbo(struct ac_nir_context
*ctx
,
2365 const nir_intrinsic_instr
*instr
)
2368 LLVMValueRef params
[6];
2371 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
) {
2372 params
[arg_count
++] = llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[3]), 0);
2374 params
[arg_count
++] = llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[2]), 0);
2375 params
[arg_count
++] = ctx
->abi
->load_ssbo(ctx
->abi
,
2376 get_src(ctx
, instr
->src
[0]),
2378 params
[arg_count
++] = ctx
->ac
.i32_0
; /* vindex */
2379 params
[arg_count
++] = get_src(ctx
, instr
->src
[1]); /* voffset */
2380 params
[arg_count
++] = LLVMConstInt(ctx
->ac
.i1
, 0, false); /* slc */
2382 switch (instr
->intrinsic
) {
2383 case nir_intrinsic_ssbo_atomic_add
:
2384 name
= "llvm.amdgcn.buffer.atomic.add";
2386 case nir_intrinsic_ssbo_atomic_imin
:
2387 name
= "llvm.amdgcn.buffer.atomic.smin";
2389 case nir_intrinsic_ssbo_atomic_umin
:
2390 name
= "llvm.amdgcn.buffer.atomic.umin";
2392 case nir_intrinsic_ssbo_atomic_imax
:
2393 name
= "llvm.amdgcn.buffer.atomic.smax";
2395 case nir_intrinsic_ssbo_atomic_umax
:
2396 name
= "llvm.amdgcn.buffer.atomic.umax";
2398 case nir_intrinsic_ssbo_atomic_and
:
2399 name
= "llvm.amdgcn.buffer.atomic.and";
2401 case nir_intrinsic_ssbo_atomic_or
:
2402 name
= "llvm.amdgcn.buffer.atomic.or";
2404 case nir_intrinsic_ssbo_atomic_xor
:
2405 name
= "llvm.amdgcn.buffer.atomic.xor";
2407 case nir_intrinsic_ssbo_atomic_exchange
:
2408 name
= "llvm.amdgcn.buffer.atomic.swap";
2410 case nir_intrinsic_ssbo_atomic_comp_swap
:
2411 name
= "llvm.amdgcn.buffer.atomic.cmpswap";
2417 return ac_build_intrinsic(&ctx
->ac
, name
, ctx
->ac
.i32
, params
, arg_count
, 0);
2420 static LLVMValueRef
visit_load_buffer(struct ac_nir_context
*ctx
,
2421 const nir_intrinsic_instr
*instr
)
2423 LLVMValueRef results
[2];
2424 int load_components
;
2425 int num_components
= instr
->num_components
;
2426 if (instr
->dest
.ssa
.bit_size
== 64)
2427 num_components
*= 2;
2429 for (int i
= 0; i
< num_components
; i
+= load_components
) {
2430 load_components
= MIN2(num_components
- i
, 4);
2431 const char *load_name
;
2432 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2433 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, i
* 4, false);
2434 offset
= LLVMBuildAdd(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[1]), offset
, "");
2436 if (load_components
== 3)
2437 data_type
= LLVMVectorType(ctx
->ac
.f32
, 4);
2438 else if (load_components
> 1)
2439 data_type
= LLVMVectorType(ctx
->ac
.f32
, load_components
);
2441 if (load_components
>= 3)
2442 load_name
= "llvm.amdgcn.buffer.load.v4f32";
2443 else if (load_components
== 2)
2444 load_name
= "llvm.amdgcn.buffer.load.v2f32";
2445 else if (load_components
== 1)
2446 load_name
= "llvm.amdgcn.buffer.load.f32";
2448 unreachable("unhandled number of components");
2450 LLVMValueRef params
[] = {
2451 ctx
->abi
->load_ssbo(ctx
->abi
,
2452 get_src(ctx
, instr
->src
[0]),
2460 results
[i
] = ac_build_intrinsic(&ctx
->ac
, load_name
, data_type
, params
, 5, 0);
2465 LLVMValueRef ret
= results
[0];
2466 if (num_components
> 4 || num_components
== 3) {
2467 LLVMValueRef masks
[] = {
2468 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
2469 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
2470 LLVMConstInt(ctx
->ac
.i32
, 4, false), LLVMConstInt(ctx
->ac
.i32
, 5, false),
2471 LLVMConstInt(ctx
->ac
.i32
, 6, false), LLVMConstInt(ctx
->ac
.i32
, 7, false)
2474 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
2475 ret
= LLVMBuildShuffleVector(ctx
->ac
.builder
, results
[0],
2476 results
[num_components
> 4 ? 1 : 0], swizzle
, "");
2479 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2480 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2483 static LLVMValueRef
visit_load_ubo_buffer(struct ac_nir_context
*ctx
,
2484 const nir_intrinsic_instr
*instr
)
2486 LLVMValueRef results
[8], ret
;
2487 LLVMValueRef rsrc
= get_src(ctx
, instr
->src
[0]);
2488 LLVMValueRef offset
= get_src(ctx
, instr
->src
[1]);
2489 int num_components
= instr
->num_components
;
2491 if (ctx
->abi
->load_ubo
)
2492 rsrc
= ctx
->abi
->load_ubo(ctx
->abi
, rsrc
);
2494 if (instr
->dest
.ssa
.bit_size
== 64)
2495 num_components
*= 2;
2497 for (unsigned i
= 0; i
< num_components
; ++i
) {
2498 LLVMValueRef params
[] = {
2500 LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, 4 * i
, 0),
2503 results
[i
] = ac_build_intrinsic(&ctx
->ac
, "llvm.SI.load.const.v4i32", ctx
->ac
.f32
,
2505 AC_FUNC_ATTR_READNONE
|
2506 AC_FUNC_ATTR_LEGACY
);
2510 ret
= ac_build_gather_values(&ctx
->ac
, results
, num_components
);
2511 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2512 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2516 get_deref_offset(struct ac_nir_context
*ctx
, nir_deref_var
*deref
,
2517 bool vs_in
, unsigned *vertex_index_out
,
2518 LLVMValueRef
*vertex_index_ref
,
2519 unsigned *const_out
, LLVMValueRef
*indir_out
)
2521 unsigned const_offset
= 0;
2522 nir_deref
*tail
= &deref
->deref
;
2523 LLVMValueRef offset
= NULL
;
2525 if (vertex_index_out
!= NULL
|| vertex_index_ref
!= NULL
) {
2527 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2528 if (vertex_index_out
)
2529 *vertex_index_out
= deref_array
->base_offset
;
2531 if (vertex_index_ref
) {
2532 LLVMValueRef vtx
= LLVMConstInt(ctx
->ac
.i32
, deref_array
->base_offset
, false);
2533 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
2534 vtx
= LLVMBuildAdd(ctx
->ac
.builder
, vtx
, get_src(ctx
, deref_array
->indirect
), "");
2536 *vertex_index_ref
= vtx
;
2540 if (deref
->var
->data
.compact
) {
2541 assert(tail
->child
->deref_type
== nir_deref_type_array
);
2542 assert(glsl_type_is_scalar(glsl_without_array(deref
->var
->type
)));
2543 nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
2544 /* We always lower indirect dereferences for "compact" array vars. */
2545 assert(deref_array
->deref_array_type
== nir_deref_array_type_direct
);
2547 const_offset
= deref_array
->base_offset
;
2551 while (tail
->child
!= NULL
) {
2552 const struct glsl_type
*parent_type
= tail
->type
;
2555 if (tail
->deref_type
== nir_deref_type_array
) {
2556 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2557 LLVMValueRef index
, stride
, local_offset
;
2558 unsigned size
= glsl_count_attribute_slots(tail
->type
, vs_in
);
2560 const_offset
+= size
* deref_array
->base_offset
;
2561 if (deref_array
->deref_array_type
== nir_deref_array_type_direct
)
2564 assert(deref_array
->deref_array_type
== nir_deref_array_type_indirect
);
2565 index
= get_src(ctx
, deref_array
->indirect
);
2566 stride
= LLVMConstInt(ctx
->ac
.i32
, size
, 0);
2567 local_offset
= LLVMBuildMul(ctx
->ac
.builder
, stride
, index
, "");
2570 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, local_offset
, "");
2572 offset
= local_offset
;
2573 } else if (tail
->deref_type
== nir_deref_type_struct
) {
2574 nir_deref_struct
*deref_struct
= nir_deref_as_struct(tail
);
2576 for (unsigned i
= 0; i
< deref_struct
->index
; i
++) {
2577 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
2578 const_offset
+= glsl_count_attribute_slots(ft
, vs_in
);
2581 unreachable("unsupported deref type");
2585 if (const_offset
&& offset
)
2586 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
2587 LLVMConstInt(ctx
->ac
.i32
, const_offset
, 0),
2590 *const_out
= const_offset
;
2591 *indir_out
= offset
;
2595 /* The offchip buffer layout for TCS->TES is
2597 * - attribute 0 of patch 0 vertex 0
2598 * - attribute 0 of patch 0 vertex 1
2599 * - attribute 0 of patch 0 vertex 2
2601 * - attribute 0 of patch 1 vertex 0
2602 * - attribute 0 of patch 1 vertex 1
2604 * - attribute 1 of patch 0 vertex 0
2605 * - attribute 1 of patch 0 vertex 1
2607 * - per patch attribute 0 of patch 0
2608 * - per patch attribute 0 of patch 1
2611 * Note that every attribute has 4 components.
2613 static LLVMValueRef
get_tcs_tes_buffer_address(struct nir_to_llvm_context
*ctx
,
2614 LLVMValueRef vertex_index
,
2615 LLVMValueRef param_index
)
2617 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
2618 LLVMValueRef param_stride
, constant16
;
2619 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
2621 vertices_per_patch
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 9, 6);
2622 num_patches
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 0, 9);
2623 total_vertices
= LLVMBuildMul(ctx
->builder
, vertices_per_patch
,
2626 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2628 base_addr
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
2629 vertices_per_patch
, "");
2631 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2634 param_stride
= total_vertices
;
2636 base_addr
= rel_patch_id
;
2637 param_stride
= num_patches
;
2640 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2641 LLVMBuildMul(ctx
->builder
, param_index
,
2642 param_stride
, ""), "");
2644 base_addr
= LLVMBuildMul(ctx
->builder
, base_addr
, constant16
, "");
2646 if (!vertex_index
) {
2647 LLVMValueRef patch_data_offset
=
2648 unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 16, 16);
2650 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2651 patch_data_offset
, "");
2656 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct nir_to_llvm_context
*ctx
,
2658 unsigned const_index
,
2660 LLVMValueRef vertex_index
,
2661 LLVMValueRef indir_index
)
2663 LLVMValueRef param_index
;
2666 param_index
= LLVMBuildAdd(ctx
->builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
2669 if (const_index
&& !is_compact
)
2670 param
+= const_index
;
2671 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
2673 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
2677 mark_tess_output(struct nir_to_llvm_context
*ctx
,
2678 bool is_patch
, uint32_t param
)
2682 ctx
->tess_patch_outputs_written
|= (1ull << param
);
2684 ctx
->tess_outputs_written
|= (1ull << param
);
2688 get_dw_address(struct nir_to_llvm_context
*ctx
,
2689 LLVMValueRef dw_addr
,
2691 unsigned const_index
,
2692 bool compact_const_index
,
2693 LLVMValueRef vertex_index
,
2694 LLVMValueRef stride
,
2695 LLVMValueRef indir_index
)
2700 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2701 LLVMBuildMul(ctx
->builder
,
2707 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2708 LLVMBuildMul(ctx
->builder
, indir_index
,
2709 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
2710 else if (const_index
&& !compact_const_index
)
2711 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2712 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2714 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2715 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
2717 if (const_index
&& compact_const_index
)
2718 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2719 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2724 load_tcs_input(struct nir_to_llvm_context
*ctx
,
2725 nir_intrinsic_instr
*instr
)
2727 LLVMValueRef dw_addr
, stride
;
2728 unsigned const_index
;
2729 LLVMValueRef vertex_index
;
2730 LLVMValueRef indir_index
;
2732 LLVMValueRef value
[4], result
;
2733 const bool per_vertex
= nir_is_per_vertex_io(instr
->variables
[0]->var
, ctx
->stage
);
2734 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
2735 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2736 get_deref_offset(ctx
->nir
, instr
->variables
[0],
2737 false, NULL
, per_vertex
? &vertex_index
: NULL
,
2738 &const_index
, &indir_index
);
2740 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 13, 8);
2741 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
2742 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2745 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
2746 for (unsigned i
= 0; i
< instr
->num_components
+ comp
; i
++) {
2747 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2748 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2751 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, instr
->num_components
, comp
);
2752 result
= LLVMBuildBitCast(ctx
->builder
, result
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
2757 load_tcs_output(struct nir_to_llvm_context
*ctx
,
2758 nir_intrinsic_instr
*instr
)
2760 LLVMValueRef dw_addr
;
2761 LLVMValueRef stride
= NULL
;
2762 LLVMValueRef value
[4], result
;
2763 LLVMValueRef vertex_index
= NULL
;
2764 LLVMValueRef indir_index
= NULL
;
2765 unsigned const_index
= 0;
2767 const bool per_vertex
= nir_is_per_vertex_io(instr
->variables
[0]->var
, ctx
->stage
);
2768 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
2769 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2770 get_deref_offset(ctx
->nir
, instr
->variables
[0],
2771 false, NULL
, per_vertex
? &vertex_index
: NULL
,
2772 &const_index
, &indir_index
);
2774 if (!instr
->variables
[0]->var
->data
.patch
) {
2775 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
2776 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2778 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2781 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2784 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
2785 for (unsigned i
= comp
; i
< instr
->num_components
+ comp
; i
++) {
2786 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2787 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2790 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, instr
->num_components
, comp
);
2791 result
= LLVMBuildBitCast(ctx
->builder
, result
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
2796 store_tcs_output(struct nir_to_llvm_context
*ctx
,
2797 nir_intrinsic_instr
*instr
,
2801 LLVMValueRef dw_addr
;
2802 LLVMValueRef stride
= NULL
;
2803 LLVMValueRef buf_addr
= NULL
;
2804 LLVMValueRef vertex_index
= NULL
;
2805 LLVMValueRef indir_index
= NULL
;
2806 unsigned const_index
= 0;
2808 const unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
2809 const bool per_vertex
= nir_is_per_vertex_io(instr
->variables
[0]->var
, ctx
->stage
);
2810 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
2811 bool store_lds
= true;
2813 if (instr
->variables
[0]->var
->data
.patch
) {
2814 if (!(ctx
->tcs_patch_outputs_read
& (1U << (instr
->variables
[0]->var
->data
.location
- VARYING_SLOT_PATCH0
))))
2817 if (!(ctx
->tcs_outputs_read
& (1ULL << instr
->variables
[0]->var
->data
.location
)))
2820 get_deref_offset(ctx
->nir
, instr
->variables
[0],
2821 false, NULL
, per_vertex
? &vertex_index
: NULL
,
2822 &const_index
, &indir_index
);
2824 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2825 if (instr
->variables
[0]->var
->data
.location
== VARYING_SLOT_CLIP_DIST0
&&
2826 is_compact
&& const_index
> 3) {
2831 if (!instr
->variables
[0]->var
->data
.patch
) {
2832 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
2833 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2835 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2838 mark_tess_output(ctx
, instr
->variables
[0]->var
->data
.patch
, param
);
2840 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2842 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
2843 vertex_index
, indir_index
);
2845 bool is_tess_factor
= false;
2846 if (instr
->variables
[0]->var
->data
.location
== VARYING_SLOT_TESS_LEVEL_INNER
||
2847 instr
->variables
[0]->var
->data
.location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
2848 is_tess_factor
= true;
2850 unsigned base
= is_compact
? const_index
: 0;
2851 for (unsigned chan
= 0; chan
< 8; chan
++) {
2852 if (!(writemask
& (1 << chan
)))
2854 LLVMValueRef value
= llvm_extract_elem(&ctx
->ac
, src
, chan
- comp
);
2856 if (store_lds
|| is_tess_factor
)
2857 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
2859 if (!is_tess_factor
&& writemask
!= 0xF)
2860 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
2861 buf_addr
, ctx
->oc_lds
,
2862 4 * (base
+ chan
), 1, 0, true, false);
2864 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2868 if (writemask
== 0xF) {
2869 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
2870 buf_addr
, ctx
->oc_lds
,
2871 (base
* 4), 1, 0, true, false);
2876 load_tes_input(struct nir_to_llvm_context
*ctx
,
2877 const nir_intrinsic_instr
*instr
)
2879 LLVMValueRef buf_addr
;
2880 LLVMValueRef result
;
2881 LLVMValueRef vertex_index
= NULL
;
2882 LLVMValueRef indir_index
= NULL
;
2883 unsigned const_index
= 0;
2885 const bool per_vertex
= nir_is_per_vertex_io(instr
->variables
[0]->var
, ctx
->stage
);
2886 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
2888 get_deref_offset(ctx
->nir
, instr
->variables
[0],
2889 false, NULL
, per_vertex
? &vertex_index
: NULL
,
2890 &const_index
, &indir_index
);
2891 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2892 if (instr
->variables
[0]->var
->data
.location
== VARYING_SLOT_CLIP_DIST0
&&
2893 is_compact
&& const_index
> 3) {
2898 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
2899 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
2900 is_compact
, vertex_index
, indir_index
);
2902 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, comp
* 4, false);
2903 buf_addr
= LLVMBuildAdd(ctx
->builder
, buf_addr
, comp_offset
, "");
2905 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, instr
->num_components
, NULL
,
2906 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
2907 result
= trim_vector(&ctx
->ac
, result
, instr
->num_components
);
2908 result
= LLVMBuildBitCast(ctx
->builder
, result
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
2913 load_gs_input(struct ac_shader_abi
*abi
,
2915 unsigned driver_location
,
2917 unsigned num_components
,
2918 unsigned vertex_index
,
2919 unsigned const_index
,
2922 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
2923 LLVMValueRef vtx_offset
;
2924 LLVMValueRef args
[9];
2925 unsigned param
, vtx_offset_param
;
2926 LLVMValueRef value
[4], result
;
2928 vtx_offset_param
= vertex_index
;
2929 assert(vtx_offset_param
< 6);
2930 vtx_offset
= LLVMBuildMul(ctx
->builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
2931 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
2933 param
= shader_io_get_unique_index(location
);
2935 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
2936 if (ctx
->ac
.chip_class
>= GFX9
) {
2937 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
2938 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2939 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
2940 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2942 args
[0] = ctx
->esgs_ring
;
2943 args
[1] = vtx_offset
;
2944 args
[2] = LLVMConstInt(ctx
->ac
.i32
, (param
* 4 + i
+ const_index
) * 256, false);
2945 args
[3] = ctx
->ac
.i32_0
;
2946 args
[4] = ctx
->ac
.i32_1
; /* OFFEN */
2947 args
[5] = ctx
->ac
.i32_0
; /* IDXEN */
2948 args
[6] = ctx
->ac
.i32_1
; /* GLC */
2949 args
[7] = ctx
->ac
.i32_0
; /* SLC */
2950 args
[8] = ctx
->ac
.i32_0
; /* TFE */
2952 value
[i
] = ac_build_intrinsic(&ctx
->ac
, "llvm.SI.buffer.load.dword.i32.i32",
2953 ctx
->ac
.i32
, args
, 9,
2954 AC_FUNC_ATTR_READONLY
|
2955 AC_FUNC_ATTR_LEGACY
);
2958 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
2964 build_gep_for_deref(struct ac_nir_context
*ctx
,
2965 nir_deref_var
*deref
)
2967 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->vars
, deref
->var
);
2968 assert(entry
->data
);
2969 LLVMValueRef val
= entry
->data
;
2970 nir_deref
*tail
= deref
->deref
.child
;
2971 while (tail
!= NULL
) {
2972 LLVMValueRef offset
;
2973 switch (tail
->deref_type
) {
2974 case nir_deref_type_array
: {
2975 nir_deref_array
*array
= nir_deref_as_array(tail
);
2976 offset
= LLVMConstInt(ctx
->ac
.i32
, array
->base_offset
, 0);
2977 if (array
->deref_array_type
==
2978 nir_deref_array_type_indirect
) {
2979 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
2986 case nir_deref_type_struct
: {
2987 nir_deref_struct
*deref_struct
=
2988 nir_deref_as_struct(tail
);
2989 offset
= LLVMConstInt(ctx
->ac
.i32
,
2990 deref_struct
->index
, 0);
2994 unreachable("bad deref type");
2996 val
= ac_build_gep0(&ctx
->ac
, val
, offset
);
3002 static LLVMValueRef
visit_load_var(struct ac_nir_context
*ctx
,
3003 nir_intrinsic_instr
*instr
)
3005 LLVMValueRef values
[8];
3006 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3007 int ve
= instr
->dest
.ssa
.num_components
;
3008 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3009 LLVMValueRef indir_index
;
3011 unsigned const_index
;
3012 bool vs_in
= ctx
->stage
== MESA_SHADER_VERTEX
&&
3013 instr
->variables
[0]->var
->data
.mode
== nir_var_shader_in
;
3014 get_deref_offset(ctx
, instr
->variables
[0], vs_in
, NULL
, NULL
,
3015 &const_index
, &indir_index
);
3017 if (instr
->dest
.ssa
.bit_size
== 64)
3020 switch (instr
->variables
[0]->var
->data
.mode
) {
3021 case nir_var_shader_in
:
3022 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
3023 return load_tcs_input(ctx
->nctx
, instr
);
3024 if (ctx
->stage
== MESA_SHADER_TESS_EVAL
)
3025 return load_tes_input(ctx
->nctx
, instr
);
3026 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3027 LLVMValueRef indir_index
;
3028 unsigned const_index
, vertex_index
;
3029 get_deref_offset(ctx
, instr
->variables
[0],
3030 false, &vertex_index
, NULL
,
3031 &const_index
, &indir_index
);
3032 return ctx
->abi
->load_inputs(ctx
->abi
, instr
->variables
[0]->var
->data
.location
,
3033 instr
->variables
[0]->var
->data
.driver_location
,
3034 instr
->variables
[0]->var
->data
.location_frac
, ve
,
3035 vertex_index
, const_index
,
3036 nir2llvmtype(ctx
, instr
->variables
[0]->var
->type
));
3039 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3041 unsigned count
= glsl_count_attribute_slots(
3042 instr
->variables
[0]->var
->type
,
3043 ctx
->stage
== MESA_SHADER_VERTEX
);
3045 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3046 &ctx
->ac
, ctx
->abi
->inputs
+ idx
+ chan
, count
,
3049 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3053 values
[chan
] = ctx
->abi
->inputs
[idx
+ chan
+ const_index
* 4];
3057 for (unsigned chan
= 0; chan
< ve
; chan
++) {
3059 unsigned count
= glsl_count_attribute_slots(
3060 instr
->variables
[0]->var
->type
, false);
3062 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3063 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3066 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3070 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, ctx
->locals
[idx
+ chan
+ const_index
* 4], "");
3074 case nir_var_shared
: {
3075 LLVMValueRef address
= build_gep_for_deref(ctx
,
3076 instr
->variables
[0]);
3077 LLVMValueRef val
= LLVMBuildLoad(ctx
->ac
.builder
, address
, "");
3078 return LLVMBuildBitCast(ctx
->ac
.builder
, val
,
3079 get_def_type(ctx
, &instr
->dest
.ssa
),
3082 case nir_var_shader_out
:
3083 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
3084 return load_tcs_output(ctx
->nctx
, instr
);
3086 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3088 unsigned count
= glsl_count_attribute_slots(
3089 instr
->variables
[0]->var
->type
, false);
3091 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3092 &ctx
->ac
, ctx
->outputs
+ idx
+ chan
, count
,
3095 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3099 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
,
3100 ctx
->outputs
[idx
+ chan
+ const_index
* 4],
3106 unreachable("unhandle variable mode");
3108 ret
= ac_build_varying_gather_values(&ctx
->ac
, values
, ve
, comp
);
3109 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3113 visit_store_var(struct ac_nir_context
*ctx
,
3114 nir_intrinsic_instr
*instr
)
3116 LLVMValueRef temp_ptr
, value
;
3117 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3118 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3119 LLVMValueRef src
= ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
3120 int writemask
= instr
->const_index
[0] << comp
;
3121 LLVMValueRef indir_index
;
3122 unsigned const_index
;
3123 get_deref_offset(ctx
, instr
->variables
[0], false,
3124 NULL
, NULL
, &const_index
, &indir_index
);
3126 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
)) == 64) {
3127 int old_writemask
= writemask
;
3129 src
= LLVMBuildBitCast(ctx
->ac
.builder
, src
,
3130 LLVMVectorType(ctx
->ac
.f32
, get_llvm_num_components(src
) * 2),
3134 for (unsigned chan
= 0; chan
< 4; chan
++) {
3135 if (old_writemask
& (1 << chan
))
3136 writemask
|= 3u << (2 * chan
);
3140 switch (instr
->variables
[0]->var
->data
.mode
) {
3141 case nir_var_shader_out
:
3143 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3144 store_tcs_output(ctx
->nctx
, instr
, src
, writemask
);
3148 for (unsigned chan
= 0; chan
< 8; chan
++) {
3150 if (!(writemask
& (1 << chan
)))
3153 value
= llvm_extract_elem(&ctx
->ac
, src
, chan
- comp
);
3155 if (instr
->variables
[0]->var
->data
.compact
)
3158 unsigned count
= glsl_count_attribute_slots(
3159 instr
->variables
[0]->var
->type
, false);
3161 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3162 &ctx
->ac
, ctx
->outputs
+ idx
+ chan
, count
,
3163 stride
, true, true);
3165 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3166 value
, indir_index
, "");
3167 build_store_values_extended(&ctx
->ac
, ctx
->outputs
+ idx
+ chan
,
3168 count
, stride
, tmp_vec
);
3171 temp_ptr
= ctx
->outputs
[idx
+ chan
+ const_index
* stride
];
3173 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3178 for (unsigned chan
= 0; chan
< 8; chan
++) {
3179 if (!(writemask
& (1 << chan
)))
3182 value
= llvm_extract_elem(&ctx
->ac
, src
, chan
);
3184 unsigned count
= glsl_count_attribute_slots(
3185 instr
->variables
[0]->var
->type
, false);
3187 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3188 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3191 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3192 value
, indir_index
, "");
3193 build_store_values_extended(&ctx
->ac
, ctx
->locals
+ idx
+ chan
,
3196 temp_ptr
= ctx
->locals
[idx
+ chan
+ const_index
* 4];
3198 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3202 case nir_var_shared
: {
3203 int writemask
= instr
->const_index
[0];
3204 LLVMValueRef address
= build_gep_for_deref(ctx
,
3205 instr
->variables
[0]);
3206 LLVMValueRef val
= get_src(ctx
, instr
->src
[0]);
3207 unsigned components
=
3208 glsl_get_vector_elements(
3209 nir_deref_tail(&instr
->variables
[0]->deref
)->type
);
3210 if (writemask
== (1 << components
) - 1) {
3211 val
= LLVMBuildBitCast(
3212 ctx
->ac
.builder
, val
,
3213 LLVMGetElementType(LLVMTypeOf(address
)), "");
3214 LLVMBuildStore(ctx
->ac
.builder
, val
, address
);
3216 for (unsigned chan
= 0; chan
< 4; chan
++) {
3217 if (!(writemask
& (1 << chan
)))
3220 LLVMBuildStructGEP(ctx
->ac
.builder
,
3222 LLVMValueRef src
= llvm_extract_elem(&ctx
->ac
, val
,
3224 src
= LLVMBuildBitCast(
3225 ctx
->ac
.builder
, src
,
3226 LLVMGetElementType(LLVMTypeOf(ptr
)), "");
3227 LLVMBuildStore(ctx
->ac
.builder
, src
, ptr
);
3237 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
3240 case GLSL_SAMPLER_DIM_BUF
:
3242 case GLSL_SAMPLER_DIM_1D
:
3243 return array
? 2 : 1;
3244 case GLSL_SAMPLER_DIM_2D
:
3245 return array
? 3 : 2;
3246 case GLSL_SAMPLER_DIM_MS
:
3247 return array
? 4 : 3;
3248 case GLSL_SAMPLER_DIM_3D
:
3249 case GLSL_SAMPLER_DIM_CUBE
:
3251 case GLSL_SAMPLER_DIM_RECT
:
3252 case GLSL_SAMPLER_DIM_SUBPASS
:
3254 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
3264 /* Adjust the sample index according to FMASK.
3266 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3267 * which is the identity mapping. Each nibble says which physical sample
3268 * should be fetched to get that sample.
3270 * For example, 0x11111100 means there are only 2 samples stored and
3271 * the second sample covers 3/4 of the pixel. When reading samples 0
3272 * and 1, return physical sample 0 (determined by the first two 0s
3273 * in FMASK), otherwise return physical sample 1.
3275 * The sample index should be adjusted as follows:
3276 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3278 static LLVMValueRef
adjust_sample_index_using_fmask(struct ac_llvm_context
*ctx
,
3279 LLVMValueRef coord_x
, LLVMValueRef coord_y
,
3280 LLVMValueRef coord_z
,
3281 LLVMValueRef sample_index
,
3282 LLVMValueRef fmask_desc_ptr
)
3284 LLVMValueRef fmask_load_address
[4];
3287 fmask_load_address
[0] = coord_x
;
3288 fmask_load_address
[1] = coord_y
;
3290 fmask_load_address
[2] = coord_z
;
3291 fmask_load_address
[3] = LLVMGetUndef(ctx
->i32
);
3294 struct ac_image_args args
= {0};
3296 args
.opcode
= ac_image_load
;
3297 args
.da
= coord_z
? true : false;
3298 args
.resource
= fmask_desc_ptr
;
3300 args
.addr
= ac_build_gather_values(ctx
, fmask_load_address
, coord_z
? 4 : 2);
3302 res
= ac_build_image_opcode(ctx
, &args
);
3304 res
= ac_to_integer(ctx
, res
);
3305 LLVMValueRef four
= LLVMConstInt(ctx
->i32
, 4, false);
3306 LLVMValueRef F
= LLVMConstInt(ctx
->i32
, 0xf, false);
3308 LLVMValueRef fmask
= LLVMBuildExtractElement(ctx
->builder
,
3312 LLVMValueRef sample_index4
=
3313 LLVMBuildMul(ctx
->builder
, sample_index
, four
, "");
3314 LLVMValueRef shifted_fmask
=
3315 LLVMBuildLShr(ctx
->builder
, fmask
, sample_index4
, "");
3316 LLVMValueRef final_sample
=
3317 LLVMBuildAnd(ctx
->builder
, shifted_fmask
, F
, "");
3319 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3320 * resource descriptor is 0 (invalid),
3322 LLVMValueRef fmask_desc
=
3323 LLVMBuildBitCast(ctx
->builder
, fmask_desc_ptr
,
3326 LLVMValueRef fmask_word1
=
3327 LLVMBuildExtractElement(ctx
->builder
, fmask_desc
,
3330 LLVMValueRef word1_is_nonzero
=
3331 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
,
3332 fmask_word1
, ctx
->i32_0
, "");
3334 /* Replace the MSAA sample index. */
3336 LLVMBuildSelect(ctx
->builder
, word1_is_nonzero
,
3337 final_sample
, sample_index
, "");
3338 return sample_index
;
3341 static LLVMValueRef
get_image_coords(struct ac_nir_context
*ctx
,
3342 const nir_intrinsic_instr
*instr
)
3344 const struct glsl_type
*type
= instr
->variables
[0]->var
->type
;
3345 if(instr
->variables
[0]->deref
.child
)
3346 type
= instr
->variables
[0]->deref
.child
->type
;
3348 LLVMValueRef src0
= get_src(ctx
, instr
->src
[0]);
3349 LLVMValueRef coords
[4];
3350 LLVMValueRef masks
[] = {
3351 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
3352 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
3355 LLVMValueRef sample_index
= llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[1]), 0);
3358 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3359 bool is_array
= glsl_sampler_type_is_array(type
);
3360 bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3361 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3362 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
||
3363 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3364 bool gfx9_1d
= ctx
->ac
.chip_class
>= GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
3365 count
= image_type_to_components_count(dim
, is_array
);
3368 LLVMValueRef fmask_load_address
[3];
3371 fmask_load_address
[0] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3372 fmask_load_address
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[1], "");
3374 fmask_load_address
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[2], "");
3376 fmask_load_address
[2] = NULL
;
3378 for (chan
= 0; chan
< 2; ++chan
)
3379 fmask_load_address
[chan
] =
3380 LLVMBuildAdd(ctx
->ac
.builder
, fmask_load_address
[chan
],
3381 LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3382 ctx
->ac
.i32
, ""), "");
3383 fmask_load_address
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3385 sample_index
= adjust_sample_index_using_fmask(&ctx
->ac
,
3386 fmask_load_address
[0],
3387 fmask_load_address
[1],
3388 fmask_load_address
[2],
3390 get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_FMASK
, NULL
, true, false));
3392 if (count
== 1 && !gfx9_1d
) {
3393 if (instr
->src
[0].ssa
->num_components
)
3394 res
= LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3401 for (chan
= 0; chan
< count
; ++chan
) {
3402 coords
[chan
] = llvm_extract_elem(&ctx
->ac
, src0
, chan
);
3405 for (chan
= 0; chan
< 2; ++chan
)
3406 coords
[chan
] = LLVMBuildAdd(ctx
->ac
.builder
, coords
[chan
], LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3407 ctx
->ac
.i32
, ""), "");
3408 coords
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3414 coords
[2] = coords
[1];
3415 coords
[1] = ctx
->ac
.i32_0
;
3417 coords
[1] = ctx
->ac
.i32_0
;
3422 coords
[count
] = sample_index
;
3427 coords
[3] = LLVMGetUndef(ctx
->ac
.i32
);
3430 res
= ac_build_gather_values(&ctx
->ac
, coords
, count
);
3435 static LLVMValueRef
visit_image_load(struct ac_nir_context
*ctx
,
3436 const nir_intrinsic_instr
*instr
)
3438 LLVMValueRef params
[7];
3440 char intrinsic_name
[64];
3441 const nir_variable
*var
= instr
->variables
[0]->var
;
3442 const struct glsl_type
*type
= var
->type
;
3444 if(instr
->variables
[0]->deref
.child
)
3445 type
= instr
->variables
[0]->deref
.child
->type
;
3447 type
= glsl_without_array(type
);
3448 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3449 params
[0] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, false);
3450 params
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3451 ctx
->ac
.i32_0
, ""); /* vindex */
3452 params
[2] = ctx
->ac
.i32_0
; /* voffset */
3453 params
[3] = ctx
->ac
.i1false
; /* glc */
3454 params
[4] = ctx
->ac
.i1false
; /* slc */
3455 res
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.load.format.v4f32", ctx
->ac
.v4f32
,
3458 res
= trim_vector(&ctx
->ac
, res
, instr
->dest
.ssa
.num_components
);
3459 res
= ac_to_integer(&ctx
->ac
, res
);
3461 bool is_da
= glsl_sampler_type_is_array(type
) ||
3462 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
||
3463 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_SUBPASS
||
3464 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_SUBPASS_MS
;
3465 LLVMValueRef da
= is_da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3466 LLVMValueRef glc
= ctx
->ac
.i1false
;
3467 LLVMValueRef slc
= ctx
->ac
.i1false
;
3469 params
[0] = get_image_coords(ctx
, instr
);
3470 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3471 params
[2] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3472 if (HAVE_LLVM
<= 0x0309) {
3473 params
[3] = ctx
->ac
.i1false
; /* r128 */
3478 LLVMValueRef lwe
= ctx
->ac
.i1false
;
3485 ac_get_image_intr_name("llvm.amdgcn.image.load",
3486 ctx
->ac
.v4f32
, /* vdata */
3487 LLVMTypeOf(params
[0]), /* coords */
3488 LLVMTypeOf(params
[1]), /* rsrc */
3489 intrinsic_name
, sizeof(intrinsic_name
));
3491 res
= ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.v4f32
,
3492 params
, 7, AC_FUNC_ATTR_READONLY
);
3494 return ac_to_integer(&ctx
->ac
, res
);
3497 static void visit_image_store(struct ac_nir_context
*ctx
,
3498 nir_intrinsic_instr
*instr
)
3500 LLVMValueRef params
[8];
3501 char intrinsic_name
[64];
3502 const nir_variable
*var
= instr
->variables
[0]->var
;
3503 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3504 LLVMValueRef glc
= ctx
->ac
.i1false
;
3505 bool force_glc
= ctx
->ac
.chip_class
== SI
;
3507 glc
= ctx
->ac
.i1true
;
3509 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3510 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2])); /* data */
3511 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, true);
3512 params
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3513 ctx
->ac
.i32_0
, ""); /* vindex */
3514 params
[3] = ctx
->ac
.i32_0
; /* voffset */
3515 params
[4] = glc
; /* glc */
3516 params
[5] = ctx
->ac
.i1false
; /* slc */
3517 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.store.format.v4f32", ctx
->ac
.voidt
,
3520 bool is_da
= glsl_sampler_type_is_array(type
) ||
3521 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
;
3522 LLVMValueRef da
= is_da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3523 LLVMValueRef slc
= ctx
->ac
.i1false
;
3525 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2]));
3526 params
[1] = get_image_coords(ctx
, instr
); /* coords */
3527 params
[2] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, true);
3528 params
[3] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3529 if (HAVE_LLVM
<= 0x0309) {
3530 params
[4] = ctx
->ac
.i1false
; /* r128 */
3535 LLVMValueRef lwe
= ctx
->ac
.i1false
;
3542 ac_get_image_intr_name("llvm.amdgcn.image.store",
3543 LLVMTypeOf(params
[0]), /* vdata */
3544 LLVMTypeOf(params
[1]), /* coords */
3545 LLVMTypeOf(params
[2]), /* rsrc */
3546 intrinsic_name
, sizeof(intrinsic_name
));
3548 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.voidt
,
3554 static LLVMValueRef
visit_image_atomic(struct ac_nir_context
*ctx
,
3555 const nir_intrinsic_instr
*instr
)
3557 LLVMValueRef params
[7];
3558 int param_count
= 0;
3559 const nir_variable
*var
= instr
->variables
[0]->var
;
3561 const char *atomic_name
;
3562 char intrinsic_name
[41];
3563 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3564 MAYBE_UNUSED
int length
;
3566 bool is_unsigned
= glsl_get_sampler_result_type(type
) == GLSL_TYPE_UINT
;
3568 switch (instr
->intrinsic
) {
3569 case nir_intrinsic_image_atomic_add
:
3570 atomic_name
= "add";
3572 case nir_intrinsic_image_atomic_min
:
3573 atomic_name
= is_unsigned
? "umin" : "smin";
3575 case nir_intrinsic_image_atomic_max
:
3576 atomic_name
= is_unsigned
? "umax" : "smax";
3578 case nir_intrinsic_image_atomic_and
:
3579 atomic_name
= "and";
3581 case nir_intrinsic_image_atomic_or
:
3584 case nir_intrinsic_image_atomic_xor
:
3585 atomic_name
= "xor";
3587 case nir_intrinsic_image_atomic_exchange
:
3588 atomic_name
= "swap";
3590 case nir_intrinsic_image_atomic_comp_swap
:
3591 atomic_name
= "cmpswap";
3597 if (instr
->intrinsic
== nir_intrinsic_image_atomic_comp_swap
)
3598 params
[param_count
++] = get_src(ctx
, instr
->src
[3]);
3599 params
[param_count
++] = get_src(ctx
, instr
->src
[2]);
3601 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3602 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
,
3604 params
[param_count
++] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3605 ctx
->ac
.i32_0
, ""); /* vindex */
3606 params
[param_count
++] = ctx
->ac
.i32_0
; /* voffset */
3607 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3609 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3610 "llvm.amdgcn.buffer.atomic.%s", atomic_name
);
3612 char coords_type
[8];
3614 bool da
= glsl_sampler_type_is_array(type
) ||
3615 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
;
3617 LLVMValueRef coords
= params
[param_count
++] = get_image_coords(ctx
, instr
);
3618 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
,
3620 params
[param_count
++] = ctx
->ac
.i1false
; /* r128 */
3621 params
[param_count
++] = da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
; /* da */
3622 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3624 build_int_type_name(LLVMTypeOf(coords
),
3625 coords_type
, sizeof(coords_type
));
3627 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3628 "llvm.amdgcn.image.atomic.%s.%s", atomic_name
, coords_type
);
3631 assert(length
< sizeof(intrinsic_name
));
3632 return ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.i32
, params
, param_count
, 0);
3635 static LLVMValueRef
visit_image_size(struct ac_nir_context
*ctx
,
3636 const nir_intrinsic_instr
*instr
)
3639 const nir_variable
*var
= instr
->variables
[0]->var
;
3640 const struct glsl_type
*type
= instr
->variables
[0]->var
->type
;
3641 bool da
= glsl_sampler_type_is_array(var
->type
) ||
3642 glsl_get_sampler_dim(var
->type
) == GLSL_SAMPLER_DIM_CUBE
;
3643 if(instr
->variables
[0]->deref
.child
)
3644 type
= instr
->variables
[0]->deref
.child
->type
;
3646 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
)
3647 return get_buffer_size(ctx
,
3648 get_sampler_desc(ctx
, instr
->variables
[0],
3649 AC_DESC_BUFFER
, NULL
, true, false), true);
3651 struct ac_image_args args
= { 0 };
3655 args
.resource
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3656 args
.opcode
= ac_image_get_resinfo
;
3657 args
.addr
= ctx
->ac
.i32_0
;
3659 res
= ac_build_image_opcode(&ctx
->ac
, &args
);
3661 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
3663 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
3664 glsl_sampler_type_is_array(type
)) {
3665 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
3666 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3667 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
3668 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, z
, two
, "");
3670 if (ctx
->ac
.chip_class
>= GFX9
&&
3671 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
3672 glsl_sampler_type_is_array(type
)) {
3673 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3674 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, layers
,
3681 #define NOOP_WAITCNT 0xf7f
3682 #define LGKM_CNT 0x07f
3683 #define VM_CNT 0xf70
3685 static void emit_membar(struct nir_to_llvm_context
*ctx
,
3686 const nir_intrinsic_instr
*instr
)
3688 unsigned waitcnt
= NOOP_WAITCNT
;
3690 switch (instr
->intrinsic
) {
3691 case nir_intrinsic_memory_barrier
:
3692 case nir_intrinsic_group_memory_barrier
:
3693 waitcnt
&= VM_CNT
& LGKM_CNT
;
3695 case nir_intrinsic_memory_barrier_atomic_counter
:
3696 case nir_intrinsic_memory_barrier_buffer
:
3697 case nir_intrinsic_memory_barrier_image
:
3700 case nir_intrinsic_memory_barrier_shared
:
3701 waitcnt
&= LGKM_CNT
;
3706 if (waitcnt
!= NOOP_WAITCNT
)
3707 ac_build_waitcnt(&ctx
->ac
, waitcnt
);
3710 static void emit_barrier(struct nir_to_llvm_context
*ctx
)
3712 /* SI only (thanks to a hw bug workaround):
3713 * The real barrier instruction isn’t needed, because an entire patch
3714 * always fits into a single wave.
3716 if (ctx
->options
->chip_class
== SI
&&
3717 ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3718 ac_build_waitcnt(&ctx
->ac
, LGKM_CNT
& VM_CNT
);
3721 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.s.barrier",
3722 ctx
->ac
.voidt
, NULL
, 0, AC_FUNC_ATTR_CONVERGENT
);
3725 static void emit_discard_if(struct ac_nir_context
*ctx
,
3726 const nir_intrinsic_instr
*instr
)
3730 cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3731 get_src(ctx
, instr
->src
[0]),
3733 ac_build_kill_if_false(&ctx
->ac
, cond
);
3737 visit_load_local_invocation_index(struct nir_to_llvm_context
*ctx
)
3739 LLVMValueRef result
;
3740 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
->ac
);
3741 result
= LLVMBuildAnd(ctx
->builder
, ctx
->tg_size
,
3742 LLVMConstInt(ctx
->ac
.i32
, 0xfc0, false), "");
3744 return LLVMBuildAdd(ctx
->builder
, result
, thread_id
, "");
3747 static LLVMValueRef
visit_var_atomic(struct nir_to_llvm_context
*ctx
,
3748 const nir_intrinsic_instr
*instr
)
3750 LLVMValueRef ptr
, result
;
3751 LLVMValueRef src
= get_src(ctx
->nir
, instr
->src
[0]);
3752 ptr
= build_gep_for_deref(ctx
->nir
, instr
->variables
[0]);
3754 if (instr
->intrinsic
== nir_intrinsic_var_atomic_comp_swap
) {
3755 LLVMValueRef src1
= get_src(ctx
->nir
, instr
->src
[1]);
3756 result
= LLVMBuildAtomicCmpXchg(ctx
->builder
,
3758 LLVMAtomicOrderingSequentiallyConsistent
,
3759 LLVMAtomicOrderingSequentiallyConsistent
,
3762 LLVMAtomicRMWBinOp op
;
3763 switch (instr
->intrinsic
) {
3764 case nir_intrinsic_var_atomic_add
:
3765 op
= LLVMAtomicRMWBinOpAdd
;
3767 case nir_intrinsic_var_atomic_umin
:
3768 op
= LLVMAtomicRMWBinOpUMin
;
3770 case nir_intrinsic_var_atomic_umax
:
3771 op
= LLVMAtomicRMWBinOpUMax
;
3773 case nir_intrinsic_var_atomic_imin
:
3774 op
= LLVMAtomicRMWBinOpMin
;
3776 case nir_intrinsic_var_atomic_imax
:
3777 op
= LLVMAtomicRMWBinOpMax
;
3779 case nir_intrinsic_var_atomic_and
:
3780 op
= LLVMAtomicRMWBinOpAnd
;
3782 case nir_intrinsic_var_atomic_or
:
3783 op
= LLVMAtomicRMWBinOpOr
;
3785 case nir_intrinsic_var_atomic_xor
:
3786 op
= LLVMAtomicRMWBinOpXor
;
3788 case nir_intrinsic_var_atomic_exchange
:
3789 op
= LLVMAtomicRMWBinOpXchg
;
3795 result
= LLVMBuildAtomicRMW(ctx
->builder
, op
, ptr
, ac_to_integer(&ctx
->ac
, src
),
3796 LLVMAtomicOrderingSequentiallyConsistent
,
3802 #define INTERP_CENTER 0
3803 #define INTERP_CENTROID 1
3804 #define INTERP_SAMPLE 2
3806 static LLVMValueRef
lookup_interp_param(struct nir_to_llvm_context
*ctx
,
3807 enum glsl_interp_mode interp
, unsigned location
)
3810 case INTERP_MODE_FLAT
:
3813 case INTERP_MODE_SMOOTH
:
3814 case INTERP_MODE_NONE
:
3815 if (location
== INTERP_CENTER
)
3816 return ctx
->persp_center
;
3817 else if (location
== INTERP_CENTROID
)
3818 return ctx
->persp_centroid
;
3819 else if (location
== INTERP_SAMPLE
)
3820 return ctx
->persp_sample
;
3822 case INTERP_MODE_NOPERSPECTIVE
:
3823 if (location
== INTERP_CENTER
)
3824 return ctx
->linear_center
;
3825 else if (location
== INTERP_CENTROID
)
3826 return ctx
->linear_centroid
;
3827 else if (location
== INTERP_SAMPLE
)
3828 return ctx
->linear_sample
;
3834 static LLVMValueRef
load_sample_position(struct nir_to_llvm_context
*ctx
,
3835 LLVMValueRef sample_id
)
3837 LLVMValueRef result
;
3838 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false));
3840 ptr
= LLVMBuildBitCast(ctx
->builder
, ptr
,
3841 const_array(ctx
->ac
.v2f32
, 64), "");
3843 sample_id
= LLVMBuildAdd(ctx
->builder
, sample_id
, ctx
->sample_pos_offset
, "");
3844 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
3849 static LLVMValueRef
load_sample_pos(struct ac_nir_context
*ctx
)
3851 LLVMValueRef values
[2];
3853 values
[0] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[0]);
3854 values
[1] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[1]);
3855 return ac_build_gather_values(&ctx
->ac
, values
, 2);
3858 static LLVMValueRef
visit_interp(struct nir_to_llvm_context
*ctx
,
3859 const nir_intrinsic_instr
*instr
)
3861 LLVMValueRef result
[4];
3862 LLVMValueRef interp_param
, attr_number
;
3865 LLVMValueRef src_c0
= NULL
;
3866 LLVMValueRef src_c1
= NULL
;
3867 LLVMValueRef src0
= NULL
;
3868 int input_index
= instr
->variables
[0]->var
->data
.location
- VARYING_SLOT_VAR0
;
3869 switch (instr
->intrinsic
) {
3870 case nir_intrinsic_interp_var_at_centroid
:
3871 location
= INTERP_CENTROID
;
3873 case nir_intrinsic_interp_var_at_sample
:
3874 case nir_intrinsic_interp_var_at_offset
:
3875 location
= INTERP_CENTER
;
3876 src0
= get_src(ctx
->nir
, instr
->src
[0]);
3882 if (instr
->intrinsic
== nir_intrinsic_interp_var_at_offset
) {
3883 src_c0
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->ac
.i32_0
, ""));
3884 src_c1
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->ac
.i32_1
, ""));
3885 } else if (instr
->intrinsic
== nir_intrinsic_interp_var_at_sample
) {
3886 LLVMValueRef sample_position
;
3887 LLVMValueRef halfval
= LLVMConstReal(ctx
->ac
.f32
, 0.5f
);
3889 /* fetch sample ID */
3890 sample_position
= load_sample_position(ctx
, src0
);
3892 src_c0
= LLVMBuildExtractElement(ctx
->builder
, sample_position
, ctx
->ac
.i32_0
, "");
3893 src_c0
= LLVMBuildFSub(ctx
->builder
, src_c0
, halfval
, "");
3894 src_c1
= LLVMBuildExtractElement(ctx
->builder
, sample_position
, ctx
->ac
.i32_1
, "");
3895 src_c1
= LLVMBuildFSub(ctx
->builder
, src_c1
, halfval
, "");
3897 interp_param
= lookup_interp_param(ctx
, instr
->variables
[0]->var
->data
.interpolation
, location
);
3898 attr_number
= LLVMConstInt(ctx
->ac
.i32
, input_index
, false);
3900 if (location
== INTERP_CENTER
) {
3901 LLVMValueRef ij_out
[2];
3902 LLVMValueRef ddxy_out
= emit_ddxy_interp(ctx
->nir
, interp_param
);
3905 * take the I then J parameters, and the DDX/Y for it, and
3906 * calculate the IJ inputs for the interpolator.
3907 * temp1 = ddx * offset/sample.x + I;
3908 * interp_param.I = ddy * offset/sample.y + temp1;
3909 * temp1 = ddx * offset/sample.x + J;
3910 * interp_param.J = ddy * offset/sample.y + temp1;
3912 for (unsigned i
= 0; i
< 2; i
++) {
3913 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->ac
.i32
, i
, false);
3914 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->ac
.i32
, i
+ 2, false);
3915 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->builder
,
3916 ddxy_out
, ix_ll
, "");
3917 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->builder
,
3918 ddxy_out
, iy_ll
, "");
3919 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->builder
,
3920 interp_param
, ix_ll
, "");
3921 LLVMValueRef temp1
, temp2
;
3923 interp_el
= LLVMBuildBitCast(ctx
->builder
, interp_el
,
3926 temp1
= LLVMBuildFMul(ctx
->builder
, ddx_el
, src_c0
, "");
3927 temp1
= LLVMBuildFAdd(ctx
->builder
, temp1
, interp_el
, "");
3929 temp2
= LLVMBuildFMul(ctx
->builder
, ddy_el
, src_c1
, "");
3930 temp2
= LLVMBuildFAdd(ctx
->builder
, temp2
, temp1
, "");
3932 ij_out
[i
] = LLVMBuildBitCast(ctx
->builder
,
3933 temp2
, ctx
->ac
.i32
, "");
3935 interp_param
= ac_build_gather_values(&ctx
->ac
, ij_out
, 2);
3939 for (chan
= 0; chan
< 4; chan
++) {
3940 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
3943 interp_param
= LLVMBuildBitCast(ctx
->builder
,
3944 interp_param
, ctx
->ac
.v2f32
, "");
3945 LLVMValueRef i
= LLVMBuildExtractElement(
3946 ctx
->builder
, interp_param
, ctx
->ac
.i32_0
, "");
3947 LLVMValueRef j
= LLVMBuildExtractElement(
3948 ctx
->builder
, interp_param
, ctx
->ac
.i32_1
, "");
3950 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
3951 llvm_chan
, attr_number
,
3952 ctx
->prim_mask
, i
, j
);
3954 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
3955 LLVMConstInt(ctx
->ac
.i32
, 2, false),
3956 llvm_chan
, attr_number
,
3960 return ac_build_varying_gather_values(&ctx
->ac
, result
, instr
->num_components
,
3961 instr
->variables
[0]->var
->data
.location_frac
);
3965 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
3967 LLVMValueRef gs_next_vertex
;
3968 LLVMValueRef can_emit
;
3970 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
3972 /* Write vertex attribute values to GSVS ring */
3973 gs_next_vertex
= LLVMBuildLoad(ctx
->builder
,
3974 ctx
->gs_next_vertex
,
3977 /* If this thread has already emitted the declared maximum number of
3978 * vertices, kill it: excessive vertex emissions are not supposed to
3979 * have any effect, and GS threads have no externally observable
3980 * effects other than emitting vertices.
3982 can_emit
= LLVMBuildICmp(ctx
->builder
, LLVMIntULT
, gs_next_vertex
,
3983 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
3984 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
3986 /* loop num outputs */
3988 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
3989 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
3994 if (!(ctx
->output_mask
& (1ull << i
)))
3997 if (i
== VARYING_SLOT_CLIP_DIST0
) {
3998 /* pack clip and cull into a single set of slots */
3999 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
4003 for (unsigned j
= 0; j
< length
; j
++) {
4004 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
,
4006 LLVMValueRef voffset
= LLVMConstInt(ctx
->ac
.i32
, (slot
* 4 + j
) * ctx
->gs_max_out_vertices
, false);
4007 voffset
= LLVMBuildAdd(ctx
->builder
, voffset
, gs_next_vertex
, "");
4008 voffset
= LLVMBuildMul(ctx
->builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4010 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->ac
.i32
, "");
4012 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->gsvs_ring
,
4014 voffset
, ctx
->gs2vs_offset
, 0,
4020 gs_next_vertex
= LLVMBuildAdd(ctx
->builder
, gs_next_vertex
,
4022 LLVMBuildStore(ctx
->builder
, gs_next_vertex
, ctx
->gs_next_vertex
);
4024 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
4028 visit_end_primitive(struct nir_to_llvm_context
*ctx
,
4029 const nir_intrinsic_instr
*instr
)
4031 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
4035 visit_load_tess_coord(struct nir_to_llvm_context
*ctx
,
4036 const nir_intrinsic_instr
*instr
)
4038 LLVMValueRef coord
[4] = {
4045 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
4046 coord
[2] = LLVMBuildFSub(ctx
->builder
, ctx
->ac
.f32_1
,
4047 LLVMBuildFAdd(ctx
->builder
, coord
[0], coord
[1], ""), "");
4049 LLVMValueRef result
= ac_build_gather_values(&ctx
->ac
, coord
, instr
->num_components
);
4050 return LLVMBuildBitCast(ctx
->builder
, result
,
4051 get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
4054 static void visit_intrinsic(struct ac_nir_context
*ctx
,
4055 nir_intrinsic_instr
*instr
)
4057 LLVMValueRef result
= NULL
;
4059 switch (instr
->intrinsic
) {
4060 case nir_intrinsic_load_work_group_id
: {
4061 LLVMValueRef values
[3];
4063 for (int i
= 0; i
< 3; i
++) {
4064 values
[i
] = ctx
->nctx
->workgroup_ids
[i
] ?
4065 ctx
->nctx
->workgroup_ids
[i
] : ctx
->ac
.i32_0
;
4068 result
= ac_build_gather_values(&ctx
->ac
, values
, 3);
4071 case nir_intrinsic_load_base_vertex
: {
4072 result
= ctx
->abi
->base_vertex
;
4075 case nir_intrinsic_load_vertex_id_zero_base
: {
4076 result
= ctx
->abi
->vertex_id
;
4079 case nir_intrinsic_load_local_invocation_id
: {
4080 result
= ctx
->nctx
->local_invocation_ids
;
4083 case nir_intrinsic_load_base_instance
:
4084 result
= ctx
->abi
->start_instance
;
4086 case nir_intrinsic_load_draw_id
:
4087 result
= ctx
->abi
->draw_id
;
4089 case nir_intrinsic_load_view_index
:
4090 result
= ctx
->nctx
->view_index
? ctx
->nctx
->view_index
: ctx
->ac
.i32_0
;
4092 case nir_intrinsic_load_invocation_id
:
4093 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
4094 result
= unpack_param(&ctx
->ac
, ctx
->nctx
->tcs_rel_ids
, 8, 5);
4096 result
= ctx
->abi
->gs_invocation_id
;
4098 case nir_intrinsic_load_primitive_id
:
4099 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
4101 ctx
->nctx
->shader_info
->gs
.uses_prim_id
= true;
4102 result
= ctx
->abi
->gs_prim_id
;
4103 } else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
4104 ctx
->nctx
->shader_info
->tcs
.uses_prim_id
= true;
4105 result
= ctx
->nctx
->tcs_patch_id
;
4106 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4107 ctx
->nctx
->shader_info
->tcs
.uses_prim_id
= true;
4108 result
= ctx
->nctx
->tes_patch_id
;
4110 fprintf(stderr
, "Unknown primitive id intrinsic: %d", ctx
->stage
);
4112 case nir_intrinsic_load_sample_id
:
4113 result
= unpack_param(&ctx
->ac
, ctx
->abi
->ancillary
, 8, 4);
4115 case nir_intrinsic_load_sample_pos
:
4116 result
= load_sample_pos(ctx
);
4118 case nir_intrinsic_load_sample_mask_in
:
4119 result
= ctx
->abi
->sample_coverage
;
4121 case nir_intrinsic_load_frag_coord
: {
4122 LLVMValueRef values
[4] = {
4123 ctx
->abi
->frag_pos
[0],
4124 ctx
->abi
->frag_pos
[1],
4125 ctx
->abi
->frag_pos
[2],
4126 ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, ctx
->abi
->frag_pos
[3])
4128 result
= ac_build_gather_values(&ctx
->ac
, values
, 4);
4131 case nir_intrinsic_load_front_face
:
4132 result
= ctx
->abi
->front_face
;
4134 case nir_intrinsic_load_instance_id
:
4135 result
= ctx
->abi
->instance_id
;
4137 case nir_intrinsic_load_num_work_groups
:
4138 result
= ctx
->nctx
->num_work_groups
;
4140 case nir_intrinsic_load_local_invocation_index
:
4141 result
= visit_load_local_invocation_index(ctx
->nctx
);
4143 case nir_intrinsic_load_push_constant
:
4144 result
= visit_load_push_constant(ctx
->nctx
, instr
);
4146 case nir_intrinsic_vulkan_resource_index
:
4147 result
= visit_vulkan_resource_index(ctx
->nctx
, instr
);
4149 case nir_intrinsic_vulkan_resource_reindex
:
4150 result
= visit_vulkan_resource_reindex(ctx
->nctx
, instr
);
4152 case nir_intrinsic_store_ssbo
:
4153 visit_store_ssbo(ctx
, instr
);
4155 case nir_intrinsic_load_ssbo
:
4156 result
= visit_load_buffer(ctx
, instr
);
4158 case nir_intrinsic_ssbo_atomic_add
:
4159 case nir_intrinsic_ssbo_atomic_imin
:
4160 case nir_intrinsic_ssbo_atomic_umin
:
4161 case nir_intrinsic_ssbo_atomic_imax
:
4162 case nir_intrinsic_ssbo_atomic_umax
:
4163 case nir_intrinsic_ssbo_atomic_and
:
4164 case nir_intrinsic_ssbo_atomic_or
:
4165 case nir_intrinsic_ssbo_atomic_xor
:
4166 case nir_intrinsic_ssbo_atomic_exchange
:
4167 case nir_intrinsic_ssbo_atomic_comp_swap
:
4168 result
= visit_atomic_ssbo(ctx
, instr
);
4170 case nir_intrinsic_load_ubo
:
4171 result
= visit_load_ubo_buffer(ctx
, instr
);
4173 case nir_intrinsic_get_buffer_size
:
4174 result
= visit_get_buffer_size(ctx
, instr
);
4176 case nir_intrinsic_load_var
:
4177 result
= visit_load_var(ctx
, instr
);
4179 case nir_intrinsic_store_var
:
4180 visit_store_var(ctx
, instr
);
4182 case nir_intrinsic_image_load
:
4183 result
= visit_image_load(ctx
, instr
);
4185 case nir_intrinsic_image_store
:
4186 visit_image_store(ctx
, instr
);
4188 case nir_intrinsic_image_atomic_add
:
4189 case nir_intrinsic_image_atomic_min
:
4190 case nir_intrinsic_image_atomic_max
:
4191 case nir_intrinsic_image_atomic_and
:
4192 case nir_intrinsic_image_atomic_or
:
4193 case nir_intrinsic_image_atomic_xor
:
4194 case nir_intrinsic_image_atomic_exchange
:
4195 case nir_intrinsic_image_atomic_comp_swap
:
4196 result
= visit_image_atomic(ctx
, instr
);
4198 case nir_intrinsic_image_size
:
4199 result
= visit_image_size(ctx
, instr
);
4201 case nir_intrinsic_discard
:
4202 ac_build_intrinsic(&ctx
->ac
, "llvm.AMDGPU.kilp",
4203 LLVMVoidTypeInContext(ctx
->ac
.context
),
4204 NULL
, 0, AC_FUNC_ATTR_LEGACY
);
4206 case nir_intrinsic_discard_if
:
4207 emit_discard_if(ctx
, instr
);
4209 case nir_intrinsic_memory_barrier
:
4210 case nir_intrinsic_group_memory_barrier
:
4211 case nir_intrinsic_memory_barrier_atomic_counter
:
4212 case nir_intrinsic_memory_barrier_buffer
:
4213 case nir_intrinsic_memory_barrier_image
:
4214 case nir_intrinsic_memory_barrier_shared
:
4215 emit_membar(ctx
->nctx
, instr
);
4217 case nir_intrinsic_barrier
:
4218 emit_barrier(ctx
->nctx
);
4220 case nir_intrinsic_var_atomic_add
:
4221 case nir_intrinsic_var_atomic_imin
:
4222 case nir_intrinsic_var_atomic_umin
:
4223 case nir_intrinsic_var_atomic_imax
:
4224 case nir_intrinsic_var_atomic_umax
:
4225 case nir_intrinsic_var_atomic_and
:
4226 case nir_intrinsic_var_atomic_or
:
4227 case nir_intrinsic_var_atomic_xor
:
4228 case nir_intrinsic_var_atomic_exchange
:
4229 case nir_intrinsic_var_atomic_comp_swap
:
4230 result
= visit_var_atomic(ctx
->nctx
, instr
);
4232 case nir_intrinsic_interp_var_at_centroid
:
4233 case nir_intrinsic_interp_var_at_sample
:
4234 case nir_intrinsic_interp_var_at_offset
:
4235 result
= visit_interp(ctx
->nctx
, instr
);
4237 case nir_intrinsic_emit_vertex
:
4238 assert(instr
->const_index
[0] == 0);
4239 ctx
->abi
->emit_vertex(ctx
->abi
, 0, ctx
->outputs
);
4241 case nir_intrinsic_end_primitive
:
4242 visit_end_primitive(ctx
->nctx
, instr
);
4244 case nir_intrinsic_load_tess_coord
:
4245 result
= visit_load_tess_coord(ctx
->nctx
, instr
);
4247 case nir_intrinsic_load_patch_vertices_in
:
4248 result
= LLVMConstInt(ctx
->ac
.i32
, ctx
->nctx
->options
->key
.tcs
.input_vertices
, false);
4251 fprintf(stderr
, "Unknown intrinsic: ");
4252 nir_print_instr(&instr
->instr
, stderr
);
4253 fprintf(stderr
, "\n");
4257 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4261 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
4262 LLVMValueRef buffer_ptr
, bool write
)
4264 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4266 if (write
&& ctx
->stage
== MESA_SHADER_FRAGMENT
)
4267 ctx
->shader_info
->fs
.writes_memory
= true;
4269 return LLVMBuildLoad(ctx
->builder
, buffer_ptr
, "");
4272 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
4274 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4276 return LLVMBuildLoad(ctx
->builder
, buffer_ptr
, "");
4279 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
4280 unsigned descriptor_set
,
4281 unsigned base_index
,
4282 unsigned constant_index
,
4284 enum ac_descriptor_type desc_type
,
4285 bool image
, bool write
)
4287 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4288 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
4289 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
4290 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
4291 unsigned offset
= binding
->offset
;
4292 unsigned stride
= binding
->size
;
4294 LLVMBuilderRef builder
= ctx
->builder
;
4297 assert(base_index
< layout
->binding_count
);
4299 if (write
&& ctx
->stage
== MESA_SHADER_FRAGMENT
)
4300 ctx
->shader_info
->fs
.writes_memory
= true;
4302 switch (desc_type
) {
4304 type
= ctx
->ac
.v8i32
;
4308 type
= ctx
->ac
.v8i32
;
4312 case AC_DESC_SAMPLER
:
4313 type
= ctx
->ac
.v4i32
;
4314 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
4319 case AC_DESC_BUFFER
:
4320 type
= ctx
->ac
.v4i32
;
4324 unreachable("invalid desc_type\n");
4327 offset
+= constant_index
* stride
;
4329 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
4330 (!index
|| binding
->immutable_samplers_equal
)) {
4331 if (binding
->immutable_samplers_equal
)
4334 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
4336 LLVMValueRef constants
[] = {
4337 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
4338 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
4339 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
4340 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
4342 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
4345 assert(stride
% type_size
== 0);
4348 index
= ctx
->ac
.i32_0
;
4350 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
4352 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->ac
.i32
, offset
, 0));
4353 list
= LLVMBuildPointerCast(builder
, list
, const_array(type
, 0), "");
4355 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
4358 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
4359 const nir_deref_var
*deref
,
4360 enum ac_descriptor_type desc_type
,
4361 const nir_tex_instr
*tex_instr
,
4362 bool image
, bool write
)
4364 LLVMValueRef index
= NULL
;
4365 unsigned constant_index
= 0;
4366 unsigned descriptor_set
;
4367 unsigned base_index
;
4370 assert(tex_instr
&& !image
);
4372 base_index
= tex_instr
->sampler_index
;
4374 const nir_deref
*tail
= &deref
->deref
;
4375 while (tail
->child
) {
4376 const nir_deref_array
*child
= nir_deref_as_array(tail
->child
);
4377 unsigned array_size
= glsl_get_aoa_size(tail
->child
->type
);
4382 assert(child
->deref_array_type
!= nir_deref_array_type_wildcard
);
4384 if (child
->deref_array_type
== nir_deref_array_type_indirect
) {
4385 LLVMValueRef indirect
= get_src(ctx
, child
->indirect
);
4387 indirect
= LLVMBuildMul(ctx
->ac
.builder
, indirect
,
4388 LLVMConstInt(ctx
->ac
.i32
, array_size
, false), "");
4393 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
, indirect
, "");
4396 constant_index
+= child
->base_offset
* array_size
;
4398 tail
= &child
->deref
;
4400 descriptor_set
= deref
->var
->data
.descriptor_set
;
4401 base_index
= deref
->var
->data
.binding
;
4404 return ctx
->abi
->load_sampler_desc(ctx
->abi
,
4407 constant_index
, index
,
4408 desc_type
, image
, write
);
4411 static void set_tex_fetch_args(struct ac_llvm_context
*ctx
,
4412 struct ac_image_args
*args
,
4413 const nir_tex_instr
*instr
,
4415 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
4416 LLVMValueRef
*param
, unsigned count
,
4419 unsigned is_rect
= 0;
4420 bool da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
4422 if (op
== nir_texop_lod
)
4424 /* Pad to power of two vector */
4425 while (count
< util_next_power_of_two(count
))
4426 param
[count
++] = LLVMGetUndef(ctx
->i32
);
4429 args
->addr
= ac_build_gather_values(ctx
, param
, count
);
4431 args
->addr
= param
[0];
4433 args
->resource
= res_ptr
;
4434 args
->sampler
= samp_ptr
;
4436 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
&& op
== nir_texop_txf
) {
4437 args
->addr
= param
[0];
4441 args
->dmask
= dmask
;
4442 args
->unorm
= is_rect
;
4446 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4449 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4450 * filtering manually. The driver sets img7 to a mask clearing
4451 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4452 * s_and_b32 samp0, samp0, img7
4455 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4457 static LLVMValueRef
sici_fix_sampler_aniso(struct ac_nir_context
*ctx
,
4458 LLVMValueRef res
, LLVMValueRef samp
)
4460 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4461 LLVMValueRef img7
, samp0
;
4463 if (ctx
->ac
.chip_class
>= VI
)
4466 img7
= LLVMBuildExtractElement(builder
, res
,
4467 LLVMConstInt(ctx
->ac
.i32
, 7, 0), "");
4468 samp0
= LLVMBuildExtractElement(builder
, samp
,
4469 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4470 samp0
= LLVMBuildAnd(builder
, samp0
, img7
, "");
4471 return LLVMBuildInsertElement(builder
, samp
, samp0
,
4472 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4475 static void tex_fetch_ptrs(struct ac_nir_context
*ctx
,
4476 nir_tex_instr
*instr
,
4477 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
4478 LLVMValueRef
*fmask_ptr
)
4480 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4481 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_BUFFER
, instr
, false, false);
4483 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_IMAGE
, instr
, false, false);
4486 *samp_ptr
= get_sampler_desc(ctx
, instr
->sampler
, AC_DESC_SAMPLER
, instr
, false, false);
4488 *samp_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_SAMPLER
, instr
, false, false);
4489 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
)
4490 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
4492 if (fmask_ptr
&& !instr
->sampler
&& (instr
->op
== nir_texop_txf_ms
||
4493 instr
->op
== nir_texop_samples_identical
))
4494 *fmask_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_FMASK
, instr
, false, false);
4497 static LLVMValueRef
apply_round_slice(struct ac_llvm_context
*ctx
,
4500 coord
= ac_to_float(ctx
, coord
);
4501 coord
= ac_build_intrinsic(ctx
, "llvm.rint.f32", ctx
->f32
, &coord
, 1, 0);
4502 coord
= ac_to_integer(ctx
, coord
);
4506 static void visit_tex(struct ac_nir_context
*ctx
, nir_tex_instr
*instr
)
4508 LLVMValueRef result
= NULL
;
4509 struct ac_image_args args
= { 0 };
4510 unsigned dmask
= 0xf;
4511 LLVMValueRef address
[16];
4512 LLVMValueRef coords
[5];
4513 LLVMValueRef coord
= NULL
, lod
= NULL
, comparator
= NULL
;
4514 LLVMValueRef bias
= NULL
, offsets
= NULL
;
4515 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
, sample_index
= NULL
;
4516 LLVMValueRef ddx
= NULL
, ddy
= NULL
;
4517 LLVMValueRef derivs
[6];
4518 unsigned chan
, count
= 0;
4519 unsigned const_src
= 0, num_deriv_comp
= 0;
4520 bool lod_is_zero
= false;
4522 tex_fetch_ptrs(ctx
, instr
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4524 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4525 switch (instr
->src
[i
].src_type
) {
4526 case nir_tex_src_coord
:
4527 coord
= get_src(ctx
, instr
->src
[i
].src
);
4529 case nir_tex_src_projector
:
4531 case nir_tex_src_comparator
:
4532 comparator
= get_src(ctx
, instr
->src
[i
].src
);
4534 case nir_tex_src_offset
:
4535 offsets
= get_src(ctx
, instr
->src
[i
].src
);
4538 case nir_tex_src_bias
:
4539 bias
= get_src(ctx
, instr
->src
[i
].src
);
4541 case nir_tex_src_lod
: {
4542 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
4544 if (val
&& val
->i32
[0] == 0)
4546 lod
= get_src(ctx
, instr
->src
[i
].src
);
4549 case nir_tex_src_ms_index
:
4550 sample_index
= get_src(ctx
, instr
->src
[i
].src
);
4552 case nir_tex_src_ms_mcs
:
4554 case nir_tex_src_ddx
:
4555 ddx
= get_src(ctx
, instr
->src
[i
].src
);
4556 num_deriv_comp
= instr
->src
[i
].src
.ssa
->num_components
;
4558 case nir_tex_src_ddy
:
4559 ddy
= get_src(ctx
, instr
->src
[i
].src
);
4561 case nir_tex_src_texture_offset
:
4562 case nir_tex_src_sampler_offset
:
4563 case nir_tex_src_plane
:
4569 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
4570 result
= get_buffer_size(ctx
, res_ptr
, true);
4574 if (instr
->op
== nir_texop_texture_samples
) {
4575 LLVMValueRef res
, samples
, is_msaa
;
4576 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->ac
.v8i32
, "");
4577 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
4578 LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
4579 is_msaa
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4580 LLVMConstInt(ctx
->ac
.i32
, 28, false), "");
4581 is_msaa
= LLVMBuildAnd(ctx
->ac
.builder
, is_msaa
,
4582 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4583 is_msaa
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, is_msaa
,
4584 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4586 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4587 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
4588 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
4589 LLVMConstInt(ctx
->ac
.i32
, 0xf, false), "");
4590 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->ac
.i32_1
,
4592 samples
= LLVMBuildSelect(ctx
->ac
.builder
, is_msaa
, samples
,
4599 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4600 coords
[chan
] = llvm_extract_elem(&ctx
->ac
, coord
, chan
);
4602 if (offsets
&& instr
->op
!= nir_texop_txf
) {
4603 LLVMValueRef offset
[3], pack
;
4604 for (chan
= 0; chan
< 3; ++chan
)
4605 offset
[chan
] = ctx
->ac
.i32_0
;
4608 for (chan
= 0; chan
< get_llvm_num_components(offsets
); chan
++) {
4609 offset
[chan
] = llvm_extract_elem(&ctx
->ac
, offsets
, chan
);
4610 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
4611 LLVMConstInt(ctx
->ac
.i32
, 0x3f, false), "");
4613 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
4614 LLVMConstInt(ctx
->ac
.i32
, chan
* 8, false), "");
4616 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
4617 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
4618 address
[count
++] = pack
;
4621 /* pack LOD bias value */
4622 if (instr
->op
== nir_texop_txb
&& bias
) {
4623 address
[count
++] = bias
;
4626 /* Pack depth comparison value */
4627 if (instr
->is_shadow
&& comparator
) {
4628 LLVMValueRef z
= ac_to_float(&ctx
->ac
,
4629 llvm_extract_elem(&ctx
->ac
, comparator
, 0));
4631 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4632 * so the depth comparison value isn't clamped for Z16 and
4633 * Z24 anymore. Do it manually here.
4635 * It's unnecessary if the original texture format was
4636 * Z32_FLOAT, but we don't know that here.
4638 if (ctx
->ac
.chip_class
== VI
&& ctx
->abi
->clamp_shadow_reference
)
4639 z
= ac_build_clamp(&ctx
->ac
, z
);
4641 address
[count
++] = z
;
4644 /* pack derivatives */
4646 int num_src_deriv_channels
, num_dest_deriv_channels
;
4647 switch (instr
->sampler_dim
) {
4648 case GLSL_SAMPLER_DIM_3D
:
4649 case GLSL_SAMPLER_DIM_CUBE
:
4651 num_src_deriv_channels
= 3;
4652 num_dest_deriv_channels
= 3;
4654 case GLSL_SAMPLER_DIM_2D
:
4656 num_src_deriv_channels
= 2;
4657 num_dest_deriv_channels
= 2;
4660 case GLSL_SAMPLER_DIM_1D
:
4661 num_src_deriv_channels
= 1;
4662 if (ctx
->ac
.chip_class
>= GFX9
) {
4663 num_dest_deriv_channels
= 2;
4666 num_dest_deriv_channels
= 1;
4672 for (unsigned i
= 0; i
< num_src_deriv_channels
; i
++) {
4673 derivs
[i
] = ac_to_float(&ctx
->ac
, llvm_extract_elem(&ctx
->ac
, ddx
, i
));
4674 derivs
[num_dest_deriv_channels
+ i
] = ac_to_float(&ctx
->ac
, llvm_extract_elem(&ctx
->ac
, ddy
, i
));
4676 for (unsigned i
= num_src_deriv_channels
; i
< num_dest_deriv_channels
; i
++) {
4677 derivs
[i
] = ctx
->ac
.f32_0
;
4678 derivs
[num_dest_deriv_channels
+ i
] = ctx
->ac
.f32_0
;
4682 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& coord
) {
4683 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4684 coords
[chan
] = ac_to_float(&ctx
->ac
, coords
[chan
]);
4685 if (instr
->coord_components
== 3)
4686 coords
[3] = LLVMGetUndef(ctx
->ac
.f32
);
4687 ac_prepare_cube_coords(&ctx
->ac
,
4688 instr
->op
== nir_texop_txd
, instr
->is_array
,
4689 instr
->op
== nir_texop_lod
, coords
, derivs
);
4695 for (unsigned i
= 0; i
< num_deriv_comp
* 2; i
++)
4696 address
[count
++] = derivs
[i
];
4699 /* Pack texture coordinates */
4701 address
[count
++] = coords
[0];
4702 if (instr
->coord_components
> 1) {
4703 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& instr
->is_array
&& instr
->op
!= nir_texop_txf
) {
4704 coords
[1] = apply_round_slice(&ctx
->ac
, coords
[1]);
4706 address
[count
++] = coords
[1];
4708 if (instr
->coord_components
> 2) {
4709 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4710 if (instr
->sampler_dim
!= GLSL_SAMPLER_DIM_3D
&&
4711 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_CUBE
&&
4712 instr
->op
!= nir_texop_txf
) {
4713 coords
[2] = apply_round_slice(&ctx
->ac
, coords
[2]);
4715 address
[count
++] = coords
[2];
4718 if (ctx
->ac
.chip_class
>= GFX9
) {
4719 LLVMValueRef filler
;
4720 if (instr
->op
== nir_texop_txf
)
4721 filler
= ctx
->ac
.i32_0
;
4723 filler
= LLVMConstReal(ctx
->ac
.f32
, 0.5);
4725 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
) {
4726 /* No nir_texop_lod, because it does not take a slice
4727 * even with array textures. */
4728 if (instr
->is_array
&& instr
->op
!= nir_texop_lod
) {
4729 address
[count
] = address
[count
- 1];
4730 address
[count
- 1] = filler
;
4733 address
[count
++] = filler
;
4739 if (lod
&& ((instr
->op
== nir_texop_txl
&& !lod_is_zero
) ||
4740 instr
->op
== nir_texop_txf
)) {
4741 address
[count
++] = lod
;
4742 } else if (instr
->op
== nir_texop_txf_ms
&& sample_index
) {
4743 address
[count
++] = sample_index
;
4744 } else if(instr
->op
== nir_texop_txs
) {
4747 address
[count
++] = lod
;
4749 address
[count
++] = ctx
->ac
.i32_0
;
4752 for (chan
= 0; chan
< count
; chan
++) {
4753 address
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
,
4754 address
[chan
], ctx
->ac
.i32
, "");
4757 if (instr
->op
== nir_texop_samples_identical
) {
4758 LLVMValueRef txf_address
[4];
4759 struct ac_image_args txf_args
= { 0 };
4760 unsigned txf_count
= count
;
4761 memcpy(txf_address
, address
, sizeof(txf_address
));
4763 if (!instr
->is_array
)
4764 txf_address
[2] = ctx
->ac
.i32_0
;
4765 txf_address
[3] = ctx
->ac
.i32_0
;
4767 set_tex_fetch_args(&ctx
->ac
, &txf_args
, instr
, nir_texop_txf
,
4769 txf_address
, txf_count
, 0xf);
4771 result
= build_tex_intrinsic(ctx
, instr
, false, &txf_args
);
4773 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
4774 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, result
, ctx
->ac
.i32_0
);
4778 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
&&
4779 instr
->op
!= nir_texop_txs
) {
4780 unsigned sample_chan
= instr
->is_array
? 3 : 2;
4781 address
[sample_chan
] = adjust_sample_index_using_fmask(&ctx
->ac
,
4784 instr
->is_array
? address
[2] : NULL
,
4785 address
[sample_chan
],
4789 if (offsets
&& instr
->op
== nir_texop_txf
) {
4790 nir_const_value
*const_offset
=
4791 nir_src_as_const_value(instr
->src
[const_src
].src
);
4792 int num_offsets
= instr
->src
[const_src
].src
.ssa
->num_components
;
4793 assert(const_offset
);
4794 num_offsets
= MIN2(num_offsets
, instr
->coord_components
);
4795 if (num_offsets
> 2)
4796 address
[2] = LLVMBuildAdd(ctx
->ac
.builder
,
4797 address
[2], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[2], false), "");
4798 if (num_offsets
> 1)
4799 address
[1] = LLVMBuildAdd(ctx
->ac
.builder
,
4800 address
[1], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[1], false), "");
4801 address
[0] = LLVMBuildAdd(ctx
->ac
.builder
,
4802 address
[0], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[0], false), "");
4806 /* TODO TG4 support */
4807 if (instr
->op
== nir_texop_tg4
) {
4808 if (instr
->is_shadow
)
4811 dmask
= 1 << instr
->component
;
4813 set_tex_fetch_args(&ctx
->ac
, &args
, instr
, instr
->op
,
4814 res_ptr
, samp_ptr
, address
, count
, dmask
);
4816 result
= build_tex_intrinsic(ctx
, instr
, lod_is_zero
, &args
);
4818 if (instr
->op
== nir_texop_query_levels
)
4819 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
4820 else if (instr
->is_shadow
&& instr
->is_new_style_shadow
&&
4821 instr
->op
!= nir_texop_txs
&& instr
->op
!= nir_texop_lod
&&
4822 instr
->op
!= nir_texop_tg4
)
4823 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
4824 else if (instr
->op
== nir_texop_txs
&&
4825 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
4827 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
4828 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
4829 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
4830 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
4831 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, z
, two
, "");
4832 } else if (ctx
->ac
.chip_class
>= GFX9
&&
4833 instr
->op
== nir_texop_txs
&&
4834 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
4836 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
4837 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
4838 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, layers
,
4840 } else if (instr
->dest
.ssa
.num_components
!= 4)
4841 result
= trim_vector(&ctx
->ac
, result
, instr
->dest
.ssa
.num_components
);
4845 assert(instr
->dest
.is_ssa
);
4846 result
= ac_to_integer(&ctx
->ac
, result
);
4847 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4852 static void visit_phi(struct ac_nir_context
*ctx
, nir_phi_instr
*instr
)
4854 LLVMTypeRef type
= get_def_type(ctx
, &instr
->dest
.ssa
);
4855 LLVMValueRef result
= LLVMBuildPhi(ctx
->ac
.builder
, type
, "");
4857 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4858 _mesa_hash_table_insert(ctx
->phis
, instr
, result
);
4861 static void visit_post_phi(struct ac_nir_context
*ctx
,
4862 nir_phi_instr
*instr
,
4863 LLVMValueRef llvm_phi
)
4865 nir_foreach_phi_src(src
, instr
) {
4866 LLVMBasicBlockRef block
= get_block(ctx
, src
->pred
);
4867 LLVMValueRef llvm_src
= get_src(ctx
, src
->src
);
4869 LLVMAddIncoming(llvm_phi
, &llvm_src
, &block
, 1);
4873 static void phi_post_pass(struct ac_nir_context
*ctx
)
4875 struct hash_entry
*entry
;
4876 hash_table_foreach(ctx
->phis
, entry
) {
4877 visit_post_phi(ctx
, (nir_phi_instr
*)entry
->key
,
4878 (LLVMValueRef
)entry
->data
);
4883 static void visit_ssa_undef(struct ac_nir_context
*ctx
,
4884 const nir_ssa_undef_instr
*instr
)
4886 unsigned num_components
= instr
->def
.num_components
;
4889 if (num_components
== 1)
4890 undef
= LLVMGetUndef(ctx
->ac
.i32
);
4892 undef
= LLVMGetUndef(LLVMVectorType(ctx
->ac
.i32
, num_components
));
4894 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, undef
);
4897 static void visit_jump(struct ac_nir_context
*ctx
,
4898 const nir_jump_instr
*instr
)
4900 switch (instr
->type
) {
4901 case nir_jump_break
:
4902 LLVMBuildBr(ctx
->ac
.builder
, ctx
->break_block
);
4903 LLVMClearInsertionPosition(ctx
->ac
.builder
);
4905 case nir_jump_continue
:
4906 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
4907 LLVMClearInsertionPosition(ctx
->ac
.builder
);
4910 fprintf(stderr
, "Unknown NIR jump instr: ");
4911 nir_print_instr(&instr
->instr
, stderr
);
4912 fprintf(stderr
, "\n");
4917 static void visit_cf_list(struct ac_nir_context
*ctx
,
4918 struct exec_list
*list
);
4920 static void visit_block(struct ac_nir_context
*ctx
, nir_block
*block
)
4922 LLVMBasicBlockRef llvm_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
4923 nir_foreach_instr(instr
, block
)
4925 switch (instr
->type
) {
4926 case nir_instr_type_alu
:
4927 visit_alu(ctx
, nir_instr_as_alu(instr
));
4929 case nir_instr_type_load_const
:
4930 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
4932 case nir_instr_type_intrinsic
:
4933 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
4935 case nir_instr_type_tex
:
4936 visit_tex(ctx
, nir_instr_as_tex(instr
));
4938 case nir_instr_type_phi
:
4939 visit_phi(ctx
, nir_instr_as_phi(instr
));
4941 case nir_instr_type_ssa_undef
:
4942 visit_ssa_undef(ctx
, nir_instr_as_ssa_undef(instr
));
4944 case nir_instr_type_jump
:
4945 visit_jump(ctx
, nir_instr_as_jump(instr
));
4948 fprintf(stderr
, "Unknown NIR instr type: ");
4949 nir_print_instr(instr
, stderr
);
4950 fprintf(stderr
, "\n");
4955 _mesa_hash_table_insert(ctx
->defs
, block
, llvm_block
);
4958 static void visit_if(struct ac_nir_context
*ctx
, nir_if
*if_stmt
)
4960 LLVMValueRef value
= get_src(ctx
, if_stmt
->condition
);
4962 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
4963 LLVMBasicBlockRef merge_block
=
4964 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
4965 LLVMBasicBlockRef if_block
=
4966 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
4967 LLVMBasicBlockRef else_block
= merge_block
;
4968 if (!exec_list_is_empty(&if_stmt
->else_list
))
4969 else_block
= LLVMAppendBasicBlockInContext(
4970 ctx
->ac
.context
, fn
, "");
4972 LLVMValueRef cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
, value
,
4974 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, if_block
, else_block
);
4976 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, if_block
);
4977 visit_cf_list(ctx
, &if_stmt
->then_list
);
4978 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
4979 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
4981 if (!exec_list_is_empty(&if_stmt
->else_list
)) {
4982 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, else_block
);
4983 visit_cf_list(ctx
, &if_stmt
->else_list
);
4984 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
4985 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
4988 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
4991 static void visit_loop(struct ac_nir_context
*ctx
, nir_loop
*loop
)
4993 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
4994 LLVMBasicBlockRef continue_parent
= ctx
->continue_block
;
4995 LLVMBasicBlockRef break_parent
= ctx
->break_block
;
4997 ctx
->continue_block
=
4998 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5000 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5002 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5003 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->continue_block
);
5004 visit_cf_list(ctx
, &loop
->body
);
5006 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5007 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5008 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->break_block
);
5010 ctx
->continue_block
= continue_parent
;
5011 ctx
->break_block
= break_parent
;
5014 static void visit_cf_list(struct ac_nir_context
*ctx
,
5015 struct exec_list
*list
)
5017 foreach_list_typed(nir_cf_node
, node
, node
, list
)
5019 switch (node
->type
) {
5020 case nir_cf_node_block
:
5021 visit_block(ctx
, nir_cf_node_as_block(node
));
5024 case nir_cf_node_if
:
5025 visit_if(ctx
, nir_cf_node_as_if(node
));
5028 case nir_cf_node_loop
:
5029 visit_loop(ctx
, nir_cf_node_as_loop(node
));
5039 handle_vs_input_decl(struct nir_to_llvm_context
*ctx
,
5040 struct nir_variable
*variable
)
5042 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
5043 LLVMValueRef t_offset
;
5044 LLVMValueRef t_list
;
5046 LLVMValueRef buffer_index
;
5047 int index
= variable
->data
.location
- VERT_ATTRIB_GENERIC0
;
5048 int idx
= variable
->data
.location
;
5049 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
5051 variable
->data
.driver_location
= idx
* 4;
5053 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << index
)) {
5054 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.instance_id
,
5055 ctx
->abi
.start_instance
, "");
5056 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(3,
5057 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5059 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.vertex_id
,
5060 ctx
->abi
.base_vertex
, "");
5062 for (unsigned i
= 0; i
< attrib_count
; ++i
, ++idx
) {
5063 t_offset
= LLVMConstInt(ctx
->ac
.i32
, index
+ i
, false);
5065 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
5067 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
5072 for (unsigned chan
= 0; chan
< 4; chan
++) {
5073 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5074 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
, chan
)] =
5075 ac_to_integer(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
,
5076 input
, llvm_chan
, ""));
5081 static void interp_fs_input(struct nir_to_llvm_context
*ctx
,
5083 LLVMValueRef interp_param
,
5084 LLVMValueRef prim_mask
,
5085 LLVMValueRef result
[4])
5087 LLVMValueRef attr_number
;
5090 bool interp
= interp_param
!= NULL
;
5092 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
5094 /* fs.constant returns the param from the middle vertex, so it's not
5095 * really useful for flat shading. It's meant to be used for custom
5096 * interpolation (but the intrinsic can't fetch from the other two
5099 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5100 * to do the right thing. The only reason we use fs.constant is that
5101 * fs.interp cannot be used on integers, because they can be equal
5105 interp_param
= LLVMBuildBitCast(ctx
->builder
, interp_param
,
5108 i
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
5110 j
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
5114 for (chan
= 0; chan
< 4; chan
++) {
5115 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5118 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
5123 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
5124 LLVMConstInt(ctx
->ac
.i32
, 2, false),
5133 handle_fs_input_decl(struct nir_to_llvm_context
*ctx
,
5134 struct nir_variable
*variable
)
5136 int idx
= variable
->data
.location
;
5137 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5138 LLVMValueRef interp
;
5140 variable
->data
.driver_location
= idx
* 4;
5141 ctx
->input_mask
|= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
5143 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
5144 unsigned interp_type
;
5145 if (variable
->data
.sample
) {
5146 interp_type
= INTERP_SAMPLE
;
5147 ctx
->shader_info
->info
.ps
.force_persample
= true;
5148 } else if (variable
->data
.centroid
)
5149 interp_type
= INTERP_CENTROID
;
5151 interp_type
= INTERP_CENTER
;
5153 interp
= lookup_interp_param(ctx
, variable
->data
.interpolation
, interp_type
);
5157 for (unsigned i
= 0; i
< attrib_count
; ++i
)
5158 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
5163 handle_vs_inputs(struct nir_to_llvm_context
*ctx
,
5164 struct nir_shader
*nir
) {
5165 nir_foreach_variable(variable
, &nir
->inputs
)
5166 handle_vs_input_decl(ctx
, variable
);
5170 prepare_interp_optimize(struct nir_to_llvm_context
*ctx
,
5171 struct nir_shader
*nir
)
5173 if (!ctx
->options
->key
.fs
.multisample
)
5176 bool uses_center
= false;
5177 bool uses_centroid
= false;
5178 nir_foreach_variable(variable
, &nir
->inputs
) {
5179 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
5180 variable
->data
.sample
)
5183 if (variable
->data
.centroid
)
5184 uses_centroid
= true;
5189 if (uses_center
&& uses_centroid
) {
5190 LLVMValueRef sel
= LLVMBuildICmp(ctx
->builder
, LLVMIntSLT
, ctx
->prim_mask
, ctx
->ac
.i32_0
, "");
5191 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
5192 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
5197 handle_fs_inputs(struct nir_to_llvm_context
*ctx
,
5198 struct nir_shader
*nir
)
5200 prepare_interp_optimize(ctx
, nir
);
5202 nir_foreach_variable(variable
, &nir
->inputs
)
5203 handle_fs_input_decl(ctx
, variable
);
5207 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
5208 ctx
->shader_info
->info
.needs_multiview_view_index
)
5209 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
5211 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
5212 LLVMValueRef interp_param
;
5213 LLVMValueRef
*inputs
= ctx
->inputs
+radeon_llvm_reg_index_soa(i
, 0);
5215 if (!(ctx
->input_mask
& (1ull << i
)))
5218 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
5219 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
5220 interp_param
= *inputs
;
5221 interp_fs_input(ctx
, index
, interp_param
, ctx
->prim_mask
,
5225 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
5227 } else if (i
== VARYING_SLOT_POS
) {
5228 for(int i
= 0; i
< 3; ++i
)
5229 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
5231 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
5232 ctx
->abi
.frag_pos
[3]);
5235 ctx
->shader_info
->fs
.num_interp
= index
;
5236 if (ctx
->input_mask
& (1 << VARYING_SLOT_PNTC
))
5237 ctx
->shader_info
->fs
.has_pcoord
= true;
5238 if (ctx
->input_mask
& (1 << VARYING_SLOT_PRIMITIVE_ID
))
5239 ctx
->shader_info
->fs
.prim_id_input
= true;
5240 if (ctx
->input_mask
& (1 << VARYING_SLOT_LAYER
))
5241 ctx
->shader_info
->fs
.layer_input
= true;
5242 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
5244 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
5245 ctx
->view_index
= ctx
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5249 ac_build_alloca(struct ac_llvm_context
*ac
,
5253 LLVMBuilderRef builder
= ac
->builder
;
5254 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(builder
);
5255 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
5256 LLVMBasicBlockRef first_block
= LLVMGetEntryBasicBlock(function
);
5257 LLVMValueRef first_instr
= LLVMGetFirstInstruction(first_block
);
5258 LLVMBuilderRef first_builder
= LLVMCreateBuilderInContext(ac
->context
);
5262 LLVMPositionBuilderBefore(first_builder
, first_instr
);
5264 LLVMPositionBuilderAtEnd(first_builder
, first_block
);
5267 res
= LLVMBuildAlloca(first_builder
, type
, name
);
5268 LLVMBuildStore(builder
, LLVMConstNull(type
), res
);
5270 LLVMDisposeBuilder(first_builder
);
5275 static LLVMValueRef
si_build_alloca_undef(struct ac_llvm_context
*ac
,
5279 LLVMValueRef ptr
= ac_build_alloca(ac
, type
, name
);
5280 LLVMBuildStore(ac
->builder
, LLVMGetUndef(type
), ptr
);
5285 scan_shader_output_decl(struct nir_to_llvm_context
*ctx
,
5286 struct nir_variable
*variable
,
5287 struct nir_shader
*shader
,
5288 gl_shader_stage stage
)
5290 int idx
= variable
->data
.location
+ variable
->data
.index
;
5291 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5292 uint64_t mask_attribs
;
5294 variable
->data
.driver_location
= idx
* 4;
5296 /* tess ctrl has it's own load/store paths for outputs */
5297 if (stage
== MESA_SHADER_TESS_CTRL
)
5300 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
5301 if (stage
== MESA_SHADER_VERTEX
||
5302 stage
== MESA_SHADER_TESS_EVAL
||
5303 stage
== MESA_SHADER_GEOMETRY
) {
5304 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5305 int length
= shader
->info
.clip_distance_array_size
+
5306 shader
->info
.cull_distance_array_size
;
5307 if (stage
== MESA_SHADER_VERTEX
) {
5308 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5309 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5311 if (stage
== MESA_SHADER_TESS_EVAL
) {
5312 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5313 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5320 mask_attribs
= 1ull << idx
;
5324 ctx
->output_mask
|= mask_attribs
;
5328 handle_shader_output_decl(struct ac_nir_context
*ctx
,
5329 struct nir_shader
*nir
,
5330 struct nir_variable
*variable
)
5332 unsigned output_loc
= variable
->data
.driver_location
/ 4;
5333 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5335 /* tess ctrl has it's own load/store paths for outputs */
5336 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
5339 if (ctx
->stage
== MESA_SHADER_VERTEX
||
5340 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
5341 ctx
->stage
== MESA_SHADER_GEOMETRY
) {
5342 int idx
= variable
->data
.location
+ variable
->data
.index
;
5343 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5344 int length
= nir
->info
.clip_distance_array_size
+
5345 nir
->info
.cull_distance_array_size
;
5354 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
5355 for (unsigned chan
= 0; chan
< 4; chan
++) {
5356 ctx
->outputs
[radeon_llvm_reg_index_soa(output_loc
+ i
, chan
)] =
5357 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5363 glsl_base_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5364 enum glsl_base_type type
)
5368 case GLSL_TYPE_UINT
:
5369 case GLSL_TYPE_BOOL
:
5370 case GLSL_TYPE_SUBROUTINE
:
5372 case GLSL_TYPE_FLOAT
: /* TODO handle mediump */
5374 case GLSL_TYPE_INT64
:
5375 case GLSL_TYPE_UINT64
:
5377 case GLSL_TYPE_DOUBLE
:
5380 unreachable("unknown GLSL type");
5385 glsl_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5386 const struct glsl_type
*type
)
5388 if (glsl_type_is_scalar(type
)) {
5389 return glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
));
5392 if (glsl_type_is_vector(type
)) {
5393 return LLVMVectorType(
5394 glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
)),
5395 glsl_get_vector_elements(type
));
5398 if (glsl_type_is_matrix(type
)) {
5399 return LLVMArrayType(
5400 glsl_to_llvm_type(ctx
, glsl_get_column_type(type
)),
5401 glsl_get_matrix_columns(type
));
5404 if (glsl_type_is_array(type
)) {
5405 return LLVMArrayType(
5406 glsl_to_llvm_type(ctx
, glsl_get_array_element(type
)),
5407 glsl_get_length(type
));
5410 assert(glsl_type_is_struct(type
));
5412 LLVMTypeRef member_types
[glsl_get_length(type
)];
5414 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
5416 glsl_to_llvm_type(ctx
,
5417 glsl_get_struct_field(type
, i
));
5420 return LLVMStructTypeInContext(ctx
->context
, member_types
,
5421 glsl_get_length(type
), false);
5425 setup_locals(struct ac_nir_context
*ctx
,
5426 struct nir_function
*func
)
5429 ctx
->num_locals
= 0;
5430 nir_foreach_variable(variable
, &func
->impl
->locals
) {
5431 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5432 variable
->data
.driver_location
= ctx
->num_locals
* 4;
5433 ctx
->num_locals
+= attrib_count
;
5435 ctx
->locals
= malloc(4 * ctx
->num_locals
* sizeof(LLVMValueRef
));
5439 for (i
= 0; i
< ctx
->num_locals
; i
++) {
5440 for (j
= 0; j
< 4; j
++) {
5441 ctx
->locals
[i
* 4 + j
] =
5442 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "temp");
5448 setup_shared(struct ac_nir_context
*ctx
,
5449 struct nir_shader
*nir
)
5451 nir_foreach_variable(variable
, &nir
->shared
) {
5452 LLVMValueRef shared
=
5453 LLVMAddGlobalInAddressSpace(
5454 ctx
->ac
.module
, glsl_to_llvm_type(ctx
->nctx
, variable
->type
),
5455 variable
->name
? variable
->name
: "",
5457 _mesa_hash_table_insert(ctx
->vars
, variable
, shared
);
5462 emit_float_saturate(struct ac_llvm_context
*ctx
, LLVMValueRef v
, float lo
, float hi
)
5464 v
= ac_to_float(ctx
, v
);
5465 v
= emit_intrin_2f_param(ctx
, "llvm.maxnum", ctx
->f32
, v
, LLVMConstReal(ctx
->f32
, lo
));
5466 return emit_intrin_2f_param(ctx
, "llvm.minnum", ctx
->f32
, v
, LLVMConstReal(ctx
->f32
, hi
));
5470 static LLVMValueRef
emit_pack_int16(struct nir_to_llvm_context
*ctx
,
5471 LLVMValueRef src0
, LLVMValueRef src1
)
5473 LLVMValueRef const16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
5474 LLVMValueRef comp
[2];
5476 comp
[0] = LLVMBuildAnd(ctx
->builder
, src0
, LLVMConstInt(ctx
->ac
.i32
, 65535, 0), "");
5477 comp
[1] = LLVMBuildAnd(ctx
->builder
, src1
, LLVMConstInt(ctx
->ac
.i32
, 65535, 0), "");
5478 comp
[1] = LLVMBuildShl(ctx
->builder
, comp
[1], const16
, "");
5479 return LLVMBuildOr(ctx
->builder
, comp
[0], comp
[1], "");
5482 /* Initialize arguments for the shader export intrinsic */
5484 si_llvm_init_export_args(struct nir_to_llvm_context
*ctx
,
5485 LLVMValueRef
*values
,
5487 struct ac_export_args
*args
)
5489 /* Default is 0xf. Adjusted below depending on the format. */
5490 args
->enabled_channels
= 0xf;
5492 /* Specify whether the EXEC mask represents the valid mask */
5493 args
->valid_mask
= 0;
5495 /* Specify whether this is the last export */
5498 /* Specify the target we are exporting */
5499 args
->target
= target
;
5501 args
->compr
= false;
5502 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
5503 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
5504 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
5505 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
5510 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& target
>= V_008DFC_SQ_EXP_MRT
) {
5511 LLVMValueRef val
[4];
5512 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
5513 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
5514 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
5515 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
5517 switch(col_format
) {
5518 case V_028714_SPI_SHADER_ZERO
:
5519 args
->enabled_channels
= 0; /* writemask */
5520 args
->target
= V_008DFC_SQ_EXP_NULL
;
5523 case V_028714_SPI_SHADER_32_R
:
5524 args
->enabled_channels
= 1;
5525 args
->out
[0] = values
[0];
5528 case V_028714_SPI_SHADER_32_GR
:
5529 args
->enabled_channels
= 0x3;
5530 args
->out
[0] = values
[0];
5531 args
->out
[1] = values
[1];
5534 case V_028714_SPI_SHADER_32_AR
:
5535 args
->enabled_channels
= 0x9;
5536 args
->out
[0] = values
[0];
5537 args
->out
[3] = values
[3];
5540 case V_028714_SPI_SHADER_FP16_ABGR
:
5543 for (unsigned chan
= 0; chan
< 2; chan
++) {
5544 LLVMValueRef pack_args
[2] = {
5546 values
[2 * chan
+ 1]
5548 LLVMValueRef packed
;
5550 packed
= ac_build_cvt_pkrtz_f16(&ctx
->ac
, pack_args
);
5551 args
->out
[chan
] = packed
;
5555 case V_028714_SPI_SHADER_UNORM16_ABGR
:
5556 for (unsigned chan
= 0; chan
< 4; chan
++) {
5557 val
[chan
] = ac_build_clamp(&ctx
->ac
, values
[chan
]);
5558 val
[chan
] = LLVMBuildFMul(ctx
->builder
, val
[chan
],
5559 LLVMConstReal(ctx
->ac
.f32
, 65535), "");
5560 val
[chan
] = LLVMBuildFAdd(ctx
->builder
, val
[chan
],
5561 LLVMConstReal(ctx
->ac
.f32
, 0.5), "");
5562 val
[chan
] = LLVMBuildFPToUI(ctx
->builder
, val
[chan
],
5567 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5568 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5571 case V_028714_SPI_SHADER_SNORM16_ABGR
:
5572 for (unsigned chan
= 0; chan
< 4; chan
++) {
5573 val
[chan
] = emit_float_saturate(&ctx
->ac
, values
[chan
], -1, 1);
5574 val
[chan
] = LLVMBuildFMul(ctx
->builder
, val
[chan
],
5575 LLVMConstReal(ctx
->ac
.f32
, 32767), "");
5577 /* If positive, add 0.5, else add -0.5. */
5578 val
[chan
] = LLVMBuildFAdd(ctx
->builder
, val
[chan
],
5579 LLVMBuildSelect(ctx
->builder
,
5580 LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
,
5581 val
[chan
], ctx
->ac
.f32_0
, ""),
5582 LLVMConstReal(ctx
->ac
.f32
, 0.5),
5583 LLVMConstReal(ctx
->ac
.f32
, -0.5), ""), "");
5584 val
[chan
] = LLVMBuildFPToSI(ctx
->builder
, val
[chan
], ctx
->ac
.i32
, "");
5588 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5589 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5592 case V_028714_SPI_SHADER_UINT16_ABGR
: {
5593 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5594 is_int8
? 255 : is_int10
? 1023 : 65535, 0);
5595 LLVMValueRef max_alpha
= !is_int10
? max_rgb
: LLVMConstInt(ctx
->ac
.i32
, 3, 0);
5597 for (unsigned chan
= 0; chan
< 4; chan
++) {
5598 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
5599 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntULT
, val
[chan
], chan
== 3 ? max_alpha
: max_rgb
);
5603 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5604 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5608 case V_028714_SPI_SHADER_SINT16_ABGR
: {
5609 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5610 is_int8
? 127 : is_int10
? 511 : 32767, 0);
5611 LLVMValueRef min_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5612 is_int8
? -128 : is_int10
? -512 : -32768, 0);
5613 LLVMValueRef max_alpha
= !is_int10
? max_rgb
: ctx
->ac
.i32_1
;
5614 LLVMValueRef min_alpha
= !is_int10
? min_rgb
: LLVMConstInt(ctx
->ac
.i32
, -2, 0);
5617 for (unsigned chan
= 0; chan
< 4; chan
++) {
5618 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
5619 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, val
[chan
], chan
== 3 ? max_alpha
: max_rgb
);
5620 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, val
[chan
], chan
== 3 ? min_alpha
: min_rgb
);
5624 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5625 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5630 case V_028714_SPI_SHADER_32_ABGR
:
5631 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5635 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5637 for (unsigned i
= 0; i
< 4; ++i
)
5638 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
5642 handle_vs_outputs_post(struct nir_to_llvm_context
*ctx
,
5643 bool export_prim_id
,
5644 struct ac_vs_output_info
*outinfo
)
5646 uint32_t param_count
= 0;
5648 unsigned pos_idx
, num_pos_exports
= 0;
5649 struct ac_export_args args
, pos_args
[4] = {};
5650 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
5653 if (ctx
->options
->key
.has_multiview_view_index
) {
5654 LLVMValueRef
* tmp_out
= &ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5656 for(unsigned i
= 0; i
< 4; ++i
)
5657 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
5658 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5661 LLVMBuildStore(ctx
->builder
, ac_to_float(&ctx
->ac
, ctx
->view_index
), *tmp_out
);
5662 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
5665 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
5666 sizeof(outinfo
->vs_output_param_offset
));
5668 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
5669 LLVMValueRef slots
[8];
5672 if (outinfo
->cull_dist_mask
)
5673 outinfo
->cull_dist_mask
<<= ctx
->num_output_clips
;
5675 i
= VARYING_SLOT_CLIP_DIST0
;
5676 for (j
= 0; j
< ctx
->num_output_clips
+ ctx
->num_output_culls
; j
++)
5677 slots
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5678 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
5680 for (i
= ctx
->num_output_clips
+ ctx
->num_output_culls
; i
< 8; i
++)
5681 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
5683 if (ctx
->num_output_clips
+ ctx
->num_output_culls
> 4) {
5684 target
= V_008DFC_SQ_EXP_POS
+ 3;
5685 si_llvm_init_export_args(ctx
, &slots
[4], target
, &args
);
5686 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5687 &args
, sizeof(args
));
5690 target
= V_008DFC_SQ_EXP_POS
+ 2;
5691 si_llvm_init_export_args(ctx
, &slots
[0], target
, &args
);
5692 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5693 &args
, sizeof(args
));
5697 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
5698 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
5699 for (unsigned j
= 0; j
< 4; j
++)
5700 pos_values
[j
] = LLVMBuildLoad(ctx
->builder
,
5701 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_POS
, j
)], "");
5703 si_llvm_init_export_args(ctx
, pos_values
, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
5705 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
5706 outinfo
->writes_pointsize
= true;
5707 psize_value
= LLVMBuildLoad(ctx
->builder
,
5708 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ
, 0)], "");
5711 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
5712 outinfo
->writes_layer
= true;
5713 layer_value
= LLVMBuildLoad(ctx
->builder
,
5714 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)], "");
5717 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
5718 outinfo
->writes_viewport_index
= true;
5719 viewport_index_value
= LLVMBuildLoad(ctx
->builder
,
5720 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT
, 0)], "");
5723 if (outinfo
->writes_pointsize
||
5724 outinfo
->writes_layer
||
5725 outinfo
->writes_viewport_index
) {
5726 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
5727 (outinfo
->writes_layer
== true ? 4 : 0));
5728 pos_args
[1].valid_mask
= 0;
5729 pos_args
[1].done
= 0;
5730 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
5731 pos_args
[1].compr
= 0;
5732 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
5733 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
5734 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
5735 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
5737 if (outinfo
->writes_pointsize
== true)
5738 pos_args
[1].out
[0] = psize_value
;
5739 if (outinfo
->writes_layer
== true)
5740 pos_args
[1].out
[2] = layer_value
;
5741 if (outinfo
->writes_viewport_index
== true) {
5742 if (ctx
->options
->chip_class
>= GFX9
) {
5743 /* GFX9 has the layer in out.z[10:0] and the viewport
5744 * index in out.z[19:16].
5746 LLVMValueRef v
= viewport_index_value
;
5747 v
= ac_to_integer(&ctx
->ac
, v
);
5748 v
= LLVMBuildShl(ctx
->builder
, v
,
5749 LLVMConstInt(ctx
->ac
.i32
, 16, false),
5751 v
= LLVMBuildOr(ctx
->builder
, v
,
5752 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
5754 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
5755 pos_args
[1].enabled_channels
|= 1 << 2;
5757 pos_args
[1].out
[3] = viewport_index_value
;
5758 pos_args
[1].enabled_channels
|= 1 << 3;
5762 for (i
= 0; i
< 4; i
++) {
5763 if (pos_args
[i
].out
[0])
5768 for (i
= 0; i
< 4; i
++) {
5769 if (!pos_args
[i
].out
[0])
5772 /* Specify the target we are exporting */
5773 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
5774 if (pos_idx
== num_pos_exports
)
5775 pos_args
[i
].done
= 1;
5776 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
5779 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5780 LLVMValueRef values
[4];
5781 if (!(ctx
->output_mask
& (1ull << i
)))
5784 for (unsigned j
= 0; j
< 4; j
++)
5785 values
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5786 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
5788 if (i
== VARYING_SLOT_LAYER
) {
5789 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5790 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = param_count
;
5792 } else if (i
== VARYING_SLOT_PRIMITIVE_ID
) {
5793 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5794 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
5796 } else if (i
>= VARYING_SLOT_VAR0
) {
5797 outinfo
->export_mask
|= 1u << (i
- VARYING_SLOT_VAR0
);
5798 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5799 outinfo
->vs_output_param_offset
[i
] = param_count
;
5804 si_llvm_init_export_args(ctx
, values
, target
, &args
);
5806 if (target
>= V_008DFC_SQ_EXP_POS
&&
5807 target
<= (V_008DFC_SQ_EXP_POS
+ 3)) {
5808 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5809 &args
, sizeof(args
));
5811 ac_build_export(&ctx
->ac
, &args
);
5815 if (export_prim_id
) {
5816 LLVMValueRef values
[4];
5817 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5818 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
5821 values
[0] = ctx
->vs_prim_id
;
5822 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
5823 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5824 for (unsigned j
= 1; j
< 4; j
++)
5825 values
[j
] = ctx
->ac
.f32_0
;
5826 si_llvm_init_export_args(ctx
, values
, target
, &args
);
5827 ac_build_export(&ctx
->ac
, &args
);
5828 outinfo
->export_prim_id
= true;
5831 outinfo
->pos_exports
= num_pos_exports
;
5832 outinfo
->param_exports
= param_count
;
5836 handle_es_outputs_post(struct nir_to_llvm_context
*ctx
,
5837 struct ac_es_output_info
*outinfo
)
5840 uint64_t max_output_written
= 0;
5841 LLVMValueRef lds_base
= NULL
;
5843 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5847 if (!(ctx
->output_mask
& (1ull << i
)))
5850 if (i
== VARYING_SLOT_CLIP_DIST0
)
5851 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
5853 param_index
= shader_io_get_unique_index(i
);
5855 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
5858 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
5860 if (ctx
->ac
.chip_class
>= GFX9
) {
5861 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
5862 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
5863 LLVMValueRef wave_idx
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
5864 LLVMConstInt(ctx
->ac
.i32
, 24, false),
5865 LLVMConstInt(ctx
->ac
.i32
, 4, false), false);
5866 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
5867 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
5868 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
5869 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
5870 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
5873 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5874 LLVMValueRef dw_addr
;
5875 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
5879 if (!(ctx
->output_mask
& (1ull << i
)))
5882 if (i
== VARYING_SLOT_CLIP_DIST0
)
5883 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
5885 param_index
= shader_io_get_unique_index(i
);
5888 dw_addr
= LLVMBuildAdd(ctx
->builder
, lds_base
,
5889 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
5892 for (j
= 0; j
< length
; j
++) {
5893 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], "");
5894 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->ac
.i32
, "");
5896 if (ctx
->ac
.chip_class
>= GFX9
) {
5897 ac_lds_store(&ctx
->ac
, dw_addr
,
5898 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
5899 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->ac
.i32_1
, "");
5901 ac_build_buffer_store_dword(&ctx
->ac
,
5904 NULL
, ctx
->es2gs_offset
,
5905 (4 * param_index
+ j
) * 4,
5913 handle_ls_outputs_post(struct nir_to_llvm_context
*ctx
)
5915 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
5916 LLVMValueRef vertex_dw_stride
= unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 13, 8);
5917 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->builder
, vertex_id
,
5918 vertex_dw_stride
, "");
5920 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5921 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
5924 if (!(ctx
->output_mask
& (1ull << i
)))
5927 if (i
== VARYING_SLOT_CLIP_DIST0
)
5928 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
5929 int param
= shader_io_get_unique_index(i
);
5930 mark_tess_output(ctx
, false, param
);
5932 mark_tess_output(ctx
, false, param
+ 1);
5933 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->builder
, base_dw_addr
,
5934 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
5936 for (unsigned j
= 0; j
< length
; j
++) {
5937 ac_lds_store(&ctx
->ac
, dw_addr
,
5938 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
5939 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->ac
.i32_1
, "");
5944 struct ac_build_if_state
5946 struct nir_to_llvm_context
*ctx
;
5947 LLVMValueRef condition
;
5948 LLVMBasicBlockRef entry_block
;
5949 LLVMBasicBlockRef true_block
;
5950 LLVMBasicBlockRef false_block
;
5951 LLVMBasicBlockRef merge_block
;
5954 static LLVMBasicBlockRef
5955 ac_build_insert_new_block(struct nir_to_llvm_context
*ctx
, const char *name
)
5957 LLVMBasicBlockRef current_block
;
5958 LLVMBasicBlockRef next_block
;
5959 LLVMBasicBlockRef new_block
;
5961 /* get current basic block */
5962 current_block
= LLVMGetInsertBlock(ctx
->builder
);
5964 /* chqeck if there's another block after this one */
5965 next_block
= LLVMGetNextBasicBlock(current_block
);
5967 /* insert the new block before the next block */
5968 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
5971 /* append new block after current block */
5972 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
5973 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
5979 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
5980 struct nir_to_llvm_context
*ctx
,
5981 LLVMValueRef condition
)
5983 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->builder
);
5985 memset(ifthen
, 0, sizeof *ifthen
);
5987 ifthen
->condition
= condition
;
5988 ifthen
->entry_block
= block
;
5990 /* create endif/merge basic block for the phi functions */
5991 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
5993 /* create/insert true_block before merge_block */
5994 ifthen
->true_block
=
5995 LLVMInsertBasicBlockInContext(ctx
->context
,
5996 ifthen
->merge_block
,
5999 /* successive code goes into the true block */
6000 LLVMPositionBuilderAtEnd(ctx
->builder
, ifthen
->true_block
);
6004 * End a conditional.
6007 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
6009 LLVMBuilderRef builder
= ifthen
->ctx
->builder
;
6011 /* Insert branch to the merge block from current block */
6012 LLVMBuildBr(builder
, ifthen
->merge_block
);
6015 * Now patch in the various branch instructions.
6018 /* Insert the conditional branch instruction at the end of entry_block */
6019 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
6020 if (ifthen
->false_block
) {
6021 /* we have an else clause */
6022 LLVMBuildCondBr(builder
, ifthen
->condition
,
6023 ifthen
->true_block
, ifthen
->false_block
);
6026 /* no else clause */
6027 LLVMBuildCondBr(builder
, ifthen
->condition
,
6028 ifthen
->true_block
, ifthen
->merge_block
);
6031 /* Resume building code at end of the ifthen->merge_block */
6032 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
6036 write_tess_factors(struct nir_to_llvm_context
*ctx
)
6038 unsigned stride
, outer_comps
, inner_comps
;
6039 struct ac_build_if_state if_ctx
, inner_if_ctx
;
6040 LLVMValueRef invocation_id
= unpack_param(&ctx
->ac
, ctx
->tcs_rel_ids
, 8, 5);
6041 LLVMValueRef rel_patch_id
= unpack_param(&ctx
->ac
, ctx
->tcs_rel_ids
, 0, 8);
6042 unsigned tess_inner_index
, tess_outer_index
;
6043 LLVMValueRef lds_base
, lds_inner
, lds_outer
, byteoffset
, buffer
;
6044 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
6048 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
6068 ac_nir_build_if(&if_ctx
, ctx
,
6069 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
6070 invocation_id
, ctx
->ac
.i32_0
, ""));
6072 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6073 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6075 mark_tess_output(ctx
, true, tess_inner_index
);
6076 mark_tess_output(ctx
, true, tess_outer_index
);
6077 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
6078 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6079 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
6080 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6081 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
6083 for (i
= 0; i
< 4; i
++) {
6084 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6085 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6089 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
6090 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
6091 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
6093 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
6095 for (i
= 0; i
< outer_comps
; i
++) {
6097 ac_lds_load(&ctx
->ac
, lds_outer
);
6098 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
6101 for (i
= 0; i
< inner_comps
; i
++) {
6102 inner
[i
] = out
[outer_comps
+i
] =
6103 ac_lds_load(&ctx
->ac
, lds_inner
);
6104 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_inner
,
6109 /* Convert the outputs to vectors for stores. */
6110 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
6114 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
6117 buffer
= ctx
->hs_ring_tess_factor
;
6118 tf_base
= ctx
->tess_factor_offset
;
6119 byteoffset
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
6120 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
6121 unsigned tf_offset
= 0;
6123 if (ctx
->options
->chip_class
<= VI
) {
6124 ac_nir_build_if(&inner_if_ctx
, ctx
,
6125 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
6126 rel_patch_id
, ctx
->ac
.i32_0
, ""));
6128 /* Store the dynamic HS control word. */
6129 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
6130 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
6131 1, ctx
->ac
.i32_0
, tf_base
,
6132 0, 1, 0, true, false);
6135 ac_nir_build_endif(&inner_if_ctx
);
6138 /* Store the tessellation factors. */
6139 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
6140 MIN2(stride
, 4), byteoffset
, tf_base
,
6141 tf_offset
, 1, 0, true, false);
6143 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
6144 stride
- 4, byteoffset
, tf_base
,
6145 16 + tf_offset
, 1, 0, true, false);
6147 //store to offchip for TES to read - only if TES reads them
6148 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
6149 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
6150 LLVMValueRef tf_inner_offset
;
6151 unsigned param_outer
, param_inner
;
6153 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6154 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6155 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
6157 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
6158 util_next_power_of_two(outer_comps
));
6160 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
6161 outer_comps
, tf_outer_offset
,
6162 ctx
->oc_lds
, 0, 1, 0, true, false);
6164 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6165 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6166 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
6168 inner_vec
= inner_comps
== 1 ? inner
[0] :
6169 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
6170 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
6171 inner_comps
, tf_inner_offset
,
6172 ctx
->oc_lds
, 0, 1, 0, true, false);
6175 ac_nir_build_endif(&if_ctx
);
6179 handle_tcs_outputs_post(struct nir_to_llvm_context
*ctx
)
6181 write_tess_factors(ctx
);
6185 si_export_mrt_color(struct nir_to_llvm_context
*ctx
,
6186 LLVMValueRef
*color
, unsigned param
, bool is_last
,
6187 struct ac_export_args
*args
)
6190 si_llvm_init_export_args(ctx
, color
, param
,
6194 args
->valid_mask
= 1; /* whether the EXEC mask is valid */
6195 args
->done
= 1; /* DONE bit */
6196 } else if (!args
->enabled_channels
)
6197 return false; /* unnecessary NULL export */
6203 radv_export_mrt_z(struct nir_to_llvm_context
*ctx
,
6204 LLVMValueRef depth
, LLVMValueRef stencil
,
6205 LLVMValueRef samplemask
)
6207 struct ac_export_args args
;
6209 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
6211 ac_build_export(&ctx
->ac
, &args
);
6215 handle_fs_outputs_post(struct nir_to_llvm_context
*ctx
)
6218 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
6219 struct ac_export_args color_args
[8];
6221 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6222 LLVMValueRef values
[4];
6224 if (!(ctx
->output_mask
& (1ull << i
)))
6227 if (i
== FRAG_RESULT_DEPTH
) {
6228 ctx
->shader_info
->fs
.writes_z
= true;
6229 depth
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6230 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6231 } else if (i
== FRAG_RESULT_STENCIL
) {
6232 ctx
->shader_info
->fs
.writes_stencil
= true;
6233 stencil
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6234 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6235 } else if (i
== FRAG_RESULT_SAMPLE_MASK
) {
6236 ctx
->shader_info
->fs
.writes_sample_mask
= true;
6237 samplemask
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6238 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6241 for (unsigned j
= 0; j
< 4; j
++)
6242 values
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6243 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
6245 if (!ctx
->shader_info
->fs
.writes_z
&& !ctx
->shader_info
->fs
.writes_stencil
&& !ctx
->shader_info
->fs
.writes_sample_mask
)
6246 last
= ctx
->output_mask
<= ((1ull << (i
+ 1)) - 1);
6248 bool ret
= si_export_mrt_color(ctx
, values
, V_008DFC_SQ_EXP_MRT
+ (i
- FRAG_RESULT_DATA0
), last
, &color_args
[index
]);
6254 for (unsigned i
= 0; i
< index
; i
++)
6255 ac_build_export(&ctx
->ac
, &color_args
[i
]);
6256 if (depth
|| stencil
|| samplemask
)
6257 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
6259 si_export_mrt_color(ctx
, NULL
, V_008DFC_SQ_EXP_NULL
, true, &color_args
[0]);
6260 ac_build_export(&ctx
->ac
, &color_args
[0]);
6263 ctx
->shader_info
->fs
.output_mask
= index
? ((1ull << index
) - 1) : 0;
6267 emit_gs_epilogue(struct nir_to_llvm_context
*ctx
)
6269 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
6273 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
6274 LLVMValueRef
*addrs
)
6276 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
6278 switch (ctx
->stage
) {
6279 case MESA_SHADER_VERTEX
:
6280 if (ctx
->options
->key
.vs
.as_ls
)
6281 handle_ls_outputs_post(ctx
);
6282 else if (ctx
->options
->key
.vs
.as_es
)
6283 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
6285 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
6286 &ctx
->shader_info
->vs
.outinfo
);
6288 case MESA_SHADER_FRAGMENT
:
6289 handle_fs_outputs_post(ctx
);
6291 case MESA_SHADER_GEOMETRY
:
6292 emit_gs_epilogue(ctx
);
6294 case MESA_SHADER_TESS_CTRL
:
6295 handle_tcs_outputs_post(ctx
);
6297 case MESA_SHADER_TESS_EVAL
:
6298 if (ctx
->options
->key
.tes
.as_es
)
6299 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
6301 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
6302 &ctx
->shader_info
->tes
.outinfo
);
6309 static void ac_llvm_finalize_module(struct nir_to_llvm_context
* ctx
)
6311 LLVMPassManagerRef passmgr
;
6312 /* Create the pass manager */
6313 passmgr
= LLVMCreateFunctionPassManagerForModule(
6316 /* This pass should eliminate all the load and store instructions */
6317 LLVMAddPromoteMemoryToRegisterPass(passmgr
);
6319 /* Add some optimization passes */
6320 LLVMAddScalarReplAggregatesPass(passmgr
);
6321 LLVMAddLICMPass(passmgr
);
6322 LLVMAddAggressiveDCEPass(passmgr
);
6323 LLVMAddCFGSimplificationPass(passmgr
);
6324 LLVMAddInstructionCombiningPass(passmgr
);
6327 LLVMInitializeFunctionPassManager(passmgr
);
6328 LLVMRunFunctionPassManager(passmgr
, ctx
->main_function
);
6329 LLVMFinalizeFunctionPassManager(passmgr
);
6331 LLVMDisposeBuilder(ctx
->builder
);
6332 LLVMDisposePassManager(passmgr
);
6336 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context
*ctx
)
6338 struct ac_vs_output_info
*outinfo
;
6340 switch (ctx
->stage
) {
6341 case MESA_SHADER_FRAGMENT
:
6342 case MESA_SHADER_COMPUTE
:
6343 case MESA_SHADER_TESS_CTRL
:
6344 case MESA_SHADER_GEOMETRY
:
6346 case MESA_SHADER_VERTEX
:
6347 if (ctx
->options
->key
.vs
.as_ls
||
6348 ctx
->options
->key
.vs
.as_es
)
6350 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
6352 case MESA_SHADER_TESS_EVAL
:
6353 if (ctx
->options
->key
.vs
.as_es
)
6355 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
6358 unreachable("Unhandled shader type");
6361 ac_optimize_vs_outputs(&ctx
->ac
,
6363 outinfo
->vs_output_param_offset
,
6365 &outinfo
->param_exports
);
6369 ac_setup_rings(struct nir_to_llvm_context
*ctx
)
6371 if ((ctx
->stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_es
) ||
6372 (ctx
->stage
== MESA_SHADER_TESS_EVAL
&& ctx
->options
->key
.tes
.as_es
)) {
6373 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_VS
, false));
6376 if (ctx
->is_gs_copy_shader
) {
6377 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_VS
, false));
6379 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
6381 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_GS
, false));
6382 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_GS
, false));
6384 ctx
->gsvs_ring
= LLVMBuildBitCast(ctx
->builder
, ctx
->gsvs_ring
, ctx
->ac
.v4i32
, "");
6386 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->gsvs_num_entries
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
6387 tmp
= LLVMBuildExtractElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->ac
.i32_1
, "");
6388 tmp
= LLVMBuildOr(ctx
->builder
, tmp
, ctx
->gsvs_ring_stride
, "");
6389 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, tmp
, ctx
->ac
.i32_1
, "");
6392 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
6393 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
6394 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
6395 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
6400 ac_nir_get_max_workgroup_size(enum chip_class chip_class
,
6401 const struct nir_shader
*nir
)
6403 switch (nir
->info
.stage
) {
6404 case MESA_SHADER_TESS_CTRL
:
6405 return chip_class
>= CIK
? 128 : 64;
6406 case MESA_SHADER_GEOMETRY
:
6407 return chip_class
>= GFX9
? 128 : 64;
6408 case MESA_SHADER_COMPUTE
:
6414 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
6415 nir
->info
.cs
.local_size
[1] *
6416 nir
->info
.cs
.local_size
[2];
6417 return max_workgroup_size
;
6420 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6421 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context
*ctx
)
6423 LLVMValueRef count
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6424 LLVMConstInt(ctx
->ac
.i32
, 8, false),
6425 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6426 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
6428 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
6429 ctx
->vs_prim_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.vertex_id
, ctx
->vs_prim_id
, "");
6430 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->tcs_rel_ids
, ctx
->rel_auto_id
, "");
6431 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->tcs_patch_id
, ctx
->abi
.vertex_id
, "");
6434 static void prepare_gs_input_vgprs(struct nir_to_llvm_context
*ctx
)
6436 for(int i
= 5; i
>= 0; --i
) {
6437 ctx
->gs_vtx_offset
[i
] = ac_build_bfe(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
6438 LLVMConstInt(ctx
->ac
.i32
, (i
& 1) * 16, false),
6439 LLVMConstInt(ctx
->ac
.i32
, 16, false), false);
6442 ctx
->gs_wave_id
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6443 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6444 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6447 void ac_nir_translate(struct ac_llvm_context
*ac
, struct ac_shader_abi
*abi
,
6448 struct nir_shader
*nir
, struct nir_to_llvm_context
*nctx
)
6450 struct ac_nir_context ctx
= {};
6451 struct nir_function
*func
;
6460 ctx
.stage
= nir
->info
.stage
;
6462 ctx
.main_function
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6464 nir_foreach_variable(variable
, &nir
->outputs
)
6465 handle_shader_output_decl(&ctx
, nir
, variable
);
6467 ctx
.defs
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6468 _mesa_key_pointer_equal
);
6469 ctx
.phis
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6470 _mesa_key_pointer_equal
);
6471 ctx
.vars
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6472 _mesa_key_pointer_equal
);
6474 func
= (struct nir_function
*)exec_list_get_head(&nir
->functions
);
6476 setup_locals(&ctx
, func
);
6478 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
6479 setup_shared(&ctx
, nir
);
6481 visit_cf_list(&ctx
, &func
->impl
->body
);
6482 phi_post_pass(&ctx
);
6484 ctx
.abi
->emit_outputs(ctx
.abi
, RADEON_LLVM_MAX_OUTPUTS
,
6488 ralloc_free(ctx
.defs
);
6489 ralloc_free(ctx
.phis
);
6490 ralloc_free(ctx
.vars
);
6497 LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm
,
6498 struct nir_shader
*const *shaders
,
6500 struct ac_shader_variant_info
*shader_info
,
6501 const struct ac_nir_compiler_options
*options
)
6503 struct nir_to_llvm_context ctx
= {0};
6505 ctx
.options
= options
;
6506 ctx
.shader_info
= shader_info
;
6507 ctx
.context
= LLVMContextCreate();
6508 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
6510 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
6512 ctx
.ac
.module
= ctx
.module
;
6513 LLVMSetTarget(ctx
.module
, options
->supports_spill
? "amdgcn-mesa-mesa3d" : "amdgcn--");
6515 LLVMTargetDataRef data_layout
= LLVMCreateTargetDataLayout(tm
);
6516 char *data_layout_str
= LLVMCopyStringRepOfTargetData(data_layout
);
6517 LLVMSetDataLayout(ctx
.module
, data_layout_str
);
6518 LLVMDisposeTargetData(data_layout
);
6519 LLVMDisposeMessage(data_layout_str
);
6521 ctx
.builder
= LLVMCreateBuilderInContext(ctx
.context
);
6522 ctx
.ac
.builder
= ctx
.builder
;
6524 memset(shader_info
, 0, sizeof(*shader_info
));
6526 for(int i
= 0; i
< shader_count
; ++i
)
6527 ac_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
6529 for (i
= 0; i
< AC_UD_MAX_SETS
; i
++)
6530 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
6531 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
6532 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
6534 ctx
.max_workgroup_size
= 0;
6535 for (int i
= 0; i
< shader_count
; ++i
) {
6536 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
6537 ac_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
6541 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
6542 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
6544 ctx
.abi
.inputs
= &ctx
.inputs
[0];
6545 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
6546 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
6547 ctx
.abi
.load_ubo
= radv_load_ubo
;
6548 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
6549 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
6550 ctx
.abi
.clamp_shadow_reference
= false;
6552 if (shader_count
>= 2)
6553 ac_init_exec_full_mask(&ctx
.ac
);
6555 if (ctx
.ac
.chip_class
== GFX9
&&
6556 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
6557 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
6559 for(int i
= 0; i
< shader_count
; ++i
) {
6560 ctx
.stage
= shaders
[i
]->info
.stage
;
6561 ctx
.output_mask
= 0;
6562 ctx
.tess_outputs_written
= 0;
6563 ctx
.num_output_clips
= shaders
[i
]->info
.clip_distance_array_size
;
6564 ctx
.num_output_culls
= shaders
[i
]->info
.cull_distance_array_size
;
6566 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6567 ctx
.gs_next_vertex
= ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "gs_next_vertex");
6568 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
6569 ctx
.abi
.load_inputs
= load_gs_input
;
6570 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6571 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
6572 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
6573 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
6574 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
6575 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
6576 if (shader_info
->info
.vs
.needs_instance_id
) {
6577 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6578 MAX2(3, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6580 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
6581 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
6587 ac_setup_rings(&ctx
);
6589 LLVMBasicBlockRef merge_block
;
6590 if (shader_count
>= 2) {
6591 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6592 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6593 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6595 LLVMValueRef count
= ac_build_bfe(&ctx
.ac
, ctx
.merged_wave_info
,
6596 LLVMConstInt(ctx
.ac
.i32
, 8 * i
, false),
6597 LLVMConstInt(ctx
.ac
.i32
, 8, false), false);
6598 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
6599 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
6600 thread_id
, count
, "");
6601 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
6603 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
6606 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
6607 handle_fs_inputs(&ctx
, shaders
[i
]);
6608 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
6609 handle_vs_inputs(&ctx
, shaders
[i
]);
6610 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
6611 prepare_gs_input_vgprs(&ctx
);
6613 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
6614 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
6616 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
], &ctx
);
6618 if (shader_count
>= 2) {
6619 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
6620 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
6623 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6624 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
6625 shaders
[i
]->info
.cull_distance_array_size
> 4;
6626 shader_info
->gs
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
6627 shader_info
->gs
.max_gsvs_emit_size
= shader_info
->gs
.gsvs_vertex_size
*
6628 shaders
[i
]->info
.gs
.vertices_out
;
6629 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6630 shader_info
->tcs
.outputs_written
= ctx
.tess_outputs_written
;
6631 shader_info
->tcs
.patch_outputs_written
= ctx
.tess_patch_outputs_written
;
6632 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&& ctx
.options
->key
.vs
.as_ls
) {
6633 shader_info
->vs
.outputs_written
= ctx
.tess_outputs_written
;
6637 LLVMBuildRetVoid(ctx
.builder
);
6639 ac_llvm_finalize_module(&ctx
);
6641 if (shader_count
== 1)
6642 ac_nir_eliminate_const_vs_outputs(&ctx
);
6647 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
6649 unsigned *retval
= (unsigned *)context
;
6650 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
6651 char *description
= LLVMGetDiagInfoDescription(di
);
6653 if (severity
== LLVMDSError
) {
6655 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
6659 LLVMDisposeMessage(description
);
6662 static unsigned ac_llvm_compile(LLVMModuleRef M
,
6663 struct ac_shader_binary
*binary
,
6664 LLVMTargetMachineRef tm
)
6666 unsigned retval
= 0;
6668 LLVMContextRef llvm_ctx
;
6669 LLVMMemoryBufferRef out_buffer
;
6670 unsigned buffer_size
;
6671 const char *buffer_data
;
6674 /* Setup Diagnostic Handler*/
6675 llvm_ctx
= LLVMGetModuleContext(M
);
6677 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
6681 mem_err
= LLVMTargetMachineEmitToMemoryBuffer(tm
, M
, LLVMObjectFile
,
6684 /* Process Errors/Warnings */
6686 fprintf(stderr
, "%s: %s", __FUNCTION__
, err
);
6692 /* Extract Shader Code*/
6693 buffer_size
= LLVMGetBufferSize(out_buffer
);
6694 buffer_data
= LLVMGetBufferStart(out_buffer
);
6696 ac_elf_read(buffer_data
, buffer_size
, binary
);
6699 LLVMDisposeMemoryBuffer(out_buffer
);
6705 static void ac_compile_llvm_module(LLVMTargetMachineRef tm
,
6706 LLVMModuleRef llvm_module
,
6707 struct ac_shader_binary
*binary
,
6708 struct ac_shader_config
*config
,
6709 struct ac_shader_variant_info
*shader_info
,
6710 gl_shader_stage stage
,
6711 bool dump_shader
, bool supports_spill
)
6714 ac_dump_module(llvm_module
);
6716 memset(binary
, 0, sizeof(*binary
));
6717 int v
= ac_llvm_compile(llvm_module
, binary
, tm
);
6719 fprintf(stderr
, "compile failed\n");
6723 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
6725 ac_shader_binary_read_config(binary
, config
, 0, supports_spill
);
6727 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
6728 LLVMDisposeModule(llvm_module
);
6729 LLVMContextDispose(ctx
);
6731 if (stage
== MESA_SHADER_FRAGMENT
) {
6732 shader_info
->num_input_vgprs
= 0;
6733 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
6734 shader_info
->num_input_vgprs
+= 2;
6735 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
6736 shader_info
->num_input_vgprs
+= 2;
6737 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
6738 shader_info
->num_input_vgprs
+= 2;
6739 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
6740 shader_info
->num_input_vgprs
+= 3;
6741 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
6742 shader_info
->num_input_vgprs
+= 2;
6743 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
6744 shader_info
->num_input_vgprs
+= 2;
6745 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
6746 shader_info
->num_input_vgprs
+= 2;
6747 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
6748 shader_info
->num_input_vgprs
+= 1;
6749 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
6750 shader_info
->num_input_vgprs
+= 1;
6751 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
6752 shader_info
->num_input_vgprs
+= 1;
6753 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
6754 shader_info
->num_input_vgprs
+= 1;
6755 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
6756 shader_info
->num_input_vgprs
+= 1;
6757 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
6758 shader_info
->num_input_vgprs
+= 1;
6759 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
6760 shader_info
->num_input_vgprs
+= 1;
6761 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
6762 shader_info
->num_input_vgprs
+= 1;
6763 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
6764 shader_info
->num_input_vgprs
+= 1;
6766 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
6768 /* +3 for scratch wave offset and VCC */
6769 config
->num_sgprs
= MAX2(config
->num_sgprs
,
6770 shader_info
->num_input_sgprs
+ 3);
6774 ac_fill_shader_info(struct ac_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct ac_nir_compiler_options
*options
)
6776 switch (nir
->info
.stage
) {
6777 case MESA_SHADER_COMPUTE
:
6778 for (int i
= 0; i
< 3; ++i
)
6779 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
6781 case MESA_SHADER_FRAGMENT
:
6782 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
6784 case MESA_SHADER_GEOMETRY
:
6785 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
6786 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
6787 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
6788 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
6790 case MESA_SHADER_TESS_EVAL
:
6791 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
6792 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
6793 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
6794 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
6795 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
6797 case MESA_SHADER_TESS_CTRL
:
6798 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
6800 case MESA_SHADER_VERTEX
:
6801 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
6802 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
6803 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6804 if (options
->key
.vs
.as_ls
)
6805 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
6812 void ac_compile_nir_shader(LLVMTargetMachineRef tm
,
6813 struct ac_shader_binary
*binary
,
6814 struct ac_shader_config
*config
,
6815 struct ac_shader_variant_info
*shader_info
,
6816 struct nir_shader
*const *nir
,
6818 const struct ac_nir_compiler_options
*options
,
6822 LLVMModuleRef llvm_module
= ac_translate_nir_to_llvm(tm
, nir
, nir_count
, shader_info
,
6825 ac_compile_llvm_module(tm
, llvm_module
, binary
, config
, shader_info
, nir
[0]->info
.stage
, dump_shader
, options
->supports_spill
);
6826 for (int i
= 0; i
< nir_count
; ++i
)
6827 ac_fill_shader_info(shader_info
, nir
[i
], options
);
6831 ac_gs_copy_shader_emit(struct nir_to_llvm_context
*ctx
)
6833 LLVMValueRef args
[9];
6834 args
[0] = ctx
->gsvs_ring
;
6835 args
[1] = LLVMBuildMul(ctx
->builder
, ctx
->abi
.vertex_id
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
6836 args
[3] = ctx
->ac
.i32_0
;
6837 args
[4] = ctx
->ac
.i32_1
; /* OFFEN */
6838 args
[5] = ctx
->ac
.i32_0
; /* IDXEN */
6839 args
[6] = ctx
->ac
.i32_1
; /* GLC */
6840 args
[7] = ctx
->ac
.i32_1
; /* SLC */
6841 args
[8] = ctx
->ac
.i32_0
; /* TFE */
6845 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6849 if (!(ctx
->output_mask
& (1ull << i
)))
6852 if (i
== VARYING_SLOT_CLIP_DIST0
) {
6853 /* unpack clip and cull from a single set of slots */
6854 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6859 for (unsigned j
= 0; j
< length
; j
++) {
6861 args
[2] = LLVMConstInt(ctx
->ac
.i32
,
6863 ctx
->gs_max_out_vertices
* 16 * 4, false);
6865 value
= ac_build_intrinsic(&ctx
->ac
,
6866 "llvm.SI.buffer.load.dword.i32.i32",
6867 ctx
->ac
.i32
, args
, 9,
6868 AC_FUNC_ATTR_READONLY
|
6869 AC_FUNC_ATTR_LEGACY
);
6871 LLVMBuildStore(ctx
->builder
,
6872 ac_to_float(&ctx
->ac
, value
), ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)]);
6876 handle_vs_outputs_post(ctx
, false, &ctx
->shader_info
->vs
.outinfo
);
6879 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm
,
6880 struct nir_shader
*geom_shader
,
6881 struct ac_shader_binary
*binary
,
6882 struct ac_shader_config
*config
,
6883 struct ac_shader_variant_info
*shader_info
,
6884 const struct ac_nir_compiler_options
*options
,
6887 struct nir_to_llvm_context ctx
= {0};
6888 ctx
.context
= LLVMContextCreate();
6889 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
6890 ctx
.options
= options
;
6891 ctx
.shader_info
= shader_info
;
6893 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
6895 ctx
.ac
.module
= ctx
.module
;
6897 ctx
.is_gs_copy_shader
= true;
6898 LLVMSetTarget(ctx
.module
, "amdgcn--");
6900 ctx
.builder
= LLVMCreateBuilderInContext(ctx
.context
);
6901 ctx
.ac
.builder
= ctx
.builder
;
6902 ctx
.stage
= MESA_SHADER_VERTEX
;
6904 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
6906 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
6907 ac_setup_rings(&ctx
);
6909 ctx
.num_output_clips
= geom_shader
->info
.clip_distance_array_size
;
6910 ctx
.num_output_culls
= geom_shader
->info
.cull_distance_array_size
;
6912 struct ac_nir_context nir_ctx
= {};
6913 nir_ctx
.ac
= ctx
.ac
;
6914 nir_ctx
.abi
= &ctx
.abi
;
6916 nir_ctx
.nctx
= &ctx
;
6919 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
6920 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
6921 handle_shader_output_decl(&nir_ctx
, geom_shader
, variable
);
6924 ac_gs_copy_shader_emit(&ctx
);
6928 LLVMBuildRetVoid(ctx
.builder
);
6930 ac_llvm_finalize_module(&ctx
);
6932 ac_compile_llvm_module(tm
, ctx
.module
, binary
, config
, shader_info
,
6934 dump_shader
, options
->supports_spill
);