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amd/common: rename set_userdata_location_shader() to set_loc_shader()
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tcs_patch_id;
115 LLVMValueRef tcs_rel_ids;
116 LLVMValueRef tes_rel_patch_id;
117 LLVMValueRef tes_patch_id;
118 LLVMValueRef tes_u;
119 LLVMValueRef tes_v;
120
121 LLVMValueRef gsvs_ring_stride;
122 LLVMValueRef gsvs_num_entries;
123 LLVMValueRef gs2vs_offset;
124 LLVMValueRef gs_wave_id;
125 LLVMValueRef gs_vtx_offset[6];
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 gl_shader_stage stage;
138
139 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
140
141 uint64_t input_mask;
142 uint64_t output_mask;
143 uint8_t num_output_clips;
144 uint8_t num_output_culls;
145
146 bool is_gs_copy_shader;
147 LLVMValueRef gs_next_vertex;
148 unsigned gs_max_out_vertices;
149
150 unsigned tes_primitive_mode;
151 uint64_t tess_outputs_written;
152 uint64_t tess_patch_outputs_written;
153
154 uint32_t tcs_patch_outputs_read;
155 uint64_t tcs_outputs_read;
156 };
157
158 static inline struct nir_to_llvm_context *
159 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
160 {
161 struct nir_to_llvm_context *ctx = NULL;
162 return container_of(abi, ctx, abi);
163 }
164
165 static LLVMTypeRef
166 nir2llvmtype(struct ac_nir_context *ctx,
167 const struct glsl_type *type)
168 {
169 switch (glsl_get_base_type(glsl_without_array(type))) {
170 case GLSL_TYPE_UINT:
171 case GLSL_TYPE_INT:
172 return ctx->ac.i32;
173 case GLSL_TYPE_UINT64:
174 case GLSL_TYPE_INT64:
175 return ctx->ac.i64;
176 case GLSL_TYPE_DOUBLE:
177 return ctx->ac.f64;
178 case GLSL_TYPE_FLOAT:
179 return ctx->ac.f32;
180 default:
181 assert(!"Unsupported type in nir2llvmtype()");
182 break;
183 }
184 return 0;
185 }
186
187 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
188 const nir_deref_var *deref,
189 enum ac_descriptor_type desc_type,
190 const nir_tex_instr *instr,
191 bool image, bool write);
192
193 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
194 {
195 return (index * 4) + chan;
196 }
197
198 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
199 {
200 /* handle patch indices separate */
201 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
202 return 0;
203 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
204 return 1;
205 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
206 return 2 + (slot - VARYING_SLOT_PATCH0);
207
208 if (slot == VARYING_SLOT_POS)
209 return 0;
210 if (slot == VARYING_SLOT_PSIZ)
211 return 1;
212 if (slot == VARYING_SLOT_CLIP_DIST0)
213 return 2;
214 /* 3 is reserved for clip dist as well */
215 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
216 return 4 + (slot - VARYING_SLOT_VAR0);
217 unreachable("illegal slot in get unique index\n");
218 }
219
220 static void set_llvm_calling_convention(LLVMValueRef func,
221 gl_shader_stage stage)
222 {
223 enum radeon_llvm_calling_convention calling_conv;
224
225 switch (stage) {
226 case MESA_SHADER_VERTEX:
227 case MESA_SHADER_TESS_EVAL:
228 calling_conv = RADEON_LLVM_AMDGPU_VS;
229 break;
230 case MESA_SHADER_GEOMETRY:
231 calling_conv = RADEON_LLVM_AMDGPU_GS;
232 break;
233 case MESA_SHADER_TESS_CTRL:
234 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
235 break;
236 case MESA_SHADER_FRAGMENT:
237 calling_conv = RADEON_LLVM_AMDGPU_PS;
238 break;
239 case MESA_SHADER_COMPUTE:
240 calling_conv = RADEON_LLVM_AMDGPU_CS;
241 break;
242 default:
243 unreachable("Unhandle shader type");
244 }
245
246 LLVMSetFunctionCallConv(func, calling_conv);
247 }
248
249 #define MAX_ARGS 23
250 struct arg_info {
251 LLVMTypeRef types[MAX_ARGS];
252 LLVMValueRef *assign[MAX_ARGS];
253 unsigned array_params_mask;
254 uint8_t count;
255 uint8_t sgpr_count;
256 uint8_t num_sgprs_used;
257 uint8_t num_vgprs_used;
258 };
259
260 enum ac_arg_regfile {
261 ARG_SGPR,
262 ARG_VGPR,
263 };
264
265 static void
266 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
267 LLVMValueRef *param_ptr)
268 {
269 assert(info->count < MAX_ARGS);
270
271 info->assign[info->count] = param_ptr;
272 info->types[info->count] = type;
273 info->count++;
274
275 if (regfile == ARG_SGPR) {
276 info->num_sgprs_used += ac_get_type_size(type) / 4;
277 info->sgpr_count++;
278 } else {
279 assert(regfile == ARG_VGPR);
280 info->num_vgprs_used += ac_get_type_size(type) / 4;
281 }
282 }
283
284 static inline void
285 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
286 {
287 info->array_params_mask |= (1 << info->count);
288 add_arg(info, ARG_SGPR, type, param_ptr);
289 }
290
291 static void assign_arguments(LLVMValueRef main_function,
292 struct arg_info *info)
293 {
294 unsigned i;
295 for (i = 0; i < info->count; i++) {
296 if (info->assign[i])
297 *info->assign[i] = LLVMGetParam(main_function, i);
298 }
299 }
300
301 static LLVMValueRef
302 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
303 LLVMBuilderRef builder, LLVMTypeRef *return_types,
304 unsigned num_return_elems,
305 struct arg_info *args,
306 unsigned max_workgroup_size,
307 bool unsafe_math)
308 {
309 LLVMTypeRef main_function_type, ret_type;
310 LLVMBasicBlockRef main_function_body;
311
312 if (num_return_elems)
313 ret_type = LLVMStructTypeInContext(ctx, return_types,
314 num_return_elems, true);
315 else
316 ret_type = LLVMVoidTypeInContext(ctx);
317
318 /* Setup the function */
319 main_function_type =
320 LLVMFunctionType(ret_type, args->types, args->count, 0);
321 LLVMValueRef main_function =
322 LLVMAddFunction(module, "main", main_function_type);
323 main_function_body =
324 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
325 LLVMPositionBuilderAtEnd(builder, main_function_body);
326
327 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
328 for (unsigned i = 0; i < args->sgpr_count; ++i) {
329 if (args->array_params_mask & (1 << i)) {
330 LLVMValueRef P = LLVMGetParam(main_function, i);
331 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
332 ac_add_attr_dereferenceable(P, UINT64_MAX);
333 }
334 else {
335 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
336 }
337 }
338
339 if (max_workgroup_size) {
340 ac_llvm_add_target_dep_function_attr(main_function,
341 "amdgpu-max-work-group-size",
342 max_workgroup_size);
343 }
344 if (unsafe_math) {
345 /* These were copied from some LLVM test. */
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "less-precise-fpmad",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-infs-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "no-nans-fp-math",
354 "true");
355 LLVMAddTargetDependentFunctionAttr(main_function,
356 "unsafe-fp-math",
357 "true");
358 }
359 return main_function;
360 }
361
362 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
363 {
364 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
365 CONST_ADDR_SPACE);
366 }
367
368 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
369 {
370 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
371 type = LLVMGetElementType(type);
372
373 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
374 return LLVMGetIntTypeWidth(type);
375
376 if (type == ctx->f16)
377 return 16;
378 if (type == ctx->f32)
379 return 32;
380 if (type == ctx->f64)
381 return 64;
382
383 unreachable("Unhandled type kind in get_elem_bits");
384 }
385
386 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
387 LLVMValueRef param, unsigned rshift,
388 unsigned bitwidth)
389 {
390 LLVMValueRef value = param;
391 if (rshift)
392 value = LLVMBuildLShr(ctx->builder, value,
393 LLVMConstInt(ctx->i32, rshift, false), "");
394
395 if (rshift + bitwidth < 32) {
396 unsigned mask = (1 << bitwidth) - 1;
397 value = LLVMBuildAnd(ctx->builder, value,
398 LLVMConstInt(ctx->i32, mask, false), "");
399 }
400 return value;
401 }
402
403 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
404 {
405 switch (ctx->stage) {
406 case MESA_SHADER_TESS_CTRL:
407 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
408 case MESA_SHADER_TESS_EVAL:
409 return ctx->tes_rel_patch_id;
410 break;
411 default:
412 unreachable("Illegal stage");
413 }
414 }
415
416 /* Tessellation shaders pass outputs to the next shader using LDS.
417 *
418 * LS outputs = TCS inputs
419 * TCS outputs = TES inputs
420 *
421 * The LDS layout is:
422 * - TCS inputs for patch 0
423 * - TCS inputs for patch 1
424 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
425 * - ...
426 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
427 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
428 * - TCS outputs for patch 1
429 * - Per-patch TCS outputs for patch 1
430 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
431 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
432 * - ...
433 *
434 * All three shaders VS(LS), TCS, TES share the same LDS space.
435 */
436 static LLVMValueRef
437 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
438 {
439 if (ctx->stage == MESA_SHADER_VERTEX)
440 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
441 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
442 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
443 else {
444 assert(0);
445 return NULL;
446 }
447 }
448
449 static LLVMValueRef
450 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
451 {
452 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
453 }
454
455 static LLVMValueRef
456 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
457 {
458 return LLVMBuildMul(ctx->builder,
459 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
460 LLVMConstInt(ctx->ac.i32, 4, false), "");
461 }
462
463 static LLVMValueRef
464 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
465 {
466 return LLVMBuildMul(ctx->builder,
467 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
468 LLVMConstInt(ctx->ac.i32, 4, false), "");
469 }
470
471 static LLVMValueRef
472 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
473 {
474 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
475 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
476
477 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
478 }
479
480 static LLVMValueRef
481 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
482 {
483 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
484 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
485 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
486
487 return LLVMBuildAdd(ctx->builder, patch0_offset,
488 LLVMBuildMul(ctx->builder, patch_stride,
489 rel_patch_id, ""),
490 "");
491 }
492
493 static LLVMValueRef
494 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
495 {
496 LLVMValueRef patch0_patch_data_offset =
497 get_tcs_out_patch0_patch_data_offset(ctx);
498 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
499 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
500
501 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
502 LLVMBuildMul(ctx->builder, patch_stride,
503 rel_patch_id, ""),
504 "");
505 }
506
507 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
508 {
509 ud_info->sgpr_idx = *sgpr_idx;
510 ud_info->num_sgprs = num_sgprs;
511 ud_info->indirect = false;
512 ud_info->indirect_offset = 0;
513 *sgpr_idx += num_sgprs;
514 }
515
516 static void
517 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
518 uint8_t num_sgprs)
519 {
520 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
521 }
522
523 static void
524 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
525 uint32_t indirect_offset)
526 {
527 struct ac_userdata_info *ud_info =
528 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
529 assert(ud_info);
530
531 ud_info->sgpr_idx = *sgpr_idx;
532 ud_info->num_sgprs = 2;
533 ud_info->indirect = indirect_offset > 0;
534 ud_info->indirect_offset = indirect_offset;
535 }
536
537 struct user_sgpr_info {
538 bool need_ring_offsets;
539 uint8_t sgpr_count;
540 bool indirect_all_descriptor_sets;
541 };
542
543 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
544 struct user_sgpr_info *user_sgpr_info)
545 {
546 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
547
548 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
549 if (ctx->stage == MESA_SHADER_GEOMETRY ||
550 ctx->stage == MESA_SHADER_VERTEX ||
551 ctx->stage == MESA_SHADER_TESS_CTRL ||
552 ctx->stage == MESA_SHADER_TESS_EVAL ||
553 ctx->is_gs_copy_shader)
554 user_sgpr_info->need_ring_offsets = true;
555
556 if (ctx->stage == MESA_SHADER_FRAGMENT &&
557 ctx->shader_info->info.ps.needs_sample_positions)
558 user_sgpr_info->need_ring_offsets = true;
559
560 /* 2 user sgprs will nearly always be allocated for scratch/rings */
561 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
562 user_sgpr_info->sgpr_count += 2;
563 }
564
565 switch (ctx->stage) {
566 case MESA_SHADER_COMPUTE:
567 if (ctx->shader_info->info.cs.uses_grid_size)
568 user_sgpr_info->sgpr_count += 3;
569 break;
570 case MESA_SHADER_FRAGMENT:
571 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
572 break;
573 case MESA_SHADER_VERTEX:
574 if (!ctx->is_gs_copy_shader) {
575 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
576 if (ctx->shader_info->info.vs.needs_draw_id) {
577 user_sgpr_info->sgpr_count += 3;
578 } else {
579 user_sgpr_info->sgpr_count += 2;
580 }
581 }
582 if (ctx->options->key.vs.as_ls)
583 user_sgpr_info->sgpr_count++;
584 break;
585 case MESA_SHADER_TESS_CTRL:
586 user_sgpr_info->sgpr_count += 4;
587 break;
588 case MESA_SHADER_TESS_EVAL:
589 user_sgpr_info->sgpr_count += 1;
590 break;
591 case MESA_SHADER_GEOMETRY:
592 user_sgpr_info->sgpr_count += 2;
593 break;
594 default:
595 break;
596 }
597
598 if (ctx->shader_info->info.needs_push_constants)
599 user_sgpr_info->sgpr_count += 2;
600
601 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
602 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
603 user_sgpr_info->sgpr_count += 2;
604 user_sgpr_info->indirect_all_descriptor_sets = true;
605 } else {
606 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
607 }
608 }
609
610 static void
611 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
612 gl_shader_stage stage,
613 bool has_previous_stage,
614 gl_shader_stage previous_stage,
615 const struct user_sgpr_info *user_sgpr_info,
616 struct arg_info *args,
617 LLVMValueRef *desc_sets)
618 {
619 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
620 unsigned num_sets = ctx->options->layout ?
621 ctx->options->layout->num_sets : 0;
622 unsigned stage_mask = 1 << stage;
623
624 if (has_previous_stage)
625 stage_mask |= 1 << previous_stage;
626
627 /* 1 for each descriptor set */
628 if (!user_sgpr_info->indirect_all_descriptor_sets) {
629 for (unsigned i = 0; i < num_sets; ++i) {
630 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
631 add_array_arg(args, type,
632 &ctx->descriptor_sets[i]);
633 }
634 }
635 } else {
636 add_array_arg(args, const_array(type, 32), desc_sets);
637 }
638
639 if (ctx->shader_info->info.needs_push_constants) {
640 /* 1 for push constants and dynamic descriptors */
641 add_array_arg(args, type, &ctx->push_constants);
642 }
643 }
644
645 static void
646 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
647 gl_shader_stage stage,
648 bool has_previous_stage,
649 gl_shader_stage previous_stage,
650 struct arg_info *args)
651 {
652 if (!ctx->is_gs_copy_shader &&
653 (stage == MESA_SHADER_VERTEX ||
654 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
655 if (ctx->shader_info->info.vs.has_vertex_buffers) {
656 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
657 &ctx->vertex_buffers);
658 }
659 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
660 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
661 if (ctx->shader_info->info.vs.needs_draw_id) {
662 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
663 }
664 }
665 }
666
667 static void
668 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
669 {
670 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
671 if (!ctx->is_gs_copy_shader) {
672 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
673 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
674 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
675 }
676 }
677
678 static void
679 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
680 {
681 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
682 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
683 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
684 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_patch_id);
685 }
686
687 static void
688 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
689 bool has_previous_stage, gl_shader_stage previous_stage,
690 const struct user_sgpr_info *user_sgpr_info,
691 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
692 {
693 unsigned num_sets = ctx->options->layout ?
694 ctx->options->layout->num_sets : 0;
695 unsigned stage_mask = 1 << stage;
696
697 if (has_previous_stage)
698 stage_mask |= 1 << previous_stage;
699
700 if (!user_sgpr_info->indirect_all_descriptor_sets) {
701 for (unsigned i = 0; i < num_sets; ++i) {
702 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
703 set_loc_desc(ctx, i, user_sgpr_idx, 0);
704 } else
705 ctx->descriptor_sets[i] = NULL;
706 }
707 } else {
708 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
709 user_sgpr_idx, 2);
710
711 for (unsigned i = 0; i < num_sets; ++i) {
712 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
713 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
714 ctx->descriptor_sets[i] =
715 ac_build_load_to_sgpr(&ctx->ac,
716 desc_sets,
717 LLVMConstInt(ctx->ac.i32, i, false));
718
719 } else
720 ctx->descriptor_sets[i] = NULL;
721 }
722 ctx->shader_info->need_indirect_descriptor_sets = true;
723 }
724
725 if (ctx->shader_info->info.needs_push_constants) {
726 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
727 }
728 }
729
730 static void
731 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
732 gl_shader_stage stage, bool has_previous_stage,
733 gl_shader_stage previous_stage,
734 uint8_t *user_sgpr_idx)
735 {
736 if (!ctx->is_gs_copy_shader &&
737 (stage == MESA_SHADER_VERTEX ||
738 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
739 if (ctx->shader_info->info.vs.has_vertex_buffers) {
740 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
741 user_sgpr_idx, 2);
742 }
743
744 unsigned vs_num = 2;
745 if (ctx->shader_info->info.vs.needs_draw_id)
746 vs_num++;
747
748 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
749 user_sgpr_idx, vs_num);
750 }
751 }
752
753 static void create_function(struct nir_to_llvm_context *ctx,
754 gl_shader_stage stage,
755 bool has_previous_stage,
756 gl_shader_stage previous_stage)
757 {
758 uint8_t user_sgpr_idx;
759 struct user_sgpr_info user_sgpr_info;
760 struct arg_info args = {};
761 LLVMValueRef desc_sets;
762
763 allocate_user_sgprs(ctx, &user_sgpr_info);
764
765 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
766 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
767 &ctx->ring_offsets);
768 }
769
770 switch (stage) {
771 case MESA_SHADER_COMPUTE:
772 declare_global_input_sgprs(ctx, stage, has_previous_stage,
773 previous_stage, &user_sgpr_info,
774 &args, &desc_sets);
775
776 if (ctx->shader_info->info.cs.uses_grid_size) {
777 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
778 &ctx->num_work_groups);
779 }
780
781 for (int i = 0; i < 3; i++) {
782 ctx->workgroup_ids[i] = NULL;
783 if (ctx->shader_info->info.cs.uses_block_id[i]) {
784 add_arg(&args, ARG_SGPR, ctx->ac.i32,
785 &ctx->workgroup_ids[i]);
786 }
787 }
788
789 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
790 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
791 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
792 &ctx->local_invocation_ids);
793 break;
794 case MESA_SHADER_VERTEX:
795 declare_global_input_sgprs(ctx, stage, has_previous_stage,
796 previous_stage, &user_sgpr_info,
797 &args, &desc_sets);
798 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
799 previous_stage, &args);
800
801 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
802 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
803 if (ctx->options->key.vs.as_es)
804 add_arg(&args, ARG_SGPR, ctx->ac.i32,
805 &ctx->es2gs_offset);
806 else if (ctx->options->key.vs.as_ls)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32,
808 &ctx->ls_out_layout);
809
810 declare_vs_input_vgprs(ctx, &args);
811 break;
812 case MESA_SHADER_TESS_CTRL:
813 if (has_previous_stage) {
814 // First 6 system regs
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->merged_wave_info);
818 add_arg(&args, ARG_SGPR, ctx->ac.i32,
819 &ctx->tess_factor_offset);
820
821 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
822 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
823 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
824
825 declare_global_input_sgprs(ctx, stage,
826 has_previous_stage,
827 previous_stage,
828 &user_sgpr_info, &args,
829 &desc_sets);
830 declare_vs_specific_input_sgprs(ctx, stage,
831 has_previous_stage,
832 previous_stage, &args);
833
834 add_arg(&args, ARG_SGPR, ctx->ac.i32,
835 &ctx->ls_out_layout);
836
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->tcs_offchip_layout);
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->tcs_out_offsets);
841 add_arg(&args, ARG_SGPR, ctx->ac.i32,
842 &ctx->tcs_out_layout);
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->tcs_in_layout);
845 if (ctx->shader_info->info.needs_multiview_view_index)
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->view_index);
848
849 add_arg(&args, ARG_VGPR, ctx->ac.i32,
850 &ctx->tcs_patch_id);
851 add_arg(&args, ARG_VGPR, ctx->ac.i32,
852 &ctx->tcs_rel_ids);
853
854 declare_vs_input_vgprs(ctx, &args);
855 } else {
856 declare_global_input_sgprs(ctx, stage,
857 has_previous_stage,
858 previous_stage,
859 &user_sgpr_info, &args,
860 &desc_sets);
861
862 add_arg(&args, ARG_SGPR, ctx->ac.i32,
863 &ctx->tcs_offchip_layout);
864 add_arg(&args, ARG_SGPR, ctx->ac.i32,
865 &ctx->tcs_out_offsets);
866 add_arg(&args, ARG_SGPR, ctx->ac.i32,
867 &ctx->tcs_out_layout);
868 add_arg(&args, ARG_SGPR, ctx->ac.i32,
869 &ctx->tcs_in_layout);
870 if (ctx->shader_info->info.needs_multiview_view_index)
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->view_index);
873
874 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tess_factor_offset);
877 add_arg(&args, ARG_VGPR, ctx->ac.i32,
878 &ctx->tcs_patch_id);
879 add_arg(&args, ARG_VGPR, ctx->ac.i32,
880 &ctx->tcs_rel_ids);
881 }
882 break;
883 case MESA_SHADER_TESS_EVAL:
884 declare_global_input_sgprs(ctx, stage, has_previous_stage,
885 previous_stage, &user_sgpr_info,
886 &args, &desc_sets);
887
888 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
889 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
890 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
891
892 if (ctx->options->key.tes.as_es) {
893 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
895 add_arg(&args, ARG_SGPR, ctx->ac.i32,
896 &ctx->es2gs_offset);
897 } else {
898 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
900 }
901 declare_tes_input_vgprs(ctx, &args);
902 break;
903 case MESA_SHADER_GEOMETRY:
904 if (has_previous_stage) {
905 // First 6 system regs
906 add_arg(&args, ARG_SGPR, ctx->ac.i32,
907 &ctx->gs2vs_offset);
908 add_arg(&args, ARG_SGPR, ctx->ac.i32,
909 &ctx->merged_wave_info);
910 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
911
912 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
915
916 declare_global_input_sgprs(ctx, stage,
917 has_previous_stage,
918 previous_stage,
919 &user_sgpr_info, &args,
920 &desc_sets);
921
922 if (previous_stage == MESA_SHADER_TESS_EVAL) {
923 add_arg(&args, ARG_SGPR, ctx->ac.i32,
924 &ctx->tcs_offchip_layout);
925 } else {
926 declare_vs_specific_input_sgprs(ctx, stage,
927 has_previous_stage,
928 previous_stage,
929 &args);
930 }
931
932 add_arg(&args, ARG_SGPR, ctx->ac.i32,
933 &ctx->gsvs_ring_stride);
934 add_arg(&args, ARG_SGPR, ctx->ac.i32,
935 &ctx->gsvs_num_entries);
936 if (ctx->shader_info->info.needs_multiview_view_index)
937 add_arg(&args, ARG_SGPR, ctx->ac.i32,
938 &ctx->view_index);
939
940 add_arg(&args, ARG_VGPR, ctx->ac.i32,
941 &ctx->gs_vtx_offset[0]);
942 add_arg(&args, ARG_VGPR, ctx->ac.i32,
943 &ctx->gs_vtx_offset[2]);
944 add_arg(&args, ARG_VGPR, ctx->ac.i32,
945 &ctx->abi.gs_prim_id);
946 add_arg(&args, ARG_VGPR, ctx->ac.i32,
947 &ctx->abi.gs_invocation_id);
948 add_arg(&args, ARG_VGPR, ctx->ac.i32,
949 &ctx->gs_vtx_offset[4]);
950
951 if (previous_stage == MESA_SHADER_VERTEX) {
952 declare_vs_input_vgprs(ctx, &args);
953 } else {
954 declare_tes_input_vgprs(ctx, &args);
955 }
956 } else {
957 declare_global_input_sgprs(ctx, stage,
958 has_previous_stage,
959 previous_stage,
960 &user_sgpr_info, &args,
961 &desc_sets);
962
963 add_arg(&args, ARG_SGPR, ctx->ac.i32,
964 &ctx->gsvs_ring_stride);
965 add_arg(&args, ARG_SGPR, ctx->ac.i32,
966 &ctx->gsvs_num_entries);
967 if (ctx->shader_info->info.needs_multiview_view_index)
968 add_arg(&args, ARG_SGPR, ctx->ac.i32,
969 &ctx->view_index);
970
971 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
972 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
973 add_arg(&args, ARG_VGPR, ctx->ac.i32,
974 &ctx->gs_vtx_offset[0]);
975 add_arg(&args, ARG_VGPR, ctx->ac.i32,
976 &ctx->gs_vtx_offset[1]);
977 add_arg(&args, ARG_VGPR, ctx->ac.i32,
978 &ctx->abi.gs_prim_id);
979 add_arg(&args, ARG_VGPR, ctx->ac.i32,
980 &ctx->gs_vtx_offset[2]);
981 add_arg(&args, ARG_VGPR, ctx->ac.i32,
982 &ctx->gs_vtx_offset[3]);
983 add_arg(&args, ARG_VGPR, ctx->ac.i32,
984 &ctx->gs_vtx_offset[4]);
985 add_arg(&args, ARG_VGPR, ctx->ac.i32,
986 &ctx->gs_vtx_offset[5]);
987 add_arg(&args, ARG_VGPR, ctx->ac.i32,
988 &ctx->abi.gs_invocation_id);
989 }
990 break;
991 case MESA_SHADER_FRAGMENT:
992 declare_global_input_sgprs(ctx, stage, has_previous_stage,
993 previous_stage, &user_sgpr_info,
994 &args, &desc_sets);
995
996 if (ctx->shader_info->info.ps.needs_sample_positions)
997 add_arg(&args, ARG_SGPR, ctx->ac.i32,
998 &ctx->sample_pos_offset);
999
1000 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1001 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1002 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1003 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1005 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1008 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1009 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1010 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1014 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1017 break;
1018 default:
1019 unreachable("Shader stage not implemented");
1020 }
1021
1022 ctx->main_function = create_llvm_function(
1023 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1024 ctx->max_workgroup_size,
1025 ctx->options->unsafe_math);
1026 set_llvm_calling_convention(ctx->main_function, stage);
1027
1028
1029 ctx->shader_info->num_input_vgprs = 0;
1030 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1031
1032 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1033
1034 if (ctx->stage != MESA_SHADER_FRAGMENT)
1035 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1036
1037 assign_arguments(ctx->main_function, &args);
1038
1039 user_sgpr_idx = 0;
1040
1041 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1042 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1043 &user_sgpr_idx, 2);
1044 if (ctx->options->supports_spill) {
1045 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1046 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1047 NULL, 0, AC_FUNC_ATTR_READNONE);
1048 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1049 const_array(ctx->ac.v4i32, 16), "");
1050 }
1051 }
1052
1053 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1054 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1055 if (has_previous_stage)
1056 user_sgpr_idx = 0;
1057
1058 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1059 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1060
1061 switch (stage) {
1062 case MESA_SHADER_COMPUTE:
1063 if (ctx->shader_info->info.cs.uses_grid_size) {
1064 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1065 &user_sgpr_idx, 3);
1066 }
1067 break;
1068 case MESA_SHADER_VERTEX:
1069 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1070 previous_stage, &user_sgpr_idx);
1071 if (ctx->view_index)
1072 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1073 if (ctx->options->key.vs.as_ls) {
1074 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1075 &user_sgpr_idx, 1);
1076 }
1077 if (ctx->options->key.vs.as_ls)
1078 ac_declare_lds_as_pointer(&ctx->ac);
1079 break;
1080 case MESA_SHADER_TESS_CTRL:
1081 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1082 previous_stage, &user_sgpr_idx);
1083 if (has_previous_stage)
1084 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1085 &user_sgpr_idx, 1);
1086 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1087 if (ctx->view_index)
1088 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1089 ac_declare_lds_as_pointer(&ctx->ac);
1090 break;
1091 case MESA_SHADER_TESS_EVAL:
1092 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1093 if (ctx->view_index)
1094 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1095 break;
1096 case MESA_SHADER_GEOMETRY:
1097 if (has_previous_stage) {
1098 if (previous_stage == MESA_SHADER_VERTEX)
1099 set_vs_specific_input_locs(ctx, stage,
1100 has_previous_stage,
1101 previous_stage,
1102 &user_sgpr_idx);
1103 else
1104 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1105 &user_sgpr_idx, 1);
1106 }
1107 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1108 &user_sgpr_idx, 2);
1109 if (ctx->view_index)
1110 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1111 if (has_previous_stage)
1112 ac_declare_lds_as_pointer(&ctx->ac);
1113 break;
1114 case MESA_SHADER_FRAGMENT:
1115 if (ctx->shader_info->info.ps.needs_sample_positions) {
1116 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1117 &user_sgpr_idx, 1);
1118 }
1119 break;
1120 default:
1121 unreachable("Shader stage not implemented");
1122 }
1123
1124 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1125 }
1126
1127 static int get_llvm_num_components(LLVMValueRef value)
1128 {
1129 LLVMTypeRef type = LLVMTypeOf(value);
1130 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1131 ? LLVMGetVectorSize(type)
1132 : 1;
1133 return num_components;
1134 }
1135
1136 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1137 LLVMValueRef value,
1138 int index)
1139 {
1140 int count = get_llvm_num_components(value);
1141
1142 if (count == 1)
1143 return value;
1144
1145 return LLVMBuildExtractElement(ac->builder, value,
1146 LLVMConstInt(ac->i32, index, false), "");
1147 }
1148
1149 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1150 LLVMValueRef value, unsigned count)
1151 {
1152 unsigned num_components = get_llvm_num_components(value);
1153 if (count == num_components)
1154 return value;
1155
1156 LLVMValueRef masks[] = {
1157 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1158 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1159
1160 if (count == 1)
1161 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1162 "");
1163
1164 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1165 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1166 }
1167
1168 static void
1169 build_store_values_extended(struct ac_llvm_context *ac,
1170 LLVMValueRef *values,
1171 unsigned value_count,
1172 unsigned value_stride,
1173 LLVMValueRef vec)
1174 {
1175 LLVMBuilderRef builder = ac->builder;
1176 unsigned i;
1177
1178 for (i = 0; i < value_count; i++) {
1179 LLVMValueRef ptr = values[i * value_stride];
1180 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1181 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1182 LLVMBuildStore(builder, value, ptr);
1183 }
1184 }
1185
1186 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1187 const nir_ssa_def *def)
1188 {
1189 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1190 if (def->num_components > 1) {
1191 type = LLVMVectorType(type, def->num_components);
1192 }
1193 return type;
1194 }
1195
1196 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1197 {
1198 assert(src.is_ssa);
1199 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1200 return (LLVMValueRef)entry->data;
1201 }
1202
1203
1204 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1205 const struct nir_block *b)
1206 {
1207 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1208 return (LLVMBasicBlockRef)entry->data;
1209 }
1210
1211 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1212 nir_alu_src src,
1213 unsigned num_components)
1214 {
1215 LLVMValueRef value = get_src(ctx, src.src);
1216 bool need_swizzle = false;
1217
1218 assert(value);
1219 LLVMTypeRef type = LLVMTypeOf(value);
1220 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1221 ? LLVMGetVectorSize(type)
1222 : 1;
1223
1224 for (unsigned i = 0; i < num_components; ++i) {
1225 assert(src.swizzle[i] < src_components);
1226 if (src.swizzle[i] != i)
1227 need_swizzle = true;
1228 }
1229
1230 if (need_swizzle || num_components != src_components) {
1231 LLVMValueRef masks[] = {
1232 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1233 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1234 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1235 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1236
1237 if (src_components > 1 && num_components == 1) {
1238 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1239 masks[0], "");
1240 } else if (src_components == 1 && num_components > 1) {
1241 LLVMValueRef values[] = {value, value, value, value};
1242 value = ac_build_gather_values(&ctx->ac, values, num_components);
1243 } else {
1244 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1245 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1246 swizzle, "");
1247 }
1248 }
1249 assert(!src.negate);
1250 assert(!src.abs);
1251 return value;
1252 }
1253
1254 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1255 LLVMIntPredicate pred, LLVMValueRef src0,
1256 LLVMValueRef src1)
1257 {
1258 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1259 return LLVMBuildSelect(ctx->builder, result,
1260 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1261 ctx->i32_0, "");
1262 }
1263
1264 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1265 LLVMRealPredicate pred, LLVMValueRef src0,
1266 LLVMValueRef src1)
1267 {
1268 LLVMValueRef result;
1269 src0 = ac_to_float(ctx, src0);
1270 src1 = ac_to_float(ctx, src1);
1271 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1272 return LLVMBuildSelect(ctx->builder, result,
1273 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1274 ctx->i32_0, "");
1275 }
1276
1277 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1278 const char *intrin,
1279 LLVMTypeRef result_type,
1280 LLVMValueRef src0)
1281 {
1282 char name[64];
1283 LLVMValueRef params[] = {
1284 ac_to_float(ctx, src0),
1285 };
1286
1287 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1288 get_elem_bits(ctx, result_type));
1289 assert(length < sizeof(name));
1290 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1291 }
1292
1293 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1294 const char *intrin,
1295 LLVMTypeRef result_type,
1296 LLVMValueRef src0, LLVMValueRef src1)
1297 {
1298 char name[64];
1299 LLVMValueRef params[] = {
1300 ac_to_float(ctx, src0),
1301 ac_to_float(ctx, src1),
1302 };
1303
1304 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1305 get_elem_bits(ctx, result_type));
1306 assert(length < sizeof(name));
1307 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1308 }
1309
1310 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1311 const char *intrin,
1312 LLVMTypeRef result_type,
1313 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1314 {
1315 char name[64];
1316 LLVMValueRef params[] = {
1317 ac_to_float(ctx, src0),
1318 ac_to_float(ctx, src1),
1319 ac_to_float(ctx, src2),
1320 };
1321
1322 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1323 get_elem_bits(ctx, result_type));
1324 assert(length < sizeof(name));
1325 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1326 }
1327
1328 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1329 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1330 {
1331 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1332 ctx->i32_0, "");
1333 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1334 }
1335
1336 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1337 LLVMIntPredicate pred,
1338 LLVMValueRef src0, LLVMValueRef src1)
1339 {
1340 return LLVMBuildSelect(ctx->builder,
1341 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1342 src0,
1343 src1, "");
1344
1345 }
1346 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1347 LLVMValueRef src0)
1348 {
1349 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1350 LLVMBuildNeg(ctx->builder, src0, ""));
1351 }
1352
1353 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1354 LLVMValueRef src0)
1355 {
1356 LLVMValueRef cmp, val;
1357
1358 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1359 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1360 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1361 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1362 return val;
1363 }
1364
1365 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1366 LLVMValueRef src0)
1367 {
1368 LLVMValueRef cmp, val;
1369
1370 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1371 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1372 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1373 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1374 return val;
1375 }
1376
1377 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1378 LLVMValueRef src0)
1379 {
1380 const char *intr = "llvm.floor.f32";
1381 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1382 LLVMValueRef params[] = {
1383 fsrc0,
1384 };
1385 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1386 ctx->f32, params, 1,
1387 AC_FUNC_ATTR_READNONE);
1388 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1389 }
1390
1391 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1392 const char *intrin,
1393 LLVMValueRef src0, LLVMValueRef src1)
1394 {
1395 LLVMTypeRef ret_type;
1396 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1397 LLVMValueRef res;
1398 LLVMValueRef params[] = { src0, src1 };
1399 ret_type = LLVMStructTypeInContext(ctx->context, types,
1400 2, true);
1401
1402 res = ac_build_intrinsic(ctx, intrin, ret_type,
1403 params, 2, AC_FUNC_ATTR_READNONE);
1404
1405 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1406 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1407 return res;
1408 }
1409
1410 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1411 LLVMValueRef src0)
1412 {
1413 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1414 }
1415
1416 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1417 LLVMValueRef src0)
1418 {
1419 src0 = ac_to_float(ctx, src0);
1420 return LLVMBuildSExt(ctx->builder,
1421 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1422 ctx->i32, "");
1423 }
1424
1425 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1426 LLVMValueRef src0)
1427 {
1428 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1429 }
1430
1431 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1432 LLVMValueRef src0)
1433 {
1434 return LLVMBuildSExt(ctx->builder,
1435 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1436 ctx->i32, "");
1437 }
1438
1439 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1440 LLVMValueRef src0)
1441 {
1442 LLVMValueRef result;
1443 LLVMValueRef cond = NULL;
1444
1445 src0 = ac_to_float(&ctx->ac, src0);
1446 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1447
1448 if (ctx->options->chip_class >= VI) {
1449 LLVMValueRef args[2];
1450 /* Check if the result is a denormal - and flush to 0 if so. */
1451 args[0] = result;
1452 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1453 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1454 }
1455
1456 /* need to convert back up to f32 */
1457 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1458
1459 if (ctx->options->chip_class >= VI)
1460 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1461 else {
1462 /* for SI/CIK */
1463 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1464 * so compare the result and flush to 0 if it's smaller.
1465 */
1466 LLVMValueRef temp, cond2;
1467 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1468 ctx->ac.f32, result);
1469 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1470 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1471 temp, "");
1472 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1473 temp, ctx->ac.f32_0, "");
1474 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1475 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1476 }
1477 return result;
1478 }
1479
1480 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1481 LLVMValueRef src0, LLVMValueRef src1)
1482 {
1483 LLVMValueRef dst64, result;
1484 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1485 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1486
1487 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1488 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1489 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1490 return result;
1491 }
1492
1493 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1494 LLVMValueRef src0, LLVMValueRef src1)
1495 {
1496 LLVMValueRef dst64, result;
1497 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1498 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1499
1500 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1501 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1502 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1503 return result;
1504 }
1505
1506 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1507 bool is_signed,
1508 const LLVMValueRef srcs[3])
1509 {
1510 LLVMValueRef result;
1511 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1512
1513 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1514 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1515 return result;
1516 }
1517
1518 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1519 LLVMValueRef src0, LLVMValueRef src1,
1520 LLVMValueRef src2, LLVMValueRef src3)
1521 {
1522 LLVMValueRef bfi_args[3], result;
1523
1524 bfi_args[0] = LLVMBuildShl(ctx->builder,
1525 LLVMBuildSub(ctx->builder,
1526 LLVMBuildShl(ctx->builder,
1527 ctx->i32_1,
1528 src3, ""),
1529 ctx->i32_1, ""),
1530 src2, "");
1531 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1532 bfi_args[2] = src0;
1533
1534 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1535
1536 /* Calculate:
1537 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1538 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1539 */
1540 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1541 LLVMBuildAnd(ctx->builder, bfi_args[0],
1542 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1543
1544 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1545 return result;
1546 }
1547
1548 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1549 LLVMValueRef src0)
1550 {
1551 LLVMValueRef comp[2];
1552
1553 src0 = ac_to_float(ctx, src0);
1554 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1555 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1556
1557 return ac_build_cvt_pkrtz_f16(ctx, comp);
1558 }
1559
1560 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1561 LLVMValueRef src0)
1562 {
1563 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1564 LLVMValueRef temps[2], result, val;
1565 int i;
1566
1567 for (i = 0; i < 2; i++) {
1568 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1569 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1570 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1571 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1572 }
1573
1574 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1575 ctx->i32_0, "");
1576 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1577 ctx->i32_1, "");
1578 return result;
1579 }
1580
1581 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1582 nir_op op,
1583 LLVMValueRef src0)
1584 {
1585 unsigned mask;
1586 int idx;
1587 LLVMValueRef result;
1588
1589 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1590 mask = AC_TID_MASK_LEFT;
1591 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1592 mask = AC_TID_MASK_TOP;
1593 else
1594 mask = AC_TID_MASK_TOP_LEFT;
1595
1596 /* for DDX we want to next X pixel, DDY next Y pixel. */
1597 if (op == nir_op_fddx_fine ||
1598 op == nir_op_fddx_coarse ||
1599 op == nir_op_fddx)
1600 idx = 1;
1601 else
1602 idx = 2;
1603
1604 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1605 return result;
1606 }
1607
1608 /*
1609 * this takes an I,J coordinate pair,
1610 * and works out the X and Y derivatives.
1611 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1612 */
1613 static LLVMValueRef emit_ddxy_interp(
1614 struct ac_nir_context *ctx,
1615 LLVMValueRef interp_ij)
1616 {
1617 LLVMValueRef result[4], a;
1618 unsigned i;
1619
1620 for (i = 0; i < 2; i++) {
1621 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1622 LLVMConstInt(ctx->ac.i32, i, false), "");
1623 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1624 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1625 }
1626 return ac_build_gather_values(&ctx->ac, result, 4);
1627 }
1628
1629 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1630 {
1631 LLVMValueRef src[4], result = NULL;
1632 unsigned num_components = instr->dest.dest.ssa.num_components;
1633 unsigned src_components;
1634 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1635
1636 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1637 switch (instr->op) {
1638 case nir_op_vec2:
1639 case nir_op_vec3:
1640 case nir_op_vec4:
1641 src_components = 1;
1642 break;
1643 case nir_op_pack_half_2x16:
1644 src_components = 2;
1645 break;
1646 case nir_op_unpack_half_2x16:
1647 src_components = 1;
1648 break;
1649 default:
1650 src_components = num_components;
1651 break;
1652 }
1653 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1654 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1655
1656 switch (instr->op) {
1657 case nir_op_fmov:
1658 case nir_op_imov:
1659 result = src[0];
1660 break;
1661 case nir_op_fneg:
1662 src[0] = ac_to_float(&ctx->ac, src[0]);
1663 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1664 break;
1665 case nir_op_ineg:
1666 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1667 break;
1668 case nir_op_inot:
1669 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1670 break;
1671 case nir_op_iadd:
1672 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1673 break;
1674 case nir_op_fadd:
1675 src[0] = ac_to_float(&ctx->ac, src[0]);
1676 src[1] = ac_to_float(&ctx->ac, src[1]);
1677 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1678 break;
1679 case nir_op_fsub:
1680 src[0] = ac_to_float(&ctx->ac, src[0]);
1681 src[1] = ac_to_float(&ctx->ac, src[1]);
1682 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1683 break;
1684 case nir_op_isub:
1685 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1686 break;
1687 case nir_op_imul:
1688 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1689 break;
1690 case nir_op_imod:
1691 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1692 break;
1693 case nir_op_umod:
1694 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1695 break;
1696 case nir_op_fmod:
1697 src[0] = ac_to_float(&ctx->ac, src[0]);
1698 src[1] = ac_to_float(&ctx->ac, src[1]);
1699 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1700 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1701 ac_to_float_type(&ctx->ac, def_type), result);
1702 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1703 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1704 break;
1705 case nir_op_frem:
1706 src[0] = ac_to_float(&ctx->ac, src[0]);
1707 src[1] = ac_to_float(&ctx->ac, src[1]);
1708 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1709 break;
1710 case nir_op_irem:
1711 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1712 break;
1713 case nir_op_idiv:
1714 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1715 break;
1716 case nir_op_udiv:
1717 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1718 break;
1719 case nir_op_fmul:
1720 src[0] = ac_to_float(&ctx->ac, src[0]);
1721 src[1] = ac_to_float(&ctx->ac, src[1]);
1722 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1723 break;
1724 case nir_op_fdiv:
1725 src[0] = ac_to_float(&ctx->ac, src[0]);
1726 src[1] = ac_to_float(&ctx->ac, src[1]);
1727 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1728 break;
1729 case nir_op_frcp:
1730 src[0] = ac_to_float(&ctx->ac, src[0]);
1731 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1732 break;
1733 case nir_op_iand:
1734 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1735 break;
1736 case nir_op_ior:
1737 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1738 break;
1739 case nir_op_ixor:
1740 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1741 break;
1742 case nir_op_ishl:
1743 result = LLVMBuildShl(ctx->ac.builder, src[0],
1744 LLVMBuildZExt(ctx->ac.builder, src[1],
1745 LLVMTypeOf(src[0]), ""),
1746 "");
1747 break;
1748 case nir_op_ishr:
1749 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1750 LLVMBuildZExt(ctx->ac.builder, src[1],
1751 LLVMTypeOf(src[0]), ""),
1752 "");
1753 break;
1754 case nir_op_ushr:
1755 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1756 LLVMBuildZExt(ctx->ac.builder, src[1],
1757 LLVMTypeOf(src[0]), ""),
1758 "");
1759 break;
1760 case nir_op_ilt:
1761 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1762 break;
1763 case nir_op_ine:
1764 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1765 break;
1766 case nir_op_ieq:
1767 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1768 break;
1769 case nir_op_ige:
1770 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1771 break;
1772 case nir_op_ult:
1773 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1774 break;
1775 case nir_op_uge:
1776 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1777 break;
1778 case nir_op_feq:
1779 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1780 break;
1781 case nir_op_fne:
1782 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1783 break;
1784 case nir_op_flt:
1785 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1786 break;
1787 case nir_op_fge:
1788 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1789 break;
1790 case nir_op_fabs:
1791 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1792 ac_to_float_type(&ctx->ac, def_type), src[0]);
1793 break;
1794 case nir_op_iabs:
1795 result = emit_iabs(&ctx->ac, src[0]);
1796 break;
1797 case nir_op_imax:
1798 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1799 break;
1800 case nir_op_imin:
1801 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1802 break;
1803 case nir_op_umax:
1804 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1805 break;
1806 case nir_op_umin:
1807 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1808 break;
1809 case nir_op_isign:
1810 result = emit_isign(&ctx->ac, src[0]);
1811 break;
1812 case nir_op_fsign:
1813 src[0] = ac_to_float(&ctx->ac, src[0]);
1814 result = emit_fsign(&ctx->ac, src[0]);
1815 break;
1816 case nir_op_ffloor:
1817 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1818 ac_to_float_type(&ctx->ac, def_type), src[0]);
1819 break;
1820 case nir_op_ftrunc:
1821 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1822 ac_to_float_type(&ctx->ac, def_type), src[0]);
1823 break;
1824 case nir_op_fceil:
1825 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1826 ac_to_float_type(&ctx->ac, def_type), src[0]);
1827 break;
1828 case nir_op_fround_even:
1829 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1830 ac_to_float_type(&ctx->ac, def_type),src[0]);
1831 break;
1832 case nir_op_ffract:
1833 result = emit_ffract(&ctx->ac, src[0]);
1834 break;
1835 case nir_op_fsin:
1836 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1837 ac_to_float_type(&ctx->ac, def_type), src[0]);
1838 break;
1839 case nir_op_fcos:
1840 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1841 ac_to_float_type(&ctx->ac, def_type), src[0]);
1842 break;
1843 case nir_op_fsqrt:
1844 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1845 ac_to_float_type(&ctx->ac, def_type), src[0]);
1846 break;
1847 case nir_op_fexp2:
1848 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1849 ac_to_float_type(&ctx->ac, def_type), src[0]);
1850 break;
1851 case nir_op_flog2:
1852 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1853 ac_to_float_type(&ctx->ac, def_type), src[0]);
1854 break;
1855 case nir_op_frsq:
1856 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1857 ac_to_float_type(&ctx->ac, def_type), src[0]);
1858 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1859 break;
1860 case nir_op_fpow:
1861 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1862 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1863 break;
1864 case nir_op_fmax:
1865 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1866 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1867 if (instr->dest.dest.ssa.bit_size == 32)
1868 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1869 ac_to_float_type(&ctx->ac, def_type),
1870 result);
1871 break;
1872 case nir_op_fmin:
1873 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1874 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1875 if (instr->dest.dest.ssa.bit_size == 32)
1876 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1877 ac_to_float_type(&ctx->ac, def_type),
1878 result);
1879 break;
1880 case nir_op_ffma:
1881 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1882 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1883 break;
1884 case nir_op_ibitfield_extract:
1885 result = emit_bitfield_extract(&ctx->ac, true, src);
1886 break;
1887 case nir_op_ubitfield_extract:
1888 result = emit_bitfield_extract(&ctx->ac, false, src);
1889 break;
1890 case nir_op_bitfield_insert:
1891 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1892 break;
1893 case nir_op_bitfield_reverse:
1894 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1895 break;
1896 case nir_op_bit_count:
1897 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1898 break;
1899 case nir_op_vec2:
1900 case nir_op_vec3:
1901 case nir_op_vec4:
1902 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1903 src[i] = ac_to_integer(&ctx->ac, src[i]);
1904 result = ac_build_gather_values(&ctx->ac, src, num_components);
1905 break;
1906 case nir_op_f2i32:
1907 case nir_op_f2i64:
1908 src[0] = ac_to_float(&ctx->ac, src[0]);
1909 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1910 break;
1911 case nir_op_f2u32:
1912 case nir_op_f2u64:
1913 src[0] = ac_to_float(&ctx->ac, src[0]);
1914 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1915 break;
1916 case nir_op_i2f32:
1917 case nir_op_i2f64:
1918 src[0] = ac_to_integer(&ctx->ac, src[0]);
1919 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1920 break;
1921 case nir_op_u2f32:
1922 case nir_op_u2f64:
1923 src[0] = ac_to_integer(&ctx->ac, src[0]);
1924 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1925 break;
1926 case nir_op_f2f64:
1927 src[0] = ac_to_float(&ctx->ac, src[0]);
1928 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1929 break;
1930 case nir_op_f2f32:
1931 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1932 break;
1933 case nir_op_u2u32:
1934 case nir_op_u2u64:
1935 src[0] = ac_to_integer(&ctx->ac, src[0]);
1936 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1937 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1938 else
1939 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1940 break;
1941 case nir_op_i2i32:
1942 case nir_op_i2i64:
1943 src[0] = ac_to_integer(&ctx->ac, src[0]);
1944 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1945 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1946 else
1947 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1948 break;
1949 case nir_op_bcsel:
1950 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1951 break;
1952 case nir_op_find_lsb:
1953 src[0] = ac_to_integer(&ctx->ac, src[0]);
1954 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1955 break;
1956 case nir_op_ufind_msb:
1957 src[0] = ac_to_integer(&ctx->ac, src[0]);
1958 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1959 break;
1960 case nir_op_ifind_msb:
1961 src[0] = ac_to_integer(&ctx->ac, src[0]);
1962 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1963 break;
1964 case nir_op_uadd_carry:
1965 src[0] = ac_to_integer(&ctx->ac, src[0]);
1966 src[1] = ac_to_integer(&ctx->ac, src[1]);
1967 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1968 break;
1969 case nir_op_usub_borrow:
1970 src[0] = ac_to_integer(&ctx->ac, src[0]);
1971 src[1] = ac_to_integer(&ctx->ac, src[1]);
1972 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1973 break;
1974 case nir_op_b2f:
1975 result = emit_b2f(&ctx->ac, src[0]);
1976 break;
1977 case nir_op_f2b:
1978 result = emit_f2b(&ctx->ac, src[0]);
1979 break;
1980 case nir_op_b2i:
1981 result = emit_b2i(&ctx->ac, src[0]);
1982 break;
1983 case nir_op_i2b:
1984 src[0] = ac_to_integer(&ctx->ac, src[0]);
1985 result = emit_i2b(&ctx->ac, src[0]);
1986 break;
1987 case nir_op_fquantize2f16:
1988 result = emit_f2f16(ctx->nctx, src[0]);
1989 break;
1990 case nir_op_umul_high:
1991 src[0] = ac_to_integer(&ctx->ac, src[0]);
1992 src[1] = ac_to_integer(&ctx->ac, src[1]);
1993 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1994 break;
1995 case nir_op_imul_high:
1996 src[0] = ac_to_integer(&ctx->ac, src[0]);
1997 src[1] = ac_to_integer(&ctx->ac, src[1]);
1998 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1999 break;
2000 case nir_op_pack_half_2x16:
2001 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2002 break;
2003 case nir_op_unpack_half_2x16:
2004 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2005 break;
2006 case nir_op_fddx:
2007 case nir_op_fddy:
2008 case nir_op_fddx_fine:
2009 case nir_op_fddy_fine:
2010 case nir_op_fddx_coarse:
2011 case nir_op_fddy_coarse:
2012 result = emit_ddxy(ctx, instr->op, src[0]);
2013 break;
2014
2015 case nir_op_unpack_64_2x32_split_x: {
2016 assert(instr->src[0].src.ssa->num_components == 1);
2017 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2018 ctx->ac.v2i32,
2019 "");
2020 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2021 ctx->ac.i32_0, "");
2022 break;
2023 }
2024
2025 case nir_op_unpack_64_2x32_split_y: {
2026 assert(instr->src[0].src.ssa->num_components == 1);
2027 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2028 ctx->ac.v2i32,
2029 "");
2030 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2031 ctx->ac.i32_1, "");
2032 break;
2033 }
2034
2035 case nir_op_pack_64_2x32_split: {
2036 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2037 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2038 src[0], ctx->ac.i32_0, "");
2039 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2040 src[1], ctx->ac.i32_1, "");
2041 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2042 break;
2043 }
2044
2045 default:
2046 fprintf(stderr, "Unknown NIR alu instr: ");
2047 nir_print_instr(&instr->instr, stderr);
2048 fprintf(stderr, "\n");
2049 abort();
2050 }
2051
2052 if (result) {
2053 assert(instr->dest.dest.is_ssa);
2054 result = ac_to_integer(&ctx->ac, result);
2055 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2056 result);
2057 }
2058 }
2059
2060 static void visit_load_const(struct ac_nir_context *ctx,
2061 const nir_load_const_instr *instr)
2062 {
2063 LLVMValueRef values[4], value = NULL;
2064 LLVMTypeRef element_type =
2065 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2066
2067 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2068 switch (instr->def.bit_size) {
2069 case 32:
2070 values[i] = LLVMConstInt(element_type,
2071 instr->value.u32[i], false);
2072 break;
2073 case 64:
2074 values[i] = LLVMConstInt(element_type,
2075 instr->value.u64[i], false);
2076 break;
2077 default:
2078 fprintf(stderr,
2079 "unsupported nir load_const bit_size: %d\n",
2080 instr->def.bit_size);
2081 abort();
2082 }
2083 }
2084 if (instr->def.num_components > 1) {
2085 value = LLVMConstVector(values, instr->def.num_components);
2086 } else
2087 value = values[0];
2088
2089 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2090 }
2091
2092 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2093 LLVMTypeRef type)
2094 {
2095 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2096 return LLVMBuildBitCast(ctx->builder, ptr,
2097 LLVMPointerType(type, addr_space), "");
2098 }
2099
2100 static LLVMValueRef
2101 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2102 {
2103 LLVMValueRef size =
2104 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2105 LLVMConstInt(ctx->ac.i32, 2, false), "");
2106
2107 /* VI only */
2108 if (ctx->ac.chip_class == VI && in_elements) {
2109 /* On VI, the descriptor contains the size in bytes,
2110 * but TXQ must return the size in elements.
2111 * The stride is always non-zero for resources using TXQ.
2112 */
2113 LLVMValueRef stride =
2114 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2115 ctx->ac.i32_1, "");
2116 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2117 LLVMConstInt(ctx->ac.i32, 16, false), "");
2118 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2119 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2120
2121 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2122 }
2123 return size;
2124 }
2125
2126 /**
2127 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2128 * intrinsic names).
2129 */
2130 static void build_int_type_name(
2131 LLVMTypeRef type,
2132 char *buf, unsigned bufsize)
2133 {
2134 assert(bufsize >= 6);
2135
2136 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2137 snprintf(buf, bufsize, "v%ui32",
2138 LLVMGetVectorSize(type));
2139 else
2140 strcpy(buf, "i32");
2141 }
2142
2143 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2144 struct ac_image_args *args,
2145 const nir_tex_instr *instr)
2146 {
2147 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2148 LLVMValueRef coord = args->addr;
2149 LLVMValueRef half_texel[2];
2150 LLVMValueRef compare_cube_wa = NULL;
2151 LLVMValueRef result;
2152 int c;
2153 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2154
2155 //TODO Rect
2156 {
2157 struct ac_image_args txq_args = { 0 };
2158
2159 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2160 txq_args.opcode = ac_image_get_resinfo;
2161 txq_args.dmask = 0xf;
2162 txq_args.addr = ctx->i32_0;
2163 txq_args.resource = args->resource;
2164 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2165
2166 for (c = 0; c < 2; c++) {
2167 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2168 LLVMConstInt(ctx->i32, c, false), "");
2169 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2170 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2171 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2172 LLVMConstReal(ctx->f32, -0.5), "");
2173 }
2174 }
2175
2176 LLVMValueRef orig_coords = args->addr;
2177
2178 for (c = 0; c < 2; c++) {
2179 LLVMValueRef tmp;
2180 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2181 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2182 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2183 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2184 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2185 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2186 }
2187
2188
2189 /*
2190 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2191 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2192 * workaround by sampling using a scaled type and converting.
2193 * This is taken from amdgpu-pro shaders.
2194 */
2195 /* NOTE this produces some ugly code compared to amdgpu-pro,
2196 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2197 * and then reads them back. -pro generates two selects,
2198 * one s_cmp for the descriptor rewriting
2199 * one v_cmp for the coordinate and result changes.
2200 */
2201 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2202 LLVMValueRef tmp, tmp2;
2203
2204 /* workaround 8/8/8/8 uint/sint cube gather bug */
2205 /* first detect it then change to a scaled read and f2i */
2206 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2207 tmp2 = tmp;
2208
2209 /* extract the DATA_FORMAT */
2210 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2211 LLVMConstInt(ctx->i32, 6, false), false);
2212
2213 /* is the DATA_FORMAT == 8_8_8_8 */
2214 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2215
2216 if (stype == GLSL_TYPE_UINT)
2217 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2218 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2219 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2220 else
2221 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2222 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2223 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2224
2225 /* replace the NUM FORMAT in the descriptor */
2226 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2227 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2228
2229 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2230
2231 /* don't modify the coordinates for this case */
2232 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2233 }
2234 args->addr = coord;
2235 result = ac_build_image_opcode(ctx, args);
2236
2237 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2238 LLVMValueRef tmp, tmp2;
2239
2240 /* if the cube workaround is in place, f2i the result. */
2241 for (c = 0; c < 4; c++) {
2242 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2243 if (stype == GLSL_TYPE_UINT)
2244 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2245 else
2246 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2247 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2248 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2249 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2250 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2251 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2252 }
2253 }
2254 return result;
2255 }
2256
2257 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2258 const nir_tex_instr *instr,
2259 bool lod_is_zero,
2260 struct ac_image_args *args)
2261 {
2262 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2263 return ac_build_buffer_load_format(&ctx->ac,
2264 args->resource,
2265 args->addr,
2266 ctx->ac.i32_0,
2267 true);
2268 }
2269
2270 args->opcode = ac_image_sample;
2271 args->compare = instr->is_shadow;
2272
2273 switch (instr->op) {
2274 case nir_texop_txf:
2275 case nir_texop_txf_ms:
2276 case nir_texop_samples_identical:
2277 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2278 args->compare = false;
2279 args->offset = false;
2280 break;
2281 case nir_texop_txb:
2282 args->bias = true;
2283 break;
2284 case nir_texop_txl:
2285 if (lod_is_zero)
2286 args->level_zero = true;
2287 else
2288 args->lod = true;
2289 break;
2290 case nir_texop_txs:
2291 case nir_texop_query_levels:
2292 args->opcode = ac_image_get_resinfo;
2293 break;
2294 case nir_texop_tex:
2295 if (ctx->stage != MESA_SHADER_FRAGMENT)
2296 args->level_zero = true;
2297 break;
2298 case nir_texop_txd:
2299 args->deriv = true;
2300 break;
2301 case nir_texop_tg4:
2302 args->opcode = ac_image_gather4;
2303 args->level_zero = true;
2304 break;
2305 case nir_texop_lod:
2306 args->opcode = ac_image_get_lod;
2307 args->compare = false;
2308 args->offset = false;
2309 break;
2310 default:
2311 break;
2312 }
2313
2314 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2315 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2316 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2317 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2318 }
2319 }
2320 return ac_build_image_opcode(&ctx->ac, args);
2321 }
2322
2323 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2324 nir_intrinsic_instr *instr)
2325 {
2326 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2327 unsigned desc_set = nir_intrinsic_desc_set(instr);
2328 unsigned binding = nir_intrinsic_binding(instr);
2329 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2330 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2331 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2332 unsigned base_offset = layout->binding[binding].offset;
2333 LLVMValueRef offset, stride;
2334
2335 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2336 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2337 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2338 layout->binding[binding].dynamic_offset_offset;
2339 desc_ptr = ctx->push_constants;
2340 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2341 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2342 } else
2343 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2344
2345 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2346 index = LLVMBuildMul(ctx->builder, index, stride, "");
2347 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2348
2349 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2350 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2351 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2352
2353 return desc_ptr;
2354 }
2355
2356 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2357 nir_intrinsic_instr *instr)
2358 {
2359 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2360 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2361
2362 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2363 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2364 return result;
2365 }
2366
2367 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2368 nir_intrinsic_instr *instr)
2369 {
2370 LLVMValueRef ptr, addr;
2371
2372 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2373 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2374
2375 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2376 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2377
2378 return LLVMBuildLoad(ctx->builder, ptr, "");
2379 }
2380
2381 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2382 const nir_intrinsic_instr *instr)
2383 {
2384 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2385
2386 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2387 }
2388 static void visit_store_ssbo(struct ac_nir_context *ctx,
2389 nir_intrinsic_instr *instr)
2390 {
2391 const char *store_name;
2392 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2393 LLVMTypeRef data_type = ctx->ac.f32;
2394 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2395 int components_32bit = elem_size_mult * instr->num_components;
2396 unsigned writemask = nir_intrinsic_write_mask(instr);
2397 LLVMValueRef base_data, base_offset;
2398 LLVMValueRef params[6];
2399
2400 params[1] = ctx->abi->load_ssbo(ctx->abi,
2401 get_src(ctx, instr->src[1]), true);
2402 params[2] = ctx->ac.i32_0; /* vindex */
2403 params[4] = ctx->ac.i1false; /* glc */
2404 params[5] = ctx->ac.i1false; /* slc */
2405
2406 if (components_32bit > 1)
2407 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2408
2409 base_data = ac_to_float(&ctx->ac, src_data);
2410 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2411 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2412 data_type, "");
2413 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2414 while (writemask) {
2415 int start, count;
2416 LLVMValueRef data;
2417 LLVMValueRef offset;
2418 LLVMValueRef tmp;
2419 u_bit_scan_consecutive_range(&writemask, &start, &count);
2420
2421 /* Due to an LLVM limitation, split 3-element writes
2422 * into a 2-element and a 1-element write. */
2423 if (count == 3) {
2424 writemask |= 1 << (start + 2);
2425 count = 2;
2426 }
2427
2428 start *= elem_size_mult;
2429 count *= elem_size_mult;
2430
2431 if (count > 4) {
2432 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2433 count = 4;
2434 }
2435
2436 if (count == 4) {
2437 store_name = "llvm.amdgcn.buffer.store.v4f32";
2438 data = base_data;
2439 } else if (count == 2) {
2440 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2441 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2442 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2443 ctx->ac.i32_0, "");
2444
2445 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2446 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2447 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2448 ctx->ac.i32_1, "");
2449 store_name = "llvm.amdgcn.buffer.store.v2f32";
2450
2451 } else {
2452 assert(count == 1);
2453 if (get_llvm_num_components(base_data) > 1)
2454 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2455 LLVMConstInt(ctx->ac.i32, start, false), "");
2456 else
2457 data = base_data;
2458 store_name = "llvm.amdgcn.buffer.store.f32";
2459 }
2460
2461 offset = base_offset;
2462 if (start != 0) {
2463 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2464 }
2465 params[0] = data;
2466 params[3] = offset;
2467 ac_build_intrinsic(&ctx->ac, store_name,
2468 ctx->ac.voidt, params, 6, 0);
2469 }
2470 }
2471
2472 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2473 const nir_intrinsic_instr *instr)
2474 {
2475 const char *name;
2476 LLVMValueRef params[6];
2477 int arg_count = 0;
2478
2479 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2480 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2481 }
2482 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2483 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2484 get_src(ctx, instr->src[0]),
2485 true);
2486 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2487 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2488 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2489
2490 switch (instr->intrinsic) {
2491 case nir_intrinsic_ssbo_atomic_add:
2492 name = "llvm.amdgcn.buffer.atomic.add";
2493 break;
2494 case nir_intrinsic_ssbo_atomic_imin:
2495 name = "llvm.amdgcn.buffer.atomic.smin";
2496 break;
2497 case nir_intrinsic_ssbo_atomic_umin:
2498 name = "llvm.amdgcn.buffer.atomic.umin";
2499 break;
2500 case nir_intrinsic_ssbo_atomic_imax:
2501 name = "llvm.amdgcn.buffer.atomic.smax";
2502 break;
2503 case nir_intrinsic_ssbo_atomic_umax:
2504 name = "llvm.amdgcn.buffer.atomic.umax";
2505 break;
2506 case nir_intrinsic_ssbo_atomic_and:
2507 name = "llvm.amdgcn.buffer.atomic.and";
2508 break;
2509 case nir_intrinsic_ssbo_atomic_or:
2510 name = "llvm.amdgcn.buffer.atomic.or";
2511 break;
2512 case nir_intrinsic_ssbo_atomic_xor:
2513 name = "llvm.amdgcn.buffer.atomic.xor";
2514 break;
2515 case nir_intrinsic_ssbo_atomic_exchange:
2516 name = "llvm.amdgcn.buffer.atomic.swap";
2517 break;
2518 case nir_intrinsic_ssbo_atomic_comp_swap:
2519 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2520 break;
2521 default:
2522 abort();
2523 }
2524
2525 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2526 }
2527
2528 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2529 const nir_intrinsic_instr *instr)
2530 {
2531 LLVMValueRef results[2];
2532 int load_components;
2533 int num_components = instr->num_components;
2534 if (instr->dest.ssa.bit_size == 64)
2535 num_components *= 2;
2536
2537 for (int i = 0; i < num_components; i += load_components) {
2538 load_components = MIN2(num_components - i, 4);
2539 const char *load_name;
2540 LLVMTypeRef data_type = ctx->ac.f32;
2541 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2542 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2543
2544 if (load_components == 3)
2545 data_type = LLVMVectorType(ctx->ac.f32, 4);
2546 else if (load_components > 1)
2547 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2548
2549 if (load_components >= 3)
2550 load_name = "llvm.amdgcn.buffer.load.v4f32";
2551 else if (load_components == 2)
2552 load_name = "llvm.amdgcn.buffer.load.v2f32";
2553 else if (load_components == 1)
2554 load_name = "llvm.amdgcn.buffer.load.f32";
2555 else
2556 unreachable("unhandled number of components");
2557
2558 LLVMValueRef params[] = {
2559 ctx->abi->load_ssbo(ctx->abi,
2560 get_src(ctx, instr->src[0]),
2561 false),
2562 ctx->ac.i32_0,
2563 offset,
2564 ctx->ac.i1false,
2565 ctx->ac.i1false,
2566 };
2567
2568 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2569
2570 }
2571
2572 assume(results[0]);
2573 LLVMValueRef ret = results[0];
2574 if (num_components > 4 || num_components == 3) {
2575 LLVMValueRef masks[] = {
2576 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2577 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2578 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2579 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2580 };
2581
2582 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2583 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2584 results[num_components > 4 ? 1 : 0], swizzle, "");
2585 }
2586
2587 return LLVMBuildBitCast(ctx->ac.builder, ret,
2588 get_def_type(ctx, &instr->dest.ssa), "");
2589 }
2590
2591 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2592 const nir_intrinsic_instr *instr)
2593 {
2594 LLVMValueRef results[8], ret;
2595 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2596 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2597 int num_components = instr->num_components;
2598
2599 if (ctx->abi->load_ubo)
2600 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2601
2602 if (instr->dest.ssa.bit_size == 64)
2603 num_components *= 2;
2604
2605 for (unsigned i = 0; i < num_components; ++i) {
2606 LLVMValueRef params[] = {
2607 rsrc,
2608 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2609 offset, "")
2610 };
2611 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2612 params, 2,
2613 AC_FUNC_ATTR_READNONE |
2614 AC_FUNC_ATTR_LEGACY);
2615 }
2616
2617
2618 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2619 return LLVMBuildBitCast(ctx->ac.builder, ret,
2620 get_def_type(ctx, &instr->dest.ssa), "");
2621 }
2622
2623 static void
2624 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2625 bool vs_in, unsigned *vertex_index_out,
2626 LLVMValueRef *vertex_index_ref,
2627 unsigned *const_out, LLVMValueRef *indir_out)
2628 {
2629 unsigned const_offset = 0;
2630 nir_deref *tail = &deref->deref;
2631 LLVMValueRef offset = NULL;
2632
2633 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2634 tail = tail->child;
2635 nir_deref_array *deref_array = nir_deref_as_array(tail);
2636 if (vertex_index_out)
2637 *vertex_index_out = deref_array->base_offset;
2638
2639 if (vertex_index_ref) {
2640 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2641 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2642 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2643 }
2644 *vertex_index_ref = vtx;
2645 }
2646 }
2647
2648 if (deref->var->data.compact) {
2649 assert(tail->child->deref_type == nir_deref_type_array);
2650 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2651 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2652 /* We always lower indirect dereferences for "compact" array vars. */
2653 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2654
2655 const_offset = deref_array->base_offset;
2656 goto out;
2657 }
2658
2659 while (tail->child != NULL) {
2660 const struct glsl_type *parent_type = tail->type;
2661 tail = tail->child;
2662
2663 if (tail->deref_type == nir_deref_type_array) {
2664 nir_deref_array *deref_array = nir_deref_as_array(tail);
2665 LLVMValueRef index, stride, local_offset;
2666 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2667
2668 const_offset += size * deref_array->base_offset;
2669 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2670 continue;
2671
2672 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2673 index = get_src(ctx, deref_array->indirect);
2674 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2675 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2676
2677 if (offset)
2678 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2679 else
2680 offset = local_offset;
2681 } else if (tail->deref_type == nir_deref_type_struct) {
2682 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2683
2684 for (unsigned i = 0; i < deref_struct->index; i++) {
2685 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2686 const_offset += glsl_count_attribute_slots(ft, vs_in);
2687 }
2688 } else
2689 unreachable("unsupported deref type");
2690
2691 }
2692 out:
2693 if (const_offset && offset)
2694 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2695 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2696 "");
2697
2698 *const_out = const_offset;
2699 *indir_out = offset;
2700 }
2701
2702
2703 /* The offchip buffer layout for TCS->TES is
2704 *
2705 * - attribute 0 of patch 0 vertex 0
2706 * - attribute 0 of patch 0 vertex 1
2707 * - attribute 0 of patch 0 vertex 2
2708 * ...
2709 * - attribute 0 of patch 1 vertex 0
2710 * - attribute 0 of patch 1 vertex 1
2711 * ...
2712 * - attribute 1 of patch 0 vertex 0
2713 * - attribute 1 of patch 0 vertex 1
2714 * ...
2715 * - per patch attribute 0 of patch 0
2716 * - per patch attribute 0 of patch 1
2717 * ...
2718 *
2719 * Note that every attribute has 4 components.
2720 */
2721 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2722 LLVMValueRef vertex_index,
2723 LLVMValueRef param_index)
2724 {
2725 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2726 LLVMValueRef param_stride, constant16;
2727 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2728
2729 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2730 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2731 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2732 num_patches, "");
2733
2734 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2735 if (vertex_index) {
2736 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2737 vertices_per_patch, "");
2738
2739 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2740 vertex_index, "");
2741
2742 param_stride = total_vertices;
2743 } else {
2744 base_addr = rel_patch_id;
2745 param_stride = num_patches;
2746 }
2747
2748 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2749 LLVMBuildMul(ctx->builder, param_index,
2750 param_stride, ""), "");
2751
2752 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2753
2754 if (!vertex_index) {
2755 LLVMValueRef patch_data_offset =
2756 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2757
2758 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2759 patch_data_offset, "");
2760 }
2761 return base_addr;
2762 }
2763
2764 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2765 unsigned param,
2766 unsigned const_index,
2767 bool is_compact,
2768 LLVMValueRef vertex_index,
2769 LLVMValueRef indir_index)
2770 {
2771 LLVMValueRef param_index;
2772
2773 if (indir_index)
2774 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2775 indir_index, "");
2776 else {
2777 if (const_index && !is_compact)
2778 param += const_index;
2779 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2780 }
2781 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2782 }
2783
2784 static void
2785 mark_tess_output(struct nir_to_llvm_context *ctx,
2786 bool is_patch, uint32_t param)
2787
2788 {
2789 if (is_patch) {
2790 ctx->tess_patch_outputs_written |= (1ull << param);
2791 } else
2792 ctx->tess_outputs_written |= (1ull << param);
2793 }
2794
2795 static LLVMValueRef
2796 get_dw_address(struct nir_to_llvm_context *ctx,
2797 LLVMValueRef dw_addr,
2798 unsigned param,
2799 unsigned const_index,
2800 bool compact_const_index,
2801 LLVMValueRef vertex_index,
2802 LLVMValueRef stride,
2803 LLVMValueRef indir_index)
2804
2805 {
2806
2807 if (vertex_index) {
2808 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2809 LLVMBuildMul(ctx->builder,
2810 vertex_index,
2811 stride, ""), "");
2812 }
2813
2814 if (indir_index)
2815 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2816 LLVMBuildMul(ctx->builder, indir_index,
2817 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2818 else if (const_index && !compact_const_index)
2819 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2820 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2821
2822 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2823 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2824
2825 if (const_index && compact_const_index)
2826 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2827 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2828 return dw_addr;
2829 }
2830
2831 static LLVMValueRef
2832 load_tcs_input(struct nir_to_llvm_context *ctx,
2833 nir_intrinsic_instr *instr)
2834 {
2835 LLVMValueRef dw_addr, stride;
2836 unsigned const_index;
2837 LLVMValueRef vertex_index;
2838 LLVMValueRef indir_index;
2839 unsigned param;
2840 LLVMValueRef value[4], result;
2841 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2842 const bool is_compact = instr->variables[0]->var->data.compact;
2843 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2844 get_deref_offset(ctx->nir, instr->variables[0],
2845 false, NULL, per_vertex ? &vertex_index : NULL,
2846 &const_index, &indir_index);
2847
2848 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2849 dw_addr = get_tcs_in_current_patch_offset(ctx);
2850 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2851 indir_index);
2852
2853 unsigned comp = instr->variables[0]->var->data.location_frac;
2854 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2855 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2856 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2857 ctx->ac.i32_1, "");
2858 }
2859 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2860 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2861 return result;
2862 }
2863
2864 static LLVMValueRef
2865 load_tcs_output(struct nir_to_llvm_context *ctx,
2866 nir_intrinsic_instr *instr)
2867 {
2868 LLVMValueRef dw_addr;
2869 LLVMValueRef stride = NULL;
2870 LLVMValueRef value[4], result;
2871 LLVMValueRef vertex_index = NULL;
2872 LLVMValueRef indir_index = NULL;
2873 unsigned const_index = 0;
2874 unsigned param;
2875 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2876 const bool is_compact = instr->variables[0]->var->data.compact;
2877 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2878 get_deref_offset(ctx->nir, instr->variables[0],
2879 false, NULL, per_vertex ? &vertex_index : NULL,
2880 &const_index, &indir_index);
2881
2882 if (!instr->variables[0]->var->data.patch) {
2883 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2884 dw_addr = get_tcs_out_current_patch_offset(ctx);
2885 } else {
2886 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2887 }
2888
2889 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2890 indir_index);
2891
2892 unsigned comp = instr->variables[0]->var->data.location_frac;
2893 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2894 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2895 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2896 ctx->ac.i32_1, "");
2897 }
2898 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2899 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2900 return result;
2901 }
2902
2903 static void
2904 store_tcs_output(struct nir_to_llvm_context *ctx,
2905 nir_intrinsic_instr *instr,
2906 LLVMValueRef src,
2907 unsigned writemask)
2908 {
2909 LLVMValueRef dw_addr;
2910 LLVMValueRef stride = NULL;
2911 LLVMValueRef buf_addr = NULL;
2912 LLVMValueRef vertex_index = NULL;
2913 LLVMValueRef indir_index = NULL;
2914 unsigned const_index = 0;
2915 unsigned param;
2916 const unsigned comp = instr->variables[0]->var->data.location_frac;
2917 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2918 const bool is_compact = instr->variables[0]->var->data.compact;
2919 bool store_lds = true;
2920
2921 if (instr->variables[0]->var->data.patch) {
2922 if (!(ctx->tcs_patch_outputs_read & (1U << (instr->variables[0]->var->data.location - VARYING_SLOT_PATCH0))))
2923 store_lds = false;
2924 } else {
2925 if (!(ctx->tcs_outputs_read & (1ULL << instr->variables[0]->var->data.location)))
2926 store_lds = false;
2927 }
2928 get_deref_offset(ctx->nir, instr->variables[0],
2929 false, NULL, per_vertex ? &vertex_index : NULL,
2930 &const_index, &indir_index);
2931
2932 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2933 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2934 is_compact && const_index > 3) {
2935 const_index -= 3;
2936 param++;
2937 }
2938
2939 if (!instr->variables[0]->var->data.patch) {
2940 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2941 dw_addr = get_tcs_out_current_patch_offset(ctx);
2942 } else {
2943 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2944 }
2945
2946 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2947
2948 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2949 indir_index);
2950 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2951 vertex_index, indir_index);
2952
2953 bool is_tess_factor = false;
2954 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2955 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2956 is_tess_factor = true;
2957
2958 unsigned base = is_compact ? const_index : 0;
2959 for (unsigned chan = 0; chan < 8; chan++) {
2960 if (!(writemask & (1 << chan)))
2961 continue;
2962 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2963
2964 if (store_lds || is_tess_factor)
2965 ac_lds_store(&ctx->ac, dw_addr, value);
2966
2967 if (!is_tess_factor && writemask != 0xF)
2968 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2969 buf_addr, ctx->oc_lds,
2970 4 * (base + chan), 1, 0, true, false);
2971
2972 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2973 ctx->ac.i32_1, "");
2974 }
2975
2976 if (writemask == 0xF) {
2977 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2978 buf_addr, ctx->oc_lds,
2979 (base * 4), 1, 0, true, false);
2980 }
2981 }
2982
2983 static LLVMValueRef
2984 load_tes_input(struct nir_to_llvm_context *ctx,
2985 const nir_intrinsic_instr *instr)
2986 {
2987 LLVMValueRef buf_addr;
2988 LLVMValueRef result;
2989 LLVMValueRef vertex_index = NULL;
2990 LLVMValueRef indir_index = NULL;
2991 unsigned const_index = 0;
2992 unsigned param;
2993 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2994 const bool is_compact = instr->variables[0]->var->data.compact;
2995
2996 get_deref_offset(ctx->nir, instr->variables[0],
2997 false, NULL, per_vertex ? &vertex_index : NULL,
2998 &const_index, &indir_index);
2999 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
3000 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
3001 is_compact && const_index > 3) {
3002 const_index -= 3;
3003 param++;
3004 }
3005
3006 unsigned comp = instr->variables[0]->var->data.location_frac;
3007 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3008 is_compact, vertex_index, indir_index);
3009
3010 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, comp * 4, false);
3011 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3012
3013 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
3014 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3015 result = trim_vector(&ctx->ac, result, instr->num_components);
3016 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
3017 return result;
3018 }
3019
3020 static LLVMValueRef
3021 load_gs_input(struct ac_shader_abi *abi,
3022 unsigned location,
3023 unsigned driver_location,
3024 unsigned component,
3025 unsigned num_components,
3026 unsigned vertex_index,
3027 unsigned const_index,
3028 LLVMTypeRef type)
3029 {
3030 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3031 LLVMValueRef vtx_offset;
3032 LLVMValueRef args[9];
3033 unsigned param, vtx_offset_param;
3034 LLVMValueRef value[4], result;
3035
3036 vtx_offset_param = vertex_index;
3037 assert(vtx_offset_param < 6);
3038 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3039 LLVMConstInt(ctx->ac.i32, 4, false), "");
3040
3041 param = shader_io_get_unique_index(location);
3042
3043 for (unsigned i = component; i < num_components + component; i++) {
3044 if (ctx->ac.chip_class >= GFX9) {
3045 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3046 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3047 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3048 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3049 } else {
3050 args[0] = ctx->esgs_ring;
3051 args[1] = vtx_offset;
3052 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3053 args[3] = ctx->ac.i32_0;
3054 args[4] = ctx->ac.i32_1; /* OFFEN */
3055 args[5] = ctx->ac.i32_0; /* IDXEN */
3056 args[6] = ctx->ac.i32_1; /* GLC */
3057 args[7] = ctx->ac.i32_0; /* SLC */
3058 args[8] = ctx->ac.i32_0; /* TFE */
3059
3060 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3061 ctx->ac.i32, args, 9,
3062 AC_FUNC_ATTR_READONLY |
3063 AC_FUNC_ATTR_LEGACY);
3064 }
3065 }
3066 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3067
3068 return result;
3069 }
3070
3071 static LLVMValueRef
3072 build_gep_for_deref(struct ac_nir_context *ctx,
3073 nir_deref_var *deref)
3074 {
3075 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3076 assert(entry->data);
3077 LLVMValueRef val = entry->data;
3078 nir_deref *tail = deref->deref.child;
3079 while (tail != NULL) {
3080 LLVMValueRef offset;
3081 switch (tail->deref_type) {
3082 case nir_deref_type_array: {
3083 nir_deref_array *array = nir_deref_as_array(tail);
3084 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3085 if (array->deref_array_type ==
3086 nir_deref_array_type_indirect) {
3087 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3088 get_src(ctx,
3089 array->indirect),
3090 "");
3091 }
3092 break;
3093 }
3094 case nir_deref_type_struct: {
3095 nir_deref_struct *deref_struct =
3096 nir_deref_as_struct(tail);
3097 offset = LLVMConstInt(ctx->ac.i32,
3098 deref_struct->index, 0);
3099 break;
3100 }
3101 default:
3102 unreachable("bad deref type");
3103 }
3104 val = ac_build_gep0(&ctx->ac, val, offset);
3105 tail = tail->child;
3106 }
3107 return val;
3108 }
3109
3110 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3111 nir_intrinsic_instr *instr)
3112 {
3113 LLVMValueRef values[8];
3114 int idx = instr->variables[0]->var->data.driver_location;
3115 int ve = instr->dest.ssa.num_components;
3116 unsigned comp = instr->variables[0]->var->data.location_frac;
3117 LLVMValueRef indir_index;
3118 LLVMValueRef ret;
3119 unsigned const_index;
3120 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3121 instr->variables[0]->var->data.mode == nir_var_shader_in;
3122 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3123 &const_index, &indir_index);
3124
3125 if (instr->dest.ssa.bit_size == 64)
3126 ve *= 2;
3127
3128 switch (instr->variables[0]->var->data.mode) {
3129 case nir_var_shader_in:
3130 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3131 return load_tcs_input(ctx->nctx, instr);
3132 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3133 return load_tes_input(ctx->nctx, instr);
3134 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3135 LLVMValueRef indir_index;
3136 unsigned const_index, vertex_index;
3137 get_deref_offset(ctx, instr->variables[0],
3138 false, &vertex_index, NULL,
3139 &const_index, &indir_index);
3140 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3141 instr->variables[0]->var->data.driver_location,
3142 instr->variables[0]->var->data.location_frac, ve,
3143 vertex_index, const_index,
3144 nir2llvmtype(ctx, instr->variables[0]->var->type));
3145 }
3146
3147 for (unsigned chan = comp; chan < ve + comp; chan++) {
3148 if (indir_index) {
3149 unsigned count = glsl_count_attribute_slots(
3150 instr->variables[0]->var->type,
3151 ctx->stage == MESA_SHADER_VERTEX);
3152 count -= chan / 4;
3153 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3154 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3155 4, false, true);
3156
3157 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3158 tmp_vec,
3159 indir_index, "");
3160 } else
3161 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3162 }
3163 break;
3164 case nir_var_local:
3165 for (unsigned chan = 0; chan < ve; chan++) {
3166 if (indir_index) {
3167 unsigned count = glsl_count_attribute_slots(
3168 instr->variables[0]->var->type, false);
3169 count -= chan / 4;
3170 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3171 &ctx->ac, ctx->locals + idx + chan, count,
3172 4, true, true);
3173
3174 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3175 tmp_vec,
3176 indir_index, "");
3177 } else {
3178 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3179 }
3180 }
3181 break;
3182 case nir_var_shared: {
3183 LLVMValueRef address = build_gep_for_deref(ctx,
3184 instr->variables[0]);
3185 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3186 return LLVMBuildBitCast(ctx->ac.builder, val,
3187 get_def_type(ctx, &instr->dest.ssa),
3188 "");
3189 }
3190 case nir_var_shader_out:
3191 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3192 return load_tcs_output(ctx->nctx, instr);
3193
3194 for (unsigned chan = comp; chan < ve + comp; chan++) {
3195 if (indir_index) {
3196 unsigned count = glsl_count_attribute_slots(
3197 instr->variables[0]->var->type, false);
3198 count -= chan / 4;
3199 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3200 &ctx->ac, ctx->outputs + idx + chan, count,
3201 4, true, true);
3202
3203 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3204 tmp_vec,
3205 indir_index, "");
3206 } else {
3207 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3208 ctx->outputs[idx + chan + const_index * 4],
3209 "");
3210 }
3211 }
3212 break;
3213 default:
3214 unreachable("unhandle variable mode");
3215 }
3216 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3217 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3218 }
3219
3220 static void
3221 visit_store_var(struct ac_nir_context *ctx,
3222 nir_intrinsic_instr *instr)
3223 {
3224 LLVMValueRef temp_ptr, value;
3225 int idx = instr->variables[0]->var->data.driver_location;
3226 unsigned comp = instr->variables[0]->var->data.location_frac;
3227 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3228 int writemask = instr->const_index[0] << comp;
3229 LLVMValueRef indir_index;
3230 unsigned const_index;
3231 get_deref_offset(ctx, instr->variables[0], false,
3232 NULL, NULL, &const_index, &indir_index);
3233
3234 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3235 int old_writemask = writemask;
3236
3237 src = LLVMBuildBitCast(ctx->ac.builder, src,
3238 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3239 "");
3240
3241 writemask = 0;
3242 for (unsigned chan = 0; chan < 4; chan++) {
3243 if (old_writemask & (1 << chan))
3244 writemask |= 3u << (2 * chan);
3245 }
3246 }
3247
3248 switch (instr->variables[0]->var->data.mode) {
3249 case nir_var_shader_out:
3250
3251 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3252 store_tcs_output(ctx->nctx, instr, src, writemask);
3253 return;
3254 }
3255
3256 for (unsigned chan = 0; chan < 8; chan++) {
3257 int stride = 4;
3258 if (!(writemask & (1 << chan)))
3259 continue;
3260
3261 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3262
3263 if (instr->variables[0]->var->data.compact)
3264 stride = 1;
3265 if (indir_index) {
3266 unsigned count = glsl_count_attribute_slots(
3267 instr->variables[0]->var->type, false);
3268 count -= chan / 4;
3269 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3270 &ctx->ac, ctx->outputs + idx + chan, count,
3271 stride, true, true);
3272
3273 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3274 value, indir_index, "");
3275 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3276 count, stride, tmp_vec);
3277
3278 } else {
3279 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3280
3281 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3282 }
3283 }
3284 break;
3285 case nir_var_local:
3286 for (unsigned chan = 0; chan < 8; chan++) {
3287 if (!(writemask & (1 << chan)))
3288 continue;
3289
3290 value = llvm_extract_elem(&ctx->ac, src, chan);
3291 if (indir_index) {
3292 unsigned count = glsl_count_attribute_slots(
3293 instr->variables[0]->var->type, false);
3294 count -= chan / 4;
3295 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3296 &ctx->ac, ctx->locals + idx + chan, count,
3297 4, true, true);
3298
3299 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3300 value, indir_index, "");
3301 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3302 count, 4, tmp_vec);
3303 } else {
3304 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3305
3306 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3307 }
3308 }
3309 break;
3310 case nir_var_shared: {
3311 int writemask = instr->const_index[0];
3312 LLVMValueRef address = build_gep_for_deref(ctx,
3313 instr->variables[0]);
3314 LLVMValueRef val = get_src(ctx, instr->src[0]);
3315 unsigned components =
3316 glsl_get_vector_elements(
3317 nir_deref_tail(&instr->variables[0]->deref)->type);
3318 if (writemask == (1 << components) - 1) {
3319 val = LLVMBuildBitCast(
3320 ctx->ac.builder, val,
3321 LLVMGetElementType(LLVMTypeOf(address)), "");
3322 LLVMBuildStore(ctx->ac.builder, val, address);
3323 } else {
3324 for (unsigned chan = 0; chan < 4; chan++) {
3325 if (!(writemask & (1 << chan)))
3326 continue;
3327 LLVMValueRef ptr =
3328 LLVMBuildStructGEP(ctx->ac.builder,
3329 address, chan, "");
3330 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3331 chan);
3332 src = LLVMBuildBitCast(
3333 ctx->ac.builder, src,
3334 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3335 LLVMBuildStore(ctx->ac.builder, src, ptr);
3336 }
3337 }
3338 break;
3339 }
3340 default:
3341 break;
3342 }
3343 }
3344
3345 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3346 {
3347 switch (dim) {
3348 case GLSL_SAMPLER_DIM_BUF:
3349 return 1;
3350 case GLSL_SAMPLER_DIM_1D:
3351 return array ? 2 : 1;
3352 case GLSL_SAMPLER_DIM_2D:
3353 return array ? 3 : 2;
3354 case GLSL_SAMPLER_DIM_MS:
3355 return array ? 4 : 3;
3356 case GLSL_SAMPLER_DIM_3D:
3357 case GLSL_SAMPLER_DIM_CUBE:
3358 return 3;
3359 case GLSL_SAMPLER_DIM_RECT:
3360 case GLSL_SAMPLER_DIM_SUBPASS:
3361 return 2;
3362 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3363 return 3;
3364 default:
3365 break;
3366 }
3367 return 0;
3368 }
3369
3370
3371
3372 /* Adjust the sample index according to FMASK.
3373 *
3374 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3375 * which is the identity mapping. Each nibble says which physical sample
3376 * should be fetched to get that sample.
3377 *
3378 * For example, 0x11111100 means there are only 2 samples stored and
3379 * the second sample covers 3/4 of the pixel. When reading samples 0
3380 * and 1, return physical sample 0 (determined by the first two 0s
3381 * in FMASK), otherwise return physical sample 1.
3382 *
3383 * The sample index should be adjusted as follows:
3384 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3385 */
3386 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3387 LLVMValueRef coord_x, LLVMValueRef coord_y,
3388 LLVMValueRef coord_z,
3389 LLVMValueRef sample_index,
3390 LLVMValueRef fmask_desc_ptr)
3391 {
3392 LLVMValueRef fmask_load_address[4];
3393 LLVMValueRef res;
3394
3395 fmask_load_address[0] = coord_x;
3396 fmask_load_address[1] = coord_y;
3397 if (coord_z) {
3398 fmask_load_address[2] = coord_z;
3399 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3400 }
3401
3402 struct ac_image_args args = {0};
3403
3404 args.opcode = ac_image_load;
3405 args.da = coord_z ? true : false;
3406 args.resource = fmask_desc_ptr;
3407 args.dmask = 0xf;
3408 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3409
3410 res = ac_build_image_opcode(ctx, &args);
3411
3412 res = ac_to_integer(ctx, res);
3413 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3414 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3415
3416 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3417 res,
3418 ctx->i32_0, "");
3419
3420 LLVMValueRef sample_index4 =
3421 LLVMBuildMul(ctx->builder, sample_index, four, "");
3422 LLVMValueRef shifted_fmask =
3423 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3424 LLVMValueRef final_sample =
3425 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3426
3427 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3428 * resource descriptor is 0 (invalid),
3429 */
3430 LLVMValueRef fmask_desc =
3431 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3432 ctx->v8i32, "");
3433
3434 LLVMValueRef fmask_word1 =
3435 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3436 ctx->i32_1, "");
3437
3438 LLVMValueRef word1_is_nonzero =
3439 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3440 fmask_word1, ctx->i32_0, "");
3441
3442 /* Replace the MSAA sample index. */
3443 sample_index =
3444 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3445 final_sample, sample_index, "");
3446 return sample_index;
3447 }
3448
3449 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3450 const nir_intrinsic_instr *instr)
3451 {
3452 const struct glsl_type *type = instr->variables[0]->var->type;
3453 if(instr->variables[0]->deref.child)
3454 type = instr->variables[0]->deref.child->type;
3455
3456 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3457 LLVMValueRef coords[4];
3458 LLVMValueRef masks[] = {
3459 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3460 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3461 };
3462 LLVMValueRef res;
3463 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3464
3465 int count;
3466 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3467 bool is_array = glsl_sampler_type_is_array(type);
3468 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3469 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3470 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3471 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3472 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3473 count = image_type_to_components_count(dim, is_array);
3474
3475 if (is_ms) {
3476 LLVMValueRef fmask_load_address[3];
3477 int chan;
3478
3479 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3480 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3481 if (is_array)
3482 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3483 else
3484 fmask_load_address[2] = NULL;
3485 if (add_frag_pos) {
3486 for (chan = 0; chan < 2; ++chan)
3487 fmask_load_address[chan] =
3488 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3489 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3490 ctx->ac.i32, ""), "");
3491 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3492 }
3493 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3494 fmask_load_address[0],
3495 fmask_load_address[1],
3496 fmask_load_address[2],
3497 sample_index,
3498 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3499 }
3500 if (count == 1 && !gfx9_1d) {
3501 if (instr->src[0].ssa->num_components)
3502 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3503 else
3504 res = src0;
3505 } else {
3506 int chan;
3507 if (is_ms)
3508 count--;
3509 for (chan = 0; chan < count; ++chan) {
3510 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3511 }
3512 if (add_frag_pos) {
3513 for (chan = 0; chan < 2; ++chan)
3514 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3515 ctx->ac.i32, ""), "");
3516 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3517 count++;
3518 }
3519
3520 if (gfx9_1d) {
3521 if (is_array) {
3522 coords[2] = coords[1];
3523 coords[1] = ctx->ac.i32_0;
3524 } else
3525 coords[1] = ctx->ac.i32_0;
3526 count++;
3527 }
3528
3529 if (is_ms) {
3530 coords[count] = sample_index;
3531 count++;
3532 }
3533
3534 if (count == 3) {
3535 coords[3] = LLVMGetUndef(ctx->ac.i32);
3536 count = 4;
3537 }
3538 res = ac_build_gather_values(&ctx->ac, coords, count);
3539 }
3540 return res;
3541 }
3542
3543 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3544 const nir_intrinsic_instr *instr)
3545 {
3546 LLVMValueRef params[7];
3547 LLVMValueRef res;
3548 char intrinsic_name[64];
3549 const nir_variable *var = instr->variables[0]->var;
3550 const struct glsl_type *type = var->type;
3551
3552 if(instr->variables[0]->deref.child)
3553 type = instr->variables[0]->deref.child->type;
3554
3555 type = glsl_without_array(type);
3556 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3557 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3558 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3559 ctx->ac.i32_0, ""); /* vindex */
3560 params[2] = ctx->ac.i32_0; /* voffset */
3561 params[3] = ctx->ac.i1false; /* glc */
3562 params[4] = ctx->ac.i1false; /* slc */
3563 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3564 params, 5, 0);
3565
3566 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3567 res = ac_to_integer(&ctx->ac, res);
3568 } else {
3569 bool is_da = glsl_sampler_type_is_array(type) ||
3570 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3571 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3572 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3573 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3574 LLVMValueRef glc = ctx->ac.i1false;
3575 LLVMValueRef slc = ctx->ac.i1false;
3576
3577 params[0] = get_image_coords(ctx, instr);
3578 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3579 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3580 if (HAVE_LLVM <= 0x0309) {
3581 params[3] = ctx->ac.i1false; /* r128 */
3582 params[4] = da;
3583 params[5] = glc;
3584 params[6] = slc;
3585 } else {
3586 LLVMValueRef lwe = ctx->ac.i1false;
3587 params[3] = glc;
3588 params[4] = slc;
3589 params[5] = lwe;
3590 params[6] = da;
3591 }
3592
3593 ac_get_image_intr_name("llvm.amdgcn.image.load",
3594 ctx->ac.v4f32, /* vdata */
3595 LLVMTypeOf(params[0]), /* coords */
3596 LLVMTypeOf(params[1]), /* rsrc */
3597 intrinsic_name, sizeof(intrinsic_name));
3598
3599 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3600 params, 7, AC_FUNC_ATTR_READONLY);
3601 }
3602 return ac_to_integer(&ctx->ac, res);
3603 }
3604
3605 static void visit_image_store(struct ac_nir_context *ctx,
3606 nir_intrinsic_instr *instr)
3607 {
3608 LLVMValueRef params[8];
3609 char intrinsic_name[64];
3610 const nir_variable *var = instr->variables[0]->var;
3611 const struct glsl_type *type = glsl_without_array(var->type);
3612 LLVMValueRef glc = ctx->ac.i1false;
3613 bool force_glc = ctx->ac.chip_class == SI;
3614 if (force_glc)
3615 glc = ctx->ac.i1true;
3616
3617 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3618 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3619 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3620 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3621 ctx->ac.i32_0, ""); /* vindex */
3622 params[3] = ctx->ac.i32_0; /* voffset */
3623 params[4] = glc; /* glc */
3624 params[5] = ctx->ac.i1false; /* slc */
3625 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3626 params, 6, 0);
3627 } else {
3628 bool is_da = glsl_sampler_type_is_array(type) ||
3629 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3630 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3631 LLVMValueRef slc = ctx->ac.i1false;
3632
3633 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3634 params[1] = get_image_coords(ctx, instr); /* coords */
3635 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3636 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3637 if (HAVE_LLVM <= 0x0309) {
3638 params[4] = ctx->ac.i1false; /* r128 */
3639 params[5] = da;
3640 params[6] = glc;
3641 params[7] = slc;
3642 } else {
3643 LLVMValueRef lwe = ctx->ac.i1false;
3644 params[4] = glc;
3645 params[5] = slc;
3646 params[6] = lwe;
3647 params[7] = da;
3648 }
3649
3650 ac_get_image_intr_name("llvm.amdgcn.image.store",
3651 LLVMTypeOf(params[0]), /* vdata */
3652 LLVMTypeOf(params[1]), /* coords */
3653 LLVMTypeOf(params[2]), /* rsrc */
3654 intrinsic_name, sizeof(intrinsic_name));
3655
3656 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3657 params, 8, 0);
3658 }
3659
3660 }
3661
3662 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3663 const nir_intrinsic_instr *instr)
3664 {
3665 LLVMValueRef params[7];
3666 int param_count = 0;
3667 const nir_variable *var = instr->variables[0]->var;
3668
3669 const char *atomic_name;
3670 char intrinsic_name[41];
3671 const struct glsl_type *type = glsl_without_array(var->type);
3672 MAYBE_UNUSED int length;
3673
3674 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3675
3676 switch (instr->intrinsic) {
3677 case nir_intrinsic_image_atomic_add:
3678 atomic_name = "add";
3679 break;
3680 case nir_intrinsic_image_atomic_min:
3681 atomic_name = is_unsigned ? "umin" : "smin";
3682 break;
3683 case nir_intrinsic_image_atomic_max:
3684 atomic_name = is_unsigned ? "umax" : "smax";
3685 break;
3686 case nir_intrinsic_image_atomic_and:
3687 atomic_name = "and";
3688 break;
3689 case nir_intrinsic_image_atomic_or:
3690 atomic_name = "or";
3691 break;
3692 case nir_intrinsic_image_atomic_xor:
3693 atomic_name = "xor";
3694 break;
3695 case nir_intrinsic_image_atomic_exchange:
3696 atomic_name = "swap";
3697 break;
3698 case nir_intrinsic_image_atomic_comp_swap:
3699 atomic_name = "cmpswap";
3700 break;
3701 default:
3702 abort();
3703 }
3704
3705 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3706 params[param_count++] = get_src(ctx, instr->src[3]);
3707 params[param_count++] = get_src(ctx, instr->src[2]);
3708
3709 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3710 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3711 NULL, true, true);
3712 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3713 ctx->ac.i32_0, ""); /* vindex */
3714 params[param_count++] = ctx->ac.i32_0; /* voffset */
3715 params[param_count++] = ctx->ac.i1false; /* slc */
3716
3717 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3718 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3719 } else {
3720 char coords_type[8];
3721
3722 bool da = glsl_sampler_type_is_array(type) ||
3723 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3724
3725 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3726 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3727 NULL, true, true);
3728 params[param_count++] = ctx->ac.i1false; /* r128 */
3729 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3730 params[param_count++] = ctx->ac.i1false; /* slc */
3731
3732 build_int_type_name(LLVMTypeOf(coords),
3733 coords_type, sizeof(coords_type));
3734
3735 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3736 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3737 }
3738
3739 assert(length < sizeof(intrinsic_name));
3740 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3741 }
3742
3743 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3744 const nir_intrinsic_instr *instr)
3745 {
3746 LLVMValueRef res;
3747 const nir_variable *var = instr->variables[0]->var;
3748 const struct glsl_type *type = instr->variables[0]->var->type;
3749 bool da = glsl_sampler_type_is_array(var->type) ||
3750 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3751 if(instr->variables[0]->deref.child)
3752 type = instr->variables[0]->deref.child->type;
3753
3754 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3755 return get_buffer_size(ctx,
3756 get_sampler_desc(ctx, instr->variables[0],
3757 AC_DESC_BUFFER, NULL, true, false), true);
3758
3759 struct ac_image_args args = { 0 };
3760
3761 args.da = da;
3762 args.dmask = 0xf;
3763 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3764 args.opcode = ac_image_get_resinfo;
3765 args.addr = ctx->ac.i32_0;
3766
3767 res = ac_build_image_opcode(&ctx->ac, &args);
3768
3769 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3770
3771 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3772 glsl_sampler_type_is_array(type)) {
3773 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3774 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3775 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3776 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3777 }
3778 if (ctx->ac.chip_class >= GFX9 &&
3779 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3780 glsl_sampler_type_is_array(type)) {
3781 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3782 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3783 ctx->ac.i32_1, "");
3784
3785 }
3786 return res;
3787 }
3788
3789 #define NOOP_WAITCNT 0xf7f
3790 #define LGKM_CNT 0x07f
3791 #define VM_CNT 0xf70
3792
3793 static void emit_membar(struct nir_to_llvm_context *ctx,
3794 const nir_intrinsic_instr *instr)
3795 {
3796 unsigned waitcnt = NOOP_WAITCNT;
3797
3798 switch (instr->intrinsic) {
3799 case nir_intrinsic_memory_barrier:
3800 case nir_intrinsic_group_memory_barrier:
3801 waitcnt &= VM_CNT & LGKM_CNT;
3802 break;
3803 case nir_intrinsic_memory_barrier_atomic_counter:
3804 case nir_intrinsic_memory_barrier_buffer:
3805 case nir_intrinsic_memory_barrier_image:
3806 waitcnt &= VM_CNT;
3807 break;
3808 case nir_intrinsic_memory_barrier_shared:
3809 waitcnt &= LGKM_CNT;
3810 break;
3811 default:
3812 break;
3813 }
3814 if (waitcnt != NOOP_WAITCNT)
3815 ac_build_waitcnt(&ctx->ac, waitcnt);
3816 }
3817
3818 static void emit_barrier(struct nir_to_llvm_context *ctx)
3819 {
3820 /* SI only (thanks to a hw bug workaround):
3821 * The real barrier instruction isn’t needed, because an entire patch
3822 * always fits into a single wave.
3823 */
3824 if (ctx->options->chip_class == SI &&
3825 ctx->stage == MESA_SHADER_TESS_CTRL) {
3826 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
3827 return;
3828 }
3829 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3830 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3831 }
3832
3833 static void emit_discard_if(struct ac_nir_context *ctx,
3834 const nir_intrinsic_instr *instr)
3835 {
3836 LLVMValueRef cond;
3837
3838 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3839 get_src(ctx, instr->src[0]),
3840 ctx->ac.i32_0, "");
3841 ac_build_kill_if_false(&ctx->ac, cond);
3842 }
3843
3844 static LLVMValueRef
3845 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3846 {
3847 LLVMValueRef result;
3848 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3849 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3850 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3851
3852 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3853 }
3854
3855 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3856 const nir_intrinsic_instr *instr)
3857 {
3858 LLVMValueRef ptr, result;
3859 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3860 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3861
3862 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3863 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3864 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3865 ptr, src, src1,
3866 LLVMAtomicOrderingSequentiallyConsistent,
3867 LLVMAtomicOrderingSequentiallyConsistent,
3868 false);
3869 } else {
3870 LLVMAtomicRMWBinOp op;
3871 switch (instr->intrinsic) {
3872 case nir_intrinsic_var_atomic_add:
3873 op = LLVMAtomicRMWBinOpAdd;
3874 break;
3875 case nir_intrinsic_var_atomic_umin:
3876 op = LLVMAtomicRMWBinOpUMin;
3877 break;
3878 case nir_intrinsic_var_atomic_umax:
3879 op = LLVMAtomicRMWBinOpUMax;
3880 break;
3881 case nir_intrinsic_var_atomic_imin:
3882 op = LLVMAtomicRMWBinOpMin;
3883 break;
3884 case nir_intrinsic_var_atomic_imax:
3885 op = LLVMAtomicRMWBinOpMax;
3886 break;
3887 case nir_intrinsic_var_atomic_and:
3888 op = LLVMAtomicRMWBinOpAnd;
3889 break;
3890 case nir_intrinsic_var_atomic_or:
3891 op = LLVMAtomicRMWBinOpOr;
3892 break;
3893 case nir_intrinsic_var_atomic_xor:
3894 op = LLVMAtomicRMWBinOpXor;
3895 break;
3896 case nir_intrinsic_var_atomic_exchange:
3897 op = LLVMAtomicRMWBinOpXchg;
3898 break;
3899 default:
3900 return NULL;
3901 }
3902
3903 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3904 LLVMAtomicOrderingSequentiallyConsistent,
3905 false);
3906 }
3907 return result;
3908 }
3909
3910 #define INTERP_CENTER 0
3911 #define INTERP_CENTROID 1
3912 #define INTERP_SAMPLE 2
3913
3914 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3915 enum glsl_interp_mode interp, unsigned location)
3916 {
3917 switch (interp) {
3918 case INTERP_MODE_FLAT:
3919 default:
3920 return NULL;
3921 case INTERP_MODE_SMOOTH:
3922 case INTERP_MODE_NONE:
3923 if (location == INTERP_CENTER)
3924 return ctx->persp_center;
3925 else if (location == INTERP_CENTROID)
3926 return ctx->persp_centroid;
3927 else if (location == INTERP_SAMPLE)
3928 return ctx->persp_sample;
3929 break;
3930 case INTERP_MODE_NOPERSPECTIVE:
3931 if (location == INTERP_CENTER)
3932 return ctx->linear_center;
3933 else if (location == INTERP_CENTROID)
3934 return ctx->linear_centroid;
3935 else if (location == INTERP_SAMPLE)
3936 return ctx->linear_sample;
3937 break;
3938 }
3939 return NULL;
3940 }
3941
3942 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3943 LLVMValueRef sample_id)
3944 {
3945 LLVMValueRef result;
3946 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3947
3948 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3949 const_array(ctx->ac.v2f32, 64), "");
3950
3951 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3952 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3953
3954 return result;
3955 }
3956
3957 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3958 {
3959 LLVMValueRef values[2];
3960
3961 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3962 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3963 return ac_build_gather_values(&ctx->ac, values, 2);
3964 }
3965
3966 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3967 const nir_intrinsic_instr *instr)
3968 {
3969 LLVMValueRef result[4];
3970 LLVMValueRef interp_param, attr_number;
3971 unsigned location;
3972 unsigned chan;
3973 LLVMValueRef src_c0 = NULL;
3974 LLVMValueRef src_c1 = NULL;
3975 LLVMValueRef src0 = NULL;
3976 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3977 switch (instr->intrinsic) {
3978 case nir_intrinsic_interp_var_at_centroid:
3979 location = INTERP_CENTROID;
3980 break;
3981 case nir_intrinsic_interp_var_at_sample:
3982 case nir_intrinsic_interp_var_at_offset:
3983 location = INTERP_CENTER;
3984 src0 = get_src(ctx->nir, instr->src[0]);
3985 break;
3986 default:
3987 break;
3988 }
3989
3990 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3991 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3992 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3993 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3994 LLVMValueRef sample_position;
3995 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
3996
3997 /* fetch sample ID */
3998 sample_position = load_sample_position(ctx, src0);
3999
4000 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4001 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4002 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4003 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4004 }
4005 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4006 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4007
4008 if (location == INTERP_CENTER) {
4009 LLVMValueRef ij_out[2];
4010 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4011
4012 /*
4013 * take the I then J parameters, and the DDX/Y for it, and
4014 * calculate the IJ inputs for the interpolator.
4015 * temp1 = ddx * offset/sample.x + I;
4016 * interp_param.I = ddy * offset/sample.y + temp1;
4017 * temp1 = ddx * offset/sample.x + J;
4018 * interp_param.J = ddy * offset/sample.y + temp1;
4019 */
4020 for (unsigned i = 0; i < 2; i++) {
4021 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4022 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4023 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4024 ddxy_out, ix_ll, "");
4025 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4026 ddxy_out, iy_ll, "");
4027 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4028 interp_param, ix_ll, "");
4029 LLVMValueRef temp1, temp2;
4030
4031 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4032 ctx->ac.f32, "");
4033
4034 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4035 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4036
4037 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4038 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4039
4040 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4041 temp2, ctx->ac.i32, "");
4042 }
4043 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4044
4045 }
4046
4047 for (chan = 0; chan < 4; chan++) {
4048 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4049
4050 if (interp_param) {
4051 interp_param = LLVMBuildBitCast(ctx->builder,
4052 interp_param, ctx->ac.v2f32, "");
4053 LLVMValueRef i = LLVMBuildExtractElement(
4054 ctx->builder, interp_param, ctx->ac.i32_0, "");
4055 LLVMValueRef j = LLVMBuildExtractElement(
4056 ctx->builder, interp_param, ctx->ac.i32_1, "");
4057
4058 result[chan] = ac_build_fs_interp(&ctx->ac,
4059 llvm_chan, attr_number,
4060 ctx->prim_mask, i, j);
4061 } else {
4062 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4063 LLVMConstInt(ctx->ac.i32, 2, false),
4064 llvm_chan, attr_number,
4065 ctx->prim_mask);
4066 }
4067 }
4068 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4069 instr->variables[0]->var->data.location_frac);
4070 }
4071
4072 static void
4073 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4074 {
4075 LLVMValueRef gs_next_vertex;
4076 LLVMValueRef can_emit;
4077 int idx;
4078 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4079
4080 /* Write vertex attribute values to GSVS ring */
4081 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4082 ctx->gs_next_vertex,
4083 "");
4084
4085 /* If this thread has already emitted the declared maximum number of
4086 * vertices, kill it: excessive vertex emissions are not supposed to
4087 * have any effect, and GS threads have no externally observable
4088 * effects other than emitting vertices.
4089 */
4090 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4091 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4092 ac_build_kill_if_false(&ctx->ac, can_emit);
4093
4094 /* loop num outputs */
4095 idx = 0;
4096 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4097 LLVMValueRef *out_ptr = &addrs[i * 4];
4098 int length = 4;
4099 int slot = idx;
4100 int slot_inc = 1;
4101
4102 if (!(ctx->output_mask & (1ull << i)))
4103 continue;
4104
4105 if (i == VARYING_SLOT_CLIP_DIST0) {
4106 /* pack clip and cull into a single set of slots */
4107 length = ctx->num_output_clips + ctx->num_output_culls;
4108 if (length > 4)
4109 slot_inc = 2;
4110 }
4111 for (unsigned j = 0; j < length; j++) {
4112 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4113 out_ptr[j], "");
4114 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4115 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4116 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4117
4118 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4119
4120 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4121 out_val, 1,
4122 voffset, ctx->gs2vs_offset, 0,
4123 1, 1, true, true);
4124 }
4125 idx += slot_inc;
4126 }
4127
4128 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4129 ctx->ac.i32_1, "");
4130 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4131
4132 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4133 }
4134
4135 static void
4136 visit_end_primitive(struct nir_to_llvm_context *ctx,
4137 const nir_intrinsic_instr *instr)
4138 {
4139 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4140 }
4141
4142 static LLVMValueRef
4143 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4144 const nir_intrinsic_instr *instr)
4145 {
4146 LLVMValueRef coord[4] = {
4147 ctx->tes_u,
4148 ctx->tes_v,
4149 ctx->ac.f32_0,
4150 ctx->ac.f32_0,
4151 };
4152
4153 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4154 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4155 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4156
4157 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4158 return LLVMBuildBitCast(ctx->builder, result,
4159 get_def_type(ctx->nir, &instr->dest.ssa), "");
4160 }
4161
4162 static void visit_intrinsic(struct ac_nir_context *ctx,
4163 nir_intrinsic_instr *instr)
4164 {
4165 LLVMValueRef result = NULL;
4166
4167 switch (instr->intrinsic) {
4168 case nir_intrinsic_load_work_group_id: {
4169 LLVMValueRef values[3];
4170
4171 for (int i = 0; i < 3; i++) {
4172 values[i] = ctx->nctx->workgroup_ids[i] ?
4173 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4174 }
4175
4176 result = ac_build_gather_values(&ctx->ac, values, 3);
4177 break;
4178 }
4179 case nir_intrinsic_load_base_vertex: {
4180 result = ctx->abi->base_vertex;
4181 break;
4182 }
4183 case nir_intrinsic_load_vertex_id_zero_base: {
4184 result = ctx->abi->vertex_id;
4185 break;
4186 }
4187 case nir_intrinsic_load_local_invocation_id: {
4188 result = ctx->nctx->local_invocation_ids;
4189 break;
4190 }
4191 case nir_intrinsic_load_base_instance:
4192 result = ctx->abi->start_instance;
4193 break;
4194 case nir_intrinsic_load_draw_id:
4195 result = ctx->abi->draw_id;
4196 break;
4197 case nir_intrinsic_load_view_index:
4198 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4199 break;
4200 case nir_intrinsic_load_invocation_id:
4201 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4202 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4203 else
4204 result = ctx->abi->gs_invocation_id;
4205 break;
4206 case nir_intrinsic_load_primitive_id:
4207 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4208 if (ctx->nctx)
4209 ctx->nctx->shader_info->gs.uses_prim_id = true;
4210 result = ctx->abi->gs_prim_id;
4211 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4212 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4213 result = ctx->nctx->tcs_patch_id;
4214 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4215 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4216 result = ctx->nctx->tes_patch_id;
4217 } else
4218 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4219 break;
4220 case nir_intrinsic_load_sample_id:
4221 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4222 break;
4223 case nir_intrinsic_load_sample_pos:
4224 result = load_sample_pos(ctx);
4225 break;
4226 case nir_intrinsic_load_sample_mask_in:
4227 result = ctx->abi->sample_coverage;
4228 break;
4229 case nir_intrinsic_load_frag_coord: {
4230 LLVMValueRef values[4] = {
4231 ctx->abi->frag_pos[0],
4232 ctx->abi->frag_pos[1],
4233 ctx->abi->frag_pos[2],
4234 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4235 };
4236 result = ac_build_gather_values(&ctx->ac, values, 4);
4237 break;
4238 }
4239 case nir_intrinsic_load_front_face:
4240 result = ctx->abi->front_face;
4241 break;
4242 case nir_intrinsic_load_instance_id:
4243 result = ctx->abi->instance_id;
4244 break;
4245 case nir_intrinsic_load_num_work_groups:
4246 result = ctx->nctx->num_work_groups;
4247 break;
4248 case nir_intrinsic_load_local_invocation_index:
4249 result = visit_load_local_invocation_index(ctx->nctx);
4250 break;
4251 case nir_intrinsic_load_push_constant:
4252 result = visit_load_push_constant(ctx->nctx, instr);
4253 break;
4254 case nir_intrinsic_vulkan_resource_index:
4255 result = visit_vulkan_resource_index(ctx->nctx, instr);
4256 break;
4257 case nir_intrinsic_vulkan_resource_reindex:
4258 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4259 break;
4260 case nir_intrinsic_store_ssbo:
4261 visit_store_ssbo(ctx, instr);
4262 break;
4263 case nir_intrinsic_load_ssbo:
4264 result = visit_load_buffer(ctx, instr);
4265 break;
4266 case nir_intrinsic_ssbo_atomic_add:
4267 case nir_intrinsic_ssbo_atomic_imin:
4268 case nir_intrinsic_ssbo_atomic_umin:
4269 case nir_intrinsic_ssbo_atomic_imax:
4270 case nir_intrinsic_ssbo_atomic_umax:
4271 case nir_intrinsic_ssbo_atomic_and:
4272 case nir_intrinsic_ssbo_atomic_or:
4273 case nir_intrinsic_ssbo_atomic_xor:
4274 case nir_intrinsic_ssbo_atomic_exchange:
4275 case nir_intrinsic_ssbo_atomic_comp_swap:
4276 result = visit_atomic_ssbo(ctx, instr);
4277 break;
4278 case nir_intrinsic_load_ubo:
4279 result = visit_load_ubo_buffer(ctx, instr);
4280 break;
4281 case nir_intrinsic_get_buffer_size:
4282 result = visit_get_buffer_size(ctx, instr);
4283 break;
4284 case nir_intrinsic_load_var:
4285 result = visit_load_var(ctx, instr);
4286 break;
4287 case nir_intrinsic_store_var:
4288 visit_store_var(ctx, instr);
4289 break;
4290 case nir_intrinsic_image_load:
4291 result = visit_image_load(ctx, instr);
4292 break;
4293 case nir_intrinsic_image_store:
4294 visit_image_store(ctx, instr);
4295 break;
4296 case nir_intrinsic_image_atomic_add:
4297 case nir_intrinsic_image_atomic_min:
4298 case nir_intrinsic_image_atomic_max:
4299 case nir_intrinsic_image_atomic_and:
4300 case nir_intrinsic_image_atomic_or:
4301 case nir_intrinsic_image_atomic_xor:
4302 case nir_intrinsic_image_atomic_exchange:
4303 case nir_intrinsic_image_atomic_comp_swap:
4304 result = visit_image_atomic(ctx, instr);
4305 break;
4306 case nir_intrinsic_image_size:
4307 result = visit_image_size(ctx, instr);
4308 break;
4309 case nir_intrinsic_discard:
4310 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4311 LLVMVoidTypeInContext(ctx->ac.context),
4312 NULL, 0, AC_FUNC_ATTR_LEGACY);
4313 break;
4314 case nir_intrinsic_discard_if:
4315 emit_discard_if(ctx, instr);
4316 break;
4317 case nir_intrinsic_memory_barrier:
4318 case nir_intrinsic_group_memory_barrier:
4319 case nir_intrinsic_memory_barrier_atomic_counter:
4320 case nir_intrinsic_memory_barrier_buffer:
4321 case nir_intrinsic_memory_barrier_image:
4322 case nir_intrinsic_memory_barrier_shared:
4323 emit_membar(ctx->nctx, instr);
4324 break;
4325 case nir_intrinsic_barrier:
4326 emit_barrier(ctx->nctx);
4327 break;
4328 case nir_intrinsic_var_atomic_add:
4329 case nir_intrinsic_var_atomic_imin:
4330 case nir_intrinsic_var_atomic_umin:
4331 case nir_intrinsic_var_atomic_imax:
4332 case nir_intrinsic_var_atomic_umax:
4333 case nir_intrinsic_var_atomic_and:
4334 case nir_intrinsic_var_atomic_or:
4335 case nir_intrinsic_var_atomic_xor:
4336 case nir_intrinsic_var_atomic_exchange:
4337 case nir_intrinsic_var_atomic_comp_swap:
4338 result = visit_var_atomic(ctx->nctx, instr);
4339 break;
4340 case nir_intrinsic_interp_var_at_centroid:
4341 case nir_intrinsic_interp_var_at_sample:
4342 case nir_intrinsic_interp_var_at_offset:
4343 result = visit_interp(ctx->nctx, instr);
4344 break;
4345 case nir_intrinsic_emit_vertex:
4346 assert(instr->const_index[0] == 0);
4347 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4348 break;
4349 case nir_intrinsic_end_primitive:
4350 visit_end_primitive(ctx->nctx, instr);
4351 break;
4352 case nir_intrinsic_load_tess_coord:
4353 result = visit_load_tess_coord(ctx->nctx, instr);
4354 break;
4355 case nir_intrinsic_load_patch_vertices_in:
4356 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4357 break;
4358 default:
4359 fprintf(stderr, "Unknown intrinsic: ");
4360 nir_print_instr(&instr->instr, stderr);
4361 fprintf(stderr, "\n");
4362 break;
4363 }
4364 if (result) {
4365 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4366 }
4367 }
4368
4369 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4370 LLVMValueRef buffer_ptr, bool write)
4371 {
4372 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4373
4374 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4375 ctx->shader_info->fs.writes_memory = true;
4376
4377 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4378 }
4379
4380 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4381 {
4382 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4383
4384 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4385 }
4386
4387 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4388 unsigned descriptor_set,
4389 unsigned base_index,
4390 unsigned constant_index,
4391 LLVMValueRef index,
4392 enum ac_descriptor_type desc_type,
4393 bool image, bool write)
4394 {
4395 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4396 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4397 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4398 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4399 unsigned offset = binding->offset;
4400 unsigned stride = binding->size;
4401 unsigned type_size;
4402 LLVMBuilderRef builder = ctx->builder;
4403 LLVMTypeRef type;
4404
4405 assert(base_index < layout->binding_count);
4406
4407 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4408 ctx->shader_info->fs.writes_memory = true;
4409
4410 switch (desc_type) {
4411 case AC_DESC_IMAGE:
4412 type = ctx->ac.v8i32;
4413 type_size = 32;
4414 break;
4415 case AC_DESC_FMASK:
4416 type = ctx->ac.v8i32;
4417 offset += 32;
4418 type_size = 32;
4419 break;
4420 case AC_DESC_SAMPLER:
4421 type = ctx->ac.v4i32;
4422 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4423 offset += 64;
4424
4425 type_size = 16;
4426 break;
4427 case AC_DESC_BUFFER:
4428 type = ctx->ac.v4i32;
4429 type_size = 16;
4430 break;
4431 default:
4432 unreachable("invalid desc_type\n");
4433 }
4434
4435 offset += constant_index * stride;
4436
4437 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4438 (!index || binding->immutable_samplers_equal)) {
4439 if (binding->immutable_samplers_equal)
4440 constant_index = 0;
4441
4442 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4443
4444 LLVMValueRef constants[] = {
4445 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4446 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4447 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4448 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4449 };
4450 return ac_build_gather_values(&ctx->ac, constants, 4);
4451 }
4452
4453 assert(stride % type_size == 0);
4454
4455 if (!index)
4456 index = ctx->ac.i32_0;
4457
4458 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4459
4460 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4461 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4462
4463 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4464 }
4465
4466 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4467 const nir_deref_var *deref,
4468 enum ac_descriptor_type desc_type,
4469 const nir_tex_instr *tex_instr,
4470 bool image, bool write)
4471 {
4472 LLVMValueRef index = NULL;
4473 unsigned constant_index = 0;
4474 unsigned descriptor_set;
4475 unsigned base_index;
4476
4477 if (!deref) {
4478 assert(tex_instr && !image);
4479 descriptor_set = 0;
4480 base_index = tex_instr->sampler_index;
4481 } else {
4482 const nir_deref *tail = &deref->deref;
4483 while (tail->child) {
4484 const nir_deref_array *child = nir_deref_as_array(tail->child);
4485 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4486
4487 if (!array_size)
4488 array_size = 1;
4489
4490 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4491
4492 if (child->deref_array_type == nir_deref_array_type_indirect) {
4493 LLVMValueRef indirect = get_src(ctx, child->indirect);
4494
4495 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4496 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4497
4498 if (!index)
4499 index = indirect;
4500 else
4501 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4502 }
4503
4504 constant_index += child->base_offset * array_size;
4505
4506 tail = &child->deref;
4507 }
4508 descriptor_set = deref->var->data.descriptor_set;
4509 base_index = deref->var->data.binding;
4510 }
4511
4512 return ctx->abi->load_sampler_desc(ctx->abi,
4513 descriptor_set,
4514 base_index,
4515 constant_index, index,
4516 desc_type, image, write);
4517 }
4518
4519 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4520 struct ac_image_args *args,
4521 const nir_tex_instr *instr,
4522 nir_texop op,
4523 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4524 LLVMValueRef *param, unsigned count,
4525 unsigned dmask)
4526 {
4527 unsigned is_rect = 0;
4528 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4529
4530 if (op == nir_texop_lod)
4531 da = false;
4532 /* Pad to power of two vector */
4533 while (count < util_next_power_of_two(count))
4534 param[count++] = LLVMGetUndef(ctx->i32);
4535
4536 if (count > 1)
4537 args->addr = ac_build_gather_values(ctx, param, count);
4538 else
4539 args->addr = param[0];
4540
4541 args->resource = res_ptr;
4542 args->sampler = samp_ptr;
4543
4544 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4545 args->addr = param[0];
4546 return;
4547 }
4548
4549 args->dmask = dmask;
4550 args->unorm = is_rect;
4551 args->da = da;
4552 }
4553
4554 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4555 *
4556 * SI-CI:
4557 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4558 * filtering manually. The driver sets img7 to a mask clearing
4559 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4560 * s_and_b32 samp0, samp0, img7
4561 *
4562 * VI:
4563 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4564 */
4565 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4566 LLVMValueRef res, LLVMValueRef samp)
4567 {
4568 LLVMBuilderRef builder = ctx->ac.builder;
4569 LLVMValueRef img7, samp0;
4570
4571 if (ctx->ac.chip_class >= VI)
4572 return samp;
4573
4574 img7 = LLVMBuildExtractElement(builder, res,
4575 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4576 samp0 = LLVMBuildExtractElement(builder, samp,
4577 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4578 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4579 return LLVMBuildInsertElement(builder, samp, samp0,
4580 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4581 }
4582
4583 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4584 nir_tex_instr *instr,
4585 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4586 LLVMValueRef *fmask_ptr)
4587 {
4588 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4589 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4590 else
4591 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4592 if (samp_ptr) {
4593 if (instr->sampler)
4594 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4595 else
4596 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4597 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4598 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4599 }
4600 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4601 instr->op == nir_texop_samples_identical))
4602 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4603 }
4604
4605 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4606 LLVMValueRef coord)
4607 {
4608 coord = ac_to_float(ctx, coord);
4609 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4610 coord = ac_to_integer(ctx, coord);
4611 return coord;
4612 }
4613
4614 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4615 {
4616 LLVMValueRef result = NULL;
4617 struct ac_image_args args = { 0 };
4618 unsigned dmask = 0xf;
4619 LLVMValueRef address[16];
4620 LLVMValueRef coords[5];
4621 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4622 LLVMValueRef bias = NULL, offsets = NULL;
4623 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4624 LLVMValueRef ddx = NULL, ddy = NULL;
4625 LLVMValueRef derivs[6];
4626 unsigned chan, count = 0;
4627 unsigned const_src = 0, num_deriv_comp = 0;
4628 bool lod_is_zero = false;
4629
4630 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4631
4632 for (unsigned i = 0; i < instr->num_srcs; i++) {
4633 switch (instr->src[i].src_type) {
4634 case nir_tex_src_coord:
4635 coord = get_src(ctx, instr->src[i].src);
4636 break;
4637 case nir_tex_src_projector:
4638 break;
4639 case nir_tex_src_comparator:
4640 comparator = get_src(ctx, instr->src[i].src);
4641 break;
4642 case nir_tex_src_offset:
4643 offsets = get_src(ctx, instr->src[i].src);
4644 const_src = i;
4645 break;
4646 case nir_tex_src_bias:
4647 bias = get_src(ctx, instr->src[i].src);
4648 break;
4649 case nir_tex_src_lod: {
4650 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4651
4652 if (val && val->i32[0] == 0)
4653 lod_is_zero = true;
4654 lod = get_src(ctx, instr->src[i].src);
4655 break;
4656 }
4657 case nir_tex_src_ms_index:
4658 sample_index = get_src(ctx, instr->src[i].src);
4659 break;
4660 case nir_tex_src_ms_mcs:
4661 break;
4662 case nir_tex_src_ddx:
4663 ddx = get_src(ctx, instr->src[i].src);
4664 num_deriv_comp = instr->src[i].src.ssa->num_components;
4665 break;
4666 case nir_tex_src_ddy:
4667 ddy = get_src(ctx, instr->src[i].src);
4668 break;
4669 case nir_tex_src_texture_offset:
4670 case nir_tex_src_sampler_offset:
4671 case nir_tex_src_plane:
4672 default:
4673 break;
4674 }
4675 }
4676
4677 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4678 result = get_buffer_size(ctx, res_ptr, true);
4679 goto write_result;
4680 }
4681
4682 if (instr->op == nir_texop_texture_samples) {
4683 LLVMValueRef res, samples, is_msaa;
4684 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4685 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4686 LLVMConstInt(ctx->ac.i32, 3, false), "");
4687 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4688 LLVMConstInt(ctx->ac.i32, 28, false), "");
4689 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4690 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4691 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4692 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4693
4694 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4695 LLVMConstInt(ctx->ac.i32, 16, false), "");
4696 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4697 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4698 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4699 samples, "");
4700 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4701 ctx->ac.i32_1, "");
4702 result = samples;
4703 goto write_result;
4704 }
4705
4706 if (coord)
4707 for (chan = 0; chan < instr->coord_components; chan++)
4708 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4709
4710 if (offsets && instr->op != nir_texop_txf) {
4711 LLVMValueRef offset[3], pack;
4712 for (chan = 0; chan < 3; ++chan)
4713 offset[chan] = ctx->ac.i32_0;
4714
4715 args.offset = true;
4716 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4717 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4718 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4719 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4720 if (chan)
4721 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4722 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4723 }
4724 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4725 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4726 address[count++] = pack;
4727
4728 }
4729 /* pack LOD bias value */
4730 if (instr->op == nir_texop_txb && bias) {
4731 address[count++] = bias;
4732 }
4733
4734 /* Pack depth comparison value */
4735 if (instr->is_shadow && comparator) {
4736 LLVMValueRef z = ac_to_float(&ctx->ac,
4737 llvm_extract_elem(&ctx->ac, comparator, 0));
4738
4739 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4740 * so the depth comparison value isn't clamped for Z16 and
4741 * Z24 anymore. Do it manually here.
4742 *
4743 * It's unnecessary if the original texture format was
4744 * Z32_FLOAT, but we don't know that here.
4745 */
4746 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4747 z = ac_build_clamp(&ctx->ac, z);
4748
4749 address[count++] = z;
4750 }
4751
4752 /* pack derivatives */
4753 if (ddx || ddy) {
4754 int num_src_deriv_channels, num_dest_deriv_channels;
4755 switch (instr->sampler_dim) {
4756 case GLSL_SAMPLER_DIM_3D:
4757 case GLSL_SAMPLER_DIM_CUBE:
4758 num_deriv_comp = 3;
4759 num_src_deriv_channels = 3;
4760 num_dest_deriv_channels = 3;
4761 break;
4762 case GLSL_SAMPLER_DIM_2D:
4763 default:
4764 num_src_deriv_channels = 2;
4765 num_dest_deriv_channels = 2;
4766 num_deriv_comp = 2;
4767 break;
4768 case GLSL_SAMPLER_DIM_1D:
4769 num_src_deriv_channels = 1;
4770 if (ctx->ac.chip_class >= GFX9) {
4771 num_dest_deriv_channels = 2;
4772 num_deriv_comp = 2;
4773 } else {
4774 num_dest_deriv_channels = 1;
4775 num_deriv_comp = 1;
4776 }
4777 break;
4778 }
4779
4780 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4781 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4782 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4783 }
4784 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4785 derivs[i] = ctx->ac.f32_0;
4786 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4787 }
4788 }
4789
4790 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4791 for (chan = 0; chan < instr->coord_components; chan++)
4792 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4793 if (instr->coord_components == 3)
4794 coords[3] = LLVMGetUndef(ctx->ac.f32);
4795 ac_prepare_cube_coords(&ctx->ac,
4796 instr->op == nir_texop_txd, instr->is_array,
4797 instr->op == nir_texop_lod, coords, derivs);
4798 if (num_deriv_comp)
4799 num_deriv_comp--;
4800 }
4801
4802 if (ddx || ddy) {
4803 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4804 address[count++] = derivs[i];
4805 }
4806
4807 /* Pack texture coordinates */
4808 if (coord) {
4809 address[count++] = coords[0];
4810 if (instr->coord_components > 1) {
4811 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4812 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4813 }
4814 address[count++] = coords[1];
4815 }
4816 if (instr->coord_components > 2) {
4817 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4818 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4819 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4820 instr->op != nir_texop_txf) {
4821 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4822 }
4823 address[count++] = coords[2];
4824 }
4825
4826 if (ctx->ac.chip_class >= GFX9) {
4827 LLVMValueRef filler;
4828 if (instr->op == nir_texop_txf)
4829 filler = ctx->ac.i32_0;
4830 else
4831 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4832
4833 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4834 /* No nir_texop_lod, because it does not take a slice
4835 * even with array textures. */
4836 if (instr->is_array && instr->op != nir_texop_lod ) {
4837 address[count] = address[count - 1];
4838 address[count - 1] = filler;
4839 count++;
4840 } else
4841 address[count++] = filler;
4842 }
4843 }
4844 }
4845
4846 /* Pack LOD */
4847 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4848 instr->op == nir_texop_txf)) {
4849 address[count++] = lod;
4850 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4851 address[count++] = sample_index;
4852 } else if(instr->op == nir_texop_txs) {
4853 count = 0;
4854 if (lod)
4855 address[count++] = lod;
4856 else
4857 address[count++] = ctx->ac.i32_0;
4858 }
4859
4860 for (chan = 0; chan < count; chan++) {
4861 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4862 address[chan], ctx->ac.i32, "");
4863 }
4864
4865 if (instr->op == nir_texop_samples_identical) {
4866 LLVMValueRef txf_address[4];
4867 struct ac_image_args txf_args = { 0 };
4868 unsigned txf_count = count;
4869 memcpy(txf_address, address, sizeof(txf_address));
4870
4871 if (!instr->is_array)
4872 txf_address[2] = ctx->ac.i32_0;
4873 txf_address[3] = ctx->ac.i32_0;
4874
4875 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4876 fmask_ptr, NULL,
4877 txf_address, txf_count, 0xf);
4878
4879 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4880
4881 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4882 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4883 goto write_result;
4884 }
4885
4886 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4887 instr->op != nir_texop_txs) {
4888 unsigned sample_chan = instr->is_array ? 3 : 2;
4889 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4890 address[0],
4891 address[1],
4892 instr->is_array ? address[2] : NULL,
4893 address[sample_chan],
4894 fmask_ptr);
4895 }
4896
4897 if (offsets && instr->op == nir_texop_txf) {
4898 nir_const_value *const_offset =
4899 nir_src_as_const_value(instr->src[const_src].src);
4900 int num_offsets = instr->src[const_src].src.ssa->num_components;
4901 assert(const_offset);
4902 num_offsets = MIN2(num_offsets, instr->coord_components);
4903 if (num_offsets > 2)
4904 address[2] = LLVMBuildAdd(ctx->ac.builder,
4905 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4906 if (num_offsets > 1)
4907 address[1] = LLVMBuildAdd(ctx->ac.builder,
4908 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4909 address[0] = LLVMBuildAdd(ctx->ac.builder,
4910 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4911
4912 }
4913
4914 /* TODO TG4 support */
4915 if (instr->op == nir_texop_tg4) {
4916 if (instr->is_shadow)
4917 dmask = 1;
4918 else
4919 dmask = 1 << instr->component;
4920 }
4921 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4922 res_ptr, samp_ptr, address, count, dmask);
4923
4924 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4925
4926 if (instr->op == nir_texop_query_levels)
4927 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4928 else if (instr->is_shadow && instr->is_new_style_shadow &&
4929 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4930 instr->op != nir_texop_tg4)
4931 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4932 else if (instr->op == nir_texop_txs &&
4933 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4934 instr->is_array) {
4935 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4936 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4937 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4938 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4939 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4940 } else if (ctx->ac.chip_class >= GFX9 &&
4941 instr->op == nir_texop_txs &&
4942 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4943 instr->is_array) {
4944 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4945 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4946 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4947 ctx->ac.i32_1, "");
4948 } else if (instr->dest.ssa.num_components != 4)
4949 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4950
4951 write_result:
4952 if (result) {
4953 assert(instr->dest.is_ssa);
4954 result = ac_to_integer(&ctx->ac, result);
4955 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4956 }
4957 }
4958
4959
4960 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4961 {
4962 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4963 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4964
4965 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4966 _mesa_hash_table_insert(ctx->phis, instr, result);
4967 }
4968
4969 static void visit_post_phi(struct ac_nir_context *ctx,
4970 nir_phi_instr *instr,
4971 LLVMValueRef llvm_phi)
4972 {
4973 nir_foreach_phi_src(src, instr) {
4974 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4975 LLVMValueRef llvm_src = get_src(ctx, src->src);
4976
4977 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4978 }
4979 }
4980
4981 static void phi_post_pass(struct ac_nir_context *ctx)
4982 {
4983 struct hash_entry *entry;
4984 hash_table_foreach(ctx->phis, entry) {
4985 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4986 (LLVMValueRef)entry->data);
4987 }
4988 }
4989
4990
4991 static void visit_ssa_undef(struct ac_nir_context *ctx,
4992 const nir_ssa_undef_instr *instr)
4993 {
4994 unsigned num_components = instr->def.num_components;
4995 LLVMValueRef undef;
4996
4997 if (num_components == 1)
4998 undef = LLVMGetUndef(ctx->ac.i32);
4999 else {
5000 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
5001 }
5002 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5003 }
5004
5005 static void visit_jump(struct ac_nir_context *ctx,
5006 const nir_jump_instr *instr)
5007 {
5008 switch (instr->type) {
5009 case nir_jump_break:
5010 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5011 LLVMClearInsertionPosition(ctx->ac.builder);
5012 break;
5013 case nir_jump_continue:
5014 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5015 LLVMClearInsertionPosition(ctx->ac.builder);
5016 break;
5017 default:
5018 fprintf(stderr, "Unknown NIR jump instr: ");
5019 nir_print_instr(&instr->instr, stderr);
5020 fprintf(stderr, "\n");
5021 abort();
5022 }
5023 }
5024
5025 static void visit_cf_list(struct ac_nir_context *ctx,
5026 struct exec_list *list);
5027
5028 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5029 {
5030 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5031 nir_foreach_instr(instr, block)
5032 {
5033 switch (instr->type) {
5034 case nir_instr_type_alu:
5035 visit_alu(ctx, nir_instr_as_alu(instr));
5036 break;
5037 case nir_instr_type_load_const:
5038 visit_load_const(ctx, nir_instr_as_load_const(instr));
5039 break;
5040 case nir_instr_type_intrinsic:
5041 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5042 break;
5043 case nir_instr_type_tex:
5044 visit_tex(ctx, nir_instr_as_tex(instr));
5045 break;
5046 case nir_instr_type_phi:
5047 visit_phi(ctx, nir_instr_as_phi(instr));
5048 break;
5049 case nir_instr_type_ssa_undef:
5050 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5051 break;
5052 case nir_instr_type_jump:
5053 visit_jump(ctx, nir_instr_as_jump(instr));
5054 break;
5055 default:
5056 fprintf(stderr, "Unknown NIR instr type: ");
5057 nir_print_instr(instr, stderr);
5058 fprintf(stderr, "\n");
5059 abort();
5060 }
5061 }
5062
5063 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5064 }
5065
5066 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5067 {
5068 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5069
5070 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5071 LLVMBasicBlockRef merge_block =
5072 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5073 LLVMBasicBlockRef if_block =
5074 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5075 LLVMBasicBlockRef else_block = merge_block;
5076 if (!exec_list_is_empty(&if_stmt->else_list))
5077 else_block = LLVMAppendBasicBlockInContext(
5078 ctx->ac.context, fn, "");
5079
5080 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5081 ctx->ac.i32_0, "");
5082 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5083
5084 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5085 visit_cf_list(ctx, &if_stmt->then_list);
5086 if (LLVMGetInsertBlock(ctx->ac.builder))
5087 LLVMBuildBr(ctx->ac.builder, merge_block);
5088
5089 if (!exec_list_is_empty(&if_stmt->else_list)) {
5090 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5091 visit_cf_list(ctx, &if_stmt->else_list);
5092 if (LLVMGetInsertBlock(ctx->ac.builder))
5093 LLVMBuildBr(ctx->ac.builder, merge_block);
5094 }
5095
5096 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5097 }
5098
5099 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5100 {
5101 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5102 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5103 LLVMBasicBlockRef break_parent = ctx->break_block;
5104
5105 ctx->continue_block =
5106 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5107 ctx->break_block =
5108 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5109
5110 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5111 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5112 visit_cf_list(ctx, &loop->body);
5113
5114 if (LLVMGetInsertBlock(ctx->ac.builder))
5115 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5116 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5117
5118 ctx->continue_block = continue_parent;
5119 ctx->break_block = break_parent;
5120 }
5121
5122 static void visit_cf_list(struct ac_nir_context *ctx,
5123 struct exec_list *list)
5124 {
5125 foreach_list_typed(nir_cf_node, node, node, list)
5126 {
5127 switch (node->type) {
5128 case nir_cf_node_block:
5129 visit_block(ctx, nir_cf_node_as_block(node));
5130 break;
5131
5132 case nir_cf_node_if:
5133 visit_if(ctx, nir_cf_node_as_if(node));
5134 break;
5135
5136 case nir_cf_node_loop:
5137 visit_loop(ctx, nir_cf_node_as_loop(node));
5138 break;
5139
5140 default:
5141 assert(0);
5142 }
5143 }
5144 }
5145
5146 static void
5147 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5148 struct nir_variable *variable)
5149 {
5150 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5151 LLVMValueRef t_offset;
5152 LLVMValueRef t_list;
5153 LLVMValueRef input;
5154 LLVMValueRef buffer_index;
5155 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5156 int idx = variable->data.location;
5157 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5158
5159 variable->data.driver_location = idx * 4;
5160
5161 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5162 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5163 ctx->abi.start_instance, "");
5164 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5165 ctx->shader_info->vs.vgpr_comp_cnt);
5166 } else
5167 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5168 ctx->abi.base_vertex, "");
5169
5170 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5171 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5172
5173 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5174
5175 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5176 buffer_index,
5177 ctx->ac.i32_0,
5178 true);
5179
5180 for (unsigned chan = 0; chan < 4; chan++) {
5181 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5182 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5183 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5184 input, llvm_chan, ""));
5185 }
5186 }
5187 }
5188
5189 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5190 unsigned attr,
5191 LLVMValueRef interp_param,
5192 LLVMValueRef prim_mask,
5193 LLVMValueRef result[4])
5194 {
5195 LLVMValueRef attr_number;
5196 unsigned chan;
5197 LLVMValueRef i, j;
5198 bool interp = interp_param != NULL;
5199
5200 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5201
5202 /* fs.constant returns the param from the middle vertex, so it's not
5203 * really useful for flat shading. It's meant to be used for custom
5204 * interpolation (but the intrinsic can't fetch from the other two
5205 * vertices).
5206 *
5207 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5208 * to do the right thing. The only reason we use fs.constant is that
5209 * fs.interp cannot be used on integers, because they can be equal
5210 * to NaN.
5211 */
5212 if (interp) {
5213 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5214 ctx->ac.v2f32, "");
5215
5216 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5217 ctx->ac.i32_0, "");
5218 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5219 ctx->ac.i32_1, "");
5220 }
5221
5222 for (chan = 0; chan < 4; chan++) {
5223 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5224
5225 if (interp) {
5226 result[chan] = ac_build_fs_interp(&ctx->ac,
5227 llvm_chan,
5228 attr_number,
5229 prim_mask, i, j);
5230 } else {
5231 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5232 LLVMConstInt(ctx->ac.i32, 2, false),
5233 llvm_chan,
5234 attr_number,
5235 prim_mask);
5236 }
5237 }
5238 }
5239
5240 static void
5241 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5242 struct nir_variable *variable)
5243 {
5244 int idx = variable->data.location;
5245 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5246 LLVMValueRef interp;
5247
5248 variable->data.driver_location = idx * 4;
5249 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5250
5251 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5252 unsigned interp_type;
5253 if (variable->data.sample) {
5254 interp_type = INTERP_SAMPLE;
5255 ctx->shader_info->info.ps.force_persample = true;
5256 } else if (variable->data.centroid)
5257 interp_type = INTERP_CENTROID;
5258 else
5259 interp_type = INTERP_CENTER;
5260
5261 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5262 } else
5263 interp = NULL;
5264
5265 for (unsigned i = 0; i < attrib_count; ++i)
5266 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5267
5268 }
5269
5270 static void
5271 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5272 struct nir_shader *nir) {
5273 nir_foreach_variable(variable, &nir->inputs)
5274 handle_vs_input_decl(ctx, variable);
5275 }
5276
5277 static void
5278 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5279 struct nir_shader *nir)
5280 {
5281 if (!ctx->options->key.fs.multisample)
5282 return;
5283
5284 bool uses_center = false;
5285 bool uses_centroid = false;
5286 nir_foreach_variable(variable, &nir->inputs) {
5287 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5288 variable->data.sample)
5289 continue;
5290
5291 if (variable->data.centroid)
5292 uses_centroid = true;
5293 else
5294 uses_center = true;
5295 }
5296
5297 if (uses_center && uses_centroid) {
5298 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5299 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5300 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5301 }
5302 }
5303
5304 static void
5305 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5306 struct nir_shader *nir)
5307 {
5308 prepare_interp_optimize(ctx, nir);
5309
5310 nir_foreach_variable(variable, &nir->inputs)
5311 handle_fs_input_decl(ctx, variable);
5312
5313 unsigned index = 0;
5314
5315 if (ctx->shader_info->info.ps.uses_input_attachments ||
5316 ctx->shader_info->info.needs_multiview_view_index)
5317 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5318
5319 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5320 LLVMValueRef interp_param;
5321 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5322
5323 if (!(ctx->input_mask & (1ull << i)))
5324 continue;
5325
5326 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5327 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5328 interp_param = *inputs;
5329 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5330 inputs);
5331
5332 if (!interp_param)
5333 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5334 ++index;
5335 } else if (i == VARYING_SLOT_POS) {
5336 for(int i = 0; i < 3; ++i)
5337 inputs[i] = ctx->abi.frag_pos[i];
5338
5339 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5340 ctx->abi.frag_pos[3]);
5341 }
5342 }
5343 ctx->shader_info->fs.num_interp = index;
5344 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5345 ctx->shader_info->fs.has_pcoord = true;
5346 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5347 ctx->shader_info->fs.prim_id_input = true;
5348 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5349 ctx->shader_info->fs.layer_input = true;
5350 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5351
5352 if (ctx->shader_info->info.needs_multiview_view_index)
5353 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5354 }
5355
5356 static LLVMValueRef
5357 ac_build_alloca(struct ac_llvm_context *ac,
5358 LLVMTypeRef type,
5359 const char *name)
5360 {
5361 LLVMBuilderRef builder = ac->builder;
5362 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5363 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5364 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5365 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5366 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5367 LLVMValueRef res;
5368
5369 if (first_instr) {
5370 LLVMPositionBuilderBefore(first_builder, first_instr);
5371 } else {
5372 LLVMPositionBuilderAtEnd(first_builder, first_block);
5373 }
5374
5375 res = LLVMBuildAlloca(first_builder, type, name);
5376 LLVMBuildStore(builder, LLVMConstNull(type), res);
5377
5378 LLVMDisposeBuilder(first_builder);
5379
5380 return res;
5381 }
5382
5383 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5384 LLVMTypeRef type,
5385 const char *name)
5386 {
5387 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5388 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5389 return ptr;
5390 }
5391
5392 static void
5393 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5394 struct nir_variable *variable,
5395 struct nir_shader *shader,
5396 gl_shader_stage stage)
5397 {
5398 int idx = variable->data.location + variable->data.index;
5399 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5400 uint64_t mask_attribs;
5401
5402 variable->data.driver_location = idx * 4;
5403
5404 /* tess ctrl has it's own load/store paths for outputs */
5405 if (stage == MESA_SHADER_TESS_CTRL)
5406 return;
5407
5408 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5409 if (stage == MESA_SHADER_VERTEX ||
5410 stage == MESA_SHADER_TESS_EVAL ||
5411 stage == MESA_SHADER_GEOMETRY) {
5412 if (idx == VARYING_SLOT_CLIP_DIST0) {
5413 int length = shader->info.clip_distance_array_size +
5414 shader->info.cull_distance_array_size;
5415 if (stage == MESA_SHADER_VERTEX) {
5416 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5417 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5418 }
5419 if (stage == MESA_SHADER_TESS_EVAL) {
5420 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5421 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5422 }
5423
5424 if (length > 4)
5425 attrib_count = 2;
5426 else
5427 attrib_count = 1;
5428 mask_attribs = 1ull << idx;
5429 }
5430 }
5431
5432 ctx->output_mask |= mask_attribs;
5433 }
5434
5435 static void
5436 handle_shader_output_decl(struct ac_nir_context *ctx,
5437 struct nir_shader *nir,
5438 struct nir_variable *variable)
5439 {
5440 unsigned output_loc = variable->data.driver_location / 4;
5441 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5442
5443 /* tess ctrl has it's own load/store paths for outputs */
5444 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5445 return;
5446
5447 if (ctx->stage == MESA_SHADER_VERTEX ||
5448 ctx->stage == MESA_SHADER_TESS_EVAL ||
5449 ctx->stage == MESA_SHADER_GEOMETRY) {
5450 int idx = variable->data.location + variable->data.index;
5451 if (idx == VARYING_SLOT_CLIP_DIST0) {
5452 int length = nir->info.clip_distance_array_size +
5453 nir->info.cull_distance_array_size;
5454
5455 if (length > 4)
5456 attrib_count = 2;
5457 else
5458 attrib_count = 1;
5459 }
5460 }
5461
5462 for (unsigned i = 0; i < attrib_count; ++i) {
5463 for (unsigned chan = 0; chan < 4; chan++) {
5464 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5465 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5466 }
5467 }
5468 }
5469
5470 static LLVMTypeRef
5471 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5472 enum glsl_base_type type)
5473 {
5474 switch (type) {
5475 case GLSL_TYPE_INT:
5476 case GLSL_TYPE_UINT:
5477 case GLSL_TYPE_BOOL:
5478 case GLSL_TYPE_SUBROUTINE:
5479 return ctx->ac.i32;
5480 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5481 return ctx->ac.f32;
5482 case GLSL_TYPE_INT64:
5483 case GLSL_TYPE_UINT64:
5484 return ctx->ac.i64;
5485 case GLSL_TYPE_DOUBLE:
5486 return ctx->ac.f64;
5487 default:
5488 unreachable("unknown GLSL type");
5489 }
5490 }
5491
5492 static LLVMTypeRef
5493 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5494 const struct glsl_type *type)
5495 {
5496 if (glsl_type_is_scalar(type)) {
5497 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5498 }
5499
5500 if (glsl_type_is_vector(type)) {
5501 return LLVMVectorType(
5502 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5503 glsl_get_vector_elements(type));
5504 }
5505
5506 if (glsl_type_is_matrix(type)) {
5507 return LLVMArrayType(
5508 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5509 glsl_get_matrix_columns(type));
5510 }
5511
5512 if (glsl_type_is_array(type)) {
5513 return LLVMArrayType(
5514 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5515 glsl_get_length(type));
5516 }
5517
5518 assert(glsl_type_is_struct(type));
5519
5520 LLVMTypeRef member_types[glsl_get_length(type)];
5521
5522 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5523 member_types[i] =
5524 glsl_to_llvm_type(ctx,
5525 glsl_get_struct_field(type, i));
5526 }
5527
5528 return LLVMStructTypeInContext(ctx->context, member_types,
5529 glsl_get_length(type), false);
5530 }
5531
5532 static void
5533 setup_locals(struct ac_nir_context *ctx,
5534 struct nir_function *func)
5535 {
5536 int i, j;
5537 ctx->num_locals = 0;
5538 nir_foreach_variable(variable, &func->impl->locals) {
5539 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5540 variable->data.driver_location = ctx->num_locals * 4;
5541 ctx->num_locals += attrib_count;
5542 }
5543 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5544 if (!ctx->locals)
5545 return;
5546
5547 for (i = 0; i < ctx->num_locals; i++) {
5548 for (j = 0; j < 4; j++) {
5549 ctx->locals[i * 4 + j] =
5550 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5551 }
5552 }
5553 }
5554
5555 static void
5556 setup_shared(struct ac_nir_context *ctx,
5557 struct nir_shader *nir)
5558 {
5559 nir_foreach_variable(variable, &nir->shared) {
5560 LLVMValueRef shared =
5561 LLVMAddGlobalInAddressSpace(
5562 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5563 variable->name ? variable->name : "",
5564 LOCAL_ADDR_SPACE);
5565 _mesa_hash_table_insert(ctx->vars, variable, shared);
5566 }
5567 }
5568
5569 static LLVMValueRef
5570 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5571 {
5572 v = ac_to_float(ctx, v);
5573 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5574 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5575 }
5576
5577
5578 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5579 LLVMValueRef src0, LLVMValueRef src1)
5580 {
5581 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5582 LLVMValueRef comp[2];
5583
5584 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5585 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5586 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5587 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5588 }
5589
5590 /* Initialize arguments for the shader export intrinsic */
5591 static void
5592 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5593 LLVMValueRef *values,
5594 unsigned target,
5595 struct ac_export_args *args)
5596 {
5597 /* Default is 0xf. Adjusted below depending on the format. */
5598 args->enabled_channels = 0xf;
5599
5600 /* Specify whether the EXEC mask represents the valid mask */
5601 args->valid_mask = 0;
5602
5603 /* Specify whether this is the last export */
5604 args->done = 0;
5605
5606 /* Specify the target we are exporting */
5607 args->target = target;
5608
5609 args->compr = false;
5610 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5611 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5612 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5613 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5614
5615 if (!values)
5616 return;
5617
5618 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5619 LLVMValueRef val[4];
5620 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5621 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5622 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5623 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5624
5625 switch(col_format) {
5626 case V_028714_SPI_SHADER_ZERO:
5627 args->enabled_channels = 0; /* writemask */
5628 args->target = V_008DFC_SQ_EXP_NULL;
5629 break;
5630
5631 case V_028714_SPI_SHADER_32_R:
5632 args->enabled_channels = 1;
5633 args->out[0] = values[0];
5634 break;
5635
5636 case V_028714_SPI_SHADER_32_GR:
5637 args->enabled_channels = 0x3;
5638 args->out[0] = values[0];
5639 args->out[1] = values[1];
5640 break;
5641
5642 case V_028714_SPI_SHADER_32_AR:
5643 args->enabled_channels = 0x9;
5644 args->out[0] = values[0];
5645 args->out[3] = values[3];
5646 break;
5647
5648 case V_028714_SPI_SHADER_FP16_ABGR:
5649 args->compr = 1;
5650
5651 for (unsigned chan = 0; chan < 2; chan++) {
5652 LLVMValueRef pack_args[2] = {
5653 values[2 * chan],
5654 values[2 * chan + 1]
5655 };
5656 LLVMValueRef packed;
5657
5658 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5659 args->out[chan] = packed;
5660 }
5661 break;
5662
5663 case V_028714_SPI_SHADER_UNORM16_ABGR:
5664 for (unsigned chan = 0; chan < 4; chan++) {
5665 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5666 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5667 LLVMConstReal(ctx->ac.f32, 65535), "");
5668 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5669 LLVMConstReal(ctx->ac.f32, 0.5), "");
5670 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5671 ctx->ac.i32, "");
5672 }
5673
5674 args->compr = 1;
5675 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5676 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5677 break;
5678
5679 case V_028714_SPI_SHADER_SNORM16_ABGR:
5680 for (unsigned chan = 0; chan < 4; chan++) {
5681 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5682 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5683 LLVMConstReal(ctx->ac.f32, 32767), "");
5684
5685 /* If positive, add 0.5, else add -0.5. */
5686 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5687 LLVMBuildSelect(ctx->builder,
5688 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5689 val[chan], ctx->ac.f32_0, ""),
5690 LLVMConstReal(ctx->ac.f32, 0.5),
5691 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5692 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5693 }
5694
5695 args->compr = 1;
5696 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5697 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5698 break;
5699
5700 case V_028714_SPI_SHADER_UINT16_ABGR: {
5701 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5702 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5703 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5704
5705 for (unsigned chan = 0; chan < 4; chan++) {
5706 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5707 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5708 }
5709
5710 args->compr = 1;
5711 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5712 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5713 break;
5714 }
5715
5716 case V_028714_SPI_SHADER_SINT16_ABGR: {
5717 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5718 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5719 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5720 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5721 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5722 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5723
5724 /* Clamp. */
5725 for (unsigned chan = 0; chan < 4; chan++) {
5726 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5727 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5728 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5729 }
5730
5731 args->compr = 1;
5732 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5733 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5734 break;
5735 }
5736
5737 default:
5738 case V_028714_SPI_SHADER_32_ABGR:
5739 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5740 break;
5741 }
5742 } else
5743 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5744
5745 for (unsigned i = 0; i < 4; ++i)
5746 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5747 }
5748
5749 static void
5750 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5751 bool export_prim_id,
5752 struct ac_vs_output_info *outinfo)
5753 {
5754 uint32_t param_count = 0;
5755 unsigned target;
5756 unsigned pos_idx, num_pos_exports = 0;
5757 struct ac_export_args args, pos_args[4] = {};
5758 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5759 int i;
5760
5761 if (ctx->options->key.has_multiview_view_index) {
5762 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5763 if(!*tmp_out) {
5764 for(unsigned i = 0; i < 4; ++i)
5765 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5766 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5767 }
5768
5769 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5770 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5771 }
5772
5773 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5774 sizeof(outinfo->vs_output_param_offset));
5775
5776 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5777 LLVMValueRef slots[8];
5778 unsigned j;
5779
5780 if (outinfo->cull_dist_mask)
5781 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5782
5783 i = VARYING_SLOT_CLIP_DIST0;
5784 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5785 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5786 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5787
5788 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5789 slots[i] = LLVMGetUndef(ctx->ac.f32);
5790
5791 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5792 target = V_008DFC_SQ_EXP_POS + 3;
5793 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5794 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5795 &args, sizeof(args));
5796 }
5797
5798 target = V_008DFC_SQ_EXP_POS + 2;
5799 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5800 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5801 &args, sizeof(args));
5802
5803 }
5804
5805 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5806 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5807 for (unsigned j = 0; j < 4; j++)
5808 pos_values[j] = LLVMBuildLoad(ctx->builder,
5809 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5810 }
5811 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5812
5813 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5814 outinfo->writes_pointsize = true;
5815 psize_value = LLVMBuildLoad(ctx->builder,
5816 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5817 }
5818
5819 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5820 outinfo->writes_layer = true;
5821 layer_value = LLVMBuildLoad(ctx->builder,
5822 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5823 }
5824
5825 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5826 outinfo->writes_viewport_index = true;
5827 viewport_index_value = LLVMBuildLoad(ctx->builder,
5828 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5829 }
5830
5831 if (outinfo->writes_pointsize ||
5832 outinfo->writes_layer ||
5833 outinfo->writes_viewport_index) {
5834 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5835 (outinfo->writes_layer == true ? 4 : 0));
5836 pos_args[1].valid_mask = 0;
5837 pos_args[1].done = 0;
5838 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5839 pos_args[1].compr = 0;
5840 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5841 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5842 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5843 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5844
5845 if (outinfo->writes_pointsize == true)
5846 pos_args[1].out[0] = psize_value;
5847 if (outinfo->writes_layer == true)
5848 pos_args[1].out[2] = layer_value;
5849 if (outinfo->writes_viewport_index == true) {
5850 if (ctx->options->chip_class >= GFX9) {
5851 /* GFX9 has the layer in out.z[10:0] and the viewport
5852 * index in out.z[19:16].
5853 */
5854 LLVMValueRef v = viewport_index_value;
5855 v = ac_to_integer(&ctx->ac, v);
5856 v = LLVMBuildShl(ctx->builder, v,
5857 LLVMConstInt(ctx->ac.i32, 16, false),
5858 "");
5859 v = LLVMBuildOr(ctx->builder, v,
5860 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5861
5862 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5863 pos_args[1].enabled_channels |= 1 << 2;
5864 } else {
5865 pos_args[1].out[3] = viewport_index_value;
5866 pos_args[1].enabled_channels |= 1 << 3;
5867 }
5868 }
5869 }
5870 for (i = 0; i < 4; i++) {
5871 if (pos_args[i].out[0])
5872 num_pos_exports++;
5873 }
5874
5875 pos_idx = 0;
5876 for (i = 0; i < 4; i++) {
5877 if (!pos_args[i].out[0])
5878 continue;
5879
5880 /* Specify the target we are exporting */
5881 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5882 if (pos_idx == num_pos_exports)
5883 pos_args[i].done = 1;
5884 ac_build_export(&ctx->ac, &pos_args[i]);
5885 }
5886
5887 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5888 LLVMValueRef values[4];
5889 if (!(ctx->output_mask & (1ull << i)))
5890 continue;
5891
5892 for (unsigned j = 0; j < 4; j++)
5893 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5894 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5895
5896 if (i == VARYING_SLOT_LAYER) {
5897 target = V_008DFC_SQ_EXP_PARAM + param_count;
5898 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5899 param_count++;
5900 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5901 target = V_008DFC_SQ_EXP_PARAM + param_count;
5902 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5903 param_count++;
5904 } else if (i >= VARYING_SLOT_VAR0) {
5905 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5906 target = V_008DFC_SQ_EXP_PARAM + param_count;
5907 outinfo->vs_output_param_offset[i] = param_count;
5908 param_count++;
5909 } else
5910 continue;
5911
5912 si_llvm_init_export_args(ctx, values, target, &args);
5913
5914 if (target >= V_008DFC_SQ_EXP_POS &&
5915 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5916 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5917 &args, sizeof(args));
5918 } else {
5919 ac_build_export(&ctx->ac, &args);
5920 }
5921 }
5922
5923 if (export_prim_id) {
5924 LLVMValueRef values[4];
5925 target = V_008DFC_SQ_EXP_PARAM + param_count;
5926 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5927 param_count++;
5928
5929 values[0] = ctx->vs_prim_id;
5930 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5931 ctx->shader_info->vs.vgpr_comp_cnt);
5932 for (unsigned j = 1; j < 4; j++)
5933 values[j] = ctx->ac.f32_0;
5934 si_llvm_init_export_args(ctx, values, target, &args);
5935 ac_build_export(&ctx->ac, &args);
5936 outinfo->export_prim_id = true;
5937 }
5938
5939 outinfo->pos_exports = num_pos_exports;
5940 outinfo->param_exports = param_count;
5941 }
5942
5943 static void
5944 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5945 struct ac_es_output_info *outinfo)
5946 {
5947 int j;
5948 uint64_t max_output_written = 0;
5949 LLVMValueRef lds_base = NULL;
5950
5951 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5952 int param_index;
5953 int length = 4;
5954
5955 if (!(ctx->output_mask & (1ull << i)))
5956 continue;
5957
5958 if (i == VARYING_SLOT_CLIP_DIST0)
5959 length = ctx->num_output_clips + ctx->num_output_culls;
5960
5961 param_index = shader_io_get_unique_index(i);
5962
5963 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5964 }
5965
5966 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5967
5968 if (ctx->ac.chip_class >= GFX9) {
5969 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5970 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5971 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5972 LLVMConstInt(ctx->ac.i32, 24, false),
5973 LLVMConstInt(ctx->ac.i32, 4, false), false);
5974 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5975 LLVMBuildMul(ctx->ac.builder, wave_idx,
5976 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5977 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5978 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5979 }
5980
5981 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5982 LLVMValueRef dw_addr;
5983 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5984 int param_index;
5985 int length = 4;
5986
5987 if (!(ctx->output_mask & (1ull << i)))
5988 continue;
5989
5990 if (i == VARYING_SLOT_CLIP_DIST0)
5991 length = ctx->num_output_clips + ctx->num_output_culls;
5992
5993 param_index = shader_io_get_unique_index(i);
5994
5995 if (lds_base) {
5996 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5997 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
5998 "");
5999 }
6000 for (j = 0; j < length; j++) {
6001 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6002 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6003
6004 if (ctx->ac.chip_class >= GFX9) {
6005 ac_lds_store(&ctx->ac, dw_addr,
6006 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6007 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6008 } else {
6009 ac_build_buffer_store_dword(&ctx->ac,
6010 ctx->esgs_ring,
6011 out_val, 1,
6012 NULL, ctx->es2gs_offset,
6013 (4 * param_index + j) * 4,
6014 1, 1, true, true);
6015 }
6016 }
6017 }
6018 }
6019
6020 static void
6021 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6022 {
6023 LLVMValueRef vertex_id = ctx->rel_auto_id;
6024 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6025 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6026 vertex_dw_stride, "");
6027
6028 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6029 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6030 int length = 4;
6031
6032 if (!(ctx->output_mask & (1ull << i)))
6033 continue;
6034
6035 if (i == VARYING_SLOT_CLIP_DIST0)
6036 length = ctx->num_output_clips + ctx->num_output_culls;
6037 int param = shader_io_get_unique_index(i);
6038 mark_tess_output(ctx, false, param);
6039 if (length > 4)
6040 mark_tess_output(ctx, false, param + 1);
6041 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6042 LLVMConstInt(ctx->ac.i32, param * 4, false),
6043 "");
6044 for (unsigned j = 0; j < length; j++) {
6045 ac_lds_store(&ctx->ac, dw_addr,
6046 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6047 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6048 }
6049 }
6050 }
6051
6052 struct ac_build_if_state
6053 {
6054 struct nir_to_llvm_context *ctx;
6055 LLVMValueRef condition;
6056 LLVMBasicBlockRef entry_block;
6057 LLVMBasicBlockRef true_block;
6058 LLVMBasicBlockRef false_block;
6059 LLVMBasicBlockRef merge_block;
6060 };
6061
6062 static LLVMBasicBlockRef
6063 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6064 {
6065 LLVMBasicBlockRef current_block;
6066 LLVMBasicBlockRef next_block;
6067 LLVMBasicBlockRef new_block;
6068
6069 /* get current basic block */
6070 current_block = LLVMGetInsertBlock(ctx->builder);
6071
6072 /* chqeck if there's another block after this one */
6073 next_block = LLVMGetNextBasicBlock(current_block);
6074 if (next_block) {
6075 /* insert the new block before the next block */
6076 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6077 }
6078 else {
6079 /* append new block after current block */
6080 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6081 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6082 }
6083 return new_block;
6084 }
6085
6086 static void
6087 ac_nir_build_if(struct ac_build_if_state *ifthen,
6088 struct nir_to_llvm_context *ctx,
6089 LLVMValueRef condition)
6090 {
6091 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6092
6093 memset(ifthen, 0, sizeof *ifthen);
6094 ifthen->ctx = ctx;
6095 ifthen->condition = condition;
6096 ifthen->entry_block = block;
6097
6098 /* create endif/merge basic block for the phi functions */
6099 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6100
6101 /* create/insert true_block before merge_block */
6102 ifthen->true_block =
6103 LLVMInsertBasicBlockInContext(ctx->context,
6104 ifthen->merge_block,
6105 "if-true-block");
6106
6107 /* successive code goes into the true block */
6108 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6109 }
6110
6111 /**
6112 * End a conditional.
6113 */
6114 static void
6115 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6116 {
6117 LLVMBuilderRef builder = ifthen->ctx->builder;
6118
6119 /* Insert branch to the merge block from current block */
6120 LLVMBuildBr(builder, ifthen->merge_block);
6121
6122 /*
6123 * Now patch in the various branch instructions.
6124 */
6125
6126 /* Insert the conditional branch instruction at the end of entry_block */
6127 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6128 if (ifthen->false_block) {
6129 /* we have an else clause */
6130 LLVMBuildCondBr(builder, ifthen->condition,
6131 ifthen->true_block, ifthen->false_block);
6132 }
6133 else {
6134 /* no else clause */
6135 LLVMBuildCondBr(builder, ifthen->condition,
6136 ifthen->true_block, ifthen->merge_block);
6137 }
6138
6139 /* Resume building code at end of the ifthen->merge_block */
6140 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6141 }
6142
6143 static void
6144 write_tess_factors(struct nir_to_llvm_context *ctx)
6145 {
6146 unsigned stride, outer_comps, inner_comps;
6147 struct ac_build_if_state if_ctx, inner_if_ctx;
6148 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6149 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6150 unsigned tess_inner_index, tess_outer_index;
6151 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6152 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6153 int i;
6154 emit_barrier(ctx);
6155
6156 switch (ctx->options->key.tcs.primitive_mode) {
6157 case GL_ISOLINES:
6158 stride = 2;
6159 outer_comps = 2;
6160 inner_comps = 0;
6161 break;
6162 case GL_TRIANGLES:
6163 stride = 4;
6164 outer_comps = 3;
6165 inner_comps = 1;
6166 break;
6167 case GL_QUADS:
6168 stride = 6;
6169 outer_comps = 4;
6170 inner_comps = 2;
6171 break;
6172 default:
6173 return;
6174 }
6175
6176 ac_nir_build_if(&if_ctx, ctx,
6177 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6178 invocation_id, ctx->ac.i32_0, ""));
6179
6180 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6181 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6182
6183 mark_tess_output(ctx, true, tess_inner_index);
6184 mark_tess_output(ctx, true, tess_outer_index);
6185 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6186 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6187 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6188 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6189 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6190
6191 for (i = 0; i < 4; i++) {
6192 inner[i] = LLVMGetUndef(ctx->ac.i32);
6193 outer[i] = LLVMGetUndef(ctx->ac.i32);
6194 }
6195
6196 // LINES reverseal
6197 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6198 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6199 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6200 ctx->ac.i32_1, "");
6201 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6202 } else {
6203 for (i = 0; i < outer_comps; i++) {
6204 outer[i] = out[i] =
6205 ac_lds_load(&ctx->ac, lds_outer);
6206 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6207 ctx->ac.i32_1, "");
6208 }
6209 for (i = 0; i < inner_comps; i++) {
6210 inner[i] = out[outer_comps+i] =
6211 ac_lds_load(&ctx->ac, lds_inner);
6212 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6213 ctx->ac.i32_1, "");
6214 }
6215 }
6216
6217 /* Convert the outputs to vectors for stores. */
6218 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6219 vec1 = NULL;
6220
6221 if (stride > 4)
6222 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6223
6224
6225 buffer = ctx->hs_ring_tess_factor;
6226 tf_base = ctx->tess_factor_offset;
6227 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6228 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6229 unsigned tf_offset = 0;
6230
6231 if (ctx->options->chip_class <= VI) {
6232 ac_nir_build_if(&inner_if_ctx, ctx,
6233 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6234 rel_patch_id, ctx->ac.i32_0, ""));
6235
6236 /* Store the dynamic HS control word. */
6237 ac_build_buffer_store_dword(&ctx->ac, buffer,
6238 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6239 1, ctx->ac.i32_0, tf_base,
6240 0, 1, 0, true, false);
6241 tf_offset += 4;
6242
6243 ac_nir_build_endif(&inner_if_ctx);
6244 }
6245
6246 /* Store the tessellation factors. */
6247 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6248 MIN2(stride, 4), byteoffset, tf_base,
6249 tf_offset, 1, 0, true, false);
6250 if (vec1)
6251 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6252 stride - 4, byteoffset, tf_base,
6253 16 + tf_offset, 1, 0, true, false);
6254
6255 //store to offchip for TES to read - only if TES reads them
6256 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6257 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6258 LLVMValueRef tf_inner_offset;
6259 unsigned param_outer, param_inner;
6260
6261 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6262 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6263 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6264
6265 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6266 util_next_power_of_two(outer_comps));
6267
6268 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6269 outer_comps, tf_outer_offset,
6270 ctx->oc_lds, 0, 1, 0, true, false);
6271 if (inner_comps) {
6272 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6273 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6274 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6275
6276 inner_vec = inner_comps == 1 ? inner[0] :
6277 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6278 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6279 inner_comps, tf_inner_offset,
6280 ctx->oc_lds, 0, 1, 0, true, false);
6281 }
6282 }
6283 ac_nir_build_endif(&if_ctx);
6284 }
6285
6286 static void
6287 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6288 {
6289 write_tess_factors(ctx);
6290 }
6291
6292 static bool
6293 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6294 LLVMValueRef *color, unsigned param, bool is_last,
6295 struct ac_export_args *args)
6296 {
6297 /* Export */
6298 si_llvm_init_export_args(ctx, color, param,
6299 args);
6300
6301 if (is_last) {
6302 args->valid_mask = 1; /* whether the EXEC mask is valid */
6303 args->done = 1; /* DONE bit */
6304 } else if (!args->enabled_channels)
6305 return false; /* unnecessary NULL export */
6306
6307 return true;
6308 }
6309
6310 static void
6311 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6312 LLVMValueRef depth, LLVMValueRef stencil,
6313 LLVMValueRef samplemask)
6314 {
6315 struct ac_export_args args;
6316
6317 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6318
6319 ac_build_export(&ctx->ac, &args);
6320 }
6321
6322 static void
6323 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6324 {
6325 unsigned index = 0;
6326 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6327 struct ac_export_args color_args[8];
6328
6329 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6330 LLVMValueRef values[4];
6331
6332 if (!(ctx->output_mask & (1ull << i)))
6333 continue;
6334
6335 if (i == FRAG_RESULT_DEPTH) {
6336 ctx->shader_info->fs.writes_z = true;
6337 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6338 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6339 } else if (i == FRAG_RESULT_STENCIL) {
6340 ctx->shader_info->fs.writes_stencil = true;
6341 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6342 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6343 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6344 ctx->shader_info->fs.writes_sample_mask = true;
6345 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6346 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6347 } else {
6348 bool last = false;
6349 for (unsigned j = 0; j < 4; j++)
6350 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6351 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6352
6353 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6354 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6355
6356 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6357 if (ret)
6358 index++;
6359 }
6360 }
6361
6362 for (unsigned i = 0; i < index; i++)
6363 ac_build_export(&ctx->ac, &color_args[i]);
6364 if (depth || stencil || samplemask)
6365 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6366 else if (!index) {
6367 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6368 ac_build_export(&ctx->ac, &color_args[0]);
6369 }
6370
6371 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6372 }
6373
6374 static void
6375 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6376 {
6377 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6378 }
6379
6380 static void
6381 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6382 LLVMValueRef *addrs)
6383 {
6384 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6385
6386 switch (ctx->stage) {
6387 case MESA_SHADER_VERTEX:
6388 if (ctx->options->key.vs.as_ls)
6389 handle_ls_outputs_post(ctx);
6390 else if (ctx->options->key.vs.as_es)
6391 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6392 else
6393 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6394 &ctx->shader_info->vs.outinfo);
6395 break;
6396 case MESA_SHADER_FRAGMENT:
6397 handle_fs_outputs_post(ctx);
6398 break;
6399 case MESA_SHADER_GEOMETRY:
6400 emit_gs_epilogue(ctx);
6401 break;
6402 case MESA_SHADER_TESS_CTRL:
6403 handle_tcs_outputs_post(ctx);
6404 break;
6405 case MESA_SHADER_TESS_EVAL:
6406 if (ctx->options->key.tes.as_es)
6407 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6408 else
6409 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6410 &ctx->shader_info->tes.outinfo);
6411 break;
6412 default:
6413 break;
6414 }
6415 }
6416
6417 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6418 {
6419 LLVMPassManagerRef passmgr;
6420 /* Create the pass manager */
6421 passmgr = LLVMCreateFunctionPassManagerForModule(
6422 ctx->module);
6423
6424 /* This pass should eliminate all the load and store instructions */
6425 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6426
6427 /* Add some optimization passes */
6428 LLVMAddScalarReplAggregatesPass(passmgr);
6429 LLVMAddLICMPass(passmgr);
6430 LLVMAddAggressiveDCEPass(passmgr);
6431 LLVMAddCFGSimplificationPass(passmgr);
6432 LLVMAddInstructionCombiningPass(passmgr);
6433
6434 /* Run the pass */
6435 LLVMInitializeFunctionPassManager(passmgr);
6436 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6437 LLVMFinalizeFunctionPassManager(passmgr);
6438
6439 LLVMDisposeBuilder(ctx->builder);
6440 LLVMDisposePassManager(passmgr);
6441 }
6442
6443 static void
6444 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6445 {
6446 struct ac_vs_output_info *outinfo;
6447
6448 switch (ctx->stage) {
6449 case MESA_SHADER_FRAGMENT:
6450 case MESA_SHADER_COMPUTE:
6451 case MESA_SHADER_TESS_CTRL:
6452 case MESA_SHADER_GEOMETRY:
6453 return;
6454 case MESA_SHADER_VERTEX:
6455 if (ctx->options->key.vs.as_ls ||
6456 ctx->options->key.vs.as_es)
6457 return;
6458 outinfo = &ctx->shader_info->vs.outinfo;
6459 break;
6460 case MESA_SHADER_TESS_EVAL:
6461 if (ctx->options->key.vs.as_es)
6462 return;
6463 outinfo = &ctx->shader_info->tes.outinfo;
6464 break;
6465 default:
6466 unreachable("Unhandled shader type");
6467 }
6468
6469 ac_optimize_vs_outputs(&ctx->ac,
6470 ctx->main_function,
6471 outinfo->vs_output_param_offset,
6472 VARYING_SLOT_MAX,
6473 &outinfo->param_exports);
6474 }
6475
6476 static void
6477 ac_setup_rings(struct nir_to_llvm_context *ctx)
6478 {
6479 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6480 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6481 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6482 }
6483
6484 if (ctx->is_gs_copy_shader) {
6485 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6486 }
6487 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6488 LLVMValueRef tmp;
6489 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6490 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6491
6492 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6493
6494 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6495 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6496 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6497 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6498 }
6499
6500 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6501 ctx->stage == MESA_SHADER_TESS_EVAL) {
6502 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6503 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6504 }
6505 }
6506
6507 static unsigned
6508 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6509 const struct nir_shader *nir)
6510 {
6511 switch (nir->info.stage) {
6512 case MESA_SHADER_TESS_CTRL:
6513 return chip_class >= CIK ? 128 : 64;
6514 case MESA_SHADER_GEOMETRY:
6515 return chip_class >= GFX9 ? 128 : 64;
6516 case MESA_SHADER_COMPUTE:
6517 break;
6518 default:
6519 return 0;
6520 }
6521
6522 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6523 nir->info.cs.local_size[1] *
6524 nir->info.cs.local_size[2];
6525 return max_workgroup_size;
6526 }
6527
6528 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6529 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6530 {
6531 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6532 LLVMConstInt(ctx->ac.i32, 8, false),
6533 LLVMConstInt(ctx->ac.i32, 8, false), false);
6534 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6535 ctx->ac.i32_0, "");
6536 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6537 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6538 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6539 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6540 }
6541
6542 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6543 {
6544 for(int i = 5; i >= 0; --i) {
6545 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6546 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6547 LLVMConstInt(ctx->ac.i32, 16, false), false);
6548 }
6549
6550 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6551 LLVMConstInt(ctx->ac.i32, 16, false),
6552 LLVMConstInt(ctx->ac.i32, 8, false), false);
6553 }
6554
6555 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6556 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6557 {
6558 struct ac_nir_context ctx = {};
6559 struct nir_function *func;
6560
6561 ctx.ac = *ac;
6562 ctx.abi = abi;
6563
6564 ctx.nctx = nctx;
6565 if (nctx)
6566 nctx->nir = &ctx;
6567
6568 ctx.stage = nir->info.stage;
6569
6570 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6571
6572 nir_foreach_variable(variable, &nir->outputs)
6573 handle_shader_output_decl(&ctx, nir, variable);
6574
6575 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6576 _mesa_key_pointer_equal);
6577 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6578 _mesa_key_pointer_equal);
6579 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6580 _mesa_key_pointer_equal);
6581
6582 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6583
6584 setup_locals(&ctx, func);
6585
6586 if (nir->info.stage == MESA_SHADER_COMPUTE)
6587 setup_shared(&ctx, nir);
6588
6589 visit_cf_list(&ctx, &func->impl->body);
6590 phi_post_pass(&ctx);
6591
6592 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6593 ctx.outputs);
6594
6595 free(ctx.locals);
6596 ralloc_free(ctx.defs);
6597 ralloc_free(ctx.phis);
6598 ralloc_free(ctx.vars);
6599
6600 if (nctx)
6601 nctx->nir = NULL;
6602 }
6603
6604 static
6605 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6606 struct nir_shader *const *shaders,
6607 int shader_count,
6608 struct ac_shader_variant_info *shader_info,
6609 const struct ac_nir_compiler_options *options)
6610 {
6611 struct nir_to_llvm_context ctx = {0};
6612 unsigned i;
6613 ctx.options = options;
6614 ctx.shader_info = shader_info;
6615 ctx.context = LLVMContextCreate();
6616 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6617
6618 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6619 options->family);
6620 ctx.ac.module = ctx.module;
6621 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6622
6623 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6624 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6625 LLVMSetDataLayout(ctx.module, data_layout_str);
6626 LLVMDisposeTargetData(data_layout);
6627 LLVMDisposeMessage(data_layout_str);
6628
6629 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6630 ctx.ac.builder = ctx.builder;
6631
6632 memset(shader_info, 0, sizeof(*shader_info));
6633
6634 for(int i = 0; i < shader_count; ++i)
6635 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6636
6637 for (i = 0; i < AC_UD_MAX_SETS; i++)
6638 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6639 for (i = 0; i < AC_UD_MAX_UD; i++)
6640 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6641
6642 ctx.max_workgroup_size = 0;
6643 for (int i = 0; i < shader_count; ++i) {
6644 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6645 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6646 shaders[i]));
6647 }
6648
6649 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6650 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6651
6652 ctx.abi.inputs = &ctx.inputs[0];
6653 ctx.abi.emit_outputs = handle_shader_outputs_post;
6654 ctx.abi.emit_vertex = visit_emit_vertex;
6655 ctx.abi.load_ubo = radv_load_ubo;
6656 ctx.abi.load_ssbo = radv_load_ssbo;
6657 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6658 ctx.abi.clamp_shadow_reference = false;
6659
6660 if (shader_count >= 2)
6661 ac_init_exec_full_mask(&ctx.ac);
6662
6663 if (ctx.ac.chip_class == GFX9 &&
6664 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6665 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6666
6667 for(int i = 0; i < shader_count; ++i) {
6668 ctx.stage = shaders[i]->info.stage;
6669 ctx.output_mask = 0;
6670 ctx.tess_outputs_written = 0;
6671 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6672 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6673
6674 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6675 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6676 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6677 ctx.abi.load_inputs = load_gs_input;
6678 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6679 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6680 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6681 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6682 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6683 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6684 if (shader_info->info.vs.needs_instance_id) {
6685 ctx.shader_info->vs.vgpr_comp_cnt =
6686 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6687 }
6688 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6689 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6690 }
6691
6692 if (i)
6693 emit_barrier(&ctx);
6694
6695 ac_setup_rings(&ctx);
6696
6697 LLVMBasicBlockRef merge_block;
6698 if (shader_count >= 2) {
6699 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6700 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6701 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6702
6703 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6704 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6705 LLVMConstInt(ctx.ac.i32, 8, false), false);
6706 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6707 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6708 thread_id, count, "");
6709 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6710
6711 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6712 }
6713
6714 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6715 handle_fs_inputs(&ctx, shaders[i]);
6716 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6717 handle_vs_inputs(&ctx, shaders[i]);
6718 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6719 prepare_gs_input_vgprs(&ctx);
6720
6721 nir_foreach_variable(variable, &shaders[i]->outputs)
6722 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6723
6724 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6725
6726 if (shader_count >= 2) {
6727 LLVMBuildBr(ctx.ac.builder, merge_block);
6728 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6729 }
6730
6731 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6732 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6733 shaders[i]->info.cull_distance_array_size > 4;
6734 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6735 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6736 shaders[i]->info.gs.vertices_out;
6737 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6738 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6739 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6740 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6741 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6742 }
6743 }
6744
6745 LLVMBuildRetVoid(ctx.builder);
6746
6747 ac_llvm_finalize_module(&ctx);
6748
6749 if (shader_count == 1)
6750 ac_nir_eliminate_const_vs_outputs(&ctx);
6751
6752 return ctx.module;
6753 }
6754
6755 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6756 {
6757 unsigned *retval = (unsigned *)context;
6758 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6759 char *description = LLVMGetDiagInfoDescription(di);
6760
6761 if (severity == LLVMDSError) {
6762 *retval = 1;
6763 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6764 description);
6765 }
6766
6767 LLVMDisposeMessage(description);
6768 }
6769
6770 static unsigned ac_llvm_compile(LLVMModuleRef M,
6771 struct ac_shader_binary *binary,
6772 LLVMTargetMachineRef tm)
6773 {
6774 unsigned retval = 0;
6775 char *err;
6776 LLVMContextRef llvm_ctx;
6777 LLVMMemoryBufferRef out_buffer;
6778 unsigned buffer_size;
6779 const char *buffer_data;
6780 LLVMBool mem_err;
6781
6782 /* Setup Diagnostic Handler*/
6783 llvm_ctx = LLVMGetModuleContext(M);
6784
6785 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6786 &retval);
6787
6788 /* Compile IR*/
6789 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6790 &err, &out_buffer);
6791
6792 /* Process Errors/Warnings */
6793 if (mem_err) {
6794 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6795 free(err);
6796 retval = 1;
6797 goto out;
6798 }
6799
6800 /* Extract Shader Code*/
6801 buffer_size = LLVMGetBufferSize(out_buffer);
6802 buffer_data = LLVMGetBufferStart(out_buffer);
6803
6804 ac_elf_read(buffer_data, buffer_size, binary);
6805
6806 /* Clean up */
6807 LLVMDisposeMemoryBuffer(out_buffer);
6808
6809 out:
6810 return retval;
6811 }
6812
6813 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6814 LLVMModuleRef llvm_module,
6815 struct ac_shader_binary *binary,
6816 struct ac_shader_config *config,
6817 struct ac_shader_variant_info *shader_info,
6818 gl_shader_stage stage,
6819 bool dump_shader, bool supports_spill)
6820 {
6821 if (dump_shader)
6822 ac_dump_module(llvm_module);
6823
6824 memset(binary, 0, sizeof(*binary));
6825 int v = ac_llvm_compile(llvm_module, binary, tm);
6826 if (v) {
6827 fprintf(stderr, "compile failed\n");
6828 }
6829
6830 if (dump_shader)
6831 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6832
6833 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6834
6835 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6836 LLVMDisposeModule(llvm_module);
6837 LLVMContextDispose(ctx);
6838
6839 if (stage == MESA_SHADER_FRAGMENT) {
6840 shader_info->num_input_vgprs = 0;
6841 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6842 shader_info->num_input_vgprs += 2;
6843 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6844 shader_info->num_input_vgprs += 2;
6845 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6846 shader_info->num_input_vgprs += 2;
6847 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6848 shader_info->num_input_vgprs += 3;
6849 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6850 shader_info->num_input_vgprs += 2;
6851 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6852 shader_info->num_input_vgprs += 2;
6853 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6854 shader_info->num_input_vgprs += 2;
6855 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6856 shader_info->num_input_vgprs += 1;
6857 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6858 shader_info->num_input_vgprs += 1;
6859 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6860 shader_info->num_input_vgprs += 1;
6861 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6862 shader_info->num_input_vgprs += 1;
6863 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6864 shader_info->num_input_vgprs += 1;
6865 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6866 shader_info->num_input_vgprs += 1;
6867 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6868 shader_info->num_input_vgprs += 1;
6869 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6870 shader_info->num_input_vgprs += 1;
6871 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6872 shader_info->num_input_vgprs += 1;
6873 }
6874 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6875
6876 /* +3 for scratch wave offset and VCC */
6877 config->num_sgprs = MAX2(config->num_sgprs,
6878 shader_info->num_input_sgprs + 3);
6879 }
6880
6881 static void
6882 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6883 {
6884 switch (nir->info.stage) {
6885 case MESA_SHADER_COMPUTE:
6886 for (int i = 0; i < 3; ++i)
6887 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6888 break;
6889 case MESA_SHADER_FRAGMENT:
6890 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6891 break;
6892 case MESA_SHADER_GEOMETRY:
6893 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6894 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6895 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6896 shader_info->gs.invocations = nir->info.gs.invocations;
6897 break;
6898 case MESA_SHADER_TESS_EVAL:
6899 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6900 shader_info->tes.spacing = nir->info.tess.spacing;
6901 shader_info->tes.ccw = nir->info.tess.ccw;
6902 shader_info->tes.point_mode = nir->info.tess.point_mode;
6903 shader_info->tes.as_es = options->key.tes.as_es;
6904 break;
6905 case MESA_SHADER_TESS_CTRL:
6906 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6907 break;
6908 case MESA_SHADER_VERTEX:
6909 shader_info->vs.as_es = options->key.vs.as_es;
6910 shader_info->vs.as_ls = options->key.vs.as_ls;
6911 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6912 if (options->key.vs.as_ls)
6913 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6914 break;
6915 default:
6916 break;
6917 }
6918 }
6919
6920 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6921 struct ac_shader_binary *binary,
6922 struct ac_shader_config *config,
6923 struct ac_shader_variant_info *shader_info,
6924 struct nir_shader *const *nir,
6925 int nir_count,
6926 const struct ac_nir_compiler_options *options,
6927 bool dump_shader)
6928 {
6929
6930 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6931 options);
6932
6933 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6934 for (int i = 0; i < nir_count; ++i)
6935 ac_fill_shader_info(shader_info, nir[i], options);
6936 }
6937
6938 static void
6939 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6940 {
6941 LLVMValueRef args[9];
6942 args[0] = ctx->gsvs_ring;
6943 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6944 args[3] = ctx->ac.i32_0;
6945 args[4] = ctx->ac.i32_1; /* OFFEN */
6946 args[5] = ctx->ac.i32_0; /* IDXEN */
6947 args[6] = ctx->ac.i32_1; /* GLC */
6948 args[7] = ctx->ac.i32_1; /* SLC */
6949 args[8] = ctx->ac.i32_0; /* TFE */
6950
6951 int idx = 0;
6952
6953 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6954 int length = 4;
6955 int slot = idx;
6956 int slot_inc = 1;
6957 if (!(ctx->output_mask & (1ull << i)))
6958 continue;
6959
6960 if (i == VARYING_SLOT_CLIP_DIST0) {
6961 /* unpack clip and cull from a single set of slots */
6962 length = ctx->num_output_clips + ctx->num_output_culls;
6963 if (length > 4)
6964 slot_inc = 2;
6965 }
6966
6967 for (unsigned j = 0; j < length; j++) {
6968 LLVMValueRef value;
6969 args[2] = LLVMConstInt(ctx->ac.i32,
6970 (slot * 4 + j) *
6971 ctx->gs_max_out_vertices * 16 * 4, false);
6972
6973 value = ac_build_intrinsic(&ctx->ac,
6974 "llvm.SI.buffer.load.dword.i32.i32",
6975 ctx->ac.i32, args, 9,
6976 AC_FUNC_ATTR_READONLY |
6977 AC_FUNC_ATTR_LEGACY);
6978
6979 LLVMBuildStore(ctx->builder,
6980 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6981 }
6982 idx += slot_inc;
6983 }
6984 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6985 }
6986
6987 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6988 struct nir_shader *geom_shader,
6989 struct ac_shader_binary *binary,
6990 struct ac_shader_config *config,
6991 struct ac_shader_variant_info *shader_info,
6992 const struct ac_nir_compiler_options *options,
6993 bool dump_shader)
6994 {
6995 struct nir_to_llvm_context ctx = {0};
6996 ctx.context = LLVMContextCreate();
6997 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6998 ctx.options = options;
6999 ctx.shader_info = shader_info;
7000
7001 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7002 options->family);
7003 ctx.ac.module = ctx.module;
7004
7005 ctx.is_gs_copy_shader = true;
7006 LLVMSetTarget(ctx.module, "amdgcn--");
7007
7008 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
7009 ctx.ac.builder = ctx.builder;
7010 ctx.stage = MESA_SHADER_VERTEX;
7011
7012 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7013
7014 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7015 ac_setup_rings(&ctx);
7016
7017 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7018 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7019
7020 struct ac_nir_context nir_ctx = {};
7021 nir_ctx.ac = ctx.ac;
7022 nir_ctx.abi = &ctx.abi;
7023
7024 nir_ctx.nctx = &ctx;
7025 ctx.nir = &nir_ctx;
7026
7027 nir_foreach_variable(variable, &geom_shader->outputs) {
7028 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7029 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7030 }
7031
7032 ac_gs_copy_shader_emit(&ctx);
7033
7034 ctx.nir = NULL;
7035
7036 LLVMBuildRetVoid(ctx.builder);
7037
7038 ac_llvm_finalize_module(&ctx);
7039
7040 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7041 MESA_SHADER_VERTEX,
7042 dump_shader, options->supports_spill);
7043 }