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ac: add si_nir_load_input_gs() to the abi
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 RADEON_LLVM_AMDGPU_HS = 93,
43 };
44
45 #define CONST_ADDR_SPACE 2
46 #define LOCAL_ADDR_SPACE 3
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
50
51 struct nir_to_llvm_context;
52
53 struct ac_nir_context {
54 struct ac_llvm_context ac;
55 struct ac_shader_abi *abi;
56
57 gl_shader_stage stage;
58
59 struct hash_table *defs;
60 struct hash_table *phis;
61 struct hash_table *vars;
62
63 LLVMValueRef main_function;
64 LLVMBasicBlockRef continue_block;
65 LLVMBasicBlockRef break_block;
66
67 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
68
69 int num_locals;
70 LLVMValueRef *locals;
71
72 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
73 };
74
75 struct nir_to_llvm_context {
76 struct ac_llvm_context ac;
77 const struct ac_nir_compiler_options *options;
78 struct ac_shader_variant_info *shader_info;
79 struct ac_shader_abi abi;
80 struct ac_nir_context *nir;
81
82 unsigned max_workgroup_size;
83 LLVMContextRef context;
84 LLVMModuleRef module;
85 LLVMBuilderRef builder;
86 LLVMValueRef main_function;
87
88 struct hash_table *defs;
89 struct hash_table *phis;
90
91 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
92 LLVMValueRef ring_offsets;
93 LLVMValueRef push_constants;
94 LLVMValueRef view_index;
95 LLVMValueRef num_work_groups;
96 LLVMValueRef workgroup_ids;
97 LLVMValueRef local_invocation_ids;
98 LLVMValueRef tg_size;
99
100 LLVMValueRef vertex_buffers;
101 LLVMValueRef rel_auto_id;
102 LLVMValueRef vs_prim_id;
103 LLVMValueRef ls_out_layout;
104 LLVMValueRef es2gs_offset;
105
106 LLVMValueRef tcs_offchip_layout;
107 LLVMValueRef tcs_out_offsets;
108 LLVMValueRef tcs_out_layout;
109 LLVMValueRef tcs_in_layout;
110 LLVMValueRef oc_lds;
111 LLVMValueRef merged_wave_info;
112 LLVMValueRef tess_factor_offset;
113 LLVMValueRef tcs_patch_id;
114 LLVMValueRef tcs_rel_ids;
115 LLVMValueRef tes_rel_patch_id;
116 LLVMValueRef tes_patch_id;
117 LLVMValueRef tes_u;
118 LLVMValueRef tes_v;
119
120 LLVMValueRef gsvs_ring_stride;
121 LLVMValueRef gsvs_num_entries;
122 LLVMValueRef gs2vs_offset;
123 LLVMValueRef gs_wave_id;
124 LLVMValueRef gs_vtx_offset[6];
125
126 LLVMValueRef esgs_ring;
127 LLVMValueRef gsvs_ring;
128 LLVMValueRef hs_ring_tess_offchip;
129 LLVMValueRef hs_ring_tess_factor;
130
131 LLVMValueRef prim_mask;
132 LLVMValueRef sample_pos_offset;
133 LLVMValueRef persp_sample, persp_center, persp_centroid;
134 LLVMValueRef linear_sample, linear_center, linear_centroid;
135
136 gl_shader_stage stage;
137
138 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
139
140 uint64_t input_mask;
141 uint64_t output_mask;
142 uint8_t num_output_clips;
143 uint8_t num_output_culls;
144
145 bool is_gs_copy_shader;
146 LLVMValueRef gs_next_vertex;
147 unsigned gs_max_out_vertices;
148
149 unsigned tes_primitive_mode;
150 uint64_t tess_outputs_written;
151 uint64_t tess_patch_outputs_written;
152
153 uint32_t tcs_patch_outputs_read;
154 uint64_t tcs_outputs_read;
155 };
156
157 static inline struct nir_to_llvm_context *
158 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
159 {
160 struct nir_to_llvm_context *ctx = NULL;
161 return container_of(abi, ctx, abi);
162 }
163
164 static LLVMTypeRef
165 nir2llvmtype(struct ac_nir_context *ctx,
166 const struct glsl_type *type)
167 {
168 switch (glsl_get_base_type(glsl_without_array(type))) {
169 case GLSL_TYPE_UINT:
170 case GLSL_TYPE_INT:
171 return ctx->ac.i32;
172 case GLSL_TYPE_UINT64:
173 case GLSL_TYPE_INT64:
174 return ctx->ac.i64;
175 case GLSL_TYPE_DOUBLE:
176 return ctx->ac.f64;
177 case GLSL_TYPE_FLOAT:
178 return ctx->ac.f32;
179 default:
180 assert(!"Unsupported type in nir2llvmtype()");
181 break;
182 }
183 return 0;
184 }
185
186 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
187 const nir_deref_var *deref,
188 enum ac_descriptor_type desc_type,
189 const nir_tex_instr *instr,
190 bool image, bool write);
191
192 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
193 {
194 return (index * 4) + chan;
195 }
196
197 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
198 {
199 /* handle patch indices separate */
200 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
201 return 0;
202 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
203 return 1;
204 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
205 return 2 + (slot - VARYING_SLOT_PATCH0);
206
207 if (slot == VARYING_SLOT_POS)
208 return 0;
209 if (slot == VARYING_SLOT_PSIZ)
210 return 1;
211 if (slot == VARYING_SLOT_CLIP_DIST0)
212 return 2;
213 /* 3 is reserved for clip dist as well */
214 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
215 return 4 + (slot - VARYING_SLOT_VAR0);
216 unreachable("illegal slot in get unique index\n");
217 }
218
219 static void set_llvm_calling_convention(LLVMValueRef func,
220 gl_shader_stage stage)
221 {
222 enum radeon_llvm_calling_convention calling_conv;
223
224 switch (stage) {
225 case MESA_SHADER_VERTEX:
226 case MESA_SHADER_TESS_EVAL:
227 calling_conv = RADEON_LLVM_AMDGPU_VS;
228 break;
229 case MESA_SHADER_GEOMETRY:
230 calling_conv = RADEON_LLVM_AMDGPU_GS;
231 break;
232 case MESA_SHADER_TESS_CTRL:
233 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
234 break;
235 case MESA_SHADER_FRAGMENT:
236 calling_conv = RADEON_LLVM_AMDGPU_PS;
237 break;
238 case MESA_SHADER_COMPUTE:
239 calling_conv = RADEON_LLVM_AMDGPU_CS;
240 break;
241 default:
242 unreachable("Unhandle shader type");
243 }
244
245 LLVMSetFunctionCallConv(func, calling_conv);
246 }
247
248 #define MAX_ARGS 23
249 struct arg_info {
250 LLVMTypeRef types[MAX_ARGS];
251 LLVMValueRef *assign[MAX_ARGS];
252 unsigned array_params_mask;
253 uint8_t count;
254 uint8_t user_sgpr_count;
255 uint8_t sgpr_count;
256 uint8_t num_user_sgprs_used;
257 uint8_t num_sgprs_used;
258 uint8_t num_vgprs_used;
259 };
260
261 static inline void
262 add_argument(struct arg_info *info,
263 LLVMTypeRef type, LLVMValueRef *param_ptr)
264 {
265 assert(info->count < MAX_ARGS);
266 info->assign[info->count] = param_ptr;
267 info->types[info->count] = type;
268 info->count++;
269 }
270
271 static inline void
272 add_sgpr_argument(struct arg_info *info,
273 LLVMTypeRef type, LLVMValueRef *param_ptr)
274 {
275 add_argument(info, type, param_ptr);
276 info->num_sgprs_used += ac_get_type_size(type) / 4;
277 info->sgpr_count++;
278 }
279
280 static inline void
281 add_user_sgpr_argument(struct arg_info *info,
282 LLVMTypeRef type,
283 LLVMValueRef *param_ptr)
284 {
285 add_sgpr_argument(info, type, param_ptr);
286 info->num_user_sgprs_used += ac_get_type_size(type) / 4;
287 info->user_sgpr_count++;
288 }
289
290 static inline void
291 add_vgpr_argument(struct arg_info *info,
292 LLVMTypeRef type,
293 LLVMValueRef *param_ptr)
294 {
295 add_argument(info, type, param_ptr);
296 info->num_vgprs_used += ac_get_type_size(type) / 4;
297 }
298
299 static inline void
300 add_user_sgpr_array_argument(struct arg_info *info,
301 LLVMTypeRef type,
302 LLVMValueRef *param_ptr)
303 {
304 info->array_params_mask |= (1 << info->count);
305 add_user_sgpr_argument(info, type, param_ptr);
306 }
307
308 static void assign_arguments(LLVMValueRef main_function,
309 struct arg_info *info)
310 {
311 unsigned i;
312 for (i = 0; i < info->count; i++) {
313 if (info->assign[i])
314 *info->assign[i] = LLVMGetParam(main_function, i);
315 }
316 }
317
318 static LLVMValueRef
319 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
320 LLVMBuilderRef builder, LLVMTypeRef *return_types,
321 unsigned num_return_elems,
322 struct arg_info *args,
323 unsigned max_workgroup_size,
324 bool unsafe_math)
325 {
326 LLVMTypeRef main_function_type, ret_type;
327 LLVMBasicBlockRef main_function_body;
328
329 if (num_return_elems)
330 ret_type = LLVMStructTypeInContext(ctx, return_types,
331 num_return_elems, true);
332 else
333 ret_type = LLVMVoidTypeInContext(ctx);
334
335 /* Setup the function */
336 main_function_type =
337 LLVMFunctionType(ret_type, args->types, args->count, 0);
338 LLVMValueRef main_function =
339 LLVMAddFunction(module, "main", main_function_type);
340 main_function_body =
341 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
342 LLVMPositionBuilderAtEnd(builder, main_function_body);
343
344 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
345 for (unsigned i = 0; i < args->sgpr_count; ++i) {
346 if (args->array_params_mask & (1 << i)) {
347 LLVMValueRef P = LLVMGetParam(main_function, i);
348 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
349 ac_add_attr_dereferenceable(P, UINT64_MAX);
350 }
351 else {
352 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
353 }
354 }
355
356 if (max_workgroup_size) {
357 ac_llvm_add_target_dep_function_attr(main_function,
358 "amdgpu-max-work-group-size",
359 max_workgroup_size);
360 }
361 if (unsafe_math) {
362 /* These were copied from some LLVM test. */
363 LLVMAddTargetDependentFunctionAttr(main_function,
364 "less-precise-fpmad",
365 "true");
366 LLVMAddTargetDependentFunctionAttr(main_function,
367 "no-infs-fp-math",
368 "true");
369 LLVMAddTargetDependentFunctionAttr(main_function,
370 "no-nans-fp-math",
371 "true");
372 LLVMAddTargetDependentFunctionAttr(main_function,
373 "unsafe-fp-math",
374 "true");
375 }
376 return main_function;
377 }
378
379 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
380 {
381 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
382 CONST_ADDR_SPACE);
383 }
384
385 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
386 {
387 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
388 type = LLVMGetElementType(type);
389
390 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
391 return LLVMGetIntTypeWidth(type);
392
393 if (type == ctx->f16)
394 return 16;
395 if (type == ctx->f32)
396 return 32;
397 if (type == ctx->f64)
398 return 64;
399
400 unreachable("Unhandled type kind in get_elem_bits");
401 }
402
403 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
404 LLVMValueRef param, unsigned rshift,
405 unsigned bitwidth)
406 {
407 LLVMValueRef value = param;
408 if (rshift)
409 value = LLVMBuildLShr(ctx->builder, value,
410 LLVMConstInt(ctx->i32, rshift, false), "");
411
412 if (rshift + bitwidth < 32) {
413 unsigned mask = (1 << bitwidth) - 1;
414 value = LLVMBuildAnd(ctx->builder, value,
415 LLVMConstInt(ctx->i32, mask, false), "");
416 }
417 return value;
418 }
419
420 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
421 {
422 switch (ctx->stage) {
423 case MESA_SHADER_TESS_CTRL:
424 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
425 case MESA_SHADER_TESS_EVAL:
426 return ctx->tes_rel_patch_id;
427 break;
428 default:
429 unreachable("Illegal stage");
430 }
431 }
432
433 /* Tessellation shaders pass outputs to the next shader using LDS.
434 *
435 * LS outputs = TCS inputs
436 * TCS outputs = TES inputs
437 *
438 * The LDS layout is:
439 * - TCS inputs for patch 0
440 * - TCS inputs for patch 1
441 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
442 * - ...
443 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
444 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
445 * - TCS outputs for patch 1
446 * - Per-patch TCS outputs for patch 1
447 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
448 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
449 * - ...
450 *
451 * All three shaders VS(LS), TCS, TES share the same LDS space.
452 */
453 static LLVMValueRef
454 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
455 {
456 if (ctx->stage == MESA_SHADER_VERTEX)
457 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
458 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
459 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
460 else {
461 assert(0);
462 return NULL;
463 }
464 }
465
466 static LLVMValueRef
467 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
468 {
469 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
470 }
471
472 static LLVMValueRef
473 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
474 {
475 return LLVMBuildMul(ctx->builder,
476 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
477 LLVMConstInt(ctx->ac.i32, 4, false), "");
478 }
479
480 static LLVMValueRef
481 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
482 {
483 return LLVMBuildMul(ctx->builder,
484 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
485 LLVMConstInt(ctx->ac.i32, 4, false), "");
486 }
487
488 static LLVMValueRef
489 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
490 {
491 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
492 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
493
494 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
495 }
496
497 static LLVMValueRef
498 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
499 {
500 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
501 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
502 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
503
504 return LLVMBuildAdd(ctx->builder, patch0_offset,
505 LLVMBuildMul(ctx->builder, patch_stride,
506 rel_patch_id, ""),
507 "");
508 }
509
510 static LLVMValueRef
511 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
512 {
513 LLVMValueRef patch0_patch_data_offset =
514 get_tcs_out_patch0_patch_data_offset(ctx);
515 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
516 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
517
518 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
519 LLVMBuildMul(ctx->builder, patch_stride,
520 rel_patch_id, ""),
521 "");
522 }
523
524 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
525 {
526 ud_info->sgpr_idx = *sgpr_idx;
527 ud_info->num_sgprs = num_sgprs;
528 ud_info->indirect = false;
529 ud_info->indirect_offset = 0;
530 *sgpr_idx += num_sgprs;
531 }
532
533 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
534 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
535 {
536 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
537 }
538
539
540 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
541 uint32_t indirect_offset)
542 {
543 ud_info->sgpr_idx = sgpr_idx;
544 ud_info->num_sgprs = num_sgprs;
545 ud_info->indirect = true;
546 ud_info->indirect_offset = indirect_offset;
547 }
548
549 struct user_sgpr_info {
550 bool need_ring_offsets;
551 uint8_t sgpr_count;
552 bool indirect_all_descriptor_sets;
553 };
554
555 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
556 struct user_sgpr_info *user_sgpr_info)
557 {
558 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
559
560 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
561 if (ctx->stage == MESA_SHADER_GEOMETRY ||
562 ctx->stage == MESA_SHADER_VERTEX ||
563 ctx->stage == MESA_SHADER_TESS_CTRL ||
564 ctx->stage == MESA_SHADER_TESS_EVAL ||
565 ctx->is_gs_copy_shader)
566 user_sgpr_info->need_ring_offsets = true;
567
568 if (ctx->stage == MESA_SHADER_FRAGMENT &&
569 ctx->shader_info->info.ps.needs_sample_positions)
570 user_sgpr_info->need_ring_offsets = true;
571
572 /* 2 user sgprs will nearly always be allocated for scratch/rings */
573 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
574 user_sgpr_info->sgpr_count += 2;
575 }
576
577 switch (ctx->stage) {
578 case MESA_SHADER_COMPUTE:
579 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
580 break;
581 case MESA_SHADER_FRAGMENT:
582 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
583 break;
584 case MESA_SHADER_VERTEX:
585 if (!ctx->is_gs_copy_shader) {
586 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
587 if (ctx->shader_info->info.vs.needs_draw_id) {
588 user_sgpr_info->sgpr_count += 3;
589 } else {
590 user_sgpr_info->sgpr_count += 2;
591 }
592 }
593 if (ctx->options->key.vs.as_ls)
594 user_sgpr_info->sgpr_count++;
595 break;
596 case MESA_SHADER_TESS_CTRL:
597 user_sgpr_info->sgpr_count += 4;
598 break;
599 case MESA_SHADER_TESS_EVAL:
600 user_sgpr_info->sgpr_count += 1;
601 break;
602 case MESA_SHADER_GEOMETRY:
603 user_sgpr_info->sgpr_count += 2;
604 break;
605 default:
606 break;
607 }
608
609 if (ctx->shader_info->info.needs_push_constants)
610 user_sgpr_info->sgpr_count += 2;
611
612 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
613 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
614 user_sgpr_info->sgpr_count += 2;
615 user_sgpr_info->indirect_all_descriptor_sets = true;
616 } else {
617 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
618 }
619 }
620
621 static void
622 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
623 gl_shader_stage stage,
624 bool has_previous_stage,
625 gl_shader_stage previous_stage,
626 const struct user_sgpr_info *user_sgpr_info,
627 struct arg_info *args,
628 LLVMValueRef *desc_sets)
629 {
630 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
631 unsigned stage_mask = 1 << stage;
632 if (has_previous_stage)
633 stage_mask |= 1 << previous_stage;
634
635 /* 1 for each descriptor set */
636 if (!user_sgpr_info->indirect_all_descriptor_sets) {
637 for (unsigned i = 0; i < num_sets; ++i) {
638 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
639 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->descriptor_sets[i]);
640 }
641 }
642 } else
643 add_user_sgpr_array_argument(args, const_array(const_array(ctx->ac.i8, 1024 * 1024), 32), desc_sets);
644
645 if (ctx->shader_info->info.needs_push_constants) {
646 /* 1 for push constants and dynamic descriptors */
647 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->push_constants);
648 }
649 }
650
651 static void
652 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
653 gl_shader_stage stage,
654 bool has_previous_stage,
655 gl_shader_stage previous_stage,
656 const struct user_sgpr_info *user_sgpr_info,
657 LLVMValueRef desc_sets,
658 uint8_t *user_sgpr_idx)
659 {
660 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
661 unsigned stage_mask = 1 << stage;
662 if (has_previous_stage)
663 stage_mask |= 1 << previous_stage;
664
665 if (!user_sgpr_info->indirect_all_descriptor_sets) {
666 for (unsigned i = 0; i < num_sets; ++i) {
667 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
668 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
669 } else
670 ctx->descriptor_sets[i] = NULL;
671 }
672 } else {
673 uint32_t desc_sgpr_idx = *user_sgpr_idx;
674 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
675
676 for (unsigned i = 0; i < num_sets; ++i) {
677 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
678 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
679 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->ac.i32, i, false));
680
681 } else
682 ctx->descriptor_sets[i] = NULL;
683 }
684 ctx->shader_info->need_indirect_descriptor_sets = true;
685 }
686
687 if (ctx->shader_info->info.needs_push_constants) {
688 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
689 }
690 }
691
692 static void
693 radv_define_vs_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
694 gl_shader_stage stage,
695 bool has_previous_stage,
696 gl_shader_stage previous_stage,
697 struct arg_info *args)
698 {
699 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
700 if (ctx->shader_info->info.vs.has_vertex_buffers)
701 add_user_sgpr_argument(args, const_array(ctx->ac.v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
702 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.base_vertex); // base vertex
703 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.start_instance);// start instance
704 if (ctx->shader_info->info.vs.needs_draw_id)
705 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.draw_id); // draw id
706 }
707 }
708
709 static void
710 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
711 gl_shader_stage stage,
712 bool has_previous_stage,
713 gl_shader_stage previous_stage,
714 uint8_t *user_sgpr_idx)
715 {
716 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
717 if (ctx->shader_info->info.vs.has_vertex_buffers) {
718 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
719 }
720 unsigned vs_num = 2;
721 if (ctx->shader_info->info.vs.needs_draw_id)
722 vs_num++;
723
724 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
725 }
726 }
727
728
729 static void create_function(struct nir_to_llvm_context *ctx,
730 gl_shader_stage stage,
731 bool has_previous_stage,
732 gl_shader_stage previous_stage)
733 {
734 uint8_t user_sgpr_idx;
735 struct user_sgpr_info user_sgpr_info;
736 struct arg_info args = {};
737 LLVMValueRef desc_sets;
738
739 allocate_user_sgprs(ctx, &user_sgpr_info);
740
741 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
742 add_user_sgpr_argument(&args, const_array(ctx->ac.v4i32, 16), &ctx->ring_offsets); /* address of rings */
743 }
744
745 switch (stage) {
746 case MESA_SHADER_COMPUTE:
747 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
748 if (ctx->shader_info->info.cs.grid_components_used)
749 add_user_sgpr_argument(&args, LLVMVectorType(ctx->ac.i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
750 add_sgpr_argument(&args, ctx->ac.v3i32, &ctx->workgroup_ids);
751 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tg_size);
752 add_vgpr_argument(&args, ctx->ac.v3i32, &ctx->local_invocation_ids);
753 break;
754 case MESA_SHADER_VERTEX:
755 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
756 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
757 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
758 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
759 if (ctx->options->key.vs.as_es)
760 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
761 else if (ctx->options->key.vs.as_ls)
762 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
763 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
764 if (!ctx->is_gs_copy_shader) {
765 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
766 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
767 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
768 }
769 break;
770 case MESA_SHADER_TESS_CTRL:
771 if (has_previous_stage) {
772 // First 6 system regs
773 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
774 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
775 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
776
777 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
778 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
779 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
780
781 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
782 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
783 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
784
785 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
786 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
787 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
788 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
789 if (ctx->shader_info->info.needs_multiview_view_index)
790 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
791
792 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
793 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
794 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
795 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
796 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
797 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
798 } else {
799 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
800 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
801 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
802 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
803 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
804 if (ctx->shader_info->info.needs_multiview_view_index)
805 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
806 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
807 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
808 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
809 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
810 }
811 break;
812 case MESA_SHADER_TESS_EVAL:
813 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
814 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
815 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
816 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
817 if (ctx->options->key.tes.as_es) {
818 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
819 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
820 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
821 } else {
822 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
823 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
824 }
825 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
826 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
827 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
828 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
829 break;
830 case MESA_SHADER_GEOMETRY:
831 if (has_previous_stage) {
832 // First 6 system regs
833 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // tess factor offset
834 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
835 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
836
837 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
838 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
839 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
840
841 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
842 if (previous_stage == MESA_SHADER_TESS_EVAL)
843 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
844 else
845 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
846 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
847 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
848 if (ctx->shader_info->info.needs_multiview_view_index)
849 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
850
851 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx01
852 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]); // vtx23
853 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_prim_id); // prim id
854 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_invocation_id);
855 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
856
857 if (previous_stage == MESA_SHADER_VERTEX) {
858 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
859 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
860 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
861 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
862 } else {
863 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
864 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
865 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
866 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
867 }
868 } else {
869 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
870 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
871 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
872 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
873 if (ctx->shader_info->info.needs_multiview_view_index)
874 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
875 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // gs2vs offset
876 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs_wave_id); // wave id
877 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx0
878 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[1]); // vtx1
879 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_prim_id); // prim id
880 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]);
881 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[3]);
882 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
883 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[5]);
884 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_invocation_id);
885 }
886 break;
887 case MESA_SHADER_FRAGMENT:
888 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
889 if (ctx->shader_info->info.ps.needs_sample_positions)
890 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->sample_pos_offset); /* sample position offset */
891 add_sgpr_argument(&args, ctx->ac.i32, &ctx->prim_mask); /* prim mask */
892 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_sample); /* persp sample */
893 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_center); /* persp center */
894 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_centroid); /* persp centroid */
895 add_vgpr_argument(&args, ctx->ac.v3i32, NULL); /* persp pull model */
896 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_sample); /* linear sample */
897 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_center); /* linear center */
898 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_centroid); /* linear centroid */
899 add_vgpr_argument(&args, ctx->ac.f32, NULL); /* line stipple tex */
900 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[0]); /* pos x float */
901 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[1]); /* pos y float */
902 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[2]); /* pos z float */
903 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[3]); /* pos w float */
904 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.front_face); /* front face */
905 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.ancillary); /* ancillary */
906 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.sample_coverage); /* sample coverage */
907 add_vgpr_argument(&args, ctx->ac.i32, NULL); /* fixed pt */
908 break;
909 default:
910 unreachable("Shader stage not implemented");
911 }
912
913 ctx->main_function = create_llvm_function(
914 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
915 ctx->max_workgroup_size,
916 ctx->options->unsafe_math);
917 set_llvm_calling_convention(ctx->main_function, stage);
918
919
920 ctx->shader_info->num_input_vgprs = 0;
921 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
922
923 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
924
925 if (ctx->stage != MESA_SHADER_FRAGMENT)
926 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
927
928 assign_arguments(ctx->main_function, &args);
929
930 user_sgpr_idx = 0;
931
932 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
933 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
934 if (ctx->options->supports_spill) {
935 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
936 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
937 NULL, 0, AC_FUNC_ATTR_READNONE);
938 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
939 const_array(ctx->ac.v4i32, 16), "");
940 }
941 }
942
943 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
944 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
945 if (has_previous_stage)
946 user_sgpr_idx = 0;
947
948 radv_define_common_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, desc_sets, &user_sgpr_idx);
949
950 switch (stage) {
951 case MESA_SHADER_COMPUTE:
952 if (ctx->shader_info->info.cs.grid_components_used) {
953 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
954 }
955 break;
956 case MESA_SHADER_VERTEX:
957 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
958 if (ctx->view_index)
959 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
960 if (ctx->options->key.vs.as_ls) {
961 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
962 }
963 if (ctx->options->key.vs.as_ls)
964 ac_declare_lds_as_pointer(&ctx->ac);
965 break;
966 case MESA_SHADER_TESS_CTRL:
967 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
968 if (has_previous_stage)
969 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
970 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
971 if (ctx->view_index)
972 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
973 ac_declare_lds_as_pointer(&ctx->ac);
974 break;
975 case MESA_SHADER_TESS_EVAL:
976 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
977 if (ctx->view_index)
978 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
979 break;
980 case MESA_SHADER_GEOMETRY:
981 if (has_previous_stage) {
982 if (previous_stage == MESA_SHADER_VERTEX)
983 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
984 else
985 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
986 }
987 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
988 if (ctx->view_index)
989 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
990 if (has_previous_stage)
991 ac_declare_lds_as_pointer(&ctx->ac);
992 break;
993 case MESA_SHADER_FRAGMENT:
994 if (ctx->shader_info->info.ps.needs_sample_positions) {
995 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
996 }
997 break;
998 default:
999 unreachable("Shader stage not implemented");
1000 }
1001
1002 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1003 }
1004
1005 static int get_llvm_num_components(LLVMValueRef value)
1006 {
1007 LLVMTypeRef type = LLVMTypeOf(value);
1008 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1009 ? LLVMGetVectorSize(type)
1010 : 1;
1011 return num_components;
1012 }
1013
1014 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1015 LLVMValueRef value,
1016 int index)
1017 {
1018 int count = get_llvm_num_components(value);
1019
1020 if (count == 1)
1021 return value;
1022
1023 return LLVMBuildExtractElement(ac->builder, value,
1024 LLVMConstInt(ac->i32, index, false), "");
1025 }
1026
1027 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1028 LLVMValueRef value, unsigned count)
1029 {
1030 unsigned num_components = get_llvm_num_components(value);
1031 if (count == num_components)
1032 return value;
1033
1034 LLVMValueRef masks[] = {
1035 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1036 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1037
1038 if (count == 1)
1039 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1040 "");
1041
1042 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1043 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1044 }
1045
1046 static void
1047 build_store_values_extended(struct ac_llvm_context *ac,
1048 LLVMValueRef *values,
1049 unsigned value_count,
1050 unsigned value_stride,
1051 LLVMValueRef vec)
1052 {
1053 LLVMBuilderRef builder = ac->builder;
1054 unsigned i;
1055
1056 for (i = 0; i < value_count; i++) {
1057 LLVMValueRef ptr = values[i * value_stride];
1058 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1059 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1060 LLVMBuildStore(builder, value, ptr);
1061 }
1062 }
1063
1064 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1065 const nir_ssa_def *def)
1066 {
1067 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1068 if (def->num_components > 1) {
1069 type = LLVMVectorType(type, def->num_components);
1070 }
1071 return type;
1072 }
1073
1074 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1075 {
1076 assert(src.is_ssa);
1077 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1078 return (LLVMValueRef)entry->data;
1079 }
1080
1081
1082 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1083 const struct nir_block *b)
1084 {
1085 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1086 return (LLVMBasicBlockRef)entry->data;
1087 }
1088
1089 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1090 nir_alu_src src,
1091 unsigned num_components)
1092 {
1093 LLVMValueRef value = get_src(ctx, src.src);
1094 bool need_swizzle = false;
1095
1096 assert(value);
1097 LLVMTypeRef type = LLVMTypeOf(value);
1098 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1099 ? LLVMGetVectorSize(type)
1100 : 1;
1101
1102 for (unsigned i = 0; i < num_components; ++i) {
1103 assert(src.swizzle[i] < src_components);
1104 if (src.swizzle[i] != i)
1105 need_swizzle = true;
1106 }
1107
1108 if (need_swizzle || num_components != src_components) {
1109 LLVMValueRef masks[] = {
1110 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1111 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1112 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1113 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1114
1115 if (src_components > 1 && num_components == 1) {
1116 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1117 masks[0], "");
1118 } else if (src_components == 1 && num_components > 1) {
1119 LLVMValueRef values[] = {value, value, value, value};
1120 value = ac_build_gather_values(&ctx->ac, values, num_components);
1121 } else {
1122 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1123 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1124 swizzle, "");
1125 }
1126 }
1127 assert(!src.negate);
1128 assert(!src.abs);
1129 return value;
1130 }
1131
1132 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1133 LLVMIntPredicate pred, LLVMValueRef src0,
1134 LLVMValueRef src1)
1135 {
1136 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1137 return LLVMBuildSelect(ctx->builder, result,
1138 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1139 LLVMConstInt(ctx->i32, 0, false), "");
1140 }
1141
1142 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1143 LLVMRealPredicate pred, LLVMValueRef src0,
1144 LLVMValueRef src1)
1145 {
1146 LLVMValueRef result;
1147 src0 = ac_to_float(ctx, src0);
1148 src1 = ac_to_float(ctx, src1);
1149 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1150 return LLVMBuildSelect(ctx->builder, result,
1151 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1152 LLVMConstInt(ctx->i32, 0, false), "");
1153 }
1154
1155 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1156 const char *intrin,
1157 LLVMTypeRef result_type,
1158 LLVMValueRef src0)
1159 {
1160 char name[64];
1161 LLVMValueRef params[] = {
1162 ac_to_float(ctx, src0),
1163 };
1164
1165 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1166 get_elem_bits(ctx, result_type));
1167 assert(length < sizeof(name));
1168 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1169 }
1170
1171 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1172 const char *intrin,
1173 LLVMTypeRef result_type,
1174 LLVMValueRef src0, LLVMValueRef src1)
1175 {
1176 char name[64];
1177 LLVMValueRef params[] = {
1178 ac_to_float(ctx, src0),
1179 ac_to_float(ctx, src1),
1180 };
1181
1182 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1183 get_elem_bits(ctx, result_type));
1184 assert(length < sizeof(name));
1185 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1186 }
1187
1188 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1189 const char *intrin,
1190 LLVMTypeRef result_type,
1191 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1192 {
1193 char name[64];
1194 LLVMValueRef params[] = {
1195 ac_to_float(ctx, src0),
1196 ac_to_float(ctx, src1),
1197 ac_to_float(ctx, src2),
1198 };
1199
1200 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1201 get_elem_bits(ctx, result_type));
1202 assert(length < sizeof(name));
1203 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1204 }
1205
1206 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1207 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1208 {
1209 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1210 ctx->i32_0, "");
1211 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1212 }
1213
1214 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1215 LLVMIntPredicate pred,
1216 LLVMValueRef src0, LLVMValueRef src1)
1217 {
1218 return LLVMBuildSelect(ctx->builder,
1219 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1220 src0,
1221 src1, "");
1222
1223 }
1224 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1225 LLVMValueRef src0)
1226 {
1227 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1228 LLVMBuildNeg(ctx->builder, src0, ""));
1229 }
1230
1231 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1232 LLVMValueRef src0)
1233 {
1234 LLVMValueRef cmp, val;
1235
1236 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1237 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1238 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1239 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1240 return val;
1241 }
1242
1243 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1244 LLVMValueRef src0)
1245 {
1246 LLVMValueRef cmp, val;
1247
1248 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1249 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1250 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1251 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1252 return val;
1253 }
1254
1255 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1256 LLVMValueRef src0)
1257 {
1258 const char *intr = "llvm.floor.f32";
1259 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1260 LLVMValueRef params[] = {
1261 fsrc0,
1262 };
1263 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1264 ctx->f32, params, 1,
1265 AC_FUNC_ATTR_READNONE);
1266 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1267 }
1268
1269 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1270 const char *intrin,
1271 LLVMValueRef src0, LLVMValueRef src1)
1272 {
1273 LLVMTypeRef ret_type;
1274 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1275 LLVMValueRef res;
1276 LLVMValueRef params[] = { src0, src1 };
1277 ret_type = LLVMStructTypeInContext(ctx->context, types,
1278 2, true);
1279
1280 res = ac_build_intrinsic(ctx, intrin, ret_type,
1281 params, 2, AC_FUNC_ATTR_READNONE);
1282
1283 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1284 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1285 return res;
1286 }
1287
1288 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1289 LLVMValueRef src0)
1290 {
1291 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1292 }
1293
1294 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1295 LLVMValueRef src0)
1296 {
1297 src0 = ac_to_float(ctx, src0);
1298 return LLVMBuildSExt(ctx->builder,
1299 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1300 ctx->i32, "");
1301 }
1302
1303 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1304 LLVMValueRef src0)
1305 {
1306 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1307 }
1308
1309 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1310 LLVMValueRef src0)
1311 {
1312 return LLVMBuildSExt(ctx->builder,
1313 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1314 ctx->i32, "");
1315 }
1316
1317 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1318 LLVMValueRef src0)
1319 {
1320 LLVMValueRef result;
1321 LLVMValueRef cond = NULL;
1322
1323 src0 = ac_to_float(&ctx->ac, src0);
1324 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1325
1326 if (ctx->options->chip_class >= VI) {
1327 LLVMValueRef args[2];
1328 /* Check if the result is a denormal - and flush to 0 if so. */
1329 args[0] = result;
1330 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1331 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1332 }
1333
1334 /* need to convert back up to f32 */
1335 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1336
1337 if (ctx->options->chip_class >= VI)
1338 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1339 else {
1340 /* for SI/CIK */
1341 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1342 * so compare the result and flush to 0 if it's smaller.
1343 */
1344 LLVMValueRef temp, cond2;
1345 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1346 ctx->ac.f32, result);
1347 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1348 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1349 temp, "");
1350 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1351 temp, ctx->ac.f32_0, "");
1352 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1353 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1354 }
1355 return result;
1356 }
1357
1358 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1359 LLVMValueRef src0, LLVMValueRef src1)
1360 {
1361 LLVMValueRef dst64, result;
1362 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1363 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1364
1365 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1366 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1367 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1368 return result;
1369 }
1370
1371 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1372 LLVMValueRef src0, LLVMValueRef src1)
1373 {
1374 LLVMValueRef dst64, result;
1375 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1376 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1377
1378 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1379 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1380 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1381 return result;
1382 }
1383
1384 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1385 bool is_signed,
1386 const LLVMValueRef srcs[3])
1387 {
1388 LLVMValueRef result;
1389 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1390
1391 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1392 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1393 return result;
1394 }
1395
1396 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1397 LLVMValueRef src0, LLVMValueRef src1,
1398 LLVMValueRef src2, LLVMValueRef src3)
1399 {
1400 LLVMValueRef bfi_args[3], result;
1401
1402 bfi_args[0] = LLVMBuildShl(ctx->builder,
1403 LLVMBuildSub(ctx->builder,
1404 LLVMBuildShl(ctx->builder,
1405 ctx->i32_1,
1406 src3, ""),
1407 ctx->i32_1, ""),
1408 src2, "");
1409 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1410 bfi_args[2] = src0;
1411
1412 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1413
1414 /* Calculate:
1415 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1416 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1417 */
1418 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1419 LLVMBuildAnd(ctx->builder, bfi_args[0],
1420 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1421
1422 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1423 return result;
1424 }
1425
1426 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1427 LLVMValueRef src0)
1428 {
1429 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1430 int i;
1431 LLVMValueRef comp[2];
1432
1433 src0 = ac_to_float(ctx, src0);
1434 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1435 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1436 for (i = 0; i < 2; i++) {
1437 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1438 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1439 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1440 }
1441
1442 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1443 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1444
1445 return comp[0];
1446 }
1447
1448 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1449 LLVMValueRef src0)
1450 {
1451 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1452 LLVMValueRef temps[2], result, val;
1453 int i;
1454
1455 for (i = 0; i < 2; i++) {
1456 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1457 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1458 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1459 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1460 }
1461
1462 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1463 ctx->i32_0, "");
1464 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1465 ctx->i32_1, "");
1466 return result;
1467 }
1468
1469 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1470 nir_op op,
1471 LLVMValueRef src0)
1472 {
1473 unsigned mask;
1474 int idx;
1475 LLVMValueRef result;
1476
1477 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1478 mask = AC_TID_MASK_LEFT;
1479 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1480 mask = AC_TID_MASK_TOP;
1481 else
1482 mask = AC_TID_MASK_TOP_LEFT;
1483
1484 /* for DDX we want to next X pixel, DDY next Y pixel. */
1485 if (op == nir_op_fddx_fine ||
1486 op == nir_op_fddx_coarse ||
1487 op == nir_op_fddx)
1488 idx = 1;
1489 else
1490 idx = 2;
1491
1492 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1493 return result;
1494 }
1495
1496 /*
1497 * this takes an I,J coordinate pair,
1498 * and works out the X and Y derivatives.
1499 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1500 */
1501 static LLVMValueRef emit_ddxy_interp(
1502 struct ac_nir_context *ctx,
1503 LLVMValueRef interp_ij)
1504 {
1505 LLVMValueRef result[4], a;
1506 unsigned i;
1507
1508 for (i = 0; i < 2; i++) {
1509 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1510 LLVMConstInt(ctx->ac.i32, i, false), "");
1511 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1512 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1513 }
1514 return ac_build_gather_values(&ctx->ac, result, 4);
1515 }
1516
1517 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1518 {
1519 LLVMValueRef src[4], result = NULL;
1520 unsigned num_components = instr->dest.dest.ssa.num_components;
1521 unsigned src_components;
1522 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1523
1524 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1525 switch (instr->op) {
1526 case nir_op_vec2:
1527 case nir_op_vec3:
1528 case nir_op_vec4:
1529 src_components = 1;
1530 break;
1531 case nir_op_pack_half_2x16:
1532 src_components = 2;
1533 break;
1534 case nir_op_unpack_half_2x16:
1535 src_components = 1;
1536 break;
1537 default:
1538 src_components = num_components;
1539 break;
1540 }
1541 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1542 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1543
1544 switch (instr->op) {
1545 case nir_op_fmov:
1546 case nir_op_imov:
1547 result = src[0];
1548 break;
1549 case nir_op_fneg:
1550 src[0] = ac_to_float(&ctx->ac, src[0]);
1551 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1552 break;
1553 case nir_op_ineg:
1554 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1555 break;
1556 case nir_op_inot:
1557 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1558 break;
1559 case nir_op_iadd:
1560 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1561 break;
1562 case nir_op_fadd:
1563 src[0] = ac_to_float(&ctx->ac, src[0]);
1564 src[1] = ac_to_float(&ctx->ac, src[1]);
1565 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1566 break;
1567 case nir_op_fsub:
1568 src[0] = ac_to_float(&ctx->ac, src[0]);
1569 src[1] = ac_to_float(&ctx->ac, src[1]);
1570 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1571 break;
1572 case nir_op_isub:
1573 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1574 break;
1575 case nir_op_imul:
1576 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1577 break;
1578 case nir_op_imod:
1579 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1580 break;
1581 case nir_op_umod:
1582 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1583 break;
1584 case nir_op_fmod:
1585 src[0] = ac_to_float(&ctx->ac, src[0]);
1586 src[1] = ac_to_float(&ctx->ac, src[1]);
1587 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1588 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1589 ac_to_float_type(&ctx->ac, def_type), result);
1590 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1591 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1592 break;
1593 case nir_op_frem:
1594 src[0] = ac_to_float(&ctx->ac, src[0]);
1595 src[1] = ac_to_float(&ctx->ac, src[1]);
1596 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1597 break;
1598 case nir_op_irem:
1599 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1600 break;
1601 case nir_op_idiv:
1602 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1603 break;
1604 case nir_op_udiv:
1605 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1606 break;
1607 case nir_op_fmul:
1608 src[0] = ac_to_float(&ctx->ac, src[0]);
1609 src[1] = ac_to_float(&ctx->ac, src[1]);
1610 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1611 break;
1612 case nir_op_fdiv:
1613 src[0] = ac_to_float(&ctx->ac, src[0]);
1614 src[1] = ac_to_float(&ctx->ac, src[1]);
1615 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1616 break;
1617 case nir_op_frcp:
1618 src[0] = ac_to_float(&ctx->ac, src[0]);
1619 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1620 break;
1621 case nir_op_iand:
1622 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1623 break;
1624 case nir_op_ior:
1625 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1626 break;
1627 case nir_op_ixor:
1628 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1629 break;
1630 case nir_op_ishl:
1631 result = LLVMBuildShl(ctx->ac.builder, src[0],
1632 LLVMBuildZExt(ctx->ac.builder, src[1],
1633 LLVMTypeOf(src[0]), ""),
1634 "");
1635 break;
1636 case nir_op_ishr:
1637 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1638 LLVMBuildZExt(ctx->ac.builder, src[1],
1639 LLVMTypeOf(src[0]), ""),
1640 "");
1641 break;
1642 case nir_op_ushr:
1643 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1644 LLVMBuildZExt(ctx->ac.builder, src[1],
1645 LLVMTypeOf(src[0]), ""),
1646 "");
1647 break;
1648 case nir_op_ilt:
1649 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1650 break;
1651 case nir_op_ine:
1652 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1653 break;
1654 case nir_op_ieq:
1655 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1656 break;
1657 case nir_op_ige:
1658 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1659 break;
1660 case nir_op_ult:
1661 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1662 break;
1663 case nir_op_uge:
1664 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1665 break;
1666 case nir_op_feq:
1667 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1668 break;
1669 case nir_op_fne:
1670 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1671 break;
1672 case nir_op_flt:
1673 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1674 break;
1675 case nir_op_fge:
1676 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1677 break;
1678 case nir_op_fabs:
1679 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1680 ac_to_float_type(&ctx->ac, def_type), src[0]);
1681 break;
1682 case nir_op_iabs:
1683 result = emit_iabs(&ctx->ac, src[0]);
1684 break;
1685 case nir_op_imax:
1686 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1687 break;
1688 case nir_op_imin:
1689 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1690 break;
1691 case nir_op_umax:
1692 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1693 break;
1694 case nir_op_umin:
1695 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1696 break;
1697 case nir_op_isign:
1698 result = emit_isign(&ctx->ac, src[0]);
1699 break;
1700 case nir_op_fsign:
1701 src[0] = ac_to_float(&ctx->ac, src[0]);
1702 result = emit_fsign(&ctx->ac, src[0]);
1703 break;
1704 case nir_op_ffloor:
1705 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1706 ac_to_float_type(&ctx->ac, def_type), src[0]);
1707 break;
1708 case nir_op_ftrunc:
1709 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1710 ac_to_float_type(&ctx->ac, def_type), src[0]);
1711 break;
1712 case nir_op_fceil:
1713 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1714 ac_to_float_type(&ctx->ac, def_type), src[0]);
1715 break;
1716 case nir_op_fround_even:
1717 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1718 ac_to_float_type(&ctx->ac, def_type),src[0]);
1719 break;
1720 case nir_op_ffract:
1721 result = emit_ffract(&ctx->ac, src[0]);
1722 break;
1723 case nir_op_fsin:
1724 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1725 ac_to_float_type(&ctx->ac, def_type), src[0]);
1726 break;
1727 case nir_op_fcos:
1728 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1729 ac_to_float_type(&ctx->ac, def_type), src[0]);
1730 break;
1731 case nir_op_fsqrt:
1732 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1733 ac_to_float_type(&ctx->ac, def_type), src[0]);
1734 break;
1735 case nir_op_fexp2:
1736 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1737 ac_to_float_type(&ctx->ac, def_type), src[0]);
1738 break;
1739 case nir_op_flog2:
1740 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1741 ac_to_float_type(&ctx->ac, def_type), src[0]);
1742 break;
1743 case nir_op_frsq:
1744 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1745 ac_to_float_type(&ctx->ac, def_type), src[0]);
1746 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1747 break;
1748 case nir_op_fpow:
1749 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1750 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1751 break;
1752 case nir_op_fmax:
1753 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1754 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1755 if (instr->dest.dest.ssa.bit_size == 32)
1756 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1757 ac_to_float_type(&ctx->ac, def_type),
1758 result);
1759 break;
1760 case nir_op_fmin:
1761 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1762 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1763 if (instr->dest.dest.ssa.bit_size == 32)
1764 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1765 ac_to_float_type(&ctx->ac, def_type),
1766 result);
1767 break;
1768 case nir_op_ffma:
1769 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1770 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1771 break;
1772 case nir_op_ibitfield_extract:
1773 result = emit_bitfield_extract(&ctx->ac, true, src);
1774 break;
1775 case nir_op_ubitfield_extract:
1776 result = emit_bitfield_extract(&ctx->ac, false, src);
1777 break;
1778 case nir_op_bitfield_insert:
1779 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1780 break;
1781 case nir_op_bitfield_reverse:
1782 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1783 break;
1784 case nir_op_bit_count:
1785 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1786 break;
1787 case nir_op_vec2:
1788 case nir_op_vec3:
1789 case nir_op_vec4:
1790 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1791 src[i] = ac_to_integer(&ctx->ac, src[i]);
1792 result = ac_build_gather_values(&ctx->ac, src, num_components);
1793 break;
1794 case nir_op_f2i32:
1795 case nir_op_f2i64:
1796 src[0] = ac_to_float(&ctx->ac, src[0]);
1797 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1798 break;
1799 case nir_op_f2u32:
1800 case nir_op_f2u64:
1801 src[0] = ac_to_float(&ctx->ac, src[0]);
1802 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1803 break;
1804 case nir_op_i2f32:
1805 case nir_op_i2f64:
1806 src[0] = ac_to_integer(&ctx->ac, src[0]);
1807 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1808 break;
1809 case nir_op_u2f32:
1810 case nir_op_u2f64:
1811 src[0] = ac_to_integer(&ctx->ac, src[0]);
1812 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1813 break;
1814 case nir_op_f2f64:
1815 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1816 break;
1817 case nir_op_f2f32:
1818 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1819 break;
1820 case nir_op_u2u32:
1821 case nir_op_u2u64:
1822 src[0] = ac_to_integer(&ctx->ac, src[0]);
1823 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1824 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1825 else
1826 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1827 break;
1828 case nir_op_i2i32:
1829 case nir_op_i2i64:
1830 src[0] = ac_to_integer(&ctx->ac, src[0]);
1831 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1832 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1833 else
1834 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1835 break;
1836 case nir_op_bcsel:
1837 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1838 break;
1839 case nir_op_find_lsb:
1840 src[0] = ac_to_integer(&ctx->ac, src[0]);
1841 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1842 break;
1843 case nir_op_ufind_msb:
1844 src[0] = ac_to_integer(&ctx->ac, src[0]);
1845 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1846 break;
1847 case nir_op_ifind_msb:
1848 src[0] = ac_to_integer(&ctx->ac, src[0]);
1849 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1850 break;
1851 case nir_op_uadd_carry:
1852 src[0] = ac_to_integer(&ctx->ac, src[0]);
1853 src[1] = ac_to_integer(&ctx->ac, src[1]);
1854 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1855 break;
1856 case nir_op_usub_borrow:
1857 src[0] = ac_to_integer(&ctx->ac, src[0]);
1858 src[1] = ac_to_integer(&ctx->ac, src[1]);
1859 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1860 break;
1861 case nir_op_b2f:
1862 result = emit_b2f(&ctx->ac, src[0]);
1863 break;
1864 case nir_op_f2b:
1865 result = emit_f2b(&ctx->ac, src[0]);
1866 break;
1867 case nir_op_b2i:
1868 result = emit_b2i(&ctx->ac, src[0]);
1869 break;
1870 case nir_op_i2b:
1871 src[0] = ac_to_integer(&ctx->ac, src[0]);
1872 result = emit_i2b(&ctx->ac, src[0]);
1873 break;
1874 case nir_op_fquantize2f16:
1875 result = emit_f2f16(ctx->nctx, src[0]);
1876 break;
1877 case nir_op_umul_high:
1878 src[0] = ac_to_integer(&ctx->ac, src[0]);
1879 src[1] = ac_to_integer(&ctx->ac, src[1]);
1880 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1881 break;
1882 case nir_op_imul_high:
1883 src[0] = ac_to_integer(&ctx->ac, src[0]);
1884 src[1] = ac_to_integer(&ctx->ac, src[1]);
1885 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1886 break;
1887 case nir_op_pack_half_2x16:
1888 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1889 break;
1890 case nir_op_unpack_half_2x16:
1891 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1892 break;
1893 case nir_op_fddx:
1894 case nir_op_fddy:
1895 case nir_op_fddx_fine:
1896 case nir_op_fddy_fine:
1897 case nir_op_fddx_coarse:
1898 case nir_op_fddy_coarse:
1899 result = emit_ddxy(ctx, instr->op, src[0]);
1900 break;
1901
1902 case nir_op_unpack_64_2x32_split_x: {
1903 assert(instr->src[0].src.ssa->num_components == 1);
1904 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1905 ctx->ac.v2i32,
1906 "");
1907 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1908 ctx->ac.i32_0, "");
1909 break;
1910 }
1911
1912 case nir_op_unpack_64_2x32_split_y: {
1913 assert(instr->src[0].src.ssa->num_components == 1);
1914 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1915 ctx->ac.v2i32,
1916 "");
1917 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1918 ctx->ac.i32_1, "");
1919 break;
1920 }
1921
1922 case nir_op_pack_64_2x32_split: {
1923 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
1924 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1925 src[0], ctx->ac.i32_0, "");
1926 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1927 src[1], ctx->ac.i32_1, "");
1928 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1929 break;
1930 }
1931
1932 default:
1933 fprintf(stderr, "Unknown NIR alu instr: ");
1934 nir_print_instr(&instr->instr, stderr);
1935 fprintf(stderr, "\n");
1936 abort();
1937 }
1938
1939 if (result) {
1940 assert(instr->dest.dest.is_ssa);
1941 result = ac_to_integer(&ctx->ac, result);
1942 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1943 result);
1944 }
1945 }
1946
1947 static void visit_load_const(struct ac_nir_context *ctx,
1948 const nir_load_const_instr *instr)
1949 {
1950 LLVMValueRef values[4], value = NULL;
1951 LLVMTypeRef element_type =
1952 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1953
1954 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1955 switch (instr->def.bit_size) {
1956 case 32:
1957 values[i] = LLVMConstInt(element_type,
1958 instr->value.u32[i], false);
1959 break;
1960 case 64:
1961 values[i] = LLVMConstInt(element_type,
1962 instr->value.u64[i], false);
1963 break;
1964 default:
1965 fprintf(stderr,
1966 "unsupported nir load_const bit_size: %d\n",
1967 instr->def.bit_size);
1968 abort();
1969 }
1970 }
1971 if (instr->def.num_components > 1) {
1972 value = LLVMConstVector(values, instr->def.num_components);
1973 } else
1974 value = values[0];
1975
1976 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1977 }
1978
1979 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1980 LLVMTypeRef type)
1981 {
1982 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1983 return LLVMBuildBitCast(ctx->builder, ptr,
1984 LLVMPointerType(type, addr_space), "");
1985 }
1986
1987 static LLVMValueRef
1988 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1989 {
1990 LLVMValueRef size =
1991 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1992 LLVMConstInt(ctx->ac.i32, 2, false), "");
1993
1994 /* VI only */
1995 if (ctx->ac.chip_class == VI && in_elements) {
1996 /* On VI, the descriptor contains the size in bytes,
1997 * but TXQ must return the size in elements.
1998 * The stride is always non-zero for resources using TXQ.
1999 */
2000 LLVMValueRef stride =
2001 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2002 LLVMConstInt(ctx->ac.i32, 1, false), "");
2003 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2004 LLVMConstInt(ctx->ac.i32, 16, false), "");
2005 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2006 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2007
2008 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2009 }
2010 return size;
2011 }
2012
2013 /**
2014 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2015 * intrinsic names).
2016 */
2017 static void build_int_type_name(
2018 LLVMTypeRef type,
2019 char *buf, unsigned bufsize)
2020 {
2021 assert(bufsize >= 6);
2022
2023 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2024 snprintf(buf, bufsize, "v%ui32",
2025 LLVMGetVectorSize(type));
2026 else
2027 strcpy(buf, "i32");
2028 }
2029
2030 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2031 struct ac_image_args *args,
2032 const nir_tex_instr *instr)
2033 {
2034 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2035 LLVMValueRef coord = args->addr;
2036 LLVMValueRef half_texel[2];
2037 LLVMValueRef compare_cube_wa = NULL;
2038 LLVMValueRef result;
2039 int c;
2040 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2041
2042 //TODO Rect
2043 {
2044 struct ac_image_args txq_args = { 0 };
2045
2046 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2047 txq_args.opcode = ac_image_get_resinfo;
2048 txq_args.dmask = 0xf;
2049 txq_args.addr = ctx->i32_0;
2050 txq_args.resource = args->resource;
2051 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2052
2053 for (c = 0; c < 2; c++) {
2054 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2055 LLVMConstInt(ctx->i32, c, false), "");
2056 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2057 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2058 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2059 LLVMConstReal(ctx->f32, -0.5), "");
2060 }
2061 }
2062
2063 LLVMValueRef orig_coords = args->addr;
2064
2065 for (c = 0; c < 2; c++) {
2066 LLVMValueRef tmp;
2067 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2068 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2069 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2070 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2071 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2072 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2073 }
2074
2075
2076 /*
2077 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2078 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2079 * workaround by sampling using a scaled type and converting.
2080 * This is taken from amdgpu-pro shaders.
2081 */
2082 /* NOTE this produces some ugly code compared to amdgpu-pro,
2083 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2084 * and then reads them back. -pro generates two selects,
2085 * one s_cmp for the descriptor rewriting
2086 * one v_cmp for the coordinate and result changes.
2087 */
2088 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2089 LLVMValueRef tmp, tmp2;
2090
2091 /* workaround 8/8/8/8 uint/sint cube gather bug */
2092 /* first detect it then change to a scaled read and f2i */
2093 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2094 tmp2 = tmp;
2095
2096 /* extract the DATA_FORMAT */
2097 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2098 LLVMConstInt(ctx->i32, 6, false), false);
2099
2100 /* is the DATA_FORMAT == 8_8_8_8 */
2101 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2102
2103 if (stype == GLSL_TYPE_UINT)
2104 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2105 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2106 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2107 else
2108 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2109 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2110 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2111
2112 /* replace the NUM FORMAT in the descriptor */
2113 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2114 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2115
2116 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2117
2118 /* don't modify the coordinates for this case */
2119 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2120 }
2121 args->addr = coord;
2122 result = ac_build_image_opcode(ctx, args);
2123
2124 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2125 LLVMValueRef tmp, tmp2;
2126
2127 /* if the cube workaround is in place, f2i the result. */
2128 for (c = 0; c < 4; c++) {
2129 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2130 if (stype == GLSL_TYPE_UINT)
2131 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2132 else
2133 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2134 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2135 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2136 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2137 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2138 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2139 }
2140 }
2141 return result;
2142 }
2143
2144 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2145 const nir_tex_instr *instr,
2146 bool lod_is_zero,
2147 struct ac_image_args *args)
2148 {
2149 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2150 return ac_build_buffer_load_format(&ctx->ac,
2151 args->resource,
2152 args->addr,
2153 LLVMConstInt(ctx->ac.i32, 0, false),
2154 true);
2155 }
2156
2157 args->opcode = ac_image_sample;
2158 args->compare = instr->is_shadow;
2159
2160 switch (instr->op) {
2161 case nir_texop_txf:
2162 case nir_texop_txf_ms:
2163 case nir_texop_samples_identical:
2164 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2165 args->compare = false;
2166 args->offset = false;
2167 break;
2168 case nir_texop_txb:
2169 args->bias = true;
2170 break;
2171 case nir_texop_txl:
2172 if (lod_is_zero)
2173 args->level_zero = true;
2174 else
2175 args->lod = true;
2176 break;
2177 case nir_texop_txs:
2178 case nir_texop_query_levels:
2179 args->opcode = ac_image_get_resinfo;
2180 break;
2181 case nir_texop_tex:
2182 if (ctx->stage != MESA_SHADER_FRAGMENT)
2183 args->level_zero = true;
2184 break;
2185 case nir_texop_txd:
2186 args->deriv = true;
2187 break;
2188 case nir_texop_tg4:
2189 args->opcode = ac_image_gather4;
2190 args->level_zero = true;
2191 break;
2192 case nir_texop_lod:
2193 args->opcode = ac_image_get_lod;
2194 args->compare = false;
2195 args->offset = false;
2196 break;
2197 default:
2198 break;
2199 }
2200
2201 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2202 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2203 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2204 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2205 }
2206 }
2207 return ac_build_image_opcode(&ctx->ac, args);
2208 }
2209
2210 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2211 nir_intrinsic_instr *instr)
2212 {
2213 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2214 unsigned desc_set = nir_intrinsic_desc_set(instr);
2215 unsigned binding = nir_intrinsic_binding(instr);
2216 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2217 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2218 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2219 unsigned base_offset = layout->binding[binding].offset;
2220 LLVMValueRef offset, stride;
2221
2222 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2223 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2224 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2225 layout->binding[binding].dynamic_offset_offset;
2226 desc_ptr = ctx->push_constants;
2227 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2228 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2229 } else
2230 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2231
2232 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2233 index = LLVMBuildMul(ctx->builder, index, stride, "");
2234 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2235
2236 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2237 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2238 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2239
2240 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2241 }
2242
2243 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2244 nir_intrinsic_instr *instr)
2245 {
2246 LLVMValueRef ptr, addr;
2247
2248 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2249 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2250
2251 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2252 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2253
2254 return LLVMBuildLoad(ctx->builder, ptr, "");
2255 }
2256
2257 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2258 const nir_intrinsic_instr *instr)
2259 {
2260 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2261
2262 return get_buffer_size(ctx, desc, false);
2263 }
2264 static void visit_store_ssbo(struct ac_nir_context *ctx,
2265 nir_intrinsic_instr *instr)
2266 {
2267 const char *store_name;
2268 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2269 LLVMTypeRef data_type = ctx->ac.f32;
2270 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2271 int components_32bit = elem_size_mult * instr->num_components;
2272 unsigned writemask = nir_intrinsic_write_mask(instr);
2273 LLVMValueRef base_data, base_offset;
2274 LLVMValueRef params[6];
2275
2276 params[1] = ctx->abi->load_ssbo(ctx->abi,
2277 get_src(ctx, instr->src[1]), true);
2278 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2279 params[4] = ctx->ac.i1false; /* glc */
2280 params[5] = ctx->ac.i1false; /* slc */
2281
2282 if (components_32bit > 1)
2283 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2284
2285 base_data = ac_to_float(&ctx->ac, src_data);
2286 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2287 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2288 data_type, "");
2289 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2290 while (writemask) {
2291 int start, count;
2292 LLVMValueRef data;
2293 LLVMValueRef offset;
2294 LLVMValueRef tmp;
2295 u_bit_scan_consecutive_range(&writemask, &start, &count);
2296
2297 /* Due to an LLVM limitation, split 3-element writes
2298 * into a 2-element and a 1-element write. */
2299 if (count == 3) {
2300 writemask |= 1 << (start + 2);
2301 count = 2;
2302 }
2303
2304 start *= elem_size_mult;
2305 count *= elem_size_mult;
2306
2307 if (count > 4) {
2308 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2309 count = 4;
2310 }
2311
2312 if (count == 4) {
2313 store_name = "llvm.amdgcn.buffer.store.v4f32";
2314 data = base_data;
2315 } else if (count == 2) {
2316 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2317 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2318 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2319 ctx->ac.i32_0, "");
2320
2321 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2322 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2323 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2324 ctx->ac.i32_1, "");
2325 store_name = "llvm.amdgcn.buffer.store.v2f32";
2326
2327 } else {
2328 assert(count == 1);
2329 if (get_llvm_num_components(base_data) > 1)
2330 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2331 LLVMConstInt(ctx->ac.i32, start, false), "");
2332 else
2333 data = base_data;
2334 store_name = "llvm.amdgcn.buffer.store.f32";
2335 }
2336
2337 offset = base_offset;
2338 if (start != 0) {
2339 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2340 }
2341 params[0] = data;
2342 params[3] = offset;
2343 ac_build_intrinsic(&ctx->ac, store_name,
2344 ctx->ac.voidt, params, 6, 0);
2345 }
2346 }
2347
2348 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2349 const nir_intrinsic_instr *instr)
2350 {
2351 const char *name;
2352 LLVMValueRef params[6];
2353 int arg_count = 0;
2354
2355 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2356 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2357 }
2358 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2359 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2360 get_src(ctx, instr->src[0]),
2361 true);
2362 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2363 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2364 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2365
2366 switch (instr->intrinsic) {
2367 case nir_intrinsic_ssbo_atomic_add:
2368 name = "llvm.amdgcn.buffer.atomic.add";
2369 break;
2370 case nir_intrinsic_ssbo_atomic_imin:
2371 name = "llvm.amdgcn.buffer.atomic.smin";
2372 break;
2373 case nir_intrinsic_ssbo_atomic_umin:
2374 name = "llvm.amdgcn.buffer.atomic.umin";
2375 break;
2376 case nir_intrinsic_ssbo_atomic_imax:
2377 name = "llvm.amdgcn.buffer.atomic.smax";
2378 break;
2379 case nir_intrinsic_ssbo_atomic_umax:
2380 name = "llvm.amdgcn.buffer.atomic.umax";
2381 break;
2382 case nir_intrinsic_ssbo_atomic_and:
2383 name = "llvm.amdgcn.buffer.atomic.and";
2384 break;
2385 case nir_intrinsic_ssbo_atomic_or:
2386 name = "llvm.amdgcn.buffer.atomic.or";
2387 break;
2388 case nir_intrinsic_ssbo_atomic_xor:
2389 name = "llvm.amdgcn.buffer.atomic.xor";
2390 break;
2391 case nir_intrinsic_ssbo_atomic_exchange:
2392 name = "llvm.amdgcn.buffer.atomic.swap";
2393 break;
2394 case nir_intrinsic_ssbo_atomic_comp_swap:
2395 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2396 break;
2397 default:
2398 abort();
2399 }
2400
2401 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2402 }
2403
2404 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2405 const nir_intrinsic_instr *instr)
2406 {
2407 LLVMValueRef results[2];
2408 int load_components;
2409 int num_components = instr->num_components;
2410 if (instr->dest.ssa.bit_size == 64)
2411 num_components *= 2;
2412
2413 for (int i = 0; i < num_components; i += load_components) {
2414 load_components = MIN2(num_components - i, 4);
2415 const char *load_name;
2416 LLVMTypeRef data_type = ctx->ac.f32;
2417 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2418 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2419
2420 if (load_components == 3)
2421 data_type = LLVMVectorType(ctx->ac.f32, 4);
2422 else if (load_components > 1)
2423 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2424
2425 if (load_components >= 3)
2426 load_name = "llvm.amdgcn.buffer.load.v4f32";
2427 else if (load_components == 2)
2428 load_name = "llvm.amdgcn.buffer.load.v2f32";
2429 else if (load_components == 1)
2430 load_name = "llvm.amdgcn.buffer.load.f32";
2431 else
2432 unreachable("unhandled number of components");
2433
2434 LLVMValueRef params[] = {
2435 ctx->abi->load_ssbo(ctx->abi,
2436 get_src(ctx, instr->src[0]),
2437 false),
2438 LLVMConstInt(ctx->ac.i32, 0, false),
2439 offset,
2440 ctx->ac.i1false,
2441 ctx->ac.i1false,
2442 };
2443
2444 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2445
2446 }
2447
2448 assume(results[0]);
2449 LLVMValueRef ret = results[0];
2450 if (num_components > 4 || num_components == 3) {
2451 LLVMValueRef masks[] = {
2452 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2453 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2454 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2455 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2456 };
2457
2458 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2459 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2460 results[num_components > 4 ? 1 : 0], swizzle, "");
2461 }
2462
2463 return LLVMBuildBitCast(ctx->ac.builder, ret,
2464 get_def_type(ctx, &instr->dest.ssa), "");
2465 }
2466
2467 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2468 const nir_intrinsic_instr *instr)
2469 {
2470 LLVMValueRef results[8], ret;
2471 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2472 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2473 int num_components = instr->num_components;
2474
2475 if (ctx->abi->load_ubo)
2476 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2477
2478 if (instr->dest.ssa.bit_size == 64)
2479 num_components *= 2;
2480
2481 for (unsigned i = 0; i < num_components; ++i) {
2482 LLVMValueRef params[] = {
2483 rsrc,
2484 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2485 offset, "")
2486 };
2487 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2488 params, 2,
2489 AC_FUNC_ATTR_READNONE |
2490 AC_FUNC_ATTR_LEGACY);
2491 }
2492
2493
2494 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2495 return LLVMBuildBitCast(ctx->ac.builder, ret,
2496 get_def_type(ctx, &instr->dest.ssa), "");
2497 }
2498
2499 static void
2500 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2501 bool vs_in, unsigned *vertex_index_out,
2502 LLVMValueRef *vertex_index_ref,
2503 unsigned *const_out, LLVMValueRef *indir_out)
2504 {
2505 unsigned const_offset = 0;
2506 nir_deref *tail = &deref->deref;
2507 LLVMValueRef offset = NULL;
2508
2509 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2510 tail = tail->child;
2511 nir_deref_array *deref_array = nir_deref_as_array(tail);
2512 if (vertex_index_out)
2513 *vertex_index_out = deref_array->base_offset;
2514
2515 if (vertex_index_ref) {
2516 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2517 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2518 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2519 }
2520 *vertex_index_ref = vtx;
2521 }
2522 }
2523
2524 if (deref->var->data.compact) {
2525 assert(tail->child->deref_type == nir_deref_type_array);
2526 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2527 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2528 /* We always lower indirect dereferences for "compact" array vars. */
2529 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2530
2531 const_offset = deref_array->base_offset;
2532 goto out;
2533 }
2534
2535 while (tail->child != NULL) {
2536 const struct glsl_type *parent_type = tail->type;
2537 tail = tail->child;
2538
2539 if (tail->deref_type == nir_deref_type_array) {
2540 nir_deref_array *deref_array = nir_deref_as_array(tail);
2541 LLVMValueRef index, stride, local_offset;
2542 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2543
2544 const_offset += size * deref_array->base_offset;
2545 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2546 continue;
2547
2548 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2549 index = get_src(ctx, deref_array->indirect);
2550 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2551 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2552
2553 if (offset)
2554 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2555 else
2556 offset = local_offset;
2557 } else if (tail->deref_type == nir_deref_type_struct) {
2558 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2559
2560 for (unsigned i = 0; i < deref_struct->index; i++) {
2561 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2562 const_offset += glsl_count_attribute_slots(ft, vs_in);
2563 }
2564 } else
2565 unreachable("unsupported deref type");
2566
2567 }
2568 out:
2569 if (const_offset && offset)
2570 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2571 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2572 "");
2573
2574 *const_out = const_offset;
2575 *indir_out = offset;
2576 }
2577
2578
2579 /* The offchip buffer layout for TCS->TES is
2580 *
2581 * - attribute 0 of patch 0 vertex 0
2582 * - attribute 0 of patch 0 vertex 1
2583 * - attribute 0 of patch 0 vertex 2
2584 * ...
2585 * - attribute 0 of patch 1 vertex 0
2586 * - attribute 0 of patch 1 vertex 1
2587 * ...
2588 * - attribute 1 of patch 0 vertex 0
2589 * - attribute 1 of patch 0 vertex 1
2590 * ...
2591 * - per patch attribute 0 of patch 0
2592 * - per patch attribute 0 of patch 1
2593 * ...
2594 *
2595 * Note that every attribute has 4 components.
2596 */
2597 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2598 LLVMValueRef vertex_index,
2599 LLVMValueRef param_index)
2600 {
2601 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2602 LLVMValueRef param_stride, constant16;
2603 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2604
2605 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2606 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2607 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2608 num_patches, "");
2609
2610 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2611 if (vertex_index) {
2612 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2613 vertices_per_patch, "");
2614
2615 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2616 vertex_index, "");
2617
2618 param_stride = total_vertices;
2619 } else {
2620 base_addr = rel_patch_id;
2621 param_stride = num_patches;
2622 }
2623
2624 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2625 LLVMBuildMul(ctx->builder, param_index,
2626 param_stride, ""), "");
2627
2628 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2629
2630 if (!vertex_index) {
2631 LLVMValueRef patch_data_offset =
2632 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2633
2634 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2635 patch_data_offset, "");
2636 }
2637 return base_addr;
2638 }
2639
2640 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2641 unsigned param,
2642 unsigned const_index,
2643 bool is_compact,
2644 LLVMValueRef vertex_index,
2645 LLVMValueRef indir_index)
2646 {
2647 LLVMValueRef param_index;
2648
2649 if (indir_index)
2650 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2651 indir_index, "");
2652 else {
2653 if (const_index && !is_compact)
2654 param += const_index;
2655 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2656 }
2657 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2658 }
2659
2660 static void
2661 mark_tess_output(struct nir_to_llvm_context *ctx,
2662 bool is_patch, uint32_t param)
2663
2664 {
2665 if (is_patch) {
2666 ctx->tess_patch_outputs_written |= (1ull << param);
2667 } else
2668 ctx->tess_outputs_written |= (1ull << param);
2669 }
2670
2671 static LLVMValueRef
2672 get_dw_address(struct nir_to_llvm_context *ctx,
2673 LLVMValueRef dw_addr,
2674 unsigned param,
2675 unsigned const_index,
2676 bool compact_const_index,
2677 LLVMValueRef vertex_index,
2678 LLVMValueRef stride,
2679 LLVMValueRef indir_index)
2680
2681 {
2682
2683 if (vertex_index) {
2684 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2685 LLVMBuildMul(ctx->builder,
2686 vertex_index,
2687 stride, ""), "");
2688 }
2689
2690 if (indir_index)
2691 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2692 LLVMBuildMul(ctx->builder, indir_index,
2693 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2694 else if (const_index && !compact_const_index)
2695 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2696 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2697
2698 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2699 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2700
2701 if (const_index && compact_const_index)
2702 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2703 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2704 return dw_addr;
2705 }
2706
2707 static LLVMValueRef
2708 load_tcs_input(struct nir_to_llvm_context *ctx,
2709 nir_intrinsic_instr *instr)
2710 {
2711 LLVMValueRef dw_addr, stride;
2712 unsigned const_index;
2713 LLVMValueRef vertex_index;
2714 LLVMValueRef indir_index;
2715 unsigned param;
2716 LLVMValueRef value[4], result;
2717 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2718 const bool is_compact = instr->variables[0]->var->data.compact;
2719 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2720 get_deref_offset(ctx->nir, instr->variables[0],
2721 false, NULL, per_vertex ? &vertex_index : NULL,
2722 &const_index, &indir_index);
2723
2724 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2725 dw_addr = get_tcs_in_current_patch_offset(ctx);
2726 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2727 indir_index);
2728
2729 unsigned comp = instr->variables[0]->var->data.location_frac;
2730 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2731 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2732 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2733 ctx->ac.i32_1, "");
2734 }
2735 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2736 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2737 return result;
2738 }
2739
2740 static LLVMValueRef
2741 load_tcs_output(struct nir_to_llvm_context *ctx,
2742 nir_intrinsic_instr *instr)
2743 {
2744 LLVMValueRef dw_addr;
2745 LLVMValueRef stride = NULL;
2746 LLVMValueRef value[4], result;
2747 LLVMValueRef vertex_index = NULL;
2748 LLVMValueRef indir_index = NULL;
2749 unsigned const_index = 0;
2750 unsigned param;
2751 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2752 const bool is_compact = instr->variables[0]->var->data.compact;
2753 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2754 get_deref_offset(ctx->nir, instr->variables[0],
2755 false, NULL, per_vertex ? &vertex_index : NULL,
2756 &const_index, &indir_index);
2757
2758 if (!instr->variables[0]->var->data.patch) {
2759 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2760 dw_addr = get_tcs_out_current_patch_offset(ctx);
2761 } else {
2762 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2763 }
2764
2765 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2766 indir_index);
2767
2768 unsigned comp = instr->variables[0]->var->data.location_frac;
2769 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2770 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2771 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2772 ctx->ac.i32_1, "");
2773 }
2774 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2775 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2776 return result;
2777 }
2778
2779 static void
2780 store_tcs_output(struct nir_to_llvm_context *ctx,
2781 nir_intrinsic_instr *instr,
2782 LLVMValueRef src,
2783 unsigned writemask)
2784 {
2785 LLVMValueRef dw_addr;
2786 LLVMValueRef stride = NULL;
2787 LLVMValueRef buf_addr = NULL;
2788 LLVMValueRef vertex_index = NULL;
2789 LLVMValueRef indir_index = NULL;
2790 unsigned const_index = 0;
2791 unsigned param;
2792 const unsigned comp = instr->variables[0]->var->data.location_frac;
2793 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2794 const bool is_compact = instr->variables[0]->var->data.compact;
2795 bool store_lds = true;
2796
2797 if (instr->variables[0]->var->data.patch) {
2798 if (!(ctx->tcs_patch_outputs_read & (1U << instr->variables[0]->var->data.location)))
2799 store_lds = false;
2800 } else {
2801 if (!(ctx->tcs_outputs_read & (1ULL << instr->variables[0]->var->data.location)))
2802 store_lds = false;
2803 }
2804 get_deref_offset(ctx->nir, instr->variables[0],
2805 false, NULL, per_vertex ? &vertex_index : NULL,
2806 &const_index, &indir_index);
2807
2808 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2809 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2810 is_compact && const_index > 3) {
2811 const_index -= 3;
2812 param++;
2813 }
2814
2815 if (!instr->variables[0]->var->data.patch) {
2816 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2817 dw_addr = get_tcs_out_current_patch_offset(ctx);
2818 } else {
2819 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2820 }
2821
2822 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2823
2824 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2825 indir_index);
2826 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2827 vertex_index, indir_index);
2828
2829 bool is_tess_factor = false;
2830 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2831 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2832 is_tess_factor = true;
2833
2834 unsigned base = is_compact ? const_index : 0;
2835 for (unsigned chan = 0; chan < 8; chan++) {
2836 if (!(writemask & (1 << chan)))
2837 continue;
2838 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2839
2840 if (store_lds || is_tess_factor)
2841 ac_lds_store(&ctx->ac, dw_addr, value);
2842
2843 if (!is_tess_factor && writemask != 0xF)
2844 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2845 buf_addr, ctx->oc_lds,
2846 4 * (base + chan), 1, 0, true, false);
2847
2848 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2849 ctx->ac.i32_1, "");
2850 }
2851
2852 if (writemask == 0xF) {
2853 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2854 buf_addr, ctx->oc_lds,
2855 (base * 4), 1, 0, true, false);
2856 }
2857 }
2858
2859 static LLVMValueRef
2860 load_tes_input(struct nir_to_llvm_context *ctx,
2861 const nir_intrinsic_instr *instr)
2862 {
2863 LLVMValueRef buf_addr;
2864 LLVMValueRef result;
2865 LLVMValueRef vertex_index = NULL;
2866 LLVMValueRef indir_index = NULL;
2867 unsigned const_index = 0;
2868 unsigned param;
2869 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2870 const bool is_compact = instr->variables[0]->var->data.compact;
2871
2872 get_deref_offset(ctx->nir, instr->variables[0],
2873 false, NULL, per_vertex ? &vertex_index : NULL,
2874 &const_index, &indir_index);
2875 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2876 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2877 is_compact && const_index > 3) {
2878 const_index -= 3;
2879 param++;
2880 }
2881
2882 unsigned comp = instr->variables[0]->var->data.location_frac;
2883 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2884 is_compact, vertex_index, indir_index);
2885
2886 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, comp * 4, false);
2887 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2888
2889 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2890 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2891 result = trim_vector(&ctx->ac, result, instr->num_components);
2892 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2893 return result;
2894 }
2895
2896 static LLVMValueRef
2897 load_gs_input(struct ac_shader_abi *abi,
2898 unsigned location,
2899 unsigned driver_location,
2900 unsigned component,
2901 unsigned num_components,
2902 unsigned vertex_index,
2903 unsigned const_index,
2904 LLVMTypeRef type)
2905 {
2906 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2907 LLVMValueRef vtx_offset;
2908 LLVMValueRef args[9];
2909 unsigned param, vtx_offset_param;
2910 LLVMValueRef value[4], result;
2911
2912 vtx_offset_param = vertex_index;
2913 assert(vtx_offset_param < 6);
2914 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2915 LLVMConstInt(ctx->ac.i32, 4, false), "");
2916
2917 param = shader_io_get_unique_index(location);
2918
2919 for (unsigned i = component; i < num_components + component; i++) {
2920 if (ctx->ac.chip_class >= GFX9) {
2921 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
2922 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2923 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
2924 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2925 } else {
2926 args[0] = ctx->esgs_ring;
2927 args[1] = vtx_offset;
2928 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
2929 args[3] = ctx->ac.i32_0;
2930 args[4] = ctx->ac.i32_1; /* OFFEN */
2931 args[5] = ctx->ac.i32_0; /* IDXEN */
2932 args[6] = ctx->ac.i32_1; /* GLC */
2933 args[7] = ctx->ac.i32_0; /* SLC */
2934 args[8] = ctx->ac.i32_0; /* TFE */
2935
2936 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2937 ctx->ac.i32, args, 9,
2938 AC_FUNC_ATTR_READONLY |
2939 AC_FUNC_ATTR_LEGACY);
2940 }
2941 }
2942 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2943
2944 return result;
2945 }
2946
2947 static LLVMValueRef
2948 build_gep_for_deref(struct ac_nir_context *ctx,
2949 nir_deref_var *deref)
2950 {
2951 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2952 assert(entry->data);
2953 LLVMValueRef val = entry->data;
2954 nir_deref *tail = deref->deref.child;
2955 while (tail != NULL) {
2956 LLVMValueRef offset;
2957 switch (tail->deref_type) {
2958 case nir_deref_type_array: {
2959 nir_deref_array *array = nir_deref_as_array(tail);
2960 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2961 if (array->deref_array_type ==
2962 nir_deref_array_type_indirect) {
2963 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2964 get_src(ctx,
2965 array->indirect),
2966 "");
2967 }
2968 break;
2969 }
2970 case nir_deref_type_struct: {
2971 nir_deref_struct *deref_struct =
2972 nir_deref_as_struct(tail);
2973 offset = LLVMConstInt(ctx->ac.i32,
2974 deref_struct->index, 0);
2975 break;
2976 }
2977 default:
2978 unreachable("bad deref type");
2979 }
2980 val = ac_build_gep0(&ctx->ac, val, offset);
2981 tail = tail->child;
2982 }
2983 return val;
2984 }
2985
2986 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
2987 nir_intrinsic_instr *instr)
2988 {
2989 LLVMValueRef values[8];
2990 int idx = instr->variables[0]->var->data.driver_location;
2991 int ve = instr->dest.ssa.num_components;
2992 unsigned comp = instr->variables[0]->var->data.location_frac;
2993 LLVMValueRef indir_index;
2994 LLVMValueRef ret;
2995 unsigned const_index;
2996 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2997 instr->variables[0]->var->data.mode == nir_var_shader_in;
2998 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2999 &const_index, &indir_index);
3000
3001 if (instr->dest.ssa.bit_size == 64)
3002 ve *= 2;
3003
3004 switch (instr->variables[0]->var->data.mode) {
3005 case nir_var_shader_in:
3006 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3007 return load_tcs_input(ctx->nctx, instr);
3008 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3009 return load_tes_input(ctx->nctx, instr);
3010 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3011 LLVMValueRef indir_index;
3012 unsigned const_index, vertex_index;
3013 get_deref_offset(ctx, instr->variables[0],
3014 false, &vertex_index, NULL,
3015 &const_index, &indir_index);
3016 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3017 instr->variables[0]->var->data.driver_location,
3018 instr->variables[0]->var->data.location_frac, ve,
3019 vertex_index, const_index,
3020 nir2llvmtype(ctx, instr->variables[0]->var->type));
3021 }
3022
3023 for (unsigned chan = comp; chan < ve + comp; chan++) {
3024 if (indir_index) {
3025 unsigned count = glsl_count_attribute_slots(
3026 instr->variables[0]->var->type,
3027 ctx->stage == MESA_SHADER_VERTEX);
3028 count -= chan / 4;
3029 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3030 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3031 4, false, true);
3032
3033 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3034 tmp_vec,
3035 indir_index, "");
3036 } else
3037 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3038 }
3039 break;
3040 case nir_var_local:
3041 for (unsigned chan = 0; chan < ve; chan++) {
3042 if (indir_index) {
3043 unsigned count = glsl_count_attribute_slots(
3044 instr->variables[0]->var->type, false);
3045 count -= chan / 4;
3046 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3047 &ctx->ac, ctx->locals + idx + chan, count,
3048 4, true, true);
3049
3050 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3051 tmp_vec,
3052 indir_index, "");
3053 } else {
3054 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3055 }
3056 }
3057 break;
3058 case nir_var_shared: {
3059 LLVMValueRef address = build_gep_for_deref(ctx,
3060 instr->variables[0]);
3061 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3062 return LLVMBuildBitCast(ctx->ac.builder, val,
3063 get_def_type(ctx, &instr->dest.ssa),
3064 "");
3065 }
3066 case nir_var_shader_out:
3067 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3068 return load_tcs_output(ctx->nctx, instr);
3069
3070 for (unsigned chan = comp; chan < ve + comp; chan++) {
3071 if (indir_index) {
3072 unsigned count = glsl_count_attribute_slots(
3073 instr->variables[0]->var->type, false);
3074 count -= chan / 4;
3075 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3076 &ctx->ac, ctx->outputs + idx + chan, count,
3077 4, true, true);
3078
3079 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3080 tmp_vec,
3081 indir_index, "");
3082 } else {
3083 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3084 ctx->outputs[idx + chan + const_index * 4],
3085 "");
3086 }
3087 }
3088 break;
3089 default:
3090 unreachable("unhandle variable mode");
3091 }
3092 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3093 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3094 }
3095
3096 static void
3097 visit_store_var(struct ac_nir_context *ctx,
3098 nir_intrinsic_instr *instr)
3099 {
3100 LLVMValueRef temp_ptr, value;
3101 int idx = instr->variables[0]->var->data.driver_location;
3102 unsigned comp = instr->variables[0]->var->data.location_frac;
3103 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3104 int writemask = instr->const_index[0] << comp;
3105 LLVMValueRef indir_index;
3106 unsigned const_index;
3107 get_deref_offset(ctx, instr->variables[0], false,
3108 NULL, NULL, &const_index, &indir_index);
3109
3110 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3111 int old_writemask = writemask;
3112
3113 src = LLVMBuildBitCast(ctx->ac.builder, src,
3114 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3115 "");
3116
3117 writemask = 0;
3118 for (unsigned chan = 0; chan < 4; chan++) {
3119 if (old_writemask & (1 << chan))
3120 writemask |= 3u << (2 * chan);
3121 }
3122 }
3123
3124 switch (instr->variables[0]->var->data.mode) {
3125 case nir_var_shader_out:
3126
3127 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3128 store_tcs_output(ctx->nctx, instr, src, writemask);
3129 return;
3130 }
3131
3132 for (unsigned chan = 0; chan < 8; chan++) {
3133 int stride = 4;
3134 if (!(writemask & (1 << chan)))
3135 continue;
3136
3137 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3138
3139 if (instr->variables[0]->var->data.compact)
3140 stride = 1;
3141 if (indir_index) {
3142 unsigned count = glsl_count_attribute_slots(
3143 instr->variables[0]->var->type, false);
3144 count -= chan / 4;
3145 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3146 &ctx->ac, ctx->outputs + idx + chan, count,
3147 stride, true, true);
3148
3149 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3150 value, indir_index, "");
3151 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3152 count, stride, tmp_vec);
3153
3154 } else {
3155 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3156
3157 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3158 }
3159 }
3160 break;
3161 case nir_var_local:
3162 for (unsigned chan = 0; chan < 8; chan++) {
3163 if (!(writemask & (1 << chan)))
3164 continue;
3165
3166 value = llvm_extract_elem(&ctx->ac, src, chan);
3167 if (indir_index) {
3168 unsigned count = glsl_count_attribute_slots(
3169 instr->variables[0]->var->type, false);
3170 count -= chan / 4;
3171 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3172 &ctx->ac, ctx->locals + idx + chan, count,
3173 4, true, true);
3174
3175 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3176 value, indir_index, "");
3177 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3178 count, 4, tmp_vec);
3179 } else {
3180 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3181
3182 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3183 }
3184 }
3185 break;
3186 case nir_var_shared: {
3187 int writemask = instr->const_index[0];
3188 LLVMValueRef address = build_gep_for_deref(ctx,
3189 instr->variables[0]);
3190 LLVMValueRef val = get_src(ctx, instr->src[0]);
3191 unsigned components =
3192 glsl_get_vector_elements(
3193 nir_deref_tail(&instr->variables[0]->deref)->type);
3194 if (writemask == (1 << components) - 1) {
3195 val = LLVMBuildBitCast(
3196 ctx->ac.builder, val,
3197 LLVMGetElementType(LLVMTypeOf(address)), "");
3198 LLVMBuildStore(ctx->ac.builder, val, address);
3199 } else {
3200 for (unsigned chan = 0; chan < 4; chan++) {
3201 if (!(writemask & (1 << chan)))
3202 continue;
3203 LLVMValueRef ptr =
3204 LLVMBuildStructGEP(ctx->ac.builder,
3205 address, chan, "");
3206 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3207 chan);
3208 src = LLVMBuildBitCast(
3209 ctx->ac.builder, src,
3210 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3211 LLVMBuildStore(ctx->ac.builder, src, ptr);
3212 }
3213 }
3214 break;
3215 }
3216 default:
3217 break;
3218 }
3219 }
3220
3221 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3222 {
3223 switch (dim) {
3224 case GLSL_SAMPLER_DIM_BUF:
3225 return 1;
3226 case GLSL_SAMPLER_DIM_1D:
3227 return array ? 2 : 1;
3228 case GLSL_SAMPLER_DIM_2D:
3229 return array ? 3 : 2;
3230 case GLSL_SAMPLER_DIM_MS:
3231 return array ? 4 : 3;
3232 case GLSL_SAMPLER_DIM_3D:
3233 case GLSL_SAMPLER_DIM_CUBE:
3234 return 3;
3235 case GLSL_SAMPLER_DIM_RECT:
3236 case GLSL_SAMPLER_DIM_SUBPASS:
3237 return 2;
3238 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3239 return 3;
3240 default:
3241 break;
3242 }
3243 return 0;
3244 }
3245
3246
3247
3248 /* Adjust the sample index according to FMASK.
3249 *
3250 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3251 * which is the identity mapping. Each nibble says which physical sample
3252 * should be fetched to get that sample.
3253 *
3254 * For example, 0x11111100 means there are only 2 samples stored and
3255 * the second sample covers 3/4 of the pixel. When reading samples 0
3256 * and 1, return physical sample 0 (determined by the first two 0s
3257 * in FMASK), otherwise return physical sample 1.
3258 *
3259 * The sample index should be adjusted as follows:
3260 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3261 */
3262 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3263 LLVMValueRef coord_x, LLVMValueRef coord_y,
3264 LLVMValueRef coord_z,
3265 LLVMValueRef sample_index,
3266 LLVMValueRef fmask_desc_ptr)
3267 {
3268 LLVMValueRef fmask_load_address[4];
3269 LLVMValueRef res;
3270
3271 fmask_load_address[0] = coord_x;
3272 fmask_load_address[1] = coord_y;
3273 if (coord_z) {
3274 fmask_load_address[2] = coord_z;
3275 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3276 }
3277
3278 struct ac_image_args args = {0};
3279
3280 args.opcode = ac_image_load;
3281 args.da = coord_z ? true : false;
3282 args.resource = fmask_desc_ptr;
3283 args.dmask = 0xf;
3284 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3285
3286 res = ac_build_image_opcode(ctx, &args);
3287
3288 res = ac_to_integer(ctx, res);
3289 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3290 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3291
3292 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3293 res,
3294 ctx->i32_0, "");
3295
3296 LLVMValueRef sample_index4 =
3297 LLVMBuildMul(ctx->builder, sample_index, four, "");
3298 LLVMValueRef shifted_fmask =
3299 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3300 LLVMValueRef final_sample =
3301 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3302
3303 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3304 * resource descriptor is 0 (invalid),
3305 */
3306 LLVMValueRef fmask_desc =
3307 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3308 ctx->v8i32, "");
3309
3310 LLVMValueRef fmask_word1 =
3311 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3312 ctx->i32_1, "");
3313
3314 LLVMValueRef word1_is_nonzero =
3315 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3316 fmask_word1, ctx->i32_0, "");
3317
3318 /* Replace the MSAA sample index. */
3319 sample_index =
3320 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3321 final_sample, sample_index, "");
3322 return sample_index;
3323 }
3324
3325 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3326 const nir_intrinsic_instr *instr)
3327 {
3328 const struct glsl_type *type = instr->variables[0]->var->type;
3329 if(instr->variables[0]->deref.child)
3330 type = instr->variables[0]->deref.child->type;
3331
3332 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3333 LLVMValueRef coords[4];
3334 LLVMValueRef masks[] = {
3335 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3336 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3337 };
3338 LLVMValueRef res;
3339 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3340
3341 int count;
3342 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3343 bool is_array = glsl_sampler_type_is_array(type);
3344 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3345 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3346 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3347 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3348 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3349 count = image_type_to_components_count(dim, is_array);
3350
3351 if (is_ms) {
3352 LLVMValueRef fmask_load_address[3];
3353 int chan;
3354
3355 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3356 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3357 if (is_array)
3358 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3359 else
3360 fmask_load_address[2] = NULL;
3361 if (add_frag_pos) {
3362 for (chan = 0; chan < 2; ++chan)
3363 fmask_load_address[chan] =
3364 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3365 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3366 ctx->ac.i32, ""), "");
3367 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3368 }
3369 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3370 fmask_load_address[0],
3371 fmask_load_address[1],
3372 fmask_load_address[2],
3373 sample_index,
3374 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3375 }
3376 if (count == 1 && !gfx9_1d) {
3377 if (instr->src[0].ssa->num_components)
3378 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3379 else
3380 res = src0;
3381 } else {
3382 int chan;
3383 if (is_ms)
3384 count--;
3385 for (chan = 0; chan < count; ++chan) {
3386 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3387 }
3388 if (add_frag_pos) {
3389 for (chan = 0; chan < 2; ++chan)
3390 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3391 ctx->ac.i32, ""), "");
3392 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3393 count++;
3394 }
3395
3396 if (gfx9_1d) {
3397 if (is_array) {
3398 coords[2] = coords[1];
3399 coords[1] = ctx->ac.i32_0;
3400 } else
3401 coords[1] = ctx->ac.i32_0;
3402 count++;
3403 }
3404
3405 if (is_ms) {
3406 coords[count] = sample_index;
3407 count++;
3408 }
3409
3410 if (count == 3) {
3411 coords[3] = LLVMGetUndef(ctx->ac.i32);
3412 count = 4;
3413 }
3414 res = ac_build_gather_values(&ctx->ac, coords, count);
3415 }
3416 return res;
3417 }
3418
3419 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3420 const nir_intrinsic_instr *instr)
3421 {
3422 LLVMValueRef params[7];
3423 LLVMValueRef res;
3424 char intrinsic_name[64];
3425 const nir_variable *var = instr->variables[0]->var;
3426 const struct glsl_type *type = var->type;
3427
3428 if(instr->variables[0]->deref.child)
3429 type = instr->variables[0]->deref.child->type;
3430
3431 type = glsl_without_array(type);
3432 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3433 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3434 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3435 ctx->ac.i32_0, ""); /* vindex */
3436 params[2] = ctx->ac.i32_0; /* voffset */
3437 params[3] = ctx->ac.i1false; /* glc */
3438 params[4] = ctx->ac.i1false; /* slc */
3439 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3440 params, 5, 0);
3441
3442 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3443 res = ac_to_integer(&ctx->ac, res);
3444 } else {
3445 bool is_da = glsl_sampler_type_is_array(type) ||
3446 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3447 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3448 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3449 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3450 LLVMValueRef glc = ctx->ac.i1false;
3451 LLVMValueRef slc = ctx->ac.i1false;
3452
3453 params[0] = get_image_coords(ctx, instr);
3454 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3455 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3456 if (HAVE_LLVM <= 0x0309) {
3457 params[3] = ctx->ac.i1false; /* r128 */
3458 params[4] = da;
3459 params[5] = glc;
3460 params[6] = slc;
3461 } else {
3462 LLVMValueRef lwe = ctx->ac.i1false;
3463 params[3] = glc;
3464 params[4] = slc;
3465 params[5] = lwe;
3466 params[6] = da;
3467 }
3468
3469 ac_get_image_intr_name("llvm.amdgcn.image.load",
3470 ctx->ac.v4f32, /* vdata */
3471 LLVMTypeOf(params[0]), /* coords */
3472 LLVMTypeOf(params[1]), /* rsrc */
3473 intrinsic_name, sizeof(intrinsic_name));
3474
3475 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3476 params, 7, AC_FUNC_ATTR_READONLY);
3477 }
3478 return ac_to_integer(&ctx->ac, res);
3479 }
3480
3481 static void visit_image_store(struct ac_nir_context *ctx,
3482 nir_intrinsic_instr *instr)
3483 {
3484 LLVMValueRef params[8];
3485 char intrinsic_name[64];
3486 const nir_variable *var = instr->variables[0]->var;
3487 const struct glsl_type *type = glsl_without_array(var->type);
3488 LLVMValueRef glc = ctx->ac.i1false;
3489 bool force_glc = ctx->ac.chip_class == SI;
3490 if (force_glc)
3491 glc = ctx->ac.i1true;
3492
3493 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3494 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3495 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3496 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3497 ctx->ac.i32_0, ""); /* vindex */
3498 params[3] = ctx->ac.i32_0; /* voffset */
3499 params[4] = glc; /* glc */
3500 params[5] = ctx->ac.i1false; /* slc */
3501 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3502 params, 6, 0);
3503 } else {
3504 bool is_da = glsl_sampler_type_is_array(type) ||
3505 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3506 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3507 LLVMValueRef slc = ctx->ac.i1false;
3508
3509 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3510 params[1] = get_image_coords(ctx, instr); /* coords */
3511 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3512 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3513 if (HAVE_LLVM <= 0x0309) {
3514 params[4] = ctx->ac.i1false; /* r128 */
3515 params[5] = da;
3516 params[6] = glc;
3517 params[7] = slc;
3518 } else {
3519 LLVMValueRef lwe = ctx->ac.i1false;
3520 params[4] = glc;
3521 params[5] = slc;
3522 params[6] = lwe;
3523 params[7] = da;
3524 }
3525
3526 ac_get_image_intr_name("llvm.amdgcn.image.store",
3527 LLVMTypeOf(params[0]), /* vdata */
3528 LLVMTypeOf(params[1]), /* coords */
3529 LLVMTypeOf(params[2]), /* rsrc */
3530 intrinsic_name, sizeof(intrinsic_name));
3531
3532 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3533 params, 8, 0);
3534 }
3535
3536 }
3537
3538 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3539 const nir_intrinsic_instr *instr)
3540 {
3541 LLVMValueRef params[7];
3542 int param_count = 0;
3543 const nir_variable *var = instr->variables[0]->var;
3544
3545 const char *atomic_name;
3546 char intrinsic_name[41];
3547 const struct glsl_type *type = glsl_without_array(var->type);
3548 MAYBE_UNUSED int length;
3549
3550 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3551
3552 switch (instr->intrinsic) {
3553 case nir_intrinsic_image_atomic_add:
3554 atomic_name = "add";
3555 break;
3556 case nir_intrinsic_image_atomic_min:
3557 atomic_name = is_unsigned ? "umin" : "smin";
3558 break;
3559 case nir_intrinsic_image_atomic_max:
3560 atomic_name = is_unsigned ? "umax" : "smax";
3561 break;
3562 case nir_intrinsic_image_atomic_and:
3563 atomic_name = "and";
3564 break;
3565 case nir_intrinsic_image_atomic_or:
3566 atomic_name = "or";
3567 break;
3568 case nir_intrinsic_image_atomic_xor:
3569 atomic_name = "xor";
3570 break;
3571 case nir_intrinsic_image_atomic_exchange:
3572 atomic_name = "swap";
3573 break;
3574 case nir_intrinsic_image_atomic_comp_swap:
3575 atomic_name = "cmpswap";
3576 break;
3577 default:
3578 abort();
3579 }
3580
3581 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3582 params[param_count++] = get_src(ctx, instr->src[3]);
3583 params[param_count++] = get_src(ctx, instr->src[2]);
3584
3585 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3586 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3587 NULL, true, true);
3588 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3589 ctx->ac.i32_0, ""); /* vindex */
3590 params[param_count++] = ctx->ac.i32_0; /* voffset */
3591 params[param_count++] = ctx->ac.i1false; /* slc */
3592
3593 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3594 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3595 } else {
3596 char coords_type[8];
3597
3598 bool da = glsl_sampler_type_is_array(type) ||
3599 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3600
3601 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3602 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3603 NULL, true, true);
3604 params[param_count++] = ctx->ac.i1false; /* r128 */
3605 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3606 params[param_count++] = ctx->ac.i1false; /* slc */
3607
3608 build_int_type_name(LLVMTypeOf(coords),
3609 coords_type, sizeof(coords_type));
3610
3611 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3612 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3613 }
3614
3615 assert(length < sizeof(intrinsic_name));
3616 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3617 }
3618
3619 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3620 const nir_intrinsic_instr *instr)
3621 {
3622 LLVMValueRef res;
3623 const nir_variable *var = instr->variables[0]->var;
3624 const struct glsl_type *type = instr->variables[0]->var->type;
3625 bool da = glsl_sampler_type_is_array(var->type) ||
3626 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3627 if(instr->variables[0]->deref.child)
3628 type = instr->variables[0]->deref.child->type;
3629
3630 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3631 return get_buffer_size(ctx,
3632 get_sampler_desc(ctx, instr->variables[0],
3633 AC_DESC_BUFFER, NULL, true, false), true);
3634
3635 struct ac_image_args args = { 0 };
3636
3637 args.da = da;
3638 args.dmask = 0xf;
3639 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3640 args.opcode = ac_image_get_resinfo;
3641 args.addr = ctx->ac.i32_0;
3642
3643 res = ac_build_image_opcode(&ctx->ac, &args);
3644
3645 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3646
3647 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3648 glsl_sampler_type_is_array(type)) {
3649 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3650 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3651 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3652 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3653 }
3654 if (ctx->ac.chip_class >= GFX9 &&
3655 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3656 glsl_sampler_type_is_array(type)) {
3657 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3658 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3659 ctx->ac.i32_1, "");
3660
3661 }
3662 return res;
3663 }
3664
3665 #define NOOP_WAITCNT 0xf7f
3666 #define LGKM_CNT 0x07f
3667 #define VM_CNT 0xf70
3668
3669 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3670 unsigned simm16)
3671 {
3672 LLVMValueRef args[1] = {
3673 LLVMConstInt(ctx->ac.i32, simm16, false),
3674 };
3675 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3676 ctx->ac.voidt, args, 1, 0);
3677 }
3678
3679 static void emit_membar(struct nir_to_llvm_context *ctx,
3680 const nir_intrinsic_instr *instr)
3681 {
3682 unsigned waitcnt = NOOP_WAITCNT;
3683
3684 switch (instr->intrinsic) {
3685 case nir_intrinsic_memory_barrier:
3686 case nir_intrinsic_group_memory_barrier:
3687 waitcnt &= VM_CNT & LGKM_CNT;
3688 break;
3689 case nir_intrinsic_memory_barrier_atomic_counter:
3690 case nir_intrinsic_memory_barrier_buffer:
3691 case nir_intrinsic_memory_barrier_image:
3692 waitcnt &= VM_CNT;
3693 break;
3694 case nir_intrinsic_memory_barrier_shared:
3695 waitcnt &= LGKM_CNT;
3696 break;
3697 default:
3698 break;
3699 }
3700 if (waitcnt != NOOP_WAITCNT)
3701 emit_waitcnt(ctx, waitcnt);
3702 }
3703
3704 static void emit_barrier(struct nir_to_llvm_context *ctx)
3705 {
3706 /* SI only (thanks to a hw bug workaround):
3707 * The real barrier instruction isn’t needed, because an entire patch
3708 * always fits into a single wave.
3709 */
3710 if (ctx->options->chip_class == SI &&
3711 ctx->stage == MESA_SHADER_TESS_CTRL) {
3712 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3713 return;
3714 }
3715 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3716 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3717 }
3718
3719 static void emit_discard_if(struct ac_nir_context *ctx,
3720 const nir_intrinsic_instr *instr)
3721 {
3722 LLVMValueRef cond;
3723
3724 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3725 get_src(ctx, instr->src[0]),
3726 ctx->ac.i32_0, "");
3727 ac_build_kill_if_false(&ctx->ac, cond);
3728 }
3729
3730 static LLVMValueRef
3731 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3732 {
3733 LLVMValueRef result;
3734 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3735 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3736 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3737
3738 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3739 }
3740
3741 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3742 const nir_intrinsic_instr *instr)
3743 {
3744 LLVMValueRef ptr, result;
3745 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3746 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3747
3748 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3749 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3750 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3751 ptr, src, src1,
3752 LLVMAtomicOrderingSequentiallyConsistent,
3753 LLVMAtomicOrderingSequentiallyConsistent,
3754 false);
3755 } else {
3756 LLVMAtomicRMWBinOp op;
3757 switch (instr->intrinsic) {
3758 case nir_intrinsic_var_atomic_add:
3759 op = LLVMAtomicRMWBinOpAdd;
3760 break;
3761 case nir_intrinsic_var_atomic_umin:
3762 op = LLVMAtomicRMWBinOpUMin;
3763 break;
3764 case nir_intrinsic_var_atomic_umax:
3765 op = LLVMAtomicRMWBinOpUMax;
3766 break;
3767 case nir_intrinsic_var_atomic_imin:
3768 op = LLVMAtomicRMWBinOpMin;
3769 break;
3770 case nir_intrinsic_var_atomic_imax:
3771 op = LLVMAtomicRMWBinOpMax;
3772 break;
3773 case nir_intrinsic_var_atomic_and:
3774 op = LLVMAtomicRMWBinOpAnd;
3775 break;
3776 case nir_intrinsic_var_atomic_or:
3777 op = LLVMAtomicRMWBinOpOr;
3778 break;
3779 case nir_intrinsic_var_atomic_xor:
3780 op = LLVMAtomicRMWBinOpXor;
3781 break;
3782 case nir_intrinsic_var_atomic_exchange:
3783 op = LLVMAtomicRMWBinOpXchg;
3784 break;
3785 default:
3786 return NULL;
3787 }
3788
3789 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3790 LLVMAtomicOrderingSequentiallyConsistent,
3791 false);
3792 }
3793 return result;
3794 }
3795
3796 #define INTERP_CENTER 0
3797 #define INTERP_CENTROID 1
3798 #define INTERP_SAMPLE 2
3799
3800 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3801 enum glsl_interp_mode interp, unsigned location)
3802 {
3803 switch (interp) {
3804 case INTERP_MODE_FLAT:
3805 default:
3806 return NULL;
3807 case INTERP_MODE_SMOOTH:
3808 case INTERP_MODE_NONE:
3809 if (location == INTERP_CENTER)
3810 return ctx->persp_center;
3811 else if (location == INTERP_CENTROID)
3812 return ctx->persp_centroid;
3813 else if (location == INTERP_SAMPLE)
3814 return ctx->persp_sample;
3815 break;
3816 case INTERP_MODE_NOPERSPECTIVE:
3817 if (location == INTERP_CENTER)
3818 return ctx->linear_center;
3819 else if (location == INTERP_CENTROID)
3820 return ctx->linear_centroid;
3821 else if (location == INTERP_SAMPLE)
3822 return ctx->linear_sample;
3823 break;
3824 }
3825 return NULL;
3826 }
3827
3828 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3829 LLVMValueRef sample_id)
3830 {
3831 LLVMValueRef result;
3832 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3833
3834 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3835 const_array(ctx->ac.v2f32, 64), "");
3836
3837 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3838 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3839
3840 return result;
3841 }
3842
3843 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3844 {
3845 LLVMValueRef values[2];
3846
3847 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3848 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3849 return ac_build_gather_values(&ctx->ac, values, 2);
3850 }
3851
3852 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3853 const nir_intrinsic_instr *instr)
3854 {
3855 LLVMValueRef result[4];
3856 LLVMValueRef interp_param, attr_number;
3857 unsigned location;
3858 unsigned chan;
3859 LLVMValueRef src_c0 = NULL;
3860 LLVMValueRef src_c1 = NULL;
3861 LLVMValueRef src0 = NULL;
3862 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3863 switch (instr->intrinsic) {
3864 case nir_intrinsic_interp_var_at_centroid:
3865 location = INTERP_CENTROID;
3866 break;
3867 case nir_intrinsic_interp_var_at_sample:
3868 case nir_intrinsic_interp_var_at_offset:
3869 location = INTERP_CENTER;
3870 src0 = get_src(ctx->nir, instr->src[0]);
3871 break;
3872 default:
3873 break;
3874 }
3875
3876 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3877 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3878 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3879 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3880 LLVMValueRef sample_position;
3881 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
3882
3883 /* fetch sample ID */
3884 sample_position = load_sample_position(ctx, src0);
3885
3886 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
3887 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3888 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
3889 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3890 }
3891 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3892 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
3893
3894 if (location == INTERP_CENTER) {
3895 LLVMValueRef ij_out[2];
3896 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3897
3898 /*
3899 * take the I then J parameters, and the DDX/Y for it, and
3900 * calculate the IJ inputs for the interpolator.
3901 * temp1 = ddx * offset/sample.x + I;
3902 * interp_param.I = ddy * offset/sample.y + temp1;
3903 * temp1 = ddx * offset/sample.x + J;
3904 * interp_param.J = ddy * offset/sample.y + temp1;
3905 */
3906 for (unsigned i = 0; i < 2; i++) {
3907 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
3908 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
3909 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3910 ddxy_out, ix_ll, "");
3911 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3912 ddxy_out, iy_ll, "");
3913 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3914 interp_param, ix_ll, "");
3915 LLVMValueRef temp1, temp2;
3916
3917 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3918 ctx->ac.f32, "");
3919
3920 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3921 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3922
3923 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3924 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3925
3926 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3927 temp2, ctx->ac.i32, "");
3928 }
3929 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3930
3931 }
3932
3933 for (chan = 0; chan < 4; chan++) {
3934 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
3935
3936 if (interp_param) {
3937 interp_param = LLVMBuildBitCast(ctx->builder,
3938 interp_param, ctx->ac.v2f32, "");
3939 LLVMValueRef i = LLVMBuildExtractElement(
3940 ctx->builder, interp_param, ctx->ac.i32_0, "");
3941 LLVMValueRef j = LLVMBuildExtractElement(
3942 ctx->builder, interp_param, ctx->ac.i32_1, "");
3943
3944 result[chan] = ac_build_fs_interp(&ctx->ac,
3945 llvm_chan, attr_number,
3946 ctx->prim_mask, i, j);
3947 } else {
3948 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3949 LLVMConstInt(ctx->ac.i32, 2, false),
3950 llvm_chan, attr_number,
3951 ctx->prim_mask);
3952 }
3953 }
3954 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
3955 instr->variables[0]->var->data.location_frac);
3956 }
3957
3958 static void
3959 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
3960 {
3961 LLVMValueRef gs_next_vertex;
3962 LLVMValueRef can_emit;
3963 int idx;
3964 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3965
3966 /* Write vertex attribute values to GSVS ring */
3967 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3968 ctx->gs_next_vertex,
3969 "");
3970
3971 /* If this thread has already emitted the declared maximum number of
3972 * vertices, kill it: excessive vertex emissions are not supposed to
3973 * have any effect, and GS threads have no externally observable
3974 * effects other than emitting vertices.
3975 */
3976 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3977 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
3978 ac_build_kill_if_false(&ctx->ac, can_emit);
3979
3980 /* loop num outputs */
3981 idx = 0;
3982 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3983 LLVMValueRef *out_ptr = &addrs[i * 4];
3984 int length = 4;
3985 int slot = idx;
3986 int slot_inc = 1;
3987
3988 if (!(ctx->output_mask & (1ull << i)))
3989 continue;
3990
3991 if (i == VARYING_SLOT_CLIP_DIST0) {
3992 /* pack clip and cull into a single set of slots */
3993 length = ctx->num_output_clips + ctx->num_output_culls;
3994 if (length > 4)
3995 slot_inc = 2;
3996 }
3997 for (unsigned j = 0; j < length; j++) {
3998 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3999 out_ptr[j], "");
4000 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4001 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4002 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4003
4004 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4005
4006 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4007 out_val, 1,
4008 voffset, ctx->gs2vs_offset, 0,
4009 1, 1, true, true);
4010 }
4011 idx += slot_inc;
4012 }
4013
4014 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4015 ctx->ac.i32_1, "");
4016 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4017
4018 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4019 }
4020
4021 static void
4022 visit_end_primitive(struct nir_to_llvm_context *ctx,
4023 const nir_intrinsic_instr *instr)
4024 {
4025 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4026 }
4027
4028 static LLVMValueRef
4029 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4030 const nir_intrinsic_instr *instr)
4031 {
4032 LLVMValueRef coord[4] = {
4033 ctx->tes_u,
4034 ctx->tes_v,
4035 ctx->ac.f32_0,
4036 ctx->ac.f32_0,
4037 };
4038
4039 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4040 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4041 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4042
4043 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4044 return LLVMBuildBitCast(ctx->builder, result,
4045 get_def_type(ctx->nir, &instr->dest.ssa), "");
4046 }
4047
4048 static void visit_intrinsic(struct ac_nir_context *ctx,
4049 nir_intrinsic_instr *instr)
4050 {
4051 LLVMValueRef result = NULL;
4052
4053 switch (instr->intrinsic) {
4054 case nir_intrinsic_load_work_group_id: {
4055 result = ctx->nctx->workgroup_ids;
4056 break;
4057 }
4058 case nir_intrinsic_load_base_vertex: {
4059 result = ctx->abi->base_vertex;
4060 break;
4061 }
4062 case nir_intrinsic_load_vertex_id_zero_base: {
4063 result = ctx->abi->vertex_id;
4064 break;
4065 }
4066 case nir_intrinsic_load_local_invocation_id: {
4067 result = ctx->nctx->local_invocation_ids;
4068 break;
4069 }
4070 case nir_intrinsic_load_base_instance:
4071 result = ctx->abi->start_instance;
4072 break;
4073 case nir_intrinsic_load_draw_id:
4074 result = ctx->abi->draw_id;
4075 break;
4076 case nir_intrinsic_load_view_index:
4077 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4078 break;
4079 case nir_intrinsic_load_invocation_id:
4080 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4081 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4082 else
4083 result = ctx->abi->gs_invocation_id;
4084 break;
4085 case nir_intrinsic_load_primitive_id:
4086 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4087 if (ctx->nctx)
4088 ctx->nctx->shader_info->gs.uses_prim_id = true;
4089 result = ctx->abi->gs_prim_id;
4090 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4091 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4092 result = ctx->nctx->tcs_patch_id;
4093 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4094 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4095 result = ctx->nctx->tes_patch_id;
4096 } else
4097 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4098 break;
4099 case nir_intrinsic_load_sample_id:
4100 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4101 break;
4102 case nir_intrinsic_load_sample_pos:
4103 result = load_sample_pos(ctx);
4104 break;
4105 case nir_intrinsic_load_sample_mask_in:
4106 result = ctx->abi->sample_coverage;
4107 break;
4108 case nir_intrinsic_load_frag_coord: {
4109 LLVMValueRef values[4] = {
4110 ctx->abi->frag_pos[0],
4111 ctx->abi->frag_pos[1],
4112 ctx->abi->frag_pos[2],
4113 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4114 };
4115 result = ac_build_gather_values(&ctx->ac, values, 4);
4116 break;
4117 }
4118 case nir_intrinsic_load_front_face:
4119 result = ctx->abi->front_face;
4120 break;
4121 case nir_intrinsic_load_instance_id:
4122 result = ctx->abi->instance_id;
4123 break;
4124 case nir_intrinsic_load_num_work_groups:
4125 result = ctx->nctx->num_work_groups;
4126 break;
4127 case nir_intrinsic_load_local_invocation_index:
4128 result = visit_load_local_invocation_index(ctx->nctx);
4129 break;
4130 case nir_intrinsic_load_push_constant:
4131 result = visit_load_push_constant(ctx->nctx, instr);
4132 break;
4133 case nir_intrinsic_vulkan_resource_index:
4134 result = visit_vulkan_resource_index(ctx->nctx, instr);
4135 break;
4136 case nir_intrinsic_store_ssbo:
4137 visit_store_ssbo(ctx, instr);
4138 break;
4139 case nir_intrinsic_load_ssbo:
4140 result = visit_load_buffer(ctx, instr);
4141 break;
4142 case nir_intrinsic_ssbo_atomic_add:
4143 case nir_intrinsic_ssbo_atomic_imin:
4144 case nir_intrinsic_ssbo_atomic_umin:
4145 case nir_intrinsic_ssbo_atomic_imax:
4146 case nir_intrinsic_ssbo_atomic_umax:
4147 case nir_intrinsic_ssbo_atomic_and:
4148 case nir_intrinsic_ssbo_atomic_or:
4149 case nir_intrinsic_ssbo_atomic_xor:
4150 case nir_intrinsic_ssbo_atomic_exchange:
4151 case nir_intrinsic_ssbo_atomic_comp_swap:
4152 result = visit_atomic_ssbo(ctx, instr);
4153 break;
4154 case nir_intrinsic_load_ubo:
4155 result = visit_load_ubo_buffer(ctx, instr);
4156 break;
4157 case nir_intrinsic_get_buffer_size:
4158 result = visit_get_buffer_size(ctx, instr);
4159 break;
4160 case nir_intrinsic_load_var:
4161 result = visit_load_var(ctx, instr);
4162 break;
4163 case nir_intrinsic_store_var:
4164 visit_store_var(ctx, instr);
4165 break;
4166 case nir_intrinsic_image_load:
4167 result = visit_image_load(ctx, instr);
4168 break;
4169 case nir_intrinsic_image_store:
4170 visit_image_store(ctx, instr);
4171 break;
4172 case nir_intrinsic_image_atomic_add:
4173 case nir_intrinsic_image_atomic_min:
4174 case nir_intrinsic_image_atomic_max:
4175 case nir_intrinsic_image_atomic_and:
4176 case nir_intrinsic_image_atomic_or:
4177 case nir_intrinsic_image_atomic_xor:
4178 case nir_intrinsic_image_atomic_exchange:
4179 case nir_intrinsic_image_atomic_comp_swap:
4180 result = visit_image_atomic(ctx, instr);
4181 break;
4182 case nir_intrinsic_image_size:
4183 result = visit_image_size(ctx, instr);
4184 break;
4185 case nir_intrinsic_discard:
4186 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4187 LLVMVoidTypeInContext(ctx->ac.context),
4188 NULL, 0, AC_FUNC_ATTR_LEGACY);
4189 break;
4190 case nir_intrinsic_discard_if:
4191 emit_discard_if(ctx, instr);
4192 break;
4193 case nir_intrinsic_memory_barrier:
4194 case nir_intrinsic_group_memory_barrier:
4195 case nir_intrinsic_memory_barrier_atomic_counter:
4196 case nir_intrinsic_memory_barrier_buffer:
4197 case nir_intrinsic_memory_barrier_image:
4198 case nir_intrinsic_memory_barrier_shared:
4199 emit_membar(ctx->nctx, instr);
4200 break;
4201 case nir_intrinsic_barrier:
4202 emit_barrier(ctx->nctx);
4203 break;
4204 case nir_intrinsic_var_atomic_add:
4205 case nir_intrinsic_var_atomic_imin:
4206 case nir_intrinsic_var_atomic_umin:
4207 case nir_intrinsic_var_atomic_imax:
4208 case nir_intrinsic_var_atomic_umax:
4209 case nir_intrinsic_var_atomic_and:
4210 case nir_intrinsic_var_atomic_or:
4211 case nir_intrinsic_var_atomic_xor:
4212 case nir_intrinsic_var_atomic_exchange:
4213 case nir_intrinsic_var_atomic_comp_swap:
4214 result = visit_var_atomic(ctx->nctx, instr);
4215 break;
4216 case nir_intrinsic_interp_var_at_centroid:
4217 case nir_intrinsic_interp_var_at_sample:
4218 case nir_intrinsic_interp_var_at_offset:
4219 result = visit_interp(ctx->nctx, instr);
4220 break;
4221 case nir_intrinsic_emit_vertex:
4222 assert(instr->const_index[0] == 0);
4223 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4224 break;
4225 case nir_intrinsic_end_primitive:
4226 visit_end_primitive(ctx->nctx, instr);
4227 break;
4228 case nir_intrinsic_load_tess_coord:
4229 result = visit_load_tess_coord(ctx->nctx, instr);
4230 break;
4231 case nir_intrinsic_load_patch_vertices_in:
4232 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4233 break;
4234 default:
4235 fprintf(stderr, "Unknown intrinsic: ");
4236 nir_print_instr(&instr->instr, stderr);
4237 fprintf(stderr, "\n");
4238 break;
4239 }
4240 if (result) {
4241 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4242 }
4243 }
4244
4245 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4246 LLVMValueRef buffer, bool write)
4247 {
4248 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4249
4250 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4251 ctx->shader_info->fs.writes_memory = true;
4252
4253 return buffer;
4254 }
4255
4256 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4257 unsigned descriptor_set,
4258 unsigned base_index,
4259 unsigned constant_index,
4260 LLVMValueRef index,
4261 enum ac_descriptor_type desc_type,
4262 bool image, bool write)
4263 {
4264 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4265 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4266 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4267 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4268 unsigned offset = binding->offset;
4269 unsigned stride = binding->size;
4270 unsigned type_size;
4271 LLVMBuilderRef builder = ctx->builder;
4272 LLVMTypeRef type;
4273
4274 assert(base_index < layout->binding_count);
4275
4276 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4277 ctx->shader_info->fs.writes_memory = true;
4278
4279 switch (desc_type) {
4280 case AC_DESC_IMAGE:
4281 type = ctx->ac.v8i32;
4282 type_size = 32;
4283 break;
4284 case AC_DESC_FMASK:
4285 type = ctx->ac.v8i32;
4286 offset += 32;
4287 type_size = 32;
4288 break;
4289 case AC_DESC_SAMPLER:
4290 type = ctx->ac.v4i32;
4291 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4292 offset += 64;
4293
4294 type_size = 16;
4295 break;
4296 case AC_DESC_BUFFER:
4297 type = ctx->ac.v4i32;
4298 type_size = 16;
4299 break;
4300 default:
4301 unreachable("invalid desc_type\n");
4302 }
4303
4304 offset += constant_index * stride;
4305
4306 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4307 (!index || binding->immutable_samplers_equal)) {
4308 if (binding->immutable_samplers_equal)
4309 constant_index = 0;
4310
4311 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4312
4313 LLVMValueRef constants[] = {
4314 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4315 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4316 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4317 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4318 };
4319 return ac_build_gather_values(&ctx->ac, constants, 4);
4320 }
4321
4322 assert(stride % type_size == 0);
4323
4324 if (!index)
4325 index = ctx->ac.i32_0;
4326
4327 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4328
4329 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4330 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4331
4332 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4333 }
4334
4335 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4336 const nir_deref_var *deref,
4337 enum ac_descriptor_type desc_type,
4338 const nir_tex_instr *tex_instr,
4339 bool image, bool write)
4340 {
4341 LLVMValueRef index = NULL;
4342 unsigned constant_index = 0;
4343 unsigned descriptor_set;
4344 unsigned base_index;
4345
4346 if (!deref) {
4347 assert(tex_instr && !image);
4348 descriptor_set = 0;
4349 base_index = tex_instr->sampler_index;
4350 } else {
4351 const nir_deref *tail = &deref->deref;
4352 while (tail->child) {
4353 const nir_deref_array *child = nir_deref_as_array(tail->child);
4354 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4355
4356 if (!array_size)
4357 array_size = 1;
4358
4359 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4360
4361 if (child->deref_array_type == nir_deref_array_type_indirect) {
4362 LLVMValueRef indirect = get_src(ctx, child->indirect);
4363
4364 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4365 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4366
4367 if (!index)
4368 index = indirect;
4369 else
4370 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4371 }
4372
4373 constant_index += child->base_offset * array_size;
4374
4375 tail = &child->deref;
4376 }
4377 descriptor_set = deref->var->data.descriptor_set;
4378 base_index = deref->var->data.binding;
4379 }
4380
4381 return ctx->abi->load_sampler_desc(ctx->abi,
4382 descriptor_set,
4383 base_index,
4384 constant_index, index,
4385 desc_type, image, write);
4386 }
4387
4388 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4389 struct ac_image_args *args,
4390 const nir_tex_instr *instr,
4391 nir_texop op,
4392 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4393 LLVMValueRef *param, unsigned count,
4394 unsigned dmask)
4395 {
4396 unsigned is_rect = 0;
4397 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4398
4399 if (op == nir_texop_lod)
4400 da = false;
4401 /* Pad to power of two vector */
4402 while (count < util_next_power_of_two(count))
4403 param[count++] = LLVMGetUndef(ctx->i32);
4404
4405 if (count > 1)
4406 args->addr = ac_build_gather_values(ctx, param, count);
4407 else
4408 args->addr = param[0];
4409
4410 args->resource = res_ptr;
4411 args->sampler = samp_ptr;
4412
4413 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4414 args->addr = param[0];
4415 return;
4416 }
4417
4418 args->dmask = dmask;
4419 args->unorm = is_rect;
4420 args->da = da;
4421 }
4422
4423 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4424 *
4425 * SI-CI:
4426 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4427 * filtering manually. The driver sets img7 to a mask clearing
4428 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4429 * s_and_b32 samp0, samp0, img7
4430 *
4431 * VI:
4432 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4433 */
4434 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4435 LLVMValueRef res, LLVMValueRef samp)
4436 {
4437 LLVMBuilderRef builder = ctx->ac.builder;
4438 LLVMValueRef img7, samp0;
4439
4440 if (ctx->ac.chip_class >= VI)
4441 return samp;
4442
4443 img7 = LLVMBuildExtractElement(builder, res,
4444 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4445 samp0 = LLVMBuildExtractElement(builder, samp,
4446 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4447 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4448 return LLVMBuildInsertElement(builder, samp, samp0,
4449 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4450 }
4451
4452 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4453 nir_tex_instr *instr,
4454 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4455 LLVMValueRef *fmask_ptr)
4456 {
4457 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4458 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4459 else
4460 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4461 if (samp_ptr) {
4462 if (instr->sampler)
4463 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4464 else
4465 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4466 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4467 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4468 }
4469 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4470 instr->op == nir_texop_samples_identical))
4471 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4472 }
4473
4474 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4475 LLVMValueRef coord)
4476 {
4477 coord = ac_to_float(ctx, coord);
4478 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4479 coord = ac_to_integer(ctx, coord);
4480 return coord;
4481 }
4482
4483 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4484 {
4485 LLVMValueRef result = NULL;
4486 struct ac_image_args args = { 0 };
4487 unsigned dmask = 0xf;
4488 LLVMValueRef address[16];
4489 LLVMValueRef coords[5];
4490 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4491 LLVMValueRef bias = NULL, offsets = NULL;
4492 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4493 LLVMValueRef ddx = NULL, ddy = NULL;
4494 LLVMValueRef derivs[6];
4495 unsigned chan, count = 0;
4496 unsigned const_src = 0, num_deriv_comp = 0;
4497 bool lod_is_zero = false;
4498
4499 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4500
4501 for (unsigned i = 0; i < instr->num_srcs; i++) {
4502 switch (instr->src[i].src_type) {
4503 case nir_tex_src_coord:
4504 coord = get_src(ctx, instr->src[i].src);
4505 break;
4506 case nir_tex_src_projector:
4507 break;
4508 case nir_tex_src_comparator:
4509 comparator = get_src(ctx, instr->src[i].src);
4510 break;
4511 case nir_tex_src_offset:
4512 offsets = get_src(ctx, instr->src[i].src);
4513 const_src = i;
4514 break;
4515 case nir_tex_src_bias:
4516 bias = get_src(ctx, instr->src[i].src);
4517 break;
4518 case nir_tex_src_lod: {
4519 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4520
4521 if (val && val->i32[0] == 0)
4522 lod_is_zero = true;
4523 lod = get_src(ctx, instr->src[i].src);
4524 break;
4525 }
4526 case nir_tex_src_ms_index:
4527 sample_index = get_src(ctx, instr->src[i].src);
4528 break;
4529 case nir_tex_src_ms_mcs:
4530 break;
4531 case nir_tex_src_ddx:
4532 ddx = get_src(ctx, instr->src[i].src);
4533 num_deriv_comp = instr->src[i].src.ssa->num_components;
4534 break;
4535 case nir_tex_src_ddy:
4536 ddy = get_src(ctx, instr->src[i].src);
4537 break;
4538 case nir_tex_src_texture_offset:
4539 case nir_tex_src_sampler_offset:
4540 case nir_tex_src_plane:
4541 default:
4542 break;
4543 }
4544 }
4545
4546 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4547 result = get_buffer_size(ctx, res_ptr, true);
4548 goto write_result;
4549 }
4550
4551 if (instr->op == nir_texop_texture_samples) {
4552 LLVMValueRef res, samples, is_msaa;
4553 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4554 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4555 LLVMConstInt(ctx->ac.i32, 3, false), "");
4556 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4557 LLVMConstInt(ctx->ac.i32, 28, false), "");
4558 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4559 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4560 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4561 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4562
4563 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4564 LLVMConstInt(ctx->ac.i32, 16, false), "");
4565 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4566 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4567 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4568 samples, "");
4569 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4570 ctx->ac.i32_1, "");
4571 result = samples;
4572 goto write_result;
4573 }
4574
4575 if (coord)
4576 for (chan = 0; chan < instr->coord_components; chan++)
4577 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4578
4579 if (offsets && instr->op != nir_texop_txf) {
4580 LLVMValueRef offset[3], pack;
4581 for (chan = 0; chan < 3; ++chan)
4582 offset[chan] = ctx->ac.i32_0;
4583
4584 args.offset = true;
4585 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4586 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4587 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4588 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4589 if (chan)
4590 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4591 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4592 }
4593 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4594 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4595 address[count++] = pack;
4596
4597 }
4598 /* pack LOD bias value */
4599 if (instr->op == nir_texop_txb && bias) {
4600 address[count++] = bias;
4601 }
4602
4603 /* Pack depth comparison value */
4604 if (instr->is_shadow && comparator) {
4605 LLVMValueRef z = ac_to_float(&ctx->ac,
4606 llvm_extract_elem(&ctx->ac, comparator, 0));
4607
4608 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4609 * so the depth comparison value isn't clamped for Z16 and
4610 * Z24 anymore. Do it manually here.
4611 *
4612 * It's unnecessary if the original texture format was
4613 * Z32_FLOAT, but we don't know that here.
4614 */
4615 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4616 z = ac_build_clamp(&ctx->ac, z);
4617
4618 address[count++] = z;
4619 }
4620
4621 /* pack derivatives */
4622 if (ddx || ddy) {
4623 int num_src_deriv_channels, num_dest_deriv_channels;
4624 switch (instr->sampler_dim) {
4625 case GLSL_SAMPLER_DIM_3D:
4626 case GLSL_SAMPLER_DIM_CUBE:
4627 num_deriv_comp = 3;
4628 num_src_deriv_channels = 3;
4629 num_dest_deriv_channels = 3;
4630 break;
4631 case GLSL_SAMPLER_DIM_2D:
4632 default:
4633 num_src_deriv_channels = 2;
4634 num_dest_deriv_channels = 2;
4635 num_deriv_comp = 2;
4636 break;
4637 case GLSL_SAMPLER_DIM_1D:
4638 num_src_deriv_channels = 1;
4639 if (ctx->ac.chip_class >= GFX9) {
4640 num_dest_deriv_channels = 2;
4641 num_deriv_comp = 2;
4642 } else {
4643 num_dest_deriv_channels = 1;
4644 num_deriv_comp = 1;
4645 }
4646 break;
4647 }
4648
4649 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4650 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4651 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4652 }
4653 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4654 derivs[i] = ctx->ac.f32_0;
4655 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4656 }
4657 }
4658
4659 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4660 for (chan = 0; chan < instr->coord_components; chan++)
4661 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4662 if (instr->coord_components == 3)
4663 coords[3] = LLVMGetUndef(ctx->ac.f32);
4664 ac_prepare_cube_coords(&ctx->ac,
4665 instr->op == nir_texop_txd, instr->is_array,
4666 instr->op == nir_texop_lod, coords, derivs);
4667 if (num_deriv_comp)
4668 num_deriv_comp--;
4669 }
4670
4671 if (ddx || ddy) {
4672 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4673 address[count++] = derivs[i];
4674 }
4675
4676 /* Pack texture coordinates */
4677 if (coord) {
4678 address[count++] = coords[0];
4679 if (instr->coord_components > 1) {
4680 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4681 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4682 }
4683 address[count++] = coords[1];
4684 }
4685 if (instr->coord_components > 2) {
4686 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4687 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4688 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4689 instr->op != nir_texop_txf) {
4690 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4691 }
4692 address[count++] = coords[2];
4693 }
4694
4695 if (ctx->ac.chip_class >= GFX9) {
4696 LLVMValueRef filler;
4697 if (instr->op == nir_texop_txf)
4698 filler = ctx->ac.i32_0;
4699 else
4700 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4701
4702 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4703 /* No nir_texop_lod, because it does not take a slice
4704 * even with array textures. */
4705 if (instr->is_array && instr->op != nir_texop_lod ) {
4706 address[count] = address[count - 1];
4707 address[count - 1] = filler;
4708 count++;
4709 } else
4710 address[count++] = filler;
4711 }
4712 }
4713 }
4714
4715 /* Pack LOD */
4716 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4717 instr->op == nir_texop_txf)) {
4718 address[count++] = lod;
4719 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4720 address[count++] = sample_index;
4721 } else if(instr->op == nir_texop_txs) {
4722 count = 0;
4723 if (lod)
4724 address[count++] = lod;
4725 else
4726 address[count++] = ctx->ac.i32_0;
4727 }
4728
4729 for (chan = 0; chan < count; chan++) {
4730 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4731 address[chan], ctx->ac.i32, "");
4732 }
4733
4734 if (instr->op == nir_texop_samples_identical) {
4735 LLVMValueRef txf_address[4];
4736 struct ac_image_args txf_args = { 0 };
4737 unsigned txf_count = count;
4738 memcpy(txf_address, address, sizeof(txf_address));
4739
4740 if (!instr->is_array)
4741 txf_address[2] = ctx->ac.i32_0;
4742 txf_address[3] = ctx->ac.i32_0;
4743
4744 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4745 fmask_ptr, NULL,
4746 txf_address, txf_count, 0xf);
4747
4748 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4749
4750 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4751 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4752 goto write_result;
4753 }
4754
4755 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4756 instr->op != nir_texop_txs) {
4757 unsigned sample_chan = instr->is_array ? 3 : 2;
4758 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4759 address[0],
4760 address[1],
4761 instr->is_array ? address[2] : NULL,
4762 address[sample_chan],
4763 fmask_ptr);
4764 }
4765
4766 if (offsets && instr->op == nir_texop_txf) {
4767 nir_const_value *const_offset =
4768 nir_src_as_const_value(instr->src[const_src].src);
4769 int num_offsets = instr->src[const_src].src.ssa->num_components;
4770 assert(const_offset);
4771 num_offsets = MIN2(num_offsets, instr->coord_components);
4772 if (num_offsets > 2)
4773 address[2] = LLVMBuildAdd(ctx->ac.builder,
4774 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4775 if (num_offsets > 1)
4776 address[1] = LLVMBuildAdd(ctx->ac.builder,
4777 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4778 address[0] = LLVMBuildAdd(ctx->ac.builder,
4779 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4780
4781 }
4782
4783 /* TODO TG4 support */
4784 if (instr->op == nir_texop_tg4) {
4785 if (instr->is_shadow)
4786 dmask = 1;
4787 else
4788 dmask = 1 << instr->component;
4789 }
4790 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4791 res_ptr, samp_ptr, address, count, dmask);
4792
4793 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4794
4795 if (instr->op == nir_texop_query_levels)
4796 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4797 else if (instr->is_shadow && instr->is_new_style_shadow &&
4798 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4799 instr->op != nir_texop_tg4)
4800 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4801 else if (instr->op == nir_texop_txs &&
4802 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4803 instr->is_array) {
4804 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4805 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4806 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4807 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4808 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4809 } else if (ctx->ac.chip_class >= GFX9 &&
4810 instr->op == nir_texop_txs &&
4811 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4812 instr->is_array) {
4813 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4814 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4815 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4816 ctx->ac.i32_1, "");
4817 } else if (instr->dest.ssa.num_components != 4)
4818 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4819
4820 write_result:
4821 if (result) {
4822 assert(instr->dest.is_ssa);
4823 result = ac_to_integer(&ctx->ac, result);
4824 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4825 }
4826 }
4827
4828
4829 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4830 {
4831 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4832 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4833
4834 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4835 _mesa_hash_table_insert(ctx->phis, instr, result);
4836 }
4837
4838 static void visit_post_phi(struct ac_nir_context *ctx,
4839 nir_phi_instr *instr,
4840 LLVMValueRef llvm_phi)
4841 {
4842 nir_foreach_phi_src(src, instr) {
4843 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4844 LLVMValueRef llvm_src = get_src(ctx, src->src);
4845
4846 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4847 }
4848 }
4849
4850 static void phi_post_pass(struct ac_nir_context *ctx)
4851 {
4852 struct hash_entry *entry;
4853 hash_table_foreach(ctx->phis, entry) {
4854 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4855 (LLVMValueRef)entry->data);
4856 }
4857 }
4858
4859
4860 static void visit_ssa_undef(struct ac_nir_context *ctx,
4861 const nir_ssa_undef_instr *instr)
4862 {
4863 unsigned num_components = instr->def.num_components;
4864 LLVMValueRef undef;
4865
4866 if (num_components == 1)
4867 undef = LLVMGetUndef(ctx->ac.i32);
4868 else {
4869 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4870 }
4871 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4872 }
4873
4874 static void visit_jump(struct ac_nir_context *ctx,
4875 const nir_jump_instr *instr)
4876 {
4877 switch (instr->type) {
4878 case nir_jump_break:
4879 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4880 LLVMClearInsertionPosition(ctx->ac.builder);
4881 break;
4882 case nir_jump_continue:
4883 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4884 LLVMClearInsertionPosition(ctx->ac.builder);
4885 break;
4886 default:
4887 fprintf(stderr, "Unknown NIR jump instr: ");
4888 nir_print_instr(&instr->instr, stderr);
4889 fprintf(stderr, "\n");
4890 abort();
4891 }
4892 }
4893
4894 static void visit_cf_list(struct ac_nir_context *ctx,
4895 struct exec_list *list);
4896
4897 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4898 {
4899 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4900 nir_foreach_instr(instr, block)
4901 {
4902 switch (instr->type) {
4903 case nir_instr_type_alu:
4904 visit_alu(ctx, nir_instr_as_alu(instr));
4905 break;
4906 case nir_instr_type_load_const:
4907 visit_load_const(ctx, nir_instr_as_load_const(instr));
4908 break;
4909 case nir_instr_type_intrinsic:
4910 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4911 break;
4912 case nir_instr_type_tex:
4913 visit_tex(ctx, nir_instr_as_tex(instr));
4914 break;
4915 case nir_instr_type_phi:
4916 visit_phi(ctx, nir_instr_as_phi(instr));
4917 break;
4918 case nir_instr_type_ssa_undef:
4919 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4920 break;
4921 case nir_instr_type_jump:
4922 visit_jump(ctx, nir_instr_as_jump(instr));
4923 break;
4924 default:
4925 fprintf(stderr, "Unknown NIR instr type: ");
4926 nir_print_instr(instr, stderr);
4927 fprintf(stderr, "\n");
4928 abort();
4929 }
4930 }
4931
4932 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4933 }
4934
4935 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4936 {
4937 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4938
4939 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4940 LLVMBasicBlockRef merge_block =
4941 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4942 LLVMBasicBlockRef if_block =
4943 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4944 LLVMBasicBlockRef else_block = merge_block;
4945 if (!exec_list_is_empty(&if_stmt->else_list))
4946 else_block = LLVMAppendBasicBlockInContext(
4947 ctx->ac.context, fn, "");
4948
4949 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4950 LLVMConstInt(ctx->ac.i32, 0, false), "");
4951 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4952
4953 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4954 visit_cf_list(ctx, &if_stmt->then_list);
4955 if (LLVMGetInsertBlock(ctx->ac.builder))
4956 LLVMBuildBr(ctx->ac.builder, merge_block);
4957
4958 if (!exec_list_is_empty(&if_stmt->else_list)) {
4959 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4960 visit_cf_list(ctx, &if_stmt->else_list);
4961 if (LLVMGetInsertBlock(ctx->ac.builder))
4962 LLVMBuildBr(ctx->ac.builder, merge_block);
4963 }
4964
4965 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4966 }
4967
4968 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4969 {
4970 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4971 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4972 LLVMBasicBlockRef break_parent = ctx->break_block;
4973
4974 ctx->continue_block =
4975 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4976 ctx->break_block =
4977 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4978
4979 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4980 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4981 visit_cf_list(ctx, &loop->body);
4982
4983 if (LLVMGetInsertBlock(ctx->ac.builder))
4984 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4985 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4986
4987 ctx->continue_block = continue_parent;
4988 ctx->break_block = break_parent;
4989 }
4990
4991 static void visit_cf_list(struct ac_nir_context *ctx,
4992 struct exec_list *list)
4993 {
4994 foreach_list_typed(nir_cf_node, node, node, list)
4995 {
4996 switch (node->type) {
4997 case nir_cf_node_block:
4998 visit_block(ctx, nir_cf_node_as_block(node));
4999 break;
5000
5001 case nir_cf_node_if:
5002 visit_if(ctx, nir_cf_node_as_if(node));
5003 break;
5004
5005 case nir_cf_node_loop:
5006 visit_loop(ctx, nir_cf_node_as_loop(node));
5007 break;
5008
5009 default:
5010 assert(0);
5011 }
5012 }
5013 }
5014
5015 static void
5016 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5017 struct nir_variable *variable)
5018 {
5019 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5020 LLVMValueRef t_offset;
5021 LLVMValueRef t_list;
5022 LLVMValueRef input;
5023 LLVMValueRef buffer_index;
5024 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5025 int idx = variable->data.location;
5026 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5027
5028 variable->data.driver_location = idx * 4;
5029
5030 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5031 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5032 ctx->abi.start_instance, "");
5033 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5034 ctx->shader_info->vs.vgpr_comp_cnt);
5035 } else
5036 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5037 ctx->abi.base_vertex, "");
5038
5039 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5040 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5041
5042 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5043
5044 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5045 buffer_index,
5046 LLVMConstInt(ctx->ac.i32, 0, false),
5047 true);
5048
5049 for (unsigned chan = 0; chan < 4; chan++) {
5050 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5051 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5052 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5053 input, llvm_chan, ""));
5054 }
5055 }
5056 }
5057
5058 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5059 unsigned attr,
5060 LLVMValueRef interp_param,
5061 LLVMValueRef prim_mask,
5062 LLVMValueRef result[4])
5063 {
5064 LLVMValueRef attr_number;
5065 unsigned chan;
5066 LLVMValueRef i, j;
5067 bool interp = interp_param != NULL;
5068
5069 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5070
5071 /* fs.constant returns the param from the middle vertex, so it's not
5072 * really useful for flat shading. It's meant to be used for custom
5073 * interpolation (but the intrinsic can't fetch from the other two
5074 * vertices).
5075 *
5076 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5077 * to do the right thing. The only reason we use fs.constant is that
5078 * fs.interp cannot be used on integers, because they can be equal
5079 * to NaN.
5080 */
5081 if (interp) {
5082 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5083 ctx->ac.v2f32, "");
5084
5085 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5086 ctx->ac.i32_0, "");
5087 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5088 ctx->ac.i32_1, "");
5089 }
5090
5091 for (chan = 0; chan < 4; chan++) {
5092 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5093
5094 if (interp) {
5095 result[chan] = ac_build_fs_interp(&ctx->ac,
5096 llvm_chan,
5097 attr_number,
5098 prim_mask, i, j);
5099 } else {
5100 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5101 LLVMConstInt(ctx->ac.i32, 2, false),
5102 llvm_chan,
5103 attr_number,
5104 prim_mask);
5105 }
5106 }
5107 }
5108
5109 static void
5110 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5111 struct nir_variable *variable)
5112 {
5113 int idx = variable->data.location;
5114 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5115 LLVMValueRef interp;
5116
5117 variable->data.driver_location = idx * 4;
5118 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5119
5120 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5121 unsigned interp_type;
5122 if (variable->data.sample) {
5123 interp_type = INTERP_SAMPLE;
5124 ctx->shader_info->info.ps.force_persample = true;
5125 } else if (variable->data.centroid)
5126 interp_type = INTERP_CENTROID;
5127 else
5128 interp_type = INTERP_CENTER;
5129
5130 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5131 } else
5132 interp = NULL;
5133
5134 for (unsigned i = 0; i < attrib_count; ++i)
5135 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5136
5137 }
5138
5139 static void
5140 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5141 struct nir_shader *nir) {
5142 nir_foreach_variable(variable, &nir->inputs)
5143 handle_vs_input_decl(ctx, variable);
5144 }
5145
5146 static void
5147 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5148 struct nir_shader *nir)
5149 {
5150 if (!ctx->options->key.fs.multisample)
5151 return;
5152
5153 bool uses_center = false;
5154 bool uses_centroid = false;
5155 nir_foreach_variable(variable, &nir->inputs) {
5156 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5157 variable->data.sample)
5158 continue;
5159
5160 if (variable->data.centroid)
5161 uses_centroid = true;
5162 else
5163 uses_center = true;
5164 }
5165
5166 if (uses_center && uses_centroid) {
5167 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5168 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5169 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5170 }
5171 }
5172
5173 static void
5174 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5175 struct nir_shader *nir)
5176 {
5177 prepare_interp_optimize(ctx, nir);
5178
5179 nir_foreach_variable(variable, &nir->inputs)
5180 handle_fs_input_decl(ctx, variable);
5181
5182 unsigned index = 0;
5183
5184 if (ctx->shader_info->info.ps.uses_input_attachments ||
5185 ctx->shader_info->info.needs_multiview_view_index)
5186 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5187
5188 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5189 LLVMValueRef interp_param;
5190 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5191
5192 if (!(ctx->input_mask & (1ull << i)))
5193 continue;
5194
5195 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5196 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5197 interp_param = *inputs;
5198 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5199 inputs);
5200
5201 if (!interp_param)
5202 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5203 ++index;
5204 } else if (i == VARYING_SLOT_POS) {
5205 for(int i = 0; i < 3; ++i)
5206 inputs[i] = ctx->abi.frag_pos[i];
5207
5208 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5209 ctx->abi.frag_pos[3]);
5210 }
5211 }
5212 ctx->shader_info->fs.num_interp = index;
5213 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5214 ctx->shader_info->fs.has_pcoord = true;
5215 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5216 ctx->shader_info->fs.prim_id_input = true;
5217 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5218 ctx->shader_info->fs.layer_input = true;
5219 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5220
5221 if (ctx->shader_info->info.needs_multiview_view_index)
5222 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5223 }
5224
5225 static LLVMValueRef
5226 ac_build_alloca(struct ac_llvm_context *ac,
5227 LLVMTypeRef type,
5228 const char *name)
5229 {
5230 LLVMBuilderRef builder = ac->builder;
5231 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5232 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5233 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5234 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5235 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5236 LLVMValueRef res;
5237
5238 if (first_instr) {
5239 LLVMPositionBuilderBefore(first_builder, first_instr);
5240 } else {
5241 LLVMPositionBuilderAtEnd(first_builder, first_block);
5242 }
5243
5244 res = LLVMBuildAlloca(first_builder, type, name);
5245 LLVMBuildStore(builder, LLVMConstNull(type), res);
5246
5247 LLVMDisposeBuilder(first_builder);
5248
5249 return res;
5250 }
5251
5252 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5253 LLVMTypeRef type,
5254 const char *name)
5255 {
5256 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5257 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5258 return ptr;
5259 }
5260
5261 static void
5262 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5263 struct nir_variable *variable,
5264 struct nir_shader *shader,
5265 gl_shader_stage stage)
5266 {
5267 int idx = variable->data.location + variable->data.index;
5268 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5269 uint64_t mask_attribs;
5270
5271 variable->data.driver_location = idx * 4;
5272
5273 /* tess ctrl has it's own load/store paths for outputs */
5274 if (stage == MESA_SHADER_TESS_CTRL)
5275 return;
5276
5277 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5278 if (stage == MESA_SHADER_VERTEX ||
5279 stage == MESA_SHADER_TESS_EVAL ||
5280 stage == MESA_SHADER_GEOMETRY) {
5281 if (idx == VARYING_SLOT_CLIP_DIST0) {
5282 int length = shader->info.clip_distance_array_size +
5283 shader->info.cull_distance_array_size;
5284 if (stage == MESA_SHADER_VERTEX) {
5285 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5286 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5287 }
5288 if (stage == MESA_SHADER_TESS_EVAL) {
5289 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5290 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5291 }
5292
5293 if (length > 4)
5294 attrib_count = 2;
5295 else
5296 attrib_count = 1;
5297 mask_attribs = 1ull << idx;
5298 }
5299 }
5300
5301 ctx->output_mask |= mask_attribs;
5302 }
5303
5304 static void
5305 handle_shader_output_decl(struct ac_nir_context *ctx,
5306 struct nir_shader *nir,
5307 struct nir_variable *variable)
5308 {
5309 unsigned output_loc = variable->data.driver_location / 4;
5310 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5311
5312 /* tess ctrl has it's own load/store paths for outputs */
5313 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5314 return;
5315
5316 if (ctx->stage == MESA_SHADER_VERTEX ||
5317 ctx->stage == MESA_SHADER_TESS_EVAL ||
5318 ctx->stage == MESA_SHADER_GEOMETRY) {
5319 int idx = variable->data.location + variable->data.index;
5320 if (idx == VARYING_SLOT_CLIP_DIST0) {
5321 int length = nir->info.clip_distance_array_size +
5322 nir->info.cull_distance_array_size;
5323
5324 if (length > 4)
5325 attrib_count = 2;
5326 else
5327 attrib_count = 1;
5328 }
5329 }
5330
5331 for (unsigned i = 0; i < attrib_count; ++i) {
5332 for (unsigned chan = 0; chan < 4; chan++) {
5333 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5334 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5335 }
5336 }
5337 }
5338
5339 static LLVMTypeRef
5340 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5341 enum glsl_base_type type)
5342 {
5343 switch (type) {
5344 case GLSL_TYPE_INT:
5345 case GLSL_TYPE_UINT:
5346 case GLSL_TYPE_BOOL:
5347 case GLSL_TYPE_SUBROUTINE:
5348 return ctx->ac.i32;
5349 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5350 return ctx->ac.f32;
5351 case GLSL_TYPE_INT64:
5352 case GLSL_TYPE_UINT64:
5353 return ctx->ac.i64;
5354 case GLSL_TYPE_DOUBLE:
5355 return ctx->ac.f64;
5356 default:
5357 unreachable("unknown GLSL type");
5358 }
5359 }
5360
5361 static LLVMTypeRef
5362 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5363 const struct glsl_type *type)
5364 {
5365 if (glsl_type_is_scalar(type)) {
5366 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5367 }
5368
5369 if (glsl_type_is_vector(type)) {
5370 return LLVMVectorType(
5371 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5372 glsl_get_vector_elements(type));
5373 }
5374
5375 if (glsl_type_is_matrix(type)) {
5376 return LLVMArrayType(
5377 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5378 glsl_get_matrix_columns(type));
5379 }
5380
5381 if (glsl_type_is_array(type)) {
5382 return LLVMArrayType(
5383 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5384 glsl_get_length(type));
5385 }
5386
5387 assert(glsl_type_is_struct(type));
5388
5389 LLVMTypeRef member_types[glsl_get_length(type)];
5390
5391 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5392 member_types[i] =
5393 glsl_to_llvm_type(ctx,
5394 glsl_get_struct_field(type, i));
5395 }
5396
5397 return LLVMStructTypeInContext(ctx->context, member_types,
5398 glsl_get_length(type), false);
5399 }
5400
5401 static void
5402 setup_locals(struct ac_nir_context *ctx,
5403 struct nir_function *func)
5404 {
5405 int i, j;
5406 ctx->num_locals = 0;
5407 nir_foreach_variable(variable, &func->impl->locals) {
5408 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5409 variable->data.driver_location = ctx->num_locals * 4;
5410 ctx->num_locals += attrib_count;
5411 }
5412 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5413 if (!ctx->locals)
5414 return;
5415
5416 for (i = 0; i < ctx->num_locals; i++) {
5417 for (j = 0; j < 4; j++) {
5418 ctx->locals[i * 4 + j] =
5419 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5420 }
5421 }
5422 }
5423
5424 static void
5425 setup_shared(struct ac_nir_context *ctx,
5426 struct nir_shader *nir)
5427 {
5428 nir_foreach_variable(variable, &nir->shared) {
5429 LLVMValueRef shared =
5430 LLVMAddGlobalInAddressSpace(
5431 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5432 variable->name ? variable->name : "",
5433 LOCAL_ADDR_SPACE);
5434 _mesa_hash_table_insert(ctx->vars, variable, shared);
5435 }
5436 }
5437
5438 static LLVMValueRef
5439 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5440 {
5441 v = ac_to_float(ctx, v);
5442 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5443 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5444 }
5445
5446
5447 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5448 LLVMValueRef src0, LLVMValueRef src1)
5449 {
5450 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5451 LLVMValueRef comp[2];
5452
5453 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5454 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5455 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5456 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5457 }
5458
5459 /* Initialize arguments for the shader export intrinsic */
5460 static void
5461 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5462 LLVMValueRef *values,
5463 unsigned target,
5464 struct ac_export_args *args)
5465 {
5466 /* Default is 0xf. Adjusted below depending on the format. */
5467 args->enabled_channels = 0xf;
5468
5469 /* Specify whether the EXEC mask represents the valid mask */
5470 args->valid_mask = 0;
5471
5472 /* Specify whether this is the last export */
5473 args->done = 0;
5474
5475 /* Specify the target we are exporting */
5476 args->target = target;
5477
5478 args->compr = false;
5479 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5480 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5481 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5482 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5483
5484 if (!values)
5485 return;
5486
5487 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5488 LLVMValueRef val[4];
5489 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5490 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5491 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5492 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5493
5494 switch(col_format) {
5495 case V_028714_SPI_SHADER_ZERO:
5496 args->enabled_channels = 0; /* writemask */
5497 args->target = V_008DFC_SQ_EXP_NULL;
5498 break;
5499
5500 case V_028714_SPI_SHADER_32_R:
5501 args->enabled_channels = 1;
5502 args->out[0] = values[0];
5503 break;
5504
5505 case V_028714_SPI_SHADER_32_GR:
5506 args->enabled_channels = 0x3;
5507 args->out[0] = values[0];
5508 args->out[1] = values[1];
5509 break;
5510
5511 case V_028714_SPI_SHADER_32_AR:
5512 args->enabled_channels = 0x9;
5513 args->out[0] = values[0];
5514 args->out[3] = values[3];
5515 break;
5516
5517 case V_028714_SPI_SHADER_FP16_ABGR:
5518 args->compr = 1;
5519
5520 for (unsigned chan = 0; chan < 2; chan++) {
5521 LLVMValueRef pack_args[2] = {
5522 values[2 * chan],
5523 values[2 * chan + 1]
5524 };
5525 LLVMValueRef packed;
5526
5527 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5528 args->out[chan] = packed;
5529 }
5530 break;
5531
5532 case V_028714_SPI_SHADER_UNORM16_ABGR:
5533 for (unsigned chan = 0; chan < 4; chan++) {
5534 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5535 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5536 LLVMConstReal(ctx->ac.f32, 65535), "");
5537 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5538 LLVMConstReal(ctx->ac.f32, 0.5), "");
5539 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5540 ctx->ac.i32, "");
5541 }
5542
5543 args->compr = 1;
5544 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5545 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5546 break;
5547
5548 case V_028714_SPI_SHADER_SNORM16_ABGR:
5549 for (unsigned chan = 0; chan < 4; chan++) {
5550 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5551 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5552 LLVMConstReal(ctx->ac.f32, 32767), "");
5553
5554 /* If positive, add 0.5, else add -0.5. */
5555 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5556 LLVMBuildSelect(ctx->builder,
5557 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5558 val[chan], ctx->ac.f32_0, ""),
5559 LLVMConstReal(ctx->ac.f32, 0.5),
5560 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5561 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5562 }
5563
5564 args->compr = 1;
5565 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5566 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5567 break;
5568
5569 case V_028714_SPI_SHADER_UINT16_ABGR: {
5570 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5571 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5572 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5573
5574 for (unsigned chan = 0; chan < 4; chan++) {
5575 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5576 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5577 }
5578
5579 args->compr = 1;
5580 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5581 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5582 break;
5583 }
5584
5585 case V_028714_SPI_SHADER_SINT16_ABGR: {
5586 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5587 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5588 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5589 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5590 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5591 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5592
5593 /* Clamp. */
5594 for (unsigned chan = 0; chan < 4; chan++) {
5595 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5596 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5597 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5598 }
5599
5600 args->compr = 1;
5601 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5602 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5603 break;
5604 }
5605
5606 default:
5607 case V_028714_SPI_SHADER_32_ABGR:
5608 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5609 break;
5610 }
5611 } else
5612 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5613
5614 for (unsigned i = 0; i < 4; ++i)
5615 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5616 }
5617
5618 static void
5619 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5620 bool export_prim_id,
5621 struct ac_vs_output_info *outinfo)
5622 {
5623 uint32_t param_count = 0;
5624 unsigned target;
5625 unsigned pos_idx, num_pos_exports = 0;
5626 struct ac_export_args args, pos_args[4] = {};
5627 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5628 int i;
5629
5630 if (ctx->options->key.has_multiview_view_index) {
5631 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5632 if(!*tmp_out) {
5633 for(unsigned i = 0; i < 4; ++i)
5634 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5635 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5636 }
5637
5638 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5639 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5640 }
5641
5642 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5643 sizeof(outinfo->vs_output_param_offset));
5644
5645 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5646 LLVMValueRef slots[8];
5647 unsigned j;
5648
5649 if (outinfo->cull_dist_mask)
5650 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5651
5652 i = VARYING_SLOT_CLIP_DIST0;
5653 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5654 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5655 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5656
5657 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5658 slots[i] = LLVMGetUndef(ctx->ac.f32);
5659
5660 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5661 target = V_008DFC_SQ_EXP_POS + 3;
5662 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5663 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5664 &args, sizeof(args));
5665 }
5666
5667 target = V_008DFC_SQ_EXP_POS + 2;
5668 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5669 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5670 &args, sizeof(args));
5671
5672 }
5673
5674 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5675 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5676 for (unsigned j = 0; j < 4; j++)
5677 pos_values[j] = LLVMBuildLoad(ctx->builder,
5678 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5679 }
5680 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5681
5682 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5683 outinfo->writes_pointsize = true;
5684 psize_value = LLVMBuildLoad(ctx->builder,
5685 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5686 }
5687
5688 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5689 outinfo->writes_layer = true;
5690 layer_value = LLVMBuildLoad(ctx->builder,
5691 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5692 }
5693
5694 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5695 outinfo->writes_viewport_index = true;
5696 viewport_index_value = LLVMBuildLoad(ctx->builder,
5697 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5698 }
5699
5700 if (outinfo->writes_pointsize ||
5701 outinfo->writes_layer ||
5702 outinfo->writes_viewport_index) {
5703 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5704 (outinfo->writes_layer == true ? 4 : 0));
5705 pos_args[1].valid_mask = 0;
5706 pos_args[1].done = 0;
5707 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5708 pos_args[1].compr = 0;
5709 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5710 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5711 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5712 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5713
5714 if (outinfo->writes_pointsize == true)
5715 pos_args[1].out[0] = psize_value;
5716 if (outinfo->writes_layer == true)
5717 pos_args[1].out[2] = layer_value;
5718 if (outinfo->writes_viewport_index == true) {
5719 if (ctx->options->chip_class >= GFX9) {
5720 /* GFX9 has the layer in out.z[10:0] and the viewport
5721 * index in out.z[19:16].
5722 */
5723 LLVMValueRef v = viewport_index_value;
5724 v = ac_to_integer(&ctx->ac, v);
5725 v = LLVMBuildShl(ctx->builder, v,
5726 LLVMConstInt(ctx->ac.i32, 16, false),
5727 "");
5728 v = LLVMBuildOr(ctx->builder, v,
5729 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5730
5731 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5732 pos_args[1].enabled_channels |= 1 << 2;
5733 } else {
5734 pos_args[1].out[3] = viewport_index_value;
5735 pos_args[1].enabled_channels |= 1 << 3;
5736 }
5737 }
5738 }
5739 for (i = 0; i < 4; i++) {
5740 if (pos_args[i].out[0])
5741 num_pos_exports++;
5742 }
5743
5744 pos_idx = 0;
5745 for (i = 0; i < 4; i++) {
5746 if (!pos_args[i].out[0])
5747 continue;
5748
5749 /* Specify the target we are exporting */
5750 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5751 if (pos_idx == num_pos_exports)
5752 pos_args[i].done = 1;
5753 ac_build_export(&ctx->ac, &pos_args[i]);
5754 }
5755
5756 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5757 LLVMValueRef values[4];
5758 if (!(ctx->output_mask & (1ull << i)))
5759 continue;
5760
5761 for (unsigned j = 0; j < 4; j++)
5762 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5763 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5764
5765 if (i == VARYING_SLOT_LAYER) {
5766 target = V_008DFC_SQ_EXP_PARAM + param_count;
5767 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5768 param_count++;
5769 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5770 target = V_008DFC_SQ_EXP_PARAM + param_count;
5771 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5772 param_count++;
5773 } else if (i >= VARYING_SLOT_VAR0) {
5774 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5775 target = V_008DFC_SQ_EXP_PARAM + param_count;
5776 outinfo->vs_output_param_offset[i] = param_count;
5777 param_count++;
5778 } else
5779 continue;
5780
5781 si_llvm_init_export_args(ctx, values, target, &args);
5782
5783 if (target >= V_008DFC_SQ_EXP_POS &&
5784 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5785 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5786 &args, sizeof(args));
5787 } else {
5788 ac_build_export(&ctx->ac, &args);
5789 }
5790 }
5791
5792 if (export_prim_id) {
5793 LLVMValueRef values[4];
5794 target = V_008DFC_SQ_EXP_PARAM + param_count;
5795 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5796 param_count++;
5797
5798 values[0] = ctx->vs_prim_id;
5799 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5800 ctx->shader_info->vs.vgpr_comp_cnt);
5801 for (unsigned j = 1; j < 4; j++)
5802 values[j] = ctx->ac.f32_0;
5803 si_llvm_init_export_args(ctx, values, target, &args);
5804 ac_build_export(&ctx->ac, &args);
5805 outinfo->export_prim_id = true;
5806 }
5807
5808 outinfo->pos_exports = num_pos_exports;
5809 outinfo->param_exports = param_count;
5810 }
5811
5812 static void
5813 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5814 struct ac_es_output_info *outinfo)
5815 {
5816 int j;
5817 uint64_t max_output_written = 0;
5818 LLVMValueRef lds_base = NULL;
5819
5820 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5821 int param_index;
5822 int length = 4;
5823
5824 if (!(ctx->output_mask & (1ull << i)))
5825 continue;
5826
5827 if (i == VARYING_SLOT_CLIP_DIST0)
5828 length = ctx->num_output_clips + ctx->num_output_culls;
5829
5830 param_index = shader_io_get_unique_index(i);
5831
5832 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5833 }
5834
5835 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5836
5837 if (ctx->ac.chip_class >= GFX9) {
5838 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5839 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5840 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5841 LLVMConstInt(ctx->ac.i32, 24, false),
5842 LLVMConstInt(ctx->ac.i32, 4, false), false);
5843 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5844 LLVMBuildMul(ctx->ac.builder, wave_idx,
5845 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5846 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5847 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5848 }
5849
5850 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5851 LLVMValueRef dw_addr;
5852 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5853 int param_index;
5854 int length = 4;
5855
5856 if (!(ctx->output_mask & (1ull << i)))
5857 continue;
5858
5859 if (i == VARYING_SLOT_CLIP_DIST0)
5860 length = ctx->num_output_clips + ctx->num_output_culls;
5861
5862 param_index = shader_io_get_unique_index(i);
5863
5864 if (lds_base) {
5865 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5866 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
5867 "");
5868 }
5869 for (j = 0; j < length; j++) {
5870 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5871 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
5872
5873 if (ctx->ac.chip_class >= GFX9) {
5874 ac_lds_store(&ctx->ac, dw_addr,
5875 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5876 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5877 } else {
5878 ac_build_buffer_store_dword(&ctx->ac,
5879 ctx->esgs_ring,
5880 out_val, 1,
5881 NULL, ctx->es2gs_offset,
5882 (4 * param_index + j) * 4,
5883 1, 1, true, true);
5884 }
5885 }
5886 }
5887 }
5888
5889 static void
5890 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5891 {
5892 LLVMValueRef vertex_id = ctx->rel_auto_id;
5893 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5894 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5895 vertex_dw_stride, "");
5896
5897 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5898 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5899 int length = 4;
5900
5901 if (!(ctx->output_mask & (1ull << i)))
5902 continue;
5903
5904 if (i == VARYING_SLOT_CLIP_DIST0)
5905 length = ctx->num_output_clips + ctx->num_output_culls;
5906 int param = shader_io_get_unique_index(i);
5907 mark_tess_output(ctx, false, param);
5908 if (length > 4)
5909 mark_tess_output(ctx, false, param + 1);
5910 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5911 LLVMConstInt(ctx->ac.i32, param * 4, false),
5912 "");
5913 for (unsigned j = 0; j < length; j++) {
5914 ac_lds_store(&ctx->ac, dw_addr,
5915 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5916 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5917 }
5918 }
5919 }
5920
5921 struct ac_build_if_state
5922 {
5923 struct nir_to_llvm_context *ctx;
5924 LLVMValueRef condition;
5925 LLVMBasicBlockRef entry_block;
5926 LLVMBasicBlockRef true_block;
5927 LLVMBasicBlockRef false_block;
5928 LLVMBasicBlockRef merge_block;
5929 };
5930
5931 static LLVMBasicBlockRef
5932 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5933 {
5934 LLVMBasicBlockRef current_block;
5935 LLVMBasicBlockRef next_block;
5936 LLVMBasicBlockRef new_block;
5937
5938 /* get current basic block */
5939 current_block = LLVMGetInsertBlock(ctx->builder);
5940
5941 /* chqeck if there's another block after this one */
5942 next_block = LLVMGetNextBasicBlock(current_block);
5943 if (next_block) {
5944 /* insert the new block before the next block */
5945 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5946 }
5947 else {
5948 /* append new block after current block */
5949 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5950 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5951 }
5952 return new_block;
5953 }
5954
5955 static void
5956 ac_nir_build_if(struct ac_build_if_state *ifthen,
5957 struct nir_to_llvm_context *ctx,
5958 LLVMValueRef condition)
5959 {
5960 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5961
5962 memset(ifthen, 0, sizeof *ifthen);
5963 ifthen->ctx = ctx;
5964 ifthen->condition = condition;
5965 ifthen->entry_block = block;
5966
5967 /* create endif/merge basic block for the phi functions */
5968 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5969
5970 /* create/insert true_block before merge_block */
5971 ifthen->true_block =
5972 LLVMInsertBasicBlockInContext(ctx->context,
5973 ifthen->merge_block,
5974 "if-true-block");
5975
5976 /* successive code goes into the true block */
5977 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5978 }
5979
5980 /**
5981 * End a conditional.
5982 */
5983 static void
5984 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5985 {
5986 LLVMBuilderRef builder = ifthen->ctx->builder;
5987
5988 /* Insert branch to the merge block from current block */
5989 LLVMBuildBr(builder, ifthen->merge_block);
5990
5991 /*
5992 * Now patch in the various branch instructions.
5993 */
5994
5995 /* Insert the conditional branch instruction at the end of entry_block */
5996 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5997 if (ifthen->false_block) {
5998 /* we have an else clause */
5999 LLVMBuildCondBr(builder, ifthen->condition,
6000 ifthen->true_block, ifthen->false_block);
6001 }
6002 else {
6003 /* no else clause */
6004 LLVMBuildCondBr(builder, ifthen->condition,
6005 ifthen->true_block, ifthen->merge_block);
6006 }
6007
6008 /* Resume building code at end of the ifthen->merge_block */
6009 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6010 }
6011
6012 static void
6013 write_tess_factors(struct nir_to_llvm_context *ctx)
6014 {
6015 unsigned stride, outer_comps, inner_comps;
6016 struct ac_build_if_state if_ctx, inner_if_ctx;
6017 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6018 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6019 unsigned tess_inner_index, tess_outer_index;
6020 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6021 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6022 int i;
6023 emit_barrier(ctx);
6024
6025 switch (ctx->options->key.tcs.primitive_mode) {
6026 case GL_ISOLINES:
6027 stride = 2;
6028 outer_comps = 2;
6029 inner_comps = 0;
6030 break;
6031 case GL_TRIANGLES:
6032 stride = 4;
6033 outer_comps = 3;
6034 inner_comps = 1;
6035 break;
6036 case GL_QUADS:
6037 stride = 6;
6038 outer_comps = 4;
6039 inner_comps = 2;
6040 break;
6041 default:
6042 return;
6043 }
6044
6045 ac_nir_build_if(&if_ctx, ctx,
6046 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6047 invocation_id, ctx->ac.i32_0, ""));
6048
6049 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6050 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6051
6052 mark_tess_output(ctx, true, tess_inner_index);
6053 mark_tess_output(ctx, true, tess_outer_index);
6054 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6055 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6056 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6057 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6058 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6059
6060 for (i = 0; i < 4; i++) {
6061 inner[i] = LLVMGetUndef(ctx->ac.i32);
6062 outer[i] = LLVMGetUndef(ctx->ac.i32);
6063 }
6064
6065 // LINES reverseal
6066 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6067 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6068 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6069 LLVMConstInt(ctx->ac.i32, 1, false), "");
6070 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6071 } else {
6072 for (i = 0; i < outer_comps; i++) {
6073 outer[i] = out[i] =
6074 ac_lds_load(&ctx->ac, lds_outer);
6075 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6076 LLVMConstInt(ctx->ac.i32, 1, false), "");
6077 }
6078 for (i = 0; i < inner_comps; i++) {
6079 inner[i] = out[outer_comps+i] =
6080 ac_lds_load(&ctx->ac, lds_inner);
6081 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6082 LLVMConstInt(ctx->ac.i32, 1, false), "");
6083 }
6084 }
6085
6086 /* Convert the outputs to vectors for stores. */
6087 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6088 vec1 = NULL;
6089
6090 if (stride > 4)
6091 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6092
6093
6094 buffer = ctx->hs_ring_tess_factor;
6095 tf_base = ctx->tess_factor_offset;
6096 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6097 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6098 unsigned tf_offset = 0;
6099
6100 if (ctx->options->chip_class <= VI) {
6101 ac_nir_build_if(&inner_if_ctx, ctx,
6102 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6103 rel_patch_id, ctx->ac.i32_0, ""));
6104
6105 /* Store the dynamic HS control word. */
6106 ac_build_buffer_store_dword(&ctx->ac, buffer,
6107 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6108 1, ctx->ac.i32_0, tf_base,
6109 0, 1, 0, true, false);
6110 tf_offset += 4;
6111
6112 ac_nir_build_endif(&inner_if_ctx);
6113 }
6114
6115 /* Store the tessellation factors. */
6116 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6117 MIN2(stride, 4), byteoffset, tf_base,
6118 tf_offset, 1, 0, true, false);
6119 if (vec1)
6120 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6121 stride - 4, byteoffset, tf_base,
6122 16 + tf_offset, 1, 0, true, false);
6123
6124 //store to offchip for TES to read - only if TES reads them
6125 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6126 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6127 LLVMValueRef tf_inner_offset;
6128 unsigned param_outer, param_inner;
6129
6130 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6131 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6132 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6133
6134 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6135 util_next_power_of_two(outer_comps));
6136
6137 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6138 outer_comps, tf_outer_offset,
6139 ctx->oc_lds, 0, 1, 0, true, false);
6140 if (inner_comps) {
6141 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6142 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6143 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6144
6145 inner_vec = inner_comps == 1 ? inner[0] :
6146 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6147 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6148 inner_comps, tf_inner_offset,
6149 ctx->oc_lds, 0, 1, 0, true, false);
6150 }
6151 }
6152 ac_nir_build_endif(&if_ctx);
6153 }
6154
6155 static void
6156 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6157 {
6158 write_tess_factors(ctx);
6159 }
6160
6161 static bool
6162 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6163 LLVMValueRef *color, unsigned param, bool is_last,
6164 struct ac_export_args *args)
6165 {
6166 /* Export */
6167 si_llvm_init_export_args(ctx, color, param,
6168 args);
6169
6170 if (is_last) {
6171 args->valid_mask = 1; /* whether the EXEC mask is valid */
6172 args->done = 1; /* DONE bit */
6173 } else if (!args->enabled_channels)
6174 return false; /* unnecessary NULL export */
6175
6176 return true;
6177 }
6178
6179 static void
6180 si_export_mrt_z(struct nir_to_llvm_context *ctx,
6181 LLVMValueRef depth, LLVMValueRef stencil,
6182 LLVMValueRef samplemask)
6183 {
6184 struct ac_export_args args;
6185
6186 args.enabled_channels = 0;
6187 args.valid_mask = 1;
6188 args.done = 1;
6189 args.target = V_008DFC_SQ_EXP_MRTZ;
6190 args.compr = false;
6191
6192 args.out[0] = LLVMGetUndef(ctx->ac.f32); /* R, depth */
6193 args.out[1] = LLVMGetUndef(ctx->ac.f32); /* G, stencil test val[0:7], stencil op val[8:15] */
6194 args.out[2] = LLVMGetUndef(ctx->ac.f32); /* B, sample mask */
6195 args.out[3] = LLVMGetUndef(ctx->ac.f32); /* A, alpha to mask */
6196
6197 if (depth) {
6198 args.out[0] = depth;
6199 args.enabled_channels |= 0x1;
6200 }
6201
6202 if (stencil) {
6203 args.out[1] = stencil;
6204 args.enabled_channels |= 0x2;
6205 }
6206
6207 if (samplemask) {
6208 args.out[2] = samplemask;
6209 args.enabled_channels |= 0x4;
6210 }
6211
6212 /* SI (except OLAND and HAINAN) has a bug that it only looks
6213 * at the X writemask component. */
6214 if (ctx->options->chip_class == SI &&
6215 ctx->options->family != CHIP_OLAND &&
6216 ctx->options->family != CHIP_HAINAN)
6217 args.enabled_channels |= 0x1;
6218
6219 ac_build_export(&ctx->ac, &args);
6220 }
6221
6222 static void
6223 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6224 {
6225 unsigned index = 0;
6226 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6227 struct ac_export_args color_args[8];
6228
6229 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6230 LLVMValueRef values[4];
6231
6232 if (!(ctx->output_mask & (1ull << i)))
6233 continue;
6234
6235 if (i == FRAG_RESULT_DEPTH) {
6236 ctx->shader_info->fs.writes_z = true;
6237 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6238 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6239 } else if (i == FRAG_RESULT_STENCIL) {
6240 ctx->shader_info->fs.writes_stencil = true;
6241 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6242 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6243 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6244 ctx->shader_info->fs.writes_sample_mask = true;
6245 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6246 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6247 } else {
6248 bool last = false;
6249 for (unsigned j = 0; j < 4; j++)
6250 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6251 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6252
6253 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6254 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6255
6256 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6257 if (ret)
6258 index++;
6259 }
6260 }
6261
6262 for (unsigned i = 0; i < index; i++)
6263 ac_build_export(&ctx->ac, &color_args[i]);
6264 if (depth || stencil || samplemask)
6265 si_export_mrt_z(ctx, depth, stencil, samplemask);
6266 else if (!index) {
6267 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6268 ac_build_export(&ctx->ac, &color_args[0]);
6269 }
6270
6271 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6272 }
6273
6274 static void
6275 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6276 {
6277 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6278 }
6279
6280 static void
6281 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6282 LLVMValueRef *addrs)
6283 {
6284 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6285
6286 switch (ctx->stage) {
6287 case MESA_SHADER_VERTEX:
6288 if (ctx->options->key.vs.as_ls)
6289 handle_ls_outputs_post(ctx);
6290 else if (ctx->options->key.vs.as_es)
6291 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6292 else
6293 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6294 &ctx->shader_info->vs.outinfo);
6295 break;
6296 case MESA_SHADER_FRAGMENT:
6297 handle_fs_outputs_post(ctx);
6298 break;
6299 case MESA_SHADER_GEOMETRY:
6300 emit_gs_epilogue(ctx);
6301 break;
6302 case MESA_SHADER_TESS_CTRL:
6303 handle_tcs_outputs_post(ctx);
6304 break;
6305 case MESA_SHADER_TESS_EVAL:
6306 if (ctx->options->key.tes.as_es)
6307 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6308 else
6309 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6310 &ctx->shader_info->tes.outinfo);
6311 break;
6312 default:
6313 break;
6314 }
6315 }
6316
6317 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6318 {
6319 LLVMPassManagerRef passmgr;
6320 /* Create the pass manager */
6321 passmgr = LLVMCreateFunctionPassManagerForModule(
6322 ctx->module);
6323
6324 /* This pass should eliminate all the load and store instructions */
6325 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6326
6327 /* Add some optimization passes */
6328 LLVMAddScalarReplAggregatesPass(passmgr);
6329 LLVMAddLICMPass(passmgr);
6330 LLVMAddAggressiveDCEPass(passmgr);
6331 LLVMAddCFGSimplificationPass(passmgr);
6332 LLVMAddInstructionCombiningPass(passmgr);
6333
6334 /* Run the pass */
6335 LLVMInitializeFunctionPassManager(passmgr);
6336 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6337 LLVMFinalizeFunctionPassManager(passmgr);
6338
6339 LLVMDisposeBuilder(ctx->builder);
6340 LLVMDisposePassManager(passmgr);
6341 }
6342
6343 static void
6344 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6345 {
6346 struct ac_vs_output_info *outinfo;
6347
6348 switch (ctx->stage) {
6349 case MESA_SHADER_FRAGMENT:
6350 case MESA_SHADER_COMPUTE:
6351 case MESA_SHADER_TESS_CTRL:
6352 case MESA_SHADER_GEOMETRY:
6353 return;
6354 case MESA_SHADER_VERTEX:
6355 if (ctx->options->key.vs.as_ls ||
6356 ctx->options->key.vs.as_es)
6357 return;
6358 outinfo = &ctx->shader_info->vs.outinfo;
6359 break;
6360 case MESA_SHADER_TESS_EVAL:
6361 if (ctx->options->key.vs.as_es)
6362 return;
6363 outinfo = &ctx->shader_info->tes.outinfo;
6364 break;
6365 default:
6366 unreachable("Unhandled shader type");
6367 }
6368
6369 ac_optimize_vs_outputs(&ctx->ac,
6370 ctx->main_function,
6371 outinfo->vs_output_param_offset,
6372 VARYING_SLOT_MAX,
6373 &outinfo->param_exports);
6374 }
6375
6376 static void
6377 ac_setup_rings(struct nir_to_llvm_context *ctx)
6378 {
6379 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6380 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6381 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6382 }
6383
6384 if (ctx->is_gs_copy_shader) {
6385 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6386 }
6387 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6388 LLVMValueRef tmp;
6389 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6390 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6391
6392 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6393
6394 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6395 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6396 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6397 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6398 }
6399
6400 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6401 ctx->stage == MESA_SHADER_TESS_EVAL) {
6402 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6403 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6404 }
6405 }
6406
6407 static unsigned
6408 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6409 const struct nir_shader *nir)
6410 {
6411 switch (nir->info.stage) {
6412 case MESA_SHADER_TESS_CTRL:
6413 return chip_class >= CIK ? 128 : 64;
6414 case MESA_SHADER_GEOMETRY:
6415 return chip_class >= GFX9 ? 128 : 64;
6416 case MESA_SHADER_COMPUTE:
6417 break;
6418 default:
6419 return 0;
6420 }
6421
6422 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6423 nir->info.cs.local_size[1] *
6424 nir->info.cs.local_size[2];
6425 return max_workgroup_size;
6426 }
6427
6428 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6429 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6430 {
6431 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6432 LLVMConstInt(ctx->ac.i32, 8, false),
6433 LLVMConstInt(ctx->ac.i32, 8, false), false);
6434 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6435 LLVMConstInt(ctx->ac.i32, 0, false), "");
6436 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6437 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6438 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6439 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6440 }
6441
6442 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6443 {
6444 for(int i = 5; i >= 0; --i) {
6445 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6446 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6447 LLVMConstInt(ctx->ac.i32, 16, false), false);
6448 }
6449
6450 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6451 LLVMConstInt(ctx->ac.i32, 16, false),
6452 LLVMConstInt(ctx->ac.i32, 8, false), false);
6453 }
6454
6455 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6456 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6457 {
6458 struct ac_nir_context ctx = {};
6459 struct nir_function *func;
6460
6461 ctx.ac = *ac;
6462 ctx.abi = abi;
6463
6464 ctx.nctx = nctx;
6465 if (nctx)
6466 nctx->nir = &ctx;
6467
6468 ctx.stage = nir->info.stage;
6469
6470 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6471
6472 nir_foreach_variable(variable, &nir->outputs)
6473 handle_shader_output_decl(&ctx, nir, variable);
6474
6475 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6476 _mesa_key_pointer_equal);
6477 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6478 _mesa_key_pointer_equal);
6479 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6480 _mesa_key_pointer_equal);
6481
6482 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6483
6484 setup_locals(&ctx, func);
6485
6486 if (nir->info.stage == MESA_SHADER_COMPUTE)
6487 setup_shared(&ctx, nir);
6488
6489 visit_cf_list(&ctx, &func->impl->body);
6490 phi_post_pass(&ctx);
6491
6492 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6493 ctx.outputs);
6494
6495 free(ctx.locals);
6496 ralloc_free(ctx.defs);
6497 ralloc_free(ctx.phis);
6498 ralloc_free(ctx.vars);
6499
6500 if (nctx)
6501 nctx->nir = NULL;
6502 }
6503
6504 static
6505 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6506 struct nir_shader *const *shaders,
6507 int shader_count,
6508 struct ac_shader_variant_info *shader_info,
6509 const struct ac_nir_compiler_options *options)
6510 {
6511 struct nir_to_llvm_context ctx = {0};
6512 unsigned i;
6513 ctx.options = options;
6514 ctx.shader_info = shader_info;
6515 ctx.context = LLVMContextCreate();
6516 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6517
6518 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6519 ctx.ac.module = ctx.module;
6520 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6521
6522 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6523 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6524 LLVMSetDataLayout(ctx.module, data_layout_str);
6525 LLVMDisposeTargetData(data_layout);
6526 LLVMDisposeMessage(data_layout_str);
6527
6528 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6529 ctx.ac.builder = ctx.builder;
6530
6531 memset(shader_info, 0, sizeof(*shader_info));
6532
6533 for(int i = 0; i < shader_count; ++i)
6534 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6535
6536 for (i = 0; i < AC_UD_MAX_SETS; i++)
6537 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6538 for (i = 0; i < AC_UD_MAX_UD; i++)
6539 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6540
6541 ctx.max_workgroup_size = 0;
6542 for (int i = 0; i < shader_count; ++i) {
6543 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6544 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6545 shaders[i]));
6546 }
6547
6548 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6549 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6550
6551 ctx.abi.inputs = &ctx.inputs[0];
6552 ctx.abi.emit_outputs = handle_shader_outputs_post;
6553 ctx.abi.emit_vertex = visit_emit_vertex;
6554 ctx.abi.load_ssbo = radv_load_ssbo;
6555 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6556 ctx.abi.clamp_shadow_reference = false;
6557
6558 if (shader_count >= 2)
6559 ac_init_exec_full_mask(&ctx.ac);
6560
6561 if (ctx.ac.chip_class == GFX9 &&
6562 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6563 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6564
6565 for(int i = 0; i < shader_count; ++i) {
6566 ctx.stage = shaders[i]->info.stage;
6567 ctx.output_mask = 0;
6568 ctx.tess_outputs_written = 0;
6569 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6570 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6571
6572 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6573 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6574 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6575 ctx.abi.load_inputs = load_gs_input;
6576 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6577 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6578 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6579 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6580 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6581 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6582 if (shader_info->info.vs.needs_instance_id) {
6583 ctx.shader_info->vs.vgpr_comp_cnt =
6584 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6585 }
6586 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6587 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6588 }
6589
6590 if (i)
6591 emit_barrier(&ctx);
6592
6593 ac_setup_rings(&ctx);
6594
6595 LLVMBasicBlockRef merge_block;
6596 if (shader_count >= 2) {
6597 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6598 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6599 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6600
6601 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6602 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6603 LLVMConstInt(ctx.ac.i32, 8, false), false);
6604 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6605 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6606 thread_id, count, "");
6607 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6608
6609 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6610 }
6611
6612 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6613 handle_fs_inputs(&ctx, shaders[i]);
6614 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6615 handle_vs_inputs(&ctx, shaders[i]);
6616 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6617 prepare_gs_input_vgprs(&ctx);
6618
6619 nir_foreach_variable(variable, &shaders[i]->outputs)
6620 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6621
6622 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6623
6624 if (shader_count >= 2) {
6625 LLVMBuildBr(ctx.ac.builder, merge_block);
6626 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6627 }
6628
6629 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6630 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6631 shaders[i]->info.cull_distance_array_size > 4;
6632 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6633 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6634 shaders[i]->info.gs.vertices_out;
6635 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6636 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6637 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6638 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6639 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6640 }
6641 }
6642
6643 LLVMBuildRetVoid(ctx.builder);
6644
6645 ac_llvm_finalize_module(&ctx);
6646
6647 if (shader_count == 1)
6648 ac_nir_eliminate_const_vs_outputs(&ctx);
6649
6650 return ctx.module;
6651 }
6652
6653 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6654 {
6655 unsigned *retval = (unsigned *)context;
6656 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6657 char *description = LLVMGetDiagInfoDescription(di);
6658
6659 if (severity == LLVMDSError) {
6660 *retval = 1;
6661 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6662 description);
6663 }
6664
6665 LLVMDisposeMessage(description);
6666 }
6667
6668 static unsigned ac_llvm_compile(LLVMModuleRef M,
6669 struct ac_shader_binary *binary,
6670 LLVMTargetMachineRef tm)
6671 {
6672 unsigned retval = 0;
6673 char *err;
6674 LLVMContextRef llvm_ctx;
6675 LLVMMemoryBufferRef out_buffer;
6676 unsigned buffer_size;
6677 const char *buffer_data;
6678 LLVMBool mem_err;
6679
6680 /* Setup Diagnostic Handler*/
6681 llvm_ctx = LLVMGetModuleContext(M);
6682
6683 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6684 &retval);
6685
6686 /* Compile IR*/
6687 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6688 &err, &out_buffer);
6689
6690 /* Process Errors/Warnings */
6691 if (mem_err) {
6692 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6693 free(err);
6694 retval = 1;
6695 goto out;
6696 }
6697
6698 /* Extract Shader Code*/
6699 buffer_size = LLVMGetBufferSize(out_buffer);
6700 buffer_data = LLVMGetBufferStart(out_buffer);
6701
6702 ac_elf_read(buffer_data, buffer_size, binary);
6703
6704 /* Clean up */
6705 LLVMDisposeMemoryBuffer(out_buffer);
6706
6707 out:
6708 return retval;
6709 }
6710
6711 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6712 LLVMModuleRef llvm_module,
6713 struct ac_shader_binary *binary,
6714 struct ac_shader_config *config,
6715 struct ac_shader_variant_info *shader_info,
6716 gl_shader_stage stage,
6717 bool dump_shader, bool supports_spill)
6718 {
6719 if (dump_shader)
6720 ac_dump_module(llvm_module);
6721
6722 memset(binary, 0, sizeof(*binary));
6723 int v = ac_llvm_compile(llvm_module, binary, tm);
6724 if (v) {
6725 fprintf(stderr, "compile failed\n");
6726 }
6727
6728 if (dump_shader)
6729 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6730
6731 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6732
6733 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6734 LLVMDisposeModule(llvm_module);
6735 LLVMContextDispose(ctx);
6736
6737 if (stage == MESA_SHADER_FRAGMENT) {
6738 shader_info->num_input_vgprs = 0;
6739 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6740 shader_info->num_input_vgprs += 2;
6741 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6742 shader_info->num_input_vgprs += 2;
6743 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6744 shader_info->num_input_vgprs += 2;
6745 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6746 shader_info->num_input_vgprs += 3;
6747 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6748 shader_info->num_input_vgprs += 2;
6749 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6750 shader_info->num_input_vgprs += 2;
6751 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6752 shader_info->num_input_vgprs += 2;
6753 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6754 shader_info->num_input_vgprs += 1;
6755 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6756 shader_info->num_input_vgprs += 1;
6757 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6758 shader_info->num_input_vgprs += 1;
6759 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6760 shader_info->num_input_vgprs += 1;
6761 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6762 shader_info->num_input_vgprs += 1;
6763 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6764 shader_info->num_input_vgprs += 1;
6765 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6766 shader_info->num_input_vgprs += 1;
6767 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6768 shader_info->num_input_vgprs += 1;
6769 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6770 shader_info->num_input_vgprs += 1;
6771 }
6772 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6773
6774 /* +3 for scratch wave offset and VCC */
6775 config->num_sgprs = MAX2(config->num_sgprs,
6776 shader_info->num_input_sgprs + 3);
6777 }
6778
6779 static void
6780 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6781 {
6782 switch (nir->info.stage) {
6783 case MESA_SHADER_COMPUTE:
6784 for (int i = 0; i < 3; ++i)
6785 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6786 break;
6787 case MESA_SHADER_FRAGMENT:
6788 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6789 break;
6790 case MESA_SHADER_GEOMETRY:
6791 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6792 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6793 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6794 shader_info->gs.invocations = nir->info.gs.invocations;
6795 break;
6796 case MESA_SHADER_TESS_EVAL:
6797 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6798 shader_info->tes.spacing = nir->info.tess.spacing;
6799 shader_info->tes.ccw = nir->info.tess.ccw;
6800 shader_info->tes.point_mode = nir->info.tess.point_mode;
6801 shader_info->tes.as_es = options->key.tes.as_es;
6802 break;
6803 case MESA_SHADER_TESS_CTRL:
6804 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6805 break;
6806 case MESA_SHADER_VERTEX:
6807 shader_info->vs.as_es = options->key.vs.as_es;
6808 shader_info->vs.as_ls = options->key.vs.as_ls;
6809 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6810 if (options->key.vs.as_ls)
6811 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6812 break;
6813 default:
6814 break;
6815 }
6816 }
6817
6818 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6819 struct ac_shader_binary *binary,
6820 struct ac_shader_config *config,
6821 struct ac_shader_variant_info *shader_info,
6822 struct nir_shader *const *nir,
6823 int nir_count,
6824 const struct ac_nir_compiler_options *options,
6825 bool dump_shader)
6826 {
6827
6828 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6829 options);
6830
6831 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6832 for (int i = 0; i < nir_count; ++i)
6833 ac_fill_shader_info(shader_info, nir[i], options);
6834 }
6835
6836 static void
6837 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6838 {
6839 LLVMValueRef args[9];
6840 args[0] = ctx->gsvs_ring;
6841 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6842 args[3] = ctx->ac.i32_0;
6843 args[4] = ctx->ac.i32_1; /* OFFEN */
6844 args[5] = ctx->ac.i32_0; /* IDXEN */
6845 args[6] = ctx->ac.i32_1; /* GLC */
6846 args[7] = ctx->ac.i32_1; /* SLC */
6847 args[8] = ctx->ac.i32_0; /* TFE */
6848
6849 int idx = 0;
6850
6851 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6852 int length = 4;
6853 int slot = idx;
6854 int slot_inc = 1;
6855 if (!(ctx->output_mask & (1ull << i)))
6856 continue;
6857
6858 if (i == VARYING_SLOT_CLIP_DIST0) {
6859 /* unpack clip and cull from a single set of slots */
6860 length = ctx->num_output_clips + ctx->num_output_culls;
6861 if (length > 4)
6862 slot_inc = 2;
6863 }
6864
6865 for (unsigned j = 0; j < length; j++) {
6866 LLVMValueRef value;
6867 args[2] = LLVMConstInt(ctx->ac.i32,
6868 (slot * 4 + j) *
6869 ctx->gs_max_out_vertices * 16 * 4, false);
6870
6871 value = ac_build_intrinsic(&ctx->ac,
6872 "llvm.SI.buffer.load.dword.i32.i32",
6873 ctx->ac.i32, args, 9,
6874 AC_FUNC_ATTR_READONLY |
6875 AC_FUNC_ATTR_LEGACY);
6876
6877 LLVMBuildStore(ctx->builder,
6878 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6879 }
6880 idx += slot_inc;
6881 }
6882 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6883 }
6884
6885 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6886 struct nir_shader *geom_shader,
6887 struct ac_shader_binary *binary,
6888 struct ac_shader_config *config,
6889 struct ac_shader_variant_info *shader_info,
6890 const struct ac_nir_compiler_options *options,
6891 bool dump_shader)
6892 {
6893 struct nir_to_llvm_context ctx = {0};
6894 ctx.context = LLVMContextCreate();
6895 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6896 ctx.options = options;
6897 ctx.shader_info = shader_info;
6898
6899 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6900 ctx.ac.module = ctx.module;
6901
6902 ctx.is_gs_copy_shader = true;
6903 LLVMSetTarget(ctx.module, "amdgcn--");
6904
6905 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6906 ctx.ac.builder = ctx.builder;
6907 ctx.stage = MESA_SHADER_VERTEX;
6908
6909 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
6910
6911 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6912 ac_setup_rings(&ctx);
6913
6914 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6915 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6916
6917 struct ac_nir_context nir_ctx = {};
6918 nir_ctx.ac = ctx.ac;
6919 nir_ctx.abi = &ctx.abi;
6920
6921 nir_ctx.nctx = &ctx;
6922 ctx.nir = &nir_ctx;
6923
6924 nir_foreach_variable(variable, &geom_shader->outputs) {
6925 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
6926 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6927 }
6928
6929 ac_gs_copy_shader_emit(&ctx);
6930
6931 ctx.nir = NULL;
6932
6933 LLVMBuildRetVoid(ctx.builder);
6934
6935 ac_llvm_finalize_module(&ctx);
6936
6937 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6938 MESA_SHADER_VERTEX,
6939 dump_shader, options->supports_spill);
6940 }