2 * Copyright © 2016 Bas Nieuwenhuizen
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
38 enum radeon_llvm_calling_convention
{
39 RADEON_LLVM_AMDGPU_VS
= 87,
40 RADEON_LLVM_AMDGPU_GS
= 88,
41 RADEON_LLVM_AMDGPU_PS
= 89,
42 RADEON_LLVM_AMDGPU_CS
= 90,
43 RADEON_LLVM_AMDGPU_HS
= 93,
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
49 struct nir_to_llvm_context
;
51 struct ac_nir_context
{
52 struct ac_llvm_context ac
;
53 struct ac_shader_abi
*abi
;
55 gl_shader_stage stage
;
57 struct hash_table
*defs
;
58 struct hash_table
*phis
;
59 struct hash_table
*vars
;
61 LLVMValueRef main_function
;
62 LLVMBasicBlockRef continue_block
;
63 LLVMBasicBlockRef break_block
;
65 LLVMValueRef outputs
[RADEON_LLVM_MAX_OUTPUTS
* 4];
70 struct nir_to_llvm_context
*nctx
; /* TODO get rid of this */
73 struct nir_to_llvm_context
{
74 struct ac_llvm_context ac
;
75 const struct ac_nir_compiler_options
*options
;
76 struct ac_shader_variant_info
*shader_info
;
77 struct ac_shader_abi abi
;
78 struct ac_nir_context
*nir
;
80 unsigned max_workgroup_size
;
81 LLVMContextRef context
;
83 LLVMBuilderRef builder
;
84 LLVMValueRef main_function
;
86 struct hash_table
*defs
;
87 struct hash_table
*phis
;
89 LLVMValueRef descriptor_sets
[AC_UD_MAX_SETS
];
90 LLVMValueRef ring_offsets
;
91 LLVMValueRef push_constants
;
92 LLVMValueRef view_index
;
95 LLVMValueRef vertex_buffers
;
96 LLVMValueRef rel_auto_id
;
97 LLVMValueRef vs_prim_id
;
98 LLVMValueRef ls_out_layout
;
99 LLVMValueRef es2gs_offset
;
101 LLVMValueRef tcs_offchip_layout
;
102 LLVMValueRef tcs_out_offsets
;
103 LLVMValueRef tcs_out_layout
;
104 LLVMValueRef tcs_in_layout
;
106 LLVMValueRef merged_wave_info
;
107 LLVMValueRef tess_factor_offset
;
108 LLVMValueRef tes_rel_patch_id
;
112 LLVMValueRef gsvs_ring_stride
;
113 LLVMValueRef gsvs_num_entries
;
114 LLVMValueRef gs2vs_offset
;
115 LLVMValueRef gs_wave_id
;
116 LLVMValueRef gs_vtx_offset
[6];
118 LLVMValueRef esgs_ring
;
119 LLVMValueRef gsvs_ring
;
120 LLVMValueRef hs_ring_tess_offchip
;
121 LLVMValueRef hs_ring_tess_factor
;
123 LLVMValueRef sample_pos_offset
;
124 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
125 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
127 gl_shader_stage stage
;
129 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
132 uint64_t output_mask
;
133 uint8_t num_output_clips
;
134 uint8_t num_output_culls
;
136 bool is_gs_copy_shader
;
137 LLVMValueRef gs_next_vertex
;
138 unsigned gs_max_out_vertices
;
140 unsigned tes_primitive_mode
;
141 uint64_t tess_outputs_written
;
142 uint64_t tess_patch_outputs_written
;
144 uint32_t tcs_patch_outputs_read
;
145 uint64_t tcs_outputs_read
;
148 static inline struct nir_to_llvm_context
*
149 nir_to_llvm_context_from_abi(struct ac_shader_abi
*abi
)
151 struct nir_to_llvm_context
*ctx
= NULL
;
152 return container_of(abi
, ctx
, abi
);
155 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
156 const nir_deref_var
*deref
,
157 enum ac_descriptor_type desc_type
,
158 const nir_tex_instr
*instr
,
159 bool image
, bool write
);
161 static unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
)
163 return (index
* 4) + chan
;
166 static unsigned shader_io_get_unique_index(gl_varying_slot slot
)
168 /* handle patch indices separate */
169 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
171 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
173 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
174 return 2 + (slot
- VARYING_SLOT_PATCH0
);
176 if (slot
== VARYING_SLOT_POS
)
178 if (slot
== VARYING_SLOT_PSIZ
)
180 if (slot
== VARYING_SLOT_CLIP_DIST0
)
182 /* 3 is reserved for clip dist as well */
183 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
184 return 4 + (slot
- VARYING_SLOT_VAR0
);
185 unreachable("illegal slot in get unique index\n");
188 static void set_llvm_calling_convention(LLVMValueRef func
,
189 gl_shader_stage stage
)
191 enum radeon_llvm_calling_convention calling_conv
;
194 case MESA_SHADER_VERTEX
:
195 case MESA_SHADER_TESS_EVAL
:
196 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
198 case MESA_SHADER_GEOMETRY
:
199 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
201 case MESA_SHADER_TESS_CTRL
:
202 calling_conv
= HAVE_LLVM
>= 0x0500 ? RADEON_LLVM_AMDGPU_HS
: RADEON_LLVM_AMDGPU_VS
;
204 case MESA_SHADER_FRAGMENT
:
205 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
207 case MESA_SHADER_COMPUTE
:
208 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
211 unreachable("Unhandle shader type");
214 LLVMSetFunctionCallConv(func
, calling_conv
);
219 LLVMTypeRef types
[MAX_ARGS
];
220 LLVMValueRef
*assign
[MAX_ARGS
];
221 unsigned array_params_mask
;
224 uint8_t num_sgprs_used
;
225 uint8_t num_vgprs_used
;
228 enum ac_arg_regfile
{
234 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
235 LLVMValueRef
*param_ptr
)
237 assert(info
->count
< MAX_ARGS
);
239 info
->assign
[info
->count
] = param_ptr
;
240 info
->types
[info
->count
] = type
;
243 if (regfile
== ARG_SGPR
) {
244 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
247 assert(regfile
== ARG_VGPR
);
248 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
253 add_array_arg(struct arg_info
*info
, LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
255 info
->array_params_mask
|= (1 << info
->count
);
256 add_arg(info
, ARG_SGPR
, type
, param_ptr
);
259 static void assign_arguments(LLVMValueRef main_function
,
260 struct arg_info
*info
)
263 for (i
= 0; i
< info
->count
; i
++) {
265 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
270 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
271 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
272 unsigned num_return_elems
,
273 struct arg_info
*args
,
274 unsigned max_workgroup_size
,
277 LLVMTypeRef main_function_type
, ret_type
;
278 LLVMBasicBlockRef main_function_body
;
280 if (num_return_elems
)
281 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
282 num_return_elems
, true);
284 ret_type
= LLVMVoidTypeInContext(ctx
);
286 /* Setup the function */
288 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
289 LLVMValueRef main_function
=
290 LLVMAddFunction(module
, "main", main_function_type
);
292 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
293 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
295 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
296 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
297 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
299 if (args
->array_params_mask
& (1 << i
)) {
300 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
301 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
302 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
306 if (max_workgroup_size
) {
307 ac_llvm_add_target_dep_function_attr(main_function
,
308 "amdgpu-max-work-group-size",
312 /* These were copied from some LLVM test. */
313 LLVMAddTargetDependentFunctionAttr(main_function
,
314 "less-precise-fpmad",
316 LLVMAddTargetDependentFunctionAttr(main_function
,
319 LLVMAddTargetDependentFunctionAttr(main_function
,
322 LLVMAddTargetDependentFunctionAttr(main_function
,
325 LLVMAddTargetDependentFunctionAttr(main_function
,
326 "no-signed-zeros-fp-math",
329 return main_function
;
332 static int get_elem_bits(struct ac_llvm_context
*ctx
, LLVMTypeRef type
)
334 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
335 type
= LLVMGetElementType(type
);
337 if (LLVMGetTypeKind(type
) == LLVMIntegerTypeKind
)
338 return LLVMGetIntTypeWidth(type
);
340 if (type
== ctx
->f16
)
342 if (type
== ctx
->f32
)
344 if (type
== ctx
->f64
)
347 unreachable("Unhandled type kind in get_elem_bits");
350 static LLVMValueRef
unpack_param(struct ac_llvm_context
*ctx
,
351 LLVMValueRef param
, unsigned rshift
,
354 LLVMValueRef value
= param
;
356 value
= LLVMBuildLShr(ctx
->builder
, value
,
357 LLVMConstInt(ctx
->i32
, rshift
, false), "");
359 if (rshift
+ bitwidth
< 32) {
360 unsigned mask
= (1 << bitwidth
) - 1;
361 value
= LLVMBuildAnd(ctx
->builder
, value
,
362 LLVMConstInt(ctx
->i32
, mask
, false), "");
367 static LLVMValueRef
get_rel_patch_id(struct nir_to_llvm_context
*ctx
)
369 switch (ctx
->stage
) {
370 case MESA_SHADER_TESS_CTRL
:
371 return unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
372 case MESA_SHADER_TESS_EVAL
:
373 return ctx
->tes_rel_patch_id
;
376 unreachable("Illegal stage");
380 /* Tessellation shaders pass outputs to the next shader using LDS.
382 * LS outputs = TCS inputs
383 * TCS outputs = TES inputs
386 * - TCS inputs for patch 0
387 * - TCS inputs for patch 1
388 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
390 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
391 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
392 * - TCS outputs for patch 1
393 * - Per-patch TCS outputs for patch 1
394 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
395 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
398 * All three shaders VS(LS), TCS, TES share the same LDS space.
401 get_tcs_in_patch_stride(struct nir_to_llvm_context
*ctx
)
403 if (ctx
->stage
== MESA_SHADER_VERTEX
)
404 return unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 0, 13);
405 else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
406 return unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 0, 13);
414 get_tcs_out_patch_stride(struct nir_to_llvm_context
*ctx
)
416 return unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 0, 13);
420 get_tcs_out_patch0_offset(struct nir_to_llvm_context
*ctx
)
422 return LLVMBuildMul(ctx
->builder
,
423 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 0, 16),
424 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
428 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context
*ctx
)
430 return LLVMBuildMul(ctx
->builder
,
431 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 16, 16),
432 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
436 get_tcs_in_current_patch_offset(struct nir_to_llvm_context
*ctx
)
438 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
439 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
441 return LLVMBuildMul(ctx
->builder
, patch_stride
, rel_patch_id
, "");
445 get_tcs_out_current_patch_offset(struct nir_to_llvm_context
*ctx
)
447 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
448 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
449 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
451 return LLVMBuildAdd(ctx
->builder
, patch0_offset
,
452 LLVMBuildMul(ctx
->builder
, patch_stride
,
458 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context
*ctx
)
460 LLVMValueRef patch0_patch_data_offset
=
461 get_tcs_out_patch0_patch_data_offset(ctx
);
462 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
463 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
465 return LLVMBuildAdd(ctx
->builder
, patch0_patch_data_offset
,
466 LLVMBuildMul(ctx
->builder
, patch_stride
,
472 set_loc(struct ac_userdata_info
*ud_info
, uint8_t *sgpr_idx
, uint8_t num_sgprs
,
473 uint32_t indirect_offset
)
475 ud_info
->sgpr_idx
= *sgpr_idx
;
476 ud_info
->num_sgprs
= num_sgprs
;
477 ud_info
->indirect
= indirect_offset
> 0;
478 ud_info
->indirect_offset
= indirect_offset
;
479 *sgpr_idx
+= num_sgprs
;
483 set_loc_shader(struct nir_to_llvm_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
486 struct ac_userdata_info
*ud_info
=
487 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
490 set_loc(ud_info
, sgpr_idx
, num_sgprs
, 0);
494 set_loc_desc(struct nir_to_llvm_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
495 uint32_t indirect_offset
)
497 struct ac_userdata_info
*ud_info
=
498 &ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[idx
];
501 set_loc(ud_info
, sgpr_idx
, 2, indirect_offset
);
504 struct user_sgpr_info
{
505 bool need_ring_offsets
;
507 bool indirect_all_descriptor_sets
;
510 static bool needs_view_index_sgpr(struct nir_to_llvm_context
*ctx
,
511 gl_shader_stage stage
)
514 case MESA_SHADER_VERTEX
:
515 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
516 (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
519 case MESA_SHADER_TESS_EVAL
:
520 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
523 case MESA_SHADER_GEOMETRY
:
524 case MESA_SHADER_TESS_CTRL
:
525 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
534 static void allocate_user_sgprs(struct nir_to_llvm_context
*ctx
,
535 gl_shader_stage stage
,
536 bool needs_view_index
,
537 struct user_sgpr_info
*user_sgpr_info
)
539 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
541 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
542 if (stage
== MESA_SHADER_GEOMETRY
||
543 stage
== MESA_SHADER_VERTEX
||
544 stage
== MESA_SHADER_TESS_CTRL
||
545 stage
== MESA_SHADER_TESS_EVAL
||
546 ctx
->is_gs_copy_shader
)
547 user_sgpr_info
->need_ring_offsets
= true;
549 if (stage
== MESA_SHADER_FRAGMENT
&&
550 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
551 user_sgpr_info
->need_ring_offsets
= true;
553 /* 2 user sgprs will nearly always be allocated for scratch/rings */
554 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
555 user_sgpr_info
->sgpr_count
+= 2;
558 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
560 case MESA_SHADER_COMPUTE
:
561 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
562 user_sgpr_info
->sgpr_count
+= 3;
564 case MESA_SHADER_FRAGMENT
:
565 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
567 case MESA_SHADER_VERTEX
:
568 if (!ctx
->is_gs_copy_shader
) {
569 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.vs
.has_vertex_buffers
? 2 : 0;
570 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
571 user_sgpr_info
->sgpr_count
+= 3;
573 user_sgpr_info
->sgpr_count
+= 2;
576 if (ctx
->options
->key
.vs
.as_ls
)
577 user_sgpr_info
->sgpr_count
++;
579 case MESA_SHADER_TESS_CTRL
:
580 user_sgpr_info
->sgpr_count
+= 4;
582 case MESA_SHADER_TESS_EVAL
:
583 user_sgpr_info
->sgpr_count
+= 1;
585 case MESA_SHADER_GEOMETRY
:
586 user_sgpr_info
->sgpr_count
+= 2;
592 if (needs_view_index
)
593 user_sgpr_info
->sgpr_count
++;
595 if (ctx
->shader_info
->info
.loads_push_constants
)
596 user_sgpr_info
->sgpr_count
+= 2;
598 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
? 32 : 16;
599 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_info
->sgpr_count
;
601 if (remaining_sgprs
/ 2 < util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
)) {
602 user_sgpr_info
->sgpr_count
+= 2;
603 user_sgpr_info
->indirect_all_descriptor_sets
= true;
605 user_sgpr_info
->sgpr_count
+= util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
) * 2;
610 declare_global_input_sgprs(struct nir_to_llvm_context
*ctx
,
611 gl_shader_stage stage
,
612 bool has_previous_stage
,
613 gl_shader_stage previous_stage
,
614 const struct user_sgpr_info
*user_sgpr_info
,
615 struct arg_info
*args
,
616 LLVMValueRef
*desc_sets
)
618 LLVMTypeRef type
= ac_array_in_const_addr_space(ctx
->ac
.i8
);
619 unsigned num_sets
= ctx
->options
->layout
?
620 ctx
->options
->layout
->num_sets
: 0;
621 unsigned stage_mask
= 1 << stage
;
623 if (has_previous_stage
)
624 stage_mask
|= 1 << previous_stage
;
626 /* 1 for each descriptor set */
627 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
628 for (unsigned i
= 0; i
< num_sets
; ++i
) {
629 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
630 add_array_arg(args
, type
,
631 &ctx
->descriptor_sets
[i
]);
635 add_array_arg(args
, ac_array_in_const_addr_space(type
), desc_sets
);
638 if (ctx
->shader_info
->info
.loads_push_constants
) {
639 /* 1 for push constants and dynamic descriptors */
640 add_array_arg(args
, type
, &ctx
->push_constants
);
645 declare_vs_specific_input_sgprs(struct nir_to_llvm_context
*ctx
,
646 gl_shader_stage stage
,
647 bool has_previous_stage
,
648 gl_shader_stage previous_stage
,
649 struct arg_info
*args
)
651 if (!ctx
->is_gs_copy_shader
&&
652 (stage
== MESA_SHADER_VERTEX
||
653 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
654 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
655 add_arg(args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
656 &ctx
->vertex_buffers
);
658 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
659 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
660 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
661 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
667 declare_vs_input_vgprs(struct nir_to_llvm_context
*ctx
, struct arg_info
*args
)
669 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
670 if (!ctx
->is_gs_copy_shader
) {
671 if (ctx
->options
->key
.vs
.as_ls
) {
672 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
673 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
675 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
676 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
678 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
683 declare_tes_input_vgprs(struct nir_to_llvm_context
*ctx
, struct arg_info
*args
)
685 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
686 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
687 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
688 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
692 set_global_input_locs(struct nir_to_llvm_context
*ctx
, gl_shader_stage stage
,
693 bool has_previous_stage
, gl_shader_stage previous_stage
,
694 const struct user_sgpr_info
*user_sgpr_info
,
695 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
697 unsigned num_sets
= ctx
->options
->layout
?
698 ctx
->options
->layout
->num_sets
: 0;
699 unsigned stage_mask
= 1 << stage
;
701 if (has_previous_stage
)
702 stage_mask
|= 1 << previous_stage
;
704 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
705 for (unsigned i
= 0; i
< num_sets
; ++i
) {
706 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
707 set_loc_desc(ctx
, i
, user_sgpr_idx
, 0);
709 ctx
->descriptor_sets
[i
] = NULL
;
712 set_loc_shader(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
715 for (unsigned i
= 0; i
< num_sets
; ++i
) {
716 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
717 set_loc_desc(ctx
, i
, user_sgpr_idx
, i
* 8);
718 ctx
->descriptor_sets
[i
] =
719 ac_build_load_to_sgpr(&ctx
->ac
,
721 LLVMConstInt(ctx
->ac
.i32
, i
, false));
724 ctx
->descriptor_sets
[i
] = NULL
;
726 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
729 if (ctx
->shader_info
->info
.loads_push_constants
) {
730 set_loc_shader(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
, 2);
735 set_vs_specific_input_locs(struct nir_to_llvm_context
*ctx
,
736 gl_shader_stage stage
, bool has_previous_stage
,
737 gl_shader_stage previous_stage
,
738 uint8_t *user_sgpr_idx
)
740 if (!ctx
->is_gs_copy_shader
&&
741 (stage
== MESA_SHADER_VERTEX
||
742 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
743 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
744 set_loc_shader(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
749 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
752 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
753 user_sgpr_idx
, vs_num
);
757 static void create_function(struct nir_to_llvm_context
*ctx
,
758 gl_shader_stage stage
,
759 bool has_previous_stage
,
760 gl_shader_stage previous_stage
)
762 uint8_t user_sgpr_idx
;
763 struct user_sgpr_info user_sgpr_info
;
764 struct arg_info args
= {};
765 LLVMValueRef desc_sets
;
766 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
767 allocate_user_sgprs(ctx
, stage
, needs_view_index
, &user_sgpr_info
);
769 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
770 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
775 case MESA_SHADER_COMPUTE
:
776 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
777 previous_stage
, &user_sgpr_info
,
780 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
781 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
782 &ctx
->abi
.num_work_groups
);
785 for (int i
= 0; i
< 3; i
++) {
786 ctx
->abi
.workgroup_ids
[i
] = NULL
;
787 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
788 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
789 &ctx
->abi
.workgroup_ids
[i
]);
793 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
794 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->tg_size
);
795 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
796 &ctx
->abi
.local_invocation_ids
);
798 case MESA_SHADER_VERTEX
:
799 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
800 previous_stage
, &user_sgpr_info
,
802 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
803 previous_stage
, &args
);
805 if (needs_view_index
)
806 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->view_index
);
807 if (ctx
->options
->key
.vs
.as_es
)
808 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
810 else if (ctx
->options
->key
.vs
.as_ls
)
811 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
812 &ctx
->ls_out_layout
);
814 declare_vs_input_vgprs(ctx
, &args
);
816 case MESA_SHADER_TESS_CTRL
:
817 if (has_previous_stage
) {
818 // First 6 system regs
819 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
820 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
821 &ctx
->merged_wave_info
);
822 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
823 &ctx
->tess_factor_offset
);
825 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
826 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
827 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
829 declare_global_input_sgprs(ctx
, stage
,
832 &user_sgpr_info
, &args
,
834 declare_vs_specific_input_sgprs(ctx
, stage
,
836 previous_stage
, &args
);
838 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
839 &ctx
->ls_out_layout
);
841 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
842 &ctx
->tcs_offchip_layout
);
843 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
844 &ctx
->tcs_out_offsets
);
845 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
846 &ctx
->tcs_out_layout
);
847 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
848 &ctx
->tcs_in_layout
);
849 if (needs_view_index
)
850 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
853 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
854 &ctx
->abi
.tcs_patch_id
);
855 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
856 &ctx
->abi
.tcs_rel_ids
);
858 declare_vs_input_vgprs(ctx
, &args
);
860 declare_global_input_sgprs(ctx
, stage
,
863 &user_sgpr_info
, &args
,
866 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
867 &ctx
->tcs_offchip_layout
);
868 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
869 &ctx
->tcs_out_offsets
);
870 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
871 &ctx
->tcs_out_layout
);
872 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
873 &ctx
->tcs_in_layout
);
874 if (needs_view_index
)
875 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
878 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
879 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
880 &ctx
->tess_factor_offset
);
881 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
882 &ctx
->abi
.tcs_patch_id
);
883 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
884 &ctx
->abi
.tcs_rel_ids
);
887 case MESA_SHADER_TESS_EVAL
:
888 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
889 previous_stage
, &user_sgpr_info
,
892 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->tcs_offchip_layout
);
893 if (needs_view_index
)
894 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->view_index
);
896 if (ctx
->options
->key
.tes
.as_es
) {
897 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
898 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
899 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
902 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
903 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
905 declare_tes_input_vgprs(ctx
, &args
);
907 case MESA_SHADER_GEOMETRY
:
908 if (has_previous_stage
) {
909 // First 6 system regs
910 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
912 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
913 &ctx
->merged_wave_info
);
914 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
916 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
917 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
918 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
920 declare_global_input_sgprs(ctx
, stage
,
923 &user_sgpr_info
, &args
,
926 if (previous_stage
== MESA_SHADER_TESS_EVAL
) {
927 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
928 &ctx
->tcs_offchip_layout
);
930 declare_vs_specific_input_sgprs(ctx
, stage
,
936 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
937 &ctx
->gsvs_ring_stride
);
938 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
939 &ctx
->gsvs_num_entries
);
940 if (needs_view_index
)
941 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
944 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
945 &ctx
->gs_vtx_offset
[0]);
946 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
947 &ctx
->gs_vtx_offset
[2]);
948 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
949 &ctx
->abi
.gs_prim_id
);
950 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
951 &ctx
->abi
.gs_invocation_id
);
952 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
953 &ctx
->gs_vtx_offset
[4]);
955 if (previous_stage
== MESA_SHADER_VERTEX
) {
956 declare_vs_input_vgprs(ctx
, &args
);
958 declare_tes_input_vgprs(ctx
, &args
);
961 declare_global_input_sgprs(ctx
, stage
,
964 &user_sgpr_info
, &args
,
967 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
968 &ctx
->gsvs_ring_stride
);
969 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
970 &ctx
->gsvs_num_entries
);
971 if (needs_view_index
)
972 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
975 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
976 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
977 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
978 &ctx
->gs_vtx_offset
[0]);
979 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
980 &ctx
->gs_vtx_offset
[1]);
981 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
982 &ctx
->abi
.gs_prim_id
);
983 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
984 &ctx
->gs_vtx_offset
[2]);
985 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
986 &ctx
->gs_vtx_offset
[3]);
987 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
988 &ctx
->gs_vtx_offset
[4]);
989 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
990 &ctx
->gs_vtx_offset
[5]);
991 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
992 &ctx
->abi
.gs_invocation_id
);
995 case MESA_SHADER_FRAGMENT
:
996 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
997 previous_stage
, &user_sgpr_info
,
1000 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
)
1001 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1002 &ctx
->sample_pos_offset
);
1004 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
1005 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
1006 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
1007 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
1008 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1009 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
1010 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
1011 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
1012 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1013 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1014 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1015 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1016 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1017 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1018 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1019 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1020 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1023 unreachable("Shader stage not implemented");
1026 ctx
->main_function
= create_llvm_function(
1027 ctx
->context
, ctx
->module
, ctx
->builder
, NULL
, 0, &args
,
1028 ctx
->max_workgroup_size
,
1029 ctx
->options
->unsafe_math
);
1030 set_llvm_calling_convention(ctx
->main_function
, stage
);
1033 ctx
->shader_info
->num_input_vgprs
= 0;
1034 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1036 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1038 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1039 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1041 assign_arguments(ctx
->main_function
, &args
);
1045 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1046 set_loc_shader(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1048 if (ctx
->options
->supports_spill
) {
1049 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1050 LLVMPointerType(ctx
->ac
.i8
, AC_CONST_ADDR_SPACE
),
1051 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1052 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->builder
, ctx
->ring_offsets
,
1053 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1057 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1058 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1059 if (has_previous_stage
)
1062 set_global_input_locs(ctx
, stage
, has_previous_stage
, previous_stage
,
1063 &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1066 case MESA_SHADER_COMPUTE
:
1067 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1068 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1072 case MESA_SHADER_VERTEX
:
1073 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1074 previous_stage
, &user_sgpr_idx
);
1075 if (ctx
->view_index
)
1076 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1077 if (ctx
->options
->key
.vs
.as_ls
) {
1078 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1081 if (ctx
->options
->key
.vs
.as_ls
)
1082 ac_declare_lds_as_pointer(&ctx
->ac
);
1084 case MESA_SHADER_TESS_CTRL
:
1085 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1086 previous_stage
, &user_sgpr_idx
);
1087 if (has_previous_stage
)
1088 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1090 set_loc_shader(ctx
, AC_UD_TCS_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 4);
1091 if (ctx
->view_index
)
1092 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1093 ac_declare_lds_as_pointer(&ctx
->ac
);
1095 case MESA_SHADER_TESS_EVAL
:
1096 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 1);
1097 if (ctx
->view_index
)
1098 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1100 case MESA_SHADER_GEOMETRY
:
1101 if (has_previous_stage
) {
1102 if (previous_stage
== MESA_SHADER_VERTEX
)
1103 set_vs_specific_input_locs(ctx
, stage
,
1108 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
,
1111 set_loc_shader(ctx
, AC_UD_GS_VS_RING_STRIDE_ENTRIES
,
1113 if (ctx
->view_index
)
1114 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1115 if (has_previous_stage
)
1116 ac_declare_lds_as_pointer(&ctx
->ac
);
1118 case MESA_SHADER_FRAGMENT
:
1119 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
) {
1120 set_loc_shader(ctx
, AC_UD_PS_SAMPLE_POS_OFFSET
,
1125 unreachable("Shader stage not implemented");
1128 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1131 static LLVMValueRef
trim_vector(struct ac_llvm_context
*ctx
,
1132 LLVMValueRef value
, unsigned count
)
1134 unsigned num_components
= ac_get_llvm_num_components(value
);
1135 if (count
== num_components
)
1138 LLVMValueRef masks
[] = {
1139 LLVMConstInt(ctx
->i32
, 0, false), LLVMConstInt(ctx
->i32
, 1, false),
1140 LLVMConstInt(ctx
->i32
, 2, false), LLVMConstInt(ctx
->i32
, 3, false)};
1143 return LLVMBuildExtractElement(ctx
->builder
, value
, masks
[0],
1146 LLVMValueRef swizzle
= LLVMConstVector(masks
, count
);
1147 return LLVMBuildShuffleVector(ctx
->builder
, value
, value
, swizzle
, "");
1151 build_store_values_extended(struct ac_llvm_context
*ac
,
1152 LLVMValueRef
*values
,
1153 unsigned value_count
,
1154 unsigned value_stride
,
1157 LLVMBuilderRef builder
= ac
->builder
;
1160 for (i
= 0; i
< value_count
; i
++) {
1161 LLVMValueRef ptr
= values
[i
* value_stride
];
1162 LLVMValueRef index
= LLVMConstInt(ac
->i32
, i
, false);
1163 LLVMValueRef value
= LLVMBuildExtractElement(builder
, vec
, index
, "");
1164 LLVMBuildStore(builder
, value
, ptr
);
1168 static LLVMTypeRef
get_def_type(struct ac_nir_context
*ctx
,
1169 const nir_ssa_def
*def
)
1171 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, def
->bit_size
);
1172 if (def
->num_components
> 1) {
1173 type
= LLVMVectorType(type
, def
->num_components
);
1178 static LLVMValueRef
get_src(struct ac_nir_context
*nir
, nir_src src
)
1181 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, src
.ssa
);
1182 return (LLVMValueRef
)entry
->data
;
1186 static LLVMBasicBlockRef
get_block(struct ac_nir_context
*nir
,
1187 const struct nir_block
*b
)
1189 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, b
);
1190 return (LLVMBasicBlockRef
)entry
->data
;
1193 static LLVMValueRef
get_alu_src(struct ac_nir_context
*ctx
,
1195 unsigned num_components
)
1197 LLVMValueRef value
= get_src(ctx
, src
.src
);
1198 bool need_swizzle
= false;
1201 LLVMTypeRef type
= LLVMTypeOf(value
);
1202 unsigned src_components
= LLVMGetTypeKind(type
) == LLVMVectorTypeKind
1203 ? LLVMGetVectorSize(type
)
1206 for (unsigned i
= 0; i
< num_components
; ++i
) {
1207 assert(src
.swizzle
[i
] < src_components
);
1208 if (src
.swizzle
[i
] != i
)
1209 need_swizzle
= true;
1212 if (need_swizzle
|| num_components
!= src_components
) {
1213 LLVMValueRef masks
[] = {
1214 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[0], false),
1215 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[1], false),
1216 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[2], false),
1217 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[3], false)};
1219 if (src_components
> 1 && num_components
== 1) {
1220 value
= LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
1222 } else if (src_components
== 1 && num_components
> 1) {
1223 LLVMValueRef values
[] = {value
, value
, value
, value
};
1224 value
= ac_build_gather_values(&ctx
->ac
, values
, num_components
);
1226 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
1227 value
= LLVMBuildShuffleVector(ctx
->ac
.builder
, value
, value
,
1231 assert(!src
.negate
);
1236 static LLVMValueRef
emit_int_cmp(struct ac_llvm_context
*ctx
,
1237 LLVMIntPredicate pred
, LLVMValueRef src0
,
1240 LLVMValueRef result
= LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, "");
1241 return LLVMBuildSelect(ctx
->builder
, result
,
1242 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1246 static LLVMValueRef
emit_float_cmp(struct ac_llvm_context
*ctx
,
1247 LLVMRealPredicate pred
, LLVMValueRef src0
,
1250 LLVMValueRef result
;
1251 src0
= ac_to_float(ctx
, src0
);
1252 src1
= ac_to_float(ctx
, src1
);
1253 result
= LLVMBuildFCmp(ctx
->builder
, pred
, src0
, src1
, "");
1254 return LLVMBuildSelect(ctx
->builder
, result
,
1255 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1259 static LLVMValueRef
emit_intrin_1f_param(struct ac_llvm_context
*ctx
,
1261 LLVMTypeRef result_type
,
1265 LLVMValueRef params
[] = {
1266 ac_to_float(ctx
, src0
),
1269 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1270 get_elem_bits(ctx
, result_type
));
1271 assert(length
< sizeof(name
));
1272 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 1, AC_FUNC_ATTR_READNONE
);
1275 static LLVMValueRef
emit_intrin_2f_param(struct ac_llvm_context
*ctx
,
1277 LLVMTypeRef result_type
,
1278 LLVMValueRef src0
, LLVMValueRef src1
)
1281 LLVMValueRef params
[] = {
1282 ac_to_float(ctx
, src0
),
1283 ac_to_float(ctx
, src1
),
1286 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1287 get_elem_bits(ctx
, result_type
));
1288 assert(length
< sizeof(name
));
1289 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 2, AC_FUNC_ATTR_READNONE
);
1292 static LLVMValueRef
emit_intrin_3f_param(struct ac_llvm_context
*ctx
,
1294 LLVMTypeRef result_type
,
1295 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1298 LLVMValueRef params
[] = {
1299 ac_to_float(ctx
, src0
),
1300 ac_to_float(ctx
, src1
),
1301 ac_to_float(ctx
, src2
),
1304 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1305 get_elem_bits(ctx
, result_type
));
1306 assert(length
< sizeof(name
));
1307 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 3, AC_FUNC_ATTR_READNONE
);
1310 static LLVMValueRef
emit_bcsel(struct ac_llvm_context
*ctx
,
1311 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1313 LLVMValueRef v
= LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
,
1315 return LLVMBuildSelect(ctx
->builder
, v
, src1
, src2
, "");
1318 static LLVMValueRef
emit_minmax_int(struct ac_llvm_context
*ctx
,
1319 LLVMIntPredicate pred
,
1320 LLVMValueRef src0
, LLVMValueRef src1
)
1322 return LLVMBuildSelect(ctx
->builder
,
1323 LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, ""),
1328 static LLVMValueRef
emit_iabs(struct ac_llvm_context
*ctx
,
1331 return emit_minmax_int(ctx
, LLVMIntSGT
, src0
,
1332 LLVMBuildNeg(ctx
->builder
, src0
, ""));
1335 static LLVMValueRef
emit_fsign(struct ac_llvm_context
*ctx
,
1339 LLVMValueRef cmp
, val
, zero
, one
;
1342 if (bitsize
== 32) {
1352 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGT
, src0
, zero
, "");
1353 val
= LLVMBuildSelect(ctx
->builder
, cmp
, one
, src0
, "");
1354 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
, val
, zero
, "");
1355 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstReal(type
, -1.0), "");
1359 static LLVMValueRef
emit_isign(struct ac_llvm_context
*ctx
,
1360 LLVMValueRef src0
, unsigned bitsize
)
1362 LLVMValueRef cmp
, val
, zero
, one
;
1365 if (bitsize
== 32) {
1375 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGT
, src0
, zero
, "");
1376 val
= LLVMBuildSelect(ctx
->builder
, cmp
, one
, src0
, "");
1377 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGE
, val
, zero
, "");
1378 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstInt(type
, -1, true), "");
1382 static LLVMValueRef
emit_ffract(struct ac_llvm_context
*ctx
,
1383 LLVMValueRef src0
, unsigned bitsize
)
1388 if (bitsize
== 32) {
1389 intr
= "llvm.floor.f32";
1392 intr
= "llvm.floor.f64";
1396 LLVMValueRef fsrc0
= ac_to_float(ctx
, src0
);
1397 LLVMValueRef params
[] = {
1400 LLVMValueRef floor
= ac_build_intrinsic(ctx
, intr
, type
, params
, 1,
1401 AC_FUNC_ATTR_READNONE
);
1402 return LLVMBuildFSub(ctx
->builder
, fsrc0
, floor
, "");
1405 static LLVMValueRef
emit_uint_carry(struct ac_llvm_context
*ctx
,
1407 LLVMValueRef src0
, LLVMValueRef src1
)
1409 LLVMTypeRef ret_type
;
1410 LLVMTypeRef types
[] = { ctx
->i32
, ctx
->i1
};
1412 LLVMValueRef params
[] = { src0
, src1
};
1413 ret_type
= LLVMStructTypeInContext(ctx
->context
, types
,
1416 res
= ac_build_intrinsic(ctx
, intrin
, ret_type
,
1417 params
, 2, AC_FUNC_ATTR_READNONE
);
1419 res
= LLVMBuildExtractValue(ctx
->builder
, res
, 1, "");
1420 res
= LLVMBuildZExt(ctx
->builder
, res
, ctx
->i32
, "");
1424 static LLVMValueRef
emit_b2f(struct ac_llvm_context
*ctx
,
1427 return LLVMBuildAnd(ctx
->builder
, src0
, LLVMBuildBitCast(ctx
->builder
, LLVMConstReal(ctx
->f32
, 1.0), ctx
->i32
, ""), "");
1430 static LLVMValueRef
emit_f2b(struct ac_llvm_context
*ctx
,
1433 src0
= ac_to_float(ctx
, src0
);
1434 return LLVMBuildSExt(ctx
->builder
,
1435 LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
, src0
, ctx
->f32_0
, ""),
1439 static LLVMValueRef
emit_b2i(struct ac_llvm_context
*ctx
,
1443 LLVMValueRef result
= LLVMBuildAnd(ctx
->builder
, src0
, ctx
->i32_1
, "");
1448 return LLVMBuildZExt(ctx
->builder
, result
, ctx
->i64
, "");
1451 static LLVMValueRef
emit_i2b(struct ac_llvm_context
*ctx
,
1454 return LLVMBuildSExt(ctx
->builder
,
1455 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
, ctx
->i32_0
, ""),
1459 static LLVMValueRef
emit_f2f16(struct nir_to_llvm_context
*ctx
,
1462 LLVMValueRef result
;
1463 LLVMValueRef cond
= NULL
;
1465 src0
= ac_to_float(&ctx
->ac
, src0
);
1466 result
= LLVMBuildFPTrunc(ctx
->builder
, src0
, ctx
->ac
.f16
, "");
1468 if (ctx
->options
->chip_class
>= VI
) {
1469 LLVMValueRef args
[2];
1470 /* Check if the result is a denormal - and flush to 0 if so. */
1472 args
[1] = LLVMConstInt(ctx
->ac
.i32
, N_SUBNORMAL
| P_SUBNORMAL
, false);
1473 cond
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.class.f16", ctx
->ac
.i1
, args
, 2, AC_FUNC_ATTR_READNONE
);
1476 /* need to convert back up to f32 */
1477 result
= LLVMBuildFPExt(ctx
->builder
, result
, ctx
->ac
.f32
, "");
1479 if (ctx
->options
->chip_class
>= VI
)
1480 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->ac
.f32_0
, result
, "");
1483 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1484 * so compare the result and flush to 0 if it's smaller.
1486 LLVMValueRef temp
, cond2
;
1487 temp
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1488 ctx
->ac
.f32
, result
);
1489 cond
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUGT
,
1490 LLVMBuildBitCast(ctx
->builder
, LLVMConstInt(ctx
->ac
.i32
, 0x38800000, false), ctx
->ac
.f32
, ""),
1492 cond2
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
,
1493 temp
, ctx
->ac
.f32_0
, "");
1494 cond
= LLVMBuildAnd(ctx
->builder
, cond
, cond2
, "");
1495 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->ac
.f32_0
, result
, "");
1500 static LLVMValueRef
emit_umul_high(struct ac_llvm_context
*ctx
,
1501 LLVMValueRef src0
, LLVMValueRef src1
)
1503 LLVMValueRef dst64
, result
;
1504 src0
= LLVMBuildZExt(ctx
->builder
, src0
, ctx
->i64
, "");
1505 src1
= LLVMBuildZExt(ctx
->builder
, src1
, ctx
->i64
, "");
1507 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1508 dst64
= LLVMBuildLShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1509 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1513 static LLVMValueRef
emit_imul_high(struct ac_llvm_context
*ctx
,
1514 LLVMValueRef src0
, LLVMValueRef src1
)
1516 LLVMValueRef dst64
, result
;
1517 src0
= LLVMBuildSExt(ctx
->builder
, src0
, ctx
->i64
, "");
1518 src1
= LLVMBuildSExt(ctx
->builder
, src1
, ctx
->i64
, "");
1520 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1521 dst64
= LLVMBuildAShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1522 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1526 static LLVMValueRef
emit_bitfield_extract(struct ac_llvm_context
*ctx
,
1528 const LLVMValueRef srcs
[3])
1530 LLVMValueRef result
;
1531 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, srcs
[2], LLVMConstInt(ctx
->i32
, 32, false), "");
1533 result
= ac_build_bfe(ctx
, srcs
[0], srcs
[1], srcs
[2], is_signed
);
1534 result
= LLVMBuildSelect(ctx
->builder
, icond
, srcs
[0], result
, "");
1538 static LLVMValueRef
emit_bitfield_insert(struct ac_llvm_context
*ctx
,
1539 LLVMValueRef src0
, LLVMValueRef src1
,
1540 LLVMValueRef src2
, LLVMValueRef src3
)
1542 LLVMValueRef bfi_args
[3], result
;
1544 bfi_args
[0] = LLVMBuildShl(ctx
->builder
,
1545 LLVMBuildSub(ctx
->builder
,
1546 LLVMBuildShl(ctx
->builder
,
1551 bfi_args
[1] = LLVMBuildShl(ctx
->builder
, src1
, src2
, "");
1554 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, src3
, LLVMConstInt(ctx
->i32
, 32, false), "");
1557 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1558 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1560 result
= LLVMBuildXor(ctx
->builder
, bfi_args
[2],
1561 LLVMBuildAnd(ctx
->builder
, bfi_args
[0],
1562 LLVMBuildXor(ctx
->builder
, bfi_args
[1], bfi_args
[2], ""), ""), "");
1564 result
= LLVMBuildSelect(ctx
->builder
, icond
, src1
, result
, "");
1568 static LLVMValueRef
emit_pack_half_2x16(struct ac_llvm_context
*ctx
,
1571 LLVMValueRef comp
[2];
1573 src0
= ac_to_float(ctx
, src0
);
1574 comp
[0] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_0
, "");
1575 comp
[1] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_1
, "");
1577 return ac_build_cvt_pkrtz_f16(ctx
, comp
);
1580 static LLVMValueRef
emit_unpack_half_2x16(struct ac_llvm_context
*ctx
,
1583 LLVMValueRef const16
= LLVMConstInt(ctx
->i32
, 16, false);
1584 LLVMValueRef temps
[2], result
, val
;
1587 for (i
= 0; i
< 2; i
++) {
1588 val
= i
== 1 ? LLVMBuildLShr(ctx
->builder
, src0
, const16
, "") : src0
;
1589 val
= LLVMBuildTrunc(ctx
->builder
, val
, ctx
->i16
, "");
1590 val
= LLVMBuildBitCast(ctx
->builder
, val
, ctx
->f16
, "");
1591 temps
[i
] = LLVMBuildFPExt(ctx
->builder
, val
, ctx
->f32
, "");
1594 result
= LLVMBuildInsertElement(ctx
->builder
, LLVMGetUndef(ctx
->v2f32
), temps
[0],
1596 result
= LLVMBuildInsertElement(ctx
->builder
, result
, temps
[1],
1601 static LLVMValueRef
emit_ddxy(struct ac_nir_context
*ctx
,
1607 LLVMValueRef result
;
1609 if (op
== nir_op_fddx_fine
|| op
== nir_op_fddx
)
1610 mask
= AC_TID_MASK_LEFT
;
1611 else if (op
== nir_op_fddy_fine
|| op
== nir_op_fddy
)
1612 mask
= AC_TID_MASK_TOP
;
1614 mask
= AC_TID_MASK_TOP_LEFT
;
1616 /* for DDX we want to next X pixel, DDY next Y pixel. */
1617 if (op
== nir_op_fddx_fine
||
1618 op
== nir_op_fddx_coarse
||
1624 result
= ac_build_ddxy(&ctx
->ac
, mask
, idx
, src0
);
1629 * this takes an I,J coordinate pair,
1630 * and works out the X and Y derivatives.
1631 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1633 static LLVMValueRef
emit_ddxy_interp(
1634 struct ac_nir_context
*ctx
,
1635 LLVMValueRef interp_ij
)
1637 LLVMValueRef result
[4], a
;
1640 for (i
= 0; i
< 2; i
++) {
1641 a
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_ij
,
1642 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
1643 result
[i
] = emit_ddxy(ctx
, nir_op_fddx
, a
);
1644 result
[2+i
] = emit_ddxy(ctx
, nir_op_fddy
, a
);
1646 return ac_build_gather_values(&ctx
->ac
, result
, 4);
1649 static void visit_alu(struct ac_nir_context
*ctx
, const nir_alu_instr
*instr
)
1651 LLVMValueRef src
[4], result
= NULL
;
1652 unsigned num_components
= instr
->dest
.dest
.ssa
.num_components
;
1653 unsigned src_components
;
1654 LLVMTypeRef def_type
= get_def_type(ctx
, &instr
->dest
.dest
.ssa
);
1656 assert(nir_op_infos
[instr
->op
].num_inputs
<= ARRAY_SIZE(src
));
1657 switch (instr
->op
) {
1663 case nir_op_pack_half_2x16
:
1666 case nir_op_unpack_half_2x16
:
1670 src_components
= num_components
;
1673 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1674 src
[i
] = get_alu_src(ctx
, instr
->src
[i
], src_components
);
1676 switch (instr
->op
) {
1682 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1683 result
= LLVMBuildFNeg(ctx
->ac
.builder
, src
[0], "");
1686 result
= LLVMBuildNeg(ctx
->ac
.builder
, src
[0], "");
1689 result
= LLVMBuildNot(ctx
->ac
.builder
, src
[0], "");
1692 result
= LLVMBuildAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1695 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1696 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1697 result
= LLVMBuildFAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1700 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1701 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1702 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1705 result
= LLVMBuildSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1708 result
= LLVMBuildMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1711 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1714 result
= LLVMBuildURem(ctx
->ac
.builder
, src
[0], src
[1], "");
1717 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1718 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1719 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1720 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1721 ac_to_float_type(&ctx
->ac
, def_type
), result
);
1722 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[1] , result
, "");
1723 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], result
, "");
1726 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1727 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1728 result
= LLVMBuildFRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1731 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1734 result
= LLVMBuildSDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1737 result
= LLVMBuildUDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1740 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1741 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1742 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1745 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1746 result
= ac_build_fdiv(&ctx
->ac
, instr
->dest
.dest
.ssa
.bit_size
== 32 ? ctx
->ac
.f32_1
: ctx
->ac
.f64_1
,
1750 result
= LLVMBuildAnd(ctx
->ac
.builder
, src
[0], src
[1], "");
1753 result
= LLVMBuildOr(ctx
->ac
.builder
, src
[0], src
[1], "");
1756 result
= LLVMBuildXor(ctx
->ac
.builder
, src
[0], src
[1], "");
1759 result
= LLVMBuildShl(ctx
->ac
.builder
, src
[0],
1760 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1761 LLVMTypeOf(src
[0]), ""),
1765 result
= LLVMBuildAShr(ctx
->ac
.builder
, src
[0],
1766 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1767 LLVMTypeOf(src
[0]), ""),
1771 result
= LLVMBuildLShr(ctx
->ac
.builder
, src
[0],
1772 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1773 LLVMTypeOf(src
[0]), ""),
1777 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1780 result
= emit_int_cmp(&ctx
->ac
, LLVMIntNE
, src
[0], src
[1]);
1783 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, src
[0], src
[1]);
1786 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSGE
, src
[0], src
[1]);
1789 result
= emit_int_cmp(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1792 result
= emit_int_cmp(&ctx
->ac
, LLVMIntUGE
, src
[0], src
[1]);
1795 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUEQ
, src
[0], src
[1]);
1798 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUNE
, src
[0], src
[1]);
1801 result
= emit_float_cmp(&ctx
->ac
, LLVMRealULT
, src
[0], src
[1]);
1804 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUGE
, src
[0], src
[1]);
1807 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1808 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1811 result
= emit_iabs(&ctx
->ac
, src
[0]);
1814 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, src
[0], src
[1]);
1817 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1820 result
= emit_minmax_int(&ctx
->ac
, LLVMIntUGT
, src
[0], src
[1]);
1823 result
= emit_minmax_int(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1826 result
= emit_isign(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
1829 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1830 result
= emit_fsign(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
1833 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1834 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1837 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.trunc",
1838 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1841 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.ceil",
1842 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1844 case nir_op_fround_even
:
1845 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.rint",
1846 ac_to_float_type(&ctx
->ac
, def_type
),src
[0]);
1849 result
= emit_ffract(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
1852 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sin",
1853 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1856 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.cos",
1857 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1860 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1861 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1864 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.exp2",
1865 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1868 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.log2",
1869 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1872 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1873 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1874 result
= ac_build_fdiv(&ctx
->ac
, instr
->dest
.dest
.ssa
.bit_size
== 32 ? ctx
->ac
.f32_1
: ctx
->ac
.f64_1
,
1878 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.pow",
1879 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1882 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.maxnum",
1883 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1884 if (ctx
->ac
.chip_class
< GFX9
&&
1885 instr
->dest
.dest
.ssa
.bit_size
== 32) {
1886 /* Only pre-GFX9 chips do not flush denorms. */
1887 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1888 ac_to_float_type(&ctx
->ac
, def_type
),
1893 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.minnum",
1894 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1895 if (ctx
->ac
.chip_class
< GFX9
&&
1896 instr
->dest
.dest
.ssa
.bit_size
== 32) {
1897 /* Only pre-GFX9 chips do not flush denorms. */
1898 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1899 ac_to_float_type(&ctx
->ac
, def_type
),
1904 result
= emit_intrin_3f_param(&ctx
->ac
, "llvm.fmuladd",
1905 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1], src
[2]);
1907 case nir_op_ibitfield_extract
:
1908 result
= emit_bitfield_extract(&ctx
->ac
, true, src
);
1910 case nir_op_ubitfield_extract
:
1911 result
= emit_bitfield_extract(&ctx
->ac
, false, src
);
1913 case nir_op_bitfield_insert
:
1914 result
= emit_bitfield_insert(&ctx
->ac
, src
[0], src
[1], src
[2], src
[3]);
1916 case nir_op_bitfield_reverse
:
1917 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.bitreverse.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1919 case nir_op_bit_count
:
1920 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1925 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1926 src
[i
] = ac_to_integer(&ctx
->ac
, src
[i
]);
1927 result
= ac_build_gather_values(&ctx
->ac
, src
, num_components
);
1931 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1932 result
= LLVMBuildFPToSI(ctx
->ac
.builder
, src
[0], def_type
, "");
1936 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1937 result
= LLVMBuildFPToUI(ctx
->ac
.builder
, src
[0], def_type
, "");
1941 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1942 result
= LLVMBuildSIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1946 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1947 result
= LLVMBuildUIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1950 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1951 result
= LLVMBuildFPExt(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1954 result
= LLVMBuildFPTrunc(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1958 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1959 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1960 result
= LLVMBuildZExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1962 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1966 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1967 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1968 result
= LLVMBuildSExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1970 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1973 result
= emit_bcsel(&ctx
->ac
, src
[0], src
[1], src
[2]);
1975 case nir_op_find_lsb
:
1976 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1977 result
= ac_find_lsb(&ctx
->ac
, ctx
->ac
.i32
, src
[0]);
1979 case nir_op_ufind_msb
:
1980 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1981 result
= ac_build_umsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1983 case nir_op_ifind_msb
:
1984 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1985 result
= ac_build_imsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1987 case nir_op_uadd_carry
:
1988 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1989 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1990 result
= emit_uint_carry(&ctx
->ac
, "llvm.uadd.with.overflow.i32", src
[0], src
[1]);
1992 case nir_op_usub_borrow
:
1993 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1994 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1995 result
= emit_uint_carry(&ctx
->ac
, "llvm.usub.with.overflow.i32", src
[0], src
[1]);
1998 result
= emit_b2f(&ctx
->ac
, src
[0]);
2001 result
= emit_f2b(&ctx
->ac
, src
[0]);
2004 result
= emit_b2i(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
2007 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2008 result
= emit_i2b(&ctx
->ac
, src
[0]);
2010 case nir_op_fquantize2f16
:
2011 result
= emit_f2f16(ctx
->nctx
, src
[0]);
2013 case nir_op_umul_high
:
2014 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2015 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
2016 result
= emit_umul_high(&ctx
->ac
, src
[0], src
[1]);
2018 case nir_op_imul_high
:
2019 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2020 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
2021 result
= emit_imul_high(&ctx
->ac
, src
[0], src
[1]);
2023 case nir_op_pack_half_2x16
:
2024 result
= emit_pack_half_2x16(&ctx
->ac
, src
[0]);
2026 case nir_op_unpack_half_2x16
:
2027 result
= emit_unpack_half_2x16(&ctx
->ac
, src
[0]);
2031 case nir_op_fddx_fine
:
2032 case nir_op_fddy_fine
:
2033 case nir_op_fddx_coarse
:
2034 case nir_op_fddy_coarse
:
2035 result
= emit_ddxy(ctx
, instr
->op
, src
[0]);
2038 case nir_op_unpack_64_2x32_split_x
: {
2039 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
2040 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
2043 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2048 case nir_op_unpack_64_2x32_split_y
: {
2049 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
2050 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
2053 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2058 case nir_op_pack_64_2x32_split
: {
2059 LLVMValueRef tmp
= LLVMGetUndef(ctx
->ac
.v2i32
);
2060 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2061 src
[0], ctx
->ac
.i32_0
, "");
2062 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2063 src
[1], ctx
->ac
.i32_1
, "");
2064 result
= LLVMBuildBitCast(ctx
->ac
.builder
, tmp
, ctx
->ac
.i64
, "");
2069 fprintf(stderr
, "Unknown NIR alu instr: ");
2070 nir_print_instr(&instr
->instr
, stderr
);
2071 fprintf(stderr
, "\n");
2076 assert(instr
->dest
.dest
.is_ssa
);
2077 result
= ac_to_integer(&ctx
->ac
, result
);
2078 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.dest
.ssa
,
2083 static void visit_load_const(struct ac_nir_context
*ctx
,
2084 const nir_load_const_instr
*instr
)
2086 LLVMValueRef values
[4], value
= NULL
;
2087 LLVMTypeRef element_type
=
2088 LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
2090 for (unsigned i
= 0; i
< instr
->def
.num_components
; ++i
) {
2091 switch (instr
->def
.bit_size
) {
2093 values
[i
] = LLVMConstInt(element_type
,
2094 instr
->value
.u32
[i
], false);
2097 values
[i
] = LLVMConstInt(element_type
,
2098 instr
->value
.u64
[i
], false);
2102 "unsupported nir load_const bit_size: %d\n",
2103 instr
->def
.bit_size
);
2107 if (instr
->def
.num_components
> 1) {
2108 value
= LLVMConstVector(values
, instr
->def
.num_components
);
2112 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, value
);
2115 static LLVMValueRef
cast_ptr(struct nir_to_llvm_context
*ctx
, LLVMValueRef ptr
,
2118 int addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
2119 return LLVMBuildBitCast(ctx
->builder
, ptr
,
2120 LLVMPointerType(type
, addr_space
), "");
2124 get_buffer_size(struct ac_nir_context
*ctx
, LLVMValueRef descriptor
, bool in_elements
)
2127 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2128 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
2131 if (ctx
->ac
.chip_class
== VI
&& in_elements
) {
2132 /* On VI, the descriptor contains the size in bytes,
2133 * but TXQ must return the size in elements.
2134 * The stride is always non-zero for resources using TXQ.
2136 LLVMValueRef stride
=
2137 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2139 stride
= LLVMBuildLShr(ctx
->ac
.builder
, stride
,
2140 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
2141 stride
= LLVMBuildAnd(ctx
->ac
.builder
, stride
,
2142 LLVMConstInt(ctx
->ac
.i32
, 0x3fff, false), "");
2144 size
= LLVMBuildUDiv(ctx
->ac
.builder
, size
, stride
, "");
2150 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2153 static void build_int_type_name(
2155 char *buf
, unsigned bufsize
)
2157 assert(bufsize
>= 6);
2159 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
2160 snprintf(buf
, bufsize
, "v%ui32",
2161 LLVMGetVectorSize(type
));
2166 static LLVMValueRef
radv_lower_gather4_integer(struct ac_llvm_context
*ctx
,
2167 struct ac_image_args
*args
,
2168 const nir_tex_instr
*instr
)
2170 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2171 LLVMValueRef coord
= args
->addr
;
2172 LLVMValueRef half_texel
[2];
2173 LLVMValueRef compare_cube_wa
= NULL
;
2174 LLVMValueRef result
;
2176 unsigned coord_vgpr_index
= (unsigned)args
->offset
+ (unsigned)args
->compare
;
2180 struct ac_image_args txq_args
= { 0 };
2182 txq_args
.da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
2183 txq_args
.opcode
= ac_image_get_resinfo
;
2184 txq_args
.dmask
= 0xf;
2185 txq_args
.addr
= ctx
->i32_0
;
2186 txq_args
.resource
= args
->resource
;
2187 LLVMValueRef size
= ac_build_image_opcode(ctx
, &txq_args
);
2189 for (c
= 0; c
< 2; c
++) {
2190 half_texel
[c
] = LLVMBuildExtractElement(ctx
->builder
, size
,
2191 LLVMConstInt(ctx
->i32
, c
, false), "");
2192 half_texel
[c
] = LLVMBuildUIToFP(ctx
->builder
, half_texel
[c
], ctx
->f32
, "");
2193 half_texel
[c
] = ac_build_fdiv(ctx
, ctx
->f32_1
, half_texel
[c
]);
2194 half_texel
[c
] = LLVMBuildFMul(ctx
->builder
, half_texel
[c
],
2195 LLVMConstReal(ctx
->f32
, -0.5), "");
2199 LLVMValueRef orig_coords
= args
->addr
;
2201 for (c
= 0; c
< 2; c
++) {
2203 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, coord_vgpr_index
+ c
, 0);
2204 tmp
= LLVMBuildExtractElement(ctx
->builder
, coord
, index
, "");
2205 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2206 tmp
= LLVMBuildFAdd(ctx
->builder
, tmp
, half_texel
[c
], "");
2207 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2208 coord
= LLVMBuildInsertElement(ctx
->builder
, coord
, tmp
, index
, "");
2213 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2214 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2215 * workaround by sampling using a scaled type and converting.
2216 * This is taken from amdgpu-pro shaders.
2218 /* NOTE this produces some ugly code compared to amdgpu-pro,
2219 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2220 * and then reads them back. -pro generates two selects,
2221 * one s_cmp for the descriptor rewriting
2222 * one v_cmp for the coordinate and result changes.
2224 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2225 LLVMValueRef tmp
, tmp2
;
2227 /* workaround 8/8/8/8 uint/sint cube gather bug */
2228 /* first detect it then change to a scaled read and f2i */
2229 tmp
= LLVMBuildExtractElement(ctx
->builder
, args
->resource
, ctx
->i32_1
, "");
2232 /* extract the DATA_FORMAT */
2233 tmp
= ac_build_bfe(ctx
, tmp
, LLVMConstInt(ctx
->i32
, 20, false),
2234 LLVMConstInt(ctx
->i32
, 6, false), false);
2236 /* is the DATA_FORMAT == 8_8_8_8 */
2237 compare_cube_wa
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, tmp
, LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false), "");
2239 if (stype
== GLSL_TYPE_UINT
)
2240 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2241 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0x8000000, false),
2242 LLVMConstInt(ctx
->i32
, 0x10000000, false), "");
2244 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2245 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0xc000000, false),
2246 LLVMConstInt(ctx
->i32
, 0x14000000, false), "");
2248 /* replace the NUM FORMAT in the descriptor */
2249 tmp2
= LLVMBuildAnd(ctx
->builder
, tmp2
, LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false), "");
2250 tmp2
= LLVMBuildOr(ctx
->builder
, tmp2
, tmp
, "");
2252 args
->resource
= LLVMBuildInsertElement(ctx
->builder
, args
->resource
, tmp2
, ctx
->i32_1
, "");
2254 /* don't modify the coordinates for this case */
2255 coord
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, orig_coords
, coord
, "");
2258 result
= ac_build_image_opcode(ctx
, args
);
2260 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2261 LLVMValueRef tmp
, tmp2
;
2263 /* if the cube workaround is in place, f2i the result. */
2264 for (c
= 0; c
< 4; c
++) {
2265 tmp
= LLVMBuildExtractElement(ctx
->builder
, result
, LLVMConstInt(ctx
->i32
, c
, false), "");
2266 if (stype
== GLSL_TYPE_UINT
)
2267 tmp2
= LLVMBuildFPToUI(ctx
->builder
, tmp
, ctx
->i32
, "");
2269 tmp2
= LLVMBuildFPToSI(ctx
->builder
, tmp
, ctx
->i32
, "");
2270 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2271 tmp2
= LLVMBuildBitCast(ctx
->builder
, tmp2
, ctx
->i32
, "");
2272 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, tmp2
, tmp
, "");
2273 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2274 result
= LLVMBuildInsertElement(ctx
->builder
, result
, tmp
, LLVMConstInt(ctx
->i32
, c
, false), "");
2280 static LLVMValueRef
build_tex_intrinsic(struct ac_nir_context
*ctx
,
2281 const nir_tex_instr
*instr
,
2283 struct ac_image_args
*args
)
2285 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
2286 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
2288 return ac_build_buffer_load_format(&ctx
->ac
,
2292 util_last_bit(mask
),
2296 args
->opcode
= ac_image_sample
;
2297 args
->compare
= instr
->is_shadow
;
2299 switch (instr
->op
) {
2301 case nir_texop_txf_ms
:
2302 case nir_texop_samples_identical
:
2303 args
->opcode
= lod_is_zero
||
2304 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
?
2305 ac_image_load
: ac_image_load_mip
;
2306 args
->compare
= false;
2307 args
->offset
= false;
2314 args
->level_zero
= true;
2319 case nir_texop_query_levels
:
2320 args
->opcode
= ac_image_get_resinfo
;
2323 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
2324 args
->level_zero
= true;
2330 args
->opcode
= ac_image_gather4
;
2331 args
->level_zero
= true;
2334 args
->opcode
= ac_image_get_lod
;
2335 args
->compare
= false;
2336 args
->offset
= false;
2342 if (instr
->op
== nir_texop_tg4
&& ctx
->ac
.chip_class
<= VI
) {
2343 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2344 if (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
) {
2345 return radv_lower_gather4_integer(&ctx
->ac
, args
, instr
);
2348 return ac_build_image_opcode(&ctx
->ac
, args
);
2351 static LLVMValueRef
visit_vulkan_resource_index(struct nir_to_llvm_context
*ctx
,
2352 nir_intrinsic_instr
*instr
)
2354 LLVMValueRef index
= get_src(ctx
->nir
, instr
->src
[0]);
2355 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
2356 unsigned binding
= nir_intrinsic_binding(instr
);
2357 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
2358 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
2359 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
2360 unsigned base_offset
= layout
->binding
[binding
].offset
;
2361 LLVMValueRef offset
, stride
;
2363 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
2364 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
2365 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
2366 layout
->binding
[binding
].dynamic_offset_offset
;
2367 desc_ptr
= ctx
->push_constants
;
2368 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
2369 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2371 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
2373 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
2374 index
= LLVMBuildMul(ctx
->builder
, index
, stride
, "");
2375 offset
= LLVMBuildAdd(ctx
->builder
, offset
, index
, "");
2377 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
2378 desc_ptr
= cast_ptr(ctx
, desc_ptr
, ctx
->ac
.v4i32
);
2379 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2384 static LLVMValueRef
visit_vulkan_resource_reindex(struct nir_to_llvm_context
*ctx
,
2385 nir_intrinsic_instr
*instr
)
2387 LLVMValueRef ptr
= get_src(ctx
->nir
, instr
->src
[0]);
2388 LLVMValueRef index
= get_src(ctx
->nir
, instr
->src
[1]);
2390 LLVMValueRef result
= LLVMBuildGEP(ctx
->builder
, ptr
, &index
, 1, "");
2391 LLVMSetMetadata(result
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2395 static LLVMValueRef
visit_load_push_constant(struct nir_to_llvm_context
*ctx
,
2396 nir_intrinsic_instr
*instr
)
2398 LLVMValueRef ptr
, addr
;
2400 addr
= LLVMConstInt(ctx
->ac
.i32
, nir_intrinsic_base(instr
), 0);
2401 addr
= LLVMBuildAdd(ctx
->builder
, addr
, get_src(ctx
->nir
, instr
->src
[0]), "");
2403 ptr
= ac_build_gep0(&ctx
->ac
, ctx
->push_constants
, addr
);
2404 ptr
= cast_ptr(ctx
, ptr
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
));
2406 return LLVMBuildLoad(ctx
->builder
, ptr
, "");
2409 static LLVMValueRef
visit_get_buffer_size(struct ac_nir_context
*ctx
,
2410 const nir_intrinsic_instr
*instr
)
2412 LLVMValueRef index
= get_src(ctx
, instr
->src
[0]);
2414 return get_buffer_size(ctx
, ctx
->abi
->load_ssbo(ctx
->abi
, index
, false), false);
2417 static uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2419 uint32_t new_mask
= 0;
2420 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2421 if (mask
& (1u << i
))
2422 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2426 static LLVMValueRef
extract_vector_range(struct ac_llvm_context
*ctx
, LLVMValueRef src
,
2427 unsigned start
, unsigned count
)
2429 LLVMTypeRef type
= LLVMTypeOf(src
);
2431 if (LLVMGetTypeKind(type
) != LLVMVectorTypeKind
) {
2437 unsigned src_elements
= LLVMGetVectorSize(type
);
2438 assert(start
< src_elements
);
2439 assert(start
+ count
<= src_elements
);
2441 if (start
== 0 && count
== src_elements
)
2445 return LLVMBuildExtractElement(ctx
->builder
, src
, LLVMConstInt(ctx
->i32
, start
, false), "");
2448 LLVMValueRef indices
[8];
2449 for (unsigned i
= 0; i
< count
; ++i
)
2450 indices
[i
] = LLVMConstInt(ctx
->i32
, start
+ i
, false);
2452 LLVMValueRef swizzle
= LLVMConstVector(indices
, count
);
2453 return LLVMBuildShuffleVector(ctx
->builder
, src
, src
, swizzle
, "");
2456 static void visit_store_ssbo(struct ac_nir_context
*ctx
,
2457 nir_intrinsic_instr
*instr
)
2459 const char *store_name
;
2460 LLVMValueRef src_data
= get_src(ctx
, instr
->src
[0]);
2461 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2462 int elem_size_mult
= get_elem_bits(&ctx
->ac
, LLVMTypeOf(src_data
)) / 32;
2463 int components_32bit
= elem_size_mult
* instr
->num_components
;
2464 unsigned writemask
= nir_intrinsic_write_mask(instr
);
2465 LLVMValueRef base_data
, base_offset
;
2466 LLVMValueRef params
[6];
2468 params
[1] = ctx
->abi
->load_ssbo(ctx
->abi
,
2469 get_src(ctx
, instr
->src
[1]), true);
2470 params
[2] = ctx
->ac
.i32_0
; /* vindex */
2471 params
[4] = ctx
->ac
.i1false
; /* glc */
2472 params
[5] = ctx
->ac
.i1false
; /* slc */
2474 if (components_32bit
> 1)
2475 data_type
= LLVMVectorType(ctx
->ac
.f32
, components_32bit
);
2477 writemask
= widen_mask(writemask
, elem_size_mult
);
2479 base_data
= ac_to_float(&ctx
->ac
, src_data
);
2480 base_data
= trim_vector(&ctx
->ac
, base_data
, instr
->num_components
);
2481 base_data
= LLVMBuildBitCast(ctx
->ac
.builder
, base_data
,
2483 base_offset
= get_src(ctx
, instr
->src
[2]); /* voffset */
2487 LLVMValueRef offset
;
2489 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
2491 /* Due to an LLVM limitation, split 3-element writes
2492 * into a 2-element and a 1-element write. */
2494 writemask
|= 1 << (start
+ 2);
2499 writemask
|= ((1u << (count
- 4)) - 1u) << (start
+ 4);
2504 store_name
= "llvm.amdgcn.buffer.store.v4f32";
2505 } else if (count
== 2) {
2506 store_name
= "llvm.amdgcn.buffer.store.v2f32";
2510 store_name
= "llvm.amdgcn.buffer.store.f32";
2512 data
= extract_vector_range(&ctx
->ac
, base_data
, start
, count
);
2514 offset
= base_offset
;
2516 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, LLVMConstInt(ctx
->ac
.i32
, start
* 4, false), "");
2520 ac_build_intrinsic(&ctx
->ac
, store_name
,
2521 ctx
->ac
.voidt
, params
, 6, 0);
2525 static LLVMValueRef
visit_atomic_ssbo(struct ac_nir_context
*ctx
,
2526 const nir_intrinsic_instr
*instr
)
2529 LLVMValueRef params
[6];
2532 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
) {
2533 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[3]), 0);
2535 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[2]), 0);
2536 params
[arg_count
++] = ctx
->abi
->load_ssbo(ctx
->abi
,
2537 get_src(ctx
, instr
->src
[0]),
2539 params
[arg_count
++] = ctx
->ac
.i32_0
; /* vindex */
2540 params
[arg_count
++] = get_src(ctx
, instr
->src
[1]); /* voffset */
2541 params
[arg_count
++] = LLVMConstInt(ctx
->ac
.i1
, 0, false); /* slc */
2543 switch (instr
->intrinsic
) {
2544 case nir_intrinsic_ssbo_atomic_add
:
2545 name
= "llvm.amdgcn.buffer.atomic.add";
2547 case nir_intrinsic_ssbo_atomic_imin
:
2548 name
= "llvm.amdgcn.buffer.atomic.smin";
2550 case nir_intrinsic_ssbo_atomic_umin
:
2551 name
= "llvm.amdgcn.buffer.atomic.umin";
2553 case nir_intrinsic_ssbo_atomic_imax
:
2554 name
= "llvm.amdgcn.buffer.atomic.smax";
2556 case nir_intrinsic_ssbo_atomic_umax
:
2557 name
= "llvm.amdgcn.buffer.atomic.umax";
2559 case nir_intrinsic_ssbo_atomic_and
:
2560 name
= "llvm.amdgcn.buffer.atomic.and";
2562 case nir_intrinsic_ssbo_atomic_or
:
2563 name
= "llvm.amdgcn.buffer.atomic.or";
2565 case nir_intrinsic_ssbo_atomic_xor
:
2566 name
= "llvm.amdgcn.buffer.atomic.xor";
2568 case nir_intrinsic_ssbo_atomic_exchange
:
2569 name
= "llvm.amdgcn.buffer.atomic.swap";
2571 case nir_intrinsic_ssbo_atomic_comp_swap
:
2572 name
= "llvm.amdgcn.buffer.atomic.cmpswap";
2578 return ac_build_intrinsic(&ctx
->ac
, name
, ctx
->ac
.i32
, params
, arg_count
, 0);
2581 static LLVMValueRef
visit_load_buffer(struct ac_nir_context
*ctx
,
2582 const nir_intrinsic_instr
*instr
)
2584 LLVMValueRef results
[2];
2585 int load_components
;
2586 int num_components
= instr
->num_components
;
2587 if (instr
->dest
.ssa
.bit_size
== 64)
2588 num_components
*= 2;
2590 for (int i
= 0; i
< num_components
; i
+= load_components
) {
2591 load_components
= MIN2(num_components
- i
, 4);
2592 const char *load_name
;
2593 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2594 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, i
* 4, false);
2595 offset
= LLVMBuildAdd(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[1]), offset
, "");
2597 if (load_components
== 3)
2598 data_type
= LLVMVectorType(ctx
->ac
.f32
, 4);
2599 else if (load_components
> 1)
2600 data_type
= LLVMVectorType(ctx
->ac
.f32
, load_components
);
2602 if (load_components
>= 3)
2603 load_name
= "llvm.amdgcn.buffer.load.v4f32";
2604 else if (load_components
== 2)
2605 load_name
= "llvm.amdgcn.buffer.load.v2f32";
2606 else if (load_components
== 1)
2607 load_name
= "llvm.amdgcn.buffer.load.f32";
2609 unreachable("unhandled number of components");
2611 LLVMValueRef params
[] = {
2612 ctx
->abi
->load_ssbo(ctx
->abi
,
2613 get_src(ctx
, instr
->src
[0]),
2621 results
[i
> 0 ? 1 : 0] = ac_build_intrinsic(&ctx
->ac
, load_name
, data_type
, params
, 5, 0);
2625 LLVMValueRef ret
= results
[0];
2626 if (num_components
> 4 || num_components
== 3) {
2627 LLVMValueRef masks
[] = {
2628 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
2629 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
2630 LLVMConstInt(ctx
->ac
.i32
, 4, false), LLVMConstInt(ctx
->ac
.i32
, 5, false),
2631 LLVMConstInt(ctx
->ac
.i32
, 6, false), LLVMConstInt(ctx
->ac
.i32
, 7, false)
2634 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
2635 ret
= LLVMBuildShuffleVector(ctx
->ac
.builder
, results
[0],
2636 results
[num_components
> 4 ? 1 : 0], swizzle
, "");
2639 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2640 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2643 static LLVMValueRef
visit_load_ubo_buffer(struct ac_nir_context
*ctx
,
2644 const nir_intrinsic_instr
*instr
)
2647 LLVMValueRef rsrc
= get_src(ctx
, instr
->src
[0]);
2648 LLVMValueRef offset
= get_src(ctx
, instr
->src
[1]);
2649 int num_components
= instr
->num_components
;
2651 if (ctx
->abi
->load_ubo
)
2652 rsrc
= ctx
->abi
->load_ubo(ctx
->abi
, rsrc
);
2654 if (instr
->dest
.ssa
.bit_size
== 64)
2655 num_components
*= 2;
2657 ret
= ac_build_buffer_load(&ctx
->ac
, rsrc
, num_components
, NULL
, offset
,
2658 NULL
, 0, false, false, true, true);
2659 ret
= trim_vector(&ctx
->ac
, ret
, num_components
);
2660 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2661 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2665 get_deref_offset(struct ac_nir_context
*ctx
, nir_deref_var
*deref
,
2666 bool vs_in
, unsigned *vertex_index_out
,
2667 LLVMValueRef
*vertex_index_ref
,
2668 unsigned *const_out
, LLVMValueRef
*indir_out
)
2670 unsigned const_offset
= 0;
2671 nir_deref
*tail
= &deref
->deref
;
2672 LLVMValueRef offset
= NULL
;
2674 if (vertex_index_out
!= NULL
|| vertex_index_ref
!= NULL
) {
2676 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2677 if (vertex_index_out
)
2678 *vertex_index_out
= deref_array
->base_offset
;
2680 if (vertex_index_ref
) {
2681 LLVMValueRef vtx
= LLVMConstInt(ctx
->ac
.i32
, deref_array
->base_offset
, false);
2682 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
2683 vtx
= LLVMBuildAdd(ctx
->ac
.builder
, vtx
, get_src(ctx
, deref_array
->indirect
), "");
2685 *vertex_index_ref
= vtx
;
2689 if (deref
->var
->data
.compact
) {
2690 assert(tail
->child
->deref_type
== nir_deref_type_array
);
2691 assert(glsl_type_is_scalar(glsl_without_array(deref
->var
->type
)));
2692 nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
2693 /* We always lower indirect dereferences for "compact" array vars. */
2694 assert(deref_array
->deref_array_type
== nir_deref_array_type_direct
);
2696 const_offset
= deref_array
->base_offset
;
2700 while (tail
->child
!= NULL
) {
2701 const struct glsl_type
*parent_type
= tail
->type
;
2704 if (tail
->deref_type
== nir_deref_type_array
) {
2705 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2706 LLVMValueRef index
, stride
, local_offset
;
2707 unsigned size
= glsl_count_attribute_slots(tail
->type
, vs_in
);
2709 const_offset
+= size
* deref_array
->base_offset
;
2710 if (deref_array
->deref_array_type
== nir_deref_array_type_direct
)
2713 assert(deref_array
->deref_array_type
== nir_deref_array_type_indirect
);
2714 index
= get_src(ctx
, deref_array
->indirect
);
2715 stride
= LLVMConstInt(ctx
->ac
.i32
, size
, 0);
2716 local_offset
= LLVMBuildMul(ctx
->ac
.builder
, stride
, index
, "");
2719 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, local_offset
, "");
2721 offset
= local_offset
;
2722 } else if (tail
->deref_type
== nir_deref_type_struct
) {
2723 nir_deref_struct
*deref_struct
= nir_deref_as_struct(tail
);
2725 for (unsigned i
= 0; i
< deref_struct
->index
; i
++) {
2726 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
2727 const_offset
+= glsl_count_attribute_slots(ft
, vs_in
);
2730 unreachable("unsupported deref type");
2734 if (const_offset
&& offset
)
2735 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
2736 LLVMConstInt(ctx
->ac
.i32
, const_offset
, 0),
2739 *const_out
= const_offset
;
2740 *indir_out
= offset
;
2744 /* The offchip buffer layout for TCS->TES is
2746 * - attribute 0 of patch 0 vertex 0
2747 * - attribute 0 of patch 0 vertex 1
2748 * - attribute 0 of patch 0 vertex 2
2750 * - attribute 0 of patch 1 vertex 0
2751 * - attribute 0 of patch 1 vertex 1
2753 * - attribute 1 of patch 0 vertex 0
2754 * - attribute 1 of patch 0 vertex 1
2756 * - per patch attribute 0 of patch 0
2757 * - per patch attribute 0 of patch 1
2760 * Note that every attribute has 4 components.
2762 static LLVMValueRef
get_tcs_tes_buffer_address(struct nir_to_llvm_context
*ctx
,
2763 LLVMValueRef vertex_index
,
2764 LLVMValueRef param_index
)
2766 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
2767 LLVMValueRef param_stride
, constant16
;
2768 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
2770 vertices_per_patch
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 9, 6);
2771 num_patches
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 0, 9);
2772 total_vertices
= LLVMBuildMul(ctx
->builder
, vertices_per_patch
,
2775 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2777 base_addr
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
2778 vertices_per_patch
, "");
2780 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2783 param_stride
= total_vertices
;
2785 base_addr
= rel_patch_id
;
2786 param_stride
= num_patches
;
2789 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2790 LLVMBuildMul(ctx
->builder
, param_index
,
2791 param_stride
, ""), "");
2793 base_addr
= LLVMBuildMul(ctx
->builder
, base_addr
, constant16
, "");
2795 if (!vertex_index
) {
2796 LLVMValueRef patch_data_offset
=
2797 unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 16, 16);
2799 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2800 patch_data_offset
, "");
2805 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct nir_to_llvm_context
*ctx
,
2807 unsigned const_index
,
2809 LLVMValueRef vertex_index
,
2810 LLVMValueRef indir_index
)
2812 LLVMValueRef param_index
;
2815 param_index
= LLVMBuildAdd(ctx
->builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
2818 if (const_index
&& !is_compact
)
2819 param
+= const_index
;
2820 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
2822 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
2826 mark_tess_output(struct nir_to_llvm_context
*ctx
,
2827 bool is_patch
, uint32_t param
)
2831 ctx
->tess_patch_outputs_written
|= (1ull << param
);
2833 ctx
->tess_outputs_written
|= (1ull << param
);
2837 get_dw_address(struct nir_to_llvm_context
*ctx
,
2838 LLVMValueRef dw_addr
,
2840 unsigned const_index
,
2841 bool compact_const_index
,
2842 LLVMValueRef vertex_index
,
2843 LLVMValueRef stride
,
2844 LLVMValueRef indir_index
)
2849 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2850 LLVMBuildMul(ctx
->builder
,
2856 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2857 LLVMBuildMul(ctx
->builder
, indir_index
,
2858 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
2859 else if (const_index
&& !compact_const_index
)
2860 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2861 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2863 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2864 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
2866 if (const_index
&& compact_const_index
)
2867 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2868 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2873 load_tcs_varyings(struct ac_shader_abi
*abi
,
2874 LLVMValueRef vertex_index
,
2875 LLVMValueRef indir_index
,
2876 unsigned const_index
,
2878 unsigned driver_location
,
2880 unsigned num_components
,
2885 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
2886 LLVMValueRef dw_addr
, stride
;
2887 LLVMValueRef value
[4], result
;
2888 unsigned param
= shader_io_get_unique_index(location
);
2891 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 13, 8);
2892 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
2895 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
2896 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2898 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2903 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2906 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
2907 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2908 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2911 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
2916 store_tcs_output(struct ac_shader_abi
*abi
,
2917 LLVMValueRef vertex_index
,
2918 LLVMValueRef param_index
,
2919 unsigned const_index
,
2921 unsigned driver_location
,
2928 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
2929 LLVMValueRef dw_addr
;
2930 LLVMValueRef stride
= NULL
;
2931 LLVMValueRef buf_addr
= NULL
;
2933 bool store_lds
= true;
2936 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
2939 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
2943 param
= shader_io_get_unique_index(location
);
2944 if (location
== VARYING_SLOT_CLIP_DIST0
&&
2945 is_compact
&& const_index
> 3) {
2951 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
2952 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2954 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2957 mark_tess_output(ctx
, is_patch
, param
);
2959 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2961 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
2962 vertex_index
, param_index
);
2964 bool is_tess_factor
= false;
2965 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
2966 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
2967 is_tess_factor
= true;
2969 unsigned base
= is_compact
? const_index
: 0;
2970 for (unsigned chan
= 0; chan
< 8; chan
++) {
2971 if (!(writemask
& (1 << chan
)))
2973 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
2975 if (store_lds
|| is_tess_factor
) {
2976 LLVMValueRef dw_addr_chan
=
2977 LLVMBuildAdd(ctx
->builder
, dw_addr
,
2978 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
2979 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
2982 if (!is_tess_factor
&& writemask
!= 0xF)
2983 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
2984 buf_addr
, ctx
->oc_lds
,
2985 4 * (base
+ chan
), 1, 0, true, false);
2988 if (writemask
== 0xF) {
2989 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
2990 buf_addr
, ctx
->oc_lds
,
2991 (base
* 4), 1, 0, true, false);
2996 load_tes_input(struct ac_shader_abi
*abi
,
2997 LLVMValueRef vertex_index
,
2998 LLVMValueRef param_index
,
2999 unsigned const_index
,
3001 unsigned driver_location
,
3003 unsigned num_components
,
3008 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
3009 LLVMValueRef buf_addr
;
3010 LLVMValueRef result
;
3011 unsigned param
= shader_io_get_unique_index(location
);
3013 if (location
== VARYING_SLOT_CLIP_DIST0
&& is_compact
&& const_index
> 3) {
3018 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
3019 is_compact
, vertex_index
, param_index
);
3021 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
3022 buf_addr
= LLVMBuildAdd(ctx
->builder
, buf_addr
, comp_offset
, "");
3024 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
3025 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
3026 result
= trim_vector(&ctx
->ac
, result
, num_components
);
3031 load_gs_input(struct ac_shader_abi
*abi
,
3033 unsigned driver_location
,
3035 unsigned num_components
,
3036 unsigned vertex_index
,
3037 unsigned const_index
,
3040 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
3041 LLVMValueRef vtx_offset
;
3042 unsigned param
, vtx_offset_param
;
3043 LLVMValueRef value
[4], result
;
3045 vtx_offset_param
= vertex_index
;
3046 assert(vtx_offset_param
< 6);
3047 vtx_offset
= LLVMBuildMul(ctx
->builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
3048 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3050 param
= shader_io_get_unique_index(location
);
3052 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
3053 if (ctx
->ac
.chip_class
>= GFX9
) {
3054 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
3055 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
3056 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
3057 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
3059 LLVMValueRef soffset
=
3060 LLVMConstInt(ctx
->ac
.i32
,
3061 (param
* 4 + i
+ const_index
) * 256,
3064 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
3067 vtx_offset
, soffset
,
3068 0, 1, 0, true, false);
3070 value
[i
] = LLVMBuildBitCast(ctx
->builder
, value
[i
],
3074 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
3075 result
= ac_to_integer(&ctx
->ac
, result
);
3080 build_gep_for_deref(struct ac_nir_context
*ctx
,
3081 nir_deref_var
*deref
)
3083 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->vars
, deref
->var
);
3084 assert(entry
->data
);
3085 LLVMValueRef val
= entry
->data
;
3086 nir_deref
*tail
= deref
->deref
.child
;
3087 while (tail
!= NULL
) {
3088 LLVMValueRef offset
;
3089 switch (tail
->deref_type
) {
3090 case nir_deref_type_array
: {
3091 nir_deref_array
*array
= nir_deref_as_array(tail
);
3092 offset
= LLVMConstInt(ctx
->ac
.i32
, array
->base_offset
, 0);
3093 if (array
->deref_array_type
==
3094 nir_deref_array_type_indirect
) {
3095 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
3102 case nir_deref_type_struct
: {
3103 nir_deref_struct
*deref_struct
=
3104 nir_deref_as_struct(tail
);
3105 offset
= LLVMConstInt(ctx
->ac
.i32
,
3106 deref_struct
->index
, 0);
3110 unreachable("bad deref type");
3112 val
= ac_build_gep0(&ctx
->ac
, val
, offset
);
3118 static LLVMValueRef
load_tess_varyings(struct ac_nir_context
*ctx
,
3119 nir_intrinsic_instr
*instr
,
3122 LLVMValueRef result
;
3123 LLVMValueRef vertex_index
= NULL
;
3124 LLVMValueRef indir_index
= NULL
;
3125 unsigned const_index
= 0;
3126 unsigned location
= instr
->variables
[0]->var
->data
.location
;
3127 unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3128 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3129 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3131 get_deref_offset(ctx
, instr
->variables
[0],
3132 false, NULL
, is_patch
? NULL
: &vertex_index
,
3133 &const_index
, &indir_index
);
3135 result
= ctx
->abi
->load_tess_varyings(ctx
->abi
, vertex_index
, indir_index
,
3136 const_index
, location
, driver_location
,
3137 instr
->variables
[0]->var
->data
.location_frac
,
3138 instr
->num_components
,
3139 is_patch
, is_compact
, load_inputs
);
3140 return LLVMBuildBitCast(ctx
->ac
.builder
, result
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3143 static LLVMValueRef
visit_load_var(struct ac_nir_context
*ctx
,
3144 nir_intrinsic_instr
*instr
)
3146 LLVMValueRef values
[8];
3147 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3148 int ve
= instr
->dest
.ssa
.num_components
;
3149 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3150 LLVMValueRef indir_index
;
3152 unsigned const_index
;
3153 unsigned stride
= instr
->variables
[0]->var
->data
.compact
? 1 : 4;
3154 bool vs_in
= ctx
->stage
== MESA_SHADER_VERTEX
&&
3155 instr
->variables
[0]->var
->data
.mode
== nir_var_shader_in
;
3156 get_deref_offset(ctx
, instr
->variables
[0], vs_in
, NULL
, NULL
,
3157 &const_index
, &indir_index
);
3159 if (instr
->dest
.ssa
.bit_size
== 64)
3162 switch (instr
->variables
[0]->var
->data
.mode
) {
3163 case nir_var_shader_in
:
3164 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3165 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3166 return load_tess_varyings(ctx
, instr
, true);
3169 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3170 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, instr
->dest
.ssa
.bit_size
);
3171 LLVMValueRef indir_index
;
3172 unsigned const_index
, vertex_index
;
3173 get_deref_offset(ctx
, instr
->variables
[0],
3174 false, &vertex_index
, NULL
,
3175 &const_index
, &indir_index
);
3177 return ctx
->abi
->load_inputs(ctx
->abi
, instr
->variables
[0]->var
->data
.location
,
3178 instr
->variables
[0]->var
->data
.driver_location
,
3179 instr
->variables
[0]->var
->data
.location_frac
, ve
,
3180 vertex_index
, const_index
, type
);
3183 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3185 unsigned count
= glsl_count_attribute_slots(
3186 instr
->variables
[0]->var
->type
,
3187 ctx
->stage
== MESA_SHADER_VERTEX
);
3189 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3190 &ctx
->ac
, ctx
->abi
->inputs
+ idx
+ chan
, count
,
3191 stride
, false, true);
3193 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3197 values
[chan
] = ctx
->abi
->inputs
[idx
+ chan
+ const_index
* stride
];
3201 for (unsigned chan
= 0; chan
< ve
; chan
++) {
3203 unsigned count
= glsl_count_attribute_slots(
3204 instr
->variables
[0]->var
->type
, false);
3206 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3207 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3208 stride
, true, true);
3210 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3214 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, ctx
->locals
[idx
+ chan
+ const_index
* stride
], "");
3218 case nir_var_shared
: {
3219 LLVMValueRef address
= build_gep_for_deref(ctx
,
3220 instr
->variables
[0]);
3221 LLVMValueRef val
= LLVMBuildLoad(ctx
->ac
.builder
, address
, "");
3222 return LLVMBuildBitCast(ctx
->ac
.builder
, val
,
3223 get_def_type(ctx
, &instr
->dest
.ssa
),
3226 case nir_var_shader_out
:
3227 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3228 return load_tess_varyings(ctx
, instr
, false);
3231 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3233 unsigned count
= glsl_count_attribute_slots(
3234 instr
->variables
[0]->var
->type
, false);
3236 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3237 &ctx
->ac
, ctx
->outputs
+ idx
+ chan
, count
,
3238 stride
, true, true);
3240 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3244 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
,
3245 ctx
->outputs
[idx
+ chan
+ const_index
* stride
],
3251 unreachable("unhandle variable mode");
3253 ret
= ac_build_varying_gather_values(&ctx
->ac
, values
, ve
, comp
);
3254 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3258 visit_store_var(struct ac_nir_context
*ctx
,
3259 nir_intrinsic_instr
*instr
)
3261 LLVMValueRef temp_ptr
, value
;
3262 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3263 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3264 LLVMValueRef src
= ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
3265 int writemask
= instr
->const_index
[0] << comp
;
3266 LLVMValueRef indir_index
;
3267 unsigned const_index
;
3268 get_deref_offset(ctx
, instr
->variables
[0], false,
3269 NULL
, NULL
, &const_index
, &indir_index
);
3271 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
)) == 64) {
3273 src
= LLVMBuildBitCast(ctx
->ac
.builder
, src
,
3274 LLVMVectorType(ctx
->ac
.f32
, ac_get_llvm_num_components(src
) * 2),
3277 writemask
= widen_mask(writemask
, 2);
3280 switch (instr
->variables
[0]->var
->data
.mode
) {
3281 case nir_var_shader_out
:
3283 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3284 LLVMValueRef vertex_index
= NULL
;
3285 LLVMValueRef indir_index
= NULL
;
3286 unsigned const_index
= 0;
3287 const unsigned location
= instr
->variables
[0]->var
->data
.location
;
3288 const unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3289 const unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3290 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3291 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3293 get_deref_offset(ctx
, instr
->variables
[0],
3294 false, NULL
, is_patch
? NULL
: &vertex_index
,
3295 &const_index
, &indir_index
);
3297 ctx
->abi
->store_tcs_outputs(ctx
->abi
, vertex_index
, indir_index
,
3298 const_index
, location
, driver_location
,
3299 src
, comp
, is_patch
, is_compact
, writemask
);
3303 for (unsigned chan
= 0; chan
< 8; chan
++) {
3305 if (!(writemask
& (1 << chan
)))
3308 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- comp
);
3310 if (instr
->variables
[0]->var
->data
.compact
)
3313 unsigned count
= glsl_count_attribute_slots(
3314 instr
->variables
[0]->var
->type
, false);
3316 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3317 &ctx
->ac
, ctx
->outputs
+ idx
+ chan
, count
,
3318 stride
, true, true);
3320 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3321 value
, indir_index
, "");
3322 build_store_values_extended(&ctx
->ac
, ctx
->outputs
+ idx
+ chan
,
3323 count
, stride
, tmp_vec
);
3326 temp_ptr
= ctx
->outputs
[idx
+ chan
+ const_index
* stride
];
3328 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3333 for (unsigned chan
= 0; chan
< 8; chan
++) {
3334 if (!(writemask
& (1 << chan
)))
3337 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
);
3339 unsigned count
= glsl_count_attribute_slots(
3340 instr
->variables
[0]->var
->type
, false);
3342 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3343 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3346 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3347 value
, indir_index
, "");
3348 build_store_values_extended(&ctx
->ac
, ctx
->locals
+ idx
+ chan
,
3351 temp_ptr
= ctx
->locals
[idx
+ chan
+ const_index
* 4];
3353 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3357 case nir_var_shared
: {
3358 int writemask
= instr
->const_index
[0];
3359 LLVMValueRef address
= build_gep_for_deref(ctx
,
3360 instr
->variables
[0]);
3361 LLVMValueRef val
= get_src(ctx
, instr
->src
[0]);
3362 unsigned components
=
3363 glsl_get_vector_elements(
3364 nir_deref_tail(&instr
->variables
[0]->deref
)->type
);
3365 if (writemask
== (1 << components
) - 1) {
3366 val
= LLVMBuildBitCast(
3367 ctx
->ac
.builder
, val
,
3368 LLVMGetElementType(LLVMTypeOf(address
)), "");
3369 LLVMBuildStore(ctx
->ac
.builder
, val
, address
);
3371 for (unsigned chan
= 0; chan
< 4; chan
++) {
3372 if (!(writemask
& (1 << chan
)))
3375 LLVMBuildStructGEP(ctx
->ac
.builder
,
3377 LLVMValueRef src
= ac_llvm_extract_elem(&ctx
->ac
, val
,
3379 src
= LLVMBuildBitCast(
3380 ctx
->ac
.builder
, src
,
3381 LLVMGetElementType(LLVMTypeOf(ptr
)), "");
3382 LLVMBuildStore(ctx
->ac
.builder
, src
, ptr
);
3392 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
3395 case GLSL_SAMPLER_DIM_BUF
:
3397 case GLSL_SAMPLER_DIM_1D
:
3398 return array
? 2 : 1;
3399 case GLSL_SAMPLER_DIM_2D
:
3400 return array
? 3 : 2;
3401 case GLSL_SAMPLER_DIM_MS
:
3402 return array
? 4 : 3;
3403 case GLSL_SAMPLER_DIM_3D
:
3404 case GLSL_SAMPLER_DIM_CUBE
:
3406 case GLSL_SAMPLER_DIM_RECT
:
3407 case GLSL_SAMPLER_DIM_SUBPASS
:
3409 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
3419 /* Adjust the sample index according to FMASK.
3421 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3422 * which is the identity mapping. Each nibble says which physical sample
3423 * should be fetched to get that sample.
3425 * For example, 0x11111100 means there are only 2 samples stored and
3426 * the second sample covers 3/4 of the pixel. When reading samples 0
3427 * and 1, return physical sample 0 (determined by the first two 0s
3428 * in FMASK), otherwise return physical sample 1.
3430 * The sample index should be adjusted as follows:
3431 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3433 static LLVMValueRef
adjust_sample_index_using_fmask(struct ac_llvm_context
*ctx
,
3434 LLVMValueRef coord_x
, LLVMValueRef coord_y
,
3435 LLVMValueRef coord_z
,
3436 LLVMValueRef sample_index
,
3437 LLVMValueRef fmask_desc_ptr
)
3439 LLVMValueRef fmask_load_address
[4];
3442 fmask_load_address
[0] = coord_x
;
3443 fmask_load_address
[1] = coord_y
;
3445 fmask_load_address
[2] = coord_z
;
3446 fmask_load_address
[3] = LLVMGetUndef(ctx
->i32
);
3449 struct ac_image_args args
= {0};
3451 args
.opcode
= ac_image_load
;
3452 args
.da
= coord_z
? true : false;
3453 args
.resource
= fmask_desc_ptr
;
3455 args
.addr
= ac_build_gather_values(ctx
, fmask_load_address
, coord_z
? 4 : 2);
3457 res
= ac_build_image_opcode(ctx
, &args
);
3459 res
= ac_to_integer(ctx
, res
);
3460 LLVMValueRef four
= LLVMConstInt(ctx
->i32
, 4, false);
3461 LLVMValueRef F
= LLVMConstInt(ctx
->i32
, 0xf, false);
3463 LLVMValueRef fmask
= LLVMBuildExtractElement(ctx
->builder
,
3467 LLVMValueRef sample_index4
=
3468 LLVMBuildMul(ctx
->builder
, sample_index
, four
, "");
3469 LLVMValueRef shifted_fmask
=
3470 LLVMBuildLShr(ctx
->builder
, fmask
, sample_index4
, "");
3471 LLVMValueRef final_sample
=
3472 LLVMBuildAnd(ctx
->builder
, shifted_fmask
, F
, "");
3474 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3475 * resource descriptor is 0 (invalid),
3477 LLVMValueRef fmask_desc
=
3478 LLVMBuildBitCast(ctx
->builder
, fmask_desc_ptr
,
3481 LLVMValueRef fmask_word1
=
3482 LLVMBuildExtractElement(ctx
->builder
, fmask_desc
,
3485 LLVMValueRef word1_is_nonzero
=
3486 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
,
3487 fmask_word1
, ctx
->i32_0
, "");
3489 /* Replace the MSAA sample index. */
3491 LLVMBuildSelect(ctx
->builder
, word1_is_nonzero
,
3492 final_sample
, sample_index
, "");
3493 return sample_index
;
3496 static LLVMValueRef
get_image_coords(struct ac_nir_context
*ctx
,
3497 const nir_intrinsic_instr
*instr
)
3499 const struct glsl_type
*type
= glsl_without_array(instr
->variables
[0]->var
->type
);
3501 LLVMValueRef src0
= get_src(ctx
, instr
->src
[0]);
3502 LLVMValueRef coords
[4];
3503 LLVMValueRef masks
[] = {
3504 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
3505 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
3508 LLVMValueRef sample_index
= ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[1]), 0);
3511 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3512 bool is_array
= glsl_sampler_type_is_array(type
);
3513 bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3514 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3515 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
||
3516 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3517 bool gfx9_1d
= ctx
->ac
.chip_class
>= GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
3518 count
= image_type_to_components_count(dim
, is_array
);
3521 LLVMValueRef fmask_load_address
[3];
3524 fmask_load_address
[0] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3525 fmask_load_address
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[1], "");
3527 fmask_load_address
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[2], "");
3529 fmask_load_address
[2] = NULL
;
3531 for (chan
= 0; chan
< 2; ++chan
)
3532 fmask_load_address
[chan
] =
3533 LLVMBuildAdd(ctx
->ac
.builder
, fmask_load_address
[chan
],
3534 LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3535 ctx
->ac
.i32
, ""), "");
3536 fmask_load_address
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3538 sample_index
= adjust_sample_index_using_fmask(&ctx
->ac
,
3539 fmask_load_address
[0],
3540 fmask_load_address
[1],
3541 fmask_load_address
[2],
3543 get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_FMASK
, NULL
, true, false));
3545 if (count
== 1 && !gfx9_1d
) {
3546 if (instr
->src
[0].ssa
->num_components
)
3547 res
= LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3554 for (chan
= 0; chan
< count
; ++chan
) {
3555 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, src0
, chan
);
3558 for (chan
= 0; chan
< 2; ++chan
)
3559 coords
[chan
] = LLVMBuildAdd(ctx
->ac
.builder
, coords
[chan
], LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3560 ctx
->ac
.i32
, ""), "");
3561 coords
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3567 coords
[2] = coords
[1];
3568 coords
[1] = ctx
->ac
.i32_0
;
3570 coords
[1] = ctx
->ac
.i32_0
;
3575 coords
[count
] = sample_index
;
3580 coords
[3] = LLVMGetUndef(ctx
->ac
.i32
);
3583 res
= ac_build_gather_values(&ctx
->ac
, coords
, count
);
3588 static LLVMValueRef
visit_image_load(struct ac_nir_context
*ctx
,
3589 const nir_intrinsic_instr
*instr
)
3591 LLVMValueRef params
[7];
3593 char intrinsic_name
[64];
3594 const nir_variable
*var
= instr
->variables
[0]->var
;
3595 const struct glsl_type
*type
= var
->type
;
3597 if(instr
->variables
[0]->deref
.child
)
3598 type
= instr
->variables
[0]->deref
.child
->type
;
3600 type
= glsl_without_array(type
);
3602 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3603 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
3604 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
3605 unsigned num_channels
= util_last_bit(mask
);
3606 LLVMValueRef rsrc
, vindex
;
3608 rsrc
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, false);
3609 vindex
= LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3612 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3613 res
= ac_build_buffer_load_format(&ctx
->ac
, rsrc
, vindex
,
3614 ctx
->ac
.i32_0
, num_channels
,
3616 res
= ac_build_expand_to_vec4(&ctx
->ac
, res
, num_channels
);
3618 res
= trim_vector(&ctx
->ac
, res
, instr
->dest
.ssa
.num_components
);
3619 res
= ac_to_integer(&ctx
->ac
, res
);
3621 bool is_da
= glsl_sampler_type_is_array(type
) ||
3622 dim
== GLSL_SAMPLER_DIM_CUBE
||
3623 dim
== GLSL_SAMPLER_DIM_3D
||
3624 dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3625 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
;
3626 LLVMValueRef da
= is_da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3627 LLVMValueRef glc
= ctx
->ac
.i1false
;
3628 LLVMValueRef slc
= ctx
->ac
.i1false
;
3630 params
[0] = get_image_coords(ctx
, instr
);
3631 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3632 params
[2] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3635 params
[5] = ctx
->ac
.i1false
;
3638 ac_get_image_intr_name("llvm.amdgcn.image.load",
3639 ctx
->ac
.v4f32
, /* vdata */
3640 LLVMTypeOf(params
[0]), /* coords */
3641 LLVMTypeOf(params
[1]), /* rsrc */
3642 intrinsic_name
, sizeof(intrinsic_name
));
3644 res
= ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.v4f32
,
3645 params
, 7, AC_FUNC_ATTR_READONLY
);
3647 return ac_to_integer(&ctx
->ac
, res
);
3650 static void visit_image_store(struct ac_nir_context
*ctx
,
3651 nir_intrinsic_instr
*instr
)
3653 LLVMValueRef params
[8];
3654 char intrinsic_name
[64];
3655 const nir_variable
*var
= instr
->variables
[0]->var
;
3656 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3657 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3658 LLVMValueRef glc
= ctx
->ac
.i1false
;
3659 bool force_glc
= ctx
->ac
.chip_class
== SI
;
3661 glc
= ctx
->ac
.i1true
;
3663 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
3664 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2])); /* data */
3665 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, true);
3666 params
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3667 ctx
->ac
.i32_0
, ""); /* vindex */
3668 params
[3] = ctx
->ac
.i32_0
; /* voffset */
3669 params
[4] = glc
; /* glc */
3670 params
[5] = ctx
->ac
.i1false
; /* slc */
3671 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.store.format.v4f32", ctx
->ac
.voidt
,
3674 bool is_da
= glsl_sampler_type_is_array(type
) ||
3675 dim
== GLSL_SAMPLER_DIM_CUBE
||
3676 dim
== GLSL_SAMPLER_DIM_3D
;
3677 LLVMValueRef da
= is_da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3678 LLVMValueRef slc
= ctx
->ac
.i1false
;
3680 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2]));
3681 params
[1] = get_image_coords(ctx
, instr
); /* coords */
3682 params
[2] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, true);
3683 params
[3] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3686 params
[6] = ctx
->ac
.i1false
;
3689 ac_get_image_intr_name("llvm.amdgcn.image.store",
3690 LLVMTypeOf(params
[0]), /* vdata */
3691 LLVMTypeOf(params
[1]), /* coords */
3692 LLVMTypeOf(params
[2]), /* rsrc */
3693 intrinsic_name
, sizeof(intrinsic_name
));
3695 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.voidt
,
3701 static LLVMValueRef
visit_image_atomic(struct ac_nir_context
*ctx
,
3702 const nir_intrinsic_instr
*instr
)
3704 LLVMValueRef params
[7];
3705 int param_count
= 0;
3706 const nir_variable
*var
= instr
->variables
[0]->var
;
3708 const char *atomic_name
;
3709 char intrinsic_name
[41];
3710 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3711 MAYBE_UNUSED
int length
;
3713 bool is_unsigned
= glsl_get_sampler_result_type(type
) == GLSL_TYPE_UINT
;
3715 switch (instr
->intrinsic
) {
3716 case nir_intrinsic_image_atomic_add
:
3717 atomic_name
= "add";
3719 case nir_intrinsic_image_atomic_min
:
3720 atomic_name
= is_unsigned
? "umin" : "smin";
3722 case nir_intrinsic_image_atomic_max
:
3723 atomic_name
= is_unsigned
? "umax" : "smax";
3725 case nir_intrinsic_image_atomic_and
:
3726 atomic_name
= "and";
3728 case nir_intrinsic_image_atomic_or
:
3731 case nir_intrinsic_image_atomic_xor
:
3732 atomic_name
= "xor";
3734 case nir_intrinsic_image_atomic_exchange
:
3735 atomic_name
= "swap";
3737 case nir_intrinsic_image_atomic_comp_swap
:
3738 atomic_name
= "cmpswap";
3744 if (instr
->intrinsic
== nir_intrinsic_image_atomic_comp_swap
)
3745 params
[param_count
++] = get_src(ctx
, instr
->src
[3]);
3746 params
[param_count
++] = get_src(ctx
, instr
->src
[2]);
3748 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3749 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
,
3751 params
[param_count
++] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3752 ctx
->ac
.i32_0
, ""); /* vindex */
3753 params
[param_count
++] = ctx
->ac
.i32_0
; /* voffset */
3754 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3756 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3757 "llvm.amdgcn.buffer.atomic.%s", atomic_name
);
3759 char coords_type
[8];
3761 bool da
= glsl_sampler_type_is_array(type
) ||
3762 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
;
3764 LLVMValueRef coords
= params
[param_count
++] = get_image_coords(ctx
, instr
);
3765 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
,
3767 params
[param_count
++] = ctx
->ac
.i1false
; /* r128 */
3768 params
[param_count
++] = da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
; /* da */
3769 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3771 build_int_type_name(LLVMTypeOf(coords
),
3772 coords_type
, sizeof(coords_type
));
3774 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3775 "llvm.amdgcn.image.atomic.%s.%s", atomic_name
, coords_type
);
3778 assert(length
< sizeof(intrinsic_name
));
3779 return ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.i32
, params
, param_count
, 0);
3782 static LLVMValueRef
visit_image_size(struct ac_nir_context
*ctx
,
3783 const nir_intrinsic_instr
*instr
)
3786 const nir_variable
*var
= instr
->variables
[0]->var
;
3787 const struct glsl_type
*type
= instr
->variables
[0]->var
->type
;
3788 bool da
= glsl_sampler_type_is_array(var
->type
) ||
3789 glsl_get_sampler_dim(var
->type
) == GLSL_SAMPLER_DIM_CUBE
||
3790 glsl_get_sampler_dim(var
->type
) == GLSL_SAMPLER_DIM_3D
;
3791 if(instr
->variables
[0]->deref
.child
)
3792 type
= instr
->variables
[0]->deref
.child
->type
;
3794 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
)
3795 return get_buffer_size(ctx
,
3796 get_sampler_desc(ctx
, instr
->variables
[0],
3797 AC_DESC_BUFFER
, NULL
, true, false), true);
3799 struct ac_image_args args
= { 0 };
3803 args
.resource
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3804 args
.opcode
= ac_image_get_resinfo
;
3805 args
.addr
= ctx
->ac
.i32_0
;
3807 res
= ac_build_image_opcode(&ctx
->ac
, &args
);
3809 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
3811 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
3812 glsl_sampler_type_is_array(type
)) {
3813 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
3814 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3815 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
3816 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, z
, two
, "");
3818 if (ctx
->ac
.chip_class
>= GFX9
&&
3819 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
3820 glsl_sampler_type_is_array(type
)) {
3821 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3822 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, layers
,
3829 #define NOOP_WAITCNT 0xf7f
3830 #define LGKM_CNT 0x07f
3831 #define VM_CNT 0xf70
3833 static void emit_membar(struct nir_to_llvm_context
*ctx
,
3834 const nir_intrinsic_instr
*instr
)
3836 unsigned waitcnt
= NOOP_WAITCNT
;
3838 switch (instr
->intrinsic
) {
3839 case nir_intrinsic_memory_barrier
:
3840 case nir_intrinsic_group_memory_barrier
:
3841 waitcnt
&= VM_CNT
& LGKM_CNT
;
3843 case nir_intrinsic_memory_barrier_atomic_counter
:
3844 case nir_intrinsic_memory_barrier_buffer
:
3845 case nir_intrinsic_memory_barrier_image
:
3848 case nir_intrinsic_memory_barrier_shared
:
3849 waitcnt
&= LGKM_CNT
;
3854 if (waitcnt
!= NOOP_WAITCNT
)
3855 ac_build_waitcnt(&ctx
->ac
, waitcnt
);
3858 static void emit_barrier(struct ac_llvm_context
*ac
, gl_shader_stage stage
)
3860 /* SI only (thanks to a hw bug workaround):
3861 * The real barrier instruction isn’t needed, because an entire patch
3862 * always fits into a single wave.
3864 if (ac
->chip_class
== SI
&& stage
== MESA_SHADER_TESS_CTRL
) {
3865 ac_build_waitcnt(ac
, LGKM_CNT
& VM_CNT
);
3868 ac_build_intrinsic(ac
, "llvm.amdgcn.s.barrier",
3869 ac
->voidt
, NULL
, 0, AC_FUNC_ATTR_CONVERGENT
);
3872 static void emit_discard(struct ac_nir_context
*ctx
,
3873 const nir_intrinsic_instr
*instr
)
3877 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3878 cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3879 get_src(ctx
, instr
->src
[0]),
3882 assert(instr
->intrinsic
== nir_intrinsic_discard
);
3883 cond
= LLVMConstInt(ctx
->ac
.i1
, false, 0);
3886 ac_build_kill_if_false(&ctx
->ac
, cond
);
3890 visit_load_helper_invocation(struct ac_nir_context
*ctx
)
3892 LLVMValueRef result
= ac_build_intrinsic(&ctx
->ac
,
3893 "llvm.amdgcn.ps.live",
3894 ctx
->ac
.i1
, NULL
, 0,
3895 AC_FUNC_ATTR_READNONE
);
3896 result
= LLVMBuildNot(ctx
->ac
.builder
, result
, "");
3897 return LLVMBuildSExt(ctx
->ac
.builder
, result
, ctx
->ac
.i32
, "");
3901 visit_load_local_invocation_index(struct nir_to_llvm_context
*ctx
)
3903 LLVMValueRef result
;
3904 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
->ac
);
3905 result
= LLVMBuildAnd(ctx
->builder
, ctx
->tg_size
,
3906 LLVMConstInt(ctx
->ac
.i32
, 0xfc0, false), "");
3908 return LLVMBuildAdd(ctx
->builder
, result
, thread_id
, "");
3911 static LLVMValueRef
visit_var_atomic(struct nir_to_llvm_context
*ctx
,
3912 const nir_intrinsic_instr
*instr
)
3914 LLVMValueRef ptr
, result
;
3915 LLVMValueRef src
= get_src(ctx
->nir
, instr
->src
[0]);
3916 ptr
= build_gep_for_deref(ctx
->nir
, instr
->variables
[0]);
3918 if (instr
->intrinsic
== nir_intrinsic_var_atomic_comp_swap
) {
3919 LLVMValueRef src1
= get_src(ctx
->nir
, instr
->src
[1]);
3920 result
= LLVMBuildAtomicCmpXchg(ctx
->builder
,
3922 LLVMAtomicOrderingSequentiallyConsistent
,
3923 LLVMAtomicOrderingSequentiallyConsistent
,
3926 LLVMAtomicRMWBinOp op
;
3927 switch (instr
->intrinsic
) {
3928 case nir_intrinsic_var_atomic_add
:
3929 op
= LLVMAtomicRMWBinOpAdd
;
3931 case nir_intrinsic_var_atomic_umin
:
3932 op
= LLVMAtomicRMWBinOpUMin
;
3934 case nir_intrinsic_var_atomic_umax
:
3935 op
= LLVMAtomicRMWBinOpUMax
;
3937 case nir_intrinsic_var_atomic_imin
:
3938 op
= LLVMAtomicRMWBinOpMin
;
3940 case nir_intrinsic_var_atomic_imax
:
3941 op
= LLVMAtomicRMWBinOpMax
;
3943 case nir_intrinsic_var_atomic_and
:
3944 op
= LLVMAtomicRMWBinOpAnd
;
3946 case nir_intrinsic_var_atomic_or
:
3947 op
= LLVMAtomicRMWBinOpOr
;
3949 case nir_intrinsic_var_atomic_xor
:
3950 op
= LLVMAtomicRMWBinOpXor
;
3952 case nir_intrinsic_var_atomic_exchange
:
3953 op
= LLVMAtomicRMWBinOpXchg
;
3959 result
= LLVMBuildAtomicRMW(ctx
->builder
, op
, ptr
, ac_to_integer(&ctx
->ac
, src
),
3960 LLVMAtomicOrderingSequentiallyConsistent
,
3966 static LLVMValueRef
lookup_interp_param(struct ac_shader_abi
*abi
,
3967 enum glsl_interp_mode interp
, unsigned location
)
3969 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
3972 case INTERP_MODE_FLAT
:
3975 case INTERP_MODE_SMOOTH
:
3976 case INTERP_MODE_NONE
:
3977 if (location
== INTERP_CENTER
)
3978 return ctx
->persp_center
;
3979 else if (location
== INTERP_CENTROID
)
3980 return ctx
->persp_centroid
;
3981 else if (location
== INTERP_SAMPLE
)
3982 return ctx
->persp_sample
;
3984 case INTERP_MODE_NOPERSPECTIVE
:
3985 if (location
== INTERP_CENTER
)
3986 return ctx
->linear_center
;
3987 else if (location
== INTERP_CENTROID
)
3988 return ctx
->linear_centroid
;
3989 else if (location
== INTERP_SAMPLE
)
3990 return ctx
->linear_sample
;
3996 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
3997 LLVMValueRef sample_id
)
3999 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4001 LLVMValueRef result
;
4002 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false));
4004 ptr
= LLVMBuildBitCast(ctx
->builder
, ptr
,
4005 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
4007 sample_id
= LLVMBuildAdd(ctx
->builder
, sample_id
, ctx
->sample_pos_offset
, "");
4008 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
4013 static LLVMValueRef
load_sample_pos(struct ac_nir_context
*ctx
)
4015 LLVMValueRef values
[2];
4017 values
[0] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[0], 32);
4018 values
[1] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[1], 32);
4019 return ac_build_gather_values(&ctx
->ac
, values
, 2);
4022 static LLVMValueRef
load_sample_mask_in(struct ac_nir_context
*ctx
)
4024 uint8_t log2_ps_iter_samples
= ctx
->nctx
->shader_info
->info
.ps
.force_persample
? ctx
->nctx
->options
->key
.fs
.log2_num_samples
: ctx
->nctx
->options
->key
.fs
.log2_ps_iter_samples
;
4026 /* The bit pattern matches that used by fixed function fragment
4028 static const uint16_t ps_iter_masks
[] = {
4029 0xffff, /* not used */
4035 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
4037 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
4039 LLVMValueRef result
, sample_id
;
4040 sample_id
= unpack_param(&ctx
->ac
, ctx
->abi
->ancillary
, 8, 4);
4041 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
4042 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, ctx
->abi
->sample_coverage
, "");
4046 static LLVMValueRef
visit_interp(struct ac_nir_context
*ctx
,
4047 const nir_intrinsic_instr
*instr
)
4049 LLVMValueRef result
[4];
4050 LLVMValueRef interp_param
, attr_number
;
4053 LLVMValueRef src_c0
= NULL
;
4054 LLVMValueRef src_c1
= NULL
;
4055 LLVMValueRef src0
= NULL
;
4056 int input_index
= instr
->variables
[0]->var
->data
.location
- VARYING_SLOT_VAR0
;
4057 switch (instr
->intrinsic
) {
4058 case nir_intrinsic_interp_var_at_centroid
:
4059 location
= INTERP_CENTROID
;
4061 case nir_intrinsic_interp_var_at_sample
:
4062 case nir_intrinsic_interp_var_at_offset
:
4063 location
= INTERP_CENTER
;
4064 src0
= get_src(ctx
, instr
->src
[0]);
4070 if (instr
->intrinsic
== nir_intrinsic_interp_var_at_offset
) {
4071 src_c0
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, ctx
->ac
.i32_0
, ""));
4072 src_c1
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, ctx
->ac
.i32_1
, ""));
4073 } else if (instr
->intrinsic
== nir_intrinsic_interp_var_at_sample
) {
4074 LLVMValueRef sample_position
;
4075 LLVMValueRef halfval
= LLVMConstReal(ctx
->ac
.f32
, 0.5f
);
4077 /* fetch sample ID */
4078 sample_position
= ctx
->abi
->load_sample_position(ctx
->abi
, src0
);
4080 src_c0
= LLVMBuildExtractElement(ctx
->ac
.builder
, sample_position
, ctx
->ac
.i32_0
, "");
4081 src_c0
= LLVMBuildFSub(ctx
->ac
.builder
, src_c0
, halfval
, "");
4082 src_c1
= LLVMBuildExtractElement(ctx
->ac
.builder
, sample_position
, ctx
->ac
.i32_1
, "");
4083 src_c1
= LLVMBuildFSub(ctx
->ac
.builder
, src_c1
, halfval
, "");
4085 interp_param
= ctx
->abi
->lookup_interp_param(ctx
->abi
, instr
->variables
[0]->var
->data
.interpolation
, location
);
4086 attr_number
= LLVMConstInt(ctx
->ac
.i32
, input_index
, false);
4088 if (location
== INTERP_CENTER
) {
4089 LLVMValueRef ij_out
[2];
4090 LLVMValueRef ddxy_out
= emit_ddxy_interp(ctx
, interp_param
);
4093 * take the I then J parameters, and the DDX/Y for it, and
4094 * calculate the IJ inputs for the interpolator.
4095 * temp1 = ddx * offset/sample.x + I;
4096 * interp_param.I = ddy * offset/sample.y + temp1;
4097 * temp1 = ddx * offset/sample.x + J;
4098 * interp_param.J = ddy * offset/sample.y + temp1;
4100 for (unsigned i
= 0; i
< 2; i
++) {
4101 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->ac
.i32
, i
, false);
4102 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->ac
.i32
, i
+ 2, false);
4103 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4104 ddxy_out
, ix_ll
, "");
4105 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4106 ddxy_out
, iy_ll
, "");
4107 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4108 interp_param
, ix_ll
, "");
4109 LLVMValueRef temp1
, temp2
;
4111 interp_el
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_el
,
4114 temp1
= LLVMBuildFMul(ctx
->ac
.builder
, ddx_el
, src_c0
, "");
4115 temp1
= LLVMBuildFAdd(ctx
->ac
.builder
, temp1
, interp_el
, "");
4117 temp2
= LLVMBuildFMul(ctx
->ac
.builder
, ddy_el
, src_c1
, "");
4118 temp2
= LLVMBuildFAdd(ctx
->ac
.builder
, temp2
, temp1
, "");
4120 ij_out
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
,
4121 temp2
, ctx
->ac
.i32
, "");
4123 interp_param
= ac_build_gather_values(&ctx
->ac
, ij_out
, 2);
4127 for (chan
= 0; chan
< 4; chan
++) {
4128 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
4131 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
,
4132 interp_param
, ctx
->ac
.v2f32
, "");
4133 LLVMValueRef i
= LLVMBuildExtractElement(
4134 ctx
->ac
.builder
, interp_param
, ctx
->ac
.i32_0
, "");
4135 LLVMValueRef j
= LLVMBuildExtractElement(
4136 ctx
->ac
.builder
, interp_param
, ctx
->ac
.i32_1
, "");
4138 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
4139 llvm_chan
, attr_number
,
4140 ctx
->abi
->prim_mask
, i
, j
);
4142 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
4143 LLVMConstInt(ctx
->ac
.i32
, 2, false),
4144 llvm_chan
, attr_number
,
4145 ctx
->abi
->prim_mask
);
4148 return ac_build_varying_gather_values(&ctx
->ac
, result
, instr
->num_components
,
4149 instr
->variables
[0]->var
->data
.location_frac
);
4153 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
4155 LLVMValueRef gs_next_vertex
;
4156 LLVMValueRef can_emit
;
4158 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4160 assert(stream
== 0);
4162 /* Write vertex attribute values to GSVS ring */
4163 gs_next_vertex
= LLVMBuildLoad(ctx
->builder
,
4164 ctx
->gs_next_vertex
,
4167 /* If this thread has already emitted the declared maximum number of
4168 * vertices, kill it: excessive vertex emissions are not supposed to
4169 * have any effect, and GS threads have no externally observable
4170 * effects other than emitting vertices.
4172 can_emit
= LLVMBuildICmp(ctx
->builder
, LLVMIntULT
, gs_next_vertex
,
4173 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
4174 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
4176 /* loop num outputs */
4178 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
4179 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
4184 if (!(ctx
->output_mask
& (1ull << i
)))
4187 if (i
== VARYING_SLOT_CLIP_DIST0
) {
4188 /* pack clip and cull into a single set of slots */
4189 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
4193 for (unsigned j
= 0; j
< length
; j
++) {
4194 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
,
4196 LLVMValueRef voffset
= LLVMConstInt(ctx
->ac
.i32
, (slot
* 4 + j
) * ctx
->gs_max_out_vertices
, false);
4197 voffset
= LLVMBuildAdd(ctx
->builder
, voffset
, gs_next_vertex
, "");
4198 voffset
= LLVMBuildMul(ctx
->builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4200 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->ac
.i32
, "");
4202 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->gsvs_ring
,
4204 voffset
, ctx
->gs2vs_offset
, 0,
4210 gs_next_vertex
= LLVMBuildAdd(ctx
->builder
, gs_next_vertex
,
4212 LLVMBuildStore(ctx
->builder
, gs_next_vertex
, ctx
->gs_next_vertex
);
4214 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
4218 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
4220 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4221 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
4225 load_tess_coord(struct ac_shader_abi
*abi
, LLVMTypeRef type
,
4226 unsigned num_components
)
4228 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4230 LLVMValueRef coord
[4] = {
4237 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
4238 coord
[2] = LLVMBuildFSub(ctx
->builder
, ctx
->ac
.f32_1
,
4239 LLVMBuildFAdd(ctx
->builder
, coord
[0], coord
[1], ""), "");
4241 LLVMValueRef result
= ac_build_gather_values(&ctx
->ac
, coord
, num_components
);
4242 return LLVMBuildBitCast(ctx
->builder
, result
, type
, "");
4246 load_patch_vertices_in(struct ac_shader_abi
*abi
)
4248 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4249 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
4252 static void visit_intrinsic(struct ac_nir_context
*ctx
,
4253 nir_intrinsic_instr
*instr
)
4255 LLVMValueRef result
= NULL
;
4257 switch (instr
->intrinsic
) {
4258 case nir_intrinsic_ballot
:
4259 result
= ac_build_ballot(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4261 case nir_intrinsic_read_invocation
:
4262 case nir_intrinsic_read_first_invocation
: {
4263 LLVMValueRef args
[2];
4266 args
[0] = get_src(ctx
, instr
->src
[0]);
4269 const char *intr_name
;
4270 if (instr
->intrinsic
== nir_intrinsic_read_invocation
) {
4272 intr_name
= "llvm.amdgcn.readlane";
4275 args
[1] = get_src(ctx
, instr
->src
[1]);
4278 intr_name
= "llvm.amdgcn.readfirstlane";
4281 /* We currently have no other way to prevent LLVM from lifting the icmp
4282 * calls to a dominating basic block.
4284 ac_build_optimization_barrier(&ctx
->ac
, &args
[0]);
4286 result
= ac_build_intrinsic(&ctx
->ac
, intr_name
,
4287 ctx
->ac
.i32
, args
, num_args
,
4288 AC_FUNC_ATTR_READNONE
|
4289 AC_FUNC_ATTR_CONVERGENT
);
4292 case nir_intrinsic_load_subgroup_invocation
:
4293 result
= ac_get_thread_id(&ctx
->ac
);
4295 case nir_intrinsic_load_work_group_id
: {
4296 LLVMValueRef values
[3];
4298 for (int i
= 0; i
< 3; i
++) {
4299 values
[i
] = ctx
->abi
->workgroup_ids
[i
] ?
4300 ctx
->abi
->workgroup_ids
[i
] : ctx
->ac
.i32_0
;
4303 result
= ac_build_gather_values(&ctx
->ac
, values
, 3);
4306 case nir_intrinsic_load_base_vertex
: {
4307 result
= ctx
->abi
->base_vertex
;
4310 case nir_intrinsic_load_local_group_size
:
4311 result
= ctx
->abi
->load_local_group_size(ctx
->abi
);
4313 case nir_intrinsic_load_vertex_id_zero_base
: {
4314 result
= ctx
->abi
->vertex_id
;
4317 case nir_intrinsic_load_local_invocation_id
: {
4318 result
= ctx
->abi
->local_invocation_ids
;
4321 case nir_intrinsic_load_base_instance
:
4322 result
= ctx
->abi
->start_instance
;
4324 case nir_intrinsic_load_draw_id
:
4325 result
= ctx
->abi
->draw_id
;
4327 case nir_intrinsic_load_view_index
:
4328 result
= ctx
->nctx
->view_index
? ctx
->nctx
->view_index
: ctx
->ac
.i32_0
;
4330 case nir_intrinsic_load_invocation_id
:
4331 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
4332 result
= unpack_param(&ctx
->ac
, ctx
->abi
->tcs_rel_ids
, 8, 5);
4334 result
= ctx
->abi
->gs_invocation_id
;
4336 case nir_intrinsic_load_primitive_id
:
4337 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
4338 result
= ctx
->abi
->gs_prim_id
;
4339 } else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
4340 result
= ctx
->abi
->tcs_patch_id
;
4341 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4342 result
= ctx
->abi
->tes_patch_id
;
4344 fprintf(stderr
, "Unknown primitive id intrinsic: %d", ctx
->stage
);
4346 case nir_intrinsic_load_sample_id
:
4347 result
= unpack_param(&ctx
->ac
, ctx
->abi
->ancillary
, 8, 4);
4349 case nir_intrinsic_load_sample_pos
:
4350 result
= load_sample_pos(ctx
);
4352 case nir_intrinsic_load_sample_mask_in
:
4354 result
= load_sample_mask_in(ctx
);
4356 result
= ctx
->abi
->sample_coverage
;
4358 case nir_intrinsic_load_frag_coord
: {
4359 LLVMValueRef values
[4] = {
4360 ctx
->abi
->frag_pos
[0],
4361 ctx
->abi
->frag_pos
[1],
4362 ctx
->abi
->frag_pos
[2],
4363 ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, ctx
->abi
->frag_pos
[3])
4365 result
= ac_build_gather_values(&ctx
->ac
, values
, 4);
4368 case nir_intrinsic_load_front_face
:
4369 result
= ctx
->abi
->front_face
;
4371 case nir_intrinsic_load_helper_invocation
:
4372 result
= visit_load_helper_invocation(ctx
);
4374 case nir_intrinsic_load_instance_id
:
4375 result
= ctx
->abi
->instance_id
;
4377 case nir_intrinsic_load_num_work_groups
:
4378 result
= ctx
->abi
->num_work_groups
;
4380 case nir_intrinsic_load_local_invocation_index
:
4381 result
= visit_load_local_invocation_index(ctx
->nctx
);
4383 case nir_intrinsic_load_push_constant
:
4384 result
= visit_load_push_constant(ctx
->nctx
, instr
);
4386 case nir_intrinsic_vulkan_resource_index
:
4387 result
= visit_vulkan_resource_index(ctx
->nctx
, instr
);
4389 case nir_intrinsic_vulkan_resource_reindex
:
4390 result
= visit_vulkan_resource_reindex(ctx
->nctx
, instr
);
4392 case nir_intrinsic_store_ssbo
:
4393 visit_store_ssbo(ctx
, instr
);
4395 case nir_intrinsic_load_ssbo
:
4396 result
= visit_load_buffer(ctx
, instr
);
4398 case nir_intrinsic_ssbo_atomic_add
:
4399 case nir_intrinsic_ssbo_atomic_imin
:
4400 case nir_intrinsic_ssbo_atomic_umin
:
4401 case nir_intrinsic_ssbo_atomic_imax
:
4402 case nir_intrinsic_ssbo_atomic_umax
:
4403 case nir_intrinsic_ssbo_atomic_and
:
4404 case nir_intrinsic_ssbo_atomic_or
:
4405 case nir_intrinsic_ssbo_atomic_xor
:
4406 case nir_intrinsic_ssbo_atomic_exchange
:
4407 case nir_intrinsic_ssbo_atomic_comp_swap
:
4408 result
= visit_atomic_ssbo(ctx
, instr
);
4410 case nir_intrinsic_load_ubo
:
4411 result
= visit_load_ubo_buffer(ctx
, instr
);
4413 case nir_intrinsic_get_buffer_size
:
4414 result
= visit_get_buffer_size(ctx
, instr
);
4416 case nir_intrinsic_load_var
:
4417 result
= visit_load_var(ctx
, instr
);
4419 case nir_intrinsic_store_var
:
4420 visit_store_var(ctx
, instr
);
4422 case nir_intrinsic_image_load
:
4423 result
= visit_image_load(ctx
, instr
);
4425 case nir_intrinsic_image_store
:
4426 visit_image_store(ctx
, instr
);
4428 case nir_intrinsic_image_atomic_add
:
4429 case nir_intrinsic_image_atomic_min
:
4430 case nir_intrinsic_image_atomic_max
:
4431 case nir_intrinsic_image_atomic_and
:
4432 case nir_intrinsic_image_atomic_or
:
4433 case nir_intrinsic_image_atomic_xor
:
4434 case nir_intrinsic_image_atomic_exchange
:
4435 case nir_intrinsic_image_atomic_comp_swap
:
4436 result
= visit_image_atomic(ctx
, instr
);
4438 case nir_intrinsic_image_size
:
4439 result
= visit_image_size(ctx
, instr
);
4441 case nir_intrinsic_shader_clock
:
4442 result
= ac_build_shader_clock(&ctx
->ac
);
4444 case nir_intrinsic_discard
:
4445 case nir_intrinsic_discard_if
:
4446 emit_discard(ctx
, instr
);
4448 case nir_intrinsic_memory_barrier
:
4449 case nir_intrinsic_group_memory_barrier
:
4450 case nir_intrinsic_memory_barrier_atomic_counter
:
4451 case nir_intrinsic_memory_barrier_buffer
:
4452 case nir_intrinsic_memory_barrier_image
:
4453 case nir_intrinsic_memory_barrier_shared
:
4454 emit_membar(ctx
->nctx
, instr
);
4456 case nir_intrinsic_barrier
:
4457 emit_barrier(&ctx
->ac
, ctx
->stage
);
4459 case nir_intrinsic_var_atomic_add
:
4460 case nir_intrinsic_var_atomic_imin
:
4461 case nir_intrinsic_var_atomic_umin
:
4462 case nir_intrinsic_var_atomic_imax
:
4463 case nir_intrinsic_var_atomic_umax
:
4464 case nir_intrinsic_var_atomic_and
:
4465 case nir_intrinsic_var_atomic_or
:
4466 case nir_intrinsic_var_atomic_xor
:
4467 case nir_intrinsic_var_atomic_exchange
:
4468 case nir_intrinsic_var_atomic_comp_swap
:
4469 result
= visit_var_atomic(ctx
->nctx
, instr
);
4471 case nir_intrinsic_interp_var_at_centroid
:
4472 case nir_intrinsic_interp_var_at_sample
:
4473 case nir_intrinsic_interp_var_at_offset
:
4474 result
= visit_interp(ctx
, instr
);
4476 case nir_intrinsic_emit_vertex
:
4477 ctx
->abi
->emit_vertex(ctx
->abi
, nir_intrinsic_stream_id(instr
), ctx
->outputs
);
4479 case nir_intrinsic_end_primitive
:
4480 ctx
->abi
->emit_primitive(ctx
->abi
, nir_intrinsic_stream_id(instr
));
4482 case nir_intrinsic_load_tess_coord
: {
4483 LLVMTypeRef type
= ctx
->nctx
?
4484 get_def_type(ctx
->nctx
->nir
, &instr
->dest
.ssa
) :
4486 result
= ctx
->abi
->load_tess_coord(ctx
->abi
, type
, instr
->num_components
);
4489 case nir_intrinsic_load_tess_level_outer
:
4490 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_OUTER
);
4492 case nir_intrinsic_load_tess_level_inner
:
4493 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_INNER
);
4495 case nir_intrinsic_load_patch_vertices_in
:
4496 result
= ctx
->abi
->load_patch_vertices_in(ctx
->abi
);
4498 case nir_intrinsic_vote_all
: {
4499 LLVMValueRef tmp
= ac_build_vote_all(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4500 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4503 case nir_intrinsic_vote_any
: {
4504 LLVMValueRef tmp
= ac_build_vote_any(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4505 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4508 case nir_intrinsic_vote_eq
: {
4509 LLVMValueRef tmp
= ac_build_vote_eq(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4510 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4514 fprintf(stderr
, "Unknown intrinsic: ");
4515 nir_print_instr(&instr
->instr
, stderr
);
4516 fprintf(stderr
, "\n");
4520 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4524 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
4525 LLVMValueRef buffer_ptr
, bool write
)
4527 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4528 LLVMValueRef result
;
4530 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
4532 result
= LLVMBuildLoad(ctx
->builder
, buffer_ptr
, "");
4533 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
4538 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
4540 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4541 LLVMValueRef result
;
4543 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
4545 result
= LLVMBuildLoad(ctx
->builder
, buffer_ptr
, "");
4546 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
4551 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
4552 unsigned descriptor_set
,
4553 unsigned base_index
,
4554 unsigned constant_index
,
4556 enum ac_descriptor_type desc_type
,
4557 bool image
, bool write
)
4559 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4560 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
4561 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
4562 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
4563 unsigned offset
= binding
->offset
;
4564 unsigned stride
= binding
->size
;
4566 LLVMBuilderRef builder
= ctx
->builder
;
4569 assert(base_index
< layout
->binding_count
);
4571 switch (desc_type
) {
4573 type
= ctx
->ac
.v8i32
;
4577 type
= ctx
->ac
.v8i32
;
4581 case AC_DESC_SAMPLER
:
4582 type
= ctx
->ac
.v4i32
;
4583 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
4588 case AC_DESC_BUFFER
:
4589 type
= ctx
->ac
.v4i32
;
4593 unreachable("invalid desc_type\n");
4596 offset
+= constant_index
* stride
;
4598 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
4599 (!index
|| binding
->immutable_samplers_equal
)) {
4600 if (binding
->immutable_samplers_equal
)
4603 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
4605 LLVMValueRef constants
[] = {
4606 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
4607 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
4608 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
4609 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
4611 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
4614 assert(stride
% type_size
== 0);
4617 index
= ctx
->ac
.i32_0
;
4619 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
4621 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->ac
.i32
, offset
, 0));
4622 list
= LLVMBuildPointerCast(builder
, list
, ac_array_in_const_addr_space(type
), "");
4624 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
4627 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
4628 const nir_deref_var
*deref
,
4629 enum ac_descriptor_type desc_type
,
4630 const nir_tex_instr
*tex_instr
,
4631 bool image
, bool write
)
4633 LLVMValueRef index
= NULL
;
4634 unsigned constant_index
= 0;
4635 unsigned descriptor_set
;
4636 unsigned base_index
;
4639 assert(tex_instr
&& !image
);
4641 base_index
= tex_instr
->sampler_index
;
4643 const nir_deref
*tail
= &deref
->deref
;
4644 while (tail
->child
) {
4645 const nir_deref_array
*child
= nir_deref_as_array(tail
->child
);
4646 unsigned array_size
= glsl_get_aoa_size(tail
->child
->type
);
4651 assert(child
->deref_array_type
!= nir_deref_array_type_wildcard
);
4653 if (child
->deref_array_type
== nir_deref_array_type_indirect
) {
4654 LLVMValueRef indirect
= get_src(ctx
, child
->indirect
);
4656 indirect
= LLVMBuildMul(ctx
->ac
.builder
, indirect
,
4657 LLVMConstInt(ctx
->ac
.i32
, array_size
, false), "");
4662 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
, indirect
, "");
4665 constant_index
+= child
->base_offset
* array_size
;
4667 tail
= &child
->deref
;
4669 descriptor_set
= deref
->var
->data
.descriptor_set
;
4670 base_index
= deref
->var
->data
.binding
;
4673 return ctx
->abi
->load_sampler_desc(ctx
->abi
,
4676 constant_index
, index
,
4677 desc_type
, image
, write
);
4680 static void set_tex_fetch_args(struct ac_llvm_context
*ctx
,
4681 struct ac_image_args
*args
,
4682 const nir_tex_instr
*instr
,
4684 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
4685 LLVMValueRef
*param
, unsigned count
,
4688 unsigned is_rect
= 0;
4689 bool da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
4691 if (op
== nir_texop_lod
)
4693 /* Pad to power of two vector */
4694 while (count
< util_next_power_of_two(count
))
4695 param
[count
++] = LLVMGetUndef(ctx
->i32
);
4698 args
->addr
= ac_build_gather_values(ctx
, param
, count
);
4700 args
->addr
= param
[0];
4702 args
->resource
= res_ptr
;
4703 args
->sampler
= samp_ptr
;
4705 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
&& op
== nir_texop_txf
) {
4706 args
->addr
= param
[0];
4710 args
->dmask
= dmask
;
4711 args
->unorm
= is_rect
;
4715 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4718 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4719 * filtering manually. The driver sets img7 to a mask clearing
4720 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4721 * s_and_b32 samp0, samp0, img7
4724 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4726 static LLVMValueRef
sici_fix_sampler_aniso(struct ac_nir_context
*ctx
,
4727 LLVMValueRef res
, LLVMValueRef samp
)
4729 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4730 LLVMValueRef img7
, samp0
;
4732 if (ctx
->ac
.chip_class
>= VI
)
4735 img7
= LLVMBuildExtractElement(builder
, res
,
4736 LLVMConstInt(ctx
->ac
.i32
, 7, 0), "");
4737 samp0
= LLVMBuildExtractElement(builder
, samp
,
4738 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4739 samp0
= LLVMBuildAnd(builder
, samp0
, img7
, "");
4740 return LLVMBuildInsertElement(builder
, samp
, samp0
,
4741 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4744 static void tex_fetch_ptrs(struct ac_nir_context
*ctx
,
4745 nir_tex_instr
*instr
,
4746 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
4747 LLVMValueRef
*fmask_ptr
)
4749 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4750 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_BUFFER
, instr
, false, false);
4752 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_IMAGE
, instr
, false, false);
4755 *samp_ptr
= get_sampler_desc(ctx
, instr
->sampler
, AC_DESC_SAMPLER
, instr
, false, false);
4757 *samp_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_SAMPLER
, instr
, false, false);
4758 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
)
4759 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
4761 if (fmask_ptr
&& !instr
->sampler
&& (instr
->op
== nir_texop_txf_ms
||
4762 instr
->op
== nir_texop_samples_identical
))
4763 *fmask_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_FMASK
, instr
, false, false);
4766 static LLVMValueRef
apply_round_slice(struct ac_llvm_context
*ctx
,
4769 coord
= ac_to_float(ctx
, coord
);
4770 coord
= ac_build_intrinsic(ctx
, "llvm.rint.f32", ctx
->f32
, &coord
, 1, 0);
4771 coord
= ac_to_integer(ctx
, coord
);
4775 static void visit_tex(struct ac_nir_context
*ctx
, nir_tex_instr
*instr
)
4777 LLVMValueRef result
= NULL
;
4778 struct ac_image_args args
= { 0 };
4779 unsigned dmask
= 0xf;
4780 LLVMValueRef address
[16];
4781 LLVMValueRef coords
[5];
4782 LLVMValueRef coord
= NULL
, lod
= NULL
, comparator
= NULL
;
4783 LLVMValueRef bias
= NULL
, offsets
= NULL
;
4784 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
, sample_index
= NULL
;
4785 LLVMValueRef ddx
= NULL
, ddy
= NULL
;
4786 LLVMValueRef derivs
[6];
4787 unsigned chan
, count
= 0;
4788 unsigned const_src
= 0, num_deriv_comp
= 0;
4789 bool lod_is_zero
= false;
4791 tex_fetch_ptrs(ctx
, instr
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4793 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4794 switch (instr
->src
[i
].src_type
) {
4795 case nir_tex_src_coord
:
4796 coord
= get_src(ctx
, instr
->src
[i
].src
);
4798 case nir_tex_src_projector
:
4800 case nir_tex_src_comparator
:
4801 comparator
= get_src(ctx
, instr
->src
[i
].src
);
4803 case nir_tex_src_offset
:
4804 offsets
= get_src(ctx
, instr
->src
[i
].src
);
4807 case nir_tex_src_bias
:
4808 bias
= get_src(ctx
, instr
->src
[i
].src
);
4810 case nir_tex_src_lod
: {
4811 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
4813 if (val
&& val
->i32
[0] == 0)
4815 lod
= get_src(ctx
, instr
->src
[i
].src
);
4818 case nir_tex_src_ms_index
:
4819 sample_index
= get_src(ctx
, instr
->src
[i
].src
);
4821 case nir_tex_src_ms_mcs
:
4823 case nir_tex_src_ddx
:
4824 ddx
= get_src(ctx
, instr
->src
[i
].src
);
4825 num_deriv_comp
= instr
->src
[i
].src
.ssa
->num_components
;
4827 case nir_tex_src_ddy
:
4828 ddy
= get_src(ctx
, instr
->src
[i
].src
);
4830 case nir_tex_src_texture_offset
:
4831 case nir_tex_src_sampler_offset
:
4832 case nir_tex_src_plane
:
4838 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
4839 result
= get_buffer_size(ctx
, res_ptr
, true);
4843 if (instr
->op
== nir_texop_texture_samples
) {
4844 LLVMValueRef res
, samples
, is_msaa
;
4845 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->ac
.v8i32
, "");
4846 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
4847 LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
4848 is_msaa
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4849 LLVMConstInt(ctx
->ac
.i32
, 28, false), "");
4850 is_msaa
= LLVMBuildAnd(ctx
->ac
.builder
, is_msaa
,
4851 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4852 is_msaa
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, is_msaa
,
4853 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4855 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4856 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
4857 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
4858 LLVMConstInt(ctx
->ac
.i32
, 0xf, false), "");
4859 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->ac
.i32_1
,
4861 samples
= LLVMBuildSelect(ctx
->ac
.builder
, is_msaa
, samples
,
4868 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4869 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, coord
, chan
);
4871 if (offsets
&& instr
->op
!= nir_texop_txf
) {
4872 LLVMValueRef offset
[3], pack
;
4873 for (chan
= 0; chan
< 3; ++chan
)
4874 offset
[chan
] = ctx
->ac
.i32_0
;
4877 for (chan
= 0; chan
< ac_get_llvm_num_components(offsets
); chan
++) {
4878 offset
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, offsets
, chan
);
4879 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
4880 LLVMConstInt(ctx
->ac
.i32
, 0x3f, false), "");
4882 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
4883 LLVMConstInt(ctx
->ac
.i32
, chan
* 8, false), "");
4885 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
4886 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
4887 address
[count
++] = pack
;
4890 /* pack LOD bias value */
4891 if (instr
->op
== nir_texop_txb
&& bias
) {
4892 address
[count
++] = bias
;
4895 /* Pack depth comparison value */
4896 if (instr
->is_shadow
&& comparator
) {
4897 LLVMValueRef z
= ac_to_float(&ctx
->ac
,
4898 ac_llvm_extract_elem(&ctx
->ac
, comparator
, 0));
4900 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4901 * so the depth comparison value isn't clamped for Z16 and
4902 * Z24 anymore. Do it manually here.
4904 * It's unnecessary if the original texture format was
4905 * Z32_FLOAT, but we don't know that here.
4907 if (ctx
->ac
.chip_class
== VI
&& ctx
->abi
->clamp_shadow_reference
)
4908 z
= ac_build_clamp(&ctx
->ac
, z
);
4910 address
[count
++] = z
;
4913 /* pack derivatives */
4915 int num_src_deriv_channels
, num_dest_deriv_channels
;
4916 switch (instr
->sampler_dim
) {
4917 case GLSL_SAMPLER_DIM_3D
:
4918 case GLSL_SAMPLER_DIM_CUBE
:
4920 num_src_deriv_channels
= 3;
4921 num_dest_deriv_channels
= 3;
4923 case GLSL_SAMPLER_DIM_2D
:
4925 num_src_deriv_channels
= 2;
4926 num_dest_deriv_channels
= 2;
4929 case GLSL_SAMPLER_DIM_1D
:
4930 num_src_deriv_channels
= 1;
4931 if (ctx
->ac
.chip_class
>= GFX9
) {
4932 num_dest_deriv_channels
= 2;
4935 num_dest_deriv_channels
= 1;
4941 for (unsigned i
= 0; i
< num_src_deriv_channels
; i
++) {
4942 derivs
[i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddx
, i
));
4943 derivs
[num_dest_deriv_channels
+ i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddy
, i
));
4945 for (unsigned i
= num_src_deriv_channels
; i
< num_dest_deriv_channels
; i
++) {
4946 derivs
[i
] = ctx
->ac
.f32_0
;
4947 derivs
[num_dest_deriv_channels
+ i
] = ctx
->ac
.f32_0
;
4951 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& coord
) {
4952 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4953 coords
[chan
] = ac_to_float(&ctx
->ac
, coords
[chan
]);
4954 if (instr
->coord_components
== 3)
4955 coords
[3] = LLVMGetUndef(ctx
->ac
.f32
);
4956 ac_prepare_cube_coords(&ctx
->ac
,
4957 instr
->op
== nir_texop_txd
, instr
->is_array
,
4958 instr
->op
== nir_texop_lod
, coords
, derivs
);
4964 for (unsigned i
= 0; i
< num_deriv_comp
* 2; i
++)
4965 address
[count
++] = derivs
[i
];
4968 /* Pack texture coordinates */
4970 address
[count
++] = coords
[0];
4971 if (instr
->coord_components
> 1) {
4972 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& instr
->is_array
&& instr
->op
!= nir_texop_txf
) {
4973 coords
[1] = apply_round_slice(&ctx
->ac
, coords
[1]);
4975 address
[count
++] = coords
[1];
4977 if (instr
->coord_components
> 2) {
4978 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4979 if (instr
->sampler_dim
!= GLSL_SAMPLER_DIM_3D
&&
4980 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_CUBE
&&
4981 instr
->op
!= nir_texop_txf
) {
4982 coords
[2] = apply_round_slice(&ctx
->ac
, coords
[2]);
4984 address
[count
++] = coords
[2];
4987 if (ctx
->ac
.chip_class
>= GFX9
) {
4988 LLVMValueRef filler
;
4989 if (instr
->op
== nir_texop_txf
)
4990 filler
= ctx
->ac
.i32_0
;
4992 filler
= LLVMConstReal(ctx
->ac
.f32
, 0.5);
4994 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
) {
4995 /* No nir_texop_lod, because it does not take a slice
4996 * even with array textures. */
4997 if (instr
->is_array
&& instr
->op
!= nir_texop_lod
) {
4998 address
[count
] = address
[count
- 1];
4999 address
[count
- 1] = filler
;
5002 address
[count
++] = filler
;
5008 if (lod
&& ((instr
->op
== nir_texop_txl
&& !lod_is_zero
) ||
5009 instr
->op
== nir_texop_txf
)) {
5010 address
[count
++] = lod
;
5011 } else if (instr
->op
== nir_texop_txf_ms
&& sample_index
) {
5012 address
[count
++] = sample_index
;
5013 } else if(instr
->op
== nir_texop_txs
) {
5016 address
[count
++] = lod
;
5018 address
[count
++] = ctx
->ac
.i32_0
;
5021 for (chan
= 0; chan
< count
; chan
++) {
5022 address
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
,
5023 address
[chan
], ctx
->ac
.i32
, "");
5026 if (instr
->op
== nir_texop_samples_identical
) {
5027 LLVMValueRef txf_address
[4];
5028 struct ac_image_args txf_args
= { 0 };
5029 unsigned txf_count
= count
;
5030 memcpy(txf_address
, address
, sizeof(txf_address
));
5032 if (!instr
->is_array
)
5033 txf_address
[2] = ctx
->ac
.i32_0
;
5034 txf_address
[3] = ctx
->ac
.i32_0
;
5036 set_tex_fetch_args(&ctx
->ac
, &txf_args
, instr
, nir_texop_txf
,
5038 txf_address
, txf_count
, 0xf);
5040 result
= build_tex_intrinsic(ctx
, instr
, false, &txf_args
);
5042 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
5043 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, result
, ctx
->ac
.i32_0
);
5047 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
&&
5048 instr
->op
!= nir_texop_txs
) {
5049 unsigned sample_chan
= instr
->is_array
? 3 : 2;
5050 address
[sample_chan
] = adjust_sample_index_using_fmask(&ctx
->ac
,
5053 instr
->is_array
? address
[2] : NULL
,
5054 address
[sample_chan
],
5058 if (offsets
&& instr
->op
== nir_texop_txf
) {
5059 nir_const_value
*const_offset
=
5060 nir_src_as_const_value(instr
->src
[const_src
].src
);
5061 int num_offsets
= instr
->src
[const_src
].src
.ssa
->num_components
;
5062 assert(const_offset
);
5063 num_offsets
= MIN2(num_offsets
, instr
->coord_components
);
5064 if (num_offsets
> 2)
5065 address
[2] = LLVMBuildAdd(ctx
->ac
.builder
,
5066 address
[2], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[2], false), "");
5067 if (num_offsets
> 1)
5068 address
[1] = LLVMBuildAdd(ctx
->ac
.builder
,
5069 address
[1], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[1], false), "");
5070 address
[0] = LLVMBuildAdd(ctx
->ac
.builder
,
5071 address
[0], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[0], false), "");
5075 /* TODO TG4 support */
5076 if (instr
->op
== nir_texop_tg4
) {
5077 if (instr
->is_shadow
)
5080 dmask
= 1 << instr
->component
;
5082 set_tex_fetch_args(&ctx
->ac
, &args
, instr
, instr
->op
,
5083 res_ptr
, samp_ptr
, address
, count
, dmask
);
5085 result
= build_tex_intrinsic(ctx
, instr
, lod_is_zero
, &args
);
5087 if (instr
->op
== nir_texop_query_levels
)
5088 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
5089 else if (instr
->is_shadow
&& instr
->is_new_style_shadow
&&
5090 instr
->op
!= nir_texop_txs
&& instr
->op
!= nir_texop_lod
&&
5091 instr
->op
!= nir_texop_tg4
)
5092 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
5093 else if (instr
->op
== nir_texop_txs
&&
5094 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
5096 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
5097 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
5098 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
5099 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
5100 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, z
, two
, "");
5101 } else if (ctx
->ac
.chip_class
>= GFX9
&&
5102 instr
->op
== nir_texop_txs
&&
5103 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
5105 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
5106 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
5107 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, layers
,
5109 } else if (instr
->dest
.ssa
.num_components
!= 4)
5110 result
= trim_vector(&ctx
->ac
, result
, instr
->dest
.ssa
.num_components
);
5114 assert(instr
->dest
.is_ssa
);
5115 result
= ac_to_integer(&ctx
->ac
, result
);
5116 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
5121 static void visit_phi(struct ac_nir_context
*ctx
, nir_phi_instr
*instr
)
5123 LLVMTypeRef type
= get_def_type(ctx
, &instr
->dest
.ssa
);
5124 LLVMValueRef result
= LLVMBuildPhi(ctx
->ac
.builder
, type
, "");
5126 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
5127 _mesa_hash_table_insert(ctx
->phis
, instr
, result
);
5130 static void visit_post_phi(struct ac_nir_context
*ctx
,
5131 nir_phi_instr
*instr
,
5132 LLVMValueRef llvm_phi
)
5134 nir_foreach_phi_src(src
, instr
) {
5135 LLVMBasicBlockRef block
= get_block(ctx
, src
->pred
);
5136 LLVMValueRef llvm_src
= get_src(ctx
, src
->src
);
5138 LLVMAddIncoming(llvm_phi
, &llvm_src
, &block
, 1);
5142 static void phi_post_pass(struct ac_nir_context
*ctx
)
5144 struct hash_entry
*entry
;
5145 hash_table_foreach(ctx
->phis
, entry
) {
5146 visit_post_phi(ctx
, (nir_phi_instr
*)entry
->key
,
5147 (LLVMValueRef
)entry
->data
);
5152 static void visit_ssa_undef(struct ac_nir_context
*ctx
,
5153 const nir_ssa_undef_instr
*instr
)
5155 unsigned num_components
= instr
->def
.num_components
;
5156 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
5159 if (num_components
== 1)
5160 undef
= LLVMGetUndef(type
);
5162 undef
= LLVMGetUndef(LLVMVectorType(type
, num_components
));
5164 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, undef
);
5167 static void visit_jump(struct ac_nir_context
*ctx
,
5168 const nir_jump_instr
*instr
)
5170 switch (instr
->type
) {
5171 case nir_jump_break
:
5172 LLVMBuildBr(ctx
->ac
.builder
, ctx
->break_block
);
5173 LLVMClearInsertionPosition(ctx
->ac
.builder
);
5175 case nir_jump_continue
:
5176 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5177 LLVMClearInsertionPosition(ctx
->ac
.builder
);
5180 fprintf(stderr
, "Unknown NIR jump instr: ");
5181 nir_print_instr(&instr
->instr
, stderr
);
5182 fprintf(stderr
, "\n");
5187 static void visit_cf_list(struct ac_nir_context
*ctx
,
5188 struct exec_list
*list
);
5190 static void visit_block(struct ac_nir_context
*ctx
, nir_block
*block
)
5192 LLVMBasicBlockRef llvm_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
5193 nir_foreach_instr(instr
, block
)
5195 switch (instr
->type
) {
5196 case nir_instr_type_alu
:
5197 visit_alu(ctx
, nir_instr_as_alu(instr
));
5199 case nir_instr_type_load_const
:
5200 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
5202 case nir_instr_type_intrinsic
:
5203 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
5205 case nir_instr_type_tex
:
5206 visit_tex(ctx
, nir_instr_as_tex(instr
));
5208 case nir_instr_type_phi
:
5209 visit_phi(ctx
, nir_instr_as_phi(instr
));
5211 case nir_instr_type_ssa_undef
:
5212 visit_ssa_undef(ctx
, nir_instr_as_ssa_undef(instr
));
5214 case nir_instr_type_jump
:
5215 visit_jump(ctx
, nir_instr_as_jump(instr
));
5218 fprintf(stderr
, "Unknown NIR instr type: ");
5219 nir_print_instr(instr
, stderr
);
5220 fprintf(stderr
, "\n");
5225 _mesa_hash_table_insert(ctx
->defs
, block
, llvm_block
);
5228 static void visit_if(struct ac_nir_context
*ctx
, nir_if
*if_stmt
)
5230 LLVMValueRef value
= get_src(ctx
, if_stmt
->condition
);
5232 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
5233 LLVMBasicBlockRef merge_block
=
5234 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5235 LLVMBasicBlockRef if_block
=
5236 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5237 LLVMBasicBlockRef else_block
= merge_block
;
5238 if (!exec_list_is_empty(&if_stmt
->else_list
))
5239 else_block
= LLVMAppendBasicBlockInContext(
5240 ctx
->ac
.context
, fn
, "");
5242 LLVMValueRef cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
, value
,
5244 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, if_block
, else_block
);
5246 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, if_block
);
5247 visit_cf_list(ctx
, &if_stmt
->then_list
);
5248 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5249 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
5251 if (!exec_list_is_empty(&if_stmt
->else_list
)) {
5252 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, else_block
);
5253 visit_cf_list(ctx
, &if_stmt
->else_list
);
5254 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5255 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
5258 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
5261 static void visit_loop(struct ac_nir_context
*ctx
, nir_loop
*loop
)
5263 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
5264 LLVMBasicBlockRef continue_parent
= ctx
->continue_block
;
5265 LLVMBasicBlockRef break_parent
= ctx
->break_block
;
5267 ctx
->continue_block
=
5268 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5270 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5272 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5273 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->continue_block
);
5274 visit_cf_list(ctx
, &loop
->body
);
5276 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5277 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5278 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->break_block
);
5280 ctx
->continue_block
= continue_parent
;
5281 ctx
->break_block
= break_parent
;
5284 static void visit_cf_list(struct ac_nir_context
*ctx
,
5285 struct exec_list
*list
)
5287 foreach_list_typed(nir_cf_node
, node
, node
, list
)
5289 switch (node
->type
) {
5290 case nir_cf_node_block
:
5291 visit_block(ctx
, nir_cf_node_as_block(node
));
5294 case nir_cf_node_if
:
5295 visit_if(ctx
, nir_cf_node_as_if(node
));
5298 case nir_cf_node_loop
:
5299 visit_loop(ctx
, nir_cf_node_as_loop(node
));
5309 handle_vs_input_decl(struct nir_to_llvm_context
*ctx
,
5310 struct nir_variable
*variable
)
5312 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
5313 LLVMValueRef t_offset
;
5314 LLVMValueRef t_list
;
5316 LLVMValueRef buffer_index
;
5317 int index
= variable
->data
.location
- VERT_ATTRIB_GENERIC0
;
5318 int idx
= variable
->data
.location
;
5319 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
5320 uint8_t input_usage_mask
=
5321 ctx
->shader_info
->info
.vs
.input_usage_mask
[variable
->data
.location
];
5322 unsigned num_channels
= util_last_bit(input_usage_mask
);
5324 variable
->data
.driver_location
= idx
* 4;
5326 for (unsigned i
= 0; i
< attrib_count
; ++i
, ++idx
) {
5327 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << (index
+ i
))) {
5328 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.instance_id
,
5329 ctx
->abi
.start_instance
, "");
5330 if (ctx
->options
->key
.vs
.as_ls
) {
5331 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5332 MAX2(2, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5334 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5335 MAX2(1, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5338 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.vertex_id
,
5339 ctx
->abi
.base_vertex
, "");
5340 t_offset
= LLVMConstInt(ctx
->ac
.i32
, index
+ i
, false);
5342 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
5344 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
5347 num_channels
, false, true);
5349 input
= ac_build_expand_to_vec4(&ctx
->ac
, input
, num_channels
);
5351 for (unsigned chan
= 0; chan
< 4; chan
++) {
5352 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5353 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
, chan
)] =
5354 ac_to_integer(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
,
5355 input
, llvm_chan
, ""));
5360 static void interp_fs_input(struct nir_to_llvm_context
*ctx
,
5362 LLVMValueRef interp_param
,
5363 LLVMValueRef prim_mask
,
5364 LLVMValueRef result
[4])
5366 LLVMValueRef attr_number
;
5369 bool interp
= interp_param
!= NULL
;
5371 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
5373 /* fs.constant returns the param from the middle vertex, so it's not
5374 * really useful for flat shading. It's meant to be used for custom
5375 * interpolation (but the intrinsic can't fetch from the other two
5378 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5379 * to do the right thing. The only reason we use fs.constant is that
5380 * fs.interp cannot be used on integers, because they can be equal
5384 interp_param
= LLVMBuildBitCast(ctx
->builder
, interp_param
,
5387 i
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
5389 j
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
5393 for (chan
= 0; chan
< 4; chan
++) {
5394 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5397 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
5402 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
5403 LLVMConstInt(ctx
->ac
.i32
, 2, false),
5412 handle_fs_input_decl(struct nir_to_llvm_context
*ctx
,
5413 struct nir_variable
*variable
)
5415 int idx
= variable
->data
.location
;
5416 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5417 LLVMValueRef interp
;
5419 variable
->data
.driver_location
= idx
* 4;
5420 ctx
->input_mask
|= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
5422 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
5423 unsigned interp_type
;
5424 if (variable
->data
.sample
) {
5425 interp_type
= INTERP_SAMPLE
;
5426 ctx
->shader_info
->info
.ps
.force_persample
= true;
5427 } else if (variable
->data
.centroid
)
5428 interp_type
= INTERP_CENTROID
;
5430 interp_type
= INTERP_CENTER
;
5432 interp
= lookup_interp_param(&ctx
->abi
, variable
->data
.interpolation
, interp_type
);
5436 for (unsigned i
= 0; i
< attrib_count
; ++i
)
5437 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
5442 handle_vs_inputs(struct nir_to_llvm_context
*ctx
,
5443 struct nir_shader
*nir
) {
5444 nir_foreach_variable(variable
, &nir
->inputs
)
5445 handle_vs_input_decl(ctx
, variable
);
5449 prepare_interp_optimize(struct nir_to_llvm_context
*ctx
,
5450 struct nir_shader
*nir
)
5452 if (!ctx
->options
->key
.fs
.multisample
)
5455 bool uses_center
= false;
5456 bool uses_centroid
= false;
5457 nir_foreach_variable(variable
, &nir
->inputs
) {
5458 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
5459 variable
->data
.sample
)
5462 if (variable
->data
.centroid
)
5463 uses_centroid
= true;
5468 if (uses_center
&& uses_centroid
) {
5469 LLVMValueRef sel
= LLVMBuildICmp(ctx
->builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
5470 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
5471 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
5476 handle_fs_inputs(struct nir_to_llvm_context
*ctx
,
5477 struct nir_shader
*nir
)
5479 prepare_interp_optimize(ctx
, nir
);
5481 nir_foreach_variable(variable
, &nir
->inputs
)
5482 handle_fs_input_decl(ctx
, variable
);
5486 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
5487 ctx
->shader_info
->info
.needs_multiview_view_index
)
5488 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
5490 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
5491 LLVMValueRef interp_param
;
5492 LLVMValueRef
*inputs
= ctx
->inputs
+radeon_llvm_reg_index_soa(i
, 0);
5494 if (!(ctx
->input_mask
& (1ull << i
)))
5497 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
5498 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
5499 interp_param
= *inputs
;
5500 interp_fs_input(ctx
, index
, interp_param
, ctx
->abi
.prim_mask
,
5504 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
5506 } else if (i
== VARYING_SLOT_POS
) {
5507 for(int i
= 0; i
< 3; ++i
)
5508 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
5510 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
5511 ctx
->abi
.frag_pos
[3]);
5514 ctx
->shader_info
->fs
.num_interp
= index
;
5515 if (ctx
->input_mask
& (1 << VARYING_SLOT_PNTC
))
5516 ctx
->shader_info
->fs
.has_pcoord
= true;
5517 if (ctx
->input_mask
& (1 << VARYING_SLOT_PRIMITIVE_ID
))
5518 ctx
->shader_info
->fs
.prim_id_input
= true;
5519 if (ctx
->input_mask
& (1 << VARYING_SLOT_LAYER
))
5520 ctx
->shader_info
->fs
.layer_input
= true;
5521 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
5523 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
5524 ctx
->view_index
= ctx
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5528 ac_build_alloca(struct ac_llvm_context
*ac
,
5532 LLVMBuilderRef builder
= ac
->builder
;
5533 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(builder
);
5534 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
5535 LLVMBasicBlockRef first_block
= LLVMGetEntryBasicBlock(function
);
5536 LLVMValueRef first_instr
= LLVMGetFirstInstruction(first_block
);
5537 LLVMBuilderRef first_builder
= LLVMCreateBuilderInContext(ac
->context
);
5541 LLVMPositionBuilderBefore(first_builder
, first_instr
);
5543 LLVMPositionBuilderAtEnd(first_builder
, first_block
);
5546 res
= LLVMBuildAlloca(first_builder
, type
, name
);
5547 LLVMBuildStore(builder
, LLVMConstNull(type
), res
);
5549 LLVMDisposeBuilder(first_builder
);
5554 static LLVMValueRef
si_build_alloca_undef(struct ac_llvm_context
*ac
,
5558 LLVMValueRef ptr
= ac_build_alloca(ac
, type
, name
);
5559 LLVMBuildStore(ac
->builder
, LLVMGetUndef(type
), ptr
);
5564 scan_shader_output_decl(struct nir_to_llvm_context
*ctx
,
5565 struct nir_variable
*variable
,
5566 struct nir_shader
*shader
,
5567 gl_shader_stage stage
)
5569 int idx
= variable
->data
.location
+ variable
->data
.index
;
5570 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5571 uint64_t mask_attribs
;
5573 variable
->data
.driver_location
= idx
* 4;
5575 /* tess ctrl has it's own load/store paths for outputs */
5576 if (stage
== MESA_SHADER_TESS_CTRL
)
5579 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
5580 if (stage
== MESA_SHADER_VERTEX
||
5581 stage
== MESA_SHADER_TESS_EVAL
||
5582 stage
== MESA_SHADER_GEOMETRY
) {
5583 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5584 int length
= shader
->info
.clip_distance_array_size
+
5585 shader
->info
.cull_distance_array_size
;
5586 if (stage
== MESA_SHADER_VERTEX
) {
5587 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5588 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5590 if (stage
== MESA_SHADER_TESS_EVAL
) {
5591 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5592 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5599 mask_attribs
= 1ull << idx
;
5603 ctx
->output_mask
|= mask_attribs
;
5607 handle_shader_output_decl(struct ac_nir_context
*ctx
,
5608 struct nir_shader
*nir
,
5609 struct nir_variable
*variable
)
5611 unsigned output_loc
= variable
->data
.driver_location
/ 4;
5612 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5614 /* tess ctrl has it's own load/store paths for outputs */
5615 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
5618 if (ctx
->stage
== MESA_SHADER_VERTEX
||
5619 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
5620 ctx
->stage
== MESA_SHADER_GEOMETRY
) {
5621 int idx
= variable
->data
.location
+ variable
->data
.index
;
5622 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5623 int length
= nir
->info
.clip_distance_array_size
+
5624 nir
->info
.cull_distance_array_size
;
5633 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
5634 for (unsigned chan
= 0; chan
< 4; chan
++) {
5635 ctx
->outputs
[radeon_llvm_reg_index_soa(output_loc
+ i
, chan
)] =
5636 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5642 glsl_base_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5643 enum glsl_base_type type
)
5647 case GLSL_TYPE_UINT
:
5648 case GLSL_TYPE_BOOL
:
5649 case GLSL_TYPE_SUBROUTINE
:
5651 case GLSL_TYPE_FLOAT
: /* TODO handle mediump */
5653 case GLSL_TYPE_INT64
:
5654 case GLSL_TYPE_UINT64
:
5656 case GLSL_TYPE_DOUBLE
:
5659 unreachable("unknown GLSL type");
5664 glsl_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5665 const struct glsl_type
*type
)
5667 if (glsl_type_is_scalar(type
)) {
5668 return glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
));
5671 if (glsl_type_is_vector(type
)) {
5672 return LLVMVectorType(
5673 glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
)),
5674 glsl_get_vector_elements(type
));
5677 if (glsl_type_is_matrix(type
)) {
5678 return LLVMArrayType(
5679 glsl_to_llvm_type(ctx
, glsl_get_column_type(type
)),
5680 glsl_get_matrix_columns(type
));
5683 if (glsl_type_is_array(type
)) {
5684 return LLVMArrayType(
5685 glsl_to_llvm_type(ctx
, glsl_get_array_element(type
)),
5686 glsl_get_length(type
));
5689 assert(glsl_type_is_struct(type
));
5691 LLVMTypeRef member_types
[glsl_get_length(type
)];
5693 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
5695 glsl_to_llvm_type(ctx
,
5696 glsl_get_struct_field(type
, i
));
5699 return LLVMStructTypeInContext(ctx
->context
, member_types
,
5700 glsl_get_length(type
), false);
5704 setup_locals(struct ac_nir_context
*ctx
,
5705 struct nir_function
*func
)
5708 ctx
->num_locals
= 0;
5709 nir_foreach_variable(variable
, &func
->impl
->locals
) {
5710 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5711 variable
->data
.driver_location
= ctx
->num_locals
* 4;
5712 variable
->data
.location_frac
= 0;
5713 ctx
->num_locals
+= attrib_count
;
5715 ctx
->locals
= malloc(4 * ctx
->num_locals
* sizeof(LLVMValueRef
));
5719 for (i
= 0; i
< ctx
->num_locals
; i
++) {
5720 for (j
= 0; j
< 4; j
++) {
5721 ctx
->locals
[i
* 4 + j
] =
5722 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "temp");
5728 setup_shared(struct ac_nir_context
*ctx
,
5729 struct nir_shader
*nir
)
5731 nir_foreach_variable(variable
, &nir
->shared
) {
5732 LLVMValueRef shared
=
5733 LLVMAddGlobalInAddressSpace(
5734 ctx
->ac
.module
, glsl_to_llvm_type(ctx
->nctx
, variable
->type
),
5735 variable
->name
? variable
->name
: "",
5736 AC_LOCAL_ADDR_SPACE
);
5737 _mesa_hash_table_insert(ctx
->vars
, variable
, shared
);
5741 /* Initialize arguments for the shader export intrinsic */
5743 si_llvm_init_export_args(struct nir_to_llvm_context
*ctx
,
5744 LLVMValueRef
*values
,
5746 struct ac_export_args
*args
)
5748 /* Default is 0xf. Adjusted below depending on the format. */
5749 args
->enabled_channels
= 0xf;
5751 /* Specify whether the EXEC mask represents the valid mask */
5752 args
->valid_mask
= 0;
5754 /* Specify whether this is the last export */
5757 /* Specify the target we are exporting */
5758 args
->target
= target
;
5760 args
->compr
= false;
5761 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
5762 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
5763 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
5764 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
5766 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& target
>= V_008DFC_SQ_EXP_MRT
) {
5767 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
5768 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
5769 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
5770 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
5773 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
5774 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
5775 unsigned bits
, bool hi
) = NULL
;
5777 switch(col_format
) {
5778 case V_028714_SPI_SHADER_ZERO
:
5779 args
->enabled_channels
= 0; /* writemask */
5780 args
->target
= V_008DFC_SQ_EXP_NULL
;
5783 case V_028714_SPI_SHADER_32_R
:
5784 args
->enabled_channels
= 1;
5785 args
->out
[0] = values
[0];
5788 case V_028714_SPI_SHADER_32_GR
:
5789 args
->enabled_channels
= 0x3;
5790 args
->out
[0] = values
[0];
5791 args
->out
[1] = values
[1];
5794 case V_028714_SPI_SHADER_32_AR
:
5795 args
->enabled_channels
= 0x9;
5796 args
->out
[0] = values
[0];
5797 args
->out
[3] = values
[3];
5800 case V_028714_SPI_SHADER_FP16_ABGR
:
5801 packf
= ac_build_cvt_pkrtz_f16
;
5804 case V_028714_SPI_SHADER_UNORM16_ABGR
:
5805 packf
= ac_build_cvt_pknorm_u16
;
5808 case V_028714_SPI_SHADER_SNORM16_ABGR
:
5809 packf
= ac_build_cvt_pknorm_i16
;
5812 case V_028714_SPI_SHADER_UINT16_ABGR
:
5813 packi
= ac_build_cvt_pk_u16
;
5816 case V_028714_SPI_SHADER_SINT16_ABGR
:
5817 packi
= ac_build_cvt_pk_i16
;
5821 case V_028714_SPI_SHADER_32_ABGR
:
5822 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5826 /* Pack f16 or norm_i16/u16. */
5828 for (chan
= 0; chan
< 2; chan
++) {
5829 LLVMValueRef pack_args
[2] = {
5831 values
[2 * chan
+ 1]
5833 LLVMValueRef packed
;
5835 packed
= packf(&ctx
->ac
, pack_args
);
5836 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
5838 args
->compr
= 1; /* COMPR flag */
5843 for (chan
= 0; chan
< 2; chan
++) {
5844 LLVMValueRef pack_args
[2] = {
5845 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
5846 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
5848 LLVMValueRef packed
;
5850 packed
= packi(&ctx
->ac
, pack_args
,
5851 is_int8
? 8 : is_int10
? 10 : 16,
5853 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
5855 args
->compr
= 1; /* COMPR flag */
5860 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5862 for (unsigned i
= 0; i
< 4; ++i
)
5863 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
5867 handle_vs_outputs_post(struct nir_to_llvm_context
*ctx
,
5868 bool export_prim_id
,
5869 struct ac_vs_output_info
*outinfo
)
5871 uint32_t param_count
= 0;
5873 unsigned pos_idx
, num_pos_exports
= 0;
5874 struct ac_export_args args
, pos_args
[4] = {};
5875 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
5878 if (ctx
->options
->key
.has_multiview_view_index
) {
5879 LLVMValueRef
* tmp_out
= &ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5881 for(unsigned i
= 0; i
< 4; ++i
)
5882 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
5883 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5886 LLVMBuildStore(ctx
->builder
, ac_to_float(&ctx
->ac
, ctx
->view_index
), *tmp_out
);
5887 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
5890 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
5891 sizeof(outinfo
->vs_output_param_offset
));
5893 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
5894 LLVMValueRef slots
[8];
5897 if (outinfo
->cull_dist_mask
)
5898 outinfo
->cull_dist_mask
<<= ctx
->num_output_clips
;
5900 i
= VARYING_SLOT_CLIP_DIST0
;
5901 for (j
= 0; j
< ctx
->num_output_clips
+ ctx
->num_output_culls
; j
++)
5902 slots
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5903 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
5905 for (i
= ctx
->num_output_clips
+ ctx
->num_output_culls
; i
< 8; i
++)
5906 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
5908 if (ctx
->num_output_clips
+ ctx
->num_output_culls
> 4) {
5909 target
= V_008DFC_SQ_EXP_POS
+ 3;
5910 si_llvm_init_export_args(ctx
, &slots
[4], target
, &args
);
5911 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5912 &args
, sizeof(args
));
5915 target
= V_008DFC_SQ_EXP_POS
+ 2;
5916 si_llvm_init_export_args(ctx
, &slots
[0], target
, &args
);
5917 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5918 &args
, sizeof(args
));
5922 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
5923 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
5924 for (unsigned j
= 0; j
< 4; j
++)
5925 pos_values
[j
] = LLVMBuildLoad(ctx
->builder
,
5926 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_POS
, j
)], "");
5928 si_llvm_init_export_args(ctx
, pos_values
, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
5930 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
5931 outinfo
->writes_pointsize
= true;
5932 psize_value
= LLVMBuildLoad(ctx
->builder
,
5933 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ
, 0)], "");
5936 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
5937 outinfo
->writes_layer
= true;
5938 layer_value
= LLVMBuildLoad(ctx
->builder
,
5939 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)], "");
5942 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
5943 outinfo
->writes_viewport_index
= true;
5944 viewport_index_value
= LLVMBuildLoad(ctx
->builder
,
5945 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT
, 0)], "");
5948 if (outinfo
->writes_pointsize
||
5949 outinfo
->writes_layer
||
5950 outinfo
->writes_viewport_index
) {
5951 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
5952 (outinfo
->writes_layer
== true ? 4 : 0));
5953 pos_args
[1].valid_mask
= 0;
5954 pos_args
[1].done
= 0;
5955 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
5956 pos_args
[1].compr
= 0;
5957 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
5958 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
5959 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
5960 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
5962 if (outinfo
->writes_pointsize
== true)
5963 pos_args
[1].out
[0] = psize_value
;
5964 if (outinfo
->writes_layer
== true)
5965 pos_args
[1].out
[2] = layer_value
;
5966 if (outinfo
->writes_viewport_index
== true) {
5967 if (ctx
->options
->chip_class
>= GFX9
) {
5968 /* GFX9 has the layer in out.z[10:0] and the viewport
5969 * index in out.z[19:16].
5971 LLVMValueRef v
= viewport_index_value
;
5972 v
= ac_to_integer(&ctx
->ac
, v
);
5973 v
= LLVMBuildShl(ctx
->builder
, v
,
5974 LLVMConstInt(ctx
->ac
.i32
, 16, false),
5976 v
= LLVMBuildOr(ctx
->builder
, v
,
5977 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
5979 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
5980 pos_args
[1].enabled_channels
|= 1 << 2;
5982 pos_args
[1].out
[3] = viewport_index_value
;
5983 pos_args
[1].enabled_channels
|= 1 << 3;
5987 for (i
= 0; i
< 4; i
++) {
5988 if (pos_args
[i
].out
[0])
5993 for (i
= 0; i
< 4; i
++) {
5994 if (!pos_args
[i
].out
[0])
5997 /* Specify the target we are exporting */
5998 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
5999 if (pos_idx
== num_pos_exports
)
6000 pos_args
[i
].done
= 1;
6001 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
6004 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6005 LLVMValueRef values
[4];
6006 if (!(ctx
->output_mask
& (1ull << i
)))
6009 for (unsigned j
= 0; j
< 4; j
++)
6010 values
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6011 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
6013 if (i
== VARYING_SLOT_LAYER
) {
6014 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
6015 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = param_count
;
6017 } else if (i
== VARYING_SLOT_PRIMITIVE_ID
) {
6018 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
6019 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
6021 } else if (i
>= VARYING_SLOT_VAR0
) {
6022 outinfo
->export_mask
|= 1u << (i
- VARYING_SLOT_VAR0
);
6023 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
6024 outinfo
->vs_output_param_offset
[i
] = param_count
;
6029 si_llvm_init_export_args(ctx
, values
, target
, &args
);
6030 ac_build_export(&ctx
->ac
, &args
);
6033 if (export_prim_id
) {
6034 LLVMValueRef values
[4];
6035 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
6036 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
6039 values
[0] = ctx
->vs_prim_id
;
6040 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
6041 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
6042 for (unsigned j
= 1; j
< 4; j
++)
6043 values
[j
] = ctx
->ac
.f32_0
;
6044 si_llvm_init_export_args(ctx
, values
, target
, &args
);
6045 ac_build_export(&ctx
->ac
, &args
);
6046 outinfo
->export_prim_id
= true;
6049 outinfo
->pos_exports
= num_pos_exports
;
6050 outinfo
->param_exports
= param_count
;
6054 handle_es_outputs_post(struct nir_to_llvm_context
*ctx
,
6055 struct ac_es_output_info
*outinfo
)
6058 uint64_t max_output_written
= 0;
6059 LLVMValueRef lds_base
= NULL
;
6061 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6065 if (!(ctx
->output_mask
& (1ull << i
)))
6068 if (i
== VARYING_SLOT_CLIP_DIST0
)
6069 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6071 param_index
= shader_io_get_unique_index(i
);
6073 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
6076 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
6078 if (ctx
->ac
.chip_class
>= GFX9
) {
6079 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
6080 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
6081 LLVMValueRef wave_idx
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6082 LLVMConstInt(ctx
->ac
.i32
, 24, false),
6083 LLVMConstInt(ctx
->ac
.i32
, 4, false), false);
6084 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
6085 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
6086 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
6087 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
6088 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
6091 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6092 LLVMValueRef dw_addr
;
6093 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
6097 if (!(ctx
->output_mask
& (1ull << i
)))
6100 if (i
== VARYING_SLOT_CLIP_DIST0
)
6101 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6103 param_index
= shader_io_get_unique_index(i
);
6106 dw_addr
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6107 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
6110 for (j
= 0; j
< length
; j
++) {
6111 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], "");
6112 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->ac
.i32
, "");
6114 if (ctx
->ac
.chip_class
>= GFX9
) {
6115 ac_lds_store(&ctx
->ac
, dw_addr
,
6116 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
6117 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6119 ac_build_buffer_store_dword(&ctx
->ac
,
6122 NULL
, ctx
->es2gs_offset
,
6123 (4 * param_index
+ j
) * 4,
6131 handle_ls_outputs_post(struct nir_to_llvm_context
*ctx
)
6133 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
6134 LLVMValueRef vertex_dw_stride
= unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 13, 8);
6135 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->builder
, vertex_id
,
6136 vertex_dw_stride
, "");
6138 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6139 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
6142 if (!(ctx
->output_mask
& (1ull << i
)))
6145 if (i
== VARYING_SLOT_CLIP_DIST0
)
6146 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6147 int param
= shader_io_get_unique_index(i
);
6148 mark_tess_output(ctx
, false, param
);
6150 mark_tess_output(ctx
, false, param
+ 1);
6151 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->builder
, base_dw_addr
,
6152 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
6154 for (unsigned j
= 0; j
< length
; j
++) {
6155 ac_lds_store(&ctx
->ac
, dw_addr
,
6156 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
6157 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6162 struct ac_build_if_state
6164 struct nir_to_llvm_context
*ctx
;
6165 LLVMValueRef condition
;
6166 LLVMBasicBlockRef entry_block
;
6167 LLVMBasicBlockRef true_block
;
6168 LLVMBasicBlockRef false_block
;
6169 LLVMBasicBlockRef merge_block
;
6172 static LLVMBasicBlockRef
6173 ac_build_insert_new_block(struct nir_to_llvm_context
*ctx
, const char *name
)
6175 LLVMBasicBlockRef current_block
;
6176 LLVMBasicBlockRef next_block
;
6177 LLVMBasicBlockRef new_block
;
6179 /* get current basic block */
6180 current_block
= LLVMGetInsertBlock(ctx
->builder
);
6182 /* chqeck if there's another block after this one */
6183 next_block
= LLVMGetNextBasicBlock(current_block
);
6185 /* insert the new block before the next block */
6186 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
6189 /* append new block after current block */
6190 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
6191 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
6197 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
6198 struct nir_to_llvm_context
*ctx
,
6199 LLVMValueRef condition
)
6201 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->builder
);
6203 memset(ifthen
, 0, sizeof *ifthen
);
6205 ifthen
->condition
= condition
;
6206 ifthen
->entry_block
= block
;
6208 /* create endif/merge basic block for the phi functions */
6209 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
6211 /* create/insert true_block before merge_block */
6212 ifthen
->true_block
=
6213 LLVMInsertBasicBlockInContext(ctx
->context
,
6214 ifthen
->merge_block
,
6217 /* successive code goes into the true block */
6218 LLVMPositionBuilderAtEnd(ctx
->builder
, ifthen
->true_block
);
6222 * End a conditional.
6225 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
6227 LLVMBuilderRef builder
= ifthen
->ctx
->builder
;
6229 /* Insert branch to the merge block from current block */
6230 LLVMBuildBr(builder
, ifthen
->merge_block
);
6233 * Now patch in the various branch instructions.
6236 /* Insert the conditional branch instruction at the end of entry_block */
6237 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
6238 if (ifthen
->false_block
) {
6239 /* we have an else clause */
6240 LLVMBuildCondBr(builder
, ifthen
->condition
,
6241 ifthen
->true_block
, ifthen
->false_block
);
6244 /* no else clause */
6245 LLVMBuildCondBr(builder
, ifthen
->condition
,
6246 ifthen
->true_block
, ifthen
->merge_block
);
6249 /* Resume building code at end of the ifthen->merge_block */
6250 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
6254 write_tess_factors(struct nir_to_llvm_context
*ctx
)
6256 unsigned stride
, outer_comps
, inner_comps
;
6257 struct ac_build_if_state if_ctx
, inner_if_ctx
;
6258 LLVMValueRef invocation_id
= unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
6259 LLVMValueRef rel_patch_id
= unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
6260 unsigned tess_inner_index
, tess_outer_index
;
6261 LLVMValueRef lds_base
, lds_inner
, lds_outer
, byteoffset
, buffer
;
6262 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
6264 emit_barrier(&ctx
->ac
, ctx
->stage
);
6266 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
6286 ac_nir_build_if(&if_ctx
, ctx
,
6287 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
6288 invocation_id
, ctx
->ac
.i32_0
, ""));
6290 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6291 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6293 mark_tess_output(ctx
, true, tess_inner_index
);
6294 mark_tess_output(ctx
, true, tess_outer_index
);
6295 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
6296 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6297 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
6298 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6299 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
6301 for (i
= 0; i
< 4; i
++) {
6302 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6303 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6307 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
6308 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
6309 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
6311 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
6313 for (i
= 0; i
< outer_comps
; i
++) {
6315 ac_lds_load(&ctx
->ac
, lds_outer
);
6316 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
6319 for (i
= 0; i
< inner_comps
; i
++) {
6320 inner
[i
] = out
[outer_comps
+i
] =
6321 ac_lds_load(&ctx
->ac
, lds_inner
);
6322 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_inner
,
6327 /* Convert the outputs to vectors for stores. */
6328 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
6332 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
6335 buffer
= ctx
->hs_ring_tess_factor
;
6336 tf_base
= ctx
->tess_factor_offset
;
6337 byteoffset
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
6338 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
6339 unsigned tf_offset
= 0;
6341 if (ctx
->options
->chip_class
<= VI
) {
6342 ac_nir_build_if(&inner_if_ctx
, ctx
,
6343 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
6344 rel_patch_id
, ctx
->ac
.i32_0
, ""));
6346 /* Store the dynamic HS control word. */
6347 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
6348 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
6349 1, ctx
->ac
.i32_0
, tf_base
,
6350 0, 1, 0, true, false);
6353 ac_nir_build_endif(&inner_if_ctx
);
6356 /* Store the tessellation factors. */
6357 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
6358 MIN2(stride
, 4), byteoffset
, tf_base
,
6359 tf_offset
, 1, 0, true, false);
6361 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
6362 stride
- 4, byteoffset
, tf_base
,
6363 16 + tf_offset
, 1, 0, true, false);
6365 //store to offchip for TES to read - only if TES reads them
6366 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
6367 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
6368 LLVMValueRef tf_inner_offset
;
6369 unsigned param_outer
, param_inner
;
6371 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6372 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6373 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
6375 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
6376 util_next_power_of_two(outer_comps
));
6378 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
6379 outer_comps
, tf_outer_offset
,
6380 ctx
->oc_lds
, 0, 1, 0, true, false);
6382 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6383 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6384 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
6386 inner_vec
= inner_comps
== 1 ? inner
[0] :
6387 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
6388 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
6389 inner_comps
, tf_inner_offset
,
6390 ctx
->oc_lds
, 0, 1, 0, true, false);
6393 ac_nir_build_endif(&if_ctx
);
6397 handle_tcs_outputs_post(struct nir_to_llvm_context
*ctx
)
6399 write_tess_factors(ctx
);
6403 si_export_mrt_color(struct nir_to_llvm_context
*ctx
,
6404 LLVMValueRef
*color
, unsigned param
, bool is_last
,
6405 struct ac_export_args
*args
)
6408 si_llvm_init_export_args(ctx
, color
, param
,
6412 args
->valid_mask
= 1; /* whether the EXEC mask is valid */
6413 args
->done
= 1; /* DONE bit */
6414 } else if (!args
->enabled_channels
)
6415 return false; /* unnecessary NULL export */
6421 radv_export_mrt_z(struct nir_to_llvm_context
*ctx
,
6422 LLVMValueRef depth
, LLVMValueRef stencil
,
6423 LLVMValueRef samplemask
)
6425 struct ac_export_args args
;
6427 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
6429 ac_build_export(&ctx
->ac
, &args
);
6433 handle_fs_outputs_post(struct nir_to_llvm_context
*ctx
)
6436 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
6437 struct ac_export_args color_args
[8];
6439 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6440 LLVMValueRef values
[4];
6442 if (!(ctx
->output_mask
& (1ull << i
)))
6445 if (i
== FRAG_RESULT_DEPTH
) {
6446 ctx
->shader_info
->fs
.writes_z
= true;
6447 depth
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6448 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6449 } else if (i
== FRAG_RESULT_STENCIL
) {
6450 ctx
->shader_info
->fs
.writes_stencil
= true;
6451 stencil
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6452 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6453 } else if (i
== FRAG_RESULT_SAMPLE_MASK
) {
6454 ctx
->shader_info
->fs
.writes_sample_mask
= true;
6455 samplemask
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6456 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6459 for (unsigned j
= 0; j
< 4; j
++)
6460 values
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6461 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
6463 if (!ctx
->shader_info
->fs
.writes_z
&& !ctx
->shader_info
->fs
.writes_stencil
&& !ctx
->shader_info
->fs
.writes_sample_mask
)
6464 last
= ctx
->output_mask
<= ((1ull << (i
+ 1)) - 1);
6466 bool ret
= si_export_mrt_color(ctx
, values
, V_008DFC_SQ_EXP_MRT
+ (i
- FRAG_RESULT_DATA0
), last
, &color_args
[index
]);
6472 for (unsigned i
= 0; i
< index
; i
++)
6473 ac_build_export(&ctx
->ac
, &color_args
[i
]);
6474 if (depth
|| stencil
|| samplemask
)
6475 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
6477 ac_build_export_null(&ctx
->ac
);
6482 emit_gs_epilogue(struct nir_to_llvm_context
*ctx
)
6484 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
6488 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
6489 LLVMValueRef
*addrs
)
6491 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
6493 switch (ctx
->stage
) {
6494 case MESA_SHADER_VERTEX
:
6495 if (ctx
->options
->key
.vs
.as_ls
)
6496 handle_ls_outputs_post(ctx
);
6497 else if (ctx
->options
->key
.vs
.as_es
)
6498 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
6500 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
6501 &ctx
->shader_info
->vs
.outinfo
);
6503 case MESA_SHADER_FRAGMENT
:
6504 handle_fs_outputs_post(ctx
);
6506 case MESA_SHADER_GEOMETRY
:
6507 emit_gs_epilogue(ctx
);
6509 case MESA_SHADER_TESS_CTRL
:
6510 handle_tcs_outputs_post(ctx
);
6512 case MESA_SHADER_TESS_EVAL
:
6513 if (ctx
->options
->key
.tes
.as_es
)
6514 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
6516 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
6517 &ctx
->shader_info
->tes
.outinfo
);
6524 static void ac_llvm_finalize_module(struct nir_to_llvm_context
* ctx
)
6526 LLVMPassManagerRef passmgr
;
6527 /* Create the pass manager */
6528 passmgr
= LLVMCreateFunctionPassManagerForModule(
6531 /* This pass should eliminate all the load and store instructions */
6532 LLVMAddPromoteMemoryToRegisterPass(passmgr
);
6534 /* Add some optimization passes */
6535 LLVMAddScalarReplAggregatesPass(passmgr
);
6536 LLVMAddLICMPass(passmgr
);
6537 LLVMAddAggressiveDCEPass(passmgr
);
6538 LLVMAddCFGSimplificationPass(passmgr
);
6539 LLVMAddInstructionCombiningPass(passmgr
);
6542 LLVMInitializeFunctionPassManager(passmgr
);
6543 LLVMRunFunctionPassManager(passmgr
, ctx
->main_function
);
6544 LLVMFinalizeFunctionPassManager(passmgr
);
6546 LLVMDisposeBuilder(ctx
->builder
);
6547 LLVMDisposePassManager(passmgr
);
6551 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context
*ctx
)
6553 struct ac_vs_output_info
*outinfo
;
6555 switch (ctx
->stage
) {
6556 case MESA_SHADER_FRAGMENT
:
6557 case MESA_SHADER_COMPUTE
:
6558 case MESA_SHADER_TESS_CTRL
:
6559 case MESA_SHADER_GEOMETRY
:
6561 case MESA_SHADER_VERTEX
:
6562 if (ctx
->options
->key
.vs
.as_ls
||
6563 ctx
->options
->key
.vs
.as_es
)
6565 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
6567 case MESA_SHADER_TESS_EVAL
:
6568 if (ctx
->options
->key
.vs
.as_es
)
6570 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
6573 unreachable("Unhandled shader type");
6576 ac_optimize_vs_outputs(&ctx
->ac
,
6578 outinfo
->vs_output_param_offset
,
6580 &outinfo
->param_exports
);
6584 ac_setup_rings(struct nir_to_llvm_context
*ctx
)
6586 if ((ctx
->stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_es
) ||
6587 (ctx
->stage
== MESA_SHADER_TESS_EVAL
&& ctx
->options
->key
.tes
.as_es
)) {
6588 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_VS
, false));
6591 if (ctx
->is_gs_copy_shader
) {
6592 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_VS
, false));
6594 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
6596 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_GS
, false));
6597 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_GS
, false));
6599 ctx
->gsvs_ring
= LLVMBuildBitCast(ctx
->builder
, ctx
->gsvs_ring
, ctx
->ac
.v4i32
, "");
6601 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->gsvs_num_entries
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
6602 tmp
= LLVMBuildExtractElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->ac
.i32_1
, "");
6603 tmp
= LLVMBuildOr(ctx
->builder
, tmp
, ctx
->gsvs_ring_stride
, "");
6604 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, tmp
, ctx
->ac
.i32_1
, "");
6607 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
6608 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
6609 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
6610 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
6615 ac_nir_get_max_workgroup_size(enum chip_class chip_class
,
6616 const struct nir_shader
*nir
)
6618 switch (nir
->info
.stage
) {
6619 case MESA_SHADER_TESS_CTRL
:
6620 return chip_class
>= CIK
? 128 : 64;
6621 case MESA_SHADER_GEOMETRY
:
6622 return chip_class
>= GFX9
? 128 : 64;
6623 case MESA_SHADER_COMPUTE
:
6629 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
6630 nir
->info
.cs
.local_size
[1] *
6631 nir
->info
.cs
.local_size
[2];
6632 return max_workgroup_size
;
6635 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6636 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context
*ctx
)
6638 LLVMValueRef count
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6639 LLVMConstInt(ctx
->ac
.i32
, 8, false),
6640 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6641 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
6643 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
6644 ctx
->vs_prim_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.vertex_id
, ctx
->vs_prim_id
, "");
6645 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
6646 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
6649 static void prepare_gs_input_vgprs(struct nir_to_llvm_context
*ctx
)
6651 for(int i
= 5; i
>= 0; --i
) {
6652 ctx
->gs_vtx_offset
[i
] = ac_build_bfe(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
6653 LLVMConstInt(ctx
->ac
.i32
, (i
& 1) * 16, false),
6654 LLVMConstInt(ctx
->ac
.i32
, 16, false), false);
6657 ctx
->gs_wave_id
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6658 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6659 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6662 void ac_nir_translate(struct ac_llvm_context
*ac
, struct ac_shader_abi
*abi
,
6663 struct nir_shader
*nir
, struct nir_to_llvm_context
*nctx
)
6665 struct ac_nir_context ctx
= {};
6666 struct nir_function
*func
;
6675 ctx
.stage
= nir
->info
.stage
;
6677 ctx
.main_function
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6679 nir_foreach_variable(variable
, &nir
->outputs
)
6680 handle_shader_output_decl(&ctx
, nir
, variable
);
6682 ctx
.defs
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6683 _mesa_key_pointer_equal
);
6684 ctx
.phis
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6685 _mesa_key_pointer_equal
);
6686 ctx
.vars
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6687 _mesa_key_pointer_equal
);
6689 func
= (struct nir_function
*)exec_list_get_head(&nir
->functions
);
6691 setup_locals(&ctx
, func
);
6693 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
6694 setup_shared(&ctx
, nir
);
6696 visit_cf_list(&ctx
, &func
->impl
->body
);
6697 phi_post_pass(&ctx
);
6699 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
6700 ctx
.abi
->emit_outputs(ctx
.abi
, RADEON_LLVM_MAX_OUTPUTS
,
6704 ralloc_free(ctx
.defs
);
6705 ralloc_free(ctx
.phis
);
6706 ralloc_free(ctx
.vars
);
6713 LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm
,
6714 struct nir_shader
*const *shaders
,
6716 struct ac_shader_variant_info
*shader_info
,
6717 const struct ac_nir_compiler_options
*options
)
6719 struct nir_to_llvm_context ctx
= {0};
6721 ctx
.options
= options
;
6722 ctx
.shader_info
= shader_info
;
6723 ctx
.context
= LLVMContextCreate();
6724 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
6726 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
6728 ctx
.ac
.module
= ctx
.module
;
6729 LLVMSetTarget(ctx
.module
, options
->supports_spill
? "amdgcn-mesa-mesa3d" : "amdgcn--");
6731 LLVMTargetDataRef data_layout
= LLVMCreateTargetDataLayout(tm
);
6732 char *data_layout_str
= LLVMCopyStringRepOfTargetData(data_layout
);
6733 LLVMSetDataLayout(ctx
.module
, data_layout_str
);
6734 LLVMDisposeTargetData(data_layout
);
6735 LLVMDisposeMessage(data_layout_str
);
6737 enum ac_float_mode float_mode
=
6738 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
6739 AC_FLOAT_MODE_DEFAULT
;
6741 ctx
.builder
= ac_create_builder(ctx
.context
, float_mode
);
6742 ctx
.ac
.builder
= ctx
.builder
;
6744 memset(shader_info
, 0, sizeof(*shader_info
));
6746 for(int i
= 0; i
< shader_count
; ++i
)
6747 ac_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
6749 for (i
= 0; i
< AC_UD_MAX_SETS
; i
++)
6750 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
6751 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
6752 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
6754 ctx
.max_workgroup_size
= 0;
6755 for (int i
= 0; i
< shader_count
; ++i
) {
6756 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
6757 ac_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
6761 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
6762 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
6764 ctx
.abi
.inputs
= &ctx
.inputs
[0];
6765 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
6766 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
6767 ctx
.abi
.load_ubo
= radv_load_ubo
;
6768 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
6769 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
6770 ctx
.abi
.clamp_shadow_reference
= false;
6772 if (shader_count
>= 2)
6773 ac_init_exec_full_mask(&ctx
.ac
);
6775 if (ctx
.ac
.chip_class
== GFX9
&&
6776 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
6777 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
6779 for(int i
= 0; i
< shader_count
; ++i
) {
6780 ctx
.stage
= shaders
[i
]->info
.stage
;
6781 ctx
.output_mask
= 0;
6782 ctx
.tess_outputs_written
= 0;
6783 ctx
.num_output_clips
= shaders
[i
]->info
.clip_distance_array_size
;
6784 ctx
.num_output_culls
= shaders
[i
]->info
.cull_distance_array_size
;
6786 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6787 ctx
.gs_next_vertex
= ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "gs_next_vertex");
6788 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
6789 ctx
.abi
.load_inputs
= load_gs_input
;
6790 ctx
.abi
.emit_primitive
= visit_end_primitive
;
6791 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6792 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
6793 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
6794 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
6795 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
6796 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
6797 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
6798 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
6799 ctx
.abi
.load_tess_varyings
= load_tes_input
;
6800 ctx
.abi
.load_tess_coord
= load_tess_coord
;
6801 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
6802 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
6803 if (shader_info
->info
.vs
.needs_instance_id
) {
6804 if (ctx
.options
->key
.vs
.as_ls
) {
6805 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6806 MAX2(2, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6808 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6809 MAX2(1, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6812 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
6813 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
6814 ctx
.abi
.lookup_interp_param
= lookup_interp_param
;
6815 ctx
.abi
.load_sample_position
= load_sample_position
;
6819 emit_barrier(&ctx
.ac
, ctx
.stage
);
6821 ac_setup_rings(&ctx
);
6823 LLVMBasicBlockRef merge_block
;
6824 if (shader_count
>= 2) {
6825 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6826 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6827 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6829 LLVMValueRef count
= ac_build_bfe(&ctx
.ac
, ctx
.merged_wave_info
,
6830 LLVMConstInt(ctx
.ac
.i32
, 8 * i
, false),
6831 LLVMConstInt(ctx
.ac
.i32
, 8, false), false);
6832 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
6833 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
6834 thread_id
, count
, "");
6835 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
6837 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
6840 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
6841 handle_fs_inputs(&ctx
, shaders
[i
]);
6842 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
6843 handle_vs_inputs(&ctx
, shaders
[i
]);
6844 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
6845 prepare_gs_input_vgprs(&ctx
);
6847 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
6848 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
6850 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
], &ctx
);
6852 if (shader_count
>= 2) {
6853 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
6854 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
6857 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6858 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
6859 shaders
[i
]->info
.cull_distance_array_size
> 4;
6860 shader_info
->gs
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
6861 shader_info
->gs
.max_gsvs_emit_size
= shader_info
->gs
.gsvs_vertex_size
*
6862 shaders
[i
]->info
.gs
.vertices_out
;
6863 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6864 shader_info
->tcs
.outputs_written
= ctx
.tess_outputs_written
;
6865 shader_info
->tcs
.patch_outputs_written
= ctx
.tess_patch_outputs_written
;
6866 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&& ctx
.options
->key
.vs
.as_ls
) {
6867 shader_info
->vs
.outputs_written
= ctx
.tess_outputs_written
;
6871 LLVMBuildRetVoid(ctx
.builder
);
6873 if (options
->dump_preoptir
)
6874 ac_dump_module(ctx
.module
);
6876 ac_llvm_finalize_module(&ctx
);
6878 if (shader_count
== 1)
6879 ac_nir_eliminate_const_vs_outputs(&ctx
);
6884 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
6886 unsigned *retval
= (unsigned *)context
;
6887 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
6888 char *description
= LLVMGetDiagInfoDescription(di
);
6890 if (severity
== LLVMDSError
) {
6892 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
6896 LLVMDisposeMessage(description
);
6899 static unsigned ac_llvm_compile(LLVMModuleRef M
,
6900 struct ac_shader_binary
*binary
,
6901 LLVMTargetMachineRef tm
)
6903 unsigned retval
= 0;
6905 LLVMContextRef llvm_ctx
;
6906 LLVMMemoryBufferRef out_buffer
;
6907 unsigned buffer_size
;
6908 const char *buffer_data
;
6911 /* Setup Diagnostic Handler*/
6912 llvm_ctx
= LLVMGetModuleContext(M
);
6914 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
6918 mem_err
= LLVMTargetMachineEmitToMemoryBuffer(tm
, M
, LLVMObjectFile
,
6921 /* Process Errors/Warnings */
6923 fprintf(stderr
, "%s: %s", __FUNCTION__
, err
);
6929 /* Extract Shader Code*/
6930 buffer_size
= LLVMGetBufferSize(out_buffer
);
6931 buffer_data
= LLVMGetBufferStart(out_buffer
);
6933 ac_elf_read(buffer_data
, buffer_size
, binary
);
6936 LLVMDisposeMemoryBuffer(out_buffer
);
6942 static void ac_compile_llvm_module(LLVMTargetMachineRef tm
,
6943 LLVMModuleRef llvm_module
,
6944 struct ac_shader_binary
*binary
,
6945 struct ac_shader_config
*config
,
6946 struct ac_shader_variant_info
*shader_info
,
6947 gl_shader_stage stage
,
6948 bool dump_shader
, bool supports_spill
)
6951 ac_dump_module(llvm_module
);
6953 memset(binary
, 0, sizeof(*binary
));
6954 int v
= ac_llvm_compile(llvm_module
, binary
, tm
);
6956 fprintf(stderr
, "compile failed\n");
6960 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
6962 ac_shader_binary_read_config(binary
, config
, 0, supports_spill
);
6964 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
6965 LLVMDisposeModule(llvm_module
);
6966 LLVMContextDispose(ctx
);
6968 if (stage
== MESA_SHADER_FRAGMENT
) {
6969 shader_info
->num_input_vgprs
= 0;
6970 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
6971 shader_info
->num_input_vgprs
+= 2;
6972 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
6973 shader_info
->num_input_vgprs
+= 2;
6974 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
6975 shader_info
->num_input_vgprs
+= 2;
6976 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
6977 shader_info
->num_input_vgprs
+= 3;
6978 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
6979 shader_info
->num_input_vgprs
+= 2;
6980 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
6981 shader_info
->num_input_vgprs
+= 2;
6982 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
6983 shader_info
->num_input_vgprs
+= 2;
6984 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
6985 shader_info
->num_input_vgprs
+= 1;
6986 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
6987 shader_info
->num_input_vgprs
+= 1;
6988 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
6989 shader_info
->num_input_vgprs
+= 1;
6990 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
6991 shader_info
->num_input_vgprs
+= 1;
6992 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
6993 shader_info
->num_input_vgprs
+= 1;
6994 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
6995 shader_info
->num_input_vgprs
+= 1;
6996 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
6997 shader_info
->num_input_vgprs
+= 1;
6998 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
6999 shader_info
->num_input_vgprs
+= 1;
7000 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
7001 shader_info
->num_input_vgprs
+= 1;
7003 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
7005 /* +3 for scratch wave offset and VCC */
7006 config
->num_sgprs
= MAX2(config
->num_sgprs
,
7007 shader_info
->num_input_sgprs
+ 3);
7009 /* Enable 64-bit and 16-bit denormals, because there is no performance
7012 * If denormals are enabled, all floating-point output modifiers are
7015 * Don't enable denormals for 32-bit floats, because:
7016 * - Floating-point output modifiers would be ignored by the hw.
7017 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7018 * have to stop using those.
7019 * - SI & CI would be very slow.
7021 config
->float_mode
|= V_00B028_FP_64_DENORMS
;
7025 ac_fill_shader_info(struct ac_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct ac_nir_compiler_options
*options
)
7027 switch (nir
->info
.stage
) {
7028 case MESA_SHADER_COMPUTE
:
7029 for (int i
= 0; i
< 3; ++i
)
7030 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
7032 case MESA_SHADER_FRAGMENT
:
7033 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
7035 case MESA_SHADER_GEOMETRY
:
7036 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
7037 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
7038 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
7039 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
7041 case MESA_SHADER_TESS_EVAL
:
7042 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
7043 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
7044 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
7045 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
7046 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
7048 case MESA_SHADER_TESS_CTRL
:
7049 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
7051 case MESA_SHADER_VERTEX
:
7052 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
7053 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
7054 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7055 if (options
->key
.vs
.as_ls
)
7056 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
7063 void ac_compile_nir_shader(LLVMTargetMachineRef tm
,
7064 struct ac_shader_binary
*binary
,
7065 struct ac_shader_config
*config
,
7066 struct ac_shader_variant_info
*shader_info
,
7067 struct nir_shader
*const *nir
,
7069 const struct ac_nir_compiler_options
*options
,
7073 LLVMModuleRef llvm_module
= ac_translate_nir_to_llvm(tm
, nir
, nir_count
, shader_info
,
7076 ac_compile_llvm_module(tm
, llvm_module
, binary
, config
, shader_info
, nir
[0]->info
.stage
, dump_shader
, options
->supports_spill
);
7077 for (int i
= 0; i
< nir_count
; ++i
)
7078 ac_fill_shader_info(shader_info
, nir
[i
], options
);
7080 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7081 if (options
->chip_class
== GFX9
) {
7082 if (nir_count
== 2 &&
7083 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
7084 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
7090 ac_gs_copy_shader_emit(struct nir_to_llvm_context
*ctx
)
7092 LLVMValueRef vtx_offset
=
7093 LLVMBuildMul(ctx
->builder
, ctx
->abi
.vertex_id
,
7094 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
7097 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
7101 if (!(ctx
->output_mask
& (1ull << i
)))
7104 if (i
== VARYING_SLOT_CLIP_DIST0
) {
7105 /* unpack clip and cull from a single set of slots */
7106 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
7111 for (unsigned j
= 0; j
< length
; j
++) {
7112 LLVMValueRef value
, soffset
;
7114 soffset
= LLVMConstInt(ctx
->ac
.i32
,
7116 ctx
->gs_max_out_vertices
* 16 * 4, false);
7118 value
= ac_build_buffer_load(&ctx
->ac
, ctx
->gsvs_ring
,
7120 vtx_offset
, soffset
,
7121 0, 1, 1, true, false);
7123 LLVMBuildStore(ctx
->builder
,
7124 ac_to_float(&ctx
->ac
, value
), ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)]);
7128 handle_vs_outputs_post(ctx
, false, &ctx
->shader_info
->vs
.outinfo
);
7131 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm
,
7132 struct nir_shader
*geom_shader
,
7133 struct ac_shader_binary
*binary
,
7134 struct ac_shader_config
*config
,
7135 struct ac_shader_variant_info
*shader_info
,
7136 const struct ac_nir_compiler_options
*options
,
7139 struct nir_to_llvm_context ctx
= {0};
7140 ctx
.context
= LLVMContextCreate();
7141 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
7142 ctx
.options
= options
;
7143 ctx
.shader_info
= shader_info
;
7145 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
7147 ctx
.ac
.module
= ctx
.module
;
7149 ctx
.is_gs_copy_shader
= true;
7150 LLVMSetTarget(ctx
.module
, "amdgcn--");
7152 enum ac_float_mode float_mode
=
7153 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
7154 AC_FLOAT_MODE_DEFAULT
;
7156 ctx
.builder
= ac_create_builder(ctx
.context
, float_mode
);
7157 ctx
.ac
.builder
= ctx
.builder
;
7158 ctx
.stage
= MESA_SHADER_VERTEX
;
7160 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
7162 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
7163 ac_setup_rings(&ctx
);
7165 ctx
.num_output_clips
= geom_shader
->info
.clip_distance_array_size
;
7166 ctx
.num_output_culls
= geom_shader
->info
.cull_distance_array_size
;
7168 struct ac_nir_context nir_ctx
= {};
7169 nir_ctx
.ac
= ctx
.ac
;
7170 nir_ctx
.abi
= &ctx
.abi
;
7172 nir_ctx
.nctx
= &ctx
;
7175 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
7176 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
7177 handle_shader_output_decl(&nir_ctx
, geom_shader
, variable
);
7180 ac_gs_copy_shader_emit(&ctx
);
7184 LLVMBuildRetVoid(ctx
.builder
);
7186 ac_llvm_finalize_module(&ctx
);
7188 ac_compile_llvm_module(tm
, ctx
.module
, binary
, config
, shader_info
,
7190 dump_shader
, options
->supports_spill
);