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[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct ac_nir_context {
49 struct ac_llvm_context ac;
50 struct ac_shader_abi *abi;
51
52 gl_shader_stage stage;
53
54 struct hash_table *defs;
55 struct hash_table *phis;
56 struct hash_table *vars;
57
58 LLVMValueRef main_function;
59 LLVMBasicBlockRef continue_block;
60 LLVMBasicBlockRef break_block;
61
62 int num_locals;
63 LLVMValueRef *locals;
64 };
65
66 struct radv_shader_context {
67 struct ac_llvm_context ac;
68 const struct ac_nir_compiler_options *options;
69 struct ac_shader_variant_info *shader_info;
70 struct ac_shader_abi abi;
71
72 unsigned max_workgroup_size;
73 LLVMContextRef context;
74 LLVMValueRef main_function;
75
76 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
77 LLVMValueRef ring_offsets;
78
79 LLVMValueRef vertex_buffers;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef ls_out_layout;
83 LLVMValueRef es2gs_offset;
84
85 LLVMValueRef tcs_offchip_layout;
86 LLVMValueRef tcs_out_offsets;
87 LLVMValueRef tcs_out_layout;
88 LLVMValueRef tcs_in_layout;
89 LLVMValueRef oc_lds;
90 LLVMValueRef merged_wave_info;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tes_rel_patch_id;
93 LLVMValueRef tes_u;
94 LLVMValueRef tes_v;
95
96 LLVMValueRef gsvs_ring_stride;
97 LLVMValueRef gsvs_num_entries;
98 LLVMValueRef gs2vs_offset;
99 LLVMValueRef gs_wave_id;
100 LLVMValueRef gs_vtx_offset[6];
101
102 LLVMValueRef esgs_ring;
103 LLVMValueRef gsvs_ring;
104 LLVMValueRef hs_ring_tess_offchip;
105 LLVMValueRef hs_ring_tess_factor;
106
107 LLVMValueRef sample_pos_offset;
108 LLVMValueRef persp_sample, persp_center, persp_centroid;
109 LLVMValueRef linear_sample, linear_center, linear_centroid;
110
111 gl_shader_stage stage;
112
113 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
114
115 uint64_t input_mask;
116 uint64_t output_mask;
117 uint8_t num_output_clips;
118 uint8_t num_output_culls;
119
120 bool is_gs_copy_shader;
121 LLVMValueRef gs_next_vertex;
122 unsigned gs_max_out_vertices;
123
124 unsigned tes_primitive_mode;
125 uint64_t tess_outputs_written;
126 uint64_t tess_patch_outputs_written;
127
128 uint32_t tcs_patch_outputs_read;
129 uint64_t tcs_outputs_read;
130 uint32_t tcs_vertices_per_patch;
131 };
132
133 static inline struct radv_shader_context *
134 radv_shader_context_from_abi(struct ac_shader_abi *abi)
135 {
136 struct radv_shader_context *ctx = NULL;
137 return container_of(abi, ctx, abi);
138 }
139
140 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
141 const nir_deref_var *deref,
142 enum ac_descriptor_type desc_type,
143 const nir_tex_instr *instr,
144 bool image, bool write);
145
146 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
147 {
148 return (index * 4) + chan;
149 }
150
151 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
152 {
153 /* handle patch indices separate */
154 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
155 return 0;
156 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
157 return 1;
158 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
159 return 2 + (slot - VARYING_SLOT_PATCH0);
160
161 if (slot == VARYING_SLOT_POS)
162 return 0;
163 if (slot == VARYING_SLOT_PSIZ)
164 return 1;
165 if (slot == VARYING_SLOT_CLIP_DIST0)
166 return 2;
167 /* 3 is reserved for clip dist as well */
168 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
169 return 4 + (slot - VARYING_SLOT_VAR0);
170 unreachable("illegal slot in get unique index\n");
171 }
172
173 static void set_llvm_calling_convention(LLVMValueRef func,
174 gl_shader_stage stage)
175 {
176 enum radeon_llvm_calling_convention calling_conv;
177
178 switch (stage) {
179 case MESA_SHADER_VERTEX:
180 case MESA_SHADER_TESS_EVAL:
181 calling_conv = RADEON_LLVM_AMDGPU_VS;
182 break;
183 case MESA_SHADER_GEOMETRY:
184 calling_conv = RADEON_LLVM_AMDGPU_GS;
185 break;
186 case MESA_SHADER_TESS_CTRL:
187 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
188 break;
189 case MESA_SHADER_FRAGMENT:
190 calling_conv = RADEON_LLVM_AMDGPU_PS;
191 break;
192 case MESA_SHADER_COMPUTE:
193 calling_conv = RADEON_LLVM_AMDGPU_CS;
194 break;
195 default:
196 unreachable("Unhandle shader type");
197 }
198
199 LLVMSetFunctionCallConv(func, calling_conv);
200 }
201
202 #define MAX_ARGS 23
203 struct arg_info {
204 LLVMTypeRef types[MAX_ARGS];
205 LLVMValueRef *assign[MAX_ARGS];
206 unsigned array_params_mask;
207 uint8_t count;
208 uint8_t sgpr_count;
209 uint8_t num_sgprs_used;
210 uint8_t num_vgprs_used;
211 };
212
213 enum ac_arg_regfile {
214 ARG_SGPR,
215 ARG_VGPR,
216 };
217
218 static void
219 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
220 LLVMValueRef *param_ptr)
221 {
222 assert(info->count < MAX_ARGS);
223
224 info->assign[info->count] = param_ptr;
225 info->types[info->count] = type;
226 info->count++;
227
228 if (regfile == ARG_SGPR) {
229 info->num_sgprs_used += ac_get_type_size(type) / 4;
230 info->sgpr_count++;
231 } else {
232 assert(regfile == ARG_VGPR);
233 info->num_vgprs_used += ac_get_type_size(type) / 4;
234 }
235 }
236
237 static inline void
238 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
239 {
240 info->array_params_mask |= (1 << info->count);
241 add_arg(info, ARG_SGPR, type, param_ptr);
242 }
243
244 static void assign_arguments(LLVMValueRef main_function,
245 struct arg_info *info)
246 {
247 unsigned i;
248 for (i = 0; i < info->count; i++) {
249 if (info->assign[i])
250 *info->assign[i] = LLVMGetParam(main_function, i);
251 }
252 }
253
254 static LLVMValueRef
255 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
256 LLVMBuilderRef builder, LLVMTypeRef *return_types,
257 unsigned num_return_elems,
258 struct arg_info *args,
259 unsigned max_workgroup_size,
260 bool unsafe_math)
261 {
262 LLVMTypeRef main_function_type, ret_type;
263 LLVMBasicBlockRef main_function_body;
264
265 if (num_return_elems)
266 ret_type = LLVMStructTypeInContext(ctx, return_types,
267 num_return_elems, true);
268 else
269 ret_type = LLVMVoidTypeInContext(ctx);
270
271 /* Setup the function */
272 main_function_type =
273 LLVMFunctionType(ret_type, args->types, args->count, 0);
274 LLVMValueRef main_function =
275 LLVMAddFunction(module, "main", main_function_type);
276 main_function_body =
277 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
278 LLVMPositionBuilderAtEnd(builder, main_function_body);
279
280 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
281 for (unsigned i = 0; i < args->sgpr_count; ++i) {
282 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
283
284 if (args->array_params_mask & (1 << i)) {
285 LLVMValueRef P = LLVMGetParam(main_function, i);
286 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
287 ac_add_attr_dereferenceable(P, UINT64_MAX);
288 }
289 }
290
291 if (max_workgroup_size) {
292 ac_llvm_add_target_dep_function_attr(main_function,
293 "amdgpu-max-work-group-size",
294 max_workgroup_size);
295 }
296 if (unsafe_math) {
297 /* These were copied from some LLVM test. */
298 LLVMAddTargetDependentFunctionAttr(main_function,
299 "less-precise-fpmad",
300 "true");
301 LLVMAddTargetDependentFunctionAttr(main_function,
302 "no-infs-fp-math",
303 "true");
304 LLVMAddTargetDependentFunctionAttr(main_function,
305 "no-nans-fp-math",
306 "true");
307 LLVMAddTargetDependentFunctionAttr(main_function,
308 "unsafe-fp-math",
309 "true");
310 LLVMAddTargetDependentFunctionAttr(main_function,
311 "no-signed-zeros-fp-math",
312 "true");
313 }
314 return main_function;
315 }
316
317 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
318 {
319 switch (ctx->stage) {
320 case MESA_SHADER_TESS_CTRL:
321 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
322 case MESA_SHADER_TESS_EVAL:
323 return ctx->tes_rel_patch_id;
324 break;
325 default:
326 unreachable("Illegal stage");
327 }
328 }
329
330 /* Tessellation shaders pass outputs to the next shader using LDS.
331 *
332 * LS outputs = TCS inputs
333 * TCS outputs = TES inputs
334 *
335 * The LDS layout is:
336 * - TCS inputs for patch 0
337 * - TCS inputs for patch 1
338 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
339 * - ...
340 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
341 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
342 * - TCS outputs for patch 1
343 * - Per-patch TCS outputs for patch 1
344 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
345 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
346 * - ...
347 *
348 * All three shaders VS(LS), TCS, TES share the same LDS space.
349 */
350 static LLVMValueRef
351 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
352 {
353 if (ctx->stage == MESA_SHADER_VERTEX)
354 return ac_unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
355 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
356 return ac_unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
357 else {
358 assert(0);
359 return NULL;
360 }
361 }
362
363 static LLVMValueRef
364 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
365 {
366 return ac_unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
367 }
368
369 static LLVMValueRef
370 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
371 {
372 return ac_unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
373 }
374
375 static LLVMValueRef
376 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
377 {
378 return LLVMBuildMul(ctx->ac.builder,
379 ac_unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
380 LLVMConstInt(ctx->ac.i32, 4, false), "");
381 }
382
383 static LLVMValueRef
384 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
385 {
386 return LLVMBuildMul(ctx->ac.builder,
387 ac_unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
388 LLVMConstInt(ctx->ac.i32, 4, false), "");
389 }
390
391 static LLVMValueRef
392 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
393 {
394 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
395 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
396
397 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
398 }
399
400 static LLVMValueRef
401 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
402 {
403 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
404 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
405 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
406
407 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
408 LLVMBuildMul(ctx->ac.builder, patch_stride,
409 rel_patch_id, ""),
410 "");
411 }
412
413 static LLVMValueRef
414 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
415 {
416 LLVMValueRef patch0_patch_data_offset =
417 get_tcs_out_patch0_patch_data_offset(ctx);
418 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
419 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
420
421 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
422 LLVMBuildMul(ctx->ac.builder, patch_stride,
423 rel_patch_id, ""),
424 "");
425 }
426
427 static void
428 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
429 uint32_t indirect_offset)
430 {
431 ud_info->sgpr_idx = *sgpr_idx;
432 ud_info->num_sgprs = num_sgprs;
433 ud_info->indirect = indirect_offset > 0;
434 ud_info->indirect_offset = indirect_offset;
435 *sgpr_idx += num_sgprs;
436 }
437
438 static void
439 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
440 uint8_t num_sgprs)
441 {
442 struct ac_userdata_info *ud_info =
443 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
444 assert(ud_info);
445
446 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
447 }
448
449 static void
450 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
451 uint32_t indirect_offset)
452 {
453 struct ac_userdata_info *ud_info =
454 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
455 assert(ud_info);
456
457 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
458 }
459
460 struct user_sgpr_info {
461 bool need_ring_offsets;
462 uint8_t sgpr_count;
463 bool indirect_all_descriptor_sets;
464 };
465
466 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
467 gl_shader_stage stage)
468 {
469 switch (stage) {
470 case MESA_SHADER_VERTEX:
471 if (ctx->shader_info->info.needs_multiview_view_index ||
472 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
473 return true;
474 break;
475 case MESA_SHADER_TESS_EVAL:
476 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
477 return true;
478 break;
479 case MESA_SHADER_GEOMETRY:
480 case MESA_SHADER_TESS_CTRL:
481 if (ctx->shader_info->info.needs_multiview_view_index)
482 return true;
483 break;
484 default:
485 break;
486 }
487 return false;
488 }
489
490 static uint8_t
491 count_vs_user_sgprs(struct radv_shader_context *ctx)
492 {
493 uint8_t count = 0;
494
495 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
496 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
497
498 return count;
499 }
500
501 static void allocate_user_sgprs(struct radv_shader_context *ctx,
502 gl_shader_stage stage,
503 bool has_previous_stage,
504 gl_shader_stage previous_stage,
505 bool needs_view_index,
506 struct user_sgpr_info *user_sgpr_info)
507 {
508 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
509
510 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
511 if (stage == MESA_SHADER_GEOMETRY ||
512 stage == MESA_SHADER_VERTEX ||
513 stage == MESA_SHADER_TESS_CTRL ||
514 stage == MESA_SHADER_TESS_EVAL ||
515 ctx->is_gs_copy_shader)
516 user_sgpr_info->need_ring_offsets = true;
517
518 if (stage == MESA_SHADER_FRAGMENT &&
519 ctx->shader_info->info.ps.needs_sample_positions)
520 user_sgpr_info->need_ring_offsets = true;
521
522 /* 2 user sgprs will nearly always be allocated for scratch/rings */
523 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
524 user_sgpr_info->sgpr_count += 2;
525 }
526
527 switch (stage) {
528 case MESA_SHADER_COMPUTE:
529 if (ctx->shader_info->info.cs.uses_grid_size)
530 user_sgpr_info->sgpr_count += 3;
531 break;
532 case MESA_SHADER_FRAGMENT:
533 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
534 break;
535 case MESA_SHADER_VERTEX:
536 if (!ctx->is_gs_copy_shader)
537 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
538 if (ctx->options->key.vs.as_ls)
539 user_sgpr_info->sgpr_count++;
540 break;
541 case MESA_SHADER_TESS_CTRL:
542 if (has_previous_stage) {
543 if (previous_stage == MESA_SHADER_VERTEX)
544 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
545 user_sgpr_info->sgpr_count++;
546 }
547 user_sgpr_info->sgpr_count += 4;
548 break;
549 case MESA_SHADER_TESS_EVAL:
550 user_sgpr_info->sgpr_count += 1;
551 break;
552 case MESA_SHADER_GEOMETRY:
553 if (has_previous_stage) {
554 if (previous_stage == MESA_SHADER_VERTEX) {
555 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
556 } else {
557 user_sgpr_info->sgpr_count++;
558 }
559 }
560 user_sgpr_info->sgpr_count += 2;
561 break;
562 default:
563 break;
564 }
565
566 if (needs_view_index)
567 user_sgpr_info->sgpr_count++;
568
569 if (ctx->shader_info->info.loads_push_constants)
570 user_sgpr_info->sgpr_count += 2;
571
572 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
573 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
574
575 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
576 user_sgpr_info->sgpr_count += 2;
577 user_sgpr_info->indirect_all_descriptor_sets = true;
578 } else {
579 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
580 }
581 }
582
583 static void
584 declare_global_input_sgprs(struct radv_shader_context *ctx,
585 gl_shader_stage stage,
586 bool has_previous_stage,
587 gl_shader_stage previous_stage,
588 const struct user_sgpr_info *user_sgpr_info,
589 struct arg_info *args,
590 LLVMValueRef *desc_sets)
591 {
592 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
593 unsigned num_sets = ctx->options->layout ?
594 ctx->options->layout->num_sets : 0;
595 unsigned stage_mask = 1 << stage;
596
597 if (has_previous_stage)
598 stage_mask |= 1 << previous_stage;
599
600 /* 1 for each descriptor set */
601 if (!user_sgpr_info->indirect_all_descriptor_sets) {
602 for (unsigned i = 0; i < num_sets; ++i) {
603 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
604 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
605 add_array_arg(args, type,
606 &ctx->descriptor_sets[i]);
607 }
608 }
609 } else {
610 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
611 }
612
613 if (ctx->shader_info->info.loads_push_constants) {
614 /* 1 for push constants and dynamic descriptors */
615 add_array_arg(args, type, &ctx->abi.push_constants);
616 }
617 }
618
619 static void
620 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
621 gl_shader_stage stage,
622 bool has_previous_stage,
623 gl_shader_stage previous_stage,
624 struct arg_info *args)
625 {
626 if (!ctx->is_gs_copy_shader &&
627 (stage == MESA_SHADER_VERTEX ||
628 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
629 if (ctx->shader_info->info.vs.has_vertex_buffers) {
630 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
631 &ctx->vertex_buffers);
632 }
633 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
634 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
635 if (ctx->shader_info->info.vs.needs_draw_id) {
636 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
637 }
638 }
639 }
640
641 static void
642 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
643 {
644 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
645 if (!ctx->is_gs_copy_shader) {
646 if (ctx->options->key.vs.as_ls) {
647 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
648 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
649 } else {
650 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
651 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
652 }
653 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
654 }
655 }
656
657 static void
658 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
659 {
660 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
661 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
662 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
663 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
664 }
665
666 static void
667 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
668 bool has_previous_stage, gl_shader_stage previous_stage,
669 const struct user_sgpr_info *user_sgpr_info,
670 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
671 {
672 unsigned num_sets = ctx->options->layout ?
673 ctx->options->layout->num_sets : 0;
674 unsigned stage_mask = 1 << stage;
675
676 if (has_previous_stage)
677 stage_mask |= 1 << previous_stage;
678
679 if (!user_sgpr_info->indirect_all_descriptor_sets) {
680 for (unsigned i = 0; i < num_sets; ++i) {
681 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
682 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
683 set_loc_desc(ctx, i, user_sgpr_idx, 0);
684 } else
685 ctx->descriptor_sets[i] = NULL;
686 }
687 } else {
688 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
689 user_sgpr_idx, 2);
690
691 for (unsigned i = 0; i < num_sets; ++i) {
692 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
693 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
694 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
695 ctx->descriptor_sets[i] =
696 ac_build_load_to_sgpr(&ctx->ac,
697 desc_sets,
698 LLVMConstInt(ctx->ac.i32, i, false));
699
700 } else
701 ctx->descriptor_sets[i] = NULL;
702 }
703 ctx->shader_info->need_indirect_descriptor_sets = true;
704 }
705
706 if (ctx->shader_info->info.loads_push_constants) {
707 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
708 }
709 }
710
711 static void
712 set_vs_specific_input_locs(struct radv_shader_context *ctx,
713 gl_shader_stage stage, bool has_previous_stage,
714 gl_shader_stage previous_stage,
715 uint8_t *user_sgpr_idx)
716 {
717 if (!ctx->is_gs_copy_shader &&
718 (stage == MESA_SHADER_VERTEX ||
719 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
720 if (ctx->shader_info->info.vs.has_vertex_buffers) {
721 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
722 user_sgpr_idx, 2);
723 }
724
725 unsigned vs_num = 2;
726 if (ctx->shader_info->info.vs.needs_draw_id)
727 vs_num++;
728
729 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
730 user_sgpr_idx, vs_num);
731 }
732 }
733
734 static void create_function(struct radv_shader_context *ctx,
735 gl_shader_stage stage,
736 bool has_previous_stage,
737 gl_shader_stage previous_stage)
738 {
739 uint8_t user_sgpr_idx;
740 struct user_sgpr_info user_sgpr_info;
741 struct arg_info args = {};
742 LLVMValueRef desc_sets;
743 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
744 allocate_user_sgprs(ctx, stage, has_previous_stage,
745 previous_stage, needs_view_index, &user_sgpr_info);
746
747 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
748 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
749 &ctx->ring_offsets);
750 }
751
752 switch (stage) {
753 case MESA_SHADER_COMPUTE:
754 declare_global_input_sgprs(ctx, stage, has_previous_stage,
755 previous_stage, &user_sgpr_info,
756 &args, &desc_sets);
757
758 if (ctx->shader_info->info.cs.uses_grid_size) {
759 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
760 &ctx->abi.num_work_groups);
761 }
762
763 for (int i = 0; i < 3; i++) {
764 ctx->abi.workgroup_ids[i] = NULL;
765 if (ctx->shader_info->info.cs.uses_block_id[i]) {
766 add_arg(&args, ARG_SGPR, ctx->ac.i32,
767 &ctx->abi.workgroup_ids[i]);
768 }
769 }
770
771 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
772 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
773 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
774 &ctx->abi.local_invocation_ids);
775 break;
776 case MESA_SHADER_VERTEX:
777 declare_global_input_sgprs(ctx, stage, has_previous_stage,
778 previous_stage, &user_sgpr_info,
779 &args, &desc_sets);
780 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
781 previous_stage, &args);
782
783 if (needs_view_index)
784 add_arg(&args, ARG_SGPR, ctx->ac.i32,
785 &ctx->abi.view_index);
786 if (ctx->options->key.vs.as_es)
787 add_arg(&args, ARG_SGPR, ctx->ac.i32,
788 &ctx->es2gs_offset);
789 else if (ctx->options->key.vs.as_ls)
790 add_arg(&args, ARG_SGPR, ctx->ac.i32,
791 &ctx->ls_out_layout);
792
793 declare_vs_input_vgprs(ctx, &args);
794 break;
795 case MESA_SHADER_TESS_CTRL:
796 if (has_previous_stage) {
797 // First 6 system regs
798 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
799 add_arg(&args, ARG_SGPR, ctx->ac.i32,
800 &ctx->merged_wave_info);
801 add_arg(&args, ARG_SGPR, ctx->ac.i32,
802 &ctx->tess_factor_offset);
803
804 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
805 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
806 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
807
808 declare_global_input_sgprs(ctx, stage,
809 has_previous_stage,
810 previous_stage,
811 &user_sgpr_info, &args,
812 &desc_sets);
813 declare_vs_specific_input_sgprs(ctx, stage,
814 has_previous_stage,
815 previous_stage, &args);
816
817 add_arg(&args, ARG_SGPR, ctx->ac.i32,
818 &ctx->ls_out_layout);
819
820 add_arg(&args, ARG_SGPR, ctx->ac.i32,
821 &ctx->tcs_offchip_layout);
822 add_arg(&args, ARG_SGPR, ctx->ac.i32,
823 &ctx->tcs_out_offsets);
824 add_arg(&args, ARG_SGPR, ctx->ac.i32,
825 &ctx->tcs_out_layout);
826 add_arg(&args, ARG_SGPR, ctx->ac.i32,
827 &ctx->tcs_in_layout);
828 if (needs_view_index)
829 add_arg(&args, ARG_SGPR, ctx->ac.i32,
830 &ctx->abi.view_index);
831
832 add_arg(&args, ARG_VGPR, ctx->ac.i32,
833 &ctx->abi.tcs_patch_id);
834 add_arg(&args, ARG_VGPR, ctx->ac.i32,
835 &ctx->abi.tcs_rel_ids);
836
837 declare_vs_input_vgprs(ctx, &args);
838 } else {
839 declare_global_input_sgprs(ctx, stage,
840 has_previous_stage,
841 previous_stage,
842 &user_sgpr_info, &args,
843 &desc_sets);
844
845 add_arg(&args, ARG_SGPR, ctx->ac.i32,
846 &ctx->tcs_offchip_layout);
847 add_arg(&args, ARG_SGPR, ctx->ac.i32,
848 &ctx->tcs_out_offsets);
849 add_arg(&args, ARG_SGPR, ctx->ac.i32,
850 &ctx->tcs_out_layout);
851 add_arg(&args, ARG_SGPR, ctx->ac.i32,
852 &ctx->tcs_in_layout);
853 if (needs_view_index)
854 add_arg(&args, ARG_SGPR, ctx->ac.i32,
855 &ctx->abi.view_index);
856
857 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
858 add_arg(&args, ARG_SGPR, ctx->ac.i32,
859 &ctx->tess_factor_offset);
860 add_arg(&args, ARG_VGPR, ctx->ac.i32,
861 &ctx->abi.tcs_patch_id);
862 add_arg(&args, ARG_VGPR, ctx->ac.i32,
863 &ctx->abi.tcs_rel_ids);
864 }
865 break;
866 case MESA_SHADER_TESS_EVAL:
867 declare_global_input_sgprs(ctx, stage, has_previous_stage,
868 previous_stage, &user_sgpr_info,
869 &args, &desc_sets);
870
871 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
872 if (needs_view_index)
873 add_arg(&args, ARG_SGPR, ctx->ac.i32,
874 &ctx->abi.view_index);
875
876 if (ctx->options->key.tes.as_es) {
877 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
878 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
879 add_arg(&args, ARG_SGPR, ctx->ac.i32,
880 &ctx->es2gs_offset);
881 } else {
882 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
883 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
884 }
885 declare_tes_input_vgprs(ctx, &args);
886 break;
887 case MESA_SHADER_GEOMETRY:
888 if (has_previous_stage) {
889 // First 6 system regs
890 add_arg(&args, ARG_SGPR, ctx->ac.i32,
891 &ctx->gs2vs_offset);
892 add_arg(&args, ARG_SGPR, ctx->ac.i32,
893 &ctx->merged_wave_info);
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
895
896 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
897 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
898 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
899
900 declare_global_input_sgprs(ctx, stage,
901 has_previous_stage,
902 previous_stage,
903 &user_sgpr_info, &args,
904 &desc_sets);
905
906 if (previous_stage == MESA_SHADER_TESS_EVAL) {
907 add_arg(&args, ARG_SGPR, ctx->ac.i32,
908 &ctx->tcs_offchip_layout);
909 } else {
910 declare_vs_specific_input_sgprs(ctx, stage,
911 has_previous_stage,
912 previous_stage,
913 &args);
914 }
915
916 add_arg(&args, ARG_SGPR, ctx->ac.i32,
917 &ctx->gsvs_ring_stride);
918 add_arg(&args, ARG_SGPR, ctx->ac.i32,
919 &ctx->gsvs_num_entries);
920 if (needs_view_index)
921 add_arg(&args, ARG_SGPR, ctx->ac.i32,
922 &ctx->abi.view_index);
923
924 add_arg(&args, ARG_VGPR, ctx->ac.i32,
925 &ctx->gs_vtx_offset[0]);
926 add_arg(&args, ARG_VGPR, ctx->ac.i32,
927 &ctx->gs_vtx_offset[2]);
928 add_arg(&args, ARG_VGPR, ctx->ac.i32,
929 &ctx->abi.gs_prim_id);
930 add_arg(&args, ARG_VGPR, ctx->ac.i32,
931 &ctx->abi.gs_invocation_id);
932 add_arg(&args, ARG_VGPR, ctx->ac.i32,
933 &ctx->gs_vtx_offset[4]);
934
935 if (previous_stage == MESA_SHADER_VERTEX) {
936 declare_vs_input_vgprs(ctx, &args);
937 } else {
938 declare_tes_input_vgprs(ctx, &args);
939 }
940 } else {
941 declare_global_input_sgprs(ctx, stage,
942 has_previous_stage,
943 previous_stage,
944 &user_sgpr_info, &args,
945 &desc_sets);
946
947 add_arg(&args, ARG_SGPR, ctx->ac.i32,
948 &ctx->gsvs_ring_stride);
949 add_arg(&args, ARG_SGPR, ctx->ac.i32,
950 &ctx->gsvs_num_entries);
951 if (needs_view_index)
952 add_arg(&args, ARG_SGPR, ctx->ac.i32,
953 &ctx->abi.view_index);
954
955 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
956 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
957 add_arg(&args, ARG_VGPR, ctx->ac.i32,
958 &ctx->gs_vtx_offset[0]);
959 add_arg(&args, ARG_VGPR, ctx->ac.i32,
960 &ctx->gs_vtx_offset[1]);
961 add_arg(&args, ARG_VGPR, ctx->ac.i32,
962 &ctx->abi.gs_prim_id);
963 add_arg(&args, ARG_VGPR, ctx->ac.i32,
964 &ctx->gs_vtx_offset[2]);
965 add_arg(&args, ARG_VGPR, ctx->ac.i32,
966 &ctx->gs_vtx_offset[3]);
967 add_arg(&args, ARG_VGPR, ctx->ac.i32,
968 &ctx->gs_vtx_offset[4]);
969 add_arg(&args, ARG_VGPR, ctx->ac.i32,
970 &ctx->gs_vtx_offset[5]);
971 add_arg(&args, ARG_VGPR, ctx->ac.i32,
972 &ctx->abi.gs_invocation_id);
973 }
974 break;
975 case MESA_SHADER_FRAGMENT:
976 declare_global_input_sgprs(ctx, stage, has_previous_stage,
977 previous_stage, &user_sgpr_info,
978 &args, &desc_sets);
979
980 if (ctx->shader_info->info.ps.needs_sample_positions)
981 add_arg(&args, ARG_SGPR, ctx->ac.i32,
982 &ctx->sample_pos_offset);
983
984 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
985 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
986 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
987 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
988 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
989 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
990 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
991 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
992 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
993 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
994 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
995 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
996 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
997 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
998 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
999 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1000 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1001 break;
1002 default:
1003 unreachable("Shader stage not implemented");
1004 }
1005
1006 ctx->main_function = create_llvm_function(
1007 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1008 ctx->max_workgroup_size,
1009 ctx->options->unsafe_math);
1010 set_llvm_calling_convention(ctx->main_function, stage);
1011
1012
1013 ctx->shader_info->num_input_vgprs = 0;
1014 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1015
1016 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1017
1018 if (ctx->stage != MESA_SHADER_FRAGMENT)
1019 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1020
1021 assign_arguments(ctx->main_function, &args);
1022
1023 user_sgpr_idx = 0;
1024
1025 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1026 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1027 &user_sgpr_idx, 2);
1028 if (ctx->options->supports_spill) {
1029 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1030 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1031 NULL, 0, AC_FUNC_ATTR_READNONE);
1032 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1033 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1034 }
1035 }
1036
1037 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1038 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1039 if (has_previous_stage)
1040 user_sgpr_idx = 0;
1041
1042 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1043 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1044
1045 switch (stage) {
1046 case MESA_SHADER_COMPUTE:
1047 if (ctx->shader_info->info.cs.uses_grid_size) {
1048 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1049 &user_sgpr_idx, 3);
1050 }
1051 break;
1052 case MESA_SHADER_VERTEX:
1053 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1054 previous_stage, &user_sgpr_idx);
1055 if (ctx->abi.view_index)
1056 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1057 if (ctx->options->key.vs.as_ls) {
1058 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1059 &user_sgpr_idx, 1);
1060 }
1061 break;
1062 case MESA_SHADER_TESS_CTRL:
1063 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1064 previous_stage, &user_sgpr_idx);
1065 if (has_previous_stage)
1066 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1067 &user_sgpr_idx, 1);
1068 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1069 if (ctx->abi.view_index)
1070 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1071 break;
1072 case MESA_SHADER_TESS_EVAL:
1073 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1074 if (ctx->abi.view_index)
1075 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1076 break;
1077 case MESA_SHADER_GEOMETRY:
1078 if (has_previous_stage) {
1079 if (previous_stage == MESA_SHADER_VERTEX)
1080 set_vs_specific_input_locs(ctx, stage,
1081 has_previous_stage,
1082 previous_stage,
1083 &user_sgpr_idx);
1084 else
1085 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1086 &user_sgpr_idx, 1);
1087 }
1088 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1089 &user_sgpr_idx, 2);
1090 if (ctx->abi.view_index)
1091 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1092 break;
1093 case MESA_SHADER_FRAGMENT:
1094 if (ctx->shader_info->info.ps.needs_sample_positions) {
1095 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1096 &user_sgpr_idx, 1);
1097 }
1098 break;
1099 default:
1100 unreachable("Shader stage not implemented");
1101 }
1102
1103 if (stage == MESA_SHADER_TESS_CTRL ||
1104 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1105 /* GFX9 has the ESGS ring buffer in LDS. */
1106 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1107 ac_declare_lds_as_pointer(&ctx->ac);
1108 }
1109
1110 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1111 }
1112
1113 static void
1114 build_store_values_extended(struct ac_llvm_context *ac,
1115 LLVMValueRef *values,
1116 unsigned value_count,
1117 unsigned value_stride,
1118 LLVMValueRef vec)
1119 {
1120 LLVMBuilderRef builder = ac->builder;
1121 unsigned i;
1122
1123 for (i = 0; i < value_count; i++) {
1124 LLVMValueRef ptr = values[i * value_stride];
1125 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1126 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1127 LLVMBuildStore(builder, value, ptr);
1128 }
1129 }
1130
1131 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1132 const nir_ssa_def *def)
1133 {
1134 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1135 if (def->num_components > 1) {
1136 type = LLVMVectorType(type, def->num_components);
1137 }
1138 return type;
1139 }
1140
1141 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1142 {
1143 assert(src.is_ssa);
1144 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1145 return (LLVMValueRef)entry->data;
1146 }
1147
1148 static LLVMValueRef
1149 get_memory_ptr(struct ac_nir_context *ctx, nir_src src)
1150 {
1151 LLVMValueRef ptr = get_src(ctx, src);
1152 ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ac.lds, &ptr, 1, "");
1153 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1154
1155 return LLVMBuildBitCast(ctx->ac.builder, ptr,
1156 LLVMPointerType(ctx->ac.i32, addr_space), "");
1157 }
1158
1159 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1160 const struct nir_block *b)
1161 {
1162 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1163 return (LLVMBasicBlockRef)entry->data;
1164 }
1165
1166 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1167 nir_alu_src src,
1168 unsigned num_components)
1169 {
1170 LLVMValueRef value = get_src(ctx, src.src);
1171 bool need_swizzle = false;
1172
1173 assert(value);
1174 unsigned src_components = ac_get_llvm_num_components(value);
1175 for (unsigned i = 0; i < num_components; ++i) {
1176 assert(src.swizzle[i] < src_components);
1177 if (src.swizzle[i] != i)
1178 need_swizzle = true;
1179 }
1180
1181 if (need_swizzle || num_components != src_components) {
1182 LLVMValueRef masks[] = {
1183 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1184 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1185 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1186 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1187
1188 if (src_components > 1 && num_components == 1) {
1189 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1190 masks[0], "");
1191 } else if (src_components == 1 && num_components > 1) {
1192 LLVMValueRef values[] = {value, value, value, value};
1193 value = ac_build_gather_values(&ctx->ac, values, num_components);
1194 } else {
1195 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1196 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1197 swizzle, "");
1198 }
1199 }
1200 assert(!src.negate);
1201 assert(!src.abs);
1202 return value;
1203 }
1204
1205 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1206 LLVMIntPredicate pred, LLVMValueRef src0,
1207 LLVMValueRef src1)
1208 {
1209 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1210 return LLVMBuildSelect(ctx->builder, result,
1211 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1212 ctx->i32_0, "");
1213 }
1214
1215 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1216 LLVMRealPredicate pred, LLVMValueRef src0,
1217 LLVMValueRef src1)
1218 {
1219 LLVMValueRef result;
1220 src0 = ac_to_float(ctx, src0);
1221 src1 = ac_to_float(ctx, src1);
1222 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1223 return LLVMBuildSelect(ctx->builder, result,
1224 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1225 ctx->i32_0, "");
1226 }
1227
1228 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1229 const char *intrin,
1230 LLVMTypeRef result_type,
1231 LLVMValueRef src0)
1232 {
1233 char name[64];
1234 LLVMValueRef params[] = {
1235 ac_to_float(ctx, src0),
1236 };
1237
1238 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1239 ac_get_elem_bits(ctx, result_type));
1240 assert(length < sizeof(name));
1241 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1242 }
1243
1244 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1245 const char *intrin,
1246 LLVMTypeRef result_type,
1247 LLVMValueRef src0, LLVMValueRef src1)
1248 {
1249 char name[64];
1250 LLVMValueRef params[] = {
1251 ac_to_float(ctx, src0),
1252 ac_to_float(ctx, src1),
1253 };
1254
1255 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1256 ac_get_elem_bits(ctx, result_type));
1257 assert(length < sizeof(name));
1258 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1259 }
1260
1261 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1262 const char *intrin,
1263 LLVMTypeRef result_type,
1264 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1265 {
1266 char name[64];
1267 LLVMValueRef params[] = {
1268 ac_to_float(ctx, src0),
1269 ac_to_float(ctx, src1),
1270 ac_to_float(ctx, src2),
1271 };
1272
1273 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1274 ac_get_elem_bits(ctx, result_type));
1275 assert(length < sizeof(name));
1276 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1277 }
1278
1279 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1280 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1281 {
1282 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1283 ctx->i32_0, "");
1284 return LLVMBuildSelect(ctx->builder, v, ac_to_integer(ctx, src1),
1285 ac_to_integer(ctx, src2), "");
1286 }
1287
1288 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1289 LLVMIntPredicate pred,
1290 LLVMValueRef src0, LLVMValueRef src1)
1291 {
1292 return LLVMBuildSelect(ctx->builder,
1293 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1294 src0,
1295 src1, "");
1296
1297 }
1298 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1299 LLVMValueRef src0)
1300 {
1301 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1302 LLVMBuildNeg(ctx->builder, src0, ""));
1303 }
1304
1305 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1306 const char *intrin,
1307 LLVMValueRef src0, LLVMValueRef src1)
1308 {
1309 LLVMTypeRef ret_type;
1310 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1311 LLVMValueRef res;
1312 LLVMValueRef params[] = { src0, src1 };
1313 ret_type = LLVMStructTypeInContext(ctx->context, types,
1314 2, true);
1315
1316 res = ac_build_intrinsic(ctx, intrin, ret_type,
1317 params, 2, AC_FUNC_ATTR_READNONE);
1318
1319 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1320 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1321 return res;
1322 }
1323
1324 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1325 LLVMValueRef src0)
1326 {
1327 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1328 }
1329
1330 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1331 LLVMValueRef src0)
1332 {
1333 src0 = ac_to_float(ctx, src0);
1334 LLVMValueRef zero = LLVMConstNull(LLVMTypeOf(src0));
1335 return LLVMBuildSExt(ctx->builder,
1336 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, zero, ""),
1337 ctx->i32, "");
1338 }
1339
1340 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1341 LLVMValueRef src0,
1342 unsigned bitsize)
1343 {
1344 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1345
1346 if (bitsize == 32)
1347 return result;
1348
1349 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1350 }
1351
1352 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1353 LLVMValueRef src0)
1354 {
1355 LLVMValueRef zero = LLVMConstNull(LLVMTypeOf(src0));
1356 return LLVMBuildSExt(ctx->builder,
1357 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, zero, ""),
1358 ctx->i32, "");
1359 }
1360
1361 static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx,
1362 LLVMValueRef src0)
1363 {
1364 LLVMValueRef result;
1365 LLVMValueRef cond = NULL;
1366
1367 src0 = ac_to_float(ctx, src0);
1368 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1369
1370 if (ctx->chip_class >= VI) {
1371 LLVMValueRef args[2];
1372 /* Check if the result is a denormal - and flush to 0 if so. */
1373 args[0] = result;
1374 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1375 cond = ac_build_intrinsic(ctx, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1376 }
1377
1378 /* need to convert back up to f32 */
1379 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1380
1381 if (ctx->chip_class >= VI)
1382 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1383 else {
1384 /* for SI/CIK */
1385 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1386 * so compare the result and flush to 0 if it's smaller.
1387 */
1388 LLVMValueRef temp, cond2;
1389 temp = emit_intrin_1f_param(ctx, "llvm.fabs", ctx->f32, result);
1390 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1391 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1392 temp, "");
1393 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1394 temp, ctx->f32_0, "");
1395 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1396 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1397 }
1398 return result;
1399 }
1400
1401 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1402 LLVMValueRef src0, LLVMValueRef src1)
1403 {
1404 LLVMValueRef dst64, result;
1405 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1406 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1407
1408 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1409 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1410 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1411 return result;
1412 }
1413
1414 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1415 LLVMValueRef src0, LLVMValueRef src1)
1416 {
1417 LLVMValueRef dst64, result;
1418 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1419 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1420
1421 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1422 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1423 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1424 return result;
1425 }
1426
1427 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1428 bool is_signed,
1429 const LLVMValueRef srcs[3])
1430 {
1431 LLVMValueRef result;
1432 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1433
1434 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1435 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1436 return result;
1437 }
1438
1439 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1440 LLVMValueRef src0, LLVMValueRef src1,
1441 LLVMValueRef src2, LLVMValueRef src3)
1442 {
1443 LLVMValueRef bfi_args[3], result;
1444
1445 bfi_args[0] = LLVMBuildShl(ctx->builder,
1446 LLVMBuildSub(ctx->builder,
1447 LLVMBuildShl(ctx->builder,
1448 ctx->i32_1,
1449 src3, ""),
1450 ctx->i32_1, ""),
1451 src2, "");
1452 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1453 bfi_args[2] = src0;
1454
1455 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1456
1457 /* Calculate:
1458 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1459 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1460 */
1461 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1462 LLVMBuildAnd(ctx->builder, bfi_args[0],
1463 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1464
1465 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1466 return result;
1467 }
1468
1469 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1470 LLVMValueRef src0)
1471 {
1472 LLVMValueRef comp[2];
1473
1474 src0 = ac_to_float(ctx, src0);
1475 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1476 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1477
1478 return ac_build_cvt_pkrtz_f16(ctx, comp);
1479 }
1480
1481 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1482 LLVMValueRef src0)
1483 {
1484 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1485 LLVMValueRef temps[2], result, val;
1486 int i;
1487
1488 for (i = 0; i < 2; i++) {
1489 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1490 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1491 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1492 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1493 }
1494
1495 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1496 ctx->i32_0, "");
1497 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1498 ctx->i32_1, "");
1499 return result;
1500 }
1501
1502 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1503 nir_op op,
1504 LLVMValueRef src0)
1505 {
1506 unsigned mask;
1507 int idx;
1508 LLVMValueRef result;
1509
1510 if (op == nir_op_fddx_fine)
1511 mask = AC_TID_MASK_LEFT;
1512 else if (op == nir_op_fddy_fine)
1513 mask = AC_TID_MASK_TOP;
1514 else
1515 mask = AC_TID_MASK_TOP_LEFT;
1516
1517 /* for DDX we want to next X pixel, DDY next Y pixel. */
1518 if (op == nir_op_fddx_fine ||
1519 op == nir_op_fddx_coarse ||
1520 op == nir_op_fddx)
1521 idx = 1;
1522 else
1523 idx = 2;
1524
1525 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1526 return result;
1527 }
1528
1529 /*
1530 * this takes an I,J coordinate pair,
1531 * and works out the X and Y derivatives.
1532 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1533 */
1534 static LLVMValueRef emit_ddxy_interp(
1535 struct ac_nir_context *ctx,
1536 LLVMValueRef interp_ij)
1537 {
1538 LLVMValueRef result[4], a;
1539 unsigned i;
1540
1541 for (i = 0; i < 2; i++) {
1542 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1543 LLVMConstInt(ctx->ac.i32, i, false), "");
1544 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1545 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1546 }
1547 return ac_build_gather_values(&ctx->ac, result, 4);
1548 }
1549
1550 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1551 {
1552 LLVMValueRef src[4], result = NULL;
1553 unsigned num_components = instr->dest.dest.ssa.num_components;
1554 unsigned src_components;
1555 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1556
1557 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1558 switch (instr->op) {
1559 case nir_op_vec2:
1560 case nir_op_vec3:
1561 case nir_op_vec4:
1562 src_components = 1;
1563 break;
1564 case nir_op_pack_half_2x16:
1565 src_components = 2;
1566 break;
1567 case nir_op_unpack_half_2x16:
1568 src_components = 1;
1569 break;
1570 case nir_op_cube_face_coord:
1571 case nir_op_cube_face_index:
1572 src_components = 3;
1573 break;
1574 default:
1575 src_components = num_components;
1576 break;
1577 }
1578 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1579 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1580
1581 switch (instr->op) {
1582 case nir_op_fmov:
1583 case nir_op_imov:
1584 result = src[0];
1585 break;
1586 case nir_op_fneg:
1587 src[0] = ac_to_float(&ctx->ac, src[0]);
1588 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1589 break;
1590 case nir_op_ineg:
1591 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1592 break;
1593 case nir_op_inot:
1594 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1595 break;
1596 case nir_op_iadd:
1597 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1598 break;
1599 case nir_op_fadd:
1600 src[0] = ac_to_float(&ctx->ac, src[0]);
1601 src[1] = ac_to_float(&ctx->ac, src[1]);
1602 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1603 break;
1604 case nir_op_fsub:
1605 src[0] = ac_to_float(&ctx->ac, src[0]);
1606 src[1] = ac_to_float(&ctx->ac, src[1]);
1607 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1608 break;
1609 case nir_op_isub:
1610 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1611 break;
1612 case nir_op_imul:
1613 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1614 break;
1615 case nir_op_imod:
1616 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1617 break;
1618 case nir_op_umod:
1619 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1620 break;
1621 case nir_op_fmod:
1622 src[0] = ac_to_float(&ctx->ac, src[0]);
1623 src[1] = ac_to_float(&ctx->ac, src[1]);
1624 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1625 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1626 ac_to_float_type(&ctx->ac, def_type), result);
1627 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1628 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1629 break;
1630 case nir_op_frem:
1631 src[0] = ac_to_float(&ctx->ac, src[0]);
1632 src[1] = ac_to_float(&ctx->ac, src[1]);
1633 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1634 break;
1635 case nir_op_irem:
1636 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1637 break;
1638 case nir_op_idiv:
1639 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1640 break;
1641 case nir_op_udiv:
1642 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1643 break;
1644 case nir_op_fmul:
1645 src[0] = ac_to_float(&ctx->ac, src[0]);
1646 src[1] = ac_to_float(&ctx->ac, src[1]);
1647 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1648 break;
1649 case nir_op_frcp:
1650 src[0] = ac_to_float(&ctx->ac, src[0]);
1651 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1652 src[0]);
1653 break;
1654 case nir_op_iand:
1655 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1656 break;
1657 case nir_op_ior:
1658 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1659 break;
1660 case nir_op_ixor:
1661 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1662 break;
1663 case nir_op_ishl:
1664 result = LLVMBuildShl(ctx->ac.builder, src[0],
1665 LLVMBuildZExt(ctx->ac.builder, src[1],
1666 LLVMTypeOf(src[0]), ""),
1667 "");
1668 break;
1669 case nir_op_ishr:
1670 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1671 LLVMBuildZExt(ctx->ac.builder, src[1],
1672 LLVMTypeOf(src[0]), ""),
1673 "");
1674 break;
1675 case nir_op_ushr:
1676 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1677 LLVMBuildZExt(ctx->ac.builder, src[1],
1678 LLVMTypeOf(src[0]), ""),
1679 "");
1680 break;
1681 case nir_op_ilt:
1682 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1683 break;
1684 case nir_op_ine:
1685 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1686 break;
1687 case nir_op_ieq:
1688 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1689 break;
1690 case nir_op_ige:
1691 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1692 break;
1693 case nir_op_ult:
1694 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1695 break;
1696 case nir_op_uge:
1697 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1698 break;
1699 case nir_op_feq:
1700 result = emit_float_cmp(&ctx->ac, LLVMRealOEQ, src[0], src[1]);
1701 break;
1702 case nir_op_fne:
1703 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1704 break;
1705 case nir_op_flt:
1706 result = emit_float_cmp(&ctx->ac, LLVMRealOLT, src[0], src[1]);
1707 break;
1708 case nir_op_fge:
1709 result = emit_float_cmp(&ctx->ac, LLVMRealOGE, src[0], src[1]);
1710 break;
1711 case nir_op_fabs:
1712 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1713 ac_to_float_type(&ctx->ac, def_type), src[0]);
1714 break;
1715 case nir_op_iabs:
1716 result = emit_iabs(&ctx->ac, src[0]);
1717 break;
1718 case nir_op_imax:
1719 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1720 break;
1721 case nir_op_imin:
1722 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1723 break;
1724 case nir_op_umax:
1725 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1726 break;
1727 case nir_op_umin:
1728 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1729 break;
1730 case nir_op_isign:
1731 result = ac_build_isign(&ctx->ac, src[0],
1732 instr->dest.dest.ssa.bit_size);
1733 break;
1734 case nir_op_fsign:
1735 src[0] = ac_to_float(&ctx->ac, src[0]);
1736 result = ac_build_fsign(&ctx->ac, src[0],
1737 instr->dest.dest.ssa.bit_size);
1738 break;
1739 case nir_op_ffloor:
1740 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1741 ac_to_float_type(&ctx->ac, def_type), src[0]);
1742 break;
1743 case nir_op_ftrunc:
1744 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1745 ac_to_float_type(&ctx->ac, def_type), src[0]);
1746 break;
1747 case nir_op_fceil:
1748 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1749 ac_to_float_type(&ctx->ac, def_type), src[0]);
1750 break;
1751 case nir_op_fround_even:
1752 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1753 ac_to_float_type(&ctx->ac, def_type),src[0]);
1754 break;
1755 case nir_op_ffract:
1756 src[0] = ac_to_float(&ctx->ac, src[0]);
1757 result = ac_build_fract(&ctx->ac, src[0],
1758 instr->dest.dest.ssa.bit_size);
1759 break;
1760 case nir_op_fsin:
1761 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1762 ac_to_float_type(&ctx->ac, def_type), src[0]);
1763 break;
1764 case nir_op_fcos:
1765 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1766 ac_to_float_type(&ctx->ac, def_type), src[0]);
1767 break;
1768 case nir_op_fsqrt:
1769 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1770 ac_to_float_type(&ctx->ac, def_type), src[0]);
1771 break;
1772 case nir_op_fexp2:
1773 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1774 ac_to_float_type(&ctx->ac, def_type), src[0]);
1775 break;
1776 case nir_op_flog2:
1777 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1778 ac_to_float_type(&ctx->ac, def_type), src[0]);
1779 break;
1780 case nir_op_frsq:
1781 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1782 ac_to_float_type(&ctx->ac, def_type), src[0]);
1783 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1784 result);
1785 break;
1786 case nir_op_fmax:
1787 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1788 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1789 if (ctx->ac.chip_class < GFX9 &&
1790 instr->dest.dest.ssa.bit_size == 32) {
1791 /* Only pre-GFX9 chips do not flush denorms. */
1792 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1793 ac_to_float_type(&ctx->ac, def_type),
1794 result);
1795 }
1796 break;
1797 case nir_op_fmin:
1798 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1799 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1800 if (ctx->ac.chip_class < GFX9 &&
1801 instr->dest.dest.ssa.bit_size == 32) {
1802 /* Only pre-GFX9 chips do not flush denorms. */
1803 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1804 ac_to_float_type(&ctx->ac, def_type),
1805 result);
1806 }
1807 break;
1808 case nir_op_ffma:
1809 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1810 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1811 break;
1812 case nir_op_ldexp:
1813 src[0] = ac_to_float(&ctx->ac, src[0]);
1814 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1815 result = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ldexp.f32", ctx->ac.f32, src, 2, AC_FUNC_ATTR_READNONE);
1816 else
1817 result = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ldexp.f64", ctx->ac.f64, src, 2, AC_FUNC_ATTR_READNONE);
1818 break;
1819 case nir_op_ibitfield_extract:
1820 result = emit_bitfield_extract(&ctx->ac, true, src);
1821 break;
1822 case nir_op_ubitfield_extract:
1823 result = emit_bitfield_extract(&ctx->ac, false, src);
1824 break;
1825 case nir_op_bitfield_insert:
1826 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1827 break;
1828 case nir_op_bitfield_reverse:
1829 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1830 break;
1831 case nir_op_bit_count:
1832 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1833 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1834 else {
1835 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1836 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1837 }
1838 break;
1839 case nir_op_vec2:
1840 case nir_op_vec3:
1841 case nir_op_vec4:
1842 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1843 src[i] = ac_to_integer(&ctx->ac, src[i]);
1844 result = ac_build_gather_values(&ctx->ac, src, num_components);
1845 break;
1846 case nir_op_f2i32:
1847 case nir_op_f2i64:
1848 src[0] = ac_to_float(&ctx->ac, src[0]);
1849 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1850 break;
1851 case nir_op_f2u32:
1852 case nir_op_f2u64:
1853 src[0] = ac_to_float(&ctx->ac, src[0]);
1854 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1855 break;
1856 case nir_op_i2f32:
1857 case nir_op_i2f64:
1858 src[0] = ac_to_integer(&ctx->ac, src[0]);
1859 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1860 break;
1861 case nir_op_u2f32:
1862 case nir_op_u2f64:
1863 src[0] = ac_to_integer(&ctx->ac, src[0]);
1864 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1865 break;
1866 case nir_op_f2f64:
1867 src[0] = ac_to_float(&ctx->ac, src[0]);
1868 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1869 break;
1870 case nir_op_f2f32:
1871 src[0] = ac_to_float(&ctx->ac, src[0]);
1872 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1873 break;
1874 case nir_op_u2u32:
1875 case nir_op_u2u64:
1876 src[0] = ac_to_integer(&ctx->ac, src[0]);
1877 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1878 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1879 else
1880 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1881 break;
1882 case nir_op_i2i32:
1883 case nir_op_i2i64:
1884 src[0] = ac_to_integer(&ctx->ac, src[0]);
1885 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1886 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1887 else
1888 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1889 break;
1890 case nir_op_bcsel:
1891 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1892 break;
1893 case nir_op_find_lsb:
1894 src[0] = ac_to_integer(&ctx->ac, src[0]);
1895 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1896 break;
1897 case nir_op_ufind_msb:
1898 src[0] = ac_to_integer(&ctx->ac, src[0]);
1899 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1900 break;
1901 case nir_op_ifind_msb:
1902 src[0] = ac_to_integer(&ctx->ac, src[0]);
1903 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1904 break;
1905 case nir_op_uadd_carry:
1906 src[0] = ac_to_integer(&ctx->ac, src[0]);
1907 src[1] = ac_to_integer(&ctx->ac, src[1]);
1908 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1909 break;
1910 case nir_op_usub_borrow:
1911 src[0] = ac_to_integer(&ctx->ac, src[0]);
1912 src[1] = ac_to_integer(&ctx->ac, src[1]);
1913 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1914 break;
1915 case nir_op_b2f:
1916 result = emit_b2f(&ctx->ac, src[0]);
1917 break;
1918 case nir_op_f2b:
1919 result = emit_f2b(&ctx->ac, src[0]);
1920 break;
1921 case nir_op_b2i:
1922 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1923 break;
1924 case nir_op_i2b:
1925 src[0] = ac_to_integer(&ctx->ac, src[0]);
1926 result = emit_i2b(&ctx->ac, src[0]);
1927 break;
1928 case nir_op_fquantize2f16:
1929 result = emit_f2f16(&ctx->ac, src[0]);
1930 break;
1931 case nir_op_umul_high:
1932 src[0] = ac_to_integer(&ctx->ac, src[0]);
1933 src[1] = ac_to_integer(&ctx->ac, src[1]);
1934 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1935 break;
1936 case nir_op_imul_high:
1937 src[0] = ac_to_integer(&ctx->ac, src[0]);
1938 src[1] = ac_to_integer(&ctx->ac, src[1]);
1939 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1940 break;
1941 case nir_op_pack_half_2x16:
1942 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1943 break;
1944 case nir_op_unpack_half_2x16:
1945 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1946 break;
1947 case nir_op_fddx:
1948 case nir_op_fddy:
1949 case nir_op_fddx_fine:
1950 case nir_op_fddy_fine:
1951 case nir_op_fddx_coarse:
1952 case nir_op_fddy_coarse:
1953 result = emit_ddxy(ctx, instr->op, src[0]);
1954 break;
1955
1956 case nir_op_unpack_64_2x32_split_x: {
1957 assert(ac_get_llvm_num_components(src[0]) == 1);
1958 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1959 ctx->ac.v2i32,
1960 "");
1961 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1962 ctx->ac.i32_0, "");
1963 break;
1964 }
1965
1966 case nir_op_unpack_64_2x32_split_y: {
1967 assert(ac_get_llvm_num_components(src[0]) == 1);
1968 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1969 ctx->ac.v2i32,
1970 "");
1971 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1972 ctx->ac.i32_1, "");
1973 break;
1974 }
1975
1976 case nir_op_pack_64_2x32_split: {
1977 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
1978 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1979 src[0], ctx->ac.i32_0, "");
1980 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1981 src[1], ctx->ac.i32_1, "");
1982 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1983 break;
1984 }
1985
1986 case nir_op_cube_face_coord: {
1987 src[0] = ac_to_float(&ctx->ac, src[0]);
1988 LLVMValueRef results[2];
1989 LLVMValueRef in[3];
1990 for (unsigned chan = 0; chan < 3; chan++)
1991 in[chan] = ac_llvm_extract_elem(&ctx->ac, src[0], chan);
1992 results[0] = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.cubetc",
1993 ctx->ac.f32, in, 3, AC_FUNC_ATTR_READNONE);
1994 results[1] = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.cubesc",
1995 ctx->ac.f32, in, 3, AC_FUNC_ATTR_READNONE);
1996 result = ac_build_gather_values(&ctx->ac, results, 2);
1997 break;
1998 }
1999
2000 case nir_op_cube_face_index: {
2001 src[0] = ac_to_float(&ctx->ac, src[0]);
2002 LLVMValueRef in[3];
2003 for (unsigned chan = 0; chan < 3; chan++)
2004 in[chan] = ac_llvm_extract_elem(&ctx->ac, src[0], chan);
2005 result = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.cubeid",
2006 ctx->ac.f32, in, 3, AC_FUNC_ATTR_READNONE);
2007 break;
2008 }
2009
2010 default:
2011 fprintf(stderr, "Unknown NIR alu instr: ");
2012 nir_print_instr(&instr->instr, stderr);
2013 fprintf(stderr, "\n");
2014 abort();
2015 }
2016
2017 if (result) {
2018 assert(instr->dest.dest.is_ssa);
2019 result = ac_to_integer(&ctx->ac, result);
2020 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2021 result);
2022 }
2023 }
2024
2025 static void visit_load_const(struct ac_nir_context *ctx,
2026 const nir_load_const_instr *instr)
2027 {
2028 LLVMValueRef values[4], value = NULL;
2029 LLVMTypeRef element_type =
2030 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2031
2032 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2033 switch (instr->def.bit_size) {
2034 case 32:
2035 values[i] = LLVMConstInt(element_type,
2036 instr->value.u32[i], false);
2037 break;
2038 case 64:
2039 values[i] = LLVMConstInt(element_type,
2040 instr->value.u64[i], false);
2041 break;
2042 default:
2043 fprintf(stderr,
2044 "unsupported nir load_const bit_size: %d\n",
2045 instr->def.bit_size);
2046 abort();
2047 }
2048 }
2049 if (instr->def.num_components > 1) {
2050 value = LLVMConstVector(values, instr->def.num_components);
2051 } else
2052 value = values[0];
2053
2054 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2055 }
2056
2057 static LLVMValueRef
2058 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2059 {
2060 LLVMValueRef size =
2061 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2062 LLVMConstInt(ctx->ac.i32, 2, false), "");
2063
2064 /* VI only */
2065 if (ctx->ac.chip_class == VI && in_elements) {
2066 /* On VI, the descriptor contains the size in bytes,
2067 * but TXQ must return the size in elements.
2068 * The stride is always non-zero for resources using TXQ.
2069 */
2070 LLVMValueRef stride =
2071 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2072 ctx->ac.i32_1, "");
2073 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2074 LLVMConstInt(ctx->ac.i32, 16, false), "");
2075 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2076 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2077
2078 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2079 }
2080 return size;
2081 }
2082
2083 /**
2084 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2085 * intrinsic names).
2086 */
2087 static void build_int_type_name(
2088 LLVMTypeRef type,
2089 char *buf, unsigned bufsize)
2090 {
2091 assert(bufsize >= 6);
2092
2093 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2094 snprintf(buf, bufsize, "v%ui32",
2095 LLVMGetVectorSize(type));
2096 else
2097 strcpy(buf, "i32");
2098 }
2099
2100 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2101 struct ac_image_args *args,
2102 const nir_tex_instr *instr)
2103 {
2104 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2105 LLVMValueRef coord = args->addr;
2106 LLVMValueRef half_texel[2];
2107 LLVMValueRef compare_cube_wa = NULL;
2108 LLVMValueRef result;
2109 int c;
2110 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2111
2112 //TODO Rect
2113 {
2114 struct ac_image_args txq_args = { 0 };
2115
2116 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2117 txq_args.opcode = ac_image_get_resinfo;
2118 txq_args.dmask = 0xf;
2119 txq_args.addr = ctx->i32_0;
2120 txq_args.resource = args->resource;
2121 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2122
2123 for (c = 0; c < 2; c++) {
2124 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2125 LLVMConstInt(ctx->i32, c, false), "");
2126 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2127 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2128 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2129 LLVMConstReal(ctx->f32, -0.5), "");
2130 }
2131 }
2132
2133 LLVMValueRef orig_coords = args->addr;
2134
2135 for (c = 0; c < 2; c++) {
2136 LLVMValueRef tmp;
2137 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2138 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2139 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2140 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2141 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2142 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2143 }
2144
2145
2146 /*
2147 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2148 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2149 * workaround by sampling using a scaled type and converting.
2150 * This is taken from amdgpu-pro shaders.
2151 */
2152 /* NOTE this produces some ugly code compared to amdgpu-pro,
2153 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2154 * and then reads them back. -pro generates two selects,
2155 * one s_cmp for the descriptor rewriting
2156 * one v_cmp for the coordinate and result changes.
2157 */
2158 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2159 LLVMValueRef tmp, tmp2;
2160
2161 /* workaround 8/8/8/8 uint/sint cube gather bug */
2162 /* first detect it then change to a scaled read and f2i */
2163 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2164 tmp2 = tmp;
2165
2166 /* extract the DATA_FORMAT */
2167 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2168 LLVMConstInt(ctx->i32, 6, false), false);
2169
2170 /* is the DATA_FORMAT == 8_8_8_8 */
2171 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2172
2173 if (stype == GLSL_TYPE_UINT)
2174 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2175 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2176 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2177 else
2178 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2179 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2180 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2181
2182 /* replace the NUM FORMAT in the descriptor */
2183 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2184 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2185
2186 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2187
2188 /* don't modify the coordinates for this case */
2189 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2190 }
2191 args->addr = coord;
2192 result = ac_build_image_opcode(ctx, args);
2193
2194 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2195 LLVMValueRef tmp, tmp2;
2196
2197 /* if the cube workaround is in place, f2i the result. */
2198 for (c = 0; c < 4; c++) {
2199 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2200 if (stype == GLSL_TYPE_UINT)
2201 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2202 else
2203 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2204 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2205 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2206 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2207 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2208 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2209 }
2210 }
2211 return result;
2212 }
2213
2214 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2215 const nir_tex_instr *instr,
2216 bool lod_is_zero,
2217 struct ac_image_args *args)
2218 {
2219 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2220 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2221
2222 return ac_build_buffer_load_format(&ctx->ac,
2223 args->resource,
2224 args->addr,
2225 ctx->ac.i32_0,
2226 util_last_bit(mask),
2227 false, true);
2228 }
2229
2230 args->opcode = ac_image_sample;
2231 args->compare = instr->is_shadow;
2232
2233 switch (instr->op) {
2234 case nir_texop_txf:
2235 case nir_texop_txf_ms:
2236 case nir_texop_samples_identical:
2237 args->opcode = lod_is_zero ||
2238 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2239 ac_image_load : ac_image_load_mip;
2240 args->compare = false;
2241 args->offset = false;
2242 break;
2243 case nir_texop_txb:
2244 args->bias = true;
2245 break;
2246 case nir_texop_txl:
2247 if (lod_is_zero)
2248 args->level_zero = true;
2249 else
2250 args->lod = true;
2251 break;
2252 case nir_texop_txs:
2253 case nir_texop_query_levels:
2254 args->opcode = ac_image_get_resinfo;
2255 break;
2256 case nir_texop_tex:
2257 if (ctx->stage != MESA_SHADER_FRAGMENT)
2258 args->level_zero = true;
2259 break;
2260 case nir_texop_txd:
2261 args->deriv = true;
2262 break;
2263 case nir_texop_tg4:
2264 args->opcode = ac_image_gather4;
2265 args->level_zero = true;
2266 break;
2267 case nir_texop_lod:
2268 args->opcode = ac_image_get_lod;
2269 args->compare = false;
2270 args->offset = false;
2271 break;
2272 default:
2273 break;
2274 }
2275
2276 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2277 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2278 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2279 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2280 }
2281 }
2282 return ac_build_image_opcode(&ctx->ac, args);
2283 }
2284
2285 static LLVMValueRef
2286 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2287 unsigned desc_set, unsigned binding)
2288 {
2289 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2290 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2291 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2292 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2293 unsigned base_offset = layout->binding[binding].offset;
2294 LLVMValueRef offset, stride;
2295
2296 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2297 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2298 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2299 layout->binding[binding].dynamic_offset_offset;
2300 desc_ptr = ctx->abi.push_constants;
2301 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2302 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2303 } else
2304 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2305
2306 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2307 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
2308 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
2309
2310 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2311 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
2312 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2313
2314 return desc_ptr;
2315 }
2316
2317 static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
2318 nir_intrinsic_instr *instr)
2319 {
2320 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2321 LLVMValueRef index = get_src(ctx, instr->src[1]);
2322
2323 LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
2324 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2325 return result;
2326 }
2327
2328 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
2329 nir_intrinsic_instr *instr)
2330 {
2331 LLVMValueRef ptr, addr;
2332
2333 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2334 addr = LLVMBuildAdd(ctx->ac.builder, addr,
2335 get_src(ctx, instr->src[0]), "");
2336
2337 ptr = ac_build_gep0(&ctx->ac, ctx->abi->push_constants, addr);
2338 ptr = ac_cast_ptr(&ctx->ac, ptr, get_def_type(ctx, &instr->dest.ssa));
2339
2340 return LLVMBuildLoad(ctx->ac.builder, ptr, "");
2341 }
2342
2343 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2344 const nir_intrinsic_instr *instr)
2345 {
2346 LLVMValueRef index = get_src(ctx, instr->src[0]);
2347
2348 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2349 }
2350
2351 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2352 {
2353 uint32_t new_mask = 0;
2354 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2355 if (mask & (1u << i))
2356 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2357 return new_mask;
2358 }
2359
2360 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2361 unsigned start, unsigned count)
2362 {
2363 LLVMTypeRef type = LLVMTypeOf(src);
2364
2365 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2366 assert(start == 0);
2367 assert(count == 1);
2368 return src;
2369 }
2370
2371 unsigned src_elements = LLVMGetVectorSize(type);
2372 assert(start < src_elements);
2373 assert(start + count <= src_elements);
2374
2375 if (start == 0 && count == src_elements)
2376 return src;
2377
2378 if (count == 1)
2379 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2380
2381 assert(count <= 8);
2382 LLVMValueRef indices[8];
2383 for (unsigned i = 0; i < count; ++i)
2384 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2385
2386 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2387 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2388 }
2389
2390 static void visit_store_ssbo(struct ac_nir_context *ctx,
2391 nir_intrinsic_instr *instr)
2392 {
2393 const char *store_name;
2394 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2395 LLVMTypeRef data_type = ctx->ac.f32;
2396 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2397 int components_32bit = elem_size_mult * instr->num_components;
2398 unsigned writemask = nir_intrinsic_write_mask(instr);
2399 LLVMValueRef base_data, base_offset;
2400 LLVMValueRef params[6];
2401
2402 params[1] = ctx->abi->load_ssbo(ctx->abi,
2403 get_src(ctx, instr->src[1]), true);
2404 params[2] = ctx->ac.i32_0; /* vindex */
2405 params[4] = ctx->ac.i1false; /* glc */
2406 params[5] = ctx->ac.i1false; /* slc */
2407
2408 if (components_32bit > 1)
2409 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2410
2411 writemask = widen_mask(writemask, elem_size_mult);
2412
2413 base_data = ac_to_float(&ctx->ac, src_data);
2414 base_data = ac_trim_vector(&ctx->ac, base_data, instr->num_components);
2415 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2416 data_type, "");
2417 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2418 while (writemask) {
2419 int start, count;
2420 LLVMValueRef data;
2421 LLVMValueRef offset;
2422
2423 u_bit_scan_consecutive_range(&writemask, &start, &count);
2424
2425 /* Due to an LLVM limitation, split 3-element writes
2426 * into a 2-element and a 1-element write. */
2427 if (count == 3) {
2428 writemask |= 1 << (start + 2);
2429 count = 2;
2430 }
2431
2432 if (count > 4) {
2433 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2434 count = 4;
2435 }
2436
2437 if (count == 4) {
2438 store_name = "llvm.amdgcn.buffer.store.v4f32";
2439 } else if (count == 2) {
2440 store_name = "llvm.amdgcn.buffer.store.v2f32";
2441
2442 } else {
2443 assert(count == 1);
2444 store_name = "llvm.amdgcn.buffer.store.f32";
2445 }
2446 data = extract_vector_range(&ctx->ac, base_data, start, count);
2447
2448 offset = base_offset;
2449 if (start != 0) {
2450 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2451 }
2452 params[0] = data;
2453 params[3] = offset;
2454 ac_build_intrinsic(&ctx->ac, store_name,
2455 ctx->ac.voidt, params, 6, 0);
2456 }
2457 }
2458
2459 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2460 const nir_intrinsic_instr *instr)
2461 {
2462 const char *name;
2463 LLVMValueRef params[6];
2464 int arg_count = 0;
2465
2466 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2467 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2468 }
2469 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2470 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2471 get_src(ctx, instr->src[0]),
2472 true);
2473 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2474 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2475 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2476
2477 switch (instr->intrinsic) {
2478 case nir_intrinsic_ssbo_atomic_add:
2479 name = "llvm.amdgcn.buffer.atomic.add";
2480 break;
2481 case nir_intrinsic_ssbo_atomic_imin:
2482 name = "llvm.amdgcn.buffer.atomic.smin";
2483 break;
2484 case nir_intrinsic_ssbo_atomic_umin:
2485 name = "llvm.amdgcn.buffer.atomic.umin";
2486 break;
2487 case nir_intrinsic_ssbo_atomic_imax:
2488 name = "llvm.amdgcn.buffer.atomic.smax";
2489 break;
2490 case nir_intrinsic_ssbo_atomic_umax:
2491 name = "llvm.amdgcn.buffer.atomic.umax";
2492 break;
2493 case nir_intrinsic_ssbo_atomic_and:
2494 name = "llvm.amdgcn.buffer.atomic.and";
2495 break;
2496 case nir_intrinsic_ssbo_atomic_or:
2497 name = "llvm.amdgcn.buffer.atomic.or";
2498 break;
2499 case nir_intrinsic_ssbo_atomic_xor:
2500 name = "llvm.amdgcn.buffer.atomic.xor";
2501 break;
2502 case nir_intrinsic_ssbo_atomic_exchange:
2503 name = "llvm.amdgcn.buffer.atomic.swap";
2504 break;
2505 case nir_intrinsic_ssbo_atomic_comp_swap:
2506 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2507 break;
2508 default:
2509 abort();
2510 }
2511
2512 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2513 }
2514
2515 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2516 const nir_intrinsic_instr *instr)
2517 {
2518 LLVMValueRef results[2];
2519 int load_components;
2520 int num_components = instr->num_components;
2521 if (instr->dest.ssa.bit_size == 64)
2522 num_components *= 2;
2523
2524 for (int i = 0; i < num_components; i += load_components) {
2525 load_components = MIN2(num_components - i, 4);
2526 const char *load_name;
2527 LLVMTypeRef data_type = ctx->ac.f32;
2528 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2529 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2530
2531 if (load_components == 3)
2532 data_type = LLVMVectorType(ctx->ac.f32, 4);
2533 else if (load_components > 1)
2534 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2535
2536 if (load_components >= 3)
2537 load_name = "llvm.amdgcn.buffer.load.v4f32";
2538 else if (load_components == 2)
2539 load_name = "llvm.amdgcn.buffer.load.v2f32";
2540 else if (load_components == 1)
2541 load_name = "llvm.amdgcn.buffer.load.f32";
2542 else
2543 unreachable("unhandled number of components");
2544
2545 LLVMValueRef params[] = {
2546 ctx->abi->load_ssbo(ctx->abi,
2547 get_src(ctx, instr->src[0]),
2548 false),
2549 ctx->ac.i32_0,
2550 offset,
2551 ctx->ac.i1false,
2552 ctx->ac.i1false,
2553 };
2554
2555 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2556 }
2557
2558 assume(results[0]);
2559 LLVMValueRef ret = results[0];
2560 if (num_components > 4 || num_components == 3) {
2561 LLVMValueRef masks[] = {
2562 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2563 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2564 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2565 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2566 };
2567
2568 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2569 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2570 results[num_components > 4 ? 1 : 0], swizzle, "");
2571 }
2572
2573 return LLVMBuildBitCast(ctx->ac.builder, ret,
2574 get_def_type(ctx, &instr->dest.ssa), "");
2575 }
2576
2577 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2578 const nir_intrinsic_instr *instr)
2579 {
2580 LLVMValueRef ret;
2581 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2582 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2583 int num_components = instr->num_components;
2584
2585 if (ctx->abi->load_ubo)
2586 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2587
2588 if (instr->dest.ssa.bit_size == 64)
2589 num_components *= 2;
2590
2591 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2592 NULL, 0, false, false, true, true);
2593 ret = ac_trim_vector(&ctx->ac, ret, num_components);
2594 return LLVMBuildBitCast(ctx->ac.builder, ret,
2595 get_def_type(ctx, &instr->dest.ssa), "");
2596 }
2597
2598 static void
2599 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2600 bool vs_in, unsigned *vertex_index_out,
2601 LLVMValueRef *vertex_index_ref,
2602 unsigned *const_out, LLVMValueRef *indir_out)
2603 {
2604 unsigned const_offset = 0;
2605 nir_deref *tail = &deref->deref;
2606 LLVMValueRef offset = NULL;
2607
2608 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2609 tail = tail->child;
2610 nir_deref_array *deref_array = nir_deref_as_array(tail);
2611 if (vertex_index_out)
2612 *vertex_index_out = deref_array->base_offset;
2613
2614 if (vertex_index_ref) {
2615 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2616 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2617 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2618 }
2619 *vertex_index_ref = vtx;
2620 }
2621 }
2622
2623 if (deref->var->data.compact) {
2624 assert(tail->child->deref_type == nir_deref_type_array);
2625 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2626 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2627 /* We always lower indirect dereferences for "compact" array vars. */
2628 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2629
2630 const_offset = deref_array->base_offset;
2631 goto out;
2632 }
2633
2634 while (tail->child != NULL) {
2635 const struct glsl_type *parent_type = tail->type;
2636 tail = tail->child;
2637
2638 if (tail->deref_type == nir_deref_type_array) {
2639 nir_deref_array *deref_array = nir_deref_as_array(tail);
2640 LLVMValueRef index, stride, local_offset;
2641 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2642
2643 const_offset += size * deref_array->base_offset;
2644 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2645 continue;
2646
2647 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2648 index = get_src(ctx, deref_array->indirect);
2649 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2650 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2651
2652 if (offset)
2653 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2654 else
2655 offset = local_offset;
2656 } else if (tail->deref_type == nir_deref_type_struct) {
2657 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2658
2659 for (unsigned i = 0; i < deref_struct->index; i++) {
2660 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2661 const_offset += glsl_count_attribute_slots(ft, vs_in);
2662 }
2663 } else
2664 unreachable("unsupported deref type");
2665
2666 }
2667 out:
2668 if (const_offset && offset)
2669 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2670 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2671 "");
2672
2673 *const_out = const_offset;
2674 *indir_out = offset;
2675 }
2676
2677
2678 /* The offchip buffer layout for TCS->TES is
2679 *
2680 * - attribute 0 of patch 0 vertex 0
2681 * - attribute 0 of patch 0 vertex 1
2682 * - attribute 0 of patch 0 vertex 2
2683 * ...
2684 * - attribute 0 of patch 1 vertex 0
2685 * - attribute 0 of patch 1 vertex 1
2686 * ...
2687 * - attribute 1 of patch 0 vertex 0
2688 * - attribute 1 of patch 0 vertex 1
2689 * ...
2690 * - per patch attribute 0 of patch 0
2691 * - per patch attribute 0 of patch 1
2692 * ...
2693 *
2694 * Note that every attribute has 4 components.
2695 */
2696 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
2697 LLVMValueRef vertex_index,
2698 LLVMValueRef param_index)
2699 {
2700 LLVMValueRef base_addr, vertices_per_patch, num_patches;
2701 LLVMValueRef param_stride, constant16;
2702 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2703
2704 vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
2705 num_patches = ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2706
2707 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2708 if (vertex_index) {
2709 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2710 vertices_per_patch, "");
2711
2712 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2713 vertex_index, "");
2714
2715 param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
2716 num_patches, "");
2717 } else {
2718 base_addr = rel_patch_id;
2719 param_stride = num_patches;
2720 }
2721
2722 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2723 LLVMBuildMul(ctx->ac.builder, param_index,
2724 param_stride, ""), "");
2725
2726 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
2727
2728 if (!vertex_index) {
2729 LLVMValueRef patch_data_offset =
2730 ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2731
2732 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2733 patch_data_offset, "");
2734 }
2735 return base_addr;
2736 }
2737
2738 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
2739 unsigned param,
2740 unsigned const_index,
2741 bool is_compact,
2742 LLVMValueRef vertex_index,
2743 LLVMValueRef indir_index)
2744 {
2745 LLVMValueRef param_index;
2746
2747 if (indir_index)
2748 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
2749 indir_index, "");
2750 else {
2751 if (const_index && !is_compact)
2752 param += const_index;
2753 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2754 }
2755 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2756 }
2757
2758 static void
2759 mark_tess_output(struct radv_shader_context *ctx,
2760 bool is_patch, uint32_t param)
2761
2762 {
2763 if (is_patch) {
2764 ctx->tess_patch_outputs_written |= (1ull << param);
2765 } else
2766 ctx->tess_outputs_written |= (1ull << param);
2767 }
2768
2769 static LLVMValueRef
2770 get_dw_address(struct radv_shader_context *ctx,
2771 LLVMValueRef dw_addr,
2772 unsigned param,
2773 unsigned const_index,
2774 bool compact_const_index,
2775 LLVMValueRef vertex_index,
2776 LLVMValueRef stride,
2777 LLVMValueRef indir_index)
2778
2779 {
2780
2781 if (vertex_index) {
2782 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2783 LLVMBuildMul(ctx->ac.builder,
2784 vertex_index,
2785 stride, ""), "");
2786 }
2787
2788 if (indir_index)
2789 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2790 LLVMBuildMul(ctx->ac.builder, indir_index,
2791 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2792 else if (const_index && !compact_const_index)
2793 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2794 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2795
2796 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2797 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2798
2799 if (const_index && compact_const_index)
2800 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2801 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2802 return dw_addr;
2803 }
2804
2805 static LLVMValueRef
2806 load_tcs_varyings(struct ac_shader_abi *abi,
2807 LLVMTypeRef type,
2808 LLVMValueRef vertex_index,
2809 LLVMValueRef indir_index,
2810 unsigned const_index,
2811 unsigned location,
2812 unsigned driver_location,
2813 unsigned component,
2814 unsigned num_components,
2815 bool is_patch,
2816 bool is_compact,
2817 bool load_input)
2818 {
2819 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2820 LLVMValueRef dw_addr, stride;
2821 LLVMValueRef value[4], result;
2822 unsigned param = shader_io_get_unique_index(location);
2823
2824 if (load_input) {
2825 stride = ac_unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2826 dw_addr = get_tcs_in_current_patch_offset(ctx);
2827 } else {
2828 if (!is_patch) {
2829 stride = get_tcs_out_vertex_stride(ctx);
2830 dw_addr = get_tcs_out_current_patch_offset(ctx);
2831 } else {
2832 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2833 stride = NULL;
2834 }
2835 }
2836
2837 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2838 indir_index);
2839
2840 for (unsigned i = 0; i < num_components + component; i++) {
2841 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2842 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2843 ctx->ac.i32_1, "");
2844 }
2845 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2846 return result;
2847 }
2848
2849 static void
2850 store_tcs_output(struct ac_shader_abi *abi,
2851 LLVMValueRef vertex_index,
2852 LLVMValueRef param_index,
2853 unsigned const_index,
2854 unsigned location,
2855 unsigned driver_location,
2856 LLVMValueRef src,
2857 unsigned component,
2858 bool is_patch,
2859 bool is_compact,
2860 unsigned writemask)
2861 {
2862 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2863 LLVMValueRef dw_addr;
2864 LLVMValueRef stride = NULL;
2865 LLVMValueRef buf_addr = NULL;
2866 unsigned param;
2867 bool store_lds = true;
2868
2869 if (is_patch) {
2870 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2871 store_lds = false;
2872 } else {
2873 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2874 store_lds = false;
2875 }
2876
2877 param = shader_io_get_unique_index(location);
2878 if (location == VARYING_SLOT_CLIP_DIST0 &&
2879 is_compact && const_index > 3) {
2880 const_index -= 3;
2881 param++;
2882 }
2883
2884 if (!is_patch) {
2885 stride = get_tcs_out_vertex_stride(ctx);
2886 dw_addr = get_tcs_out_current_patch_offset(ctx);
2887 } else {
2888 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2889 }
2890
2891 mark_tess_output(ctx, is_patch, param);
2892
2893 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2894 param_index);
2895 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2896 vertex_index, param_index);
2897
2898 bool is_tess_factor = false;
2899 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2900 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2901 is_tess_factor = true;
2902
2903 unsigned base = is_compact ? const_index : 0;
2904 for (unsigned chan = 0; chan < 8; chan++) {
2905 if (!(writemask & (1 << chan)))
2906 continue;
2907 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2908
2909 if (store_lds || is_tess_factor) {
2910 LLVMValueRef dw_addr_chan =
2911 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2912 LLVMConstInt(ctx->ac.i32, chan, false), "");
2913 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2914 }
2915
2916 if (!is_tess_factor && writemask != 0xF)
2917 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2918 buf_addr, ctx->oc_lds,
2919 4 * (base + chan), 1, 0, true, false);
2920 }
2921
2922 if (writemask == 0xF) {
2923 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2924 buf_addr, ctx->oc_lds,
2925 (base * 4), 1, 0, true, false);
2926 }
2927 }
2928
2929 static LLVMValueRef
2930 load_tes_input(struct ac_shader_abi *abi,
2931 LLVMTypeRef type,
2932 LLVMValueRef vertex_index,
2933 LLVMValueRef param_index,
2934 unsigned const_index,
2935 unsigned location,
2936 unsigned driver_location,
2937 unsigned component,
2938 unsigned num_components,
2939 bool is_patch,
2940 bool is_compact,
2941 bool load_input)
2942 {
2943 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2944 LLVMValueRef buf_addr;
2945 LLVMValueRef result;
2946 unsigned param = shader_io_get_unique_index(location);
2947
2948 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
2949 const_index -= 3;
2950 param++;
2951 }
2952
2953 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2954 is_compact, vertex_index, param_index);
2955
2956 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
2957 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
2958
2959 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
2960 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2961 result = ac_trim_vector(&ctx->ac, result, num_components);
2962 return result;
2963 }
2964
2965 static LLVMValueRef
2966 load_gs_input(struct ac_shader_abi *abi,
2967 unsigned location,
2968 unsigned driver_location,
2969 unsigned component,
2970 unsigned num_components,
2971 unsigned vertex_index,
2972 unsigned const_index,
2973 LLVMTypeRef type)
2974 {
2975 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2976 LLVMValueRef vtx_offset;
2977 unsigned param, vtx_offset_param;
2978 LLVMValueRef value[4], result;
2979
2980 vtx_offset_param = vertex_index;
2981 assert(vtx_offset_param < 6);
2982 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
2983 LLVMConstInt(ctx->ac.i32, 4, false), "");
2984
2985 param = shader_io_get_unique_index(location);
2986
2987 for (unsigned i = component; i < num_components + component; i++) {
2988 if (ctx->ac.chip_class >= GFX9) {
2989 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
2990 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2991 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
2992 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2993 } else {
2994 LLVMValueRef soffset =
2995 LLVMConstInt(ctx->ac.i32,
2996 (param * 4 + i + const_index) * 256,
2997 false);
2998
2999 value[i] = ac_build_buffer_load(&ctx->ac,
3000 ctx->esgs_ring, 1,
3001 ctx->ac.i32_0,
3002 vtx_offset, soffset,
3003 0, 1, 0, true, false);
3004
3005 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
3006 type, "");
3007 }
3008 }
3009 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3010 result = ac_to_integer(&ctx->ac, result);
3011 return result;
3012 }
3013
3014 static LLVMValueRef
3015 build_gep_for_deref(struct ac_nir_context *ctx,
3016 nir_deref_var *deref)
3017 {
3018 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3019 assert(entry->data);
3020 LLVMValueRef val = entry->data;
3021 nir_deref *tail = deref->deref.child;
3022 while (tail != NULL) {
3023 LLVMValueRef offset;
3024 switch (tail->deref_type) {
3025 case nir_deref_type_array: {
3026 nir_deref_array *array = nir_deref_as_array(tail);
3027 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3028 if (array->deref_array_type ==
3029 nir_deref_array_type_indirect) {
3030 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3031 get_src(ctx,
3032 array->indirect),
3033 "");
3034 }
3035 break;
3036 }
3037 case nir_deref_type_struct: {
3038 nir_deref_struct *deref_struct =
3039 nir_deref_as_struct(tail);
3040 offset = LLVMConstInt(ctx->ac.i32,
3041 deref_struct->index, 0);
3042 break;
3043 }
3044 default:
3045 unreachable("bad deref type");
3046 }
3047 val = ac_build_gep0(&ctx->ac, val, offset);
3048 tail = tail->child;
3049 }
3050 return val;
3051 }
3052
3053 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3054 nir_intrinsic_instr *instr,
3055 bool load_inputs)
3056 {
3057 LLVMValueRef result;
3058 LLVMValueRef vertex_index = NULL;
3059 LLVMValueRef indir_index = NULL;
3060 unsigned const_index = 0;
3061 unsigned location = instr->variables[0]->var->data.location;
3062 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3063 const bool is_patch = instr->variables[0]->var->data.patch;
3064 const bool is_compact = instr->variables[0]->var->data.compact;
3065
3066 get_deref_offset(ctx, instr->variables[0],
3067 false, NULL, is_patch ? NULL : &vertex_index,
3068 &const_index, &indir_index);
3069
3070 LLVMTypeRef dest_type = get_def_type(ctx, &instr->dest.ssa);
3071
3072 LLVMTypeRef src_component_type;
3073 if (LLVMGetTypeKind(dest_type) == LLVMVectorTypeKind)
3074 src_component_type = LLVMGetElementType(dest_type);
3075 else
3076 src_component_type = dest_type;
3077
3078 result = ctx->abi->load_tess_varyings(ctx->abi, src_component_type,
3079 vertex_index, indir_index,
3080 const_index, location, driver_location,
3081 instr->variables[0]->var->data.location_frac,
3082 instr->num_components,
3083 is_patch, is_compact, load_inputs);
3084 return LLVMBuildBitCast(ctx->ac.builder, result, dest_type, "");
3085 }
3086
3087 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3088 nir_intrinsic_instr *instr)
3089 {
3090 LLVMValueRef values[8];
3091 int idx = instr->variables[0]->var->data.driver_location;
3092 int ve = instr->dest.ssa.num_components;
3093 unsigned comp = instr->variables[0]->var->data.location_frac;
3094 LLVMValueRef indir_index;
3095 LLVMValueRef ret;
3096 unsigned const_index;
3097 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3098 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3099 instr->variables[0]->var->data.mode == nir_var_shader_in;
3100 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3101 &const_index, &indir_index);
3102
3103 if (instr->dest.ssa.bit_size == 64)
3104 ve *= 2;
3105
3106 switch (instr->variables[0]->var->data.mode) {
3107 case nir_var_shader_in:
3108 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3109 ctx->stage == MESA_SHADER_TESS_EVAL) {
3110 return load_tess_varyings(ctx, instr, true);
3111 }
3112
3113 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3114 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3115 LLVMValueRef indir_index;
3116 unsigned const_index, vertex_index;
3117 get_deref_offset(ctx, instr->variables[0],
3118 false, &vertex_index, NULL,
3119 &const_index, &indir_index);
3120
3121 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3122 instr->variables[0]->var->data.driver_location,
3123 instr->variables[0]->var->data.location_frac,
3124 instr->num_components, vertex_index, const_index, type);
3125 }
3126
3127 for (unsigned chan = comp; chan < ve + comp; chan++) {
3128 if (indir_index) {
3129 unsigned count = glsl_count_attribute_slots(
3130 instr->variables[0]->var->type,
3131 ctx->stage == MESA_SHADER_VERTEX);
3132 count -= chan / 4;
3133 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3134 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3135 stride, false, true);
3136
3137 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3138 tmp_vec,
3139 indir_index, "");
3140 } else
3141 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3142 }
3143 break;
3144 case nir_var_local:
3145 for (unsigned chan = 0; chan < ve; chan++) {
3146 if (indir_index) {
3147 unsigned count = glsl_count_attribute_slots(
3148 instr->variables[0]->var->type, false);
3149 count -= chan / 4;
3150 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3151 &ctx->ac, ctx->locals + idx + chan, count,
3152 stride, true, true);
3153
3154 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3155 tmp_vec,
3156 indir_index, "");
3157 } else {
3158 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3159 }
3160 }
3161 break;
3162 case nir_var_shared: {
3163 LLVMValueRef address = build_gep_for_deref(ctx,
3164 instr->variables[0]);
3165 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3166 return LLVMBuildBitCast(ctx->ac.builder, val,
3167 get_def_type(ctx, &instr->dest.ssa),
3168 "");
3169 }
3170 case nir_var_shader_out:
3171 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3172 return load_tess_varyings(ctx, instr, false);
3173 }
3174
3175 for (unsigned chan = comp; chan < ve + comp; chan++) {
3176 if (indir_index) {
3177 unsigned count = glsl_count_attribute_slots(
3178 instr->variables[0]->var->type, false);
3179 count -= chan / 4;
3180 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3181 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3182 stride, true, true);
3183
3184 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3185 tmp_vec,
3186 indir_index, "");
3187 } else {
3188 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3189 ctx->abi->outputs[idx + chan + const_index * stride],
3190 "");
3191 }
3192 }
3193 break;
3194 default:
3195 unreachable("unhandle variable mode");
3196 }
3197 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3198 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3199 }
3200
3201 static void
3202 visit_store_var(struct ac_nir_context *ctx,
3203 nir_intrinsic_instr *instr)
3204 {
3205 LLVMValueRef temp_ptr, value;
3206 int idx = instr->variables[0]->var->data.driver_location;
3207 unsigned comp = instr->variables[0]->var->data.location_frac;
3208 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3209 int writemask = instr->const_index[0] << comp;
3210 LLVMValueRef indir_index;
3211 unsigned const_index;
3212 get_deref_offset(ctx, instr->variables[0], false,
3213 NULL, NULL, &const_index, &indir_index);
3214
3215 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3216
3217 src = LLVMBuildBitCast(ctx->ac.builder, src,
3218 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3219 "");
3220
3221 writemask = widen_mask(writemask, 2);
3222 }
3223
3224 switch (instr->variables[0]->var->data.mode) {
3225 case nir_var_shader_out:
3226
3227 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3228 LLVMValueRef vertex_index = NULL;
3229 LLVMValueRef indir_index = NULL;
3230 unsigned const_index = 0;
3231 const unsigned location = instr->variables[0]->var->data.location;
3232 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3233 const unsigned comp = instr->variables[0]->var->data.location_frac;
3234 const bool is_patch = instr->variables[0]->var->data.patch;
3235 const bool is_compact = instr->variables[0]->var->data.compact;
3236
3237 get_deref_offset(ctx, instr->variables[0],
3238 false, NULL, is_patch ? NULL : &vertex_index,
3239 &const_index, &indir_index);
3240
3241 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3242 const_index, location, driver_location,
3243 src, comp, is_patch, is_compact, writemask);
3244 return;
3245 }
3246
3247 for (unsigned chan = 0; chan < 8; chan++) {
3248 int stride = 4;
3249 if (!(writemask & (1 << chan)))
3250 continue;
3251
3252 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3253
3254 if (instr->variables[0]->var->data.compact)
3255 stride = 1;
3256 if (indir_index) {
3257 unsigned count = glsl_count_attribute_slots(
3258 instr->variables[0]->var->type, false);
3259 count -= chan / 4;
3260 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3261 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3262 stride, true, true);
3263
3264 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3265 value, indir_index, "");
3266 build_store_values_extended(&ctx->ac, ctx->abi->outputs + idx + chan,
3267 count, stride, tmp_vec);
3268
3269 } else {
3270 temp_ptr = ctx->abi->outputs[idx + chan + const_index * stride];
3271
3272 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3273 }
3274 }
3275 break;
3276 case nir_var_local:
3277 for (unsigned chan = 0; chan < 8; chan++) {
3278 if (!(writemask & (1 << chan)))
3279 continue;
3280
3281 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3282 if (indir_index) {
3283 unsigned count = glsl_count_attribute_slots(
3284 instr->variables[0]->var->type, false);
3285 count -= chan / 4;
3286 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3287 &ctx->ac, ctx->locals + idx + chan, count,
3288 4, true, true);
3289
3290 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3291 value, indir_index, "");
3292 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3293 count, 4, tmp_vec);
3294 } else {
3295 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3296
3297 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3298 }
3299 }
3300 break;
3301 case nir_var_shared: {
3302 int writemask = instr->const_index[0];
3303 LLVMValueRef address = build_gep_for_deref(ctx,
3304 instr->variables[0]);
3305 LLVMValueRef val = get_src(ctx, instr->src[0]);
3306 unsigned components =
3307 glsl_get_vector_elements(
3308 nir_deref_tail(&instr->variables[0]->deref)->type);
3309 if (writemask == (1 << components) - 1) {
3310 val = LLVMBuildBitCast(
3311 ctx->ac.builder, val,
3312 LLVMGetElementType(LLVMTypeOf(address)), "");
3313 LLVMBuildStore(ctx->ac.builder, val, address);
3314 } else {
3315 for (unsigned chan = 0; chan < 4; chan++) {
3316 if (!(writemask & (1 << chan)))
3317 continue;
3318 LLVMValueRef ptr =
3319 LLVMBuildStructGEP(ctx->ac.builder,
3320 address, chan, "");
3321 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3322 chan);
3323 src = LLVMBuildBitCast(
3324 ctx->ac.builder, src,
3325 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3326 LLVMBuildStore(ctx->ac.builder, src, ptr);
3327 }
3328 }
3329 break;
3330 }
3331 default:
3332 break;
3333 }
3334 }
3335
3336 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3337 {
3338 switch (dim) {
3339 case GLSL_SAMPLER_DIM_BUF:
3340 return 1;
3341 case GLSL_SAMPLER_DIM_1D:
3342 return array ? 2 : 1;
3343 case GLSL_SAMPLER_DIM_2D:
3344 return array ? 3 : 2;
3345 case GLSL_SAMPLER_DIM_MS:
3346 return array ? 4 : 3;
3347 case GLSL_SAMPLER_DIM_3D:
3348 case GLSL_SAMPLER_DIM_CUBE:
3349 return 3;
3350 case GLSL_SAMPLER_DIM_RECT:
3351 case GLSL_SAMPLER_DIM_SUBPASS:
3352 return 2;
3353 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3354 return 3;
3355 default:
3356 break;
3357 }
3358 return 0;
3359 }
3360
3361 static bool
3362 glsl_is_array_image(const struct glsl_type *type)
3363 {
3364 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3365
3366 if (glsl_sampler_type_is_array(type))
3367 return true;
3368
3369 return dim == GLSL_SAMPLER_DIM_CUBE ||
3370 dim == GLSL_SAMPLER_DIM_3D ||
3371 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3372 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3373 }
3374
3375
3376 /* Adjust the sample index according to FMASK.
3377 *
3378 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3379 * which is the identity mapping. Each nibble says which physical sample
3380 * should be fetched to get that sample.
3381 *
3382 * For example, 0x11111100 means there are only 2 samples stored and
3383 * the second sample covers 3/4 of the pixel. When reading samples 0
3384 * and 1, return physical sample 0 (determined by the first two 0s
3385 * in FMASK), otherwise return physical sample 1.
3386 *
3387 * The sample index should be adjusted as follows:
3388 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3389 */
3390 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3391 LLVMValueRef coord_x, LLVMValueRef coord_y,
3392 LLVMValueRef coord_z,
3393 LLVMValueRef sample_index,
3394 LLVMValueRef fmask_desc_ptr)
3395 {
3396 LLVMValueRef fmask_load_address[4];
3397 LLVMValueRef res;
3398
3399 fmask_load_address[0] = coord_x;
3400 fmask_load_address[1] = coord_y;
3401 if (coord_z) {
3402 fmask_load_address[2] = coord_z;
3403 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3404 }
3405
3406 struct ac_image_args args = {0};
3407
3408 args.opcode = ac_image_load;
3409 args.da = coord_z ? true : false;
3410 args.resource = fmask_desc_ptr;
3411 args.dmask = 0xf;
3412 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3413
3414 res = ac_build_image_opcode(ctx, &args);
3415
3416 res = ac_to_integer(ctx, res);
3417 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3418 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3419
3420 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3421 res,
3422 ctx->i32_0, "");
3423
3424 LLVMValueRef sample_index4 =
3425 LLVMBuildMul(ctx->builder, sample_index, four, "");
3426 LLVMValueRef shifted_fmask =
3427 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3428 LLVMValueRef final_sample =
3429 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3430
3431 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3432 * resource descriptor is 0 (invalid),
3433 */
3434 LLVMValueRef fmask_desc =
3435 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3436 ctx->v8i32, "");
3437
3438 LLVMValueRef fmask_word1 =
3439 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3440 ctx->i32_1, "");
3441
3442 LLVMValueRef word1_is_nonzero =
3443 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3444 fmask_word1, ctx->i32_0, "");
3445
3446 /* Replace the MSAA sample index. */
3447 sample_index =
3448 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3449 final_sample, sample_index, "");
3450 return sample_index;
3451 }
3452
3453 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3454 const nir_intrinsic_instr *instr)
3455 {
3456 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3457
3458 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3459 LLVMValueRef coords[4];
3460 LLVMValueRef masks[] = {
3461 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3462 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3463 };
3464 LLVMValueRef res;
3465 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3466
3467 int count;
3468 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3469 bool is_array = glsl_sampler_type_is_array(type);
3470 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3471 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3472 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3473 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3474 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3475 count = image_type_to_components_count(dim, is_array);
3476
3477 if (is_ms) {
3478 LLVMValueRef fmask_load_address[3];
3479 int chan;
3480
3481 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3482 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3483 if (is_array)
3484 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3485 else
3486 fmask_load_address[2] = NULL;
3487 if (add_frag_pos) {
3488 for (chan = 0; chan < 2; ++chan)
3489 fmask_load_address[chan] =
3490 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3491 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3492 ctx->ac.i32, ""), "");
3493 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3494 }
3495 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3496 fmask_load_address[0],
3497 fmask_load_address[1],
3498 fmask_load_address[2],
3499 sample_index,
3500 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3501 }
3502 if (count == 1 && !gfx9_1d) {
3503 if (instr->src[0].ssa->num_components)
3504 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3505 else
3506 res = src0;
3507 } else {
3508 int chan;
3509 if (is_ms)
3510 count--;
3511 for (chan = 0; chan < count; ++chan) {
3512 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3513 }
3514 if (add_frag_pos) {
3515 for (chan = 0; chan < 2; ++chan)
3516 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3517 ctx->ac.i32, ""), "");
3518 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3519 count++;
3520 }
3521
3522 if (gfx9_1d) {
3523 if (is_array) {
3524 coords[2] = coords[1];
3525 coords[1] = ctx->ac.i32_0;
3526 } else
3527 coords[1] = ctx->ac.i32_0;
3528 count++;
3529 }
3530
3531 if (is_ms) {
3532 coords[count] = sample_index;
3533 count++;
3534 }
3535
3536 if (count == 3) {
3537 coords[3] = LLVMGetUndef(ctx->ac.i32);
3538 count = 4;
3539 }
3540 res = ac_build_gather_values(&ctx->ac, coords, count);
3541 }
3542 return res;
3543 }
3544
3545 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3546 const nir_intrinsic_instr *instr)
3547 {
3548 LLVMValueRef params[7];
3549 LLVMValueRef res;
3550 char intrinsic_name[64];
3551 const nir_variable *var = instr->variables[0]->var;
3552 const struct glsl_type *type = var->type;
3553
3554 if(instr->variables[0]->deref.child)
3555 type = instr->variables[0]->deref.child->type;
3556
3557 type = glsl_without_array(type);
3558
3559 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3560 if (dim == GLSL_SAMPLER_DIM_BUF) {
3561 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3562 unsigned num_channels = util_last_bit(mask);
3563 LLVMValueRef rsrc, vindex;
3564
3565 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3566 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3567 ctx->ac.i32_0, "");
3568
3569 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3570 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3571 ctx->ac.i32_0, num_channels,
3572 false, false);
3573 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3574
3575 res = ac_trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3576 res = ac_to_integer(&ctx->ac, res);
3577 } else {
3578 LLVMValueRef da = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false;
3579 LLVMValueRef slc = ctx->ac.i1false;
3580
3581 params[0] = get_image_coords(ctx, instr);
3582 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3583 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3584 params[3] = (var->data.image._volatile || var->data.image.coherent) ?
3585 ctx->ac.i1true : ctx->ac.i1false;
3586 params[4] = slc;
3587 params[5] = ctx->ac.i1false;
3588 params[6] = da;
3589
3590 ac_get_image_intr_name("llvm.amdgcn.image.load",
3591 ctx->ac.v4f32, /* vdata */
3592 LLVMTypeOf(params[0]), /* coords */
3593 LLVMTypeOf(params[1]), /* rsrc */
3594 intrinsic_name, sizeof(intrinsic_name));
3595
3596 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3597 params, 7, AC_FUNC_ATTR_READONLY);
3598 }
3599 return ac_to_integer(&ctx->ac, res);
3600 }
3601
3602 static void visit_image_store(struct ac_nir_context *ctx,
3603 nir_intrinsic_instr *instr)
3604 {
3605 LLVMValueRef params[8];
3606 char intrinsic_name[64];
3607 const nir_variable *var = instr->variables[0]->var;
3608 const struct glsl_type *type = glsl_without_array(var->type);
3609 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3610 LLVMValueRef glc = ctx->ac.i1false;
3611 bool force_glc = ctx->ac.chip_class == SI;
3612 if (force_glc)
3613 glc = ctx->ac.i1true;
3614
3615 if (dim == GLSL_SAMPLER_DIM_BUF) {
3616 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3617 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3618 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3619 ctx->ac.i32_0, ""); /* vindex */
3620 params[3] = ctx->ac.i32_0; /* voffset */
3621 params[4] = glc; /* glc */
3622 params[5] = ctx->ac.i1false; /* slc */
3623 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3624 params, 6, 0);
3625 } else {
3626 LLVMValueRef da = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false;
3627 LLVMValueRef slc = ctx->ac.i1false;
3628
3629 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3630 params[1] = get_image_coords(ctx, instr); /* coords */
3631 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3632 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3633 params[4] = (force_glc || var->data.image._volatile || var->data.image.coherent) ?
3634 ctx->ac.i1true : ctx->ac.i1false;
3635 params[5] = slc;
3636 params[6] = ctx->ac.i1false;
3637 params[7] = da;
3638
3639 ac_get_image_intr_name("llvm.amdgcn.image.store",
3640 LLVMTypeOf(params[0]), /* vdata */
3641 LLVMTypeOf(params[1]), /* coords */
3642 LLVMTypeOf(params[2]), /* rsrc */
3643 intrinsic_name, sizeof(intrinsic_name));
3644
3645 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3646 params, 8, 0);
3647 }
3648
3649 }
3650
3651 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3652 const nir_intrinsic_instr *instr)
3653 {
3654 LLVMValueRef params[7];
3655 int param_count = 0;
3656 const nir_variable *var = instr->variables[0]->var;
3657
3658 const char *atomic_name;
3659 char intrinsic_name[41];
3660 const struct glsl_type *type = glsl_without_array(var->type);
3661 MAYBE_UNUSED int length;
3662
3663 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3664
3665 switch (instr->intrinsic) {
3666 case nir_intrinsic_image_atomic_add:
3667 atomic_name = "add";
3668 break;
3669 case nir_intrinsic_image_atomic_min:
3670 atomic_name = is_unsigned ? "umin" : "smin";
3671 break;
3672 case nir_intrinsic_image_atomic_max:
3673 atomic_name = is_unsigned ? "umax" : "smax";
3674 break;
3675 case nir_intrinsic_image_atomic_and:
3676 atomic_name = "and";
3677 break;
3678 case nir_intrinsic_image_atomic_or:
3679 atomic_name = "or";
3680 break;
3681 case nir_intrinsic_image_atomic_xor:
3682 atomic_name = "xor";
3683 break;
3684 case nir_intrinsic_image_atomic_exchange:
3685 atomic_name = "swap";
3686 break;
3687 case nir_intrinsic_image_atomic_comp_swap:
3688 atomic_name = "cmpswap";
3689 break;
3690 default:
3691 abort();
3692 }
3693
3694 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3695 params[param_count++] = get_src(ctx, instr->src[3]);
3696 params[param_count++] = get_src(ctx, instr->src[2]);
3697
3698 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3699 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3700 NULL, true, true);
3701 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3702 ctx->ac.i32_0, ""); /* vindex */
3703 params[param_count++] = ctx->ac.i32_0; /* voffset */
3704 params[param_count++] = ctx->ac.i1false; /* slc */
3705
3706 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3707 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3708 } else {
3709 char coords_type[8];
3710
3711 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3712 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3713 NULL, true, true);
3714 params[param_count++] = ctx->ac.i1false; /* r128 */
3715 params[param_count++] = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3716 params[param_count++] = ctx->ac.i1false; /* slc */
3717
3718 build_int_type_name(LLVMTypeOf(coords),
3719 coords_type, sizeof(coords_type));
3720
3721 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3722 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3723 }
3724
3725 assert(length < sizeof(intrinsic_name));
3726 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3727 }
3728
3729 static LLVMValueRef visit_image_samples(struct ac_nir_context *ctx,
3730 const nir_intrinsic_instr *instr)
3731 {
3732 const nir_variable *var = instr->variables[0]->var;
3733 const struct glsl_type *type = glsl_without_array(var->type);
3734
3735 struct ac_image_args args = { 0 };
3736 args.da = glsl_is_array_image(type);
3737 args.dmask = 0xf;
3738 args.resource = get_sampler_desc(ctx, instr->variables[0],
3739 AC_DESC_IMAGE, NULL, true, false);
3740 args.opcode = ac_image_get_resinfo;
3741 args.addr = ctx->ac.i32_0;
3742
3743 return ac_build_image_opcode(&ctx->ac, &args);
3744 }
3745
3746 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3747 const nir_intrinsic_instr *instr)
3748 {
3749 LLVMValueRef res;
3750 const nir_variable *var = instr->variables[0]->var;
3751 const struct glsl_type *type = glsl_without_array(var->type);
3752
3753 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3754 return get_buffer_size(ctx,
3755 get_sampler_desc(ctx, instr->variables[0],
3756 AC_DESC_BUFFER, NULL, true, false), true);
3757
3758 struct ac_image_args args = { 0 };
3759
3760 args.da = glsl_is_array_image(type);
3761 args.dmask = 0xf;
3762 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3763 args.opcode = ac_image_get_resinfo;
3764 args.addr = ctx->ac.i32_0;
3765
3766 res = ac_build_image_opcode(&ctx->ac, &args);
3767
3768 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3769
3770 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3771 glsl_sampler_type_is_array(type)) {
3772 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3773 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3774 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3775 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3776 }
3777 if (ctx->ac.chip_class >= GFX9 &&
3778 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3779 glsl_sampler_type_is_array(type)) {
3780 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3781 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3782 ctx->ac.i32_1, "");
3783
3784 }
3785 return res;
3786 }
3787
3788 #define NOOP_WAITCNT 0xf7f
3789 #define LGKM_CNT 0x07f
3790 #define VM_CNT 0xf70
3791
3792 static void emit_membar(struct ac_llvm_context *ac,
3793 const nir_intrinsic_instr *instr)
3794 {
3795 unsigned waitcnt = NOOP_WAITCNT;
3796
3797 switch (instr->intrinsic) {
3798 case nir_intrinsic_memory_barrier:
3799 case nir_intrinsic_group_memory_barrier:
3800 waitcnt &= VM_CNT & LGKM_CNT;
3801 break;
3802 case nir_intrinsic_memory_barrier_atomic_counter:
3803 case nir_intrinsic_memory_barrier_buffer:
3804 case nir_intrinsic_memory_barrier_image:
3805 waitcnt &= VM_CNT;
3806 break;
3807 case nir_intrinsic_memory_barrier_shared:
3808 waitcnt &= LGKM_CNT;
3809 break;
3810 default:
3811 break;
3812 }
3813 if (waitcnt != NOOP_WAITCNT)
3814 ac_build_waitcnt(ac, waitcnt);
3815 }
3816
3817 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3818 {
3819 /* SI only (thanks to a hw bug workaround):
3820 * The real barrier instruction isn’t needed, because an entire patch
3821 * always fits into a single wave.
3822 */
3823 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3824 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3825 return;
3826 }
3827 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3828 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3829 }
3830
3831 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
3832 {
3833 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3834 ac_build_kill_if_false(&ctx->ac, visible);
3835 }
3836
3837 static void emit_discard(struct ac_nir_context *ctx,
3838 const nir_intrinsic_instr *instr)
3839 {
3840 LLVMValueRef cond;
3841
3842 if (instr->intrinsic == nir_intrinsic_discard_if) {
3843 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3844 get_src(ctx, instr->src[0]),
3845 ctx->ac.i32_0, "");
3846 } else {
3847 assert(instr->intrinsic == nir_intrinsic_discard);
3848 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3849 }
3850
3851 ctx->abi->emit_kill(ctx->abi, cond);
3852 }
3853
3854 static LLVMValueRef
3855 visit_load_helper_invocation(struct ac_nir_context *ctx)
3856 {
3857 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3858 "llvm.amdgcn.ps.live",
3859 ctx->ac.i1, NULL, 0,
3860 AC_FUNC_ATTR_READNONE);
3861 result = LLVMBuildNot(ctx->ac.builder, result, "");
3862 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3863 }
3864
3865 static LLVMValueRef
3866 visit_load_local_invocation_index(struct ac_nir_context *ctx)
3867 {
3868 LLVMValueRef result;
3869 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3870 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3871 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3872
3873 return LLVMBuildAdd(ctx->ac.builder, result, thread_id, "");
3874 }
3875
3876 static LLVMValueRef
3877 visit_load_subgroup_id(struct ac_nir_context *ctx)
3878 {
3879 if (ctx->stage == MESA_SHADER_COMPUTE) {
3880 LLVMValueRef result;
3881 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3882 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3883 return LLVMBuildLShr(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 6, false), "");
3884 } else {
3885 return LLVMConstInt(ctx->ac.i32, 0, false);
3886 }
3887 }
3888
3889 static LLVMValueRef
3890 visit_load_num_subgroups(struct ac_nir_context *ctx)
3891 {
3892 if (ctx->stage == MESA_SHADER_COMPUTE) {
3893 return LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3894 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
3895 } else {
3896 return LLVMConstInt(ctx->ac.i32, 1, false);
3897 }
3898 }
3899
3900 static LLVMValueRef
3901 visit_first_invocation(struct ac_nir_context *ctx)
3902 {
3903 LLVMValueRef active_set = ac_build_ballot(&ctx->ac, ctx->ac.i32_1);
3904
3905 /* The second argument is whether cttz(0) should be defined, but we do not care. */
3906 LLVMValueRef args[] = {active_set, LLVMConstInt(ctx->ac.i1, 0, false)};
3907 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3908 "llvm.cttz.i64",
3909 ctx->ac.i64, args, 2,
3910 AC_FUNC_ATTR_NOUNWIND |
3911 AC_FUNC_ATTR_READNONE);
3912
3913 return LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
3914 }
3915
3916 static LLVMValueRef
3917 visit_load_shared(struct ac_nir_context *ctx,
3918 const nir_intrinsic_instr *instr)
3919 {
3920 LLVMValueRef values[4], derived_ptr, index, ret;
3921
3922 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
3923
3924 for (int chan = 0; chan < instr->num_components; chan++) {
3925 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3926 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
3927 values[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
3928 }
3929
3930 ret = ac_build_gather_values(&ctx->ac, values, instr->num_components);
3931 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3932 }
3933
3934 static void
3935 visit_store_shared(struct ac_nir_context *ctx,
3936 const nir_intrinsic_instr *instr)
3937 {
3938 LLVMValueRef derived_ptr, data,index;
3939 LLVMBuilderRef builder = ctx->ac.builder;
3940
3941 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
3942 LLVMValueRef src = get_src(ctx, instr->src[0]);
3943
3944 int writemask = nir_intrinsic_write_mask(instr);
3945 for (int chan = 0; chan < 4; chan++) {
3946 if (!(writemask & (1 << chan))) {
3947 continue;
3948 }
3949 data = ac_llvm_extract_elem(&ctx->ac, src, chan);
3950 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3951 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3952 LLVMBuildStore(builder, data, derived_ptr);
3953 }
3954 }
3955
3956 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
3957 const nir_intrinsic_instr *instr,
3958 LLVMValueRef ptr, int src_idx)
3959 {
3960 LLVMValueRef result;
3961 LLVMValueRef src = get_src(ctx, instr->src[src_idx]);
3962
3963 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
3964 instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
3965 LLVMValueRef src1 = get_src(ctx, instr->src[src_idx + 1]);
3966 result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
3967 ptr, src, src1,
3968 LLVMAtomicOrderingSequentiallyConsistent,
3969 LLVMAtomicOrderingSequentiallyConsistent,
3970 false);
3971 } else {
3972 LLVMAtomicRMWBinOp op;
3973 switch (instr->intrinsic) {
3974 case nir_intrinsic_var_atomic_add:
3975 case nir_intrinsic_shared_atomic_add:
3976 op = LLVMAtomicRMWBinOpAdd;
3977 break;
3978 case nir_intrinsic_var_atomic_umin:
3979 case nir_intrinsic_shared_atomic_umin:
3980 op = LLVMAtomicRMWBinOpUMin;
3981 break;
3982 case nir_intrinsic_var_atomic_umax:
3983 case nir_intrinsic_shared_atomic_umax:
3984 op = LLVMAtomicRMWBinOpUMax;
3985 break;
3986 case nir_intrinsic_var_atomic_imin:
3987 case nir_intrinsic_shared_atomic_imin:
3988 op = LLVMAtomicRMWBinOpMin;
3989 break;
3990 case nir_intrinsic_var_atomic_imax:
3991 case nir_intrinsic_shared_atomic_imax:
3992 op = LLVMAtomicRMWBinOpMax;
3993 break;
3994 case nir_intrinsic_var_atomic_and:
3995 case nir_intrinsic_shared_atomic_and:
3996 op = LLVMAtomicRMWBinOpAnd;
3997 break;
3998 case nir_intrinsic_var_atomic_or:
3999 case nir_intrinsic_shared_atomic_or:
4000 op = LLVMAtomicRMWBinOpOr;
4001 break;
4002 case nir_intrinsic_var_atomic_xor:
4003 case nir_intrinsic_shared_atomic_xor:
4004 op = LLVMAtomicRMWBinOpXor;
4005 break;
4006 case nir_intrinsic_var_atomic_exchange:
4007 case nir_intrinsic_shared_atomic_exchange:
4008 op = LLVMAtomicRMWBinOpXchg;
4009 break;
4010 default:
4011 return NULL;
4012 }
4013
4014 result = LLVMBuildAtomicRMW(ctx->ac.builder, op, ptr, ac_to_integer(&ctx->ac, src),
4015 LLVMAtomicOrderingSequentiallyConsistent,
4016 false);
4017 }
4018 return result;
4019 }
4020
4021 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
4022 enum glsl_interp_mode interp, unsigned location)
4023 {
4024 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4025
4026 switch (interp) {
4027 case INTERP_MODE_FLAT:
4028 default:
4029 return NULL;
4030 case INTERP_MODE_SMOOTH:
4031 case INTERP_MODE_NONE:
4032 if (location == INTERP_CENTER)
4033 return ctx->persp_center;
4034 else if (location == INTERP_CENTROID)
4035 return ctx->persp_centroid;
4036 else if (location == INTERP_SAMPLE)
4037 return ctx->persp_sample;
4038 break;
4039 case INTERP_MODE_NOPERSPECTIVE:
4040 if (location == INTERP_CENTER)
4041 return ctx->linear_center;
4042 else if (location == INTERP_CENTROID)
4043 return ctx->linear_centroid;
4044 else if (location == INTERP_SAMPLE)
4045 return ctx->linear_sample;
4046 break;
4047 }
4048 return NULL;
4049 }
4050
4051 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
4052 LLVMValueRef sample_id)
4053 {
4054 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4055
4056 LLVMValueRef result;
4057 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4058
4059 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
4060 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4061
4062 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
4063 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4064
4065 return result;
4066 }
4067
4068 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4069 {
4070 LLVMValueRef values[2];
4071 LLVMValueRef pos[2];
4072
4073 pos[0] = ac_to_float(&ctx->ac, ctx->abi->frag_pos[0]);
4074 pos[1] = ac_to_float(&ctx->ac, ctx->abi->frag_pos[1]);
4075
4076 values[0] = ac_build_fract(&ctx->ac, pos[0], 32);
4077 values[1] = ac_build_fract(&ctx->ac, pos[1], 32);
4078 return ac_build_gather_values(&ctx->ac, values, 2);
4079 }
4080
4081 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4082 {
4083 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4084 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4085 ctx->options->key.fs.log2_num_samples :
4086 ctx->options->key.fs.log2_ps_iter_samples;
4087
4088 /* The bit pattern matches that used by fixed function fragment
4089 * processing. */
4090 static const uint16_t ps_iter_masks[] = {
4091 0xffff, /* not used */
4092 0x5555,
4093 0x1111,
4094 0x0101,
4095 0x0001,
4096 };
4097 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4098
4099 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4100
4101 LLVMValueRef result, sample_id;
4102 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4103 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4104 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4105 return result;
4106 }
4107
4108 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4109 const nir_intrinsic_instr *instr)
4110 {
4111 LLVMValueRef result[4];
4112 LLVMValueRef interp_param, attr_number;
4113 unsigned location;
4114 unsigned chan;
4115 LLVMValueRef src_c0 = NULL;
4116 LLVMValueRef src_c1 = NULL;
4117 LLVMValueRef src0 = NULL;
4118 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4119 switch (instr->intrinsic) {
4120 case nir_intrinsic_interp_var_at_centroid:
4121 location = INTERP_CENTROID;
4122 break;
4123 case nir_intrinsic_interp_var_at_sample:
4124 case nir_intrinsic_interp_var_at_offset:
4125 location = INTERP_CENTER;
4126 src0 = get_src(ctx, instr->src[0]);
4127 break;
4128 default:
4129 break;
4130 }
4131
4132 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4133 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4134 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4135 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4136 LLVMValueRef sample_position;
4137 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4138
4139 /* fetch sample ID */
4140 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4141
4142 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4143 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4144 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4145 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4146 }
4147 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4148 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4149
4150 if (location == INTERP_CENTER) {
4151 LLVMValueRef ij_out[2];
4152 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4153
4154 /*
4155 * take the I then J parameters, and the DDX/Y for it, and
4156 * calculate the IJ inputs for the interpolator.
4157 * temp1 = ddx * offset/sample.x + I;
4158 * interp_param.I = ddy * offset/sample.y + temp1;
4159 * temp1 = ddx * offset/sample.x + J;
4160 * interp_param.J = ddy * offset/sample.y + temp1;
4161 */
4162 for (unsigned i = 0; i < 2; i++) {
4163 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4164 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4165 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4166 ddxy_out, ix_ll, "");
4167 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4168 ddxy_out, iy_ll, "");
4169 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4170 interp_param, ix_ll, "");
4171 LLVMValueRef temp1, temp2;
4172
4173 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4174 ctx->ac.f32, "");
4175
4176 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4177 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4178
4179 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4180 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4181
4182 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4183 temp2, ctx->ac.i32, "");
4184 }
4185 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4186
4187 }
4188
4189 for (chan = 0; chan < 4; chan++) {
4190 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4191
4192 if (interp_param) {
4193 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4194 interp_param, ctx->ac.v2f32, "");
4195 LLVMValueRef i = LLVMBuildExtractElement(
4196 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4197 LLVMValueRef j = LLVMBuildExtractElement(
4198 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4199
4200 result[chan] = ac_build_fs_interp(&ctx->ac,
4201 llvm_chan, attr_number,
4202 ctx->abi->prim_mask, i, j);
4203 } else {
4204 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4205 LLVMConstInt(ctx->ac.i32, 2, false),
4206 llvm_chan, attr_number,
4207 ctx->abi->prim_mask);
4208 }
4209 }
4210 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4211 instr->variables[0]->var->data.location_frac);
4212 }
4213
4214 static void
4215 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4216 {
4217 LLVMValueRef gs_next_vertex;
4218 LLVMValueRef can_emit;
4219 int idx;
4220 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4221
4222 assert(stream == 0);
4223
4224 /* Write vertex attribute values to GSVS ring */
4225 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4226 ctx->gs_next_vertex,
4227 "");
4228
4229 /* If this thread has already emitted the declared maximum number of
4230 * vertices, kill it: excessive vertex emissions are not supposed to
4231 * have any effect, and GS threads have no externally observable
4232 * effects other than emitting vertices.
4233 */
4234 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4235 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4236 ac_build_kill_if_false(&ctx->ac, can_emit);
4237
4238 /* loop num outputs */
4239 idx = 0;
4240 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4241 LLVMValueRef *out_ptr = &addrs[i * 4];
4242 int length = 4;
4243 int slot = idx;
4244 int slot_inc = 1;
4245
4246 if (!(ctx->output_mask & (1ull << i)))
4247 continue;
4248
4249 if (i == VARYING_SLOT_CLIP_DIST0) {
4250 /* pack clip and cull into a single set of slots */
4251 length = ctx->num_output_clips + ctx->num_output_culls;
4252 if (length > 4)
4253 slot_inc = 2;
4254 }
4255 for (unsigned j = 0; j < length; j++) {
4256 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4257 out_ptr[j], "");
4258 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4259 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4260 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4261
4262 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4263
4264 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4265 out_val, 1,
4266 voffset, ctx->gs2vs_offset, 0,
4267 1, 1, true, true);
4268 }
4269 idx += slot_inc;
4270 }
4271
4272 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
4273 ctx->ac.i32_1, "");
4274 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
4275
4276 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4277 }
4278
4279 static void
4280 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4281 {
4282 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4283 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4284 }
4285
4286 static LLVMValueRef
4287 load_tess_coord(struct ac_shader_abi *abi)
4288 {
4289 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4290
4291 LLVMValueRef coord[4] = {
4292 ctx->tes_u,
4293 ctx->tes_v,
4294 ctx->ac.f32_0,
4295 ctx->ac.f32_0,
4296 };
4297
4298 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4299 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
4300 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
4301
4302 return ac_build_gather_values(&ctx->ac, coord, 3);
4303 }
4304
4305 static LLVMValueRef
4306 load_patch_vertices_in(struct ac_shader_abi *abi)
4307 {
4308 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4309 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4310 }
4311
4312 static void visit_intrinsic(struct ac_nir_context *ctx,
4313 nir_intrinsic_instr *instr)
4314 {
4315 LLVMValueRef result = NULL;
4316
4317 switch (instr->intrinsic) {
4318 case nir_intrinsic_ballot:
4319 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4320 break;
4321 case nir_intrinsic_read_invocation:
4322 case nir_intrinsic_read_first_invocation: {
4323 LLVMValueRef args[2];
4324
4325 /* Value */
4326 args[0] = get_src(ctx, instr->src[0]);
4327
4328 unsigned num_args;
4329 const char *intr_name;
4330 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4331 num_args = 2;
4332 intr_name = "llvm.amdgcn.readlane";
4333
4334 /* Invocation */
4335 args[1] = get_src(ctx, instr->src[1]);
4336 } else {
4337 num_args = 1;
4338 intr_name = "llvm.amdgcn.readfirstlane";
4339 }
4340
4341 /* We currently have no other way to prevent LLVM from lifting the icmp
4342 * calls to a dominating basic block.
4343 */
4344 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4345
4346 result = ac_build_intrinsic(&ctx->ac, intr_name,
4347 ctx->ac.i32, args, num_args,
4348 AC_FUNC_ATTR_READNONE |
4349 AC_FUNC_ATTR_CONVERGENT);
4350 break;
4351 }
4352 case nir_intrinsic_load_subgroup_invocation:
4353 result = ac_get_thread_id(&ctx->ac);
4354 break;
4355 case nir_intrinsic_load_work_group_id: {
4356 LLVMValueRef values[3];
4357
4358 for (int i = 0; i < 3; i++) {
4359 values[i] = ctx->abi->workgroup_ids[i] ?
4360 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4361 }
4362
4363 result = ac_build_gather_values(&ctx->ac, values, 3);
4364 break;
4365 }
4366 case nir_intrinsic_load_base_vertex: {
4367 result = ctx->abi->load_base_vertex(ctx->abi);
4368 break;
4369 }
4370 case nir_intrinsic_load_local_group_size:
4371 result = ctx->abi->load_local_group_size(ctx->abi);
4372 break;
4373 case nir_intrinsic_load_vertex_id:
4374 result = LLVMBuildAdd(ctx->ac.builder, ctx->abi->vertex_id,
4375 ctx->abi->base_vertex, "");
4376 break;
4377 case nir_intrinsic_load_vertex_id_zero_base: {
4378 result = ctx->abi->vertex_id;
4379 break;
4380 }
4381 case nir_intrinsic_load_local_invocation_id: {
4382 result = ctx->abi->local_invocation_ids;
4383 break;
4384 }
4385 case nir_intrinsic_load_base_instance:
4386 result = ctx->abi->start_instance;
4387 break;
4388 case nir_intrinsic_load_draw_id:
4389 result = ctx->abi->draw_id;
4390 break;
4391 case nir_intrinsic_load_view_index:
4392 result = ctx->abi->view_index;
4393 break;
4394 case nir_intrinsic_load_invocation_id:
4395 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4396 result = ac_unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4397 else
4398 result = ctx->abi->gs_invocation_id;
4399 break;
4400 case nir_intrinsic_load_primitive_id:
4401 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4402 result = ctx->abi->gs_prim_id;
4403 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4404 result = ctx->abi->tcs_patch_id;
4405 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4406 result = ctx->abi->tes_patch_id;
4407 } else
4408 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4409 break;
4410 case nir_intrinsic_load_sample_id:
4411 result = ac_unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4412 break;
4413 case nir_intrinsic_load_sample_pos:
4414 result = load_sample_pos(ctx);
4415 break;
4416 case nir_intrinsic_load_sample_mask_in:
4417 result = ctx->abi->load_sample_mask_in(ctx->abi);
4418 break;
4419 case nir_intrinsic_load_frag_coord: {
4420 LLVMValueRef values[4] = {
4421 ctx->abi->frag_pos[0],
4422 ctx->abi->frag_pos[1],
4423 ctx->abi->frag_pos[2],
4424 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4425 };
4426 result = ac_build_gather_values(&ctx->ac, values, 4);
4427 break;
4428 }
4429 case nir_intrinsic_load_front_face:
4430 result = ctx->abi->front_face;
4431 break;
4432 case nir_intrinsic_load_helper_invocation:
4433 result = visit_load_helper_invocation(ctx);
4434 break;
4435 case nir_intrinsic_load_instance_id:
4436 result = ctx->abi->instance_id;
4437 break;
4438 case nir_intrinsic_load_num_work_groups:
4439 result = ctx->abi->num_work_groups;
4440 break;
4441 case nir_intrinsic_load_local_invocation_index:
4442 result = visit_load_local_invocation_index(ctx);
4443 break;
4444 case nir_intrinsic_load_subgroup_id:
4445 result = visit_load_subgroup_id(ctx);
4446 break;
4447 case nir_intrinsic_load_num_subgroups:
4448 result = visit_load_num_subgroups(ctx);
4449 break;
4450 case nir_intrinsic_first_invocation:
4451 result = visit_first_invocation(ctx);
4452 break;
4453 case nir_intrinsic_load_push_constant:
4454 result = visit_load_push_constant(ctx, instr);
4455 break;
4456 case nir_intrinsic_vulkan_resource_index: {
4457 LLVMValueRef index = get_src(ctx, instr->src[0]);
4458 unsigned desc_set = nir_intrinsic_desc_set(instr);
4459 unsigned binding = nir_intrinsic_binding(instr);
4460
4461 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4462 binding);
4463 break;
4464 }
4465 case nir_intrinsic_vulkan_resource_reindex:
4466 result = visit_vulkan_resource_reindex(ctx, instr);
4467 break;
4468 case nir_intrinsic_store_ssbo:
4469 visit_store_ssbo(ctx, instr);
4470 break;
4471 case nir_intrinsic_load_ssbo:
4472 result = visit_load_buffer(ctx, instr);
4473 break;
4474 case nir_intrinsic_ssbo_atomic_add:
4475 case nir_intrinsic_ssbo_atomic_imin:
4476 case nir_intrinsic_ssbo_atomic_umin:
4477 case nir_intrinsic_ssbo_atomic_imax:
4478 case nir_intrinsic_ssbo_atomic_umax:
4479 case nir_intrinsic_ssbo_atomic_and:
4480 case nir_intrinsic_ssbo_atomic_or:
4481 case nir_intrinsic_ssbo_atomic_xor:
4482 case nir_intrinsic_ssbo_atomic_exchange:
4483 case nir_intrinsic_ssbo_atomic_comp_swap:
4484 result = visit_atomic_ssbo(ctx, instr);
4485 break;
4486 case nir_intrinsic_load_ubo:
4487 result = visit_load_ubo_buffer(ctx, instr);
4488 break;
4489 case nir_intrinsic_get_buffer_size:
4490 result = visit_get_buffer_size(ctx, instr);
4491 break;
4492 case nir_intrinsic_load_var:
4493 result = visit_load_var(ctx, instr);
4494 break;
4495 case nir_intrinsic_store_var:
4496 visit_store_var(ctx, instr);
4497 break;
4498 case nir_intrinsic_load_shared:
4499 result = visit_load_shared(ctx, instr);
4500 break;
4501 case nir_intrinsic_store_shared:
4502 visit_store_shared(ctx, instr);
4503 break;
4504 case nir_intrinsic_image_samples:
4505 result = visit_image_samples(ctx, instr);
4506 break;
4507 case nir_intrinsic_image_load:
4508 result = visit_image_load(ctx, instr);
4509 break;
4510 case nir_intrinsic_image_store:
4511 visit_image_store(ctx, instr);
4512 break;
4513 case nir_intrinsic_image_atomic_add:
4514 case nir_intrinsic_image_atomic_min:
4515 case nir_intrinsic_image_atomic_max:
4516 case nir_intrinsic_image_atomic_and:
4517 case nir_intrinsic_image_atomic_or:
4518 case nir_intrinsic_image_atomic_xor:
4519 case nir_intrinsic_image_atomic_exchange:
4520 case nir_intrinsic_image_atomic_comp_swap:
4521 result = visit_image_atomic(ctx, instr);
4522 break;
4523 case nir_intrinsic_image_size:
4524 result = visit_image_size(ctx, instr);
4525 break;
4526 case nir_intrinsic_shader_clock:
4527 result = ac_build_shader_clock(&ctx->ac);
4528 break;
4529 case nir_intrinsic_discard:
4530 case nir_intrinsic_discard_if:
4531 emit_discard(ctx, instr);
4532 break;
4533 case nir_intrinsic_memory_barrier:
4534 case nir_intrinsic_group_memory_barrier:
4535 case nir_intrinsic_memory_barrier_atomic_counter:
4536 case nir_intrinsic_memory_barrier_buffer:
4537 case nir_intrinsic_memory_barrier_image:
4538 case nir_intrinsic_memory_barrier_shared:
4539 emit_membar(&ctx->ac, instr);
4540 break;
4541 case nir_intrinsic_barrier:
4542 emit_barrier(&ctx->ac, ctx->stage);
4543 break;
4544 case nir_intrinsic_shared_atomic_add:
4545 case nir_intrinsic_shared_atomic_imin:
4546 case nir_intrinsic_shared_atomic_umin:
4547 case nir_intrinsic_shared_atomic_imax:
4548 case nir_intrinsic_shared_atomic_umax:
4549 case nir_intrinsic_shared_atomic_and:
4550 case nir_intrinsic_shared_atomic_or:
4551 case nir_intrinsic_shared_atomic_xor:
4552 case nir_intrinsic_shared_atomic_exchange:
4553 case nir_intrinsic_shared_atomic_comp_swap: {
4554 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
4555 result = visit_var_atomic(ctx, instr, ptr, 1);
4556 break;
4557 }
4558 case nir_intrinsic_var_atomic_add:
4559 case nir_intrinsic_var_atomic_imin:
4560 case nir_intrinsic_var_atomic_umin:
4561 case nir_intrinsic_var_atomic_imax:
4562 case nir_intrinsic_var_atomic_umax:
4563 case nir_intrinsic_var_atomic_and:
4564 case nir_intrinsic_var_atomic_or:
4565 case nir_intrinsic_var_atomic_xor:
4566 case nir_intrinsic_var_atomic_exchange:
4567 case nir_intrinsic_var_atomic_comp_swap: {
4568 LLVMValueRef ptr = build_gep_for_deref(ctx, instr->variables[0]);
4569 result = visit_var_atomic(ctx, instr, ptr, 0);
4570 break;
4571 }
4572 case nir_intrinsic_interp_var_at_centroid:
4573 case nir_intrinsic_interp_var_at_sample:
4574 case nir_intrinsic_interp_var_at_offset:
4575 result = visit_interp(ctx, instr);
4576 break;
4577 case nir_intrinsic_emit_vertex:
4578 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->abi->outputs);
4579 break;
4580 case nir_intrinsic_end_primitive:
4581 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4582 break;
4583 case nir_intrinsic_load_tess_coord:
4584 result = ctx->abi->load_tess_coord(ctx->abi);
4585 break;
4586 case nir_intrinsic_load_tess_level_outer:
4587 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4588 break;
4589 case nir_intrinsic_load_tess_level_inner:
4590 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4591 break;
4592 case nir_intrinsic_load_patch_vertices_in:
4593 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4594 break;
4595 case nir_intrinsic_vote_all: {
4596 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4597 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4598 break;
4599 }
4600 case nir_intrinsic_vote_any: {
4601 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4602 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4603 break;
4604 }
4605 default:
4606 fprintf(stderr, "Unknown intrinsic: ");
4607 nir_print_instr(&instr->instr, stderr);
4608 fprintf(stderr, "\n");
4609 break;
4610 }
4611 if (result) {
4612 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4613 }
4614 }
4615
4616 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
4617 {
4618 return abi->base_vertex;
4619 }
4620
4621 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4622 LLVMValueRef buffer_ptr, bool write)
4623 {
4624 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4625 LLVMValueRef result;
4626
4627 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4628
4629 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4630 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4631
4632 return result;
4633 }
4634
4635 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4636 {
4637 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4638 LLVMValueRef result;
4639
4640 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4641
4642 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4643 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4644
4645 return result;
4646 }
4647
4648 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4649 unsigned descriptor_set,
4650 unsigned base_index,
4651 unsigned constant_index,
4652 LLVMValueRef index,
4653 enum ac_descriptor_type desc_type,
4654 bool image, bool write)
4655 {
4656 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4657 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4658 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4659 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4660 unsigned offset = binding->offset;
4661 unsigned stride = binding->size;
4662 unsigned type_size;
4663 LLVMBuilderRef builder = ctx->ac.builder;
4664 LLVMTypeRef type;
4665
4666 assert(base_index < layout->binding_count);
4667
4668 switch (desc_type) {
4669 case AC_DESC_IMAGE:
4670 type = ctx->ac.v8i32;
4671 type_size = 32;
4672 break;
4673 case AC_DESC_FMASK:
4674 type = ctx->ac.v8i32;
4675 offset += 32;
4676 type_size = 32;
4677 break;
4678 case AC_DESC_SAMPLER:
4679 type = ctx->ac.v4i32;
4680 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4681 offset += 64;
4682
4683 type_size = 16;
4684 break;
4685 case AC_DESC_BUFFER:
4686 type = ctx->ac.v4i32;
4687 type_size = 16;
4688 break;
4689 default:
4690 unreachable("invalid desc_type\n");
4691 }
4692
4693 offset += constant_index * stride;
4694
4695 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4696 (!index || binding->immutable_samplers_equal)) {
4697 if (binding->immutable_samplers_equal)
4698 constant_index = 0;
4699
4700 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4701
4702 LLVMValueRef constants[] = {
4703 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4704 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4705 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4706 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4707 };
4708 return ac_build_gather_values(&ctx->ac, constants, 4);
4709 }
4710
4711 assert(stride % type_size == 0);
4712
4713 if (!index)
4714 index = ctx->ac.i32_0;
4715
4716 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4717
4718 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4719 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4720
4721 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4722 }
4723
4724 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4725 const nir_deref_var *deref,
4726 enum ac_descriptor_type desc_type,
4727 const nir_tex_instr *tex_instr,
4728 bool image, bool write)
4729 {
4730 LLVMValueRef index = NULL;
4731 unsigned constant_index = 0;
4732 unsigned descriptor_set;
4733 unsigned base_index;
4734
4735 if (!deref) {
4736 assert(tex_instr && !image);
4737 descriptor_set = 0;
4738 base_index = tex_instr->sampler_index;
4739 } else {
4740 const nir_deref *tail = &deref->deref;
4741 while (tail->child) {
4742 const nir_deref_array *child = nir_deref_as_array(tail->child);
4743 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4744
4745 if (!array_size)
4746 array_size = 1;
4747
4748 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4749
4750 if (child->deref_array_type == nir_deref_array_type_indirect) {
4751 LLVMValueRef indirect = get_src(ctx, child->indirect);
4752
4753 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4754 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4755
4756 if (!index)
4757 index = indirect;
4758 else
4759 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4760 }
4761
4762 constant_index += child->base_offset * array_size;
4763
4764 tail = &child->deref;
4765 }
4766 descriptor_set = deref->var->data.descriptor_set;
4767 base_index = deref->var->data.binding;
4768 }
4769
4770 return ctx->abi->load_sampler_desc(ctx->abi,
4771 descriptor_set,
4772 base_index,
4773 constant_index, index,
4774 desc_type, image, write);
4775 }
4776
4777 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4778 struct ac_image_args *args,
4779 const nir_tex_instr *instr,
4780 nir_texop op,
4781 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4782 LLVMValueRef *param, unsigned count,
4783 unsigned dmask)
4784 {
4785 unsigned is_rect = 0;
4786 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4787
4788 if (op == nir_texop_lod)
4789 da = false;
4790 /* Pad to power of two vector */
4791 while (count < util_next_power_of_two(count))
4792 param[count++] = LLVMGetUndef(ctx->i32);
4793
4794 if (count > 1)
4795 args->addr = ac_build_gather_values(ctx, param, count);
4796 else
4797 args->addr = param[0];
4798
4799 args->resource = res_ptr;
4800 args->sampler = samp_ptr;
4801
4802 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4803 args->addr = param[0];
4804 return;
4805 }
4806
4807 args->dmask = dmask;
4808 args->unorm = is_rect;
4809 args->da = da;
4810 }
4811
4812 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4813 *
4814 * SI-CI:
4815 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4816 * filtering manually. The driver sets img7 to a mask clearing
4817 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4818 * s_and_b32 samp0, samp0, img7
4819 *
4820 * VI:
4821 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4822 */
4823 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4824 LLVMValueRef res, LLVMValueRef samp)
4825 {
4826 LLVMBuilderRef builder = ctx->ac.builder;
4827 LLVMValueRef img7, samp0;
4828
4829 if (ctx->ac.chip_class >= VI)
4830 return samp;
4831
4832 img7 = LLVMBuildExtractElement(builder, res,
4833 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4834 samp0 = LLVMBuildExtractElement(builder, samp,
4835 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4836 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4837 return LLVMBuildInsertElement(builder, samp, samp0,
4838 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4839 }
4840
4841 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4842 nir_tex_instr *instr,
4843 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4844 LLVMValueRef *fmask_ptr)
4845 {
4846 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4847 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4848 else
4849 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4850 if (samp_ptr) {
4851 if (instr->sampler)
4852 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4853 else
4854 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4855 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4856 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4857 }
4858 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4859 instr->op == nir_texop_samples_identical))
4860 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4861 }
4862
4863 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4864 LLVMValueRef coord)
4865 {
4866 coord = ac_to_float(ctx, coord);
4867 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4868 coord = ac_to_integer(ctx, coord);
4869 return coord;
4870 }
4871
4872 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4873 {
4874 LLVMValueRef result = NULL;
4875 struct ac_image_args args = { 0 };
4876 unsigned dmask = 0xf;
4877 LLVMValueRef address[16];
4878 LLVMValueRef coords[5];
4879 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4880 LLVMValueRef bias = NULL, offsets = NULL;
4881 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4882 LLVMValueRef ddx = NULL, ddy = NULL;
4883 LLVMValueRef derivs[6];
4884 unsigned chan, count = 0;
4885 unsigned const_src = 0, num_deriv_comp = 0;
4886 bool lod_is_zero = false;
4887
4888 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4889
4890 for (unsigned i = 0; i < instr->num_srcs; i++) {
4891 switch (instr->src[i].src_type) {
4892 case nir_tex_src_coord:
4893 coord = get_src(ctx, instr->src[i].src);
4894 break;
4895 case nir_tex_src_projector:
4896 break;
4897 case nir_tex_src_comparator:
4898 comparator = get_src(ctx, instr->src[i].src);
4899 break;
4900 case nir_tex_src_offset:
4901 offsets = get_src(ctx, instr->src[i].src);
4902 const_src = i;
4903 break;
4904 case nir_tex_src_bias:
4905 bias = get_src(ctx, instr->src[i].src);
4906 break;
4907 case nir_tex_src_lod: {
4908 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4909
4910 if (val && val->i32[0] == 0)
4911 lod_is_zero = true;
4912 lod = get_src(ctx, instr->src[i].src);
4913 break;
4914 }
4915 case nir_tex_src_ms_index:
4916 sample_index = get_src(ctx, instr->src[i].src);
4917 break;
4918 case nir_tex_src_ms_mcs:
4919 break;
4920 case nir_tex_src_ddx:
4921 ddx = get_src(ctx, instr->src[i].src);
4922 num_deriv_comp = instr->src[i].src.ssa->num_components;
4923 break;
4924 case nir_tex_src_ddy:
4925 ddy = get_src(ctx, instr->src[i].src);
4926 break;
4927 case nir_tex_src_texture_offset:
4928 case nir_tex_src_sampler_offset:
4929 case nir_tex_src_plane:
4930 default:
4931 break;
4932 }
4933 }
4934
4935 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4936 result = get_buffer_size(ctx, res_ptr, true);
4937 goto write_result;
4938 }
4939
4940 if (instr->op == nir_texop_texture_samples) {
4941 LLVMValueRef res, samples, is_msaa;
4942 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4943 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4944 LLVMConstInt(ctx->ac.i32, 3, false), "");
4945 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4946 LLVMConstInt(ctx->ac.i32, 28, false), "");
4947 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4948 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4949 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4950 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4951
4952 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4953 LLVMConstInt(ctx->ac.i32, 16, false), "");
4954 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4955 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4956 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4957 samples, "");
4958 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4959 ctx->ac.i32_1, "");
4960 result = samples;
4961 goto write_result;
4962 }
4963
4964 if (coord)
4965 for (chan = 0; chan < instr->coord_components; chan++)
4966 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4967
4968 if (offsets && instr->op != nir_texop_txf) {
4969 LLVMValueRef offset[3], pack;
4970 for (chan = 0; chan < 3; ++chan)
4971 offset[chan] = ctx->ac.i32_0;
4972
4973 args.offset = true;
4974 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4975 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4976 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4977 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4978 if (chan)
4979 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4980 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4981 }
4982 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4983 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4984 address[count++] = pack;
4985
4986 }
4987 /* pack LOD bias value */
4988 if (instr->op == nir_texop_txb && bias) {
4989 address[count++] = bias;
4990 }
4991
4992 /* Pack depth comparison value */
4993 if (instr->is_shadow && comparator) {
4994 LLVMValueRef z = ac_to_float(&ctx->ac,
4995 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4996
4997 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4998 * so the depth comparison value isn't clamped for Z16 and
4999 * Z24 anymore. Do it manually here.
5000 *
5001 * It's unnecessary if the original texture format was
5002 * Z32_FLOAT, but we don't know that here.
5003 */
5004 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
5005 z = ac_build_clamp(&ctx->ac, z);
5006
5007 address[count++] = z;
5008 }
5009
5010 /* pack derivatives */
5011 if (ddx || ddy) {
5012 int num_src_deriv_channels, num_dest_deriv_channels;
5013 switch (instr->sampler_dim) {
5014 case GLSL_SAMPLER_DIM_3D:
5015 case GLSL_SAMPLER_DIM_CUBE:
5016 num_deriv_comp = 3;
5017 num_src_deriv_channels = 3;
5018 num_dest_deriv_channels = 3;
5019 break;
5020 case GLSL_SAMPLER_DIM_2D:
5021 default:
5022 num_src_deriv_channels = 2;
5023 num_dest_deriv_channels = 2;
5024 num_deriv_comp = 2;
5025 break;
5026 case GLSL_SAMPLER_DIM_1D:
5027 num_src_deriv_channels = 1;
5028 if (ctx->ac.chip_class >= GFX9) {
5029 num_dest_deriv_channels = 2;
5030 num_deriv_comp = 2;
5031 } else {
5032 num_dest_deriv_channels = 1;
5033 num_deriv_comp = 1;
5034 }
5035 break;
5036 }
5037
5038 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
5039 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
5040 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
5041 }
5042 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
5043 derivs[i] = ctx->ac.f32_0;
5044 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
5045 }
5046 }
5047
5048 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
5049 for (chan = 0; chan < instr->coord_components; chan++)
5050 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
5051 if (instr->coord_components == 3)
5052 coords[3] = LLVMGetUndef(ctx->ac.f32);
5053 ac_prepare_cube_coords(&ctx->ac,
5054 instr->op == nir_texop_txd, instr->is_array,
5055 instr->op == nir_texop_lod, coords, derivs);
5056 if (num_deriv_comp)
5057 num_deriv_comp--;
5058 }
5059
5060 if (ddx || ddy) {
5061 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
5062 address[count++] = derivs[i];
5063 }
5064
5065 /* Pack texture coordinates */
5066 if (coord) {
5067 address[count++] = coords[0];
5068 if (instr->coord_components > 1) {
5069 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
5070 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
5071 }
5072 address[count++] = coords[1];
5073 }
5074 if (instr->coord_components > 2) {
5075 if ((instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
5076 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
5077 instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
5078 instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
5079 instr->is_array &&
5080 instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
5081 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
5082 }
5083 address[count++] = coords[2];
5084 }
5085
5086 if (ctx->ac.chip_class >= GFX9) {
5087 LLVMValueRef filler;
5088 if (instr->op == nir_texop_txf)
5089 filler = ctx->ac.i32_0;
5090 else
5091 filler = LLVMConstReal(ctx->ac.f32, 0.5);
5092
5093 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
5094 /* No nir_texop_lod, because it does not take a slice
5095 * even with array textures. */
5096 if (instr->is_array && instr->op != nir_texop_lod ) {
5097 address[count] = address[count - 1];
5098 address[count - 1] = filler;
5099 count++;
5100 } else
5101 address[count++] = filler;
5102 }
5103 }
5104 }
5105
5106 /* Pack LOD */
5107 if (lod && ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && !lod_is_zero)) {
5108 address[count++] = lod;
5109 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5110 address[count++] = sample_index;
5111 } else if(instr->op == nir_texop_txs) {
5112 count = 0;
5113 if (lod)
5114 address[count++] = lod;
5115 else
5116 address[count++] = ctx->ac.i32_0;
5117 }
5118
5119 for (chan = 0; chan < count; chan++) {
5120 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5121 address[chan], ctx->ac.i32, "");
5122 }
5123
5124 if (instr->op == nir_texop_samples_identical) {
5125 LLVMValueRef txf_address[4];
5126 struct ac_image_args txf_args = { 0 };
5127 unsigned txf_count = count;
5128 memcpy(txf_address, address, sizeof(txf_address));
5129
5130 if (!instr->is_array)
5131 txf_address[2] = ctx->ac.i32_0;
5132 txf_address[3] = ctx->ac.i32_0;
5133
5134 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5135 fmask_ptr, NULL,
5136 txf_address, txf_count, 0xf);
5137
5138 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5139
5140 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5141 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5142 goto write_result;
5143 }
5144
5145 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5146 instr->op != nir_texop_txs) {
5147 unsigned sample_chan = instr->is_array ? 3 : 2;
5148 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5149 address[0],
5150 address[1],
5151 instr->is_array ? address[2] : NULL,
5152 address[sample_chan],
5153 fmask_ptr);
5154 }
5155
5156 if (offsets && instr->op == nir_texop_txf) {
5157 nir_const_value *const_offset =
5158 nir_src_as_const_value(instr->src[const_src].src);
5159 int num_offsets = instr->src[const_src].src.ssa->num_components;
5160 assert(const_offset);
5161 num_offsets = MIN2(num_offsets, instr->coord_components);
5162 if (num_offsets > 2)
5163 address[2] = LLVMBuildAdd(ctx->ac.builder,
5164 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5165 if (num_offsets > 1)
5166 address[1] = LLVMBuildAdd(ctx->ac.builder,
5167 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5168 address[0] = LLVMBuildAdd(ctx->ac.builder,
5169 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5170
5171 }
5172
5173 /* TODO TG4 support */
5174 if (instr->op == nir_texop_tg4) {
5175 if (instr->is_shadow)
5176 dmask = 1;
5177 else
5178 dmask = 1 << instr->component;
5179 }
5180 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5181 res_ptr, samp_ptr, address, count, dmask);
5182
5183 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5184
5185 if (instr->op == nir_texop_query_levels)
5186 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5187 else if (instr->is_shadow && instr->is_new_style_shadow &&
5188 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5189 instr->op != nir_texop_tg4)
5190 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5191 else if (instr->op == nir_texop_txs &&
5192 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5193 instr->is_array) {
5194 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5195 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5196 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5197 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5198 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5199 } else if (ctx->ac.chip_class >= GFX9 &&
5200 instr->op == nir_texop_txs &&
5201 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5202 instr->is_array) {
5203 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5204 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5205 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5206 ctx->ac.i32_1, "");
5207 } else if (instr->dest.ssa.num_components != 4)
5208 result = ac_trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5209
5210 write_result:
5211 if (result) {
5212 assert(instr->dest.is_ssa);
5213 result = ac_to_integer(&ctx->ac, result);
5214 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5215 }
5216 }
5217
5218
5219 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5220 {
5221 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5222 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5223
5224 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5225 _mesa_hash_table_insert(ctx->phis, instr, result);
5226 }
5227
5228 static void visit_post_phi(struct ac_nir_context *ctx,
5229 nir_phi_instr *instr,
5230 LLVMValueRef llvm_phi)
5231 {
5232 nir_foreach_phi_src(src, instr) {
5233 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5234 LLVMValueRef llvm_src = get_src(ctx, src->src);
5235
5236 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5237 }
5238 }
5239
5240 static void phi_post_pass(struct ac_nir_context *ctx)
5241 {
5242 struct hash_entry *entry;
5243 hash_table_foreach(ctx->phis, entry) {
5244 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5245 (LLVMValueRef)entry->data);
5246 }
5247 }
5248
5249
5250 static void visit_ssa_undef(struct ac_nir_context *ctx,
5251 const nir_ssa_undef_instr *instr)
5252 {
5253 unsigned num_components = instr->def.num_components;
5254 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5255 LLVMValueRef undef;
5256
5257 if (num_components == 1)
5258 undef = LLVMGetUndef(type);
5259 else {
5260 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5261 }
5262 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5263 }
5264
5265 static void visit_jump(struct ac_llvm_context *ctx,
5266 const nir_jump_instr *instr)
5267 {
5268 switch (instr->type) {
5269 case nir_jump_break:
5270 ac_build_break(ctx);
5271 break;
5272 case nir_jump_continue:
5273 ac_build_continue(ctx);
5274 break;
5275 default:
5276 fprintf(stderr, "Unknown NIR jump instr: ");
5277 nir_print_instr(&instr->instr, stderr);
5278 fprintf(stderr, "\n");
5279 abort();
5280 }
5281 }
5282
5283 static void visit_cf_list(struct ac_nir_context *ctx,
5284 struct exec_list *list);
5285
5286 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5287 {
5288 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5289 nir_foreach_instr(instr, block)
5290 {
5291 switch (instr->type) {
5292 case nir_instr_type_alu:
5293 visit_alu(ctx, nir_instr_as_alu(instr));
5294 break;
5295 case nir_instr_type_load_const:
5296 visit_load_const(ctx, nir_instr_as_load_const(instr));
5297 break;
5298 case nir_instr_type_intrinsic:
5299 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5300 break;
5301 case nir_instr_type_tex:
5302 visit_tex(ctx, nir_instr_as_tex(instr));
5303 break;
5304 case nir_instr_type_phi:
5305 visit_phi(ctx, nir_instr_as_phi(instr));
5306 break;
5307 case nir_instr_type_ssa_undef:
5308 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5309 break;
5310 case nir_instr_type_jump:
5311 visit_jump(&ctx->ac, nir_instr_as_jump(instr));
5312 break;
5313 default:
5314 fprintf(stderr, "Unknown NIR instr type: ");
5315 nir_print_instr(instr, stderr);
5316 fprintf(stderr, "\n");
5317 abort();
5318 }
5319 }
5320
5321 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5322 }
5323
5324 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5325 {
5326 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5327
5328 nir_block *then_block =
5329 (nir_block *) exec_list_get_head(&if_stmt->then_list);
5330
5331 ac_build_uif(&ctx->ac, value, then_block->index);
5332
5333 visit_cf_list(ctx, &if_stmt->then_list);
5334
5335 if (!exec_list_is_empty(&if_stmt->else_list)) {
5336 nir_block *else_block =
5337 (nir_block *) exec_list_get_head(&if_stmt->else_list);
5338
5339 ac_build_else(&ctx->ac, else_block->index);
5340 visit_cf_list(ctx, &if_stmt->else_list);
5341 }
5342
5343 ac_build_endif(&ctx->ac, then_block->index);
5344 }
5345
5346 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5347 {
5348 nir_block *first_loop_block =
5349 (nir_block *) exec_list_get_head(&loop->body);
5350
5351 ac_build_bgnloop(&ctx->ac, first_loop_block->index);
5352
5353 visit_cf_list(ctx, &loop->body);
5354
5355 ac_build_endloop(&ctx->ac, first_loop_block->index);
5356 }
5357
5358 static void visit_cf_list(struct ac_nir_context *ctx,
5359 struct exec_list *list)
5360 {
5361 foreach_list_typed(nir_cf_node, node, node, list)
5362 {
5363 switch (node->type) {
5364 case nir_cf_node_block:
5365 visit_block(ctx, nir_cf_node_as_block(node));
5366 break;
5367
5368 case nir_cf_node_if:
5369 visit_if(ctx, nir_cf_node_as_if(node));
5370 break;
5371
5372 case nir_cf_node_loop:
5373 visit_loop(ctx, nir_cf_node_as_loop(node));
5374 break;
5375
5376 default:
5377 assert(0);
5378 }
5379 }
5380 }
5381
5382 static void
5383 handle_vs_input_decl(struct radv_shader_context *ctx,
5384 struct nir_variable *variable)
5385 {
5386 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5387 LLVMValueRef t_offset;
5388 LLVMValueRef t_list;
5389 LLVMValueRef input;
5390 LLVMValueRef buffer_index;
5391 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5392 int idx = variable->data.location;
5393 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5394 uint8_t input_usage_mask =
5395 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5396 unsigned num_channels = util_last_bit(input_usage_mask);
5397
5398 variable->data.driver_location = idx * 4;
5399
5400 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5401 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5402 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
5403 ctx->abi.start_instance, "");
5404 if (ctx->options->key.vs.as_ls) {
5405 ctx->shader_info->vs.vgpr_comp_cnt =
5406 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5407 } else {
5408 ctx->shader_info->vs.vgpr_comp_cnt =
5409 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5410 }
5411 } else
5412 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
5413 ctx->abi.base_vertex, "");
5414 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5415
5416 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5417
5418 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5419 buffer_index,
5420 ctx->ac.i32_0,
5421 num_channels, false, true);
5422
5423 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5424
5425 for (unsigned chan = 0; chan < 4; chan++) {
5426 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5427 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5428 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
5429 input, llvm_chan, ""));
5430 }
5431 }
5432 }
5433
5434 static void interp_fs_input(struct radv_shader_context *ctx,
5435 unsigned attr,
5436 LLVMValueRef interp_param,
5437 LLVMValueRef prim_mask,
5438 LLVMValueRef result[4])
5439 {
5440 LLVMValueRef attr_number;
5441 unsigned chan;
5442 LLVMValueRef i, j;
5443 bool interp = interp_param != NULL;
5444
5445 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5446
5447 /* fs.constant returns the param from the middle vertex, so it's not
5448 * really useful for flat shading. It's meant to be used for custom
5449 * interpolation (but the intrinsic can't fetch from the other two
5450 * vertices).
5451 *
5452 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5453 * to do the right thing. The only reason we use fs.constant is that
5454 * fs.interp cannot be used on integers, because they can be equal
5455 * to NaN.
5456 */
5457 if (interp) {
5458 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
5459 ctx->ac.v2f32, "");
5460
5461 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5462 ctx->ac.i32_0, "");
5463 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5464 ctx->ac.i32_1, "");
5465 }
5466
5467 for (chan = 0; chan < 4; chan++) {
5468 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5469
5470 if (interp) {
5471 result[chan] = ac_build_fs_interp(&ctx->ac,
5472 llvm_chan,
5473 attr_number,
5474 prim_mask, i, j);
5475 } else {
5476 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5477 LLVMConstInt(ctx->ac.i32, 2, false),
5478 llvm_chan,
5479 attr_number,
5480 prim_mask);
5481 }
5482 }
5483 }
5484
5485 static void
5486 handle_fs_input_decl(struct radv_shader_context *ctx,
5487 struct nir_variable *variable)
5488 {
5489 int idx = variable->data.location;
5490 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5491 LLVMValueRef interp;
5492
5493 variable->data.driver_location = idx * 4;
5494 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5495
5496 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5497 unsigned interp_type;
5498 if (variable->data.sample)
5499 interp_type = INTERP_SAMPLE;
5500 else if (variable->data.centroid)
5501 interp_type = INTERP_CENTROID;
5502 else
5503 interp_type = INTERP_CENTER;
5504
5505 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5506 } else
5507 interp = NULL;
5508
5509 for (unsigned i = 0; i < attrib_count; ++i)
5510 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5511
5512 }
5513
5514 static void
5515 handle_vs_inputs(struct radv_shader_context *ctx,
5516 struct nir_shader *nir) {
5517 nir_foreach_variable(variable, &nir->inputs)
5518 handle_vs_input_decl(ctx, variable);
5519 }
5520
5521 static void
5522 prepare_interp_optimize(struct radv_shader_context *ctx,
5523 struct nir_shader *nir)
5524 {
5525 if (!ctx->options->key.fs.multisample)
5526 return;
5527
5528 bool uses_center = false;
5529 bool uses_centroid = false;
5530 nir_foreach_variable(variable, &nir->inputs) {
5531 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5532 variable->data.sample)
5533 continue;
5534
5535 if (variable->data.centroid)
5536 uses_centroid = true;
5537 else
5538 uses_center = true;
5539 }
5540
5541 if (uses_center && uses_centroid) {
5542 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5543 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5544 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5545 }
5546 }
5547
5548 static void
5549 handle_fs_inputs(struct radv_shader_context *ctx,
5550 struct nir_shader *nir)
5551 {
5552 prepare_interp_optimize(ctx, nir);
5553
5554 nir_foreach_variable(variable, &nir->inputs)
5555 handle_fs_input_decl(ctx, variable);
5556
5557 unsigned index = 0;
5558
5559 if (ctx->shader_info->info.ps.uses_input_attachments ||
5560 ctx->shader_info->info.needs_multiview_view_index)
5561 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5562
5563 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5564 LLVMValueRef interp_param;
5565 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5566
5567 if (!(ctx->input_mask & (1ull << i)))
5568 continue;
5569
5570 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5571 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5572 interp_param = *inputs;
5573 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5574 inputs);
5575
5576 if (!interp_param)
5577 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5578 ++index;
5579 } else if (i == VARYING_SLOT_POS) {
5580 for(int i = 0; i < 3; ++i)
5581 inputs[i] = ctx->abi.frag_pos[i];
5582
5583 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5584 ctx->abi.frag_pos[3]);
5585 }
5586 }
5587 ctx->shader_info->fs.num_interp = index;
5588 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5589
5590 if (ctx->shader_info->info.needs_multiview_view_index)
5591 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5592 }
5593
5594 static void
5595 scan_shader_output_decl(struct radv_shader_context *ctx,
5596 struct nir_variable *variable,
5597 struct nir_shader *shader,
5598 gl_shader_stage stage)
5599 {
5600 int idx = variable->data.location + variable->data.index;
5601 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5602 uint64_t mask_attribs;
5603
5604 variable->data.driver_location = idx * 4;
5605
5606 /* tess ctrl has it's own load/store paths for outputs */
5607 if (stage == MESA_SHADER_TESS_CTRL)
5608 return;
5609
5610 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5611 if (stage == MESA_SHADER_VERTEX ||
5612 stage == MESA_SHADER_TESS_EVAL ||
5613 stage == MESA_SHADER_GEOMETRY) {
5614 if (idx == VARYING_SLOT_CLIP_DIST0) {
5615 int length = shader->info.clip_distance_array_size +
5616 shader->info.cull_distance_array_size;
5617 if (stage == MESA_SHADER_VERTEX) {
5618 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5619 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5620 }
5621 if (stage == MESA_SHADER_TESS_EVAL) {
5622 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5623 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5624 }
5625
5626 if (length > 4)
5627 attrib_count = 2;
5628 else
5629 attrib_count = 1;
5630 mask_attribs = 1ull << idx;
5631 }
5632 }
5633
5634 ctx->output_mask |= mask_attribs;
5635 }
5636
5637 static void
5638 handle_shader_output_decl(struct ac_llvm_context *ctx,
5639 struct ac_shader_abi *abi,
5640 struct nir_shader *nir,
5641 struct nir_variable *variable,
5642 gl_shader_stage stage)
5643 {
5644 unsigned output_loc = variable->data.driver_location / 4;
5645 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5646
5647 /* tess ctrl has it's own load/store paths for outputs */
5648 if (stage == MESA_SHADER_TESS_CTRL)
5649 return;
5650
5651 if (stage == MESA_SHADER_VERTEX ||
5652 stage == MESA_SHADER_TESS_EVAL ||
5653 stage == MESA_SHADER_GEOMETRY) {
5654 int idx = variable->data.location + variable->data.index;
5655 if (idx == VARYING_SLOT_CLIP_DIST0) {
5656 int length = nir->info.clip_distance_array_size +
5657 nir->info.cull_distance_array_size;
5658
5659 if (length > 4)
5660 attrib_count = 2;
5661 else
5662 attrib_count = 1;
5663 }
5664 }
5665
5666 for (unsigned i = 0; i < attrib_count; ++i) {
5667 for (unsigned chan = 0; chan < 4; chan++) {
5668 abi->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5669 ac_build_alloca_undef(ctx, ctx->f32, "");
5670 }
5671 }
5672 }
5673
5674 static LLVMTypeRef
5675 glsl_base_to_llvm_type(struct ac_llvm_context *ac,
5676 enum glsl_base_type type)
5677 {
5678 switch (type) {
5679 case GLSL_TYPE_INT:
5680 case GLSL_TYPE_UINT:
5681 case GLSL_TYPE_BOOL:
5682 case GLSL_TYPE_SUBROUTINE:
5683 return ac->i32;
5684 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5685 return ac->f32;
5686 case GLSL_TYPE_INT64:
5687 case GLSL_TYPE_UINT64:
5688 return ac->i64;
5689 case GLSL_TYPE_DOUBLE:
5690 return ac->f64;
5691 default:
5692 unreachable("unknown GLSL type");
5693 }
5694 }
5695
5696 static LLVMTypeRef
5697 glsl_to_llvm_type(struct ac_llvm_context *ac,
5698 const struct glsl_type *type)
5699 {
5700 if (glsl_type_is_scalar(type)) {
5701 return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
5702 }
5703
5704 if (glsl_type_is_vector(type)) {
5705 return LLVMVectorType(
5706 glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
5707 glsl_get_vector_elements(type));
5708 }
5709
5710 if (glsl_type_is_matrix(type)) {
5711 return LLVMArrayType(
5712 glsl_to_llvm_type(ac, glsl_get_column_type(type)),
5713 glsl_get_matrix_columns(type));
5714 }
5715
5716 if (glsl_type_is_array(type)) {
5717 return LLVMArrayType(
5718 glsl_to_llvm_type(ac, glsl_get_array_element(type)),
5719 glsl_get_length(type));
5720 }
5721
5722 assert(glsl_type_is_struct(type));
5723
5724 LLVMTypeRef member_types[glsl_get_length(type)];
5725
5726 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5727 member_types[i] =
5728 glsl_to_llvm_type(ac,
5729 glsl_get_struct_field(type, i));
5730 }
5731
5732 return LLVMStructTypeInContext(ac->context, member_types,
5733 glsl_get_length(type), false);
5734 }
5735
5736 static void
5737 setup_locals(struct ac_nir_context *ctx,
5738 struct nir_function *func)
5739 {
5740 int i, j;
5741 ctx->num_locals = 0;
5742 nir_foreach_variable(variable, &func->impl->locals) {
5743 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5744 variable->data.driver_location = ctx->num_locals * 4;
5745 variable->data.location_frac = 0;
5746 ctx->num_locals += attrib_count;
5747 }
5748 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5749 if (!ctx->locals)
5750 return;
5751
5752 for (i = 0; i < ctx->num_locals; i++) {
5753 for (j = 0; j < 4; j++) {
5754 ctx->locals[i * 4 + j] =
5755 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5756 }
5757 }
5758 }
5759
5760 static void
5761 setup_shared(struct ac_nir_context *ctx,
5762 struct nir_shader *nir)
5763 {
5764 nir_foreach_variable(variable, &nir->shared) {
5765 LLVMValueRef shared =
5766 LLVMAddGlobalInAddressSpace(
5767 ctx->ac.module, glsl_to_llvm_type(&ctx->ac, variable->type),
5768 variable->name ? variable->name : "",
5769 AC_LOCAL_ADDR_SPACE);
5770 _mesa_hash_table_insert(ctx->vars, variable, shared);
5771 }
5772 }
5773
5774 /* Initialize arguments for the shader export intrinsic */
5775 static void
5776 si_llvm_init_export_args(struct radv_shader_context *ctx,
5777 LLVMValueRef *values,
5778 unsigned enabled_channels,
5779 unsigned target,
5780 struct ac_export_args *args)
5781 {
5782 /* Specify the channels that are enabled. */
5783 args->enabled_channels = enabled_channels;
5784
5785 /* Specify whether the EXEC mask represents the valid mask */
5786 args->valid_mask = 0;
5787
5788 /* Specify whether this is the last export */
5789 args->done = 0;
5790
5791 /* Specify the target we are exporting */
5792 args->target = target;
5793
5794 args->compr = false;
5795 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5796 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5797 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5798 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5799
5800 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5801 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5802 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5803 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5804 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5805 unsigned chan;
5806
5807 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5808 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5809 unsigned bits, bool hi) = NULL;
5810
5811 switch(col_format) {
5812 case V_028714_SPI_SHADER_ZERO:
5813 args->enabled_channels = 0; /* writemask */
5814 args->target = V_008DFC_SQ_EXP_NULL;
5815 break;
5816
5817 case V_028714_SPI_SHADER_32_R:
5818 args->enabled_channels = 1;
5819 args->out[0] = values[0];
5820 break;
5821
5822 case V_028714_SPI_SHADER_32_GR:
5823 args->enabled_channels = 0x3;
5824 args->out[0] = values[0];
5825 args->out[1] = values[1];
5826 break;
5827
5828 case V_028714_SPI_SHADER_32_AR:
5829 args->enabled_channels = 0x9;
5830 args->out[0] = values[0];
5831 args->out[3] = values[3];
5832 break;
5833
5834 case V_028714_SPI_SHADER_FP16_ABGR:
5835 args->enabled_channels = 0x5;
5836 packf = ac_build_cvt_pkrtz_f16;
5837 break;
5838
5839 case V_028714_SPI_SHADER_UNORM16_ABGR:
5840 args->enabled_channels = 0x5;
5841 packf = ac_build_cvt_pknorm_u16;
5842 break;
5843
5844 case V_028714_SPI_SHADER_SNORM16_ABGR:
5845 args->enabled_channels = 0x5;
5846 packf = ac_build_cvt_pknorm_i16;
5847 break;
5848
5849 case V_028714_SPI_SHADER_UINT16_ABGR:
5850 args->enabled_channels = 0x5;
5851 packi = ac_build_cvt_pk_u16;
5852 break;
5853
5854 case V_028714_SPI_SHADER_SINT16_ABGR:
5855 args->enabled_channels = 0x5;
5856 packi = ac_build_cvt_pk_i16;
5857 break;
5858
5859 default:
5860 case V_028714_SPI_SHADER_32_ABGR:
5861 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5862 break;
5863 }
5864
5865 /* Pack f16 or norm_i16/u16. */
5866 if (packf) {
5867 for (chan = 0; chan < 2; chan++) {
5868 LLVMValueRef pack_args[2] = {
5869 values[2 * chan],
5870 values[2 * chan + 1]
5871 };
5872 LLVMValueRef packed;
5873
5874 packed = packf(&ctx->ac, pack_args);
5875 args->out[chan] = ac_to_float(&ctx->ac, packed);
5876 }
5877 args->compr = 1; /* COMPR flag */
5878 }
5879
5880 /* Pack i16/u16. */
5881 if (packi) {
5882 for (chan = 0; chan < 2; chan++) {
5883 LLVMValueRef pack_args[2] = {
5884 ac_to_integer(&ctx->ac, values[2 * chan]),
5885 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5886 };
5887 LLVMValueRef packed;
5888
5889 packed = packi(&ctx->ac, pack_args,
5890 is_int8 ? 8 : is_int10 ? 10 : 16,
5891 chan == 1);
5892 args->out[chan] = ac_to_float(&ctx->ac, packed);
5893 }
5894 args->compr = 1; /* COMPR flag */
5895 }
5896 return;
5897 }
5898
5899 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5900
5901 for (unsigned i = 0; i < 4; ++i) {
5902 if (!(args->enabled_channels & (1 << i)))
5903 continue;
5904
5905 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5906 }
5907 }
5908
5909 static void
5910 radv_export_param(struct radv_shader_context *ctx, unsigned index,
5911 LLVMValueRef *values, unsigned enabled_channels)
5912 {
5913 struct ac_export_args args;
5914
5915 si_llvm_init_export_args(ctx, values, enabled_channels,
5916 V_008DFC_SQ_EXP_PARAM + index, &args);
5917 ac_build_export(&ctx->ac, &args);
5918 }
5919
5920 static LLVMValueRef
5921 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
5922 {
5923 LLVMValueRef output =
5924 ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
5925
5926 return LLVMBuildLoad(ctx->ac.builder, output, "");
5927 }
5928
5929 static void
5930 handle_vs_outputs_post(struct radv_shader_context *ctx,
5931 bool export_prim_id,
5932 struct ac_vs_output_info *outinfo)
5933 {
5934 uint32_t param_count = 0;
5935 unsigned target;
5936 unsigned pos_idx, num_pos_exports = 0;
5937 struct ac_export_args args, pos_args[4] = {};
5938 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5939 int i;
5940
5941 if (ctx->options->key.has_multiview_view_index) {
5942 LLVMValueRef* tmp_out = &ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5943 if(!*tmp_out) {
5944 for(unsigned i = 0; i < 4; ++i)
5945 ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5946 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5947 }
5948
5949 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
5950 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5951 }
5952
5953 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5954 sizeof(outinfo->vs_output_param_offset));
5955
5956 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5957 LLVMValueRef slots[8];
5958 unsigned j;
5959
5960 if (outinfo->cull_dist_mask)
5961 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5962
5963 i = VARYING_SLOT_CLIP_DIST0;
5964 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5965 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
5966
5967 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5968 slots[i] = LLVMGetUndef(ctx->ac.f32);
5969
5970 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5971 target = V_008DFC_SQ_EXP_POS + 3;
5972 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
5973 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5974 &args, sizeof(args));
5975 }
5976
5977 target = V_008DFC_SQ_EXP_POS + 2;
5978 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
5979 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5980 &args, sizeof(args));
5981
5982 }
5983
5984 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5985 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5986 for (unsigned j = 0; j < 4; j++)
5987 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
5988 }
5989 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5990
5991 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5992 outinfo->writes_pointsize = true;
5993 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
5994 }
5995
5996 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5997 outinfo->writes_layer = true;
5998 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
5999 }
6000
6001 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
6002 outinfo->writes_viewport_index = true;
6003 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
6004 }
6005
6006 if (outinfo->writes_pointsize ||
6007 outinfo->writes_layer ||
6008 outinfo->writes_viewport_index) {
6009 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
6010 (outinfo->writes_layer == true ? 4 : 0));
6011 pos_args[1].valid_mask = 0;
6012 pos_args[1].done = 0;
6013 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6014 pos_args[1].compr = 0;
6015 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6016 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6017 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6018 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6019
6020 if (outinfo->writes_pointsize == true)
6021 pos_args[1].out[0] = psize_value;
6022 if (outinfo->writes_layer == true)
6023 pos_args[1].out[2] = layer_value;
6024 if (outinfo->writes_viewport_index == true) {
6025 if (ctx->options->chip_class >= GFX9) {
6026 /* GFX9 has the layer in out.z[10:0] and the viewport
6027 * index in out.z[19:16].
6028 */
6029 LLVMValueRef v = viewport_index_value;
6030 v = ac_to_integer(&ctx->ac, v);
6031 v = LLVMBuildShl(ctx->ac.builder, v,
6032 LLVMConstInt(ctx->ac.i32, 16, false),
6033 "");
6034 v = LLVMBuildOr(ctx->ac.builder, v,
6035 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6036
6037 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6038 pos_args[1].enabled_channels |= 1 << 2;
6039 } else {
6040 pos_args[1].out[3] = viewport_index_value;
6041 pos_args[1].enabled_channels |= 1 << 3;
6042 }
6043 }
6044 }
6045 for (i = 0; i < 4; i++) {
6046 if (pos_args[i].out[0])
6047 num_pos_exports++;
6048 }
6049
6050 pos_idx = 0;
6051 for (i = 0; i < 4; i++) {
6052 if (!pos_args[i].out[0])
6053 continue;
6054
6055 /* Specify the target we are exporting */
6056 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6057 if (pos_idx == num_pos_exports)
6058 pos_args[i].done = 1;
6059 ac_build_export(&ctx->ac, &pos_args[i]);
6060 }
6061
6062 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6063 LLVMValueRef values[4];
6064 if (!(ctx->output_mask & (1ull << i)))
6065 continue;
6066
6067 if (i != VARYING_SLOT_LAYER &&
6068 i != VARYING_SLOT_PRIMITIVE_ID &&
6069 i < VARYING_SLOT_VAR0)
6070 continue;
6071
6072 for (unsigned j = 0; j < 4; j++)
6073 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6074
6075 unsigned output_usage_mask;
6076
6077 if (ctx->stage == MESA_SHADER_VERTEX &&
6078 !ctx->is_gs_copy_shader) {
6079 output_usage_mask =
6080 ctx->shader_info->info.vs.output_usage_mask[i];
6081 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
6082 output_usage_mask =
6083 ctx->shader_info->info.tes.output_usage_mask[i];
6084 } else {
6085 /* Enable all channels for the GS copy shader because
6086 * we don't know the output usage mask currently.
6087 */
6088 output_usage_mask = 0xf;
6089 }
6090
6091 radv_export_param(ctx, param_count, values, output_usage_mask);
6092
6093 outinfo->vs_output_param_offset[i] = param_count++;
6094 }
6095
6096 if (export_prim_id) {
6097 LLVMValueRef values[4];
6098
6099 values[0] = ctx->vs_prim_id;
6100 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6101 ctx->shader_info->vs.vgpr_comp_cnt);
6102 for (unsigned j = 1; j < 4; j++)
6103 values[j] = ctx->ac.f32_0;
6104
6105 radv_export_param(ctx, param_count, values, 0xf);
6106
6107 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6108 outinfo->export_prim_id = true;
6109 }
6110
6111 outinfo->pos_exports = num_pos_exports;
6112 outinfo->param_exports = param_count;
6113 }
6114
6115 static void
6116 handle_es_outputs_post(struct radv_shader_context *ctx,
6117 struct ac_es_output_info *outinfo)
6118 {
6119 int j;
6120 uint64_t max_output_written = 0;
6121 LLVMValueRef lds_base = NULL;
6122
6123 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6124 int param_index;
6125 int length = 4;
6126
6127 if (!(ctx->output_mask & (1ull << i)))
6128 continue;
6129
6130 if (i == VARYING_SLOT_CLIP_DIST0)
6131 length = ctx->num_output_clips + ctx->num_output_culls;
6132
6133 param_index = shader_io_get_unique_index(i);
6134
6135 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6136 }
6137
6138 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6139
6140 if (ctx->ac.chip_class >= GFX9) {
6141 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6142 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6143 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6144 LLVMConstInt(ctx->ac.i32, 24, false),
6145 LLVMConstInt(ctx->ac.i32, 4, false), false);
6146 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6147 LLVMBuildMul(ctx->ac.builder, wave_idx,
6148 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6149 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6150 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6151 }
6152
6153 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6154 LLVMValueRef dw_addr = NULL;
6155 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6156 int param_index;
6157 int length = 4;
6158
6159 if (!(ctx->output_mask & (1ull << i)))
6160 continue;
6161
6162 if (i == VARYING_SLOT_CLIP_DIST0)
6163 length = ctx->num_output_clips + ctx->num_output_culls;
6164
6165 param_index = shader_io_get_unique_index(i);
6166
6167 if (lds_base) {
6168 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
6169 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6170 "");
6171 }
6172 for (j = 0; j < length; j++) {
6173 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
6174 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
6175
6176 if (ctx->ac.chip_class >= GFX9) {
6177 ac_lds_store(&ctx->ac, dw_addr,
6178 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6179 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6180 } else {
6181 ac_build_buffer_store_dword(&ctx->ac,
6182 ctx->esgs_ring,
6183 out_val, 1,
6184 NULL, ctx->es2gs_offset,
6185 (4 * param_index + j) * 4,
6186 1, 1, true, true);
6187 }
6188 }
6189 }
6190 }
6191
6192 static void
6193 handle_ls_outputs_post(struct radv_shader_context *ctx)
6194 {
6195 LLVMValueRef vertex_id = ctx->rel_auto_id;
6196 LLVMValueRef vertex_dw_stride = ac_unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6197 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
6198 vertex_dw_stride, "");
6199
6200 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6201 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6202 int length = 4;
6203
6204 if (!(ctx->output_mask & (1ull << i)))
6205 continue;
6206
6207 if (i == VARYING_SLOT_CLIP_DIST0)
6208 length = ctx->num_output_clips + ctx->num_output_culls;
6209 int param = shader_io_get_unique_index(i);
6210 mark_tess_output(ctx, false, param);
6211 if (length > 4)
6212 mark_tess_output(ctx, false, param + 1);
6213 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
6214 LLVMConstInt(ctx->ac.i32, param * 4, false),
6215 "");
6216 for (unsigned j = 0; j < length; j++) {
6217 ac_lds_store(&ctx->ac, dw_addr,
6218 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6219 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6220 }
6221 }
6222 }
6223
6224 struct ac_build_if_state
6225 {
6226 struct radv_shader_context *ctx;
6227 LLVMValueRef condition;
6228 LLVMBasicBlockRef entry_block;
6229 LLVMBasicBlockRef true_block;
6230 LLVMBasicBlockRef false_block;
6231 LLVMBasicBlockRef merge_block;
6232 };
6233
6234 static LLVMBasicBlockRef
6235 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
6236 {
6237 LLVMBasicBlockRef current_block;
6238 LLVMBasicBlockRef next_block;
6239 LLVMBasicBlockRef new_block;
6240
6241 /* get current basic block */
6242 current_block = LLVMGetInsertBlock(ctx->ac.builder);
6243
6244 /* chqeck if there's another block after this one */
6245 next_block = LLVMGetNextBasicBlock(current_block);
6246 if (next_block) {
6247 /* insert the new block before the next block */
6248 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6249 }
6250 else {
6251 /* append new block after current block */
6252 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6253 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6254 }
6255 return new_block;
6256 }
6257
6258 static void
6259 ac_nir_build_if(struct ac_build_if_state *ifthen,
6260 struct radv_shader_context *ctx,
6261 LLVMValueRef condition)
6262 {
6263 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
6264
6265 memset(ifthen, 0, sizeof *ifthen);
6266 ifthen->ctx = ctx;
6267 ifthen->condition = condition;
6268 ifthen->entry_block = block;
6269
6270 /* create endif/merge basic block for the phi functions */
6271 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6272
6273 /* create/insert true_block before merge_block */
6274 ifthen->true_block =
6275 LLVMInsertBasicBlockInContext(ctx->context,
6276 ifthen->merge_block,
6277 "if-true-block");
6278
6279 /* successive code goes into the true block */
6280 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
6281 }
6282
6283 /**
6284 * End a conditional.
6285 */
6286 static void
6287 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6288 {
6289 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
6290
6291 /* Insert branch to the merge block from current block */
6292 LLVMBuildBr(builder, ifthen->merge_block);
6293
6294 /*
6295 * Now patch in the various branch instructions.
6296 */
6297
6298 /* Insert the conditional branch instruction at the end of entry_block */
6299 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6300 if (ifthen->false_block) {
6301 /* we have an else clause */
6302 LLVMBuildCondBr(builder, ifthen->condition,
6303 ifthen->true_block, ifthen->false_block);
6304 }
6305 else {
6306 /* no else clause */
6307 LLVMBuildCondBr(builder, ifthen->condition,
6308 ifthen->true_block, ifthen->merge_block);
6309 }
6310
6311 /* Resume building code at end of the ifthen->merge_block */
6312 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6313 }
6314
6315 static void
6316 write_tess_factors(struct radv_shader_context *ctx)
6317 {
6318 unsigned stride, outer_comps, inner_comps;
6319 struct ac_build_if_state if_ctx, inner_if_ctx;
6320 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6321 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6322 unsigned tess_inner_index = 0, tess_outer_index;
6323 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
6324 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6325 int i;
6326 emit_barrier(&ctx->ac, ctx->stage);
6327
6328 switch (ctx->options->key.tcs.primitive_mode) {
6329 case GL_ISOLINES:
6330 stride = 2;
6331 outer_comps = 2;
6332 inner_comps = 0;
6333 break;
6334 case GL_TRIANGLES:
6335 stride = 4;
6336 outer_comps = 3;
6337 inner_comps = 1;
6338 break;
6339 case GL_QUADS:
6340 stride = 6;
6341 outer_comps = 4;
6342 inner_comps = 2;
6343 break;
6344 default:
6345 return;
6346 }
6347
6348 ac_nir_build_if(&if_ctx, ctx,
6349 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6350 invocation_id, ctx->ac.i32_0, ""));
6351
6352 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6353
6354 if (inner_comps) {
6355 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6356 mark_tess_output(ctx, true, tess_inner_index);
6357 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
6358 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6359 }
6360
6361 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6362 mark_tess_output(ctx, true, tess_outer_index);
6363 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
6364 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6365
6366 for (i = 0; i < 4; i++) {
6367 inner[i] = LLVMGetUndef(ctx->ac.i32);
6368 outer[i] = LLVMGetUndef(ctx->ac.i32);
6369 }
6370
6371 // LINES reverseal
6372 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6373 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6374 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6375 ctx->ac.i32_1, "");
6376 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6377 } else {
6378 for (i = 0; i < outer_comps; i++) {
6379 outer[i] = out[i] =
6380 ac_lds_load(&ctx->ac, lds_outer);
6381 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6382 ctx->ac.i32_1, "");
6383 }
6384 for (i = 0; i < inner_comps; i++) {
6385 inner[i] = out[outer_comps+i] =
6386 ac_lds_load(&ctx->ac, lds_inner);
6387 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
6388 ctx->ac.i32_1, "");
6389 }
6390 }
6391
6392 /* Convert the outputs to vectors for stores. */
6393 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6394 vec1 = NULL;
6395
6396 if (stride > 4)
6397 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6398
6399
6400 buffer = ctx->hs_ring_tess_factor;
6401 tf_base = ctx->tess_factor_offset;
6402 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
6403 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6404 unsigned tf_offset = 0;
6405
6406 if (ctx->options->chip_class <= VI) {
6407 ac_nir_build_if(&inner_if_ctx, ctx,
6408 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6409 rel_patch_id, ctx->ac.i32_0, ""));
6410
6411 /* Store the dynamic HS control word. */
6412 ac_build_buffer_store_dword(&ctx->ac, buffer,
6413 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6414 1, ctx->ac.i32_0, tf_base,
6415 0, 1, 0, true, false);
6416 tf_offset += 4;
6417
6418 ac_nir_build_endif(&inner_if_ctx);
6419 }
6420
6421 /* Store the tessellation factors. */
6422 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6423 MIN2(stride, 4), byteoffset, tf_base,
6424 tf_offset, 1, 0, true, false);
6425 if (vec1)
6426 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6427 stride - 4, byteoffset, tf_base,
6428 16 + tf_offset, 1, 0, true, false);
6429
6430 //store to offchip for TES to read - only if TES reads them
6431 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6432 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6433 LLVMValueRef tf_inner_offset;
6434 unsigned param_outer, param_inner;
6435
6436 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6437 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6438 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6439
6440 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6441 util_next_power_of_two(outer_comps));
6442
6443 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6444 outer_comps, tf_outer_offset,
6445 ctx->oc_lds, 0, 1, 0, true, false);
6446 if (inner_comps) {
6447 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6448 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6449 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6450
6451 inner_vec = inner_comps == 1 ? inner[0] :
6452 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6453 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6454 inner_comps, tf_inner_offset,
6455 ctx->oc_lds, 0, 1, 0, true, false);
6456 }
6457 }
6458 ac_nir_build_endif(&if_ctx);
6459 }
6460
6461 static void
6462 handle_tcs_outputs_post(struct radv_shader_context *ctx)
6463 {
6464 write_tess_factors(ctx);
6465 }
6466
6467 static bool
6468 si_export_mrt_color(struct radv_shader_context *ctx,
6469 LLVMValueRef *color, unsigned index,
6470 struct ac_export_args *args)
6471 {
6472 /* Export */
6473 si_llvm_init_export_args(ctx, color, 0xf,
6474 V_008DFC_SQ_EXP_MRT + index, args);
6475 if (!args->enabled_channels)
6476 return false; /* unnecessary NULL export */
6477
6478 return true;
6479 }
6480
6481 static void
6482 radv_export_mrt_z(struct radv_shader_context *ctx,
6483 LLVMValueRef depth, LLVMValueRef stencil,
6484 LLVMValueRef samplemask)
6485 {
6486 struct ac_export_args args;
6487
6488 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6489
6490 ac_build_export(&ctx->ac, &args);
6491 }
6492
6493 static void
6494 handle_fs_outputs_post(struct radv_shader_context *ctx)
6495 {
6496 unsigned index = 0;
6497 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6498 struct ac_export_args color_args[8];
6499
6500 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6501 LLVMValueRef values[4];
6502
6503 if (!(ctx->output_mask & (1ull << i)))
6504 continue;
6505
6506 if (i < FRAG_RESULT_DATA0)
6507 continue;
6508
6509 for (unsigned j = 0; j < 4; j++)
6510 values[j] = ac_to_float(&ctx->ac,
6511 radv_load_output(ctx, i, j));
6512
6513 bool ret = si_export_mrt_color(ctx, values,
6514 i - FRAG_RESULT_DATA0,
6515 &color_args[index]);
6516 if (ret)
6517 index++;
6518 }
6519
6520 /* Process depth, stencil, samplemask. */
6521 if (ctx->shader_info->info.ps.writes_z) {
6522 depth = ac_to_float(&ctx->ac,
6523 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6524 }
6525 if (ctx->shader_info->info.ps.writes_stencil) {
6526 stencil = ac_to_float(&ctx->ac,
6527 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6528 }
6529 if (ctx->shader_info->info.ps.writes_sample_mask) {
6530 samplemask = ac_to_float(&ctx->ac,
6531 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6532 }
6533
6534 /* Set the DONE bit on last non-null color export only if Z isn't
6535 * exported.
6536 */
6537 if (index > 0 &&
6538 !ctx->shader_info->info.ps.writes_z &&
6539 !ctx->shader_info->info.ps.writes_stencil &&
6540 !ctx->shader_info->info.ps.writes_sample_mask) {
6541 unsigned last = index - 1;
6542
6543 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
6544 color_args[last].done = 1; /* DONE bit */
6545 }
6546
6547 /* Export PS outputs. */
6548 for (unsigned i = 0; i < index; i++)
6549 ac_build_export(&ctx->ac, &color_args[i]);
6550
6551 if (depth || stencil || samplemask)
6552 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6553 else if (!index)
6554 ac_build_export_null(&ctx->ac);
6555 }
6556
6557 static void
6558 emit_gs_epilogue(struct radv_shader_context *ctx)
6559 {
6560 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6561 }
6562
6563 static void
6564 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6565 LLVMValueRef *addrs)
6566 {
6567 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
6568
6569 switch (ctx->stage) {
6570 case MESA_SHADER_VERTEX:
6571 if (ctx->options->key.vs.as_ls)
6572 handle_ls_outputs_post(ctx);
6573 else if (ctx->options->key.vs.as_es)
6574 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6575 else
6576 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6577 &ctx->shader_info->vs.outinfo);
6578 break;
6579 case MESA_SHADER_FRAGMENT:
6580 handle_fs_outputs_post(ctx);
6581 break;
6582 case MESA_SHADER_GEOMETRY:
6583 emit_gs_epilogue(ctx);
6584 break;
6585 case MESA_SHADER_TESS_CTRL:
6586 handle_tcs_outputs_post(ctx);
6587 break;
6588 case MESA_SHADER_TESS_EVAL:
6589 if (ctx->options->key.tes.as_es)
6590 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6591 else
6592 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6593 &ctx->shader_info->tes.outinfo);
6594 break;
6595 default:
6596 break;
6597 }
6598 }
6599
6600 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
6601 {
6602 LLVMPassManagerRef passmgr;
6603 /* Create the pass manager */
6604 passmgr = LLVMCreateFunctionPassManagerForModule(
6605 ctx->ac.module);
6606
6607 /* This pass should eliminate all the load and store instructions */
6608 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6609
6610 /* Add some optimization passes */
6611 LLVMAddScalarReplAggregatesPass(passmgr);
6612 LLVMAddLICMPass(passmgr);
6613 LLVMAddAggressiveDCEPass(passmgr);
6614 LLVMAddCFGSimplificationPass(passmgr);
6615 LLVMAddInstructionCombiningPass(passmgr);
6616
6617 /* Run the pass */
6618 LLVMInitializeFunctionPassManager(passmgr);
6619 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6620 LLVMFinalizeFunctionPassManager(passmgr);
6621
6622 LLVMDisposeBuilder(ctx->ac.builder);
6623 LLVMDisposePassManager(passmgr);
6624
6625 ac_llvm_context_dispose(&ctx->ac);
6626 }
6627
6628 static void
6629 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
6630 {
6631 struct ac_vs_output_info *outinfo;
6632
6633 switch (ctx->stage) {
6634 case MESA_SHADER_FRAGMENT:
6635 case MESA_SHADER_COMPUTE:
6636 case MESA_SHADER_TESS_CTRL:
6637 case MESA_SHADER_GEOMETRY:
6638 return;
6639 case MESA_SHADER_VERTEX:
6640 if (ctx->options->key.vs.as_ls ||
6641 ctx->options->key.vs.as_es)
6642 return;
6643 outinfo = &ctx->shader_info->vs.outinfo;
6644 break;
6645 case MESA_SHADER_TESS_EVAL:
6646 if (ctx->options->key.vs.as_es)
6647 return;
6648 outinfo = &ctx->shader_info->tes.outinfo;
6649 break;
6650 default:
6651 unreachable("Unhandled shader type");
6652 }
6653
6654 ac_optimize_vs_outputs(&ctx->ac,
6655 ctx->main_function,
6656 outinfo->vs_output_param_offset,
6657 VARYING_SLOT_MAX,
6658 &outinfo->param_exports);
6659 }
6660
6661 static void
6662 ac_setup_rings(struct radv_shader_context *ctx)
6663 {
6664 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6665 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6666 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6667 }
6668
6669 if (ctx->is_gs_copy_shader) {
6670 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6671 }
6672 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6673 LLVMValueRef tmp;
6674 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6675 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6676
6677 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6678
6679 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6680 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6681 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
6682 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6683 }
6684
6685 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6686 ctx->stage == MESA_SHADER_TESS_EVAL) {
6687 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6688 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6689 }
6690 }
6691
6692 static unsigned
6693 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6694 const struct nir_shader *nir)
6695 {
6696 switch (nir->info.stage) {
6697 case MESA_SHADER_TESS_CTRL:
6698 return chip_class >= CIK ? 128 : 64;
6699 case MESA_SHADER_GEOMETRY:
6700 return chip_class >= GFX9 ? 128 : 64;
6701 case MESA_SHADER_COMPUTE:
6702 break;
6703 default:
6704 return 0;
6705 }
6706
6707 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6708 nir->info.cs.local_size[1] *
6709 nir->info.cs.local_size[2];
6710 return max_workgroup_size;
6711 }
6712
6713 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6714 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
6715 {
6716 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6717 LLVMConstInt(ctx->ac.i32, 8, false),
6718 LLVMConstInt(ctx->ac.i32, 8, false), false);
6719 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6720 ctx->ac.i32_0, "");
6721 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6722 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6723 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6724 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6725 }
6726
6727 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
6728 {
6729 for(int i = 5; i >= 0; --i) {
6730 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6731 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6732 LLVMConstInt(ctx->ac.i32, 16, false), false);
6733 }
6734
6735 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6736 LLVMConstInt(ctx->ac.i32, 16, false),
6737 LLVMConstInt(ctx->ac.i32, 8, false), false);
6738 }
6739
6740 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6741 struct nir_shader *nir)
6742 {
6743 struct ac_nir_context ctx = {};
6744 struct nir_function *func;
6745
6746 /* Last minute passes for both radv & radeonsi */
6747 ac_lower_subgroups(nir);
6748
6749 ctx.ac = *ac;
6750 ctx.abi = abi;
6751
6752 ctx.stage = nir->info.stage;
6753
6754 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6755
6756 nir_foreach_variable(variable, &nir->outputs)
6757 handle_shader_output_decl(&ctx.ac, ctx.abi, nir, variable,
6758 ctx.stage);
6759
6760 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6761 _mesa_key_pointer_equal);
6762 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6763 _mesa_key_pointer_equal);
6764 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6765 _mesa_key_pointer_equal);
6766
6767 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6768
6769 setup_locals(&ctx, func);
6770
6771 if (nir->info.stage == MESA_SHADER_COMPUTE)
6772 setup_shared(&ctx, nir);
6773
6774 visit_cf_list(&ctx, &func->impl->body);
6775 phi_post_pass(&ctx);
6776
6777 if (nir->info.stage != MESA_SHADER_COMPUTE)
6778 ctx.abi->emit_outputs(ctx.abi, AC_LLVM_MAX_OUTPUTS,
6779 ctx.abi->outputs);
6780
6781 free(ctx.locals);
6782 ralloc_free(ctx.defs);
6783 ralloc_free(ctx.phis);
6784 ralloc_free(ctx.vars);
6785 }
6786
6787 static
6788 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6789 struct nir_shader *const *shaders,
6790 int shader_count,
6791 struct ac_shader_variant_info *shader_info,
6792 const struct ac_nir_compiler_options *options,
6793 bool dump_shader)
6794 {
6795 struct radv_shader_context ctx = {0};
6796 unsigned i;
6797 ctx.options = options;
6798 ctx.shader_info = shader_info;
6799 ctx.context = LLVMContextCreate();
6800
6801 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6802 options->family);
6803 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6804 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6805
6806 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6807 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6808 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
6809 LLVMDisposeTargetData(data_layout);
6810 LLVMDisposeMessage(data_layout_str);
6811
6812 enum ac_float_mode float_mode =
6813 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6814 AC_FLOAT_MODE_DEFAULT;
6815
6816 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
6817
6818 memset(shader_info, 0, sizeof(*shader_info));
6819
6820 for(int i = 0; i < shader_count; ++i)
6821 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6822
6823 for (i = 0; i < AC_UD_MAX_SETS; i++)
6824 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6825 for (i = 0; i < AC_UD_MAX_UD; i++)
6826 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6827
6828 ctx.max_workgroup_size = 0;
6829 for (int i = 0; i < shader_count; ++i) {
6830 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6831 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6832 shaders[i]));
6833 }
6834
6835 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6836 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6837
6838 ctx.abi.inputs = &ctx.inputs[0];
6839 ctx.abi.emit_outputs = handle_shader_outputs_post;
6840 ctx.abi.emit_vertex = visit_emit_vertex;
6841 ctx.abi.load_ubo = radv_load_ubo;
6842 ctx.abi.load_ssbo = radv_load_ssbo;
6843 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6844 ctx.abi.load_resource = radv_load_resource;
6845 ctx.abi.clamp_shadow_reference = false;
6846
6847 if (shader_count >= 2)
6848 ac_init_exec_full_mask(&ctx.ac);
6849
6850 if (ctx.ac.chip_class == GFX9 &&
6851 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6852 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6853
6854 for(int i = 0; i < shader_count; ++i) {
6855 ctx.stage = shaders[i]->info.stage;
6856 ctx.output_mask = 0;
6857 ctx.tess_outputs_written = 0;
6858 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6859 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6860
6861 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6862 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6863 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6864 ctx.abi.load_inputs = load_gs_input;
6865 ctx.abi.emit_primitive = visit_end_primitive;
6866 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6867 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6868 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6869 ctx.abi.load_tess_varyings = load_tcs_varyings;
6870 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6871 ctx.abi.store_tcs_outputs = store_tcs_output;
6872 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6873 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6874 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6875 ctx.abi.load_tess_varyings = load_tes_input;
6876 ctx.abi.load_tess_coord = load_tess_coord;
6877 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6878 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6879 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6880 if (shader_info->info.vs.needs_instance_id) {
6881 if (ctx.options->key.vs.as_ls) {
6882 ctx.shader_info->vs.vgpr_comp_cnt =
6883 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6884 } else {
6885 ctx.shader_info->vs.vgpr_comp_cnt =
6886 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6887 }
6888 }
6889 ctx.abi.load_base_vertex = radv_load_base_vertex;
6890 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6891 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6892 ctx.abi.lookup_interp_param = lookup_interp_param;
6893 ctx.abi.load_sample_position = load_sample_position;
6894 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6895 ctx.abi.emit_kill = radv_emit_kill;
6896 }
6897
6898 if (i)
6899 emit_barrier(&ctx.ac, ctx.stage);
6900
6901 ac_setup_rings(&ctx);
6902
6903 LLVMBasicBlockRef merge_block;
6904 if (shader_count >= 2) {
6905 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6906 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6907 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6908
6909 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6910 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6911 LLVMConstInt(ctx.ac.i32, 8, false), false);
6912 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6913 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6914 thread_id, count, "");
6915 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6916
6917 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6918 }
6919
6920 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6921 handle_fs_inputs(&ctx, shaders[i]);
6922 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6923 handle_vs_inputs(&ctx, shaders[i]);
6924 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6925 prepare_gs_input_vgprs(&ctx);
6926
6927 nir_foreach_variable(variable, &shaders[i]->outputs)
6928 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6929
6930 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
6931
6932 if (shader_count >= 2) {
6933 LLVMBuildBr(ctx.ac.builder, merge_block);
6934 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6935 }
6936
6937 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6938 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6939 shaders[i]->info.cull_distance_array_size > 4;
6940 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6941 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6942 shaders[i]->info.gs.vertices_out;
6943 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6944 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6945 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6946 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6947 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6948 }
6949 }
6950
6951 LLVMBuildRetVoid(ctx.ac.builder);
6952
6953 if (options->dump_preoptir)
6954 ac_dump_module(ctx.ac.module);
6955
6956 ac_llvm_finalize_module(&ctx);
6957
6958 if (shader_count == 1)
6959 ac_nir_eliminate_const_vs_outputs(&ctx);
6960
6961 if (dump_shader) {
6962 ctx.shader_info->private_mem_vgprs =
6963 ac_count_scratch_private_memory(ctx.main_function);
6964 }
6965
6966 return ctx.ac.module;
6967 }
6968
6969 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6970 {
6971 unsigned *retval = (unsigned *)context;
6972 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6973 char *description = LLVMGetDiagInfoDescription(di);
6974
6975 if (severity == LLVMDSError) {
6976 *retval = 1;
6977 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6978 description);
6979 }
6980
6981 LLVMDisposeMessage(description);
6982 }
6983
6984 static unsigned ac_llvm_compile(LLVMModuleRef M,
6985 struct ac_shader_binary *binary,
6986 LLVMTargetMachineRef tm)
6987 {
6988 unsigned retval = 0;
6989 char *err;
6990 LLVMContextRef llvm_ctx;
6991 LLVMMemoryBufferRef out_buffer;
6992 unsigned buffer_size;
6993 const char *buffer_data;
6994 LLVMBool mem_err;
6995
6996 /* Setup Diagnostic Handler*/
6997 llvm_ctx = LLVMGetModuleContext(M);
6998
6999 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
7000 &retval);
7001
7002 /* Compile IR*/
7003 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
7004 &err, &out_buffer);
7005
7006 /* Process Errors/Warnings */
7007 if (mem_err) {
7008 fprintf(stderr, "%s: %s", __FUNCTION__, err);
7009 free(err);
7010 retval = 1;
7011 goto out;
7012 }
7013
7014 /* Extract Shader Code*/
7015 buffer_size = LLVMGetBufferSize(out_buffer);
7016 buffer_data = LLVMGetBufferStart(out_buffer);
7017
7018 ac_elf_read(buffer_data, buffer_size, binary);
7019
7020 /* Clean up */
7021 LLVMDisposeMemoryBuffer(out_buffer);
7022
7023 out:
7024 return retval;
7025 }
7026
7027 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
7028 LLVMModuleRef llvm_module,
7029 struct ac_shader_binary *binary,
7030 struct ac_shader_config *config,
7031 struct ac_shader_variant_info *shader_info,
7032 gl_shader_stage stage,
7033 bool dump_shader, bool supports_spill)
7034 {
7035 if (dump_shader)
7036 ac_dump_module(llvm_module);
7037
7038 memset(binary, 0, sizeof(*binary));
7039 int v = ac_llvm_compile(llvm_module, binary, tm);
7040 if (v) {
7041 fprintf(stderr, "compile failed\n");
7042 }
7043
7044 if (dump_shader)
7045 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7046
7047 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7048
7049 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7050 LLVMDisposeModule(llvm_module);
7051 LLVMContextDispose(ctx);
7052
7053 if (stage == MESA_SHADER_FRAGMENT) {
7054 shader_info->num_input_vgprs = 0;
7055 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7056 shader_info->num_input_vgprs += 2;
7057 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7058 shader_info->num_input_vgprs += 2;
7059 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7060 shader_info->num_input_vgprs += 2;
7061 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7062 shader_info->num_input_vgprs += 3;
7063 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7064 shader_info->num_input_vgprs += 2;
7065 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7066 shader_info->num_input_vgprs += 2;
7067 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7068 shader_info->num_input_vgprs += 2;
7069 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7070 shader_info->num_input_vgprs += 1;
7071 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7072 shader_info->num_input_vgprs += 1;
7073 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7074 shader_info->num_input_vgprs += 1;
7075 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7076 shader_info->num_input_vgprs += 1;
7077 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7078 shader_info->num_input_vgprs += 1;
7079 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7080 shader_info->num_input_vgprs += 1;
7081 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7082 shader_info->num_input_vgprs += 1;
7083 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7084 shader_info->num_input_vgprs += 1;
7085 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7086 shader_info->num_input_vgprs += 1;
7087 }
7088 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7089
7090 /* +3 for scratch wave offset and VCC */
7091 config->num_sgprs = MAX2(config->num_sgprs,
7092 shader_info->num_input_sgprs + 3);
7093
7094 /* Enable 64-bit and 16-bit denormals, because there is no performance
7095 * cost.
7096 *
7097 * If denormals are enabled, all floating-point output modifiers are
7098 * ignored.
7099 *
7100 * Don't enable denormals for 32-bit floats, because:
7101 * - Floating-point output modifiers would be ignored by the hw.
7102 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7103 * have to stop using those.
7104 * - SI & CI would be very slow.
7105 */
7106 config->float_mode |= V_00B028_FP_64_DENORMS;
7107 }
7108
7109 static void
7110 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7111 {
7112 switch (nir->info.stage) {
7113 case MESA_SHADER_COMPUTE:
7114 for (int i = 0; i < 3; ++i)
7115 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7116 break;
7117 case MESA_SHADER_FRAGMENT:
7118 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7119 break;
7120 case MESA_SHADER_GEOMETRY:
7121 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7122 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7123 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7124 shader_info->gs.invocations = nir->info.gs.invocations;
7125 break;
7126 case MESA_SHADER_TESS_EVAL:
7127 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7128 shader_info->tes.spacing = nir->info.tess.spacing;
7129 shader_info->tes.ccw = nir->info.tess.ccw;
7130 shader_info->tes.point_mode = nir->info.tess.point_mode;
7131 shader_info->tes.as_es = options->key.tes.as_es;
7132 break;
7133 case MESA_SHADER_TESS_CTRL:
7134 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7135 break;
7136 case MESA_SHADER_VERTEX:
7137 shader_info->vs.as_es = options->key.vs.as_es;
7138 shader_info->vs.as_ls = options->key.vs.as_ls;
7139 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7140 if (options->key.vs.as_ls)
7141 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7142 break;
7143 default:
7144 break;
7145 }
7146 }
7147
7148 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7149 struct ac_shader_binary *binary,
7150 struct ac_shader_config *config,
7151 struct ac_shader_variant_info *shader_info,
7152 struct nir_shader *const *nir,
7153 int nir_count,
7154 const struct ac_nir_compiler_options *options,
7155 bool dump_shader)
7156 {
7157
7158 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7159 options, dump_shader);
7160
7161 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7162 for (int i = 0; i < nir_count; ++i)
7163 ac_fill_shader_info(shader_info, nir[i], options);
7164
7165 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7166 if (options->chip_class == GFX9) {
7167 if (nir_count == 2 &&
7168 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7169 shader_info->gs.es_type = nir[0]->info.stage;
7170 }
7171 }
7172 }
7173
7174 static void
7175 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
7176 {
7177 LLVMValueRef vtx_offset =
7178 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
7179 LLVMConstInt(ctx->ac.i32, 4, false), "");
7180 int idx = 0;
7181
7182 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
7183 int length = 4;
7184 int slot = idx;
7185 int slot_inc = 1;
7186 if (!(ctx->output_mask & (1ull << i)))
7187 continue;
7188
7189 if (i == VARYING_SLOT_CLIP_DIST0) {
7190 /* unpack clip and cull from a single set of slots */
7191 length = ctx->num_output_clips + ctx->num_output_culls;
7192 if (length > 4)
7193 slot_inc = 2;
7194 }
7195
7196 for (unsigned j = 0; j < length; j++) {
7197 LLVMValueRef value, soffset;
7198
7199 soffset = LLVMConstInt(ctx->ac.i32,
7200 (slot * 4 + j) *
7201 ctx->gs_max_out_vertices * 16 * 4, false);
7202
7203 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7204 1, ctx->ac.i32_0,
7205 vtx_offset, soffset,
7206 0, 1, 1, true, false);
7207
7208 LLVMBuildStore(ctx->ac.builder,
7209 ac_to_float(&ctx->ac, value), ctx->abi.outputs[radeon_llvm_reg_index_soa(i, j)]);
7210 }
7211 idx += slot_inc;
7212 }
7213 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7214 }
7215
7216 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7217 struct nir_shader *geom_shader,
7218 struct ac_shader_binary *binary,
7219 struct ac_shader_config *config,
7220 struct ac_shader_variant_info *shader_info,
7221 const struct ac_nir_compiler_options *options,
7222 bool dump_shader)
7223 {
7224 struct radv_shader_context ctx = {0};
7225 ctx.context = LLVMContextCreate();
7226 ctx.options = options;
7227 ctx.shader_info = shader_info;
7228
7229 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7230 options->family);
7231 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7232
7233 ctx.is_gs_copy_shader = true;
7234 LLVMSetTarget(ctx.ac.module, "amdgcn--");
7235
7236 enum ac_float_mode float_mode =
7237 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7238 AC_FLOAT_MODE_DEFAULT;
7239
7240 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
7241 ctx.stage = MESA_SHADER_VERTEX;
7242
7243 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7244
7245 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7246 ac_setup_rings(&ctx);
7247
7248 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7249 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7250
7251 nir_foreach_variable(variable, &geom_shader->outputs) {
7252 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7253 handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
7254 variable, MESA_SHADER_VERTEX);
7255 }
7256
7257 ac_gs_copy_shader_emit(&ctx);
7258
7259 LLVMBuildRetVoid(ctx.ac.builder);
7260
7261 ac_llvm_finalize_module(&ctx);
7262
7263 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
7264 MESA_SHADER_VERTEX,
7265 dump_shader, options->supports_spill);
7266 }
7267
7268 void
7269 ac_lower_indirect_derefs(struct nir_shader *nir, enum chip_class chip_class)
7270 {
7271 /* While it would be nice not to have this flag, we are constrained
7272 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
7273 * on GFX9.
7274 */
7275 bool llvm_has_working_vgpr_indexing = chip_class <= VI;
7276
7277 /* TODO: Indirect indexing of GS inputs is unimplemented.
7278 *
7279 * TCS and TES load inputs directly from LDS or offchip memory, so
7280 * indirect indexing is trivial.
7281 */
7282 nir_variable_mode indirect_mask = 0;
7283 if (nir->info.stage == MESA_SHADER_GEOMETRY ||
7284 (nir->info.stage != MESA_SHADER_TESS_CTRL &&
7285 nir->info.stage != MESA_SHADER_TESS_EVAL &&
7286 !llvm_has_working_vgpr_indexing)) {
7287 indirect_mask |= nir_var_shader_in;
7288 }
7289 if (!llvm_has_working_vgpr_indexing &&
7290 nir->info.stage != MESA_SHADER_TESS_CTRL)
7291 indirect_mask |= nir_var_shader_out;
7292
7293 /* TODO: We shouldn't need to do this, however LLVM isn't currently
7294 * smart enough to handle indirects without causing excess spilling
7295 * causing the gpu to hang.
7296 *
7297 * See the following thread for more details of the problem:
7298 * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
7299 */
7300 indirect_mask |= nir_var_local;
7301
7302 nir_lower_indirect_derefs(nir, indirect_mask);
7303 }