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[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tcs_patch_id;
115 LLVMValueRef tcs_rel_ids;
116 LLVMValueRef tes_rel_patch_id;
117 LLVMValueRef tes_patch_id;
118 LLVMValueRef tes_u;
119 LLVMValueRef tes_v;
120
121 LLVMValueRef gsvs_ring_stride;
122 LLVMValueRef gsvs_num_entries;
123 LLVMValueRef gs2vs_offset;
124 LLVMValueRef gs_wave_id;
125 LLVMValueRef gs_vtx_offset[6];
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 gl_shader_stage stage;
138
139 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
140
141 uint64_t input_mask;
142 uint64_t output_mask;
143 uint8_t num_output_clips;
144 uint8_t num_output_culls;
145
146 bool is_gs_copy_shader;
147 LLVMValueRef gs_next_vertex;
148 unsigned gs_max_out_vertices;
149
150 unsigned tes_primitive_mode;
151 uint64_t tess_outputs_written;
152 uint64_t tess_patch_outputs_written;
153
154 uint32_t tcs_patch_outputs_read;
155 uint64_t tcs_outputs_read;
156 };
157
158 static inline struct nir_to_llvm_context *
159 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
160 {
161 struct nir_to_llvm_context *ctx = NULL;
162 return container_of(abi, ctx, abi);
163 }
164
165 static LLVMTypeRef
166 nir2llvmtype(struct ac_nir_context *ctx,
167 const struct glsl_type *type)
168 {
169 switch (glsl_get_base_type(glsl_without_array(type))) {
170 case GLSL_TYPE_UINT:
171 case GLSL_TYPE_INT:
172 return ctx->ac.i32;
173 case GLSL_TYPE_UINT64:
174 case GLSL_TYPE_INT64:
175 return ctx->ac.i64;
176 case GLSL_TYPE_DOUBLE:
177 return ctx->ac.f64;
178 case GLSL_TYPE_FLOAT:
179 return ctx->ac.f32;
180 default:
181 assert(!"Unsupported type in nir2llvmtype()");
182 break;
183 }
184 return 0;
185 }
186
187 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
188 const nir_deref_var *deref,
189 enum ac_descriptor_type desc_type,
190 const nir_tex_instr *instr,
191 bool image, bool write);
192
193 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
194 {
195 return (index * 4) + chan;
196 }
197
198 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
199 {
200 /* handle patch indices separate */
201 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
202 return 0;
203 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
204 return 1;
205 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
206 return 2 + (slot - VARYING_SLOT_PATCH0);
207
208 if (slot == VARYING_SLOT_POS)
209 return 0;
210 if (slot == VARYING_SLOT_PSIZ)
211 return 1;
212 if (slot == VARYING_SLOT_CLIP_DIST0)
213 return 2;
214 /* 3 is reserved for clip dist as well */
215 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
216 return 4 + (slot - VARYING_SLOT_VAR0);
217 unreachable("illegal slot in get unique index\n");
218 }
219
220 static void set_llvm_calling_convention(LLVMValueRef func,
221 gl_shader_stage stage)
222 {
223 enum radeon_llvm_calling_convention calling_conv;
224
225 switch (stage) {
226 case MESA_SHADER_VERTEX:
227 case MESA_SHADER_TESS_EVAL:
228 calling_conv = RADEON_LLVM_AMDGPU_VS;
229 break;
230 case MESA_SHADER_GEOMETRY:
231 calling_conv = RADEON_LLVM_AMDGPU_GS;
232 break;
233 case MESA_SHADER_TESS_CTRL:
234 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
235 break;
236 case MESA_SHADER_FRAGMENT:
237 calling_conv = RADEON_LLVM_AMDGPU_PS;
238 break;
239 case MESA_SHADER_COMPUTE:
240 calling_conv = RADEON_LLVM_AMDGPU_CS;
241 break;
242 default:
243 unreachable("Unhandle shader type");
244 }
245
246 LLVMSetFunctionCallConv(func, calling_conv);
247 }
248
249 #define MAX_ARGS 23
250 struct arg_info {
251 LLVMTypeRef types[MAX_ARGS];
252 LLVMValueRef *assign[MAX_ARGS];
253 unsigned array_params_mask;
254 uint8_t count;
255 uint8_t sgpr_count;
256 uint8_t num_sgprs_used;
257 uint8_t num_vgprs_used;
258 };
259
260 static inline void
261 add_argument(struct arg_info *info,
262 LLVMTypeRef type, LLVMValueRef *param_ptr)
263 {
264 assert(info->count < MAX_ARGS);
265 info->assign[info->count] = param_ptr;
266 info->types[info->count] = type;
267 info->count++;
268 }
269
270 static inline void
271 add_sgpr_argument(struct arg_info *info,
272 LLVMTypeRef type, LLVMValueRef *param_ptr)
273 {
274 add_argument(info, type, param_ptr);
275 info->num_sgprs_used += ac_get_type_size(type) / 4;
276 info->sgpr_count++;
277 }
278
279 static inline void
280 add_user_sgpr_argument(struct arg_info *info,
281 LLVMTypeRef type,
282 LLVMValueRef *param_ptr)
283 {
284 add_sgpr_argument(info, type, param_ptr);
285 }
286
287 static inline void
288 add_vgpr_argument(struct arg_info *info,
289 LLVMTypeRef type,
290 LLVMValueRef *param_ptr)
291 {
292 add_argument(info, type, param_ptr);
293 info->num_vgprs_used += ac_get_type_size(type) / 4;
294 }
295
296 static inline void
297 add_user_sgpr_array_argument(struct arg_info *info,
298 LLVMTypeRef type,
299 LLVMValueRef *param_ptr)
300 {
301 info->array_params_mask |= (1 << info->count);
302 add_user_sgpr_argument(info, type, param_ptr);
303 }
304
305 static void assign_arguments(LLVMValueRef main_function,
306 struct arg_info *info)
307 {
308 unsigned i;
309 for (i = 0; i < info->count; i++) {
310 if (info->assign[i])
311 *info->assign[i] = LLVMGetParam(main_function, i);
312 }
313 }
314
315 static LLVMValueRef
316 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
317 LLVMBuilderRef builder, LLVMTypeRef *return_types,
318 unsigned num_return_elems,
319 struct arg_info *args,
320 unsigned max_workgroup_size,
321 bool unsafe_math)
322 {
323 LLVMTypeRef main_function_type, ret_type;
324 LLVMBasicBlockRef main_function_body;
325
326 if (num_return_elems)
327 ret_type = LLVMStructTypeInContext(ctx, return_types,
328 num_return_elems, true);
329 else
330 ret_type = LLVMVoidTypeInContext(ctx);
331
332 /* Setup the function */
333 main_function_type =
334 LLVMFunctionType(ret_type, args->types, args->count, 0);
335 LLVMValueRef main_function =
336 LLVMAddFunction(module, "main", main_function_type);
337 main_function_body =
338 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
339 LLVMPositionBuilderAtEnd(builder, main_function_body);
340
341 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
342 for (unsigned i = 0; i < args->sgpr_count; ++i) {
343 if (args->array_params_mask & (1 << i)) {
344 LLVMValueRef P = LLVMGetParam(main_function, i);
345 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
346 ac_add_attr_dereferenceable(P, UINT64_MAX);
347 }
348 else {
349 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
350 }
351 }
352
353 if (max_workgroup_size) {
354 ac_llvm_add_target_dep_function_attr(main_function,
355 "amdgpu-max-work-group-size",
356 max_workgroup_size);
357 }
358 if (unsafe_math) {
359 /* These were copied from some LLVM test. */
360 LLVMAddTargetDependentFunctionAttr(main_function,
361 "less-precise-fpmad",
362 "true");
363 LLVMAddTargetDependentFunctionAttr(main_function,
364 "no-infs-fp-math",
365 "true");
366 LLVMAddTargetDependentFunctionAttr(main_function,
367 "no-nans-fp-math",
368 "true");
369 LLVMAddTargetDependentFunctionAttr(main_function,
370 "unsafe-fp-math",
371 "true");
372 }
373 return main_function;
374 }
375
376 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
377 {
378 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
379 CONST_ADDR_SPACE);
380 }
381
382 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
383 {
384 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
385 type = LLVMGetElementType(type);
386
387 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
388 return LLVMGetIntTypeWidth(type);
389
390 if (type == ctx->f16)
391 return 16;
392 if (type == ctx->f32)
393 return 32;
394 if (type == ctx->f64)
395 return 64;
396
397 unreachable("Unhandled type kind in get_elem_bits");
398 }
399
400 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
401 LLVMValueRef param, unsigned rshift,
402 unsigned bitwidth)
403 {
404 LLVMValueRef value = param;
405 if (rshift)
406 value = LLVMBuildLShr(ctx->builder, value,
407 LLVMConstInt(ctx->i32, rshift, false), "");
408
409 if (rshift + bitwidth < 32) {
410 unsigned mask = (1 << bitwidth) - 1;
411 value = LLVMBuildAnd(ctx->builder, value,
412 LLVMConstInt(ctx->i32, mask, false), "");
413 }
414 return value;
415 }
416
417 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
418 {
419 switch (ctx->stage) {
420 case MESA_SHADER_TESS_CTRL:
421 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
422 case MESA_SHADER_TESS_EVAL:
423 return ctx->tes_rel_patch_id;
424 break;
425 default:
426 unreachable("Illegal stage");
427 }
428 }
429
430 /* Tessellation shaders pass outputs to the next shader using LDS.
431 *
432 * LS outputs = TCS inputs
433 * TCS outputs = TES inputs
434 *
435 * The LDS layout is:
436 * - TCS inputs for patch 0
437 * - TCS inputs for patch 1
438 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
439 * - ...
440 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
441 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
442 * - TCS outputs for patch 1
443 * - Per-patch TCS outputs for patch 1
444 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
445 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
446 * - ...
447 *
448 * All three shaders VS(LS), TCS, TES share the same LDS space.
449 */
450 static LLVMValueRef
451 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
452 {
453 if (ctx->stage == MESA_SHADER_VERTEX)
454 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
455 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
456 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
457 else {
458 assert(0);
459 return NULL;
460 }
461 }
462
463 static LLVMValueRef
464 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
465 {
466 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
467 }
468
469 static LLVMValueRef
470 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
471 {
472 return LLVMBuildMul(ctx->builder,
473 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
474 LLVMConstInt(ctx->ac.i32, 4, false), "");
475 }
476
477 static LLVMValueRef
478 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
479 {
480 return LLVMBuildMul(ctx->builder,
481 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
482 LLVMConstInt(ctx->ac.i32, 4, false), "");
483 }
484
485 static LLVMValueRef
486 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
487 {
488 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
489 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
490
491 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
492 }
493
494 static LLVMValueRef
495 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
496 {
497 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
498 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
499 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
500
501 return LLVMBuildAdd(ctx->builder, patch0_offset,
502 LLVMBuildMul(ctx->builder, patch_stride,
503 rel_patch_id, ""),
504 "");
505 }
506
507 static LLVMValueRef
508 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
509 {
510 LLVMValueRef patch0_patch_data_offset =
511 get_tcs_out_patch0_patch_data_offset(ctx);
512 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
513 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
514
515 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
516 LLVMBuildMul(ctx->builder, patch_stride,
517 rel_patch_id, ""),
518 "");
519 }
520
521 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
522 {
523 ud_info->sgpr_idx = *sgpr_idx;
524 ud_info->num_sgprs = num_sgprs;
525 ud_info->indirect = false;
526 ud_info->indirect_offset = 0;
527 *sgpr_idx += num_sgprs;
528 }
529
530 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
531 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
532 {
533 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
534 }
535
536
537 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
538 uint32_t indirect_offset)
539 {
540 ud_info->sgpr_idx = sgpr_idx;
541 ud_info->num_sgprs = num_sgprs;
542 ud_info->indirect = true;
543 ud_info->indirect_offset = indirect_offset;
544 }
545
546 struct user_sgpr_info {
547 bool need_ring_offsets;
548 uint8_t sgpr_count;
549 bool indirect_all_descriptor_sets;
550 };
551
552 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
553 struct user_sgpr_info *user_sgpr_info)
554 {
555 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
556
557 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
558 if (ctx->stage == MESA_SHADER_GEOMETRY ||
559 ctx->stage == MESA_SHADER_VERTEX ||
560 ctx->stage == MESA_SHADER_TESS_CTRL ||
561 ctx->stage == MESA_SHADER_TESS_EVAL ||
562 ctx->is_gs_copy_shader)
563 user_sgpr_info->need_ring_offsets = true;
564
565 if (ctx->stage == MESA_SHADER_FRAGMENT &&
566 ctx->shader_info->info.ps.needs_sample_positions)
567 user_sgpr_info->need_ring_offsets = true;
568
569 /* 2 user sgprs will nearly always be allocated for scratch/rings */
570 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
571 user_sgpr_info->sgpr_count += 2;
572 }
573
574 switch (ctx->stage) {
575 case MESA_SHADER_COMPUTE:
576 if (ctx->shader_info->info.cs.uses_grid_size)
577 user_sgpr_info->sgpr_count += 3;
578 break;
579 case MESA_SHADER_FRAGMENT:
580 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
581 break;
582 case MESA_SHADER_VERTEX:
583 if (!ctx->is_gs_copy_shader) {
584 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
585 if (ctx->shader_info->info.vs.needs_draw_id) {
586 user_sgpr_info->sgpr_count += 3;
587 } else {
588 user_sgpr_info->sgpr_count += 2;
589 }
590 }
591 if (ctx->options->key.vs.as_ls)
592 user_sgpr_info->sgpr_count++;
593 break;
594 case MESA_SHADER_TESS_CTRL:
595 user_sgpr_info->sgpr_count += 4;
596 break;
597 case MESA_SHADER_TESS_EVAL:
598 user_sgpr_info->sgpr_count += 1;
599 break;
600 case MESA_SHADER_GEOMETRY:
601 user_sgpr_info->sgpr_count += 2;
602 break;
603 default:
604 break;
605 }
606
607 if (ctx->shader_info->info.needs_push_constants)
608 user_sgpr_info->sgpr_count += 2;
609
610 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
611 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
612 user_sgpr_info->sgpr_count += 2;
613 user_sgpr_info->indirect_all_descriptor_sets = true;
614 } else {
615 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
616 }
617 }
618
619 static void
620 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
621 gl_shader_stage stage,
622 bool has_previous_stage,
623 gl_shader_stage previous_stage,
624 const struct user_sgpr_info *user_sgpr_info,
625 struct arg_info *args,
626 LLVMValueRef *desc_sets)
627 {
628 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
629 unsigned stage_mask = 1 << stage;
630 if (has_previous_stage)
631 stage_mask |= 1 << previous_stage;
632
633 /* 1 for each descriptor set */
634 if (!user_sgpr_info->indirect_all_descriptor_sets) {
635 for (unsigned i = 0; i < num_sets; ++i) {
636 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
637 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->descriptor_sets[i]);
638 }
639 }
640 } else
641 add_user_sgpr_array_argument(args, const_array(const_array(ctx->ac.i8, 1024 * 1024), 32), desc_sets);
642
643 if (ctx->shader_info->info.needs_push_constants) {
644 /* 1 for push constants and dynamic descriptors */
645 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->push_constants);
646 }
647 }
648
649 static void
650 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
651 gl_shader_stage stage,
652 bool has_previous_stage,
653 gl_shader_stage previous_stage,
654 const struct user_sgpr_info *user_sgpr_info,
655 LLVMValueRef desc_sets,
656 uint8_t *user_sgpr_idx)
657 {
658 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
659 unsigned stage_mask = 1 << stage;
660 if (has_previous_stage)
661 stage_mask |= 1 << previous_stage;
662
663 if (!user_sgpr_info->indirect_all_descriptor_sets) {
664 for (unsigned i = 0; i < num_sets; ++i) {
665 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
666 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
667 } else
668 ctx->descriptor_sets[i] = NULL;
669 }
670 } else {
671 uint32_t desc_sgpr_idx = *user_sgpr_idx;
672 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
673
674 for (unsigned i = 0; i < num_sets; ++i) {
675 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
676 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
677 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->ac.i32, i, false));
678
679 } else
680 ctx->descriptor_sets[i] = NULL;
681 }
682 ctx->shader_info->need_indirect_descriptor_sets = true;
683 }
684
685 if (ctx->shader_info->info.needs_push_constants) {
686 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
687 }
688 }
689
690
691 static void
692 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
693 gl_shader_stage stage,
694 bool has_previous_stage,
695 gl_shader_stage previous_stage,
696 uint8_t *user_sgpr_idx)
697 {
698 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
699 if (ctx->shader_info->info.vs.has_vertex_buffers) {
700 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
701 }
702 unsigned vs_num = 2;
703 if (ctx->shader_info->info.vs.needs_draw_id)
704 vs_num++;
705
706 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
707 }
708 }
709
710 static void
711 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
712 gl_shader_stage stage,
713 bool has_previous_stage,
714 gl_shader_stage previous_stage,
715 struct arg_info *args)
716 {
717 if (!ctx->is_gs_copy_shader &&
718 (stage == MESA_SHADER_VERTEX ||
719 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
720 if (ctx->shader_info->info.vs.has_vertex_buffers) {
721 add_user_sgpr_argument(args,
722 const_array(ctx->ac.v4i32, 16),
723 &ctx->vertex_buffers);
724 }
725 add_user_sgpr_argument(args, ctx->ac.i32,
726 &ctx->abi.base_vertex);
727 add_user_sgpr_argument(args, ctx->ac.i32,
728 &ctx->abi.start_instance);
729 if (ctx->shader_info->info.vs.needs_draw_id) {
730 add_user_sgpr_argument(args, ctx->ac.i32,
731 &ctx->abi.draw_id);
732 }
733 }
734 }
735
736 static void
737 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
738 {
739 add_vgpr_argument(args, ctx->ac.i32, &ctx->abi.vertex_id);
740 if (!ctx->is_gs_copy_shader) {
741 add_vgpr_argument(args, ctx->ac.i32, &ctx->rel_auto_id);
742 add_vgpr_argument(args, ctx->ac.i32, &ctx->vs_prim_id);
743 add_vgpr_argument(args, ctx->ac.i32, &ctx->abi.instance_id);
744 }
745 }
746
747 static void
748 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
749 {
750 add_vgpr_argument(args, ctx->ac.f32, &ctx->tes_u);
751 add_vgpr_argument(args, ctx->ac.f32, &ctx->tes_v);
752 add_vgpr_argument(args, ctx->ac.i32, &ctx->tes_rel_patch_id);
753 add_vgpr_argument(args, ctx->ac.i32, &ctx->tes_patch_id);
754 }
755
756 static void create_function(struct nir_to_llvm_context *ctx,
757 gl_shader_stage stage,
758 bool has_previous_stage,
759 gl_shader_stage previous_stage)
760 {
761 uint8_t user_sgpr_idx;
762 struct user_sgpr_info user_sgpr_info;
763 struct arg_info args = {};
764 LLVMValueRef desc_sets;
765
766 allocate_user_sgprs(ctx, &user_sgpr_info);
767
768 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
769 add_user_sgpr_argument(&args, const_array(ctx->ac.v4i32, 16), &ctx->ring_offsets); /* address of rings */
770 }
771
772 switch (stage) {
773 case MESA_SHADER_COMPUTE:
774 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
775 if (ctx->shader_info->info.cs.uses_grid_size) {
776 add_user_sgpr_argument(&args, ctx->ac.v3i32,
777 &ctx->num_work_groups);
778 }
779
780 for (int i = 0; i < 3; i++) {
781 ctx->workgroup_ids[i] = NULL;
782 if (ctx->shader_info->info.cs.uses_block_id[i]) {
783 add_sgpr_argument(&args, ctx->ac.i32,
784 &ctx->workgroup_ids[i]);
785 }
786 }
787
788 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
789 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tg_size);
790 add_vgpr_argument(&args, ctx->ac.v3i32, &ctx->local_invocation_ids);
791 break;
792 case MESA_SHADER_VERTEX:
793 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
794 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
795 previous_stage, &args);
796
797 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
798 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
799 if (ctx->options->key.vs.as_es)
800 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
801 else if (ctx->options->key.vs.as_ls)
802 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
803
804 declare_vs_input_vgprs(ctx, &args);
805 break;
806 case MESA_SHADER_TESS_CTRL:
807 if (has_previous_stage) {
808 // First 6 system regs
809 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
810 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
811 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
812
813 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
814 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
815 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
816
817 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
818 declare_vs_specific_input_sgprs(ctx, stage,
819 has_previous_stage,
820 previous_stage, &args);
821
822 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
823
824 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
825 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
826 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
827 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
828 if (ctx->shader_info->info.needs_multiview_view_index)
829 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
830
831 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
832 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
833
834 declare_vs_input_vgprs(ctx, &args);
835 } else {
836 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
837 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
838 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
839 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
840 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
841 if (ctx->shader_info->info.needs_multiview_view_index)
842 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
843 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
844 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
845 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
846 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
847 }
848 break;
849 case MESA_SHADER_TESS_EVAL:
850 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
851 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
852 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
853 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
854 if (ctx->options->key.tes.as_es) {
855 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
856 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
857 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
858 } else {
859 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
860 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
861 }
862 declare_tes_input_vgprs(ctx, &args);
863 break;
864 case MESA_SHADER_GEOMETRY:
865 if (has_previous_stage) {
866 // First 6 system regs
867 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // tess factor offset
868 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
869 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
870
871 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
872 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
873 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
874
875 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
876
877 if (previous_stage == MESA_SHADER_TESS_EVAL) {
878 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
879 } else {
880 declare_vs_specific_input_sgprs(ctx, stage,
881 has_previous_stage,
882 previous_stage,
883 &args);
884 }
885
886 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
887 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
888 if (ctx->shader_info->info.needs_multiview_view_index)
889 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
890
891 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx01
892 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]); // vtx23
893 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_prim_id); // prim id
894 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_invocation_id);
895 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
896
897 if (previous_stage == MESA_SHADER_VERTEX) {
898 declare_vs_input_vgprs(ctx, &args);
899 } else {
900 declare_tes_input_vgprs(ctx, &args);
901 }
902 } else {
903 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
904 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
905 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
906 if (ctx->shader_info->info.needs_multiview_view_index)
907 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
908 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // gs2vs offset
909 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs_wave_id); // wave id
910 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx0
911 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[1]); // vtx1
912 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_prim_id); // prim id
913 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]);
914 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[3]);
915 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
916 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[5]);
917 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_invocation_id);
918 }
919 break;
920 case MESA_SHADER_FRAGMENT:
921 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
922 if (ctx->shader_info->info.ps.needs_sample_positions)
923 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->sample_pos_offset); /* sample position offset */
924 add_sgpr_argument(&args, ctx->ac.i32, &ctx->prim_mask); /* prim mask */
925 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_sample); /* persp sample */
926 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_center); /* persp center */
927 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_centroid); /* persp centroid */
928 add_vgpr_argument(&args, ctx->ac.v3i32, NULL); /* persp pull model */
929 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_sample); /* linear sample */
930 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_center); /* linear center */
931 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_centroid); /* linear centroid */
932 add_vgpr_argument(&args, ctx->ac.f32, NULL); /* line stipple tex */
933 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[0]); /* pos x float */
934 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[1]); /* pos y float */
935 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[2]); /* pos z float */
936 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[3]); /* pos w float */
937 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.front_face); /* front face */
938 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.ancillary); /* ancillary */
939 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.sample_coverage); /* sample coverage */
940 add_vgpr_argument(&args, ctx->ac.i32, NULL); /* fixed pt */
941 break;
942 default:
943 unreachable("Shader stage not implemented");
944 }
945
946 ctx->main_function = create_llvm_function(
947 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
948 ctx->max_workgroup_size,
949 ctx->options->unsafe_math);
950 set_llvm_calling_convention(ctx->main_function, stage);
951
952
953 ctx->shader_info->num_input_vgprs = 0;
954 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
955
956 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
957
958 if (ctx->stage != MESA_SHADER_FRAGMENT)
959 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
960
961 assign_arguments(ctx->main_function, &args);
962
963 user_sgpr_idx = 0;
964
965 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
966 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
967 if (ctx->options->supports_spill) {
968 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
969 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
970 NULL, 0, AC_FUNC_ATTR_READNONE);
971 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
972 const_array(ctx->ac.v4i32, 16), "");
973 }
974 }
975
976 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
977 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
978 if (has_previous_stage)
979 user_sgpr_idx = 0;
980
981 radv_define_common_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, desc_sets, &user_sgpr_idx);
982
983 switch (stage) {
984 case MESA_SHADER_COMPUTE:
985 if (ctx->shader_info->info.cs.uses_grid_size) {
986 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE,
987 &user_sgpr_idx, 3);
988 }
989 break;
990 case MESA_SHADER_VERTEX:
991 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
992 if (ctx->view_index)
993 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
994 if (ctx->options->key.vs.as_ls) {
995 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
996 }
997 if (ctx->options->key.vs.as_ls)
998 ac_declare_lds_as_pointer(&ctx->ac);
999 break;
1000 case MESA_SHADER_TESS_CTRL:
1001 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
1002 if (has_previous_stage)
1003 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
1004 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1005 if (ctx->view_index)
1006 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1007 ac_declare_lds_as_pointer(&ctx->ac);
1008 break;
1009 case MESA_SHADER_TESS_EVAL:
1010 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1011 if (ctx->view_index)
1012 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1013 break;
1014 case MESA_SHADER_GEOMETRY:
1015 if (has_previous_stage) {
1016 if (previous_stage == MESA_SHADER_VERTEX)
1017 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
1018 else
1019 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1020 }
1021 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
1022 if (ctx->view_index)
1023 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1024 if (has_previous_stage)
1025 ac_declare_lds_as_pointer(&ctx->ac);
1026 break;
1027 case MESA_SHADER_FRAGMENT:
1028 if (ctx->shader_info->info.ps.needs_sample_positions) {
1029 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
1030 }
1031 break;
1032 default:
1033 unreachable("Shader stage not implemented");
1034 }
1035
1036 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1037 }
1038
1039 static int get_llvm_num_components(LLVMValueRef value)
1040 {
1041 LLVMTypeRef type = LLVMTypeOf(value);
1042 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1043 ? LLVMGetVectorSize(type)
1044 : 1;
1045 return num_components;
1046 }
1047
1048 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1049 LLVMValueRef value,
1050 int index)
1051 {
1052 int count = get_llvm_num_components(value);
1053
1054 if (count == 1)
1055 return value;
1056
1057 return LLVMBuildExtractElement(ac->builder, value,
1058 LLVMConstInt(ac->i32, index, false), "");
1059 }
1060
1061 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1062 LLVMValueRef value, unsigned count)
1063 {
1064 unsigned num_components = get_llvm_num_components(value);
1065 if (count == num_components)
1066 return value;
1067
1068 LLVMValueRef masks[] = {
1069 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1070 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1071
1072 if (count == 1)
1073 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1074 "");
1075
1076 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1077 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1078 }
1079
1080 static void
1081 build_store_values_extended(struct ac_llvm_context *ac,
1082 LLVMValueRef *values,
1083 unsigned value_count,
1084 unsigned value_stride,
1085 LLVMValueRef vec)
1086 {
1087 LLVMBuilderRef builder = ac->builder;
1088 unsigned i;
1089
1090 for (i = 0; i < value_count; i++) {
1091 LLVMValueRef ptr = values[i * value_stride];
1092 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1093 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1094 LLVMBuildStore(builder, value, ptr);
1095 }
1096 }
1097
1098 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1099 const nir_ssa_def *def)
1100 {
1101 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1102 if (def->num_components > 1) {
1103 type = LLVMVectorType(type, def->num_components);
1104 }
1105 return type;
1106 }
1107
1108 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1109 {
1110 assert(src.is_ssa);
1111 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1112 return (LLVMValueRef)entry->data;
1113 }
1114
1115
1116 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1117 const struct nir_block *b)
1118 {
1119 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1120 return (LLVMBasicBlockRef)entry->data;
1121 }
1122
1123 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1124 nir_alu_src src,
1125 unsigned num_components)
1126 {
1127 LLVMValueRef value = get_src(ctx, src.src);
1128 bool need_swizzle = false;
1129
1130 assert(value);
1131 LLVMTypeRef type = LLVMTypeOf(value);
1132 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1133 ? LLVMGetVectorSize(type)
1134 : 1;
1135
1136 for (unsigned i = 0; i < num_components; ++i) {
1137 assert(src.swizzle[i] < src_components);
1138 if (src.swizzle[i] != i)
1139 need_swizzle = true;
1140 }
1141
1142 if (need_swizzle || num_components != src_components) {
1143 LLVMValueRef masks[] = {
1144 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1145 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1146 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1147 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1148
1149 if (src_components > 1 && num_components == 1) {
1150 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1151 masks[0], "");
1152 } else if (src_components == 1 && num_components > 1) {
1153 LLVMValueRef values[] = {value, value, value, value};
1154 value = ac_build_gather_values(&ctx->ac, values, num_components);
1155 } else {
1156 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1157 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1158 swizzle, "");
1159 }
1160 }
1161 assert(!src.negate);
1162 assert(!src.abs);
1163 return value;
1164 }
1165
1166 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1167 LLVMIntPredicate pred, LLVMValueRef src0,
1168 LLVMValueRef src1)
1169 {
1170 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1171 return LLVMBuildSelect(ctx->builder, result,
1172 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1173 ctx->i32_0, "");
1174 }
1175
1176 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1177 LLVMRealPredicate pred, LLVMValueRef src0,
1178 LLVMValueRef src1)
1179 {
1180 LLVMValueRef result;
1181 src0 = ac_to_float(ctx, src0);
1182 src1 = ac_to_float(ctx, src1);
1183 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1184 return LLVMBuildSelect(ctx->builder, result,
1185 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1186 ctx->i32_0, "");
1187 }
1188
1189 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1190 const char *intrin,
1191 LLVMTypeRef result_type,
1192 LLVMValueRef src0)
1193 {
1194 char name[64];
1195 LLVMValueRef params[] = {
1196 ac_to_float(ctx, src0),
1197 };
1198
1199 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1200 get_elem_bits(ctx, result_type));
1201 assert(length < sizeof(name));
1202 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1203 }
1204
1205 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1206 const char *intrin,
1207 LLVMTypeRef result_type,
1208 LLVMValueRef src0, LLVMValueRef src1)
1209 {
1210 char name[64];
1211 LLVMValueRef params[] = {
1212 ac_to_float(ctx, src0),
1213 ac_to_float(ctx, src1),
1214 };
1215
1216 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1217 get_elem_bits(ctx, result_type));
1218 assert(length < sizeof(name));
1219 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1220 }
1221
1222 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1223 const char *intrin,
1224 LLVMTypeRef result_type,
1225 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1226 {
1227 char name[64];
1228 LLVMValueRef params[] = {
1229 ac_to_float(ctx, src0),
1230 ac_to_float(ctx, src1),
1231 ac_to_float(ctx, src2),
1232 };
1233
1234 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1235 get_elem_bits(ctx, result_type));
1236 assert(length < sizeof(name));
1237 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1238 }
1239
1240 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1241 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1242 {
1243 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1244 ctx->i32_0, "");
1245 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1246 }
1247
1248 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1249 LLVMIntPredicate pred,
1250 LLVMValueRef src0, LLVMValueRef src1)
1251 {
1252 return LLVMBuildSelect(ctx->builder,
1253 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1254 src0,
1255 src1, "");
1256
1257 }
1258 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1259 LLVMValueRef src0)
1260 {
1261 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1262 LLVMBuildNeg(ctx->builder, src0, ""));
1263 }
1264
1265 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1266 LLVMValueRef src0)
1267 {
1268 LLVMValueRef cmp, val;
1269
1270 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1271 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1272 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1273 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1274 return val;
1275 }
1276
1277 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1278 LLVMValueRef src0)
1279 {
1280 LLVMValueRef cmp, val;
1281
1282 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1283 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1284 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1285 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1286 return val;
1287 }
1288
1289 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1290 LLVMValueRef src0)
1291 {
1292 const char *intr = "llvm.floor.f32";
1293 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1294 LLVMValueRef params[] = {
1295 fsrc0,
1296 };
1297 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1298 ctx->f32, params, 1,
1299 AC_FUNC_ATTR_READNONE);
1300 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1301 }
1302
1303 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1304 const char *intrin,
1305 LLVMValueRef src0, LLVMValueRef src1)
1306 {
1307 LLVMTypeRef ret_type;
1308 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1309 LLVMValueRef res;
1310 LLVMValueRef params[] = { src0, src1 };
1311 ret_type = LLVMStructTypeInContext(ctx->context, types,
1312 2, true);
1313
1314 res = ac_build_intrinsic(ctx, intrin, ret_type,
1315 params, 2, AC_FUNC_ATTR_READNONE);
1316
1317 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1318 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1319 return res;
1320 }
1321
1322 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1323 LLVMValueRef src0)
1324 {
1325 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1326 }
1327
1328 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1329 LLVMValueRef src0)
1330 {
1331 src0 = ac_to_float(ctx, src0);
1332 return LLVMBuildSExt(ctx->builder,
1333 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1334 ctx->i32, "");
1335 }
1336
1337 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1338 LLVMValueRef src0)
1339 {
1340 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1341 }
1342
1343 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1344 LLVMValueRef src0)
1345 {
1346 return LLVMBuildSExt(ctx->builder,
1347 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1348 ctx->i32, "");
1349 }
1350
1351 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1352 LLVMValueRef src0)
1353 {
1354 LLVMValueRef result;
1355 LLVMValueRef cond = NULL;
1356
1357 src0 = ac_to_float(&ctx->ac, src0);
1358 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1359
1360 if (ctx->options->chip_class >= VI) {
1361 LLVMValueRef args[2];
1362 /* Check if the result is a denormal - and flush to 0 if so. */
1363 args[0] = result;
1364 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1365 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1366 }
1367
1368 /* need to convert back up to f32 */
1369 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1370
1371 if (ctx->options->chip_class >= VI)
1372 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1373 else {
1374 /* for SI/CIK */
1375 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1376 * so compare the result and flush to 0 if it's smaller.
1377 */
1378 LLVMValueRef temp, cond2;
1379 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1380 ctx->ac.f32, result);
1381 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1382 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1383 temp, "");
1384 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1385 temp, ctx->ac.f32_0, "");
1386 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1387 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1388 }
1389 return result;
1390 }
1391
1392 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1393 LLVMValueRef src0, LLVMValueRef src1)
1394 {
1395 LLVMValueRef dst64, result;
1396 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1397 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1398
1399 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1400 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1401 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1402 return result;
1403 }
1404
1405 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1406 LLVMValueRef src0, LLVMValueRef src1)
1407 {
1408 LLVMValueRef dst64, result;
1409 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1410 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1411
1412 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1413 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1414 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1415 return result;
1416 }
1417
1418 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1419 bool is_signed,
1420 const LLVMValueRef srcs[3])
1421 {
1422 LLVMValueRef result;
1423 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1424
1425 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1426 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1427 return result;
1428 }
1429
1430 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1431 LLVMValueRef src0, LLVMValueRef src1,
1432 LLVMValueRef src2, LLVMValueRef src3)
1433 {
1434 LLVMValueRef bfi_args[3], result;
1435
1436 bfi_args[0] = LLVMBuildShl(ctx->builder,
1437 LLVMBuildSub(ctx->builder,
1438 LLVMBuildShl(ctx->builder,
1439 ctx->i32_1,
1440 src3, ""),
1441 ctx->i32_1, ""),
1442 src2, "");
1443 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1444 bfi_args[2] = src0;
1445
1446 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1447
1448 /* Calculate:
1449 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1450 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1451 */
1452 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1453 LLVMBuildAnd(ctx->builder, bfi_args[0],
1454 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1455
1456 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1457 return result;
1458 }
1459
1460 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1461 LLVMValueRef src0)
1462 {
1463 LLVMValueRef comp[2];
1464
1465 src0 = ac_to_float(ctx, src0);
1466 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1467 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1468
1469 return ac_build_cvt_pkrtz_f16(ctx, comp);
1470 }
1471
1472 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1473 LLVMValueRef src0)
1474 {
1475 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1476 LLVMValueRef temps[2], result, val;
1477 int i;
1478
1479 for (i = 0; i < 2; i++) {
1480 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1481 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1482 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1483 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1484 }
1485
1486 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1487 ctx->i32_0, "");
1488 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1489 ctx->i32_1, "");
1490 return result;
1491 }
1492
1493 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1494 nir_op op,
1495 LLVMValueRef src0)
1496 {
1497 unsigned mask;
1498 int idx;
1499 LLVMValueRef result;
1500
1501 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1502 mask = AC_TID_MASK_LEFT;
1503 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1504 mask = AC_TID_MASK_TOP;
1505 else
1506 mask = AC_TID_MASK_TOP_LEFT;
1507
1508 /* for DDX we want to next X pixel, DDY next Y pixel. */
1509 if (op == nir_op_fddx_fine ||
1510 op == nir_op_fddx_coarse ||
1511 op == nir_op_fddx)
1512 idx = 1;
1513 else
1514 idx = 2;
1515
1516 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1517 return result;
1518 }
1519
1520 /*
1521 * this takes an I,J coordinate pair,
1522 * and works out the X and Y derivatives.
1523 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1524 */
1525 static LLVMValueRef emit_ddxy_interp(
1526 struct ac_nir_context *ctx,
1527 LLVMValueRef interp_ij)
1528 {
1529 LLVMValueRef result[4], a;
1530 unsigned i;
1531
1532 for (i = 0; i < 2; i++) {
1533 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1534 LLVMConstInt(ctx->ac.i32, i, false), "");
1535 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1536 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1537 }
1538 return ac_build_gather_values(&ctx->ac, result, 4);
1539 }
1540
1541 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1542 {
1543 LLVMValueRef src[4], result = NULL;
1544 unsigned num_components = instr->dest.dest.ssa.num_components;
1545 unsigned src_components;
1546 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1547
1548 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1549 switch (instr->op) {
1550 case nir_op_vec2:
1551 case nir_op_vec3:
1552 case nir_op_vec4:
1553 src_components = 1;
1554 break;
1555 case nir_op_pack_half_2x16:
1556 src_components = 2;
1557 break;
1558 case nir_op_unpack_half_2x16:
1559 src_components = 1;
1560 break;
1561 default:
1562 src_components = num_components;
1563 break;
1564 }
1565 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1566 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1567
1568 switch (instr->op) {
1569 case nir_op_fmov:
1570 case nir_op_imov:
1571 result = src[0];
1572 break;
1573 case nir_op_fneg:
1574 src[0] = ac_to_float(&ctx->ac, src[0]);
1575 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1576 break;
1577 case nir_op_ineg:
1578 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1579 break;
1580 case nir_op_inot:
1581 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1582 break;
1583 case nir_op_iadd:
1584 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1585 break;
1586 case nir_op_fadd:
1587 src[0] = ac_to_float(&ctx->ac, src[0]);
1588 src[1] = ac_to_float(&ctx->ac, src[1]);
1589 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1590 break;
1591 case nir_op_fsub:
1592 src[0] = ac_to_float(&ctx->ac, src[0]);
1593 src[1] = ac_to_float(&ctx->ac, src[1]);
1594 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1595 break;
1596 case nir_op_isub:
1597 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1598 break;
1599 case nir_op_imul:
1600 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1601 break;
1602 case nir_op_imod:
1603 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1604 break;
1605 case nir_op_umod:
1606 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1607 break;
1608 case nir_op_fmod:
1609 src[0] = ac_to_float(&ctx->ac, src[0]);
1610 src[1] = ac_to_float(&ctx->ac, src[1]);
1611 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1612 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1613 ac_to_float_type(&ctx->ac, def_type), result);
1614 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1615 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1616 break;
1617 case nir_op_frem:
1618 src[0] = ac_to_float(&ctx->ac, src[0]);
1619 src[1] = ac_to_float(&ctx->ac, src[1]);
1620 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1621 break;
1622 case nir_op_irem:
1623 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1624 break;
1625 case nir_op_idiv:
1626 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1627 break;
1628 case nir_op_udiv:
1629 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1630 break;
1631 case nir_op_fmul:
1632 src[0] = ac_to_float(&ctx->ac, src[0]);
1633 src[1] = ac_to_float(&ctx->ac, src[1]);
1634 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1635 break;
1636 case nir_op_fdiv:
1637 src[0] = ac_to_float(&ctx->ac, src[0]);
1638 src[1] = ac_to_float(&ctx->ac, src[1]);
1639 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1640 break;
1641 case nir_op_frcp:
1642 src[0] = ac_to_float(&ctx->ac, src[0]);
1643 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1644 break;
1645 case nir_op_iand:
1646 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1647 break;
1648 case nir_op_ior:
1649 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1650 break;
1651 case nir_op_ixor:
1652 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1653 break;
1654 case nir_op_ishl:
1655 result = LLVMBuildShl(ctx->ac.builder, src[0],
1656 LLVMBuildZExt(ctx->ac.builder, src[1],
1657 LLVMTypeOf(src[0]), ""),
1658 "");
1659 break;
1660 case nir_op_ishr:
1661 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1662 LLVMBuildZExt(ctx->ac.builder, src[1],
1663 LLVMTypeOf(src[0]), ""),
1664 "");
1665 break;
1666 case nir_op_ushr:
1667 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1668 LLVMBuildZExt(ctx->ac.builder, src[1],
1669 LLVMTypeOf(src[0]), ""),
1670 "");
1671 break;
1672 case nir_op_ilt:
1673 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1674 break;
1675 case nir_op_ine:
1676 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1677 break;
1678 case nir_op_ieq:
1679 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1680 break;
1681 case nir_op_ige:
1682 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1683 break;
1684 case nir_op_ult:
1685 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1686 break;
1687 case nir_op_uge:
1688 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1689 break;
1690 case nir_op_feq:
1691 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1692 break;
1693 case nir_op_fne:
1694 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1695 break;
1696 case nir_op_flt:
1697 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1698 break;
1699 case nir_op_fge:
1700 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1701 break;
1702 case nir_op_fabs:
1703 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1704 ac_to_float_type(&ctx->ac, def_type), src[0]);
1705 break;
1706 case nir_op_iabs:
1707 result = emit_iabs(&ctx->ac, src[0]);
1708 break;
1709 case nir_op_imax:
1710 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1711 break;
1712 case nir_op_imin:
1713 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1714 break;
1715 case nir_op_umax:
1716 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1717 break;
1718 case nir_op_umin:
1719 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1720 break;
1721 case nir_op_isign:
1722 result = emit_isign(&ctx->ac, src[0]);
1723 break;
1724 case nir_op_fsign:
1725 src[0] = ac_to_float(&ctx->ac, src[0]);
1726 result = emit_fsign(&ctx->ac, src[0]);
1727 break;
1728 case nir_op_ffloor:
1729 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1730 ac_to_float_type(&ctx->ac, def_type), src[0]);
1731 break;
1732 case nir_op_ftrunc:
1733 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1734 ac_to_float_type(&ctx->ac, def_type), src[0]);
1735 break;
1736 case nir_op_fceil:
1737 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1738 ac_to_float_type(&ctx->ac, def_type), src[0]);
1739 break;
1740 case nir_op_fround_even:
1741 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1742 ac_to_float_type(&ctx->ac, def_type),src[0]);
1743 break;
1744 case nir_op_ffract:
1745 result = emit_ffract(&ctx->ac, src[0]);
1746 break;
1747 case nir_op_fsin:
1748 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1749 ac_to_float_type(&ctx->ac, def_type), src[0]);
1750 break;
1751 case nir_op_fcos:
1752 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1753 ac_to_float_type(&ctx->ac, def_type), src[0]);
1754 break;
1755 case nir_op_fsqrt:
1756 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1757 ac_to_float_type(&ctx->ac, def_type), src[0]);
1758 break;
1759 case nir_op_fexp2:
1760 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1761 ac_to_float_type(&ctx->ac, def_type), src[0]);
1762 break;
1763 case nir_op_flog2:
1764 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1765 ac_to_float_type(&ctx->ac, def_type), src[0]);
1766 break;
1767 case nir_op_frsq:
1768 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1769 ac_to_float_type(&ctx->ac, def_type), src[0]);
1770 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1771 break;
1772 case nir_op_fpow:
1773 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1774 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1775 break;
1776 case nir_op_fmax:
1777 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1778 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1779 if (instr->dest.dest.ssa.bit_size == 32)
1780 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1781 ac_to_float_type(&ctx->ac, def_type),
1782 result);
1783 break;
1784 case nir_op_fmin:
1785 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1786 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1787 if (instr->dest.dest.ssa.bit_size == 32)
1788 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1789 ac_to_float_type(&ctx->ac, def_type),
1790 result);
1791 break;
1792 case nir_op_ffma:
1793 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1794 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1795 break;
1796 case nir_op_ibitfield_extract:
1797 result = emit_bitfield_extract(&ctx->ac, true, src);
1798 break;
1799 case nir_op_ubitfield_extract:
1800 result = emit_bitfield_extract(&ctx->ac, false, src);
1801 break;
1802 case nir_op_bitfield_insert:
1803 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1804 break;
1805 case nir_op_bitfield_reverse:
1806 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1807 break;
1808 case nir_op_bit_count:
1809 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1810 break;
1811 case nir_op_vec2:
1812 case nir_op_vec3:
1813 case nir_op_vec4:
1814 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1815 src[i] = ac_to_integer(&ctx->ac, src[i]);
1816 result = ac_build_gather_values(&ctx->ac, src, num_components);
1817 break;
1818 case nir_op_f2i32:
1819 case nir_op_f2i64:
1820 src[0] = ac_to_float(&ctx->ac, src[0]);
1821 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1822 break;
1823 case nir_op_f2u32:
1824 case nir_op_f2u64:
1825 src[0] = ac_to_float(&ctx->ac, src[0]);
1826 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1827 break;
1828 case nir_op_i2f32:
1829 case nir_op_i2f64:
1830 src[0] = ac_to_integer(&ctx->ac, src[0]);
1831 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1832 break;
1833 case nir_op_u2f32:
1834 case nir_op_u2f64:
1835 src[0] = ac_to_integer(&ctx->ac, src[0]);
1836 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1837 break;
1838 case nir_op_f2f64:
1839 src[0] = ac_to_float(&ctx->ac, src[0]);
1840 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1841 break;
1842 case nir_op_f2f32:
1843 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1844 break;
1845 case nir_op_u2u32:
1846 case nir_op_u2u64:
1847 src[0] = ac_to_integer(&ctx->ac, src[0]);
1848 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1849 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1850 else
1851 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1852 break;
1853 case nir_op_i2i32:
1854 case nir_op_i2i64:
1855 src[0] = ac_to_integer(&ctx->ac, src[0]);
1856 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1857 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1858 else
1859 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1860 break;
1861 case nir_op_bcsel:
1862 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1863 break;
1864 case nir_op_find_lsb:
1865 src[0] = ac_to_integer(&ctx->ac, src[0]);
1866 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1867 break;
1868 case nir_op_ufind_msb:
1869 src[0] = ac_to_integer(&ctx->ac, src[0]);
1870 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1871 break;
1872 case nir_op_ifind_msb:
1873 src[0] = ac_to_integer(&ctx->ac, src[0]);
1874 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1875 break;
1876 case nir_op_uadd_carry:
1877 src[0] = ac_to_integer(&ctx->ac, src[0]);
1878 src[1] = ac_to_integer(&ctx->ac, src[1]);
1879 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1880 break;
1881 case nir_op_usub_borrow:
1882 src[0] = ac_to_integer(&ctx->ac, src[0]);
1883 src[1] = ac_to_integer(&ctx->ac, src[1]);
1884 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1885 break;
1886 case nir_op_b2f:
1887 result = emit_b2f(&ctx->ac, src[0]);
1888 break;
1889 case nir_op_f2b:
1890 result = emit_f2b(&ctx->ac, src[0]);
1891 break;
1892 case nir_op_b2i:
1893 result = emit_b2i(&ctx->ac, src[0]);
1894 break;
1895 case nir_op_i2b:
1896 src[0] = ac_to_integer(&ctx->ac, src[0]);
1897 result = emit_i2b(&ctx->ac, src[0]);
1898 break;
1899 case nir_op_fquantize2f16:
1900 result = emit_f2f16(ctx->nctx, src[0]);
1901 break;
1902 case nir_op_umul_high:
1903 src[0] = ac_to_integer(&ctx->ac, src[0]);
1904 src[1] = ac_to_integer(&ctx->ac, src[1]);
1905 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1906 break;
1907 case nir_op_imul_high:
1908 src[0] = ac_to_integer(&ctx->ac, src[0]);
1909 src[1] = ac_to_integer(&ctx->ac, src[1]);
1910 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1911 break;
1912 case nir_op_pack_half_2x16:
1913 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1914 break;
1915 case nir_op_unpack_half_2x16:
1916 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1917 break;
1918 case nir_op_fddx:
1919 case nir_op_fddy:
1920 case nir_op_fddx_fine:
1921 case nir_op_fddy_fine:
1922 case nir_op_fddx_coarse:
1923 case nir_op_fddy_coarse:
1924 result = emit_ddxy(ctx, instr->op, src[0]);
1925 break;
1926
1927 case nir_op_unpack_64_2x32_split_x: {
1928 assert(instr->src[0].src.ssa->num_components == 1);
1929 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1930 ctx->ac.v2i32,
1931 "");
1932 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1933 ctx->ac.i32_0, "");
1934 break;
1935 }
1936
1937 case nir_op_unpack_64_2x32_split_y: {
1938 assert(instr->src[0].src.ssa->num_components == 1);
1939 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1940 ctx->ac.v2i32,
1941 "");
1942 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1943 ctx->ac.i32_1, "");
1944 break;
1945 }
1946
1947 case nir_op_pack_64_2x32_split: {
1948 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
1949 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1950 src[0], ctx->ac.i32_0, "");
1951 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1952 src[1], ctx->ac.i32_1, "");
1953 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1954 break;
1955 }
1956
1957 default:
1958 fprintf(stderr, "Unknown NIR alu instr: ");
1959 nir_print_instr(&instr->instr, stderr);
1960 fprintf(stderr, "\n");
1961 abort();
1962 }
1963
1964 if (result) {
1965 assert(instr->dest.dest.is_ssa);
1966 result = ac_to_integer(&ctx->ac, result);
1967 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1968 result);
1969 }
1970 }
1971
1972 static void visit_load_const(struct ac_nir_context *ctx,
1973 const nir_load_const_instr *instr)
1974 {
1975 LLVMValueRef values[4], value = NULL;
1976 LLVMTypeRef element_type =
1977 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1978
1979 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1980 switch (instr->def.bit_size) {
1981 case 32:
1982 values[i] = LLVMConstInt(element_type,
1983 instr->value.u32[i], false);
1984 break;
1985 case 64:
1986 values[i] = LLVMConstInt(element_type,
1987 instr->value.u64[i], false);
1988 break;
1989 default:
1990 fprintf(stderr,
1991 "unsupported nir load_const bit_size: %d\n",
1992 instr->def.bit_size);
1993 abort();
1994 }
1995 }
1996 if (instr->def.num_components > 1) {
1997 value = LLVMConstVector(values, instr->def.num_components);
1998 } else
1999 value = values[0];
2000
2001 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2002 }
2003
2004 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2005 LLVMTypeRef type)
2006 {
2007 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2008 return LLVMBuildBitCast(ctx->builder, ptr,
2009 LLVMPointerType(type, addr_space), "");
2010 }
2011
2012 static LLVMValueRef
2013 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2014 {
2015 LLVMValueRef size =
2016 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2017 LLVMConstInt(ctx->ac.i32, 2, false), "");
2018
2019 /* VI only */
2020 if (ctx->ac.chip_class == VI && in_elements) {
2021 /* On VI, the descriptor contains the size in bytes,
2022 * but TXQ must return the size in elements.
2023 * The stride is always non-zero for resources using TXQ.
2024 */
2025 LLVMValueRef stride =
2026 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2027 ctx->ac.i32_1, "");
2028 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2029 LLVMConstInt(ctx->ac.i32, 16, false), "");
2030 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2031 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2032
2033 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2034 }
2035 return size;
2036 }
2037
2038 /**
2039 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2040 * intrinsic names).
2041 */
2042 static void build_int_type_name(
2043 LLVMTypeRef type,
2044 char *buf, unsigned bufsize)
2045 {
2046 assert(bufsize >= 6);
2047
2048 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2049 snprintf(buf, bufsize, "v%ui32",
2050 LLVMGetVectorSize(type));
2051 else
2052 strcpy(buf, "i32");
2053 }
2054
2055 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2056 struct ac_image_args *args,
2057 const nir_tex_instr *instr)
2058 {
2059 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2060 LLVMValueRef coord = args->addr;
2061 LLVMValueRef half_texel[2];
2062 LLVMValueRef compare_cube_wa = NULL;
2063 LLVMValueRef result;
2064 int c;
2065 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2066
2067 //TODO Rect
2068 {
2069 struct ac_image_args txq_args = { 0 };
2070
2071 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2072 txq_args.opcode = ac_image_get_resinfo;
2073 txq_args.dmask = 0xf;
2074 txq_args.addr = ctx->i32_0;
2075 txq_args.resource = args->resource;
2076 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2077
2078 for (c = 0; c < 2; c++) {
2079 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2080 LLVMConstInt(ctx->i32, c, false), "");
2081 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2082 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2083 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2084 LLVMConstReal(ctx->f32, -0.5), "");
2085 }
2086 }
2087
2088 LLVMValueRef orig_coords = args->addr;
2089
2090 for (c = 0; c < 2; c++) {
2091 LLVMValueRef tmp;
2092 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2093 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2094 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2095 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2096 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2097 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2098 }
2099
2100
2101 /*
2102 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2103 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2104 * workaround by sampling using a scaled type and converting.
2105 * This is taken from amdgpu-pro shaders.
2106 */
2107 /* NOTE this produces some ugly code compared to amdgpu-pro,
2108 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2109 * and then reads them back. -pro generates two selects,
2110 * one s_cmp for the descriptor rewriting
2111 * one v_cmp for the coordinate and result changes.
2112 */
2113 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2114 LLVMValueRef tmp, tmp2;
2115
2116 /* workaround 8/8/8/8 uint/sint cube gather bug */
2117 /* first detect it then change to a scaled read and f2i */
2118 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2119 tmp2 = tmp;
2120
2121 /* extract the DATA_FORMAT */
2122 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2123 LLVMConstInt(ctx->i32, 6, false), false);
2124
2125 /* is the DATA_FORMAT == 8_8_8_8 */
2126 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2127
2128 if (stype == GLSL_TYPE_UINT)
2129 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2130 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2131 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2132 else
2133 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2134 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2135 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2136
2137 /* replace the NUM FORMAT in the descriptor */
2138 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2139 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2140
2141 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2142
2143 /* don't modify the coordinates for this case */
2144 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2145 }
2146 args->addr = coord;
2147 result = ac_build_image_opcode(ctx, args);
2148
2149 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2150 LLVMValueRef tmp, tmp2;
2151
2152 /* if the cube workaround is in place, f2i the result. */
2153 for (c = 0; c < 4; c++) {
2154 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2155 if (stype == GLSL_TYPE_UINT)
2156 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2157 else
2158 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2159 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2160 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2161 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2162 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2163 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2164 }
2165 }
2166 return result;
2167 }
2168
2169 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2170 const nir_tex_instr *instr,
2171 bool lod_is_zero,
2172 struct ac_image_args *args)
2173 {
2174 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2175 return ac_build_buffer_load_format(&ctx->ac,
2176 args->resource,
2177 args->addr,
2178 ctx->ac.i32_0,
2179 true);
2180 }
2181
2182 args->opcode = ac_image_sample;
2183 args->compare = instr->is_shadow;
2184
2185 switch (instr->op) {
2186 case nir_texop_txf:
2187 case nir_texop_txf_ms:
2188 case nir_texop_samples_identical:
2189 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2190 args->compare = false;
2191 args->offset = false;
2192 break;
2193 case nir_texop_txb:
2194 args->bias = true;
2195 break;
2196 case nir_texop_txl:
2197 if (lod_is_zero)
2198 args->level_zero = true;
2199 else
2200 args->lod = true;
2201 break;
2202 case nir_texop_txs:
2203 case nir_texop_query_levels:
2204 args->opcode = ac_image_get_resinfo;
2205 break;
2206 case nir_texop_tex:
2207 if (ctx->stage != MESA_SHADER_FRAGMENT)
2208 args->level_zero = true;
2209 break;
2210 case nir_texop_txd:
2211 args->deriv = true;
2212 break;
2213 case nir_texop_tg4:
2214 args->opcode = ac_image_gather4;
2215 args->level_zero = true;
2216 break;
2217 case nir_texop_lod:
2218 args->opcode = ac_image_get_lod;
2219 args->compare = false;
2220 args->offset = false;
2221 break;
2222 default:
2223 break;
2224 }
2225
2226 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2227 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2228 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2229 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2230 }
2231 }
2232 return ac_build_image_opcode(&ctx->ac, args);
2233 }
2234
2235 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2236 nir_intrinsic_instr *instr)
2237 {
2238 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2239 unsigned desc_set = nir_intrinsic_desc_set(instr);
2240 unsigned binding = nir_intrinsic_binding(instr);
2241 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2242 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2243 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2244 unsigned base_offset = layout->binding[binding].offset;
2245 LLVMValueRef offset, stride;
2246
2247 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2248 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2249 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2250 layout->binding[binding].dynamic_offset_offset;
2251 desc_ptr = ctx->push_constants;
2252 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2253 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2254 } else
2255 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2256
2257 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2258 index = LLVMBuildMul(ctx->builder, index, stride, "");
2259 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2260
2261 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2262 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2263 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2264
2265 return desc_ptr;
2266 }
2267
2268 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2269 nir_intrinsic_instr *instr)
2270 {
2271 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2272 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2273
2274 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2275 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2276 return result;
2277 }
2278
2279 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2280 nir_intrinsic_instr *instr)
2281 {
2282 LLVMValueRef ptr, addr;
2283
2284 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2285 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2286
2287 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2288 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2289
2290 return LLVMBuildLoad(ctx->builder, ptr, "");
2291 }
2292
2293 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2294 const nir_intrinsic_instr *instr)
2295 {
2296 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2297
2298 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2299 }
2300 static void visit_store_ssbo(struct ac_nir_context *ctx,
2301 nir_intrinsic_instr *instr)
2302 {
2303 const char *store_name;
2304 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2305 LLVMTypeRef data_type = ctx->ac.f32;
2306 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2307 int components_32bit = elem_size_mult * instr->num_components;
2308 unsigned writemask = nir_intrinsic_write_mask(instr);
2309 LLVMValueRef base_data, base_offset;
2310 LLVMValueRef params[6];
2311
2312 params[1] = ctx->abi->load_ssbo(ctx->abi,
2313 get_src(ctx, instr->src[1]), true);
2314 params[2] = ctx->ac.i32_0; /* vindex */
2315 params[4] = ctx->ac.i1false; /* glc */
2316 params[5] = ctx->ac.i1false; /* slc */
2317
2318 if (components_32bit > 1)
2319 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2320
2321 base_data = ac_to_float(&ctx->ac, src_data);
2322 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2323 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2324 data_type, "");
2325 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2326 while (writemask) {
2327 int start, count;
2328 LLVMValueRef data;
2329 LLVMValueRef offset;
2330 LLVMValueRef tmp;
2331 u_bit_scan_consecutive_range(&writemask, &start, &count);
2332
2333 /* Due to an LLVM limitation, split 3-element writes
2334 * into a 2-element and a 1-element write. */
2335 if (count == 3) {
2336 writemask |= 1 << (start + 2);
2337 count = 2;
2338 }
2339
2340 start *= elem_size_mult;
2341 count *= elem_size_mult;
2342
2343 if (count > 4) {
2344 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2345 count = 4;
2346 }
2347
2348 if (count == 4) {
2349 store_name = "llvm.amdgcn.buffer.store.v4f32";
2350 data = base_data;
2351 } else if (count == 2) {
2352 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2353 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2354 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2355 ctx->ac.i32_0, "");
2356
2357 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2358 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2359 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2360 ctx->ac.i32_1, "");
2361 store_name = "llvm.amdgcn.buffer.store.v2f32";
2362
2363 } else {
2364 assert(count == 1);
2365 if (get_llvm_num_components(base_data) > 1)
2366 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2367 LLVMConstInt(ctx->ac.i32, start, false), "");
2368 else
2369 data = base_data;
2370 store_name = "llvm.amdgcn.buffer.store.f32";
2371 }
2372
2373 offset = base_offset;
2374 if (start != 0) {
2375 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2376 }
2377 params[0] = data;
2378 params[3] = offset;
2379 ac_build_intrinsic(&ctx->ac, store_name,
2380 ctx->ac.voidt, params, 6, 0);
2381 }
2382 }
2383
2384 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2385 const nir_intrinsic_instr *instr)
2386 {
2387 const char *name;
2388 LLVMValueRef params[6];
2389 int arg_count = 0;
2390
2391 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2392 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2393 }
2394 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2395 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2396 get_src(ctx, instr->src[0]),
2397 true);
2398 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2399 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2400 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2401
2402 switch (instr->intrinsic) {
2403 case nir_intrinsic_ssbo_atomic_add:
2404 name = "llvm.amdgcn.buffer.atomic.add";
2405 break;
2406 case nir_intrinsic_ssbo_atomic_imin:
2407 name = "llvm.amdgcn.buffer.atomic.smin";
2408 break;
2409 case nir_intrinsic_ssbo_atomic_umin:
2410 name = "llvm.amdgcn.buffer.atomic.umin";
2411 break;
2412 case nir_intrinsic_ssbo_atomic_imax:
2413 name = "llvm.amdgcn.buffer.atomic.smax";
2414 break;
2415 case nir_intrinsic_ssbo_atomic_umax:
2416 name = "llvm.amdgcn.buffer.atomic.umax";
2417 break;
2418 case nir_intrinsic_ssbo_atomic_and:
2419 name = "llvm.amdgcn.buffer.atomic.and";
2420 break;
2421 case nir_intrinsic_ssbo_atomic_or:
2422 name = "llvm.amdgcn.buffer.atomic.or";
2423 break;
2424 case nir_intrinsic_ssbo_atomic_xor:
2425 name = "llvm.amdgcn.buffer.atomic.xor";
2426 break;
2427 case nir_intrinsic_ssbo_atomic_exchange:
2428 name = "llvm.amdgcn.buffer.atomic.swap";
2429 break;
2430 case nir_intrinsic_ssbo_atomic_comp_swap:
2431 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2432 break;
2433 default:
2434 abort();
2435 }
2436
2437 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2438 }
2439
2440 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2441 const nir_intrinsic_instr *instr)
2442 {
2443 LLVMValueRef results[2];
2444 int load_components;
2445 int num_components = instr->num_components;
2446 if (instr->dest.ssa.bit_size == 64)
2447 num_components *= 2;
2448
2449 for (int i = 0; i < num_components; i += load_components) {
2450 load_components = MIN2(num_components - i, 4);
2451 const char *load_name;
2452 LLVMTypeRef data_type = ctx->ac.f32;
2453 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2454 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2455
2456 if (load_components == 3)
2457 data_type = LLVMVectorType(ctx->ac.f32, 4);
2458 else if (load_components > 1)
2459 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2460
2461 if (load_components >= 3)
2462 load_name = "llvm.amdgcn.buffer.load.v4f32";
2463 else if (load_components == 2)
2464 load_name = "llvm.amdgcn.buffer.load.v2f32";
2465 else if (load_components == 1)
2466 load_name = "llvm.amdgcn.buffer.load.f32";
2467 else
2468 unreachable("unhandled number of components");
2469
2470 LLVMValueRef params[] = {
2471 ctx->abi->load_ssbo(ctx->abi,
2472 get_src(ctx, instr->src[0]),
2473 false),
2474 ctx->ac.i32_0,
2475 offset,
2476 ctx->ac.i1false,
2477 ctx->ac.i1false,
2478 };
2479
2480 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2481
2482 }
2483
2484 assume(results[0]);
2485 LLVMValueRef ret = results[0];
2486 if (num_components > 4 || num_components == 3) {
2487 LLVMValueRef masks[] = {
2488 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2489 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2490 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2491 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2492 };
2493
2494 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2495 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2496 results[num_components > 4 ? 1 : 0], swizzle, "");
2497 }
2498
2499 return LLVMBuildBitCast(ctx->ac.builder, ret,
2500 get_def_type(ctx, &instr->dest.ssa), "");
2501 }
2502
2503 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2504 const nir_intrinsic_instr *instr)
2505 {
2506 LLVMValueRef results[8], ret;
2507 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2508 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2509 int num_components = instr->num_components;
2510
2511 if (ctx->abi->load_ubo)
2512 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2513
2514 if (instr->dest.ssa.bit_size == 64)
2515 num_components *= 2;
2516
2517 for (unsigned i = 0; i < num_components; ++i) {
2518 LLVMValueRef params[] = {
2519 rsrc,
2520 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2521 offset, "")
2522 };
2523 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2524 params, 2,
2525 AC_FUNC_ATTR_READNONE |
2526 AC_FUNC_ATTR_LEGACY);
2527 }
2528
2529
2530 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2531 return LLVMBuildBitCast(ctx->ac.builder, ret,
2532 get_def_type(ctx, &instr->dest.ssa), "");
2533 }
2534
2535 static void
2536 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2537 bool vs_in, unsigned *vertex_index_out,
2538 LLVMValueRef *vertex_index_ref,
2539 unsigned *const_out, LLVMValueRef *indir_out)
2540 {
2541 unsigned const_offset = 0;
2542 nir_deref *tail = &deref->deref;
2543 LLVMValueRef offset = NULL;
2544
2545 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2546 tail = tail->child;
2547 nir_deref_array *deref_array = nir_deref_as_array(tail);
2548 if (vertex_index_out)
2549 *vertex_index_out = deref_array->base_offset;
2550
2551 if (vertex_index_ref) {
2552 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2553 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2554 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2555 }
2556 *vertex_index_ref = vtx;
2557 }
2558 }
2559
2560 if (deref->var->data.compact) {
2561 assert(tail->child->deref_type == nir_deref_type_array);
2562 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2563 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2564 /* We always lower indirect dereferences for "compact" array vars. */
2565 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2566
2567 const_offset = deref_array->base_offset;
2568 goto out;
2569 }
2570
2571 while (tail->child != NULL) {
2572 const struct glsl_type *parent_type = tail->type;
2573 tail = tail->child;
2574
2575 if (tail->deref_type == nir_deref_type_array) {
2576 nir_deref_array *deref_array = nir_deref_as_array(tail);
2577 LLVMValueRef index, stride, local_offset;
2578 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2579
2580 const_offset += size * deref_array->base_offset;
2581 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2582 continue;
2583
2584 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2585 index = get_src(ctx, deref_array->indirect);
2586 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2587 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2588
2589 if (offset)
2590 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2591 else
2592 offset = local_offset;
2593 } else if (tail->deref_type == nir_deref_type_struct) {
2594 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2595
2596 for (unsigned i = 0; i < deref_struct->index; i++) {
2597 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2598 const_offset += glsl_count_attribute_slots(ft, vs_in);
2599 }
2600 } else
2601 unreachable("unsupported deref type");
2602
2603 }
2604 out:
2605 if (const_offset && offset)
2606 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2607 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2608 "");
2609
2610 *const_out = const_offset;
2611 *indir_out = offset;
2612 }
2613
2614
2615 /* The offchip buffer layout for TCS->TES is
2616 *
2617 * - attribute 0 of patch 0 vertex 0
2618 * - attribute 0 of patch 0 vertex 1
2619 * - attribute 0 of patch 0 vertex 2
2620 * ...
2621 * - attribute 0 of patch 1 vertex 0
2622 * - attribute 0 of patch 1 vertex 1
2623 * ...
2624 * - attribute 1 of patch 0 vertex 0
2625 * - attribute 1 of patch 0 vertex 1
2626 * ...
2627 * - per patch attribute 0 of patch 0
2628 * - per patch attribute 0 of patch 1
2629 * ...
2630 *
2631 * Note that every attribute has 4 components.
2632 */
2633 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2634 LLVMValueRef vertex_index,
2635 LLVMValueRef param_index)
2636 {
2637 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2638 LLVMValueRef param_stride, constant16;
2639 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2640
2641 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2642 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2643 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2644 num_patches, "");
2645
2646 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2647 if (vertex_index) {
2648 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2649 vertices_per_patch, "");
2650
2651 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2652 vertex_index, "");
2653
2654 param_stride = total_vertices;
2655 } else {
2656 base_addr = rel_patch_id;
2657 param_stride = num_patches;
2658 }
2659
2660 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2661 LLVMBuildMul(ctx->builder, param_index,
2662 param_stride, ""), "");
2663
2664 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2665
2666 if (!vertex_index) {
2667 LLVMValueRef patch_data_offset =
2668 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2669
2670 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2671 patch_data_offset, "");
2672 }
2673 return base_addr;
2674 }
2675
2676 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2677 unsigned param,
2678 unsigned const_index,
2679 bool is_compact,
2680 LLVMValueRef vertex_index,
2681 LLVMValueRef indir_index)
2682 {
2683 LLVMValueRef param_index;
2684
2685 if (indir_index)
2686 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2687 indir_index, "");
2688 else {
2689 if (const_index && !is_compact)
2690 param += const_index;
2691 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2692 }
2693 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2694 }
2695
2696 static void
2697 mark_tess_output(struct nir_to_llvm_context *ctx,
2698 bool is_patch, uint32_t param)
2699
2700 {
2701 if (is_patch) {
2702 ctx->tess_patch_outputs_written |= (1ull << param);
2703 } else
2704 ctx->tess_outputs_written |= (1ull << param);
2705 }
2706
2707 static LLVMValueRef
2708 get_dw_address(struct nir_to_llvm_context *ctx,
2709 LLVMValueRef dw_addr,
2710 unsigned param,
2711 unsigned const_index,
2712 bool compact_const_index,
2713 LLVMValueRef vertex_index,
2714 LLVMValueRef stride,
2715 LLVMValueRef indir_index)
2716
2717 {
2718
2719 if (vertex_index) {
2720 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2721 LLVMBuildMul(ctx->builder,
2722 vertex_index,
2723 stride, ""), "");
2724 }
2725
2726 if (indir_index)
2727 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2728 LLVMBuildMul(ctx->builder, indir_index,
2729 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2730 else if (const_index && !compact_const_index)
2731 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2732 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2733
2734 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2735 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2736
2737 if (const_index && compact_const_index)
2738 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2739 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2740 return dw_addr;
2741 }
2742
2743 static LLVMValueRef
2744 load_tcs_input(struct nir_to_llvm_context *ctx,
2745 nir_intrinsic_instr *instr)
2746 {
2747 LLVMValueRef dw_addr, stride;
2748 unsigned const_index;
2749 LLVMValueRef vertex_index;
2750 LLVMValueRef indir_index;
2751 unsigned param;
2752 LLVMValueRef value[4], result;
2753 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2754 const bool is_compact = instr->variables[0]->var->data.compact;
2755 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2756 get_deref_offset(ctx->nir, instr->variables[0],
2757 false, NULL, per_vertex ? &vertex_index : NULL,
2758 &const_index, &indir_index);
2759
2760 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2761 dw_addr = get_tcs_in_current_patch_offset(ctx);
2762 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2763 indir_index);
2764
2765 unsigned comp = instr->variables[0]->var->data.location_frac;
2766 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2767 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2768 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2769 ctx->ac.i32_1, "");
2770 }
2771 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2772 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2773 return result;
2774 }
2775
2776 static LLVMValueRef
2777 load_tcs_output(struct nir_to_llvm_context *ctx,
2778 nir_intrinsic_instr *instr)
2779 {
2780 LLVMValueRef dw_addr;
2781 LLVMValueRef stride = NULL;
2782 LLVMValueRef value[4], result;
2783 LLVMValueRef vertex_index = NULL;
2784 LLVMValueRef indir_index = NULL;
2785 unsigned const_index = 0;
2786 unsigned param;
2787 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2788 const bool is_compact = instr->variables[0]->var->data.compact;
2789 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2790 get_deref_offset(ctx->nir, instr->variables[0],
2791 false, NULL, per_vertex ? &vertex_index : NULL,
2792 &const_index, &indir_index);
2793
2794 if (!instr->variables[0]->var->data.patch) {
2795 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2796 dw_addr = get_tcs_out_current_patch_offset(ctx);
2797 } else {
2798 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2799 }
2800
2801 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2802 indir_index);
2803
2804 unsigned comp = instr->variables[0]->var->data.location_frac;
2805 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2806 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2807 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2808 ctx->ac.i32_1, "");
2809 }
2810 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2811 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2812 return result;
2813 }
2814
2815 static void
2816 store_tcs_output(struct nir_to_llvm_context *ctx,
2817 nir_intrinsic_instr *instr,
2818 LLVMValueRef src,
2819 unsigned writemask)
2820 {
2821 LLVMValueRef dw_addr;
2822 LLVMValueRef stride = NULL;
2823 LLVMValueRef buf_addr = NULL;
2824 LLVMValueRef vertex_index = NULL;
2825 LLVMValueRef indir_index = NULL;
2826 unsigned const_index = 0;
2827 unsigned param;
2828 const unsigned comp = instr->variables[0]->var->data.location_frac;
2829 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2830 const bool is_compact = instr->variables[0]->var->data.compact;
2831 bool store_lds = true;
2832
2833 if (instr->variables[0]->var->data.patch) {
2834 if (!(ctx->tcs_patch_outputs_read & (1U << (instr->variables[0]->var->data.location - VARYING_SLOT_PATCH0))))
2835 store_lds = false;
2836 } else {
2837 if (!(ctx->tcs_outputs_read & (1ULL << instr->variables[0]->var->data.location)))
2838 store_lds = false;
2839 }
2840 get_deref_offset(ctx->nir, instr->variables[0],
2841 false, NULL, per_vertex ? &vertex_index : NULL,
2842 &const_index, &indir_index);
2843
2844 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2845 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2846 is_compact && const_index > 3) {
2847 const_index -= 3;
2848 param++;
2849 }
2850
2851 if (!instr->variables[0]->var->data.patch) {
2852 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2853 dw_addr = get_tcs_out_current_patch_offset(ctx);
2854 } else {
2855 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2856 }
2857
2858 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2859
2860 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2861 indir_index);
2862 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2863 vertex_index, indir_index);
2864
2865 bool is_tess_factor = false;
2866 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2867 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2868 is_tess_factor = true;
2869
2870 unsigned base = is_compact ? const_index : 0;
2871 for (unsigned chan = 0; chan < 8; chan++) {
2872 if (!(writemask & (1 << chan)))
2873 continue;
2874 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2875
2876 if (store_lds || is_tess_factor)
2877 ac_lds_store(&ctx->ac, dw_addr, value);
2878
2879 if (!is_tess_factor && writemask != 0xF)
2880 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2881 buf_addr, ctx->oc_lds,
2882 4 * (base + chan), 1, 0, true, false);
2883
2884 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2885 ctx->ac.i32_1, "");
2886 }
2887
2888 if (writemask == 0xF) {
2889 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2890 buf_addr, ctx->oc_lds,
2891 (base * 4), 1, 0, true, false);
2892 }
2893 }
2894
2895 static LLVMValueRef
2896 load_tes_input(struct nir_to_llvm_context *ctx,
2897 const nir_intrinsic_instr *instr)
2898 {
2899 LLVMValueRef buf_addr;
2900 LLVMValueRef result;
2901 LLVMValueRef vertex_index = NULL;
2902 LLVMValueRef indir_index = NULL;
2903 unsigned const_index = 0;
2904 unsigned param;
2905 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2906 const bool is_compact = instr->variables[0]->var->data.compact;
2907
2908 get_deref_offset(ctx->nir, instr->variables[0],
2909 false, NULL, per_vertex ? &vertex_index : NULL,
2910 &const_index, &indir_index);
2911 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2912 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2913 is_compact && const_index > 3) {
2914 const_index -= 3;
2915 param++;
2916 }
2917
2918 unsigned comp = instr->variables[0]->var->data.location_frac;
2919 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2920 is_compact, vertex_index, indir_index);
2921
2922 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, comp * 4, false);
2923 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2924
2925 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2926 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2927 result = trim_vector(&ctx->ac, result, instr->num_components);
2928 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2929 return result;
2930 }
2931
2932 static LLVMValueRef
2933 load_gs_input(struct ac_shader_abi *abi,
2934 unsigned location,
2935 unsigned driver_location,
2936 unsigned component,
2937 unsigned num_components,
2938 unsigned vertex_index,
2939 unsigned const_index,
2940 LLVMTypeRef type)
2941 {
2942 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2943 LLVMValueRef vtx_offset;
2944 LLVMValueRef args[9];
2945 unsigned param, vtx_offset_param;
2946 LLVMValueRef value[4], result;
2947
2948 vtx_offset_param = vertex_index;
2949 assert(vtx_offset_param < 6);
2950 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2951 LLVMConstInt(ctx->ac.i32, 4, false), "");
2952
2953 param = shader_io_get_unique_index(location);
2954
2955 for (unsigned i = component; i < num_components + component; i++) {
2956 if (ctx->ac.chip_class >= GFX9) {
2957 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
2958 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2959 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
2960 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2961 } else {
2962 args[0] = ctx->esgs_ring;
2963 args[1] = vtx_offset;
2964 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
2965 args[3] = ctx->ac.i32_0;
2966 args[4] = ctx->ac.i32_1; /* OFFEN */
2967 args[5] = ctx->ac.i32_0; /* IDXEN */
2968 args[6] = ctx->ac.i32_1; /* GLC */
2969 args[7] = ctx->ac.i32_0; /* SLC */
2970 args[8] = ctx->ac.i32_0; /* TFE */
2971
2972 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2973 ctx->ac.i32, args, 9,
2974 AC_FUNC_ATTR_READONLY |
2975 AC_FUNC_ATTR_LEGACY);
2976 }
2977 }
2978 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2979
2980 return result;
2981 }
2982
2983 static LLVMValueRef
2984 build_gep_for_deref(struct ac_nir_context *ctx,
2985 nir_deref_var *deref)
2986 {
2987 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2988 assert(entry->data);
2989 LLVMValueRef val = entry->data;
2990 nir_deref *tail = deref->deref.child;
2991 while (tail != NULL) {
2992 LLVMValueRef offset;
2993 switch (tail->deref_type) {
2994 case nir_deref_type_array: {
2995 nir_deref_array *array = nir_deref_as_array(tail);
2996 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2997 if (array->deref_array_type ==
2998 nir_deref_array_type_indirect) {
2999 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3000 get_src(ctx,
3001 array->indirect),
3002 "");
3003 }
3004 break;
3005 }
3006 case nir_deref_type_struct: {
3007 nir_deref_struct *deref_struct =
3008 nir_deref_as_struct(tail);
3009 offset = LLVMConstInt(ctx->ac.i32,
3010 deref_struct->index, 0);
3011 break;
3012 }
3013 default:
3014 unreachable("bad deref type");
3015 }
3016 val = ac_build_gep0(&ctx->ac, val, offset);
3017 tail = tail->child;
3018 }
3019 return val;
3020 }
3021
3022 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3023 nir_intrinsic_instr *instr)
3024 {
3025 LLVMValueRef values[8];
3026 int idx = instr->variables[0]->var->data.driver_location;
3027 int ve = instr->dest.ssa.num_components;
3028 unsigned comp = instr->variables[0]->var->data.location_frac;
3029 LLVMValueRef indir_index;
3030 LLVMValueRef ret;
3031 unsigned const_index;
3032 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3033 instr->variables[0]->var->data.mode == nir_var_shader_in;
3034 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3035 &const_index, &indir_index);
3036
3037 if (instr->dest.ssa.bit_size == 64)
3038 ve *= 2;
3039
3040 switch (instr->variables[0]->var->data.mode) {
3041 case nir_var_shader_in:
3042 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3043 return load_tcs_input(ctx->nctx, instr);
3044 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3045 return load_tes_input(ctx->nctx, instr);
3046 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3047 LLVMValueRef indir_index;
3048 unsigned const_index, vertex_index;
3049 get_deref_offset(ctx, instr->variables[0],
3050 false, &vertex_index, NULL,
3051 &const_index, &indir_index);
3052 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3053 instr->variables[0]->var->data.driver_location,
3054 instr->variables[0]->var->data.location_frac, ve,
3055 vertex_index, const_index,
3056 nir2llvmtype(ctx, instr->variables[0]->var->type));
3057 }
3058
3059 for (unsigned chan = comp; chan < ve + comp; chan++) {
3060 if (indir_index) {
3061 unsigned count = glsl_count_attribute_slots(
3062 instr->variables[0]->var->type,
3063 ctx->stage == MESA_SHADER_VERTEX);
3064 count -= chan / 4;
3065 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3066 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3067 4, false, true);
3068
3069 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3070 tmp_vec,
3071 indir_index, "");
3072 } else
3073 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3074 }
3075 break;
3076 case nir_var_local:
3077 for (unsigned chan = 0; chan < ve; chan++) {
3078 if (indir_index) {
3079 unsigned count = glsl_count_attribute_slots(
3080 instr->variables[0]->var->type, false);
3081 count -= chan / 4;
3082 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3083 &ctx->ac, ctx->locals + idx + chan, count,
3084 4, true, true);
3085
3086 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3087 tmp_vec,
3088 indir_index, "");
3089 } else {
3090 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3091 }
3092 }
3093 break;
3094 case nir_var_shared: {
3095 LLVMValueRef address = build_gep_for_deref(ctx,
3096 instr->variables[0]);
3097 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3098 return LLVMBuildBitCast(ctx->ac.builder, val,
3099 get_def_type(ctx, &instr->dest.ssa),
3100 "");
3101 }
3102 case nir_var_shader_out:
3103 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3104 return load_tcs_output(ctx->nctx, instr);
3105
3106 for (unsigned chan = comp; chan < ve + comp; chan++) {
3107 if (indir_index) {
3108 unsigned count = glsl_count_attribute_slots(
3109 instr->variables[0]->var->type, false);
3110 count -= chan / 4;
3111 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3112 &ctx->ac, ctx->outputs + idx + chan, count,
3113 4, true, true);
3114
3115 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3116 tmp_vec,
3117 indir_index, "");
3118 } else {
3119 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3120 ctx->outputs[idx + chan + const_index * 4],
3121 "");
3122 }
3123 }
3124 break;
3125 default:
3126 unreachable("unhandle variable mode");
3127 }
3128 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3129 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3130 }
3131
3132 static void
3133 visit_store_var(struct ac_nir_context *ctx,
3134 nir_intrinsic_instr *instr)
3135 {
3136 LLVMValueRef temp_ptr, value;
3137 int idx = instr->variables[0]->var->data.driver_location;
3138 unsigned comp = instr->variables[0]->var->data.location_frac;
3139 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3140 int writemask = instr->const_index[0] << comp;
3141 LLVMValueRef indir_index;
3142 unsigned const_index;
3143 get_deref_offset(ctx, instr->variables[0], false,
3144 NULL, NULL, &const_index, &indir_index);
3145
3146 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3147 int old_writemask = writemask;
3148
3149 src = LLVMBuildBitCast(ctx->ac.builder, src,
3150 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3151 "");
3152
3153 writemask = 0;
3154 for (unsigned chan = 0; chan < 4; chan++) {
3155 if (old_writemask & (1 << chan))
3156 writemask |= 3u << (2 * chan);
3157 }
3158 }
3159
3160 switch (instr->variables[0]->var->data.mode) {
3161 case nir_var_shader_out:
3162
3163 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3164 store_tcs_output(ctx->nctx, instr, src, writemask);
3165 return;
3166 }
3167
3168 for (unsigned chan = 0; chan < 8; chan++) {
3169 int stride = 4;
3170 if (!(writemask & (1 << chan)))
3171 continue;
3172
3173 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3174
3175 if (instr->variables[0]->var->data.compact)
3176 stride = 1;
3177 if (indir_index) {
3178 unsigned count = glsl_count_attribute_slots(
3179 instr->variables[0]->var->type, false);
3180 count -= chan / 4;
3181 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3182 &ctx->ac, ctx->outputs + idx + chan, count,
3183 stride, true, true);
3184
3185 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3186 value, indir_index, "");
3187 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3188 count, stride, tmp_vec);
3189
3190 } else {
3191 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3192
3193 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3194 }
3195 }
3196 break;
3197 case nir_var_local:
3198 for (unsigned chan = 0; chan < 8; chan++) {
3199 if (!(writemask & (1 << chan)))
3200 continue;
3201
3202 value = llvm_extract_elem(&ctx->ac, src, chan);
3203 if (indir_index) {
3204 unsigned count = glsl_count_attribute_slots(
3205 instr->variables[0]->var->type, false);
3206 count -= chan / 4;
3207 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3208 &ctx->ac, ctx->locals + idx + chan, count,
3209 4, true, true);
3210
3211 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3212 value, indir_index, "");
3213 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3214 count, 4, tmp_vec);
3215 } else {
3216 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3217
3218 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3219 }
3220 }
3221 break;
3222 case nir_var_shared: {
3223 int writemask = instr->const_index[0];
3224 LLVMValueRef address = build_gep_for_deref(ctx,
3225 instr->variables[0]);
3226 LLVMValueRef val = get_src(ctx, instr->src[0]);
3227 unsigned components =
3228 glsl_get_vector_elements(
3229 nir_deref_tail(&instr->variables[0]->deref)->type);
3230 if (writemask == (1 << components) - 1) {
3231 val = LLVMBuildBitCast(
3232 ctx->ac.builder, val,
3233 LLVMGetElementType(LLVMTypeOf(address)), "");
3234 LLVMBuildStore(ctx->ac.builder, val, address);
3235 } else {
3236 for (unsigned chan = 0; chan < 4; chan++) {
3237 if (!(writemask & (1 << chan)))
3238 continue;
3239 LLVMValueRef ptr =
3240 LLVMBuildStructGEP(ctx->ac.builder,
3241 address, chan, "");
3242 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3243 chan);
3244 src = LLVMBuildBitCast(
3245 ctx->ac.builder, src,
3246 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3247 LLVMBuildStore(ctx->ac.builder, src, ptr);
3248 }
3249 }
3250 break;
3251 }
3252 default:
3253 break;
3254 }
3255 }
3256
3257 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3258 {
3259 switch (dim) {
3260 case GLSL_SAMPLER_DIM_BUF:
3261 return 1;
3262 case GLSL_SAMPLER_DIM_1D:
3263 return array ? 2 : 1;
3264 case GLSL_SAMPLER_DIM_2D:
3265 return array ? 3 : 2;
3266 case GLSL_SAMPLER_DIM_MS:
3267 return array ? 4 : 3;
3268 case GLSL_SAMPLER_DIM_3D:
3269 case GLSL_SAMPLER_DIM_CUBE:
3270 return 3;
3271 case GLSL_SAMPLER_DIM_RECT:
3272 case GLSL_SAMPLER_DIM_SUBPASS:
3273 return 2;
3274 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3275 return 3;
3276 default:
3277 break;
3278 }
3279 return 0;
3280 }
3281
3282
3283
3284 /* Adjust the sample index according to FMASK.
3285 *
3286 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3287 * which is the identity mapping. Each nibble says which physical sample
3288 * should be fetched to get that sample.
3289 *
3290 * For example, 0x11111100 means there are only 2 samples stored and
3291 * the second sample covers 3/4 of the pixel. When reading samples 0
3292 * and 1, return physical sample 0 (determined by the first two 0s
3293 * in FMASK), otherwise return physical sample 1.
3294 *
3295 * The sample index should be adjusted as follows:
3296 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3297 */
3298 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3299 LLVMValueRef coord_x, LLVMValueRef coord_y,
3300 LLVMValueRef coord_z,
3301 LLVMValueRef sample_index,
3302 LLVMValueRef fmask_desc_ptr)
3303 {
3304 LLVMValueRef fmask_load_address[4];
3305 LLVMValueRef res;
3306
3307 fmask_load_address[0] = coord_x;
3308 fmask_load_address[1] = coord_y;
3309 if (coord_z) {
3310 fmask_load_address[2] = coord_z;
3311 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3312 }
3313
3314 struct ac_image_args args = {0};
3315
3316 args.opcode = ac_image_load;
3317 args.da = coord_z ? true : false;
3318 args.resource = fmask_desc_ptr;
3319 args.dmask = 0xf;
3320 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3321
3322 res = ac_build_image_opcode(ctx, &args);
3323
3324 res = ac_to_integer(ctx, res);
3325 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3326 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3327
3328 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3329 res,
3330 ctx->i32_0, "");
3331
3332 LLVMValueRef sample_index4 =
3333 LLVMBuildMul(ctx->builder, sample_index, four, "");
3334 LLVMValueRef shifted_fmask =
3335 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3336 LLVMValueRef final_sample =
3337 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3338
3339 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3340 * resource descriptor is 0 (invalid),
3341 */
3342 LLVMValueRef fmask_desc =
3343 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3344 ctx->v8i32, "");
3345
3346 LLVMValueRef fmask_word1 =
3347 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3348 ctx->i32_1, "");
3349
3350 LLVMValueRef word1_is_nonzero =
3351 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3352 fmask_word1, ctx->i32_0, "");
3353
3354 /* Replace the MSAA sample index. */
3355 sample_index =
3356 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3357 final_sample, sample_index, "");
3358 return sample_index;
3359 }
3360
3361 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3362 const nir_intrinsic_instr *instr)
3363 {
3364 const struct glsl_type *type = instr->variables[0]->var->type;
3365 if(instr->variables[0]->deref.child)
3366 type = instr->variables[0]->deref.child->type;
3367
3368 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3369 LLVMValueRef coords[4];
3370 LLVMValueRef masks[] = {
3371 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3372 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3373 };
3374 LLVMValueRef res;
3375 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3376
3377 int count;
3378 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3379 bool is_array = glsl_sampler_type_is_array(type);
3380 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3381 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3382 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3383 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3384 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3385 count = image_type_to_components_count(dim, is_array);
3386
3387 if (is_ms) {
3388 LLVMValueRef fmask_load_address[3];
3389 int chan;
3390
3391 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3392 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3393 if (is_array)
3394 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3395 else
3396 fmask_load_address[2] = NULL;
3397 if (add_frag_pos) {
3398 for (chan = 0; chan < 2; ++chan)
3399 fmask_load_address[chan] =
3400 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3401 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3402 ctx->ac.i32, ""), "");
3403 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3404 }
3405 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3406 fmask_load_address[0],
3407 fmask_load_address[1],
3408 fmask_load_address[2],
3409 sample_index,
3410 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3411 }
3412 if (count == 1 && !gfx9_1d) {
3413 if (instr->src[0].ssa->num_components)
3414 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3415 else
3416 res = src0;
3417 } else {
3418 int chan;
3419 if (is_ms)
3420 count--;
3421 for (chan = 0; chan < count; ++chan) {
3422 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3423 }
3424 if (add_frag_pos) {
3425 for (chan = 0; chan < 2; ++chan)
3426 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3427 ctx->ac.i32, ""), "");
3428 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3429 count++;
3430 }
3431
3432 if (gfx9_1d) {
3433 if (is_array) {
3434 coords[2] = coords[1];
3435 coords[1] = ctx->ac.i32_0;
3436 } else
3437 coords[1] = ctx->ac.i32_0;
3438 count++;
3439 }
3440
3441 if (is_ms) {
3442 coords[count] = sample_index;
3443 count++;
3444 }
3445
3446 if (count == 3) {
3447 coords[3] = LLVMGetUndef(ctx->ac.i32);
3448 count = 4;
3449 }
3450 res = ac_build_gather_values(&ctx->ac, coords, count);
3451 }
3452 return res;
3453 }
3454
3455 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3456 const nir_intrinsic_instr *instr)
3457 {
3458 LLVMValueRef params[7];
3459 LLVMValueRef res;
3460 char intrinsic_name[64];
3461 const nir_variable *var = instr->variables[0]->var;
3462 const struct glsl_type *type = var->type;
3463
3464 if(instr->variables[0]->deref.child)
3465 type = instr->variables[0]->deref.child->type;
3466
3467 type = glsl_without_array(type);
3468 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3469 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3470 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3471 ctx->ac.i32_0, ""); /* vindex */
3472 params[2] = ctx->ac.i32_0; /* voffset */
3473 params[3] = ctx->ac.i1false; /* glc */
3474 params[4] = ctx->ac.i1false; /* slc */
3475 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3476 params, 5, 0);
3477
3478 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3479 res = ac_to_integer(&ctx->ac, res);
3480 } else {
3481 bool is_da = glsl_sampler_type_is_array(type) ||
3482 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3483 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3484 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3485 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3486 LLVMValueRef glc = ctx->ac.i1false;
3487 LLVMValueRef slc = ctx->ac.i1false;
3488
3489 params[0] = get_image_coords(ctx, instr);
3490 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3491 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3492 if (HAVE_LLVM <= 0x0309) {
3493 params[3] = ctx->ac.i1false; /* r128 */
3494 params[4] = da;
3495 params[5] = glc;
3496 params[6] = slc;
3497 } else {
3498 LLVMValueRef lwe = ctx->ac.i1false;
3499 params[3] = glc;
3500 params[4] = slc;
3501 params[5] = lwe;
3502 params[6] = da;
3503 }
3504
3505 ac_get_image_intr_name("llvm.amdgcn.image.load",
3506 ctx->ac.v4f32, /* vdata */
3507 LLVMTypeOf(params[0]), /* coords */
3508 LLVMTypeOf(params[1]), /* rsrc */
3509 intrinsic_name, sizeof(intrinsic_name));
3510
3511 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3512 params, 7, AC_FUNC_ATTR_READONLY);
3513 }
3514 return ac_to_integer(&ctx->ac, res);
3515 }
3516
3517 static void visit_image_store(struct ac_nir_context *ctx,
3518 nir_intrinsic_instr *instr)
3519 {
3520 LLVMValueRef params[8];
3521 char intrinsic_name[64];
3522 const nir_variable *var = instr->variables[0]->var;
3523 const struct glsl_type *type = glsl_without_array(var->type);
3524 LLVMValueRef glc = ctx->ac.i1false;
3525 bool force_glc = ctx->ac.chip_class == SI;
3526 if (force_glc)
3527 glc = ctx->ac.i1true;
3528
3529 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3530 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3531 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3532 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3533 ctx->ac.i32_0, ""); /* vindex */
3534 params[3] = ctx->ac.i32_0; /* voffset */
3535 params[4] = glc; /* glc */
3536 params[5] = ctx->ac.i1false; /* slc */
3537 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3538 params, 6, 0);
3539 } else {
3540 bool is_da = glsl_sampler_type_is_array(type) ||
3541 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3542 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3543 LLVMValueRef slc = ctx->ac.i1false;
3544
3545 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3546 params[1] = get_image_coords(ctx, instr); /* coords */
3547 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3548 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3549 if (HAVE_LLVM <= 0x0309) {
3550 params[4] = ctx->ac.i1false; /* r128 */
3551 params[5] = da;
3552 params[6] = glc;
3553 params[7] = slc;
3554 } else {
3555 LLVMValueRef lwe = ctx->ac.i1false;
3556 params[4] = glc;
3557 params[5] = slc;
3558 params[6] = lwe;
3559 params[7] = da;
3560 }
3561
3562 ac_get_image_intr_name("llvm.amdgcn.image.store",
3563 LLVMTypeOf(params[0]), /* vdata */
3564 LLVMTypeOf(params[1]), /* coords */
3565 LLVMTypeOf(params[2]), /* rsrc */
3566 intrinsic_name, sizeof(intrinsic_name));
3567
3568 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3569 params, 8, 0);
3570 }
3571
3572 }
3573
3574 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3575 const nir_intrinsic_instr *instr)
3576 {
3577 LLVMValueRef params[7];
3578 int param_count = 0;
3579 const nir_variable *var = instr->variables[0]->var;
3580
3581 const char *atomic_name;
3582 char intrinsic_name[41];
3583 const struct glsl_type *type = glsl_without_array(var->type);
3584 MAYBE_UNUSED int length;
3585
3586 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3587
3588 switch (instr->intrinsic) {
3589 case nir_intrinsic_image_atomic_add:
3590 atomic_name = "add";
3591 break;
3592 case nir_intrinsic_image_atomic_min:
3593 atomic_name = is_unsigned ? "umin" : "smin";
3594 break;
3595 case nir_intrinsic_image_atomic_max:
3596 atomic_name = is_unsigned ? "umax" : "smax";
3597 break;
3598 case nir_intrinsic_image_atomic_and:
3599 atomic_name = "and";
3600 break;
3601 case nir_intrinsic_image_atomic_or:
3602 atomic_name = "or";
3603 break;
3604 case nir_intrinsic_image_atomic_xor:
3605 atomic_name = "xor";
3606 break;
3607 case nir_intrinsic_image_atomic_exchange:
3608 atomic_name = "swap";
3609 break;
3610 case nir_intrinsic_image_atomic_comp_swap:
3611 atomic_name = "cmpswap";
3612 break;
3613 default:
3614 abort();
3615 }
3616
3617 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3618 params[param_count++] = get_src(ctx, instr->src[3]);
3619 params[param_count++] = get_src(ctx, instr->src[2]);
3620
3621 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3622 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3623 NULL, true, true);
3624 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3625 ctx->ac.i32_0, ""); /* vindex */
3626 params[param_count++] = ctx->ac.i32_0; /* voffset */
3627 params[param_count++] = ctx->ac.i1false; /* slc */
3628
3629 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3630 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3631 } else {
3632 char coords_type[8];
3633
3634 bool da = glsl_sampler_type_is_array(type) ||
3635 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3636
3637 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3638 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3639 NULL, true, true);
3640 params[param_count++] = ctx->ac.i1false; /* r128 */
3641 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3642 params[param_count++] = ctx->ac.i1false; /* slc */
3643
3644 build_int_type_name(LLVMTypeOf(coords),
3645 coords_type, sizeof(coords_type));
3646
3647 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3648 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3649 }
3650
3651 assert(length < sizeof(intrinsic_name));
3652 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3653 }
3654
3655 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3656 const nir_intrinsic_instr *instr)
3657 {
3658 LLVMValueRef res;
3659 const nir_variable *var = instr->variables[0]->var;
3660 const struct glsl_type *type = instr->variables[0]->var->type;
3661 bool da = glsl_sampler_type_is_array(var->type) ||
3662 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3663 if(instr->variables[0]->deref.child)
3664 type = instr->variables[0]->deref.child->type;
3665
3666 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3667 return get_buffer_size(ctx,
3668 get_sampler_desc(ctx, instr->variables[0],
3669 AC_DESC_BUFFER, NULL, true, false), true);
3670
3671 struct ac_image_args args = { 0 };
3672
3673 args.da = da;
3674 args.dmask = 0xf;
3675 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3676 args.opcode = ac_image_get_resinfo;
3677 args.addr = ctx->ac.i32_0;
3678
3679 res = ac_build_image_opcode(&ctx->ac, &args);
3680
3681 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3682
3683 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3684 glsl_sampler_type_is_array(type)) {
3685 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3686 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3687 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3688 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3689 }
3690 if (ctx->ac.chip_class >= GFX9 &&
3691 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3692 glsl_sampler_type_is_array(type)) {
3693 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3694 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3695 ctx->ac.i32_1, "");
3696
3697 }
3698 return res;
3699 }
3700
3701 #define NOOP_WAITCNT 0xf7f
3702 #define LGKM_CNT 0x07f
3703 #define VM_CNT 0xf70
3704
3705 static void emit_membar(struct nir_to_llvm_context *ctx,
3706 const nir_intrinsic_instr *instr)
3707 {
3708 unsigned waitcnt = NOOP_WAITCNT;
3709
3710 switch (instr->intrinsic) {
3711 case nir_intrinsic_memory_barrier:
3712 case nir_intrinsic_group_memory_barrier:
3713 waitcnt &= VM_CNT & LGKM_CNT;
3714 break;
3715 case nir_intrinsic_memory_barrier_atomic_counter:
3716 case nir_intrinsic_memory_barrier_buffer:
3717 case nir_intrinsic_memory_barrier_image:
3718 waitcnt &= VM_CNT;
3719 break;
3720 case nir_intrinsic_memory_barrier_shared:
3721 waitcnt &= LGKM_CNT;
3722 break;
3723 default:
3724 break;
3725 }
3726 if (waitcnt != NOOP_WAITCNT)
3727 ac_build_waitcnt(&ctx->ac, waitcnt);
3728 }
3729
3730 static void emit_barrier(struct nir_to_llvm_context *ctx)
3731 {
3732 /* SI only (thanks to a hw bug workaround):
3733 * The real barrier instruction isn’t needed, because an entire patch
3734 * always fits into a single wave.
3735 */
3736 if (ctx->options->chip_class == SI &&
3737 ctx->stage == MESA_SHADER_TESS_CTRL) {
3738 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
3739 return;
3740 }
3741 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3742 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3743 }
3744
3745 static void emit_discard_if(struct ac_nir_context *ctx,
3746 const nir_intrinsic_instr *instr)
3747 {
3748 LLVMValueRef cond;
3749
3750 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3751 get_src(ctx, instr->src[0]),
3752 ctx->ac.i32_0, "");
3753 ac_build_kill_if_false(&ctx->ac, cond);
3754 }
3755
3756 static LLVMValueRef
3757 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3758 {
3759 LLVMValueRef result;
3760 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3761 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3762 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3763
3764 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3765 }
3766
3767 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3768 const nir_intrinsic_instr *instr)
3769 {
3770 LLVMValueRef ptr, result;
3771 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3772 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3773
3774 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3775 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3776 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3777 ptr, src, src1,
3778 LLVMAtomicOrderingSequentiallyConsistent,
3779 LLVMAtomicOrderingSequentiallyConsistent,
3780 false);
3781 } else {
3782 LLVMAtomicRMWBinOp op;
3783 switch (instr->intrinsic) {
3784 case nir_intrinsic_var_atomic_add:
3785 op = LLVMAtomicRMWBinOpAdd;
3786 break;
3787 case nir_intrinsic_var_atomic_umin:
3788 op = LLVMAtomicRMWBinOpUMin;
3789 break;
3790 case nir_intrinsic_var_atomic_umax:
3791 op = LLVMAtomicRMWBinOpUMax;
3792 break;
3793 case nir_intrinsic_var_atomic_imin:
3794 op = LLVMAtomicRMWBinOpMin;
3795 break;
3796 case nir_intrinsic_var_atomic_imax:
3797 op = LLVMAtomicRMWBinOpMax;
3798 break;
3799 case nir_intrinsic_var_atomic_and:
3800 op = LLVMAtomicRMWBinOpAnd;
3801 break;
3802 case nir_intrinsic_var_atomic_or:
3803 op = LLVMAtomicRMWBinOpOr;
3804 break;
3805 case nir_intrinsic_var_atomic_xor:
3806 op = LLVMAtomicRMWBinOpXor;
3807 break;
3808 case nir_intrinsic_var_atomic_exchange:
3809 op = LLVMAtomicRMWBinOpXchg;
3810 break;
3811 default:
3812 return NULL;
3813 }
3814
3815 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3816 LLVMAtomicOrderingSequentiallyConsistent,
3817 false);
3818 }
3819 return result;
3820 }
3821
3822 #define INTERP_CENTER 0
3823 #define INTERP_CENTROID 1
3824 #define INTERP_SAMPLE 2
3825
3826 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3827 enum glsl_interp_mode interp, unsigned location)
3828 {
3829 switch (interp) {
3830 case INTERP_MODE_FLAT:
3831 default:
3832 return NULL;
3833 case INTERP_MODE_SMOOTH:
3834 case INTERP_MODE_NONE:
3835 if (location == INTERP_CENTER)
3836 return ctx->persp_center;
3837 else if (location == INTERP_CENTROID)
3838 return ctx->persp_centroid;
3839 else if (location == INTERP_SAMPLE)
3840 return ctx->persp_sample;
3841 break;
3842 case INTERP_MODE_NOPERSPECTIVE:
3843 if (location == INTERP_CENTER)
3844 return ctx->linear_center;
3845 else if (location == INTERP_CENTROID)
3846 return ctx->linear_centroid;
3847 else if (location == INTERP_SAMPLE)
3848 return ctx->linear_sample;
3849 break;
3850 }
3851 return NULL;
3852 }
3853
3854 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3855 LLVMValueRef sample_id)
3856 {
3857 LLVMValueRef result;
3858 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3859
3860 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3861 const_array(ctx->ac.v2f32, 64), "");
3862
3863 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3864 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3865
3866 return result;
3867 }
3868
3869 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3870 {
3871 LLVMValueRef values[2];
3872
3873 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3874 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3875 return ac_build_gather_values(&ctx->ac, values, 2);
3876 }
3877
3878 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3879 const nir_intrinsic_instr *instr)
3880 {
3881 LLVMValueRef result[4];
3882 LLVMValueRef interp_param, attr_number;
3883 unsigned location;
3884 unsigned chan;
3885 LLVMValueRef src_c0 = NULL;
3886 LLVMValueRef src_c1 = NULL;
3887 LLVMValueRef src0 = NULL;
3888 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3889 switch (instr->intrinsic) {
3890 case nir_intrinsic_interp_var_at_centroid:
3891 location = INTERP_CENTROID;
3892 break;
3893 case nir_intrinsic_interp_var_at_sample:
3894 case nir_intrinsic_interp_var_at_offset:
3895 location = INTERP_CENTER;
3896 src0 = get_src(ctx->nir, instr->src[0]);
3897 break;
3898 default:
3899 break;
3900 }
3901
3902 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3903 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3904 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3905 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3906 LLVMValueRef sample_position;
3907 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
3908
3909 /* fetch sample ID */
3910 sample_position = load_sample_position(ctx, src0);
3911
3912 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
3913 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3914 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
3915 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3916 }
3917 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3918 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
3919
3920 if (location == INTERP_CENTER) {
3921 LLVMValueRef ij_out[2];
3922 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3923
3924 /*
3925 * take the I then J parameters, and the DDX/Y for it, and
3926 * calculate the IJ inputs for the interpolator.
3927 * temp1 = ddx * offset/sample.x + I;
3928 * interp_param.I = ddy * offset/sample.y + temp1;
3929 * temp1 = ddx * offset/sample.x + J;
3930 * interp_param.J = ddy * offset/sample.y + temp1;
3931 */
3932 for (unsigned i = 0; i < 2; i++) {
3933 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
3934 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
3935 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3936 ddxy_out, ix_ll, "");
3937 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3938 ddxy_out, iy_ll, "");
3939 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3940 interp_param, ix_ll, "");
3941 LLVMValueRef temp1, temp2;
3942
3943 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3944 ctx->ac.f32, "");
3945
3946 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3947 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3948
3949 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3950 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3951
3952 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3953 temp2, ctx->ac.i32, "");
3954 }
3955 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3956
3957 }
3958
3959 for (chan = 0; chan < 4; chan++) {
3960 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
3961
3962 if (interp_param) {
3963 interp_param = LLVMBuildBitCast(ctx->builder,
3964 interp_param, ctx->ac.v2f32, "");
3965 LLVMValueRef i = LLVMBuildExtractElement(
3966 ctx->builder, interp_param, ctx->ac.i32_0, "");
3967 LLVMValueRef j = LLVMBuildExtractElement(
3968 ctx->builder, interp_param, ctx->ac.i32_1, "");
3969
3970 result[chan] = ac_build_fs_interp(&ctx->ac,
3971 llvm_chan, attr_number,
3972 ctx->prim_mask, i, j);
3973 } else {
3974 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3975 LLVMConstInt(ctx->ac.i32, 2, false),
3976 llvm_chan, attr_number,
3977 ctx->prim_mask);
3978 }
3979 }
3980 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
3981 instr->variables[0]->var->data.location_frac);
3982 }
3983
3984 static void
3985 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
3986 {
3987 LLVMValueRef gs_next_vertex;
3988 LLVMValueRef can_emit;
3989 int idx;
3990 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3991
3992 /* Write vertex attribute values to GSVS ring */
3993 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3994 ctx->gs_next_vertex,
3995 "");
3996
3997 /* If this thread has already emitted the declared maximum number of
3998 * vertices, kill it: excessive vertex emissions are not supposed to
3999 * have any effect, and GS threads have no externally observable
4000 * effects other than emitting vertices.
4001 */
4002 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4003 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4004 ac_build_kill_if_false(&ctx->ac, can_emit);
4005
4006 /* loop num outputs */
4007 idx = 0;
4008 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4009 LLVMValueRef *out_ptr = &addrs[i * 4];
4010 int length = 4;
4011 int slot = idx;
4012 int slot_inc = 1;
4013
4014 if (!(ctx->output_mask & (1ull << i)))
4015 continue;
4016
4017 if (i == VARYING_SLOT_CLIP_DIST0) {
4018 /* pack clip and cull into a single set of slots */
4019 length = ctx->num_output_clips + ctx->num_output_culls;
4020 if (length > 4)
4021 slot_inc = 2;
4022 }
4023 for (unsigned j = 0; j < length; j++) {
4024 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4025 out_ptr[j], "");
4026 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4027 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4028 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4029
4030 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4031
4032 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4033 out_val, 1,
4034 voffset, ctx->gs2vs_offset, 0,
4035 1, 1, true, true);
4036 }
4037 idx += slot_inc;
4038 }
4039
4040 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4041 ctx->ac.i32_1, "");
4042 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4043
4044 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4045 }
4046
4047 static void
4048 visit_end_primitive(struct nir_to_llvm_context *ctx,
4049 const nir_intrinsic_instr *instr)
4050 {
4051 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4052 }
4053
4054 static LLVMValueRef
4055 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4056 const nir_intrinsic_instr *instr)
4057 {
4058 LLVMValueRef coord[4] = {
4059 ctx->tes_u,
4060 ctx->tes_v,
4061 ctx->ac.f32_0,
4062 ctx->ac.f32_0,
4063 };
4064
4065 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4066 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4067 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4068
4069 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4070 return LLVMBuildBitCast(ctx->builder, result,
4071 get_def_type(ctx->nir, &instr->dest.ssa), "");
4072 }
4073
4074 static void visit_intrinsic(struct ac_nir_context *ctx,
4075 nir_intrinsic_instr *instr)
4076 {
4077 LLVMValueRef result = NULL;
4078
4079 switch (instr->intrinsic) {
4080 case nir_intrinsic_load_work_group_id: {
4081 LLVMValueRef values[3];
4082
4083 for (int i = 0; i < 3; i++) {
4084 values[i] = ctx->nctx->workgroup_ids[i] ?
4085 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4086 }
4087
4088 result = ac_build_gather_values(&ctx->ac, values, 3);
4089 break;
4090 }
4091 case nir_intrinsic_load_base_vertex: {
4092 result = ctx->abi->base_vertex;
4093 break;
4094 }
4095 case nir_intrinsic_load_vertex_id_zero_base: {
4096 result = ctx->abi->vertex_id;
4097 break;
4098 }
4099 case nir_intrinsic_load_local_invocation_id: {
4100 result = ctx->nctx->local_invocation_ids;
4101 break;
4102 }
4103 case nir_intrinsic_load_base_instance:
4104 result = ctx->abi->start_instance;
4105 break;
4106 case nir_intrinsic_load_draw_id:
4107 result = ctx->abi->draw_id;
4108 break;
4109 case nir_intrinsic_load_view_index:
4110 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4111 break;
4112 case nir_intrinsic_load_invocation_id:
4113 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4114 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4115 else
4116 result = ctx->abi->gs_invocation_id;
4117 break;
4118 case nir_intrinsic_load_primitive_id:
4119 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4120 if (ctx->nctx)
4121 ctx->nctx->shader_info->gs.uses_prim_id = true;
4122 result = ctx->abi->gs_prim_id;
4123 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4124 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4125 result = ctx->nctx->tcs_patch_id;
4126 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4127 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4128 result = ctx->nctx->tes_patch_id;
4129 } else
4130 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4131 break;
4132 case nir_intrinsic_load_sample_id:
4133 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4134 break;
4135 case nir_intrinsic_load_sample_pos:
4136 result = load_sample_pos(ctx);
4137 break;
4138 case nir_intrinsic_load_sample_mask_in:
4139 result = ctx->abi->sample_coverage;
4140 break;
4141 case nir_intrinsic_load_frag_coord: {
4142 LLVMValueRef values[4] = {
4143 ctx->abi->frag_pos[0],
4144 ctx->abi->frag_pos[1],
4145 ctx->abi->frag_pos[2],
4146 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4147 };
4148 result = ac_build_gather_values(&ctx->ac, values, 4);
4149 break;
4150 }
4151 case nir_intrinsic_load_front_face:
4152 result = ctx->abi->front_face;
4153 break;
4154 case nir_intrinsic_load_instance_id:
4155 result = ctx->abi->instance_id;
4156 break;
4157 case nir_intrinsic_load_num_work_groups:
4158 result = ctx->nctx->num_work_groups;
4159 break;
4160 case nir_intrinsic_load_local_invocation_index:
4161 result = visit_load_local_invocation_index(ctx->nctx);
4162 break;
4163 case nir_intrinsic_load_push_constant:
4164 result = visit_load_push_constant(ctx->nctx, instr);
4165 break;
4166 case nir_intrinsic_vulkan_resource_index:
4167 result = visit_vulkan_resource_index(ctx->nctx, instr);
4168 break;
4169 case nir_intrinsic_vulkan_resource_reindex:
4170 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4171 break;
4172 case nir_intrinsic_store_ssbo:
4173 visit_store_ssbo(ctx, instr);
4174 break;
4175 case nir_intrinsic_load_ssbo:
4176 result = visit_load_buffer(ctx, instr);
4177 break;
4178 case nir_intrinsic_ssbo_atomic_add:
4179 case nir_intrinsic_ssbo_atomic_imin:
4180 case nir_intrinsic_ssbo_atomic_umin:
4181 case nir_intrinsic_ssbo_atomic_imax:
4182 case nir_intrinsic_ssbo_atomic_umax:
4183 case nir_intrinsic_ssbo_atomic_and:
4184 case nir_intrinsic_ssbo_atomic_or:
4185 case nir_intrinsic_ssbo_atomic_xor:
4186 case nir_intrinsic_ssbo_atomic_exchange:
4187 case nir_intrinsic_ssbo_atomic_comp_swap:
4188 result = visit_atomic_ssbo(ctx, instr);
4189 break;
4190 case nir_intrinsic_load_ubo:
4191 result = visit_load_ubo_buffer(ctx, instr);
4192 break;
4193 case nir_intrinsic_get_buffer_size:
4194 result = visit_get_buffer_size(ctx, instr);
4195 break;
4196 case nir_intrinsic_load_var:
4197 result = visit_load_var(ctx, instr);
4198 break;
4199 case nir_intrinsic_store_var:
4200 visit_store_var(ctx, instr);
4201 break;
4202 case nir_intrinsic_image_load:
4203 result = visit_image_load(ctx, instr);
4204 break;
4205 case nir_intrinsic_image_store:
4206 visit_image_store(ctx, instr);
4207 break;
4208 case nir_intrinsic_image_atomic_add:
4209 case nir_intrinsic_image_atomic_min:
4210 case nir_intrinsic_image_atomic_max:
4211 case nir_intrinsic_image_atomic_and:
4212 case nir_intrinsic_image_atomic_or:
4213 case nir_intrinsic_image_atomic_xor:
4214 case nir_intrinsic_image_atomic_exchange:
4215 case nir_intrinsic_image_atomic_comp_swap:
4216 result = visit_image_atomic(ctx, instr);
4217 break;
4218 case nir_intrinsic_image_size:
4219 result = visit_image_size(ctx, instr);
4220 break;
4221 case nir_intrinsic_discard:
4222 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4223 LLVMVoidTypeInContext(ctx->ac.context),
4224 NULL, 0, AC_FUNC_ATTR_LEGACY);
4225 break;
4226 case nir_intrinsic_discard_if:
4227 emit_discard_if(ctx, instr);
4228 break;
4229 case nir_intrinsic_memory_barrier:
4230 case nir_intrinsic_group_memory_barrier:
4231 case nir_intrinsic_memory_barrier_atomic_counter:
4232 case nir_intrinsic_memory_barrier_buffer:
4233 case nir_intrinsic_memory_barrier_image:
4234 case nir_intrinsic_memory_barrier_shared:
4235 emit_membar(ctx->nctx, instr);
4236 break;
4237 case nir_intrinsic_barrier:
4238 emit_barrier(ctx->nctx);
4239 break;
4240 case nir_intrinsic_var_atomic_add:
4241 case nir_intrinsic_var_atomic_imin:
4242 case nir_intrinsic_var_atomic_umin:
4243 case nir_intrinsic_var_atomic_imax:
4244 case nir_intrinsic_var_atomic_umax:
4245 case nir_intrinsic_var_atomic_and:
4246 case nir_intrinsic_var_atomic_or:
4247 case nir_intrinsic_var_atomic_xor:
4248 case nir_intrinsic_var_atomic_exchange:
4249 case nir_intrinsic_var_atomic_comp_swap:
4250 result = visit_var_atomic(ctx->nctx, instr);
4251 break;
4252 case nir_intrinsic_interp_var_at_centroid:
4253 case nir_intrinsic_interp_var_at_sample:
4254 case nir_intrinsic_interp_var_at_offset:
4255 result = visit_interp(ctx->nctx, instr);
4256 break;
4257 case nir_intrinsic_emit_vertex:
4258 assert(instr->const_index[0] == 0);
4259 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4260 break;
4261 case nir_intrinsic_end_primitive:
4262 visit_end_primitive(ctx->nctx, instr);
4263 break;
4264 case nir_intrinsic_load_tess_coord:
4265 result = visit_load_tess_coord(ctx->nctx, instr);
4266 break;
4267 case nir_intrinsic_load_patch_vertices_in:
4268 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4269 break;
4270 default:
4271 fprintf(stderr, "Unknown intrinsic: ");
4272 nir_print_instr(&instr->instr, stderr);
4273 fprintf(stderr, "\n");
4274 break;
4275 }
4276 if (result) {
4277 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4278 }
4279 }
4280
4281 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4282 LLVMValueRef buffer_ptr, bool write)
4283 {
4284 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4285
4286 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4287 ctx->shader_info->fs.writes_memory = true;
4288
4289 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4290 }
4291
4292 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4293 {
4294 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4295
4296 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4297 }
4298
4299 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4300 unsigned descriptor_set,
4301 unsigned base_index,
4302 unsigned constant_index,
4303 LLVMValueRef index,
4304 enum ac_descriptor_type desc_type,
4305 bool image, bool write)
4306 {
4307 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4308 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4309 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4310 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4311 unsigned offset = binding->offset;
4312 unsigned stride = binding->size;
4313 unsigned type_size;
4314 LLVMBuilderRef builder = ctx->builder;
4315 LLVMTypeRef type;
4316
4317 assert(base_index < layout->binding_count);
4318
4319 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4320 ctx->shader_info->fs.writes_memory = true;
4321
4322 switch (desc_type) {
4323 case AC_DESC_IMAGE:
4324 type = ctx->ac.v8i32;
4325 type_size = 32;
4326 break;
4327 case AC_DESC_FMASK:
4328 type = ctx->ac.v8i32;
4329 offset += 32;
4330 type_size = 32;
4331 break;
4332 case AC_DESC_SAMPLER:
4333 type = ctx->ac.v4i32;
4334 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4335 offset += 64;
4336
4337 type_size = 16;
4338 break;
4339 case AC_DESC_BUFFER:
4340 type = ctx->ac.v4i32;
4341 type_size = 16;
4342 break;
4343 default:
4344 unreachable("invalid desc_type\n");
4345 }
4346
4347 offset += constant_index * stride;
4348
4349 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4350 (!index || binding->immutable_samplers_equal)) {
4351 if (binding->immutable_samplers_equal)
4352 constant_index = 0;
4353
4354 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4355
4356 LLVMValueRef constants[] = {
4357 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4358 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4359 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4360 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4361 };
4362 return ac_build_gather_values(&ctx->ac, constants, 4);
4363 }
4364
4365 assert(stride % type_size == 0);
4366
4367 if (!index)
4368 index = ctx->ac.i32_0;
4369
4370 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4371
4372 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4373 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4374
4375 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4376 }
4377
4378 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4379 const nir_deref_var *deref,
4380 enum ac_descriptor_type desc_type,
4381 const nir_tex_instr *tex_instr,
4382 bool image, bool write)
4383 {
4384 LLVMValueRef index = NULL;
4385 unsigned constant_index = 0;
4386 unsigned descriptor_set;
4387 unsigned base_index;
4388
4389 if (!deref) {
4390 assert(tex_instr && !image);
4391 descriptor_set = 0;
4392 base_index = tex_instr->sampler_index;
4393 } else {
4394 const nir_deref *tail = &deref->deref;
4395 while (tail->child) {
4396 const nir_deref_array *child = nir_deref_as_array(tail->child);
4397 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4398
4399 if (!array_size)
4400 array_size = 1;
4401
4402 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4403
4404 if (child->deref_array_type == nir_deref_array_type_indirect) {
4405 LLVMValueRef indirect = get_src(ctx, child->indirect);
4406
4407 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4408 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4409
4410 if (!index)
4411 index = indirect;
4412 else
4413 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4414 }
4415
4416 constant_index += child->base_offset * array_size;
4417
4418 tail = &child->deref;
4419 }
4420 descriptor_set = deref->var->data.descriptor_set;
4421 base_index = deref->var->data.binding;
4422 }
4423
4424 return ctx->abi->load_sampler_desc(ctx->abi,
4425 descriptor_set,
4426 base_index,
4427 constant_index, index,
4428 desc_type, image, write);
4429 }
4430
4431 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4432 struct ac_image_args *args,
4433 const nir_tex_instr *instr,
4434 nir_texop op,
4435 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4436 LLVMValueRef *param, unsigned count,
4437 unsigned dmask)
4438 {
4439 unsigned is_rect = 0;
4440 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4441
4442 if (op == nir_texop_lod)
4443 da = false;
4444 /* Pad to power of two vector */
4445 while (count < util_next_power_of_two(count))
4446 param[count++] = LLVMGetUndef(ctx->i32);
4447
4448 if (count > 1)
4449 args->addr = ac_build_gather_values(ctx, param, count);
4450 else
4451 args->addr = param[0];
4452
4453 args->resource = res_ptr;
4454 args->sampler = samp_ptr;
4455
4456 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4457 args->addr = param[0];
4458 return;
4459 }
4460
4461 args->dmask = dmask;
4462 args->unorm = is_rect;
4463 args->da = da;
4464 }
4465
4466 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4467 *
4468 * SI-CI:
4469 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4470 * filtering manually. The driver sets img7 to a mask clearing
4471 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4472 * s_and_b32 samp0, samp0, img7
4473 *
4474 * VI:
4475 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4476 */
4477 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4478 LLVMValueRef res, LLVMValueRef samp)
4479 {
4480 LLVMBuilderRef builder = ctx->ac.builder;
4481 LLVMValueRef img7, samp0;
4482
4483 if (ctx->ac.chip_class >= VI)
4484 return samp;
4485
4486 img7 = LLVMBuildExtractElement(builder, res,
4487 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4488 samp0 = LLVMBuildExtractElement(builder, samp,
4489 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4490 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4491 return LLVMBuildInsertElement(builder, samp, samp0,
4492 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4493 }
4494
4495 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4496 nir_tex_instr *instr,
4497 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4498 LLVMValueRef *fmask_ptr)
4499 {
4500 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4501 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4502 else
4503 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4504 if (samp_ptr) {
4505 if (instr->sampler)
4506 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4507 else
4508 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4509 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4510 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4511 }
4512 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4513 instr->op == nir_texop_samples_identical))
4514 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4515 }
4516
4517 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4518 LLVMValueRef coord)
4519 {
4520 coord = ac_to_float(ctx, coord);
4521 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4522 coord = ac_to_integer(ctx, coord);
4523 return coord;
4524 }
4525
4526 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4527 {
4528 LLVMValueRef result = NULL;
4529 struct ac_image_args args = { 0 };
4530 unsigned dmask = 0xf;
4531 LLVMValueRef address[16];
4532 LLVMValueRef coords[5];
4533 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4534 LLVMValueRef bias = NULL, offsets = NULL;
4535 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4536 LLVMValueRef ddx = NULL, ddy = NULL;
4537 LLVMValueRef derivs[6];
4538 unsigned chan, count = 0;
4539 unsigned const_src = 0, num_deriv_comp = 0;
4540 bool lod_is_zero = false;
4541
4542 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4543
4544 for (unsigned i = 0; i < instr->num_srcs; i++) {
4545 switch (instr->src[i].src_type) {
4546 case nir_tex_src_coord:
4547 coord = get_src(ctx, instr->src[i].src);
4548 break;
4549 case nir_tex_src_projector:
4550 break;
4551 case nir_tex_src_comparator:
4552 comparator = get_src(ctx, instr->src[i].src);
4553 break;
4554 case nir_tex_src_offset:
4555 offsets = get_src(ctx, instr->src[i].src);
4556 const_src = i;
4557 break;
4558 case nir_tex_src_bias:
4559 bias = get_src(ctx, instr->src[i].src);
4560 break;
4561 case nir_tex_src_lod: {
4562 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4563
4564 if (val && val->i32[0] == 0)
4565 lod_is_zero = true;
4566 lod = get_src(ctx, instr->src[i].src);
4567 break;
4568 }
4569 case nir_tex_src_ms_index:
4570 sample_index = get_src(ctx, instr->src[i].src);
4571 break;
4572 case nir_tex_src_ms_mcs:
4573 break;
4574 case nir_tex_src_ddx:
4575 ddx = get_src(ctx, instr->src[i].src);
4576 num_deriv_comp = instr->src[i].src.ssa->num_components;
4577 break;
4578 case nir_tex_src_ddy:
4579 ddy = get_src(ctx, instr->src[i].src);
4580 break;
4581 case nir_tex_src_texture_offset:
4582 case nir_tex_src_sampler_offset:
4583 case nir_tex_src_plane:
4584 default:
4585 break;
4586 }
4587 }
4588
4589 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4590 result = get_buffer_size(ctx, res_ptr, true);
4591 goto write_result;
4592 }
4593
4594 if (instr->op == nir_texop_texture_samples) {
4595 LLVMValueRef res, samples, is_msaa;
4596 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4597 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4598 LLVMConstInt(ctx->ac.i32, 3, false), "");
4599 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4600 LLVMConstInt(ctx->ac.i32, 28, false), "");
4601 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4602 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4603 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4604 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4605
4606 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4607 LLVMConstInt(ctx->ac.i32, 16, false), "");
4608 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4609 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4610 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4611 samples, "");
4612 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4613 ctx->ac.i32_1, "");
4614 result = samples;
4615 goto write_result;
4616 }
4617
4618 if (coord)
4619 for (chan = 0; chan < instr->coord_components; chan++)
4620 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4621
4622 if (offsets && instr->op != nir_texop_txf) {
4623 LLVMValueRef offset[3], pack;
4624 for (chan = 0; chan < 3; ++chan)
4625 offset[chan] = ctx->ac.i32_0;
4626
4627 args.offset = true;
4628 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4629 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4630 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4631 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4632 if (chan)
4633 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4634 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4635 }
4636 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4637 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4638 address[count++] = pack;
4639
4640 }
4641 /* pack LOD bias value */
4642 if (instr->op == nir_texop_txb && bias) {
4643 address[count++] = bias;
4644 }
4645
4646 /* Pack depth comparison value */
4647 if (instr->is_shadow && comparator) {
4648 LLVMValueRef z = ac_to_float(&ctx->ac,
4649 llvm_extract_elem(&ctx->ac, comparator, 0));
4650
4651 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4652 * so the depth comparison value isn't clamped for Z16 and
4653 * Z24 anymore. Do it manually here.
4654 *
4655 * It's unnecessary if the original texture format was
4656 * Z32_FLOAT, but we don't know that here.
4657 */
4658 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4659 z = ac_build_clamp(&ctx->ac, z);
4660
4661 address[count++] = z;
4662 }
4663
4664 /* pack derivatives */
4665 if (ddx || ddy) {
4666 int num_src_deriv_channels, num_dest_deriv_channels;
4667 switch (instr->sampler_dim) {
4668 case GLSL_SAMPLER_DIM_3D:
4669 case GLSL_SAMPLER_DIM_CUBE:
4670 num_deriv_comp = 3;
4671 num_src_deriv_channels = 3;
4672 num_dest_deriv_channels = 3;
4673 break;
4674 case GLSL_SAMPLER_DIM_2D:
4675 default:
4676 num_src_deriv_channels = 2;
4677 num_dest_deriv_channels = 2;
4678 num_deriv_comp = 2;
4679 break;
4680 case GLSL_SAMPLER_DIM_1D:
4681 num_src_deriv_channels = 1;
4682 if (ctx->ac.chip_class >= GFX9) {
4683 num_dest_deriv_channels = 2;
4684 num_deriv_comp = 2;
4685 } else {
4686 num_dest_deriv_channels = 1;
4687 num_deriv_comp = 1;
4688 }
4689 break;
4690 }
4691
4692 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4693 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4694 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4695 }
4696 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4697 derivs[i] = ctx->ac.f32_0;
4698 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4699 }
4700 }
4701
4702 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4703 for (chan = 0; chan < instr->coord_components; chan++)
4704 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4705 if (instr->coord_components == 3)
4706 coords[3] = LLVMGetUndef(ctx->ac.f32);
4707 ac_prepare_cube_coords(&ctx->ac,
4708 instr->op == nir_texop_txd, instr->is_array,
4709 instr->op == nir_texop_lod, coords, derivs);
4710 if (num_deriv_comp)
4711 num_deriv_comp--;
4712 }
4713
4714 if (ddx || ddy) {
4715 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4716 address[count++] = derivs[i];
4717 }
4718
4719 /* Pack texture coordinates */
4720 if (coord) {
4721 address[count++] = coords[0];
4722 if (instr->coord_components > 1) {
4723 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4724 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4725 }
4726 address[count++] = coords[1];
4727 }
4728 if (instr->coord_components > 2) {
4729 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4730 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4731 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4732 instr->op != nir_texop_txf) {
4733 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4734 }
4735 address[count++] = coords[2];
4736 }
4737
4738 if (ctx->ac.chip_class >= GFX9) {
4739 LLVMValueRef filler;
4740 if (instr->op == nir_texop_txf)
4741 filler = ctx->ac.i32_0;
4742 else
4743 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4744
4745 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4746 /* No nir_texop_lod, because it does not take a slice
4747 * even with array textures. */
4748 if (instr->is_array && instr->op != nir_texop_lod ) {
4749 address[count] = address[count - 1];
4750 address[count - 1] = filler;
4751 count++;
4752 } else
4753 address[count++] = filler;
4754 }
4755 }
4756 }
4757
4758 /* Pack LOD */
4759 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4760 instr->op == nir_texop_txf)) {
4761 address[count++] = lod;
4762 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4763 address[count++] = sample_index;
4764 } else if(instr->op == nir_texop_txs) {
4765 count = 0;
4766 if (lod)
4767 address[count++] = lod;
4768 else
4769 address[count++] = ctx->ac.i32_0;
4770 }
4771
4772 for (chan = 0; chan < count; chan++) {
4773 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4774 address[chan], ctx->ac.i32, "");
4775 }
4776
4777 if (instr->op == nir_texop_samples_identical) {
4778 LLVMValueRef txf_address[4];
4779 struct ac_image_args txf_args = { 0 };
4780 unsigned txf_count = count;
4781 memcpy(txf_address, address, sizeof(txf_address));
4782
4783 if (!instr->is_array)
4784 txf_address[2] = ctx->ac.i32_0;
4785 txf_address[3] = ctx->ac.i32_0;
4786
4787 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4788 fmask_ptr, NULL,
4789 txf_address, txf_count, 0xf);
4790
4791 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4792
4793 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4794 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4795 goto write_result;
4796 }
4797
4798 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4799 instr->op != nir_texop_txs) {
4800 unsigned sample_chan = instr->is_array ? 3 : 2;
4801 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4802 address[0],
4803 address[1],
4804 instr->is_array ? address[2] : NULL,
4805 address[sample_chan],
4806 fmask_ptr);
4807 }
4808
4809 if (offsets && instr->op == nir_texop_txf) {
4810 nir_const_value *const_offset =
4811 nir_src_as_const_value(instr->src[const_src].src);
4812 int num_offsets = instr->src[const_src].src.ssa->num_components;
4813 assert(const_offset);
4814 num_offsets = MIN2(num_offsets, instr->coord_components);
4815 if (num_offsets > 2)
4816 address[2] = LLVMBuildAdd(ctx->ac.builder,
4817 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4818 if (num_offsets > 1)
4819 address[1] = LLVMBuildAdd(ctx->ac.builder,
4820 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4821 address[0] = LLVMBuildAdd(ctx->ac.builder,
4822 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4823
4824 }
4825
4826 /* TODO TG4 support */
4827 if (instr->op == nir_texop_tg4) {
4828 if (instr->is_shadow)
4829 dmask = 1;
4830 else
4831 dmask = 1 << instr->component;
4832 }
4833 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4834 res_ptr, samp_ptr, address, count, dmask);
4835
4836 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4837
4838 if (instr->op == nir_texop_query_levels)
4839 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4840 else if (instr->is_shadow && instr->is_new_style_shadow &&
4841 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4842 instr->op != nir_texop_tg4)
4843 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4844 else if (instr->op == nir_texop_txs &&
4845 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4846 instr->is_array) {
4847 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4848 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4849 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4850 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4851 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4852 } else if (ctx->ac.chip_class >= GFX9 &&
4853 instr->op == nir_texop_txs &&
4854 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4855 instr->is_array) {
4856 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4857 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4858 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4859 ctx->ac.i32_1, "");
4860 } else if (instr->dest.ssa.num_components != 4)
4861 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4862
4863 write_result:
4864 if (result) {
4865 assert(instr->dest.is_ssa);
4866 result = ac_to_integer(&ctx->ac, result);
4867 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4868 }
4869 }
4870
4871
4872 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4873 {
4874 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4875 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4876
4877 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4878 _mesa_hash_table_insert(ctx->phis, instr, result);
4879 }
4880
4881 static void visit_post_phi(struct ac_nir_context *ctx,
4882 nir_phi_instr *instr,
4883 LLVMValueRef llvm_phi)
4884 {
4885 nir_foreach_phi_src(src, instr) {
4886 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4887 LLVMValueRef llvm_src = get_src(ctx, src->src);
4888
4889 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4890 }
4891 }
4892
4893 static void phi_post_pass(struct ac_nir_context *ctx)
4894 {
4895 struct hash_entry *entry;
4896 hash_table_foreach(ctx->phis, entry) {
4897 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4898 (LLVMValueRef)entry->data);
4899 }
4900 }
4901
4902
4903 static void visit_ssa_undef(struct ac_nir_context *ctx,
4904 const nir_ssa_undef_instr *instr)
4905 {
4906 unsigned num_components = instr->def.num_components;
4907 LLVMValueRef undef;
4908
4909 if (num_components == 1)
4910 undef = LLVMGetUndef(ctx->ac.i32);
4911 else {
4912 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4913 }
4914 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4915 }
4916
4917 static void visit_jump(struct ac_nir_context *ctx,
4918 const nir_jump_instr *instr)
4919 {
4920 switch (instr->type) {
4921 case nir_jump_break:
4922 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4923 LLVMClearInsertionPosition(ctx->ac.builder);
4924 break;
4925 case nir_jump_continue:
4926 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4927 LLVMClearInsertionPosition(ctx->ac.builder);
4928 break;
4929 default:
4930 fprintf(stderr, "Unknown NIR jump instr: ");
4931 nir_print_instr(&instr->instr, stderr);
4932 fprintf(stderr, "\n");
4933 abort();
4934 }
4935 }
4936
4937 static void visit_cf_list(struct ac_nir_context *ctx,
4938 struct exec_list *list);
4939
4940 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4941 {
4942 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4943 nir_foreach_instr(instr, block)
4944 {
4945 switch (instr->type) {
4946 case nir_instr_type_alu:
4947 visit_alu(ctx, nir_instr_as_alu(instr));
4948 break;
4949 case nir_instr_type_load_const:
4950 visit_load_const(ctx, nir_instr_as_load_const(instr));
4951 break;
4952 case nir_instr_type_intrinsic:
4953 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4954 break;
4955 case nir_instr_type_tex:
4956 visit_tex(ctx, nir_instr_as_tex(instr));
4957 break;
4958 case nir_instr_type_phi:
4959 visit_phi(ctx, nir_instr_as_phi(instr));
4960 break;
4961 case nir_instr_type_ssa_undef:
4962 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4963 break;
4964 case nir_instr_type_jump:
4965 visit_jump(ctx, nir_instr_as_jump(instr));
4966 break;
4967 default:
4968 fprintf(stderr, "Unknown NIR instr type: ");
4969 nir_print_instr(instr, stderr);
4970 fprintf(stderr, "\n");
4971 abort();
4972 }
4973 }
4974
4975 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4976 }
4977
4978 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4979 {
4980 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4981
4982 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4983 LLVMBasicBlockRef merge_block =
4984 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4985 LLVMBasicBlockRef if_block =
4986 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4987 LLVMBasicBlockRef else_block = merge_block;
4988 if (!exec_list_is_empty(&if_stmt->else_list))
4989 else_block = LLVMAppendBasicBlockInContext(
4990 ctx->ac.context, fn, "");
4991
4992 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4993 ctx->ac.i32_0, "");
4994 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4995
4996 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4997 visit_cf_list(ctx, &if_stmt->then_list);
4998 if (LLVMGetInsertBlock(ctx->ac.builder))
4999 LLVMBuildBr(ctx->ac.builder, merge_block);
5000
5001 if (!exec_list_is_empty(&if_stmt->else_list)) {
5002 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5003 visit_cf_list(ctx, &if_stmt->else_list);
5004 if (LLVMGetInsertBlock(ctx->ac.builder))
5005 LLVMBuildBr(ctx->ac.builder, merge_block);
5006 }
5007
5008 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5009 }
5010
5011 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5012 {
5013 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5014 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5015 LLVMBasicBlockRef break_parent = ctx->break_block;
5016
5017 ctx->continue_block =
5018 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5019 ctx->break_block =
5020 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5021
5022 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5023 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5024 visit_cf_list(ctx, &loop->body);
5025
5026 if (LLVMGetInsertBlock(ctx->ac.builder))
5027 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5028 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5029
5030 ctx->continue_block = continue_parent;
5031 ctx->break_block = break_parent;
5032 }
5033
5034 static void visit_cf_list(struct ac_nir_context *ctx,
5035 struct exec_list *list)
5036 {
5037 foreach_list_typed(nir_cf_node, node, node, list)
5038 {
5039 switch (node->type) {
5040 case nir_cf_node_block:
5041 visit_block(ctx, nir_cf_node_as_block(node));
5042 break;
5043
5044 case nir_cf_node_if:
5045 visit_if(ctx, nir_cf_node_as_if(node));
5046 break;
5047
5048 case nir_cf_node_loop:
5049 visit_loop(ctx, nir_cf_node_as_loop(node));
5050 break;
5051
5052 default:
5053 assert(0);
5054 }
5055 }
5056 }
5057
5058 static void
5059 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5060 struct nir_variable *variable)
5061 {
5062 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5063 LLVMValueRef t_offset;
5064 LLVMValueRef t_list;
5065 LLVMValueRef input;
5066 LLVMValueRef buffer_index;
5067 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5068 int idx = variable->data.location;
5069 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5070
5071 variable->data.driver_location = idx * 4;
5072
5073 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5074 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5075 ctx->abi.start_instance, "");
5076 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5077 ctx->shader_info->vs.vgpr_comp_cnt);
5078 } else
5079 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5080 ctx->abi.base_vertex, "");
5081
5082 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5083 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5084
5085 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5086
5087 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5088 buffer_index,
5089 ctx->ac.i32_0,
5090 true);
5091
5092 for (unsigned chan = 0; chan < 4; chan++) {
5093 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5094 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5095 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5096 input, llvm_chan, ""));
5097 }
5098 }
5099 }
5100
5101 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5102 unsigned attr,
5103 LLVMValueRef interp_param,
5104 LLVMValueRef prim_mask,
5105 LLVMValueRef result[4])
5106 {
5107 LLVMValueRef attr_number;
5108 unsigned chan;
5109 LLVMValueRef i, j;
5110 bool interp = interp_param != NULL;
5111
5112 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5113
5114 /* fs.constant returns the param from the middle vertex, so it's not
5115 * really useful for flat shading. It's meant to be used for custom
5116 * interpolation (but the intrinsic can't fetch from the other two
5117 * vertices).
5118 *
5119 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5120 * to do the right thing. The only reason we use fs.constant is that
5121 * fs.interp cannot be used on integers, because they can be equal
5122 * to NaN.
5123 */
5124 if (interp) {
5125 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5126 ctx->ac.v2f32, "");
5127
5128 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5129 ctx->ac.i32_0, "");
5130 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5131 ctx->ac.i32_1, "");
5132 }
5133
5134 for (chan = 0; chan < 4; chan++) {
5135 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5136
5137 if (interp) {
5138 result[chan] = ac_build_fs_interp(&ctx->ac,
5139 llvm_chan,
5140 attr_number,
5141 prim_mask, i, j);
5142 } else {
5143 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5144 LLVMConstInt(ctx->ac.i32, 2, false),
5145 llvm_chan,
5146 attr_number,
5147 prim_mask);
5148 }
5149 }
5150 }
5151
5152 static void
5153 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5154 struct nir_variable *variable)
5155 {
5156 int idx = variable->data.location;
5157 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5158 LLVMValueRef interp;
5159
5160 variable->data.driver_location = idx * 4;
5161 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5162
5163 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5164 unsigned interp_type;
5165 if (variable->data.sample) {
5166 interp_type = INTERP_SAMPLE;
5167 ctx->shader_info->info.ps.force_persample = true;
5168 } else if (variable->data.centroid)
5169 interp_type = INTERP_CENTROID;
5170 else
5171 interp_type = INTERP_CENTER;
5172
5173 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5174 } else
5175 interp = NULL;
5176
5177 for (unsigned i = 0; i < attrib_count; ++i)
5178 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5179
5180 }
5181
5182 static void
5183 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5184 struct nir_shader *nir) {
5185 nir_foreach_variable(variable, &nir->inputs)
5186 handle_vs_input_decl(ctx, variable);
5187 }
5188
5189 static void
5190 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5191 struct nir_shader *nir)
5192 {
5193 if (!ctx->options->key.fs.multisample)
5194 return;
5195
5196 bool uses_center = false;
5197 bool uses_centroid = false;
5198 nir_foreach_variable(variable, &nir->inputs) {
5199 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5200 variable->data.sample)
5201 continue;
5202
5203 if (variable->data.centroid)
5204 uses_centroid = true;
5205 else
5206 uses_center = true;
5207 }
5208
5209 if (uses_center && uses_centroid) {
5210 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5211 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5212 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5213 }
5214 }
5215
5216 static void
5217 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5218 struct nir_shader *nir)
5219 {
5220 prepare_interp_optimize(ctx, nir);
5221
5222 nir_foreach_variable(variable, &nir->inputs)
5223 handle_fs_input_decl(ctx, variable);
5224
5225 unsigned index = 0;
5226
5227 if (ctx->shader_info->info.ps.uses_input_attachments ||
5228 ctx->shader_info->info.needs_multiview_view_index)
5229 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5230
5231 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5232 LLVMValueRef interp_param;
5233 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5234
5235 if (!(ctx->input_mask & (1ull << i)))
5236 continue;
5237
5238 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5239 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5240 interp_param = *inputs;
5241 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5242 inputs);
5243
5244 if (!interp_param)
5245 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5246 ++index;
5247 } else if (i == VARYING_SLOT_POS) {
5248 for(int i = 0; i < 3; ++i)
5249 inputs[i] = ctx->abi.frag_pos[i];
5250
5251 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5252 ctx->abi.frag_pos[3]);
5253 }
5254 }
5255 ctx->shader_info->fs.num_interp = index;
5256 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5257 ctx->shader_info->fs.has_pcoord = true;
5258 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5259 ctx->shader_info->fs.prim_id_input = true;
5260 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5261 ctx->shader_info->fs.layer_input = true;
5262 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5263
5264 if (ctx->shader_info->info.needs_multiview_view_index)
5265 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5266 }
5267
5268 static LLVMValueRef
5269 ac_build_alloca(struct ac_llvm_context *ac,
5270 LLVMTypeRef type,
5271 const char *name)
5272 {
5273 LLVMBuilderRef builder = ac->builder;
5274 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5275 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5276 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5277 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5278 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5279 LLVMValueRef res;
5280
5281 if (first_instr) {
5282 LLVMPositionBuilderBefore(first_builder, first_instr);
5283 } else {
5284 LLVMPositionBuilderAtEnd(first_builder, first_block);
5285 }
5286
5287 res = LLVMBuildAlloca(first_builder, type, name);
5288 LLVMBuildStore(builder, LLVMConstNull(type), res);
5289
5290 LLVMDisposeBuilder(first_builder);
5291
5292 return res;
5293 }
5294
5295 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5296 LLVMTypeRef type,
5297 const char *name)
5298 {
5299 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5300 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5301 return ptr;
5302 }
5303
5304 static void
5305 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5306 struct nir_variable *variable,
5307 struct nir_shader *shader,
5308 gl_shader_stage stage)
5309 {
5310 int idx = variable->data.location + variable->data.index;
5311 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5312 uint64_t mask_attribs;
5313
5314 variable->data.driver_location = idx * 4;
5315
5316 /* tess ctrl has it's own load/store paths for outputs */
5317 if (stage == MESA_SHADER_TESS_CTRL)
5318 return;
5319
5320 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5321 if (stage == MESA_SHADER_VERTEX ||
5322 stage == MESA_SHADER_TESS_EVAL ||
5323 stage == MESA_SHADER_GEOMETRY) {
5324 if (idx == VARYING_SLOT_CLIP_DIST0) {
5325 int length = shader->info.clip_distance_array_size +
5326 shader->info.cull_distance_array_size;
5327 if (stage == MESA_SHADER_VERTEX) {
5328 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5329 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5330 }
5331 if (stage == MESA_SHADER_TESS_EVAL) {
5332 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5333 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5334 }
5335
5336 if (length > 4)
5337 attrib_count = 2;
5338 else
5339 attrib_count = 1;
5340 mask_attribs = 1ull << idx;
5341 }
5342 }
5343
5344 ctx->output_mask |= mask_attribs;
5345 }
5346
5347 static void
5348 handle_shader_output_decl(struct ac_nir_context *ctx,
5349 struct nir_shader *nir,
5350 struct nir_variable *variable)
5351 {
5352 unsigned output_loc = variable->data.driver_location / 4;
5353 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5354
5355 /* tess ctrl has it's own load/store paths for outputs */
5356 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5357 return;
5358
5359 if (ctx->stage == MESA_SHADER_VERTEX ||
5360 ctx->stage == MESA_SHADER_TESS_EVAL ||
5361 ctx->stage == MESA_SHADER_GEOMETRY) {
5362 int idx = variable->data.location + variable->data.index;
5363 if (idx == VARYING_SLOT_CLIP_DIST0) {
5364 int length = nir->info.clip_distance_array_size +
5365 nir->info.cull_distance_array_size;
5366
5367 if (length > 4)
5368 attrib_count = 2;
5369 else
5370 attrib_count = 1;
5371 }
5372 }
5373
5374 for (unsigned i = 0; i < attrib_count; ++i) {
5375 for (unsigned chan = 0; chan < 4; chan++) {
5376 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5377 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5378 }
5379 }
5380 }
5381
5382 static LLVMTypeRef
5383 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5384 enum glsl_base_type type)
5385 {
5386 switch (type) {
5387 case GLSL_TYPE_INT:
5388 case GLSL_TYPE_UINT:
5389 case GLSL_TYPE_BOOL:
5390 case GLSL_TYPE_SUBROUTINE:
5391 return ctx->ac.i32;
5392 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5393 return ctx->ac.f32;
5394 case GLSL_TYPE_INT64:
5395 case GLSL_TYPE_UINT64:
5396 return ctx->ac.i64;
5397 case GLSL_TYPE_DOUBLE:
5398 return ctx->ac.f64;
5399 default:
5400 unreachable("unknown GLSL type");
5401 }
5402 }
5403
5404 static LLVMTypeRef
5405 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5406 const struct glsl_type *type)
5407 {
5408 if (glsl_type_is_scalar(type)) {
5409 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5410 }
5411
5412 if (glsl_type_is_vector(type)) {
5413 return LLVMVectorType(
5414 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5415 glsl_get_vector_elements(type));
5416 }
5417
5418 if (glsl_type_is_matrix(type)) {
5419 return LLVMArrayType(
5420 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5421 glsl_get_matrix_columns(type));
5422 }
5423
5424 if (glsl_type_is_array(type)) {
5425 return LLVMArrayType(
5426 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5427 glsl_get_length(type));
5428 }
5429
5430 assert(glsl_type_is_struct(type));
5431
5432 LLVMTypeRef member_types[glsl_get_length(type)];
5433
5434 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5435 member_types[i] =
5436 glsl_to_llvm_type(ctx,
5437 glsl_get_struct_field(type, i));
5438 }
5439
5440 return LLVMStructTypeInContext(ctx->context, member_types,
5441 glsl_get_length(type), false);
5442 }
5443
5444 static void
5445 setup_locals(struct ac_nir_context *ctx,
5446 struct nir_function *func)
5447 {
5448 int i, j;
5449 ctx->num_locals = 0;
5450 nir_foreach_variable(variable, &func->impl->locals) {
5451 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5452 variable->data.driver_location = ctx->num_locals * 4;
5453 ctx->num_locals += attrib_count;
5454 }
5455 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5456 if (!ctx->locals)
5457 return;
5458
5459 for (i = 0; i < ctx->num_locals; i++) {
5460 for (j = 0; j < 4; j++) {
5461 ctx->locals[i * 4 + j] =
5462 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5463 }
5464 }
5465 }
5466
5467 static void
5468 setup_shared(struct ac_nir_context *ctx,
5469 struct nir_shader *nir)
5470 {
5471 nir_foreach_variable(variable, &nir->shared) {
5472 LLVMValueRef shared =
5473 LLVMAddGlobalInAddressSpace(
5474 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5475 variable->name ? variable->name : "",
5476 LOCAL_ADDR_SPACE);
5477 _mesa_hash_table_insert(ctx->vars, variable, shared);
5478 }
5479 }
5480
5481 static LLVMValueRef
5482 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5483 {
5484 v = ac_to_float(ctx, v);
5485 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5486 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5487 }
5488
5489
5490 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5491 LLVMValueRef src0, LLVMValueRef src1)
5492 {
5493 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5494 LLVMValueRef comp[2];
5495
5496 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5497 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5498 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5499 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5500 }
5501
5502 /* Initialize arguments for the shader export intrinsic */
5503 static void
5504 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5505 LLVMValueRef *values,
5506 unsigned target,
5507 struct ac_export_args *args)
5508 {
5509 /* Default is 0xf. Adjusted below depending on the format. */
5510 args->enabled_channels = 0xf;
5511
5512 /* Specify whether the EXEC mask represents the valid mask */
5513 args->valid_mask = 0;
5514
5515 /* Specify whether this is the last export */
5516 args->done = 0;
5517
5518 /* Specify the target we are exporting */
5519 args->target = target;
5520
5521 args->compr = false;
5522 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5523 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5524 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5525 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5526
5527 if (!values)
5528 return;
5529
5530 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5531 LLVMValueRef val[4];
5532 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5533 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5534 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5535 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5536
5537 switch(col_format) {
5538 case V_028714_SPI_SHADER_ZERO:
5539 args->enabled_channels = 0; /* writemask */
5540 args->target = V_008DFC_SQ_EXP_NULL;
5541 break;
5542
5543 case V_028714_SPI_SHADER_32_R:
5544 args->enabled_channels = 1;
5545 args->out[0] = values[0];
5546 break;
5547
5548 case V_028714_SPI_SHADER_32_GR:
5549 args->enabled_channels = 0x3;
5550 args->out[0] = values[0];
5551 args->out[1] = values[1];
5552 break;
5553
5554 case V_028714_SPI_SHADER_32_AR:
5555 args->enabled_channels = 0x9;
5556 args->out[0] = values[0];
5557 args->out[3] = values[3];
5558 break;
5559
5560 case V_028714_SPI_SHADER_FP16_ABGR:
5561 args->compr = 1;
5562
5563 for (unsigned chan = 0; chan < 2; chan++) {
5564 LLVMValueRef pack_args[2] = {
5565 values[2 * chan],
5566 values[2 * chan + 1]
5567 };
5568 LLVMValueRef packed;
5569
5570 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5571 args->out[chan] = packed;
5572 }
5573 break;
5574
5575 case V_028714_SPI_SHADER_UNORM16_ABGR:
5576 for (unsigned chan = 0; chan < 4; chan++) {
5577 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5578 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5579 LLVMConstReal(ctx->ac.f32, 65535), "");
5580 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5581 LLVMConstReal(ctx->ac.f32, 0.5), "");
5582 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5583 ctx->ac.i32, "");
5584 }
5585
5586 args->compr = 1;
5587 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5588 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5589 break;
5590
5591 case V_028714_SPI_SHADER_SNORM16_ABGR:
5592 for (unsigned chan = 0; chan < 4; chan++) {
5593 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5594 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5595 LLVMConstReal(ctx->ac.f32, 32767), "");
5596
5597 /* If positive, add 0.5, else add -0.5. */
5598 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5599 LLVMBuildSelect(ctx->builder,
5600 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5601 val[chan], ctx->ac.f32_0, ""),
5602 LLVMConstReal(ctx->ac.f32, 0.5),
5603 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5604 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5605 }
5606
5607 args->compr = 1;
5608 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5609 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5610 break;
5611
5612 case V_028714_SPI_SHADER_UINT16_ABGR: {
5613 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5614 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5615 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5616
5617 for (unsigned chan = 0; chan < 4; chan++) {
5618 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5619 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5620 }
5621
5622 args->compr = 1;
5623 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5624 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5625 break;
5626 }
5627
5628 case V_028714_SPI_SHADER_SINT16_ABGR: {
5629 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5630 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5631 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5632 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5633 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5634 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5635
5636 /* Clamp. */
5637 for (unsigned chan = 0; chan < 4; chan++) {
5638 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5639 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5640 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5641 }
5642
5643 args->compr = 1;
5644 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5645 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5646 break;
5647 }
5648
5649 default:
5650 case V_028714_SPI_SHADER_32_ABGR:
5651 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5652 break;
5653 }
5654 } else
5655 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5656
5657 for (unsigned i = 0; i < 4; ++i)
5658 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5659 }
5660
5661 static void
5662 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5663 bool export_prim_id,
5664 struct ac_vs_output_info *outinfo)
5665 {
5666 uint32_t param_count = 0;
5667 unsigned target;
5668 unsigned pos_idx, num_pos_exports = 0;
5669 struct ac_export_args args, pos_args[4] = {};
5670 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5671 int i;
5672
5673 if (ctx->options->key.has_multiview_view_index) {
5674 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5675 if(!*tmp_out) {
5676 for(unsigned i = 0; i < 4; ++i)
5677 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5678 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5679 }
5680
5681 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5682 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5683 }
5684
5685 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5686 sizeof(outinfo->vs_output_param_offset));
5687
5688 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5689 LLVMValueRef slots[8];
5690 unsigned j;
5691
5692 if (outinfo->cull_dist_mask)
5693 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5694
5695 i = VARYING_SLOT_CLIP_DIST0;
5696 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5697 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5698 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5699
5700 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5701 slots[i] = LLVMGetUndef(ctx->ac.f32);
5702
5703 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5704 target = V_008DFC_SQ_EXP_POS + 3;
5705 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5706 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5707 &args, sizeof(args));
5708 }
5709
5710 target = V_008DFC_SQ_EXP_POS + 2;
5711 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5712 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5713 &args, sizeof(args));
5714
5715 }
5716
5717 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5718 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5719 for (unsigned j = 0; j < 4; j++)
5720 pos_values[j] = LLVMBuildLoad(ctx->builder,
5721 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5722 }
5723 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5724
5725 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5726 outinfo->writes_pointsize = true;
5727 psize_value = LLVMBuildLoad(ctx->builder,
5728 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5729 }
5730
5731 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5732 outinfo->writes_layer = true;
5733 layer_value = LLVMBuildLoad(ctx->builder,
5734 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5735 }
5736
5737 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5738 outinfo->writes_viewport_index = true;
5739 viewport_index_value = LLVMBuildLoad(ctx->builder,
5740 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5741 }
5742
5743 if (outinfo->writes_pointsize ||
5744 outinfo->writes_layer ||
5745 outinfo->writes_viewport_index) {
5746 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5747 (outinfo->writes_layer == true ? 4 : 0));
5748 pos_args[1].valid_mask = 0;
5749 pos_args[1].done = 0;
5750 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5751 pos_args[1].compr = 0;
5752 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5753 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5754 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5755 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5756
5757 if (outinfo->writes_pointsize == true)
5758 pos_args[1].out[0] = psize_value;
5759 if (outinfo->writes_layer == true)
5760 pos_args[1].out[2] = layer_value;
5761 if (outinfo->writes_viewport_index == true) {
5762 if (ctx->options->chip_class >= GFX9) {
5763 /* GFX9 has the layer in out.z[10:0] and the viewport
5764 * index in out.z[19:16].
5765 */
5766 LLVMValueRef v = viewport_index_value;
5767 v = ac_to_integer(&ctx->ac, v);
5768 v = LLVMBuildShl(ctx->builder, v,
5769 LLVMConstInt(ctx->ac.i32, 16, false),
5770 "");
5771 v = LLVMBuildOr(ctx->builder, v,
5772 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5773
5774 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5775 pos_args[1].enabled_channels |= 1 << 2;
5776 } else {
5777 pos_args[1].out[3] = viewport_index_value;
5778 pos_args[1].enabled_channels |= 1 << 3;
5779 }
5780 }
5781 }
5782 for (i = 0; i < 4; i++) {
5783 if (pos_args[i].out[0])
5784 num_pos_exports++;
5785 }
5786
5787 pos_idx = 0;
5788 for (i = 0; i < 4; i++) {
5789 if (!pos_args[i].out[0])
5790 continue;
5791
5792 /* Specify the target we are exporting */
5793 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5794 if (pos_idx == num_pos_exports)
5795 pos_args[i].done = 1;
5796 ac_build_export(&ctx->ac, &pos_args[i]);
5797 }
5798
5799 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5800 LLVMValueRef values[4];
5801 if (!(ctx->output_mask & (1ull << i)))
5802 continue;
5803
5804 for (unsigned j = 0; j < 4; j++)
5805 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5806 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5807
5808 if (i == VARYING_SLOT_LAYER) {
5809 target = V_008DFC_SQ_EXP_PARAM + param_count;
5810 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5811 param_count++;
5812 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5813 target = V_008DFC_SQ_EXP_PARAM + param_count;
5814 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5815 param_count++;
5816 } else if (i >= VARYING_SLOT_VAR0) {
5817 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5818 target = V_008DFC_SQ_EXP_PARAM + param_count;
5819 outinfo->vs_output_param_offset[i] = param_count;
5820 param_count++;
5821 } else
5822 continue;
5823
5824 si_llvm_init_export_args(ctx, values, target, &args);
5825
5826 if (target >= V_008DFC_SQ_EXP_POS &&
5827 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5828 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5829 &args, sizeof(args));
5830 } else {
5831 ac_build_export(&ctx->ac, &args);
5832 }
5833 }
5834
5835 if (export_prim_id) {
5836 LLVMValueRef values[4];
5837 target = V_008DFC_SQ_EXP_PARAM + param_count;
5838 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5839 param_count++;
5840
5841 values[0] = ctx->vs_prim_id;
5842 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5843 ctx->shader_info->vs.vgpr_comp_cnt);
5844 for (unsigned j = 1; j < 4; j++)
5845 values[j] = ctx->ac.f32_0;
5846 si_llvm_init_export_args(ctx, values, target, &args);
5847 ac_build_export(&ctx->ac, &args);
5848 outinfo->export_prim_id = true;
5849 }
5850
5851 outinfo->pos_exports = num_pos_exports;
5852 outinfo->param_exports = param_count;
5853 }
5854
5855 static void
5856 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5857 struct ac_es_output_info *outinfo)
5858 {
5859 int j;
5860 uint64_t max_output_written = 0;
5861 LLVMValueRef lds_base = NULL;
5862
5863 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5864 int param_index;
5865 int length = 4;
5866
5867 if (!(ctx->output_mask & (1ull << i)))
5868 continue;
5869
5870 if (i == VARYING_SLOT_CLIP_DIST0)
5871 length = ctx->num_output_clips + ctx->num_output_culls;
5872
5873 param_index = shader_io_get_unique_index(i);
5874
5875 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5876 }
5877
5878 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5879
5880 if (ctx->ac.chip_class >= GFX9) {
5881 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5882 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5883 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5884 LLVMConstInt(ctx->ac.i32, 24, false),
5885 LLVMConstInt(ctx->ac.i32, 4, false), false);
5886 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5887 LLVMBuildMul(ctx->ac.builder, wave_idx,
5888 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5889 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5890 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5891 }
5892
5893 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5894 LLVMValueRef dw_addr;
5895 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5896 int param_index;
5897 int length = 4;
5898
5899 if (!(ctx->output_mask & (1ull << i)))
5900 continue;
5901
5902 if (i == VARYING_SLOT_CLIP_DIST0)
5903 length = ctx->num_output_clips + ctx->num_output_culls;
5904
5905 param_index = shader_io_get_unique_index(i);
5906
5907 if (lds_base) {
5908 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5909 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
5910 "");
5911 }
5912 for (j = 0; j < length; j++) {
5913 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5914 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
5915
5916 if (ctx->ac.chip_class >= GFX9) {
5917 ac_lds_store(&ctx->ac, dw_addr,
5918 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5919 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5920 } else {
5921 ac_build_buffer_store_dword(&ctx->ac,
5922 ctx->esgs_ring,
5923 out_val, 1,
5924 NULL, ctx->es2gs_offset,
5925 (4 * param_index + j) * 4,
5926 1, 1, true, true);
5927 }
5928 }
5929 }
5930 }
5931
5932 static void
5933 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5934 {
5935 LLVMValueRef vertex_id = ctx->rel_auto_id;
5936 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5937 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5938 vertex_dw_stride, "");
5939
5940 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5941 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5942 int length = 4;
5943
5944 if (!(ctx->output_mask & (1ull << i)))
5945 continue;
5946
5947 if (i == VARYING_SLOT_CLIP_DIST0)
5948 length = ctx->num_output_clips + ctx->num_output_culls;
5949 int param = shader_io_get_unique_index(i);
5950 mark_tess_output(ctx, false, param);
5951 if (length > 4)
5952 mark_tess_output(ctx, false, param + 1);
5953 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5954 LLVMConstInt(ctx->ac.i32, param * 4, false),
5955 "");
5956 for (unsigned j = 0; j < length; j++) {
5957 ac_lds_store(&ctx->ac, dw_addr,
5958 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5959 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5960 }
5961 }
5962 }
5963
5964 struct ac_build_if_state
5965 {
5966 struct nir_to_llvm_context *ctx;
5967 LLVMValueRef condition;
5968 LLVMBasicBlockRef entry_block;
5969 LLVMBasicBlockRef true_block;
5970 LLVMBasicBlockRef false_block;
5971 LLVMBasicBlockRef merge_block;
5972 };
5973
5974 static LLVMBasicBlockRef
5975 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5976 {
5977 LLVMBasicBlockRef current_block;
5978 LLVMBasicBlockRef next_block;
5979 LLVMBasicBlockRef new_block;
5980
5981 /* get current basic block */
5982 current_block = LLVMGetInsertBlock(ctx->builder);
5983
5984 /* chqeck if there's another block after this one */
5985 next_block = LLVMGetNextBasicBlock(current_block);
5986 if (next_block) {
5987 /* insert the new block before the next block */
5988 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5989 }
5990 else {
5991 /* append new block after current block */
5992 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5993 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5994 }
5995 return new_block;
5996 }
5997
5998 static void
5999 ac_nir_build_if(struct ac_build_if_state *ifthen,
6000 struct nir_to_llvm_context *ctx,
6001 LLVMValueRef condition)
6002 {
6003 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6004
6005 memset(ifthen, 0, sizeof *ifthen);
6006 ifthen->ctx = ctx;
6007 ifthen->condition = condition;
6008 ifthen->entry_block = block;
6009
6010 /* create endif/merge basic block for the phi functions */
6011 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6012
6013 /* create/insert true_block before merge_block */
6014 ifthen->true_block =
6015 LLVMInsertBasicBlockInContext(ctx->context,
6016 ifthen->merge_block,
6017 "if-true-block");
6018
6019 /* successive code goes into the true block */
6020 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6021 }
6022
6023 /**
6024 * End a conditional.
6025 */
6026 static void
6027 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6028 {
6029 LLVMBuilderRef builder = ifthen->ctx->builder;
6030
6031 /* Insert branch to the merge block from current block */
6032 LLVMBuildBr(builder, ifthen->merge_block);
6033
6034 /*
6035 * Now patch in the various branch instructions.
6036 */
6037
6038 /* Insert the conditional branch instruction at the end of entry_block */
6039 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6040 if (ifthen->false_block) {
6041 /* we have an else clause */
6042 LLVMBuildCondBr(builder, ifthen->condition,
6043 ifthen->true_block, ifthen->false_block);
6044 }
6045 else {
6046 /* no else clause */
6047 LLVMBuildCondBr(builder, ifthen->condition,
6048 ifthen->true_block, ifthen->merge_block);
6049 }
6050
6051 /* Resume building code at end of the ifthen->merge_block */
6052 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6053 }
6054
6055 static void
6056 write_tess_factors(struct nir_to_llvm_context *ctx)
6057 {
6058 unsigned stride, outer_comps, inner_comps;
6059 struct ac_build_if_state if_ctx, inner_if_ctx;
6060 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6061 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6062 unsigned tess_inner_index, tess_outer_index;
6063 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6064 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6065 int i;
6066 emit_barrier(ctx);
6067
6068 switch (ctx->options->key.tcs.primitive_mode) {
6069 case GL_ISOLINES:
6070 stride = 2;
6071 outer_comps = 2;
6072 inner_comps = 0;
6073 break;
6074 case GL_TRIANGLES:
6075 stride = 4;
6076 outer_comps = 3;
6077 inner_comps = 1;
6078 break;
6079 case GL_QUADS:
6080 stride = 6;
6081 outer_comps = 4;
6082 inner_comps = 2;
6083 break;
6084 default:
6085 return;
6086 }
6087
6088 ac_nir_build_if(&if_ctx, ctx,
6089 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6090 invocation_id, ctx->ac.i32_0, ""));
6091
6092 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6093 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6094
6095 mark_tess_output(ctx, true, tess_inner_index);
6096 mark_tess_output(ctx, true, tess_outer_index);
6097 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6098 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6099 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6100 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6101 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6102
6103 for (i = 0; i < 4; i++) {
6104 inner[i] = LLVMGetUndef(ctx->ac.i32);
6105 outer[i] = LLVMGetUndef(ctx->ac.i32);
6106 }
6107
6108 // LINES reverseal
6109 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6110 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6111 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6112 ctx->ac.i32_1, "");
6113 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6114 } else {
6115 for (i = 0; i < outer_comps; i++) {
6116 outer[i] = out[i] =
6117 ac_lds_load(&ctx->ac, lds_outer);
6118 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6119 ctx->ac.i32_1, "");
6120 }
6121 for (i = 0; i < inner_comps; i++) {
6122 inner[i] = out[outer_comps+i] =
6123 ac_lds_load(&ctx->ac, lds_inner);
6124 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6125 ctx->ac.i32_1, "");
6126 }
6127 }
6128
6129 /* Convert the outputs to vectors for stores. */
6130 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6131 vec1 = NULL;
6132
6133 if (stride > 4)
6134 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6135
6136
6137 buffer = ctx->hs_ring_tess_factor;
6138 tf_base = ctx->tess_factor_offset;
6139 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6140 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6141 unsigned tf_offset = 0;
6142
6143 if (ctx->options->chip_class <= VI) {
6144 ac_nir_build_if(&inner_if_ctx, ctx,
6145 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6146 rel_patch_id, ctx->ac.i32_0, ""));
6147
6148 /* Store the dynamic HS control word. */
6149 ac_build_buffer_store_dword(&ctx->ac, buffer,
6150 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6151 1, ctx->ac.i32_0, tf_base,
6152 0, 1, 0, true, false);
6153 tf_offset += 4;
6154
6155 ac_nir_build_endif(&inner_if_ctx);
6156 }
6157
6158 /* Store the tessellation factors. */
6159 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6160 MIN2(stride, 4), byteoffset, tf_base,
6161 tf_offset, 1, 0, true, false);
6162 if (vec1)
6163 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6164 stride - 4, byteoffset, tf_base,
6165 16 + tf_offset, 1, 0, true, false);
6166
6167 //store to offchip for TES to read - only if TES reads them
6168 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6169 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6170 LLVMValueRef tf_inner_offset;
6171 unsigned param_outer, param_inner;
6172
6173 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6174 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6175 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6176
6177 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6178 util_next_power_of_two(outer_comps));
6179
6180 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6181 outer_comps, tf_outer_offset,
6182 ctx->oc_lds, 0, 1, 0, true, false);
6183 if (inner_comps) {
6184 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6185 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6186 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6187
6188 inner_vec = inner_comps == 1 ? inner[0] :
6189 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6190 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6191 inner_comps, tf_inner_offset,
6192 ctx->oc_lds, 0, 1, 0, true, false);
6193 }
6194 }
6195 ac_nir_build_endif(&if_ctx);
6196 }
6197
6198 static void
6199 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6200 {
6201 write_tess_factors(ctx);
6202 }
6203
6204 static bool
6205 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6206 LLVMValueRef *color, unsigned param, bool is_last,
6207 struct ac_export_args *args)
6208 {
6209 /* Export */
6210 si_llvm_init_export_args(ctx, color, param,
6211 args);
6212
6213 if (is_last) {
6214 args->valid_mask = 1; /* whether the EXEC mask is valid */
6215 args->done = 1; /* DONE bit */
6216 } else if (!args->enabled_channels)
6217 return false; /* unnecessary NULL export */
6218
6219 return true;
6220 }
6221
6222 static void
6223 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6224 LLVMValueRef depth, LLVMValueRef stencil,
6225 LLVMValueRef samplemask)
6226 {
6227 struct ac_export_args args;
6228
6229 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6230
6231 ac_build_export(&ctx->ac, &args);
6232 }
6233
6234 static void
6235 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6236 {
6237 unsigned index = 0;
6238 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6239 struct ac_export_args color_args[8];
6240
6241 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6242 LLVMValueRef values[4];
6243
6244 if (!(ctx->output_mask & (1ull << i)))
6245 continue;
6246
6247 if (i == FRAG_RESULT_DEPTH) {
6248 ctx->shader_info->fs.writes_z = true;
6249 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6250 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6251 } else if (i == FRAG_RESULT_STENCIL) {
6252 ctx->shader_info->fs.writes_stencil = true;
6253 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6254 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6255 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6256 ctx->shader_info->fs.writes_sample_mask = true;
6257 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6258 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6259 } else {
6260 bool last = false;
6261 for (unsigned j = 0; j < 4; j++)
6262 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6263 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6264
6265 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6266 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6267
6268 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6269 if (ret)
6270 index++;
6271 }
6272 }
6273
6274 for (unsigned i = 0; i < index; i++)
6275 ac_build_export(&ctx->ac, &color_args[i]);
6276 if (depth || stencil || samplemask)
6277 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6278 else if (!index) {
6279 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6280 ac_build_export(&ctx->ac, &color_args[0]);
6281 }
6282
6283 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6284 }
6285
6286 static void
6287 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6288 {
6289 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6290 }
6291
6292 static void
6293 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6294 LLVMValueRef *addrs)
6295 {
6296 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6297
6298 switch (ctx->stage) {
6299 case MESA_SHADER_VERTEX:
6300 if (ctx->options->key.vs.as_ls)
6301 handle_ls_outputs_post(ctx);
6302 else if (ctx->options->key.vs.as_es)
6303 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6304 else
6305 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6306 &ctx->shader_info->vs.outinfo);
6307 break;
6308 case MESA_SHADER_FRAGMENT:
6309 handle_fs_outputs_post(ctx);
6310 break;
6311 case MESA_SHADER_GEOMETRY:
6312 emit_gs_epilogue(ctx);
6313 break;
6314 case MESA_SHADER_TESS_CTRL:
6315 handle_tcs_outputs_post(ctx);
6316 break;
6317 case MESA_SHADER_TESS_EVAL:
6318 if (ctx->options->key.tes.as_es)
6319 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6320 else
6321 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6322 &ctx->shader_info->tes.outinfo);
6323 break;
6324 default:
6325 break;
6326 }
6327 }
6328
6329 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6330 {
6331 LLVMPassManagerRef passmgr;
6332 /* Create the pass manager */
6333 passmgr = LLVMCreateFunctionPassManagerForModule(
6334 ctx->module);
6335
6336 /* This pass should eliminate all the load and store instructions */
6337 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6338
6339 /* Add some optimization passes */
6340 LLVMAddScalarReplAggregatesPass(passmgr);
6341 LLVMAddLICMPass(passmgr);
6342 LLVMAddAggressiveDCEPass(passmgr);
6343 LLVMAddCFGSimplificationPass(passmgr);
6344 LLVMAddInstructionCombiningPass(passmgr);
6345
6346 /* Run the pass */
6347 LLVMInitializeFunctionPassManager(passmgr);
6348 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6349 LLVMFinalizeFunctionPassManager(passmgr);
6350
6351 LLVMDisposeBuilder(ctx->builder);
6352 LLVMDisposePassManager(passmgr);
6353 }
6354
6355 static void
6356 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6357 {
6358 struct ac_vs_output_info *outinfo;
6359
6360 switch (ctx->stage) {
6361 case MESA_SHADER_FRAGMENT:
6362 case MESA_SHADER_COMPUTE:
6363 case MESA_SHADER_TESS_CTRL:
6364 case MESA_SHADER_GEOMETRY:
6365 return;
6366 case MESA_SHADER_VERTEX:
6367 if (ctx->options->key.vs.as_ls ||
6368 ctx->options->key.vs.as_es)
6369 return;
6370 outinfo = &ctx->shader_info->vs.outinfo;
6371 break;
6372 case MESA_SHADER_TESS_EVAL:
6373 if (ctx->options->key.vs.as_es)
6374 return;
6375 outinfo = &ctx->shader_info->tes.outinfo;
6376 break;
6377 default:
6378 unreachable("Unhandled shader type");
6379 }
6380
6381 ac_optimize_vs_outputs(&ctx->ac,
6382 ctx->main_function,
6383 outinfo->vs_output_param_offset,
6384 VARYING_SLOT_MAX,
6385 &outinfo->param_exports);
6386 }
6387
6388 static void
6389 ac_setup_rings(struct nir_to_llvm_context *ctx)
6390 {
6391 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6392 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6393 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6394 }
6395
6396 if (ctx->is_gs_copy_shader) {
6397 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6398 }
6399 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6400 LLVMValueRef tmp;
6401 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6402 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6403
6404 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6405
6406 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6407 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6408 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6409 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6410 }
6411
6412 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6413 ctx->stage == MESA_SHADER_TESS_EVAL) {
6414 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6415 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6416 }
6417 }
6418
6419 static unsigned
6420 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6421 const struct nir_shader *nir)
6422 {
6423 switch (nir->info.stage) {
6424 case MESA_SHADER_TESS_CTRL:
6425 return chip_class >= CIK ? 128 : 64;
6426 case MESA_SHADER_GEOMETRY:
6427 return chip_class >= GFX9 ? 128 : 64;
6428 case MESA_SHADER_COMPUTE:
6429 break;
6430 default:
6431 return 0;
6432 }
6433
6434 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6435 nir->info.cs.local_size[1] *
6436 nir->info.cs.local_size[2];
6437 return max_workgroup_size;
6438 }
6439
6440 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6441 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6442 {
6443 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6444 LLVMConstInt(ctx->ac.i32, 8, false),
6445 LLVMConstInt(ctx->ac.i32, 8, false), false);
6446 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6447 ctx->ac.i32_0, "");
6448 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6449 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6450 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6451 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6452 }
6453
6454 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6455 {
6456 for(int i = 5; i >= 0; --i) {
6457 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6458 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6459 LLVMConstInt(ctx->ac.i32, 16, false), false);
6460 }
6461
6462 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6463 LLVMConstInt(ctx->ac.i32, 16, false),
6464 LLVMConstInt(ctx->ac.i32, 8, false), false);
6465 }
6466
6467 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6468 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6469 {
6470 struct ac_nir_context ctx = {};
6471 struct nir_function *func;
6472
6473 ctx.ac = *ac;
6474 ctx.abi = abi;
6475
6476 ctx.nctx = nctx;
6477 if (nctx)
6478 nctx->nir = &ctx;
6479
6480 ctx.stage = nir->info.stage;
6481
6482 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6483
6484 nir_foreach_variable(variable, &nir->outputs)
6485 handle_shader_output_decl(&ctx, nir, variable);
6486
6487 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6488 _mesa_key_pointer_equal);
6489 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6490 _mesa_key_pointer_equal);
6491 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6492 _mesa_key_pointer_equal);
6493
6494 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6495
6496 setup_locals(&ctx, func);
6497
6498 if (nir->info.stage == MESA_SHADER_COMPUTE)
6499 setup_shared(&ctx, nir);
6500
6501 visit_cf_list(&ctx, &func->impl->body);
6502 phi_post_pass(&ctx);
6503
6504 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6505 ctx.outputs);
6506
6507 free(ctx.locals);
6508 ralloc_free(ctx.defs);
6509 ralloc_free(ctx.phis);
6510 ralloc_free(ctx.vars);
6511
6512 if (nctx)
6513 nctx->nir = NULL;
6514 }
6515
6516 static
6517 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6518 struct nir_shader *const *shaders,
6519 int shader_count,
6520 struct ac_shader_variant_info *shader_info,
6521 const struct ac_nir_compiler_options *options)
6522 {
6523 struct nir_to_llvm_context ctx = {0};
6524 unsigned i;
6525 ctx.options = options;
6526 ctx.shader_info = shader_info;
6527 ctx.context = LLVMContextCreate();
6528 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6529
6530 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6531 options->family);
6532 ctx.ac.module = ctx.module;
6533 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6534
6535 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6536 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6537 LLVMSetDataLayout(ctx.module, data_layout_str);
6538 LLVMDisposeTargetData(data_layout);
6539 LLVMDisposeMessage(data_layout_str);
6540
6541 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6542 ctx.ac.builder = ctx.builder;
6543
6544 memset(shader_info, 0, sizeof(*shader_info));
6545
6546 for(int i = 0; i < shader_count; ++i)
6547 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6548
6549 for (i = 0; i < AC_UD_MAX_SETS; i++)
6550 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6551 for (i = 0; i < AC_UD_MAX_UD; i++)
6552 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6553
6554 ctx.max_workgroup_size = 0;
6555 for (int i = 0; i < shader_count; ++i) {
6556 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6557 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6558 shaders[i]));
6559 }
6560
6561 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6562 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6563
6564 ctx.abi.inputs = &ctx.inputs[0];
6565 ctx.abi.emit_outputs = handle_shader_outputs_post;
6566 ctx.abi.emit_vertex = visit_emit_vertex;
6567 ctx.abi.load_ubo = radv_load_ubo;
6568 ctx.abi.load_ssbo = radv_load_ssbo;
6569 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6570 ctx.abi.clamp_shadow_reference = false;
6571
6572 if (shader_count >= 2)
6573 ac_init_exec_full_mask(&ctx.ac);
6574
6575 if (ctx.ac.chip_class == GFX9 &&
6576 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6577 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6578
6579 for(int i = 0; i < shader_count; ++i) {
6580 ctx.stage = shaders[i]->info.stage;
6581 ctx.output_mask = 0;
6582 ctx.tess_outputs_written = 0;
6583 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6584 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6585
6586 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6587 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6588 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6589 ctx.abi.load_inputs = load_gs_input;
6590 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6591 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6592 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6593 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6594 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6595 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6596 if (shader_info->info.vs.needs_instance_id) {
6597 ctx.shader_info->vs.vgpr_comp_cnt =
6598 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6599 }
6600 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6601 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6602 }
6603
6604 if (i)
6605 emit_barrier(&ctx);
6606
6607 ac_setup_rings(&ctx);
6608
6609 LLVMBasicBlockRef merge_block;
6610 if (shader_count >= 2) {
6611 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6612 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6613 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6614
6615 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6616 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6617 LLVMConstInt(ctx.ac.i32, 8, false), false);
6618 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6619 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6620 thread_id, count, "");
6621 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6622
6623 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6624 }
6625
6626 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6627 handle_fs_inputs(&ctx, shaders[i]);
6628 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6629 handle_vs_inputs(&ctx, shaders[i]);
6630 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6631 prepare_gs_input_vgprs(&ctx);
6632
6633 nir_foreach_variable(variable, &shaders[i]->outputs)
6634 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6635
6636 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6637
6638 if (shader_count >= 2) {
6639 LLVMBuildBr(ctx.ac.builder, merge_block);
6640 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6641 }
6642
6643 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6644 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6645 shaders[i]->info.cull_distance_array_size > 4;
6646 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6647 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6648 shaders[i]->info.gs.vertices_out;
6649 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6650 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6651 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6652 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6653 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6654 }
6655 }
6656
6657 LLVMBuildRetVoid(ctx.builder);
6658
6659 ac_llvm_finalize_module(&ctx);
6660
6661 if (shader_count == 1)
6662 ac_nir_eliminate_const_vs_outputs(&ctx);
6663
6664 return ctx.module;
6665 }
6666
6667 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6668 {
6669 unsigned *retval = (unsigned *)context;
6670 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6671 char *description = LLVMGetDiagInfoDescription(di);
6672
6673 if (severity == LLVMDSError) {
6674 *retval = 1;
6675 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6676 description);
6677 }
6678
6679 LLVMDisposeMessage(description);
6680 }
6681
6682 static unsigned ac_llvm_compile(LLVMModuleRef M,
6683 struct ac_shader_binary *binary,
6684 LLVMTargetMachineRef tm)
6685 {
6686 unsigned retval = 0;
6687 char *err;
6688 LLVMContextRef llvm_ctx;
6689 LLVMMemoryBufferRef out_buffer;
6690 unsigned buffer_size;
6691 const char *buffer_data;
6692 LLVMBool mem_err;
6693
6694 /* Setup Diagnostic Handler*/
6695 llvm_ctx = LLVMGetModuleContext(M);
6696
6697 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6698 &retval);
6699
6700 /* Compile IR*/
6701 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6702 &err, &out_buffer);
6703
6704 /* Process Errors/Warnings */
6705 if (mem_err) {
6706 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6707 free(err);
6708 retval = 1;
6709 goto out;
6710 }
6711
6712 /* Extract Shader Code*/
6713 buffer_size = LLVMGetBufferSize(out_buffer);
6714 buffer_data = LLVMGetBufferStart(out_buffer);
6715
6716 ac_elf_read(buffer_data, buffer_size, binary);
6717
6718 /* Clean up */
6719 LLVMDisposeMemoryBuffer(out_buffer);
6720
6721 out:
6722 return retval;
6723 }
6724
6725 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6726 LLVMModuleRef llvm_module,
6727 struct ac_shader_binary *binary,
6728 struct ac_shader_config *config,
6729 struct ac_shader_variant_info *shader_info,
6730 gl_shader_stage stage,
6731 bool dump_shader, bool supports_spill)
6732 {
6733 if (dump_shader)
6734 ac_dump_module(llvm_module);
6735
6736 memset(binary, 0, sizeof(*binary));
6737 int v = ac_llvm_compile(llvm_module, binary, tm);
6738 if (v) {
6739 fprintf(stderr, "compile failed\n");
6740 }
6741
6742 if (dump_shader)
6743 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6744
6745 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6746
6747 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6748 LLVMDisposeModule(llvm_module);
6749 LLVMContextDispose(ctx);
6750
6751 if (stage == MESA_SHADER_FRAGMENT) {
6752 shader_info->num_input_vgprs = 0;
6753 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6754 shader_info->num_input_vgprs += 2;
6755 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6756 shader_info->num_input_vgprs += 2;
6757 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6758 shader_info->num_input_vgprs += 2;
6759 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6760 shader_info->num_input_vgprs += 3;
6761 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6762 shader_info->num_input_vgprs += 2;
6763 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6764 shader_info->num_input_vgprs += 2;
6765 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6766 shader_info->num_input_vgprs += 2;
6767 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6768 shader_info->num_input_vgprs += 1;
6769 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6770 shader_info->num_input_vgprs += 1;
6771 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6772 shader_info->num_input_vgprs += 1;
6773 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6774 shader_info->num_input_vgprs += 1;
6775 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6776 shader_info->num_input_vgprs += 1;
6777 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6778 shader_info->num_input_vgprs += 1;
6779 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6780 shader_info->num_input_vgprs += 1;
6781 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6782 shader_info->num_input_vgprs += 1;
6783 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6784 shader_info->num_input_vgprs += 1;
6785 }
6786 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6787
6788 /* +3 for scratch wave offset and VCC */
6789 config->num_sgprs = MAX2(config->num_sgprs,
6790 shader_info->num_input_sgprs + 3);
6791 }
6792
6793 static void
6794 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6795 {
6796 switch (nir->info.stage) {
6797 case MESA_SHADER_COMPUTE:
6798 for (int i = 0; i < 3; ++i)
6799 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6800 break;
6801 case MESA_SHADER_FRAGMENT:
6802 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6803 break;
6804 case MESA_SHADER_GEOMETRY:
6805 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6806 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6807 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6808 shader_info->gs.invocations = nir->info.gs.invocations;
6809 break;
6810 case MESA_SHADER_TESS_EVAL:
6811 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6812 shader_info->tes.spacing = nir->info.tess.spacing;
6813 shader_info->tes.ccw = nir->info.tess.ccw;
6814 shader_info->tes.point_mode = nir->info.tess.point_mode;
6815 shader_info->tes.as_es = options->key.tes.as_es;
6816 break;
6817 case MESA_SHADER_TESS_CTRL:
6818 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6819 break;
6820 case MESA_SHADER_VERTEX:
6821 shader_info->vs.as_es = options->key.vs.as_es;
6822 shader_info->vs.as_ls = options->key.vs.as_ls;
6823 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6824 if (options->key.vs.as_ls)
6825 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6826 break;
6827 default:
6828 break;
6829 }
6830 }
6831
6832 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6833 struct ac_shader_binary *binary,
6834 struct ac_shader_config *config,
6835 struct ac_shader_variant_info *shader_info,
6836 struct nir_shader *const *nir,
6837 int nir_count,
6838 const struct ac_nir_compiler_options *options,
6839 bool dump_shader)
6840 {
6841
6842 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6843 options);
6844
6845 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6846 for (int i = 0; i < nir_count; ++i)
6847 ac_fill_shader_info(shader_info, nir[i], options);
6848 }
6849
6850 static void
6851 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6852 {
6853 LLVMValueRef args[9];
6854 args[0] = ctx->gsvs_ring;
6855 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6856 args[3] = ctx->ac.i32_0;
6857 args[4] = ctx->ac.i32_1; /* OFFEN */
6858 args[5] = ctx->ac.i32_0; /* IDXEN */
6859 args[6] = ctx->ac.i32_1; /* GLC */
6860 args[7] = ctx->ac.i32_1; /* SLC */
6861 args[8] = ctx->ac.i32_0; /* TFE */
6862
6863 int idx = 0;
6864
6865 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6866 int length = 4;
6867 int slot = idx;
6868 int slot_inc = 1;
6869 if (!(ctx->output_mask & (1ull << i)))
6870 continue;
6871
6872 if (i == VARYING_SLOT_CLIP_DIST0) {
6873 /* unpack clip and cull from a single set of slots */
6874 length = ctx->num_output_clips + ctx->num_output_culls;
6875 if (length > 4)
6876 slot_inc = 2;
6877 }
6878
6879 for (unsigned j = 0; j < length; j++) {
6880 LLVMValueRef value;
6881 args[2] = LLVMConstInt(ctx->ac.i32,
6882 (slot * 4 + j) *
6883 ctx->gs_max_out_vertices * 16 * 4, false);
6884
6885 value = ac_build_intrinsic(&ctx->ac,
6886 "llvm.SI.buffer.load.dword.i32.i32",
6887 ctx->ac.i32, args, 9,
6888 AC_FUNC_ATTR_READONLY |
6889 AC_FUNC_ATTR_LEGACY);
6890
6891 LLVMBuildStore(ctx->builder,
6892 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6893 }
6894 idx += slot_inc;
6895 }
6896 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6897 }
6898
6899 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6900 struct nir_shader *geom_shader,
6901 struct ac_shader_binary *binary,
6902 struct ac_shader_config *config,
6903 struct ac_shader_variant_info *shader_info,
6904 const struct ac_nir_compiler_options *options,
6905 bool dump_shader)
6906 {
6907 struct nir_to_llvm_context ctx = {0};
6908 ctx.context = LLVMContextCreate();
6909 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6910 ctx.options = options;
6911 ctx.shader_info = shader_info;
6912
6913 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6914 options->family);
6915 ctx.ac.module = ctx.module;
6916
6917 ctx.is_gs_copy_shader = true;
6918 LLVMSetTarget(ctx.module, "amdgcn--");
6919
6920 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6921 ctx.ac.builder = ctx.builder;
6922 ctx.stage = MESA_SHADER_VERTEX;
6923
6924 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
6925
6926 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6927 ac_setup_rings(&ctx);
6928
6929 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6930 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6931
6932 struct ac_nir_context nir_ctx = {};
6933 nir_ctx.ac = ctx.ac;
6934 nir_ctx.abi = &ctx.abi;
6935
6936 nir_ctx.nctx = &ctx;
6937 ctx.nir = &nir_ctx;
6938
6939 nir_foreach_variable(variable, &geom_shader->outputs) {
6940 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
6941 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6942 }
6943
6944 ac_gs_copy_shader_emit(&ctx);
6945
6946 ctx.nir = NULL;
6947
6948 LLVMBuildRetVoid(ctx.builder);
6949
6950 ac_llvm_finalize_module(&ctx);
6951
6952 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6953 MESA_SHADER_VERTEX,
6954 dump_shader, options->supports_spill);
6955 }