projects / mesa.git / blob
? search:


b58bae90c5dc3bf5ba962f3f66d1c9dce7d60928
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 RADEON_LLVM_AMDGPU_HS = 93,
43 };
44
45 #define CONST_ADDR_SPACE 2
46 #define LOCAL_ADDR_SPACE 3
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
50
51 struct nir_to_llvm_context;
52
53 struct ac_nir_context {
54 struct ac_llvm_context ac;
55 struct ac_shader_abi *abi;
56
57 gl_shader_stage stage;
58
59 struct hash_table *defs;
60 struct hash_table *phis;
61 struct hash_table *vars;
62
63 LLVMValueRef main_function;
64 LLVMBasicBlockRef continue_block;
65 LLVMBasicBlockRef break_block;
66
67 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
68
69 int num_locals;
70 LLVMValueRef *locals;
71
72 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
73 };
74
75 struct nir_to_llvm_context {
76 struct ac_llvm_context ac;
77 const struct ac_nir_compiler_options *options;
78 struct ac_shader_variant_info *shader_info;
79 struct ac_shader_abi abi;
80 struct ac_nir_context *nir;
81
82 unsigned max_workgroup_size;
83 LLVMContextRef context;
84 LLVMModuleRef module;
85 LLVMBuilderRef builder;
86 LLVMValueRef main_function;
87
88 struct hash_table *defs;
89 struct hash_table *phis;
90
91 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
92 LLVMValueRef ring_offsets;
93 LLVMValueRef push_constants;
94 LLVMValueRef view_index;
95 LLVMValueRef num_work_groups;
96 LLVMValueRef workgroup_ids;
97 LLVMValueRef local_invocation_ids;
98 LLVMValueRef tg_size;
99
100 LLVMValueRef vertex_buffers;
101 LLVMValueRef rel_auto_id;
102 LLVMValueRef vs_prim_id;
103 LLVMValueRef ls_out_layout;
104 LLVMValueRef es2gs_offset;
105
106 LLVMValueRef tcs_offchip_layout;
107 LLVMValueRef tcs_out_offsets;
108 LLVMValueRef tcs_out_layout;
109 LLVMValueRef tcs_in_layout;
110 LLVMValueRef oc_lds;
111 LLVMValueRef merged_wave_info;
112 LLVMValueRef tess_factor_offset;
113 LLVMValueRef tcs_patch_id;
114 LLVMValueRef tcs_rel_ids;
115 LLVMValueRef tes_rel_patch_id;
116 LLVMValueRef tes_patch_id;
117 LLVMValueRef tes_u;
118 LLVMValueRef tes_v;
119
120 LLVMValueRef gsvs_ring_stride;
121 LLVMValueRef gsvs_num_entries;
122 LLVMValueRef gs2vs_offset;
123 LLVMValueRef gs_wave_id;
124 LLVMValueRef gs_vtx_offset[6];
125
126 LLVMValueRef esgs_ring;
127 LLVMValueRef gsvs_ring;
128 LLVMValueRef hs_ring_tess_offchip;
129 LLVMValueRef hs_ring_tess_factor;
130
131 LLVMValueRef prim_mask;
132 LLVMValueRef sample_pos_offset;
133 LLVMValueRef persp_sample, persp_center, persp_centroid;
134 LLVMValueRef linear_sample, linear_center, linear_centroid;
135
136 gl_shader_stage stage;
137
138 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
139
140 uint64_t input_mask;
141 uint64_t output_mask;
142 uint8_t num_output_clips;
143 uint8_t num_output_culls;
144
145 bool is_gs_copy_shader;
146 LLVMValueRef gs_next_vertex;
147 unsigned gs_max_out_vertices;
148
149 unsigned tes_primitive_mode;
150 uint64_t tess_outputs_written;
151 uint64_t tess_patch_outputs_written;
152
153 uint32_t tcs_patch_outputs_read;
154 uint64_t tcs_outputs_read;
155 };
156
157 static inline struct nir_to_llvm_context *
158 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
159 {
160 struct nir_to_llvm_context *ctx = NULL;
161 return container_of(abi, ctx, abi);
162 }
163
164 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
165 const nir_deref_var *deref,
166 enum ac_descriptor_type desc_type,
167 const nir_tex_instr *instr,
168 bool image, bool write);
169
170 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
171 {
172 return (index * 4) + chan;
173 }
174
175 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
176 {
177 /* handle patch indices separate */
178 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
179 return 0;
180 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
181 return 1;
182 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
183 return 2 + (slot - VARYING_SLOT_PATCH0);
184
185 if (slot == VARYING_SLOT_POS)
186 return 0;
187 if (slot == VARYING_SLOT_PSIZ)
188 return 1;
189 if (slot == VARYING_SLOT_CLIP_DIST0)
190 return 2;
191 /* 3 is reserved for clip dist as well */
192 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
193 return 4 + (slot - VARYING_SLOT_VAR0);
194 unreachable("illegal slot in get unique index\n");
195 }
196
197 static void set_llvm_calling_convention(LLVMValueRef func,
198 gl_shader_stage stage)
199 {
200 enum radeon_llvm_calling_convention calling_conv;
201
202 switch (stage) {
203 case MESA_SHADER_VERTEX:
204 case MESA_SHADER_TESS_EVAL:
205 calling_conv = RADEON_LLVM_AMDGPU_VS;
206 break;
207 case MESA_SHADER_GEOMETRY:
208 calling_conv = RADEON_LLVM_AMDGPU_GS;
209 break;
210 case MESA_SHADER_TESS_CTRL:
211 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
212 break;
213 case MESA_SHADER_FRAGMENT:
214 calling_conv = RADEON_LLVM_AMDGPU_PS;
215 break;
216 case MESA_SHADER_COMPUTE:
217 calling_conv = RADEON_LLVM_AMDGPU_CS;
218 break;
219 default:
220 unreachable("Unhandle shader type");
221 }
222
223 LLVMSetFunctionCallConv(func, calling_conv);
224 }
225
226 #define MAX_ARGS 23
227 struct arg_info {
228 LLVMTypeRef types[MAX_ARGS];
229 LLVMValueRef *assign[MAX_ARGS];
230 unsigned array_params_mask;
231 uint8_t count;
232 uint8_t user_sgpr_count;
233 uint8_t sgpr_count;
234 uint8_t num_user_sgprs_used;
235 uint8_t num_sgprs_used;
236 uint8_t num_vgprs_used;
237 };
238
239 static inline void
240 add_argument(struct arg_info *info,
241 LLVMTypeRef type, LLVMValueRef *param_ptr)
242 {
243 assert(info->count < MAX_ARGS);
244 info->assign[info->count] = param_ptr;
245 info->types[info->count] = type;
246 info->count++;
247 }
248
249 static inline void
250 add_sgpr_argument(struct arg_info *info,
251 LLVMTypeRef type, LLVMValueRef *param_ptr)
252 {
253 add_argument(info, type, param_ptr);
254 info->num_sgprs_used += ac_get_type_size(type) / 4;
255 info->sgpr_count++;
256 }
257
258 static inline void
259 add_user_sgpr_argument(struct arg_info *info,
260 LLVMTypeRef type,
261 LLVMValueRef *param_ptr)
262 {
263 add_sgpr_argument(info, type, param_ptr);
264 info->num_user_sgprs_used += ac_get_type_size(type) / 4;
265 info->user_sgpr_count++;
266 }
267
268 static inline void
269 add_vgpr_argument(struct arg_info *info,
270 LLVMTypeRef type,
271 LLVMValueRef *param_ptr)
272 {
273 add_argument(info, type, param_ptr);
274 info->num_vgprs_used += ac_get_type_size(type) / 4;
275 }
276
277 static inline void
278 add_user_sgpr_array_argument(struct arg_info *info,
279 LLVMTypeRef type,
280 LLVMValueRef *param_ptr)
281 {
282 info->array_params_mask |= (1 << info->count);
283 add_user_sgpr_argument(info, type, param_ptr);
284 }
285
286 static void assign_arguments(LLVMValueRef main_function,
287 struct arg_info *info)
288 {
289 unsigned i;
290 for (i = 0; i < info->count; i++) {
291 if (info->assign[i])
292 *info->assign[i] = LLVMGetParam(main_function, i);
293 }
294 }
295
296 static LLVMValueRef
297 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
298 LLVMBuilderRef builder, LLVMTypeRef *return_types,
299 unsigned num_return_elems,
300 struct arg_info *args,
301 unsigned max_workgroup_size,
302 bool unsafe_math)
303 {
304 LLVMTypeRef main_function_type, ret_type;
305 LLVMBasicBlockRef main_function_body;
306
307 if (num_return_elems)
308 ret_type = LLVMStructTypeInContext(ctx, return_types,
309 num_return_elems, true);
310 else
311 ret_type = LLVMVoidTypeInContext(ctx);
312
313 /* Setup the function */
314 main_function_type =
315 LLVMFunctionType(ret_type, args->types, args->count, 0);
316 LLVMValueRef main_function =
317 LLVMAddFunction(module, "main", main_function_type);
318 main_function_body =
319 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
320 LLVMPositionBuilderAtEnd(builder, main_function_body);
321
322 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
323 for (unsigned i = 0; i < args->sgpr_count; ++i) {
324 if (args->array_params_mask & (1 << i)) {
325 LLVMValueRef P = LLVMGetParam(main_function, i);
326 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
327 ac_add_attr_dereferenceable(P, UINT64_MAX);
328 }
329 else {
330 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
331 }
332 }
333
334 if (max_workgroup_size) {
335 ac_llvm_add_target_dep_function_attr(main_function,
336 "amdgpu-max-work-group-size",
337 max_workgroup_size);
338 }
339 if (unsafe_math) {
340 /* These were copied from some LLVM test. */
341 LLVMAddTargetDependentFunctionAttr(main_function,
342 "less-precise-fpmad",
343 "true");
344 LLVMAddTargetDependentFunctionAttr(main_function,
345 "no-infs-fp-math",
346 "true");
347 LLVMAddTargetDependentFunctionAttr(main_function,
348 "no-nans-fp-math",
349 "true");
350 LLVMAddTargetDependentFunctionAttr(main_function,
351 "unsafe-fp-math",
352 "true");
353 }
354 return main_function;
355 }
356
357 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
358 {
359 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
360 CONST_ADDR_SPACE);
361 }
362
363 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
364 {
365 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
366 type = LLVMGetElementType(type);
367
368 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
369 return LLVMGetIntTypeWidth(type);
370
371 if (type == ctx->f16)
372 return 16;
373 if (type == ctx->f32)
374 return 32;
375 if (type == ctx->f64)
376 return 64;
377
378 unreachable("Unhandled type kind in get_elem_bits");
379 }
380
381 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
382 LLVMValueRef param, unsigned rshift,
383 unsigned bitwidth)
384 {
385 LLVMValueRef value = param;
386 if (rshift)
387 value = LLVMBuildLShr(ctx->builder, value,
388 LLVMConstInt(ctx->i32, rshift, false), "");
389
390 if (rshift + bitwidth < 32) {
391 unsigned mask = (1 << bitwidth) - 1;
392 value = LLVMBuildAnd(ctx->builder, value,
393 LLVMConstInt(ctx->i32, mask, false), "");
394 }
395 return value;
396 }
397
398 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
399 {
400 switch (ctx->stage) {
401 case MESA_SHADER_TESS_CTRL:
402 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
403 case MESA_SHADER_TESS_EVAL:
404 return ctx->tes_rel_patch_id;
405 break;
406 default:
407 unreachable("Illegal stage");
408 }
409 }
410
411 /* Tessellation shaders pass outputs to the next shader using LDS.
412 *
413 * LS outputs = TCS inputs
414 * TCS outputs = TES inputs
415 *
416 * The LDS layout is:
417 * - TCS inputs for patch 0
418 * - TCS inputs for patch 1
419 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
420 * - ...
421 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
422 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
423 * - TCS outputs for patch 1
424 * - Per-patch TCS outputs for patch 1
425 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
426 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
427 * - ...
428 *
429 * All three shaders VS(LS), TCS, TES share the same LDS space.
430 */
431 static LLVMValueRef
432 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
433 {
434 if (ctx->stage == MESA_SHADER_VERTEX)
435 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
436 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
437 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
438 else {
439 assert(0);
440 return NULL;
441 }
442 }
443
444 static LLVMValueRef
445 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
446 {
447 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
448 }
449
450 static LLVMValueRef
451 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
452 {
453 return LLVMBuildMul(ctx->builder,
454 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
455 LLVMConstInt(ctx->ac.i32, 4, false), "");
456 }
457
458 static LLVMValueRef
459 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
460 {
461 return LLVMBuildMul(ctx->builder,
462 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
463 LLVMConstInt(ctx->ac.i32, 4, false), "");
464 }
465
466 static LLVMValueRef
467 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
468 {
469 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
470 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
471
472 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
473 }
474
475 static LLVMValueRef
476 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
477 {
478 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
479 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
480 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
481
482 return LLVMBuildAdd(ctx->builder, patch0_offset,
483 LLVMBuildMul(ctx->builder, patch_stride,
484 rel_patch_id, ""),
485 "");
486 }
487
488 static LLVMValueRef
489 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
490 {
491 LLVMValueRef patch0_patch_data_offset =
492 get_tcs_out_patch0_patch_data_offset(ctx);
493 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
494 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
495
496 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
497 LLVMBuildMul(ctx->builder, patch_stride,
498 rel_patch_id, ""),
499 "");
500 }
501
502 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
503 {
504 ud_info->sgpr_idx = *sgpr_idx;
505 ud_info->num_sgprs = num_sgprs;
506 ud_info->indirect = false;
507 ud_info->indirect_offset = 0;
508 *sgpr_idx += num_sgprs;
509 }
510
511 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
512 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
513 {
514 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
515 }
516
517
518 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
519 uint32_t indirect_offset)
520 {
521 ud_info->sgpr_idx = sgpr_idx;
522 ud_info->num_sgprs = num_sgprs;
523 ud_info->indirect = true;
524 ud_info->indirect_offset = indirect_offset;
525 }
526
527 struct user_sgpr_info {
528 bool need_ring_offsets;
529 uint8_t sgpr_count;
530 bool indirect_all_descriptor_sets;
531 };
532
533 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
534 struct user_sgpr_info *user_sgpr_info)
535 {
536 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
537
538 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
539 if (ctx->stage == MESA_SHADER_GEOMETRY ||
540 ctx->stage == MESA_SHADER_VERTEX ||
541 ctx->stage == MESA_SHADER_TESS_CTRL ||
542 ctx->stage == MESA_SHADER_TESS_EVAL ||
543 ctx->is_gs_copy_shader)
544 user_sgpr_info->need_ring_offsets = true;
545
546 if (ctx->stage == MESA_SHADER_FRAGMENT &&
547 ctx->shader_info->info.ps.needs_sample_positions)
548 user_sgpr_info->need_ring_offsets = true;
549
550 /* 2 user sgprs will nearly always be allocated for scratch/rings */
551 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
552 user_sgpr_info->sgpr_count += 2;
553 }
554
555 switch (ctx->stage) {
556 case MESA_SHADER_COMPUTE:
557 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
558 break;
559 case MESA_SHADER_FRAGMENT:
560 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
561 break;
562 case MESA_SHADER_VERTEX:
563 if (!ctx->is_gs_copy_shader) {
564 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
565 if (ctx->shader_info->info.vs.needs_draw_id) {
566 user_sgpr_info->sgpr_count += 3;
567 } else {
568 user_sgpr_info->sgpr_count += 2;
569 }
570 }
571 if (ctx->options->key.vs.as_ls)
572 user_sgpr_info->sgpr_count++;
573 break;
574 case MESA_SHADER_TESS_CTRL:
575 user_sgpr_info->sgpr_count += 4;
576 break;
577 case MESA_SHADER_TESS_EVAL:
578 user_sgpr_info->sgpr_count += 1;
579 break;
580 case MESA_SHADER_GEOMETRY:
581 user_sgpr_info->sgpr_count += 2;
582 break;
583 default:
584 break;
585 }
586
587 if (ctx->shader_info->info.needs_push_constants)
588 user_sgpr_info->sgpr_count += 2;
589
590 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
591 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
592 user_sgpr_info->sgpr_count += 2;
593 user_sgpr_info->indirect_all_descriptor_sets = true;
594 } else {
595 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
596 }
597 }
598
599 static void
600 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
601 gl_shader_stage stage,
602 bool has_previous_stage,
603 gl_shader_stage previous_stage,
604 const struct user_sgpr_info *user_sgpr_info,
605 struct arg_info *args,
606 LLVMValueRef *desc_sets)
607 {
608 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
609 unsigned stage_mask = 1 << stage;
610 if (has_previous_stage)
611 stage_mask |= 1 << previous_stage;
612
613 /* 1 for each descriptor set */
614 if (!user_sgpr_info->indirect_all_descriptor_sets) {
615 for (unsigned i = 0; i < num_sets; ++i) {
616 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
617 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->descriptor_sets[i]);
618 }
619 }
620 } else
621 add_user_sgpr_array_argument(args, const_array(const_array(ctx->ac.i8, 1024 * 1024), 32), desc_sets);
622
623 if (ctx->shader_info->info.needs_push_constants) {
624 /* 1 for push constants and dynamic descriptors */
625 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->push_constants);
626 }
627 }
628
629 static void
630 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
631 gl_shader_stage stage,
632 bool has_previous_stage,
633 gl_shader_stage previous_stage,
634 const struct user_sgpr_info *user_sgpr_info,
635 LLVMValueRef desc_sets,
636 uint8_t *user_sgpr_idx)
637 {
638 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
639 unsigned stage_mask = 1 << stage;
640 if (has_previous_stage)
641 stage_mask |= 1 << previous_stage;
642
643 if (!user_sgpr_info->indirect_all_descriptor_sets) {
644 for (unsigned i = 0; i < num_sets; ++i) {
645 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
646 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
647 } else
648 ctx->descriptor_sets[i] = NULL;
649 }
650 } else {
651 uint32_t desc_sgpr_idx = *user_sgpr_idx;
652 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
653
654 for (unsigned i = 0; i < num_sets; ++i) {
655 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
656 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
657 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->ac.i32, i, false));
658
659 } else
660 ctx->descriptor_sets[i] = NULL;
661 }
662 ctx->shader_info->need_indirect_descriptor_sets = true;
663 }
664
665 if (ctx->shader_info->info.needs_push_constants) {
666 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
667 }
668 }
669
670 static void
671 radv_define_vs_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
672 gl_shader_stage stage,
673 bool has_previous_stage,
674 gl_shader_stage previous_stage,
675 struct arg_info *args)
676 {
677 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
678 if (ctx->shader_info->info.vs.has_vertex_buffers)
679 add_user_sgpr_argument(args, const_array(ctx->ac.v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
680 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.base_vertex); // base vertex
681 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.start_instance);// start instance
682 if (ctx->shader_info->info.vs.needs_draw_id)
683 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.draw_id); // draw id
684 }
685 }
686
687 static void
688 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
689 gl_shader_stage stage,
690 bool has_previous_stage,
691 gl_shader_stage previous_stage,
692 uint8_t *user_sgpr_idx)
693 {
694 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
695 if (ctx->shader_info->info.vs.has_vertex_buffers) {
696 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
697 }
698 unsigned vs_num = 2;
699 if (ctx->shader_info->info.vs.needs_draw_id)
700 vs_num++;
701
702 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
703 }
704 }
705
706
707 static void create_function(struct nir_to_llvm_context *ctx,
708 gl_shader_stage stage,
709 bool has_previous_stage,
710 gl_shader_stage previous_stage)
711 {
712 uint8_t user_sgpr_idx;
713 struct user_sgpr_info user_sgpr_info;
714 struct arg_info args = {};
715 LLVMValueRef desc_sets;
716
717 allocate_user_sgprs(ctx, &user_sgpr_info);
718
719 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
720 add_user_sgpr_argument(&args, const_array(ctx->ac.v4i32, 16), &ctx->ring_offsets); /* address of rings */
721 }
722
723 switch (stage) {
724 case MESA_SHADER_COMPUTE:
725 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
726 if (ctx->shader_info->info.cs.grid_components_used)
727 add_user_sgpr_argument(&args, LLVMVectorType(ctx->ac.i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
728 add_sgpr_argument(&args, ctx->ac.v3i32, &ctx->workgroup_ids);
729 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tg_size);
730 add_vgpr_argument(&args, ctx->ac.v3i32, &ctx->local_invocation_ids);
731 break;
732 case MESA_SHADER_VERTEX:
733 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
734 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
735 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
736 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
737 if (ctx->options->key.vs.as_es)
738 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
739 else if (ctx->options->key.vs.as_ls)
740 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
741 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
742 if (!ctx->is_gs_copy_shader) {
743 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
744 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
745 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
746 }
747 break;
748 case MESA_SHADER_TESS_CTRL:
749 if (has_previous_stage) {
750 // First 6 system regs
751 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
752 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
753 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
754
755 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
756 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
757 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
758
759 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
760 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
761 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
762
763 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
764 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
765 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
766 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
767 if (ctx->shader_info->info.needs_multiview_view_index)
768 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
769
770 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
771 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
772 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
773 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
774 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
775 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
776 } else {
777 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
778 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
779 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
780 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
781 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
782 if (ctx->shader_info->info.needs_multiview_view_index)
783 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
784 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
785 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
786 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
787 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
788 }
789 break;
790 case MESA_SHADER_TESS_EVAL:
791 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
792 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
793 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
794 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
795 if (ctx->options->key.tes.as_es) {
796 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
797 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
798 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
799 } else {
800 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
801 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
802 }
803 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
804 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
805 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
806 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
807 break;
808 case MESA_SHADER_GEOMETRY:
809 if (has_previous_stage) {
810 // First 6 system regs
811 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // tess factor offset
812 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
813 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
814
815 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
816 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
817 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
818
819 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
820 if (previous_stage == MESA_SHADER_TESS_EVAL)
821 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
822 else
823 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
824 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
825 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
826 if (ctx->shader_info->info.needs_multiview_view_index)
827 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
828
829 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx01
830 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]); // vtx23
831 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_prim_id); // prim id
832 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_invocation_id);
833 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
834
835 if (previous_stage == MESA_SHADER_VERTEX) {
836 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
837 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
838 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
839 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
840 } else {
841 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
842 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
843 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
844 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
845 }
846 } else {
847 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
848 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
849 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
850 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
851 if (ctx->shader_info->info.needs_multiview_view_index)
852 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
853 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // gs2vs offset
854 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs_wave_id); // wave id
855 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx0
856 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[1]); // vtx1
857 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_prim_id); // prim id
858 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]);
859 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[3]);
860 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
861 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[5]);
862 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_invocation_id);
863 }
864 break;
865 case MESA_SHADER_FRAGMENT:
866 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
867 if (ctx->shader_info->info.ps.needs_sample_positions)
868 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->sample_pos_offset); /* sample position offset */
869 add_sgpr_argument(&args, ctx->ac.i32, &ctx->prim_mask); /* prim mask */
870 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_sample); /* persp sample */
871 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_center); /* persp center */
872 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_centroid); /* persp centroid */
873 add_vgpr_argument(&args, ctx->ac.v3i32, NULL); /* persp pull model */
874 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_sample); /* linear sample */
875 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_center); /* linear center */
876 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_centroid); /* linear centroid */
877 add_vgpr_argument(&args, ctx->ac.f32, NULL); /* line stipple tex */
878 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[0]); /* pos x float */
879 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[1]); /* pos y float */
880 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[2]); /* pos z float */
881 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[3]); /* pos w float */
882 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.front_face); /* front face */
883 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.ancillary); /* ancillary */
884 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.sample_coverage); /* sample coverage */
885 add_vgpr_argument(&args, ctx->ac.i32, NULL); /* fixed pt */
886 break;
887 default:
888 unreachable("Shader stage not implemented");
889 }
890
891 ctx->main_function = create_llvm_function(
892 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
893 ctx->max_workgroup_size,
894 ctx->options->unsafe_math);
895 set_llvm_calling_convention(ctx->main_function, stage);
896
897
898 ctx->shader_info->num_input_vgprs = 0;
899 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
900
901 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
902
903 if (ctx->stage != MESA_SHADER_FRAGMENT)
904 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
905
906 assign_arguments(ctx->main_function, &args);
907
908 user_sgpr_idx = 0;
909
910 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
911 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
912 if (ctx->options->supports_spill) {
913 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
914 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
915 NULL, 0, AC_FUNC_ATTR_READNONE);
916 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
917 const_array(ctx->ac.v4i32, 16), "");
918 }
919 }
920
921 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
922 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
923 if (has_previous_stage)
924 user_sgpr_idx = 0;
925
926 radv_define_common_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, desc_sets, &user_sgpr_idx);
927
928 switch (stage) {
929 case MESA_SHADER_COMPUTE:
930 if (ctx->shader_info->info.cs.grid_components_used) {
931 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
932 }
933 break;
934 case MESA_SHADER_VERTEX:
935 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
936 if (ctx->view_index)
937 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
938 if (ctx->options->key.vs.as_ls) {
939 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
940 }
941 if (ctx->options->key.vs.as_ls)
942 ac_declare_lds_as_pointer(&ctx->ac);
943 break;
944 case MESA_SHADER_TESS_CTRL:
945 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
946 if (has_previous_stage)
947 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
948 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
949 if (ctx->view_index)
950 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
951 ac_declare_lds_as_pointer(&ctx->ac);
952 break;
953 case MESA_SHADER_TESS_EVAL:
954 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
955 if (ctx->view_index)
956 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
957 break;
958 case MESA_SHADER_GEOMETRY:
959 if (has_previous_stage) {
960 if (previous_stage == MESA_SHADER_VERTEX)
961 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
962 else
963 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
964 }
965 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
966 if (ctx->view_index)
967 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
968 if (has_previous_stage)
969 ac_declare_lds_as_pointer(&ctx->ac);
970 break;
971 case MESA_SHADER_FRAGMENT:
972 if (ctx->shader_info->info.ps.needs_sample_positions) {
973 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
974 }
975 break;
976 default:
977 unreachable("Shader stage not implemented");
978 }
979
980 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
981 }
982
983 static int get_llvm_num_components(LLVMValueRef value)
984 {
985 LLVMTypeRef type = LLVMTypeOf(value);
986 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
987 ? LLVMGetVectorSize(type)
988 : 1;
989 return num_components;
990 }
991
992 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
993 LLVMValueRef value,
994 int index)
995 {
996 int count = get_llvm_num_components(value);
997
998 if (count == 1)
999 return value;
1000
1001 return LLVMBuildExtractElement(ac->builder, value,
1002 LLVMConstInt(ac->i32, index, false), "");
1003 }
1004
1005 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1006 LLVMValueRef value, unsigned count)
1007 {
1008 unsigned num_components = get_llvm_num_components(value);
1009 if (count == num_components)
1010 return value;
1011
1012 LLVMValueRef masks[] = {
1013 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1014 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1015
1016 if (count == 1)
1017 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1018 "");
1019
1020 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1021 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1022 }
1023
1024 static void
1025 build_store_values_extended(struct ac_llvm_context *ac,
1026 LLVMValueRef *values,
1027 unsigned value_count,
1028 unsigned value_stride,
1029 LLVMValueRef vec)
1030 {
1031 LLVMBuilderRef builder = ac->builder;
1032 unsigned i;
1033
1034 for (i = 0; i < value_count; i++) {
1035 LLVMValueRef ptr = values[i * value_stride];
1036 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1037 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1038 LLVMBuildStore(builder, value, ptr);
1039 }
1040 }
1041
1042 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1043 const nir_ssa_def *def)
1044 {
1045 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1046 if (def->num_components > 1) {
1047 type = LLVMVectorType(type, def->num_components);
1048 }
1049 return type;
1050 }
1051
1052 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1053 {
1054 assert(src.is_ssa);
1055 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1056 return (LLVMValueRef)entry->data;
1057 }
1058
1059
1060 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1061 const struct nir_block *b)
1062 {
1063 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1064 return (LLVMBasicBlockRef)entry->data;
1065 }
1066
1067 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1068 nir_alu_src src,
1069 unsigned num_components)
1070 {
1071 LLVMValueRef value = get_src(ctx, src.src);
1072 bool need_swizzle = false;
1073
1074 assert(value);
1075 LLVMTypeRef type = LLVMTypeOf(value);
1076 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1077 ? LLVMGetVectorSize(type)
1078 : 1;
1079
1080 for (unsigned i = 0; i < num_components; ++i) {
1081 assert(src.swizzle[i] < src_components);
1082 if (src.swizzle[i] != i)
1083 need_swizzle = true;
1084 }
1085
1086 if (need_swizzle || num_components != src_components) {
1087 LLVMValueRef masks[] = {
1088 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1089 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1090 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1091 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1092
1093 if (src_components > 1 && num_components == 1) {
1094 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1095 masks[0], "");
1096 } else if (src_components == 1 && num_components > 1) {
1097 LLVMValueRef values[] = {value, value, value, value};
1098 value = ac_build_gather_values(&ctx->ac, values, num_components);
1099 } else {
1100 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1101 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1102 swizzle, "");
1103 }
1104 }
1105 assert(!src.negate);
1106 assert(!src.abs);
1107 return value;
1108 }
1109
1110 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1111 LLVMIntPredicate pred, LLVMValueRef src0,
1112 LLVMValueRef src1)
1113 {
1114 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1115 return LLVMBuildSelect(ctx->builder, result,
1116 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1117 LLVMConstInt(ctx->i32, 0, false), "");
1118 }
1119
1120 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1121 LLVMRealPredicate pred, LLVMValueRef src0,
1122 LLVMValueRef src1)
1123 {
1124 LLVMValueRef result;
1125 src0 = ac_to_float(ctx, src0);
1126 src1 = ac_to_float(ctx, src1);
1127 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1128 return LLVMBuildSelect(ctx->builder, result,
1129 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1130 LLVMConstInt(ctx->i32, 0, false), "");
1131 }
1132
1133 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1134 const char *intrin,
1135 LLVMTypeRef result_type,
1136 LLVMValueRef src0)
1137 {
1138 char name[64];
1139 LLVMValueRef params[] = {
1140 ac_to_float(ctx, src0),
1141 };
1142
1143 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1144 get_elem_bits(ctx, result_type));
1145 assert(length < sizeof(name));
1146 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1147 }
1148
1149 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1150 const char *intrin,
1151 LLVMTypeRef result_type,
1152 LLVMValueRef src0, LLVMValueRef src1)
1153 {
1154 char name[64];
1155 LLVMValueRef params[] = {
1156 ac_to_float(ctx, src0),
1157 ac_to_float(ctx, src1),
1158 };
1159
1160 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1161 get_elem_bits(ctx, result_type));
1162 assert(length < sizeof(name));
1163 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1164 }
1165
1166 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1167 const char *intrin,
1168 LLVMTypeRef result_type,
1169 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1170 {
1171 char name[64];
1172 LLVMValueRef params[] = {
1173 ac_to_float(ctx, src0),
1174 ac_to_float(ctx, src1),
1175 ac_to_float(ctx, src2),
1176 };
1177
1178 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1179 get_elem_bits(ctx, result_type));
1180 assert(length < sizeof(name));
1181 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1182 }
1183
1184 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1185 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1186 {
1187 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1188 ctx->i32_0, "");
1189 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1190 }
1191
1192 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1193 LLVMIntPredicate pred,
1194 LLVMValueRef src0, LLVMValueRef src1)
1195 {
1196 return LLVMBuildSelect(ctx->builder,
1197 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1198 src0,
1199 src1, "");
1200
1201 }
1202 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1203 LLVMValueRef src0)
1204 {
1205 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1206 LLVMBuildNeg(ctx->builder, src0, ""));
1207 }
1208
1209 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1210 LLVMValueRef src0)
1211 {
1212 LLVMValueRef cmp, val;
1213
1214 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1215 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1216 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1217 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1218 return val;
1219 }
1220
1221 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1222 LLVMValueRef src0)
1223 {
1224 LLVMValueRef cmp, val;
1225
1226 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1227 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1228 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1229 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1230 return val;
1231 }
1232
1233 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1234 LLVMValueRef src0)
1235 {
1236 const char *intr = "llvm.floor.f32";
1237 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1238 LLVMValueRef params[] = {
1239 fsrc0,
1240 };
1241 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1242 ctx->f32, params, 1,
1243 AC_FUNC_ATTR_READNONE);
1244 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1245 }
1246
1247 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1248 const char *intrin,
1249 LLVMValueRef src0, LLVMValueRef src1)
1250 {
1251 LLVMTypeRef ret_type;
1252 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1253 LLVMValueRef res;
1254 LLVMValueRef params[] = { src0, src1 };
1255 ret_type = LLVMStructTypeInContext(ctx->context, types,
1256 2, true);
1257
1258 res = ac_build_intrinsic(ctx, intrin, ret_type,
1259 params, 2, AC_FUNC_ATTR_READNONE);
1260
1261 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1262 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1263 return res;
1264 }
1265
1266 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1267 LLVMValueRef src0)
1268 {
1269 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1270 }
1271
1272 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1273 LLVMValueRef src0)
1274 {
1275 src0 = ac_to_float(ctx, src0);
1276 return LLVMBuildSExt(ctx->builder,
1277 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1278 ctx->i32, "");
1279 }
1280
1281 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1282 LLVMValueRef src0)
1283 {
1284 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1285 }
1286
1287 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1288 LLVMValueRef src0)
1289 {
1290 return LLVMBuildSExt(ctx->builder,
1291 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1292 ctx->i32, "");
1293 }
1294
1295 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1296 LLVMValueRef src0)
1297 {
1298 LLVMValueRef result;
1299 LLVMValueRef cond = NULL;
1300
1301 src0 = ac_to_float(&ctx->ac, src0);
1302 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1303
1304 if (ctx->options->chip_class >= VI) {
1305 LLVMValueRef args[2];
1306 /* Check if the result is a denormal - and flush to 0 if so. */
1307 args[0] = result;
1308 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1309 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1310 }
1311
1312 /* need to convert back up to f32 */
1313 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1314
1315 if (ctx->options->chip_class >= VI)
1316 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1317 else {
1318 /* for SI/CIK */
1319 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1320 * so compare the result and flush to 0 if it's smaller.
1321 */
1322 LLVMValueRef temp, cond2;
1323 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1324 ctx->ac.f32, result);
1325 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1326 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1327 temp, "");
1328 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1329 temp, ctx->ac.f32_0, "");
1330 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1331 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1332 }
1333 return result;
1334 }
1335
1336 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1337 LLVMValueRef src0, LLVMValueRef src1)
1338 {
1339 LLVMValueRef dst64, result;
1340 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1341 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1342
1343 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1344 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1345 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1346 return result;
1347 }
1348
1349 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1350 LLVMValueRef src0, LLVMValueRef src1)
1351 {
1352 LLVMValueRef dst64, result;
1353 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1354 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1355
1356 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1357 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1358 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1359 return result;
1360 }
1361
1362 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1363 bool is_signed,
1364 const LLVMValueRef srcs[3])
1365 {
1366 LLVMValueRef result;
1367 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1368
1369 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1370 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1371 return result;
1372 }
1373
1374 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1375 LLVMValueRef src0, LLVMValueRef src1,
1376 LLVMValueRef src2, LLVMValueRef src3)
1377 {
1378 LLVMValueRef bfi_args[3], result;
1379
1380 bfi_args[0] = LLVMBuildShl(ctx->builder,
1381 LLVMBuildSub(ctx->builder,
1382 LLVMBuildShl(ctx->builder,
1383 ctx->i32_1,
1384 src3, ""),
1385 ctx->i32_1, ""),
1386 src2, "");
1387 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1388 bfi_args[2] = src0;
1389
1390 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1391
1392 /* Calculate:
1393 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1394 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1395 */
1396 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1397 LLVMBuildAnd(ctx->builder, bfi_args[0],
1398 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1399
1400 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1401 return result;
1402 }
1403
1404 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1405 LLVMValueRef src0)
1406 {
1407 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1408 int i;
1409 LLVMValueRef comp[2];
1410
1411 src0 = ac_to_float(ctx, src0);
1412 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1413 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1414 for (i = 0; i < 2; i++) {
1415 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1416 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1417 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1418 }
1419
1420 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1421 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1422
1423 return comp[0];
1424 }
1425
1426 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1427 LLVMValueRef src0)
1428 {
1429 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1430 LLVMValueRef temps[2], result, val;
1431 int i;
1432
1433 for (i = 0; i < 2; i++) {
1434 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1435 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1436 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1437 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1438 }
1439
1440 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1441 ctx->i32_0, "");
1442 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1443 ctx->i32_1, "");
1444 return result;
1445 }
1446
1447 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1448 nir_op op,
1449 LLVMValueRef src0)
1450 {
1451 unsigned mask;
1452 int idx;
1453 LLVMValueRef result;
1454
1455 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1456 mask = AC_TID_MASK_LEFT;
1457 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1458 mask = AC_TID_MASK_TOP;
1459 else
1460 mask = AC_TID_MASK_TOP_LEFT;
1461
1462 /* for DDX we want to next X pixel, DDY next Y pixel. */
1463 if (op == nir_op_fddx_fine ||
1464 op == nir_op_fddx_coarse ||
1465 op == nir_op_fddx)
1466 idx = 1;
1467 else
1468 idx = 2;
1469
1470 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1471 return result;
1472 }
1473
1474 /*
1475 * this takes an I,J coordinate pair,
1476 * and works out the X and Y derivatives.
1477 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1478 */
1479 static LLVMValueRef emit_ddxy_interp(
1480 struct ac_nir_context *ctx,
1481 LLVMValueRef interp_ij)
1482 {
1483 LLVMValueRef result[4], a;
1484 unsigned i;
1485
1486 for (i = 0; i < 2; i++) {
1487 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1488 LLVMConstInt(ctx->ac.i32, i, false), "");
1489 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1490 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1491 }
1492 return ac_build_gather_values(&ctx->ac, result, 4);
1493 }
1494
1495 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1496 {
1497 LLVMValueRef src[4], result = NULL;
1498 unsigned num_components = instr->dest.dest.ssa.num_components;
1499 unsigned src_components;
1500 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1501
1502 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1503 switch (instr->op) {
1504 case nir_op_vec2:
1505 case nir_op_vec3:
1506 case nir_op_vec4:
1507 src_components = 1;
1508 break;
1509 case nir_op_pack_half_2x16:
1510 src_components = 2;
1511 break;
1512 case nir_op_unpack_half_2x16:
1513 src_components = 1;
1514 break;
1515 default:
1516 src_components = num_components;
1517 break;
1518 }
1519 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1520 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1521
1522 switch (instr->op) {
1523 case nir_op_fmov:
1524 case nir_op_imov:
1525 result = src[0];
1526 break;
1527 case nir_op_fneg:
1528 src[0] = ac_to_float(&ctx->ac, src[0]);
1529 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1530 break;
1531 case nir_op_ineg:
1532 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1533 break;
1534 case nir_op_inot:
1535 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1536 break;
1537 case nir_op_iadd:
1538 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1539 break;
1540 case nir_op_fadd:
1541 src[0] = ac_to_float(&ctx->ac, src[0]);
1542 src[1] = ac_to_float(&ctx->ac, src[1]);
1543 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1544 break;
1545 case nir_op_fsub:
1546 src[0] = ac_to_float(&ctx->ac, src[0]);
1547 src[1] = ac_to_float(&ctx->ac, src[1]);
1548 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1549 break;
1550 case nir_op_isub:
1551 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1552 break;
1553 case nir_op_imul:
1554 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1555 break;
1556 case nir_op_imod:
1557 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1558 break;
1559 case nir_op_umod:
1560 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1561 break;
1562 case nir_op_fmod:
1563 src[0] = ac_to_float(&ctx->ac, src[0]);
1564 src[1] = ac_to_float(&ctx->ac, src[1]);
1565 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1566 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1567 ac_to_float_type(&ctx->ac, def_type), result);
1568 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1569 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1570 break;
1571 case nir_op_frem:
1572 src[0] = ac_to_float(&ctx->ac, src[0]);
1573 src[1] = ac_to_float(&ctx->ac, src[1]);
1574 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1575 break;
1576 case nir_op_irem:
1577 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1578 break;
1579 case nir_op_idiv:
1580 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1581 break;
1582 case nir_op_udiv:
1583 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1584 break;
1585 case nir_op_fmul:
1586 src[0] = ac_to_float(&ctx->ac, src[0]);
1587 src[1] = ac_to_float(&ctx->ac, src[1]);
1588 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1589 break;
1590 case nir_op_fdiv:
1591 src[0] = ac_to_float(&ctx->ac, src[0]);
1592 src[1] = ac_to_float(&ctx->ac, src[1]);
1593 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1594 break;
1595 case nir_op_frcp:
1596 src[0] = ac_to_float(&ctx->ac, src[0]);
1597 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1598 break;
1599 case nir_op_iand:
1600 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1601 break;
1602 case nir_op_ior:
1603 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1604 break;
1605 case nir_op_ixor:
1606 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1607 break;
1608 case nir_op_ishl:
1609 result = LLVMBuildShl(ctx->ac.builder, src[0],
1610 LLVMBuildZExt(ctx->ac.builder, src[1],
1611 LLVMTypeOf(src[0]), ""),
1612 "");
1613 break;
1614 case nir_op_ishr:
1615 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1616 LLVMBuildZExt(ctx->ac.builder, src[1],
1617 LLVMTypeOf(src[0]), ""),
1618 "");
1619 break;
1620 case nir_op_ushr:
1621 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1622 LLVMBuildZExt(ctx->ac.builder, src[1],
1623 LLVMTypeOf(src[0]), ""),
1624 "");
1625 break;
1626 case nir_op_ilt:
1627 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1628 break;
1629 case nir_op_ine:
1630 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1631 break;
1632 case nir_op_ieq:
1633 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1634 break;
1635 case nir_op_ige:
1636 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1637 break;
1638 case nir_op_ult:
1639 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1640 break;
1641 case nir_op_uge:
1642 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1643 break;
1644 case nir_op_feq:
1645 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1646 break;
1647 case nir_op_fne:
1648 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1649 break;
1650 case nir_op_flt:
1651 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1652 break;
1653 case nir_op_fge:
1654 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1655 break;
1656 case nir_op_fabs:
1657 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1658 ac_to_float_type(&ctx->ac, def_type), src[0]);
1659 break;
1660 case nir_op_iabs:
1661 result = emit_iabs(&ctx->ac, src[0]);
1662 break;
1663 case nir_op_imax:
1664 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1665 break;
1666 case nir_op_imin:
1667 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1668 break;
1669 case nir_op_umax:
1670 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1671 break;
1672 case nir_op_umin:
1673 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1674 break;
1675 case nir_op_isign:
1676 result = emit_isign(&ctx->ac, src[0]);
1677 break;
1678 case nir_op_fsign:
1679 src[0] = ac_to_float(&ctx->ac, src[0]);
1680 result = emit_fsign(&ctx->ac, src[0]);
1681 break;
1682 case nir_op_ffloor:
1683 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1684 ac_to_float_type(&ctx->ac, def_type), src[0]);
1685 break;
1686 case nir_op_ftrunc:
1687 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1688 ac_to_float_type(&ctx->ac, def_type), src[0]);
1689 break;
1690 case nir_op_fceil:
1691 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1692 ac_to_float_type(&ctx->ac, def_type), src[0]);
1693 break;
1694 case nir_op_fround_even:
1695 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1696 ac_to_float_type(&ctx->ac, def_type),src[0]);
1697 break;
1698 case nir_op_ffract:
1699 result = emit_ffract(&ctx->ac, src[0]);
1700 break;
1701 case nir_op_fsin:
1702 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1703 ac_to_float_type(&ctx->ac, def_type), src[0]);
1704 break;
1705 case nir_op_fcos:
1706 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1707 ac_to_float_type(&ctx->ac, def_type), src[0]);
1708 break;
1709 case nir_op_fsqrt:
1710 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1711 ac_to_float_type(&ctx->ac, def_type), src[0]);
1712 break;
1713 case nir_op_fexp2:
1714 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1715 ac_to_float_type(&ctx->ac, def_type), src[0]);
1716 break;
1717 case nir_op_flog2:
1718 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1719 ac_to_float_type(&ctx->ac, def_type), src[0]);
1720 break;
1721 case nir_op_frsq:
1722 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1723 ac_to_float_type(&ctx->ac, def_type), src[0]);
1724 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1725 break;
1726 case nir_op_fpow:
1727 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1728 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1729 break;
1730 case nir_op_fmax:
1731 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1732 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1733 if (instr->dest.dest.ssa.bit_size == 32)
1734 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1735 ac_to_float_type(&ctx->ac, def_type),
1736 result);
1737 break;
1738 case nir_op_fmin:
1739 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1740 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1741 if (instr->dest.dest.ssa.bit_size == 32)
1742 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1743 ac_to_float_type(&ctx->ac, def_type),
1744 result);
1745 break;
1746 case nir_op_ffma:
1747 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1748 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1749 break;
1750 case nir_op_ibitfield_extract:
1751 result = emit_bitfield_extract(&ctx->ac, true, src);
1752 break;
1753 case nir_op_ubitfield_extract:
1754 result = emit_bitfield_extract(&ctx->ac, false, src);
1755 break;
1756 case nir_op_bitfield_insert:
1757 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1758 break;
1759 case nir_op_bitfield_reverse:
1760 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1761 break;
1762 case nir_op_bit_count:
1763 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1764 break;
1765 case nir_op_vec2:
1766 case nir_op_vec3:
1767 case nir_op_vec4:
1768 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1769 src[i] = ac_to_integer(&ctx->ac, src[i]);
1770 result = ac_build_gather_values(&ctx->ac, src, num_components);
1771 break;
1772 case nir_op_f2i32:
1773 case nir_op_f2i64:
1774 src[0] = ac_to_float(&ctx->ac, src[0]);
1775 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1776 break;
1777 case nir_op_f2u32:
1778 case nir_op_f2u64:
1779 src[0] = ac_to_float(&ctx->ac, src[0]);
1780 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1781 break;
1782 case nir_op_i2f32:
1783 case nir_op_i2f64:
1784 src[0] = ac_to_integer(&ctx->ac, src[0]);
1785 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1786 break;
1787 case nir_op_u2f32:
1788 case nir_op_u2f64:
1789 src[0] = ac_to_integer(&ctx->ac, src[0]);
1790 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1791 break;
1792 case nir_op_f2f64:
1793 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1794 break;
1795 case nir_op_f2f32:
1796 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1797 break;
1798 case nir_op_u2u32:
1799 case nir_op_u2u64:
1800 src[0] = ac_to_integer(&ctx->ac, src[0]);
1801 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1802 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1803 else
1804 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1805 break;
1806 case nir_op_i2i32:
1807 case nir_op_i2i64:
1808 src[0] = ac_to_integer(&ctx->ac, src[0]);
1809 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1810 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1811 else
1812 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1813 break;
1814 case nir_op_bcsel:
1815 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1816 break;
1817 case nir_op_find_lsb:
1818 src[0] = ac_to_integer(&ctx->ac, src[0]);
1819 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1820 break;
1821 case nir_op_ufind_msb:
1822 src[0] = ac_to_integer(&ctx->ac, src[0]);
1823 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1824 break;
1825 case nir_op_ifind_msb:
1826 src[0] = ac_to_integer(&ctx->ac, src[0]);
1827 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1828 break;
1829 case nir_op_uadd_carry:
1830 src[0] = ac_to_integer(&ctx->ac, src[0]);
1831 src[1] = ac_to_integer(&ctx->ac, src[1]);
1832 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1833 break;
1834 case nir_op_usub_borrow:
1835 src[0] = ac_to_integer(&ctx->ac, src[0]);
1836 src[1] = ac_to_integer(&ctx->ac, src[1]);
1837 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1838 break;
1839 case nir_op_b2f:
1840 result = emit_b2f(&ctx->ac, src[0]);
1841 break;
1842 case nir_op_f2b:
1843 result = emit_f2b(&ctx->ac, src[0]);
1844 break;
1845 case nir_op_b2i:
1846 result = emit_b2i(&ctx->ac, src[0]);
1847 break;
1848 case nir_op_i2b:
1849 src[0] = ac_to_integer(&ctx->ac, src[0]);
1850 result = emit_i2b(&ctx->ac, src[0]);
1851 break;
1852 case nir_op_fquantize2f16:
1853 result = emit_f2f16(ctx->nctx, src[0]);
1854 break;
1855 case nir_op_umul_high:
1856 src[0] = ac_to_integer(&ctx->ac, src[0]);
1857 src[1] = ac_to_integer(&ctx->ac, src[1]);
1858 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1859 break;
1860 case nir_op_imul_high:
1861 src[0] = ac_to_integer(&ctx->ac, src[0]);
1862 src[1] = ac_to_integer(&ctx->ac, src[1]);
1863 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1864 break;
1865 case nir_op_pack_half_2x16:
1866 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1867 break;
1868 case nir_op_unpack_half_2x16:
1869 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1870 break;
1871 case nir_op_fddx:
1872 case nir_op_fddy:
1873 case nir_op_fddx_fine:
1874 case nir_op_fddy_fine:
1875 case nir_op_fddx_coarse:
1876 case nir_op_fddy_coarse:
1877 result = emit_ddxy(ctx, instr->op, src[0]);
1878 break;
1879
1880 case nir_op_unpack_64_2x32_split_x: {
1881 assert(instr->src[0].src.ssa->num_components == 1);
1882 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1883 ctx->ac.v2i32,
1884 "");
1885 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1886 ctx->ac.i32_0, "");
1887 break;
1888 }
1889
1890 case nir_op_unpack_64_2x32_split_y: {
1891 assert(instr->src[0].src.ssa->num_components == 1);
1892 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1893 ctx->ac.v2i32,
1894 "");
1895 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1896 ctx->ac.i32_1, "");
1897 break;
1898 }
1899
1900 case nir_op_pack_64_2x32_split: {
1901 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
1902 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1903 src[0], ctx->ac.i32_0, "");
1904 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1905 src[1], ctx->ac.i32_1, "");
1906 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1907 break;
1908 }
1909
1910 default:
1911 fprintf(stderr, "Unknown NIR alu instr: ");
1912 nir_print_instr(&instr->instr, stderr);
1913 fprintf(stderr, "\n");
1914 abort();
1915 }
1916
1917 if (result) {
1918 assert(instr->dest.dest.is_ssa);
1919 result = ac_to_integer(&ctx->ac, result);
1920 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1921 result);
1922 }
1923 }
1924
1925 static void visit_load_const(struct ac_nir_context *ctx,
1926 const nir_load_const_instr *instr)
1927 {
1928 LLVMValueRef values[4], value = NULL;
1929 LLVMTypeRef element_type =
1930 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1931
1932 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1933 switch (instr->def.bit_size) {
1934 case 32:
1935 values[i] = LLVMConstInt(element_type,
1936 instr->value.u32[i], false);
1937 break;
1938 case 64:
1939 values[i] = LLVMConstInt(element_type,
1940 instr->value.u64[i], false);
1941 break;
1942 default:
1943 fprintf(stderr,
1944 "unsupported nir load_const bit_size: %d\n",
1945 instr->def.bit_size);
1946 abort();
1947 }
1948 }
1949 if (instr->def.num_components > 1) {
1950 value = LLVMConstVector(values, instr->def.num_components);
1951 } else
1952 value = values[0];
1953
1954 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1955 }
1956
1957 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1958 LLVMTypeRef type)
1959 {
1960 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1961 return LLVMBuildBitCast(ctx->builder, ptr,
1962 LLVMPointerType(type, addr_space), "");
1963 }
1964
1965 static LLVMValueRef
1966 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1967 {
1968 LLVMValueRef size =
1969 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1970 LLVMConstInt(ctx->ac.i32, 2, false), "");
1971
1972 /* VI only */
1973 if (ctx->ac.chip_class == VI && in_elements) {
1974 /* On VI, the descriptor contains the size in bytes,
1975 * but TXQ must return the size in elements.
1976 * The stride is always non-zero for resources using TXQ.
1977 */
1978 LLVMValueRef stride =
1979 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1980 LLVMConstInt(ctx->ac.i32, 1, false), "");
1981 stride = LLVMBuildLShr(ctx->ac.builder, stride,
1982 LLVMConstInt(ctx->ac.i32, 16, false), "");
1983 stride = LLVMBuildAnd(ctx->ac.builder, stride,
1984 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
1985
1986 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
1987 }
1988 return size;
1989 }
1990
1991 /**
1992 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1993 * intrinsic names).
1994 */
1995 static void build_int_type_name(
1996 LLVMTypeRef type,
1997 char *buf, unsigned bufsize)
1998 {
1999 assert(bufsize >= 6);
2000
2001 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2002 snprintf(buf, bufsize, "v%ui32",
2003 LLVMGetVectorSize(type));
2004 else
2005 strcpy(buf, "i32");
2006 }
2007
2008 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2009 struct ac_image_args *args,
2010 const nir_tex_instr *instr)
2011 {
2012 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2013 LLVMValueRef coord = args->addr;
2014 LLVMValueRef half_texel[2];
2015 LLVMValueRef compare_cube_wa = NULL;
2016 LLVMValueRef result;
2017 int c;
2018 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2019
2020 //TODO Rect
2021 {
2022 struct ac_image_args txq_args = { 0 };
2023
2024 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2025 txq_args.opcode = ac_image_get_resinfo;
2026 txq_args.dmask = 0xf;
2027 txq_args.addr = ctx->i32_0;
2028 txq_args.resource = args->resource;
2029 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2030
2031 for (c = 0; c < 2; c++) {
2032 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2033 LLVMConstInt(ctx->i32, c, false), "");
2034 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2035 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2036 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2037 LLVMConstReal(ctx->f32, -0.5), "");
2038 }
2039 }
2040
2041 LLVMValueRef orig_coords = args->addr;
2042
2043 for (c = 0; c < 2; c++) {
2044 LLVMValueRef tmp;
2045 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2046 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2047 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2048 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2049 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2050 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2051 }
2052
2053
2054 /*
2055 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2056 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2057 * workaround by sampling using a scaled type and converting.
2058 * This is taken from amdgpu-pro shaders.
2059 */
2060 /* NOTE this produces some ugly code compared to amdgpu-pro,
2061 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2062 * and then reads them back. -pro generates two selects,
2063 * one s_cmp for the descriptor rewriting
2064 * one v_cmp for the coordinate and result changes.
2065 */
2066 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2067 LLVMValueRef tmp, tmp2;
2068
2069 /* workaround 8/8/8/8 uint/sint cube gather bug */
2070 /* first detect it then change to a scaled read and f2i */
2071 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2072 tmp2 = tmp;
2073
2074 /* extract the DATA_FORMAT */
2075 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2076 LLVMConstInt(ctx->i32, 6, false), false);
2077
2078 /* is the DATA_FORMAT == 8_8_8_8 */
2079 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2080
2081 if (stype == GLSL_TYPE_UINT)
2082 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2083 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2084 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2085 else
2086 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2087 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2088 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2089
2090 /* replace the NUM FORMAT in the descriptor */
2091 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2092 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2093
2094 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2095
2096 /* don't modify the coordinates for this case */
2097 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2098 }
2099 args->addr = coord;
2100 result = ac_build_image_opcode(ctx, args);
2101
2102 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2103 LLVMValueRef tmp, tmp2;
2104
2105 /* if the cube workaround is in place, f2i the result. */
2106 for (c = 0; c < 4; c++) {
2107 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2108 if (stype == GLSL_TYPE_UINT)
2109 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2110 else
2111 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2112 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2113 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2114 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2115 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2116 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2117 }
2118 }
2119 return result;
2120 }
2121
2122 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2123 const nir_tex_instr *instr,
2124 bool lod_is_zero,
2125 struct ac_image_args *args)
2126 {
2127 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2128 return ac_build_buffer_load_format(&ctx->ac,
2129 args->resource,
2130 args->addr,
2131 LLVMConstInt(ctx->ac.i32, 0, false),
2132 true);
2133 }
2134
2135 args->opcode = ac_image_sample;
2136 args->compare = instr->is_shadow;
2137
2138 switch (instr->op) {
2139 case nir_texop_txf:
2140 case nir_texop_txf_ms:
2141 case nir_texop_samples_identical:
2142 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2143 args->compare = false;
2144 args->offset = false;
2145 break;
2146 case nir_texop_txb:
2147 args->bias = true;
2148 break;
2149 case nir_texop_txl:
2150 if (lod_is_zero)
2151 args->level_zero = true;
2152 else
2153 args->lod = true;
2154 break;
2155 case nir_texop_txs:
2156 case nir_texop_query_levels:
2157 args->opcode = ac_image_get_resinfo;
2158 break;
2159 case nir_texop_tex:
2160 if (ctx->stage != MESA_SHADER_FRAGMENT)
2161 args->level_zero = true;
2162 break;
2163 case nir_texop_txd:
2164 args->deriv = true;
2165 break;
2166 case nir_texop_tg4:
2167 args->opcode = ac_image_gather4;
2168 args->level_zero = true;
2169 break;
2170 case nir_texop_lod:
2171 args->opcode = ac_image_get_lod;
2172 args->compare = false;
2173 args->offset = false;
2174 break;
2175 default:
2176 break;
2177 }
2178
2179 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2180 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2181 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2182 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2183 }
2184 }
2185 return ac_build_image_opcode(&ctx->ac, args);
2186 }
2187
2188 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2189 nir_intrinsic_instr *instr)
2190 {
2191 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2192 unsigned desc_set = nir_intrinsic_desc_set(instr);
2193 unsigned binding = nir_intrinsic_binding(instr);
2194 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2195 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2196 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2197 unsigned base_offset = layout->binding[binding].offset;
2198 LLVMValueRef offset, stride;
2199
2200 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2201 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2202 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2203 layout->binding[binding].dynamic_offset_offset;
2204 desc_ptr = ctx->push_constants;
2205 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2206 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2207 } else
2208 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2209
2210 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2211 index = LLVMBuildMul(ctx->builder, index, stride, "");
2212 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2213
2214 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2215 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2216 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2217
2218 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2219 }
2220
2221 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2222 nir_intrinsic_instr *instr)
2223 {
2224 LLVMValueRef ptr, addr;
2225
2226 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2227 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2228
2229 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2230 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2231
2232 return LLVMBuildLoad(ctx->builder, ptr, "");
2233 }
2234
2235 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2236 const nir_intrinsic_instr *instr)
2237 {
2238 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2239
2240 return get_buffer_size(ctx, desc, false);
2241 }
2242 static void visit_store_ssbo(struct ac_nir_context *ctx,
2243 nir_intrinsic_instr *instr)
2244 {
2245 const char *store_name;
2246 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2247 LLVMTypeRef data_type = ctx->ac.f32;
2248 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2249 int components_32bit = elem_size_mult * instr->num_components;
2250 unsigned writemask = nir_intrinsic_write_mask(instr);
2251 LLVMValueRef base_data, base_offset;
2252 LLVMValueRef params[6];
2253
2254 params[1] = ctx->abi->load_ssbo(ctx->abi,
2255 get_src(ctx, instr->src[1]), true);
2256 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2257 params[4] = ctx->ac.i1false; /* glc */
2258 params[5] = ctx->ac.i1false; /* slc */
2259
2260 if (components_32bit > 1)
2261 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2262
2263 base_data = ac_to_float(&ctx->ac, src_data);
2264 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2265 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2266 data_type, "");
2267 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2268 while (writemask) {
2269 int start, count;
2270 LLVMValueRef data;
2271 LLVMValueRef offset;
2272 LLVMValueRef tmp;
2273 u_bit_scan_consecutive_range(&writemask, &start, &count);
2274
2275 /* Due to an LLVM limitation, split 3-element writes
2276 * into a 2-element and a 1-element write. */
2277 if (count == 3) {
2278 writemask |= 1 << (start + 2);
2279 count = 2;
2280 }
2281
2282 start *= elem_size_mult;
2283 count *= elem_size_mult;
2284
2285 if (count > 4) {
2286 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2287 count = 4;
2288 }
2289
2290 if (count == 4) {
2291 store_name = "llvm.amdgcn.buffer.store.v4f32";
2292 data = base_data;
2293 } else if (count == 2) {
2294 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2295 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2296 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2297 ctx->ac.i32_0, "");
2298
2299 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2300 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2301 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2302 ctx->ac.i32_1, "");
2303 store_name = "llvm.amdgcn.buffer.store.v2f32";
2304
2305 } else {
2306 assert(count == 1);
2307 if (get_llvm_num_components(base_data) > 1)
2308 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2309 LLVMConstInt(ctx->ac.i32, start, false), "");
2310 else
2311 data = base_data;
2312 store_name = "llvm.amdgcn.buffer.store.f32";
2313 }
2314
2315 offset = base_offset;
2316 if (start != 0) {
2317 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2318 }
2319 params[0] = data;
2320 params[3] = offset;
2321 ac_build_intrinsic(&ctx->ac, store_name,
2322 ctx->ac.voidt, params, 6, 0);
2323 }
2324 }
2325
2326 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2327 const nir_intrinsic_instr *instr)
2328 {
2329 const char *name;
2330 LLVMValueRef params[6];
2331 int arg_count = 0;
2332
2333 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2334 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2335 }
2336 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2337 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2338 get_src(ctx, instr->src[0]),
2339 true);
2340 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2341 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2342 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2343
2344 switch (instr->intrinsic) {
2345 case nir_intrinsic_ssbo_atomic_add:
2346 name = "llvm.amdgcn.buffer.atomic.add";
2347 break;
2348 case nir_intrinsic_ssbo_atomic_imin:
2349 name = "llvm.amdgcn.buffer.atomic.smin";
2350 break;
2351 case nir_intrinsic_ssbo_atomic_umin:
2352 name = "llvm.amdgcn.buffer.atomic.umin";
2353 break;
2354 case nir_intrinsic_ssbo_atomic_imax:
2355 name = "llvm.amdgcn.buffer.atomic.smax";
2356 break;
2357 case nir_intrinsic_ssbo_atomic_umax:
2358 name = "llvm.amdgcn.buffer.atomic.umax";
2359 break;
2360 case nir_intrinsic_ssbo_atomic_and:
2361 name = "llvm.amdgcn.buffer.atomic.and";
2362 break;
2363 case nir_intrinsic_ssbo_atomic_or:
2364 name = "llvm.amdgcn.buffer.atomic.or";
2365 break;
2366 case nir_intrinsic_ssbo_atomic_xor:
2367 name = "llvm.amdgcn.buffer.atomic.xor";
2368 break;
2369 case nir_intrinsic_ssbo_atomic_exchange:
2370 name = "llvm.amdgcn.buffer.atomic.swap";
2371 break;
2372 case nir_intrinsic_ssbo_atomic_comp_swap:
2373 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2374 break;
2375 default:
2376 abort();
2377 }
2378
2379 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2380 }
2381
2382 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2383 const nir_intrinsic_instr *instr)
2384 {
2385 LLVMValueRef results[2];
2386 int load_components;
2387 int num_components = instr->num_components;
2388 if (instr->dest.ssa.bit_size == 64)
2389 num_components *= 2;
2390
2391 for (int i = 0; i < num_components; i += load_components) {
2392 load_components = MIN2(num_components - i, 4);
2393 const char *load_name;
2394 LLVMTypeRef data_type = ctx->ac.f32;
2395 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2396 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2397
2398 if (load_components == 3)
2399 data_type = LLVMVectorType(ctx->ac.f32, 4);
2400 else if (load_components > 1)
2401 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2402
2403 if (load_components >= 3)
2404 load_name = "llvm.amdgcn.buffer.load.v4f32";
2405 else if (load_components == 2)
2406 load_name = "llvm.amdgcn.buffer.load.v2f32";
2407 else if (load_components == 1)
2408 load_name = "llvm.amdgcn.buffer.load.f32";
2409 else
2410 unreachable("unhandled number of components");
2411
2412 LLVMValueRef params[] = {
2413 ctx->abi->load_ssbo(ctx->abi,
2414 get_src(ctx, instr->src[0]),
2415 false),
2416 LLVMConstInt(ctx->ac.i32, 0, false),
2417 offset,
2418 ctx->ac.i1false,
2419 ctx->ac.i1false,
2420 };
2421
2422 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2423
2424 }
2425
2426 assume(results[0]);
2427 LLVMValueRef ret = results[0];
2428 if (num_components > 4 || num_components == 3) {
2429 LLVMValueRef masks[] = {
2430 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2431 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2432 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2433 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2434 };
2435
2436 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2437 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2438 results[num_components > 4 ? 1 : 0], swizzle, "");
2439 }
2440
2441 return LLVMBuildBitCast(ctx->ac.builder, ret,
2442 get_def_type(ctx, &instr->dest.ssa), "");
2443 }
2444
2445 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2446 const nir_intrinsic_instr *instr)
2447 {
2448 LLVMValueRef results[8], ret;
2449 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2450 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2451 int num_components = instr->num_components;
2452
2453 if (ctx->abi->load_ubo)
2454 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2455
2456 if (instr->dest.ssa.bit_size == 64)
2457 num_components *= 2;
2458
2459 for (unsigned i = 0; i < num_components; ++i) {
2460 LLVMValueRef params[] = {
2461 rsrc,
2462 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2463 offset, "")
2464 };
2465 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2466 params, 2,
2467 AC_FUNC_ATTR_READNONE |
2468 AC_FUNC_ATTR_LEGACY);
2469 }
2470
2471
2472 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2473 return LLVMBuildBitCast(ctx->ac.builder, ret,
2474 get_def_type(ctx, &instr->dest.ssa), "");
2475 }
2476
2477 static void
2478 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2479 bool vs_in, unsigned *vertex_index_out,
2480 LLVMValueRef *vertex_index_ref,
2481 unsigned *const_out, LLVMValueRef *indir_out)
2482 {
2483 unsigned const_offset = 0;
2484 nir_deref *tail = &deref->deref;
2485 LLVMValueRef offset = NULL;
2486
2487 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2488 tail = tail->child;
2489 nir_deref_array *deref_array = nir_deref_as_array(tail);
2490 if (vertex_index_out)
2491 *vertex_index_out = deref_array->base_offset;
2492
2493 if (vertex_index_ref) {
2494 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2495 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2496 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2497 }
2498 *vertex_index_ref = vtx;
2499 }
2500 }
2501
2502 if (deref->var->data.compact) {
2503 assert(tail->child->deref_type == nir_deref_type_array);
2504 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2505 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2506 /* We always lower indirect dereferences for "compact" array vars. */
2507 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2508
2509 const_offset = deref_array->base_offset;
2510 goto out;
2511 }
2512
2513 while (tail->child != NULL) {
2514 const struct glsl_type *parent_type = tail->type;
2515 tail = tail->child;
2516
2517 if (tail->deref_type == nir_deref_type_array) {
2518 nir_deref_array *deref_array = nir_deref_as_array(tail);
2519 LLVMValueRef index, stride, local_offset;
2520 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2521
2522 const_offset += size * deref_array->base_offset;
2523 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2524 continue;
2525
2526 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2527 index = get_src(ctx, deref_array->indirect);
2528 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2529 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2530
2531 if (offset)
2532 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2533 else
2534 offset = local_offset;
2535 } else if (tail->deref_type == nir_deref_type_struct) {
2536 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2537
2538 for (unsigned i = 0; i < deref_struct->index; i++) {
2539 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2540 const_offset += glsl_count_attribute_slots(ft, vs_in);
2541 }
2542 } else
2543 unreachable("unsupported deref type");
2544
2545 }
2546 out:
2547 if (const_offset && offset)
2548 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2549 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2550 "");
2551
2552 *const_out = const_offset;
2553 *indir_out = offset;
2554 }
2555
2556
2557 /* The offchip buffer layout for TCS->TES is
2558 *
2559 * - attribute 0 of patch 0 vertex 0
2560 * - attribute 0 of patch 0 vertex 1
2561 * - attribute 0 of patch 0 vertex 2
2562 * ...
2563 * - attribute 0 of patch 1 vertex 0
2564 * - attribute 0 of patch 1 vertex 1
2565 * ...
2566 * - attribute 1 of patch 0 vertex 0
2567 * - attribute 1 of patch 0 vertex 1
2568 * ...
2569 * - per patch attribute 0 of patch 0
2570 * - per patch attribute 0 of patch 1
2571 * ...
2572 *
2573 * Note that every attribute has 4 components.
2574 */
2575 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2576 LLVMValueRef vertex_index,
2577 LLVMValueRef param_index)
2578 {
2579 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2580 LLVMValueRef param_stride, constant16;
2581 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2582
2583 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2584 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2585 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2586 num_patches, "");
2587
2588 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2589 if (vertex_index) {
2590 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2591 vertices_per_patch, "");
2592
2593 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2594 vertex_index, "");
2595
2596 param_stride = total_vertices;
2597 } else {
2598 base_addr = rel_patch_id;
2599 param_stride = num_patches;
2600 }
2601
2602 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2603 LLVMBuildMul(ctx->builder, param_index,
2604 param_stride, ""), "");
2605
2606 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2607
2608 if (!vertex_index) {
2609 LLVMValueRef patch_data_offset =
2610 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2611
2612 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2613 patch_data_offset, "");
2614 }
2615 return base_addr;
2616 }
2617
2618 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2619 unsigned param,
2620 unsigned const_index,
2621 bool is_compact,
2622 LLVMValueRef vertex_index,
2623 LLVMValueRef indir_index)
2624 {
2625 LLVMValueRef param_index;
2626
2627 if (indir_index)
2628 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2629 indir_index, "");
2630 else {
2631 if (const_index && !is_compact)
2632 param += const_index;
2633 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2634 }
2635 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2636 }
2637
2638 static void
2639 mark_tess_output(struct nir_to_llvm_context *ctx,
2640 bool is_patch, uint32_t param)
2641
2642 {
2643 if (is_patch) {
2644 ctx->tess_patch_outputs_written |= (1ull << param);
2645 } else
2646 ctx->tess_outputs_written |= (1ull << param);
2647 }
2648
2649 static LLVMValueRef
2650 get_dw_address(struct nir_to_llvm_context *ctx,
2651 LLVMValueRef dw_addr,
2652 unsigned param,
2653 unsigned const_index,
2654 bool compact_const_index,
2655 LLVMValueRef vertex_index,
2656 LLVMValueRef stride,
2657 LLVMValueRef indir_index)
2658
2659 {
2660
2661 if (vertex_index) {
2662 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2663 LLVMBuildMul(ctx->builder,
2664 vertex_index,
2665 stride, ""), "");
2666 }
2667
2668 if (indir_index)
2669 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2670 LLVMBuildMul(ctx->builder, indir_index,
2671 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2672 else if (const_index && !compact_const_index)
2673 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2674 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2675
2676 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2677 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2678
2679 if (const_index && compact_const_index)
2680 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2681 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2682 return dw_addr;
2683 }
2684
2685 static LLVMValueRef
2686 build_varying_gather_values(struct ac_llvm_context *ctx, LLVMValueRef *values,
2687 unsigned value_count, unsigned component)
2688 {
2689 LLVMValueRef vec = NULL;
2690
2691 if (value_count == 1) {
2692 return values[component];
2693 } else if (!value_count)
2694 unreachable("value_count is 0");
2695
2696 for (unsigned i = component; i < value_count + component; i++) {
2697 LLVMValueRef value = values[i];
2698
2699 if (!i)
2700 vec = LLVMGetUndef( LLVMVectorType(LLVMTypeOf(value), value_count));
2701 LLVMValueRef index = LLVMConstInt(ctx->i32, i - component, false);
2702 vec = LLVMBuildInsertElement(ctx->builder, vec, value, index, "");
2703 }
2704 return vec;
2705 }
2706
2707 static LLVMValueRef
2708 load_tcs_input(struct nir_to_llvm_context *ctx,
2709 nir_intrinsic_instr *instr)
2710 {
2711 LLVMValueRef dw_addr, stride;
2712 unsigned const_index;
2713 LLVMValueRef vertex_index;
2714 LLVMValueRef indir_index;
2715 unsigned param;
2716 LLVMValueRef value[4], result;
2717 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2718 const bool is_compact = instr->variables[0]->var->data.compact;
2719 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2720 get_deref_offset(ctx->nir, instr->variables[0],
2721 false, NULL, per_vertex ? &vertex_index : NULL,
2722 &const_index, &indir_index);
2723
2724 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2725 dw_addr = get_tcs_in_current_patch_offset(ctx);
2726 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2727 indir_index);
2728
2729 unsigned comp = instr->variables[0]->var->data.location_frac;
2730 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2731 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2732 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2733 ctx->ac.i32_1, "");
2734 }
2735 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2736 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2737 return result;
2738 }
2739
2740 static LLVMValueRef
2741 load_tcs_output(struct nir_to_llvm_context *ctx,
2742 nir_intrinsic_instr *instr)
2743 {
2744 LLVMValueRef dw_addr;
2745 LLVMValueRef stride = NULL;
2746 LLVMValueRef value[4], result;
2747 LLVMValueRef vertex_index = NULL;
2748 LLVMValueRef indir_index = NULL;
2749 unsigned const_index = 0;
2750 unsigned param;
2751 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2752 const bool is_compact = instr->variables[0]->var->data.compact;
2753 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2754 get_deref_offset(ctx->nir, instr->variables[0],
2755 false, NULL, per_vertex ? &vertex_index : NULL,
2756 &const_index, &indir_index);
2757
2758 if (!instr->variables[0]->var->data.patch) {
2759 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2760 dw_addr = get_tcs_out_current_patch_offset(ctx);
2761 } else {
2762 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2763 }
2764
2765 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2766 indir_index);
2767
2768 unsigned comp = instr->variables[0]->var->data.location_frac;
2769 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2770 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2771 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2772 ctx->ac.i32_1, "");
2773 }
2774 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2775 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2776 return result;
2777 }
2778
2779 static void
2780 store_tcs_output(struct nir_to_llvm_context *ctx,
2781 nir_intrinsic_instr *instr,
2782 LLVMValueRef src,
2783 unsigned writemask)
2784 {
2785 LLVMValueRef dw_addr;
2786 LLVMValueRef stride = NULL;
2787 LLVMValueRef buf_addr = NULL;
2788 LLVMValueRef vertex_index = NULL;
2789 LLVMValueRef indir_index = NULL;
2790 unsigned const_index = 0;
2791 unsigned param;
2792 const unsigned comp = instr->variables[0]->var->data.location_frac;
2793 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2794 const bool is_compact = instr->variables[0]->var->data.compact;
2795 bool store_lds = true;
2796
2797 if (instr->variables[0]->var->data.patch) {
2798 if (!(ctx->tcs_patch_outputs_read & (1U << instr->variables[0]->var->data.location)))
2799 store_lds = false;
2800 } else {
2801 if (!(ctx->tcs_outputs_read & (1ULL << instr->variables[0]->var->data.location)))
2802 store_lds = false;
2803 }
2804 get_deref_offset(ctx->nir, instr->variables[0],
2805 false, NULL, per_vertex ? &vertex_index : NULL,
2806 &const_index, &indir_index);
2807
2808 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2809 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2810 is_compact && const_index > 3) {
2811 const_index -= 3;
2812 param++;
2813 }
2814
2815 if (!instr->variables[0]->var->data.patch) {
2816 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2817 dw_addr = get_tcs_out_current_patch_offset(ctx);
2818 } else {
2819 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2820 }
2821
2822 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2823
2824 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2825 indir_index);
2826 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2827 vertex_index, indir_index);
2828
2829 bool is_tess_factor = false;
2830 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2831 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2832 is_tess_factor = true;
2833
2834 unsigned base = is_compact ? const_index : 0;
2835 for (unsigned chan = 0; chan < 8; chan++) {
2836 if (!(writemask & (1 << chan)))
2837 continue;
2838 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2839
2840 if (store_lds || is_tess_factor)
2841 ac_lds_store(&ctx->ac, dw_addr, value);
2842
2843 if (!is_tess_factor && writemask != 0xF)
2844 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2845 buf_addr, ctx->oc_lds,
2846 4 * (base + chan), 1, 0, true, false);
2847
2848 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2849 ctx->ac.i32_1, "");
2850 }
2851
2852 if (writemask == 0xF) {
2853 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2854 buf_addr, ctx->oc_lds,
2855 (base * 4), 1, 0, true, false);
2856 }
2857 }
2858
2859 static LLVMValueRef
2860 load_tes_input(struct nir_to_llvm_context *ctx,
2861 const nir_intrinsic_instr *instr)
2862 {
2863 LLVMValueRef buf_addr;
2864 LLVMValueRef result;
2865 LLVMValueRef vertex_index = NULL;
2866 LLVMValueRef indir_index = NULL;
2867 unsigned const_index = 0;
2868 unsigned param;
2869 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2870 const bool is_compact = instr->variables[0]->var->data.compact;
2871
2872 get_deref_offset(ctx->nir, instr->variables[0],
2873 false, NULL, per_vertex ? &vertex_index : NULL,
2874 &const_index, &indir_index);
2875 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2876 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2877 is_compact && const_index > 3) {
2878 const_index -= 3;
2879 param++;
2880 }
2881
2882 unsigned comp = instr->variables[0]->var->data.location_frac;
2883 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2884 is_compact, vertex_index, indir_index);
2885
2886 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, comp * 4, false);
2887 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2888
2889 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2890 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2891 result = trim_vector(&ctx->ac, result, instr->num_components);
2892 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2893 return result;
2894 }
2895
2896 static LLVMValueRef
2897 load_gs_input(struct nir_to_llvm_context *ctx,
2898 nir_intrinsic_instr *instr)
2899 {
2900 LLVMValueRef indir_index, vtx_offset;
2901 unsigned const_index;
2902 LLVMValueRef args[9];
2903 unsigned param, vtx_offset_param;
2904 LLVMValueRef value[4], result;
2905 unsigned vertex_index;
2906 get_deref_offset(ctx->nir, instr->variables[0],
2907 false, &vertex_index, NULL,
2908 &const_index, &indir_index);
2909 vtx_offset_param = vertex_index;
2910 assert(vtx_offset_param < 6);
2911 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2912 LLVMConstInt(ctx->ac.i32, 4, false), "");
2913
2914 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2915
2916 unsigned comp = instr->variables[0]->var->data.location_frac;
2917 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2918 if (ctx->ac.chip_class >= GFX9) {
2919 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
2920 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2921 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
2922 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2923 } else {
2924 args[0] = ctx->esgs_ring;
2925 args[1] = vtx_offset;
2926 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
2927 args[3] = ctx->ac.i32_0;
2928 args[4] = ctx->ac.i32_1; /* OFFEN */
2929 args[5] = ctx->ac.i32_0; /* IDXEN */
2930 args[6] = ctx->ac.i32_1; /* GLC */
2931 args[7] = ctx->ac.i32_0; /* SLC */
2932 args[8] = ctx->ac.i32_0; /* TFE */
2933
2934 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2935 ctx->ac.i32, args, 9,
2936 AC_FUNC_ATTR_READONLY |
2937 AC_FUNC_ATTR_LEGACY);
2938 }
2939 }
2940 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2941
2942 return result;
2943 }
2944
2945 static LLVMValueRef
2946 build_gep_for_deref(struct ac_nir_context *ctx,
2947 nir_deref_var *deref)
2948 {
2949 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2950 assert(entry->data);
2951 LLVMValueRef val = entry->data;
2952 nir_deref *tail = deref->deref.child;
2953 while (tail != NULL) {
2954 LLVMValueRef offset;
2955 switch (tail->deref_type) {
2956 case nir_deref_type_array: {
2957 nir_deref_array *array = nir_deref_as_array(tail);
2958 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2959 if (array->deref_array_type ==
2960 nir_deref_array_type_indirect) {
2961 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2962 get_src(ctx,
2963 array->indirect),
2964 "");
2965 }
2966 break;
2967 }
2968 case nir_deref_type_struct: {
2969 nir_deref_struct *deref_struct =
2970 nir_deref_as_struct(tail);
2971 offset = LLVMConstInt(ctx->ac.i32,
2972 deref_struct->index, 0);
2973 break;
2974 }
2975 default:
2976 unreachable("bad deref type");
2977 }
2978 val = ac_build_gep0(&ctx->ac, val, offset);
2979 tail = tail->child;
2980 }
2981 return val;
2982 }
2983
2984 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
2985 nir_intrinsic_instr *instr)
2986 {
2987 LLVMValueRef values[8];
2988 int idx = instr->variables[0]->var->data.driver_location;
2989 int ve = instr->dest.ssa.num_components;
2990 unsigned comp = instr->variables[0]->var->data.location_frac;
2991 LLVMValueRef indir_index;
2992 LLVMValueRef ret;
2993 unsigned const_index;
2994 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2995 instr->variables[0]->var->data.mode == nir_var_shader_in;
2996 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2997 &const_index, &indir_index);
2998
2999 if (instr->dest.ssa.bit_size == 64)
3000 ve *= 2;
3001
3002 switch (instr->variables[0]->var->data.mode) {
3003 case nir_var_shader_in:
3004 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3005 return load_tcs_input(ctx->nctx, instr);
3006 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3007 return load_tes_input(ctx->nctx, instr);
3008 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3009 return load_gs_input(ctx->nctx, instr);
3010 }
3011
3012 for (unsigned chan = comp; chan < ve + comp; chan++) {
3013 if (indir_index) {
3014 unsigned count = glsl_count_attribute_slots(
3015 instr->variables[0]->var->type,
3016 ctx->stage == MESA_SHADER_VERTEX);
3017 count -= chan / 4;
3018 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3019 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3020 4, false, true);
3021
3022 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3023 tmp_vec,
3024 indir_index, "");
3025 } else
3026 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3027 }
3028 break;
3029 case nir_var_local:
3030 for (unsigned chan = 0; chan < ve; chan++) {
3031 if (indir_index) {
3032 unsigned count = glsl_count_attribute_slots(
3033 instr->variables[0]->var->type, false);
3034 count -= chan / 4;
3035 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3036 &ctx->ac, ctx->locals + idx + chan, count,
3037 4, true, true);
3038
3039 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3040 tmp_vec,
3041 indir_index, "");
3042 } else {
3043 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3044 }
3045 }
3046 break;
3047 case nir_var_shared: {
3048 LLVMValueRef address = build_gep_for_deref(ctx,
3049 instr->variables[0]);
3050 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3051 return LLVMBuildBitCast(ctx->ac.builder, val,
3052 get_def_type(ctx, &instr->dest.ssa),
3053 "");
3054 }
3055 case nir_var_shader_out:
3056 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3057 return load_tcs_output(ctx->nctx, instr);
3058
3059 for (unsigned chan = comp; chan < ve + comp; chan++) {
3060 if (indir_index) {
3061 unsigned count = glsl_count_attribute_slots(
3062 instr->variables[0]->var->type, false);
3063 count -= chan / 4;
3064 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3065 &ctx->ac, ctx->outputs + idx + chan, count,
3066 4, true, true);
3067
3068 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3069 tmp_vec,
3070 indir_index, "");
3071 } else {
3072 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3073 ctx->outputs[idx + chan + const_index * 4],
3074 "");
3075 }
3076 }
3077 break;
3078 default:
3079 unreachable("unhandle variable mode");
3080 }
3081 ret = build_varying_gather_values(&ctx->ac, values, ve, comp);
3082 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3083 }
3084
3085 static void
3086 visit_store_var(struct ac_nir_context *ctx,
3087 nir_intrinsic_instr *instr)
3088 {
3089 LLVMValueRef temp_ptr, value;
3090 int idx = instr->variables[0]->var->data.driver_location;
3091 unsigned comp = instr->variables[0]->var->data.location_frac;
3092 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3093 int writemask = instr->const_index[0] << comp;
3094 LLVMValueRef indir_index;
3095 unsigned const_index;
3096 get_deref_offset(ctx, instr->variables[0], false,
3097 NULL, NULL, &const_index, &indir_index);
3098
3099 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3100 int old_writemask = writemask;
3101
3102 src = LLVMBuildBitCast(ctx->ac.builder, src,
3103 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3104 "");
3105
3106 writemask = 0;
3107 for (unsigned chan = 0; chan < 4; chan++) {
3108 if (old_writemask & (1 << chan))
3109 writemask |= 3u << (2 * chan);
3110 }
3111 }
3112
3113 switch (instr->variables[0]->var->data.mode) {
3114 case nir_var_shader_out:
3115
3116 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3117 store_tcs_output(ctx->nctx, instr, src, writemask);
3118 return;
3119 }
3120
3121 for (unsigned chan = 0; chan < 8; chan++) {
3122 int stride = 4;
3123 if (!(writemask & (1 << chan)))
3124 continue;
3125
3126 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3127
3128 if (instr->variables[0]->var->data.compact)
3129 stride = 1;
3130 if (indir_index) {
3131 unsigned count = glsl_count_attribute_slots(
3132 instr->variables[0]->var->type, false);
3133 count -= chan / 4;
3134 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3135 &ctx->ac, ctx->outputs + idx + chan, count,
3136 stride, true, true);
3137
3138 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3139 value, indir_index, "");
3140 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3141 count, stride, tmp_vec);
3142
3143 } else {
3144 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3145
3146 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3147 }
3148 }
3149 break;
3150 case nir_var_local:
3151 for (unsigned chan = 0; chan < 8; chan++) {
3152 if (!(writemask & (1 << chan)))
3153 continue;
3154
3155 value = llvm_extract_elem(&ctx->ac, src, chan);
3156 if (indir_index) {
3157 unsigned count = glsl_count_attribute_slots(
3158 instr->variables[0]->var->type, false);
3159 count -= chan / 4;
3160 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3161 &ctx->ac, ctx->locals + idx + chan, count,
3162 4, true, true);
3163
3164 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3165 value, indir_index, "");
3166 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3167 count, 4, tmp_vec);
3168 } else {
3169 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3170
3171 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3172 }
3173 }
3174 break;
3175 case nir_var_shared: {
3176 int writemask = instr->const_index[0];
3177 LLVMValueRef address = build_gep_for_deref(ctx,
3178 instr->variables[0]);
3179 LLVMValueRef val = get_src(ctx, instr->src[0]);
3180 unsigned components =
3181 glsl_get_vector_elements(
3182 nir_deref_tail(&instr->variables[0]->deref)->type);
3183 if (writemask == (1 << components) - 1) {
3184 val = LLVMBuildBitCast(
3185 ctx->ac.builder, val,
3186 LLVMGetElementType(LLVMTypeOf(address)), "");
3187 LLVMBuildStore(ctx->ac.builder, val, address);
3188 } else {
3189 for (unsigned chan = 0; chan < 4; chan++) {
3190 if (!(writemask & (1 << chan)))
3191 continue;
3192 LLVMValueRef ptr =
3193 LLVMBuildStructGEP(ctx->ac.builder,
3194 address, chan, "");
3195 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3196 chan);
3197 src = LLVMBuildBitCast(
3198 ctx->ac.builder, src,
3199 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3200 LLVMBuildStore(ctx->ac.builder, src, ptr);
3201 }
3202 }
3203 break;
3204 }
3205 default:
3206 break;
3207 }
3208 }
3209
3210 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3211 {
3212 switch (dim) {
3213 case GLSL_SAMPLER_DIM_BUF:
3214 return 1;
3215 case GLSL_SAMPLER_DIM_1D:
3216 return array ? 2 : 1;
3217 case GLSL_SAMPLER_DIM_2D:
3218 return array ? 3 : 2;
3219 case GLSL_SAMPLER_DIM_MS:
3220 return array ? 4 : 3;
3221 case GLSL_SAMPLER_DIM_3D:
3222 case GLSL_SAMPLER_DIM_CUBE:
3223 return 3;
3224 case GLSL_SAMPLER_DIM_RECT:
3225 case GLSL_SAMPLER_DIM_SUBPASS:
3226 return 2;
3227 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3228 return 3;
3229 default:
3230 break;
3231 }
3232 return 0;
3233 }
3234
3235
3236
3237 /* Adjust the sample index according to FMASK.
3238 *
3239 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3240 * which is the identity mapping. Each nibble says which physical sample
3241 * should be fetched to get that sample.
3242 *
3243 * For example, 0x11111100 means there are only 2 samples stored and
3244 * the second sample covers 3/4 of the pixel. When reading samples 0
3245 * and 1, return physical sample 0 (determined by the first two 0s
3246 * in FMASK), otherwise return physical sample 1.
3247 *
3248 * The sample index should be adjusted as follows:
3249 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3250 */
3251 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3252 LLVMValueRef coord_x, LLVMValueRef coord_y,
3253 LLVMValueRef coord_z,
3254 LLVMValueRef sample_index,
3255 LLVMValueRef fmask_desc_ptr)
3256 {
3257 LLVMValueRef fmask_load_address[4];
3258 LLVMValueRef res;
3259
3260 fmask_load_address[0] = coord_x;
3261 fmask_load_address[1] = coord_y;
3262 if (coord_z) {
3263 fmask_load_address[2] = coord_z;
3264 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3265 }
3266
3267 struct ac_image_args args = {0};
3268
3269 args.opcode = ac_image_load;
3270 args.da = coord_z ? true : false;
3271 args.resource = fmask_desc_ptr;
3272 args.dmask = 0xf;
3273 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3274
3275 res = ac_build_image_opcode(ctx, &args);
3276
3277 res = ac_to_integer(ctx, res);
3278 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3279 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3280
3281 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3282 res,
3283 ctx->i32_0, "");
3284
3285 LLVMValueRef sample_index4 =
3286 LLVMBuildMul(ctx->builder, sample_index, four, "");
3287 LLVMValueRef shifted_fmask =
3288 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3289 LLVMValueRef final_sample =
3290 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3291
3292 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3293 * resource descriptor is 0 (invalid),
3294 */
3295 LLVMValueRef fmask_desc =
3296 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3297 ctx->v8i32, "");
3298
3299 LLVMValueRef fmask_word1 =
3300 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3301 ctx->i32_1, "");
3302
3303 LLVMValueRef word1_is_nonzero =
3304 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3305 fmask_word1, ctx->i32_0, "");
3306
3307 /* Replace the MSAA sample index. */
3308 sample_index =
3309 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3310 final_sample, sample_index, "");
3311 return sample_index;
3312 }
3313
3314 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3315 const nir_intrinsic_instr *instr)
3316 {
3317 const struct glsl_type *type = instr->variables[0]->var->type;
3318 if(instr->variables[0]->deref.child)
3319 type = instr->variables[0]->deref.child->type;
3320
3321 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3322 LLVMValueRef coords[4];
3323 LLVMValueRef masks[] = {
3324 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3325 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3326 };
3327 LLVMValueRef res;
3328 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3329
3330 int count;
3331 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3332 bool is_array = glsl_sampler_type_is_array(type);
3333 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3334 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3335 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3336 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3337 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3338 count = image_type_to_components_count(dim, is_array);
3339
3340 if (is_ms) {
3341 LLVMValueRef fmask_load_address[3];
3342 int chan;
3343
3344 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3345 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3346 if (is_array)
3347 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3348 else
3349 fmask_load_address[2] = NULL;
3350 if (add_frag_pos) {
3351 for (chan = 0; chan < 2; ++chan)
3352 fmask_load_address[chan] =
3353 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3354 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3355 ctx->ac.i32, ""), "");
3356 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3357 }
3358 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3359 fmask_load_address[0],
3360 fmask_load_address[1],
3361 fmask_load_address[2],
3362 sample_index,
3363 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3364 }
3365 if (count == 1 && !gfx9_1d) {
3366 if (instr->src[0].ssa->num_components)
3367 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3368 else
3369 res = src0;
3370 } else {
3371 int chan;
3372 if (is_ms)
3373 count--;
3374 for (chan = 0; chan < count; ++chan) {
3375 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3376 }
3377 if (add_frag_pos) {
3378 for (chan = 0; chan < 2; ++chan)
3379 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3380 ctx->ac.i32, ""), "");
3381 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3382 count++;
3383 }
3384
3385 if (gfx9_1d) {
3386 if (is_array) {
3387 coords[2] = coords[1];
3388 coords[1] = ctx->ac.i32_0;
3389 } else
3390 coords[1] = ctx->ac.i32_0;
3391 count++;
3392 }
3393
3394 if (is_ms) {
3395 coords[count] = sample_index;
3396 count++;
3397 }
3398
3399 if (count == 3) {
3400 coords[3] = LLVMGetUndef(ctx->ac.i32);
3401 count = 4;
3402 }
3403 res = ac_build_gather_values(&ctx->ac, coords, count);
3404 }
3405 return res;
3406 }
3407
3408 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3409 const nir_intrinsic_instr *instr)
3410 {
3411 LLVMValueRef params[7];
3412 LLVMValueRef res;
3413 char intrinsic_name[64];
3414 const nir_variable *var = instr->variables[0]->var;
3415 const struct glsl_type *type = var->type;
3416
3417 if(instr->variables[0]->deref.child)
3418 type = instr->variables[0]->deref.child->type;
3419
3420 type = glsl_without_array(type);
3421 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3422 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3423 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3424 ctx->ac.i32_0, ""); /* vindex */
3425 params[2] = ctx->ac.i32_0; /* voffset */
3426 params[3] = ctx->ac.i1false; /* glc */
3427 params[4] = ctx->ac.i1false; /* slc */
3428 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3429 params, 5, 0);
3430
3431 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3432 res = ac_to_integer(&ctx->ac, res);
3433 } else {
3434 bool is_da = glsl_sampler_type_is_array(type) ||
3435 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3436 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3437 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3438 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3439 LLVMValueRef glc = ctx->ac.i1false;
3440 LLVMValueRef slc = ctx->ac.i1false;
3441
3442 params[0] = get_image_coords(ctx, instr);
3443 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3444 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3445 if (HAVE_LLVM <= 0x0309) {
3446 params[3] = ctx->ac.i1false; /* r128 */
3447 params[4] = da;
3448 params[5] = glc;
3449 params[6] = slc;
3450 } else {
3451 LLVMValueRef lwe = ctx->ac.i1false;
3452 params[3] = glc;
3453 params[4] = slc;
3454 params[5] = lwe;
3455 params[6] = da;
3456 }
3457
3458 ac_get_image_intr_name("llvm.amdgcn.image.load",
3459 ctx->ac.v4f32, /* vdata */
3460 LLVMTypeOf(params[0]), /* coords */
3461 LLVMTypeOf(params[1]), /* rsrc */
3462 intrinsic_name, sizeof(intrinsic_name));
3463
3464 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3465 params, 7, AC_FUNC_ATTR_READONLY);
3466 }
3467 return ac_to_integer(&ctx->ac, res);
3468 }
3469
3470 static void visit_image_store(struct ac_nir_context *ctx,
3471 nir_intrinsic_instr *instr)
3472 {
3473 LLVMValueRef params[8];
3474 char intrinsic_name[64];
3475 const nir_variable *var = instr->variables[0]->var;
3476 const struct glsl_type *type = glsl_without_array(var->type);
3477 LLVMValueRef glc = ctx->ac.i1false;
3478 bool force_glc = ctx->ac.chip_class == SI;
3479 if (force_glc)
3480 glc = ctx->ac.i1true;
3481
3482 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3483 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3484 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3485 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3486 ctx->ac.i32_0, ""); /* vindex */
3487 params[3] = ctx->ac.i32_0; /* voffset */
3488 params[4] = glc; /* glc */
3489 params[5] = ctx->ac.i1false; /* slc */
3490 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3491 params, 6, 0);
3492 } else {
3493 bool is_da = glsl_sampler_type_is_array(type) ||
3494 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3495 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3496 LLVMValueRef slc = ctx->ac.i1false;
3497
3498 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3499 params[1] = get_image_coords(ctx, instr); /* coords */
3500 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3501 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3502 if (HAVE_LLVM <= 0x0309) {
3503 params[4] = ctx->ac.i1false; /* r128 */
3504 params[5] = da;
3505 params[6] = glc;
3506 params[7] = slc;
3507 } else {
3508 LLVMValueRef lwe = ctx->ac.i1false;
3509 params[4] = glc;
3510 params[5] = slc;
3511 params[6] = lwe;
3512 params[7] = da;
3513 }
3514
3515 ac_get_image_intr_name("llvm.amdgcn.image.store",
3516 LLVMTypeOf(params[0]), /* vdata */
3517 LLVMTypeOf(params[1]), /* coords */
3518 LLVMTypeOf(params[2]), /* rsrc */
3519 intrinsic_name, sizeof(intrinsic_name));
3520
3521 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3522 params, 8, 0);
3523 }
3524
3525 }
3526
3527 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3528 const nir_intrinsic_instr *instr)
3529 {
3530 LLVMValueRef params[7];
3531 int param_count = 0;
3532 const nir_variable *var = instr->variables[0]->var;
3533
3534 const char *atomic_name;
3535 char intrinsic_name[41];
3536 const struct glsl_type *type = glsl_without_array(var->type);
3537 MAYBE_UNUSED int length;
3538
3539 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3540
3541 switch (instr->intrinsic) {
3542 case nir_intrinsic_image_atomic_add:
3543 atomic_name = "add";
3544 break;
3545 case nir_intrinsic_image_atomic_min:
3546 atomic_name = is_unsigned ? "umin" : "smin";
3547 break;
3548 case nir_intrinsic_image_atomic_max:
3549 atomic_name = is_unsigned ? "umax" : "smax";
3550 break;
3551 case nir_intrinsic_image_atomic_and:
3552 atomic_name = "and";
3553 break;
3554 case nir_intrinsic_image_atomic_or:
3555 atomic_name = "or";
3556 break;
3557 case nir_intrinsic_image_atomic_xor:
3558 atomic_name = "xor";
3559 break;
3560 case nir_intrinsic_image_atomic_exchange:
3561 atomic_name = "swap";
3562 break;
3563 case nir_intrinsic_image_atomic_comp_swap:
3564 atomic_name = "cmpswap";
3565 break;
3566 default:
3567 abort();
3568 }
3569
3570 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3571 params[param_count++] = get_src(ctx, instr->src[3]);
3572 params[param_count++] = get_src(ctx, instr->src[2]);
3573
3574 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3575 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3576 NULL, true, true);
3577 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3578 ctx->ac.i32_0, ""); /* vindex */
3579 params[param_count++] = ctx->ac.i32_0; /* voffset */
3580 params[param_count++] = ctx->ac.i1false; /* slc */
3581
3582 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3583 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3584 } else {
3585 char coords_type[8];
3586
3587 bool da = glsl_sampler_type_is_array(type) ||
3588 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3589
3590 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3591 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3592 NULL, true, true);
3593 params[param_count++] = ctx->ac.i1false; /* r128 */
3594 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3595 params[param_count++] = ctx->ac.i1false; /* slc */
3596
3597 build_int_type_name(LLVMTypeOf(coords),
3598 coords_type, sizeof(coords_type));
3599
3600 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3601 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3602 }
3603
3604 assert(length < sizeof(intrinsic_name));
3605 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3606 }
3607
3608 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3609 const nir_intrinsic_instr *instr)
3610 {
3611 LLVMValueRef res;
3612 const nir_variable *var = instr->variables[0]->var;
3613 const struct glsl_type *type = instr->variables[0]->var->type;
3614 bool da = glsl_sampler_type_is_array(var->type) ||
3615 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3616 if(instr->variables[0]->deref.child)
3617 type = instr->variables[0]->deref.child->type;
3618
3619 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3620 return get_buffer_size(ctx,
3621 get_sampler_desc(ctx, instr->variables[0],
3622 AC_DESC_BUFFER, NULL, true, false), true);
3623
3624 struct ac_image_args args = { 0 };
3625
3626 args.da = da;
3627 args.dmask = 0xf;
3628 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3629 args.opcode = ac_image_get_resinfo;
3630 args.addr = ctx->ac.i32_0;
3631
3632 res = ac_build_image_opcode(&ctx->ac, &args);
3633
3634 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3635
3636 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3637 glsl_sampler_type_is_array(type)) {
3638 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3639 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3640 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3641 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3642 }
3643 if (ctx->ac.chip_class >= GFX9 &&
3644 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3645 glsl_sampler_type_is_array(type)) {
3646 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3647 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3648 ctx->ac.i32_1, "");
3649
3650 }
3651 return res;
3652 }
3653
3654 #define NOOP_WAITCNT 0xf7f
3655 #define LGKM_CNT 0x07f
3656 #define VM_CNT 0xf70
3657
3658 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3659 unsigned simm16)
3660 {
3661 LLVMValueRef args[1] = {
3662 LLVMConstInt(ctx->ac.i32, simm16, false),
3663 };
3664 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3665 ctx->ac.voidt, args, 1, 0);
3666 }
3667
3668 static void emit_membar(struct nir_to_llvm_context *ctx,
3669 const nir_intrinsic_instr *instr)
3670 {
3671 unsigned waitcnt = NOOP_WAITCNT;
3672
3673 switch (instr->intrinsic) {
3674 case nir_intrinsic_memory_barrier:
3675 case nir_intrinsic_group_memory_barrier:
3676 waitcnt &= VM_CNT & LGKM_CNT;
3677 break;
3678 case nir_intrinsic_memory_barrier_atomic_counter:
3679 case nir_intrinsic_memory_barrier_buffer:
3680 case nir_intrinsic_memory_barrier_image:
3681 waitcnt &= VM_CNT;
3682 break;
3683 case nir_intrinsic_memory_barrier_shared:
3684 waitcnt &= LGKM_CNT;
3685 break;
3686 default:
3687 break;
3688 }
3689 if (waitcnt != NOOP_WAITCNT)
3690 emit_waitcnt(ctx, waitcnt);
3691 }
3692
3693 static void emit_barrier(struct nir_to_llvm_context *ctx)
3694 {
3695 /* SI only (thanks to a hw bug workaround):
3696 * The real barrier instruction isn’t needed, because an entire patch
3697 * always fits into a single wave.
3698 */
3699 if (ctx->options->chip_class == SI &&
3700 ctx->stage == MESA_SHADER_TESS_CTRL) {
3701 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3702 return;
3703 }
3704 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3705 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3706 }
3707
3708 static void emit_discard_if(struct ac_nir_context *ctx,
3709 const nir_intrinsic_instr *instr)
3710 {
3711 LLVMValueRef cond;
3712
3713 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3714 get_src(ctx, instr->src[0]),
3715 ctx->ac.i32_0, "");
3716 ac_build_kill_if_false(&ctx->ac, cond);
3717 }
3718
3719 static LLVMValueRef
3720 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3721 {
3722 LLVMValueRef result;
3723 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3724 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3725 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3726
3727 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3728 }
3729
3730 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3731 const nir_intrinsic_instr *instr)
3732 {
3733 LLVMValueRef ptr, result;
3734 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3735 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3736
3737 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3738 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3739 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3740 ptr, src, src1,
3741 LLVMAtomicOrderingSequentiallyConsistent,
3742 LLVMAtomicOrderingSequentiallyConsistent,
3743 false);
3744 } else {
3745 LLVMAtomicRMWBinOp op;
3746 switch (instr->intrinsic) {
3747 case nir_intrinsic_var_atomic_add:
3748 op = LLVMAtomicRMWBinOpAdd;
3749 break;
3750 case nir_intrinsic_var_atomic_umin:
3751 op = LLVMAtomicRMWBinOpUMin;
3752 break;
3753 case nir_intrinsic_var_atomic_umax:
3754 op = LLVMAtomicRMWBinOpUMax;
3755 break;
3756 case nir_intrinsic_var_atomic_imin:
3757 op = LLVMAtomicRMWBinOpMin;
3758 break;
3759 case nir_intrinsic_var_atomic_imax:
3760 op = LLVMAtomicRMWBinOpMax;
3761 break;
3762 case nir_intrinsic_var_atomic_and:
3763 op = LLVMAtomicRMWBinOpAnd;
3764 break;
3765 case nir_intrinsic_var_atomic_or:
3766 op = LLVMAtomicRMWBinOpOr;
3767 break;
3768 case nir_intrinsic_var_atomic_xor:
3769 op = LLVMAtomicRMWBinOpXor;
3770 break;
3771 case nir_intrinsic_var_atomic_exchange:
3772 op = LLVMAtomicRMWBinOpXchg;
3773 break;
3774 default:
3775 return NULL;
3776 }
3777
3778 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3779 LLVMAtomicOrderingSequentiallyConsistent,
3780 false);
3781 }
3782 return result;
3783 }
3784
3785 #define INTERP_CENTER 0
3786 #define INTERP_CENTROID 1
3787 #define INTERP_SAMPLE 2
3788
3789 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3790 enum glsl_interp_mode interp, unsigned location)
3791 {
3792 switch (interp) {
3793 case INTERP_MODE_FLAT:
3794 default:
3795 return NULL;
3796 case INTERP_MODE_SMOOTH:
3797 case INTERP_MODE_NONE:
3798 if (location == INTERP_CENTER)
3799 return ctx->persp_center;
3800 else if (location == INTERP_CENTROID)
3801 return ctx->persp_centroid;
3802 else if (location == INTERP_SAMPLE)
3803 return ctx->persp_sample;
3804 break;
3805 case INTERP_MODE_NOPERSPECTIVE:
3806 if (location == INTERP_CENTER)
3807 return ctx->linear_center;
3808 else if (location == INTERP_CENTROID)
3809 return ctx->linear_centroid;
3810 else if (location == INTERP_SAMPLE)
3811 return ctx->linear_sample;
3812 break;
3813 }
3814 return NULL;
3815 }
3816
3817 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3818 LLVMValueRef sample_id)
3819 {
3820 LLVMValueRef result;
3821 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3822
3823 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3824 const_array(ctx->ac.v2f32, 64), "");
3825
3826 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3827 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3828
3829 return result;
3830 }
3831
3832 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3833 {
3834 LLVMValueRef values[2];
3835
3836 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3837 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3838 return ac_build_gather_values(&ctx->ac, values, 2);
3839 }
3840
3841 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3842 const nir_intrinsic_instr *instr)
3843 {
3844 LLVMValueRef result[4];
3845 LLVMValueRef interp_param, attr_number;
3846 unsigned location;
3847 unsigned chan;
3848 LLVMValueRef src_c0 = NULL;
3849 LLVMValueRef src_c1 = NULL;
3850 LLVMValueRef src0 = NULL;
3851 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3852 switch (instr->intrinsic) {
3853 case nir_intrinsic_interp_var_at_centroid:
3854 location = INTERP_CENTROID;
3855 break;
3856 case nir_intrinsic_interp_var_at_sample:
3857 case nir_intrinsic_interp_var_at_offset:
3858 location = INTERP_CENTER;
3859 src0 = get_src(ctx->nir, instr->src[0]);
3860 break;
3861 default:
3862 break;
3863 }
3864
3865 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3866 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3867 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3868 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3869 LLVMValueRef sample_position;
3870 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
3871
3872 /* fetch sample ID */
3873 sample_position = load_sample_position(ctx, src0);
3874
3875 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
3876 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3877 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
3878 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3879 }
3880 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3881 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
3882
3883 if (location == INTERP_CENTER) {
3884 LLVMValueRef ij_out[2];
3885 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3886
3887 /*
3888 * take the I then J parameters, and the DDX/Y for it, and
3889 * calculate the IJ inputs for the interpolator.
3890 * temp1 = ddx * offset/sample.x + I;
3891 * interp_param.I = ddy * offset/sample.y + temp1;
3892 * temp1 = ddx * offset/sample.x + J;
3893 * interp_param.J = ddy * offset/sample.y + temp1;
3894 */
3895 for (unsigned i = 0; i < 2; i++) {
3896 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
3897 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
3898 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3899 ddxy_out, ix_ll, "");
3900 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3901 ddxy_out, iy_ll, "");
3902 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3903 interp_param, ix_ll, "");
3904 LLVMValueRef temp1, temp2;
3905
3906 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3907 ctx->ac.f32, "");
3908
3909 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3910 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3911
3912 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3913 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3914
3915 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3916 temp2, ctx->ac.i32, "");
3917 }
3918 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3919
3920 }
3921
3922 for (chan = 0; chan < 4; chan++) {
3923 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
3924
3925 if (interp_param) {
3926 interp_param = LLVMBuildBitCast(ctx->builder,
3927 interp_param, ctx->ac.v2f32, "");
3928 LLVMValueRef i = LLVMBuildExtractElement(
3929 ctx->builder, interp_param, ctx->ac.i32_0, "");
3930 LLVMValueRef j = LLVMBuildExtractElement(
3931 ctx->builder, interp_param, ctx->ac.i32_1, "");
3932
3933 result[chan] = ac_build_fs_interp(&ctx->ac,
3934 llvm_chan, attr_number,
3935 ctx->prim_mask, i, j);
3936 } else {
3937 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3938 LLVMConstInt(ctx->ac.i32, 2, false),
3939 llvm_chan, attr_number,
3940 ctx->prim_mask);
3941 }
3942 }
3943 return build_varying_gather_values(&ctx->ac, result, instr->num_components,
3944 instr->variables[0]->var->data.location_frac);
3945 }
3946
3947 static void
3948 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
3949 {
3950 LLVMValueRef gs_next_vertex;
3951 LLVMValueRef can_emit;
3952 int idx;
3953 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3954
3955 /* Write vertex attribute values to GSVS ring */
3956 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3957 ctx->gs_next_vertex,
3958 "");
3959
3960 /* If this thread has already emitted the declared maximum number of
3961 * vertices, kill it: excessive vertex emissions are not supposed to
3962 * have any effect, and GS threads have no externally observable
3963 * effects other than emitting vertices.
3964 */
3965 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3966 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
3967 ac_build_kill_if_false(&ctx->ac, can_emit);
3968
3969 /* loop num outputs */
3970 idx = 0;
3971 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3972 LLVMValueRef *out_ptr = &addrs[i * 4];
3973 int length = 4;
3974 int slot = idx;
3975 int slot_inc = 1;
3976
3977 if (!(ctx->output_mask & (1ull << i)))
3978 continue;
3979
3980 if (i == VARYING_SLOT_CLIP_DIST0) {
3981 /* pack clip and cull into a single set of slots */
3982 length = ctx->num_output_clips + ctx->num_output_culls;
3983 if (length > 4)
3984 slot_inc = 2;
3985 }
3986 for (unsigned j = 0; j < length; j++) {
3987 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3988 out_ptr[j], "");
3989 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3990 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3991 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
3992
3993 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
3994
3995 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3996 out_val, 1,
3997 voffset, ctx->gs2vs_offset, 0,
3998 1, 1, true, true);
3999 }
4000 idx += slot_inc;
4001 }
4002
4003 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4004 ctx->ac.i32_1, "");
4005 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4006
4007 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4008 }
4009
4010 static void
4011 visit_end_primitive(struct nir_to_llvm_context *ctx,
4012 const nir_intrinsic_instr *instr)
4013 {
4014 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4015 }
4016
4017 static LLVMValueRef
4018 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4019 const nir_intrinsic_instr *instr)
4020 {
4021 LLVMValueRef coord[4] = {
4022 ctx->tes_u,
4023 ctx->tes_v,
4024 ctx->ac.f32_0,
4025 ctx->ac.f32_0,
4026 };
4027
4028 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4029 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4030 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4031
4032 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4033 return LLVMBuildBitCast(ctx->builder, result,
4034 get_def_type(ctx->nir, &instr->dest.ssa), "");
4035 }
4036
4037 static void visit_intrinsic(struct ac_nir_context *ctx,
4038 nir_intrinsic_instr *instr)
4039 {
4040 LLVMValueRef result = NULL;
4041
4042 switch (instr->intrinsic) {
4043 case nir_intrinsic_load_work_group_id: {
4044 result = ctx->nctx->workgroup_ids;
4045 break;
4046 }
4047 case nir_intrinsic_load_base_vertex: {
4048 result = ctx->abi->base_vertex;
4049 break;
4050 }
4051 case nir_intrinsic_load_vertex_id_zero_base: {
4052 result = ctx->abi->vertex_id;
4053 break;
4054 }
4055 case nir_intrinsic_load_local_invocation_id: {
4056 result = ctx->nctx->local_invocation_ids;
4057 break;
4058 }
4059 case nir_intrinsic_load_base_instance:
4060 result = ctx->abi->start_instance;
4061 break;
4062 case nir_intrinsic_load_draw_id:
4063 result = ctx->abi->draw_id;
4064 break;
4065 case nir_intrinsic_load_view_index:
4066 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4067 break;
4068 case nir_intrinsic_load_invocation_id:
4069 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4070 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4071 else
4072 result = ctx->abi->gs_invocation_id;
4073 break;
4074 case nir_intrinsic_load_primitive_id:
4075 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4076 if (ctx->nctx)
4077 ctx->nctx->shader_info->gs.uses_prim_id = true;
4078 result = ctx->abi->gs_prim_id;
4079 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4080 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4081 result = ctx->nctx->tcs_patch_id;
4082 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4083 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4084 result = ctx->nctx->tes_patch_id;
4085 } else
4086 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4087 break;
4088 case nir_intrinsic_load_sample_id:
4089 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4090 break;
4091 case nir_intrinsic_load_sample_pos:
4092 result = load_sample_pos(ctx);
4093 break;
4094 case nir_intrinsic_load_sample_mask_in:
4095 result = ctx->abi->sample_coverage;
4096 break;
4097 case nir_intrinsic_load_frag_coord: {
4098 LLVMValueRef values[4] = {
4099 ctx->abi->frag_pos[0],
4100 ctx->abi->frag_pos[1],
4101 ctx->abi->frag_pos[2],
4102 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4103 };
4104 result = ac_build_gather_values(&ctx->ac, values, 4);
4105 break;
4106 }
4107 case nir_intrinsic_load_front_face:
4108 result = ctx->abi->front_face;
4109 break;
4110 case nir_intrinsic_load_instance_id:
4111 result = ctx->abi->instance_id;
4112 break;
4113 case nir_intrinsic_load_num_work_groups:
4114 result = ctx->nctx->num_work_groups;
4115 break;
4116 case nir_intrinsic_load_local_invocation_index:
4117 result = visit_load_local_invocation_index(ctx->nctx);
4118 break;
4119 case nir_intrinsic_load_push_constant:
4120 result = visit_load_push_constant(ctx->nctx, instr);
4121 break;
4122 case nir_intrinsic_vulkan_resource_index:
4123 result = visit_vulkan_resource_index(ctx->nctx, instr);
4124 break;
4125 case nir_intrinsic_store_ssbo:
4126 visit_store_ssbo(ctx, instr);
4127 break;
4128 case nir_intrinsic_load_ssbo:
4129 result = visit_load_buffer(ctx, instr);
4130 break;
4131 case nir_intrinsic_ssbo_atomic_add:
4132 case nir_intrinsic_ssbo_atomic_imin:
4133 case nir_intrinsic_ssbo_atomic_umin:
4134 case nir_intrinsic_ssbo_atomic_imax:
4135 case nir_intrinsic_ssbo_atomic_umax:
4136 case nir_intrinsic_ssbo_atomic_and:
4137 case nir_intrinsic_ssbo_atomic_or:
4138 case nir_intrinsic_ssbo_atomic_xor:
4139 case nir_intrinsic_ssbo_atomic_exchange:
4140 case nir_intrinsic_ssbo_atomic_comp_swap:
4141 result = visit_atomic_ssbo(ctx, instr);
4142 break;
4143 case nir_intrinsic_load_ubo:
4144 result = visit_load_ubo_buffer(ctx, instr);
4145 break;
4146 case nir_intrinsic_get_buffer_size:
4147 result = visit_get_buffer_size(ctx, instr);
4148 break;
4149 case nir_intrinsic_load_var:
4150 result = visit_load_var(ctx, instr);
4151 break;
4152 case nir_intrinsic_store_var:
4153 visit_store_var(ctx, instr);
4154 break;
4155 case nir_intrinsic_image_load:
4156 result = visit_image_load(ctx, instr);
4157 break;
4158 case nir_intrinsic_image_store:
4159 visit_image_store(ctx, instr);
4160 break;
4161 case nir_intrinsic_image_atomic_add:
4162 case nir_intrinsic_image_atomic_min:
4163 case nir_intrinsic_image_atomic_max:
4164 case nir_intrinsic_image_atomic_and:
4165 case nir_intrinsic_image_atomic_or:
4166 case nir_intrinsic_image_atomic_xor:
4167 case nir_intrinsic_image_atomic_exchange:
4168 case nir_intrinsic_image_atomic_comp_swap:
4169 result = visit_image_atomic(ctx, instr);
4170 break;
4171 case nir_intrinsic_image_size:
4172 result = visit_image_size(ctx, instr);
4173 break;
4174 case nir_intrinsic_discard:
4175 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4176 LLVMVoidTypeInContext(ctx->ac.context),
4177 NULL, 0, AC_FUNC_ATTR_LEGACY);
4178 break;
4179 case nir_intrinsic_discard_if:
4180 emit_discard_if(ctx, instr);
4181 break;
4182 case nir_intrinsic_memory_barrier:
4183 case nir_intrinsic_group_memory_barrier:
4184 case nir_intrinsic_memory_barrier_atomic_counter:
4185 case nir_intrinsic_memory_barrier_buffer:
4186 case nir_intrinsic_memory_barrier_image:
4187 case nir_intrinsic_memory_barrier_shared:
4188 emit_membar(ctx->nctx, instr);
4189 break;
4190 case nir_intrinsic_barrier:
4191 emit_barrier(ctx->nctx);
4192 break;
4193 case nir_intrinsic_var_atomic_add:
4194 case nir_intrinsic_var_atomic_imin:
4195 case nir_intrinsic_var_atomic_umin:
4196 case nir_intrinsic_var_atomic_imax:
4197 case nir_intrinsic_var_atomic_umax:
4198 case nir_intrinsic_var_atomic_and:
4199 case nir_intrinsic_var_atomic_or:
4200 case nir_intrinsic_var_atomic_xor:
4201 case nir_intrinsic_var_atomic_exchange:
4202 case nir_intrinsic_var_atomic_comp_swap:
4203 result = visit_var_atomic(ctx->nctx, instr);
4204 break;
4205 case nir_intrinsic_interp_var_at_centroid:
4206 case nir_intrinsic_interp_var_at_sample:
4207 case nir_intrinsic_interp_var_at_offset:
4208 result = visit_interp(ctx->nctx, instr);
4209 break;
4210 case nir_intrinsic_emit_vertex:
4211 assert(instr->const_index[0] == 0);
4212 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4213 break;
4214 case nir_intrinsic_end_primitive:
4215 visit_end_primitive(ctx->nctx, instr);
4216 break;
4217 case nir_intrinsic_load_tess_coord:
4218 result = visit_load_tess_coord(ctx->nctx, instr);
4219 break;
4220 case nir_intrinsic_load_patch_vertices_in:
4221 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4222 break;
4223 default:
4224 fprintf(stderr, "Unknown intrinsic: ");
4225 nir_print_instr(&instr->instr, stderr);
4226 fprintf(stderr, "\n");
4227 break;
4228 }
4229 if (result) {
4230 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4231 }
4232 }
4233
4234 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4235 LLVMValueRef buffer, bool write)
4236 {
4237 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4238
4239 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4240 ctx->shader_info->fs.writes_memory = true;
4241
4242 return buffer;
4243 }
4244
4245 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4246 unsigned descriptor_set,
4247 unsigned base_index,
4248 unsigned constant_index,
4249 LLVMValueRef index,
4250 enum ac_descriptor_type desc_type,
4251 bool image, bool write)
4252 {
4253 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4254 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4255 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4256 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4257 unsigned offset = binding->offset;
4258 unsigned stride = binding->size;
4259 unsigned type_size;
4260 LLVMBuilderRef builder = ctx->builder;
4261 LLVMTypeRef type;
4262
4263 assert(base_index < layout->binding_count);
4264
4265 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4266 ctx->shader_info->fs.writes_memory = true;
4267
4268 switch (desc_type) {
4269 case AC_DESC_IMAGE:
4270 type = ctx->ac.v8i32;
4271 type_size = 32;
4272 break;
4273 case AC_DESC_FMASK:
4274 type = ctx->ac.v8i32;
4275 offset += 32;
4276 type_size = 32;
4277 break;
4278 case AC_DESC_SAMPLER:
4279 type = ctx->ac.v4i32;
4280 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4281 offset += 64;
4282
4283 type_size = 16;
4284 break;
4285 case AC_DESC_BUFFER:
4286 type = ctx->ac.v4i32;
4287 type_size = 16;
4288 break;
4289 default:
4290 unreachable("invalid desc_type\n");
4291 }
4292
4293 offset += constant_index * stride;
4294
4295 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4296 (!index || binding->immutable_samplers_equal)) {
4297 if (binding->immutable_samplers_equal)
4298 constant_index = 0;
4299
4300 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4301
4302 LLVMValueRef constants[] = {
4303 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4304 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4305 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4306 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4307 };
4308 return ac_build_gather_values(&ctx->ac, constants, 4);
4309 }
4310
4311 assert(stride % type_size == 0);
4312
4313 if (!index)
4314 index = ctx->ac.i32_0;
4315
4316 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4317
4318 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4319 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4320
4321 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4322 }
4323
4324 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4325 const nir_deref_var *deref,
4326 enum ac_descriptor_type desc_type,
4327 const nir_tex_instr *tex_instr,
4328 bool image, bool write)
4329 {
4330 LLVMValueRef index = NULL;
4331 unsigned constant_index = 0;
4332 unsigned descriptor_set;
4333 unsigned base_index;
4334
4335 if (!deref) {
4336 assert(tex_instr && !image);
4337 descriptor_set = 0;
4338 base_index = tex_instr->sampler_index;
4339 } else {
4340 const nir_deref *tail = &deref->deref;
4341 while (tail->child) {
4342 const nir_deref_array *child = nir_deref_as_array(tail->child);
4343 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4344
4345 if (!array_size)
4346 array_size = 1;
4347
4348 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4349
4350 if (child->deref_array_type == nir_deref_array_type_indirect) {
4351 LLVMValueRef indirect = get_src(ctx, child->indirect);
4352
4353 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4354 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4355
4356 if (!index)
4357 index = indirect;
4358 else
4359 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4360 }
4361
4362 constant_index += child->base_offset * array_size;
4363
4364 tail = &child->deref;
4365 }
4366 descriptor_set = deref->var->data.descriptor_set;
4367 base_index = deref->var->data.binding;
4368 }
4369
4370 return ctx->abi->load_sampler_desc(ctx->abi,
4371 descriptor_set,
4372 base_index,
4373 constant_index, index,
4374 desc_type, image, write);
4375 }
4376
4377 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4378 struct ac_image_args *args,
4379 const nir_tex_instr *instr,
4380 nir_texop op,
4381 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4382 LLVMValueRef *param, unsigned count,
4383 unsigned dmask)
4384 {
4385 unsigned is_rect = 0;
4386 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4387
4388 if (op == nir_texop_lod)
4389 da = false;
4390 /* Pad to power of two vector */
4391 while (count < util_next_power_of_two(count))
4392 param[count++] = LLVMGetUndef(ctx->i32);
4393
4394 if (count > 1)
4395 args->addr = ac_build_gather_values(ctx, param, count);
4396 else
4397 args->addr = param[0];
4398
4399 args->resource = res_ptr;
4400 args->sampler = samp_ptr;
4401
4402 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4403 args->addr = param[0];
4404 return;
4405 }
4406
4407 args->dmask = dmask;
4408 args->unorm = is_rect;
4409 args->da = da;
4410 }
4411
4412 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4413 *
4414 * SI-CI:
4415 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4416 * filtering manually. The driver sets img7 to a mask clearing
4417 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4418 * s_and_b32 samp0, samp0, img7
4419 *
4420 * VI:
4421 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4422 */
4423 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4424 LLVMValueRef res, LLVMValueRef samp)
4425 {
4426 LLVMBuilderRef builder = ctx->ac.builder;
4427 LLVMValueRef img7, samp0;
4428
4429 if (ctx->ac.chip_class >= VI)
4430 return samp;
4431
4432 img7 = LLVMBuildExtractElement(builder, res,
4433 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4434 samp0 = LLVMBuildExtractElement(builder, samp,
4435 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4436 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4437 return LLVMBuildInsertElement(builder, samp, samp0,
4438 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4439 }
4440
4441 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4442 nir_tex_instr *instr,
4443 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4444 LLVMValueRef *fmask_ptr)
4445 {
4446 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4447 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4448 else
4449 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4450 if (samp_ptr) {
4451 if (instr->sampler)
4452 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4453 else
4454 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4455 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4456 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4457 }
4458 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4459 instr->op == nir_texop_samples_identical))
4460 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4461 }
4462
4463 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4464 LLVMValueRef coord)
4465 {
4466 coord = ac_to_float(ctx, coord);
4467 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4468 coord = ac_to_integer(ctx, coord);
4469 return coord;
4470 }
4471
4472 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4473 {
4474 LLVMValueRef result = NULL;
4475 struct ac_image_args args = { 0 };
4476 unsigned dmask = 0xf;
4477 LLVMValueRef address[16];
4478 LLVMValueRef coords[5];
4479 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4480 LLVMValueRef bias = NULL, offsets = NULL;
4481 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4482 LLVMValueRef ddx = NULL, ddy = NULL;
4483 LLVMValueRef derivs[6];
4484 unsigned chan, count = 0;
4485 unsigned const_src = 0, num_deriv_comp = 0;
4486 bool lod_is_zero = false;
4487
4488 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4489
4490 for (unsigned i = 0; i < instr->num_srcs; i++) {
4491 switch (instr->src[i].src_type) {
4492 case nir_tex_src_coord:
4493 coord = get_src(ctx, instr->src[i].src);
4494 break;
4495 case nir_tex_src_projector:
4496 break;
4497 case nir_tex_src_comparator:
4498 comparator = get_src(ctx, instr->src[i].src);
4499 break;
4500 case nir_tex_src_offset:
4501 offsets = get_src(ctx, instr->src[i].src);
4502 const_src = i;
4503 break;
4504 case nir_tex_src_bias:
4505 bias = get_src(ctx, instr->src[i].src);
4506 break;
4507 case nir_tex_src_lod: {
4508 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4509
4510 if (val && val->i32[0] == 0)
4511 lod_is_zero = true;
4512 lod = get_src(ctx, instr->src[i].src);
4513 break;
4514 }
4515 case nir_tex_src_ms_index:
4516 sample_index = get_src(ctx, instr->src[i].src);
4517 break;
4518 case nir_tex_src_ms_mcs:
4519 break;
4520 case nir_tex_src_ddx:
4521 ddx = get_src(ctx, instr->src[i].src);
4522 num_deriv_comp = instr->src[i].src.ssa->num_components;
4523 break;
4524 case nir_tex_src_ddy:
4525 ddy = get_src(ctx, instr->src[i].src);
4526 break;
4527 case nir_tex_src_texture_offset:
4528 case nir_tex_src_sampler_offset:
4529 case nir_tex_src_plane:
4530 default:
4531 break;
4532 }
4533 }
4534
4535 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4536 result = get_buffer_size(ctx, res_ptr, true);
4537 goto write_result;
4538 }
4539
4540 if (instr->op == nir_texop_texture_samples) {
4541 LLVMValueRef res, samples, is_msaa;
4542 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4543 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4544 LLVMConstInt(ctx->ac.i32, 3, false), "");
4545 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4546 LLVMConstInt(ctx->ac.i32, 28, false), "");
4547 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4548 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4549 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4550 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4551
4552 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4553 LLVMConstInt(ctx->ac.i32, 16, false), "");
4554 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4555 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4556 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4557 samples, "");
4558 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4559 ctx->ac.i32_1, "");
4560 result = samples;
4561 goto write_result;
4562 }
4563
4564 if (coord)
4565 for (chan = 0; chan < instr->coord_components; chan++)
4566 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4567
4568 if (offsets && instr->op != nir_texop_txf) {
4569 LLVMValueRef offset[3], pack;
4570 for (chan = 0; chan < 3; ++chan)
4571 offset[chan] = ctx->ac.i32_0;
4572
4573 args.offset = true;
4574 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4575 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4576 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4577 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4578 if (chan)
4579 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4580 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4581 }
4582 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4583 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4584 address[count++] = pack;
4585
4586 }
4587 /* pack LOD bias value */
4588 if (instr->op == nir_texop_txb && bias) {
4589 address[count++] = bias;
4590 }
4591
4592 /* Pack depth comparison value */
4593 if (instr->is_shadow && comparator) {
4594 LLVMValueRef z = ac_to_float(&ctx->ac,
4595 llvm_extract_elem(&ctx->ac, comparator, 0));
4596
4597 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4598 * so the depth comparison value isn't clamped for Z16 and
4599 * Z24 anymore. Do it manually here.
4600 *
4601 * It's unnecessary if the original texture format was
4602 * Z32_FLOAT, but we don't know that here.
4603 */
4604 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4605 z = ac_build_clamp(&ctx->ac, z);
4606
4607 address[count++] = z;
4608 }
4609
4610 /* pack derivatives */
4611 if (ddx || ddy) {
4612 int num_src_deriv_channels, num_dest_deriv_channels;
4613 switch (instr->sampler_dim) {
4614 case GLSL_SAMPLER_DIM_3D:
4615 case GLSL_SAMPLER_DIM_CUBE:
4616 num_deriv_comp = 3;
4617 num_src_deriv_channels = 3;
4618 num_dest_deriv_channels = 3;
4619 break;
4620 case GLSL_SAMPLER_DIM_2D:
4621 default:
4622 num_src_deriv_channels = 2;
4623 num_dest_deriv_channels = 2;
4624 num_deriv_comp = 2;
4625 break;
4626 case GLSL_SAMPLER_DIM_1D:
4627 num_src_deriv_channels = 1;
4628 if (ctx->ac.chip_class >= GFX9) {
4629 num_dest_deriv_channels = 2;
4630 num_deriv_comp = 2;
4631 } else {
4632 num_dest_deriv_channels = 1;
4633 num_deriv_comp = 1;
4634 }
4635 break;
4636 }
4637
4638 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4639 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4640 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4641 }
4642 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4643 derivs[i] = ctx->ac.f32_0;
4644 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4645 }
4646 }
4647
4648 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4649 for (chan = 0; chan < instr->coord_components; chan++)
4650 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4651 if (instr->coord_components == 3)
4652 coords[3] = LLVMGetUndef(ctx->ac.f32);
4653 ac_prepare_cube_coords(&ctx->ac,
4654 instr->op == nir_texop_txd, instr->is_array,
4655 instr->op == nir_texop_lod, coords, derivs);
4656 if (num_deriv_comp)
4657 num_deriv_comp--;
4658 }
4659
4660 if (ddx || ddy) {
4661 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4662 address[count++] = derivs[i];
4663 }
4664
4665 /* Pack texture coordinates */
4666 if (coord) {
4667 address[count++] = coords[0];
4668 if (instr->coord_components > 1) {
4669 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4670 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4671 }
4672 address[count++] = coords[1];
4673 }
4674 if (instr->coord_components > 2) {
4675 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4676 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4677 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4678 instr->op != nir_texop_txf) {
4679 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4680 }
4681 address[count++] = coords[2];
4682 }
4683
4684 if (ctx->ac.chip_class >= GFX9) {
4685 LLVMValueRef filler;
4686 if (instr->op == nir_texop_txf)
4687 filler = ctx->ac.i32_0;
4688 else
4689 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4690
4691 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4692 /* No nir_texop_lod, because it does not take a slice
4693 * even with array textures. */
4694 if (instr->is_array && instr->op != nir_texop_lod ) {
4695 address[count] = address[count - 1];
4696 address[count - 1] = filler;
4697 count++;
4698 } else
4699 address[count++] = filler;
4700 }
4701 }
4702 }
4703
4704 /* Pack LOD */
4705 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4706 instr->op == nir_texop_txf)) {
4707 address[count++] = lod;
4708 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4709 address[count++] = sample_index;
4710 } else if(instr->op == nir_texop_txs) {
4711 count = 0;
4712 if (lod)
4713 address[count++] = lod;
4714 else
4715 address[count++] = ctx->ac.i32_0;
4716 }
4717
4718 for (chan = 0; chan < count; chan++) {
4719 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4720 address[chan], ctx->ac.i32, "");
4721 }
4722
4723 if (instr->op == nir_texop_samples_identical) {
4724 LLVMValueRef txf_address[4];
4725 struct ac_image_args txf_args = { 0 };
4726 unsigned txf_count = count;
4727 memcpy(txf_address, address, sizeof(txf_address));
4728
4729 if (!instr->is_array)
4730 txf_address[2] = ctx->ac.i32_0;
4731 txf_address[3] = ctx->ac.i32_0;
4732
4733 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4734 fmask_ptr, NULL,
4735 txf_address, txf_count, 0xf);
4736
4737 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4738
4739 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4740 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4741 goto write_result;
4742 }
4743
4744 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4745 instr->op != nir_texop_txs) {
4746 unsigned sample_chan = instr->is_array ? 3 : 2;
4747 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4748 address[0],
4749 address[1],
4750 instr->is_array ? address[2] : NULL,
4751 address[sample_chan],
4752 fmask_ptr);
4753 }
4754
4755 if (offsets && instr->op == nir_texop_txf) {
4756 nir_const_value *const_offset =
4757 nir_src_as_const_value(instr->src[const_src].src);
4758 int num_offsets = instr->src[const_src].src.ssa->num_components;
4759 assert(const_offset);
4760 num_offsets = MIN2(num_offsets, instr->coord_components);
4761 if (num_offsets > 2)
4762 address[2] = LLVMBuildAdd(ctx->ac.builder,
4763 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4764 if (num_offsets > 1)
4765 address[1] = LLVMBuildAdd(ctx->ac.builder,
4766 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4767 address[0] = LLVMBuildAdd(ctx->ac.builder,
4768 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4769
4770 }
4771
4772 /* TODO TG4 support */
4773 if (instr->op == nir_texop_tg4) {
4774 if (instr->is_shadow)
4775 dmask = 1;
4776 else
4777 dmask = 1 << instr->component;
4778 }
4779 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4780 res_ptr, samp_ptr, address, count, dmask);
4781
4782 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4783
4784 if (instr->op == nir_texop_query_levels)
4785 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4786 else if (instr->is_shadow && instr->is_new_style_shadow &&
4787 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4788 instr->op != nir_texop_tg4)
4789 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4790 else if (instr->op == nir_texop_txs &&
4791 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4792 instr->is_array) {
4793 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4794 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4795 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4796 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4797 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4798 } else if (ctx->ac.chip_class >= GFX9 &&
4799 instr->op == nir_texop_txs &&
4800 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4801 instr->is_array) {
4802 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4803 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4804 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4805 ctx->ac.i32_1, "");
4806 } else if (instr->dest.ssa.num_components != 4)
4807 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4808
4809 write_result:
4810 if (result) {
4811 assert(instr->dest.is_ssa);
4812 result = ac_to_integer(&ctx->ac, result);
4813 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4814 }
4815 }
4816
4817
4818 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4819 {
4820 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4821 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4822
4823 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4824 _mesa_hash_table_insert(ctx->phis, instr, result);
4825 }
4826
4827 static void visit_post_phi(struct ac_nir_context *ctx,
4828 nir_phi_instr *instr,
4829 LLVMValueRef llvm_phi)
4830 {
4831 nir_foreach_phi_src(src, instr) {
4832 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4833 LLVMValueRef llvm_src = get_src(ctx, src->src);
4834
4835 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4836 }
4837 }
4838
4839 static void phi_post_pass(struct ac_nir_context *ctx)
4840 {
4841 struct hash_entry *entry;
4842 hash_table_foreach(ctx->phis, entry) {
4843 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4844 (LLVMValueRef)entry->data);
4845 }
4846 }
4847
4848
4849 static void visit_ssa_undef(struct ac_nir_context *ctx,
4850 const nir_ssa_undef_instr *instr)
4851 {
4852 unsigned num_components = instr->def.num_components;
4853 LLVMValueRef undef;
4854
4855 if (num_components == 1)
4856 undef = LLVMGetUndef(ctx->ac.i32);
4857 else {
4858 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4859 }
4860 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4861 }
4862
4863 static void visit_jump(struct ac_nir_context *ctx,
4864 const nir_jump_instr *instr)
4865 {
4866 switch (instr->type) {
4867 case nir_jump_break:
4868 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4869 LLVMClearInsertionPosition(ctx->ac.builder);
4870 break;
4871 case nir_jump_continue:
4872 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4873 LLVMClearInsertionPosition(ctx->ac.builder);
4874 break;
4875 default:
4876 fprintf(stderr, "Unknown NIR jump instr: ");
4877 nir_print_instr(&instr->instr, stderr);
4878 fprintf(stderr, "\n");
4879 abort();
4880 }
4881 }
4882
4883 static void visit_cf_list(struct ac_nir_context *ctx,
4884 struct exec_list *list);
4885
4886 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4887 {
4888 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4889 nir_foreach_instr(instr, block)
4890 {
4891 switch (instr->type) {
4892 case nir_instr_type_alu:
4893 visit_alu(ctx, nir_instr_as_alu(instr));
4894 break;
4895 case nir_instr_type_load_const:
4896 visit_load_const(ctx, nir_instr_as_load_const(instr));
4897 break;
4898 case nir_instr_type_intrinsic:
4899 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4900 break;
4901 case nir_instr_type_tex:
4902 visit_tex(ctx, nir_instr_as_tex(instr));
4903 break;
4904 case nir_instr_type_phi:
4905 visit_phi(ctx, nir_instr_as_phi(instr));
4906 break;
4907 case nir_instr_type_ssa_undef:
4908 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4909 break;
4910 case nir_instr_type_jump:
4911 visit_jump(ctx, nir_instr_as_jump(instr));
4912 break;
4913 default:
4914 fprintf(stderr, "Unknown NIR instr type: ");
4915 nir_print_instr(instr, stderr);
4916 fprintf(stderr, "\n");
4917 abort();
4918 }
4919 }
4920
4921 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4922 }
4923
4924 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4925 {
4926 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4927
4928 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4929 LLVMBasicBlockRef merge_block =
4930 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4931 LLVMBasicBlockRef if_block =
4932 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4933 LLVMBasicBlockRef else_block = merge_block;
4934 if (!exec_list_is_empty(&if_stmt->else_list))
4935 else_block = LLVMAppendBasicBlockInContext(
4936 ctx->ac.context, fn, "");
4937
4938 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4939 LLVMConstInt(ctx->ac.i32, 0, false), "");
4940 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4941
4942 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4943 visit_cf_list(ctx, &if_stmt->then_list);
4944 if (LLVMGetInsertBlock(ctx->ac.builder))
4945 LLVMBuildBr(ctx->ac.builder, merge_block);
4946
4947 if (!exec_list_is_empty(&if_stmt->else_list)) {
4948 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4949 visit_cf_list(ctx, &if_stmt->else_list);
4950 if (LLVMGetInsertBlock(ctx->ac.builder))
4951 LLVMBuildBr(ctx->ac.builder, merge_block);
4952 }
4953
4954 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4955 }
4956
4957 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4958 {
4959 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4960 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4961 LLVMBasicBlockRef break_parent = ctx->break_block;
4962
4963 ctx->continue_block =
4964 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4965 ctx->break_block =
4966 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4967
4968 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4969 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4970 visit_cf_list(ctx, &loop->body);
4971
4972 if (LLVMGetInsertBlock(ctx->ac.builder))
4973 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4974 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4975
4976 ctx->continue_block = continue_parent;
4977 ctx->break_block = break_parent;
4978 }
4979
4980 static void visit_cf_list(struct ac_nir_context *ctx,
4981 struct exec_list *list)
4982 {
4983 foreach_list_typed(nir_cf_node, node, node, list)
4984 {
4985 switch (node->type) {
4986 case nir_cf_node_block:
4987 visit_block(ctx, nir_cf_node_as_block(node));
4988 break;
4989
4990 case nir_cf_node_if:
4991 visit_if(ctx, nir_cf_node_as_if(node));
4992 break;
4993
4994 case nir_cf_node_loop:
4995 visit_loop(ctx, nir_cf_node_as_loop(node));
4996 break;
4997
4998 default:
4999 assert(0);
5000 }
5001 }
5002 }
5003
5004 static void
5005 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5006 struct nir_variable *variable)
5007 {
5008 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5009 LLVMValueRef t_offset;
5010 LLVMValueRef t_list;
5011 LLVMValueRef input;
5012 LLVMValueRef buffer_index;
5013 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5014 int idx = variable->data.location;
5015 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5016
5017 variable->data.driver_location = idx * 4;
5018
5019 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5020 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5021 ctx->abi.start_instance, "");
5022 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5023 ctx->shader_info->vs.vgpr_comp_cnt);
5024 } else
5025 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5026 ctx->abi.base_vertex, "");
5027
5028 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5029 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5030
5031 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5032
5033 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5034 buffer_index,
5035 LLVMConstInt(ctx->ac.i32, 0, false),
5036 true);
5037
5038 for (unsigned chan = 0; chan < 4; chan++) {
5039 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5040 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5041 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5042 input, llvm_chan, ""));
5043 }
5044 }
5045 }
5046
5047 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5048 unsigned attr,
5049 LLVMValueRef interp_param,
5050 LLVMValueRef prim_mask,
5051 LLVMValueRef result[4])
5052 {
5053 LLVMValueRef attr_number;
5054 unsigned chan;
5055 LLVMValueRef i, j;
5056 bool interp = interp_param != NULL;
5057
5058 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5059
5060 /* fs.constant returns the param from the middle vertex, so it's not
5061 * really useful for flat shading. It's meant to be used for custom
5062 * interpolation (but the intrinsic can't fetch from the other two
5063 * vertices).
5064 *
5065 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5066 * to do the right thing. The only reason we use fs.constant is that
5067 * fs.interp cannot be used on integers, because they can be equal
5068 * to NaN.
5069 */
5070 if (interp) {
5071 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5072 ctx->ac.v2f32, "");
5073
5074 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5075 ctx->ac.i32_0, "");
5076 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5077 ctx->ac.i32_1, "");
5078 }
5079
5080 for (chan = 0; chan < 4; chan++) {
5081 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5082
5083 if (interp) {
5084 result[chan] = ac_build_fs_interp(&ctx->ac,
5085 llvm_chan,
5086 attr_number,
5087 prim_mask, i, j);
5088 } else {
5089 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5090 LLVMConstInt(ctx->ac.i32, 2, false),
5091 llvm_chan,
5092 attr_number,
5093 prim_mask);
5094 }
5095 }
5096 }
5097
5098 static void
5099 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5100 struct nir_variable *variable)
5101 {
5102 int idx = variable->data.location;
5103 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5104 LLVMValueRef interp;
5105
5106 variable->data.driver_location = idx * 4;
5107 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5108
5109 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5110 unsigned interp_type;
5111 if (variable->data.sample) {
5112 interp_type = INTERP_SAMPLE;
5113 ctx->shader_info->info.ps.force_persample = true;
5114 } else if (variable->data.centroid)
5115 interp_type = INTERP_CENTROID;
5116 else
5117 interp_type = INTERP_CENTER;
5118
5119 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5120 } else
5121 interp = NULL;
5122
5123 for (unsigned i = 0; i < attrib_count; ++i)
5124 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5125
5126 }
5127
5128 static void
5129 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5130 struct nir_shader *nir) {
5131 nir_foreach_variable(variable, &nir->inputs)
5132 handle_vs_input_decl(ctx, variable);
5133 }
5134
5135 static void
5136 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5137 struct nir_shader *nir)
5138 {
5139 if (!ctx->options->key.fs.multisample)
5140 return;
5141
5142 bool uses_center = false;
5143 bool uses_centroid = false;
5144 nir_foreach_variable(variable, &nir->inputs) {
5145 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5146 variable->data.sample)
5147 continue;
5148
5149 if (variable->data.centroid)
5150 uses_centroid = true;
5151 else
5152 uses_center = true;
5153 }
5154
5155 if (uses_center && uses_centroid) {
5156 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5157 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5158 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5159 }
5160 }
5161
5162 static void
5163 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5164 struct nir_shader *nir)
5165 {
5166 prepare_interp_optimize(ctx, nir);
5167
5168 nir_foreach_variable(variable, &nir->inputs)
5169 handle_fs_input_decl(ctx, variable);
5170
5171 unsigned index = 0;
5172
5173 if (ctx->shader_info->info.ps.uses_input_attachments ||
5174 ctx->shader_info->info.needs_multiview_view_index)
5175 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5176
5177 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5178 LLVMValueRef interp_param;
5179 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5180
5181 if (!(ctx->input_mask & (1ull << i)))
5182 continue;
5183
5184 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5185 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5186 interp_param = *inputs;
5187 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5188 inputs);
5189
5190 if (!interp_param)
5191 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5192 ++index;
5193 } else if (i == VARYING_SLOT_POS) {
5194 for(int i = 0; i < 3; ++i)
5195 inputs[i] = ctx->abi.frag_pos[i];
5196
5197 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5198 ctx->abi.frag_pos[3]);
5199 }
5200 }
5201 ctx->shader_info->fs.num_interp = index;
5202 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5203 ctx->shader_info->fs.has_pcoord = true;
5204 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5205 ctx->shader_info->fs.prim_id_input = true;
5206 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5207 ctx->shader_info->fs.layer_input = true;
5208 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5209
5210 if (ctx->shader_info->info.needs_multiview_view_index)
5211 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5212 }
5213
5214 static LLVMValueRef
5215 ac_build_alloca(struct ac_llvm_context *ac,
5216 LLVMTypeRef type,
5217 const char *name)
5218 {
5219 LLVMBuilderRef builder = ac->builder;
5220 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5221 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5222 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5223 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5224 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5225 LLVMValueRef res;
5226
5227 if (first_instr) {
5228 LLVMPositionBuilderBefore(first_builder, first_instr);
5229 } else {
5230 LLVMPositionBuilderAtEnd(first_builder, first_block);
5231 }
5232
5233 res = LLVMBuildAlloca(first_builder, type, name);
5234 LLVMBuildStore(builder, LLVMConstNull(type), res);
5235
5236 LLVMDisposeBuilder(first_builder);
5237
5238 return res;
5239 }
5240
5241 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5242 LLVMTypeRef type,
5243 const char *name)
5244 {
5245 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5246 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5247 return ptr;
5248 }
5249
5250 static void
5251 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5252 struct nir_variable *variable,
5253 struct nir_shader *shader,
5254 gl_shader_stage stage)
5255 {
5256 int idx = variable->data.location + variable->data.index;
5257 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5258 uint64_t mask_attribs;
5259
5260 variable->data.driver_location = idx * 4;
5261
5262 /* tess ctrl has it's own load/store paths for outputs */
5263 if (stage == MESA_SHADER_TESS_CTRL)
5264 return;
5265
5266 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5267 if (stage == MESA_SHADER_VERTEX ||
5268 stage == MESA_SHADER_TESS_EVAL ||
5269 stage == MESA_SHADER_GEOMETRY) {
5270 if (idx == VARYING_SLOT_CLIP_DIST0) {
5271 int length = shader->info.clip_distance_array_size +
5272 shader->info.cull_distance_array_size;
5273 if (stage == MESA_SHADER_VERTEX) {
5274 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5275 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5276 }
5277 if (stage == MESA_SHADER_TESS_EVAL) {
5278 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5279 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5280 }
5281
5282 if (length > 4)
5283 attrib_count = 2;
5284 else
5285 attrib_count = 1;
5286 mask_attribs = 1ull << idx;
5287 }
5288 }
5289
5290 ctx->output_mask |= mask_attribs;
5291 }
5292
5293 static void
5294 handle_shader_output_decl(struct ac_nir_context *ctx,
5295 struct nir_shader *nir,
5296 struct nir_variable *variable)
5297 {
5298 unsigned output_loc = variable->data.driver_location / 4;
5299 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5300
5301 /* tess ctrl has it's own load/store paths for outputs */
5302 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5303 return;
5304
5305 if (ctx->stage == MESA_SHADER_VERTEX ||
5306 ctx->stage == MESA_SHADER_TESS_EVAL ||
5307 ctx->stage == MESA_SHADER_GEOMETRY) {
5308 int idx = variable->data.location + variable->data.index;
5309 if (idx == VARYING_SLOT_CLIP_DIST0) {
5310 int length = nir->info.clip_distance_array_size +
5311 nir->info.cull_distance_array_size;
5312
5313 if (length > 4)
5314 attrib_count = 2;
5315 else
5316 attrib_count = 1;
5317 }
5318 }
5319
5320 for (unsigned i = 0; i < attrib_count; ++i) {
5321 for (unsigned chan = 0; chan < 4; chan++) {
5322 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5323 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5324 }
5325 }
5326 }
5327
5328 static LLVMTypeRef
5329 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5330 enum glsl_base_type type)
5331 {
5332 switch (type) {
5333 case GLSL_TYPE_INT:
5334 case GLSL_TYPE_UINT:
5335 case GLSL_TYPE_BOOL:
5336 case GLSL_TYPE_SUBROUTINE:
5337 return ctx->ac.i32;
5338 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5339 return ctx->ac.f32;
5340 case GLSL_TYPE_INT64:
5341 case GLSL_TYPE_UINT64:
5342 return ctx->ac.i64;
5343 case GLSL_TYPE_DOUBLE:
5344 return ctx->ac.f64;
5345 default:
5346 unreachable("unknown GLSL type");
5347 }
5348 }
5349
5350 static LLVMTypeRef
5351 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5352 const struct glsl_type *type)
5353 {
5354 if (glsl_type_is_scalar(type)) {
5355 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5356 }
5357
5358 if (glsl_type_is_vector(type)) {
5359 return LLVMVectorType(
5360 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5361 glsl_get_vector_elements(type));
5362 }
5363
5364 if (glsl_type_is_matrix(type)) {
5365 return LLVMArrayType(
5366 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5367 glsl_get_matrix_columns(type));
5368 }
5369
5370 if (glsl_type_is_array(type)) {
5371 return LLVMArrayType(
5372 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5373 glsl_get_length(type));
5374 }
5375
5376 assert(glsl_type_is_struct(type));
5377
5378 LLVMTypeRef member_types[glsl_get_length(type)];
5379
5380 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5381 member_types[i] =
5382 glsl_to_llvm_type(ctx,
5383 glsl_get_struct_field(type, i));
5384 }
5385
5386 return LLVMStructTypeInContext(ctx->context, member_types,
5387 glsl_get_length(type), false);
5388 }
5389
5390 static void
5391 setup_locals(struct ac_nir_context *ctx,
5392 struct nir_function *func)
5393 {
5394 int i, j;
5395 ctx->num_locals = 0;
5396 nir_foreach_variable(variable, &func->impl->locals) {
5397 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5398 variable->data.driver_location = ctx->num_locals * 4;
5399 ctx->num_locals += attrib_count;
5400 }
5401 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5402 if (!ctx->locals)
5403 return;
5404
5405 for (i = 0; i < ctx->num_locals; i++) {
5406 for (j = 0; j < 4; j++) {
5407 ctx->locals[i * 4 + j] =
5408 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5409 }
5410 }
5411 }
5412
5413 static void
5414 setup_shared(struct ac_nir_context *ctx,
5415 struct nir_shader *nir)
5416 {
5417 nir_foreach_variable(variable, &nir->shared) {
5418 LLVMValueRef shared =
5419 LLVMAddGlobalInAddressSpace(
5420 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5421 variable->name ? variable->name : "",
5422 LOCAL_ADDR_SPACE);
5423 _mesa_hash_table_insert(ctx->vars, variable, shared);
5424 }
5425 }
5426
5427 static LLVMValueRef
5428 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5429 {
5430 v = ac_to_float(ctx, v);
5431 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5432 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5433 }
5434
5435
5436 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5437 LLVMValueRef src0, LLVMValueRef src1)
5438 {
5439 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5440 LLVMValueRef comp[2];
5441
5442 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5443 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5444 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5445 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5446 }
5447
5448 /* Initialize arguments for the shader export intrinsic */
5449 static void
5450 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5451 LLVMValueRef *values,
5452 unsigned target,
5453 struct ac_export_args *args)
5454 {
5455 /* Default is 0xf. Adjusted below depending on the format. */
5456 args->enabled_channels = 0xf;
5457
5458 /* Specify whether the EXEC mask represents the valid mask */
5459 args->valid_mask = 0;
5460
5461 /* Specify whether this is the last export */
5462 args->done = 0;
5463
5464 /* Specify the target we are exporting */
5465 args->target = target;
5466
5467 args->compr = false;
5468 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5469 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5470 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5471 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5472
5473 if (!values)
5474 return;
5475
5476 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5477 LLVMValueRef val[4];
5478 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5479 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5480 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5481 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5482
5483 switch(col_format) {
5484 case V_028714_SPI_SHADER_ZERO:
5485 args->enabled_channels = 0; /* writemask */
5486 args->target = V_008DFC_SQ_EXP_NULL;
5487 break;
5488
5489 case V_028714_SPI_SHADER_32_R:
5490 args->enabled_channels = 1;
5491 args->out[0] = values[0];
5492 break;
5493
5494 case V_028714_SPI_SHADER_32_GR:
5495 args->enabled_channels = 0x3;
5496 args->out[0] = values[0];
5497 args->out[1] = values[1];
5498 break;
5499
5500 case V_028714_SPI_SHADER_32_AR:
5501 args->enabled_channels = 0x9;
5502 args->out[0] = values[0];
5503 args->out[3] = values[3];
5504 break;
5505
5506 case V_028714_SPI_SHADER_FP16_ABGR:
5507 args->compr = 1;
5508
5509 for (unsigned chan = 0; chan < 2; chan++) {
5510 LLVMValueRef pack_args[2] = {
5511 values[2 * chan],
5512 values[2 * chan + 1]
5513 };
5514 LLVMValueRef packed;
5515
5516 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5517 args->out[chan] = packed;
5518 }
5519 break;
5520
5521 case V_028714_SPI_SHADER_UNORM16_ABGR:
5522 for (unsigned chan = 0; chan < 4; chan++) {
5523 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5524 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5525 LLVMConstReal(ctx->ac.f32, 65535), "");
5526 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5527 LLVMConstReal(ctx->ac.f32, 0.5), "");
5528 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5529 ctx->ac.i32, "");
5530 }
5531
5532 args->compr = 1;
5533 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5534 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5535 break;
5536
5537 case V_028714_SPI_SHADER_SNORM16_ABGR:
5538 for (unsigned chan = 0; chan < 4; chan++) {
5539 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5540 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5541 LLVMConstReal(ctx->ac.f32, 32767), "");
5542
5543 /* If positive, add 0.5, else add -0.5. */
5544 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5545 LLVMBuildSelect(ctx->builder,
5546 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5547 val[chan], ctx->ac.f32_0, ""),
5548 LLVMConstReal(ctx->ac.f32, 0.5),
5549 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5550 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5551 }
5552
5553 args->compr = 1;
5554 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5555 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5556 break;
5557
5558 case V_028714_SPI_SHADER_UINT16_ABGR: {
5559 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5560 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5561 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5562
5563 for (unsigned chan = 0; chan < 4; chan++) {
5564 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5565 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5566 }
5567
5568 args->compr = 1;
5569 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5570 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5571 break;
5572 }
5573
5574 case V_028714_SPI_SHADER_SINT16_ABGR: {
5575 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5576 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5577 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5578 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5579 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5580 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5581
5582 /* Clamp. */
5583 for (unsigned chan = 0; chan < 4; chan++) {
5584 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5585 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5586 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5587 }
5588
5589 args->compr = 1;
5590 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5591 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5592 break;
5593 }
5594
5595 default:
5596 case V_028714_SPI_SHADER_32_ABGR:
5597 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5598 break;
5599 }
5600 } else
5601 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5602
5603 for (unsigned i = 0; i < 4; ++i)
5604 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5605 }
5606
5607 static void
5608 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5609 bool export_prim_id,
5610 struct ac_vs_output_info *outinfo)
5611 {
5612 uint32_t param_count = 0;
5613 unsigned target;
5614 unsigned pos_idx, num_pos_exports = 0;
5615 struct ac_export_args args, pos_args[4] = {};
5616 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5617 int i;
5618
5619 if (ctx->options->key.has_multiview_view_index) {
5620 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5621 if(!*tmp_out) {
5622 for(unsigned i = 0; i < 4; ++i)
5623 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5624 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5625 }
5626
5627 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5628 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5629 }
5630
5631 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5632 sizeof(outinfo->vs_output_param_offset));
5633
5634 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5635 LLVMValueRef slots[8];
5636 unsigned j;
5637
5638 if (outinfo->cull_dist_mask)
5639 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5640
5641 i = VARYING_SLOT_CLIP_DIST0;
5642 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5643 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5644 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5645
5646 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5647 slots[i] = LLVMGetUndef(ctx->ac.f32);
5648
5649 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5650 target = V_008DFC_SQ_EXP_POS + 3;
5651 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5652 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5653 &args, sizeof(args));
5654 }
5655
5656 target = V_008DFC_SQ_EXP_POS + 2;
5657 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5658 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5659 &args, sizeof(args));
5660
5661 }
5662
5663 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5664 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5665 for (unsigned j = 0; j < 4; j++)
5666 pos_values[j] = LLVMBuildLoad(ctx->builder,
5667 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5668 }
5669 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5670
5671 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5672 outinfo->writes_pointsize = true;
5673 psize_value = LLVMBuildLoad(ctx->builder,
5674 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5675 }
5676
5677 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5678 outinfo->writes_layer = true;
5679 layer_value = LLVMBuildLoad(ctx->builder,
5680 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5681 }
5682
5683 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5684 outinfo->writes_viewport_index = true;
5685 viewport_index_value = LLVMBuildLoad(ctx->builder,
5686 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5687 }
5688
5689 if (outinfo->writes_pointsize ||
5690 outinfo->writes_layer ||
5691 outinfo->writes_viewport_index) {
5692 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5693 (outinfo->writes_layer == true ? 4 : 0));
5694 pos_args[1].valid_mask = 0;
5695 pos_args[1].done = 0;
5696 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5697 pos_args[1].compr = 0;
5698 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5699 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5700 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5701 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5702
5703 if (outinfo->writes_pointsize == true)
5704 pos_args[1].out[0] = psize_value;
5705 if (outinfo->writes_layer == true)
5706 pos_args[1].out[2] = layer_value;
5707 if (outinfo->writes_viewport_index == true) {
5708 if (ctx->options->chip_class >= GFX9) {
5709 /* GFX9 has the layer in out.z[10:0] and the viewport
5710 * index in out.z[19:16].
5711 */
5712 LLVMValueRef v = viewport_index_value;
5713 v = ac_to_integer(&ctx->ac, v);
5714 v = LLVMBuildShl(ctx->builder, v,
5715 LLVMConstInt(ctx->ac.i32, 16, false),
5716 "");
5717 v = LLVMBuildOr(ctx->builder, v,
5718 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5719
5720 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5721 pos_args[1].enabled_channels |= 1 << 2;
5722 } else {
5723 pos_args[1].out[3] = viewport_index_value;
5724 pos_args[1].enabled_channels |= 1 << 3;
5725 }
5726 }
5727 }
5728 for (i = 0; i < 4; i++) {
5729 if (pos_args[i].out[0])
5730 num_pos_exports++;
5731 }
5732
5733 pos_idx = 0;
5734 for (i = 0; i < 4; i++) {
5735 if (!pos_args[i].out[0])
5736 continue;
5737
5738 /* Specify the target we are exporting */
5739 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5740 if (pos_idx == num_pos_exports)
5741 pos_args[i].done = 1;
5742 ac_build_export(&ctx->ac, &pos_args[i]);
5743 }
5744
5745 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5746 LLVMValueRef values[4];
5747 if (!(ctx->output_mask & (1ull << i)))
5748 continue;
5749
5750 for (unsigned j = 0; j < 4; j++)
5751 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5752 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5753
5754 if (i == VARYING_SLOT_LAYER) {
5755 target = V_008DFC_SQ_EXP_PARAM + param_count;
5756 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5757 param_count++;
5758 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5759 target = V_008DFC_SQ_EXP_PARAM + param_count;
5760 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5761 param_count++;
5762 } else if (i >= VARYING_SLOT_VAR0) {
5763 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5764 target = V_008DFC_SQ_EXP_PARAM + param_count;
5765 outinfo->vs_output_param_offset[i] = param_count;
5766 param_count++;
5767 } else
5768 continue;
5769
5770 si_llvm_init_export_args(ctx, values, target, &args);
5771
5772 if (target >= V_008DFC_SQ_EXP_POS &&
5773 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5774 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5775 &args, sizeof(args));
5776 } else {
5777 ac_build_export(&ctx->ac, &args);
5778 }
5779 }
5780
5781 if (export_prim_id) {
5782 LLVMValueRef values[4];
5783 target = V_008DFC_SQ_EXP_PARAM + param_count;
5784 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5785 param_count++;
5786
5787 values[0] = ctx->vs_prim_id;
5788 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5789 ctx->shader_info->vs.vgpr_comp_cnt);
5790 for (unsigned j = 1; j < 4; j++)
5791 values[j] = ctx->ac.f32_0;
5792 si_llvm_init_export_args(ctx, values, target, &args);
5793 ac_build_export(&ctx->ac, &args);
5794 outinfo->export_prim_id = true;
5795 }
5796
5797 outinfo->pos_exports = num_pos_exports;
5798 outinfo->param_exports = param_count;
5799 }
5800
5801 static void
5802 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5803 struct ac_es_output_info *outinfo)
5804 {
5805 int j;
5806 uint64_t max_output_written = 0;
5807 LLVMValueRef lds_base = NULL;
5808
5809 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5810 int param_index;
5811 int length = 4;
5812
5813 if (!(ctx->output_mask & (1ull << i)))
5814 continue;
5815
5816 if (i == VARYING_SLOT_CLIP_DIST0)
5817 length = ctx->num_output_clips + ctx->num_output_culls;
5818
5819 param_index = shader_io_get_unique_index(i);
5820
5821 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5822 }
5823
5824 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5825
5826 if (ctx->ac.chip_class >= GFX9) {
5827 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5828 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5829 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5830 LLVMConstInt(ctx->ac.i32, 24, false),
5831 LLVMConstInt(ctx->ac.i32, 4, false), false);
5832 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5833 LLVMBuildMul(ctx->ac.builder, wave_idx,
5834 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5835 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5836 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5837 }
5838
5839 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5840 LLVMValueRef dw_addr;
5841 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5842 int param_index;
5843 int length = 4;
5844
5845 if (!(ctx->output_mask & (1ull << i)))
5846 continue;
5847
5848 if (i == VARYING_SLOT_CLIP_DIST0)
5849 length = ctx->num_output_clips + ctx->num_output_culls;
5850
5851 param_index = shader_io_get_unique_index(i);
5852
5853 if (lds_base) {
5854 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5855 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
5856 "");
5857 }
5858 for (j = 0; j < length; j++) {
5859 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5860 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
5861
5862 if (ctx->ac.chip_class >= GFX9) {
5863 ac_lds_store(&ctx->ac, dw_addr,
5864 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5865 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5866 } else {
5867 ac_build_buffer_store_dword(&ctx->ac,
5868 ctx->esgs_ring,
5869 out_val, 1,
5870 NULL, ctx->es2gs_offset,
5871 (4 * param_index + j) * 4,
5872 1, 1, true, true);
5873 }
5874 }
5875 }
5876 }
5877
5878 static void
5879 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5880 {
5881 LLVMValueRef vertex_id = ctx->rel_auto_id;
5882 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5883 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5884 vertex_dw_stride, "");
5885
5886 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5887 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5888 int length = 4;
5889
5890 if (!(ctx->output_mask & (1ull << i)))
5891 continue;
5892
5893 if (i == VARYING_SLOT_CLIP_DIST0)
5894 length = ctx->num_output_clips + ctx->num_output_culls;
5895 int param = shader_io_get_unique_index(i);
5896 mark_tess_output(ctx, false, param);
5897 if (length > 4)
5898 mark_tess_output(ctx, false, param + 1);
5899 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5900 LLVMConstInt(ctx->ac.i32, param * 4, false),
5901 "");
5902 for (unsigned j = 0; j < length; j++) {
5903 ac_lds_store(&ctx->ac, dw_addr,
5904 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5905 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5906 }
5907 }
5908 }
5909
5910 struct ac_build_if_state
5911 {
5912 struct nir_to_llvm_context *ctx;
5913 LLVMValueRef condition;
5914 LLVMBasicBlockRef entry_block;
5915 LLVMBasicBlockRef true_block;
5916 LLVMBasicBlockRef false_block;
5917 LLVMBasicBlockRef merge_block;
5918 };
5919
5920 static LLVMBasicBlockRef
5921 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5922 {
5923 LLVMBasicBlockRef current_block;
5924 LLVMBasicBlockRef next_block;
5925 LLVMBasicBlockRef new_block;
5926
5927 /* get current basic block */
5928 current_block = LLVMGetInsertBlock(ctx->builder);
5929
5930 /* chqeck if there's another block after this one */
5931 next_block = LLVMGetNextBasicBlock(current_block);
5932 if (next_block) {
5933 /* insert the new block before the next block */
5934 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5935 }
5936 else {
5937 /* append new block after current block */
5938 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5939 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5940 }
5941 return new_block;
5942 }
5943
5944 static void
5945 ac_nir_build_if(struct ac_build_if_state *ifthen,
5946 struct nir_to_llvm_context *ctx,
5947 LLVMValueRef condition)
5948 {
5949 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5950
5951 memset(ifthen, 0, sizeof *ifthen);
5952 ifthen->ctx = ctx;
5953 ifthen->condition = condition;
5954 ifthen->entry_block = block;
5955
5956 /* create endif/merge basic block for the phi functions */
5957 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5958
5959 /* create/insert true_block before merge_block */
5960 ifthen->true_block =
5961 LLVMInsertBasicBlockInContext(ctx->context,
5962 ifthen->merge_block,
5963 "if-true-block");
5964
5965 /* successive code goes into the true block */
5966 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5967 }
5968
5969 /**
5970 * End a conditional.
5971 */
5972 static void
5973 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5974 {
5975 LLVMBuilderRef builder = ifthen->ctx->builder;
5976
5977 /* Insert branch to the merge block from current block */
5978 LLVMBuildBr(builder, ifthen->merge_block);
5979
5980 /*
5981 * Now patch in the various branch instructions.
5982 */
5983
5984 /* Insert the conditional branch instruction at the end of entry_block */
5985 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5986 if (ifthen->false_block) {
5987 /* we have an else clause */
5988 LLVMBuildCondBr(builder, ifthen->condition,
5989 ifthen->true_block, ifthen->false_block);
5990 }
5991 else {
5992 /* no else clause */
5993 LLVMBuildCondBr(builder, ifthen->condition,
5994 ifthen->true_block, ifthen->merge_block);
5995 }
5996
5997 /* Resume building code at end of the ifthen->merge_block */
5998 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5999 }
6000
6001 static void
6002 write_tess_factors(struct nir_to_llvm_context *ctx)
6003 {
6004 unsigned stride, outer_comps, inner_comps;
6005 struct ac_build_if_state if_ctx, inner_if_ctx;
6006 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6007 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6008 unsigned tess_inner_index, tess_outer_index;
6009 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6010 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6011 int i;
6012 emit_barrier(ctx);
6013
6014 switch (ctx->options->key.tcs.primitive_mode) {
6015 case GL_ISOLINES:
6016 stride = 2;
6017 outer_comps = 2;
6018 inner_comps = 0;
6019 break;
6020 case GL_TRIANGLES:
6021 stride = 4;
6022 outer_comps = 3;
6023 inner_comps = 1;
6024 break;
6025 case GL_QUADS:
6026 stride = 6;
6027 outer_comps = 4;
6028 inner_comps = 2;
6029 break;
6030 default:
6031 return;
6032 }
6033
6034 ac_nir_build_if(&if_ctx, ctx,
6035 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6036 invocation_id, ctx->ac.i32_0, ""));
6037
6038 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6039 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6040
6041 mark_tess_output(ctx, true, tess_inner_index);
6042 mark_tess_output(ctx, true, tess_outer_index);
6043 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6044 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6045 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6046 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6047 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6048
6049 for (i = 0; i < 4; i++) {
6050 inner[i] = LLVMGetUndef(ctx->ac.i32);
6051 outer[i] = LLVMGetUndef(ctx->ac.i32);
6052 }
6053
6054 // LINES reverseal
6055 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6056 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6057 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6058 LLVMConstInt(ctx->ac.i32, 1, false), "");
6059 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6060 } else {
6061 for (i = 0; i < outer_comps; i++) {
6062 outer[i] = out[i] =
6063 ac_lds_load(&ctx->ac, lds_outer);
6064 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6065 LLVMConstInt(ctx->ac.i32, 1, false), "");
6066 }
6067 for (i = 0; i < inner_comps; i++) {
6068 inner[i] = out[outer_comps+i] =
6069 ac_lds_load(&ctx->ac, lds_inner);
6070 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6071 LLVMConstInt(ctx->ac.i32, 1, false), "");
6072 }
6073 }
6074
6075 /* Convert the outputs to vectors for stores. */
6076 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6077 vec1 = NULL;
6078
6079 if (stride > 4)
6080 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6081
6082
6083 buffer = ctx->hs_ring_tess_factor;
6084 tf_base = ctx->tess_factor_offset;
6085 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6086 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6087 unsigned tf_offset = 0;
6088
6089 if (ctx->options->chip_class <= VI) {
6090 ac_nir_build_if(&inner_if_ctx, ctx,
6091 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6092 rel_patch_id, ctx->ac.i32_0, ""));
6093
6094 /* Store the dynamic HS control word. */
6095 ac_build_buffer_store_dword(&ctx->ac, buffer,
6096 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6097 1, ctx->ac.i32_0, tf_base,
6098 0, 1, 0, true, false);
6099 tf_offset += 4;
6100
6101 ac_nir_build_endif(&inner_if_ctx);
6102 }
6103
6104 /* Store the tessellation factors. */
6105 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6106 MIN2(stride, 4), byteoffset, tf_base,
6107 tf_offset, 1, 0, true, false);
6108 if (vec1)
6109 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6110 stride - 4, byteoffset, tf_base,
6111 16 + tf_offset, 1, 0, true, false);
6112
6113 //store to offchip for TES to read - only if TES reads them
6114 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6115 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6116 LLVMValueRef tf_inner_offset;
6117 unsigned param_outer, param_inner;
6118
6119 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6120 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6121 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6122
6123 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6124 util_next_power_of_two(outer_comps));
6125
6126 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6127 outer_comps, tf_outer_offset,
6128 ctx->oc_lds, 0, 1, 0, true, false);
6129 if (inner_comps) {
6130 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6131 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6132 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6133
6134 inner_vec = inner_comps == 1 ? inner[0] :
6135 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6136 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6137 inner_comps, tf_inner_offset,
6138 ctx->oc_lds, 0, 1, 0, true, false);
6139 }
6140 }
6141 ac_nir_build_endif(&if_ctx);
6142 }
6143
6144 static void
6145 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6146 {
6147 write_tess_factors(ctx);
6148 }
6149
6150 static bool
6151 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6152 LLVMValueRef *color, unsigned param, bool is_last,
6153 struct ac_export_args *args)
6154 {
6155 /* Export */
6156 si_llvm_init_export_args(ctx, color, param,
6157 args);
6158
6159 if (is_last) {
6160 args->valid_mask = 1; /* whether the EXEC mask is valid */
6161 args->done = 1; /* DONE bit */
6162 } else if (!args->enabled_channels)
6163 return false; /* unnecessary NULL export */
6164
6165 return true;
6166 }
6167
6168 static void
6169 si_export_mrt_z(struct nir_to_llvm_context *ctx,
6170 LLVMValueRef depth, LLVMValueRef stencil,
6171 LLVMValueRef samplemask)
6172 {
6173 struct ac_export_args args;
6174
6175 args.enabled_channels = 0;
6176 args.valid_mask = 1;
6177 args.done = 1;
6178 args.target = V_008DFC_SQ_EXP_MRTZ;
6179 args.compr = false;
6180
6181 args.out[0] = LLVMGetUndef(ctx->ac.f32); /* R, depth */
6182 args.out[1] = LLVMGetUndef(ctx->ac.f32); /* G, stencil test val[0:7], stencil op val[8:15] */
6183 args.out[2] = LLVMGetUndef(ctx->ac.f32); /* B, sample mask */
6184 args.out[3] = LLVMGetUndef(ctx->ac.f32); /* A, alpha to mask */
6185
6186 if (depth) {
6187 args.out[0] = depth;
6188 args.enabled_channels |= 0x1;
6189 }
6190
6191 if (stencil) {
6192 args.out[1] = stencil;
6193 args.enabled_channels |= 0x2;
6194 }
6195
6196 if (samplemask) {
6197 args.out[2] = samplemask;
6198 args.enabled_channels |= 0x4;
6199 }
6200
6201 /* SI (except OLAND and HAINAN) has a bug that it only looks
6202 * at the X writemask component. */
6203 if (ctx->options->chip_class == SI &&
6204 ctx->options->family != CHIP_OLAND &&
6205 ctx->options->family != CHIP_HAINAN)
6206 args.enabled_channels |= 0x1;
6207
6208 ac_build_export(&ctx->ac, &args);
6209 }
6210
6211 static void
6212 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6213 {
6214 unsigned index = 0;
6215 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6216 struct ac_export_args color_args[8];
6217
6218 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6219 LLVMValueRef values[4];
6220
6221 if (!(ctx->output_mask & (1ull << i)))
6222 continue;
6223
6224 if (i == FRAG_RESULT_DEPTH) {
6225 ctx->shader_info->fs.writes_z = true;
6226 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6227 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6228 } else if (i == FRAG_RESULT_STENCIL) {
6229 ctx->shader_info->fs.writes_stencil = true;
6230 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6231 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6232 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6233 ctx->shader_info->fs.writes_sample_mask = true;
6234 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6235 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6236 } else {
6237 bool last = false;
6238 for (unsigned j = 0; j < 4; j++)
6239 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6240 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6241
6242 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6243 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6244
6245 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6246 if (ret)
6247 index++;
6248 }
6249 }
6250
6251 for (unsigned i = 0; i < index; i++)
6252 ac_build_export(&ctx->ac, &color_args[i]);
6253 if (depth || stencil || samplemask)
6254 si_export_mrt_z(ctx, depth, stencil, samplemask);
6255 else if (!index) {
6256 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6257 ac_build_export(&ctx->ac, &color_args[0]);
6258 }
6259
6260 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6261 }
6262
6263 static void
6264 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6265 {
6266 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6267 }
6268
6269 static void
6270 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6271 LLVMValueRef *addrs)
6272 {
6273 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6274
6275 switch (ctx->stage) {
6276 case MESA_SHADER_VERTEX:
6277 if (ctx->options->key.vs.as_ls)
6278 handle_ls_outputs_post(ctx);
6279 else if (ctx->options->key.vs.as_es)
6280 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6281 else
6282 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6283 &ctx->shader_info->vs.outinfo);
6284 break;
6285 case MESA_SHADER_FRAGMENT:
6286 handle_fs_outputs_post(ctx);
6287 break;
6288 case MESA_SHADER_GEOMETRY:
6289 emit_gs_epilogue(ctx);
6290 break;
6291 case MESA_SHADER_TESS_CTRL:
6292 handle_tcs_outputs_post(ctx);
6293 break;
6294 case MESA_SHADER_TESS_EVAL:
6295 if (ctx->options->key.tes.as_es)
6296 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6297 else
6298 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6299 &ctx->shader_info->tes.outinfo);
6300 break;
6301 default:
6302 break;
6303 }
6304 }
6305
6306 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6307 {
6308 LLVMPassManagerRef passmgr;
6309 /* Create the pass manager */
6310 passmgr = LLVMCreateFunctionPassManagerForModule(
6311 ctx->module);
6312
6313 /* This pass should eliminate all the load and store instructions */
6314 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6315
6316 /* Add some optimization passes */
6317 LLVMAddScalarReplAggregatesPass(passmgr);
6318 LLVMAddLICMPass(passmgr);
6319 LLVMAddAggressiveDCEPass(passmgr);
6320 LLVMAddCFGSimplificationPass(passmgr);
6321 LLVMAddInstructionCombiningPass(passmgr);
6322
6323 /* Run the pass */
6324 LLVMInitializeFunctionPassManager(passmgr);
6325 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6326 LLVMFinalizeFunctionPassManager(passmgr);
6327
6328 LLVMDisposeBuilder(ctx->builder);
6329 LLVMDisposePassManager(passmgr);
6330 }
6331
6332 static void
6333 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6334 {
6335 struct ac_vs_output_info *outinfo;
6336
6337 switch (ctx->stage) {
6338 case MESA_SHADER_FRAGMENT:
6339 case MESA_SHADER_COMPUTE:
6340 case MESA_SHADER_TESS_CTRL:
6341 case MESA_SHADER_GEOMETRY:
6342 return;
6343 case MESA_SHADER_VERTEX:
6344 if (ctx->options->key.vs.as_ls ||
6345 ctx->options->key.vs.as_es)
6346 return;
6347 outinfo = &ctx->shader_info->vs.outinfo;
6348 break;
6349 case MESA_SHADER_TESS_EVAL:
6350 if (ctx->options->key.vs.as_es)
6351 return;
6352 outinfo = &ctx->shader_info->tes.outinfo;
6353 break;
6354 default:
6355 unreachable("Unhandled shader type");
6356 }
6357
6358 ac_optimize_vs_outputs(&ctx->ac,
6359 ctx->main_function,
6360 outinfo->vs_output_param_offset,
6361 VARYING_SLOT_MAX,
6362 &outinfo->param_exports);
6363 }
6364
6365 static void
6366 ac_setup_rings(struct nir_to_llvm_context *ctx)
6367 {
6368 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6369 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6370 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6371 }
6372
6373 if (ctx->is_gs_copy_shader) {
6374 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6375 }
6376 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6377 LLVMValueRef tmp;
6378 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6379 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6380
6381 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6382
6383 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6384 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6385 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6386 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6387 }
6388
6389 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6390 ctx->stage == MESA_SHADER_TESS_EVAL) {
6391 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6392 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6393 }
6394 }
6395
6396 static unsigned
6397 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6398 const struct nir_shader *nir)
6399 {
6400 switch (nir->info.stage) {
6401 case MESA_SHADER_TESS_CTRL:
6402 return chip_class >= CIK ? 128 : 64;
6403 case MESA_SHADER_GEOMETRY:
6404 return chip_class >= GFX9 ? 128 : 64;
6405 case MESA_SHADER_COMPUTE:
6406 break;
6407 default:
6408 return 0;
6409 }
6410
6411 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6412 nir->info.cs.local_size[1] *
6413 nir->info.cs.local_size[2];
6414 return max_workgroup_size;
6415 }
6416
6417 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6418 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6419 {
6420 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6421 LLVMConstInt(ctx->ac.i32, 8, false),
6422 LLVMConstInt(ctx->ac.i32, 8, false), false);
6423 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6424 LLVMConstInt(ctx->ac.i32, 0, false), "");
6425 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6426 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6427 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6428 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6429 }
6430
6431 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6432 {
6433 for(int i = 5; i >= 0; --i) {
6434 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6435 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6436 LLVMConstInt(ctx->ac.i32, 16, false), false);
6437 }
6438
6439 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6440 LLVMConstInt(ctx->ac.i32, 16, false),
6441 LLVMConstInt(ctx->ac.i32, 8, false), false);
6442 }
6443
6444 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6445 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6446 {
6447 struct ac_nir_context ctx = {};
6448 struct nir_function *func;
6449
6450 ctx.ac = *ac;
6451 ctx.abi = abi;
6452
6453 ctx.nctx = nctx;
6454 if (nctx)
6455 nctx->nir = &ctx;
6456
6457 ctx.stage = nir->info.stage;
6458
6459 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6460
6461 nir_foreach_variable(variable, &nir->outputs)
6462 handle_shader_output_decl(&ctx, nir, variable);
6463
6464 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6465 _mesa_key_pointer_equal);
6466 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6467 _mesa_key_pointer_equal);
6468 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6469 _mesa_key_pointer_equal);
6470
6471 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6472
6473 setup_locals(&ctx, func);
6474
6475 if (nir->info.stage == MESA_SHADER_COMPUTE)
6476 setup_shared(&ctx, nir);
6477
6478 visit_cf_list(&ctx, &func->impl->body);
6479 phi_post_pass(&ctx);
6480
6481 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6482 ctx.outputs);
6483
6484 free(ctx.locals);
6485 ralloc_free(ctx.defs);
6486 ralloc_free(ctx.phis);
6487 ralloc_free(ctx.vars);
6488
6489 if (nctx)
6490 nctx->nir = NULL;
6491 }
6492
6493 static
6494 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6495 struct nir_shader *const *shaders,
6496 int shader_count,
6497 struct ac_shader_variant_info *shader_info,
6498 const struct ac_nir_compiler_options *options)
6499 {
6500 struct nir_to_llvm_context ctx = {0};
6501 unsigned i;
6502 ctx.options = options;
6503 ctx.shader_info = shader_info;
6504 ctx.context = LLVMContextCreate();
6505 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6506
6507 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6508 ctx.ac.module = ctx.module;
6509 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6510
6511 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6512 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6513 LLVMSetDataLayout(ctx.module, data_layout_str);
6514 LLVMDisposeTargetData(data_layout);
6515 LLVMDisposeMessage(data_layout_str);
6516
6517 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6518 ctx.ac.builder = ctx.builder;
6519
6520 memset(shader_info, 0, sizeof(*shader_info));
6521
6522 for(int i = 0; i < shader_count; ++i)
6523 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6524
6525 for (i = 0; i < AC_UD_MAX_SETS; i++)
6526 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6527 for (i = 0; i < AC_UD_MAX_UD; i++)
6528 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6529
6530 ctx.max_workgroup_size = 0;
6531 for (int i = 0; i < shader_count; ++i) {
6532 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6533 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6534 shaders[i]));
6535 }
6536
6537 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6538 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6539
6540 ctx.abi.inputs = &ctx.inputs[0];
6541 ctx.abi.emit_outputs = handle_shader_outputs_post;
6542 ctx.abi.emit_vertex = visit_emit_vertex;
6543 ctx.abi.load_ssbo = radv_load_ssbo;
6544 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6545 ctx.abi.clamp_shadow_reference = false;
6546
6547 if (shader_count >= 2)
6548 ac_init_exec_full_mask(&ctx.ac);
6549
6550 if (ctx.ac.chip_class == GFX9 &&
6551 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6552 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6553
6554 for(int i = 0; i < shader_count; ++i) {
6555 ctx.stage = shaders[i]->info.stage;
6556 ctx.output_mask = 0;
6557 ctx.tess_outputs_written = 0;
6558 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6559 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6560
6561 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6562 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6563
6564 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6565 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6566 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6567 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6568 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6569 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6570 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6571 if (shader_info->info.vs.needs_instance_id) {
6572 ctx.shader_info->vs.vgpr_comp_cnt =
6573 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6574 }
6575 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6576 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6577 }
6578
6579 if (i)
6580 emit_barrier(&ctx);
6581
6582 ac_setup_rings(&ctx);
6583
6584 LLVMBasicBlockRef merge_block;
6585 if (shader_count >= 2) {
6586 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6587 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6588 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6589
6590 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6591 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6592 LLVMConstInt(ctx.ac.i32, 8, false), false);
6593 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6594 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6595 thread_id, count, "");
6596 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6597
6598 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6599 }
6600
6601 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6602 handle_fs_inputs(&ctx, shaders[i]);
6603 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6604 handle_vs_inputs(&ctx, shaders[i]);
6605 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6606 prepare_gs_input_vgprs(&ctx);
6607
6608 nir_foreach_variable(variable, &shaders[i]->outputs)
6609 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6610
6611 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6612
6613 if (shader_count >= 2) {
6614 LLVMBuildBr(ctx.ac.builder, merge_block);
6615 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6616 }
6617
6618 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6619 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6620 shaders[i]->info.cull_distance_array_size > 4;
6621 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6622 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6623 shaders[i]->info.gs.vertices_out;
6624 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6625 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6626 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6627 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6628 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6629 }
6630 }
6631
6632 LLVMBuildRetVoid(ctx.builder);
6633
6634 ac_llvm_finalize_module(&ctx);
6635
6636 if (shader_count == 1)
6637 ac_nir_eliminate_const_vs_outputs(&ctx);
6638
6639 return ctx.module;
6640 }
6641
6642 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6643 {
6644 unsigned *retval = (unsigned *)context;
6645 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6646 char *description = LLVMGetDiagInfoDescription(di);
6647
6648 if (severity == LLVMDSError) {
6649 *retval = 1;
6650 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6651 description);
6652 }
6653
6654 LLVMDisposeMessage(description);
6655 }
6656
6657 static unsigned ac_llvm_compile(LLVMModuleRef M,
6658 struct ac_shader_binary *binary,
6659 LLVMTargetMachineRef tm)
6660 {
6661 unsigned retval = 0;
6662 char *err;
6663 LLVMContextRef llvm_ctx;
6664 LLVMMemoryBufferRef out_buffer;
6665 unsigned buffer_size;
6666 const char *buffer_data;
6667 LLVMBool mem_err;
6668
6669 /* Setup Diagnostic Handler*/
6670 llvm_ctx = LLVMGetModuleContext(M);
6671
6672 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6673 &retval);
6674
6675 /* Compile IR*/
6676 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6677 &err, &out_buffer);
6678
6679 /* Process Errors/Warnings */
6680 if (mem_err) {
6681 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6682 free(err);
6683 retval = 1;
6684 goto out;
6685 }
6686
6687 /* Extract Shader Code*/
6688 buffer_size = LLVMGetBufferSize(out_buffer);
6689 buffer_data = LLVMGetBufferStart(out_buffer);
6690
6691 ac_elf_read(buffer_data, buffer_size, binary);
6692
6693 /* Clean up */
6694 LLVMDisposeMemoryBuffer(out_buffer);
6695
6696 out:
6697 return retval;
6698 }
6699
6700 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6701 LLVMModuleRef llvm_module,
6702 struct ac_shader_binary *binary,
6703 struct ac_shader_config *config,
6704 struct ac_shader_variant_info *shader_info,
6705 gl_shader_stage stage,
6706 bool dump_shader, bool supports_spill)
6707 {
6708 if (dump_shader)
6709 ac_dump_module(llvm_module);
6710
6711 memset(binary, 0, sizeof(*binary));
6712 int v = ac_llvm_compile(llvm_module, binary, tm);
6713 if (v) {
6714 fprintf(stderr, "compile failed\n");
6715 }
6716
6717 if (dump_shader)
6718 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6719
6720 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6721
6722 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6723 LLVMDisposeModule(llvm_module);
6724 LLVMContextDispose(ctx);
6725
6726 if (stage == MESA_SHADER_FRAGMENT) {
6727 shader_info->num_input_vgprs = 0;
6728 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6729 shader_info->num_input_vgprs += 2;
6730 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6731 shader_info->num_input_vgprs += 2;
6732 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6733 shader_info->num_input_vgprs += 2;
6734 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6735 shader_info->num_input_vgprs += 3;
6736 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6737 shader_info->num_input_vgprs += 2;
6738 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6739 shader_info->num_input_vgprs += 2;
6740 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6741 shader_info->num_input_vgprs += 2;
6742 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6743 shader_info->num_input_vgprs += 1;
6744 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6745 shader_info->num_input_vgprs += 1;
6746 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6747 shader_info->num_input_vgprs += 1;
6748 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6749 shader_info->num_input_vgprs += 1;
6750 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6751 shader_info->num_input_vgprs += 1;
6752 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6753 shader_info->num_input_vgprs += 1;
6754 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6755 shader_info->num_input_vgprs += 1;
6756 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6757 shader_info->num_input_vgprs += 1;
6758 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6759 shader_info->num_input_vgprs += 1;
6760 }
6761 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6762
6763 /* +3 for scratch wave offset and VCC */
6764 config->num_sgprs = MAX2(config->num_sgprs,
6765 shader_info->num_input_sgprs + 3);
6766 }
6767
6768 static void
6769 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6770 {
6771 switch (nir->info.stage) {
6772 case MESA_SHADER_COMPUTE:
6773 for (int i = 0; i < 3; ++i)
6774 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6775 break;
6776 case MESA_SHADER_FRAGMENT:
6777 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6778 break;
6779 case MESA_SHADER_GEOMETRY:
6780 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6781 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6782 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6783 shader_info->gs.invocations = nir->info.gs.invocations;
6784 break;
6785 case MESA_SHADER_TESS_EVAL:
6786 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6787 shader_info->tes.spacing = nir->info.tess.spacing;
6788 shader_info->tes.ccw = nir->info.tess.ccw;
6789 shader_info->tes.point_mode = nir->info.tess.point_mode;
6790 shader_info->tes.as_es = options->key.tes.as_es;
6791 break;
6792 case MESA_SHADER_TESS_CTRL:
6793 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6794 break;
6795 case MESA_SHADER_VERTEX:
6796 shader_info->vs.as_es = options->key.vs.as_es;
6797 shader_info->vs.as_ls = options->key.vs.as_ls;
6798 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6799 if (options->key.vs.as_ls)
6800 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6801 break;
6802 default:
6803 break;
6804 }
6805 }
6806
6807 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6808 struct ac_shader_binary *binary,
6809 struct ac_shader_config *config,
6810 struct ac_shader_variant_info *shader_info,
6811 struct nir_shader *const *nir,
6812 int nir_count,
6813 const struct ac_nir_compiler_options *options,
6814 bool dump_shader)
6815 {
6816
6817 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6818 options);
6819
6820 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6821 for (int i = 0; i < nir_count; ++i)
6822 ac_fill_shader_info(shader_info, nir[i], options);
6823 }
6824
6825 static void
6826 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6827 {
6828 LLVMValueRef args[9];
6829 args[0] = ctx->gsvs_ring;
6830 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6831 args[3] = ctx->ac.i32_0;
6832 args[4] = ctx->ac.i32_1; /* OFFEN */
6833 args[5] = ctx->ac.i32_0; /* IDXEN */
6834 args[6] = ctx->ac.i32_1; /* GLC */
6835 args[7] = ctx->ac.i32_1; /* SLC */
6836 args[8] = ctx->ac.i32_0; /* TFE */
6837
6838 int idx = 0;
6839
6840 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6841 int length = 4;
6842 int slot = idx;
6843 int slot_inc = 1;
6844 if (!(ctx->output_mask & (1ull << i)))
6845 continue;
6846
6847 if (i == VARYING_SLOT_CLIP_DIST0) {
6848 /* unpack clip and cull from a single set of slots */
6849 length = ctx->num_output_clips + ctx->num_output_culls;
6850 if (length > 4)
6851 slot_inc = 2;
6852 }
6853
6854 for (unsigned j = 0; j < length; j++) {
6855 LLVMValueRef value;
6856 args[2] = LLVMConstInt(ctx->ac.i32,
6857 (slot * 4 + j) *
6858 ctx->gs_max_out_vertices * 16 * 4, false);
6859
6860 value = ac_build_intrinsic(&ctx->ac,
6861 "llvm.SI.buffer.load.dword.i32.i32",
6862 ctx->ac.i32, args, 9,
6863 AC_FUNC_ATTR_READONLY |
6864 AC_FUNC_ATTR_LEGACY);
6865
6866 LLVMBuildStore(ctx->builder,
6867 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6868 }
6869 idx += slot_inc;
6870 }
6871 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6872 }
6873
6874 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6875 struct nir_shader *geom_shader,
6876 struct ac_shader_binary *binary,
6877 struct ac_shader_config *config,
6878 struct ac_shader_variant_info *shader_info,
6879 const struct ac_nir_compiler_options *options,
6880 bool dump_shader)
6881 {
6882 struct nir_to_llvm_context ctx = {0};
6883 ctx.context = LLVMContextCreate();
6884 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6885 ctx.options = options;
6886 ctx.shader_info = shader_info;
6887
6888 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6889 ctx.ac.module = ctx.module;
6890
6891 ctx.is_gs_copy_shader = true;
6892 LLVMSetTarget(ctx.module, "amdgcn--");
6893
6894 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6895 ctx.ac.builder = ctx.builder;
6896 ctx.stage = MESA_SHADER_VERTEX;
6897
6898 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
6899
6900 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6901 ac_setup_rings(&ctx);
6902
6903 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6904 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6905
6906 struct ac_nir_context nir_ctx = {};
6907 nir_ctx.ac = ctx.ac;
6908 nir_ctx.abi = &ctx.abi;
6909
6910 nir_ctx.nctx = &ctx;
6911 ctx.nir = &nir_ctx;
6912
6913 nir_foreach_variable(variable, &geom_shader->outputs) {
6914 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
6915 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6916 }
6917
6918 ac_gs_copy_shader_emit(&ctx);
6919
6920 ctx.nir = NULL;
6921
6922 LLVMBuildRetVoid(ctx.builder);
6923
6924 ac_llvm_finalize_module(&ctx);
6925
6926 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6927 MESA_SHADER_VERTEX,
6928 dump_shader, options->supports_spill);
6929 }