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ac/nir_to_llvm: move some interp defines to the header
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
48
49 struct nir_to_llvm_context;
50
51 struct ac_nir_context {
52 struct ac_llvm_context ac;
53 struct ac_shader_abi *abi;
54
55 gl_shader_stage stage;
56
57 struct hash_table *defs;
58 struct hash_table *phis;
59 struct hash_table *vars;
60
61 LLVMValueRef main_function;
62 LLVMBasicBlockRef continue_block;
63 LLVMBasicBlockRef break_block;
64
65 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
66
67 int num_locals;
68 LLVMValueRef *locals;
69
70 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
71 };
72
73 struct nir_to_llvm_context {
74 struct ac_llvm_context ac;
75 const struct ac_nir_compiler_options *options;
76 struct ac_shader_variant_info *shader_info;
77 struct ac_shader_abi abi;
78 struct ac_nir_context *nir;
79
80 unsigned max_workgroup_size;
81 LLVMContextRef context;
82 LLVMModuleRef module;
83 LLVMBuilderRef builder;
84 LLVMValueRef main_function;
85
86 struct hash_table *defs;
87 struct hash_table *phis;
88
89 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
90 LLVMValueRef ring_offsets;
91 LLVMValueRef push_constants;
92 LLVMValueRef view_index;
93 LLVMValueRef num_work_groups;
94 LLVMValueRef workgroup_ids[3];
95 LLVMValueRef local_invocation_ids;
96 LLVMValueRef tg_size;
97
98 LLVMValueRef vertex_buffers;
99 LLVMValueRef rel_auto_id;
100 LLVMValueRef vs_prim_id;
101 LLVMValueRef ls_out_layout;
102 LLVMValueRef es2gs_offset;
103
104 LLVMValueRef tcs_offchip_layout;
105 LLVMValueRef tcs_out_offsets;
106 LLVMValueRef tcs_out_layout;
107 LLVMValueRef tcs_in_layout;
108 LLVMValueRef oc_lds;
109 LLVMValueRef merged_wave_info;
110 LLVMValueRef tess_factor_offset;
111 LLVMValueRef tes_rel_patch_id;
112 LLVMValueRef tes_u;
113 LLVMValueRef tes_v;
114
115 LLVMValueRef gsvs_ring_stride;
116 LLVMValueRef gsvs_num_entries;
117 LLVMValueRef gs2vs_offset;
118 LLVMValueRef gs_wave_id;
119 LLVMValueRef gs_vtx_offset[6];
120
121 LLVMValueRef esgs_ring;
122 LLVMValueRef gsvs_ring;
123 LLVMValueRef hs_ring_tess_offchip;
124 LLVMValueRef hs_ring_tess_factor;
125
126 LLVMValueRef prim_mask;
127 LLVMValueRef sample_pos_offset;
128 LLVMValueRef persp_sample, persp_center, persp_centroid;
129 LLVMValueRef linear_sample, linear_center, linear_centroid;
130
131 gl_shader_stage stage;
132
133 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
134
135 uint64_t input_mask;
136 uint64_t output_mask;
137 uint8_t num_output_clips;
138 uint8_t num_output_culls;
139
140 bool is_gs_copy_shader;
141 LLVMValueRef gs_next_vertex;
142 unsigned gs_max_out_vertices;
143
144 unsigned tes_primitive_mode;
145 uint64_t tess_outputs_written;
146 uint64_t tess_patch_outputs_written;
147
148 uint32_t tcs_patch_outputs_read;
149 uint64_t tcs_outputs_read;
150 };
151
152 static inline struct nir_to_llvm_context *
153 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
154 {
155 struct nir_to_llvm_context *ctx = NULL;
156 return container_of(abi, ctx, abi);
157 }
158
159 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
160 const nir_deref_var *deref,
161 enum ac_descriptor_type desc_type,
162 const nir_tex_instr *instr,
163 bool image, bool write);
164
165 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
166 {
167 return (index * 4) + chan;
168 }
169
170 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
171 {
172 /* handle patch indices separate */
173 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
174 return 0;
175 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
176 return 1;
177 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
178 return 2 + (slot - VARYING_SLOT_PATCH0);
179
180 if (slot == VARYING_SLOT_POS)
181 return 0;
182 if (slot == VARYING_SLOT_PSIZ)
183 return 1;
184 if (slot == VARYING_SLOT_CLIP_DIST0)
185 return 2;
186 /* 3 is reserved for clip dist as well */
187 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
188 return 4 + (slot - VARYING_SLOT_VAR0);
189 unreachable("illegal slot in get unique index\n");
190 }
191
192 static void set_llvm_calling_convention(LLVMValueRef func,
193 gl_shader_stage stage)
194 {
195 enum radeon_llvm_calling_convention calling_conv;
196
197 switch (stage) {
198 case MESA_SHADER_VERTEX:
199 case MESA_SHADER_TESS_EVAL:
200 calling_conv = RADEON_LLVM_AMDGPU_VS;
201 break;
202 case MESA_SHADER_GEOMETRY:
203 calling_conv = RADEON_LLVM_AMDGPU_GS;
204 break;
205 case MESA_SHADER_TESS_CTRL:
206 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
207 break;
208 case MESA_SHADER_FRAGMENT:
209 calling_conv = RADEON_LLVM_AMDGPU_PS;
210 break;
211 case MESA_SHADER_COMPUTE:
212 calling_conv = RADEON_LLVM_AMDGPU_CS;
213 break;
214 default:
215 unreachable("Unhandle shader type");
216 }
217
218 LLVMSetFunctionCallConv(func, calling_conv);
219 }
220
221 #define MAX_ARGS 23
222 struct arg_info {
223 LLVMTypeRef types[MAX_ARGS];
224 LLVMValueRef *assign[MAX_ARGS];
225 unsigned array_params_mask;
226 uint8_t count;
227 uint8_t sgpr_count;
228 uint8_t num_sgprs_used;
229 uint8_t num_vgprs_used;
230 };
231
232 enum ac_arg_regfile {
233 ARG_SGPR,
234 ARG_VGPR,
235 };
236
237 static void
238 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
239 LLVMValueRef *param_ptr)
240 {
241 assert(info->count < MAX_ARGS);
242
243 info->assign[info->count] = param_ptr;
244 info->types[info->count] = type;
245 info->count++;
246
247 if (regfile == ARG_SGPR) {
248 info->num_sgprs_used += ac_get_type_size(type) / 4;
249 info->sgpr_count++;
250 } else {
251 assert(regfile == ARG_VGPR);
252 info->num_vgprs_used += ac_get_type_size(type) / 4;
253 }
254 }
255
256 static inline void
257 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
258 {
259 info->array_params_mask |= (1 << info->count);
260 add_arg(info, ARG_SGPR, type, param_ptr);
261 }
262
263 static void assign_arguments(LLVMValueRef main_function,
264 struct arg_info *info)
265 {
266 unsigned i;
267 for (i = 0; i < info->count; i++) {
268 if (info->assign[i])
269 *info->assign[i] = LLVMGetParam(main_function, i);
270 }
271 }
272
273 static LLVMValueRef
274 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
275 LLVMBuilderRef builder, LLVMTypeRef *return_types,
276 unsigned num_return_elems,
277 struct arg_info *args,
278 unsigned max_workgroup_size,
279 bool unsafe_math)
280 {
281 LLVMTypeRef main_function_type, ret_type;
282 LLVMBasicBlockRef main_function_body;
283
284 if (num_return_elems)
285 ret_type = LLVMStructTypeInContext(ctx, return_types,
286 num_return_elems, true);
287 else
288 ret_type = LLVMVoidTypeInContext(ctx);
289
290 /* Setup the function */
291 main_function_type =
292 LLVMFunctionType(ret_type, args->types, args->count, 0);
293 LLVMValueRef main_function =
294 LLVMAddFunction(module, "main", main_function_type);
295 main_function_body =
296 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
297 LLVMPositionBuilderAtEnd(builder, main_function_body);
298
299 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
300 for (unsigned i = 0; i < args->sgpr_count; ++i) {
301 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
302
303 if (args->array_params_mask & (1 << i)) {
304 LLVMValueRef P = LLVMGetParam(main_function, i);
305 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
306 ac_add_attr_dereferenceable(P, UINT64_MAX);
307 }
308 }
309
310 if (max_workgroup_size) {
311 ac_llvm_add_target_dep_function_attr(main_function,
312 "amdgpu-max-work-group-size",
313 max_workgroup_size);
314 }
315 if (unsafe_math) {
316 /* These were copied from some LLVM test. */
317 LLVMAddTargetDependentFunctionAttr(main_function,
318 "less-precise-fpmad",
319 "true");
320 LLVMAddTargetDependentFunctionAttr(main_function,
321 "no-infs-fp-math",
322 "true");
323 LLVMAddTargetDependentFunctionAttr(main_function,
324 "no-nans-fp-math",
325 "true");
326 LLVMAddTargetDependentFunctionAttr(main_function,
327 "unsafe-fp-math",
328 "true");
329 LLVMAddTargetDependentFunctionAttr(main_function,
330 "no-signed-zeros-fp-math",
331 "true");
332 }
333 return main_function;
334 }
335
336 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
337 {
338 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
339 type = LLVMGetElementType(type);
340
341 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
342 return LLVMGetIntTypeWidth(type);
343
344 if (type == ctx->f16)
345 return 16;
346 if (type == ctx->f32)
347 return 32;
348 if (type == ctx->f64)
349 return 64;
350
351 unreachable("Unhandled type kind in get_elem_bits");
352 }
353
354 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
355 LLVMValueRef param, unsigned rshift,
356 unsigned bitwidth)
357 {
358 LLVMValueRef value = param;
359 if (rshift)
360 value = LLVMBuildLShr(ctx->builder, value,
361 LLVMConstInt(ctx->i32, rshift, false), "");
362
363 if (rshift + bitwidth < 32) {
364 unsigned mask = (1 << bitwidth) - 1;
365 value = LLVMBuildAnd(ctx->builder, value,
366 LLVMConstInt(ctx->i32, mask, false), "");
367 }
368 return value;
369 }
370
371 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
372 {
373 switch (ctx->stage) {
374 case MESA_SHADER_TESS_CTRL:
375 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
376 case MESA_SHADER_TESS_EVAL:
377 return ctx->tes_rel_patch_id;
378 break;
379 default:
380 unreachable("Illegal stage");
381 }
382 }
383
384 /* Tessellation shaders pass outputs to the next shader using LDS.
385 *
386 * LS outputs = TCS inputs
387 * TCS outputs = TES inputs
388 *
389 * The LDS layout is:
390 * - TCS inputs for patch 0
391 * - TCS inputs for patch 1
392 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
393 * - ...
394 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
395 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
396 * - TCS outputs for patch 1
397 * - Per-patch TCS outputs for patch 1
398 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
399 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
400 * - ...
401 *
402 * All three shaders VS(LS), TCS, TES share the same LDS space.
403 */
404 static LLVMValueRef
405 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
406 {
407 if (ctx->stage == MESA_SHADER_VERTEX)
408 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
409 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
410 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
411 else {
412 assert(0);
413 return NULL;
414 }
415 }
416
417 static LLVMValueRef
418 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
419 {
420 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
421 }
422
423 static LLVMValueRef
424 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
425 {
426 return LLVMBuildMul(ctx->builder,
427 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
428 LLVMConstInt(ctx->ac.i32, 4, false), "");
429 }
430
431 static LLVMValueRef
432 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
433 {
434 return LLVMBuildMul(ctx->builder,
435 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
436 LLVMConstInt(ctx->ac.i32, 4, false), "");
437 }
438
439 static LLVMValueRef
440 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
441 {
442 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
443 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
444
445 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
446 }
447
448 static LLVMValueRef
449 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
450 {
451 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
452 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
453 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
454
455 return LLVMBuildAdd(ctx->builder, patch0_offset,
456 LLVMBuildMul(ctx->builder, patch_stride,
457 rel_patch_id, ""),
458 "");
459 }
460
461 static LLVMValueRef
462 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
463 {
464 LLVMValueRef patch0_patch_data_offset =
465 get_tcs_out_patch0_patch_data_offset(ctx);
466 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
467 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
468
469 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
470 LLVMBuildMul(ctx->builder, patch_stride,
471 rel_patch_id, ""),
472 "");
473 }
474
475 static void
476 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
477 uint32_t indirect_offset)
478 {
479 ud_info->sgpr_idx = *sgpr_idx;
480 ud_info->num_sgprs = num_sgprs;
481 ud_info->indirect = indirect_offset > 0;
482 ud_info->indirect_offset = indirect_offset;
483 *sgpr_idx += num_sgprs;
484 }
485
486 static void
487 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
488 uint8_t num_sgprs)
489 {
490 struct ac_userdata_info *ud_info =
491 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
492 assert(ud_info);
493
494 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
495 }
496
497 static void
498 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
499 uint32_t indirect_offset)
500 {
501 struct ac_userdata_info *ud_info =
502 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
503 assert(ud_info);
504
505 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
506 }
507
508 struct user_sgpr_info {
509 bool need_ring_offsets;
510 uint8_t sgpr_count;
511 bool indirect_all_descriptor_sets;
512 };
513
514 static bool needs_view_index_sgpr(struct nir_to_llvm_context *ctx,
515 gl_shader_stage stage)
516 {
517 switch (stage) {
518 case MESA_SHADER_VERTEX:
519 if (ctx->shader_info->info.needs_multiview_view_index ||
520 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
521 return true;
522 break;
523 case MESA_SHADER_TESS_EVAL:
524 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
525 return true;
526 break;
527 case MESA_SHADER_GEOMETRY:
528 case MESA_SHADER_TESS_CTRL:
529 if (ctx->shader_info->info.needs_multiview_view_index)
530 return true;
531 break;
532 default:
533 break;
534 }
535 return false;
536 }
537
538 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
539 gl_shader_stage stage,
540 bool needs_view_index,
541 struct user_sgpr_info *user_sgpr_info)
542 {
543 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
544
545 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
546 if (stage == MESA_SHADER_GEOMETRY ||
547 stage == MESA_SHADER_VERTEX ||
548 stage == MESA_SHADER_TESS_CTRL ||
549 stage == MESA_SHADER_TESS_EVAL ||
550 ctx->is_gs_copy_shader)
551 user_sgpr_info->need_ring_offsets = true;
552
553 if (stage == MESA_SHADER_FRAGMENT &&
554 ctx->shader_info->info.ps.needs_sample_positions)
555 user_sgpr_info->need_ring_offsets = true;
556
557 /* 2 user sgprs will nearly always be allocated for scratch/rings */
558 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
559 user_sgpr_info->sgpr_count += 2;
560 }
561
562 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
563 switch (stage) {
564 case MESA_SHADER_COMPUTE:
565 if (ctx->shader_info->info.cs.uses_grid_size)
566 user_sgpr_info->sgpr_count += 3;
567 break;
568 case MESA_SHADER_FRAGMENT:
569 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
570 break;
571 case MESA_SHADER_VERTEX:
572 if (!ctx->is_gs_copy_shader) {
573 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
574 if (ctx->shader_info->info.vs.needs_draw_id) {
575 user_sgpr_info->sgpr_count += 3;
576 } else {
577 user_sgpr_info->sgpr_count += 2;
578 }
579 }
580 if (ctx->options->key.vs.as_ls)
581 user_sgpr_info->sgpr_count++;
582 break;
583 case MESA_SHADER_TESS_CTRL:
584 user_sgpr_info->sgpr_count += 4;
585 break;
586 case MESA_SHADER_TESS_EVAL:
587 user_sgpr_info->sgpr_count += 1;
588 break;
589 case MESA_SHADER_GEOMETRY:
590 user_sgpr_info->sgpr_count += 2;
591 break;
592 default:
593 break;
594 }
595
596 if (needs_view_index)
597 user_sgpr_info->sgpr_count++;
598
599 if (ctx->shader_info->info.loads_push_constants)
600 user_sgpr_info->sgpr_count += 2;
601
602 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
603 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
604
605 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
606 user_sgpr_info->sgpr_count += 2;
607 user_sgpr_info->indirect_all_descriptor_sets = true;
608 } else {
609 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
610 }
611 }
612
613 static void
614 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
615 gl_shader_stage stage,
616 bool has_previous_stage,
617 gl_shader_stage previous_stage,
618 const struct user_sgpr_info *user_sgpr_info,
619 struct arg_info *args,
620 LLVMValueRef *desc_sets)
621 {
622 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
623 unsigned num_sets = ctx->options->layout ?
624 ctx->options->layout->num_sets : 0;
625 unsigned stage_mask = 1 << stage;
626
627 if (has_previous_stage)
628 stage_mask |= 1 << previous_stage;
629
630 /* 1 for each descriptor set */
631 if (!user_sgpr_info->indirect_all_descriptor_sets) {
632 for (unsigned i = 0; i < num_sets; ++i) {
633 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
634 add_array_arg(args, type,
635 &ctx->descriptor_sets[i]);
636 }
637 }
638 } else {
639 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
640 }
641
642 if (ctx->shader_info->info.loads_push_constants) {
643 /* 1 for push constants and dynamic descriptors */
644 add_array_arg(args, type, &ctx->push_constants);
645 }
646 }
647
648 static void
649 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
650 gl_shader_stage stage,
651 bool has_previous_stage,
652 gl_shader_stage previous_stage,
653 struct arg_info *args)
654 {
655 if (!ctx->is_gs_copy_shader &&
656 (stage == MESA_SHADER_VERTEX ||
657 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
658 if (ctx->shader_info->info.vs.has_vertex_buffers) {
659 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
660 &ctx->vertex_buffers);
661 }
662 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
663 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
664 if (ctx->shader_info->info.vs.needs_draw_id) {
665 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
666 }
667 }
668 }
669
670 static void
671 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
672 {
673 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
674 if (!ctx->is_gs_copy_shader) {
675 if (ctx->options->key.vs.as_ls) {
676 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
677 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
678 } else {
679 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
680 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
681 }
682 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
683 }
684 }
685
686 static void
687 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
688 {
689 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
690 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
691 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
692 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
693 }
694
695 static void
696 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
697 bool has_previous_stage, gl_shader_stage previous_stage,
698 const struct user_sgpr_info *user_sgpr_info,
699 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
700 {
701 unsigned num_sets = ctx->options->layout ?
702 ctx->options->layout->num_sets : 0;
703 unsigned stage_mask = 1 << stage;
704
705 if (has_previous_stage)
706 stage_mask |= 1 << previous_stage;
707
708 if (!user_sgpr_info->indirect_all_descriptor_sets) {
709 for (unsigned i = 0; i < num_sets; ++i) {
710 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
711 set_loc_desc(ctx, i, user_sgpr_idx, 0);
712 } else
713 ctx->descriptor_sets[i] = NULL;
714 }
715 } else {
716 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
717 user_sgpr_idx, 2);
718
719 for (unsigned i = 0; i < num_sets; ++i) {
720 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
721 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
722 ctx->descriptor_sets[i] =
723 ac_build_load_to_sgpr(&ctx->ac,
724 desc_sets,
725 LLVMConstInt(ctx->ac.i32, i, false));
726
727 } else
728 ctx->descriptor_sets[i] = NULL;
729 }
730 ctx->shader_info->need_indirect_descriptor_sets = true;
731 }
732
733 if (ctx->shader_info->info.loads_push_constants) {
734 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
735 }
736 }
737
738 static void
739 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
740 gl_shader_stage stage, bool has_previous_stage,
741 gl_shader_stage previous_stage,
742 uint8_t *user_sgpr_idx)
743 {
744 if (!ctx->is_gs_copy_shader &&
745 (stage == MESA_SHADER_VERTEX ||
746 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
747 if (ctx->shader_info->info.vs.has_vertex_buffers) {
748 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
749 user_sgpr_idx, 2);
750 }
751
752 unsigned vs_num = 2;
753 if (ctx->shader_info->info.vs.needs_draw_id)
754 vs_num++;
755
756 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
757 user_sgpr_idx, vs_num);
758 }
759 }
760
761 static void create_function(struct nir_to_llvm_context *ctx,
762 gl_shader_stage stage,
763 bool has_previous_stage,
764 gl_shader_stage previous_stage)
765 {
766 uint8_t user_sgpr_idx;
767 struct user_sgpr_info user_sgpr_info;
768 struct arg_info args = {};
769 LLVMValueRef desc_sets;
770 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
771 allocate_user_sgprs(ctx, stage, needs_view_index, &user_sgpr_info);
772
773 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
774 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
775 &ctx->ring_offsets);
776 }
777
778 switch (stage) {
779 case MESA_SHADER_COMPUTE:
780 declare_global_input_sgprs(ctx, stage, has_previous_stage,
781 previous_stage, &user_sgpr_info,
782 &args, &desc_sets);
783
784 if (ctx->shader_info->info.cs.uses_grid_size) {
785 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
786 &ctx->num_work_groups);
787 }
788
789 for (int i = 0; i < 3; i++) {
790 ctx->workgroup_ids[i] = NULL;
791 if (ctx->shader_info->info.cs.uses_block_id[i]) {
792 add_arg(&args, ARG_SGPR, ctx->ac.i32,
793 &ctx->workgroup_ids[i]);
794 }
795 }
796
797 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
798 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
799 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
800 &ctx->local_invocation_ids);
801 break;
802 case MESA_SHADER_VERTEX:
803 declare_global_input_sgprs(ctx, stage, has_previous_stage,
804 previous_stage, &user_sgpr_info,
805 &args, &desc_sets);
806 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
807 previous_stage, &args);
808
809 if (needs_view_index)
810 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
811 if (ctx->options->key.vs.as_es)
812 add_arg(&args, ARG_SGPR, ctx->ac.i32,
813 &ctx->es2gs_offset);
814 else if (ctx->options->key.vs.as_ls)
815 add_arg(&args, ARG_SGPR, ctx->ac.i32,
816 &ctx->ls_out_layout);
817
818 declare_vs_input_vgprs(ctx, &args);
819 break;
820 case MESA_SHADER_TESS_CTRL:
821 if (has_previous_stage) {
822 // First 6 system regs
823 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
824 add_arg(&args, ARG_SGPR, ctx->ac.i32,
825 &ctx->merged_wave_info);
826 add_arg(&args, ARG_SGPR, ctx->ac.i32,
827 &ctx->tess_factor_offset);
828
829 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
830 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
831 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
832
833 declare_global_input_sgprs(ctx, stage,
834 has_previous_stage,
835 previous_stage,
836 &user_sgpr_info, &args,
837 &desc_sets);
838 declare_vs_specific_input_sgprs(ctx, stage,
839 has_previous_stage,
840 previous_stage, &args);
841
842 add_arg(&args, ARG_SGPR, ctx->ac.i32,
843 &ctx->ls_out_layout);
844
845 add_arg(&args, ARG_SGPR, ctx->ac.i32,
846 &ctx->tcs_offchip_layout);
847 add_arg(&args, ARG_SGPR, ctx->ac.i32,
848 &ctx->tcs_out_offsets);
849 add_arg(&args, ARG_SGPR, ctx->ac.i32,
850 &ctx->tcs_out_layout);
851 add_arg(&args, ARG_SGPR, ctx->ac.i32,
852 &ctx->tcs_in_layout);
853 if (needs_view_index)
854 add_arg(&args, ARG_SGPR, ctx->ac.i32,
855 &ctx->view_index);
856
857 add_arg(&args, ARG_VGPR, ctx->ac.i32,
858 &ctx->abi.tcs_patch_id);
859 add_arg(&args, ARG_VGPR, ctx->ac.i32,
860 &ctx->abi.tcs_rel_ids);
861
862 declare_vs_input_vgprs(ctx, &args);
863 } else {
864 declare_global_input_sgprs(ctx, stage,
865 has_previous_stage,
866 previous_stage,
867 &user_sgpr_info, &args,
868 &desc_sets);
869
870 add_arg(&args, ARG_SGPR, ctx->ac.i32,
871 &ctx->tcs_offchip_layout);
872 add_arg(&args, ARG_SGPR, ctx->ac.i32,
873 &ctx->tcs_out_offsets);
874 add_arg(&args, ARG_SGPR, ctx->ac.i32,
875 &ctx->tcs_out_layout);
876 add_arg(&args, ARG_SGPR, ctx->ac.i32,
877 &ctx->tcs_in_layout);
878 if (needs_view_index)
879 add_arg(&args, ARG_SGPR, ctx->ac.i32,
880 &ctx->view_index);
881
882 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
883 add_arg(&args, ARG_SGPR, ctx->ac.i32,
884 &ctx->tess_factor_offset);
885 add_arg(&args, ARG_VGPR, ctx->ac.i32,
886 &ctx->abi.tcs_patch_id);
887 add_arg(&args, ARG_VGPR, ctx->ac.i32,
888 &ctx->abi.tcs_rel_ids);
889 }
890 break;
891 case MESA_SHADER_TESS_EVAL:
892 declare_global_input_sgprs(ctx, stage, has_previous_stage,
893 previous_stage, &user_sgpr_info,
894 &args, &desc_sets);
895
896 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
897 if (needs_view_index)
898 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
899
900 if (ctx->options->key.tes.as_es) {
901 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
902 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
903 add_arg(&args, ARG_SGPR, ctx->ac.i32,
904 &ctx->es2gs_offset);
905 } else {
906 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
907 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
908 }
909 declare_tes_input_vgprs(ctx, &args);
910 break;
911 case MESA_SHADER_GEOMETRY:
912 if (has_previous_stage) {
913 // First 6 system regs
914 add_arg(&args, ARG_SGPR, ctx->ac.i32,
915 &ctx->gs2vs_offset);
916 add_arg(&args, ARG_SGPR, ctx->ac.i32,
917 &ctx->merged_wave_info);
918 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
919
920 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
921 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
922 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
923
924 declare_global_input_sgprs(ctx, stage,
925 has_previous_stage,
926 previous_stage,
927 &user_sgpr_info, &args,
928 &desc_sets);
929
930 if (previous_stage == MESA_SHADER_TESS_EVAL) {
931 add_arg(&args, ARG_SGPR, ctx->ac.i32,
932 &ctx->tcs_offchip_layout);
933 } else {
934 declare_vs_specific_input_sgprs(ctx, stage,
935 has_previous_stage,
936 previous_stage,
937 &args);
938 }
939
940 add_arg(&args, ARG_SGPR, ctx->ac.i32,
941 &ctx->gsvs_ring_stride);
942 add_arg(&args, ARG_SGPR, ctx->ac.i32,
943 &ctx->gsvs_num_entries);
944 if (needs_view_index)
945 add_arg(&args, ARG_SGPR, ctx->ac.i32,
946 &ctx->view_index);
947
948 add_arg(&args, ARG_VGPR, ctx->ac.i32,
949 &ctx->gs_vtx_offset[0]);
950 add_arg(&args, ARG_VGPR, ctx->ac.i32,
951 &ctx->gs_vtx_offset[2]);
952 add_arg(&args, ARG_VGPR, ctx->ac.i32,
953 &ctx->abi.gs_prim_id);
954 add_arg(&args, ARG_VGPR, ctx->ac.i32,
955 &ctx->abi.gs_invocation_id);
956 add_arg(&args, ARG_VGPR, ctx->ac.i32,
957 &ctx->gs_vtx_offset[4]);
958
959 if (previous_stage == MESA_SHADER_VERTEX) {
960 declare_vs_input_vgprs(ctx, &args);
961 } else {
962 declare_tes_input_vgprs(ctx, &args);
963 }
964 } else {
965 declare_global_input_sgprs(ctx, stage,
966 has_previous_stage,
967 previous_stage,
968 &user_sgpr_info, &args,
969 &desc_sets);
970
971 add_arg(&args, ARG_SGPR, ctx->ac.i32,
972 &ctx->gsvs_ring_stride);
973 add_arg(&args, ARG_SGPR, ctx->ac.i32,
974 &ctx->gsvs_num_entries);
975 if (needs_view_index)
976 add_arg(&args, ARG_SGPR, ctx->ac.i32,
977 &ctx->view_index);
978
979 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
980 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
981 add_arg(&args, ARG_VGPR, ctx->ac.i32,
982 &ctx->gs_vtx_offset[0]);
983 add_arg(&args, ARG_VGPR, ctx->ac.i32,
984 &ctx->gs_vtx_offset[1]);
985 add_arg(&args, ARG_VGPR, ctx->ac.i32,
986 &ctx->abi.gs_prim_id);
987 add_arg(&args, ARG_VGPR, ctx->ac.i32,
988 &ctx->gs_vtx_offset[2]);
989 add_arg(&args, ARG_VGPR, ctx->ac.i32,
990 &ctx->gs_vtx_offset[3]);
991 add_arg(&args, ARG_VGPR, ctx->ac.i32,
992 &ctx->gs_vtx_offset[4]);
993 add_arg(&args, ARG_VGPR, ctx->ac.i32,
994 &ctx->gs_vtx_offset[5]);
995 add_arg(&args, ARG_VGPR, ctx->ac.i32,
996 &ctx->abi.gs_invocation_id);
997 }
998 break;
999 case MESA_SHADER_FRAGMENT:
1000 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1001 previous_stage, &user_sgpr_info,
1002 &args, &desc_sets);
1003
1004 if (ctx->shader_info->info.ps.needs_sample_positions)
1005 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1006 &ctx->sample_pos_offset);
1007
1008 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1009 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1010 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1011 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1012 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1013 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1014 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1015 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1016 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1017 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1018 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1019 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1020 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1021 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1022 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1023 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1024 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1025 break;
1026 default:
1027 unreachable("Shader stage not implemented");
1028 }
1029
1030 ctx->main_function = create_llvm_function(
1031 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1032 ctx->max_workgroup_size,
1033 ctx->options->unsafe_math);
1034 set_llvm_calling_convention(ctx->main_function, stage);
1035
1036
1037 ctx->shader_info->num_input_vgprs = 0;
1038 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1039
1040 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1041
1042 if (ctx->stage != MESA_SHADER_FRAGMENT)
1043 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1044
1045 assign_arguments(ctx->main_function, &args);
1046
1047 user_sgpr_idx = 0;
1048
1049 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1050 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1051 &user_sgpr_idx, 2);
1052 if (ctx->options->supports_spill) {
1053 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1054 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1055 NULL, 0, AC_FUNC_ATTR_READNONE);
1056 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1057 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1058 }
1059 }
1060
1061 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1062 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1063 if (has_previous_stage)
1064 user_sgpr_idx = 0;
1065
1066 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1067 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1068
1069 switch (stage) {
1070 case MESA_SHADER_COMPUTE:
1071 if (ctx->shader_info->info.cs.uses_grid_size) {
1072 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1073 &user_sgpr_idx, 3);
1074 }
1075 break;
1076 case MESA_SHADER_VERTEX:
1077 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1078 previous_stage, &user_sgpr_idx);
1079 if (ctx->view_index)
1080 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1081 if (ctx->options->key.vs.as_ls) {
1082 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1083 &user_sgpr_idx, 1);
1084 }
1085 if (ctx->options->key.vs.as_ls)
1086 ac_declare_lds_as_pointer(&ctx->ac);
1087 break;
1088 case MESA_SHADER_TESS_CTRL:
1089 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1090 previous_stage, &user_sgpr_idx);
1091 if (has_previous_stage)
1092 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1093 &user_sgpr_idx, 1);
1094 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1095 if (ctx->view_index)
1096 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1097 ac_declare_lds_as_pointer(&ctx->ac);
1098 break;
1099 case MESA_SHADER_TESS_EVAL:
1100 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1101 if (ctx->view_index)
1102 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1103 break;
1104 case MESA_SHADER_GEOMETRY:
1105 if (has_previous_stage) {
1106 if (previous_stage == MESA_SHADER_VERTEX)
1107 set_vs_specific_input_locs(ctx, stage,
1108 has_previous_stage,
1109 previous_stage,
1110 &user_sgpr_idx);
1111 else
1112 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1113 &user_sgpr_idx, 1);
1114 }
1115 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1116 &user_sgpr_idx, 2);
1117 if (ctx->view_index)
1118 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1119 if (has_previous_stage)
1120 ac_declare_lds_as_pointer(&ctx->ac);
1121 break;
1122 case MESA_SHADER_FRAGMENT:
1123 if (ctx->shader_info->info.ps.needs_sample_positions) {
1124 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1125 &user_sgpr_idx, 1);
1126 }
1127 break;
1128 default:
1129 unreachable("Shader stage not implemented");
1130 }
1131
1132 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1133 }
1134
1135 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1136 LLVMValueRef value, unsigned count)
1137 {
1138 unsigned num_components = ac_get_llvm_num_components(value);
1139 if (count == num_components)
1140 return value;
1141
1142 LLVMValueRef masks[] = {
1143 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1144 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1145
1146 if (count == 1)
1147 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1148 "");
1149
1150 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1151 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1152 }
1153
1154 static void
1155 build_store_values_extended(struct ac_llvm_context *ac,
1156 LLVMValueRef *values,
1157 unsigned value_count,
1158 unsigned value_stride,
1159 LLVMValueRef vec)
1160 {
1161 LLVMBuilderRef builder = ac->builder;
1162 unsigned i;
1163
1164 for (i = 0; i < value_count; i++) {
1165 LLVMValueRef ptr = values[i * value_stride];
1166 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1167 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1168 LLVMBuildStore(builder, value, ptr);
1169 }
1170 }
1171
1172 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1173 const nir_ssa_def *def)
1174 {
1175 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1176 if (def->num_components > 1) {
1177 type = LLVMVectorType(type, def->num_components);
1178 }
1179 return type;
1180 }
1181
1182 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1183 {
1184 assert(src.is_ssa);
1185 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1186 return (LLVMValueRef)entry->data;
1187 }
1188
1189
1190 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1191 const struct nir_block *b)
1192 {
1193 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1194 return (LLVMBasicBlockRef)entry->data;
1195 }
1196
1197 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1198 nir_alu_src src,
1199 unsigned num_components)
1200 {
1201 LLVMValueRef value = get_src(ctx, src.src);
1202 bool need_swizzle = false;
1203
1204 assert(value);
1205 LLVMTypeRef type = LLVMTypeOf(value);
1206 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1207 ? LLVMGetVectorSize(type)
1208 : 1;
1209
1210 for (unsigned i = 0; i < num_components; ++i) {
1211 assert(src.swizzle[i] < src_components);
1212 if (src.swizzle[i] != i)
1213 need_swizzle = true;
1214 }
1215
1216 if (need_swizzle || num_components != src_components) {
1217 LLVMValueRef masks[] = {
1218 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1219 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1220 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1221 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1222
1223 if (src_components > 1 && num_components == 1) {
1224 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1225 masks[0], "");
1226 } else if (src_components == 1 && num_components > 1) {
1227 LLVMValueRef values[] = {value, value, value, value};
1228 value = ac_build_gather_values(&ctx->ac, values, num_components);
1229 } else {
1230 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1231 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1232 swizzle, "");
1233 }
1234 }
1235 assert(!src.negate);
1236 assert(!src.abs);
1237 return value;
1238 }
1239
1240 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1241 LLVMIntPredicate pred, LLVMValueRef src0,
1242 LLVMValueRef src1)
1243 {
1244 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1245 return LLVMBuildSelect(ctx->builder, result,
1246 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1247 ctx->i32_0, "");
1248 }
1249
1250 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1251 LLVMRealPredicate pred, LLVMValueRef src0,
1252 LLVMValueRef src1)
1253 {
1254 LLVMValueRef result;
1255 src0 = ac_to_float(ctx, src0);
1256 src1 = ac_to_float(ctx, src1);
1257 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1258 return LLVMBuildSelect(ctx->builder, result,
1259 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1260 ctx->i32_0, "");
1261 }
1262
1263 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1264 const char *intrin,
1265 LLVMTypeRef result_type,
1266 LLVMValueRef src0)
1267 {
1268 char name[64];
1269 LLVMValueRef params[] = {
1270 ac_to_float(ctx, src0),
1271 };
1272
1273 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1274 get_elem_bits(ctx, result_type));
1275 assert(length < sizeof(name));
1276 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1277 }
1278
1279 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1280 const char *intrin,
1281 LLVMTypeRef result_type,
1282 LLVMValueRef src0, LLVMValueRef src1)
1283 {
1284 char name[64];
1285 LLVMValueRef params[] = {
1286 ac_to_float(ctx, src0),
1287 ac_to_float(ctx, src1),
1288 };
1289
1290 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1291 get_elem_bits(ctx, result_type));
1292 assert(length < sizeof(name));
1293 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1294 }
1295
1296 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1297 const char *intrin,
1298 LLVMTypeRef result_type,
1299 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1300 {
1301 char name[64];
1302 LLVMValueRef params[] = {
1303 ac_to_float(ctx, src0),
1304 ac_to_float(ctx, src1),
1305 ac_to_float(ctx, src2),
1306 };
1307
1308 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1309 get_elem_bits(ctx, result_type));
1310 assert(length < sizeof(name));
1311 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1312 }
1313
1314 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1315 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1316 {
1317 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1318 ctx->i32_0, "");
1319 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1320 }
1321
1322 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1323 LLVMIntPredicate pred,
1324 LLVMValueRef src0, LLVMValueRef src1)
1325 {
1326 return LLVMBuildSelect(ctx->builder,
1327 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1328 src0,
1329 src1, "");
1330
1331 }
1332 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1333 LLVMValueRef src0)
1334 {
1335 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1336 LLVMBuildNeg(ctx->builder, src0, ""));
1337 }
1338
1339 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1340 LLVMValueRef src0,
1341 unsigned bitsize)
1342 {
1343 LLVMValueRef cmp, val, zero, one;
1344 LLVMTypeRef type;
1345
1346 if (bitsize == 32) {
1347 type = ctx->f32;
1348 zero = ctx->f32_0;
1349 one = ctx->f32_1;
1350 } else {
1351 type = ctx->f64;
1352 zero = ctx->f64_0;
1353 one = ctx->f64_1;
1354 }
1355
1356 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1357 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1358 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1359 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1360 return val;
1361 }
1362
1363 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1364 LLVMValueRef src0, unsigned bitsize)
1365 {
1366 LLVMValueRef cmp, val, zero, one;
1367 LLVMTypeRef type;
1368
1369 if (bitsize == 32) {
1370 type = ctx->i32;
1371 zero = ctx->i32_0;
1372 one = ctx->i32_1;
1373 } else {
1374 type = ctx->i64;
1375 zero = ctx->i64_0;
1376 one = ctx->i64_1;
1377 }
1378
1379 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1380 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1381 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1382 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1383 return val;
1384 }
1385
1386 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1387 LLVMValueRef src0)
1388 {
1389 const char *intr = "llvm.floor.f32";
1390 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1391 LLVMValueRef params[] = {
1392 fsrc0,
1393 };
1394 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1395 ctx->f32, params, 1,
1396 AC_FUNC_ATTR_READNONE);
1397 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1398 }
1399
1400 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1401 const char *intrin,
1402 LLVMValueRef src0, LLVMValueRef src1)
1403 {
1404 LLVMTypeRef ret_type;
1405 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1406 LLVMValueRef res;
1407 LLVMValueRef params[] = { src0, src1 };
1408 ret_type = LLVMStructTypeInContext(ctx->context, types,
1409 2, true);
1410
1411 res = ac_build_intrinsic(ctx, intrin, ret_type,
1412 params, 2, AC_FUNC_ATTR_READNONE);
1413
1414 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1415 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1416 return res;
1417 }
1418
1419 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1420 LLVMValueRef src0)
1421 {
1422 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1423 }
1424
1425 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1426 LLVMValueRef src0)
1427 {
1428 src0 = ac_to_float(ctx, src0);
1429 return LLVMBuildSExt(ctx->builder,
1430 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1431 ctx->i32, "");
1432 }
1433
1434 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1435 LLVMValueRef src0,
1436 unsigned bitsize)
1437 {
1438 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1439
1440 if (bitsize == 32)
1441 return result;
1442
1443 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1444 }
1445
1446 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1447 LLVMValueRef src0)
1448 {
1449 return LLVMBuildSExt(ctx->builder,
1450 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1451 ctx->i32, "");
1452 }
1453
1454 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1455 LLVMValueRef src0)
1456 {
1457 LLVMValueRef result;
1458 LLVMValueRef cond = NULL;
1459
1460 src0 = ac_to_float(&ctx->ac, src0);
1461 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1462
1463 if (ctx->options->chip_class >= VI) {
1464 LLVMValueRef args[2];
1465 /* Check if the result is a denormal - and flush to 0 if so. */
1466 args[0] = result;
1467 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1468 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1469 }
1470
1471 /* need to convert back up to f32 */
1472 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1473
1474 if (ctx->options->chip_class >= VI)
1475 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1476 else {
1477 /* for SI/CIK */
1478 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1479 * so compare the result and flush to 0 if it's smaller.
1480 */
1481 LLVMValueRef temp, cond2;
1482 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1483 ctx->ac.f32, result);
1484 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1485 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1486 temp, "");
1487 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1488 temp, ctx->ac.f32_0, "");
1489 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1490 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1491 }
1492 return result;
1493 }
1494
1495 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1496 LLVMValueRef src0, LLVMValueRef src1)
1497 {
1498 LLVMValueRef dst64, result;
1499 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1500 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1501
1502 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1503 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1504 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1505 return result;
1506 }
1507
1508 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1509 LLVMValueRef src0, LLVMValueRef src1)
1510 {
1511 LLVMValueRef dst64, result;
1512 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1513 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1514
1515 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1516 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1517 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1518 return result;
1519 }
1520
1521 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1522 bool is_signed,
1523 const LLVMValueRef srcs[3])
1524 {
1525 LLVMValueRef result;
1526 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1527
1528 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1529 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1530 return result;
1531 }
1532
1533 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1534 LLVMValueRef src0, LLVMValueRef src1,
1535 LLVMValueRef src2, LLVMValueRef src3)
1536 {
1537 LLVMValueRef bfi_args[3], result;
1538
1539 bfi_args[0] = LLVMBuildShl(ctx->builder,
1540 LLVMBuildSub(ctx->builder,
1541 LLVMBuildShl(ctx->builder,
1542 ctx->i32_1,
1543 src3, ""),
1544 ctx->i32_1, ""),
1545 src2, "");
1546 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1547 bfi_args[2] = src0;
1548
1549 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1550
1551 /* Calculate:
1552 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1553 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1554 */
1555 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1556 LLVMBuildAnd(ctx->builder, bfi_args[0],
1557 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1558
1559 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1560 return result;
1561 }
1562
1563 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1564 LLVMValueRef src0)
1565 {
1566 LLVMValueRef comp[2];
1567
1568 src0 = ac_to_float(ctx, src0);
1569 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1570 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1571
1572 return ac_build_cvt_pkrtz_f16(ctx, comp);
1573 }
1574
1575 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1576 LLVMValueRef src0)
1577 {
1578 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1579 LLVMValueRef temps[2], result, val;
1580 int i;
1581
1582 for (i = 0; i < 2; i++) {
1583 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1584 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1585 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1586 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1587 }
1588
1589 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1590 ctx->i32_0, "");
1591 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1592 ctx->i32_1, "");
1593 return result;
1594 }
1595
1596 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1597 nir_op op,
1598 LLVMValueRef src0)
1599 {
1600 unsigned mask;
1601 int idx;
1602 LLVMValueRef result;
1603
1604 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1605 mask = AC_TID_MASK_LEFT;
1606 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1607 mask = AC_TID_MASK_TOP;
1608 else
1609 mask = AC_TID_MASK_TOP_LEFT;
1610
1611 /* for DDX we want to next X pixel, DDY next Y pixel. */
1612 if (op == nir_op_fddx_fine ||
1613 op == nir_op_fddx_coarse ||
1614 op == nir_op_fddx)
1615 idx = 1;
1616 else
1617 idx = 2;
1618
1619 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1620 return result;
1621 }
1622
1623 /*
1624 * this takes an I,J coordinate pair,
1625 * and works out the X and Y derivatives.
1626 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1627 */
1628 static LLVMValueRef emit_ddxy_interp(
1629 struct ac_nir_context *ctx,
1630 LLVMValueRef interp_ij)
1631 {
1632 LLVMValueRef result[4], a;
1633 unsigned i;
1634
1635 for (i = 0; i < 2; i++) {
1636 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1637 LLVMConstInt(ctx->ac.i32, i, false), "");
1638 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1639 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1640 }
1641 return ac_build_gather_values(&ctx->ac, result, 4);
1642 }
1643
1644 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1645 {
1646 LLVMValueRef src[4], result = NULL;
1647 unsigned num_components = instr->dest.dest.ssa.num_components;
1648 unsigned src_components;
1649 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1650
1651 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1652 switch (instr->op) {
1653 case nir_op_vec2:
1654 case nir_op_vec3:
1655 case nir_op_vec4:
1656 src_components = 1;
1657 break;
1658 case nir_op_pack_half_2x16:
1659 src_components = 2;
1660 break;
1661 case nir_op_unpack_half_2x16:
1662 src_components = 1;
1663 break;
1664 default:
1665 src_components = num_components;
1666 break;
1667 }
1668 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1669 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1670
1671 switch (instr->op) {
1672 case nir_op_fmov:
1673 case nir_op_imov:
1674 result = src[0];
1675 break;
1676 case nir_op_fneg:
1677 src[0] = ac_to_float(&ctx->ac, src[0]);
1678 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1679 break;
1680 case nir_op_ineg:
1681 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1682 break;
1683 case nir_op_inot:
1684 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1685 break;
1686 case nir_op_iadd:
1687 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1688 break;
1689 case nir_op_fadd:
1690 src[0] = ac_to_float(&ctx->ac, src[0]);
1691 src[1] = ac_to_float(&ctx->ac, src[1]);
1692 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1693 break;
1694 case nir_op_fsub:
1695 src[0] = ac_to_float(&ctx->ac, src[0]);
1696 src[1] = ac_to_float(&ctx->ac, src[1]);
1697 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1698 break;
1699 case nir_op_isub:
1700 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1701 break;
1702 case nir_op_imul:
1703 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1704 break;
1705 case nir_op_imod:
1706 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1707 break;
1708 case nir_op_umod:
1709 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1710 break;
1711 case nir_op_fmod:
1712 src[0] = ac_to_float(&ctx->ac, src[0]);
1713 src[1] = ac_to_float(&ctx->ac, src[1]);
1714 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1715 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1716 ac_to_float_type(&ctx->ac, def_type), result);
1717 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1718 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1719 break;
1720 case nir_op_frem:
1721 src[0] = ac_to_float(&ctx->ac, src[0]);
1722 src[1] = ac_to_float(&ctx->ac, src[1]);
1723 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1724 break;
1725 case nir_op_irem:
1726 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1727 break;
1728 case nir_op_idiv:
1729 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1730 break;
1731 case nir_op_udiv:
1732 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1733 break;
1734 case nir_op_fmul:
1735 src[0] = ac_to_float(&ctx->ac, src[0]);
1736 src[1] = ac_to_float(&ctx->ac, src[1]);
1737 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1738 break;
1739 case nir_op_fdiv:
1740 src[0] = ac_to_float(&ctx->ac, src[0]);
1741 src[1] = ac_to_float(&ctx->ac, src[1]);
1742 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1743 break;
1744 case nir_op_frcp:
1745 src[0] = ac_to_float(&ctx->ac, src[0]);
1746 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1747 src[0]);
1748 break;
1749 case nir_op_iand:
1750 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1751 break;
1752 case nir_op_ior:
1753 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1754 break;
1755 case nir_op_ixor:
1756 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1757 break;
1758 case nir_op_ishl:
1759 result = LLVMBuildShl(ctx->ac.builder, src[0],
1760 LLVMBuildZExt(ctx->ac.builder, src[1],
1761 LLVMTypeOf(src[0]), ""),
1762 "");
1763 break;
1764 case nir_op_ishr:
1765 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1766 LLVMBuildZExt(ctx->ac.builder, src[1],
1767 LLVMTypeOf(src[0]), ""),
1768 "");
1769 break;
1770 case nir_op_ushr:
1771 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1772 LLVMBuildZExt(ctx->ac.builder, src[1],
1773 LLVMTypeOf(src[0]), ""),
1774 "");
1775 break;
1776 case nir_op_ilt:
1777 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1778 break;
1779 case nir_op_ine:
1780 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1781 break;
1782 case nir_op_ieq:
1783 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1784 break;
1785 case nir_op_ige:
1786 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1787 break;
1788 case nir_op_ult:
1789 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1790 break;
1791 case nir_op_uge:
1792 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1793 break;
1794 case nir_op_feq:
1795 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1796 break;
1797 case nir_op_fne:
1798 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1799 break;
1800 case nir_op_flt:
1801 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1802 break;
1803 case nir_op_fge:
1804 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1805 break;
1806 case nir_op_fabs:
1807 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1808 ac_to_float_type(&ctx->ac, def_type), src[0]);
1809 break;
1810 case nir_op_iabs:
1811 result = emit_iabs(&ctx->ac, src[0]);
1812 break;
1813 case nir_op_imax:
1814 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1815 break;
1816 case nir_op_imin:
1817 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1818 break;
1819 case nir_op_umax:
1820 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1821 break;
1822 case nir_op_umin:
1823 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1824 break;
1825 case nir_op_isign:
1826 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1827 break;
1828 case nir_op_fsign:
1829 src[0] = ac_to_float(&ctx->ac, src[0]);
1830 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1831 break;
1832 case nir_op_ffloor:
1833 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1834 ac_to_float_type(&ctx->ac, def_type), src[0]);
1835 break;
1836 case nir_op_ftrunc:
1837 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1838 ac_to_float_type(&ctx->ac, def_type), src[0]);
1839 break;
1840 case nir_op_fceil:
1841 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1842 ac_to_float_type(&ctx->ac, def_type), src[0]);
1843 break;
1844 case nir_op_fround_even:
1845 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1846 ac_to_float_type(&ctx->ac, def_type),src[0]);
1847 break;
1848 case nir_op_ffract:
1849 result = emit_ffract(&ctx->ac, src[0]);
1850 break;
1851 case nir_op_fsin:
1852 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1853 ac_to_float_type(&ctx->ac, def_type), src[0]);
1854 break;
1855 case nir_op_fcos:
1856 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1857 ac_to_float_type(&ctx->ac, def_type), src[0]);
1858 break;
1859 case nir_op_fsqrt:
1860 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1861 ac_to_float_type(&ctx->ac, def_type), src[0]);
1862 break;
1863 case nir_op_fexp2:
1864 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1865 ac_to_float_type(&ctx->ac, def_type), src[0]);
1866 break;
1867 case nir_op_flog2:
1868 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1869 ac_to_float_type(&ctx->ac, def_type), src[0]);
1870 break;
1871 case nir_op_frsq:
1872 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1873 ac_to_float_type(&ctx->ac, def_type), src[0]);
1874 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1875 result);
1876 break;
1877 case nir_op_fpow:
1878 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1879 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1880 break;
1881 case nir_op_fmax:
1882 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1883 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1884 if (ctx->ac.chip_class < GFX9 &&
1885 instr->dest.dest.ssa.bit_size == 32) {
1886 /* Only pre-GFX9 chips do not flush denorms. */
1887 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1888 ac_to_float_type(&ctx->ac, def_type),
1889 result);
1890 }
1891 break;
1892 case nir_op_fmin:
1893 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1894 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1895 if (ctx->ac.chip_class < GFX9 &&
1896 instr->dest.dest.ssa.bit_size == 32) {
1897 /* Only pre-GFX9 chips do not flush denorms. */
1898 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1899 ac_to_float_type(&ctx->ac, def_type),
1900 result);
1901 }
1902 break;
1903 case nir_op_ffma:
1904 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1905 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1906 break;
1907 case nir_op_ibitfield_extract:
1908 result = emit_bitfield_extract(&ctx->ac, true, src);
1909 break;
1910 case nir_op_ubitfield_extract:
1911 result = emit_bitfield_extract(&ctx->ac, false, src);
1912 break;
1913 case nir_op_bitfield_insert:
1914 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1915 break;
1916 case nir_op_bitfield_reverse:
1917 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1918 break;
1919 case nir_op_bit_count:
1920 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1921 break;
1922 case nir_op_vec2:
1923 case nir_op_vec3:
1924 case nir_op_vec4:
1925 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1926 src[i] = ac_to_integer(&ctx->ac, src[i]);
1927 result = ac_build_gather_values(&ctx->ac, src, num_components);
1928 break;
1929 case nir_op_f2i32:
1930 case nir_op_f2i64:
1931 src[0] = ac_to_float(&ctx->ac, src[0]);
1932 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1933 break;
1934 case nir_op_f2u32:
1935 case nir_op_f2u64:
1936 src[0] = ac_to_float(&ctx->ac, src[0]);
1937 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1938 break;
1939 case nir_op_i2f32:
1940 case nir_op_i2f64:
1941 src[0] = ac_to_integer(&ctx->ac, src[0]);
1942 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1943 break;
1944 case nir_op_u2f32:
1945 case nir_op_u2f64:
1946 src[0] = ac_to_integer(&ctx->ac, src[0]);
1947 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1948 break;
1949 case nir_op_f2f64:
1950 src[0] = ac_to_float(&ctx->ac, src[0]);
1951 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1952 break;
1953 case nir_op_f2f32:
1954 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1955 break;
1956 case nir_op_u2u32:
1957 case nir_op_u2u64:
1958 src[0] = ac_to_integer(&ctx->ac, src[0]);
1959 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1960 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1961 else
1962 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1963 break;
1964 case nir_op_i2i32:
1965 case nir_op_i2i64:
1966 src[0] = ac_to_integer(&ctx->ac, src[0]);
1967 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1968 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1969 else
1970 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1971 break;
1972 case nir_op_bcsel:
1973 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1974 break;
1975 case nir_op_find_lsb:
1976 src[0] = ac_to_integer(&ctx->ac, src[0]);
1977 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1978 break;
1979 case nir_op_ufind_msb:
1980 src[0] = ac_to_integer(&ctx->ac, src[0]);
1981 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1982 break;
1983 case nir_op_ifind_msb:
1984 src[0] = ac_to_integer(&ctx->ac, src[0]);
1985 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1986 break;
1987 case nir_op_uadd_carry:
1988 src[0] = ac_to_integer(&ctx->ac, src[0]);
1989 src[1] = ac_to_integer(&ctx->ac, src[1]);
1990 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1991 break;
1992 case nir_op_usub_borrow:
1993 src[0] = ac_to_integer(&ctx->ac, src[0]);
1994 src[1] = ac_to_integer(&ctx->ac, src[1]);
1995 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1996 break;
1997 case nir_op_b2f:
1998 result = emit_b2f(&ctx->ac, src[0]);
1999 break;
2000 case nir_op_f2b:
2001 result = emit_f2b(&ctx->ac, src[0]);
2002 break;
2003 case nir_op_b2i:
2004 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2005 break;
2006 case nir_op_i2b:
2007 src[0] = ac_to_integer(&ctx->ac, src[0]);
2008 result = emit_i2b(&ctx->ac, src[0]);
2009 break;
2010 case nir_op_fquantize2f16:
2011 result = emit_f2f16(ctx->nctx, src[0]);
2012 break;
2013 case nir_op_umul_high:
2014 src[0] = ac_to_integer(&ctx->ac, src[0]);
2015 src[1] = ac_to_integer(&ctx->ac, src[1]);
2016 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2017 break;
2018 case nir_op_imul_high:
2019 src[0] = ac_to_integer(&ctx->ac, src[0]);
2020 src[1] = ac_to_integer(&ctx->ac, src[1]);
2021 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2022 break;
2023 case nir_op_pack_half_2x16:
2024 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2025 break;
2026 case nir_op_unpack_half_2x16:
2027 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2028 break;
2029 case nir_op_fddx:
2030 case nir_op_fddy:
2031 case nir_op_fddx_fine:
2032 case nir_op_fddy_fine:
2033 case nir_op_fddx_coarse:
2034 case nir_op_fddy_coarse:
2035 result = emit_ddxy(ctx, instr->op, src[0]);
2036 break;
2037
2038 case nir_op_unpack_64_2x32_split_x: {
2039 assert(instr->src[0].src.ssa->num_components == 1);
2040 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2041 ctx->ac.v2i32,
2042 "");
2043 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2044 ctx->ac.i32_0, "");
2045 break;
2046 }
2047
2048 case nir_op_unpack_64_2x32_split_y: {
2049 assert(instr->src[0].src.ssa->num_components == 1);
2050 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2051 ctx->ac.v2i32,
2052 "");
2053 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2054 ctx->ac.i32_1, "");
2055 break;
2056 }
2057
2058 case nir_op_pack_64_2x32_split: {
2059 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2060 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2061 src[0], ctx->ac.i32_0, "");
2062 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2063 src[1], ctx->ac.i32_1, "");
2064 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2065 break;
2066 }
2067
2068 default:
2069 fprintf(stderr, "Unknown NIR alu instr: ");
2070 nir_print_instr(&instr->instr, stderr);
2071 fprintf(stderr, "\n");
2072 abort();
2073 }
2074
2075 if (result) {
2076 assert(instr->dest.dest.is_ssa);
2077 result = ac_to_integer(&ctx->ac, result);
2078 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2079 result);
2080 }
2081 }
2082
2083 static void visit_load_const(struct ac_nir_context *ctx,
2084 const nir_load_const_instr *instr)
2085 {
2086 LLVMValueRef values[4], value = NULL;
2087 LLVMTypeRef element_type =
2088 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2089
2090 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2091 switch (instr->def.bit_size) {
2092 case 32:
2093 values[i] = LLVMConstInt(element_type,
2094 instr->value.u32[i], false);
2095 break;
2096 case 64:
2097 values[i] = LLVMConstInt(element_type,
2098 instr->value.u64[i], false);
2099 break;
2100 default:
2101 fprintf(stderr,
2102 "unsupported nir load_const bit_size: %d\n",
2103 instr->def.bit_size);
2104 abort();
2105 }
2106 }
2107 if (instr->def.num_components > 1) {
2108 value = LLVMConstVector(values, instr->def.num_components);
2109 } else
2110 value = values[0];
2111
2112 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2113 }
2114
2115 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2116 LLVMTypeRef type)
2117 {
2118 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2119 return LLVMBuildBitCast(ctx->builder, ptr,
2120 LLVMPointerType(type, addr_space), "");
2121 }
2122
2123 static LLVMValueRef
2124 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2125 {
2126 LLVMValueRef size =
2127 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2128 LLVMConstInt(ctx->ac.i32, 2, false), "");
2129
2130 /* VI only */
2131 if (ctx->ac.chip_class == VI && in_elements) {
2132 /* On VI, the descriptor contains the size in bytes,
2133 * but TXQ must return the size in elements.
2134 * The stride is always non-zero for resources using TXQ.
2135 */
2136 LLVMValueRef stride =
2137 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2138 ctx->ac.i32_1, "");
2139 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2140 LLVMConstInt(ctx->ac.i32, 16, false), "");
2141 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2142 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2143
2144 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2145 }
2146 return size;
2147 }
2148
2149 /**
2150 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2151 * intrinsic names).
2152 */
2153 static void build_int_type_name(
2154 LLVMTypeRef type,
2155 char *buf, unsigned bufsize)
2156 {
2157 assert(bufsize >= 6);
2158
2159 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2160 snprintf(buf, bufsize, "v%ui32",
2161 LLVMGetVectorSize(type));
2162 else
2163 strcpy(buf, "i32");
2164 }
2165
2166 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2167 struct ac_image_args *args,
2168 const nir_tex_instr *instr)
2169 {
2170 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2171 LLVMValueRef coord = args->addr;
2172 LLVMValueRef half_texel[2];
2173 LLVMValueRef compare_cube_wa = NULL;
2174 LLVMValueRef result;
2175 int c;
2176 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2177
2178 //TODO Rect
2179 {
2180 struct ac_image_args txq_args = { 0 };
2181
2182 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2183 txq_args.opcode = ac_image_get_resinfo;
2184 txq_args.dmask = 0xf;
2185 txq_args.addr = ctx->i32_0;
2186 txq_args.resource = args->resource;
2187 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2188
2189 for (c = 0; c < 2; c++) {
2190 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2191 LLVMConstInt(ctx->i32, c, false), "");
2192 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2193 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2194 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2195 LLVMConstReal(ctx->f32, -0.5), "");
2196 }
2197 }
2198
2199 LLVMValueRef orig_coords = args->addr;
2200
2201 for (c = 0; c < 2; c++) {
2202 LLVMValueRef tmp;
2203 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2204 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2205 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2206 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2207 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2208 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2209 }
2210
2211
2212 /*
2213 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2214 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2215 * workaround by sampling using a scaled type and converting.
2216 * This is taken from amdgpu-pro shaders.
2217 */
2218 /* NOTE this produces some ugly code compared to amdgpu-pro,
2219 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2220 * and then reads them back. -pro generates two selects,
2221 * one s_cmp for the descriptor rewriting
2222 * one v_cmp for the coordinate and result changes.
2223 */
2224 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2225 LLVMValueRef tmp, tmp2;
2226
2227 /* workaround 8/8/8/8 uint/sint cube gather bug */
2228 /* first detect it then change to a scaled read and f2i */
2229 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2230 tmp2 = tmp;
2231
2232 /* extract the DATA_FORMAT */
2233 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2234 LLVMConstInt(ctx->i32, 6, false), false);
2235
2236 /* is the DATA_FORMAT == 8_8_8_8 */
2237 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2238
2239 if (stype == GLSL_TYPE_UINT)
2240 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2241 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2242 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2243 else
2244 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2245 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2246 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2247
2248 /* replace the NUM FORMAT in the descriptor */
2249 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2250 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2251
2252 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2253
2254 /* don't modify the coordinates for this case */
2255 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2256 }
2257 args->addr = coord;
2258 result = ac_build_image_opcode(ctx, args);
2259
2260 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2261 LLVMValueRef tmp, tmp2;
2262
2263 /* if the cube workaround is in place, f2i the result. */
2264 for (c = 0; c < 4; c++) {
2265 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2266 if (stype == GLSL_TYPE_UINT)
2267 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2268 else
2269 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2270 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2271 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2272 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2273 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2274 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2275 }
2276 }
2277 return result;
2278 }
2279
2280 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2281 const nir_tex_instr *instr,
2282 bool lod_is_zero,
2283 struct ac_image_args *args)
2284 {
2285 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2286 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2287
2288 return ac_build_buffer_load_format(&ctx->ac,
2289 args->resource,
2290 args->addr,
2291 ctx->ac.i32_0,
2292 util_last_bit(mask),
2293 true);
2294 }
2295
2296 args->opcode = ac_image_sample;
2297 args->compare = instr->is_shadow;
2298
2299 switch (instr->op) {
2300 case nir_texop_txf:
2301 case nir_texop_txf_ms:
2302 case nir_texop_samples_identical:
2303 args->opcode = lod_is_zero ||
2304 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2305 ac_image_load : ac_image_load_mip;
2306 args->compare = false;
2307 args->offset = false;
2308 break;
2309 case nir_texop_txb:
2310 args->bias = true;
2311 break;
2312 case nir_texop_txl:
2313 if (lod_is_zero)
2314 args->level_zero = true;
2315 else
2316 args->lod = true;
2317 break;
2318 case nir_texop_txs:
2319 case nir_texop_query_levels:
2320 args->opcode = ac_image_get_resinfo;
2321 break;
2322 case nir_texop_tex:
2323 if (ctx->stage != MESA_SHADER_FRAGMENT)
2324 args->level_zero = true;
2325 break;
2326 case nir_texop_txd:
2327 args->deriv = true;
2328 break;
2329 case nir_texop_tg4:
2330 args->opcode = ac_image_gather4;
2331 args->level_zero = true;
2332 break;
2333 case nir_texop_lod:
2334 args->opcode = ac_image_get_lod;
2335 args->compare = false;
2336 args->offset = false;
2337 break;
2338 default:
2339 break;
2340 }
2341
2342 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2343 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2344 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2345 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2346 }
2347 }
2348 return ac_build_image_opcode(&ctx->ac, args);
2349 }
2350
2351 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2352 nir_intrinsic_instr *instr)
2353 {
2354 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2355 unsigned desc_set = nir_intrinsic_desc_set(instr);
2356 unsigned binding = nir_intrinsic_binding(instr);
2357 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2358 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2359 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2360 unsigned base_offset = layout->binding[binding].offset;
2361 LLVMValueRef offset, stride;
2362
2363 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2364 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2365 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2366 layout->binding[binding].dynamic_offset_offset;
2367 desc_ptr = ctx->push_constants;
2368 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2369 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2370 } else
2371 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2372
2373 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2374 index = LLVMBuildMul(ctx->builder, index, stride, "");
2375 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2376
2377 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2378 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2379 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2380
2381 return desc_ptr;
2382 }
2383
2384 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2385 nir_intrinsic_instr *instr)
2386 {
2387 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2388 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2389
2390 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2391 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2392 return result;
2393 }
2394
2395 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2396 nir_intrinsic_instr *instr)
2397 {
2398 LLVMValueRef ptr, addr;
2399
2400 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2401 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2402
2403 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2404 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2405
2406 return LLVMBuildLoad(ctx->builder, ptr, "");
2407 }
2408
2409 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2410 const nir_intrinsic_instr *instr)
2411 {
2412 LLVMValueRef index = get_src(ctx, instr->src[0]);
2413
2414 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2415 }
2416
2417 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2418 {
2419 uint32_t new_mask = 0;
2420 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2421 if (mask & (1u << i))
2422 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2423 return new_mask;
2424 }
2425
2426 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2427 unsigned start, unsigned count)
2428 {
2429 LLVMTypeRef type = LLVMTypeOf(src);
2430
2431 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2432 assert(start == 0);
2433 assert(count == 1);
2434 return src;
2435 }
2436
2437 unsigned src_elements = LLVMGetVectorSize(type);
2438 assert(start < src_elements);
2439 assert(start + count <= src_elements);
2440
2441 if (start == 0 && count == src_elements)
2442 return src;
2443
2444 if (count == 1)
2445 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2446
2447 assert(count <= 8);
2448 LLVMValueRef indices[8];
2449 for (unsigned i = 0; i < count; ++i)
2450 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2451
2452 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2453 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2454 }
2455
2456 static void visit_store_ssbo(struct ac_nir_context *ctx,
2457 nir_intrinsic_instr *instr)
2458 {
2459 const char *store_name;
2460 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2461 LLVMTypeRef data_type = ctx->ac.f32;
2462 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2463 int components_32bit = elem_size_mult * instr->num_components;
2464 unsigned writemask = nir_intrinsic_write_mask(instr);
2465 LLVMValueRef base_data, base_offset;
2466 LLVMValueRef params[6];
2467
2468 params[1] = ctx->abi->load_ssbo(ctx->abi,
2469 get_src(ctx, instr->src[1]), true);
2470 params[2] = ctx->ac.i32_0; /* vindex */
2471 params[4] = ctx->ac.i1false; /* glc */
2472 params[5] = ctx->ac.i1false; /* slc */
2473
2474 if (components_32bit > 1)
2475 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2476
2477 writemask = widen_mask(writemask, elem_size_mult);
2478
2479 base_data = ac_to_float(&ctx->ac, src_data);
2480 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2481 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2482 data_type, "");
2483 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2484 while (writemask) {
2485 int start, count;
2486 LLVMValueRef data;
2487 LLVMValueRef offset;
2488
2489 u_bit_scan_consecutive_range(&writemask, &start, &count);
2490
2491 /* Due to an LLVM limitation, split 3-element writes
2492 * into a 2-element and a 1-element write. */
2493 if (count == 3) {
2494 writemask |= 1 << (start + 2);
2495 count = 2;
2496 }
2497
2498 if (count > 4) {
2499 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2500 count = 4;
2501 }
2502
2503 if (count == 4) {
2504 store_name = "llvm.amdgcn.buffer.store.v4f32";
2505 } else if (count == 2) {
2506 store_name = "llvm.amdgcn.buffer.store.v2f32";
2507
2508 } else {
2509 assert(count == 1);
2510 store_name = "llvm.amdgcn.buffer.store.f32";
2511 }
2512 data = extract_vector_range(&ctx->ac, base_data, start, count);
2513
2514 offset = base_offset;
2515 if (start != 0) {
2516 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2517 }
2518 params[0] = data;
2519 params[3] = offset;
2520 ac_build_intrinsic(&ctx->ac, store_name,
2521 ctx->ac.voidt, params, 6, 0);
2522 }
2523 }
2524
2525 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2526 const nir_intrinsic_instr *instr)
2527 {
2528 const char *name;
2529 LLVMValueRef params[6];
2530 int arg_count = 0;
2531
2532 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2533 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2534 }
2535 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2536 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2537 get_src(ctx, instr->src[0]),
2538 true);
2539 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2540 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2541 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2542
2543 switch (instr->intrinsic) {
2544 case nir_intrinsic_ssbo_atomic_add:
2545 name = "llvm.amdgcn.buffer.atomic.add";
2546 break;
2547 case nir_intrinsic_ssbo_atomic_imin:
2548 name = "llvm.amdgcn.buffer.atomic.smin";
2549 break;
2550 case nir_intrinsic_ssbo_atomic_umin:
2551 name = "llvm.amdgcn.buffer.atomic.umin";
2552 break;
2553 case nir_intrinsic_ssbo_atomic_imax:
2554 name = "llvm.amdgcn.buffer.atomic.smax";
2555 break;
2556 case nir_intrinsic_ssbo_atomic_umax:
2557 name = "llvm.amdgcn.buffer.atomic.umax";
2558 break;
2559 case nir_intrinsic_ssbo_atomic_and:
2560 name = "llvm.amdgcn.buffer.atomic.and";
2561 break;
2562 case nir_intrinsic_ssbo_atomic_or:
2563 name = "llvm.amdgcn.buffer.atomic.or";
2564 break;
2565 case nir_intrinsic_ssbo_atomic_xor:
2566 name = "llvm.amdgcn.buffer.atomic.xor";
2567 break;
2568 case nir_intrinsic_ssbo_atomic_exchange:
2569 name = "llvm.amdgcn.buffer.atomic.swap";
2570 break;
2571 case nir_intrinsic_ssbo_atomic_comp_swap:
2572 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2573 break;
2574 default:
2575 abort();
2576 }
2577
2578 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2579 }
2580
2581 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2582 const nir_intrinsic_instr *instr)
2583 {
2584 LLVMValueRef results[2];
2585 int load_components;
2586 int num_components = instr->num_components;
2587 if (instr->dest.ssa.bit_size == 64)
2588 num_components *= 2;
2589
2590 for (int i = 0; i < num_components; i += load_components) {
2591 load_components = MIN2(num_components - i, 4);
2592 const char *load_name;
2593 LLVMTypeRef data_type = ctx->ac.f32;
2594 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2595 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2596
2597 if (load_components == 3)
2598 data_type = LLVMVectorType(ctx->ac.f32, 4);
2599 else if (load_components > 1)
2600 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2601
2602 if (load_components >= 3)
2603 load_name = "llvm.amdgcn.buffer.load.v4f32";
2604 else if (load_components == 2)
2605 load_name = "llvm.amdgcn.buffer.load.v2f32";
2606 else if (load_components == 1)
2607 load_name = "llvm.amdgcn.buffer.load.f32";
2608 else
2609 unreachable("unhandled number of components");
2610
2611 LLVMValueRef params[] = {
2612 ctx->abi->load_ssbo(ctx->abi,
2613 get_src(ctx, instr->src[0]),
2614 false),
2615 ctx->ac.i32_0,
2616 offset,
2617 ctx->ac.i1false,
2618 ctx->ac.i1false,
2619 };
2620
2621 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2622 }
2623
2624 assume(results[0]);
2625 LLVMValueRef ret = results[0];
2626 if (num_components > 4 || num_components == 3) {
2627 LLVMValueRef masks[] = {
2628 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2629 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2630 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2631 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2632 };
2633
2634 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2635 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2636 results[num_components > 4 ? 1 : 0], swizzle, "");
2637 }
2638
2639 return LLVMBuildBitCast(ctx->ac.builder, ret,
2640 get_def_type(ctx, &instr->dest.ssa), "");
2641 }
2642
2643 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2644 const nir_intrinsic_instr *instr)
2645 {
2646 LLVMValueRef ret;
2647 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2648 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2649 int num_components = instr->num_components;
2650
2651 if (ctx->abi->load_ubo)
2652 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2653
2654 if (instr->dest.ssa.bit_size == 64)
2655 num_components *= 2;
2656
2657 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2658 NULL, 0, false, false, true, true);
2659 ret = trim_vector(&ctx->ac, ret, num_components);
2660 return LLVMBuildBitCast(ctx->ac.builder, ret,
2661 get_def_type(ctx, &instr->dest.ssa), "");
2662 }
2663
2664 static void
2665 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2666 bool vs_in, unsigned *vertex_index_out,
2667 LLVMValueRef *vertex_index_ref,
2668 unsigned *const_out, LLVMValueRef *indir_out)
2669 {
2670 unsigned const_offset = 0;
2671 nir_deref *tail = &deref->deref;
2672 LLVMValueRef offset = NULL;
2673
2674 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2675 tail = tail->child;
2676 nir_deref_array *deref_array = nir_deref_as_array(tail);
2677 if (vertex_index_out)
2678 *vertex_index_out = deref_array->base_offset;
2679
2680 if (vertex_index_ref) {
2681 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2682 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2683 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2684 }
2685 *vertex_index_ref = vtx;
2686 }
2687 }
2688
2689 if (deref->var->data.compact) {
2690 assert(tail->child->deref_type == nir_deref_type_array);
2691 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2692 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2693 /* We always lower indirect dereferences for "compact" array vars. */
2694 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2695
2696 const_offset = deref_array->base_offset;
2697 goto out;
2698 }
2699
2700 while (tail->child != NULL) {
2701 const struct glsl_type *parent_type = tail->type;
2702 tail = tail->child;
2703
2704 if (tail->deref_type == nir_deref_type_array) {
2705 nir_deref_array *deref_array = nir_deref_as_array(tail);
2706 LLVMValueRef index, stride, local_offset;
2707 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2708
2709 const_offset += size * deref_array->base_offset;
2710 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2711 continue;
2712
2713 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2714 index = get_src(ctx, deref_array->indirect);
2715 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2716 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2717
2718 if (offset)
2719 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2720 else
2721 offset = local_offset;
2722 } else if (tail->deref_type == nir_deref_type_struct) {
2723 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2724
2725 for (unsigned i = 0; i < deref_struct->index; i++) {
2726 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2727 const_offset += glsl_count_attribute_slots(ft, vs_in);
2728 }
2729 } else
2730 unreachable("unsupported deref type");
2731
2732 }
2733 out:
2734 if (const_offset && offset)
2735 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2736 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2737 "");
2738
2739 *const_out = const_offset;
2740 *indir_out = offset;
2741 }
2742
2743
2744 /* The offchip buffer layout for TCS->TES is
2745 *
2746 * - attribute 0 of patch 0 vertex 0
2747 * - attribute 0 of patch 0 vertex 1
2748 * - attribute 0 of patch 0 vertex 2
2749 * ...
2750 * - attribute 0 of patch 1 vertex 0
2751 * - attribute 0 of patch 1 vertex 1
2752 * ...
2753 * - attribute 1 of patch 0 vertex 0
2754 * - attribute 1 of patch 0 vertex 1
2755 * ...
2756 * - per patch attribute 0 of patch 0
2757 * - per patch attribute 0 of patch 1
2758 * ...
2759 *
2760 * Note that every attribute has 4 components.
2761 */
2762 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2763 LLVMValueRef vertex_index,
2764 LLVMValueRef param_index)
2765 {
2766 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2767 LLVMValueRef param_stride, constant16;
2768 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2769
2770 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2771 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2772 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2773 num_patches, "");
2774
2775 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2776 if (vertex_index) {
2777 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2778 vertices_per_patch, "");
2779
2780 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2781 vertex_index, "");
2782
2783 param_stride = total_vertices;
2784 } else {
2785 base_addr = rel_patch_id;
2786 param_stride = num_patches;
2787 }
2788
2789 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2790 LLVMBuildMul(ctx->builder, param_index,
2791 param_stride, ""), "");
2792
2793 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2794
2795 if (!vertex_index) {
2796 LLVMValueRef patch_data_offset =
2797 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2798
2799 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2800 patch_data_offset, "");
2801 }
2802 return base_addr;
2803 }
2804
2805 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2806 unsigned param,
2807 unsigned const_index,
2808 bool is_compact,
2809 LLVMValueRef vertex_index,
2810 LLVMValueRef indir_index)
2811 {
2812 LLVMValueRef param_index;
2813
2814 if (indir_index)
2815 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2816 indir_index, "");
2817 else {
2818 if (const_index && !is_compact)
2819 param += const_index;
2820 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2821 }
2822 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2823 }
2824
2825 static void
2826 mark_tess_output(struct nir_to_llvm_context *ctx,
2827 bool is_patch, uint32_t param)
2828
2829 {
2830 if (is_patch) {
2831 ctx->tess_patch_outputs_written |= (1ull << param);
2832 } else
2833 ctx->tess_outputs_written |= (1ull << param);
2834 }
2835
2836 static LLVMValueRef
2837 get_dw_address(struct nir_to_llvm_context *ctx,
2838 LLVMValueRef dw_addr,
2839 unsigned param,
2840 unsigned const_index,
2841 bool compact_const_index,
2842 LLVMValueRef vertex_index,
2843 LLVMValueRef stride,
2844 LLVMValueRef indir_index)
2845
2846 {
2847
2848 if (vertex_index) {
2849 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2850 LLVMBuildMul(ctx->builder,
2851 vertex_index,
2852 stride, ""), "");
2853 }
2854
2855 if (indir_index)
2856 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2857 LLVMBuildMul(ctx->builder, indir_index,
2858 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2859 else if (const_index && !compact_const_index)
2860 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2861 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2862
2863 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2864 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2865
2866 if (const_index && compact_const_index)
2867 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2868 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2869 return dw_addr;
2870 }
2871
2872 static LLVMValueRef
2873 load_tcs_varyings(struct ac_shader_abi *abi,
2874 LLVMValueRef vertex_index,
2875 LLVMValueRef indir_index,
2876 unsigned const_index,
2877 unsigned location,
2878 unsigned driver_location,
2879 unsigned component,
2880 unsigned num_components,
2881 bool is_patch,
2882 bool is_compact,
2883 bool load_input)
2884 {
2885 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2886 LLVMValueRef dw_addr, stride;
2887 LLVMValueRef value[4], result;
2888 unsigned param = shader_io_get_unique_index(location);
2889
2890 if (load_input) {
2891 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2892 dw_addr = get_tcs_in_current_patch_offset(ctx);
2893 } else {
2894 if (!is_patch) {
2895 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2896 dw_addr = get_tcs_out_current_patch_offset(ctx);
2897 } else {
2898 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2899 stride = NULL;
2900 }
2901 }
2902
2903 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2904 indir_index);
2905
2906 for (unsigned i = 0; i < num_components + component; i++) {
2907 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2908 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2909 ctx->ac.i32_1, "");
2910 }
2911 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2912 return result;
2913 }
2914
2915 static void
2916 store_tcs_output(struct ac_shader_abi *abi,
2917 LLVMValueRef vertex_index,
2918 LLVMValueRef param_index,
2919 unsigned const_index,
2920 unsigned location,
2921 unsigned driver_location,
2922 LLVMValueRef src,
2923 unsigned component,
2924 bool is_patch,
2925 bool is_compact,
2926 unsigned writemask)
2927 {
2928 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2929 LLVMValueRef dw_addr;
2930 LLVMValueRef stride = NULL;
2931 LLVMValueRef buf_addr = NULL;
2932 unsigned param;
2933 bool store_lds = true;
2934
2935 if (is_patch) {
2936 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2937 store_lds = false;
2938 } else {
2939 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2940 store_lds = false;
2941 }
2942
2943 param = shader_io_get_unique_index(location);
2944 if (location == VARYING_SLOT_CLIP_DIST0 &&
2945 is_compact && const_index > 3) {
2946 const_index -= 3;
2947 param++;
2948 }
2949
2950 if (!is_patch) {
2951 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2952 dw_addr = get_tcs_out_current_patch_offset(ctx);
2953 } else {
2954 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2955 }
2956
2957 mark_tess_output(ctx, is_patch, param);
2958
2959 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2960 param_index);
2961 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2962 vertex_index, param_index);
2963
2964 bool is_tess_factor = false;
2965 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2966 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2967 is_tess_factor = true;
2968
2969 unsigned base = is_compact ? const_index : 0;
2970 for (unsigned chan = 0; chan < 8; chan++) {
2971 if (!(writemask & (1 << chan)))
2972 continue;
2973 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2974
2975 if (store_lds || is_tess_factor) {
2976 LLVMValueRef dw_addr_chan =
2977 LLVMBuildAdd(ctx->builder, dw_addr,
2978 LLVMConstInt(ctx->ac.i32, chan, false), "");
2979 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2980 }
2981
2982 if (!is_tess_factor && writemask != 0xF)
2983 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2984 buf_addr, ctx->oc_lds,
2985 4 * (base + chan), 1, 0, true, false);
2986 }
2987
2988 if (writemask == 0xF) {
2989 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2990 buf_addr, ctx->oc_lds,
2991 (base * 4), 1, 0, true, false);
2992 }
2993 }
2994
2995 static LLVMValueRef
2996 load_tes_input(struct ac_shader_abi *abi,
2997 LLVMValueRef vertex_index,
2998 LLVMValueRef param_index,
2999 unsigned const_index,
3000 unsigned location,
3001 unsigned driver_location,
3002 unsigned component,
3003 unsigned num_components,
3004 bool is_patch,
3005 bool is_compact,
3006 bool load_input)
3007 {
3008 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3009 LLVMValueRef buf_addr;
3010 LLVMValueRef result;
3011 unsigned param = shader_io_get_unique_index(location);
3012
3013 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3014 const_index -= 3;
3015 param++;
3016 }
3017
3018 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3019 is_compact, vertex_index, param_index);
3020
3021 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3022 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3023
3024 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3025 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3026 result = trim_vector(&ctx->ac, result, num_components);
3027 return result;
3028 }
3029
3030 static LLVMValueRef
3031 load_gs_input(struct ac_shader_abi *abi,
3032 unsigned location,
3033 unsigned driver_location,
3034 unsigned component,
3035 unsigned num_components,
3036 unsigned vertex_index,
3037 unsigned const_index,
3038 LLVMTypeRef type)
3039 {
3040 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3041 LLVMValueRef vtx_offset;
3042 LLVMValueRef args[9];
3043 unsigned param, vtx_offset_param;
3044 LLVMValueRef value[4], result;
3045
3046 vtx_offset_param = vertex_index;
3047 assert(vtx_offset_param < 6);
3048 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3049 LLVMConstInt(ctx->ac.i32, 4, false), "");
3050
3051 param = shader_io_get_unique_index(location);
3052
3053 for (unsigned i = component; i < num_components + component; i++) {
3054 if (ctx->ac.chip_class >= GFX9) {
3055 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3056 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3057 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3058 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3059 } else {
3060 args[0] = ctx->esgs_ring;
3061 args[1] = vtx_offset;
3062 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3063 args[3] = ctx->ac.i32_0;
3064 args[4] = ctx->ac.i32_1; /* OFFEN */
3065 args[5] = ctx->ac.i32_0; /* IDXEN */
3066 args[6] = ctx->ac.i32_1; /* GLC */
3067 args[7] = ctx->ac.i32_0; /* SLC */
3068 args[8] = ctx->ac.i32_0; /* TFE */
3069
3070 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3071 ctx->ac.i32, args, 9,
3072 AC_FUNC_ATTR_READONLY |
3073 AC_FUNC_ATTR_LEGACY);
3074 }
3075 }
3076 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3077
3078 return result;
3079 }
3080
3081 static LLVMValueRef
3082 build_gep_for_deref(struct ac_nir_context *ctx,
3083 nir_deref_var *deref)
3084 {
3085 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3086 assert(entry->data);
3087 LLVMValueRef val = entry->data;
3088 nir_deref *tail = deref->deref.child;
3089 while (tail != NULL) {
3090 LLVMValueRef offset;
3091 switch (tail->deref_type) {
3092 case nir_deref_type_array: {
3093 nir_deref_array *array = nir_deref_as_array(tail);
3094 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3095 if (array->deref_array_type ==
3096 nir_deref_array_type_indirect) {
3097 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3098 get_src(ctx,
3099 array->indirect),
3100 "");
3101 }
3102 break;
3103 }
3104 case nir_deref_type_struct: {
3105 nir_deref_struct *deref_struct =
3106 nir_deref_as_struct(tail);
3107 offset = LLVMConstInt(ctx->ac.i32,
3108 deref_struct->index, 0);
3109 break;
3110 }
3111 default:
3112 unreachable("bad deref type");
3113 }
3114 val = ac_build_gep0(&ctx->ac, val, offset);
3115 tail = tail->child;
3116 }
3117 return val;
3118 }
3119
3120 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3121 nir_intrinsic_instr *instr,
3122 bool load_inputs)
3123 {
3124 LLVMValueRef result;
3125 LLVMValueRef vertex_index = NULL;
3126 LLVMValueRef indir_index = NULL;
3127 unsigned const_index = 0;
3128 unsigned location = instr->variables[0]->var->data.location;
3129 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3130 const bool is_patch = instr->variables[0]->var->data.patch;
3131 const bool is_compact = instr->variables[0]->var->data.compact;
3132
3133 get_deref_offset(ctx, instr->variables[0],
3134 false, NULL, is_patch ? NULL : &vertex_index,
3135 &const_index, &indir_index);
3136
3137 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3138 const_index, location, driver_location,
3139 instr->variables[0]->var->data.location_frac,
3140 instr->num_components,
3141 is_patch, is_compact, load_inputs);
3142 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3143 }
3144
3145 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3146 nir_intrinsic_instr *instr)
3147 {
3148 LLVMValueRef values[8];
3149 int idx = instr->variables[0]->var->data.driver_location;
3150 int ve = instr->dest.ssa.num_components;
3151 unsigned comp = instr->variables[0]->var->data.location_frac;
3152 LLVMValueRef indir_index;
3153 LLVMValueRef ret;
3154 unsigned const_index;
3155 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3156 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3157 instr->variables[0]->var->data.mode == nir_var_shader_in;
3158 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3159 &const_index, &indir_index);
3160
3161 if (instr->dest.ssa.bit_size == 64)
3162 ve *= 2;
3163
3164 switch (instr->variables[0]->var->data.mode) {
3165 case nir_var_shader_in:
3166 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3167 ctx->stage == MESA_SHADER_TESS_EVAL) {
3168 return load_tess_varyings(ctx, instr, true);
3169 }
3170
3171 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3172 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3173 LLVMValueRef indir_index;
3174 unsigned const_index, vertex_index;
3175 get_deref_offset(ctx, instr->variables[0],
3176 false, &vertex_index, NULL,
3177 &const_index, &indir_index);
3178
3179 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3180 instr->variables[0]->var->data.driver_location,
3181 instr->variables[0]->var->data.location_frac, ve,
3182 vertex_index, const_index, type);
3183 }
3184
3185 for (unsigned chan = comp; chan < ve + comp; chan++) {
3186 if (indir_index) {
3187 unsigned count = glsl_count_attribute_slots(
3188 instr->variables[0]->var->type,
3189 ctx->stage == MESA_SHADER_VERTEX);
3190 count -= chan / 4;
3191 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3192 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3193 stride, false, true);
3194
3195 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3196 tmp_vec,
3197 indir_index, "");
3198 } else
3199 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3200 }
3201 break;
3202 case nir_var_local:
3203 for (unsigned chan = 0; chan < ve; chan++) {
3204 if (indir_index) {
3205 unsigned count = glsl_count_attribute_slots(
3206 instr->variables[0]->var->type, false);
3207 count -= chan / 4;
3208 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3209 &ctx->ac, ctx->locals + idx + chan, count,
3210 stride, true, true);
3211
3212 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3213 tmp_vec,
3214 indir_index, "");
3215 } else {
3216 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3217 }
3218 }
3219 break;
3220 case nir_var_shared: {
3221 LLVMValueRef address = build_gep_for_deref(ctx,
3222 instr->variables[0]);
3223 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3224 return LLVMBuildBitCast(ctx->ac.builder, val,
3225 get_def_type(ctx, &instr->dest.ssa),
3226 "");
3227 }
3228 case nir_var_shader_out:
3229 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3230 return load_tess_varyings(ctx, instr, false);
3231 }
3232
3233 for (unsigned chan = comp; chan < ve + comp; chan++) {
3234 if (indir_index) {
3235 unsigned count = glsl_count_attribute_slots(
3236 instr->variables[0]->var->type, false);
3237 count -= chan / 4;
3238 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3239 &ctx->ac, ctx->outputs + idx + chan, count,
3240 stride, true, true);
3241
3242 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3243 tmp_vec,
3244 indir_index, "");
3245 } else {
3246 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3247 ctx->outputs[idx + chan + const_index * stride],
3248 "");
3249 }
3250 }
3251 break;
3252 default:
3253 unreachable("unhandle variable mode");
3254 }
3255 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3256 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3257 }
3258
3259 static void
3260 visit_store_var(struct ac_nir_context *ctx,
3261 nir_intrinsic_instr *instr)
3262 {
3263 LLVMValueRef temp_ptr, value;
3264 int idx = instr->variables[0]->var->data.driver_location;
3265 unsigned comp = instr->variables[0]->var->data.location_frac;
3266 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3267 int writemask = instr->const_index[0] << comp;
3268 LLVMValueRef indir_index;
3269 unsigned const_index;
3270 get_deref_offset(ctx, instr->variables[0], false,
3271 NULL, NULL, &const_index, &indir_index);
3272
3273 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3274
3275 src = LLVMBuildBitCast(ctx->ac.builder, src,
3276 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3277 "");
3278
3279 writemask = widen_mask(writemask, 2);
3280 }
3281
3282 switch (instr->variables[0]->var->data.mode) {
3283 case nir_var_shader_out:
3284
3285 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3286 LLVMValueRef vertex_index = NULL;
3287 LLVMValueRef indir_index = NULL;
3288 unsigned const_index = 0;
3289 const unsigned location = instr->variables[0]->var->data.location;
3290 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3291 const unsigned comp = instr->variables[0]->var->data.location_frac;
3292 const bool is_patch = instr->variables[0]->var->data.patch;
3293 const bool is_compact = instr->variables[0]->var->data.compact;
3294
3295 get_deref_offset(ctx, instr->variables[0],
3296 false, NULL, is_patch ? NULL : &vertex_index,
3297 &const_index, &indir_index);
3298
3299 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3300 const_index, location, driver_location,
3301 src, comp, is_patch, is_compact, writemask);
3302 return;
3303 }
3304
3305 for (unsigned chan = 0; chan < 8; chan++) {
3306 int stride = 4;
3307 if (!(writemask & (1 << chan)))
3308 continue;
3309
3310 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3311
3312 if (instr->variables[0]->var->data.compact)
3313 stride = 1;
3314 if (indir_index) {
3315 unsigned count = glsl_count_attribute_slots(
3316 instr->variables[0]->var->type, false);
3317 count -= chan / 4;
3318 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3319 &ctx->ac, ctx->outputs + idx + chan, count,
3320 stride, true, true);
3321
3322 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3323 value, indir_index, "");
3324 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3325 count, stride, tmp_vec);
3326
3327 } else {
3328 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3329
3330 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3331 }
3332 }
3333 break;
3334 case nir_var_local:
3335 for (unsigned chan = 0; chan < 8; chan++) {
3336 if (!(writemask & (1 << chan)))
3337 continue;
3338
3339 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3340 if (indir_index) {
3341 unsigned count = glsl_count_attribute_slots(
3342 instr->variables[0]->var->type, false);
3343 count -= chan / 4;
3344 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3345 &ctx->ac, ctx->locals + idx + chan, count,
3346 4, true, true);
3347
3348 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3349 value, indir_index, "");
3350 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3351 count, 4, tmp_vec);
3352 } else {
3353 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3354
3355 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3356 }
3357 }
3358 break;
3359 case nir_var_shared: {
3360 int writemask = instr->const_index[0];
3361 LLVMValueRef address = build_gep_for_deref(ctx,
3362 instr->variables[0]);
3363 LLVMValueRef val = get_src(ctx, instr->src[0]);
3364 unsigned components =
3365 glsl_get_vector_elements(
3366 nir_deref_tail(&instr->variables[0]->deref)->type);
3367 if (writemask == (1 << components) - 1) {
3368 val = LLVMBuildBitCast(
3369 ctx->ac.builder, val,
3370 LLVMGetElementType(LLVMTypeOf(address)), "");
3371 LLVMBuildStore(ctx->ac.builder, val, address);
3372 } else {
3373 for (unsigned chan = 0; chan < 4; chan++) {
3374 if (!(writemask & (1 << chan)))
3375 continue;
3376 LLVMValueRef ptr =
3377 LLVMBuildStructGEP(ctx->ac.builder,
3378 address, chan, "");
3379 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3380 chan);
3381 src = LLVMBuildBitCast(
3382 ctx->ac.builder, src,
3383 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3384 LLVMBuildStore(ctx->ac.builder, src, ptr);
3385 }
3386 }
3387 break;
3388 }
3389 default:
3390 break;
3391 }
3392 }
3393
3394 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3395 {
3396 switch (dim) {
3397 case GLSL_SAMPLER_DIM_BUF:
3398 return 1;
3399 case GLSL_SAMPLER_DIM_1D:
3400 return array ? 2 : 1;
3401 case GLSL_SAMPLER_DIM_2D:
3402 return array ? 3 : 2;
3403 case GLSL_SAMPLER_DIM_MS:
3404 return array ? 4 : 3;
3405 case GLSL_SAMPLER_DIM_3D:
3406 case GLSL_SAMPLER_DIM_CUBE:
3407 return 3;
3408 case GLSL_SAMPLER_DIM_RECT:
3409 case GLSL_SAMPLER_DIM_SUBPASS:
3410 return 2;
3411 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3412 return 3;
3413 default:
3414 break;
3415 }
3416 return 0;
3417 }
3418
3419
3420
3421 /* Adjust the sample index according to FMASK.
3422 *
3423 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3424 * which is the identity mapping. Each nibble says which physical sample
3425 * should be fetched to get that sample.
3426 *
3427 * For example, 0x11111100 means there are only 2 samples stored and
3428 * the second sample covers 3/4 of the pixel. When reading samples 0
3429 * and 1, return physical sample 0 (determined by the first two 0s
3430 * in FMASK), otherwise return physical sample 1.
3431 *
3432 * The sample index should be adjusted as follows:
3433 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3434 */
3435 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3436 LLVMValueRef coord_x, LLVMValueRef coord_y,
3437 LLVMValueRef coord_z,
3438 LLVMValueRef sample_index,
3439 LLVMValueRef fmask_desc_ptr)
3440 {
3441 LLVMValueRef fmask_load_address[4];
3442 LLVMValueRef res;
3443
3444 fmask_load_address[0] = coord_x;
3445 fmask_load_address[1] = coord_y;
3446 if (coord_z) {
3447 fmask_load_address[2] = coord_z;
3448 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3449 }
3450
3451 struct ac_image_args args = {0};
3452
3453 args.opcode = ac_image_load;
3454 args.da = coord_z ? true : false;
3455 args.resource = fmask_desc_ptr;
3456 args.dmask = 0xf;
3457 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3458
3459 res = ac_build_image_opcode(ctx, &args);
3460
3461 res = ac_to_integer(ctx, res);
3462 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3463 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3464
3465 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3466 res,
3467 ctx->i32_0, "");
3468
3469 LLVMValueRef sample_index4 =
3470 LLVMBuildMul(ctx->builder, sample_index, four, "");
3471 LLVMValueRef shifted_fmask =
3472 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3473 LLVMValueRef final_sample =
3474 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3475
3476 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3477 * resource descriptor is 0 (invalid),
3478 */
3479 LLVMValueRef fmask_desc =
3480 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3481 ctx->v8i32, "");
3482
3483 LLVMValueRef fmask_word1 =
3484 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3485 ctx->i32_1, "");
3486
3487 LLVMValueRef word1_is_nonzero =
3488 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3489 fmask_word1, ctx->i32_0, "");
3490
3491 /* Replace the MSAA sample index. */
3492 sample_index =
3493 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3494 final_sample, sample_index, "");
3495 return sample_index;
3496 }
3497
3498 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3499 const nir_intrinsic_instr *instr)
3500 {
3501 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3502
3503 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3504 LLVMValueRef coords[4];
3505 LLVMValueRef masks[] = {
3506 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3507 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3508 };
3509 LLVMValueRef res;
3510 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3511
3512 int count;
3513 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3514 bool is_array = glsl_sampler_type_is_array(type);
3515 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3516 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3517 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3518 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3519 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3520 count = image_type_to_components_count(dim, is_array);
3521
3522 if (is_ms) {
3523 LLVMValueRef fmask_load_address[3];
3524 int chan;
3525
3526 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3527 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3528 if (is_array)
3529 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3530 else
3531 fmask_load_address[2] = NULL;
3532 if (add_frag_pos) {
3533 for (chan = 0; chan < 2; ++chan)
3534 fmask_load_address[chan] =
3535 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3536 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3537 ctx->ac.i32, ""), "");
3538 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3539 }
3540 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3541 fmask_load_address[0],
3542 fmask_load_address[1],
3543 fmask_load_address[2],
3544 sample_index,
3545 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3546 }
3547 if (count == 1 && !gfx9_1d) {
3548 if (instr->src[0].ssa->num_components)
3549 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3550 else
3551 res = src0;
3552 } else {
3553 int chan;
3554 if (is_ms)
3555 count--;
3556 for (chan = 0; chan < count; ++chan) {
3557 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3558 }
3559 if (add_frag_pos) {
3560 for (chan = 0; chan < 2; ++chan)
3561 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3562 ctx->ac.i32, ""), "");
3563 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3564 count++;
3565 }
3566
3567 if (gfx9_1d) {
3568 if (is_array) {
3569 coords[2] = coords[1];
3570 coords[1] = ctx->ac.i32_0;
3571 } else
3572 coords[1] = ctx->ac.i32_0;
3573 count++;
3574 }
3575
3576 if (is_ms) {
3577 coords[count] = sample_index;
3578 count++;
3579 }
3580
3581 if (count == 3) {
3582 coords[3] = LLVMGetUndef(ctx->ac.i32);
3583 count = 4;
3584 }
3585 res = ac_build_gather_values(&ctx->ac, coords, count);
3586 }
3587 return res;
3588 }
3589
3590 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3591 const nir_intrinsic_instr *instr)
3592 {
3593 LLVMValueRef params[7];
3594 LLVMValueRef res;
3595 char intrinsic_name[64];
3596 const nir_variable *var = instr->variables[0]->var;
3597 const struct glsl_type *type = var->type;
3598
3599 if(instr->variables[0]->deref.child)
3600 type = instr->variables[0]->deref.child->type;
3601
3602 type = glsl_without_array(type);
3603
3604 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3605 if (dim == GLSL_SAMPLER_DIM_BUF) {
3606 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3607 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3608 ctx->ac.i32_0, ""); /* vindex */
3609 params[2] = ctx->ac.i32_0; /* voffset */
3610 params[3] = ctx->ac.i1false; /* glc */
3611 params[4] = ctx->ac.i1false; /* slc */
3612 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3613 params, 5, 0);
3614
3615 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3616 res = ac_to_integer(&ctx->ac, res);
3617 } else {
3618 bool is_da = glsl_sampler_type_is_array(type) ||
3619 dim == GLSL_SAMPLER_DIM_CUBE ||
3620 dim == GLSL_SAMPLER_DIM_3D ||
3621 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3622 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3623 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3624 LLVMValueRef glc = ctx->ac.i1false;
3625 LLVMValueRef slc = ctx->ac.i1false;
3626
3627 params[0] = get_image_coords(ctx, instr);
3628 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3629 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3630 if (HAVE_LLVM <= 0x0309) {
3631 params[3] = ctx->ac.i1false; /* r128 */
3632 params[4] = da;
3633 params[5] = glc;
3634 params[6] = slc;
3635 } else {
3636 LLVMValueRef lwe = ctx->ac.i1false;
3637 params[3] = glc;
3638 params[4] = slc;
3639 params[5] = lwe;
3640 params[6] = da;
3641 }
3642
3643 ac_get_image_intr_name("llvm.amdgcn.image.load",
3644 ctx->ac.v4f32, /* vdata */
3645 LLVMTypeOf(params[0]), /* coords */
3646 LLVMTypeOf(params[1]), /* rsrc */
3647 intrinsic_name, sizeof(intrinsic_name));
3648
3649 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3650 params, 7, AC_FUNC_ATTR_READONLY);
3651 }
3652 return ac_to_integer(&ctx->ac, res);
3653 }
3654
3655 static void visit_image_store(struct ac_nir_context *ctx,
3656 nir_intrinsic_instr *instr)
3657 {
3658 LLVMValueRef params[8];
3659 char intrinsic_name[64];
3660 const nir_variable *var = instr->variables[0]->var;
3661 const struct glsl_type *type = glsl_without_array(var->type);
3662 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3663 LLVMValueRef glc = ctx->ac.i1false;
3664 bool force_glc = ctx->ac.chip_class == SI;
3665 if (force_glc)
3666 glc = ctx->ac.i1true;
3667
3668 if (dim == GLSL_SAMPLER_DIM_BUF) {
3669 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3670 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3671 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3672 ctx->ac.i32_0, ""); /* vindex */
3673 params[3] = ctx->ac.i32_0; /* voffset */
3674 params[4] = glc; /* glc */
3675 params[5] = ctx->ac.i1false; /* slc */
3676 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3677 params, 6, 0);
3678 } else {
3679 bool is_da = glsl_sampler_type_is_array(type) ||
3680 dim == GLSL_SAMPLER_DIM_CUBE ||
3681 dim == GLSL_SAMPLER_DIM_3D;
3682 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3683 LLVMValueRef slc = ctx->ac.i1false;
3684
3685 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3686 params[1] = get_image_coords(ctx, instr); /* coords */
3687 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3688 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3689 if (HAVE_LLVM <= 0x0309) {
3690 params[4] = ctx->ac.i1false; /* r128 */
3691 params[5] = da;
3692 params[6] = glc;
3693 params[7] = slc;
3694 } else {
3695 LLVMValueRef lwe = ctx->ac.i1false;
3696 params[4] = glc;
3697 params[5] = slc;
3698 params[6] = lwe;
3699 params[7] = da;
3700 }
3701
3702 ac_get_image_intr_name("llvm.amdgcn.image.store",
3703 LLVMTypeOf(params[0]), /* vdata */
3704 LLVMTypeOf(params[1]), /* coords */
3705 LLVMTypeOf(params[2]), /* rsrc */
3706 intrinsic_name, sizeof(intrinsic_name));
3707
3708 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3709 params, 8, 0);
3710 }
3711
3712 }
3713
3714 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3715 const nir_intrinsic_instr *instr)
3716 {
3717 LLVMValueRef params[7];
3718 int param_count = 0;
3719 const nir_variable *var = instr->variables[0]->var;
3720
3721 const char *atomic_name;
3722 char intrinsic_name[41];
3723 const struct glsl_type *type = glsl_without_array(var->type);
3724 MAYBE_UNUSED int length;
3725
3726 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3727
3728 switch (instr->intrinsic) {
3729 case nir_intrinsic_image_atomic_add:
3730 atomic_name = "add";
3731 break;
3732 case nir_intrinsic_image_atomic_min:
3733 atomic_name = is_unsigned ? "umin" : "smin";
3734 break;
3735 case nir_intrinsic_image_atomic_max:
3736 atomic_name = is_unsigned ? "umax" : "smax";
3737 break;
3738 case nir_intrinsic_image_atomic_and:
3739 atomic_name = "and";
3740 break;
3741 case nir_intrinsic_image_atomic_or:
3742 atomic_name = "or";
3743 break;
3744 case nir_intrinsic_image_atomic_xor:
3745 atomic_name = "xor";
3746 break;
3747 case nir_intrinsic_image_atomic_exchange:
3748 atomic_name = "swap";
3749 break;
3750 case nir_intrinsic_image_atomic_comp_swap:
3751 atomic_name = "cmpswap";
3752 break;
3753 default:
3754 abort();
3755 }
3756
3757 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3758 params[param_count++] = get_src(ctx, instr->src[3]);
3759 params[param_count++] = get_src(ctx, instr->src[2]);
3760
3761 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3762 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3763 NULL, true, true);
3764 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3765 ctx->ac.i32_0, ""); /* vindex */
3766 params[param_count++] = ctx->ac.i32_0; /* voffset */
3767 params[param_count++] = ctx->ac.i1false; /* slc */
3768
3769 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3770 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3771 } else {
3772 char coords_type[8];
3773
3774 bool da = glsl_sampler_type_is_array(type) ||
3775 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3776
3777 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3778 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3779 NULL, true, true);
3780 params[param_count++] = ctx->ac.i1false; /* r128 */
3781 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3782 params[param_count++] = ctx->ac.i1false; /* slc */
3783
3784 build_int_type_name(LLVMTypeOf(coords),
3785 coords_type, sizeof(coords_type));
3786
3787 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3788 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3789 }
3790
3791 assert(length < sizeof(intrinsic_name));
3792 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3793 }
3794
3795 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3796 const nir_intrinsic_instr *instr)
3797 {
3798 LLVMValueRef res;
3799 const nir_variable *var = instr->variables[0]->var;
3800 const struct glsl_type *type = instr->variables[0]->var->type;
3801 bool da = glsl_sampler_type_is_array(var->type) ||
3802 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE ||
3803 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_3D;
3804 if(instr->variables[0]->deref.child)
3805 type = instr->variables[0]->deref.child->type;
3806
3807 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3808 return get_buffer_size(ctx,
3809 get_sampler_desc(ctx, instr->variables[0],
3810 AC_DESC_BUFFER, NULL, true, false), true);
3811
3812 struct ac_image_args args = { 0 };
3813
3814 args.da = da;
3815 args.dmask = 0xf;
3816 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3817 args.opcode = ac_image_get_resinfo;
3818 args.addr = ctx->ac.i32_0;
3819
3820 res = ac_build_image_opcode(&ctx->ac, &args);
3821
3822 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3823
3824 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3825 glsl_sampler_type_is_array(type)) {
3826 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3827 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3828 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3829 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3830 }
3831 if (ctx->ac.chip_class >= GFX9 &&
3832 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3833 glsl_sampler_type_is_array(type)) {
3834 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3835 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3836 ctx->ac.i32_1, "");
3837
3838 }
3839 return res;
3840 }
3841
3842 #define NOOP_WAITCNT 0xf7f
3843 #define LGKM_CNT 0x07f
3844 #define VM_CNT 0xf70
3845
3846 static void emit_membar(struct nir_to_llvm_context *ctx,
3847 const nir_intrinsic_instr *instr)
3848 {
3849 unsigned waitcnt = NOOP_WAITCNT;
3850
3851 switch (instr->intrinsic) {
3852 case nir_intrinsic_memory_barrier:
3853 case nir_intrinsic_group_memory_barrier:
3854 waitcnt &= VM_CNT & LGKM_CNT;
3855 break;
3856 case nir_intrinsic_memory_barrier_atomic_counter:
3857 case nir_intrinsic_memory_barrier_buffer:
3858 case nir_intrinsic_memory_barrier_image:
3859 waitcnt &= VM_CNT;
3860 break;
3861 case nir_intrinsic_memory_barrier_shared:
3862 waitcnt &= LGKM_CNT;
3863 break;
3864 default:
3865 break;
3866 }
3867 if (waitcnt != NOOP_WAITCNT)
3868 ac_build_waitcnt(&ctx->ac, waitcnt);
3869 }
3870
3871 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3872 {
3873 /* SI only (thanks to a hw bug workaround):
3874 * The real barrier instruction isn’t needed, because an entire patch
3875 * always fits into a single wave.
3876 */
3877 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3878 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3879 return;
3880 }
3881 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3882 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3883 }
3884
3885 static void emit_discard(struct ac_nir_context *ctx,
3886 const nir_intrinsic_instr *instr)
3887 {
3888 LLVMValueRef cond;
3889
3890 if (instr->intrinsic == nir_intrinsic_discard_if) {
3891 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3892 get_src(ctx, instr->src[0]),
3893 ctx->ac.i32_0, "");
3894 } else {
3895 assert(instr->intrinsic == nir_intrinsic_discard);
3896 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3897 }
3898
3899 ac_build_kill_if_false(&ctx->ac, cond);
3900 }
3901
3902 static LLVMValueRef
3903 visit_load_helper_invocation(struct ac_nir_context *ctx)
3904 {
3905 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3906 "llvm.amdgcn.ps.live",
3907 ctx->ac.i1, NULL, 0,
3908 AC_FUNC_ATTR_READNONE);
3909 result = LLVMBuildNot(ctx->ac.builder, result, "");
3910 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3911 }
3912
3913 static LLVMValueRef
3914 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3915 {
3916 LLVMValueRef result;
3917 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3918 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3919 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3920
3921 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3922 }
3923
3924 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3925 const nir_intrinsic_instr *instr)
3926 {
3927 LLVMValueRef ptr, result;
3928 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3929 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3930
3931 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3932 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3933 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3934 ptr, src, src1,
3935 LLVMAtomicOrderingSequentiallyConsistent,
3936 LLVMAtomicOrderingSequentiallyConsistent,
3937 false);
3938 } else {
3939 LLVMAtomicRMWBinOp op;
3940 switch (instr->intrinsic) {
3941 case nir_intrinsic_var_atomic_add:
3942 op = LLVMAtomicRMWBinOpAdd;
3943 break;
3944 case nir_intrinsic_var_atomic_umin:
3945 op = LLVMAtomicRMWBinOpUMin;
3946 break;
3947 case nir_intrinsic_var_atomic_umax:
3948 op = LLVMAtomicRMWBinOpUMax;
3949 break;
3950 case nir_intrinsic_var_atomic_imin:
3951 op = LLVMAtomicRMWBinOpMin;
3952 break;
3953 case nir_intrinsic_var_atomic_imax:
3954 op = LLVMAtomicRMWBinOpMax;
3955 break;
3956 case nir_intrinsic_var_atomic_and:
3957 op = LLVMAtomicRMWBinOpAnd;
3958 break;
3959 case nir_intrinsic_var_atomic_or:
3960 op = LLVMAtomicRMWBinOpOr;
3961 break;
3962 case nir_intrinsic_var_atomic_xor:
3963 op = LLVMAtomicRMWBinOpXor;
3964 break;
3965 case nir_intrinsic_var_atomic_exchange:
3966 op = LLVMAtomicRMWBinOpXchg;
3967 break;
3968 default:
3969 return NULL;
3970 }
3971
3972 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3973 LLVMAtomicOrderingSequentiallyConsistent,
3974 false);
3975 }
3976 return result;
3977 }
3978
3979 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3980 enum glsl_interp_mode interp, unsigned location)
3981 {
3982 switch (interp) {
3983 case INTERP_MODE_FLAT:
3984 default:
3985 return NULL;
3986 case INTERP_MODE_SMOOTH:
3987 case INTERP_MODE_NONE:
3988 if (location == INTERP_CENTER)
3989 return ctx->persp_center;
3990 else if (location == INTERP_CENTROID)
3991 return ctx->persp_centroid;
3992 else if (location == INTERP_SAMPLE)
3993 return ctx->persp_sample;
3994 break;
3995 case INTERP_MODE_NOPERSPECTIVE:
3996 if (location == INTERP_CENTER)
3997 return ctx->linear_center;
3998 else if (location == INTERP_CENTROID)
3999 return ctx->linear_centroid;
4000 else if (location == INTERP_SAMPLE)
4001 return ctx->linear_sample;
4002 break;
4003 }
4004 return NULL;
4005 }
4006
4007 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
4008 LLVMValueRef sample_id)
4009 {
4010 LLVMValueRef result;
4011 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4012
4013 ptr = LLVMBuildBitCast(ctx->builder, ptr,
4014 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4015
4016 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
4017 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4018
4019 return result;
4020 }
4021
4022 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4023 {
4024 LLVMValueRef values[2];
4025
4026 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
4027 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
4028 return ac_build_gather_values(&ctx->ac, values, 2);
4029 }
4030
4031 static LLVMValueRef load_sample_mask_in(struct ac_nir_context *ctx)
4032 {
4033 uint8_t log2_ps_iter_samples = ctx->nctx->shader_info->info.ps.force_persample ? ctx->nctx->options->key.fs.log2_num_samples : ctx->nctx->options->key.fs.log2_ps_iter_samples;
4034
4035 /* The bit pattern matches that used by fixed function fragment
4036 * processing. */
4037 static const uint16_t ps_iter_masks[] = {
4038 0xffff, /* not used */
4039 0x5555,
4040 0x1111,
4041 0x0101,
4042 0x0001,
4043 };
4044 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4045
4046 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4047
4048 LLVMValueRef result, sample_id;
4049 sample_id = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4050 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4051 result = LLVMBuildAnd(ctx->ac.builder, sample_id, ctx->abi->sample_coverage, "");
4052 return result;
4053 }
4054
4055 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
4056 const nir_intrinsic_instr *instr)
4057 {
4058 LLVMValueRef result[4];
4059 LLVMValueRef interp_param, attr_number;
4060 unsigned location;
4061 unsigned chan;
4062 LLVMValueRef src_c0 = NULL;
4063 LLVMValueRef src_c1 = NULL;
4064 LLVMValueRef src0 = NULL;
4065 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4066 switch (instr->intrinsic) {
4067 case nir_intrinsic_interp_var_at_centroid:
4068 location = INTERP_CENTROID;
4069 break;
4070 case nir_intrinsic_interp_var_at_sample:
4071 case nir_intrinsic_interp_var_at_offset:
4072 location = INTERP_CENTER;
4073 src0 = get_src(ctx->nir, instr->src[0]);
4074 break;
4075 default:
4076 break;
4077 }
4078
4079 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4080 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
4081 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
4082 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4083 LLVMValueRef sample_position;
4084 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4085
4086 /* fetch sample ID */
4087 sample_position = load_sample_position(ctx, src0);
4088
4089 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4090 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4091 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4092 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4093 }
4094 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4095 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4096
4097 if (location == INTERP_CENTER) {
4098 LLVMValueRef ij_out[2];
4099 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4100
4101 /*
4102 * take the I then J parameters, and the DDX/Y for it, and
4103 * calculate the IJ inputs for the interpolator.
4104 * temp1 = ddx * offset/sample.x + I;
4105 * interp_param.I = ddy * offset/sample.y + temp1;
4106 * temp1 = ddx * offset/sample.x + J;
4107 * interp_param.J = ddy * offset/sample.y + temp1;
4108 */
4109 for (unsigned i = 0; i < 2; i++) {
4110 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4111 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4112 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4113 ddxy_out, ix_ll, "");
4114 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4115 ddxy_out, iy_ll, "");
4116 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4117 interp_param, ix_ll, "");
4118 LLVMValueRef temp1, temp2;
4119
4120 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4121 ctx->ac.f32, "");
4122
4123 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4124 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4125
4126 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4127 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4128
4129 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4130 temp2, ctx->ac.i32, "");
4131 }
4132 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4133
4134 }
4135
4136 for (chan = 0; chan < 4; chan++) {
4137 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4138
4139 if (interp_param) {
4140 interp_param = LLVMBuildBitCast(ctx->builder,
4141 interp_param, ctx->ac.v2f32, "");
4142 LLVMValueRef i = LLVMBuildExtractElement(
4143 ctx->builder, interp_param, ctx->ac.i32_0, "");
4144 LLVMValueRef j = LLVMBuildExtractElement(
4145 ctx->builder, interp_param, ctx->ac.i32_1, "");
4146
4147 result[chan] = ac_build_fs_interp(&ctx->ac,
4148 llvm_chan, attr_number,
4149 ctx->prim_mask, i, j);
4150 } else {
4151 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4152 LLVMConstInt(ctx->ac.i32, 2, false),
4153 llvm_chan, attr_number,
4154 ctx->prim_mask);
4155 }
4156 }
4157 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4158 instr->variables[0]->var->data.location_frac);
4159 }
4160
4161 static void
4162 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4163 {
4164 LLVMValueRef gs_next_vertex;
4165 LLVMValueRef can_emit;
4166 int idx;
4167 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4168
4169 assert(stream == 0);
4170
4171 /* Write vertex attribute values to GSVS ring */
4172 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4173 ctx->gs_next_vertex,
4174 "");
4175
4176 /* If this thread has already emitted the declared maximum number of
4177 * vertices, kill it: excessive vertex emissions are not supposed to
4178 * have any effect, and GS threads have no externally observable
4179 * effects other than emitting vertices.
4180 */
4181 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4182 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4183 ac_build_kill_if_false(&ctx->ac, can_emit);
4184
4185 /* loop num outputs */
4186 idx = 0;
4187 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4188 LLVMValueRef *out_ptr = &addrs[i * 4];
4189 int length = 4;
4190 int slot = idx;
4191 int slot_inc = 1;
4192
4193 if (!(ctx->output_mask & (1ull << i)))
4194 continue;
4195
4196 if (i == VARYING_SLOT_CLIP_DIST0) {
4197 /* pack clip and cull into a single set of slots */
4198 length = ctx->num_output_clips + ctx->num_output_culls;
4199 if (length > 4)
4200 slot_inc = 2;
4201 }
4202 for (unsigned j = 0; j < length; j++) {
4203 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4204 out_ptr[j], "");
4205 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4206 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4207 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4208
4209 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4210
4211 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4212 out_val, 1,
4213 voffset, ctx->gs2vs_offset, 0,
4214 1, 1, true, true);
4215 }
4216 idx += slot_inc;
4217 }
4218
4219 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4220 ctx->ac.i32_1, "");
4221 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4222
4223 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4224 }
4225
4226 static void
4227 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4228 {
4229 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4230 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4231 }
4232
4233 static LLVMValueRef
4234 load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
4235 unsigned num_components)
4236 {
4237 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4238
4239 LLVMValueRef coord[4] = {
4240 ctx->tes_u,
4241 ctx->tes_v,
4242 ctx->ac.f32_0,
4243 ctx->ac.f32_0,
4244 };
4245
4246 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4247 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4248 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4249
4250 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, num_components);
4251 return LLVMBuildBitCast(ctx->builder, result, type, "");
4252 }
4253
4254 static LLVMValueRef
4255 load_patch_vertices_in(struct ac_shader_abi *abi)
4256 {
4257 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4258 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4259 }
4260
4261 static void visit_intrinsic(struct ac_nir_context *ctx,
4262 nir_intrinsic_instr *instr)
4263 {
4264 LLVMValueRef result = NULL;
4265
4266 switch (instr->intrinsic) {
4267 case nir_intrinsic_ballot:
4268 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4269 break;
4270 case nir_intrinsic_read_invocation:
4271 case nir_intrinsic_read_first_invocation: {
4272 LLVMValueRef args[2];
4273
4274 /* Value */
4275 args[0] = get_src(ctx, instr->src[0]);
4276
4277 unsigned num_args;
4278 const char *intr_name;
4279 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4280 num_args = 2;
4281 intr_name = "llvm.amdgcn.readlane";
4282
4283 /* Invocation */
4284 args[1] = get_src(ctx, instr->src[1]);
4285 } else {
4286 num_args = 1;
4287 intr_name = "llvm.amdgcn.readfirstlane";
4288 }
4289
4290 /* We currently have no other way to prevent LLVM from lifting the icmp
4291 * calls to a dominating basic block.
4292 */
4293 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4294
4295 result = ac_build_intrinsic(&ctx->ac, intr_name,
4296 ctx->ac.i32, args, num_args,
4297 AC_FUNC_ATTR_READNONE |
4298 AC_FUNC_ATTR_CONVERGENT);
4299 break;
4300 }
4301 case nir_intrinsic_load_subgroup_invocation:
4302 result = ac_get_thread_id(&ctx->ac);
4303 break;
4304 case nir_intrinsic_load_work_group_id: {
4305 LLVMValueRef values[3];
4306
4307 for (int i = 0; i < 3; i++) {
4308 values[i] = ctx->nctx->workgroup_ids[i] ?
4309 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4310 }
4311
4312 result = ac_build_gather_values(&ctx->ac, values, 3);
4313 break;
4314 }
4315 case nir_intrinsic_load_base_vertex: {
4316 result = ctx->abi->base_vertex;
4317 break;
4318 }
4319 case nir_intrinsic_load_vertex_id_zero_base: {
4320 result = ctx->abi->vertex_id;
4321 break;
4322 }
4323 case nir_intrinsic_load_local_invocation_id: {
4324 result = ctx->nctx->local_invocation_ids;
4325 break;
4326 }
4327 case nir_intrinsic_load_base_instance:
4328 result = ctx->abi->start_instance;
4329 break;
4330 case nir_intrinsic_load_draw_id:
4331 result = ctx->abi->draw_id;
4332 break;
4333 case nir_intrinsic_load_view_index:
4334 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4335 break;
4336 case nir_intrinsic_load_invocation_id:
4337 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4338 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4339 else
4340 result = ctx->abi->gs_invocation_id;
4341 break;
4342 case nir_intrinsic_load_primitive_id:
4343 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4344 result = ctx->abi->gs_prim_id;
4345 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4346 result = ctx->abi->tcs_patch_id;
4347 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4348 result = ctx->abi->tes_patch_id;
4349 } else
4350 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4351 break;
4352 case nir_intrinsic_load_sample_id:
4353 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4354 break;
4355 case nir_intrinsic_load_sample_pos:
4356 result = load_sample_pos(ctx);
4357 break;
4358 case nir_intrinsic_load_sample_mask_in:
4359 if (ctx->nctx)
4360 result = load_sample_mask_in(ctx);
4361 else
4362 result = ctx->abi->sample_coverage;
4363 break;
4364 case nir_intrinsic_load_frag_coord: {
4365 LLVMValueRef values[4] = {
4366 ctx->abi->frag_pos[0],
4367 ctx->abi->frag_pos[1],
4368 ctx->abi->frag_pos[2],
4369 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4370 };
4371 result = ac_build_gather_values(&ctx->ac, values, 4);
4372 break;
4373 }
4374 case nir_intrinsic_load_front_face:
4375 result = ctx->abi->front_face;
4376 break;
4377 case nir_intrinsic_load_helper_invocation:
4378 result = visit_load_helper_invocation(ctx);
4379 break;
4380 case nir_intrinsic_load_instance_id:
4381 result = ctx->abi->instance_id;
4382 break;
4383 case nir_intrinsic_load_num_work_groups:
4384 result = ctx->nctx->num_work_groups;
4385 break;
4386 case nir_intrinsic_load_local_invocation_index:
4387 result = visit_load_local_invocation_index(ctx->nctx);
4388 break;
4389 case nir_intrinsic_load_push_constant:
4390 result = visit_load_push_constant(ctx->nctx, instr);
4391 break;
4392 case nir_intrinsic_vulkan_resource_index:
4393 result = visit_vulkan_resource_index(ctx->nctx, instr);
4394 break;
4395 case nir_intrinsic_vulkan_resource_reindex:
4396 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4397 break;
4398 case nir_intrinsic_store_ssbo:
4399 visit_store_ssbo(ctx, instr);
4400 break;
4401 case nir_intrinsic_load_ssbo:
4402 result = visit_load_buffer(ctx, instr);
4403 break;
4404 case nir_intrinsic_ssbo_atomic_add:
4405 case nir_intrinsic_ssbo_atomic_imin:
4406 case nir_intrinsic_ssbo_atomic_umin:
4407 case nir_intrinsic_ssbo_atomic_imax:
4408 case nir_intrinsic_ssbo_atomic_umax:
4409 case nir_intrinsic_ssbo_atomic_and:
4410 case nir_intrinsic_ssbo_atomic_or:
4411 case nir_intrinsic_ssbo_atomic_xor:
4412 case nir_intrinsic_ssbo_atomic_exchange:
4413 case nir_intrinsic_ssbo_atomic_comp_swap:
4414 result = visit_atomic_ssbo(ctx, instr);
4415 break;
4416 case nir_intrinsic_load_ubo:
4417 result = visit_load_ubo_buffer(ctx, instr);
4418 break;
4419 case nir_intrinsic_get_buffer_size:
4420 result = visit_get_buffer_size(ctx, instr);
4421 break;
4422 case nir_intrinsic_load_var:
4423 result = visit_load_var(ctx, instr);
4424 break;
4425 case nir_intrinsic_store_var:
4426 visit_store_var(ctx, instr);
4427 break;
4428 case nir_intrinsic_image_load:
4429 result = visit_image_load(ctx, instr);
4430 break;
4431 case nir_intrinsic_image_store:
4432 visit_image_store(ctx, instr);
4433 break;
4434 case nir_intrinsic_image_atomic_add:
4435 case nir_intrinsic_image_atomic_min:
4436 case nir_intrinsic_image_atomic_max:
4437 case nir_intrinsic_image_atomic_and:
4438 case nir_intrinsic_image_atomic_or:
4439 case nir_intrinsic_image_atomic_xor:
4440 case nir_intrinsic_image_atomic_exchange:
4441 case nir_intrinsic_image_atomic_comp_swap:
4442 result = visit_image_atomic(ctx, instr);
4443 break;
4444 case nir_intrinsic_image_size:
4445 result = visit_image_size(ctx, instr);
4446 break;
4447 case nir_intrinsic_discard:
4448 case nir_intrinsic_discard_if:
4449 emit_discard(ctx, instr);
4450 break;
4451 case nir_intrinsic_memory_barrier:
4452 case nir_intrinsic_group_memory_barrier:
4453 case nir_intrinsic_memory_barrier_atomic_counter:
4454 case nir_intrinsic_memory_barrier_buffer:
4455 case nir_intrinsic_memory_barrier_image:
4456 case nir_intrinsic_memory_barrier_shared:
4457 emit_membar(ctx->nctx, instr);
4458 break;
4459 case nir_intrinsic_barrier:
4460 emit_barrier(&ctx->ac, ctx->stage);
4461 break;
4462 case nir_intrinsic_var_atomic_add:
4463 case nir_intrinsic_var_atomic_imin:
4464 case nir_intrinsic_var_atomic_umin:
4465 case nir_intrinsic_var_atomic_imax:
4466 case nir_intrinsic_var_atomic_umax:
4467 case nir_intrinsic_var_atomic_and:
4468 case nir_intrinsic_var_atomic_or:
4469 case nir_intrinsic_var_atomic_xor:
4470 case nir_intrinsic_var_atomic_exchange:
4471 case nir_intrinsic_var_atomic_comp_swap:
4472 result = visit_var_atomic(ctx->nctx, instr);
4473 break;
4474 case nir_intrinsic_interp_var_at_centroid:
4475 case nir_intrinsic_interp_var_at_sample:
4476 case nir_intrinsic_interp_var_at_offset:
4477 result = visit_interp(ctx->nctx, instr);
4478 break;
4479 case nir_intrinsic_emit_vertex:
4480 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->outputs);
4481 break;
4482 case nir_intrinsic_end_primitive:
4483 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4484 break;
4485 case nir_intrinsic_load_tess_coord: {
4486 LLVMTypeRef type = ctx->nctx ?
4487 get_def_type(ctx->nctx->nir, &instr->dest.ssa) :
4488 NULL;
4489 result = ctx->abi->load_tess_coord(ctx->abi, type, instr->num_components);
4490 break;
4491 }
4492 case nir_intrinsic_load_tess_level_outer:
4493 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4494 break;
4495 case nir_intrinsic_load_tess_level_inner:
4496 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4497 break;
4498 case nir_intrinsic_load_patch_vertices_in:
4499 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4500 break;
4501 case nir_intrinsic_vote_all: {
4502 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4503 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4504 break;
4505 }
4506 case nir_intrinsic_vote_any: {
4507 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4508 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4509 break;
4510 }
4511 case nir_intrinsic_vote_eq: {
4512 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4513 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4514 break;
4515 }
4516 default:
4517 fprintf(stderr, "Unknown intrinsic: ");
4518 nir_print_instr(&instr->instr, stderr);
4519 fprintf(stderr, "\n");
4520 break;
4521 }
4522 if (result) {
4523 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4524 }
4525 }
4526
4527 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4528 LLVMValueRef buffer_ptr, bool write)
4529 {
4530 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4531 LLVMValueRef result;
4532
4533 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4534
4535 result = LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4536 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4537
4538 return result;
4539 }
4540
4541 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4542 {
4543 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4544 LLVMValueRef result;
4545
4546 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4547
4548 result = LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4549 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4550
4551 return result;
4552 }
4553
4554 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4555 unsigned descriptor_set,
4556 unsigned base_index,
4557 unsigned constant_index,
4558 LLVMValueRef index,
4559 enum ac_descriptor_type desc_type,
4560 bool image, bool write)
4561 {
4562 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4563 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4564 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4565 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4566 unsigned offset = binding->offset;
4567 unsigned stride = binding->size;
4568 unsigned type_size;
4569 LLVMBuilderRef builder = ctx->builder;
4570 LLVMTypeRef type;
4571
4572 assert(base_index < layout->binding_count);
4573
4574 switch (desc_type) {
4575 case AC_DESC_IMAGE:
4576 type = ctx->ac.v8i32;
4577 type_size = 32;
4578 break;
4579 case AC_DESC_FMASK:
4580 type = ctx->ac.v8i32;
4581 offset += 32;
4582 type_size = 32;
4583 break;
4584 case AC_DESC_SAMPLER:
4585 type = ctx->ac.v4i32;
4586 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4587 offset += 64;
4588
4589 type_size = 16;
4590 break;
4591 case AC_DESC_BUFFER:
4592 type = ctx->ac.v4i32;
4593 type_size = 16;
4594 break;
4595 default:
4596 unreachable("invalid desc_type\n");
4597 }
4598
4599 offset += constant_index * stride;
4600
4601 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4602 (!index || binding->immutable_samplers_equal)) {
4603 if (binding->immutable_samplers_equal)
4604 constant_index = 0;
4605
4606 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4607
4608 LLVMValueRef constants[] = {
4609 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4610 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4611 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4612 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4613 };
4614 return ac_build_gather_values(&ctx->ac, constants, 4);
4615 }
4616
4617 assert(stride % type_size == 0);
4618
4619 if (!index)
4620 index = ctx->ac.i32_0;
4621
4622 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4623
4624 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4625 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4626
4627 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4628 }
4629
4630 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4631 const nir_deref_var *deref,
4632 enum ac_descriptor_type desc_type,
4633 const nir_tex_instr *tex_instr,
4634 bool image, bool write)
4635 {
4636 LLVMValueRef index = NULL;
4637 unsigned constant_index = 0;
4638 unsigned descriptor_set;
4639 unsigned base_index;
4640
4641 if (!deref) {
4642 assert(tex_instr && !image);
4643 descriptor_set = 0;
4644 base_index = tex_instr->sampler_index;
4645 } else {
4646 const nir_deref *tail = &deref->deref;
4647 while (tail->child) {
4648 const nir_deref_array *child = nir_deref_as_array(tail->child);
4649 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4650
4651 if (!array_size)
4652 array_size = 1;
4653
4654 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4655
4656 if (child->deref_array_type == nir_deref_array_type_indirect) {
4657 LLVMValueRef indirect = get_src(ctx, child->indirect);
4658
4659 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4660 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4661
4662 if (!index)
4663 index = indirect;
4664 else
4665 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4666 }
4667
4668 constant_index += child->base_offset * array_size;
4669
4670 tail = &child->deref;
4671 }
4672 descriptor_set = deref->var->data.descriptor_set;
4673 base_index = deref->var->data.binding;
4674 }
4675
4676 return ctx->abi->load_sampler_desc(ctx->abi,
4677 descriptor_set,
4678 base_index,
4679 constant_index, index,
4680 desc_type, image, write);
4681 }
4682
4683 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4684 struct ac_image_args *args,
4685 const nir_tex_instr *instr,
4686 nir_texop op,
4687 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4688 LLVMValueRef *param, unsigned count,
4689 unsigned dmask)
4690 {
4691 unsigned is_rect = 0;
4692 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4693
4694 if (op == nir_texop_lod)
4695 da = false;
4696 /* Pad to power of two vector */
4697 while (count < util_next_power_of_two(count))
4698 param[count++] = LLVMGetUndef(ctx->i32);
4699
4700 if (count > 1)
4701 args->addr = ac_build_gather_values(ctx, param, count);
4702 else
4703 args->addr = param[0];
4704
4705 args->resource = res_ptr;
4706 args->sampler = samp_ptr;
4707
4708 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4709 args->addr = param[0];
4710 return;
4711 }
4712
4713 args->dmask = dmask;
4714 args->unorm = is_rect;
4715 args->da = da;
4716 }
4717
4718 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4719 *
4720 * SI-CI:
4721 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4722 * filtering manually. The driver sets img7 to a mask clearing
4723 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4724 * s_and_b32 samp0, samp0, img7
4725 *
4726 * VI:
4727 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4728 */
4729 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4730 LLVMValueRef res, LLVMValueRef samp)
4731 {
4732 LLVMBuilderRef builder = ctx->ac.builder;
4733 LLVMValueRef img7, samp0;
4734
4735 if (ctx->ac.chip_class >= VI)
4736 return samp;
4737
4738 img7 = LLVMBuildExtractElement(builder, res,
4739 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4740 samp0 = LLVMBuildExtractElement(builder, samp,
4741 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4742 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4743 return LLVMBuildInsertElement(builder, samp, samp0,
4744 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4745 }
4746
4747 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4748 nir_tex_instr *instr,
4749 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4750 LLVMValueRef *fmask_ptr)
4751 {
4752 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4753 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4754 else
4755 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4756 if (samp_ptr) {
4757 if (instr->sampler)
4758 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4759 else
4760 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4761 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4762 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4763 }
4764 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4765 instr->op == nir_texop_samples_identical))
4766 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4767 }
4768
4769 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4770 LLVMValueRef coord)
4771 {
4772 coord = ac_to_float(ctx, coord);
4773 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4774 coord = ac_to_integer(ctx, coord);
4775 return coord;
4776 }
4777
4778 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4779 {
4780 LLVMValueRef result = NULL;
4781 struct ac_image_args args = { 0 };
4782 unsigned dmask = 0xf;
4783 LLVMValueRef address[16];
4784 LLVMValueRef coords[5];
4785 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4786 LLVMValueRef bias = NULL, offsets = NULL;
4787 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4788 LLVMValueRef ddx = NULL, ddy = NULL;
4789 LLVMValueRef derivs[6];
4790 unsigned chan, count = 0;
4791 unsigned const_src = 0, num_deriv_comp = 0;
4792 bool lod_is_zero = false;
4793
4794 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4795
4796 for (unsigned i = 0; i < instr->num_srcs; i++) {
4797 switch (instr->src[i].src_type) {
4798 case nir_tex_src_coord:
4799 coord = get_src(ctx, instr->src[i].src);
4800 break;
4801 case nir_tex_src_projector:
4802 break;
4803 case nir_tex_src_comparator:
4804 comparator = get_src(ctx, instr->src[i].src);
4805 break;
4806 case nir_tex_src_offset:
4807 offsets = get_src(ctx, instr->src[i].src);
4808 const_src = i;
4809 break;
4810 case nir_tex_src_bias:
4811 bias = get_src(ctx, instr->src[i].src);
4812 break;
4813 case nir_tex_src_lod: {
4814 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4815
4816 if (val && val->i32[0] == 0)
4817 lod_is_zero = true;
4818 lod = get_src(ctx, instr->src[i].src);
4819 break;
4820 }
4821 case nir_tex_src_ms_index:
4822 sample_index = get_src(ctx, instr->src[i].src);
4823 break;
4824 case nir_tex_src_ms_mcs:
4825 break;
4826 case nir_tex_src_ddx:
4827 ddx = get_src(ctx, instr->src[i].src);
4828 num_deriv_comp = instr->src[i].src.ssa->num_components;
4829 break;
4830 case nir_tex_src_ddy:
4831 ddy = get_src(ctx, instr->src[i].src);
4832 break;
4833 case nir_tex_src_texture_offset:
4834 case nir_tex_src_sampler_offset:
4835 case nir_tex_src_plane:
4836 default:
4837 break;
4838 }
4839 }
4840
4841 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4842 result = get_buffer_size(ctx, res_ptr, true);
4843 goto write_result;
4844 }
4845
4846 if (instr->op == nir_texop_texture_samples) {
4847 LLVMValueRef res, samples, is_msaa;
4848 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4849 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4850 LLVMConstInt(ctx->ac.i32, 3, false), "");
4851 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4852 LLVMConstInt(ctx->ac.i32, 28, false), "");
4853 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4854 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4855 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4856 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4857
4858 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4859 LLVMConstInt(ctx->ac.i32, 16, false), "");
4860 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4861 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4862 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4863 samples, "");
4864 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4865 ctx->ac.i32_1, "");
4866 result = samples;
4867 goto write_result;
4868 }
4869
4870 if (coord)
4871 for (chan = 0; chan < instr->coord_components; chan++)
4872 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4873
4874 if (offsets && instr->op != nir_texop_txf) {
4875 LLVMValueRef offset[3], pack;
4876 for (chan = 0; chan < 3; ++chan)
4877 offset[chan] = ctx->ac.i32_0;
4878
4879 args.offset = true;
4880 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4881 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4882 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4883 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4884 if (chan)
4885 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4886 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4887 }
4888 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4889 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4890 address[count++] = pack;
4891
4892 }
4893 /* pack LOD bias value */
4894 if (instr->op == nir_texop_txb && bias) {
4895 address[count++] = bias;
4896 }
4897
4898 /* Pack depth comparison value */
4899 if (instr->is_shadow && comparator) {
4900 LLVMValueRef z = ac_to_float(&ctx->ac,
4901 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4902
4903 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4904 * so the depth comparison value isn't clamped for Z16 and
4905 * Z24 anymore. Do it manually here.
4906 *
4907 * It's unnecessary if the original texture format was
4908 * Z32_FLOAT, but we don't know that here.
4909 */
4910 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4911 z = ac_build_clamp(&ctx->ac, z);
4912
4913 address[count++] = z;
4914 }
4915
4916 /* pack derivatives */
4917 if (ddx || ddy) {
4918 int num_src_deriv_channels, num_dest_deriv_channels;
4919 switch (instr->sampler_dim) {
4920 case GLSL_SAMPLER_DIM_3D:
4921 case GLSL_SAMPLER_DIM_CUBE:
4922 num_deriv_comp = 3;
4923 num_src_deriv_channels = 3;
4924 num_dest_deriv_channels = 3;
4925 break;
4926 case GLSL_SAMPLER_DIM_2D:
4927 default:
4928 num_src_deriv_channels = 2;
4929 num_dest_deriv_channels = 2;
4930 num_deriv_comp = 2;
4931 break;
4932 case GLSL_SAMPLER_DIM_1D:
4933 num_src_deriv_channels = 1;
4934 if (ctx->ac.chip_class >= GFX9) {
4935 num_dest_deriv_channels = 2;
4936 num_deriv_comp = 2;
4937 } else {
4938 num_dest_deriv_channels = 1;
4939 num_deriv_comp = 1;
4940 }
4941 break;
4942 }
4943
4944 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4945 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4946 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4947 }
4948 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4949 derivs[i] = ctx->ac.f32_0;
4950 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4951 }
4952 }
4953
4954 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4955 for (chan = 0; chan < instr->coord_components; chan++)
4956 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4957 if (instr->coord_components == 3)
4958 coords[3] = LLVMGetUndef(ctx->ac.f32);
4959 ac_prepare_cube_coords(&ctx->ac,
4960 instr->op == nir_texop_txd, instr->is_array,
4961 instr->op == nir_texop_lod, coords, derivs);
4962 if (num_deriv_comp)
4963 num_deriv_comp--;
4964 }
4965
4966 if (ddx || ddy) {
4967 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4968 address[count++] = derivs[i];
4969 }
4970
4971 /* Pack texture coordinates */
4972 if (coord) {
4973 address[count++] = coords[0];
4974 if (instr->coord_components > 1) {
4975 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4976 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4977 }
4978 address[count++] = coords[1];
4979 }
4980 if (instr->coord_components > 2) {
4981 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4982 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4983 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4984 instr->op != nir_texop_txf) {
4985 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4986 }
4987 address[count++] = coords[2];
4988 }
4989
4990 if (ctx->ac.chip_class >= GFX9) {
4991 LLVMValueRef filler;
4992 if (instr->op == nir_texop_txf)
4993 filler = ctx->ac.i32_0;
4994 else
4995 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4996
4997 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4998 /* No nir_texop_lod, because it does not take a slice
4999 * even with array textures. */
5000 if (instr->is_array && instr->op != nir_texop_lod ) {
5001 address[count] = address[count - 1];
5002 address[count - 1] = filler;
5003 count++;
5004 } else
5005 address[count++] = filler;
5006 }
5007 }
5008 }
5009
5010 /* Pack LOD */
5011 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5012 instr->op == nir_texop_txf)) {
5013 address[count++] = lod;
5014 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5015 address[count++] = sample_index;
5016 } else if(instr->op == nir_texop_txs) {
5017 count = 0;
5018 if (lod)
5019 address[count++] = lod;
5020 else
5021 address[count++] = ctx->ac.i32_0;
5022 }
5023
5024 for (chan = 0; chan < count; chan++) {
5025 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5026 address[chan], ctx->ac.i32, "");
5027 }
5028
5029 if (instr->op == nir_texop_samples_identical) {
5030 LLVMValueRef txf_address[4];
5031 struct ac_image_args txf_args = { 0 };
5032 unsigned txf_count = count;
5033 memcpy(txf_address, address, sizeof(txf_address));
5034
5035 if (!instr->is_array)
5036 txf_address[2] = ctx->ac.i32_0;
5037 txf_address[3] = ctx->ac.i32_0;
5038
5039 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5040 fmask_ptr, NULL,
5041 txf_address, txf_count, 0xf);
5042
5043 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5044
5045 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5046 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5047 goto write_result;
5048 }
5049
5050 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5051 instr->op != nir_texop_txs) {
5052 unsigned sample_chan = instr->is_array ? 3 : 2;
5053 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5054 address[0],
5055 address[1],
5056 instr->is_array ? address[2] : NULL,
5057 address[sample_chan],
5058 fmask_ptr);
5059 }
5060
5061 if (offsets && instr->op == nir_texop_txf) {
5062 nir_const_value *const_offset =
5063 nir_src_as_const_value(instr->src[const_src].src);
5064 int num_offsets = instr->src[const_src].src.ssa->num_components;
5065 assert(const_offset);
5066 num_offsets = MIN2(num_offsets, instr->coord_components);
5067 if (num_offsets > 2)
5068 address[2] = LLVMBuildAdd(ctx->ac.builder,
5069 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5070 if (num_offsets > 1)
5071 address[1] = LLVMBuildAdd(ctx->ac.builder,
5072 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5073 address[0] = LLVMBuildAdd(ctx->ac.builder,
5074 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5075
5076 }
5077
5078 /* TODO TG4 support */
5079 if (instr->op == nir_texop_tg4) {
5080 if (instr->is_shadow)
5081 dmask = 1;
5082 else
5083 dmask = 1 << instr->component;
5084 }
5085 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5086 res_ptr, samp_ptr, address, count, dmask);
5087
5088 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5089
5090 if (instr->op == nir_texop_query_levels)
5091 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5092 else if (instr->is_shadow && instr->is_new_style_shadow &&
5093 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5094 instr->op != nir_texop_tg4)
5095 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5096 else if (instr->op == nir_texop_txs &&
5097 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5098 instr->is_array) {
5099 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5100 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5101 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5102 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5103 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5104 } else if (ctx->ac.chip_class >= GFX9 &&
5105 instr->op == nir_texop_txs &&
5106 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5107 instr->is_array) {
5108 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5109 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5110 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5111 ctx->ac.i32_1, "");
5112 } else if (instr->dest.ssa.num_components != 4)
5113 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5114
5115 write_result:
5116 if (result) {
5117 assert(instr->dest.is_ssa);
5118 result = ac_to_integer(&ctx->ac, result);
5119 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5120 }
5121 }
5122
5123
5124 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5125 {
5126 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5127 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5128
5129 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5130 _mesa_hash_table_insert(ctx->phis, instr, result);
5131 }
5132
5133 static void visit_post_phi(struct ac_nir_context *ctx,
5134 nir_phi_instr *instr,
5135 LLVMValueRef llvm_phi)
5136 {
5137 nir_foreach_phi_src(src, instr) {
5138 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5139 LLVMValueRef llvm_src = get_src(ctx, src->src);
5140
5141 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5142 }
5143 }
5144
5145 static void phi_post_pass(struct ac_nir_context *ctx)
5146 {
5147 struct hash_entry *entry;
5148 hash_table_foreach(ctx->phis, entry) {
5149 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5150 (LLVMValueRef)entry->data);
5151 }
5152 }
5153
5154
5155 static void visit_ssa_undef(struct ac_nir_context *ctx,
5156 const nir_ssa_undef_instr *instr)
5157 {
5158 unsigned num_components = instr->def.num_components;
5159 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5160 LLVMValueRef undef;
5161
5162 if (num_components == 1)
5163 undef = LLVMGetUndef(type);
5164 else {
5165 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5166 }
5167 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5168 }
5169
5170 static void visit_jump(struct ac_nir_context *ctx,
5171 const nir_jump_instr *instr)
5172 {
5173 switch (instr->type) {
5174 case nir_jump_break:
5175 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5176 LLVMClearInsertionPosition(ctx->ac.builder);
5177 break;
5178 case nir_jump_continue:
5179 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5180 LLVMClearInsertionPosition(ctx->ac.builder);
5181 break;
5182 default:
5183 fprintf(stderr, "Unknown NIR jump instr: ");
5184 nir_print_instr(&instr->instr, stderr);
5185 fprintf(stderr, "\n");
5186 abort();
5187 }
5188 }
5189
5190 static void visit_cf_list(struct ac_nir_context *ctx,
5191 struct exec_list *list);
5192
5193 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5194 {
5195 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5196 nir_foreach_instr(instr, block)
5197 {
5198 switch (instr->type) {
5199 case nir_instr_type_alu:
5200 visit_alu(ctx, nir_instr_as_alu(instr));
5201 break;
5202 case nir_instr_type_load_const:
5203 visit_load_const(ctx, nir_instr_as_load_const(instr));
5204 break;
5205 case nir_instr_type_intrinsic:
5206 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5207 break;
5208 case nir_instr_type_tex:
5209 visit_tex(ctx, nir_instr_as_tex(instr));
5210 break;
5211 case nir_instr_type_phi:
5212 visit_phi(ctx, nir_instr_as_phi(instr));
5213 break;
5214 case nir_instr_type_ssa_undef:
5215 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5216 break;
5217 case nir_instr_type_jump:
5218 visit_jump(ctx, nir_instr_as_jump(instr));
5219 break;
5220 default:
5221 fprintf(stderr, "Unknown NIR instr type: ");
5222 nir_print_instr(instr, stderr);
5223 fprintf(stderr, "\n");
5224 abort();
5225 }
5226 }
5227
5228 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5229 }
5230
5231 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5232 {
5233 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5234
5235 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5236 LLVMBasicBlockRef merge_block =
5237 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5238 LLVMBasicBlockRef if_block =
5239 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5240 LLVMBasicBlockRef else_block = merge_block;
5241 if (!exec_list_is_empty(&if_stmt->else_list))
5242 else_block = LLVMAppendBasicBlockInContext(
5243 ctx->ac.context, fn, "");
5244
5245 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5246 ctx->ac.i32_0, "");
5247 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5248
5249 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5250 visit_cf_list(ctx, &if_stmt->then_list);
5251 if (LLVMGetInsertBlock(ctx->ac.builder))
5252 LLVMBuildBr(ctx->ac.builder, merge_block);
5253
5254 if (!exec_list_is_empty(&if_stmt->else_list)) {
5255 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5256 visit_cf_list(ctx, &if_stmt->else_list);
5257 if (LLVMGetInsertBlock(ctx->ac.builder))
5258 LLVMBuildBr(ctx->ac.builder, merge_block);
5259 }
5260
5261 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5262 }
5263
5264 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5265 {
5266 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5267 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5268 LLVMBasicBlockRef break_parent = ctx->break_block;
5269
5270 ctx->continue_block =
5271 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5272 ctx->break_block =
5273 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5274
5275 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5276 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5277 visit_cf_list(ctx, &loop->body);
5278
5279 if (LLVMGetInsertBlock(ctx->ac.builder))
5280 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5281 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5282
5283 ctx->continue_block = continue_parent;
5284 ctx->break_block = break_parent;
5285 }
5286
5287 static void visit_cf_list(struct ac_nir_context *ctx,
5288 struct exec_list *list)
5289 {
5290 foreach_list_typed(nir_cf_node, node, node, list)
5291 {
5292 switch (node->type) {
5293 case nir_cf_node_block:
5294 visit_block(ctx, nir_cf_node_as_block(node));
5295 break;
5296
5297 case nir_cf_node_if:
5298 visit_if(ctx, nir_cf_node_as_if(node));
5299 break;
5300
5301 case nir_cf_node_loop:
5302 visit_loop(ctx, nir_cf_node_as_loop(node));
5303 break;
5304
5305 default:
5306 assert(0);
5307 }
5308 }
5309 }
5310
5311 static void
5312 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5313 struct nir_variable *variable)
5314 {
5315 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5316 LLVMValueRef t_offset;
5317 LLVMValueRef t_list;
5318 LLVMValueRef input;
5319 LLVMValueRef buffer_index;
5320 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5321 int idx = variable->data.location;
5322 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5323
5324 variable->data.driver_location = idx * 4;
5325
5326 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5327 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5328 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5329 ctx->abi.start_instance, "");
5330 if (ctx->options->key.vs.as_ls) {
5331 ctx->shader_info->vs.vgpr_comp_cnt =
5332 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5333 } else {
5334 ctx->shader_info->vs.vgpr_comp_cnt =
5335 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5336 }
5337 } else
5338 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5339 ctx->abi.base_vertex, "");
5340 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5341
5342 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5343
5344 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5345 buffer_index,
5346 ctx->ac.i32_0,
5347 4, true);
5348
5349 for (unsigned chan = 0; chan < 4; chan++) {
5350 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5351 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5352 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5353 input, llvm_chan, ""));
5354 }
5355 }
5356 }
5357
5358 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5359 unsigned attr,
5360 LLVMValueRef interp_param,
5361 LLVMValueRef prim_mask,
5362 LLVMValueRef result[4])
5363 {
5364 LLVMValueRef attr_number;
5365 unsigned chan;
5366 LLVMValueRef i, j;
5367 bool interp = interp_param != NULL;
5368
5369 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5370
5371 /* fs.constant returns the param from the middle vertex, so it's not
5372 * really useful for flat shading. It's meant to be used for custom
5373 * interpolation (but the intrinsic can't fetch from the other two
5374 * vertices).
5375 *
5376 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5377 * to do the right thing. The only reason we use fs.constant is that
5378 * fs.interp cannot be used on integers, because they can be equal
5379 * to NaN.
5380 */
5381 if (interp) {
5382 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5383 ctx->ac.v2f32, "");
5384
5385 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5386 ctx->ac.i32_0, "");
5387 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5388 ctx->ac.i32_1, "");
5389 }
5390
5391 for (chan = 0; chan < 4; chan++) {
5392 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5393
5394 if (interp) {
5395 result[chan] = ac_build_fs_interp(&ctx->ac,
5396 llvm_chan,
5397 attr_number,
5398 prim_mask, i, j);
5399 } else {
5400 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5401 LLVMConstInt(ctx->ac.i32, 2, false),
5402 llvm_chan,
5403 attr_number,
5404 prim_mask);
5405 }
5406 }
5407 }
5408
5409 static void
5410 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5411 struct nir_variable *variable)
5412 {
5413 int idx = variable->data.location;
5414 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5415 LLVMValueRef interp;
5416
5417 variable->data.driver_location = idx * 4;
5418 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5419
5420 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5421 unsigned interp_type;
5422 if (variable->data.sample) {
5423 interp_type = INTERP_SAMPLE;
5424 ctx->shader_info->info.ps.force_persample = true;
5425 } else if (variable->data.centroid)
5426 interp_type = INTERP_CENTROID;
5427 else
5428 interp_type = INTERP_CENTER;
5429
5430 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5431 } else
5432 interp = NULL;
5433
5434 for (unsigned i = 0; i < attrib_count; ++i)
5435 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5436
5437 }
5438
5439 static void
5440 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5441 struct nir_shader *nir) {
5442 nir_foreach_variable(variable, &nir->inputs)
5443 handle_vs_input_decl(ctx, variable);
5444 }
5445
5446 static void
5447 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5448 struct nir_shader *nir)
5449 {
5450 if (!ctx->options->key.fs.multisample)
5451 return;
5452
5453 bool uses_center = false;
5454 bool uses_centroid = false;
5455 nir_foreach_variable(variable, &nir->inputs) {
5456 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5457 variable->data.sample)
5458 continue;
5459
5460 if (variable->data.centroid)
5461 uses_centroid = true;
5462 else
5463 uses_center = true;
5464 }
5465
5466 if (uses_center && uses_centroid) {
5467 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5468 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5469 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5470 }
5471 }
5472
5473 static void
5474 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5475 struct nir_shader *nir)
5476 {
5477 prepare_interp_optimize(ctx, nir);
5478
5479 nir_foreach_variable(variable, &nir->inputs)
5480 handle_fs_input_decl(ctx, variable);
5481
5482 unsigned index = 0;
5483
5484 if (ctx->shader_info->info.ps.uses_input_attachments ||
5485 ctx->shader_info->info.needs_multiview_view_index)
5486 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5487
5488 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5489 LLVMValueRef interp_param;
5490 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5491
5492 if (!(ctx->input_mask & (1ull << i)))
5493 continue;
5494
5495 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5496 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5497 interp_param = *inputs;
5498 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5499 inputs);
5500
5501 if (!interp_param)
5502 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5503 ++index;
5504 } else if (i == VARYING_SLOT_POS) {
5505 for(int i = 0; i < 3; ++i)
5506 inputs[i] = ctx->abi.frag_pos[i];
5507
5508 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5509 ctx->abi.frag_pos[3]);
5510 }
5511 }
5512 ctx->shader_info->fs.num_interp = index;
5513 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5514 ctx->shader_info->fs.has_pcoord = true;
5515 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5516 ctx->shader_info->fs.prim_id_input = true;
5517 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5518 ctx->shader_info->fs.layer_input = true;
5519 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5520
5521 if (ctx->shader_info->info.needs_multiview_view_index)
5522 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5523 }
5524
5525 static LLVMValueRef
5526 ac_build_alloca(struct ac_llvm_context *ac,
5527 LLVMTypeRef type,
5528 const char *name)
5529 {
5530 LLVMBuilderRef builder = ac->builder;
5531 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5532 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5533 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5534 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5535 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5536 LLVMValueRef res;
5537
5538 if (first_instr) {
5539 LLVMPositionBuilderBefore(first_builder, first_instr);
5540 } else {
5541 LLVMPositionBuilderAtEnd(first_builder, first_block);
5542 }
5543
5544 res = LLVMBuildAlloca(first_builder, type, name);
5545 LLVMBuildStore(builder, LLVMConstNull(type), res);
5546
5547 LLVMDisposeBuilder(first_builder);
5548
5549 return res;
5550 }
5551
5552 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5553 LLVMTypeRef type,
5554 const char *name)
5555 {
5556 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5557 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5558 return ptr;
5559 }
5560
5561 static void
5562 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5563 struct nir_variable *variable,
5564 struct nir_shader *shader,
5565 gl_shader_stage stage)
5566 {
5567 int idx = variable->data.location + variable->data.index;
5568 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5569 uint64_t mask_attribs;
5570
5571 variable->data.driver_location = idx * 4;
5572
5573 /* tess ctrl has it's own load/store paths for outputs */
5574 if (stage == MESA_SHADER_TESS_CTRL)
5575 return;
5576
5577 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5578 if (stage == MESA_SHADER_VERTEX ||
5579 stage == MESA_SHADER_TESS_EVAL ||
5580 stage == MESA_SHADER_GEOMETRY) {
5581 if (idx == VARYING_SLOT_CLIP_DIST0) {
5582 int length = shader->info.clip_distance_array_size +
5583 shader->info.cull_distance_array_size;
5584 if (stage == MESA_SHADER_VERTEX) {
5585 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5586 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5587 }
5588 if (stage == MESA_SHADER_TESS_EVAL) {
5589 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5590 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5591 }
5592
5593 if (length > 4)
5594 attrib_count = 2;
5595 else
5596 attrib_count = 1;
5597 mask_attribs = 1ull << idx;
5598 }
5599 }
5600
5601 ctx->output_mask |= mask_attribs;
5602 }
5603
5604 static void
5605 handle_shader_output_decl(struct ac_nir_context *ctx,
5606 struct nir_shader *nir,
5607 struct nir_variable *variable)
5608 {
5609 unsigned output_loc = variable->data.driver_location / 4;
5610 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5611
5612 /* tess ctrl has it's own load/store paths for outputs */
5613 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5614 return;
5615
5616 if (ctx->stage == MESA_SHADER_VERTEX ||
5617 ctx->stage == MESA_SHADER_TESS_EVAL ||
5618 ctx->stage == MESA_SHADER_GEOMETRY) {
5619 int idx = variable->data.location + variable->data.index;
5620 if (idx == VARYING_SLOT_CLIP_DIST0) {
5621 int length = nir->info.clip_distance_array_size +
5622 nir->info.cull_distance_array_size;
5623
5624 if (length > 4)
5625 attrib_count = 2;
5626 else
5627 attrib_count = 1;
5628 }
5629 }
5630
5631 for (unsigned i = 0; i < attrib_count; ++i) {
5632 for (unsigned chan = 0; chan < 4; chan++) {
5633 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5634 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5635 }
5636 }
5637 }
5638
5639 static LLVMTypeRef
5640 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5641 enum glsl_base_type type)
5642 {
5643 switch (type) {
5644 case GLSL_TYPE_INT:
5645 case GLSL_TYPE_UINT:
5646 case GLSL_TYPE_BOOL:
5647 case GLSL_TYPE_SUBROUTINE:
5648 return ctx->ac.i32;
5649 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5650 return ctx->ac.f32;
5651 case GLSL_TYPE_INT64:
5652 case GLSL_TYPE_UINT64:
5653 return ctx->ac.i64;
5654 case GLSL_TYPE_DOUBLE:
5655 return ctx->ac.f64;
5656 default:
5657 unreachable("unknown GLSL type");
5658 }
5659 }
5660
5661 static LLVMTypeRef
5662 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5663 const struct glsl_type *type)
5664 {
5665 if (glsl_type_is_scalar(type)) {
5666 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5667 }
5668
5669 if (glsl_type_is_vector(type)) {
5670 return LLVMVectorType(
5671 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5672 glsl_get_vector_elements(type));
5673 }
5674
5675 if (glsl_type_is_matrix(type)) {
5676 return LLVMArrayType(
5677 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5678 glsl_get_matrix_columns(type));
5679 }
5680
5681 if (glsl_type_is_array(type)) {
5682 return LLVMArrayType(
5683 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5684 glsl_get_length(type));
5685 }
5686
5687 assert(glsl_type_is_struct(type));
5688
5689 LLVMTypeRef member_types[glsl_get_length(type)];
5690
5691 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5692 member_types[i] =
5693 glsl_to_llvm_type(ctx,
5694 glsl_get_struct_field(type, i));
5695 }
5696
5697 return LLVMStructTypeInContext(ctx->context, member_types,
5698 glsl_get_length(type), false);
5699 }
5700
5701 static void
5702 setup_locals(struct ac_nir_context *ctx,
5703 struct nir_function *func)
5704 {
5705 int i, j;
5706 ctx->num_locals = 0;
5707 nir_foreach_variable(variable, &func->impl->locals) {
5708 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5709 variable->data.driver_location = ctx->num_locals * 4;
5710 variable->data.location_frac = 0;
5711 ctx->num_locals += attrib_count;
5712 }
5713 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5714 if (!ctx->locals)
5715 return;
5716
5717 for (i = 0; i < ctx->num_locals; i++) {
5718 for (j = 0; j < 4; j++) {
5719 ctx->locals[i * 4 + j] =
5720 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5721 }
5722 }
5723 }
5724
5725 static void
5726 setup_shared(struct ac_nir_context *ctx,
5727 struct nir_shader *nir)
5728 {
5729 nir_foreach_variable(variable, &nir->shared) {
5730 LLVMValueRef shared =
5731 LLVMAddGlobalInAddressSpace(
5732 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5733 variable->name ? variable->name : "",
5734 AC_LOCAL_ADDR_SPACE);
5735 _mesa_hash_table_insert(ctx->vars, variable, shared);
5736 }
5737 }
5738
5739 static LLVMValueRef
5740 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5741 {
5742 v = ac_to_float(ctx, v);
5743 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5744 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5745 }
5746
5747
5748 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5749 LLVMValueRef src0, LLVMValueRef src1)
5750 {
5751 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5752 LLVMValueRef comp[2];
5753
5754 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5755 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5756 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5757 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5758 }
5759
5760 /* Initialize arguments for the shader export intrinsic */
5761 static void
5762 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5763 LLVMValueRef *values,
5764 unsigned target,
5765 struct ac_export_args *args)
5766 {
5767 /* Default is 0xf. Adjusted below depending on the format. */
5768 args->enabled_channels = 0xf;
5769
5770 /* Specify whether the EXEC mask represents the valid mask */
5771 args->valid_mask = 0;
5772
5773 /* Specify whether this is the last export */
5774 args->done = 0;
5775
5776 /* Specify the target we are exporting */
5777 args->target = target;
5778
5779 args->compr = false;
5780 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5781 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5782 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5783 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5784
5785 if (!values)
5786 return;
5787
5788 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5789 LLVMValueRef val[4];
5790 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5791 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5792 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5793 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5794
5795 switch(col_format) {
5796 case V_028714_SPI_SHADER_ZERO:
5797 args->enabled_channels = 0; /* writemask */
5798 args->target = V_008DFC_SQ_EXP_NULL;
5799 break;
5800
5801 case V_028714_SPI_SHADER_32_R:
5802 args->enabled_channels = 1;
5803 args->out[0] = values[0];
5804 break;
5805
5806 case V_028714_SPI_SHADER_32_GR:
5807 args->enabled_channels = 0x3;
5808 args->out[0] = values[0];
5809 args->out[1] = values[1];
5810 break;
5811
5812 case V_028714_SPI_SHADER_32_AR:
5813 args->enabled_channels = 0x9;
5814 args->out[0] = values[0];
5815 args->out[3] = values[3];
5816 break;
5817
5818 case V_028714_SPI_SHADER_FP16_ABGR:
5819 args->compr = 1;
5820
5821 for (unsigned chan = 0; chan < 2; chan++) {
5822 LLVMValueRef pack_args[2] = {
5823 values[2 * chan],
5824 values[2 * chan + 1]
5825 };
5826 LLVMValueRef packed;
5827
5828 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5829 args->out[chan] = packed;
5830 }
5831 break;
5832
5833 case V_028714_SPI_SHADER_UNORM16_ABGR:
5834 for (unsigned chan = 0; chan < 4; chan++) {
5835 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5836 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5837 LLVMConstReal(ctx->ac.f32, 65535), "");
5838 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5839 LLVMConstReal(ctx->ac.f32, 0.5), "");
5840 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5841 ctx->ac.i32, "");
5842 }
5843
5844 args->compr = 1;
5845 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5846 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5847 break;
5848
5849 case V_028714_SPI_SHADER_SNORM16_ABGR:
5850 for (unsigned chan = 0; chan < 4; chan++) {
5851 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5852 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5853 LLVMConstReal(ctx->ac.f32, 32767), "");
5854
5855 /* If positive, add 0.5, else add -0.5. */
5856 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5857 LLVMBuildSelect(ctx->builder,
5858 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5859 val[chan], ctx->ac.f32_0, ""),
5860 LLVMConstReal(ctx->ac.f32, 0.5),
5861 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5862 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5863 }
5864
5865 args->compr = 1;
5866 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5867 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5868 break;
5869
5870 case V_028714_SPI_SHADER_UINT16_ABGR: {
5871 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5872 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5873 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5874
5875 for (unsigned chan = 0; chan < 4; chan++) {
5876 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5877 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5878 }
5879
5880 args->compr = 1;
5881 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5882 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5883 break;
5884 }
5885
5886 case V_028714_SPI_SHADER_SINT16_ABGR: {
5887 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5888 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5889 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5890 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5891 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5892 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5893
5894 /* Clamp. */
5895 for (unsigned chan = 0; chan < 4; chan++) {
5896 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5897 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5898 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5899 }
5900
5901 args->compr = 1;
5902 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5903 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5904 break;
5905 }
5906
5907 default:
5908 case V_028714_SPI_SHADER_32_ABGR:
5909 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5910 break;
5911 }
5912 } else
5913 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5914
5915 for (unsigned i = 0; i < 4; ++i)
5916 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5917 }
5918
5919 static void
5920 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5921 bool export_prim_id,
5922 struct ac_vs_output_info *outinfo)
5923 {
5924 uint32_t param_count = 0;
5925 unsigned target;
5926 unsigned pos_idx, num_pos_exports = 0;
5927 struct ac_export_args args, pos_args[4] = {};
5928 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5929 int i;
5930
5931 if (ctx->options->key.has_multiview_view_index) {
5932 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5933 if(!*tmp_out) {
5934 for(unsigned i = 0; i < 4; ++i)
5935 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5936 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5937 }
5938
5939 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5940 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5941 }
5942
5943 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5944 sizeof(outinfo->vs_output_param_offset));
5945
5946 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5947 LLVMValueRef slots[8];
5948 unsigned j;
5949
5950 if (outinfo->cull_dist_mask)
5951 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5952
5953 i = VARYING_SLOT_CLIP_DIST0;
5954 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5955 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5956 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5957
5958 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5959 slots[i] = LLVMGetUndef(ctx->ac.f32);
5960
5961 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5962 target = V_008DFC_SQ_EXP_POS + 3;
5963 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5964 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5965 &args, sizeof(args));
5966 }
5967
5968 target = V_008DFC_SQ_EXP_POS + 2;
5969 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5970 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5971 &args, sizeof(args));
5972
5973 }
5974
5975 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5976 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5977 for (unsigned j = 0; j < 4; j++)
5978 pos_values[j] = LLVMBuildLoad(ctx->builder,
5979 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5980 }
5981 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5982
5983 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5984 outinfo->writes_pointsize = true;
5985 psize_value = LLVMBuildLoad(ctx->builder,
5986 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5987 }
5988
5989 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5990 outinfo->writes_layer = true;
5991 layer_value = LLVMBuildLoad(ctx->builder,
5992 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5993 }
5994
5995 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5996 outinfo->writes_viewport_index = true;
5997 viewport_index_value = LLVMBuildLoad(ctx->builder,
5998 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5999 }
6000
6001 if (outinfo->writes_pointsize ||
6002 outinfo->writes_layer ||
6003 outinfo->writes_viewport_index) {
6004 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
6005 (outinfo->writes_layer == true ? 4 : 0));
6006 pos_args[1].valid_mask = 0;
6007 pos_args[1].done = 0;
6008 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6009 pos_args[1].compr = 0;
6010 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6011 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6012 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6013 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6014
6015 if (outinfo->writes_pointsize == true)
6016 pos_args[1].out[0] = psize_value;
6017 if (outinfo->writes_layer == true)
6018 pos_args[1].out[2] = layer_value;
6019 if (outinfo->writes_viewport_index == true) {
6020 if (ctx->options->chip_class >= GFX9) {
6021 /* GFX9 has the layer in out.z[10:0] and the viewport
6022 * index in out.z[19:16].
6023 */
6024 LLVMValueRef v = viewport_index_value;
6025 v = ac_to_integer(&ctx->ac, v);
6026 v = LLVMBuildShl(ctx->builder, v,
6027 LLVMConstInt(ctx->ac.i32, 16, false),
6028 "");
6029 v = LLVMBuildOr(ctx->builder, v,
6030 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6031
6032 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6033 pos_args[1].enabled_channels |= 1 << 2;
6034 } else {
6035 pos_args[1].out[3] = viewport_index_value;
6036 pos_args[1].enabled_channels |= 1 << 3;
6037 }
6038 }
6039 }
6040 for (i = 0; i < 4; i++) {
6041 if (pos_args[i].out[0])
6042 num_pos_exports++;
6043 }
6044
6045 pos_idx = 0;
6046 for (i = 0; i < 4; i++) {
6047 if (!pos_args[i].out[0])
6048 continue;
6049
6050 /* Specify the target we are exporting */
6051 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6052 if (pos_idx == num_pos_exports)
6053 pos_args[i].done = 1;
6054 ac_build_export(&ctx->ac, &pos_args[i]);
6055 }
6056
6057 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6058 LLVMValueRef values[4];
6059 if (!(ctx->output_mask & (1ull << i)))
6060 continue;
6061
6062 for (unsigned j = 0; j < 4; j++)
6063 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6064 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6065
6066 if (i == VARYING_SLOT_LAYER) {
6067 target = V_008DFC_SQ_EXP_PARAM + param_count;
6068 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
6069 param_count++;
6070 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
6071 target = V_008DFC_SQ_EXP_PARAM + param_count;
6072 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
6073 param_count++;
6074 } else if (i >= VARYING_SLOT_VAR0) {
6075 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
6076 target = V_008DFC_SQ_EXP_PARAM + param_count;
6077 outinfo->vs_output_param_offset[i] = param_count;
6078 param_count++;
6079 } else
6080 continue;
6081
6082 si_llvm_init_export_args(ctx, values, target, &args);
6083
6084 if (target >= V_008DFC_SQ_EXP_POS &&
6085 target <= (V_008DFC_SQ_EXP_POS + 3)) {
6086 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6087 &args, sizeof(args));
6088 } else {
6089 ac_build_export(&ctx->ac, &args);
6090 }
6091 }
6092
6093 if (export_prim_id) {
6094 LLVMValueRef values[4];
6095 target = V_008DFC_SQ_EXP_PARAM + param_count;
6096 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
6097 param_count++;
6098
6099 values[0] = ctx->vs_prim_id;
6100 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6101 ctx->shader_info->vs.vgpr_comp_cnt);
6102 for (unsigned j = 1; j < 4; j++)
6103 values[j] = ctx->ac.f32_0;
6104 si_llvm_init_export_args(ctx, values, target, &args);
6105 ac_build_export(&ctx->ac, &args);
6106 outinfo->export_prim_id = true;
6107 }
6108
6109 outinfo->pos_exports = num_pos_exports;
6110 outinfo->param_exports = param_count;
6111 }
6112
6113 static void
6114 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
6115 struct ac_es_output_info *outinfo)
6116 {
6117 int j;
6118 uint64_t max_output_written = 0;
6119 LLVMValueRef lds_base = NULL;
6120
6121 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6122 int param_index;
6123 int length = 4;
6124
6125 if (!(ctx->output_mask & (1ull << i)))
6126 continue;
6127
6128 if (i == VARYING_SLOT_CLIP_DIST0)
6129 length = ctx->num_output_clips + ctx->num_output_culls;
6130
6131 param_index = shader_io_get_unique_index(i);
6132
6133 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6134 }
6135
6136 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6137
6138 if (ctx->ac.chip_class >= GFX9) {
6139 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6140 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6141 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6142 LLVMConstInt(ctx->ac.i32, 24, false),
6143 LLVMConstInt(ctx->ac.i32, 4, false), false);
6144 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6145 LLVMBuildMul(ctx->ac.builder, wave_idx,
6146 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6147 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6148 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6149 }
6150
6151 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6152 LLVMValueRef dw_addr;
6153 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6154 int param_index;
6155 int length = 4;
6156
6157 if (!(ctx->output_mask & (1ull << i)))
6158 continue;
6159
6160 if (i == VARYING_SLOT_CLIP_DIST0)
6161 length = ctx->num_output_clips + ctx->num_output_culls;
6162
6163 param_index = shader_io_get_unique_index(i);
6164
6165 if (lds_base) {
6166 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6167 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6168 "");
6169 }
6170 for (j = 0; j < length; j++) {
6171 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6172 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6173
6174 if (ctx->ac.chip_class >= GFX9) {
6175 ac_lds_store(&ctx->ac, dw_addr,
6176 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6177 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6178 } else {
6179 ac_build_buffer_store_dword(&ctx->ac,
6180 ctx->esgs_ring,
6181 out_val, 1,
6182 NULL, ctx->es2gs_offset,
6183 (4 * param_index + j) * 4,
6184 1, 1, true, true);
6185 }
6186 }
6187 }
6188 }
6189
6190 static void
6191 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6192 {
6193 LLVMValueRef vertex_id = ctx->rel_auto_id;
6194 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6195 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6196 vertex_dw_stride, "");
6197
6198 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6199 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6200 int length = 4;
6201
6202 if (!(ctx->output_mask & (1ull << i)))
6203 continue;
6204
6205 if (i == VARYING_SLOT_CLIP_DIST0)
6206 length = ctx->num_output_clips + ctx->num_output_culls;
6207 int param = shader_io_get_unique_index(i);
6208 mark_tess_output(ctx, false, param);
6209 if (length > 4)
6210 mark_tess_output(ctx, false, param + 1);
6211 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6212 LLVMConstInt(ctx->ac.i32, param * 4, false),
6213 "");
6214 for (unsigned j = 0; j < length; j++) {
6215 ac_lds_store(&ctx->ac, dw_addr,
6216 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6217 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6218 }
6219 }
6220 }
6221
6222 struct ac_build_if_state
6223 {
6224 struct nir_to_llvm_context *ctx;
6225 LLVMValueRef condition;
6226 LLVMBasicBlockRef entry_block;
6227 LLVMBasicBlockRef true_block;
6228 LLVMBasicBlockRef false_block;
6229 LLVMBasicBlockRef merge_block;
6230 };
6231
6232 static LLVMBasicBlockRef
6233 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6234 {
6235 LLVMBasicBlockRef current_block;
6236 LLVMBasicBlockRef next_block;
6237 LLVMBasicBlockRef new_block;
6238
6239 /* get current basic block */
6240 current_block = LLVMGetInsertBlock(ctx->builder);
6241
6242 /* chqeck if there's another block after this one */
6243 next_block = LLVMGetNextBasicBlock(current_block);
6244 if (next_block) {
6245 /* insert the new block before the next block */
6246 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6247 }
6248 else {
6249 /* append new block after current block */
6250 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6251 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6252 }
6253 return new_block;
6254 }
6255
6256 static void
6257 ac_nir_build_if(struct ac_build_if_state *ifthen,
6258 struct nir_to_llvm_context *ctx,
6259 LLVMValueRef condition)
6260 {
6261 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6262
6263 memset(ifthen, 0, sizeof *ifthen);
6264 ifthen->ctx = ctx;
6265 ifthen->condition = condition;
6266 ifthen->entry_block = block;
6267
6268 /* create endif/merge basic block for the phi functions */
6269 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6270
6271 /* create/insert true_block before merge_block */
6272 ifthen->true_block =
6273 LLVMInsertBasicBlockInContext(ctx->context,
6274 ifthen->merge_block,
6275 "if-true-block");
6276
6277 /* successive code goes into the true block */
6278 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6279 }
6280
6281 /**
6282 * End a conditional.
6283 */
6284 static void
6285 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6286 {
6287 LLVMBuilderRef builder = ifthen->ctx->builder;
6288
6289 /* Insert branch to the merge block from current block */
6290 LLVMBuildBr(builder, ifthen->merge_block);
6291
6292 /*
6293 * Now patch in the various branch instructions.
6294 */
6295
6296 /* Insert the conditional branch instruction at the end of entry_block */
6297 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6298 if (ifthen->false_block) {
6299 /* we have an else clause */
6300 LLVMBuildCondBr(builder, ifthen->condition,
6301 ifthen->true_block, ifthen->false_block);
6302 }
6303 else {
6304 /* no else clause */
6305 LLVMBuildCondBr(builder, ifthen->condition,
6306 ifthen->true_block, ifthen->merge_block);
6307 }
6308
6309 /* Resume building code at end of the ifthen->merge_block */
6310 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6311 }
6312
6313 static void
6314 write_tess_factors(struct nir_to_llvm_context *ctx)
6315 {
6316 unsigned stride, outer_comps, inner_comps;
6317 struct ac_build_if_state if_ctx, inner_if_ctx;
6318 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6319 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6320 unsigned tess_inner_index, tess_outer_index;
6321 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6322 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6323 int i;
6324 emit_barrier(&ctx->ac, ctx->stage);
6325
6326 switch (ctx->options->key.tcs.primitive_mode) {
6327 case GL_ISOLINES:
6328 stride = 2;
6329 outer_comps = 2;
6330 inner_comps = 0;
6331 break;
6332 case GL_TRIANGLES:
6333 stride = 4;
6334 outer_comps = 3;
6335 inner_comps = 1;
6336 break;
6337 case GL_QUADS:
6338 stride = 6;
6339 outer_comps = 4;
6340 inner_comps = 2;
6341 break;
6342 default:
6343 return;
6344 }
6345
6346 ac_nir_build_if(&if_ctx, ctx,
6347 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6348 invocation_id, ctx->ac.i32_0, ""));
6349
6350 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6351 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6352
6353 mark_tess_output(ctx, true, tess_inner_index);
6354 mark_tess_output(ctx, true, tess_outer_index);
6355 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6356 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6357 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6358 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6359 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6360
6361 for (i = 0; i < 4; i++) {
6362 inner[i] = LLVMGetUndef(ctx->ac.i32);
6363 outer[i] = LLVMGetUndef(ctx->ac.i32);
6364 }
6365
6366 // LINES reverseal
6367 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6368 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6369 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6370 ctx->ac.i32_1, "");
6371 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6372 } else {
6373 for (i = 0; i < outer_comps; i++) {
6374 outer[i] = out[i] =
6375 ac_lds_load(&ctx->ac, lds_outer);
6376 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6377 ctx->ac.i32_1, "");
6378 }
6379 for (i = 0; i < inner_comps; i++) {
6380 inner[i] = out[outer_comps+i] =
6381 ac_lds_load(&ctx->ac, lds_inner);
6382 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6383 ctx->ac.i32_1, "");
6384 }
6385 }
6386
6387 /* Convert the outputs to vectors for stores. */
6388 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6389 vec1 = NULL;
6390
6391 if (stride > 4)
6392 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6393
6394
6395 buffer = ctx->hs_ring_tess_factor;
6396 tf_base = ctx->tess_factor_offset;
6397 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6398 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6399 unsigned tf_offset = 0;
6400
6401 if (ctx->options->chip_class <= VI) {
6402 ac_nir_build_if(&inner_if_ctx, ctx,
6403 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6404 rel_patch_id, ctx->ac.i32_0, ""));
6405
6406 /* Store the dynamic HS control word. */
6407 ac_build_buffer_store_dword(&ctx->ac, buffer,
6408 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6409 1, ctx->ac.i32_0, tf_base,
6410 0, 1, 0, true, false);
6411 tf_offset += 4;
6412
6413 ac_nir_build_endif(&inner_if_ctx);
6414 }
6415
6416 /* Store the tessellation factors. */
6417 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6418 MIN2(stride, 4), byteoffset, tf_base,
6419 tf_offset, 1, 0, true, false);
6420 if (vec1)
6421 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6422 stride - 4, byteoffset, tf_base,
6423 16 + tf_offset, 1, 0, true, false);
6424
6425 //store to offchip for TES to read - only if TES reads them
6426 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6427 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6428 LLVMValueRef tf_inner_offset;
6429 unsigned param_outer, param_inner;
6430
6431 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6432 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6433 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6434
6435 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6436 util_next_power_of_two(outer_comps));
6437
6438 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6439 outer_comps, tf_outer_offset,
6440 ctx->oc_lds, 0, 1, 0, true, false);
6441 if (inner_comps) {
6442 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6443 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6444 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6445
6446 inner_vec = inner_comps == 1 ? inner[0] :
6447 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6448 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6449 inner_comps, tf_inner_offset,
6450 ctx->oc_lds, 0, 1, 0, true, false);
6451 }
6452 }
6453 ac_nir_build_endif(&if_ctx);
6454 }
6455
6456 static void
6457 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6458 {
6459 write_tess_factors(ctx);
6460 }
6461
6462 static bool
6463 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6464 LLVMValueRef *color, unsigned param, bool is_last,
6465 struct ac_export_args *args)
6466 {
6467 /* Export */
6468 si_llvm_init_export_args(ctx, color, param,
6469 args);
6470
6471 if (is_last) {
6472 args->valid_mask = 1; /* whether the EXEC mask is valid */
6473 args->done = 1; /* DONE bit */
6474 } else if (!args->enabled_channels)
6475 return false; /* unnecessary NULL export */
6476
6477 return true;
6478 }
6479
6480 static void
6481 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6482 LLVMValueRef depth, LLVMValueRef stencil,
6483 LLVMValueRef samplemask)
6484 {
6485 struct ac_export_args args;
6486
6487 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6488
6489 ac_build_export(&ctx->ac, &args);
6490 }
6491
6492 static void
6493 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6494 {
6495 unsigned index = 0;
6496 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6497 struct ac_export_args color_args[8];
6498
6499 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6500 LLVMValueRef values[4];
6501
6502 if (!(ctx->output_mask & (1ull << i)))
6503 continue;
6504
6505 if (i == FRAG_RESULT_DEPTH) {
6506 ctx->shader_info->fs.writes_z = true;
6507 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6508 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6509 } else if (i == FRAG_RESULT_STENCIL) {
6510 ctx->shader_info->fs.writes_stencil = true;
6511 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6512 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6513 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6514 ctx->shader_info->fs.writes_sample_mask = true;
6515 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6516 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6517 } else {
6518 bool last = false;
6519 for (unsigned j = 0; j < 4; j++)
6520 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6521 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6522
6523 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6524 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6525
6526 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6527 if (ret)
6528 index++;
6529 }
6530 }
6531
6532 for (unsigned i = 0; i < index; i++)
6533 ac_build_export(&ctx->ac, &color_args[i]);
6534 if (depth || stencil || samplemask)
6535 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6536 else if (!index) {
6537 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6538 ac_build_export(&ctx->ac, &color_args[0]);
6539 }
6540 }
6541
6542 static void
6543 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6544 {
6545 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6546 }
6547
6548 static void
6549 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6550 LLVMValueRef *addrs)
6551 {
6552 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6553
6554 switch (ctx->stage) {
6555 case MESA_SHADER_VERTEX:
6556 if (ctx->options->key.vs.as_ls)
6557 handle_ls_outputs_post(ctx);
6558 else if (ctx->options->key.vs.as_es)
6559 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6560 else
6561 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6562 &ctx->shader_info->vs.outinfo);
6563 break;
6564 case MESA_SHADER_FRAGMENT:
6565 handle_fs_outputs_post(ctx);
6566 break;
6567 case MESA_SHADER_GEOMETRY:
6568 emit_gs_epilogue(ctx);
6569 break;
6570 case MESA_SHADER_TESS_CTRL:
6571 handle_tcs_outputs_post(ctx);
6572 break;
6573 case MESA_SHADER_TESS_EVAL:
6574 if (ctx->options->key.tes.as_es)
6575 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6576 else
6577 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6578 &ctx->shader_info->tes.outinfo);
6579 break;
6580 default:
6581 break;
6582 }
6583 }
6584
6585 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6586 {
6587 LLVMPassManagerRef passmgr;
6588 /* Create the pass manager */
6589 passmgr = LLVMCreateFunctionPassManagerForModule(
6590 ctx->module);
6591
6592 /* This pass should eliminate all the load and store instructions */
6593 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6594
6595 /* Add some optimization passes */
6596 LLVMAddScalarReplAggregatesPass(passmgr);
6597 LLVMAddLICMPass(passmgr);
6598 LLVMAddAggressiveDCEPass(passmgr);
6599 LLVMAddCFGSimplificationPass(passmgr);
6600 LLVMAddInstructionCombiningPass(passmgr);
6601
6602 /* Run the pass */
6603 LLVMInitializeFunctionPassManager(passmgr);
6604 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6605 LLVMFinalizeFunctionPassManager(passmgr);
6606
6607 LLVMDisposeBuilder(ctx->builder);
6608 LLVMDisposePassManager(passmgr);
6609 }
6610
6611 static void
6612 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6613 {
6614 struct ac_vs_output_info *outinfo;
6615
6616 switch (ctx->stage) {
6617 case MESA_SHADER_FRAGMENT:
6618 case MESA_SHADER_COMPUTE:
6619 case MESA_SHADER_TESS_CTRL:
6620 case MESA_SHADER_GEOMETRY:
6621 return;
6622 case MESA_SHADER_VERTEX:
6623 if (ctx->options->key.vs.as_ls ||
6624 ctx->options->key.vs.as_es)
6625 return;
6626 outinfo = &ctx->shader_info->vs.outinfo;
6627 break;
6628 case MESA_SHADER_TESS_EVAL:
6629 if (ctx->options->key.vs.as_es)
6630 return;
6631 outinfo = &ctx->shader_info->tes.outinfo;
6632 break;
6633 default:
6634 unreachable("Unhandled shader type");
6635 }
6636
6637 ac_optimize_vs_outputs(&ctx->ac,
6638 ctx->main_function,
6639 outinfo->vs_output_param_offset,
6640 VARYING_SLOT_MAX,
6641 &outinfo->param_exports);
6642 }
6643
6644 static void
6645 ac_setup_rings(struct nir_to_llvm_context *ctx)
6646 {
6647 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6648 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6649 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6650 }
6651
6652 if (ctx->is_gs_copy_shader) {
6653 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6654 }
6655 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6656 LLVMValueRef tmp;
6657 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6658 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6659
6660 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6661
6662 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6663 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6664 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6665 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6666 }
6667
6668 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6669 ctx->stage == MESA_SHADER_TESS_EVAL) {
6670 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6671 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6672 }
6673 }
6674
6675 static unsigned
6676 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6677 const struct nir_shader *nir)
6678 {
6679 switch (nir->info.stage) {
6680 case MESA_SHADER_TESS_CTRL:
6681 return chip_class >= CIK ? 128 : 64;
6682 case MESA_SHADER_GEOMETRY:
6683 return chip_class >= GFX9 ? 128 : 64;
6684 case MESA_SHADER_COMPUTE:
6685 break;
6686 default:
6687 return 0;
6688 }
6689
6690 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6691 nir->info.cs.local_size[1] *
6692 nir->info.cs.local_size[2];
6693 return max_workgroup_size;
6694 }
6695
6696 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6697 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6698 {
6699 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6700 LLVMConstInt(ctx->ac.i32, 8, false),
6701 LLVMConstInt(ctx->ac.i32, 8, false), false);
6702 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6703 ctx->ac.i32_0, "");
6704 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6705 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6706 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6707 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6708 }
6709
6710 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6711 {
6712 for(int i = 5; i >= 0; --i) {
6713 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6714 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6715 LLVMConstInt(ctx->ac.i32, 16, false), false);
6716 }
6717
6718 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6719 LLVMConstInt(ctx->ac.i32, 16, false),
6720 LLVMConstInt(ctx->ac.i32, 8, false), false);
6721 }
6722
6723 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6724 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6725 {
6726 struct ac_nir_context ctx = {};
6727 struct nir_function *func;
6728
6729 ctx.ac = *ac;
6730 ctx.abi = abi;
6731
6732 ctx.nctx = nctx;
6733 if (nctx)
6734 nctx->nir = &ctx;
6735
6736 ctx.stage = nir->info.stage;
6737
6738 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6739
6740 nir_foreach_variable(variable, &nir->outputs)
6741 handle_shader_output_decl(&ctx, nir, variable);
6742
6743 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6744 _mesa_key_pointer_equal);
6745 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6746 _mesa_key_pointer_equal);
6747 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6748 _mesa_key_pointer_equal);
6749
6750 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6751
6752 setup_locals(&ctx, func);
6753
6754 if (nir->info.stage == MESA_SHADER_COMPUTE)
6755 setup_shared(&ctx, nir);
6756
6757 visit_cf_list(&ctx, &func->impl->body);
6758 phi_post_pass(&ctx);
6759
6760 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6761 ctx.outputs);
6762
6763 free(ctx.locals);
6764 ralloc_free(ctx.defs);
6765 ralloc_free(ctx.phis);
6766 ralloc_free(ctx.vars);
6767
6768 if (nctx)
6769 nctx->nir = NULL;
6770 }
6771
6772 static
6773 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6774 struct nir_shader *const *shaders,
6775 int shader_count,
6776 struct ac_shader_variant_info *shader_info,
6777 const struct ac_nir_compiler_options *options)
6778 {
6779 struct nir_to_llvm_context ctx = {0};
6780 unsigned i;
6781 ctx.options = options;
6782 ctx.shader_info = shader_info;
6783 ctx.context = LLVMContextCreate();
6784 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6785
6786 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6787 options->family);
6788 ctx.ac.module = ctx.module;
6789 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6790
6791 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6792 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6793 LLVMSetDataLayout(ctx.module, data_layout_str);
6794 LLVMDisposeTargetData(data_layout);
6795 LLVMDisposeMessage(data_layout_str);
6796
6797 enum ac_float_mode float_mode =
6798 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6799 AC_FLOAT_MODE_DEFAULT;
6800
6801 ctx.builder = ac_create_builder(ctx.context, float_mode);
6802 ctx.ac.builder = ctx.builder;
6803
6804 memset(shader_info, 0, sizeof(*shader_info));
6805
6806 for(int i = 0; i < shader_count; ++i)
6807 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6808
6809 for (i = 0; i < AC_UD_MAX_SETS; i++)
6810 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6811 for (i = 0; i < AC_UD_MAX_UD; i++)
6812 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6813
6814 ctx.max_workgroup_size = 0;
6815 for (int i = 0; i < shader_count; ++i) {
6816 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6817 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6818 shaders[i]));
6819 }
6820
6821 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6822 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6823
6824 ctx.abi.inputs = &ctx.inputs[0];
6825 ctx.abi.emit_outputs = handle_shader_outputs_post;
6826 ctx.abi.emit_vertex = visit_emit_vertex;
6827 ctx.abi.load_ubo = radv_load_ubo;
6828 ctx.abi.load_ssbo = radv_load_ssbo;
6829 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6830 ctx.abi.clamp_shadow_reference = false;
6831
6832 if (shader_count >= 2)
6833 ac_init_exec_full_mask(&ctx.ac);
6834
6835 if (ctx.ac.chip_class == GFX9 &&
6836 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6837 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6838
6839 for(int i = 0; i < shader_count; ++i) {
6840 ctx.stage = shaders[i]->info.stage;
6841 ctx.output_mask = 0;
6842 ctx.tess_outputs_written = 0;
6843 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6844 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6845
6846 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6847 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6848 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6849 ctx.abi.load_inputs = load_gs_input;
6850 ctx.abi.emit_primitive = visit_end_primitive;
6851 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6852 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6853 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6854 ctx.abi.load_tess_varyings = load_tcs_varyings;
6855 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6856 ctx.abi.store_tcs_outputs = store_tcs_output;
6857 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6858 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6859 ctx.abi.load_tess_varyings = load_tes_input;
6860 ctx.abi.load_tess_coord = load_tess_coord;
6861 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6862 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6863 if (shader_info->info.vs.needs_instance_id) {
6864 if (ctx.options->key.vs.as_ls) {
6865 ctx.shader_info->vs.vgpr_comp_cnt =
6866 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6867 } else {
6868 ctx.shader_info->vs.vgpr_comp_cnt =
6869 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6870 }
6871 }
6872 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6873 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6874 }
6875
6876 if (i)
6877 emit_barrier(&ctx.ac, ctx.stage);
6878
6879 ac_setup_rings(&ctx);
6880
6881 LLVMBasicBlockRef merge_block;
6882 if (shader_count >= 2) {
6883 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6884 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6885 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6886
6887 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6888 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6889 LLVMConstInt(ctx.ac.i32, 8, false), false);
6890 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6891 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6892 thread_id, count, "");
6893 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6894
6895 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6896 }
6897
6898 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6899 handle_fs_inputs(&ctx, shaders[i]);
6900 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6901 handle_vs_inputs(&ctx, shaders[i]);
6902 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6903 prepare_gs_input_vgprs(&ctx);
6904
6905 nir_foreach_variable(variable, &shaders[i]->outputs)
6906 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6907
6908 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6909
6910 if (shader_count >= 2) {
6911 LLVMBuildBr(ctx.ac.builder, merge_block);
6912 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6913 }
6914
6915 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6916 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6917 shaders[i]->info.cull_distance_array_size > 4;
6918 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6919 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6920 shaders[i]->info.gs.vertices_out;
6921 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6922 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6923 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6924 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6925 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6926 }
6927 }
6928
6929 LLVMBuildRetVoid(ctx.builder);
6930
6931 if (options->dump_preoptir)
6932 ac_dump_module(ctx.module);
6933
6934 ac_llvm_finalize_module(&ctx);
6935
6936 if (shader_count == 1)
6937 ac_nir_eliminate_const_vs_outputs(&ctx);
6938
6939 return ctx.module;
6940 }
6941
6942 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6943 {
6944 unsigned *retval = (unsigned *)context;
6945 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6946 char *description = LLVMGetDiagInfoDescription(di);
6947
6948 if (severity == LLVMDSError) {
6949 *retval = 1;
6950 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6951 description);
6952 }
6953
6954 LLVMDisposeMessage(description);
6955 }
6956
6957 static unsigned ac_llvm_compile(LLVMModuleRef M,
6958 struct ac_shader_binary *binary,
6959 LLVMTargetMachineRef tm)
6960 {
6961 unsigned retval = 0;
6962 char *err;
6963 LLVMContextRef llvm_ctx;
6964 LLVMMemoryBufferRef out_buffer;
6965 unsigned buffer_size;
6966 const char *buffer_data;
6967 LLVMBool mem_err;
6968
6969 /* Setup Diagnostic Handler*/
6970 llvm_ctx = LLVMGetModuleContext(M);
6971
6972 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6973 &retval);
6974
6975 /* Compile IR*/
6976 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6977 &err, &out_buffer);
6978
6979 /* Process Errors/Warnings */
6980 if (mem_err) {
6981 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6982 free(err);
6983 retval = 1;
6984 goto out;
6985 }
6986
6987 /* Extract Shader Code*/
6988 buffer_size = LLVMGetBufferSize(out_buffer);
6989 buffer_data = LLVMGetBufferStart(out_buffer);
6990
6991 ac_elf_read(buffer_data, buffer_size, binary);
6992
6993 /* Clean up */
6994 LLVMDisposeMemoryBuffer(out_buffer);
6995
6996 out:
6997 return retval;
6998 }
6999
7000 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
7001 LLVMModuleRef llvm_module,
7002 struct ac_shader_binary *binary,
7003 struct ac_shader_config *config,
7004 struct ac_shader_variant_info *shader_info,
7005 gl_shader_stage stage,
7006 bool dump_shader, bool supports_spill)
7007 {
7008 if (dump_shader)
7009 ac_dump_module(llvm_module);
7010
7011 memset(binary, 0, sizeof(*binary));
7012 int v = ac_llvm_compile(llvm_module, binary, tm);
7013 if (v) {
7014 fprintf(stderr, "compile failed\n");
7015 }
7016
7017 if (dump_shader)
7018 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7019
7020 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7021
7022 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7023 LLVMDisposeModule(llvm_module);
7024 LLVMContextDispose(ctx);
7025
7026 if (stage == MESA_SHADER_FRAGMENT) {
7027 shader_info->num_input_vgprs = 0;
7028 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7029 shader_info->num_input_vgprs += 2;
7030 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7031 shader_info->num_input_vgprs += 2;
7032 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7033 shader_info->num_input_vgprs += 2;
7034 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7035 shader_info->num_input_vgprs += 3;
7036 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7037 shader_info->num_input_vgprs += 2;
7038 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7039 shader_info->num_input_vgprs += 2;
7040 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7041 shader_info->num_input_vgprs += 2;
7042 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7043 shader_info->num_input_vgprs += 1;
7044 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7045 shader_info->num_input_vgprs += 1;
7046 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7047 shader_info->num_input_vgprs += 1;
7048 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7049 shader_info->num_input_vgprs += 1;
7050 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7051 shader_info->num_input_vgprs += 1;
7052 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7053 shader_info->num_input_vgprs += 1;
7054 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7055 shader_info->num_input_vgprs += 1;
7056 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7057 shader_info->num_input_vgprs += 1;
7058 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7059 shader_info->num_input_vgprs += 1;
7060 }
7061 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7062
7063 /* +3 for scratch wave offset and VCC */
7064 config->num_sgprs = MAX2(config->num_sgprs,
7065 shader_info->num_input_sgprs + 3);
7066
7067 /* Enable 64-bit and 16-bit denormals, because there is no performance
7068 * cost.
7069 *
7070 * If denormals are enabled, all floating-point output modifiers are
7071 * ignored.
7072 *
7073 * Don't enable denormals for 32-bit floats, because:
7074 * - Floating-point output modifiers would be ignored by the hw.
7075 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7076 * have to stop using those.
7077 * - SI & CI would be very slow.
7078 */
7079 config->float_mode |= V_00B028_FP_64_DENORMS;
7080 }
7081
7082 static void
7083 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7084 {
7085 switch (nir->info.stage) {
7086 case MESA_SHADER_COMPUTE:
7087 for (int i = 0; i < 3; ++i)
7088 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7089 break;
7090 case MESA_SHADER_FRAGMENT:
7091 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7092 break;
7093 case MESA_SHADER_GEOMETRY:
7094 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7095 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7096 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7097 shader_info->gs.invocations = nir->info.gs.invocations;
7098 break;
7099 case MESA_SHADER_TESS_EVAL:
7100 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7101 shader_info->tes.spacing = nir->info.tess.spacing;
7102 shader_info->tes.ccw = nir->info.tess.ccw;
7103 shader_info->tes.point_mode = nir->info.tess.point_mode;
7104 shader_info->tes.as_es = options->key.tes.as_es;
7105 break;
7106 case MESA_SHADER_TESS_CTRL:
7107 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7108 break;
7109 case MESA_SHADER_VERTEX:
7110 shader_info->vs.as_es = options->key.vs.as_es;
7111 shader_info->vs.as_ls = options->key.vs.as_ls;
7112 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7113 if (options->key.vs.as_ls)
7114 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7115 break;
7116 default:
7117 break;
7118 }
7119 }
7120
7121 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7122 struct ac_shader_binary *binary,
7123 struct ac_shader_config *config,
7124 struct ac_shader_variant_info *shader_info,
7125 struct nir_shader *const *nir,
7126 int nir_count,
7127 const struct ac_nir_compiler_options *options,
7128 bool dump_shader)
7129 {
7130
7131 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7132 options);
7133
7134 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7135 for (int i = 0; i < nir_count; ++i)
7136 ac_fill_shader_info(shader_info, nir[i], options);
7137
7138 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7139 if (options->chip_class == GFX9) {
7140 if (nir_count == 2 &&
7141 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7142 shader_info->gs.es_type = nir[0]->info.stage;
7143 }
7144 }
7145 }
7146
7147 static void
7148 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
7149 {
7150 LLVMValueRef args[9];
7151 args[0] = ctx->gsvs_ring;
7152 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
7153 args[3] = ctx->ac.i32_0;
7154 args[4] = ctx->ac.i32_1; /* OFFEN */
7155 args[5] = ctx->ac.i32_0; /* IDXEN */
7156 args[6] = ctx->ac.i32_1; /* GLC */
7157 args[7] = ctx->ac.i32_1; /* SLC */
7158 args[8] = ctx->ac.i32_0; /* TFE */
7159
7160 int idx = 0;
7161
7162 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7163 int length = 4;
7164 int slot = idx;
7165 int slot_inc = 1;
7166 if (!(ctx->output_mask & (1ull << i)))
7167 continue;
7168
7169 if (i == VARYING_SLOT_CLIP_DIST0) {
7170 /* unpack clip and cull from a single set of slots */
7171 length = ctx->num_output_clips + ctx->num_output_culls;
7172 if (length > 4)
7173 slot_inc = 2;
7174 }
7175
7176 for (unsigned j = 0; j < length; j++) {
7177 LLVMValueRef value;
7178 args[2] = LLVMConstInt(ctx->ac.i32,
7179 (slot * 4 + j) *
7180 ctx->gs_max_out_vertices * 16 * 4, false);
7181
7182 value = ac_build_intrinsic(&ctx->ac,
7183 "llvm.SI.buffer.load.dword.i32.i32",
7184 ctx->ac.i32, args, 9,
7185 AC_FUNC_ATTR_READONLY |
7186 AC_FUNC_ATTR_LEGACY);
7187
7188 LLVMBuildStore(ctx->builder,
7189 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7190 }
7191 idx += slot_inc;
7192 }
7193 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7194 }
7195
7196 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7197 struct nir_shader *geom_shader,
7198 struct ac_shader_binary *binary,
7199 struct ac_shader_config *config,
7200 struct ac_shader_variant_info *shader_info,
7201 const struct ac_nir_compiler_options *options,
7202 bool dump_shader)
7203 {
7204 struct nir_to_llvm_context ctx = {0};
7205 ctx.context = LLVMContextCreate();
7206 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7207 ctx.options = options;
7208 ctx.shader_info = shader_info;
7209
7210 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7211 options->family);
7212 ctx.ac.module = ctx.module;
7213
7214 ctx.is_gs_copy_shader = true;
7215 LLVMSetTarget(ctx.module, "amdgcn--");
7216
7217 enum ac_float_mode float_mode =
7218 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7219 AC_FLOAT_MODE_DEFAULT;
7220
7221 ctx.builder = ac_create_builder(ctx.context, float_mode);
7222 ctx.ac.builder = ctx.builder;
7223 ctx.stage = MESA_SHADER_VERTEX;
7224
7225 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7226
7227 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7228 ac_setup_rings(&ctx);
7229
7230 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7231 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7232
7233 struct ac_nir_context nir_ctx = {};
7234 nir_ctx.ac = ctx.ac;
7235 nir_ctx.abi = &ctx.abi;
7236
7237 nir_ctx.nctx = &ctx;
7238 ctx.nir = &nir_ctx;
7239
7240 nir_foreach_variable(variable, &geom_shader->outputs) {
7241 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7242 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7243 }
7244
7245 ac_gs_copy_shader_emit(&ctx);
7246
7247 ctx.nir = NULL;
7248
7249 LLVMBuildRetVoid(ctx.builder);
7250
7251 ac_llvm_finalize_module(&ctx);
7252
7253 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7254 MESA_SHADER_VERTEX,
7255 dump_shader, options->supports_spill);
7256 }