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ac: remove offen parameter from ac_build_buffer_store_dword
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef gsvs_ring_stride;
87 LLVMValueRef gsvs_num_entries;
88 LLVMValueRef gs2vs_offset;
89 LLVMValueRef gs_wave_id;
90 LLVMValueRef gs_vtx_offset[6];
91 LLVMValueRef gs_prim_id, gs_invocation_id;
92
93 LLVMValueRef esgs_ring;
94 LLVMValueRef gsvs_ring;
95
96 LLVMValueRef prim_mask;
97 LLVMValueRef sample_positions;
98 LLVMValueRef persp_sample, persp_center, persp_centroid;
99 LLVMValueRef linear_sample, linear_center, linear_centroid;
100 LLVMValueRef front_face;
101 LLVMValueRef ancillary;
102 LLVMValueRef sample_coverage;
103 LLVMValueRef frag_pos[4];
104
105 LLVMBasicBlockRef continue_block;
106 LLVMBasicBlockRef break_block;
107
108 LLVMTypeRef i1;
109 LLVMTypeRef i8;
110 LLVMTypeRef i16;
111 LLVMTypeRef i32;
112 LLVMTypeRef i64;
113 LLVMTypeRef v2i32;
114 LLVMTypeRef v3i32;
115 LLVMTypeRef v4i32;
116 LLVMTypeRef v8i32;
117 LLVMTypeRef f64;
118 LLVMTypeRef f32;
119 LLVMTypeRef f16;
120 LLVMTypeRef v2f32;
121 LLVMTypeRef v4f32;
122 LLVMTypeRef v16i8;
123 LLVMTypeRef voidt;
124
125 LLVMValueRef i32zero;
126 LLVMValueRef i32one;
127 LLVMValueRef f32zero;
128 LLVMValueRef f32one;
129 LLVMValueRef v4f32empty;
130
131 unsigned uniform_md_kind;
132 LLVMValueRef empty_md;
133 gl_shader_stage stage;
134
135 LLVMValueRef lds;
136 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
137 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
138
139 LLVMValueRef shared_memory;
140 uint64_t input_mask;
141 uint64_t output_mask;
142 int num_locals;
143 LLVMValueRef *locals;
144 bool has_ddxy;
145 uint8_t num_input_clips;
146 uint8_t num_input_culls;
147 uint8_t num_output_clips;
148 uint8_t num_output_culls;
149
150 bool has_ds_bpermute;
151
152 bool is_gs_copy_shader;
153 LLVMValueRef gs_next_vertex;
154 unsigned gs_max_out_vertices;
155 };
156
157 struct ac_tex_info {
158 LLVMValueRef args[12];
159 int arg_count;
160 LLVMTypeRef dst_type;
161 bool has_offset;
162 };
163
164 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
165 nir_deref_var *deref,
166 enum desc_type desc_type);
167 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
168 {
169 return (index * 4) + chan;
170 }
171
172 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
173 {
174 if (slot == VARYING_SLOT_POS)
175 return 0;
176 if (slot == VARYING_SLOT_PSIZ)
177 return 1;
178 if (slot == VARYING_SLOT_CLIP_DIST0 ||
179 slot == VARYING_SLOT_CULL_DIST0)
180 return 2;
181 if (slot == VARYING_SLOT_CLIP_DIST1 ||
182 slot == VARYING_SLOT_CULL_DIST1)
183 return 3;
184 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
185 return 4 + (slot - VARYING_SLOT_VAR0);
186 unreachable("illegal slot in get unique index\n");
187 }
188
189 static unsigned llvm_get_type_size(LLVMTypeRef type)
190 {
191 LLVMTypeKind kind = LLVMGetTypeKind(type);
192
193 switch (kind) {
194 case LLVMIntegerTypeKind:
195 return LLVMGetIntTypeWidth(type) / 8;
196 case LLVMFloatTypeKind:
197 return 4;
198 case LLVMPointerTypeKind:
199 return 8;
200 case LLVMVectorTypeKind:
201 return LLVMGetVectorSize(type) *
202 llvm_get_type_size(LLVMGetElementType(type));
203 default:
204 assert(0);
205 return 0;
206 }
207 }
208
209 static void set_llvm_calling_convention(LLVMValueRef func,
210 gl_shader_stage stage)
211 {
212 enum radeon_llvm_calling_convention calling_conv;
213
214 switch (stage) {
215 case MESA_SHADER_VERTEX:
216 case MESA_SHADER_TESS_CTRL:
217 case MESA_SHADER_TESS_EVAL:
218 calling_conv = RADEON_LLVM_AMDGPU_VS;
219 break;
220 case MESA_SHADER_GEOMETRY:
221 calling_conv = RADEON_LLVM_AMDGPU_GS;
222 break;
223 case MESA_SHADER_FRAGMENT:
224 calling_conv = RADEON_LLVM_AMDGPU_PS;
225 break;
226 case MESA_SHADER_COMPUTE:
227 calling_conv = RADEON_LLVM_AMDGPU_CS;
228 break;
229 default:
230 unreachable("Unhandle shader type");
231 }
232
233 LLVMSetFunctionCallConv(func, calling_conv);
234 }
235
236 static LLVMValueRef
237 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
238 LLVMBuilderRef builder, LLVMTypeRef *return_types,
239 unsigned num_return_elems, LLVMTypeRef *param_types,
240 unsigned param_count, unsigned array_params_mask,
241 unsigned sgpr_params, bool unsafe_math)
242 {
243 LLVMTypeRef main_function_type, ret_type;
244 LLVMBasicBlockRef main_function_body;
245
246 if (num_return_elems)
247 ret_type = LLVMStructTypeInContext(ctx, return_types,
248 num_return_elems, true);
249 else
250 ret_type = LLVMVoidTypeInContext(ctx);
251
252 /* Setup the function */
253 main_function_type =
254 LLVMFunctionType(ret_type, param_types, param_count, 0);
255 LLVMValueRef main_function =
256 LLVMAddFunction(module, "main", main_function_type);
257 main_function_body =
258 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
259 LLVMPositionBuilderAtEnd(builder, main_function_body);
260
261 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
262 for (unsigned i = 0; i < sgpr_params; ++i) {
263 if (array_params_mask & (1 << i)) {
264 LLVMValueRef P = LLVMGetParam(main_function, i);
265 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
266 ac_add_attr_dereferenceable(P, UINT64_MAX);
267 }
268 else {
269 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
270 }
271 }
272
273 if (unsafe_math) {
274 /* These were copied from some LLVM test. */
275 LLVMAddTargetDependentFunctionAttr(main_function,
276 "less-precise-fpmad",
277 "true");
278 LLVMAddTargetDependentFunctionAttr(main_function,
279 "no-infs-fp-math",
280 "true");
281 LLVMAddTargetDependentFunctionAttr(main_function,
282 "no-nans-fp-math",
283 "true");
284 LLVMAddTargetDependentFunctionAttr(main_function,
285 "unsafe-fp-math",
286 "true");
287 }
288 return main_function;
289 }
290
291 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
292 {
293 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
294 CONST_ADDR_SPACE);
295 }
296
297 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
298 int idx,
299 LLVMTypeRef type)
300 {
301 LLVMValueRef offset;
302 LLVMValueRef ptr;
303 int addr_space;
304
305 offset = LLVMConstInt(ctx->i32, idx, false);
306
307 ptr = ctx->shared_memory;
308 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
309 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
310 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
311 return ptr;
312 }
313
314 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
315 {
316 if (t == ctx->f16 || t == ctx->i16)
317 return ctx->i16;
318 else if (t == ctx->f32 || t == ctx->i32)
319 return ctx->i32;
320 else if (t == ctx->f64 || t == ctx->i64)
321 return ctx->i64;
322 else
323 unreachable("Unhandled integer size");
324 }
325
326 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
327 {
328 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
329 LLVMTypeRef elem_type = LLVMGetElementType(t);
330 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
331 LLVMGetVectorSize(t));
332 }
333 return to_integer_type_scalar(ctx, t);
334 }
335
336 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
337 {
338 LLVMTypeRef type = LLVMTypeOf(v);
339 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
340 }
341
342 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
343 {
344 if (t == ctx->i16 || t == ctx->f16)
345 return ctx->f16;
346 else if (t == ctx->i32 || t == ctx->f32)
347 return ctx->f32;
348 else if (t == ctx->i64 || t == ctx->f64)
349 return ctx->f64;
350 else
351 unreachable("Unhandled float size");
352 }
353
354 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
355 {
356 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
357 LLVMTypeRef elem_type = LLVMGetElementType(t);
358 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
359 LLVMGetVectorSize(t));
360 }
361 return to_float_type_scalar(ctx, t);
362 }
363
364 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
365 {
366 LLVMTypeRef type = LLVMTypeOf(v);
367 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
368 }
369
370 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
371 {
372 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
373 type = LLVMGetElementType(type);
374
375 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
376 return LLVMGetIntTypeWidth(type);
377
378 if (type == ctx->f16)
379 return 16;
380 if (type == ctx->f32)
381 return 32;
382 if (type == ctx->f64)
383 return 64;
384
385 unreachable("Unhandled type kind in get_elem_bits");
386 }
387
388 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
389 LLVMValueRef param, unsigned rshift,
390 unsigned bitwidth)
391 {
392 LLVMValueRef value = param;
393 if (rshift)
394 value = LLVMBuildLShr(ctx->builder, value,
395 LLVMConstInt(ctx->i32, rshift, false), "");
396
397 if (rshift + bitwidth < 32) {
398 unsigned mask = (1 << bitwidth) - 1;
399 value = LLVMBuildAnd(ctx->builder, value,
400 LLVMConstInt(ctx->i32, mask, false), "");
401 }
402 return value;
403 }
404
405 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
406 {
407 ud_info->sgpr_idx = sgpr_idx;
408 ud_info->num_sgprs = num_sgprs;
409 ud_info->indirect = false;
410 ud_info->indirect_offset = 0;
411 }
412
413 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
414 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
415 {
416 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
417 }
418
419 #if 0
420 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
421 uint32_t indirect_offset)
422 {
423 ud_info->sgpr_idx = sgpr_idx;
424 ud_info->num_sgprs = num_sgprs;
425 ud_info->indirect = true;
426 ud_info->indirect_offset = indirect_offset;
427 }
428 #endif
429
430 static void create_function(struct nir_to_llvm_context *ctx)
431 {
432 LLVMTypeRef arg_types[23];
433 unsigned arg_idx = 0;
434 unsigned array_params_mask = 0;
435 unsigned sgpr_count = 0, user_sgpr_count;
436 unsigned i;
437 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
438 unsigned user_sgpr_idx;
439 bool need_push_constants;
440 bool need_ring_offsets = false;
441
442 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
443 if (ctx->stage == MESA_SHADER_GEOMETRY ||
444 ctx->stage == MESA_SHADER_VERTEX ||
445 ctx->is_gs_copy_shader)
446 need_ring_offsets = true;
447
448 need_push_constants = true;
449 if (!ctx->options->layout)
450 need_push_constants = false;
451 else if (!ctx->options->layout->push_constant_size &&
452 !ctx->options->layout->dynamic_offset_count)
453 need_push_constants = false;
454
455 if (need_ring_offsets && !ctx->options->supports_spill) {
456 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
457 }
458
459 /* 1 for each descriptor set */
460 for (unsigned i = 0; i < num_sets; ++i) {
461 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
462 array_params_mask |= (1 << arg_idx);
463 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
464 }
465 }
466
467 if (need_push_constants) {
468 /* 1 for push constants and dynamic descriptors */
469 array_params_mask |= (1 << arg_idx);
470 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
471 }
472
473 switch (ctx->stage) {
474 case MESA_SHADER_COMPUTE:
475 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
476 user_sgpr_count = arg_idx;
477 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
478 arg_types[arg_idx++] = ctx->i32;
479 sgpr_count = arg_idx;
480
481 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
482 break;
483 case MESA_SHADER_VERTEX:
484 if (!ctx->is_gs_copy_shader) {
485 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
486 arg_types[arg_idx++] = ctx->i32; // base vertex
487 arg_types[arg_idx++] = ctx->i32; // start instance
488 arg_types[arg_idx++] = ctx->i32; // draw index
489 }
490 user_sgpr_count = arg_idx;
491 if (ctx->options->key.vs.as_es)
492 arg_types[arg_idx++] = ctx->i32; //es2gs offset
493 sgpr_count = arg_idx;
494 arg_types[arg_idx++] = ctx->i32; // vertex id
495 if (!ctx->is_gs_copy_shader) {
496 arg_types[arg_idx++] = ctx->i32; // rel auto id
497 arg_types[arg_idx++] = ctx->i32; // vs prim id
498 arg_types[arg_idx++] = ctx->i32; // instance id
499 }
500 break;
501 case MESA_SHADER_GEOMETRY:
502 arg_types[arg_idx++] = ctx->i32; // gsvs stride
503 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
504 user_sgpr_count = arg_idx;
505 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
506 arg_types[arg_idx++] = ctx->i32; // wave id
507 sgpr_count = arg_idx;
508 arg_types[arg_idx++] = ctx->i32; // vtx0
509 arg_types[arg_idx++] = ctx->i32; // vtx1
510 arg_types[arg_idx++] = ctx->i32; // prim id
511 arg_types[arg_idx++] = ctx->i32; // vtx2
512 arg_types[arg_idx++] = ctx->i32; // vtx3
513 arg_types[arg_idx++] = ctx->i32; // vtx4
514 arg_types[arg_idx++] = ctx->i32; // vtx5
515 arg_types[arg_idx++] = ctx->i32; // GS instance id
516 break;
517 case MESA_SHADER_FRAGMENT:
518 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
519 user_sgpr_count = arg_idx;
520 arg_types[arg_idx++] = ctx->i32; /* prim mask */
521 sgpr_count = arg_idx;
522 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
523 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
524 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
525 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
526 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
527 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
528 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
529 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
530 arg_types[arg_idx++] = ctx->f32; /* pos x float */
531 arg_types[arg_idx++] = ctx->f32; /* pos y float */
532 arg_types[arg_idx++] = ctx->f32; /* pos z float */
533 arg_types[arg_idx++] = ctx->f32; /* pos w float */
534 arg_types[arg_idx++] = ctx->i32; /* front face */
535 arg_types[arg_idx++] = ctx->i32; /* ancillary */
536 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
537 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
538 break;
539 default:
540 unreachable("Shader stage not implemented");
541 }
542
543 ctx->main_function = create_llvm_function(
544 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
545 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
546 set_llvm_calling_convention(ctx->main_function, ctx->stage);
547
548 ctx->shader_info->num_input_sgprs = 0;
549 ctx->shader_info->num_input_vgprs = 0;
550
551 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
552 for (i = 0; i < user_sgpr_count; i++)
553 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
554
555 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
556 for (; i < sgpr_count; i++)
557 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
558
559 if (ctx->stage != MESA_SHADER_FRAGMENT)
560 for (; i < arg_idx; ++i)
561 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
562
563 arg_idx = 0;
564 user_sgpr_idx = 0;
565
566 if (ctx->options->supports_spill || need_ring_offsets) {
567 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
568 user_sgpr_idx += 2;
569 if (ctx->options->supports_spill) {
570 ctx->ring_offsets = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
571 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
572 NULL, 0, AC_FUNC_ATTR_READNONE);
573 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
574 const_array(ctx->v16i8, 8), "");
575 } else
576 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
577 }
578
579 for (unsigned i = 0; i < num_sets; ++i) {
580 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
581 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
582 user_sgpr_idx += 2;
583 ctx->descriptor_sets[i] =
584 LLVMGetParam(ctx->main_function, arg_idx++);
585 } else
586 ctx->descriptor_sets[i] = NULL;
587 }
588
589 if (need_push_constants) {
590 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
591 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
592 user_sgpr_idx += 2;
593 }
594
595 switch (ctx->stage) {
596 case MESA_SHADER_COMPUTE:
597 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
598 user_sgpr_idx += 3;
599 ctx->num_work_groups =
600 LLVMGetParam(ctx->main_function, arg_idx++);
601 ctx->workgroup_ids =
602 LLVMGetParam(ctx->main_function, arg_idx++);
603 ctx->tg_size =
604 LLVMGetParam(ctx->main_function, arg_idx++);
605 ctx->local_invocation_ids =
606 LLVMGetParam(ctx->main_function, arg_idx++);
607 break;
608 case MESA_SHADER_VERTEX:
609 if (!ctx->is_gs_copy_shader) {
610 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
611 user_sgpr_idx += 2;
612 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
613 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
614 user_sgpr_idx += 3;
615 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
616 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
617 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
618 }
619 if (ctx->options->key.vs.as_es)
620 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
621 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
622 if (!ctx->is_gs_copy_shader) {
623 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
624 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
625 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
626 }
627 break;
628 case MESA_SHADER_GEOMETRY:
629 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
630 user_sgpr_idx += 2;
631 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
632 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
633 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
634 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
635 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
636 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
637 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
638 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
639 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
640 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
641 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
642 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
643 break;
644 case MESA_SHADER_FRAGMENT:
645 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
646 user_sgpr_idx += 2;
647 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
648 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
649 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
650 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
651 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
652 arg_idx++;
653 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
654 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
655 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
656 arg_idx++; /* line stipple */
657 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
658 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
659 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
660 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
661 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
662 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
663 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
664 break;
665 default:
666 unreachable("Shader stage not implemented");
667 }
668 }
669
670 static void setup_types(struct nir_to_llvm_context *ctx)
671 {
672 LLVMValueRef args[4];
673
674 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
675 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
676 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
677 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
678 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
679 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
680 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
681 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
682 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
683 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
684 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
685 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
686 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
687 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
688 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
689 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
690
691 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
692 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
693 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
694 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
695
696 args[0] = ctx->f32zero;
697 args[1] = ctx->f32zero;
698 args[2] = ctx->f32zero;
699 args[3] = ctx->f32one;
700 ctx->v4f32empty = LLVMConstVector(args, 4);
701
702 ctx->uniform_md_kind =
703 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
704 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
705
706 args[0] = LLVMConstReal(ctx->f32, 2.5);
707 }
708
709 static int get_llvm_num_components(LLVMValueRef value)
710 {
711 LLVMTypeRef type = LLVMTypeOf(value);
712 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
713 ? LLVMGetVectorSize(type)
714 : 1;
715 return num_components;
716 }
717
718 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
719 LLVMValueRef value,
720 int index)
721 {
722 int count = get_llvm_num_components(value);
723
724 assert(index < count);
725 if (count == 1)
726 return value;
727
728 return LLVMBuildExtractElement(ctx->builder, value,
729 LLVMConstInt(ctx->i32, index, false), "");
730 }
731
732 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
733 LLVMValueRef value, unsigned count)
734 {
735 unsigned num_components = get_llvm_num_components(value);
736 if (count == num_components)
737 return value;
738
739 LLVMValueRef masks[] = {
740 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
741 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
742
743 if (count == 1)
744 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
745 "");
746
747 LLVMValueRef swizzle = LLVMConstVector(masks, count);
748 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
749 }
750
751 static void
752 build_store_values_extended(struct nir_to_llvm_context *ctx,
753 LLVMValueRef *values,
754 unsigned value_count,
755 unsigned value_stride,
756 LLVMValueRef vec)
757 {
758 LLVMBuilderRef builder = ctx->builder;
759 unsigned i;
760
761 if (value_count == 1) {
762 LLVMBuildStore(builder, vec, values[0]);
763 return;
764 }
765
766 for (i = 0; i < value_count; i++) {
767 LLVMValueRef ptr = values[i * value_stride];
768 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
769 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
770 LLVMBuildStore(builder, value, ptr);
771 }
772 }
773
774 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
775 nir_ssa_def *def)
776 {
777 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
778 if (def->num_components > 1) {
779 type = LLVMVectorType(type, def->num_components);
780 }
781 return type;
782 }
783
784 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
785 {
786 assert(src.is_ssa);
787 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
788 return (LLVMValueRef)entry->data;
789 }
790
791
792 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
793 struct nir_block *b)
794 {
795 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
796 return (LLVMBasicBlockRef)entry->data;
797 }
798
799 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
800 nir_alu_src src,
801 unsigned num_components)
802 {
803 LLVMValueRef value = get_src(ctx, src.src);
804 bool need_swizzle = false;
805
806 assert(value);
807 LLVMTypeRef type = LLVMTypeOf(value);
808 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
809 ? LLVMGetVectorSize(type)
810 : 1;
811
812 for (unsigned i = 0; i < num_components; ++i) {
813 assert(src.swizzle[i] < src_components);
814 if (src.swizzle[i] != i)
815 need_swizzle = true;
816 }
817
818 if (need_swizzle || num_components != src_components) {
819 LLVMValueRef masks[] = {
820 LLVMConstInt(ctx->i32, src.swizzle[0], false),
821 LLVMConstInt(ctx->i32, src.swizzle[1], false),
822 LLVMConstInt(ctx->i32, src.swizzle[2], false),
823 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
824
825 if (src_components > 1 && num_components == 1) {
826 value = LLVMBuildExtractElement(ctx->builder, value,
827 masks[0], "");
828 } else if (src_components == 1 && num_components > 1) {
829 LLVMValueRef values[] = {value, value, value, value};
830 value = ac_build_gather_values(&ctx->ac, values, num_components);
831 } else {
832 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
833 value = LLVMBuildShuffleVector(ctx->builder, value, value,
834 swizzle, "");
835 }
836 }
837 assert(!src.negate);
838 assert(!src.abs);
839 return value;
840 }
841
842 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
843 LLVMIntPredicate pred, LLVMValueRef src0,
844 LLVMValueRef src1)
845 {
846 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
847 return LLVMBuildSelect(ctx->builder, result,
848 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
849 LLVMConstInt(ctx->i32, 0, false), "");
850 }
851
852 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
853 LLVMRealPredicate pred, LLVMValueRef src0,
854 LLVMValueRef src1)
855 {
856 LLVMValueRef result;
857 src0 = to_float(ctx, src0);
858 src1 = to_float(ctx, src1);
859 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
860 return LLVMBuildSelect(ctx->builder, result,
861 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
862 LLVMConstInt(ctx->i32, 0, false), "");
863 }
864
865 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
866 const char *intrin,
867 LLVMTypeRef result_type,
868 LLVMValueRef src0)
869 {
870 char name[64];
871 LLVMValueRef params[] = {
872 to_float(ctx, src0),
873 };
874
875 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
876 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
877 }
878
879 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
880 const char *intrin,
881 LLVMTypeRef result_type,
882 LLVMValueRef src0, LLVMValueRef src1)
883 {
884 char name[64];
885 LLVMValueRef params[] = {
886 to_float(ctx, src0),
887 to_float(ctx, src1),
888 };
889
890 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
891 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
892 }
893
894 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
895 const char *intrin,
896 LLVMTypeRef result_type,
897 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
898 {
899 char name[64];
900 LLVMValueRef params[] = {
901 to_float(ctx, src0),
902 to_float(ctx, src1),
903 to_float(ctx, src2),
904 };
905
906 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
907 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
908 }
909
910 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
911 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
912 {
913 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
914 ctx->i32zero, "");
915 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
916 }
917
918 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
919 LLVMValueRef src0)
920 {
921 LLVMValueRef params[2] = {
922 src0,
923
924 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
925 * add special code to check for x=0. The reason is that
926 * the LLVM behavior for x=0 is different from what we
927 * need here.
928 *
929 * The hardware already implements the correct behavior.
930 */
931 LLVMConstInt(ctx->i32, 1, false),
932 };
933 return ac_emit_llvm_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
934 }
935
936 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
937 LLVMValueRef src0)
938 {
939 return ac_emit_imsb(&ctx->ac, src0, ctx->i32);
940 }
941
942 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
943 LLVMValueRef src0)
944 {
945 return ac_emit_umsb(&ctx->ac, src0, ctx->i32);
946 }
947
948 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
949 LLVMIntPredicate pred,
950 LLVMValueRef src0, LLVMValueRef src1)
951 {
952 return LLVMBuildSelect(ctx->builder,
953 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
954 src0,
955 src1, "");
956
957 }
958 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
959 LLVMValueRef src0)
960 {
961 return emit_minmax_int(ctx, LLVMIntSGT, src0,
962 LLVMBuildNeg(ctx->builder, src0, ""));
963 }
964
965 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
966 LLVMValueRef src0)
967 {
968 LLVMValueRef cmp, val;
969
970 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
971 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
972 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
973 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
974 return val;
975 }
976
977 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
978 LLVMValueRef src0)
979 {
980 LLVMValueRef cmp, val;
981
982 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
983 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
984 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
985 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
986 return val;
987 }
988
989 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
990 LLVMValueRef src0)
991 {
992 const char *intr = "llvm.floor.f32";
993 LLVMValueRef fsrc0 = to_float(ctx, src0);
994 LLVMValueRef params[] = {
995 fsrc0,
996 };
997 LLVMValueRef floor = ac_emit_llvm_intrinsic(&ctx->ac, intr,
998 ctx->f32, params, 1,
999 AC_FUNC_ATTR_READNONE);
1000 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1001 }
1002
1003 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1004 const char *intrin,
1005 LLVMValueRef src0, LLVMValueRef src1)
1006 {
1007 LLVMTypeRef ret_type;
1008 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1009 LLVMValueRef res;
1010 LLVMValueRef params[] = { src0, src1 };
1011 ret_type = LLVMStructTypeInContext(ctx->context, types,
1012 2, true);
1013
1014 res = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ret_type,
1015 params, 2, AC_FUNC_ATTR_READNONE);
1016
1017 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1018 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1019 return res;
1020 }
1021
1022 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1023 LLVMValueRef src0)
1024 {
1025 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1026 }
1027
1028 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1029 LLVMValueRef src0, LLVMValueRef src1)
1030 {
1031 LLVMValueRef dst64, result;
1032 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1033 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1034
1035 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1036 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1037 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1038 return result;
1039 }
1040
1041 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1042 LLVMValueRef src0, LLVMValueRef src1)
1043 {
1044 LLVMValueRef dst64, result;
1045 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1046 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1047
1048 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1049 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1050 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1051 return result;
1052 }
1053
1054 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1055 const char *intrin, unsigned attr_mask,
1056 LLVMValueRef srcs[3])
1057 {
1058 LLVMValueRef result;
1059 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1060 result = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->i32, srcs, 3,
1061 AC_FUNC_ATTR_READNONE | attr_mask);
1062
1063 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1064 return result;
1065 }
1066
1067 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1068 LLVMValueRef src0, LLVMValueRef src1,
1069 LLVMValueRef src2, LLVMValueRef src3)
1070 {
1071 LLVMValueRef bfi_args[3], result;
1072
1073 bfi_args[0] = LLVMBuildShl(ctx->builder,
1074 LLVMBuildSub(ctx->builder,
1075 LLVMBuildShl(ctx->builder,
1076 ctx->i32one,
1077 src3, ""),
1078 ctx->i32one, ""),
1079 src2, "");
1080 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1081 bfi_args[2] = src0;
1082
1083 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1084
1085 /* Calculate:
1086 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1087 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1088 */
1089 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1090 LLVMBuildAnd(ctx->builder, bfi_args[0],
1091 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1092
1093 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1094 return result;
1095 }
1096
1097 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1098 LLVMValueRef src0)
1099 {
1100 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1101 int i;
1102 LLVMValueRef comp[2];
1103
1104 src0 = to_float(ctx, src0);
1105 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1106 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1107 for (i = 0; i < 2; i++) {
1108 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1109 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1110 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1111 }
1112
1113 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1114 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1115
1116 return comp[0];
1117 }
1118
1119 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1120 LLVMValueRef src0)
1121 {
1122 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1123 LLVMValueRef temps[2], result, val;
1124 int i;
1125
1126 for (i = 0; i < 2; i++) {
1127 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1128 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1129 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1130 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1131 }
1132
1133 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1134 ctx->i32zero, "");
1135 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1136 ctx->i32one, "");
1137 return result;
1138 }
1139
1140 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1141 nir_op op,
1142 LLVMValueRef src0)
1143 {
1144 unsigned mask;
1145 int idx;
1146 LLVMValueRef result;
1147 ctx->has_ddxy = true;
1148
1149 if (!ctx->lds && !ctx->has_ds_bpermute)
1150 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1151 LLVMArrayType(ctx->i32, 64),
1152 "ddxy_lds", LOCAL_ADDR_SPACE);
1153
1154 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1155 mask = AC_TID_MASK_LEFT;
1156 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1157 mask = AC_TID_MASK_TOP;
1158 else
1159 mask = AC_TID_MASK_TOP_LEFT;
1160
1161 /* for DDX we want to next X pixel, DDY next Y pixel. */
1162 if (op == nir_op_fddx_fine ||
1163 op == nir_op_fddx_coarse ||
1164 op == nir_op_fddx)
1165 idx = 1;
1166 else
1167 idx = 2;
1168
1169 result = ac_emit_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1170 mask, idx, ctx->lds,
1171 src0);
1172 return result;
1173 }
1174
1175 /*
1176 * this takes an I,J coordinate pair,
1177 * and works out the X and Y derivatives.
1178 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1179 */
1180 static LLVMValueRef emit_ddxy_interp(
1181 struct nir_to_llvm_context *ctx,
1182 LLVMValueRef interp_ij)
1183 {
1184 LLVMValueRef result[4], a;
1185 unsigned i;
1186
1187 for (i = 0; i < 2; i++) {
1188 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1189 LLVMConstInt(ctx->i32, i, false), "");
1190 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1191 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1192 }
1193 return ac_build_gather_values(&ctx->ac, result, 4);
1194 }
1195
1196 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1197 {
1198 LLVMValueRef src[4], result = NULL;
1199 unsigned num_components = instr->dest.dest.ssa.num_components;
1200 unsigned src_components;
1201 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1202
1203 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1204 switch (instr->op) {
1205 case nir_op_vec2:
1206 case nir_op_vec3:
1207 case nir_op_vec4:
1208 src_components = 1;
1209 break;
1210 case nir_op_pack_half_2x16:
1211 src_components = 2;
1212 break;
1213 case nir_op_unpack_half_2x16:
1214 src_components = 1;
1215 break;
1216 default:
1217 src_components = num_components;
1218 break;
1219 }
1220 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1221 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1222
1223 switch (instr->op) {
1224 case nir_op_fmov:
1225 case nir_op_imov:
1226 result = src[0];
1227 break;
1228 case nir_op_fneg:
1229 src[0] = to_float(ctx, src[0]);
1230 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1231 break;
1232 case nir_op_ineg:
1233 result = LLVMBuildNeg(ctx->builder, src[0], "");
1234 break;
1235 case nir_op_inot:
1236 result = LLVMBuildNot(ctx->builder, src[0], "");
1237 break;
1238 case nir_op_iadd:
1239 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1240 break;
1241 case nir_op_fadd:
1242 src[0] = to_float(ctx, src[0]);
1243 src[1] = to_float(ctx, src[1]);
1244 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1245 break;
1246 case nir_op_fsub:
1247 src[0] = to_float(ctx, src[0]);
1248 src[1] = to_float(ctx, src[1]);
1249 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1250 break;
1251 case nir_op_isub:
1252 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1253 break;
1254 case nir_op_imul:
1255 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1256 break;
1257 case nir_op_imod:
1258 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1259 break;
1260 case nir_op_umod:
1261 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1262 break;
1263 case nir_op_fmod:
1264 src[0] = to_float(ctx, src[0]);
1265 src[1] = to_float(ctx, src[1]);
1266 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1267 result = emit_intrin_1f_param(ctx, "llvm.floor",
1268 to_float_type(ctx, def_type), result);
1269 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1270 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1271 break;
1272 case nir_op_frem:
1273 src[0] = to_float(ctx, src[0]);
1274 src[1] = to_float(ctx, src[1]);
1275 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1276 break;
1277 case nir_op_irem:
1278 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1279 break;
1280 case nir_op_idiv:
1281 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1282 break;
1283 case nir_op_udiv:
1284 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1285 break;
1286 case nir_op_fmul:
1287 src[0] = to_float(ctx, src[0]);
1288 src[1] = to_float(ctx, src[1]);
1289 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1290 break;
1291 case nir_op_fdiv:
1292 src[0] = to_float(ctx, src[0]);
1293 src[1] = to_float(ctx, src[1]);
1294 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1295 break;
1296 case nir_op_frcp:
1297 src[0] = to_float(ctx, src[0]);
1298 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, src[0]);
1299 break;
1300 case nir_op_iand:
1301 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1302 break;
1303 case nir_op_ior:
1304 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1305 break;
1306 case nir_op_ixor:
1307 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1308 break;
1309 case nir_op_ishl:
1310 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1311 break;
1312 case nir_op_ishr:
1313 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1314 break;
1315 case nir_op_ushr:
1316 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1317 break;
1318 case nir_op_ilt:
1319 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1320 break;
1321 case nir_op_ine:
1322 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1323 break;
1324 case nir_op_ieq:
1325 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1326 break;
1327 case nir_op_ige:
1328 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1329 break;
1330 case nir_op_ult:
1331 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1332 break;
1333 case nir_op_uge:
1334 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1335 break;
1336 case nir_op_feq:
1337 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1338 break;
1339 case nir_op_fne:
1340 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1341 break;
1342 case nir_op_flt:
1343 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1344 break;
1345 case nir_op_fge:
1346 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1347 break;
1348 case nir_op_fabs:
1349 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1350 to_float_type(ctx, def_type), src[0]);
1351 break;
1352 case nir_op_iabs:
1353 result = emit_iabs(ctx, src[0]);
1354 break;
1355 case nir_op_imax:
1356 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1357 break;
1358 case nir_op_imin:
1359 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1360 break;
1361 case nir_op_umax:
1362 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1363 break;
1364 case nir_op_umin:
1365 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1366 break;
1367 case nir_op_isign:
1368 result = emit_isign(ctx, src[0]);
1369 break;
1370 case nir_op_fsign:
1371 src[0] = to_float(ctx, src[0]);
1372 result = emit_fsign(ctx, src[0]);
1373 break;
1374 case nir_op_ffloor:
1375 result = emit_intrin_1f_param(ctx, "llvm.floor",
1376 to_float_type(ctx, def_type), src[0]);
1377 break;
1378 case nir_op_ftrunc:
1379 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1380 to_float_type(ctx, def_type), src[0]);
1381 break;
1382 case nir_op_fceil:
1383 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1384 to_float_type(ctx, def_type), src[0]);
1385 break;
1386 case nir_op_fround_even:
1387 result = emit_intrin_1f_param(ctx, "llvm.rint",
1388 to_float_type(ctx, def_type),src[0]);
1389 break;
1390 case nir_op_ffract:
1391 result = emit_ffract(ctx, src[0]);
1392 break;
1393 case nir_op_fsin:
1394 result = emit_intrin_1f_param(ctx, "llvm.sin",
1395 to_float_type(ctx, def_type), src[0]);
1396 break;
1397 case nir_op_fcos:
1398 result = emit_intrin_1f_param(ctx, "llvm.cos",
1399 to_float_type(ctx, def_type), src[0]);
1400 break;
1401 case nir_op_fsqrt:
1402 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1403 to_float_type(ctx, def_type), src[0]);
1404 break;
1405 case nir_op_fexp2:
1406 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1407 to_float_type(ctx, def_type), src[0]);
1408 break;
1409 case nir_op_flog2:
1410 result = emit_intrin_1f_param(ctx, "llvm.log2",
1411 to_float_type(ctx, def_type), src[0]);
1412 break;
1413 case nir_op_frsq:
1414 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1415 to_float_type(ctx, def_type), src[0]);
1416 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, result);
1417 break;
1418 case nir_op_fpow:
1419 result = emit_intrin_2f_param(ctx, "llvm.pow",
1420 to_float_type(ctx, def_type), src[0], src[1]);
1421 break;
1422 case nir_op_fmax:
1423 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1424 to_float_type(ctx, def_type), src[0], src[1]);
1425 break;
1426 case nir_op_fmin:
1427 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1428 to_float_type(ctx, def_type), src[0], src[1]);
1429 break;
1430 case nir_op_ffma:
1431 result = emit_intrin_3f_param(ctx, "llvm.fma",
1432 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1433 break;
1434 case nir_op_ibitfield_extract:
1435 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.i32",
1436 AC_FUNC_ATTR_LEGACY, src);
1437 break;
1438 case nir_op_ubitfield_extract:
1439 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.u32",
1440 AC_FUNC_ATTR_LEGACY, src);
1441 break;
1442 case nir_op_bitfield_insert:
1443 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1444 break;
1445 case nir_op_bitfield_reverse:
1446 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1447 break;
1448 case nir_op_bit_count:
1449 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1450 break;
1451 case nir_op_vec2:
1452 case nir_op_vec3:
1453 case nir_op_vec4:
1454 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1455 src[i] = to_integer(ctx, src[i]);
1456 result = ac_build_gather_values(&ctx->ac, src, num_components);
1457 break;
1458 case nir_op_d2i:
1459 case nir_op_f2i:
1460 src[0] = to_float(ctx, src[0]);
1461 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1462 break;
1463 case nir_op_d2u:
1464 case nir_op_f2u:
1465 src[0] = to_float(ctx, src[0]);
1466 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1467 break;
1468 case nir_op_i2d:
1469 case nir_op_i2f:
1470 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1471 break;
1472 case nir_op_u2d:
1473 case nir_op_u2f:
1474 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1475 break;
1476 case nir_op_f2d:
1477 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1478 break;
1479 case nir_op_d2f:
1480 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1481 break;
1482 case nir_op_u2u32:
1483 case nir_op_u2u64:
1484 case nir_op_u2i32:
1485 case nir_op_u2i64:
1486 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1487 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1488 else
1489 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1490 break;
1491 case nir_op_i2u32:
1492 case nir_op_i2u64:
1493 case nir_op_i2i32:
1494 case nir_op_i2i64:
1495 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1496 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1497 else
1498 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1499 break;
1500 case nir_op_bcsel:
1501 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1502 break;
1503 case nir_op_find_lsb:
1504 result = emit_find_lsb(ctx, src[0]);
1505 break;
1506 case nir_op_ufind_msb:
1507 result = emit_ufind_msb(ctx, src[0]);
1508 break;
1509 case nir_op_ifind_msb:
1510 result = emit_ifind_msb(ctx, src[0]);
1511 break;
1512 case nir_op_uadd_carry:
1513 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1514 break;
1515 case nir_op_usub_borrow:
1516 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1517 break;
1518 case nir_op_b2f:
1519 result = emit_b2f(ctx, src[0]);
1520 break;
1521 case nir_op_fquantize2f16:
1522 src[0] = to_float(ctx, src[0]);
1523 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1524 /* need to convert back up to f32 */
1525 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1526 break;
1527 case nir_op_umul_high:
1528 result = emit_umul_high(ctx, src[0], src[1]);
1529 break;
1530 case nir_op_imul_high:
1531 result = emit_imul_high(ctx, src[0], src[1]);
1532 break;
1533 case nir_op_pack_half_2x16:
1534 result = emit_pack_half_2x16(ctx, src[0]);
1535 break;
1536 case nir_op_unpack_half_2x16:
1537 result = emit_unpack_half_2x16(ctx, src[0]);
1538 break;
1539 case nir_op_fddx:
1540 case nir_op_fddy:
1541 case nir_op_fddx_fine:
1542 case nir_op_fddy_fine:
1543 case nir_op_fddx_coarse:
1544 case nir_op_fddy_coarse:
1545 result = emit_ddxy(ctx, instr->op, src[0]);
1546 break;
1547 default:
1548 fprintf(stderr, "Unknown NIR alu instr: ");
1549 nir_print_instr(&instr->instr, stderr);
1550 fprintf(stderr, "\n");
1551 abort();
1552 }
1553
1554 if (result) {
1555 assert(instr->dest.dest.is_ssa);
1556 result = to_integer(ctx, result);
1557 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1558 result);
1559 }
1560 }
1561
1562 static void visit_load_const(struct nir_to_llvm_context *ctx,
1563 nir_load_const_instr *instr)
1564 {
1565 LLVMValueRef values[4], value = NULL;
1566 LLVMTypeRef element_type =
1567 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1568
1569 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1570 switch (instr->def.bit_size) {
1571 case 32:
1572 values[i] = LLVMConstInt(element_type,
1573 instr->value.u32[i], false);
1574 break;
1575 case 64:
1576 values[i] = LLVMConstInt(element_type,
1577 instr->value.u64[i], false);
1578 break;
1579 default:
1580 fprintf(stderr,
1581 "unsupported nir load_const bit_size: %d\n",
1582 instr->def.bit_size);
1583 abort();
1584 }
1585 }
1586 if (instr->def.num_components > 1) {
1587 value = LLVMConstVector(values, instr->def.num_components);
1588 } else
1589 value = values[0];
1590
1591 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1592 }
1593
1594 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1595 LLVMTypeRef type)
1596 {
1597 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1598 return LLVMBuildBitCast(ctx->builder, ptr,
1599 LLVMPointerType(type, addr_space), "");
1600 }
1601
1602 static LLVMValueRef
1603 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1604 {
1605 LLVMValueRef size =
1606 LLVMBuildExtractElement(ctx->builder, descriptor,
1607 LLVMConstInt(ctx->i32, 2, false), "");
1608
1609 /* VI only */
1610 if (ctx->options->chip_class >= VI && in_elements) {
1611 /* On VI, the descriptor contains the size in bytes,
1612 * but TXQ must return the size in elements.
1613 * The stride is always non-zero for resources using TXQ.
1614 */
1615 LLVMValueRef stride =
1616 LLVMBuildExtractElement(ctx->builder, descriptor,
1617 LLVMConstInt(ctx->i32, 1, false), "");
1618 stride = LLVMBuildLShr(ctx->builder, stride,
1619 LLVMConstInt(ctx->i32, 16, false), "");
1620 stride = LLVMBuildAnd(ctx->builder, stride,
1621 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1622
1623 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1624 }
1625 return size;
1626 }
1627
1628 /**
1629 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1630 * intrinsic names).
1631 */
1632 static void build_int_type_name(
1633 LLVMTypeRef type,
1634 char *buf, unsigned bufsize)
1635 {
1636 assert(bufsize >= 6);
1637
1638 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1639 snprintf(buf, bufsize, "v%ui32",
1640 LLVMGetVectorSize(type));
1641 else
1642 strcpy(buf, "i32");
1643 }
1644
1645 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1646 struct ac_tex_info *tinfo,
1647 nir_tex_instr *instr,
1648 const char *intr_name,
1649 unsigned coord_vgpr_index)
1650 {
1651 LLVMValueRef coord = tinfo->args[0];
1652 LLVMValueRef half_texel[2];
1653 int c;
1654
1655 //TODO Rect
1656 {
1657 LLVMValueRef txq_args[10];
1658 int txq_arg_count = 0;
1659 LLVMValueRef size;
1660 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1661 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, false);
1662 txq_args[txq_arg_count++] = tinfo->args[1];
1663 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0xf, 0); /* dmask */
1664 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* unorm */
1665 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
1666 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
1667 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
1668 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
1669 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
1670 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
1671 size = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
1672 txq_args, txq_arg_count,
1673 AC_FUNC_ATTR_READNONE |
1674 AC_FUNC_ATTR_LEGACY);
1675
1676 for (c = 0; c < 2; c++) {
1677 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1678 LLVMConstInt(ctx->i32, c, false), "");
1679 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1680 half_texel[c] = ac_emit_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1681 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1682 LLVMConstReal(ctx->f32, -0.5), "");
1683 }
1684 }
1685
1686 for (c = 0; c < 2; c++) {
1687 LLVMValueRef tmp;
1688 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1689 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1690 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1691 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1692 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1693 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1694 }
1695
1696 tinfo->args[0] = coord;
1697 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1698 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND |
1699 AC_FUNC_ATTR_LEGACY);
1700
1701 }
1702
1703 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1704 nir_tex_instr *instr,
1705 struct ac_tex_info *tinfo)
1706 {
1707 const char *name = "llvm.SI.image.sample";
1708 const char *infix = "";
1709 char intr_name[127];
1710 char type[64];
1711 bool is_shadow = instr->is_shadow;
1712 bool has_offset = tinfo->has_offset;
1713 switch (instr->op) {
1714 case nir_texop_txf:
1715 case nir_texop_txf_ms:
1716 case nir_texop_samples_identical:
1717 name = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? "llvm.SI.image.load" :
1718 instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? "llvm.SI.vs.load.input" :
1719 "llvm.SI.image.load.mip";
1720 is_shadow = false;
1721 has_offset = false;
1722 break;
1723 case nir_texop_txb:
1724 infix = ".b";
1725 break;
1726 case nir_texop_txl:
1727 infix = ".l";
1728 break;
1729 case nir_texop_txs:
1730 name = "llvm.SI.getresinfo";
1731 break;
1732 case nir_texop_query_levels:
1733 name = "llvm.SI.getresinfo";
1734 break;
1735 case nir_texop_tex:
1736 if (ctx->stage != MESA_SHADER_FRAGMENT)
1737 infix = ".lz";
1738 break;
1739 case nir_texop_txd:
1740 infix = ".d";
1741 break;
1742 case nir_texop_tg4:
1743 name = "llvm.SI.gather4";
1744 infix = ".lz";
1745 break;
1746 case nir_texop_lod:
1747 name = "llvm.SI.getlod";
1748 is_shadow = false;
1749 has_offset = false;
1750 break;
1751 default:
1752 break;
1753 }
1754
1755 build_int_type_name(LLVMTypeOf(tinfo->args[0]), type, sizeof(type));
1756 sprintf(intr_name, "%s%s%s%s.%s", name, is_shadow ? ".c" : "", infix,
1757 has_offset ? ".o" : "", type);
1758
1759 if (instr->op == nir_texop_tg4) {
1760 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1761 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1762 return radv_lower_gather4_integer(ctx, tinfo, instr, intr_name,
1763 (int)has_offset + (int)is_shadow);
1764 }
1765 }
1766 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1767 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND |
1768 AC_FUNC_ATTR_LEGACY);
1769
1770 }
1771
1772 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1773 nir_intrinsic_instr *instr)
1774 {
1775 LLVMValueRef index = get_src(ctx, instr->src[0]);
1776 unsigned desc_set = nir_intrinsic_desc_set(instr);
1777 unsigned binding = nir_intrinsic_binding(instr);
1778 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1779 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
1780 unsigned base_offset = layout->binding[binding].offset;
1781 LLVMValueRef offset, stride;
1782
1783 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1784 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1785 desc_ptr = ctx->push_constants;
1786 base_offset = ctx->options->layout->push_constant_size;
1787 base_offset += 16 * layout->binding[binding].dynamic_offset_offset;
1788 stride = LLVMConstInt(ctx->i32, 16, false);
1789 } else
1790 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1791
1792 offset = LLVMConstInt(ctx->i32, base_offset, false);
1793 index = LLVMBuildMul(ctx->builder, index, stride, "");
1794 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1795
1796 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1797 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1798 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1799
1800 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1801 }
1802
1803 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1804 nir_intrinsic_instr *instr)
1805 {
1806 LLVMValueRef ptr, addr;
1807
1808 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1809 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1810
1811 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
1812 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1813
1814 return LLVMBuildLoad(ctx->builder, ptr, "");
1815 }
1816
1817 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1818 nir_intrinsic_instr *instr)
1819 {
1820 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1821
1822 return get_buffer_size(ctx, desc, false);
1823 }
1824 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1825 nir_intrinsic_instr *instr)
1826 {
1827 const char *store_name;
1828 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
1829 LLVMTypeRef data_type = ctx->f32;
1830 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
1831 int components_32bit = elem_size_mult * instr->num_components;
1832 unsigned writemask = nir_intrinsic_write_mask(instr);
1833 LLVMValueRef base_data, base_offset;
1834 LLVMValueRef params[6];
1835
1836 if (ctx->stage == MESA_SHADER_FRAGMENT)
1837 ctx->shader_info->fs.writes_memory = true;
1838
1839 params[1] = get_src(ctx, instr->src[1]);
1840 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1841 params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
1842 params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1843
1844 if (components_32bit > 1)
1845 data_type = LLVMVectorType(ctx->f32, components_32bit);
1846
1847 base_data = to_float(ctx, src_data);
1848 base_data = trim_vector(ctx, base_data, instr->num_components);
1849 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1850 data_type, "");
1851 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1852 while (writemask) {
1853 int start, count;
1854 LLVMValueRef data;
1855 LLVMValueRef offset;
1856 LLVMValueRef tmp;
1857 u_bit_scan_consecutive_range(&writemask, &start, &count);
1858
1859 /* Due to an LLVM limitation, split 3-element writes
1860 * into a 2-element and a 1-element write. */
1861 if (count == 3) {
1862 writemask |= 1 << (start + 2);
1863 count = 2;
1864 }
1865
1866 start *= elem_size_mult;
1867 count *= elem_size_mult;
1868
1869 if (count > 4) {
1870 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
1871 count = 4;
1872 }
1873
1874 if (count == 4) {
1875 store_name = "llvm.amdgcn.buffer.store.v4f32";
1876 data = base_data;
1877 } else if (count == 2) {
1878 tmp = LLVMBuildExtractElement(ctx->builder,
1879 base_data, LLVMConstInt(ctx->i32, start, false), "");
1880 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
1881 ctx->i32zero, "");
1882
1883 tmp = LLVMBuildExtractElement(ctx->builder,
1884 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
1885 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
1886 ctx->i32one, "");
1887 store_name = "llvm.amdgcn.buffer.store.v2f32";
1888
1889 } else {
1890 assert(count == 1);
1891 if (get_llvm_num_components(base_data) > 1)
1892 data = LLVMBuildExtractElement(ctx->builder, base_data,
1893 LLVMConstInt(ctx->i32, start, false), "");
1894 else
1895 data = base_data;
1896 store_name = "llvm.amdgcn.buffer.store.f32";
1897 }
1898
1899 offset = base_offset;
1900 if (start != 0) {
1901 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
1902 }
1903 params[0] = data;
1904 params[3] = offset;
1905 ac_emit_llvm_intrinsic(&ctx->ac, store_name,
1906 ctx->voidt, params, 6, 0);
1907 }
1908 }
1909
1910 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
1911 nir_intrinsic_instr *instr)
1912 {
1913 const char *name;
1914 LLVMValueRef params[6];
1915 int arg_count = 0;
1916 if (ctx->stage == MESA_SHADER_FRAGMENT)
1917 ctx->shader_info->fs.writes_memory = true;
1918
1919 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
1920 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
1921 }
1922 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
1923 params[arg_count++] = get_src(ctx, instr->src[0]);
1924 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1925 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
1926 params[arg_count++] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1927
1928 switch (instr->intrinsic) {
1929 case nir_intrinsic_ssbo_atomic_add:
1930 name = "llvm.amdgcn.buffer.atomic.add";
1931 break;
1932 case nir_intrinsic_ssbo_atomic_imin:
1933 name = "llvm.amdgcn.buffer.atomic.smin";
1934 break;
1935 case nir_intrinsic_ssbo_atomic_umin:
1936 name = "llvm.amdgcn.buffer.atomic.umin";
1937 break;
1938 case nir_intrinsic_ssbo_atomic_imax:
1939 name = "llvm.amdgcn.buffer.atomic.smax";
1940 break;
1941 case nir_intrinsic_ssbo_atomic_umax:
1942 name = "llvm.amdgcn.buffer.atomic.umax";
1943 break;
1944 case nir_intrinsic_ssbo_atomic_and:
1945 name = "llvm.amdgcn.buffer.atomic.and";
1946 break;
1947 case nir_intrinsic_ssbo_atomic_or:
1948 name = "llvm.amdgcn.buffer.atomic.or";
1949 break;
1950 case nir_intrinsic_ssbo_atomic_xor:
1951 name = "llvm.amdgcn.buffer.atomic.xor";
1952 break;
1953 case nir_intrinsic_ssbo_atomic_exchange:
1954 name = "llvm.amdgcn.buffer.atomic.swap";
1955 break;
1956 case nir_intrinsic_ssbo_atomic_comp_swap:
1957 name = "llvm.amdgcn.buffer.atomic.cmpswap";
1958 break;
1959 default:
1960 abort();
1961 }
1962
1963 return ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
1964 }
1965
1966 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
1967 nir_intrinsic_instr *instr)
1968 {
1969 LLVMValueRef results[2];
1970 int load_components;
1971 int num_components = instr->num_components;
1972 if (instr->dest.ssa.bit_size == 64)
1973 num_components *= 2;
1974
1975 for (int i = 0; i < num_components; i += load_components) {
1976 load_components = MIN2(num_components - i, 4);
1977 const char *load_name;
1978 LLVMTypeRef data_type = ctx->f32;
1979 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
1980 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
1981
1982 if (load_components == 3)
1983 data_type = LLVMVectorType(ctx->f32, 4);
1984 else if (load_components > 1)
1985 data_type = LLVMVectorType(ctx->f32, load_components);
1986
1987 if (load_components >= 3)
1988 load_name = "llvm.amdgcn.buffer.load.v4f32";
1989 else if (load_components == 2)
1990 load_name = "llvm.amdgcn.buffer.load.v2f32";
1991 else if (load_components == 1)
1992 load_name = "llvm.amdgcn.buffer.load.f32";
1993 else
1994 unreachable("unhandled number of components");
1995
1996 LLVMValueRef params[] = {
1997 get_src(ctx, instr->src[0]),
1998 LLVMConstInt(ctx->i32, 0, false),
1999 offset,
2000 LLVMConstInt(ctx->i1, 0, false),
2001 LLVMConstInt(ctx->i1, 0, false),
2002 };
2003
2004 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2005
2006 }
2007
2008 LLVMValueRef ret = results[0];
2009 if (num_components > 4 || num_components == 3) {
2010 LLVMValueRef masks[] = {
2011 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2012 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2013 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2014 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2015 };
2016
2017 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2018 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2019 results[num_components > 4 ? 1 : 0], swizzle, "");
2020 }
2021
2022 return LLVMBuildBitCast(ctx->builder, ret,
2023 get_def_type(ctx, &instr->dest.ssa), "");
2024 }
2025
2026 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2027 nir_intrinsic_instr *instr)
2028 {
2029 LLVMValueRef results[8], ret;
2030 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2031 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2032 int num_components = instr->num_components;
2033
2034 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2035
2036 if (instr->dest.ssa.bit_size == 64)
2037 num_components *= 2;
2038
2039 for (unsigned i = 0; i < num_components; ++i) {
2040 LLVMValueRef params[] = {
2041 rsrc,
2042 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2043 offset, "")
2044 };
2045 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2046 params, 2,
2047 AC_FUNC_ATTR_READNONE |
2048 AC_FUNC_ATTR_LEGACY);
2049 }
2050
2051
2052 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2053 return LLVMBuildBitCast(ctx->builder, ret,
2054 get_def_type(ctx, &instr->dest.ssa), "");
2055 }
2056
2057 static void
2058 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2059 bool vs_in, unsigned *vertex_index_out,
2060 unsigned *const_out, LLVMValueRef *indir_out)
2061 {
2062 unsigned const_offset = 0;
2063 LLVMValueRef offset = NULL;
2064
2065 if (vertex_index_out != NULL) {
2066 tail = tail->child;
2067 nir_deref_array *deref_array = nir_deref_as_array(tail);
2068 *vertex_index_out = deref_array->base_offset;
2069 }
2070
2071 while (tail->child != NULL) {
2072 const struct glsl_type *parent_type = tail->type;
2073 tail = tail->child;
2074
2075 if (tail->deref_type == nir_deref_type_array) {
2076 nir_deref_array *deref_array = nir_deref_as_array(tail);
2077 LLVMValueRef index, stride, local_offset;
2078 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2079
2080 const_offset += size * deref_array->base_offset;
2081 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2082 continue;
2083
2084 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2085 index = get_src(ctx, deref_array->indirect);
2086 stride = LLVMConstInt(ctx->i32, size, 0);
2087 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2088
2089 if (offset)
2090 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2091 else
2092 offset = local_offset;
2093 } else if (tail->deref_type == nir_deref_type_struct) {
2094 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2095
2096 for (unsigned i = 0; i < deref_struct->index; i++) {
2097 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2098 const_offset += glsl_count_attribute_slots(ft, vs_in);
2099 }
2100 } else
2101 unreachable("unsupported deref type");
2102
2103 }
2104
2105 if (const_offset && offset)
2106 offset = LLVMBuildAdd(ctx->builder, offset,
2107 LLVMConstInt(ctx->i32, const_offset, 0),
2108 "");
2109
2110 *const_out = const_offset;
2111 *indir_out = offset;
2112 }
2113
2114 static LLVMValueRef
2115 load_gs_input(struct nir_to_llvm_context *ctx,
2116 nir_intrinsic_instr *instr)
2117 {
2118 LLVMValueRef indir_index, vtx_offset;
2119 unsigned const_index;
2120 LLVMValueRef args[9];
2121 unsigned param, vtx_offset_param;
2122 LLVMValueRef value[4], result;
2123 unsigned vertex_index;
2124 unsigned cull_offset = 0;
2125 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2126 false, &vertex_index,
2127 &const_index, &indir_index);
2128 vtx_offset_param = vertex_index;
2129 assert(vtx_offset_param < 6);
2130 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2131 LLVMConstInt(ctx->i32, 4, false), "");
2132
2133 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2134 if (instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2135 cull_offset += ctx->num_input_clips;
2136 for (unsigned i = 0; i < instr->num_components; i++) {
2137
2138 args[0] = ctx->esgs_ring;
2139 args[1] = vtx_offset;
2140 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index + cull_offset) * 256, false);
2141 args[3] = ctx->i32zero;
2142 args[4] = ctx->i32one; /* OFFEN */
2143 args[5] = ctx->i32zero; /* IDXEN */
2144 args[6] = ctx->i32one; /* GLC */
2145 args[7] = ctx->i32zero; /* SLC */
2146 args[8] = ctx->i32zero; /* TFE */
2147
2148 value[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2149 ctx->i32, args, 9,
2150 AC_FUNC_ATTR_READONLY |
2151 AC_FUNC_ATTR_LEGACY);
2152 }
2153 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2154
2155 return result;
2156 }
2157
2158 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2159 nir_intrinsic_instr *instr)
2160 {
2161 LLVMValueRef values[8];
2162 int idx = instr->variables[0]->var->data.driver_location;
2163 int ve = instr->dest.ssa.num_components;
2164 LLVMValueRef indir_index;
2165 LLVMValueRef ret;
2166 unsigned const_index;
2167 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2168 instr->variables[0]->var->data.mode == nir_var_shader_in;
2169 radv_get_deref_offset(ctx, &instr->variables[0]->deref, vs_in, NULL,
2170 &const_index, &indir_index);
2171
2172 if (instr->dest.ssa.bit_size == 64)
2173 ve *= 2;
2174
2175 switch (instr->variables[0]->var->data.mode) {
2176 case nir_var_shader_in:
2177 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2178 return load_gs_input(ctx, instr);
2179 }
2180 for (unsigned chan = 0; chan < ve; chan++) {
2181 if (indir_index) {
2182 unsigned count = glsl_count_attribute_slots(
2183 instr->variables[0]->var->type,
2184 ctx->stage == MESA_SHADER_VERTEX);
2185 count -= chan / 4;
2186 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2187 &ctx->ac, ctx->inputs + idx + chan, count,
2188 4, false);
2189
2190 values[chan] = LLVMBuildExtractElement(ctx->builder,
2191 tmp_vec,
2192 indir_index, "");
2193 } else
2194 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2195 }
2196 break;
2197 case nir_var_local:
2198 for (unsigned chan = 0; chan < ve; chan++) {
2199 if (indir_index) {
2200 unsigned count = glsl_count_attribute_slots(
2201 instr->variables[0]->var->type, false);
2202 count -= chan / 4;
2203 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2204 &ctx->ac, ctx->locals + idx + chan, count,
2205 4, true);
2206
2207 values[chan] = LLVMBuildExtractElement(ctx->builder,
2208 tmp_vec,
2209 indir_index, "");
2210 } else {
2211 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2212 }
2213 }
2214 break;
2215 case nir_var_shader_out:
2216 for (unsigned chan = 0; chan < ve; chan++) {
2217 if (indir_index) {
2218 unsigned count = glsl_count_attribute_slots(
2219 instr->variables[0]->var->type, false);
2220 count -= chan / 4;
2221 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2222 &ctx->ac, ctx->outputs + idx + chan, count,
2223 4, true);
2224
2225 values[chan] = LLVMBuildExtractElement(ctx->builder,
2226 tmp_vec,
2227 indir_index, "");
2228 } else {
2229 values[chan] = LLVMBuildLoad(ctx->builder,
2230 ctx->outputs[idx + chan + const_index * 4],
2231 "");
2232 }
2233 }
2234 break;
2235 case nir_var_shared: {
2236 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2237 LLVMValueRef derived_ptr;
2238
2239 if (indir_index)
2240 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2241
2242 for (unsigned chan = 0; chan < ve; chan++) {
2243 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2244 if (indir_index)
2245 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2246 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2247
2248 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2249 }
2250 break;
2251 }
2252 default:
2253 unreachable("unhandle variable mode");
2254 }
2255 ret = ac_build_gather_values(&ctx->ac, values, ve);
2256 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2257 }
2258
2259 static void
2260 visit_store_var(struct nir_to_llvm_context *ctx,
2261 nir_intrinsic_instr *instr)
2262 {
2263 LLVMValueRef temp_ptr, value;
2264 int idx = instr->variables[0]->var->data.driver_location;
2265 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2266 int writemask = instr->const_index[0];
2267 LLVMValueRef indir_index;
2268 unsigned const_index;
2269 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2270 NULL, &const_index, &indir_index);
2271
2272 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2273 int old_writemask = writemask;
2274
2275 src = LLVMBuildBitCast(ctx->builder, src,
2276 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2277 "");
2278
2279 writemask = 0;
2280 for (unsigned chan = 0; chan < 4; chan++) {
2281 if (old_writemask & (1 << chan))
2282 writemask |= 3u << (2 * chan);
2283 }
2284 }
2285
2286 switch (instr->variables[0]->var->data.mode) {
2287 case nir_var_shader_out:
2288 for (unsigned chan = 0; chan < 8; chan++) {
2289 int stride = 4;
2290 if (!(writemask & (1 << chan)))
2291 continue;
2292
2293 value = llvm_extract_elem(ctx, src, chan);
2294
2295 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2296 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2297 stride = 1;
2298 if (indir_index) {
2299 unsigned count = glsl_count_attribute_slots(
2300 instr->variables[0]->var->type, false);
2301 count -= chan / 4;
2302 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2303 &ctx->ac, ctx->outputs + idx + chan, count,
2304 stride, true);
2305
2306 if (get_llvm_num_components(tmp_vec) > 1) {
2307 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2308 value, indir_index, "");
2309 } else
2310 tmp_vec = value;
2311 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2312 count, stride, tmp_vec);
2313
2314 } else {
2315 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2316
2317 LLVMBuildStore(ctx->builder, value, temp_ptr);
2318 }
2319 }
2320 break;
2321 case nir_var_local:
2322 for (unsigned chan = 0; chan < 8; chan++) {
2323 if (!(writemask & (1 << chan)))
2324 continue;
2325
2326 value = llvm_extract_elem(ctx, src, chan);
2327 if (indir_index) {
2328 unsigned count = glsl_count_attribute_slots(
2329 instr->variables[0]->var->type, false);
2330 count -= chan / 4;
2331 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2332 &ctx->ac, ctx->locals + idx + chan, count,
2333 4, true);
2334
2335 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2336 value, indir_index, "");
2337 build_store_values_extended(ctx, ctx->locals + idx + chan,
2338 count, 4, tmp_vec);
2339 } else {
2340 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2341
2342 LLVMBuildStore(ctx->builder, value, temp_ptr);
2343 }
2344 }
2345 break;
2346 case nir_var_shared: {
2347 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2348
2349 if (indir_index)
2350 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2351
2352 for (unsigned chan = 0; chan < 8; chan++) {
2353 if (!(writemask & (1 << chan)))
2354 continue;
2355 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2356 LLVMValueRef derived_ptr;
2357
2358 if (indir_index)
2359 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2360
2361 value = llvm_extract_elem(ctx, src, chan);
2362 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2363 LLVMBuildStore(ctx->builder,
2364 to_integer(ctx, value), derived_ptr);
2365 }
2366 break;
2367 }
2368 default:
2369 break;
2370 }
2371 }
2372
2373 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2374 {
2375 switch (dim) {
2376 case GLSL_SAMPLER_DIM_BUF:
2377 return 1;
2378 case GLSL_SAMPLER_DIM_1D:
2379 return array ? 2 : 1;
2380 case GLSL_SAMPLER_DIM_2D:
2381 return array ? 3 : 2;
2382 case GLSL_SAMPLER_DIM_MS:
2383 return array ? 4 : 3;
2384 case GLSL_SAMPLER_DIM_3D:
2385 case GLSL_SAMPLER_DIM_CUBE:
2386 return 3;
2387 case GLSL_SAMPLER_DIM_RECT:
2388 case GLSL_SAMPLER_DIM_SUBPASS:
2389 return 2;
2390 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2391 return 3;
2392 default:
2393 break;
2394 }
2395 return 0;
2396 }
2397
2398
2399 static void get_image_intr_name(const char *base_name,
2400 LLVMTypeRef data_type,
2401 LLVMTypeRef coords_type,
2402 LLVMTypeRef rsrc_type,
2403 char *out_name, unsigned out_len)
2404 {
2405 char coords_type_name[8];
2406
2407 ac_build_type_name_for_intr(coords_type, coords_type_name,
2408 sizeof(coords_type_name));
2409
2410 if (HAVE_LLVM <= 0x0309) {
2411 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
2412 } else {
2413 char data_type_name[8];
2414 char rsrc_type_name[8];
2415
2416 ac_build_type_name_for_intr(data_type, data_type_name,
2417 sizeof(data_type_name));
2418 ac_build_type_name_for_intr(rsrc_type, rsrc_type_name,
2419 sizeof(rsrc_type_name));
2420 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
2421 data_type_name, coords_type_name, rsrc_type_name);
2422 }
2423 }
2424
2425 /* Adjust the sample index according to FMASK.
2426 *
2427 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2428 * which is the identity mapping. Each nibble says which physical sample
2429 * should be fetched to get that sample.
2430 *
2431 * For example, 0x11111100 means there are only 2 samples stored and
2432 * the second sample covers 3/4 of the pixel. When reading samples 0
2433 * and 1, return physical sample 0 (determined by the first two 0s
2434 * in FMASK), otherwise return physical sample 1.
2435 *
2436 * The sample index should be adjusted as follows:
2437 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2438 */
2439 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
2440 LLVMValueRef coord_x, LLVMValueRef coord_y,
2441 LLVMValueRef coord_z,
2442 LLVMValueRef sample_index,
2443 LLVMValueRef fmask_desc_ptr)
2444 {
2445 LLVMValueRef fmask_load_address[4], params[7];
2446 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2447 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2448 LLVMValueRef da = coord_z ? ctx->i32one : ctx->i32zero;
2449 LLVMValueRef res;
2450 char intrinsic_name[64];
2451
2452 fmask_load_address[0] = coord_x;
2453 fmask_load_address[1] = coord_y;
2454 if (coord_z) {
2455 fmask_load_address[2] = coord_z;
2456 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
2457 }
2458
2459 params[0] = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
2460 params[1] = fmask_desc_ptr;
2461 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2462 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2463 params[3] = glc;
2464 params[4] = slc;
2465 params[5] = lwe;
2466 params[6] = da;
2467
2468 get_image_intr_name("llvm.amdgcn.image.load",
2469 ctx->v4f32, /* vdata */
2470 LLVMTypeOf(params[0]), /* coords */
2471 LLVMTypeOf(params[1]), /* rsrc */
2472 intrinsic_name, sizeof(intrinsic_name));
2473
2474 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2475 params, 7, AC_FUNC_ATTR_READONLY);
2476
2477 res = to_integer(ctx, res);
2478 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
2479 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
2480
2481 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
2482 res,
2483 ctx->i32zero, "");
2484
2485 LLVMValueRef sample_index4 =
2486 LLVMBuildMul(ctx->builder, sample_index, four, "");
2487 LLVMValueRef shifted_fmask =
2488 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
2489 LLVMValueRef final_sample =
2490 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
2491
2492 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2493 * resource descriptor is 0 (invalid),
2494 */
2495 LLVMValueRef fmask_desc =
2496 LLVMBuildBitCast(ctx->builder, params[1],
2497 ctx->v8i32, "");
2498
2499 LLVMValueRef fmask_word1 =
2500 LLVMBuildExtractElement(ctx->builder, fmask_desc,
2501 ctx->i32one, "");
2502
2503 LLVMValueRef word1_is_nonzero =
2504 LLVMBuildICmp(ctx->builder, LLVMIntNE,
2505 fmask_word1, ctx->i32zero, "");
2506
2507 /* Replace the MSAA sample index. */
2508 sample_index =
2509 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
2510 final_sample, sample_index, "");
2511 return sample_index;
2512 }
2513
2514 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2515 nir_intrinsic_instr *instr)
2516 {
2517 const struct glsl_type *type = instr->variables[0]->var->type;
2518 if(instr->variables[0]->deref.child)
2519 type = instr->variables[0]->deref.child->type;
2520
2521 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2522 LLVMValueRef coords[4];
2523 LLVMValueRef masks[] = {
2524 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2525 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2526 };
2527 LLVMValueRef res;
2528 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2529
2530 int count;
2531 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2532 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2533 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2534 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2535 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2536
2537 count = image_type_to_components_count(dim,
2538 glsl_sampler_type_is_array(type));
2539
2540 if (is_ms) {
2541 LLVMValueRef fmask_load_address[3];
2542 int chan;
2543
2544 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2545 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
2546 if (glsl_sampler_type_is_array(type))
2547 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
2548 else
2549 fmask_load_address[2] = NULL;
2550 if (add_frag_pos) {
2551 for (chan = 0; chan < 2; ++chan)
2552 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2553 }
2554 sample_index = adjust_sample_index_using_fmask(ctx,
2555 fmask_load_address[0],
2556 fmask_load_address[1],
2557 fmask_load_address[2],
2558 sample_index,
2559 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
2560 }
2561 if (count == 1) {
2562 if (instr->src[0].ssa->num_components)
2563 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2564 else
2565 res = src0;
2566 } else {
2567 int chan;
2568 if (is_ms)
2569 count--;
2570 for (chan = 0; chan < count; ++chan) {
2571 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2572 }
2573
2574 if (add_frag_pos) {
2575 for (chan = 0; chan < count; ++chan)
2576 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2577 }
2578 if (is_ms) {
2579 coords[count] = sample_index;
2580 count++;
2581 }
2582
2583 if (count == 3) {
2584 coords[3] = LLVMGetUndef(ctx->i32);
2585 count = 4;
2586 }
2587 res = ac_build_gather_values(&ctx->ac, coords, count);
2588 }
2589 return res;
2590 }
2591
2592 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2593 nir_intrinsic_instr *instr)
2594 {
2595 LLVMValueRef params[7];
2596 LLVMValueRef res;
2597 char intrinsic_name[64];
2598 const nir_variable *var = instr->variables[0]->var;
2599 const struct glsl_type *type = var->type;
2600 if(instr->variables[0]->deref.child)
2601 type = instr->variables[0]->deref.child->type;
2602
2603 type = glsl_without_array(type);
2604 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2605 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2606 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2607 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2608 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2609 params[3] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2610 params[4] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2611 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2612 params, 5, 0);
2613
2614 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2615 res = to_integer(ctx, res);
2616 } else {
2617 bool is_da = glsl_sampler_type_is_array(type) ||
2618 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2619 LLVMValueRef da = is_da ? ctx->i32one : ctx->i32zero;
2620 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2621 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2622
2623 params[0] = get_image_coords(ctx, instr);
2624 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2625 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2626 if (HAVE_LLVM <= 0x0309) {
2627 params[3] = LLVMConstInt(ctx->i1, 0, false); /* r128 */
2628 params[4] = da;
2629 params[5] = glc;
2630 params[6] = slc;
2631 } else {
2632 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2633 params[3] = glc;
2634 params[4] = slc;
2635 params[5] = lwe;
2636 params[6] = da;
2637 }
2638
2639 get_image_intr_name("llvm.amdgcn.image.load",
2640 ctx->v4f32, /* vdata */
2641 LLVMTypeOf(params[0]), /* coords */
2642 LLVMTypeOf(params[1]), /* rsrc */
2643 intrinsic_name, sizeof(intrinsic_name));
2644
2645 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2646 params, 7, AC_FUNC_ATTR_READONLY);
2647 }
2648 return to_integer(ctx, res);
2649 }
2650
2651 static void visit_image_store(struct nir_to_llvm_context *ctx,
2652 nir_intrinsic_instr *instr)
2653 {
2654 LLVMValueRef params[8];
2655 char intrinsic_name[64];
2656 const nir_variable *var = instr->variables[0]->var;
2657 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2658 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2659 const struct glsl_type *type = glsl_without_array(var->type);
2660
2661 if (ctx->stage == MESA_SHADER_FRAGMENT)
2662 ctx->shader_info->fs.writes_memory = true;
2663
2664 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2665 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2666 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2667 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2668 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2669 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2670 params[4] = i1false; /* glc */
2671 params[5] = i1false; /* slc */
2672 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2673 params, 6, 0);
2674 } else {
2675 bool is_da = glsl_sampler_type_is_array(type) ||
2676 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2677 LLVMValueRef da = is_da ? i1true : i1false;
2678 LLVMValueRef glc = i1false;
2679 LLVMValueRef slc = i1false;
2680
2681 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2682 params[1] = get_image_coords(ctx, instr); /* coords */
2683 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2684 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2685 if (HAVE_LLVM <= 0x0309) {
2686 params[4] = i1false; /* r128 */
2687 params[5] = da;
2688 params[6] = glc;
2689 params[7] = slc;
2690 } else {
2691 LLVMValueRef lwe = i1false;
2692 params[4] = glc;
2693 params[5] = slc;
2694 params[6] = lwe;
2695 params[7] = da;
2696 }
2697
2698 get_image_intr_name("llvm.amdgcn.image.store",
2699 LLVMTypeOf(params[0]), /* vdata */
2700 LLVMTypeOf(params[1]), /* coords */
2701 LLVMTypeOf(params[2]), /* rsrc */
2702 intrinsic_name, sizeof(intrinsic_name));
2703
2704 ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2705 params, 8, 0);
2706 }
2707
2708 }
2709
2710 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2711 nir_intrinsic_instr *instr)
2712 {
2713 LLVMValueRef params[6];
2714 int param_count = 0;
2715 const nir_variable *var = instr->variables[0]->var;
2716 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2717 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2718 const char *base_name = "llvm.amdgcn.image.atomic";
2719 const char *atomic_name;
2720 LLVMValueRef coords;
2721 char intrinsic_name[32], coords_type[8];
2722 const struct glsl_type *type = glsl_without_array(var->type);
2723
2724 if (ctx->stage == MESA_SHADER_FRAGMENT)
2725 ctx->shader_info->fs.writes_memory = true;
2726
2727 params[param_count++] = get_src(ctx, instr->src[2]);
2728 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2729 params[param_count++] = get_src(ctx, instr->src[3]);
2730
2731 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2732 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2733 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2734 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2735 params[param_count++] = ctx->i32zero; /* voffset */
2736 params[param_count++] = i1false; /* glc */
2737 params[param_count++] = i1false; /* slc */
2738 } else {
2739 bool da = glsl_sampler_type_is_array(type) ||
2740 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2741
2742 coords = params[param_count++] = get_image_coords(ctx, instr);
2743 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2744 params[param_count++] = i1false; /* r128 */
2745 params[param_count++] = da ? i1true : i1false; /* da */
2746 params[param_count++] = i1false; /* slc */
2747 }
2748
2749 switch (instr->intrinsic) {
2750 case nir_intrinsic_image_atomic_add:
2751 atomic_name = "add";
2752 break;
2753 case nir_intrinsic_image_atomic_min:
2754 atomic_name = "smin";
2755 break;
2756 case nir_intrinsic_image_atomic_max:
2757 atomic_name = "smax";
2758 break;
2759 case nir_intrinsic_image_atomic_and:
2760 atomic_name = "and";
2761 break;
2762 case nir_intrinsic_image_atomic_or:
2763 atomic_name = "or";
2764 break;
2765 case nir_intrinsic_image_atomic_xor:
2766 atomic_name = "xor";
2767 break;
2768 case nir_intrinsic_image_atomic_exchange:
2769 atomic_name = "swap";
2770 break;
2771 case nir_intrinsic_image_atomic_comp_swap:
2772 atomic_name = "cmpswap";
2773 break;
2774 default:
2775 abort();
2776 }
2777 build_int_type_name(LLVMTypeOf(coords),
2778 coords_type, sizeof(coords_type));
2779
2780 snprintf(intrinsic_name, sizeof(intrinsic_name),
2781 "%s.%s.%s", base_name, atomic_name, coords_type);
2782 return ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2783 }
2784
2785 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2786 nir_intrinsic_instr *instr)
2787 {
2788 LLVMValueRef res;
2789 LLVMValueRef params[10];
2790 const nir_variable *var = instr->variables[0]->var;
2791 const struct glsl_type *type = instr->variables[0]->var->type;
2792 bool da = glsl_sampler_type_is_array(var->type) ||
2793 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2794 if(instr->variables[0]->deref.child)
2795 type = instr->variables[0]->deref.child->type;
2796
2797 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2798 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2799 params[0] = ctx->i32zero;
2800 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2801 params[2] = LLVMConstInt(ctx->i32, 15, false);
2802 params[3] = ctx->i32zero;
2803 params[4] = ctx->i32zero;
2804 params[5] = da ? ctx->i32one : ctx->i32zero;
2805 params[6] = ctx->i32zero;
2806 params[7] = ctx->i32zero;
2807 params[8] = ctx->i32zero;
2808 params[9] = ctx->i32zero;
2809
2810 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
2811 params, 10,
2812 AC_FUNC_ATTR_READNONE |
2813 AC_FUNC_ATTR_LEGACY);
2814
2815 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2816 glsl_sampler_type_is_array(type)) {
2817 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2818 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2819 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2820 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2821 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2822 }
2823 return res;
2824 }
2825
2826 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2827 {
2828 LLVMValueRef args[1] = {
2829 LLVMConstInt(ctx->i32, 0xf70, false),
2830 };
2831 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2832 ctx->voidt, args, 1, 0);
2833 }
2834
2835 static void emit_barrier(struct nir_to_llvm_context *ctx)
2836 {
2837 // TODO tess
2838 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2839 ctx->voidt, NULL, 0, 0);
2840 }
2841
2842 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2843 nir_intrinsic_instr *instr)
2844 {
2845 LLVMValueRef cond;
2846 ctx->shader_info->fs.can_discard = true;
2847
2848 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2849 get_src(ctx, instr->src[0]),
2850 ctx->i32zero, "");
2851
2852 cond = LLVMBuildSelect(ctx->builder, cond,
2853 LLVMConstReal(ctx->f32, -1.0f),
2854 ctx->f32zero, "");
2855 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
2856 ctx->voidt,
2857 &cond, 1, AC_FUNC_ATTR_LEGACY);
2858 }
2859
2860 static LLVMValueRef
2861 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2862 {
2863 LLVMValueRef result;
2864 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
2865 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2866 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2867
2868 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2869 }
2870
2871 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2872 nir_intrinsic_instr *instr)
2873 {
2874 LLVMValueRef ptr, result;
2875 int idx = instr->variables[0]->var->data.driver_location;
2876 LLVMValueRef src = get_src(ctx, instr->src[0]);
2877 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2878
2879 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2880 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2881 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2882 ptr, src, src1,
2883 LLVMAtomicOrderingSequentiallyConsistent,
2884 LLVMAtomicOrderingSequentiallyConsistent,
2885 false);
2886 } else {
2887 LLVMAtomicRMWBinOp op;
2888 switch (instr->intrinsic) {
2889 case nir_intrinsic_var_atomic_add:
2890 op = LLVMAtomicRMWBinOpAdd;
2891 break;
2892 case nir_intrinsic_var_atomic_umin:
2893 op = LLVMAtomicRMWBinOpUMin;
2894 break;
2895 case nir_intrinsic_var_atomic_umax:
2896 op = LLVMAtomicRMWBinOpUMax;
2897 break;
2898 case nir_intrinsic_var_atomic_imin:
2899 op = LLVMAtomicRMWBinOpMin;
2900 break;
2901 case nir_intrinsic_var_atomic_imax:
2902 op = LLVMAtomicRMWBinOpMax;
2903 break;
2904 case nir_intrinsic_var_atomic_and:
2905 op = LLVMAtomicRMWBinOpAnd;
2906 break;
2907 case nir_intrinsic_var_atomic_or:
2908 op = LLVMAtomicRMWBinOpOr;
2909 break;
2910 case nir_intrinsic_var_atomic_xor:
2911 op = LLVMAtomicRMWBinOpXor;
2912 break;
2913 case nir_intrinsic_var_atomic_exchange:
2914 op = LLVMAtomicRMWBinOpXchg;
2915 break;
2916 default:
2917 return NULL;
2918 }
2919
2920 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2921 LLVMAtomicOrderingSequentiallyConsistent,
2922 false);
2923 }
2924 return result;
2925 }
2926
2927 #define INTERP_CENTER 0
2928 #define INTERP_CENTROID 1
2929 #define INTERP_SAMPLE 2
2930
2931 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2932 enum glsl_interp_mode interp, unsigned location)
2933 {
2934 switch (interp) {
2935 case INTERP_MODE_FLAT:
2936 default:
2937 return NULL;
2938 case INTERP_MODE_SMOOTH:
2939 case INTERP_MODE_NONE:
2940 if (location == INTERP_CENTER)
2941 return ctx->persp_center;
2942 else if (location == INTERP_CENTROID)
2943 return ctx->persp_centroid;
2944 else if (location == INTERP_SAMPLE)
2945 return ctx->persp_sample;
2946 break;
2947 case INTERP_MODE_NOPERSPECTIVE:
2948 if (location == INTERP_CENTER)
2949 return ctx->linear_center;
2950 else if (location == INTERP_CENTROID)
2951 return ctx->linear_centroid;
2952 else if (location == INTERP_SAMPLE)
2953 return ctx->linear_sample;
2954 break;
2955 }
2956 return NULL;
2957 }
2958
2959 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
2960 LLVMValueRef sample_id)
2961 {
2962 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2963 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
2964 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
2965 LLVMValueRef result[2];
2966
2967 result[0] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset0);
2968 result[1] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset1);
2969
2970 return ac_build_gather_values(&ctx->ac, result, 2);
2971 }
2972
2973 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
2974 {
2975 LLVMValueRef values[2];
2976
2977 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
2978 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
2979 return ac_build_gather_values(&ctx->ac, values, 2);
2980 }
2981
2982 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
2983 nir_intrinsic_instr *instr)
2984 {
2985 LLVMValueRef result[2];
2986 LLVMValueRef interp_param, attr_number;
2987 unsigned location;
2988 unsigned chan;
2989 LLVMValueRef src_c0, src_c1;
2990 LLVMValueRef src0;
2991 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
2992 switch (instr->intrinsic) {
2993 case nir_intrinsic_interp_var_at_centroid:
2994 location = INTERP_CENTROID;
2995 break;
2996 case nir_intrinsic_interp_var_at_sample:
2997 location = INTERP_SAMPLE;
2998 src0 = get_src(ctx, instr->src[0]);
2999 break;
3000 case nir_intrinsic_interp_var_at_offset:
3001 location = INTERP_CENTER;
3002 src0 = get_src(ctx, instr->src[0]);
3003 default:
3004 break;
3005 }
3006
3007 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3008 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3009 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3010 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3011 LLVMValueRef sample_position;
3012 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3013
3014 /* fetch sample ID */
3015 sample_position = load_sample_position(ctx, src0);
3016
3017 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3018 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3019 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3020 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3021 }
3022 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3023 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3024
3025 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3026 LLVMValueRef ij_out[2];
3027 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3028
3029 /*
3030 * take the I then J parameters, and the DDX/Y for it, and
3031 * calculate the IJ inputs for the interpolator.
3032 * temp1 = ddx * offset/sample.x + I;
3033 * interp_param.I = ddy * offset/sample.y + temp1;
3034 * temp1 = ddx * offset/sample.x + J;
3035 * interp_param.J = ddy * offset/sample.y + temp1;
3036 */
3037 for (unsigned i = 0; i < 2; i++) {
3038 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3039 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3040 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3041 ddxy_out, ix_ll, "");
3042 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3043 ddxy_out, iy_ll, "");
3044 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3045 interp_param, ix_ll, "");
3046 LLVMValueRef temp1, temp2;
3047
3048 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3049 ctx->f32, "");
3050
3051 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3052 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3053
3054 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3055 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3056
3057 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3058 temp2, ctx->i32, "");
3059 }
3060 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3061
3062 }
3063
3064 for (chan = 0; chan < 2; chan++) {
3065 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3066
3067 if (interp_param) {
3068 interp_param = LLVMBuildBitCast(ctx->builder,
3069 interp_param, LLVMVectorType(ctx->f32, 2), "");
3070 LLVMValueRef i = LLVMBuildExtractElement(
3071 ctx->builder, interp_param, ctx->i32zero, "");
3072 LLVMValueRef j = LLVMBuildExtractElement(
3073 ctx->builder, interp_param, ctx->i32one, "");
3074
3075 result[chan] = ac_build_fs_interp(&ctx->ac,
3076 llvm_chan, attr_number,
3077 ctx->prim_mask, i, j);
3078 } else {
3079 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3080 LLVMConstInt(ctx->i32, 2, false),
3081 llvm_chan, attr_number,
3082 ctx->prim_mask);
3083 }
3084 }
3085 return ac_build_gather_values(&ctx->ac, result, 2);
3086 }
3087
3088 static void
3089 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3090 nir_intrinsic_instr *instr)
3091 {
3092 LLVMValueRef gs_next_vertex;
3093 LLVMValueRef can_emit, kill;
3094 int idx;
3095 int clip_cull_slot = -1;
3096 assert(instr->const_index[0] == 0);
3097 /* Write vertex attribute values to GSVS ring */
3098 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3099 ctx->gs_next_vertex,
3100 "");
3101
3102 /* If this thread has already emitted the declared maximum number of
3103 * vertices, kill it: excessive vertex emissions are not supposed to
3104 * have any effect, and GS threads have no externally observable
3105 * effects other than emitting vertices.
3106 */
3107 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3108 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3109
3110 kill = LLVMBuildSelect(ctx->builder, can_emit,
3111 LLVMConstReal(ctx->f32, 1.0f),
3112 LLVMConstReal(ctx->f32, -1.0f), "");
3113 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
3114 ctx->voidt, &kill, 1, AC_FUNC_ATTR_LEGACY);
3115
3116 /* loop num outputs */
3117 idx = 0;
3118 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3119 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3120 int length = 4;
3121 int start = 0;
3122 int slot = idx;
3123 int slot_inc = 1;
3124
3125 if (!(ctx->output_mask & (1ull << i)))
3126 continue;
3127
3128 if (i == VARYING_SLOT_CLIP_DIST1 ||
3129 i == VARYING_SLOT_CULL_DIST1)
3130 continue;
3131
3132 if (i == VARYING_SLOT_CLIP_DIST0 ||
3133 i == VARYING_SLOT_CULL_DIST0) {
3134 /* pack clip and cull into a single set of slots */
3135 if (clip_cull_slot == -1) {
3136 clip_cull_slot = idx;
3137 if (ctx->num_output_clips + ctx->num_output_culls > 4)
3138 slot_inc = 2;
3139 } else {
3140 slot = clip_cull_slot;
3141 slot_inc = 0;
3142 }
3143 if (i == VARYING_SLOT_CLIP_DIST0)
3144 length = ctx->num_output_clips;
3145 if (i == VARYING_SLOT_CULL_DIST0) {
3146 start = ctx->num_output_clips;
3147 length = ctx->num_output_culls;
3148 }
3149 }
3150 for (unsigned j = 0; j < length; j++) {
3151 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3152 out_ptr[j], "");
3153 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j + start) * ctx->gs_max_out_vertices, false);
3154 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3155 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3156
3157 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3158
3159 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3160 out_val, 1,
3161 voffset, ctx->gs2vs_offset, 0,
3162 1, 1);
3163 }
3164 idx += slot_inc;
3165 }
3166
3167 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3168 ctx->i32one, "");
3169 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3170
3171 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3172 }
3173
3174 static void
3175 visit_end_primitive(struct nir_to_llvm_context *ctx,
3176 nir_intrinsic_instr *instr)
3177 {
3178 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3179 }
3180
3181 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3182 nir_intrinsic_instr *instr)
3183 {
3184 LLVMValueRef result = NULL;
3185
3186 switch (instr->intrinsic) {
3187 case nir_intrinsic_load_work_group_id: {
3188 result = ctx->workgroup_ids;
3189 break;
3190 }
3191 case nir_intrinsic_load_base_vertex: {
3192 result = ctx->base_vertex;
3193 break;
3194 }
3195 case nir_intrinsic_load_vertex_id_zero_base: {
3196 result = ctx->vertex_id;
3197 break;
3198 }
3199 case nir_intrinsic_load_local_invocation_id: {
3200 result = ctx->local_invocation_ids;
3201 break;
3202 }
3203 case nir_intrinsic_load_base_instance:
3204 result = ctx->start_instance;
3205 break;
3206 case nir_intrinsic_load_draw_id:
3207 result = ctx->draw_index;
3208 break;
3209 case nir_intrinsic_load_invocation_id:
3210 result = ctx->gs_invocation_id;
3211 break;
3212 case nir_intrinsic_load_primitive_id:
3213 if (ctx->stage == MESA_SHADER_GEOMETRY)
3214 result = ctx->gs_prim_id;
3215 else
3216 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3217 break;
3218 case nir_intrinsic_load_sample_id:
3219 ctx->shader_info->fs.force_persample = true;
3220 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3221 break;
3222 case nir_intrinsic_load_sample_pos:
3223 ctx->shader_info->fs.force_persample = true;
3224 result = load_sample_pos(ctx);
3225 break;
3226 case nir_intrinsic_load_sample_mask_in:
3227 result = ctx->sample_coverage;
3228 break;
3229 case nir_intrinsic_load_front_face:
3230 result = ctx->front_face;
3231 break;
3232 case nir_intrinsic_load_instance_id:
3233 result = ctx->instance_id;
3234 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3235 ctx->shader_info->vs.vgpr_comp_cnt);
3236 break;
3237 case nir_intrinsic_load_num_work_groups:
3238 result = ctx->num_work_groups;
3239 break;
3240 case nir_intrinsic_load_local_invocation_index:
3241 result = visit_load_local_invocation_index(ctx);
3242 break;
3243 case nir_intrinsic_load_push_constant:
3244 result = visit_load_push_constant(ctx, instr);
3245 break;
3246 case nir_intrinsic_vulkan_resource_index:
3247 result = visit_vulkan_resource_index(ctx, instr);
3248 break;
3249 case nir_intrinsic_store_ssbo:
3250 visit_store_ssbo(ctx, instr);
3251 break;
3252 case nir_intrinsic_load_ssbo:
3253 result = visit_load_buffer(ctx, instr);
3254 break;
3255 case nir_intrinsic_ssbo_atomic_add:
3256 case nir_intrinsic_ssbo_atomic_imin:
3257 case nir_intrinsic_ssbo_atomic_umin:
3258 case nir_intrinsic_ssbo_atomic_imax:
3259 case nir_intrinsic_ssbo_atomic_umax:
3260 case nir_intrinsic_ssbo_atomic_and:
3261 case nir_intrinsic_ssbo_atomic_or:
3262 case nir_intrinsic_ssbo_atomic_xor:
3263 case nir_intrinsic_ssbo_atomic_exchange:
3264 case nir_intrinsic_ssbo_atomic_comp_swap:
3265 result = visit_atomic_ssbo(ctx, instr);
3266 break;
3267 case nir_intrinsic_load_ubo:
3268 result = visit_load_ubo_buffer(ctx, instr);
3269 break;
3270 case nir_intrinsic_get_buffer_size:
3271 result = visit_get_buffer_size(ctx, instr);
3272 break;
3273 case nir_intrinsic_load_var:
3274 result = visit_load_var(ctx, instr);
3275 break;
3276 case nir_intrinsic_store_var:
3277 visit_store_var(ctx, instr);
3278 break;
3279 case nir_intrinsic_image_load:
3280 result = visit_image_load(ctx, instr);
3281 break;
3282 case nir_intrinsic_image_store:
3283 visit_image_store(ctx, instr);
3284 break;
3285 case nir_intrinsic_image_atomic_add:
3286 case nir_intrinsic_image_atomic_min:
3287 case nir_intrinsic_image_atomic_max:
3288 case nir_intrinsic_image_atomic_and:
3289 case nir_intrinsic_image_atomic_or:
3290 case nir_intrinsic_image_atomic_xor:
3291 case nir_intrinsic_image_atomic_exchange:
3292 case nir_intrinsic_image_atomic_comp_swap:
3293 result = visit_image_atomic(ctx, instr);
3294 break;
3295 case nir_intrinsic_image_size:
3296 result = visit_image_size(ctx, instr);
3297 break;
3298 case nir_intrinsic_discard:
3299 ctx->shader_info->fs.can_discard = true;
3300 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3301 ctx->voidt,
3302 NULL, 0, AC_FUNC_ATTR_LEGACY);
3303 break;
3304 case nir_intrinsic_discard_if:
3305 emit_discard_if(ctx, instr);
3306 break;
3307 case nir_intrinsic_memory_barrier:
3308 emit_waitcnt(ctx);
3309 break;
3310 case nir_intrinsic_barrier:
3311 emit_barrier(ctx);
3312 break;
3313 case nir_intrinsic_var_atomic_add:
3314 case nir_intrinsic_var_atomic_imin:
3315 case nir_intrinsic_var_atomic_umin:
3316 case nir_intrinsic_var_atomic_imax:
3317 case nir_intrinsic_var_atomic_umax:
3318 case nir_intrinsic_var_atomic_and:
3319 case nir_intrinsic_var_atomic_or:
3320 case nir_intrinsic_var_atomic_xor:
3321 case nir_intrinsic_var_atomic_exchange:
3322 case nir_intrinsic_var_atomic_comp_swap:
3323 result = visit_var_atomic(ctx, instr);
3324 break;
3325 case nir_intrinsic_interp_var_at_centroid:
3326 case nir_intrinsic_interp_var_at_sample:
3327 case nir_intrinsic_interp_var_at_offset:
3328 result = visit_interp(ctx, instr);
3329 break;
3330 case nir_intrinsic_emit_vertex:
3331 visit_emit_vertex(ctx, instr);
3332 break;
3333 case nir_intrinsic_end_primitive:
3334 visit_end_primitive(ctx, instr);
3335 break;
3336 default:
3337 fprintf(stderr, "Unknown intrinsic: ");
3338 nir_print_instr(&instr->instr, stderr);
3339 fprintf(stderr, "\n");
3340 break;
3341 }
3342 if (result) {
3343 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3344 }
3345 }
3346
3347 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3348 nir_deref_var *deref,
3349 enum desc_type desc_type)
3350 {
3351 unsigned desc_set = deref->var->data.descriptor_set;
3352 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3353 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3354 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3355 unsigned offset = binding->offset;
3356 unsigned stride = binding->size;
3357 unsigned type_size;
3358 LLVMBuilderRef builder = ctx->builder;
3359 LLVMTypeRef type;
3360 LLVMValueRef index = NULL;
3361 unsigned constant_index = 0;
3362
3363 assert(deref->var->data.binding < layout->binding_count);
3364
3365 switch (desc_type) {
3366 case DESC_IMAGE:
3367 type = ctx->v8i32;
3368 type_size = 32;
3369 break;
3370 case DESC_FMASK:
3371 type = ctx->v8i32;
3372 offset += 32;
3373 type_size = 32;
3374 break;
3375 case DESC_SAMPLER:
3376 type = ctx->v4i32;
3377 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3378 offset += 64;
3379
3380 type_size = 16;
3381 break;
3382 case DESC_BUFFER:
3383 type = ctx->v4i32;
3384 type_size = 16;
3385 break;
3386 default:
3387 unreachable("invalid desc_type\n");
3388 }
3389
3390 if (deref->deref.child) {
3391 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3392
3393 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3394 offset += child->base_offset * stride;
3395 if (child->deref_array_type == nir_deref_array_type_indirect) {
3396 index = get_src(ctx, child->indirect);
3397 }
3398
3399 constant_index = child->base_offset;
3400 }
3401 if (desc_type == DESC_SAMPLER && binding->immutable_samplers &&
3402 (!index || binding->immutable_samplers_equal)) {
3403 if (binding->immutable_samplers_equal)
3404 constant_index = 0;
3405
3406 LLVMValueRef constants[] = {
3407 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 0], 0),
3408 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 1], 0),
3409 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 2], 0),
3410 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 3], 0),
3411 };
3412 return ac_build_gather_values(&ctx->ac, constants, 4);
3413 }
3414
3415 assert(stride % type_size == 0);
3416
3417 if (!index)
3418 index = ctx->i32zero;
3419
3420 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3421
3422 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
3423 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3424
3425 return ac_build_indexed_load_const(&ctx->ac, list, index);
3426 }
3427
3428 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3429 struct ac_tex_info *tinfo,
3430 nir_tex_instr *instr,
3431 nir_texop op,
3432 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3433 LLVMValueRef *param, unsigned count,
3434 unsigned dmask)
3435 {
3436 int num_args;
3437 unsigned is_rect = 0;
3438 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3439
3440 if (op == nir_texop_lod)
3441 da = false;
3442 /* Pad to power of two vector */
3443 while (count < util_next_power_of_two(count))
3444 param[count++] = LLVMGetUndef(ctx->i32);
3445
3446 if (count > 1)
3447 tinfo->args[0] = ac_build_gather_values(&ctx->ac, param, count);
3448 else
3449 tinfo->args[0] = param[0];
3450
3451 tinfo->args[1] = res_ptr;
3452 num_args = 2;
3453
3454 if (op == nir_texop_txf ||
3455 op == nir_texop_txf_ms ||
3456 op == nir_texop_query_levels ||
3457 op == nir_texop_texture_samples ||
3458 op == nir_texop_txs)
3459 tinfo->dst_type = ctx->v4i32;
3460 else {
3461 tinfo->dst_type = ctx->v4f32;
3462 tinfo->args[num_args++] = samp_ptr;
3463 }
3464
3465 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3466 tinfo->args[0] = res_ptr;
3467 tinfo->args[1] = LLVMConstInt(ctx->i32, 0, false);
3468 tinfo->args[2] = param[0];
3469 tinfo->arg_count = 3;
3470 return;
3471 }
3472
3473 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, dmask, 0);
3474 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, is_rect, 0); /* unorm */
3475 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
3476 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
3477 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
3478 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
3479 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
3480 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
3481
3482 tinfo->arg_count = num_args;
3483 }
3484
3485 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3486 *
3487 * SI-CI:
3488 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3489 * filtering manually. The driver sets img7 to a mask clearing
3490 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3491 * s_and_b32 samp0, samp0, img7
3492 *
3493 * VI:
3494 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3495 */
3496 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3497 LLVMValueRef res, LLVMValueRef samp)
3498 {
3499 LLVMBuilderRef builder = ctx->builder;
3500 LLVMValueRef img7, samp0;
3501
3502 if (ctx->options->chip_class >= VI)
3503 return samp;
3504
3505 img7 = LLVMBuildExtractElement(builder, res,
3506 LLVMConstInt(ctx->i32, 7, 0), "");
3507 samp0 = LLVMBuildExtractElement(builder, samp,
3508 LLVMConstInt(ctx->i32, 0, 0), "");
3509 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3510 return LLVMBuildInsertElement(builder, samp, samp0,
3511 LLVMConstInt(ctx->i32, 0, 0), "");
3512 }
3513
3514 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3515 nir_tex_instr *instr,
3516 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3517 LLVMValueRef *fmask_ptr)
3518 {
3519 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3520 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3521 else
3522 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3523 if (samp_ptr) {
3524 if (instr->sampler)
3525 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3526 else
3527 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3528 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3529 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3530 }
3531 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3532 instr->op == nir_texop_samples_identical))
3533 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3534 }
3535
3536 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
3537 LLVMValueRef coord)
3538 {
3539 coord = to_float(ctx, coord);
3540 coord = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
3541 coord = to_integer(ctx, coord);
3542 return coord;
3543 }
3544
3545 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3546 {
3547 LLVMValueRef result = NULL;
3548 struct ac_tex_info tinfo = { 0 };
3549 unsigned dmask = 0xf;
3550 LLVMValueRef address[16];
3551 LLVMValueRef coords[5];
3552 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3553 LLVMValueRef bias = NULL, offsets = NULL;
3554 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3555 LLVMValueRef ddx = NULL, ddy = NULL;
3556 LLVMValueRef derivs[6];
3557 unsigned chan, count = 0;
3558 unsigned const_src = 0, num_deriv_comp = 0;
3559
3560 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3561
3562 for (unsigned i = 0; i < instr->num_srcs; i++) {
3563 switch (instr->src[i].src_type) {
3564 case nir_tex_src_coord:
3565 coord = get_src(ctx, instr->src[i].src);
3566 break;
3567 case nir_tex_src_projector:
3568 break;
3569 case nir_tex_src_comparator:
3570 comparator = get_src(ctx, instr->src[i].src);
3571 break;
3572 case nir_tex_src_offset:
3573 offsets = get_src(ctx, instr->src[i].src);
3574 const_src = i;
3575 break;
3576 case nir_tex_src_bias:
3577 bias = get_src(ctx, instr->src[i].src);
3578 break;
3579 case nir_tex_src_lod:
3580 lod = get_src(ctx, instr->src[i].src);
3581 break;
3582 case nir_tex_src_ms_index:
3583 sample_index = get_src(ctx, instr->src[i].src);
3584 break;
3585 case nir_tex_src_ms_mcs:
3586 break;
3587 case nir_tex_src_ddx:
3588 ddx = get_src(ctx, instr->src[i].src);
3589 num_deriv_comp = instr->src[i].src.ssa->num_components;
3590 break;
3591 case nir_tex_src_ddy:
3592 ddy = get_src(ctx, instr->src[i].src);
3593 break;
3594 case nir_tex_src_texture_offset:
3595 case nir_tex_src_sampler_offset:
3596 case nir_tex_src_plane:
3597 default:
3598 break;
3599 }
3600 }
3601
3602 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3603 result = get_buffer_size(ctx, res_ptr, true);
3604 goto write_result;
3605 }
3606
3607 if (instr->op == nir_texop_texture_samples) {
3608 LLVMValueRef res, samples, is_msaa;
3609 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3610 samples = LLVMBuildExtractElement(ctx->builder, res,
3611 LLVMConstInt(ctx->i32, 3, false), "");
3612 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3613 LLVMConstInt(ctx->i32, 28, false), "");
3614 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3615 LLVMConstInt(ctx->i32, 0xe, false), "");
3616 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3617 LLVMConstInt(ctx->i32, 0xe, false), "");
3618
3619 samples = LLVMBuildLShr(ctx->builder, samples,
3620 LLVMConstInt(ctx->i32, 16, false), "");
3621 samples = LLVMBuildAnd(ctx->builder, samples,
3622 LLVMConstInt(ctx->i32, 0xf, false), "");
3623 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3624 samples, "");
3625 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3626 ctx->i32one, "");
3627 result = samples;
3628 goto write_result;
3629 }
3630
3631 if (coord)
3632 for (chan = 0; chan < instr->coord_components; chan++)
3633 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3634
3635 if (offsets && instr->op != nir_texop_txf) {
3636 LLVMValueRef offset[3], pack;
3637 for (chan = 0; chan < 3; ++chan)
3638 offset[chan] = ctx->i32zero;
3639
3640 tinfo.has_offset = true;
3641 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3642 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3643 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3644 LLVMConstInt(ctx->i32, 0x3f, false), "");
3645 if (chan)
3646 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3647 LLVMConstInt(ctx->i32, chan * 8, false), "");
3648 }
3649 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3650 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3651 address[count++] = pack;
3652
3653 }
3654 /* pack LOD bias value */
3655 if (instr->op == nir_texop_txb && bias) {
3656 address[count++] = bias;
3657 }
3658
3659 /* Pack depth comparison value */
3660 if (instr->is_shadow && comparator) {
3661 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3662 }
3663
3664 /* pack derivatives */
3665 if (ddx || ddy) {
3666 switch (instr->sampler_dim) {
3667 case GLSL_SAMPLER_DIM_3D:
3668 case GLSL_SAMPLER_DIM_CUBE:
3669 num_deriv_comp = 3;
3670 break;
3671 case GLSL_SAMPLER_DIM_2D:
3672 default:
3673 num_deriv_comp = 2;
3674 break;
3675 case GLSL_SAMPLER_DIM_1D:
3676 num_deriv_comp = 1;
3677 break;
3678 }
3679
3680 for (unsigned i = 0; i < num_deriv_comp; i++) {
3681 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3682 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3683 }
3684 }
3685
3686 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3687 for (chan = 0; chan < instr->coord_components; chan++)
3688 coords[chan] = to_float(ctx, coords[chan]);
3689 if (instr->coord_components == 3)
3690 coords[3] = LLVMGetUndef(ctx->f32);
3691 ac_prepare_cube_coords(&ctx->ac,
3692 instr->op == nir_texop_txd, instr->is_array,
3693 coords, derivs);
3694 if (num_deriv_comp)
3695 num_deriv_comp--;
3696 }
3697
3698 if (ddx || ddy) {
3699 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3700 address[count++] = derivs[i];
3701 }
3702
3703 /* Pack texture coordinates */
3704 if (coord) {
3705 address[count++] = coords[0];
3706 if (instr->coord_components > 1) {
3707 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
3708 coords[1] = apply_round_slice(ctx, coords[1]);
3709 }
3710 address[count++] = coords[1];
3711 }
3712 if (instr->coord_components > 2) {
3713 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3714 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3715 coords[2] = apply_round_slice(ctx, coords[2]);
3716 }
3717 address[count++] = coords[2];
3718 }
3719 }
3720
3721 /* Pack LOD */
3722 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3723 address[count++] = lod;
3724 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3725 address[count++] = sample_index;
3726 } else if(instr->op == nir_texop_txs) {
3727 count = 0;
3728 if (lod)
3729 address[count++] = lod;
3730 else
3731 address[count++] = ctx->i32zero;
3732 }
3733
3734 for (chan = 0; chan < count; chan++) {
3735 address[chan] = LLVMBuildBitCast(ctx->builder,
3736 address[chan], ctx->i32, "");
3737 }
3738
3739 if (instr->op == nir_texop_samples_identical) {
3740 LLVMValueRef txf_address[4];
3741 struct ac_tex_info txf_info = { 0 };
3742 unsigned txf_count = count;
3743 memcpy(txf_address, address, sizeof(txf_address));
3744
3745 if (!instr->is_array)
3746 txf_address[2] = ctx->i32zero;
3747 txf_address[3] = ctx->i32zero;
3748
3749 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3750 fmask_ptr, NULL,
3751 txf_address, txf_count, 0xf);
3752
3753 result = build_tex_intrinsic(ctx, instr, &txf_info);
3754
3755 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3756 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3757 goto write_result;
3758 }
3759
3760 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
3761 instr->op != nir_texop_txs) {
3762 unsigned sample_chan = instr->is_array ? 3 : 2;
3763 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
3764 address[0],
3765 address[1],
3766 instr->is_array ? address[2] : NULL,
3767 address[sample_chan],
3768 fmask_ptr);
3769 }
3770
3771 if (offsets && instr->op == nir_texop_txf) {
3772 nir_const_value *const_offset =
3773 nir_src_as_const_value(instr->src[const_src].src);
3774 int num_offsets = instr->src[const_src].src.ssa->num_components;
3775 assert(const_offset);
3776 num_offsets = MIN2(num_offsets, instr->coord_components);
3777 if (num_offsets > 2)
3778 address[2] = LLVMBuildAdd(ctx->builder,
3779 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3780 if (num_offsets > 1)
3781 address[1] = LLVMBuildAdd(ctx->builder,
3782 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3783 address[0] = LLVMBuildAdd(ctx->builder,
3784 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3785
3786 }
3787
3788 /* TODO TG4 support */
3789 if (instr->op == nir_texop_tg4) {
3790 if (instr->is_shadow)
3791 dmask = 1;
3792 else
3793 dmask = 1 << instr->component;
3794 }
3795 set_tex_fetch_args(ctx, &tinfo, instr, instr->op,
3796 res_ptr, samp_ptr, address, count, dmask);
3797
3798 result = build_tex_intrinsic(ctx, instr, &tinfo);
3799
3800 if (instr->op == nir_texop_query_levels)
3801 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3802 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3803 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3804 else if (instr->op == nir_texop_txs &&
3805 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3806 instr->is_array) {
3807 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3808 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3809 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3810 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3811 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3812 } else if (instr->dest.ssa.num_components != 4)
3813 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3814
3815 write_result:
3816 if (result) {
3817 assert(instr->dest.is_ssa);
3818 result = to_integer(ctx, result);
3819 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3820 }
3821 }
3822
3823
3824 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3825 {
3826 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3827 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3828
3829 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3830 _mesa_hash_table_insert(ctx->phis, instr, result);
3831 }
3832
3833 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3834 nir_phi_instr *instr,
3835 LLVMValueRef llvm_phi)
3836 {
3837 nir_foreach_phi_src(src, instr) {
3838 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3839 LLVMValueRef llvm_src = get_src(ctx, src->src);
3840
3841 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3842 }
3843 }
3844
3845 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3846 {
3847 struct hash_entry *entry;
3848 hash_table_foreach(ctx->phis, entry) {
3849 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3850 (LLVMValueRef)entry->data);
3851 }
3852 }
3853
3854
3855 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3856 nir_ssa_undef_instr *instr)
3857 {
3858 unsigned num_components = instr->def.num_components;
3859 LLVMValueRef undef;
3860
3861 if (num_components == 1)
3862 undef = LLVMGetUndef(ctx->i32);
3863 else {
3864 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3865 }
3866 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3867 }
3868
3869 static void visit_jump(struct nir_to_llvm_context *ctx,
3870 nir_jump_instr *instr)
3871 {
3872 switch (instr->type) {
3873 case nir_jump_break:
3874 LLVMBuildBr(ctx->builder, ctx->break_block);
3875 LLVMClearInsertionPosition(ctx->builder);
3876 break;
3877 case nir_jump_continue:
3878 LLVMBuildBr(ctx->builder, ctx->continue_block);
3879 LLVMClearInsertionPosition(ctx->builder);
3880 break;
3881 default:
3882 fprintf(stderr, "Unknown NIR jump instr: ");
3883 nir_print_instr(&instr->instr, stderr);
3884 fprintf(stderr, "\n");
3885 abort();
3886 }
3887 }
3888
3889 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3890 struct exec_list *list);
3891
3892 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3893 {
3894 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3895 nir_foreach_instr(instr, block)
3896 {
3897 switch (instr->type) {
3898 case nir_instr_type_alu:
3899 visit_alu(ctx, nir_instr_as_alu(instr));
3900 break;
3901 case nir_instr_type_load_const:
3902 visit_load_const(ctx, nir_instr_as_load_const(instr));
3903 break;
3904 case nir_instr_type_intrinsic:
3905 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3906 break;
3907 case nir_instr_type_tex:
3908 visit_tex(ctx, nir_instr_as_tex(instr));
3909 break;
3910 case nir_instr_type_phi:
3911 visit_phi(ctx, nir_instr_as_phi(instr));
3912 break;
3913 case nir_instr_type_ssa_undef:
3914 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3915 break;
3916 case nir_instr_type_jump:
3917 visit_jump(ctx, nir_instr_as_jump(instr));
3918 break;
3919 default:
3920 fprintf(stderr, "Unknown NIR instr type: ");
3921 nir_print_instr(instr, stderr);
3922 fprintf(stderr, "\n");
3923 abort();
3924 }
3925 }
3926
3927 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3928 }
3929
3930 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3931 {
3932 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3933
3934 LLVMBasicBlockRef merge_block =
3935 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3936 LLVMBasicBlockRef if_block =
3937 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3938 LLVMBasicBlockRef else_block = merge_block;
3939 if (!exec_list_is_empty(&if_stmt->else_list))
3940 else_block = LLVMAppendBasicBlockInContext(
3941 ctx->context, ctx->main_function, "");
3942
3943 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3944 LLVMConstInt(ctx->i32, 0, false), "");
3945 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3946
3947 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3948 visit_cf_list(ctx, &if_stmt->then_list);
3949 if (LLVMGetInsertBlock(ctx->builder))
3950 LLVMBuildBr(ctx->builder, merge_block);
3951
3952 if (!exec_list_is_empty(&if_stmt->else_list)) {
3953 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3954 visit_cf_list(ctx, &if_stmt->else_list);
3955 if (LLVMGetInsertBlock(ctx->builder))
3956 LLVMBuildBr(ctx->builder, merge_block);
3957 }
3958
3959 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3960 }
3961
3962 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3963 {
3964 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3965 LLVMBasicBlockRef break_parent = ctx->break_block;
3966
3967 ctx->continue_block =
3968 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3969 ctx->break_block =
3970 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3971
3972 LLVMBuildBr(ctx->builder, ctx->continue_block);
3973 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
3974 visit_cf_list(ctx, &loop->body);
3975
3976 if (LLVMGetInsertBlock(ctx->builder))
3977 LLVMBuildBr(ctx->builder, ctx->continue_block);
3978 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
3979
3980 ctx->continue_block = continue_parent;
3981 ctx->break_block = break_parent;
3982 }
3983
3984 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3985 struct exec_list *list)
3986 {
3987 foreach_list_typed(nir_cf_node, node, node, list)
3988 {
3989 switch (node->type) {
3990 case nir_cf_node_block:
3991 visit_block(ctx, nir_cf_node_as_block(node));
3992 break;
3993
3994 case nir_cf_node_if:
3995 visit_if(ctx, nir_cf_node_as_if(node));
3996 break;
3997
3998 case nir_cf_node_loop:
3999 visit_loop(ctx, nir_cf_node_as_loop(node));
4000 break;
4001
4002 default:
4003 assert(0);
4004 }
4005 }
4006 }
4007
4008 static void
4009 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4010 struct nir_variable *variable)
4011 {
4012 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4013 LLVMValueRef t_offset;
4014 LLVMValueRef t_list;
4015 LLVMValueRef args[3];
4016 LLVMValueRef input;
4017 LLVMValueRef buffer_index;
4018 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4019 int idx = variable->data.location;
4020 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4021
4022 variable->data.driver_location = idx * 4;
4023
4024 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4025 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4026 ctx->start_instance, "");
4027 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4028 ctx->shader_info->vs.vgpr_comp_cnt);
4029 } else
4030 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4031 ctx->base_vertex, "");
4032
4033 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4034 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4035
4036 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4037 args[0] = t_list;
4038 args[1] = LLVMConstInt(ctx->i32, 0, false);
4039 args[2] = buffer_index;
4040 input = ac_emit_llvm_intrinsic(&ctx->ac,
4041 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
4042 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND |
4043 AC_FUNC_ATTR_LEGACY);
4044
4045 for (unsigned chan = 0; chan < 4; chan++) {
4046 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4047 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4048 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4049 input, llvm_chan, ""));
4050 }
4051 }
4052 }
4053
4054 static void
4055 handle_gs_input_decl(struct nir_to_llvm_context *ctx,
4056 struct nir_variable *variable)
4057 {
4058 int idx = variable->data.location;
4059
4060 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4061 idx == VARYING_SLOT_CULL_DIST0) {
4062 int length = glsl_get_length(glsl_get_array_element(variable->type));
4063 if (idx == VARYING_SLOT_CLIP_DIST0)
4064 ctx->num_input_clips = length;
4065 else
4066 ctx->num_input_culls = length;
4067 }
4068 }
4069
4070 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4071 unsigned attr,
4072 LLVMValueRef interp_param,
4073 LLVMValueRef prim_mask,
4074 LLVMValueRef result[4])
4075 {
4076 LLVMValueRef attr_number;
4077 unsigned chan;
4078 LLVMValueRef i, j;
4079 bool interp = interp_param != NULL;
4080
4081 attr_number = LLVMConstInt(ctx->i32, attr, false);
4082
4083 /* fs.constant returns the param from the middle vertex, so it's not
4084 * really useful for flat shading. It's meant to be used for custom
4085 * interpolation (but the intrinsic can't fetch from the other two
4086 * vertices).
4087 *
4088 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4089 * to do the right thing. The only reason we use fs.constant is that
4090 * fs.interp cannot be used on integers, because they can be equal
4091 * to NaN.
4092 */
4093 if (interp) {
4094 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4095 LLVMVectorType(ctx->f32, 2), "");
4096
4097 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4098 ctx->i32zero, "");
4099 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4100 ctx->i32one, "");
4101 }
4102
4103 for (chan = 0; chan < 4; chan++) {
4104 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4105
4106 if (interp) {
4107 result[chan] = ac_build_fs_interp(&ctx->ac,
4108 llvm_chan,
4109 attr_number,
4110 prim_mask, i, j);
4111 } else {
4112 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4113 LLVMConstInt(ctx->i32, 2, false),
4114 llvm_chan,
4115 attr_number,
4116 prim_mask);
4117 }
4118 }
4119 }
4120
4121 static void
4122 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4123 struct nir_variable *variable)
4124 {
4125 int idx = variable->data.location;
4126 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4127 LLVMValueRef interp;
4128
4129 variable->data.driver_location = idx * 4;
4130 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4131
4132 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4133 unsigned interp_type;
4134 if (variable->data.sample) {
4135 interp_type = INTERP_SAMPLE;
4136 ctx->shader_info->fs.force_persample = true;
4137 } else if (variable->data.centroid)
4138 interp_type = INTERP_CENTROID;
4139 else
4140 interp_type = INTERP_CENTER;
4141
4142 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4143 } else
4144 interp = NULL;
4145
4146 for (unsigned i = 0; i < attrib_count; ++i)
4147 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4148
4149 }
4150
4151 static void
4152 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4153 struct nir_variable *variable)
4154 {
4155 switch (ctx->stage) {
4156 case MESA_SHADER_VERTEX:
4157 handle_vs_input_decl(ctx, variable);
4158 break;
4159 case MESA_SHADER_FRAGMENT:
4160 handle_fs_input_decl(ctx, variable);
4161 break;
4162 case MESA_SHADER_GEOMETRY:
4163 handle_gs_input_decl(ctx, variable);
4164 break;
4165 default:
4166 break;
4167 }
4168
4169 }
4170
4171 static void
4172 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4173 struct nir_shader *nir)
4174 {
4175 unsigned index = 0;
4176 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4177 LLVMValueRef interp_param;
4178 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4179
4180 if (!(ctx->input_mask & (1ull << i)))
4181 continue;
4182
4183 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4184 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4185 interp_param = *inputs;
4186 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4187 inputs);
4188
4189 if (!interp_param)
4190 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4191 ++index;
4192 } else if (i == VARYING_SLOT_POS) {
4193 for(int i = 0; i < 3; ++i)
4194 inputs[i] = ctx->frag_pos[i];
4195
4196 inputs[3] = ac_emit_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4197 }
4198 }
4199 ctx->shader_info->fs.num_interp = index;
4200 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4201 ctx->shader_info->fs.has_pcoord = true;
4202 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4203 ctx->shader_info->fs.prim_id_input = true;
4204 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4205 ctx->shader_info->fs.layer_input = true;
4206 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4207 }
4208
4209 static LLVMValueRef
4210 ac_build_alloca(struct nir_to_llvm_context *ctx,
4211 LLVMTypeRef type,
4212 const char *name)
4213 {
4214 LLVMBuilderRef builder = ctx->builder;
4215 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4216 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4217 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4218 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4219 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4220 LLVMValueRef res;
4221
4222 if (first_instr) {
4223 LLVMPositionBuilderBefore(first_builder, first_instr);
4224 } else {
4225 LLVMPositionBuilderAtEnd(first_builder, first_block);
4226 }
4227
4228 res = LLVMBuildAlloca(first_builder, type, name);
4229 LLVMBuildStore(builder, LLVMConstNull(type), res);
4230
4231 LLVMDisposeBuilder(first_builder);
4232
4233 return res;
4234 }
4235
4236 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4237 LLVMTypeRef type,
4238 const char *name)
4239 {
4240 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4241 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4242 return ptr;
4243 }
4244
4245 static void
4246 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4247 struct nir_variable *variable)
4248 {
4249 int idx = variable->data.location + variable->data.index;
4250 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4251
4252 variable->data.driver_location = idx * 4;
4253
4254 if (ctx->stage == MESA_SHADER_VERTEX ||
4255 ctx->stage == MESA_SHADER_GEOMETRY) {
4256 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4257 idx == VARYING_SLOT_CULL_DIST0) {
4258 int length = glsl_get_length(variable->type);
4259 if (idx == VARYING_SLOT_CLIP_DIST0) {
4260 if (ctx->stage == MESA_SHADER_VERTEX)
4261 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
4262 ctx->num_output_clips = length;
4263 } else if (idx == VARYING_SLOT_CULL_DIST0) {
4264 if (ctx->stage == MESA_SHADER_VERTEX)
4265 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
4266 ctx->num_output_culls = length;
4267 }
4268 if (length > 4)
4269 attrib_count = 2;
4270 else
4271 attrib_count = 1;
4272 }
4273 }
4274
4275 for (unsigned i = 0; i < attrib_count; ++i) {
4276 for (unsigned chan = 0; chan < 4; chan++) {
4277 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4278 si_build_alloca_undef(ctx, ctx->f32, "");
4279 }
4280 }
4281 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
4282 }
4283
4284 static void
4285 setup_locals(struct nir_to_llvm_context *ctx,
4286 struct nir_function *func)
4287 {
4288 int i, j;
4289 ctx->num_locals = 0;
4290 nir_foreach_variable(variable, &func->impl->locals) {
4291 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4292 variable->data.driver_location = ctx->num_locals * 4;
4293 ctx->num_locals += attrib_count;
4294 }
4295 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4296 if (!ctx->locals)
4297 return;
4298
4299 for (i = 0; i < ctx->num_locals; i++) {
4300 for (j = 0; j < 4; j++) {
4301 ctx->locals[i * 4 + j] =
4302 si_build_alloca_undef(ctx, ctx->f32, "temp");
4303 }
4304 }
4305 }
4306
4307 static LLVMValueRef
4308 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4309 {
4310 v = to_float(ctx, v);
4311 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4312 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4313 }
4314
4315
4316 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4317 LLVMValueRef src0, LLVMValueRef src1)
4318 {
4319 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4320 LLVMValueRef comp[2];
4321
4322 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4323 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4324 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4325 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4326 }
4327
4328 /* Initialize arguments for the shader export intrinsic */
4329 static void
4330 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4331 LLVMValueRef *values,
4332 unsigned target,
4333 LLVMValueRef *args)
4334 {
4335 /* Default is 0xf. Adjusted below depending on the format. */
4336 args[0] = LLVMConstInt(ctx->i32, target != V_008DFC_SQ_EXP_NULL ? 0xf : 0, false);
4337 /* Specify whether the EXEC mask represents the valid mask */
4338 args[1] = LLVMConstInt(ctx->i32, 0, false);
4339
4340 /* Specify whether this is the last export */
4341 args[2] = LLVMConstInt(ctx->i32, 0, false);
4342 /* Specify the target we are exporting */
4343 args[3] = LLVMConstInt(ctx->i32, target, false);
4344
4345 args[4] = LLVMConstInt(ctx->i32, 0, false); /* COMPR flag */
4346 args[5] = LLVMGetUndef(ctx->f32);
4347 args[6] = LLVMGetUndef(ctx->f32);
4348 args[7] = LLVMGetUndef(ctx->f32);
4349 args[8] = LLVMGetUndef(ctx->f32);
4350
4351 if (!values)
4352 return;
4353
4354 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4355 LLVMValueRef val[4];
4356 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4357 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4358 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4359
4360 switch(col_format) {
4361 case V_028714_SPI_SHADER_ZERO:
4362 args[0] = LLVMConstInt(ctx->i32, 0x0, 0);
4363 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_NULL, 0);
4364 break;
4365
4366 case V_028714_SPI_SHADER_32_R:
4367 args[0] = LLVMConstInt(ctx->i32, 0x1, 0);
4368 args[5] = values[0];
4369 break;
4370
4371 case V_028714_SPI_SHADER_32_GR:
4372 args[0] = LLVMConstInt(ctx->i32, 0x3, 0);
4373 args[5] = values[0];
4374 args[6] = values[1];
4375 break;
4376
4377 case V_028714_SPI_SHADER_32_AR:
4378 args[0] = LLVMConstInt(ctx->i32, 0x9, 0);
4379 args[5] = values[0];
4380 args[8] = values[3];
4381 break;
4382
4383 case V_028714_SPI_SHADER_FP16_ABGR:
4384 args[4] = ctx->i32one;
4385
4386 for (unsigned chan = 0; chan < 2; chan++) {
4387 LLVMValueRef pack_args[2] = {
4388 values[2 * chan],
4389 values[2 * chan + 1]
4390 };
4391 LLVMValueRef packed;
4392
4393 packed = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.packf16",
4394 ctx->i32, pack_args, 2,
4395 AC_FUNC_ATTR_READNONE |
4396 AC_FUNC_ATTR_LEGACY);
4397 args[chan + 5] = packed;
4398 }
4399 break;
4400
4401 case V_028714_SPI_SHADER_UNORM16_ABGR:
4402 for (unsigned chan = 0; chan < 4; chan++) {
4403 val[chan] = emit_float_saturate(ctx, values[chan], 0, 1);
4404 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4405 LLVMConstReal(ctx->f32, 65535), "");
4406 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4407 LLVMConstReal(ctx->f32, 0.5), "");
4408 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4409 ctx->i32, "");
4410 }
4411
4412 args[4] = ctx->i32one;
4413 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4414 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4415 break;
4416
4417 case V_028714_SPI_SHADER_SNORM16_ABGR:
4418 for (unsigned chan = 0; chan < 4; chan++) {
4419 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4420 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4421 LLVMConstReal(ctx->f32, 32767), "");
4422
4423 /* If positive, add 0.5, else add -0.5. */
4424 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4425 LLVMBuildSelect(ctx->builder,
4426 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4427 val[chan], ctx->f32zero, ""),
4428 LLVMConstReal(ctx->f32, 0.5),
4429 LLVMConstReal(ctx->f32, -0.5), ""), "");
4430 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4431 }
4432
4433 args[4] = ctx->i32one;
4434 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4435 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4436 break;
4437
4438 case V_028714_SPI_SHADER_UINT16_ABGR: {
4439 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4440
4441 for (unsigned chan = 0; chan < 4; chan++) {
4442 val[chan] = to_integer(ctx, values[chan]);
4443 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4444 }
4445
4446 args[4] = ctx->i32one;
4447 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4448 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4449 break;
4450 }
4451
4452 case V_028714_SPI_SHADER_SINT16_ABGR: {
4453 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4454 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4455
4456 /* Clamp. */
4457 for (unsigned chan = 0; chan < 4; chan++) {
4458 val[chan] = to_integer(ctx, values[chan]);
4459 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4460 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4461 }
4462
4463 args[4] = ctx->i32one;
4464 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4465 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4466 break;
4467 }
4468
4469 default:
4470 case V_028714_SPI_SHADER_32_ABGR:
4471 memcpy(&args[5], values, sizeof(values[0]) * 4);
4472 break;
4473 }
4474 } else
4475 memcpy(&args[5], values, sizeof(values[0]) * 4);
4476
4477 for (unsigned i = 5; i < 9; ++i)
4478 args[i] = to_float(ctx, args[i]);
4479 }
4480
4481 static void
4482 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4483 {
4484 uint32_t param_count = 0;
4485 unsigned target;
4486 unsigned pos_idx, num_pos_exports = 0;
4487 LLVMValueRef args[9];
4488 LLVMValueRef pos_args[4][9] = { { 0 } };
4489 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4490 int i;
4491 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4492 (1ull << VARYING_SLOT_CLIP_DIST1) |
4493 (1ull << VARYING_SLOT_CULL_DIST0) |
4494 (1ull << VARYING_SLOT_CULL_DIST1));
4495
4496 ctx->shader_info->vs.prim_id_output = 0xffffffff;
4497 ctx->shader_info->vs.layer_output = 0xffffffff;
4498 if (clip_mask) {
4499 LLVMValueRef slots[8];
4500 unsigned j;
4501
4502 if (ctx->shader_info->vs.cull_dist_mask)
4503 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_output_clips;
4504
4505 i = VARYING_SLOT_CLIP_DIST0;
4506 for (j = 0; j < ctx->num_output_clips; j++)
4507 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4508 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4509 i = VARYING_SLOT_CULL_DIST0;
4510 for (j = 0; j < ctx->num_output_culls; j++)
4511 slots[ctx->num_output_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4512 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4513
4514 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
4515 slots[i] = LLVMGetUndef(ctx->f32);
4516
4517 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
4518 target = V_008DFC_SQ_EXP_POS + 3;
4519 si_llvm_init_export_args(ctx, &slots[4], target, args);
4520 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4521 args, sizeof(args));
4522 }
4523
4524 target = V_008DFC_SQ_EXP_POS + 2;
4525 si_llvm_init_export_args(ctx, &slots[0], target, args);
4526 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4527 args, sizeof(args));
4528
4529 }
4530
4531 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4532 LLVMValueRef values[4];
4533 if (!(ctx->output_mask & (1ull << i)))
4534 continue;
4535
4536 for (unsigned j = 0; j < 4; j++)
4537 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4538 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4539
4540 if (i == VARYING_SLOT_POS) {
4541 target = V_008DFC_SQ_EXP_POS;
4542 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4543 i == VARYING_SLOT_CLIP_DIST1 ||
4544 i == VARYING_SLOT_CULL_DIST0 ||
4545 i == VARYING_SLOT_CULL_DIST1) {
4546 continue;
4547 } else if (i == VARYING_SLOT_PSIZ) {
4548 ctx->shader_info->vs.writes_pointsize = true;
4549 psize_value = values[0];
4550 continue;
4551 } else if (i == VARYING_SLOT_LAYER) {
4552 ctx->shader_info->vs.writes_layer = true;
4553 layer_value = values[0];
4554 ctx->shader_info->vs.layer_output = param_count;
4555 target = V_008DFC_SQ_EXP_PARAM + param_count;
4556 param_count++;
4557 } else if (i == VARYING_SLOT_VIEWPORT) {
4558 ctx->shader_info->vs.writes_viewport_index = true;
4559 viewport_index_value = values[0];
4560 continue;
4561 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
4562 ctx->shader_info->vs.prim_id_output = param_count;
4563 target = V_008DFC_SQ_EXP_PARAM + param_count;
4564 param_count++;
4565 } else if (i >= VARYING_SLOT_VAR0) {
4566 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4567 target = V_008DFC_SQ_EXP_PARAM + param_count;
4568 param_count++;
4569 }
4570
4571 si_llvm_init_export_args(ctx, values, target, args);
4572
4573 if (target >= V_008DFC_SQ_EXP_POS &&
4574 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4575 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4576 args, sizeof(args));
4577 } else {
4578 ac_emit_llvm_intrinsic(&ctx->ac,
4579 "llvm.SI.export",
4580 ctx->voidt,
4581 args, 9,
4582 AC_FUNC_ATTR_LEGACY);
4583 }
4584 }
4585
4586 /* We need to add the position output manually if it's missing. */
4587 if (!pos_args[0][0]) {
4588 pos_args[0][0] = LLVMConstInt(ctx->i32, 0xf, false);
4589 pos_args[0][1] = ctx->i32zero; /* EXEC mask */
4590 pos_args[0][2] = ctx->i32zero; /* last export? */
4591 pos_args[0][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS, false);
4592 pos_args[0][4] = ctx->i32zero; /* COMPR flag */
4593 pos_args[0][5] = ctx->f32zero; /* X */
4594 pos_args[0][6] = ctx->f32zero; /* Y */
4595 pos_args[0][7] = ctx->f32zero; /* Z */
4596 pos_args[0][8] = ctx->f32one; /* W */
4597 }
4598
4599 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4600 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4601 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4602 if (mask) {
4603 pos_args[1][0] = LLVMConstInt(ctx->i32, mask, false); /* writemask */
4604 pos_args[1][1] = ctx->i32zero; /* EXEC mask */
4605 pos_args[1][2] = ctx->i32zero; /* last export? */
4606 pos_args[1][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + 1, false);
4607 pos_args[1][4] = ctx->i32zero; /* COMPR flag */
4608 pos_args[1][5] = ctx->f32zero; /* X */
4609 pos_args[1][6] = ctx->f32zero; /* Y */
4610 pos_args[1][7] = ctx->f32zero; /* Z */
4611 pos_args[1][8] = ctx->f32zero; /* W */
4612
4613 if (ctx->shader_info->vs.writes_pointsize == true)
4614 pos_args[1][5] = psize_value;
4615 if (ctx->shader_info->vs.writes_layer == true)
4616 pos_args[1][7] = layer_value;
4617 if (ctx->shader_info->vs.writes_viewport_index == true)
4618 pos_args[1][8] = viewport_index_value;
4619 }
4620 for (i = 0; i < 4; i++) {
4621 if (pos_args[i][0])
4622 num_pos_exports++;
4623 }
4624
4625 pos_idx = 0;
4626 for (i = 0; i < 4; i++) {
4627 if (!pos_args[i][0])
4628 continue;
4629
4630 /* Specify the target we are exporting */
4631 pos_args[i][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + pos_idx++, false);
4632 if (pos_idx == num_pos_exports)
4633 pos_args[i][2] = ctx->i32one;
4634 ac_emit_llvm_intrinsic(&ctx->ac,
4635 "llvm.SI.export",
4636 ctx->voidt,
4637 pos_args[i], 9,
4638 AC_FUNC_ATTR_LEGACY);
4639 }
4640
4641 ctx->shader_info->vs.pos_exports = num_pos_exports;
4642 ctx->shader_info->vs.param_exports = param_count;
4643 }
4644
4645 static void
4646 handle_es_outputs_post(struct nir_to_llvm_context *ctx)
4647 {
4648 int j;
4649 uint64_t max_output_written = 0;
4650 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4651 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
4652 int param_index;
4653 int length = 4;
4654 int start = 0;
4655 if (!(ctx->output_mask & (1ull << i)))
4656 continue;
4657
4658 if (i == VARYING_SLOT_CLIP_DIST0) {
4659 length = ctx->num_output_clips;
4660 } else if (i == VARYING_SLOT_CULL_DIST0) {
4661 start = ctx->num_output_clips;
4662 length = ctx->num_output_culls;
4663 }
4664 param_index = shader_io_get_unique_index(i);
4665
4666 if (param_index > max_output_written)
4667 max_output_written = param_index;
4668
4669 for (j = 0; j < length; j++) {
4670 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
4671 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4672
4673 ac_build_buffer_store_dword(&ctx->ac,
4674 ctx->esgs_ring,
4675 out_val, 1,
4676 NULL, ctx->es2gs_offset,
4677 (4 * param_index + j + start) * 4,
4678 1, 1);
4679 }
4680 }
4681 ctx->shader_info->vs.esgs_itemsize = (max_output_written + 1) * 16;
4682 }
4683
4684 static void
4685 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4686 LLVMValueRef *color, unsigned param, bool is_last)
4687 {
4688 LLVMValueRef args[9];
4689 /* Export */
4690 si_llvm_init_export_args(ctx, color, param,
4691 args);
4692
4693 if (is_last) {
4694 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4695 args[2] = ctx->i32one; /* DONE bit */
4696 } else if (args[0] == ctx->i32zero)
4697 return; /* unnecessary NULL export */
4698
4699 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4700 ctx->voidt, args, 9,
4701 AC_FUNC_ATTR_LEGACY);
4702 }
4703
4704 static void
4705 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4706 LLVMValueRef depth, LLVMValueRef stencil,
4707 LLVMValueRef samplemask)
4708 {
4709 LLVMValueRef args[9];
4710 unsigned mask = 0;
4711 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4712 args[2] = ctx->i32one; /* DONE bit */
4713 /* Specify the target we are exporting */
4714 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_MRTZ, false);
4715
4716 args[4] = ctx->i32zero; /* COMP flag */
4717 args[5] = LLVMGetUndef(ctx->f32); /* R, depth */
4718 args[6] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4719 args[7] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4720 args[8] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4721
4722 if (depth) {
4723 args[5] = depth;
4724 mask |= 0x1;
4725 }
4726
4727 if (stencil) {
4728 args[6] = stencil;
4729 mask |= 0x2;
4730 }
4731
4732 if (samplemask) {
4733 args[7] = samplemask;
4734 mask |= 0x04;
4735 }
4736
4737 /* SI (except OLAND) has a bug that it only looks
4738 * at the X writemask component. */
4739 if (ctx->options->chip_class == SI &&
4740 ctx->options->family != CHIP_OLAND)
4741 mask |= 0x01;
4742
4743 args[0] = LLVMConstInt(ctx->i32, mask, false);
4744 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4745 ctx->voidt, args, 9,
4746 AC_FUNC_ATTR_LEGACY);
4747 }
4748
4749 static void
4750 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4751 {
4752 unsigned index = 0;
4753 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4754
4755 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4756 LLVMValueRef values[4];
4757
4758 if (!(ctx->output_mask & (1ull << i)))
4759 continue;
4760
4761 if (i == FRAG_RESULT_DEPTH) {
4762 ctx->shader_info->fs.writes_z = true;
4763 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4764 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4765 } else if (i == FRAG_RESULT_STENCIL) {
4766 ctx->shader_info->fs.writes_stencil = true;
4767 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4768 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4769 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
4770 ctx->shader_info->fs.writes_sample_mask = true;
4771 samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
4772 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4773 } else {
4774 bool last = false;
4775 for (unsigned j = 0; j < 4; j++)
4776 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4777 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4778
4779 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
4780 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4781
4782 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4783 index++;
4784 }
4785 }
4786
4787 if (depth || stencil || samplemask)
4788 si_export_mrt_z(ctx, depth, stencil, samplemask);
4789 else if (!index)
4790 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4791
4792 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4793 }
4794
4795 static void
4796 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4797 {
4798 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
4799 }
4800
4801 static void
4802 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4803 {
4804 switch (ctx->stage) {
4805 case MESA_SHADER_VERTEX:
4806 if (ctx->options->key.vs.as_es)
4807 handle_es_outputs_post(ctx);
4808 else
4809 handle_vs_outputs_post(ctx);
4810 break;
4811 case MESA_SHADER_FRAGMENT:
4812 handle_fs_outputs_post(ctx);
4813 break;
4814 case MESA_SHADER_GEOMETRY:
4815 emit_gs_epilogue(ctx);
4816 break;
4817 default:
4818 break;
4819 }
4820 }
4821
4822 static void
4823 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4824 struct nir_variable *variable, uint32_t *offset, int idx)
4825 {
4826 unsigned size = glsl_count_attribute_slots(variable->type, false);
4827 variable->data.driver_location = *offset;
4828 *offset += size;
4829 }
4830
4831 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4832 {
4833 LLVMPassManagerRef passmgr;
4834 /* Create the pass manager */
4835 passmgr = LLVMCreateFunctionPassManagerForModule(
4836 ctx->module);
4837
4838 /* This pass should eliminate all the load and store instructions */
4839 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4840
4841 /* Add some optimization passes */
4842 LLVMAddScalarReplAggregatesPass(passmgr);
4843 LLVMAddLICMPass(passmgr);
4844 LLVMAddAggressiveDCEPass(passmgr);
4845 LLVMAddCFGSimplificationPass(passmgr);
4846 LLVMAddInstructionCombiningPass(passmgr);
4847
4848 /* Run the pass */
4849 LLVMInitializeFunctionPassManager(passmgr);
4850 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4851 LLVMFinalizeFunctionPassManager(passmgr);
4852
4853 LLVMDisposeBuilder(ctx->builder);
4854 LLVMDisposePassManager(passmgr);
4855 }
4856
4857 static void
4858 ac_setup_rings(struct nir_to_llvm_context *ctx)
4859 {
4860 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4861 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, ctx->i32one);
4862 }
4863
4864 if (ctx->is_gs_copy_shader) {
4865 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4866 }
4867 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4868 LLVMValueRef tmp;
4869 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4870 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4871
4872 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4873
4874 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4875 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4876 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4877 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4878
4879 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4880 }
4881 }
4882
4883 static
4884 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4885 struct nir_shader *nir,
4886 struct ac_shader_variant_info *shader_info,
4887 const struct ac_nir_compiler_options *options)
4888 {
4889 struct nir_to_llvm_context ctx = {0};
4890 struct nir_function *func;
4891 unsigned i;
4892 ctx.options = options;
4893 ctx.shader_info = shader_info;
4894 ctx.context = LLVMContextCreate();
4895 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4896
4897 ac_llvm_context_init(&ctx.ac, ctx.context);
4898 ctx.ac.module = ctx.module;
4899
4900 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4901
4902 memset(shader_info, 0, sizeof(*shader_info));
4903
4904 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4905 setup_types(&ctx);
4906
4907 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4908 ctx.ac.builder = ctx.builder;
4909 ctx.stage = nir->stage;
4910
4911 for (i = 0; i < AC_UD_MAX_SETS; i++)
4912 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4913 for (i = 0; i < AC_UD_MAX_UD; i++)
4914 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4915
4916 create_function(&ctx);
4917
4918 if (nir->stage == MESA_SHADER_COMPUTE) {
4919 int num_shared = 0;
4920 nir_foreach_variable(variable, &nir->shared)
4921 num_shared++;
4922 if (num_shared) {
4923 int idx = 0;
4924 uint32_t shared_size = 0;
4925 LLVMValueRef var;
4926 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4927 nir_foreach_variable(variable, &nir->shared) {
4928 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4929 idx++;
4930 }
4931
4932 shared_size *= 16;
4933 var = LLVMAddGlobalInAddressSpace(ctx.module,
4934 LLVMArrayType(ctx.i8, shared_size),
4935 "compute_lds",
4936 LOCAL_ADDR_SPACE);
4937 LLVMSetAlignment(var, 4);
4938 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4939 }
4940 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4941 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4942
4943 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4944 }
4945
4946 ac_setup_rings(&ctx);
4947
4948 nir_foreach_variable(variable, &nir->inputs)
4949 handle_shader_input_decl(&ctx, variable);
4950
4951 if (nir->stage == MESA_SHADER_FRAGMENT)
4952 handle_fs_inputs_pre(&ctx, nir);
4953
4954 nir_foreach_variable(variable, &nir->outputs)
4955 handle_shader_output_decl(&ctx, variable);
4956
4957 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4958 _mesa_key_pointer_equal);
4959 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4960 _mesa_key_pointer_equal);
4961
4962 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4963
4964 setup_locals(&ctx, func);
4965
4966 visit_cf_list(&ctx, &func->impl->body);
4967 phi_post_pass(&ctx);
4968
4969 handle_shader_outputs_post(&ctx);
4970 LLVMBuildRetVoid(ctx.builder);
4971
4972 ac_llvm_finalize_module(&ctx);
4973 free(ctx.locals);
4974 ralloc_free(ctx.defs);
4975 ralloc_free(ctx.phis);
4976
4977 if (nir->stage == MESA_SHADER_GEOMETRY) {
4978 shader_info->gs.gsvs_vertex_size = util_bitcount64(ctx.output_mask) * 16;
4979 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
4980 nir->info->gs.vertices_out;
4981 }
4982 return ctx.module;
4983 }
4984
4985 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4986 {
4987 unsigned *retval = (unsigned *)context;
4988 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4989 char *description = LLVMGetDiagInfoDescription(di);
4990
4991 if (severity == LLVMDSError) {
4992 *retval = 1;
4993 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4994 description);
4995 }
4996
4997 LLVMDisposeMessage(description);
4998 }
4999
5000 static unsigned ac_llvm_compile(LLVMModuleRef M,
5001 struct ac_shader_binary *binary,
5002 LLVMTargetMachineRef tm)
5003 {
5004 unsigned retval = 0;
5005 char *err;
5006 LLVMContextRef llvm_ctx;
5007 LLVMMemoryBufferRef out_buffer;
5008 unsigned buffer_size;
5009 const char *buffer_data;
5010 LLVMBool mem_err;
5011
5012 /* Setup Diagnostic Handler*/
5013 llvm_ctx = LLVMGetModuleContext(M);
5014
5015 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
5016 &retval);
5017
5018 /* Compile IR*/
5019 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
5020 &err, &out_buffer);
5021
5022 /* Process Errors/Warnings */
5023 if (mem_err) {
5024 fprintf(stderr, "%s: %s", __FUNCTION__, err);
5025 free(err);
5026 retval = 1;
5027 goto out;
5028 }
5029
5030 /* Extract Shader Code*/
5031 buffer_size = LLVMGetBufferSize(out_buffer);
5032 buffer_data = LLVMGetBufferStart(out_buffer);
5033
5034 ac_elf_read(buffer_data, buffer_size, binary);
5035
5036 /* Clean up */
5037 LLVMDisposeMemoryBuffer(out_buffer);
5038
5039 out:
5040 return retval;
5041 }
5042
5043 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
5044 LLVMModuleRef llvm_module,
5045 struct ac_shader_binary *binary,
5046 struct ac_shader_config *config,
5047 struct ac_shader_variant_info *shader_info,
5048 gl_shader_stage stage,
5049 bool dump_shader, bool supports_spill)
5050 {
5051 if (dump_shader)
5052 ac_dump_module(llvm_module);
5053
5054 memset(binary, 0, sizeof(*binary));
5055 int v = ac_llvm_compile(llvm_module, binary, tm);
5056 if (v) {
5057 fprintf(stderr, "compile failed\n");
5058 }
5059
5060 if (dump_shader)
5061 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
5062
5063 ac_shader_binary_read_config(binary, config, 0, supports_spill);
5064
5065 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
5066 LLVMDisposeModule(llvm_module);
5067 LLVMContextDispose(ctx);
5068
5069 if (stage == MESA_SHADER_FRAGMENT) {
5070 shader_info->num_input_vgprs = 0;
5071 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
5072 shader_info->num_input_vgprs += 2;
5073 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
5074 shader_info->num_input_vgprs += 2;
5075 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
5076 shader_info->num_input_vgprs += 2;
5077 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
5078 shader_info->num_input_vgprs += 3;
5079 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
5080 shader_info->num_input_vgprs += 2;
5081 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
5082 shader_info->num_input_vgprs += 2;
5083 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
5084 shader_info->num_input_vgprs += 2;
5085 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
5086 shader_info->num_input_vgprs += 1;
5087 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
5088 shader_info->num_input_vgprs += 1;
5089 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
5090 shader_info->num_input_vgprs += 1;
5091 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5092 shader_info->num_input_vgprs += 1;
5093 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5094 shader_info->num_input_vgprs += 1;
5095 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5096 shader_info->num_input_vgprs += 1;
5097 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5098 shader_info->num_input_vgprs += 1;
5099 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5100 shader_info->num_input_vgprs += 1;
5101 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5102 shader_info->num_input_vgprs += 1;
5103 }
5104 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5105
5106 /* +3 for scratch wave offset and VCC */
5107 config->num_sgprs = MAX2(config->num_sgprs,
5108 shader_info->num_input_sgprs + 3);
5109 }
5110
5111 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5112 struct ac_shader_binary *binary,
5113 struct ac_shader_config *config,
5114 struct ac_shader_variant_info *shader_info,
5115 struct nir_shader *nir,
5116 const struct ac_nir_compiler_options *options,
5117 bool dump_shader)
5118 {
5119
5120 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5121 options);
5122
5123 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5124 switch (nir->stage) {
5125 case MESA_SHADER_COMPUTE:
5126 for (int i = 0; i < 3; ++i)
5127 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5128 break;
5129 case MESA_SHADER_FRAGMENT:
5130 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5131 break;
5132 case MESA_SHADER_GEOMETRY:
5133 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5134 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5135 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5136 shader_info->gs.invocations = nir->info->gs.invocations;
5137 break;
5138 case MESA_SHADER_VERTEX:
5139 shader_info->vs.as_es = options->key.vs.as_es;
5140 break;
5141 default:
5142 break;
5143 }
5144 }
5145
5146 static void
5147 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5148 {
5149 LLVMValueRef args[9];
5150 args[0] = ctx->gsvs_ring;
5151 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5152 args[3] = ctx->i32zero;
5153 args[4] = ctx->i32one; /* OFFEN */
5154 args[5] = ctx->i32zero; /* IDXEN */
5155 args[6] = ctx->i32one; /* GLC */
5156 args[7] = ctx->i32one; /* SLC */
5157 args[8] = ctx->i32zero; /* TFE */
5158
5159 int idx = 0;
5160 int clip_cull_slot = -1;
5161 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5162 int length = 4;
5163 int start = 0;
5164 int slot = idx;
5165 int slot_inc = 1;
5166 if (!(ctx->output_mask & (1ull << i)))
5167 continue;
5168
5169 if (i == VARYING_SLOT_CLIP_DIST1 ||
5170 i == VARYING_SLOT_CULL_DIST1)
5171 continue;
5172
5173 if (i == VARYING_SLOT_CLIP_DIST0 ||
5174 i == VARYING_SLOT_CULL_DIST0) {
5175 /* unpack clip and cull from a single set of slots */
5176 if (clip_cull_slot == -1) {
5177 clip_cull_slot = idx;
5178 if (ctx->num_output_clips + ctx->num_output_culls > 4)
5179 slot_inc = 2;
5180 } else {
5181 slot = clip_cull_slot;
5182 slot_inc = 0;
5183 }
5184 if (i == VARYING_SLOT_CLIP_DIST0)
5185 length = ctx->num_output_clips;
5186 if (i == VARYING_SLOT_CULL_DIST0) {
5187 start = ctx->num_output_clips;
5188 length = ctx->num_output_culls;
5189 }
5190 }
5191
5192 for (unsigned j = 0; j < length; j++) {
5193 LLVMValueRef value;
5194 args[2] = LLVMConstInt(ctx->i32,
5195 (slot * 4 + j + start) *
5196 ctx->gs_max_out_vertices * 16 * 4, false);
5197
5198 value = ac_emit_llvm_intrinsic(&ctx->ac,
5199 "llvm.SI.buffer.load.dword.i32.i32",
5200 ctx->i32, args, 9,
5201 AC_FUNC_ATTR_READONLY |
5202 AC_FUNC_ATTR_LEGACY);
5203
5204 LLVMBuildStore(ctx->builder,
5205 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
5206 }
5207 idx += slot_inc;
5208 }
5209 handle_vs_outputs_post(ctx);
5210 }
5211
5212 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5213 struct nir_shader *geom_shader,
5214 struct ac_shader_binary *binary,
5215 struct ac_shader_config *config,
5216 struct ac_shader_variant_info *shader_info,
5217 const struct ac_nir_compiler_options *options,
5218 bool dump_shader)
5219 {
5220 struct nir_to_llvm_context ctx = {0};
5221 ctx.context = LLVMContextCreate();
5222 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5223 ctx.options = options;
5224 ctx.shader_info = shader_info;
5225
5226 ac_llvm_context_init(&ctx.ac, ctx.context);
5227 ctx.ac.module = ctx.module;
5228
5229 ctx.is_gs_copy_shader = true;
5230 LLVMSetTarget(ctx.module, "amdgcn--");
5231 setup_types(&ctx);
5232
5233 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5234 ctx.ac.builder = ctx.builder;
5235 ctx.stage = MESA_SHADER_VERTEX;
5236
5237 create_function(&ctx);
5238
5239 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5240 ac_setup_rings(&ctx);
5241
5242 nir_foreach_variable(variable, &geom_shader->outputs)
5243 handle_shader_output_decl(&ctx, variable);
5244
5245 ac_gs_copy_shader_emit(&ctx);
5246
5247 LLVMBuildRetVoid(ctx.builder);
5248
5249 ac_llvm_finalize_module(&ctx);
5250
5251 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5252 MESA_SHADER_VERTEX,
5253 dump_shader, options->supports_spill);
5254 }