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[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_util.h"
26 #include "ac_binary.h"
27 #include "sid.h"
28 #include "nir/nir.h"
29 #include "../vulkan/radv_descriptor_set.h"
30 #include "util/bitscan.h"
31 #include <llvm-c/Transforms/Scalar.h>
32
33 enum radeon_llvm_calling_convention {
34 RADEON_LLVM_AMDGPU_VS = 87,
35 RADEON_LLVM_AMDGPU_GS = 88,
36 RADEON_LLVM_AMDGPU_PS = 89,
37 RADEON_LLVM_AMDGPU_CS = 90,
38 };
39
40 #define CONST_ADDR_SPACE 2
41 #define LOCAL_ADDR_SPACE 3
42
43 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
44 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
45
46 #define SENDMSG_GS 2
47 #define SENDMSG_GS_DONE 3
48
49 #define SENDMSG_GS_OP_NOP (0 << 4)
50 #define SENDMSG_GS_OP_CUT (1 << 4)
51 #define SENDMSG_GS_OP_EMIT (2 << 4)
52 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
53
54 enum desc_type {
55 DESC_IMAGE,
56 DESC_FMASK,
57 DESC_SAMPLER,
58 DESC_BUFFER,
59 };
60
61 struct nir_to_llvm_context {
62 struct ac_llvm_context ac;
63 const struct ac_nir_compiler_options *options;
64 struct ac_shader_variant_info *shader_info;
65
66 LLVMContextRef context;
67 LLVMModuleRef module;
68 LLVMBuilderRef builder;
69 LLVMValueRef main_function;
70
71 struct hash_table *defs;
72 struct hash_table *phis;
73
74 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
75 LLVMValueRef ring_offsets;
76 LLVMValueRef push_constants;
77 LLVMValueRef num_work_groups;
78 LLVMValueRef workgroup_ids;
79 LLVMValueRef local_invocation_ids;
80 LLVMValueRef tg_size;
81
82 LLVMValueRef vertex_buffers;
83 LLVMValueRef base_vertex;
84 LLVMValueRef start_instance;
85 LLVMValueRef vertex_id;
86 LLVMValueRef rel_auto_id;
87 LLVMValueRef vs_prim_id;
88 LLVMValueRef instance_id;
89
90 LLVMValueRef es2gs_offset;
91
92 LLVMValueRef gsvs_ring_stride;
93 LLVMValueRef gsvs_num_entries;
94 LLVMValueRef gs2vs_offset;
95 LLVMValueRef gs_wave_id;
96 LLVMValueRef gs_vtx_offset[6];
97 LLVMValueRef gs_prim_id, gs_invocation_id;
98
99 LLVMValueRef esgs_ring;
100 LLVMValueRef gsvs_ring;
101
102 LLVMValueRef prim_mask;
103 LLVMValueRef sample_positions;
104 LLVMValueRef persp_sample, persp_center, persp_centroid;
105 LLVMValueRef linear_sample, linear_center, linear_centroid;
106 LLVMValueRef front_face;
107 LLVMValueRef ancillary;
108 LLVMValueRef frag_pos[4];
109
110 LLVMBasicBlockRef continue_block;
111 LLVMBasicBlockRef break_block;
112
113 LLVMTypeRef i1;
114 LLVMTypeRef i8;
115 LLVMTypeRef i16;
116 LLVMTypeRef i32;
117 LLVMTypeRef i64;
118 LLVMTypeRef v2i32;
119 LLVMTypeRef v3i32;
120 LLVMTypeRef v4i32;
121 LLVMTypeRef v8i32;
122 LLVMTypeRef f32;
123 LLVMTypeRef f16;
124 LLVMTypeRef v2f32;
125 LLVMTypeRef v4f32;
126 LLVMTypeRef v16i8;
127 LLVMTypeRef voidt;
128
129 LLVMValueRef i32zero;
130 LLVMValueRef i32one;
131 LLVMValueRef f32zero;
132 LLVMValueRef f32one;
133 LLVMValueRef v4f32empty;
134
135 unsigned range_md_kind;
136 unsigned uniform_md_kind;
137 unsigned invariant_load_md_kind;
138 LLVMValueRef empty_md;
139 gl_shader_stage stage;
140
141 LLVMValueRef lds;
142 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
143 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
144
145 LLVMValueRef shared_memory;
146 uint64_t input_mask;
147 uint64_t output_mask;
148 int num_locals;
149 LLVMValueRef *locals;
150 bool has_ddxy;
151 unsigned num_clips;
152 unsigned num_culls;
153
154 bool has_ds_bpermute;
155
156 bool is_gs_copy_shader;
157 LLVMValueRef gs_next_vertex;
158 unsigned gs_max_out_vertices;
159 };
160
161 struct ac_tex_info {
162 LLVMValueRef args[12];
163 int arg_count;
164 LLVMTypeRef dst_type;
165 bool has_offset;
166 };
167
168 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
169 nir_deref_var *deref,
170 enum desc_type desc_type);
171 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
172 {
173 return (index * 4) + chan;
174 }
175
176 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
177 {
178 if (slot == VARYING_SLOT_POS)
179 return 0;
180 if (slot == VARYING_SLOT_PSIZ)
181 return 1;
182 if (slot == VARYING_SLOT_CLIP_DIST0)
183 return 2;
184 if (slot == VARYING_SLOT_CLIP_DIST1)
185 return 3;
186 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
187 return 4 + (slot - VARYING_SLOT_VAR0);
188 unreachable("illegal slot in get unique index\n");
189 }
190
191 static unsigned llvm_get_type_size(LLVMTypeRef type)
192 {
193 LLVMTypeKind kind = LLVMGetTypeKind(type);
194
195 switch (kind) {
196 case LLVMIntegerTypeKind:
197 return LLVMGetIntTypeWidth(type) / 8;
198 case LLVMFloatTypeKind:
199 return 4;
200 case LLVMPointerTypeKind:
201 return 8;
202 case LLVMVectorTypeKind:
203 return LLVMGetVectorSize(type) *
204 llvm_get_type_size(LLVMGetElementType(type));
205 default:
206 assert(0);
207 return 0;
208 }
209 }
210
211 static void set_llvm_calling_convention(LLVMValueRef func,
212 gl_shader_stage stage)
213 {
214 enum radeon_llvm_calling_convention calling_conv;
215
216 switch (stage) {
217 case MESA_SHADER_VERTEX:
218 case MESA_SHADER_TESS_CTRL:
219 case MESA_SHADER_TESS_EVAL:
220 calling_conv = RADEON_LLVM_AMDGPU_VS;
221 break;
222 case MESA_SHADER_GEOMETRY:
223 calling_conv = RADEON_LLVM_AMDGPU_GS;
224 break;
225 case MESA_SHADER_FRAGMENT:
226 calling_conv = RADEON_LLVM_AMDGPU_PS;
227 break;
228 case MESA_SHADER_COMPUTE:
229 calling_conv = RADEON_LLVM_AMDGPU_CS;
230 break;
231 default:
232 unreachable("Unhandle shader type");
233 }
234
235 LLVMSetFunctionCallConv(func, calling_conv);
236 }
237
238 static LLVMValueRef
239 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
240 LLVMBuilderRef builder, LLVMTypeRef *return_types,
241 unsigned num_return_elems, LLVMTypeRef *param_types,
242 unsigned param_count, unsigned array_params_mask,
243 unsigned sgpr_params, bool unsafe_math)
244 {
245 LLVMTypeRef main_function_type, ret_type;
246 LLVMBasicBlockRef main_function_body;
247
248 if (num_return_elems)
249 ret_type = LLVMStructTypeInContext(ctx, return_types,
250 num_return_elems, true);
251 else
252 ret_type = LLVMVoidTypeInContext(ctx);
253
254 /* Setup the function */
255 main_function_type =
256 LLVMFunctionType(ret_type, param_types, param_count, 0);
257 LLVMValueRef main_function =
258 LLVMAddFunction(module, "main", main_function_type);
259 main_function_body =
260 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
261 LLVMPositionBuilderAtEnd(builder, main_function_body);
262
263 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
264 for (unsigned i = 0; i < sgpr_params; ++i) {
265 if (array_params_mask & (1 << i)) {
266 LLVMValueRef P = LLVMGetParam(main_function, i);
267 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_BYVAL);
268 ac_add_attr_dereferenceable(P, UINT64_MAX);
269 }
270 else {
271 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_INREG);
272 }
273 }
274
275 if (unsafe_math) {
276 /* These were copied from some LLVM test. */
277 LLVMAddTargetDependentFunctionAttr(main_function,
278 "less-precise-fpmad",
279 "true");
280 LLVMAddTargetDependentFunctionAttr(main_function,
281 "no-infs-fp-math",
282 "true");
283 LLVMAddTargetDependentFunctionAttr(main_function,
284 "no-nans-fp-math",
285 "true");
286 LLVMAddTargetDependentFunctionAttr(main_function,
287 "unsafe-fp-math",
288 "true");
289 }
290 return main_function;
291 }
292
293 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
294 {
295 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
296 CONST_ADDR_SPACE);
297 }
298
299 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
300 int idx,
301 LLVMTypeRef type)
302 {
303 LLVMValueRef offset;
304 LLVMValueRef ptr;
305 int addr_space;
306
307 offset = LLVMConstInt(ctx->i32, idx, false);
308
309 ptr = ctx->shared_memory;
310 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
311 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
312 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
313 return ptr;
314 }
315
316 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
317 {
318 LLVMTypeRef type = LLVMTypeOf(v);
319 if (type == ctx->f32) {
320 return LLVMBuildBitCast(ctx->builder, v, ctx->i32, "");
321 } else if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
322 LLVMTypeRef elem_type = LLVMGetElementType(type);
323 if (elem_type == ctx->f32) {
324 LLVMTypeRef nt = LLVMVectorType(ctx->i32, LLVMGetVectorSize(type));
325 return LLVMBuildBitCast(ctx->builder, v, nt, "");
326 }
327 }
328 return v;
329 }
330
331 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
332 {
333 LLVMTypeRef type = LLVMTypeOf(v);
334 if (type == ctx->i32) {
335 return LLVMBuildBitCast(ctx->builder, v, ctx->f32, "");
336 } else if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
337 LLVMTypeRef elem_type = LLVMGetElementType(type);
338 if (elem_type == ctx->i32) {
339 LLVMTypeRef nt = LLVMVectorType(ctx->f32, LLVMGetVectorSize(type));
340 return LLVMBuildBitCast(ctx->builder, v, nt, "");
341 }
342 }
343 return v;
344 }
345
346 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
347 LLVMValueRef param, unsigned rshift,
348 unsigned bitwidth)
349 {
350 LLVMValueRef value = param;
351 if (rshift)
352 value = LLVMBuildLShr(ctx->builder, value,
353 LLVMConstInt(ctx->i32, rshift, false), "");
354
355 if (rshift + bitwidth < 32) {
356 unsigned mask = (1 << bitwidth) - 1;
357 value = LLVMBuildAnd(ctx->builder, value,
358 LLVMConstInt(ctx->i32, mask, false), "");
359 }
360 return value;
361 }
362
363 static LLVMValueRef build_gep0(struct nir_to_llvm_context *ctx,
364 LLVMValueRef base_ptr, LLVMValueRef index)
365 {
366 LLVMValueRef indices[2] = {
367 ctx->i32zero,
368 index,
369 };
370 return LLVMBuildGEP(ctx->builder, base_ptr,
371 indices, 2, "");
372 }
373
374 static LLVMValueRef build_indexed_load(struct nir_to_llvm_context *ctx,
375 LLVMValueRef base_ptr, LLVMValueRef index,
376 bool uniform)
377 {
378 LLVMValueRef pointer;
379 pointer = build_gep0(ctx, base_ptr, index);
380 if (uniform)
381 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
382 return LLVMBuildLoad(ctx->builder, pointer, "");
383 }
384
385 static LLVMValueRef build_indexed_load_const(struct nir_to_llvm_context *ctx,
386 LLVMValueRef base_ptr, LLVMValueRef index)
387 {
388 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
389 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
390 return result;
391 }
392
393 static void build_tbuffer_store(struct nir_to_llvm_context *ctx,
394 LLVMValueRef rsrc,
395 LLVMValueRef vdata,
396 unsigned num_channels,
397 LLVMValueRef vaddr,
398 LLVMValueRef soffset,
399 unsigned inst_offset,
400 unsigned dfmt,
401 unsigned nfmt,
402 unsigned offen,
403 unsigned idxen,
404 unsigned glc,
405 unsigned slc,
406 unsigned tfe)
407 {
408 LLVMValueRef args[] = {
409 rsrc,
410 vdata,
411 LLVMConstInt(ctx->i32, num_channels, 0),
412 vaddr,
413 soffset,
414 LLVMConstInt(ctx->i32, inst_offset, 0),
415 LLVMConstInt(ctx->i32, dfmt, 0),
416 LLVMConstInt(ctx->i32, nfmt, 0),
417 LLVMConstInt(ctx->i32, offen, 0),
418 LLVMConstInt(ctx->i32, idxen, 0),
419 LLVMConstInt(ctx->i32, glc, 0),
420 LLVMConstInt(ctx->i32, slc, 0),
421 LLVMConstInt(ctx->i32, tfe, 0)
422 };
423
424 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
425 unsigned func = CLAMP(num_channels, 1, 3) - 1;
426 const char *types[] = {"i32", "v2i32", "v4i32"};
427 char name[256];
428 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
429
430 ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->voidt,
431 args, ARRAY_SIZE(args), 0);
432
433 }
434
435 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
436 {
437 ud_info->sgpr_idx = sgpr_idx;
438 ud_info->num_sgprs = num_sgprs;
439 ud_info->indirect = false;
440 ud_info->indirect_offset = 0;
441 }
442
443 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
444 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
445 {
446 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
447 }
448
449 #if 0
450 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
451 uint32_t indirect_offset)
452 {
453 ud_info->sgpr_idx = sgpr_idx;
454 ud_info->num_sgprs = num_sgprs;
455 ud_info->indirect = true;
456 ud_info->indirect_offset = indirect_offset;
457 }
458 #endif
459
460 static void create_function(struct nir_to_llvm_context *ctx)
461 {
462 LLVMTypeRef arg_types[23];
463 unsigned arg_idx = 0;
464 unsigned array_params_mask = 0;
465 unsigned sgpr_count = 0, user_sgpr_count;
466 unsigned i;
467 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
468 unsigned user_sgpr_idx;
469 bool need_push_constants;
470 bool need_ring_offsets = false;
471
472 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
473 if (ctx->stage == MESA_SHADER_GEOMETRY ||
474 ctx->stage == MESA_SHADER_VERTEX ||
475 ctx->is_gs_copy_shader)
476 need_ring_offsets = true;
477
478 need_push_constants = true;
479 if (!ctx->options->layout)
480 need_push_constants = false;
481 else if (!ctx->options->layout->push_constant_size &&
482 !ctx->options->layout->dynamic_offset_count)
483 need_push_constants = false;
484
485 if (need_ring_offsets && !ctx->options->supports_spill) {
486 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
487 }
488
489 /* 1 for each descriptor set */
490 for (unsigned i = 0; i < num_sets; ++i) {
491 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
492 array_params_mask |= (1 << arg_idx);
493 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
494 }
495 }
496
497 if (need_push_constants) {
498 /* 1 for push constants and dynamic descriptors */
499 array_params_mask |= (1 << arg_idx);
500 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
501 }
502
503 switch (ctx->stage) {
504 case MESA_SHADER_COMPUTE:
505 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
506 user_sgpr_count = arg_idx;
507 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
508 arg_types[arg_idx++] = ctx->i32;
509 sgpr_count = arg_idx;
510
511 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
512 break;
513 case MESA_SHADER_VERTEX:
514 if (!ctx->is_gs_copy_shader) {
515 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
516 arg_types[arg_idx++] = ctx->i32; // base vertex
517 arg_types[arg_idx++] = ctx->i32; // start instance
518 }
519 user_sgpr_count = arg_idx;
520 if (ctx->options->key.vs.as_es)
521 arg_types[arg_idx++] = ctx->i32; //es2gs offset
522 sgpr_count = arg_idx;
523 arg_types[arg_idx++] = ctx->i32; // vertex id
524 if (!ctx->is_gs_copy_shader) {
525 arg_types[arg_idx++] = ctx->i32; // rel auto id
526 arg_types[arg_idx++] = ctx->i32; // vs prim id
527 arg_types[arg_idx++] = ctx->i32; // instance id
528 }
529 break;
530 case MESA_SHADER_GEOMETRY:
531 arg_types[arg_idx++] = ctx->i32; // gsvs stride
532 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
533 user_sgpr_count = arg_idx;
534 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
535 arg_types[arg_idx++] = ctx->i32; // wave id
536 sgpr_count = arg_idx;
537 arg_types[arg_idx++] = ctx->i32; // vtx0
538 arg_types[arg_idx++] = ctx->i32; // vtx1
539 arg_types[arg_idx++] = ctx->i32; // prim id
540 arg_types[arg_idx++] = ctx->i32; // vtx2
541 arg_types[arg_idx++] = ctx->i32; // vtx3
542 arg_types[arg_idx++] = ctx->i32; // vtx4
543 arg_types[arg_idx++] = ctx->i32; // vtx5
544 arg_types[arg_idx++] = ctx->i32; // GS instance id
545 break;
546 case MESA_SHADER_FRAGMENT:
547 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
548 user_sgpr_count = arg_idx;
549 arg_types[arg_idx++] = ctx->i32; /* prim mask */
550 sgpr_count = arg_idx;
551 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
552 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
553 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
554 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
555 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
556 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
557 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
558 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
559 arg_types[arg_idx++] = ctx->f32; /* pos x float */
560 arg_types[arg_idx++] = ctx->f32; /* pos y float */
561 arg_types[arg_idx++] = ctx->f32; /* pos z float */
562 arg_types[arg_idx++] = ctx->f32; /* pos w float */
563 arg_types[arg_idx++] = ctx->i32; /* front face */
564 arg_types[arg_idx++] = ctx->i32; /* ancillary */
565 arg_types[arg_idx++] = ctx->f32; /* sample coverage */
566 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
567 break;
568 default:
569 unreachable("Shader stage not implemented");
570 }
571
572 ctx->main_function = create_llvm_function(
573 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
574 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
575 set_llvm_calling_convention(ctx->main_function, ctx->stage);
576
577 ctx->shader_info->num_input_sgprs = 0;
578 ctx->shader_info->num_input_vgprs = 0;
579
580 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
581 for (i = 0; i < user_sgpr_count; i++)
582 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
583
584 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
585 for (; i < sgpr_count; i++)
586 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
587
588 if (ctx->stage != MESA_SHADER_FRAGMENT)
589 for (; i < arg_idx; ++i)
590 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
591
592 arg_idx = 0;
593 user_sgpr_idx = 0;
594
595 if (ctx->options->supports_spill || need_ring_offsets) {
596 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
597 user_sgpr_idx += 2;
598 if (ctx->options->supports_spill) {
599 ctx->ring_offsets = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
600 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
601 NULL, 0, AC_FUNC_ATTR_READNONE);
602 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
603 const_array(ctx->v16i8, 8), "");
604 } else
605 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
606 }
607
608 for (unsigned i = 0; i < num_sets; ++i) {
609 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
610 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
611 user_sgpr_idx += 2;
612 ctx->descriptor_sets[i] =
613 LLVMGetParam(ctx->main_function, arg_idx++);
614 } else
615 ctx->descriptor_sets[i] = NULL;
616 }
617
618 if (need_push_constants) {
619 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
620 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
621 user_sgpr_idx += 2;
622 }
623
624 switch (ctx->stage) {
625 case MESA_SHADER_COMPUTE:
626 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
627 user_sgpr_idx += 3;
628 ctx->num_work_groups =
629 LLVMGetParam(ctx->main_function, arg_idx++);
630 ctx->workgroup_ids =
631 LLVMGetParam(ctx->main_function, arg_idx++);
632 ctx->tg_size =
633 LLVMGetParam(ctx->main_function, arg_idx++);
634 ctx->local_invocation_ids =
635 LLVMGetParam(ctx->main_function, arg_idx++);
636 break;
637 case MESA_SHADER_VERTEX:
638 if (!ctx->is_gs_copy_shader) {
639 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
640 user_sgpr_idx += 2;
641 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
642 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 2);
643 user_sgpr_idx += 2;
644 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
645 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
646 }
647 if (ctx->options->key.vs.as_es)
648 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
649 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
650 if (!ctx->is_gs_copy_shader) {
651 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
652 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
653 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
654 }
655 break;
656 case MESA_SHADER_GEOMETRY:
657 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
658 user_sgpr_idx += 2;
659 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
660 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
661 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
662 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
663 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
664 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
665 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
666 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
667 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
668 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
669 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
670 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
671 break;
672 case MESA_SHADER_FRAGMENT:
673 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
674 user_sgpr_idx += 2;
675 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
676 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
677 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
678 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
679 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
680 arg_idx++;
681 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
682 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
683 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
684 arg_idx++; /* line stipple */
685 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
686 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
687 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
688 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
689 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
690 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
691 break;
692 default:
693 unreachable("Shader stage not implemented");
694 }
695 }
696
697 static void setup_types(struct nir_to_llvm_context *ctx)
698 {
699 LLVMValueRef args[4];
700
701 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
702 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
703 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
704 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
705 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
706 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
707 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
708 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
709 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
710 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
711 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
712 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
713 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
714 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
715 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
716
717 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
718 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
719 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
720 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
721
722 args[0] = ctx->f32zero;
723 args[1] = ctx->f32zero;
724 args[2] = ctx->f32zero;
725 args[3] = ctx->f32one;
726 ctx->v4f32empty = LLVMConstVector(args, 4);
727
728 ctx->range_md_kind = LLVMGetMDKindIDInContext(ctx->context,
729 "range", 5);
730 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(ctx->context,
731 "invariant.load", 14);
732 ctx->uniform_md_kind =
733 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
734 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
735
736 args[0] = LLVMConstReal(ctx->f32, 2.5);
737 }
738
739 static int get_llvm_num_components(LLVMValueRef value)
740 {
741 LLVMTypeRef type = LLVMTypeOf(value);
742 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
743 ? LLVMGetVectorSize(type)
744 : 1;
745 return num_components;
746 }
747
748 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
749 LLVMValueRef value,
750 int index)
751 {
752 int count = get_llvm_num_components(value);
753
754 assert(index < count);
755 if (count == 1)
756 return value;
757
758 return LLVMBuildExtractElement(ctx->builder, value,
759 LLVMConstInt(ctx->i32, index, false), "");
760 }
761
762 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
763 LLVMValueRef value, unsigned count)
764 {
765 unsigned num_components = get_llvm_num_components(value);
766 if (count == num_components)
767 return value;
768
769 LLVMValueRef masks[] = {
770 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
771 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
772
773 if (count == 1)
774 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
775 "");
776
777 LLVMValueRef swizzle = LLVMConstVector(masks, count);
778 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
779 }
780
781 static void
782 build_store_values_extended(struct nir_to_llvm_context *ctx,
783 LLVMValueRef *values,
784 unsigned value_count,
785 unsigned value_stride,
786 LLVMValueRef vec)
787 {
788 LLVMBuilderRef builder = ctx->builder;
789 unsigned i;
790
791 if (value_count == 1) {
792 LLVMBuildStore(builder, vec, values[0]);
793 return;
794 }
795
796 for (i = 0; i < value_count; i++) {
797 LLVMValueRef ptr = values[i * value_stride];
798 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
799 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
800 LLVMBuildStore(builder, value, ptr);
801 }
802 }
803
804 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
805 nir_ssa_def *def)
806 {
807 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
808 if (def->num_components > 1) {
809 type = LLVMVectorType(type, def->num_components);
810 }
811 return type;
812 }
813
814 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
815 {
816 assert(src.is_ssa);
817 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
818 return (LLVMValueRef)entry->data;
819 }
820
821
822 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
823 struct nir_block *b)
824 {
825 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
826 return (LLVMBasicBlockRef)entry->data;
827 }
828
829 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
830 nir_alu_src src,
831 unsigned num_components)
832 {
833 LLVMValueRef value = get_src(ctx, src.src);
834 bool need_swizzle = false;
835
836 assert(value);
837 LLVMTypeRef type = LLVMTypeOf(value);
838 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
839 ? LLVMGetVectorSize(type)
840 : 1;
841
842 for (unsigned i = 0; i < num_components; ++i) {
843 assert(src.swizzle[i] < src_components);
844 if (src.swizzle[i] != i)
845 need_swizzle = true;
846 }
847
848 if (need_swizzle || num_components != src_components) {
849 LLVMValueRef masks[] = {
850 LLVMConstInt(ctx->i32, src.swizzle[0], false),
851 LLVMConstInt(ctx->i32, src.swizzle[1], false),
852 LLVMConstInt(ctx->i32, src.swizzle[2], false),
853 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
854
855 if (src_components > 1 && num_components == 1) {
856 value = LLVMBuildExtractElement(ctx->builder, value,
857 masks[0], "");
858 } else if (src_components == 1 && num_components > 1) {
859 LLVMValueRef values[] = {value, value, value, value};
860 value = ac_build_gather_values(&ctx->ac, values, num_components);
861 } else {
862 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
863 value = LLVMBuildShuffleVector(ctx->builder, value, value,
864 swizzle, "");
865 }
866 }
867 assert(!src.negate);
868 assert(!src.abs);
869 return value;
870 }
871
872 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
873 LLVMIntPredicate pred, LLVMValueRef src0,
874 LLVMValueRef src1)
875 {
876 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
877 return LLVMBuildSelect(ctx->builder, result,
878 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
879 LLVMConstInt(ctx->i32, 0, false), "");
880 }
881
882 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
883 LLVMRealPredicate pred, LLVMValueRef src0,
884 LLVMValueRef src1)
885 {
886 LLVMValueRef result;
887 src0 = to_float(ctx, src0);
888 src1 = to_float(ctx, src1);
889 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
890 return LLVMBuildSelect(ctx->builder, result,
891 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
892 LLVMConstInt(ctx->i32, 0, false), "");
893 }
894
895 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
896 const char *intrin,
897 LLVMValueRef src0)
898 {
899 LLVMValueRef params[] = {
900 to_float(ctx, src0),
901 };
902 return ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->f32, params, 1, AC_FUNC_ATTR_READNONE);
903 }
904
905 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
906 const char *intrin,
907 LLVMValueRef src0, LLVMValueRef src1)
908 {
909 LLVMValueRef params[] = {
910 to_float(ctx, src0),
911 to_float(ctx, src1),
912 };
913 return ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->f32, params, 2, AC_FUNC_ATTR_READNONE);
914 }
915
916 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
917 const char *intrin,
918 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
919 {
920 LLVMValueRef params[] = {
921 to_float(ctx, src0),
922 to_float(ctx, src1),
923 to_float(ctx, src2),
924 };
925 return ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->f32, params, 3, AC_FUNC_ATTR_READNONE);
926 }
927
928 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
929 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
930 {
931 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
932 ctx->i32zero, "");
933 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
934 }
935
936 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
937 LLVMValueRef src0)
938 {
939 LLVMValueRef params[2] = {
940 src0,
941
942 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
943 * add special code to check for x=0. The reason is that
944 * the LLVM behavior for x=0 is different from what we
945 * need here.
946 *
947 * The hardware already implements the correct behavior.
948 */
949 LLVMConstInt(ctx->i32, 1, false),
950 };
951 return ac_emit_llvm_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
952 }
953
954 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
955 LLVMValueRef src0)
956 {
957 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.flbit.i32",
958 ctx->i32, &src0, 1,
959 AC_FUNC_ATTR_READNONE);
960
961 /* The HW returns the last bit index from MSB, but NIR wants
962 * the index from LSB. Invert it by doing "31 - msb". */
963 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
964 msb, "");
965
966 LLVMValueRef all_ones = LLVMConstInt(ctx->i32, -1, true);
967 LLVMValueRef cond = LLVMBuildOr(ctx->builder,
968 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
969 src0, ctx->i32zero, ""),
970 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
971 src0, all_ones, ""), "");
972
973 return LLVMBuildSelect(ctx->builder, cond, all_ones, msb, "");
974 }
975
976 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
977 LLVMValueRef src0)
978 {
979 LLVMValueRef args[2] = {
980 src0,
981 ctx->i32one,
982 };
983 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctlz.i32",
984 ctx->i32, args, ARRAY_SIZE(args),
985 AC_FUNC_ATTR_READNONE);
986
987 /* The HW returns the last bit index from MSB, but NIR wants
988 * the index from LSB. Invert it by doing "31 - msb". */
989 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
990 msb, "");
991
992 return LLVMBuildSelect(ctx->builder,
993 LLVMBuildICmp(ctx->builder, LLVMIntEQ, src0,
994 ctx->i32zero, ""),
995 LLVMConstInt(ctx->i32, -1, true), msb, "");
996 }
997
998 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
999 LLVMIntPredicate pred,
1000 LLVMValueRef src0, LLVMValueRef src1)
1001 {
1002 return LLVMBuildSelect(ctx->builder,
1003 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1004 src0,
1005 src1, "");
1006
1007 }
1008 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
1009 LLVMValueRef src0)
1010 {
1011 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1012 LLVMBuildNeg(ctx->builder, src0, ""));
1013 }
1014
1015 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1016 LLVMValueRef src0)
1017 {
1018 LLVMValueRef cmp, val;
1019
1020 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1021 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1022 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1023 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1024 return val;
1025 }
1026
1027 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1028 LLVMValueRef src0)
1029 {
1030 LLVMValueRef cmp, val;
1031
1032 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1033 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1034 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1035 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1036 return val;
1037 }
1038
1039 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1040 LLVMValueRef src0)
1041 {
1042 const char *intr = "llvm.floor.f32";
1043 LLVMValueRef fsrc0 = to_float(ctx, src0);
1044 LLVMValueRef params[] = {
1045 fsrc0,
1046 };
1047 LLVMValueRef floor = ac_emit_llvm_intrinsic(&ctx->ac, intr,
1048 ctx->f32, params, 1,
1049 AC_FUNC_ATTR_READNONE);
1050 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1051 }
1052
1053 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1054 const char *intrin,
1055 LLVMValueRef src0, LLVMValueRef src1)
1056 {
1057 LLVMTypeRef ret_type;
1058 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1059 LLVMValueRef res;
1060 LLVMValueRef params[] = { src0, src1 };
1061 ret_type = LLVMStructTypeInContext(ctx->context, types,
1062 2, true);
1063
1064 res = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ret_type,
1065 params, 2, AC_FUNC_ATTR_READNONE);
1066
1067 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1068 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1069 return res;
1070 }
1071
1072 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1073 LLVMValueRef src0)
1074 {
1075 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1076 }
1077
1078 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1079 LLVMValueRef src0, LLVMValueRef src1)
1080 {
1081 LLVMValueRef dst64, result;
1082 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1083 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1084
1085 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1086 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1087 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1088 return result;
1089 }
1090
1091 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1092 LLVMValueRef src0, LLVMValueRef src1)
1093 {
1094 LLVMValueRef dst64, result;
1095 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1096 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1097
1098 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1099 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1100 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1101 return result;
1102 }
1103
1104 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1105 const char *intrin,
1106 LLVMValueRef srcs[3])
1107 {
1108 LLVMValueRef result;
1109 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1110 result = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->i32, srcs, 3, AC_FUNC_ATTR_READNONE);
1111
1112 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1113 return result;
1114 }
1115
1116 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1117 LLVMValueRef src0, LLVMValueRef src1,
1118 LLVMValueRef src2, LLVMValueRef src3)
1119 {
1120 LLVMValueRef bfi_args[3], result;
1121
1122 bfi_args[0] = LLVMBuildShl(ctx->builder,
1123 LLVMBuildSub(ctx->builder,
1124 LLVMBuildShl(ctx->builder,
1125 ctx->i32one,
1126 src3, ""),
1127 ctx->i32one, ""),
1128 src2, "");
1129 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1130 bfi_args[2] = src0;
1131
1132 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1133
1134 /* Calculate:
1135 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1136 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1137 */
1138 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1139 LLVMBuildAnd(ctx->builder, bfi_args[0],
1140 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1141
1142 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1143 return result;
1144 }
1145
1146 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1147 LLVMValueRef src0)
1148 {
1149 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1150 int i;
1151 LLVMValueRef comp[2];
1152
1153 src0 = to_float(ctx, src0);
1154 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1155 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1156 for (i = 0; i < 2; i++) {
1157 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1158 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1159 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1160 }
1161
1162 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1163 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1164
1165 return comp[0];
1166 }
1167
1168 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1169 LLVMValueRef src0)
1170 {
1171 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1172 LLVMValueRef temps[2], result, val;
1173 int i;
1174
1175 for (i = 0; i < 2; i++) {
1176 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1177 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1178 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1179 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1180 }
1181
1182 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1183 ctx->i32zero, "");
1184 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1185 ctx->i32one, "");
1186 return result;
1187 }
1188
1189 /**
1190 * Set range metadata on an instruction. This can only be used on load and
1191 * call instructions. If you know an instruction can only produce the values
1192 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1193 * \p lo is the minimum value inclusive.
1194 * \p hi is the maximum value exclusive.
1195 */
1196 static void set_range_metadata(struct nir_to_llvm_context *ctx,
1197 LLVMValueRef value, unsigned lo, unsigned hi)
1198 {
1199 LLVMValueRef range_md, md_args[2];
1200 LLVMTypeRef type = LLVMTypeOf(value);
1201 LLVMContextRef context = LLVMGetTypeContext(type);
1202
1203 md_args[0] = LLVMConstInt(type, lo, false);
1204 md_args[1] = LLVMConstInt(type, hi, false);
1205 range_md = LLVMMDNodeInContext(context, md_args, 2);
1206 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1207 }
1208
1209 static LLVMValueRef get_thread_id(struct nir_to_llvm_context *ctx)
1210 {
1211 LLVMValueRef tid;
1212 LLVMValueRef tid_args[2];
1213 tid_args[0] = LLVMConstInt(ctx->i32, 0xffffffff, false);
1214 tid_args[1] = ctx->i32zero;
1215 tid_args[1] = ac_emit_llvm_intrinsic(&ctx->ac,
1216 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1217 tid_args, 2, AC_FUNC_ATTR_READNONE);
1218
1219 tid = ac_emit_llvm_intrinsic(&ctx->ac,
1220 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1221 tid_args, 2, AC_FUNC_ATTR_READNONE);
1222 set_range_metadata(ctx, tid, 0, 64);
1223 return tid;
1224 }
1225
1226 /*
1227 * SI implements derivatives using the local data store (LDS)
1228 * All writes to the LDS happen in all executing threads at
1229 * the same time. TID is the Thread ID for the current
1230 * thread and is a value between 0 and 63, representing
1231 * the thread's position in the wavefront.
1232 *
1233 * For the pixel shader threads are grouped into quads of four pixels.
1234 * The TIDs of the pixels of a quad are:
1235 *
1236 * +------+------+
1237 * |4n + 0|4n + 1|
1238 * +------+------+
1239 * |4n + 2|4n + 3|
1240 * +------+------+
1241 *
1242 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
1243 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
1244 * the current pixel's column, and masking with 0xfffffffe yields the TID
1245 * of the left pixel of the current pixel's row.
1246 *
1247 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
1248 * adding 2 yields the TID of the pixel below the top pixel.
1249 */
1250 /* masks for thread ID. */
1251 #define TID_MASK_TOP_LEFT 0xfffffffc
1252 #define TID_MASK_TOP 0xfffffffd
1253 #define TID_MASK_LEFT 0xfffffffe
1254 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1255 nir_op op,
1256 LLVMValueRef src0)
1257 {
1258 LLVMValueRef tl, trbl, result;
1259 LLVMValueRef tl_tid, trbl_tid;
1260 LLVMValueRef args[2];
1261 LLVMValueRef thread_id;
1262 unsigned mask;
1263 int idx;
1264 ctx->has_ddxy = true;
1265
1266 if (!ctx->lds && !ctx->has_ds_bpermute)
1267 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1268 LLVMArrayType(ctx->i32, 64),
1269 "ddxy_lds", LOCAL_ADDR_SPACE);
1270
1271 thread_id = get_thread_id(ctx);
1272 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1273 mask = TID_MASK_LEFT;
1274 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1275 mask = TID_MASK_TOP;
1276 else
1277 mask = TID_MASK_TOP_LEFT;
1278
1279 tl_tid = LLVMBuildAnd(ctx->builder, thread_id,
1280 LLVMConstInt(ctx->i32, mask, false), "");
1281 /* for DDX we want to next X pixel, DDY next Y pixel. */
1282 if (op == nir_op_fddx_fine ||
1283 op == nir_op_fddx_coarse ||
1284 op == nir_op_fddx)
1285 idx = 1;
1286 else
1287 idx = 2;
1288
1289 trbl_tid = LLVMBuildAdd(ctx->builder, tl_tid,
1290 LLVMConstInt(ctx->i32, idx, false), "");
1291
1292 if (ctx->has_ds_bpermute) {
1293 args[0] = LLVMBuildMul(ctx->builder, tl_tid,
1294 LLVMConstInt(ctx->i32, 4, false), "");
1295 args[1] = src0;
1296 tl = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.ds.bpermute",
1297 ctx->i32, args, 2,
1298 AC_FUNC_ATTR_READNONE);
1299
1300 args[0] = LLVMBuildMul(ctx->builder, trbl_tid,
1301 LLVMConstInt(ctx->i32, 4, false), "");
1302 trbl = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.ds.bpermute",
1303 ctx->i32, args, 2,
1304 AC_FUNC_ATTR_READNONE);
1305 } else {
1306 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
1307
1308 store_ptr = build_gep0(ctx, ctx->lds, thread_id);
1309 load_ptr0 = build_gep0(ctx, ctx->lds, tl_tid);
1310 load_ptr1 = build_gep0(ctx, ctx->lds, trbl_tid);
1311
1312 LLVMBuildStore(ctx->builder, src0, store_ptr);
1313 tl = LLVMBuildLoad(ctx->builder, load_ptr0, "");
1314 trbl = LLVMBuildLoad(ctx->builder, load_ptr1, "");
1315 }
1316 tl = LLVMBuildBitCast(ctx->builder, tl, ctx->f32, "");
1317 trbl = LLVMBuildBitCast(ctx->builder, trbl, ctx->f32, "");
1318 result = LLVMBuildFSub(ctx->builder, trbl, tl, "");
1319 return result;
1320 }
1321
1322 /*
1323 * this takes an I,J coordinate pair,
1324 * and works out the X and Y derivatives.
1325 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1326 */
1327 static LLVMValueRef emit_ddxy_interp(
1328 struct nir_to_llvm_context *ctx,
1329 LLVMValueRef interp_ij)
1330 {
1331 LLVMValueRef result[4], a;
1332 unsigned i;
1333
1334 for (i = 0; i < 2; i++) {
1335 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1336 LLVMConstInt(ctx->i32, i, false), "");
1337 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1338 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1339 }
1340 return ac_build_gather_values(&ctx->ac, result, 4);
1341 }
1342
1343 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1344 {
1345 LLVMValueRef src[4], result = NULL;
1346 unsigned num_components = instr->dest.dest.ssa.num_components;
1347 unsigned src_components;
1348
1349 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1350 switch (instr->op) {
1351 case nir_op_vec2:
1352 case nir_op_vec3:
1353 case nir_op_vec4:
1354 src_components = 1;
1355 break;
1356 case nir_op_pack_half_2x16:
1357 src_components = 2;
1358 break;
1359 case nir_op_unpack_half_2x16:
1360 src_components = 1;
1361 break;
1362 default:
1363 src_components = num_components;
1364 break;
1365 }
1366 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1367 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1368
1369 switch (instr->op) {
1370 case nir_op_fmov:
1371 case nir_op_imov:
1372 result = src[0];
1373 break;
1374 case nir_op_fneg:
1375 src[0] = to_float(ctx, src[0]);
1376 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1377 break;
1378 case nir_op_ineg:
1379 result = LLVMBuildNeg(ctx->builder, src[0], "");
1380 break;
1381 case nir_op_inot:
1382 result = LLVMBuildNot(ctx->builder, src[0], "");
1383 break;
1384 case nir_op_iadd:
1385 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1386 break;
1387 case nir_op_fadd:
1388 src[0] = to_float(ctx, src[0]);
1389 src[1] = to_float(ctx, src[1]);
1390 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1391 break;
1392 case nir_op_fsub:
1393 src[0] = to_float(ctx, src[0]);
1394 src[1] = to_float(ctx, src[1]);
1395 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1396 break;
1397 case nir_op_isub:
1398 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1399 break;
1400 case nir_op_imul:
1401 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1402 break;
1403 case nir_op_imod:
1404 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1405 break;
1406 case nir_op_umod:
1407 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1408 break;
1409 case nir_op_fmod:
1410 src[0] = to_float(ctx, src[0]);
1411 src[1] = to_float(ctx, src[1]);
1412 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1413 result = emit_intrin_1f_param(ctx, "llvm.floor.f32", result);
1414 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1415 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1416 break;
1417 case nir_op_frem:
1418 src[0] = to_float(ctx, src[0]);
1419 src[1] = to_float(ctx, src[1]);
1420 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1421 break;
1422 case nir_op_irem:
1423 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1424 break;
1425 case nir_op_idiv:
1426 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1427 break;
1428 case nir_op_udiv:
1429 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1430 break;
1431 case nir_op_fmul:
1432 src[0] = to_float(ctx, src[0]);
1433 src[1] = to_float(ctx, src[1]);
1434 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1435 break;
1436 case nir_op_fdiv:
1437 src[0] = to_float(ctx, src[0]);
1438 src[1] = to_float(ctx, src[1]);
1439 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1440 break;
1441 case nir_op_frcp:
1442 src[0] = to_float(ctx, src[0]);
1443 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, src[0]);
1444 break;
1445 case nir_op_iand:
1446 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1447 break;
1448 case nir_op_ior:
1449 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1450 break;
1451 case nir_op_ixor:
1452 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1453 break;
1454 case nir_op_ishl:
1455 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1456 break;
1457 case nir_op_ishr:
1458 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1459 break;
1460 case nir_op_ushr:
1461 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1462 break;
1463 case nir_op_ilt:
1464 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1465 break;
1466 case nir_op_ine:
1467 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1468 break;
1469 case nir_op_ieq:
1470 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1471 break;
1472 case nir_op_ige:
1473 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1474 break;
1475 case nir_op_ult:
1476 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1477 break;
1478 case nir_op_uge:
1479 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1480 break;
1481 case nir_op_feq:
1482 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1483 break;
1484 case nir_op_fne:
1485 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1486 break;
1487 case nir_op_flt:
1488 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1489 break;
1490 case nir_op_fge:
1491 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1492 break;
1493 case nir_op_fabs:
1494 result = emit_intrin_1f_param(ctx, "llvm.fabs.f32", src[0]);
1495 break;
1496 case nir_op_iabs:
1497 result = emit_iabs(ctx, src[0]);
1498 break;
1499 case nir_op_imax:
1500 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1501 break;
1502 case nir_op_imin:
1503 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1504 break;
1505 case nir_op_umax:
1506 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1507 break;
1508 case nir_op_umin:
1509 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1510 break;
1511 case nir_op_isign:
1512 result = emit_isign(ctx, src[0]);
1513 break;
1514 case nir_op_fsign:
1515 src[0] = to_float(ctx, src[0]);
1516 result = emit_fsign(ctx, src[0]);
1517 break;
1518 case nir_op_ffloor:
1519 result = emit_intrin_1f_param(ctx, "llvm.floor.f32", src[0]);
1520 break;
1521 case nir_op_ftrunc:
1522 result = emit_intrin_1f_param(ctx, "llvm.trunc.f32", src[0]);
1523 break;
1524 case nir_op_fceil:
1525 result = emit_intrin_1f_param(ctx, "llvm.ceil.f32", src[0]);
1526 break;
1527 case nir_op_fround_even:
1528 result = emit_intrin_1f_param(ctx, "llvm.rint.f32", src[0]);
1529 break;
1530 case nir_op_ffract:
1531 result = emit_ffract(ctx, src[0]);
1532 break;
1533 case nir_op_fsin:
1534 result = emit_intrin_1f_param(ctx, "llvm.sin.f32", src[0]);
1535 break;
1536 case nir_op_fcos:
1537 result = emit_intrin_1f_param(ctx, "llvm.cos.f32", src[0]);
1538 break;
1539 case nir_op_fsqrt:
1540 result = emit_intrin_1f_param(ctx, "llvm.sqrt.f32", src[0]);
1541 break;
1542 case nir_op_fexp2:
1543 result = emit_intrin_1f_param(ctx, "llvm.exp2.f32", src[0]);
1544 break;
1545 case nir_op_flog2:
1546 result = emit_intrin_1f_param(ctx, "llvm.log2.f32", src[0]);
1547 break;
1548 case nir_op_frsq:
1549 result = emit_intrin_1f_param(ctx, "llvm.sqrt.f32", src[0]);
1550 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, result);
1551 break;
1552 case nir_op_fpow:
1553 result = emit_intrin_2f_param(ctx, "llvm.pow.f32", src[0], src[1]);
1554 break;
1555 case nir_op_fmax:
1556 result = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", src[0], src[1]);
1557 break;
1558 case nir_op_fmin:
1559 result = emit_intrin_2f_param(ctx, "llvm.minnum.f32", src[0], src[1]);
1560 break;
1561 case nir_op_ffma:
1562 result = emit_intrin_3f_param(ctx, "llvm.fma.f32", src[0], src[1], src[2]);
1563 break;
1564 case nir_op_ibitfield_extract:
1565 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.i32", src);
1566 break;
1567 case nir_op_ubitfield_extract:
1568 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.u32", src);
1569 break;
1570 case nir_op_bitfield_insert:
1571 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1572 break;
1573 case nir_op_bitfield_reverse:
1574 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1575 break;
1576 case nir_op_bit_count:
1577 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1578 break;
1579 case nir_op_vec2:
1580 case nir_op_vec3:
1581 case nir_op_vec4:
1582 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1583 src[i] = to_integer(ctx, src[i]);
1584 result = ac_build_gather_values(&ctx->ac, src, num_components);
1585 break;
1586 case nir_op_f2i:
1587 src[0] = to_float(ctx, src[0]);
1588 result = LLVMBuildFPToSI(ctx->builder, src[0], ctx->i32, "");
1589 break;
1590 case nir_op_f2u:
1591 src[0] = to_float(ctx, src[0]);
1592 result = LLVMBuildFPToUI(ctx->builder, src[0], ctx->i32, "");
1593 break;
1594 case nir_op_i2f:
1595 result = LLVMBuildSIToFP(ctx->builder, src[0], ctx->f32, "");
1596 break;
1597 case nir_op_u2f:
1598 result = LLVMBuildUIToFP(ctx->builder, src[0], ctx->f32, "");
1599 break;
1600 case nir_op_bcsel:
1601 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1602 break;
1603 case nir_op_find_lsb:
1604 result = emit_find_lsb(ctx, src[0]);
1605 break;
1606 case nir_op_ufind_msb:
1607 result = emit_ufind_msb(ctx, src[0]);
1608 break;
1609 case nir_op_ifind_msb:
1610 result = emit_ifind_msb(ctx, src[0]);
1611 break;
1612 case nir_op_uadd_carry:
1613 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1614 break;
1615 case nir_op_usub_borrow:
1616 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1617 break;
1618 case nir_op_b2f:
1619 result = emit_b2f(ctx, src[0]);
1620 break;
1621 case nir_op_fquantize2f16:
1622 src[0] = to_float(ctx, src[0]);
1623 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1624 /* need to convert back up to f32 */
1625 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1626 break;
1627 case nir_op_umul_high:
1628 result = emit_umul_high(ctx, src[0], src[1]);
1629 break;
1630 case nir_op_imul_high:
1631 result = emit_imul_high(ctx, src[0], src[1]);
1632 break;
1633 case nir_op_pack_half_2x16:
1634 result = emit_pack_half_2x16(ctx, src[0]);
1635 break;
1636 case nir_op_unpack_half_2x16:
1637 result = emit_unpack_half_2x16(ctx, src[0]);
1638 break;
1639 case nir_op_fddx:
1640 case nir_op_fddy:
1641 case nir_op_fddx_fine:
1642 case nir_op_fddy_fine:
1643 case nir_op_fddx_coarse:
1644 case nir_op_fddy_coarse:
1645 result = emit_ddxy(ctx, instr->op, src[0]);
1646 break;
1647 default:
1648 fprintf(stderr, "Unknown NIR alu instr: ");
1649 nir_print_instr(&instr->instr, stderr);
1650 fprintf(stderr, "\n");
1651 abort();
1652 }
1653
1654 if (result) {
1655 assert(instr->dest.dest.is_ssa);
1656 result = to_integer(ctx, result);
1657 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1658 result);
1659 }
1660 }
1661
1662 static void visit_load_const(struct nir_to_llvm_context *ctx,
1663 nir_load_const_instr *instr)
1664 {
1665 LLVMValueRef values[4], value = NULL;
1666 LLVMTypeRef element_type =
1667 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1668
1669 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1670 switch (instr->def.bit_size) {
1671 case 32:
1672 values[i] = LLVMConstInt(element_type,
1673 instr->value.u32[i], false);
1674 break;
1675 case 64:
1676 values[i] = LLVMConstInt(element_type,
1677 instr->value.u64[i], false);
1678 break;
1679 default:
1680 fprintf(stderr,
1681 "unsupported nir load_const bit_size: %d\n",
1682 instr->def.bit_size);
1683 abort();
1684 }
1685 }
1686 if (instr->def.num_components > 1) {
1687 value = LLVMConstVector(values, instr->def.num_components);
1688 } else
1689 value = values[0];
1690
1691 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1692 }
1693
1694 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1695 LLVMTypeRef type)
1696 {
1697 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1698 return LLVMBuildBitCast(ctx->builder, ptr,
1699 LLVMPointerType(type, addr_space), "");
1700 }
1701
1702 static LLVMValueRef
1703 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1704 {
1705 LLVMValueRef size =
1706 LLVMBuildExtractElement(ctx->builder, descriptor,
1707 LLVMConstInt(ctx->i32, 2, false), "");
1708
1709 /* VI only */
1710 if (ctx->options->chip_class >= VI && in_elements) {
1711 /* On VI, the descriptor contains the size in bytes,
1712 * but TXQ must return the size in elements.
1713 * The stride is always non-zero for resources using TXQ.
1714 */
1715 LLVMValueRef stride =
1716 LLVMBuildExtractElement(ctx->builder, descriptor,
1717 LLVMConstInt(ctx->i32, 1, false), "");
1718 stride = LLVMBuildLShr(ctx->builder, stride,
1719 LLVMConstInt(ctx->i32, 16, false), "");
1720 stride = LLVMBuildAnd(ctx->builder, stride,
1721 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1722
1723 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1724 }
1725 return size;
1726 }
1727
1728 /**
1729 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1730 * intrinsic names).
1731 */
1732 static void build_int_type_name(
1733 LLVMTypeRef type,
1734 char *buf, unsigned bufsize)
1735 {
1736 assert(bufsize >= 6);
1737
1738 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1739 snprintf(buf, bufsize, "v%ui32",
1740 LLVMGetVectorSize(type));
1741 else
1742 strcpy(buf, "i32");
1743 }
1744
1745 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1746 struct ac_tex_info *tinfo,
1747 nir_tex_instr *instr,
1748 const char *intr_name,
1749 unsigned coord_vgpr_index)
1750 {
1751 LLVMValueRef coord = tinfo->args[0];
1752 LLVMValueRef half_texel[2];
1753 int c;
1754
1755 //TODO Rect
1756 {
1757 LLVMValueRef txq_args[10];
1758 int txq_arg_count = 0;
1759 LLVMValueRef size;
1760 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1761 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, false);
1762 txq_args[txq_arg_count++] = tinfo->args[1];
1763 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0xf, 0); /* dmask */
1764 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* unorm */
1765 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
1766 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
1767 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
1768 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
1769 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
1770 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
1771 size = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
1772 txq_args, txq_arg_count,
1773 AC_FUNC_ATTR_READNONE);
1774
1775 for (c = 0; c < 2; c++) {
1776 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1777 LLVMConstInt(ctx->i32, c, false), "");
1778 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1779 half_texel[c] = ac_emit_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1780 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1781 LLVMConstReal(ctx->f32, -0.5), "");
1782 }
1783 }
1784
1785 for (c = 0; c < 2; c++) {
1786 LLVMValueRef tmp;
1787 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1788 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1789 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1790 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1791 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1792 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1793 }
1794
1795 tinfo->args[0] = coord;
1796 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1797 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1798
1799 }
1800
1801 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1802 nir_tex_instr *instr,
1803 struct ac_tex_info *tinfo)
1804 {
1805 const char *name = "llvm.SI.image.sample";
1806 const char *infix = "";
1807 char intr_name[127];
1808 char type[64];
1809 bool is_shadow = instr->is_shadow;
1810 bool has_offset = tinfo->has_offset;
1811 switch (instr->op) {
1812 case nir_texop_txf:
1813 case nir_texop_txf_ms:
1814 case nir_texop_samples_identical:
1815 name = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? "llvm.SI.image.load" :
1816 instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? "llvm.SI.vs.load.input" :
1817 "llvm.SI.image.load.mip";
1818 is_shadow = false;
1819 has_offset = false;
1820 break;
1821 case nir_texop_txb:
1822 infix = ".b";
1823 break;
1824 case nir_texop_txl:
1825 infix = ".l";
1826 break;
1827 case nir_texop_txs:
1828 name = "llvm.SI.getresinfo";
1829 break;
1830 case nir_texop_query_levels:
1831 name = "llvm.SI.getresinfo";
1832 break;
1833 case nir_texop_tex:
1834 if (ctx->stage != MESA_SHADER_FRAGMENT)
1835 infix = ".lz";
1836 break;
1837 case nir_texop_txd:
1838 infix = ".d";
1839 break;
1840 case nir_texop_tg4:
1841 name = "llvm.SI.gather4";
1842 infix = ".lz";
1843 break;
1844 case nir_texop_lod:
1845 name = "llvm.SI.getlod";
1846 is_shadow = false;
1847 has_offset = false;
1848 break;
1849 default:
1850 break;
1851 }
1852
1853 build_int_type_name(LLVMTypeOf(tinfo->args[0]), type, sizeof(type));
1854 sprintf(intr_name, "%s%s%s%s.%s", name, is_shadow ? ".c" : "", infix,
1855 has_offset ? ".o" : "", type);
1856
1857 if (instr->op == nir_texop_tg4) {
1858 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1859 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1860 return radv_lower_gather4_integer(ctx, tinfo, instr, intr_name,
1861 (int)has_offset + (int)is_shadow);
1862 }
1863 }
1864 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1865 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1866
1867 }
1868
1869 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1870 nir_intrinsic_instr *instr)
1871 {
1872 LLVMValueRef index = get_src(ctx, instr->src[0]);
1873 unsigned desc_set = nir_intrinsic_desc_set(instr);
1874 unsigned binding = nir_intrinsic_binding(instr);
1875 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1876 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
1877 unsigned base_offset = layout->binding[binding].offset;
1878 LLVMValueRef offset, stride;
1879
1880 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1881 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1882 desc_ptr = ctx->push_constants;
1883 base_offset = ctx->options->layout->push_constant_size;
1884 base_offset += 16 * layout->binding[binding].dynamic_offset_offset;
1885 stride = LLVMConstInt(ctx->i32, 16, false);
1886 } else
1887 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1888
1889 offset = LLVMConstInt(ctx->i32, base_offset, false);
1890 index = LLVMBuildMul(ctx->builder, index, stride, "");
1891 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1892
1893 desc_ptr = build_gep0(ctx, desc_ptr, offset);
1894 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1895 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1896
1897 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1898 }
1899
1900 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1901 nir_intrinsic_instr *instr)
1902 {
1903 LLVMValueRef ptr, addr;
1904
1905 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1906 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1907
1908 ptr = build_gep0(ctx, ctx->push_constants, addr);
1909 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1910
1911 return LLVMBuildLoad(ctx->builder, ptr, "");
1912 }
1913
1914 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1915 nir_intrinsic_instr *instr)
1916 {
1917 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1918
1919 return get_buffer_size(ctx, desc, false);
1920 }
1921 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1922 nir_intrinsic_instr *instr)
1923 {
1924 const char *store_name;
1925 LLVMTypeRef data_type = ctx->f32;
1926 unsigned writemask = nir_intrinsic_write_mask(instr);
1927 LLVMValueRef base_data, base_offset;
1928 LLVMValueRef params[6];
1929
1930 if (ctx->stage == MESA_SHADER_FRAGMENT)
1931 ctx->shader_info->fs.writes_memory = true;
1932
1933 params[1] = get_src(ctx, instr->src[1]);
1934 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1935 params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
1936 params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1937
1938 if (instr->num_components > 1)
1939 data_type = LLVMVectorType(ctx->f32, instr->num_components);
1940
1941 base_data = to_float(ctx, get_src(ctx, instr->src[0]));
1942 base_data = trim_vector(ctx, base_data, instr->num_components);
1943 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1944 data_type, "");
1945 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1946 while (writemask) {
1947 int start, count;
1948 LLVMValueRef data;
1949 LLVMValueRef offset;
1950 LLVMValueRef tmp;
1951 u_bit_scan_consecutive_range(&writemask, &start, &count);
1952
1953 /* Due to an LLVM limitation, split 3-element writes
1954 * into a 2-element and a 1-element write. */
1955 if (count == 3) {
1956 writemask |= 1 << (start + 2);
1957 count = 2;
1958 }
1959
1960 if (count == 4) {
1961 store_name = "llvm.amdgcn.buffer.store.v4f32";
1962 data = base_data;
1963 } else if (count == 2) {
1964 tmp = LLVMBuildExtractElement(ctx->builder,
1965 base_data, LLVMConstInt(ctx->i32, start, false), "");
1966 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
1967 ctx->i32zero, "");
1968
1969 tmp = LLVMBuildExtractElement(ctx->builder,
1970 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
1971 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
1972 ctx->i32one, "");
1973 store_name = "llvm.amdgcn.buffer.store.v2f32";
1974
1975 } else {
1976 assert(count == 1);
1977 if (get_llvm_num_components(base_data) > 1)
1978 data = LLVMBuildExtractElement(ctx->builder, base_data,
1979 LLVMConstInt(ctx->i32, start, false), "");
1980 else
1981 data = base_data;
1982 store_name = "llvm.amdgcn.buffer.store.f32";
1983 }
1984
1985 offset = base_offset;
1986 if (start != 0) {
1987 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
1988 }
1989 params[0] = data;
1990 params[3] = offset;
1991 ac_emit_llvm_intrinsic(&ctx->ac, store_name,
1992 ctx->voidt, params, 6, 0);
1993 }
1994 }
1995
1996 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
1997 nir_intrinsic_instr *instr)
1998 {
1999 const char *name;
2000 LLVMValueRef params[6];
2001 int arg_count = 0;
2002 if (ctx->stage == MESA_SHADER_FRAGMENT)
2003 ctx->shader_info->fs.writes_memory = true;
2004
2005 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2006 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2007 }
2008 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2009 params[arg_count++] = get_src(ctx, instr->src[0]);
2010 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2011 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2012 params[arg_count++] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2013
2014 switch (instr->intrinsic) {
2015 case nir_intrinsic_ssbo_atomic_add:
2016 name = "llvm.amdgcn.buffer.atomic.add";
2017 break;
2018 case nir_intrinsic_ssbo_atomic_imin:
2019 name = "llvm.amdgcn.buffer.atomic.smin";
2020 break;
2021 case nir_intrinsic_ssbo_atomic_umin:
2022 name = "llvm.amdgcn.buffer.atomic.umin";
2023 break;
2024 case nir_intrinsic_ssbo_atomic_imax:
2025 name = "llvm.amdgcn.buffer.atomic.smax";
2026 break;
2027 case nir_intrinsic_ssbo_atomic_umax:
2028 name = "llvm.amdgcn.buffer.atomic.umax";
2029 break;
2030 case nir_intrinsic_ssbo_atomic_and:
2031 name = "llvm.amdgcn.buffer.atomic.and";
2032 break;
2033 case nir_intrinsic_ssbo_atomic_or:
2034 name = "llvm.amdgcn.buffer.atomic.or";
2035 break;
2036 case nir_intrinsic_ssbo_atomic_xor:
2037 name = "llvm.amdgcn.buffer.atomic.xor";
2038 break;
2039 case nir_intrinsic_ssbo_atomic_exchange:
2040 name = "llvm.amdgcn.buffer.atomic.swap";
2041 break;
2042 case nir_intrinsic_ssbo_atomic_comp_swap:
2043 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2044 break;
2045 default:
2046 abort();
2047 }
2048
2049 return ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2050 }
2051
2052 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2053 nir_intrinsic_instr *instr)
2054 {
2055 const char *load_name;
2056 LLVMTypeRef data_type = ctx->f32;
2057 if (instr->num_components == 3)
2058 data_type = LLVMVectorType(ctx->f32, 4);
2059 else if (instr->num_components > 1)
2060 data_type = LLVMVectorType(ctx->f32, instr->num_components);
2061
2062 if (instr->num_components == 4 || instr->num_components == 3)
2063 load_name = "llvm.amdgcn.buffer.load.v4f32";
2064 else if (instr->num_components == 2)
2065 load_name = "llvm.amdgcn.buffer.load.v2f32";
2066 else if (instr->num_components == 1)
2067 load_name = "llvm.amdgcn.buffer.load.f32";
2068 else
2069 abort();
2070
2071 LLVMValueRef params[] = {
2072 get_src(ctx, instr->src[0]),
2073 LLVMConstInt(ctx->i32, 0, false),
2074 get_src(ctx, instr->src[1]),
2075 LLVMConstInt(ctx->i1, 0, false),
2076 LLVMConstInt(ctx->i1, 0, false),
2077 };
2078
2079 LLVMValueRef ret =
2080 ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2081
2082 if (instr->num_components == 3)
2083 ret = trim_vector(ctx, ret, 3);
2084
2085 return LLVMBuildBitCast(ctx->builder, ret,
2086 get_def_type(ctx, &instr->dest.ssa), "");
2087 }
2088
2089 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2090 nir_intrinsic_instr *instr)
2091 {
2092 LLVMValueRef results[4], ret;
2093 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2094 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2095
2096 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2097
2098 for (unsigned i = 0; i < instr->num_components; ++i) {
2099 LLVMValueRef params[] = {
2100 rsrc,
2101 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2102 offset, "")
2103 };
2104 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2105 params, 2, AC_FUNC_ATTR_READNONE);
2106 }
2107
2108
2109 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2110 return LLVMBuildBitCast(ctx->builder, ret,
2111 get_def_type(ctx, &instr->dest.ssa), "");
2112 }
2113
2114 static void
2115 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2116 bool vs_in, unsigned *vertex_index_out,
2117 unsigned *const_out, LLVMValueRef *indir_out)
2118 {
2119 unsigned const_offset = 0;
2120 LLVMValueRef offset = NULL;
2121
2122 if (vertex_index_out != NULL) {
2123 tail = tail->child;
2124 nir_deref_array *deref_array = nir_deref_as_array(tail);
2125 *vertex_index_out = deref_array->base_offset;
2126 }
2127
2128 while (tail->child != NULL) {
2129 const struct glsl_type *parent_type = tail->type;
2130 tail = tail->child;
2131
2132 if (tail->deref_type == nir_deref_type_array) {
2133 nir_deref_array *deref_array = nir_deref_as_array(tail);
2134 LLVMValueRef index, stride, local_offset;
2135 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2136
2137 const_offset += size * deref_array->base_offset;
2138 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2139 continue;
2140
2141 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2142 index = get_src(ctx, deref_array->indirect);
2143 stride = LLVMConstInt(ctx->i32, size, 0);
2144 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2145
2146 if (offset)
2147 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2148 else
2149 offset = local_offset;
2150 } else if (tail->deref_type == nir_deref_type_struct) {
2151 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2152
2153 for (unsigned i = 0; i < deref_struct->index; i++) {
2154 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2155 const_offset += glsl_count_attribute_slots(ft, vs_in);
2156 }
2157 } else
2158 unreachable("unsupported deref type");
2159
2160 }
2161
2162 if (const_offset && offset)
2163 offset = LLVMBuildAdd(ctx->builder, offset,
2164 LLVMConstInt(ctx->i32, const_offset, 0),
2165 "");
2166
2167 *const_out = const_offset;
2168 *indir_out = offset;
2169 }
2170
2171 static LLVMValueRef
2172 load_gs_input(struct nir_to_llvm_context *ctx,
2173 nir_intrinsic_instr *instr)
2174 {
2175 LLVMValueRef indir_index, vtx_offset;
2176 unsigned const_index;
2177 LLVMValueRef args[9];
2178 unsigned param, vtx_offset_param;
2179 LLVMValueRef value[4], result;
2180 unsigned vertex_index;
2181 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2182 false, &vertex_index,
2183 &const_index, &indir_index);
2184 vtx_offset_param = vertex_index;
2185 assert(vtx_offset_param < 6);
2186 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2187 LLVMConstInt(ctx->i32, 4, false), "");
2188
2189 for (unsigned i = 0; i < instr->num_components; i++) {
2190 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2191 args[0] = ctx->esgs_ring;
2192 args[1] = vtx_offset;
2193 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i) * 256, false);
2194 args[3] = ctx->i32zero;
2195 args[4] = ctx->i32one; /* OFFEN */
2196 args[5] = ctx->i32zero; /* IDXEN */
2197 args[6] = ctx->i32one; /* GLC */
2198 args[7] = ctx->i32zero; /* SLC */
2199 args[8] = ctx->i32zero; /* TFE */
2200
2201 value[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2202 ctx->i32, args, 9, AC_FUNC_ATTR_READONLY);
2203 }
2204 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2205
2206 return result;
2207 }
2208
2209 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2210 nir_intrinsic_instr *instr)
2211 {
2212 LLVMValueRef values[4];
2213 int idx = instr->variables[0]->var->data.driver_location;
2214 int ve = instr->dest.ssa.num_components;
2215 LLVMValueRef indir_index;
2216 unsigned const_index;
2217 switch (instr->variables[0]->var->data.mode) {
2218 case nir_var_shader_in:
2219 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2220 return load_gs_input(ctx, instr);
2221 }
2222 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2223 ctx->stage == MESA_SHADER_VERTEX, NULL,
2224 &const_index, &indir_index);
2225 for (unsigned chan = 0; chan < ve; chan++) {
2226 if (indir_index) {
2227 unsigned count = glsl_count_attribute_slots(
2228 instr->variables[0]->var->type,
2229 ctx->stage == MESA_SHADER_VERTEX);
2230 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2231 &ctx->ac, ctx->inputs + idx + chan, count,
2232 4, false);
2233
2234 values[chan] = LLVMBuildExtractElement(ctx->builder,
2235 tmp_vec,
2236 indir_index, "");
2237 } else
2238 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2239 }
2240 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2241 break;
2242 case nir_var_local:
2243 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2244 NULL, &const_index, &indir_index);
2245 for (unsigned chan = 0; chan < ve; chan++) {
2246 if (indir_index) {
2247 unsigned count = glsl_count_attribute_slots(
2248 instr->variables[0]->var->type, false);
2249 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2250 &ctx->ac, ctx->locals + idx + chan, count,
2251 4, true);
2252
2253 values[chan] = LLVMBuildExtractElement(ctx->builder,
2254 tmp_vec,
2255 indir_index, "");
2256 } else {
2257 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2258 }
2259 }
2260 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2261 case nir_var_shader_out:
2262 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2263 NULL, &const_index, &indir_index);
2264 for (unsigned chan = 0; chan < ve; chan++) {
2265 if (indir_index) {
2266 unsigned count = glsl_count_attribute_slots(
2267 instr->variables[0]->var->type, false);
2268 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2269 &ctx->ac, ctx->outputs + idx + chan, count,
2270 4, true);
2271
2272 values[chan] = LLVMBuildExtractElement(ctx->builder,
2273 tmp_vec,
2274 indir_index, "");
2275 } else {
2276 values[chan] = LLVMBuildLoad(ctx->builder,
2277 ctx->outputs[idx + chan + const_index * 4],
2278 "");
2279 }
2280 }
2281 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2282 case nir_var_shared: {
2283 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2284 NULL, &const_index, &indir_index);
2285 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2286 LLVMValueRef derived_ptr;
2287
2288 for (unsigned chan = 0; chan < ve; chan++) {
2289 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2290 if (indir_index)
2291 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2292 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2293 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2294 }
2295 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2296 }
2297 default:
2298 break;
2299 }
2300 return NULL;
2301 }
2302
2303 static void
2304 visit_store_var(struct nir_to_llvm_context *ctx,
2305 nir_intrinsic_instr *instr)
2306 {
2307 LLVMValueRef temp_ptr, value;
2308 int idx = instr->variables[0]->var->data.driver_location;
2309 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2310 int writemask = instr->const_index[0];
2311 LLVMValueRef indir_index;
2312 unsigned const_index;
2313 switch (instr->variables[0]->var->data.mode) {
2314 case nir_var_shader_out:
2315 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2316 NULL, &const_index, &indir_index);
2317 for (unsigned chan = 0; chan < 4; chan++) {
2318 int stride = 4;
2319 if (!(writemask & (1 << chan)))
2320 continue;
2321 if (get_llvm_num_components(src) == 1)
2322 value = src;
2323 else
2324 value = LLVMBuildExtractElement(ctx->builder, src,
2325 LLVMConstInt(ctx->i32,
2326 chan, false),
2327 "");
2328
2329 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2330 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2331 stride = 1;
2332 if (indir_index) {
2333 unsigned count = glsl_count_attribute_slots(
2334 instr->variables[0]->var->type, false);
2335 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2336 &ctx->ac, ctx->outputs + idx + chan, count,
2337 stride, true);
2338
2339 if (get_llvm_num_components(tmp_vec) > 1) {
2340 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2341 value, indir_index, "");
2342 } else
2343 tmp_vec = value;
2344 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2345 count, stride, tmp_vec);
2346
2347 } else {
2348 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2349
2350 LLVMBuildStore(ctx->builder, value, temp_ptr);
2351 }
2352 }
2353 break;
2354 case nir_var_local:
2355 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2356 NULL, &const_index, &indir_index);
2357 for (unsigned chan = 0; chan < 4; chan++) {
2358 if (!(writemask & (1 << chan)))
2359 continue;
2360
2361 if (get_llvm_num_components(src) == 1)
2362 value = src;
2363 else
2364 value = LLVMBuildExtractElement(ctx->builder, src,
2365 LLVMConstInt(ctx->i32, chan, false), "");
2366 if (indir_index) {
2367 unsigned count = glsl_count_attribute_slots(
2368 instr->variables[0]->var->type, false);
2369 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2370 &ctx->ac, ctx->locals + idx + chan, count,
2371 4, true);
2372
2373 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2374 value, indir_index, "");
2375 build_store_values_extended(ctx, ctx->locals + idx + chan,
2376 count, 4, tmp_vec);
2377 } else {
2378 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2379
2380 LLVMBuildStore(ctx->builder, value, temp_ptr);
2381 }
2382 }
2383 break;
2384 case nir_var_shared: {
2385 LLVMValueRef ptr;
2386 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2387 NULL, &const_index, &indir_index);
2388
2389 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2390 LLVMValueRef derived_ptr;
2391
2392 for (unsigned chan = 0; chan < 4; chan++) {
2393 if (!(writemask & (1 << chan)))
2394 continue;
2395
2396 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2397
2398 if (get_llvm_num_components(src) == 1)
2399 value = src;
2400 else
2401 value = LLVMBuildExtractElement(ctx->builder, src,
2402 LLVMConstInt(ctx->i32,
2403 chan, false),
2404 "");
2405
2406 if (indir_index)
2407 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2408
2409 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2410 LLVMBuildStore(ctx->builder,
2411 to_integer(ctx, value), derived_ptr);
2412 }
2413 break;
2414 }
2415 default:
2416 break;
2417 }
2418 }
2419
2420 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2421 {
2422 switch (dim) {
2423 case GLSL_SAMPLER_DIM_BUF:
2424 return 1;
2425 case GLSL_SAMPLER_DIM_1D:
2426 return array ? 2 : 1;
2427 case GLSL_SAMPLER_DIM_2D:
2428 return array ? 3 : 2;
2429 case GLSL_SAMPLER_DIM_MS:
2430 return array ? 4 : 3;
2431 case GLSL_SAMPLER_DIM_3D:
2432 case GLSL_SAMPLER_DIM_CUBE:
2433 return 3;
2434 case GLSL_SAMPLER_DIM_RECT:
2435 case GLSL_SAMPLER_DIM_SUBPASS:
2436 return 2;
2437 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2438 return 3;
2439 default:
2440 break;
2441 }
2442 return 0;
2443 }
2444
2445 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2446 nir_intrinsic_instr *instr)
2447 {
2448 const struct glsl_type *type = instr->variables[0]->var->type;
2449 if(instr->variables[0]->deref.child)
2450 type = instr->variables[0]->deref.child->type;
2451
2452 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2453 LLVMValueRef coords[4];
2454 LLVMValueRef masks[] = {
2455 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2456 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2457 };
2458 LLVMValueRef res;
2459 int count;
2460 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2461 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2462 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2463 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2464 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2465
2466 count = image_type_to_components_count(dim,
2467 glsl_sampler_type_is_array(type));
2468
2469 if (count == 1) {
2470 if (instr->src[0].ssa->num_components)
2471 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2472 else
2473 res = src0;
2474 } else {
2475 int chan;
2476 if (is_ms)
2477 count--;
2478 for (chan = 0; chan < count; ++chan) {
2479 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2480 }
2481
2482 if (add_frag_pos) {
2483 for (chan = 0; chan < count; ++chan)
2484 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2485 }
2486 if (is_ms) {
2487 coords[count] = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2488 count++;
2489 }
2490
2491 if (count == 3) {
2492 coords[3] = LLVMGetUndef(ctx->i32);
2493 count = 4;
2494 }
2495 res = ac_build_gather_values(&ctx->ac, coords, count);
2496 }
2497 return res;
2498 }
2499
2500 static void build_type_name_for_intr(
2501 LLVMTypeRef type,
2502 char *buf, unsigned bufsize)
2503 {
2504 LLVMTypeRef elem_type = type;
2505
2506 assert(bufsize >= 8);
2507
2508 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
2509 int ret = snprintf(buf, bufsize, "v%u",
2510 LLVMGetVectorSize(type));
2511 if (ret < 0) {
2512 char *type_name = LLVMPrintTypeToString(type);
2513 fprintf(stderr, "Error building type name for: %s\n",
2514 type_name);
2515 return;
2516 }
2517 elem_type = LLVMGetElementType(type);
2518 buf += ret;
2519 bufsize -= ret;
2520 }
2521 switch (LLVMGetTypeKind(elem_type)) {
2522 default: break;
2523 case LLVMIntegerTypeKind:
2524 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
2525 break;
2526 case LLVMFloatTypeKind:
2527 snprintf(buf, bufsize, "f32");
2528 break;
2529 case LLVMDoubleTypeKind:
2530 snprintf(buf, bufsize, "f64");
2531 break;
2532 }
2533 }
2534
2535 static void get_image_intr_name(const char *base_name,
2536 LLVMTypeRef data_type,
2537 LLVMTypeRef coords_type,
2538 LLVMTypeRef rsrc_type,
2539 char *out_name, unsigned out_len)
2540 {
2541 char coords_type_name[8];
2542
2543 build_type_name_for_intr(coords_type, coords_type_name,
2544 sizeof(coords_type_name));
2545
2546 if (HAVE_LLVM <= 0x0309) {
2547 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
2548 } else {
2549 char data_type_name[8];
2550 char rsrc_type_name[8];
2551
2552 build_type_name_for_intr(data_type, data_type_name,
2553 sizeof(data_type_name));
2554 build_type_name_for_intr(rsrc_type, rsrc_type_name,
2555 sizeof(rsrc_type_name));
2556 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
2557 data_type_name, coords_type_name, rsrc_type_name);
2558 }
2559 }
2560
2561 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2562 nir_intrinsic_instr *instr)
2563 {
2564 LLVMValueRef params[7];
2565 LLVMValueRef res;
2566 char intrinsic_name[64];
2567 const nir_variable *var = instr->variables[0]->var;
2568 const struct glsl_type *type = var->type;
2569 if(instr->variables[0]->deref.child)
2570 type = instr->variables[0]->deref.child->type;
2571
2572 type = glsl_without_array(type);
2573 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2574 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2575 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2576 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2577 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2578 params[3] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2579 params[4] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2580 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2581 params, 5, 0);
2582
2583 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2584 res = to_integer(ctx, res);
2585 } else {
2586 bool is_da = glsl_sampler_type_is_array(type) ||
2587 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2588 LLVMValueRef da = is_da ? ctx->i32one : ctx->i32zero;
2589 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2590 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2591
2592 params[0] = get_image_coords(ctx, instr);
2593 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2594 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2595 if (HAVE_LLVM <= 0x0309) {
2596 params[3] = LLVMConstInt(ctx->i1, 0, false); /* r128 */
2597 params[4] = da;
2598 params[5] = glc;
2599 params[6] = slc;
2600 } else {
2601 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2602 params[3] = glc;
2603 params[4] = slc;
2604 params[5] = lwe;
2605 params[6] = da;
2606 }
2607
2608 get_image_intr_name("llvm.amdgcn.image.load",
2609 ctx->v4f32, /* vdata */
2610 LLVMTypeOf(params[0]), /* coords */
2611 LLVMTypeOf(params[1]), /* rsrc */
2612 intrinsic_name, sizeof(intrinsic_name));
2613
2614 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2615 params, 7, AC_FUNC_ATTR_READONLY);
2616 }
2617 return to_integer(ctx, res);
2618 }
2619
2620 static void visit_image_store(struct nir_to_llvm_context *ctx,
2621 nir_intrinsic_instr *instr)
2622 {
2623 LLVMValueRef params[8];
2624 char intrinsic_name[64];
2625 const nir_variable *var = instr->variables[0]->var;
2626 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2627 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2628 const struct glsl_type *type = glsl_without_array(var->type);
2629
2630 if (ctx->stage == MESA_SHADER_FRAGMENT)
2631 ctx->shader_info->fs.writes_memory = true;
2632
2633 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2634 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2635 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2636 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2637 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2638 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2639 params[4] = i1false; /* glc */
2640 params[5] = i1false; /* slc */
2641 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2642 params, 6, 0);
2643 } else {
2644 bool is_da = glsl_sampler_type_is_array(type) ||
2645 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2646 LLVMValueRef da = is_da ? i1true : i1false;
2647 LLVMValueRef glc = i1false;
2648 LLVMValueRef slc = i1false;
2649
2650 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2651 params[1] = get_image_coords(ctx, instr); /* coords */
2652 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2653 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2654 if (HAVE_LLVM <= 0x0309) {
2655 params[4] = i1false; /* r128 */
2656 params[5] = da;
2657 params[6] = glc;
2658 params[7] = slc;
2659 } else {
2660 LLVMValueRef lwe = i1false;
2661 params[4] = glc;
2662 params[5] = slc;
2663 params[6] = lwe;
2664 params[7] = da;
2665 }
2666
2667 get_image_intr_name("llvm.amdgcn.image.store",
2668 LLVMTypeOf(params[0]), /* vdata */
2669 LLVMTypeOf(params[1]), /* coords */
2670 LLVMTypeOf(params[2]), /* rsrc */
2671 intrinsic_name, sizeof(intrinsic_name));
2672
2673 ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2674 params, 8, 0);
2675 }
2676
2677 }
2678
2679 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2680 nir_intrinsic_instr *instr)
2681 {
2682 LLVMValueRef params[6];
2683 int param_count = 0;
2684 const nir_variable *var = instr->variables[0]->var;
2685 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2686 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2687 const char *base_name = "llvm.amdgcn.image.atomic";
2688 const char *atomic_name;
2689 LLVMValueRef coords;
2690 char intrinsic_name[32], coords_type[8];
2691 const struct glsl_type *type = glsl_without_array(var->type);
2692
2693 if (ctx->stage == MESA_SHADER_FRAGMENT)
2694 ctx->shader_info->fs.writes_memory = true;
2695
2696 params[param_count++] = get_src(ctx, instr->src[2]);
2697 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2698 params[param_count++] = get_src(ctx, instr->src[3]);
2699
2700 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2701 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2702 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2703 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2704 params[param_count++] = ctx->i32zero; /* voffset */
2705 params[param_count++] = i1false; /* glc */
2706 params[param_count++] = i1false; /* slc */
2707 } else {
2708 bool da = glsl_sampler_type_is_array(type) ||
2709 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2710
2711 coords = params[param_count++] = get_image_coords(ctx, instr);
2712 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2713 params[param_count++] = i1false; /* r128 */
2714 params[param_count++] = da ? i1true : i1false; /* da */
2715 params[param_count++] = i1false; /* slc */
2716 }
2717
2718 switch (instr->intrinsic) {
2719 case nir_intrinsic_image_atomic_add:
2720 atomic_name = "add";
2721 break;
2722 case nir_intrinsic_image_atomic_min:
2723 atomic_name = "smin";
2724 break;
2725 case nir_intrinsic_image_atomic_max:
2726 atomic_name = "smax";
2727 break;
2728 case nir_intrinsic_image_atomic_and:
2729 atomic_name = "and";
2730 break;
2731 case nir_intrinsic_image_atomic_or:
2732 atomic_name = "or";
2733 break;
2734 case nir_intrinsic_image_atomic_xor:
2735 atomic_name = "xor";
2736 break;
2737 case nir_intrinsic_image_atomic_exchange:
2738 atomic_name = "swap";
2739 break;
2740 case nir_intrinsic_image_atomic_comp_swap:
2741 atomic_name = "cmpswap";
2742 break;
2743 default:
2744 abort();
2745 }
2746 build_int_type_name(LLVMTypeOf(coords),
2747 coords_type, sizeof(coords_type));
2748
2749 snprintf(intrinsic_name, sizeof(intrinsic_name),
2750 "%s.%s.%s", base_name, atomic_name, coords_type);
2751 return ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2752 }
2753
2754 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2755 nir_intrinsic_instr *instr)
2756 {
2757 LLVMValueRef res;
2758 LLVMValueRef params[10];
2759 const nir_variable *var = instr->variables[0]->var;
2760 const struct glsl_type *type = instr->variables[0]->var->type;
2761 bool da = glsl_sampler_type_is_array(var->type) ||
2762 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2763 if(instr->variables[0]->deref.child)
2764 type = instr->variables[0]->deref.child->type;
2765
2766 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2767 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2768 params[0] = ctx->i32zero;
2769 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2770 params[2] = LLVMConstInt(ctx->i32, 15, false);
2771 params[3] = ctx->i32zero;
2772 params[4] = ctx->i32zero;
2773 params[5] = da ? ctx->i32one : ctx->i32zero;
2774 params[6] = ctx->i32zero;
2775 params[7] = ctx->i32zero;
2776 params[8] = ctx->i32zero;
2777 params[9] = ctx->i32zero;
2778
2779 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
2780 params, 10, AC_FUNC_ATTR_READNONE);
2781
2782 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2783 glsl_sampler_type_is_array(type)) {
2784 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2785 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2786 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2787 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2788 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2789 }
2790 return res;
2791 }
2792
2793 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2794 {
2795 LLVMValueRef args[1] = {
2796 LLVMConstInt(ctx->i32, 0xf70, false),
2797 };
2798 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2799 ctx->voidt, args, 1, 0);
2800 }
2801
2802 static void emit_barrier(struct nir_to_llvm_context *ctx)
2803 {
2804 // TODO tess
2805 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2806 ctx->voidt, NULL, 0, 0);
2807 }
2808
2809 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2810 nir_intrinsic_instr *instr)
2811 {
2812 LLVMValueRef cond;
2813 ctx->shader_info->fs.can_discard = true;
2814
2815 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2816 get_src(ctx, instr->src[0]),
2817 ctx->i32zero, "");
2818
2819 cond = LLVMBuildSelect(ctx->builder, cond,
2820 LLVMConstReal(ctx->f32, -1.0f),
2821 ctx->f32zero, "");
2822 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
2823 ctx->voidt,
2824 &cond, 1, 0);
2825 }
2826
2827 static LLVMValueRef
2828 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2829 {
2830 LLVMValueRef result;
2831 LLVMValueRef thread_id = get_thread_id(ctx);
2832 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2833 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2834
2835 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2836 }
2837
2838 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2839 nir_intrinsic_instr *instr)
2840 {
2841 LLVMValueRef ptr, result;
2842 int idx = instr->variables[0]->var->data.driver_location;
2843 LLVMValueRef src = get_src(ctx, instr->src[0]);
2844 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2845
2846 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2847 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2848 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2849 ptr, src, src1,
2850 LLVMAtomicOrderingSequentiallyConsistent,
2851 LLVMAtomicOrderingSequentiallyConsistent,
2852 false);
2853 } else {
2854 LLVMAtomicRMWBinOp op;
2855 switch (instr->intrinsic) {
2856 case nir_intrinsic_var_atomic_add:
2857 op = LLVMAtomicRMWBinOpAdd;
2858 break;
2859 case nir_intrinsic_var_atomic_umin:
2860 op = LLVMAtomicRMWBinOpUMin;
2861 break;
2862 case nir_intrinsic_var_atomic_umax:
2863 op = LLVMAtomicRMWBinOpUMax;
2864 break;
2865 case nir_intrinsic_var_atomic_imin:
2866 op = LLVMAtomicRMWBinOpMin;
2867 break;
2868 case nir_intrinsic_var_atomic_imax:
2869 op = LLVMAtomicRMWBinOpMax;
2870 break;
2871 case nir_intrinsic_var_atomic_and:
2872 op = LLVMAtomicRMWBinOpAnd;
2873 break;
2874 case nir_intrinsic_var_atomic_or:
2875 op = LLVMAtomicRMWBinOpOr;
2876 break;
2877 case nir_intrinsic_var_atomic_xor:
2878 op = LLVMAtomicRMWBinOpXor;
2879 break;
2880 case nir_intrinsic_var_atomic_exchange:
2881 op = LLVMAtomicRMWBinOpXchg;
2882 break;
2883 default:
2884 return NULL;
2885 }
2886
2887 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2888 LLVMAtomicOrderingSequentiallyConsistent,
2889 false);
2890 }
2891 return result;
2892 }
2893
2894 #define INTERP_CENTER 0
2895 #define INTERP_CENTROID 1
2896 #define INTERP_SAMPLE 2
2897
2898 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2899 enum glsl_interp_mode interp, unsigned location)
2900 {
2901 switch (interp) {
2902 case INTERP_MODE_FLAT:
2903 default:
2904 return NULL;
2905 case INTERP_MODE_SMOOTH:
2906 case INTERP_MODE_NONE:
2907 if (location == INTERP_CENTER)
2908 return ctx->persp_center;
2909 else if (location == INTERP_CENTROID)
2910 return ctx->persp_centroid;
2911 else if (location == INTERP_SAMPLE)
2912 return ctx->persp_sample;
2913 break;
2914 case INTERP_MODE_NOPERSPECTIVE:
2915 if (location == INTERP_CENTER)
2916 return ctx->linear_center;
2917 else if (location == INTERP_CENTROID)
2918 return ctx->linear_centroid;
2919 else if (location == INTERP_SAMPLE)
2920 return ctx->linear_sample;
2921 break;
2922 }
2923 return NULL;
2924 }
2925
2926 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
2927 LLVMValueRef sample_id)
2928 {
2929 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2930 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
2931 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
2932 LLVMValueRef result[2];
2933
2934 result[0] = build_indexed_load_const(ctx, ctx->sample_positions, offset0);
2935 result[1] = build_indexed_load_const(ctx, ctx->sample_positions, offset1);
2936
2937 return ac_build_gather_values(&ctx->ac, result, 2);
2938 }
2939
2940 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
2941 {
2942 LLVMValueRef values[2];
2943
2944 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
2945 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
2946 return ac_build_gather_values(&ctx->ac, values, 2);
2947 }
2948
2949 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
2950 nir_intrinsic_instr *instr)
2951 {
2952 LLVMValueRef result[2];
2953 LLVMValueRef interp_param, attr_number;
2954 unsigned location;
2955 unsigned chan;
2956 LLVMValueRef src_c0, src_c1;
2957 const char *intr_name;
2958 LLVMValueRef src0;
2959 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
2960 switch (instr->intrinsic) {
2961 case nir_intrinsic_interp_var_at_centroid:
2962 location = INTERP_CENTROID;
2963 break;
2964 case nir_intrinsic_interp_var_at_sample:
2965 case nir_intrinsic_interp_var_at_offset:
2966 location = INTERP_SAMPLE;
2967 src0 = get_src(ctx, instr->src[0]);
2968 break;
2969 default:
2970 break;
2971 }
2972
2973 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
2974 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
2975 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
2976 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
2977 LLVMValueRef sample_position;
2978 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
2979
2980 /* fetch sample ID */
2981 sample_position = load_sample_position(ctx, src0);
2982
2983 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
2984 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
2985 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
2986 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
2987 }
2988 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
2989 attr_number = LLVMConstInt(ctx->i32, input_index, false);
2990
2991 if (location == INTERP_SAMPLE) {
2992 LLVMValueRef ij_out[2];
2993 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
2994
2995 /*
2996 * take the I then J parameters, and the DDX/Y for it, and
2997 * calculate the IJ inputs for the interpolator.
2998 * temp1 = ddx * offset/sample.x + I;
2999 * interp_param.I = ddy * offset/sample.y + temp1;
3000 * temp1 = ddx * offset/sample.x + J;
3001 * interp_param.J = ddy * offset/sample.y + temp1;
3002 */
3003 for (unsigned i = 0; i < 2; i++) {
3004 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3005 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3006 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3007 ddxy_out, ix_ll, "");
3008 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3009 ddxy_out, iy_ll, "");
3010 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3011 interp_param, ix_ll, "");
3012 LLVMValueRef temp1, temp2;
3013
3014 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3015 ctx->f32, "");
3016
3017 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3018 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3019
3020 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3021 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3022
3023 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3024 temp2, ctx->i32, "");
3025 }
3026 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3027
3028 }
3029 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3030 for (chan = 0; chan < 2; chan++) {
3031 LLVMValueRef args[4];
3032 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3033
3034 args[0] = llvm_chan;
3035 args[1] = attr_number;
3036 args[2] = ctx->prim_mask;
3037 args[3] = interp_param;
3038 result[chan] = ac_emit_llvm_intrinsic(&ctx->ac, intr_name,
3039 ctx->f32, args, args[3] ? 4 : 3,
3040 AC_FUNC_ATTR_READNONE);
3041 }
3042 return ac_build_gather_values(&ctx->ac, result, 2);
3043 }
3044
3045 static void
3046 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3047 nir_intrinsic_instr *instr)
3048 {
3049 LLVMValueRef gs_next_vertex;
3050 LLVMValueRef can_emit, kill;
3051 LLVMValueRef args[2];
3052 int idx;
3053
3054 assert(instr->const_index[0] == 0);
3055 /* Write vertex attribute values to GSVS ring */
3056 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3057 ctx->gs_next_vertex,
3058 "");
3059
3060 /* If this thread has already emitted the declared maximum number of
3061 * vertices, kill it: excessive vertex emissions are not supposed to
3062 * have any effect, and GS threads have no externally observable
3063 * effects other than emitting vertices.
3064 */
3065 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3066 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3067
3068 kill = LLVMBuildSelect(ctx->builder, can_emit,
3069 LLVMConstReal(ctx->f32, 1.0f),
3070 LLVMConstReal(ctx->f32, -1.0f), "");
3071 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
3072 ctx->voidt, &kill, 1, 0);
3073
3074 /* loop num outputs */
3075 idx = 0;
3076 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3077 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3078 if (!(ctx->output_mask & (1ull << i)))
3079 continue;
3080
3081 for (unsigned j = 0; j < 4; j++) {
3082 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3083 out_ptr[j], "");
3084 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (idx * 4 + j) * ctx->gs_max_out_vertices, false);
3085 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3086 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3087
3088 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3089
3090 build_tbuffer_store(ctx, ctx->gsvs_ring,
3091 out_val, 1,
3092 voffset, ctx->gs2vs_offset, 0,
3093 V_008F0C_BUF_DATA_FORMAT_32,
3094 V_008F0C_BUF_NUM_FORMAT_UINT,
3095 1, 0, 1, 1, 0);
3096 }
3097 idx++;
3098 }
3099
3100 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3101 ctx->i32one, "");
3102 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3103 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (0 << 8), false);
3104 args[1] = ctx->gs_wave_id;
3105 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg",
3106 ctx->voidt, args, 2, 0);
3107 }
3108
3109 static void
3110 visit_end_primitive(struct nir_to_llvm_context *ctx,
3111 nir_intrinsic_instr *instr)
3112 {
3113 LLVMValueRef args[2];
3114
3115 assert(instr->const_index[0] == 0);
3116 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_CUT | SENDMSG_GS | (0 << 8), false);
3117 args[1] = ctx->gs_wave_id;
3118
3119 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg", ctx->voidt,
3120 args, 2, 0);
3121 }
3122
3123 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3124 nir_intrinsic_instr *instr)
3125 {
3126 LLVMValueRef result = NULL;
3127
3128 switch (instr->intrinsic) {
3129 case nir_intrinsic_load_work_group_id: {
3130 result = ctx->workgroup_ids;
3131 break;
3132 }
3133 case nir_intrinsic_load_base_vertex: {
3134 result = ctx->base_vertex;
3135 break;
3136 }
3137 case nir_intrinsic_load_vertex_id_zero_base: {
3138 result = ctx->vertex_id;
3139 break;
3140 }
3141 case nir_intrinsic_load_local_invocation_id: {
3142 result = ctx->local_invocation_ids;
3143 break;
3144 }
3145 case nir_intrinsic_load_base_instance:
3146 result = ctx->start_instance;
3147 break;
3148 case nir_intrinsic_load_invocation_id:
3149 result = ctx->gs_invocation_id;
3150 break;
3151 case nir_intrinsic_load_primitive_id:
3152 if (ctx->stage == MESA_SHADER_GEOMETRY)
3153 result = ctx->gs_prim_id;
3154 else
3155 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3156 break;
3157 case nir_intrinsic_load_sample_id:
3158 ctx->shader_info->fs.force_persample = true;
3159 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3160 break;
3161 case nir_intrinsic_load_sample_pos:
3162 ctx->shader_info->fs.force_persample = true;
3163 result = load_sample_pos(ctx);
3164 break;
3165 case nir_intrinsic_load_front_face:
3166 result = ctx->front_face;
3167 break;
3168 case nir_intrinsic_load_instance_id:
3169 result = ctx->instance_id;
3170 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3171 ctx->shader_info->vs.vgpr_comp_cnt);
3172 break;
3173 case nir_intrinsic_load_num_work_groups:
3174 result = ctx->num_work_groups;
3175 break;
3176 case nir_intrinsic_load_local_invocation_index:
3177 result = visit_load_local_invocation_index(ctx);
3178 break;
3179 case nir_intrinsic_load_push_constant:
3180 result = visit_load_push_constant(ctx, instr);
3181 break;
3182 case nir_intrinsic_vulkan_resource_index:
3183 result = visit_vulkan_resource_index(ctx, instr);
3184 break;
3185 case nir_intrinsic_store_ssbo:
3186 visit_store_ssbo(ctx, instr);
3187 break;
3188 case nir_intrinsic_load_ssbo:
3189 result = visit_load_buffer(ctx, instr);
3190 break;
3191 case nir_intrinsic_ssbo_atomic_add:
3192 case nir_intrinsic_ssbo_atomic_imin:
3193 case nir_intrinsic_ssbo_atomic_umin:
3194 case nir_intrinsic_ssbo_atomic_imax:
3195 case nir_intrinsic_ssbo_atomic_umax:
3196 case nir_intrinsic_ssbo_atomic_and:
3197 case nir_intrinsic_ssbo_atomic_or:
3198 case nir_intrinsic_ssbo_atomic_xor:
3199 case nir_intrinsic_ssbo_atomic_exchange:
3200 case nir_intrinsic_ssbo_atomic_comp_swap:
3201 result = visit_atomic_ssbo(ctx, instr);
3202 break;
3203 case nir_intrinsic_load_ubo:
3204 result = visit_load_ubo_buffer(ctx, instr);
3205 break;
3206 case nir_intrinsic_get_buffer_size:
3207 result = visit_get_buffer_size(ctx, instr);
3208 break;
3209 case nir_intrinsic_load_var:
3210 result = visit_load_var(ctx, instr);
3211 break;
3212 case nir_intrinsic_store_var:
3213 visit_store_var(ctx, instr);
3214 break;
3215 case nir_intrinsic_image_load:
3216 result = visit_image_load(ctx, instr);
3217 break;
3218 case nir_intrinsic_image_store:
3219 visit_image_store(ctx, instr);
3220 break;
3221 case nir_intrinsic_image_atomic_add:
3222 case nir_intrinsic_image_atomic_min:
3223 case nir_intrinsic_image_atomic_max:
3224 case nir_intrinsic_image_atomic_and:
3225 case nir_intrinsic_image_atomic_or:
3226 case nir_intrinsic_image_atomic_xor:
3227 case nir_intrinsic_image_atomic_exchange:
3228 case nir_intrinsic_image_atomic_comp_swap:
3229 result = visit_image_atomic(ctx, instr);
3230 break;
3231 case nir_intrinsic_image_size:
3232 result = visit_image_size(ctx, instr);
3233 break;
3234 case nir_intrinsic_discard:
3235 ctx->shader_info->fs.can_discard = true;
3236 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3237 ctx->voidt,
3238 NULL, 0, 0);
3239 break;
3240 case nir_intrinsic_discard_if:
3241 emit_discard_if(ctx, instr);
3242 break;
3243 case nir_intrinsic_memory_barrier:
3244 emit_waitcnt(ctx);
3245 break;
3246 case nir_intrinsic_barrier:
3247 emit_barrier(ctx);
3248 break;
3249 case nir_intrinsic_var_atomic_add:
3250 case nir_intrinsic_var_atomic_imin:
3251 case nir_intrinsic_var_atomic_umin:
3252 case nir_intrinsic_var_atomic_imax:
3253 case nir_intrinsic_var_atomic_umax:
3254 case nir_intrinsic_var_atomic_and:
3255 case nir_intrinsic_var_atomic_or:
3256 case nir_intrinsic_var_atomic_xor:
3257 case nir_intrinsic_var_atomic_exchange:
3258 case nir_intrinsic_var_atomic_comp_swap:
3259 result = visit_var_atomic(ctx, instr);
3260 break;
3261 case nir_intrinsic_interp_var_at_centroid:
3262 case nir_intrinsic_interp_var_at_sample:
3263 case nir_intrinsic_interp_var_at_offset:
3264 result = visit_interp(ctx, instr);
3265 break;
3266 case nir_intrinsic_emit_vertex:
3267 visit_emit_vertex(ctx, instr);
3268 break;
3269 case nir_intrinsic_end_primitive:
3270 visit_end_primitive(ctx, instr);
3271 break;
3272 default:
3273 fprintf(stderr, "Unknown intrinsic: ");
3274 nir_print_instr(&instr->instr, stderr);
3275 fprintf(stderr, "\n");
3276 break;
3277 }
3278 if (result) {
3279 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3280 }
3281 }
3282
3283 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3284 nir_deref_var *deref,
3285 enum desc_type desc_type)
3286 {
3287 unsigned desc_set = deref->var->data.descriptor_set;
3288 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3289 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3290 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3291 unsigned offset = binding->offset;
3292 unsigned stride = binding->size;
3293 unsigned type_size;
3294 LLVMBuilderRef builder = ctx->builder;
3295 LLVMTypeRef type;
3296 LLVMValueRef index = NULL;
3297
3298 assert(deref->var->data.binding < layout->binding_count);
3299
3300 switch (desc_type) {
3301 case DESC_IMAGE:
3302 type = ctx->v8i32;
3303 type_size = 32;
3304 break;
3305 case DESC_FMASK:
3306 type = ctx->v8i32;
3307 offset += 32;
3308 type_size = 32;
3309 break;
3310 case DESC_SAMPLER:
3311 type = ctx->v4i32;
3312 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3313 offset += 64;
3314
3315 type_size = 16;
3316 break;
3317 case DESC_BUFFER:
3318 type = ctx->v4i32;
3319 type_size = 16;
3320 break;
3321 default:
3322 unreachable("invalid desc_type\n");
3323 }
3324
3325 if (deref->deref.child) {
3326 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3327
3328 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3329 offset += child->base_offset * stride;
3330 if (child->deref_array_type == nir_deref_array_type_indirect) {
3331 index = get_src(ctx, child->indirect);
3332 }
3333 }
3334
3335 assert(stride % type_size == 0);
3336
3337 if (!index)
3338 index = ctx->i32zero;
3339
3340 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3341
3342 list = build_gep0(ctx, list, LLVMConstInt(ctx->i32, offset, 0));
3343 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3344
3345 return build_indexed_load_const(ctx, list, index);
3346 }
3347
3348 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3349 struct ac_tex_info *tinfo,
3350 nir_tex_instr *instr,
3351 nir_texop op,
3352 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3353 LLVMValueRef *param, unsigned count,
3354 unsigned dmask)
3355 {
3356 int num_args;
3357 unsigned is_rect = 0;
3358 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3359
3360 if (op == nir_texop_lod)
3361 da = false;
3362 /* Pad to power of two vector */
3363 while (count < util_next_power_of_two(count))
3364 param[count++] = LLVMGetUndef(ctx->i32);
3365
3366 if (count > 1)
3367 tinfo->args[0] = ac_build_gather_values(&ctx->ac, param, count);
3368 else
3369 tinfo->args[0] = param[0];
3370
3371 tinfo->args[1] = res_ptr;
3372 num_args = 2;
3373
3374 if (op == nir_texop_txf ||
3375 op == nir_texop_txf_ms ||
3376 op == nir_texop_query_levels ||
3377 op == nir_texop_texture_samples ||
3378 op == nir_texop_txs)
3379 tinfo->dst_type = ctx->v4i32;
3380 else {
3381 tinfo->dst_type = ctx->v4f32;
3382 tinfo->args[num_args++] = samp_ptr;
3383 }
3384
3385 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3386 tinfo->args[0] = res_ptr;
3387 tinfo->args[1] = LLVMConstInt(ctx->i32, 0, false);
3388 tinfo->args[2] = param[0];
3389 tinfo->arg_count = 3;
3390 return;
3391 }
3392
3393 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, dmask, 0);
3394 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, is_rect, 0); /* unorm */
3395 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
3396 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
3397 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
3398 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
3399 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
3400 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
3401
3402 tinfo->arg_count = num_args;
3403 }
3404
3405 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3406 *
3407 * SI-CI:
3408 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3409 * filtering manually. The driver sets img7 to a mask clearing
3410 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3411 * s_and_b32 samp0, samp0, img7
3412 *
3413 * VI:
3414 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3415 */
3416 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3417 LLVMValueRef res, LLVMValueRef samp)
3418 {
3419 LLVMBuilderRef builder = ctx->builder;
3420 LLVMValueRef img7, samp0;
3421
3422 if (ctx->options->chip_class >= VI)
3423 return samp;
3424
3425 img7 = LLVMBuildExtractElement(builder, res,
3426 LLVMConstInt(ctx->i32, 7, 0), "");
3427 samp0 = LLVMBuildExtractElement(builder, samp,
3428 LLVMConstInt(ctx->i32, 0, 0), "");
3429 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3430 return LLVMBuildInsertElement(builder, samp, samp0,
3431 LLVMConstInt(ctx->i32, 0, 0), "");
3432 }
3433
3434 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3435 nir_tex_instr *instr,
3436 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3437 LLVMValueRef *fmask_ptr)
3438 {
3439 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3440 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3441 else
3442 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3443 if (samp_ptr) {
3444 if (instr->sampler)
3445 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3446 else
3447 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3448 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3449 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3450 }
3451 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3452 instr->op == nir_texop_samples_identical))
3453 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3454 }
3455
3456 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3457 {
3458 LLVMValueRef result = NULL;
3459 struct ac_tex_info tinfo = { 0 };
3460 unsigned dmask = 0xf;
3461 LLVMValueRef address[16];
3462 LLVMValueRef coords[5];
3463 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3464 LLVMValueRef bias = NULL, offsets = NULL;
3465 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3466 LLVMValueRef ddx = NULL, ddy = NULL;
3467 LLVMValueRef derivs[6];
3468 unsigned chan, count = 0;
3469 unsigned const_src = 0, num_deriv_comp = 0;
3470
3471 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3472
3473 for (unsigned i = 0; i < instr->num_srcs; i++) {
3474 switch (instr->src[i].src_type) {
3475 case nir_tex_src_coord:
3476 coord = get_src(ctx, instr->src[i].src);
3477 break;
3478 case nir_tex_src_projector:
3479 break;
3480 case nir_tex_src_comparator:
3481 comparator = get_src(ctx, instr->src[i].src);
3482 break;
3483 case nir_tex_src_offset:
3484 offsets = get_src(ctx, instr->src[i].src);
3485 const_src = i;
3486 break;
3487 case nir_tex_src_bias:
3488 bias = get_src(ctx, instr->src[i].src);
3489 break;
3490 case nir_tex_src_lod:
3491 lod = get_src(ctx, instr->src[i].src);
3492 break;
3493 case nir_tex_src_ms_index:
3494 sample_index = get_src(ctx, instr->src[i].src);
3495 break;
3496 case nir_tex_src_ms_mcs:
3497 break;
3498 case nir_tex_src_ddx:
3499 ddx = get_src(ctx, instr->src[i].src);
3500 num_deriv_comp = instr->src[i].src.ssa->num_components;
3501 break;
3502 case nir_tex_src_ddy:
3503 ddy = get_src(ctx, instr->src[i].src);
3504 break;
3505 case nir_tex_src_texture_offset:
3506 case nir_tex_src_sampler_offset:
3507 case nir_tex_src_plane:
3508 default:
3509 break;
3510 }
3511 }
3512
3513 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3514 result = get_buffer_size(ctx, res_ptr, false);
3515 goto write_result;
3516 }
3517
3518 if (instr->op == nir_texop_texture_samples) {
3519 LLVMValueRef res, samples, is_msaa;
3520 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3521 samples = LLVMBuildExtractElement(ctx->builder, res,
3522 LLVMConstInt(ctx->i32, 3, false), "");
3523 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3524 LLVMConstInt(ctx->i32, 28, false), "");
3525 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3526 LLVMConstInt(ctx->i32, 0xe, false), "");
3527 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3528 LLVMConstInt(ctx->i32, 0xe, false), "");
3529
3530 samples = LLVMBuildLShr(ctx->builder, samples,
3531 LLVMConstInt(ctx->i32, 16, false), "");
3532 samples = LLVMBuildAnd(ctx->builder, samples,
3533 LLVMConstInt(ctx->i32, 0xf, false), "");
3534 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3535 samples, "");
3536 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3537 ctx->i32one, "");
3538 result = samples;
3539 goto write_result;
3540 }
3541
3542 if (coord)
3543 for (chan = 0; chan < instr->coord_components; chan++)
3544 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3545
3546 if (offsets && instr->op != nir_texop_txf) {
3547 LLVMValueRef offset[3], pack;
3548 for (chan = 0; chan < 3; ++chan)
3549 offset[chan] = ctx->i32zero;
3550
3551 tinfo.has_offset = true;
3552 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3553 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3554 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3555 LLVMConstInt(ctx->i32, 0x3f, false), "");
3556 if (chan)
3557 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3558 LLVMConstInt(ctx->i32, chan * 8, false), "");
3559 }
3560 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3561 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3562 address[count++] = pack;
3563
3564 }
3565 /* pack LOD bias value */
3566 if (instr->op == nir_texop_txb && bias) {
3567 address[count++] = bias;
3568 }
3569
3570 /* Pack depth comparison value */
3571 if (instr->is_shadow && comparator) {
3572 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3573 }
3574
3575 /* pack derivatives */
3576 if (ddx || ddy) {
3577 switch (instr->sampler_dim) {
3578 case GLSL_SAMPLER_DIM_3D:
3579 case GLSL_SAMPLER_DIM_CUBE:
3580 num_deriv_comp = 3;
3581 break;
3582 case GLSL_SAMPLER_DIM_2D:
3583 default:
3584 num_deriv_comp = 2;
3585 break;
3586 case GLSL_SAMPLER_DIM_1D:
3587 num_deriv_comp = 1;
3588 break;
3589 }
3590
3591 for (unsigned i = 0; i < num_deriv_comp; i++) {
3592 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3593 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3594 }
3595 }
3596
3597 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3598 for (chan = 0; chan < instr->coord_components; chan++)
3599 coords[chan] = to_float(ctx, coords[chan]);
3600 if (instr->coord_components == 3)
3601 coords[3] = LLVMGetUndef(ctx->f32);
3602 ac_prepare_cube_coords(&ctx->ac,
3603 instr->op == nir_texop_txd, instr->is_array,
3604 coords, derivs);
3605 if (num_deriv_comp)
3606 num_deriv_comp--;
3607 }
3608
3609 if (ddx || ddy) {
3610 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3611 address[count++] = derivs[i];
3612 }
3613
3614 /* Pack texture coordinates */
3615 if (coord) {
3616 address[count++] = coords[0];
3617 if (instr->coord_components > 1)
3618 address[count++] = coords[1];
3619 if (instr->coord_components > 2) {
3620 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3621 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3622 coords[2] = to_float(ctx, coords[2]);
3623 coords[2] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coords[2],
3624 1, 0);
3625 coords[2] = to_integer(ctx, coords[2]);
3626 }
3627 address[count++] = coords[2];
3628 }
3629 }
3630
3631 /* Pack LOD */
3632 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3633 address[count++] = lod;
3634 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3635 address[count++] = sample_index;
3636 } else if(instr->op == nir_texop_txs) {
3637 count = 0;
3638 if (lod)
3639 address[count++] = lod;
3640 else
3641 address[count++] = ctx->i32zero;
3642 }
3643
3644 for (chan = 0; chan < count; chan++) {
3645 address[chan] = LLVMBuildBitCast(ctx->builder,
3646 address[chan], ctx->i32, "");
3647 }
3648
3649 if (instr->op == nir_texop_samples_identical) {
3650 LLVMValueRef txf_address[4];
3651 struct ac_tex_info txf_info = { 0 };
3652 unsigned txf_count = count;
3653 memcpy(txf_address, address, sizeof(txf_address));
3654
3655 if (!instr->is_array)
3656 txf_address[2] = ctx->i32zero;
3657 txf_address[3] = ctx->i32zero;
3658
3659 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3660 fmask_ptr, NULL,
3661 txf_address, txf_count, 0xf);
3662
3663 result = build_tex_intrinsic(ctx, instr, &txf_info);
3664
3665 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3666 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3667 goto write_result;
3668 }
3669
3670 /* Adjust the sample index according to FMASK.
3671 *
3672 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3673 * which is the identity mapping. Each nibble says which physical sample
3674 * should be fetched to get that sample.
3675 *
3676 * For example, 0x11111100 means there are only 2 samples stored and
3677 * the second sample covers 3/4 of the pixel. When reading samples 0
3678 * and 1, return physical sample 0 (determined by the first two 0s
3679 * in FMASK), otherwise return physical sample 1.
3680 *
3681 * The sample index should be adjusted as follows:
3682 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3683 */
3684 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS) {
3685 LLVMValueRef txf_address[4];
3686 struct ac_tex_info txf_info = { 0 };
3687 unsigned txf_count = count;
3688 memcpy(txf_address, address, sizeof(txf_address));
3689
3690 if (!instr->is_array)
3691 txf_address[2] = ctx->i32zero;
3692 txf_address[3] = ctx->i32zero;
3693
3694 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3695 fmask_ptr, NULL,
3696 txf_address, txf_count, 0xf);
3697
3698 result = build_tex_intrinsic(ctx, instr, &txf_info);
3699 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3700 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3701
3702 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3703 result,
3704 ctx->i32zero, "");
3705
3706 unsigned sample_chan = instr->is_array ? 3 : 2;
3707
3708 LLVMValueRef sample_index4 =
3709 LLVMBuildMul(ctx->builder, address[sample_chan], four, "");
3710 LLVMValueRef shifted_fmask =
3711 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3712 LLVMValueRef final_sample =
3713 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3714
3715 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3716 * resource descriptor is 0 (invalid),
3717 */
3718 LLVMValueRef fmask_desc =
3719 LLVMBuildBitCast(ctx->builder, fmask_ptr,
3720 ctx->v8i32, "");
3721
3722 LLVMValueRef fmask_word1 =
3723 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3724 ctx->i32one, "");
3725
3726 LLVMValueRef word1_is_nonzero =
3727 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3728 fmask_word1, ctx->i32zero, "");
3729
3730 /* Replace the MSAA sample index. */
3731 address[sample_chan] =
3732 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3733 final_sample, address[sample_chan], "");
3734 }
3735
3736 if (offsets && instr->op == nir_texop_txf) {
3737 nir_const_value *const_offset =
3738 nir_src_as_const_value(instr->src[const_src].src);
3739 int num_offsets = instr->src[const_src].src.ssa->num_components;
3740 assert(const_offset);
3741 num_offsets = MIN2(num_offsets, instr->coord_components);
3742 if (num_offsets > 2)
3743 address[2] = LLVMBuildAdd(ctx->builder,
3744 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3745 if (num_offsets > 1)
3746 address[1] = LLVMBuildAdd(ctx->builder,
3747 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3748 address[0] = LLVMBuildAdd(ctx->builder,
3749 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3750
3751 }
3752
3753 /* TODO TG4 support */
3754 if (instr->op == nir_texop_tg4) {
3755 if (instr->is_shadow)
3756 dmask = 1;
3757 else
3758 dmask = 1 << instr->component;
3759 }
3760 set_tex_fetch_args(ctx, &tinfo, instr, instr->op,
3761 res_ptr, samp_ptr, address, count, dmask);
3762
3763 result = build_tex_intrinsic(ctx, instr, &tinfo);
3764
3765 if (instr->op == nir_texop_query_levels)
3766 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3767 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3768 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3769 else if (instr->op == nir_texop_txs &&
3770 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3771 instr->is_array) {
3772 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3773 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3774 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3775 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3776 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3777 } else if (instr->dest.ssa.num_components != 4)
3778 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3779
3780 write_result:
3781 if (result) {
3782 assert(instr->dest.is_ssa);
3783 result = to_integer(ctx, result);
3784 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3785 }
3786 }
3787
3788
3789 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3790 {
3791 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3792 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3793
3794 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3795 _mesa_hash_table_insert(ctx->phis, instr, result);
3796 }
3797
3798 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3799 nir_phi_instr *instr,
3800 LLVMValueRef llvm_phi)
3801 {
3802 nir_foreach_phi_src(src, instr) {
3803 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3804 LLVMValueRef llvm_src = get_src(ctx, src->src);
3805
3806 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3807 }
3808 }
3809
3810 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3811 {
3812 struct hash_entry *entry;
3813 hash_table_foreach(ctx->phis, entry) {
3814 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3815 (LLVMValueRef)entry->data);
3816 }
3817 }
3818
3819
3820 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3821 nir_ssa_undef_instr *instr)
3822 {
3823 unsigned num_components = instr->def.num_components;
3824 LLVMValueRef undef;
3825
3826 if (num_components == 1)
3827 undef = LLVMGetUndef(ctx->i32);
3828 else {
3829 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3830 }
3831 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3832 }
3833
3834 static void visit_jump(struct nir_to_llvm_context *ctx,
3835 nir_jump_instr *instr)
3836 {
3837 switch (instr->type) {
3838 case nir_jump_break:
3839 LLVMBuildBr(ctx->builder, ctx->break_block);
3840 LLVMClearInsertionPosition(ctx->builder);
3841 break;
3842 case nir_jump_continue:
3843 LLVMBuildBr(ctx->builder, ctx->continue_block);
3844 LLVMClearInsertionPosition(ctx->builder);
3845 break;
3846 default:
3847 fprintf(stderr, "Unknown NIR jump instr: ");
3848 nir_print_instr(&instr->instr, stderr);
3849 fprintf(stderr, "\n");
3850 abort();
3851 }
3852 }
3853
3854 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3855 struct exec_list *list);
3856
3857 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3858 {
3859 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3860 nir_foreach_instr(instr, block)
3861 {
3862 switch (instr->type) {
3863 case nir_instr_type_alu:
3864 visit_alu(ctx, nir_instr_as_alu(instr));
3865 break;
3866 case nir_instr_type_load_const:
3867 visit_load_const(ctx, nir_instr_as_load_const(instr));
3868 break;
3869 case nir_instr_type_intrinsic:
3870 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3871 break;
3872 case nir_instr_type_tex:
3873 visit_tex(ctx, nir_instr_as_tex(instr));
3874 break;
3875 case nir_instr_type_phi:
3876 visit_phi(ctx, nir_instr_as_phi(instr));
3877 break;
3878 case nir_instr_type_ssa_undef:
3879 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3880 break;
3881 case nir_instr_type_jump:
3882 visit_jump(ctx, nir_instr_as_jump(instr));
3883 break;
3884 default:
3885 fprintf(stderr, "Unknown NIR instr type: ");
3886 nir_print_instr(instr, stderr);
3887 fprintf(stderr, "\n");
3888 abort();
3889 }
3890 }
3891
3892 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3893 }
3894
3895 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3896 {
3897 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3898
3899 LLVMBasicBlockRef merge_block =
3900 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3901 LLVMBasicBlockRef if_block =
3902 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3903 LLVMBasicBlockRef else_block = merge_block;
3904 if (!exec_list_is_empty(&if_stmt->else_list))
3905 else_block = LLVMAppendBasicBlockInContext(
3906 ctx->context, ctx->main_function, "");
3907
3908 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3909 LLVMConstInt(ctx->i32, 0, false), "");
3910 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3911
3912 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3913 visit_cf_list(ctx, &if_stmt->then_list);
3914 if (LLVMGetInsertBlock(ctx->builder))
3915 LLVMBuildBr(ctx->builder, merge_block);
3916
3917 if (!exec_list_is_empty(&if_stmt->else_list)) {
3918 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3919 visit_cf_list(ctx, &if_stmt->else_list);
3920 if (LLVMGetInsertBlock(ctx->builder))
3921 LLVMBuildBr(ctx->builder, merge_block);
3922 }
3923
3924 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3925 }
3926
3927 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3928 {
3929 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3930 LLVMBasicBlockRef break_parent = ctx->break_block;
3931
3932 ctx->continue_block =
3933 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3934 ctx->break_block =
3935 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3936
3937 LLVMBuildBr(ctx->builder, ctx->continue_block);
3938 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
3939 visit_cf_list(ctx, &loop->body);
3940
3941 if (LLVMGetInsertBlock(ctx->builder))
3942 LLVMBuildBr(ctx->builder, ctx->continue_block);
3943 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
3944
3945 ctx->continue_block = continue_parent;
3946 ctx->break_block = break_parent;
3947 }
3948
3949 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3950 struct exec_list *list)
3951 {
3952 foreach_list_typed(nir_cf_node, node, node, list)
3953 {
3954 switch (node->type) {
3955 case nir_cf_node_block:
3956 visit_block(ctx, nir_cf_node_as_block(node));
3957 break;
3958
3959 case nir_cf_node_if:
3960 visit_if(ctx, nir_cf_node_as_if(node));
3961 break;
3962
3963 case nir_cf_node_loop:
3964 visit_loop(ctx, nir_cf_node_as_loop(node));
3965 break;
3966
3967 default:
3968 assert(0);
3969 }
3970 }
3971 }
3972
3973 static void
3974 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
3975 struct nir_variable *variable)
3976 {
3977 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
3978 LLVMValueRef t_offset;
3979 LLVMValueRef t_list;
3980 LLVMValueRef args[3];
3981 LLVMValueRef input;
3982 LLVMValueRef buffer_index;
3983 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
3984 int idx = variable->data.location;
3985 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
3986
3987 variable->data.driver_location = idx * 4;
3988
3989 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
3990 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
3991 ctx->start_instance, "");
3992 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3993 ctx->shader_info->vs.vgpr_comp_cnt);
3994 } else
3995 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
3996 ctx->base_vertex, "");
3997
3998 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
3999 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4000
4001 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
4002 args[0] = t_list;
4003 args[1] = LLVMConstInt(ctx->i32, 0, false);
4004 args[2] = buffer_index;
4005 input = ac_emit_llvm_intrinsic(&ctx->ac,
4006 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
4007 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
4008
4009 for (unsigned chan = 0; chan < 4; chan++) {
4010 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4011 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4012 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4013 input, llvm_chan, ""));
4014 }
4015 }
4016 }
4017
4018
4019 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4020 unsigned attr,
4021 LLVMValueRef interp_param,
4022 LLVMValueRef prim_mask,
4023 LLVMValueRef result[4])
4024 {
4025 const char *intr_name;
4026 LLVMValueRef attr_number;
4027 unsigned chan;
4028
4029 attr_number = LLVMConstInt(ctx->i32, attr, false);
4030
4031 /* fs.constant returns the param from the middle vertex, so it's not
4032 * really useful for flat shading. It's meant to be used for custom
4033 * interpolation (but the intrinsic can't fetch from the other two
4034 * vertices).
4035 *
4036 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4037 * to do the right thing. The only reason we use fs.constant is that
4038 * fs.interp cannot be used on integers, because they can be equal
4039 * to NaN.
4040 */
4041 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
4042
4043 for (chan = 0; chan < 4; chan++) {
4044 LLVMValueRef args[4];
4045 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4046
4047 args[0] = llvm_chan;
4048 args[1] = attr_number;
4049 args[2] = prim_mask;
4050 args[3] = interp_param;
4051 result[chan] = ac_emit_llvm_intrinsic(&ctx->ac, intr_name,
4052 ctx->f32, args, args[3] ? 4 : 3,
4053 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
4054 }
4055 }
4056
4057 static void
4058 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4059 struct nir_variable *variable)
4060 {
4061 int idx = variable->data.location;
4062 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4063 LLVMValueRef interp;
4064
4065 variable->data.driver_location = idx * 4;
4066 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4067
4068 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4069 unsigned interp_type;
4070 if (variable->data.sample) {
4071 interp_type = INTERP_SAMPLE;
4072 ctx->shader_info->fs.force_persample = true;
4073 } else if (variable->data.centroid)
4074 interp_type = INTERP_CENTROID;
4075 else
4076 interp_type = INTERP_CENTER;
4077
4078 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4079 } else
4080 interp = NULL;
4081
4082 for (unsigned i = 0; i < attrib_count; ++i)
4083 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4084
4085 }
4086
4087 static void
4088 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4089 struct nir_variable *variable)
4090 {
4091 switch (ctx->stage) {
4092 case MESA_SHADER_VERTEX:
4093 handle_vs_input_decl(ctx, variable);
4094 break;
4095 case MESA_SHADER_FRAGMENT:
4096 handle_fs_input_decl(ctx, variable);
4097 break;
4098 default:
4099 break;
4100 }
4101
4102 }
4103
4104 static void
4105 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4106 struct nir_shader *nir)
4107 {
4108 unsigned index = 0;
4109 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4110 LLVMValueRef interp_param;
4111 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4112
4113 if (!(ctx->input_mask & (1ull << i)))
4114 continue;
4115
4116 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC) {
4117 interp_param = *inputs;
4118 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4119 inputs);
4120
4121 if (!interp_param)
4122 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4123 ++index;
4124 } else if (i == VARYING_SLOT_POS) {
4125 for(int i = 0; i < 3; ++i)
4126 inputs[i] = ctx->frag_pos[i];
4127
4128 inputs[3] = ac_emit_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4129 }
4130 }
4131 ctx->shader_info->fs.num_interp = index;
4132 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4133 ctx->shader_info->fs.has_pcoord = true;
4134 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4135 }
4136
4137 static LLVMValueRef
4138 ac_build_alloca(struct nir_to_llvm_context *ctx,
4139 LLVMTypeRef type,
4140 const char *name)
4141 {
4142 LLVMBuilderRef builder = ctx->builder;
4143 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4144 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4145 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4146 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4147 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4148 LLVMValueRef res;
4149
4150 if (first_instr) {
4151 LLVMPositionBuilderBefore(first_builder, first_instr);
4152 } else {
4153 LLVMPositionBuilderAtEnd(first_builder, first_block);
4154 }
4155
4156 res = LLVMBuildAlloca(first_builder, type, name);
4157 LLVMBuildStore(builder, LLVMConstNull(type), res);
4158
4159 LLVMDisposeBuilder(first_builder);
4160
4161 return res;
4162 }
4163
4164 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4165 LLVMTypeRef type,
4166 const char *name)
4167 {
4168 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4169 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4170 return ptr;
4171 }
4172
4173 static void
4174 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4175 struct nir_variable *variable)
4176 {
4177 int idx = variable->data.location + variable->data.index;
4178 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4179
4180 variable->data.driver_location = idx * 4;
4181
4182 if (ctx->stage == MESA_SHADER_VERTEX) {
4183
4184 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4185 idx == VARYING_SLOT_CULL_DIST0) {
4186 int length = glsl_get_length(variable->type);
4187 if (idx == VARYING_SLOT_CLIP_DIST0) {
4188 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
4189 ctx->num_clips = length;
4190 } else if (idx == VARYING_SLOT_CULL_DIST0) {
4191 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
4192 ctx->num_culls = length;
4193 }
4194 if (length > 4)
4195 attrib_count = 2;
4196 else
4197 attrib_count = 1;
4198 }
4199 }
4200
4201 for (unsigned i = 0; i < attrib_count; ++i) {
4202 for (unsigned chan = 0; chan < 4; chan++) {
4203 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4204 si_build_alloca_undef(ctx, ctx->f32, "");
4205 }
4206 }
4207 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
4208 }
4209
4210 static void
4211 setup_locals(struct nir_to_llvm_context *ctx,
4212 struct nir_function *func)
4213 {
4214 int i, j;
4215 ctx->num_locals = 0;
4216 nir_foreach_variable(variable, &func->impl->locals) {
4217 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4218 variable->data.driver_location = ctx->num_locals * 4;
4219 ctx->num_locals += attrib_count;
4220 }
4221 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4222 if (!ctx->locals)
4223 return;
4224
4225 for (i = 0; i < ctx->num_locals; i++) {
4226 for (j = 0; j < 4; j++) {
4227 ctx->locals[i * 4 + j] =
4228 si_build_alloca_undef(ctx, ctx->f32, "temp");
4229 }
4230 }
4231 }
4232
4233 static LLVMValueRef
4234 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4235 {
4236 v = to_float(ctx, v);
4237 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", v, LLVMConstReal(ctx->f32, lo));
4238 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", v, LLVMConstReal(ctx->f32, hi));
4239 }
4240
4241
4242 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4243 LLVMValueRef src0, LLVMValueRef src1)
4244 {
4245 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4246 LLVMValueRef comp[2];
4247
4248 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4249 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4250 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4251 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4252 }
4253
4254 /* Initialize arguments for the shader export intrinsic */
4255 static void
4256 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4257 LLVMValueRef *values,
4258 unsigned target,
4259 LLVMValueRef *args)
4260 {
4261 /* Default is 0xf. Adjusted below depending on the format. */
4262 args[0] = LLVMConstInt(ctx->i32, target != V_008DFC_SQ_EXP_NULL ? 0xf : 0, false);
4263 /* Specify whether the EXEC mask represents the valid mask */
4264 args[1] = LLVMConstInt(ctx->i32, 0, false);
4265
4266 /* Specify whether this is the last export */
4267 args[2] = LLVMConstInt(ctx->i32, 0, false);
4268 /* Specify the target we are exporting */
4269 args[3] = LLVMConstInt(ctx->i32, target, false);
4270
4271 args[4] = LLVMConstInt(ctx->i32, 0, false); /* COMPR flag */
4272 args[5] = LLVMGetUndef(ctx->f32);
4273 args[6] = LLVMGetUndef(ctx->f32);
4274 args[7] = LLVMGetUndef(ctx->f32);
4275 args[8] = LLVMGetUndef(ctx->f32);
4276
4277 if (!values)
4278 return;
4279
4280 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4281 LLVMValueRef val[4];
4282 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4283 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4284 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4285
4286 switch(col_format) {
4287 case V_028714_SPI_SHADER_ZERO:
4288 args[0] = LLVMConstInt(ctx->i32, 0x0, 0);
4289 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_NULL, 0);
4290 break;
4291
4292 case V_028714_SPI_SHADER_32_R:
4293 args[0] = LLVMConstInt(ctx->i32, 0x1, 0);
4294 args[5] = values[0];
4295 break;
4296
4297 case V_028714_SPI_SHADER_32_GR:
4298 args[0] = LLVMConstInt(ctx->i32, 0x3, 0);
4299 args[5] = values[0];
4300 args[6] = values[1];
4301 break;
4302
4303 case V_028714_SPI_SHADER_32_AR:
4304 args[0] = LLVMConstInt(ctx->i32, 0x9, 0);
4305 args[5] = values[0];
4306 args[8] = values[3];
4307 break;
4308
4309 case V_028714_SPI_SHADER_FP16_ABGR:
4310 args[4] = ctx->i32one;
4311
4312 for (unsigned chan = 0; chan < 2; chan++) {
4313 LLVMValueRef pack_args[2] = {
4314 values[2 * chan],
4315 values[2 * chan + 1]
4316 };
4317 LLVMValueRef packed;
4318
4319 packed = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.packf16",
4320 ctx->i32, pack_args, 2,
4321 AC_FUNC_ATTR_READNONE);
4322 args[chan + 5] = packed;
4323 }
4324 break;
4325
4326 case V_028714_SPI_SHADER_UNORM16_ABGR:
4327 for (unsigned chan = 0; chan < 4; chan++) {
4328 val[chan] = emit_float_saturate(ctx, values[chan], 0, 1);
4329 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4330 LLVMConstReal(ctx->f32, 65535), "");
4331 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4332 LLVMConstReal(ctx->f32, 0.5), "");
4333 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4334 ctx->i32, "");
4335 }
4336
4337 args[4] = ctx->i32one;
4338 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4339 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4340 break;
4341
4342 case V_028714_SPI_SHADER_SNORM16_ABGR:
4343 for (unsigned chan = 0; chan < 4; chan++) {
4344 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4345 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4346 LLVMConstReal(ctx->f32, 32767), "");
4347
4348 /* If positive, add 0.5, else add -0.5. */
4349 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4350 LLVMBuildSelect(ctx->builder,
4351 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4352 val[chan], ctx->f32zero, ""),
4353 LLVMConstReal(ctx->f32, 0.5),
4354 LLVMConstReal(ctx->f32, -0.5), ""), "");
4355 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4356 }
4357
4358 args[4] = ctx->i32one;
4359 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4360 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4361 break;
4362
4363 case V_028714_SPI_SHADER_UINT16_ABGR: {
4364 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4365
4366 for (unsigned chan = 0; chan < 4; chan++) {
4367 val[chan] = to_integer(ctx, values[chan]);
4368 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4369 }
4370
4371 args[4] = ctx->i32one;
4372 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4373 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4374 break;
4375 }
4376
4377 case V_028714_SPI_SHADER_SINT16_ABGR: {
4378 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4379 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4380
4381 /* Clamp. */
4382 for (unsigned chan = 0; chan < 4; chan++) {
4383 val[chan] = to_integer(ctx, values[chan]);
4384 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4385 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4386 }
4387
4388 args[4] = ctx->i32one;
4389 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4390 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4391 break;
4392 }
4393
4394 default:
4395 case V_028714_SPI_SHADER_32_ABGR:
4396 memcpy(&args[5], values, sizeof(values[0]) * 4);
4397 break;
4398 }
4399 } else
4400 memcpy(&args[5], values, sizeof(values[0]) * 4);
4401
4402 for (unsigned i = 5; i < 9; ++i)
4403 args[i] = to_float(ctx, args[i]);
4404 }
4405
4406 static void
4407 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4408 {
4409 uint32_t param_count = 0;
4410 unsigned target;
4411 unsigned pos_idx, num_pos_exports = 0;
4412 LLVMValueRef args[9];
4413 LLVMValueRef pos_args[4][9] = { { 0 } };
4414 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4415 int i;
4416 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4417 (1ull << VARYING_SLOT_CLIP_DIST1) |
4418 (1ull << VARYING_SLOT_CULL_DIST0) |
4419 (1ull << VARYING_SLOT_CULL_DIST1));
4420
4421 if (clip_mask) {
4422 LLVMValueRef slots[8];
4423 unsigned j;
4424
4425 if (ctx->shader_info->vs.cull_dist_mask)
4426 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_clips;
4427
4428 i = VARYING_SLOT_CLIP_DIST0;
4429 for (j = 0; j < ctx->num_clips; j++)
4430 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4431 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4432 i = VARYING_SLOT_CULL_DIST0;
4433 for (j = 0; j < ctx->num_culls; j++)
4434 slots[ctx->num_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4435 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4436
4437 for (i = ctx->num_clips + ctx->num_culls; i < 8; i++)
4438 slots[i] = LLVMGetUndef(ctx->f32);
4439
4440 if (ctx->num_clips + ctx->num_culls > 4) {
4441 target = V_008DFC_SQ_EXP_POS + 3;
4442 si_llvm_init_export_args(ctx, &slots[4], target, args);
4443 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4444 args, sizeof(args));
4445 }
4446
4447 target = V_008DFC_SQ_EXP_POS + 2;
4448 si_llvm_init_export_args(ctx, &slots[0], target, args);
4449 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4450 args, sizeof(args));
4451
4452 }
4453
4454 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4455 LLVMValueRef values[4];
4456 if (!(ctx->output_mask & (1ull << i)))
4457 continue;
4458
4459 for (unsigned j = 0; j < 4; j++)
4460 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4461 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4462
4463 if (i == VARYING_SLOT_POS) {
4464 target = V_008DFC_SQ_EXP_POS;
4465 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4466 i == VARYING_SLOT_CLIP_DIST1 ||
4467 i == VARYING_SLOT_CULL_DIST0 ||
4468 i == VARYING_SLOT_CULL_DIST1) {
4469 continue;
4470 } else if (i == VARYING_SLOT_PSIZ) {
4471 ctx->shader_info->vs.writes_pointsize = true;
4472 psize_value = values[0];
4473 continue;
4474 } else if (i == VARYING_SLOT_LAYER) {
4475 ctx->shader_info->vs.writes_layer = true;
4476 layer_value = values[0];
4477 continue;
4478 } else if (i == VARYING_SLOT_VIEWPORT) {
4479 ctx->shader_info->vs.writes_viewport_index = true;
4480 viewport_index_value = values[0];
4481 continue;
4482 } else if (i >= VARYING_SLOT_VAR0) {
4483 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4484 target = V_008DFC_SQ_EXP_PARAM + param_count;
4485 param_count++;
4486 }
4487
4488 si_llvm_init_export_args(ctx, values, target, args);
4489
4490 if (target >= V_008DFC_SQ_EXP_POS &&
4491 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4492 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4493 args, sizeof(args));
4494 } else {
4495 ac_emit_llvm_intrinsic(&ctx->ac,
4496 "llvm.SI.export",
4497 ctx->voidt,
4498 args, 9, 0);
4499 }
4500 }
4501
4502 /* We need to add the position output manually if it's missing. */
4503 if (!pos_args[0][0]) {
4504 pos_args[0][0] = LLVMConstInt(ctx->i32, 0xf, false);
4505 pos_args[0][1] = ctx->i32zero; /* EXEC mask */
4506 pos_args[0][2] = ctx->i32zero; /* last export? */
4507 pos_args[0][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS, false);
4508 pos_args[0][4] = ctx->i32zero; /* COMPR flag */
4509 pos_args[0][5] = ctx->f32zero; /* X */
4510 pos_args[0][6] = ctx->f32zero; /* Y */
4511 pos_args[0][7] = ctx->f32zero; /* Z */
4512 pos_args[0][8] = ctx->f32one; /* W */
4513 }
4514
4515 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4516 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4517 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4518 if (mask) {
4519 pos_args[1][0] = LLVMConstInt(ctx->i32, mask, false); /* writemask */
4520 pos_args[1][1] = ctx->i32zero; /* EXEC mask */
4521 pos_args[1][2] = ctx->i32zero; /* last export? */
4522 pos_args[1][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + 1, false);
4523 pos_args[1][4] = ctx->i32zero; /* COMPR flag */
4524 pos_args[1][5] = ctx->f32zero; /* X */
4525 pos_args[1][6] = ctx->f32zero; /* Y */
4526 pos_args[1][7] = ctx->f32zero; /* Z */
4527 pos_args[1][8] = ctx->f32zero; /* W */
4528
4529 if (ctx->shader_info->vs.writes_pointsize == true)
4530 pos_args[1][5] = psize_value;
4531 if (ctx->shader_info->vs.writes_layer == true)
4532 pos_args[1][7] = layer_value;
4533 if (ctx->shader_info->vs.writes_viewport_index == true)
4534 pos_args[1][8] = viewport_index_value;
4535 }
4536 for (i = 0; i < 4; i++) {
4537 if (pos_args[i][0])
4538 num_pos_exports++;
4539 }
4540
4541 pos_idx = 0;
4542 for (i = 0; i < 4; i++) {
4543 if (!pos_args[i][0])
4544 continue;
4545
4546 /* Specify the target we are exporting */
4547 pos_args[i][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + pos_idx++, false);
4548 if (pos_idx == num_pos_exports)
4549 pos_args[i][2] = ctx->i32one;
4550 ac_emit_llvm_intrinsic(&ctx->ac,
4551 "llvm.SI.export",
4552 ctx->voidt,
4553 pos_args[i], 9, 0);
4554 }
4555
4556 ctx->shader_info->vs.pos_exports = num_pos_exports;
4557 ctx->shader_info->vs.param_exports = param_count;
4558 }
4559
4560 static void
4561 handle_es_outputs_post(struct nir_to_llvm_context *ctx)
4562 {
4563 int j;
4564 uint64_t max_output_written = 0;
4565 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4566 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
4567 int param_index;
4568 if (!(ctx->output_mask & (1ull << i)))
4569 continue;
4570
4571 param_index = shader_io_get_unique_index(i);
4572
4573 if (param_index > max_output_written)
4574 max_output_written = param_index;
4575
4576 for (j = 0; j < 4; j++) {
4577 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
4578 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4579
4580 build_tbuffer_store(ctx,
4581 ctx->esgs_ring,
4582 out_val, 1,
4583 LLVMGetUndef(ctx->i32), ctx->es2gs_offset,
4584 (4 * param_index + j) * 4,
4585 V_008F0C_BUF_DATA_FORMAT_32,
4586 V_008F0C_BUF_NUM_FORMAT_UINT,
4587 0, 0, 1, 1, 0);
4588 }
4589 }
4590 ctx->shader_info->vs.esgs_itemsize = (max_output_written + 1) * 16;
4591 }
4592
4593 static void
4594 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4595 LLVMValueRef *color, unsigned param, bool is_last)
4596 {
4597 LLVMValueRef args[9];
4598 /* Export */
4599 si_llvm_init_export_args(ctx, color, param,
4600 args);
4601
4602 if (is_last) {
4603 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4604 args[2] = ctx->i32one; /* DONE bit */
4605 } else if (args[0] == ctx->i32zero)
4606 return; /* unnecessary NULL export */
4607
4608 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4609 ctx->voidt, args, 9, 0);
4610 }
4611
4612 static void
4613 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4614 LLVMValueRef depth, LLVMValueRef stencil,
4615 LLVMValueRef samplemask)
4616 {
4617 LLVMValueRef args[9];
4618 unsigned mask = 0;
4619 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4620 args[2] = ctx->i32one; /* DONE bit */
4621 /* Specify the target we are exporting */
4622 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_MRTZ, false);
4623
4624 args[4] = ctx->i32zero; /* COMP flag */
4625 args[5] = LLVMGetUndef(ctx->f32); /* R, depth */
4626 args[6] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4627 args[7] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4628 args[8] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4629
4630 if (depth) {
4631 args[5] = depth;
4632 mask |= 0x1;
4633 }
4634
4635 if (stencil) {
4636 args[6] = stencil;
4637 mask |= 0x2;
4638 }
4639
4640 if (samplemask) {
4641 args[7] = samplemask;
4642 mask |= 0x04;
4643 }
4644
4645 /* SI (except OLAND) has a bug that it only looks
4646 * at the X writemask component. */
4647 if (ctx->options->chip_class == SI &&
4648 ctx->options->family != CHIP_OLAND)
4649 mask |= 0x01;
4650
4651 args[0] = LLVMConstInt(ctx->i32, mask, false);
4652 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4653 ctx->voidt, args, 9, 0);
4654 }
4655
4656 static void
4657 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4658 {
4659 unsigned index = 0;
4660 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4661
4662 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4663 LLVMValueRef values[4];
4664
4665 if (!(ctx->output_mask & (1ull << i)))
4666 continue;
4667
4668 if (i == FRAG_RESULT_DEPTH) {
4669 ctx->shader_info->fs.writes_z = true;
4670 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4671 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4672 } else if (i == FRAG_RESULT_STENCIL) {
4673 ctx->shader_info->fs.writes_stencil = true;
4674 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4675 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4676 } else {
4677 bool last = false;
4678 for (unsigned j = 0; j < 4; j++)
4679 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4680 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4681
4682 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil)
4683 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4684
4685 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4686 index++;
4687 }
4688 }
4689
4690 if (depth || stencil)
4691 si_export_mrt_z(ctx, depth, stencil, samplemask);
4692 else if (!index)
4693 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4694
4695 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4696 }
4697
4698 static void
4699 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4700 {
4701 LLVMValueRef args[2];
4702
4703 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE, false);
4704 args[1] = ctx->gs_wave_id;
4705 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg",
4706 ctx->voidt, args, 2, 0);
4707 }
4708
4709 static void
4710 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4711 {
4712 switch (ctx->stage) {
4713 case MESA_SHADER_VERTEX:
4714 if (ctx->options->key.vs.as_es)
4715 handle_es_outputs_post(ctx);
4716 else
4717 handle_vs_outputs_post(ctx);
4718 break;
4719 case MESA_SHADER_FRAGMENT:
4720 handle_fs_outputs_post(ctx);
4721 break;
4722 case MESA_SHADER_GEOMETRY:
4723 emit_gs_epilogue(ctx);
4724 break;
4725 default:
4726 break;
4727 }
4728 }
4729
4730 static void
4731 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4732 struct nir_variable *variable, uint32_t *offset, int idx)
4733 {
4734 unsigned size = glsl_count_attribute_slots(variable->type, false);
4735 variable->data.driver_location = *offset;
4736 *offset += size;
4737 }
4738
4739 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4740 {
4741 LLVMPassManagerRef passmgr;
4742 /* Create the pass manager */
4743 passmgr = LLVMCreateFunctionPassManagerForModule(
4744 ctx->module);
4745
4746 /* This pass should eliminate all the load and store instructions */
4747 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4748
4749 /* Add some optimization passes */
4750 LLVMAddScalarReplAggregatesPass(passmgr);
4751 LLVMAddLICMPass(passmgr);
4752 LLVMAddAggressiveDCEPass(passmgr);
4753 LLVMAddCFGSimplificationPass(passmgr);
4754 LLVMAddInstructionCombiningPass(passmgr);
4755
4756 /* Run the pass */
4757 LLVMInitializeFunctionPassManager(passmgr);
4758 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4759 LLVMFinalizeFunctionPassManager(passmgr);
4760
4761 LLVMDisposeBuilder(ctx->builder);
4762 LLVMDisposePassManager(passmgr);
4763 }
4764
4765 static void
4766 ac_setup_rings(struct nir_to_llvm_context *ctx)
4767 {
4768 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4769 ctx->esgs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, ctx->i32one);
4770 }
4771
4772 if (ctx->is_gs_copy_shader) {
4773 ctx->gsvs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4774 }
4775 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4776 LLVMValueRef tmp;
4777 ctx->esgs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4778 ctx->gsvs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4779
4780 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4781
4782 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4783 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4784 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4785 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4786
4787 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4788 }
4789 }
4790
4791 static
4792 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4793 struct nir_shader *nir,
4794 struct ac_shader_variant_info *shader_info,
4795 const struct ac_nir_compiler_options *options)
4796 {
4797 struct nir_to_llvm_context ctx = {0};
4798 struct nir_function *func;
4799 unsigned i;
4800 ctx.options = options;
4801 ctx.shader_info = shader_info;
4802 ctx.context = LLVMContextCreate();
4803 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4804
4805 ac_llvm_context_init(&ctx.ac, ctx.context);
4806 ctx.ac.module = ctx.module;
4807
4808 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4809
4810 memset(shader_info, 0, sizeof(*shader_info));
4811
4812 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4813 setup_types(&ctx);
4814
4815 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4816 ctx.ac.builder = ctx.builder;
4817 ctx.stage = nir->stage;
4818
4819 for (i = 0; i < AC_UD_MAX_SETS; i++)
4820 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4821 for (i = 0; i < AC_UD_MAX_UD; i++)
4822 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4823
4824 create_function(&ctx);
4825
4826 if (nir->stage == MESA_SHADER_COMPUTE) {
4827 int num_shared = 0;
4828 nir_foreach_variable(variable, &nir->shared)
4829 num_shared++;
4830 if (num_shared) {
4831 int idx = 0;
4832 uint32_t shared_size = 0;
4833 LLVMValueRef var;
4834 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4835 nir_foreach_variable(variable, &nir->shared) {
4836 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4837 idx++;
4838 }
4839
4840 shared_size *= 4;
4841 var = LLVMAddGlobalInAddressSpace(ctx.module,
4842 LLVMArrayType(ctx.i8, shared_size),
4843 "compute_lds",
4844 LOCAL_ADDR_SPACE);
4845 LLVMSetAlignment(var, 4);
4846 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4847 }
4848 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4849 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4850
4851 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4852 }
4853
4854 ac_setup_rings(&ctx);
4855
4856 nir_foreach_variable(variable, &nir->inputs)
4857 handle_shader_input_decl(&ctx, variable);
4858
4859 if (nir->stage == MESA_SHADER_FRAGMENT)
4860 handle_fs_inputs_pre(&ctx, nir);
4861
4862 nir_foreach_variable(variable, &nir->outputs)
4863 handle_shader_output_decl(&ctx, variable);
4864
4865 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4866 _mesa_key_pointer_equal);
4867 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4868 _mesa_key_pointer_equal);
4869
4870 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4871
4872 setup_locals(&ctx, func);
4873
4874 visit_cf_list(&ctx, &func->impl->body);
4875 phi_post_pass(&ctx);
4876
4877 handle_shader_outputs_post(&ctx);
4878 LLVMBuildRetVoid(ctx.builder);
4879
4880 ac_llvm_finalize_module(&ctx);
4881 free(ctx.locals);
4882 ralloc_free(ctx.defs);
4883 ralloc_free(ctx.phis);
4884
4885 if (nir->stage == MESA_SHADER_GEOMETRY) {
4886 shader_info->gs.gsvs_vertex_size = util_bitcount64(ctx.output_mask) * 16;
4887 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
4888 nir->info->gs.vertices_out;
4889 }
4890 return ctx.module;
4891 }
4892
4893 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4894 {
4895 unsigned *retval = (unsigned *)context;
4896 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4897 char *description = LLVMGetDiagInfoDescription(di);
4898
4899 if (severity == LLVMDSError) {
4900 *retval = 1;
4901 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4902 description);
4903 }
4904
4905 LLVMDisposeMessage(description);
4906 }
4907
4908 static unsigned ac_llvm_compile(LLVMModuleRef M,
4909 struct ac_shader_binary *binary,
4910 LLVMTargetMachineRef tm)
4911 {
4912 unsigned retval = 0;
4913 char *err;
4914 LLVMContextRef llvm_ctx;
4915 LLVMMemoryBufferRef out_buffer;
4916 unsigned buffer_size;
4917 const char *buffer_data;
4918 LLVMBool mem_err;
4919
4920 /* Setup Diagnostic Handler*/
4921 llvm_ctx = LLVMGetModuleContext(M);
4922
4923 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4924 &retval);
4925
4926 /* Compile IR*/
4927 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
4928 &err, &out_buffer);
4929
4930 /* Process Errors/Warnings */
4931 if (mem_err) {
4932 fprintf(stderr, "%s: %s", __FUNCTION__, err);
4933 free(err);
4934 retval = 1;
4935 goto out;
4936 }
4937
4938 /* Extract Shader Code*/
4939 buffer_size = LLVMGetBufferSize(out_buffer);
4940 buffer_data = LLVMGetBufferStart(out_buffer);
4941
4942 ac_elf_read(buffer_data, buffer_size, binary);
4943
4944 /* Clean up */
4945 LLVMDisposeMemoryBuffer(out_buffer);
4946
4947 out:
4948 return retval;
4949 }
4950
4951 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
4952 LLVMModuleRef llvm_module,
4953 struct ac_shader_binary *binary,
4954 struct ac_shader_config *config,
4955 struct ac_shader_variant_info *shader_info,
4956 gl_shader_stage stage,
4957 bool dump_shader, bool supports_spill)
4958 {
4959 if (dump_shader)
4960 ac_dump_module(llvm_module);
4961
4962 memset(binary, 0, sizeof(*binary));
4963 int v = ac_llvm_compile(llvm_module, binary, tm);
4964 if (v) {
4965 fprintf(stderr, "compile failed\n");
4966 }
4967
4968 if (dump_shader)
4969 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
4970
4971 ac_shader_binary_read_config(binary, config, 0, supports_spill);
4972
4973 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4974 LLVMDisposeModule(llvm_module);
4975 LLVMContextDispose(ctx);
4976
4977 if (stage == MESA_SHADER_FRAGMENT) {
4978 shader_info->num_input_vgprs = 0;
4979 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
4980 shader_info->num_input_vgprs += 2;
4981 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
4982 shader_info->num_input_vgprs += 2;
4983 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
4984 shader_info->num_input_vgprs += 2;
4985 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
4986 shader_info->num_input_vgprs += 3;
4987 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
4988 shader_info->num_input_vgprs += 2;
4989 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
4990 shader_info->num_input_vgprs += 2;
4991 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
4992 shader_info->num_input_vgprs += 2;
4993 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
4994 shader_info->num_input_vgprs += 1;
4995 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
4996 shader_info->num_input_vgprs += 1;
4997 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
4998 shader_info->num_input_vgprs += 1;
4999 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5000 shader_info->num_input_vgprs += 1;
5001 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5002 shader_info->num_input_vgprs += 1;
5003 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5004 shader_info->num_input_vgprs += 1;
5005 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5006 shader_info->num_input_vgprs += 1;
5007 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5008 shader_info->num_input_vgprs += 1;
5009 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5010 shader_info->num_input_vgprs += 1;
5011 }
5012 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5013
5014 /* +3 for scratch wave offset and VCC */
5015 config->num_sgprs = MAX2(config->num_sgprs,
5016 shader_info->num_input_sgprs + 3);
5017 }
5018
5019 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5020 struct ac_shader_binary *binary,
5021 struct ac_shader_config *config,
5022 struct ac_shader_variant_info *shader_info,
5023 struct nir_shader *nir,
5024 const struct ac_nir_compiler_options *options,
5025 bool dump_shader)
5026 {
5027
5028 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5029 options);
5030
5031 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5032 switch (nir->stage) {
5033 case MESA_SHADER_COMPUTE:
5034 for (int i = 0; i < 3; ++i)
5035 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5036 break;
5037 case MESA_SHADER_FRAGMENT:
5038 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5039 break;
5040 case MESA_SHADER_GEOMETRY:
5041 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5042 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5043 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5044 shader_info->gs.invocations = nir->info->gs.invocations;
5045 break;
5046 case MESA_SHADER_VERTEX:
5047 shader_info->vs.as_es = options->key.vs.as_es;
5048 break;
5049 default:
5050 break;
5051 }
5052 }
5053
5054 static void
5055 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5056 {
5057 LLVMValueRef args[9];
5058 args[0] = ctx->gsvs_ring;
5059 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5060 args[3] = ctx->i32zero;
5061 args[4] = ctx->i32one; /* OFFEN */
5062 args[5] = ctx->i32zero; /* IDXEN */
5063 args[6] = ctx->i32one; /* GLC */
5064 args[7] = ctx->i32one; /* SLC */
5065 args[8] = ctx->i32zero; /* TFE */
5066
5067 int idx = 0;
5068 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5069 if (!(ctx->output_mask & (1ull << i)))
5070 continue;
5071
5072 for (unsigned j = 0; j < 4; j++) {
5073 LLVMValueRef value;
5074 args[2] = LLVMConstInt(ctx->i32,
5075 (idx * 4 + j) *
5076 ctx->gs_max_out_vertices * 16 * 4, false);
5077
5078 value = ac_emit_llvm_intrinsic(&ctx->ac,
5079 "llvm.SI.buffer.load.dword.i32.i32",
5080 ctx->i32, args, 9,
5081 AC_FUNC_ATTR_READONLY);
5082
5083 LLVMBuildStore(ctx->builder,
5084 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
5085 }
5086 idx++;
5087 }
5088 handle_vs_outputs_post(ctx);
5089 }
5090
5091 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5092 struct nir_shader *geom_shader,
5093 struct ac_shader_binary *binary,
5094 struct ac_shader_config *config,
5095 struct ac_shader_variant_info *shader_info,
5096 const struct ac_nir_compiler_options *options,
5097 bool dump_shader)
5098 {
5099 struct nir_to_llvm_context ctx = {0};
5100 ctx.context = LLVMContextCreate();
5101 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5102 ctx.options = options;
5103 ctx.shader_info = shader_info;
5104
5105 ac_llvm_context_init(&ctx.ac, ctx.context);
5106 ctx.ac.module = ctx.module;
5107
5108 ctx.is_gs_copy_shader = true;
5109 LLVMSetTarget(ctx.module, "amdgcn--");
5110 setup_types(&ctx);
5111
5112 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5113 ctx.ac.builder = ctx.builder;
5114 ctx.stage = MESA_SHADER_VERTEX;
5115
5116 create_function(&ctx);
5117
5118 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5119 ac_setup_rings(&ctx);
5120
5121 nir_foreach_variable(variable, &geom_shader->outputs)
5122 handle_shader_output_decl(&ctx, variable);
5123
5124 ac_gs_copy_shader_emit(&ctx);
5125
5126 LLVMBuildRetVoid(ctx.builder);
5127
5128 ac_llvm_finalize_module(&ctx);
5129
5130 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5131 MESA_SHADER_VERTEX,
5132 dump_shader, options->supports_spill);
5133 }