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[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 };
43
44 #define CONST_ADDR_SPACE 2
45 #define LOCAL_ADDR_SPACE 3
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
49
50 enum desc_type {
51 DESC_IMAGE,
52 DESC_FMASK,
53 DESC_SAMPLER,
54 DESC_BUFFER,
55 };
56
57 struct nir_to_llvm_context;
58
59 struct ac_nir_context {
60 struct ac_llvm_context ac;
61 struct ac_shader_abi *abi;
62
63 gl_shader_stage stage;
64
65 struct hash_table *defs;
66 struct hash_table *phis;
67 struct hash_table *vars;
68
69 LLVMValueRef main_function;
70 LLVMBasicBlockRef continue_block;
71 LLVMBasicBlockRef break_block;
72
73 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
74
75 int num_locals;
76 LLVMValueRef *locals;
77
78 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
79 };
80
81 struct nir_to_llvm_context {
82 struct ac_llvm_context ac;
83 const struct ac_nir_compiler_options *options;
84 struct ac_shader_variant_info *shader_info;
85 struct ac_shader_abi abi;
86 struct ac_nir_context *nir;
87
88 unsigned max_workgroup_size;
89 LLVMContextRef context;
90 LLVMModuleRef module;
91 LLVMBuilderRef builder;
92 LLVMValueRef main_function;
93
94 struct hash_table *defs;
95 struct hash_table *phis;
96
97 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
98 LLVMValueRef ring_offsets;
99 LLVMValueRef push_constants;
100 LLVMValueRef num_work_groups;
101 LLVMValueRef workgroup_ids;
102 LLVMValueRef local_invocation_ids;
103 LLVMValueRef tg_size;
104
105 LLVMValueRef vertex_buffers;
106 LLVMValueRef rel_auto_id;
107 LLVMValueRef vs_prim_id;
108 LLVMValueRef ls_out_layout;
109 LLVMValueRef es2gs_offset;
110
111 LLVMValueRef tcs_offchip_layout;
112 LLVMValueRef tcs_out_offsets;
113 LLVMValueRef tcs_out_layout;
114 LLVMValueRef tcs_in_layout;
115 LLVMValueRef oc_lds;
116 LLVMValueRef tess_factor_offset;
117 LLVMValueRef tcs_patch_id;
118 LLVMValueRef tcs_rel_ids;
119 LLVMValueRef tes_rel_patch_id;
120 LLVMValueRef tes_patch_id;
121 LLVMValueRef tes_u;
122 LLVMValueRef tes_v;
123
124 LLVMValueRef gsvs_ring_stride;
125 LLVMValueRef gsvs_num_entries;
126 LLVMValueRef gs2vs_offset;
127 LLVMValueRef gs_wave_id;
128 LLVMValueRef gs_vtx_offset[6];
129 LLVMValueRef gs_prim_id, gs_invocation_id;
130
131 LLVMValueRef esgs_ring;
132 LLVMValueRef gsvs_ring;
133 LLVMValueRef hs_ring_tess_offchip;
134 LLVMValueRef hs_ring_tess_factor;
135
136 LLVMValueRef prim_mask;
137 LLVMValueRef sample_pos_offset;
138 LLVMValueRef persp_sample, persp_center, persp_centroid;
139 LLVMValueRef linear_sample, linear_center, linear_centroid;
140 LLVMValueRef front_face;
141 LLVMValueRef ancillary;
142 LLVMValueRef sample_coverage;
143 LLVMValueRef frag_pos[4];
144
145 LLVMTypeRef i1;
146 LLVMTypeRef i8;
147 LLVMTypeRef i16;
148 LLVMTypeRef i32;
149 LLVMTypeRef i64;
150 LLVMTypeRef v2i32;
151 LLVMTypeRef v3i32;
152 LLVMTypeRef v4i32;
153 LLVMTypeRef v8i32;
154 LLVMTypeRef f64;
155 LLVMTypeRef f32;
156 LLVMTypeRef f16;
157 LLVMTypeRef v2f32;
158 LLVMTypeRef v4f32;
159 LLVMTypeRef voidt;
160
161 LLVMValueRef i1true;
162 LLVMValueRef i1false;
163 LLVMValueRef i32zero;
164 LLVMValueRef i32one;
165 LLVMValueRef f32zero;
166 LLVMValueRef f32one;
167 LLVMValueRef v4f32empty;
168
169 unsigned uniform_md_kind;
170 LLVMValueRef empty_md;
171 gl_shader_stage stage;
172
173 LLVMValueRef lds;
174 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
175
176 uint64_t input_mask;
177 uint64_t output_mask;
178 uint8_t num_output_clips;
179 uint8_t num_output_culls;
180
181 bool has_ds_bpermute;
182
183 bool is_gs_copy_shader;
184 LLVMValueRef gs_next_vertex;
185 unsigned gs_max_out_vertices;
186
187 unsigned tes_primitive_mode;
188 uint64_t tess_outputs_written;
189 uint64_t tess_patch_outputs_written;
190 };
191
192 static inline struct nir_to_llvm_context *
193 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
194 {
195 struct nir_to_llvm_context *ctx = NULL;
196 return container_of(abi, ctx, abi);
197 }
198
199 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
200 const nir_deref_var *deref,
201 enum desc_type desc_type);
202 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
203 {
204 return (index * 4) + chan;
205 }
206
207 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
208 {
209 /* handle patch indices separate */
210 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
211 return 0;
212 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
213 return 1;
214 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
215 return 2 + (slot - VARYING_SLOT_PATCH0);
216
217 if (slot == VARYING_SLOT_POS)
218 return 0;
219 if (slot == VARYING_SLOT_PSIZ)
220 return 1;
221 if (slot == VARYING_SLOT_CLIP_DIST0)
222 return 2;
223 /* 3 is reserved for clip dist as well */
224 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
225 return 4 + (slot - VARYING_SLOT_VAR0);
226 unreachable("illegal slot in get unique index\n");
227 }
228
229 static unsigned llvm_get_type_size(LLVMTypeRef type)
230 {
231 LLVMTypeKind kind = LLVMGetTypeKind(type);
232
233 switch (kind) {
234 case LLVMIntegerTypeKind:
235 return LLVMGetIntTypeWidth(type) / 8;
236 case LLVMFloatTypeKind:
237 return 4;
238 case LLVMPointerTypeKind:
239 return 8;
240 case LLVMVectorTypeKind:
241 return LLVMGetVectorSize(type) *
242 llvm_get_type_size(LLVMGetElementType(type));
243 default:
244 assert(0);
245 return 0;
246 }
247 }
248
249 static void set_llvm_calling_convention(LLVMValueRef func,
250 gl_shader_stage stage)
251 {
252 enum radeon_llvm_calling_convention calling_conv;
253
254 switch (stage) {
255 case MESA_SHADER_VERTEX:
256 case MESA_SHADER_TESS_CTRL:
257 case MESA_SHADER_TESS_EVAL:
258 calling_conv = RADEON_LLVM_AMDGPU_VS;
259 break;
260 case MESA_SHADER_GEOMETRY:
261 calling_conv = RADEON_LLVM_AMDGPU_GS;
262 break;
263 case MESA_SHADER_FRAGMENT:
264 calling_conv = RADEON_LLVM_AMDGPU_PS;
265 break;
266 case MESA_SHADER_COMPUTE:
267 calling_conv = RADEON_LLVM_AMDGPU_CS;
268 break;
269 default:
270 unreachable("Unhandle shader type");
271 }
272
273 LLVMSetFunctionCallConv(func, calling_conv);
274 }
275
276 #define MAX_ARGS 23
277 struct arg_info {
278 LLVMTypeRef types[MAX_ARGS];
279 LLVMValueRef *assign[MAX_ARGS];
280 unsigned array_params_mask;
281 uint8_t count;
282 uint8_t user_sgpr_count;
283 uint8_t sgpr_count;
284 uint8_t num_user_sgprs_used;
285 uint8_t num_sgprs_used;
286 uint8_t num_vgprs_used;
287 };
288
289 static inline void
290 add_argument(struct arg_info *info,
291 LLVMTypeRef type, LLVMValueRef *param_ptr)
292 {
293 assert(info->count < MAX_ARGS);
294 info->assign[info->count] = param_ptr;
295 info->types[info->count] = type;
296 info->count++;
297 }
298
299 static inline void
300 add_sgpr_argument(struct arg_info *info,
301 LLVMTypeRef type, LLVMValueRef *param_ptr)
302 {
303 add_argument(info, type, param_ptr);
304 info->num_sgprs_used += llvm_get_type_size(type) / 4;
305 info->sgpr_count++;
306 }
307
308 static inline void
309 add_user_sgpr_argument(struct arg_info *info,
310 LLVMTypeRef type,
311 LLVMValueRef *param_ptr)
312 {
313 add_sgpr_argument(info, type, param_ptr);
314 info->num_user_sgprs_used += llvm_get_type_size(type) / 4;
315 info->user_sgpr_count++;
316 }
317
318 static inline void
319 add_vgpr_argument(struct arg_info *info,
320 LLVMTypeRef type,
321 LLVMValueRef *param_ptr)
322 {
323 add_argument(info, type, param_ptr);
324 info->num_vgprs_used += llvm_get_type_size(type) / 4;
325 }
326
327 static inline void
328 add_user_sgpr_array_argument(struct arg_info *info,
329 LLVMTypeRef type,
330 LLVMValueRef *param_ptr)
331 {
332 info->array_params_mask |= (1 << info->count);
333 add_user_sgpr_argument(info, type, param_ptr);
334 }
335
336 static void assign_arguments(LLVMValueRef main_function,
337 struct arg_info *info)
338 {
339 unsigned i;
340 for (i = 0; i < info->count; i++) {
341 if (info->assign[i])
342 *info->assign[i] = LLVMGetParam(main_function, i);
343 }
344 }
345
346 static LLVMValueRef
347 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
348 LLVMBuilderRef builder, LLVMTypeRef *return_types,
349 unsigned num_return_elems,
350 struct arg_info *args,
351 unsigned max_workgroup_size,
352 bool unsafe_math)
353 {
354 LLVMTypeRef main_function_type, ret_type;
355 LLVMBasicBlockRef main_function_body;
356
357 if (num_return_elems)
358 ret_type = LLVMStructTypeInContext(ctx, return_types,
359 num_return_elems, true);
360 else
361 ret_type = LLVMVoidTypeInContext(ctx);
362
363 /* Setup the function */
364 main_function_type =
365 LLVMFunctionType(ret_type, args->types, args->count, 0);
366 LLVMValueRef main_function =
367 LLVMAddFunction(module, "main", main_function_type);
368 main_function_body =
369 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
370 LLVMPositionBuilderAtEnd(builder, main_function_body);
371
372 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
373 for (unsigned i = 0; i < args->sgpr_count; ++i) {
374 if (args->array_params_mask & (1 << i)) {
375 LLVMValueRef P = LLVMGetParam(main_function, i);
376 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
377 ac_add_attr_dereferenceable(P, UINT64_MAX);
378 }
379 else {
380 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
381 }
382 }
383
384 if (max_workgroup_size) {
385 ac_llvm_add_target_dep_function_attr(main_function,
386 "amdgpu-max-work-group-size",
387 max_workgroup_size);
388 }
389 if (unsafe_math) {
390 /* These were copied from some LLVM test. */
391 LLVMAddTargetDependentFunctionAttr(main_function,
392 "less-precise-fpmad",
393 "true");
394 LLVMAddTargetDependentFunctionAttr(main_function,
395 "no-infs-fp-math",
396 "true");
397 LLVMAddTargetDependentFunctionAttr(main_function,
398 "no-nans-fp-math",
399 "true");
400 LLVMAddTargetDependentFunctionAttr(main_function,
401 "unsafe-fp-math",
402 "true");
403 }
404 return main_function;
405 }
406
407 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
408 {
409 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
410 CONST_ADDR_SPACE);
411 }
412
413 static LLVMTypeRef to_integer_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
414 {
415 if (t == ctx->f16 || t == ctx->i16)
416 return ctx->i16;
417 else if (t == ctx->f32 || t == ctx->i32)
418 return ctx->i32;
419 else if (t == ctx->f64 || t == ctx->i64)
420 return ctx->i64;
421 else
422 unreachable("Unhandled integer size");
423 }
424
425 static LLVMTypeRef to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
426 {
427 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
428 LLVMTypeRef elem_type = LLVMGetElementType(t);
429 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
430 LLVMGetVectorSize(t));
431 }
432 return to_integer_type_scalar(ctx, t);
433 }
434
435 static LLVMValueRef to_integer(struct ac_llvm_context *ctx, LLVMValueRef v)
436 {
437 LLVMTypeRef type = LLVMTypeOf(v);
438 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
439 }
440
441 static LLVMTypeRef to_float_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
442 {
443 if (t == ctx->i16 || t == ctx->f16)
444 return ctx->f16;
445 else if (t == ctx->i32 || t == ctx->f32)
446 return ctx->f32;
447 else if (t == ctx->i64 || t == ctx->f64)
448 return ctx->f64;
449 else
450 unreachable("Unhandled float size");
451 }
452
453 static LLVMTypeRef to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
454 {
455 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
456 LLVMTypeRef elem_type = LLVMGetElementType(t);
457 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
458 LLVMGetVectorSize(t));
459 }
460 return to_float_type_scalar(ctx, t);
461 }
462
463 static LLVMValueRef to_float(struct ac_llvm_context *ctx, LLVMValueRef v)
464 {
465 LLVMTypeRef type = LLVMTypeOf(v);
466 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
467 }
468
469 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
470 {
471 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
472 type = LLVMGetElementType(type);
473
474 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
475 return LLVMGetIntTypeWidth(type);
476
477 if (type == ctx->f16)
478 return 16;
479 if (type == ctx->f32)
480 return 32;
481 if (type == ctx->f64)
482 return 64;
483
484 unreachable("Unhandled type kind in get_elem_bits");
485 }
486
487 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
488 LLVMValueRef param, unsigned rshift,
489 unsigned bitwidth)
490 {
491 LLVMValueRef value = param;
492 if (rshift)
493 value = LLVMBuildLShr(ctx->builder, value,
494 LLVMConstInt(ctx->i32, rshift, false), "");
495
496 if (rshift + bitwidth < 32) {
497 unsigned mask = (1 << bitwidth) - 1;
498 value = LLVMBuildAnd(ctx->builder, value,
499 LLVMConstInt(ctx->i32, mask, false), "");
500 }
501 return value;
502 }
503
504 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
505 {
506 switch (ctx->stage) {
507 case MESA_SHADER_TESS_CTRL:
508 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
509 case MESA_SHADER_TESS_EVAL:
510 return ctx->tes_rel_patch_id;
511 break;
512 default:
513 unreachable("Illegal stage");
514 }
515 }
516
517 /* Tessellation shaders pass outputs to the next shader using LDS.
518 *
519 * LS outputs = TCS inputs
520 * TCS outputs = TES inputs
521 *
522 * The LDS layout is:
523 * - TCS inputs for patch 0
524 * - TCS inputs for patch 1
525 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
526 * - ...
527 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
528 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
529 * - TCS outputs for patch 1
530 * - Per-patch TCS outputs for patch 1
531 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
532 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
533 * - ...
534 *
535 * All three shaders VS(LS), TCS, TES share the same LDS space.
536 */
537 static LLVMValueRef
538 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
539 {
540 if (ctx->stage == MESA_SHADER_VERTEX)
541 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
542 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
543 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
544 else {
545 assert(0);
546 return NULL;
547 }
548 }
549
550 static LLVMValueRef
551 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
552 {
553 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
554 }
555
556 static LLVMValueRef
557 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
558 {
559 return LLVMBuildMul(ctx->builder,
560 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
561 LLVMConstInt(ctx->i32, 4, false), "");
562 }
563
564 static LLVMValueRef
565 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
566 {
567 return LLVMBuildMul(ctx->builder,
568 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
569 LLVMConstInt(ctx->i32, 4, false), "");
570 }
571
572 static LLVMValueRef
573 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
574 {
575 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
576 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
577
578 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
579 }
580
581 static LLVMValueRef
582 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
583 {
584 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
585 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
586 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
587
588 return LLVMBuildAdd(ctx->builder, patch0_offset,
589 LLVMBuildMul(ctx->builder, patch_stride,
590 rel_patch_id, ""),
591 "");
592 }
593
594 static LLVMValueRef
595 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
596 {
597 LLVMValueRef patch0_patch_data_offset =
598 get_tcs_out_patch0_patch_data_offset(ctx);
599 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
600 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
601
602 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
603 LLVMBuildMul(ctx->builder, patch_stride,
604 rel_patch_id, ""),
605 "");
606 }
607
608 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
609 {
610 ud_info->sgpr_idx = *sgpr_idx;
611 ud_info->num_sgprs = num_sgprs;
612 ud_info->indirect = false;
613 ud_info->indirect_offset = 0;
614 *sgpr_idx += num_sgprs;
615 }
616
617 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
618 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
619 {
620 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
621 }
622
623
624 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
625 uint32_t indirect_offset)
626 {
627 ud_info->sgpr_idx = sgpr_idx;
628 ud_info->num_sgprs = num_sgprs;
629 ud_info->indirect = true;
630 ud_info->indirect_offset = indirect_offset;
631 }
632
633 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
634 {
635 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
636 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
637 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
638 "tess_lds");
639 }
640
641 struct user_sgpr_info {
642 bool need_ring_offsets;
643 uint8_t sgpr_count;
644 bool indirect_all_descriptor_sets;
645 };
646
647 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
648 struct user_sgpr_info *user_sgpr_info)
649 {
650 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
651
652 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
653 if (ctx->stage == MESA_SHADER_GEOMETRY ||
654 ctx->stage == MESA_SHADER_VERTEX ||
655 ctx->stage == MESA_SHADER_TESS_CTRL ||
656 ctx->stage == MESA_SHADER_TESS_EVAL ||
657 ctx->is_gs_copy_shader)
658 user_sgpr_info->need_ring_offsets = true;
659
660 if (ctx->stage == MESA_SHADER_FRAGMENT &&
661 ctx->shader_info->info.ps.needs_sample_positions)
662 user_sgpr_info->need_ring_offsets = true;
663
664 /* 2 user sgprs will nearly always be allocated for scratch/rings */
665 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
666 user_sgpr_info->sgpr_count += 2;
667 }
668
669 switch (ctx->stage) {
670 case MESA_SHADER_COMPUTE:
671 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
672 break;
673 case MESA_SHADER_FRAGMENT:
674 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
675 break;
676 case MESA_SHADER_VERTEX:
677 if (!ctx->is_gs_copy_shader) {
678 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
679 if (ctx->shader_info->info.vs.needs_draw_id) {
680 user_sgpr_info->sgpr_count += 3;
681 } else {
682 user_sgpr_info->sgpr_count += 2;
683 }
684 }
685 if (ctx->options->key.vs.as_ls)
686 user_sgpr_info->sgpr_count++;
687 break;
688 case MESA_SHADER_TESS_CTRL:
689 user_sgpr_info->sgpr_count += 4;
690 break;
691 case MESA_SHADER_TESS_EVAL:
692 user_sgpr_info->sgpr_count += 1;
693 break;
694 case MESA_SHADER_GEOMETRY:
695 user_sgpr_info->sgpr_count += 2;
696 break;
697 default:
698 break;
699 }
700
701 if (ctx->shader_info->info.needs_push_constants)
702 user_sgpr_info->sgpr_count += 2;
703
704 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
705 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
706 user_sgpr_info->sgpr_count += 2;
707 user_sgpr_info->indirect_all_descriptor_sets = true;
708 } else {
709 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
710 }
711 }
712
713 static void create_function(struct nir_to_llvm_context *ctx)
714 {
715 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
716 uint8_t user_sgpr_idx;
717 struct user_sgpr_info user_sgpr_info;
718 struct arg_info args = {};
719 LLVMValueRef desc_sets;
720
721 allocate_user_sgprs(ctx, &user_sgpr_info);
722 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
723 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
724 }
725
726 /* 1 for each descriptor set */
727 if (!user_sgpr_info.indirect_all_descriptor_sets) {
728 for (unsigned i = 0; i < num_sets; ++i) {
729 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
730 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
731 }
732 }
733 } else
734 add_user_sgpr_array_argument(&args, const_array(const_array(ctx->i8, 1024 * 1024), 32), &desc_sets);
735
736 if (ctx->shader_info->info.needs_push_constants) {
737 /* 1 for push constants and dynamic descriptors */
738 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
739 }
740
741 switch (ctx->stage) {
742 case MESA_SHADER_COMPUTE:
743 if (ctx->shader_info->info.cs.grid_components_used)
744 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
745 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
746 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
747 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
748 break;
749 case MESA_SHADER_VERTEX:
750 if (!ctx->is_gs_copy_shader) {
751 if (ctx->shader_info->info.vs.has_vertex_buffers)
752 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
753 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.base_vertex); // base vertex
754 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.start_instance);// start instance
755 if (ctx->shader_info->info.vs.needs_draw_id)
756 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.draw_id); // draw id
757 }
758 if (ctx->options->key.vs.as_es)
759 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
760 else if (ctx->options->key.vs.as_ls)
761 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
762 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
763 if (!ctx->is_gs_copy_shader) {
764 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
765 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
766 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
767 }
768 break;
769 case MESA_SHADER_TESS_CTRL:
770 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
771 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
772 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
773 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
774 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
775 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
776 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
777 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
778 break;
779 case MESA_SHADER_TESS_EVAL:
780 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
781 if (ctx->options->key.tes.as_es) {
782 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
783 add_sgpr_argument(&args, ctx->i32, NULL); //
784 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
785 } else {
786 add_sgpr_argument(&args, ctx->i32, NULL); //
787 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
788 }
789 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
790 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
791 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
792 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
793 break;
794 case MESA_SHADER_GEOMETRY:
795 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
796 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
797 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
798 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
799 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
800 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
801 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
802 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
803 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
804 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
805 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
806 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
807 break;
808 case MESA_SHADER_FRAGMENT:
809 if (ctx->shader_info->info.ps.needs_sample_positions)
810 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
811 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
812 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
813 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
814 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
815 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
816 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
817 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
818 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
819 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
820 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[0]); /* pos x float */
821 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[1]); /* pos y float */
822 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[2]); /* pos z float */
823 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[3]); /* pos w float */
824 add_vgpr_argument(&args, ctx->i32, &ctx->front_face); /* front face */
825 add_vgpr_argument(&args, ctx->i32, &ctx->ancillary); /* ancillary */
826 add_vgpr_argument(&args, ctx->i32, &ctx->sample_coverage); /* sample coverage */
827 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
828 break;
829 default:
830 unreachable("Shader stage not implemented");
831 }
832
833 ctx->main_function = create_llvm_function(
834 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
835 ctx->max_workgroup_size,
836 ctx->options->unsafe_math);
837 set_llvm_calling_convention(ctx->main_function, ctx->stage);
838
839
840 ctx->shader_info->num_input_vgprs = 0;
841 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs =
842 ctx->options->supports_spill ? 2 : 0;
843
844 ctx->shader_info->num_user_sgprs += args.num_user_sgprs_used;
845 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
846
847 if (ctx->stage != MESA_SHADER_FRAGMENT)
848 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
849
850 assign_arguments(ctx->main_function, &args);
851
852 user_sgpr_idx = 0;
853
854 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
855 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
856 if (ctx->options->supports_spill) {
857 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
858 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
859 NULL, 0, AC_FUNC_ATTR_READNONE);
860 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
861 const_array(ctx->v4i32, 16), "");
862 }
863 }
864
865 if (!user_sgpr_info.indirect_all_descriptor_sets) {
866 for (unsigned i = 0; i < num_sets; ++i) {
867 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
868 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
869 } else
870 ctx->descriptor_sets[i] = NULL;
871 }
872 } else {
873 uint32_t desc_sgpr_idx = user_sgpr_idx;
874 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
875
876 for (unsigned i = 0; i < num_sets; ++i) {
877 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
878 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
879 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
880
881 } else
882 ctx->descriptor_sets[i] = NULL;
883 }
884 ctx->shader_info->need_indirect_descriptor_sets = true;
885 }
886
887 if (ctx->shader_info->info.needs_push_constants) {
888 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
889 }
890
891 switch (ctx->stage) {
892 case MESA_SHADER_COMPUTE:
893 if (ctx->shader_info->info.cs.grid_components_used) {
894 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
895 }
896 break;
897 case MESA_SHADER_VERTEX:
898 if (!ctx->is_gs_copy_shader) {
899 if (ctx->shader_info->info.vs.has_vertex_buffers) {
900 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
901 }
902 unsigned vs_num = 2;
903 if (ctx->shader_info->info.vs.needs_draw_id)
904 vs_num++;
905
906 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
907 }
908 if (ctx->options->key.vs.as_ls) {
909 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
910 }
911 if (ctx->options->key.vs.as_ls)
912 declare_tess_lds(ctx);
913 break;
914 case MESA_SHADER_TESS_CTRL:
915 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
916 declare_tess_lds(ctx);
917 break;
918 case MESA_SHADER_TESS_EVAL:
919 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
920 break;
921 case MESA_SHADER_GEOMETRY:
922 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
923 break;
924 case MESA_SHADER_FRAGMENT:
925 if (ctx->shader_info->info.ps.needs_sample_positions) {
926 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
927 }
928 break;
929 default:
930 unreachable("Shader stage not implemented");
931 }
932 }
933
934 static void setup_types(struct nir_to_llvm_context *ctx)
935 {
936 LLVMValueRef args[4];
937
938 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
939 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
940 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
941 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
942 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
943 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
944 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
945 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
946 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
947 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
948 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
949 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
950 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
951 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
952 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
953
954 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
955 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
956 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
957 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
958 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
959 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
960
961 args[0] = ctx->f32zero;
962 args[1] = ctx->f32zero;
963 args[2] = ctx->f32zero;
964 args[3] = ctx->f32one;
965 ctx->v4f32empty = LLVMConstVector(args, 4);
966
967 ctx->uniform_md_kind =
968 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
969 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
970
971 args[0] = LLVMConstReal(ctx->f32, 2.5);
972 }
973
974 static int get_llvm_num_components(LLVMValueRef value)
975 {
976 LLVMTypeRef type = LLVMTypeOf(value);
977 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
978 ? LLVMGetVectorSize(type)
979 : 1;
980 return num_components;
981 }
982
983 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
984 LLVMValueRef value,
985 int index)
986 {
987 int count = get_llvm_num_components(value);
988
989 assert(index < count);
990 if (count == 1)
991 return value;
992
993 return LLVMBuildExtractElement(ac->builder, value,
994 LLVMConstInt(ac->i32, index, false), "");
995 }
996
997 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
998 LLVMValueRef value, unsigned count)
999 {
1000 unsigned num_components = get_llvm_num_components(value);
1001 if (count == num_components)
1002 return value;
1003
1004 LLVMValueRef masks[] = {
1005 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1006 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1007
1008 if (count == 1)
1009 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1010 "");
1011
1012 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1013 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1014 }
1015
1016 static void
1017 build_store_values_extended(struct ac_llvm_context *ac,
1018 LLVMValueRef *values,
1019 unsigned value_count,
1020 unsigned value_stride,
1021 LLVMValueRef vec)
1022 {
1023 LLVMBuilderRef builder = ac->builder;
1024 unsigned i;
1025
1026 if (value_count == 1) {
1027 LLVMBuildStore(builder, vec, values[0]);
1028 return;
1029 }
1030
1031 for (i = 0; i < value_count; i++) {
1032 LLVMValueRef ptr = values[i * value_stride];
1033 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1034 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1035 LLVMBuildStore(builder, value, ptr);
1036 }
1037 }
1038
1039 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1040 const nir_ssa_def *def)
1041 {
1042 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1043 if (def->num_components > 1) {
1044 type = LLVMVectorType(type, def->num_components);
1045 }
1046 return type;
1047 }
1048
1049 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1050 {
1051 assert(src.is_ssa);
1052 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1053 return (LLVMValueRef)entry->data;
1054 }
1055
1056
1057 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1058 const struct nir_block *b)
1059 {
1060 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1061 return (LLVMBasicBlockRef)entry->data;
1062 }
1063
1064 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1065 nir_alu_src src,
1066 unsigned num_components)
1067 {
1068 LLVMValueRef value = get_src(ctx, src.src);
1069 bool need_swizzle = false;
1070
1071 assert(value);
1072 LLVMTypeRef type = LLVMTypeOf(value);
1073 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1074 ? LLVMGetVectorSize(type)
1075 : 1;
1076
1077 for (unsigned i = 0; i < num_components; ++i) {
1078 assert(src.swizzle[i] < src_components);
1079 if (src.swizzle[i] != i)
1080 need_swizzle = true;
1081 }
1082
1083 if (need_swizzle || num_components != src_components) {
1084 LLVMValueRef masks[] = {
1085 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1086 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1087 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1088 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1089
1090 if (src_components > 1 && num_components == 1) {
1091 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1092 masks[0], "");
1093 } else if (src_components == 1 && num_components > 1) {
1094 LLVMValueRef values[] = {value, value, value, value};
1095 value = ac_build_gather_values(&ctx->ac, values, num_components);
1096 } else {
1097 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1098 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1099 swizzle, "");
1100 }
1101 }
1102 assert(!src.negate);
1103 assert(!src.abs);
1104 return value;
1105 }
1106
1107 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1108 LLVMIntPredicate pred, LLVMValueRef src0,
1109 LLVMValueRef src1)
1110 {
1111 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1112 return LLVMBuildSelect(ctx->builder, result,
1113 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1114 LLVMConstInt(ctx->i32, 0, false), "");
1115 }
1116
1117 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1118 LLVMRealPredicate pred, LLVMValueRef src0,
1119 LLVMValueRef src1)
1120 {
1121 LLVMValueRef result;
1122 src0 = to_float(ctx, src0);
1123 src1 = to_float(ctx, src1);
1124 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1125 return LLVMBuildSelect(ctx->builder, result,
1126 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1127 LLVMConstInt(ctx->i32, 0, false), "");
1128 }
1129
1130 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1131 const char *intrin,
1132 LLVMTypeRef result_type,
1133 LLVMValueRef src0)
1134 {
1135 char name[64];
1136 LLVMValueRef params[] = {
1137 to_float(ctx, src0),
1138 };
1139
1140 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1141 get_elem_bits(ctx, result_type));
1142 assert(length < sizeof(name));
1143 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1144 }
1145
1146 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1147 const char *intrin,
1148 LLVMTypeRef result_type,
1149 LLVMValueRef src0, LLVMValueRef src1)
1150 {
1151 char name[64];
1152 LLVMValueRef params[] = {
1153 to_float(ctx, src0),
1154 to_float(ctx, src1),
1155 };
1156
1157 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1158 get_elem_bits(ctx, result_type));
1159 assert(length < sizeof(name));
1160 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1161 }
1162
1163 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1164 const char *intrin,
1165 LLVMTypeRef result_type,
1166 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1167 {
1168 char name[64];
1169 LLVMValueRef params[] = {
1170 to_float(ctx, src0),
1171 to_float(ctx, src1),
1172 to_float(ctx, src2),
1173 };
1174
1175 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1176 get_elem_bits(ctx, result_type));
1177 assert(length < sizeof(name));
1178 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1179 }
1180
1181 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1182 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1183 {
1184 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1185 ctx->i32_0, "");
1186 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1187 }
1188
1189 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1190 LLVMValueRef src0)
1191 {
1192 LLVMValueRef params[2] = {
1193 src0,
1194
1195 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1196 * add special code to check for x=0. The reason is that
1197 * the LLVM behavior for x=0 is different from what we
1198 * need here.
1199 *
1200 * The hardware already implements the correct behavior.
1201 */
1202 LLVMConstInt(ctx->i1, 1, false),
1203 };
1204 return ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1205 }
1206
1207 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1208 LLVMValueRef src0)
1209 {
1210 return ac_build_imsb(ctx, src0, ctx->i32);
1211 }
1212
1213 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1214 LLVMValueRef src0)
1215 {
1216 return ac_build_umsb(ctx, src0, ctx->i32);
1217 }
1218
1219 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1220 LLVMIntPredicate pred,
1221 LLVMValueRef src0, LLVMValueRef src1)
1222 {
1223 return LLVMBuildSelect(ctx->builder,
1224 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1225 src0,
1226 src1, "");
1227
1228 }
1229 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1230 LLVMValueRef src0)
1231 {
1232 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1233 LLVMBuildNeg(ctx->builder, src0, ""));
1234 }
1235
1236 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1237 LLVMValueRef src0)
1238 {
1239 LLVMValueRef cmp, val;
1240
1241 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1242 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1243 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1244 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1245 return val;
1246 }
1247
1248 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1249 LLVMValueRef src0)
1250 {
1251 LLVMValueRef cmp, val;
1252
1253 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1254 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1255 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1256 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1257 return val;
1258 }
1259
1260 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1261 LLVMValueRef src0)
1262 {
1263 const char *intr = "llvm.floor.f32";
1264 LLVMValueRef fsrc0 = to_float(ctx, src0);
1265 LLVMValueRef params[] = {
1266 fsrc0,
1267 };
1268 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1269 ctx->f32, params, 1,
1270 AC_FUNC_ATTR_READNONE);
1271 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1272 }
1273
1274 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1275 const char *intrin,
1276 LLVMValueRef src0, LLVMValueRef src1)
1277 {
1278 LLVMTypeRef ret_type;
1279 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1280 LLVMValueRef res;
1281 LLVMValueRef params[] = { src0, src1 };
1282 ret_type = LLVMStructTypeInContext(ctx->context, types,
1283 2, true);
1284
1285 res = ac_build_intrinsic(ctx, intrin, ret_type,
1286 params, 2, AC_FUNC_ATTR_READNONE);
1287
1288 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1289 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1290 return res;
1291 }
1292
1293 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1294 LLVMValueRef src0)
1295 {
1296 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1297 }
1298
1299 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1300 LLVMValueRef src0)
1301 {
1302 src0 = to_float(ctx, src0);
1303 return LLVMBuildSExt(ctx->builder,
1304 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1305 ctx->i32, "");
1306 }
1307
1308 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1309 LLVMValueRef src0)
1310 {
1311 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1312 }
1313
1314 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1315 LLVMValueRef src0)
1316 {
1317 return LLVMBuildSExt(ctx->builder,
1318 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1319 ctx->i32, "");
1320 }
1321
1322 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1323 LLVMValueRef src0)
1324 {
1325 LLVMValueRef result;
1326 LLVMValueRef cond;
1327
1328 src0 = to_float(&ctx->ac, src0);
1329 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1330
1331 /* TODO SI/CIK options here */
1332 if (ctx->options->chip_class >= VI) {
1333 LLVMValueRef args[2];
1334 /* Check if the result is a denormal - and flush to 0 if so. */
1335 args[0] = result;
1336 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1337 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1338 }
1339
1340 /* need to convert back up to f32 */
1341 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1342
1343 if (ctx->options->chip_class >= VI)
1344 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1345
1346 return result;
1347 }
1348
1349 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1350 LLVMValueRef src0, LLVMValueRef src1)
1351 {
1352 LLVMValueRef dst64, result;
1353 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1354 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1355
1356 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1357 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1358 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1359 return result;
1360 }
1361
1362 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1363 LLVMValueRef src0, LLVMValueRef src1)
1364 {
1365 LLVMValueRef dst64, result;
1366 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1367 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1368
1369 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1370 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1371 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1372 return result;
1373 }
1374
1375 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1376 bool is_signed,
1377 const LLVMValueRef srcs[3])
1378 {
1379 LLVMValueRef result;
1380 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1381
1382 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1383 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1384 return result;
1385 }
1386
1387 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1388 LLVMValueRef src0, LLVMValueRef src1,
1389 LLVMValueRef src2, LLVMValueRef src3)
1390 {
1391 LLVMValueRef bfi_args[3], result;
1392
1393 bfi_args[0] = LLVMBuildShl(ctx->builder,
1394 LLVMBuildSub(ctx->builder,
1395 LLVMBuildShl(ctx->builder,
1396 ctx->i32_1,
1397 src3, ""),
1398 ctx->i32_1, ""),
1399 src2, "");
1400 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1401 bfi_args[2] = src0;
1402
1403 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1404
1405 /* Calculate:
1406 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1407 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1408 */
1409 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1410 LLVMBuildAnd(ctx->builder, bfi_args[0],
1411 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1412
1413 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1414 return result;
1415 }
1416
1417 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1418 LLVMValueRef src0)
1419 {
1420 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1421 int i;
1422 LLVMValueRef comp[2];
1423
1424 src0 = to_float(ctx, src0);
1425 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1426 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1427 for (i = 0; i < 2; i++) {
1428 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1429 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1430 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1431 }
1432
1433 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1434 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1435
1436 return comp[0];
1437 }
1438
1439 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1440 LLVMValueRef src0)
1441 {
1442 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1443 LLVMValueRef temps[2], result, val;
1444 int i;
1445
1446 for (i = 0; i < 2; i++) {
1447 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1448 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1449 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1450 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1451 }
1452
1453 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1454 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1455 ctx->i32_0, "");
1456 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1457 ctx->i32_1, "");
1458 return result;
1459 }
1460
1461 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1462 nir_op op,
1463 LLVMValueRef src0)
1464 {
1465 unsigned mask;
1466 int idx;
1467 LLVMValueRef result;
1468
1469 if (!ctx->lds && !ctx->has_ds_bpermute)
1470 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1471 LLVMArrayType(ctx->i32, 64),
1472 "ddxy_lds", LOCAL_ADDR_SPACE);
1473
1474 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1475 mask = AC_TID_MASK_LEFT;
1476 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1477 mask = AC_TID_MASK_TOP;
1478 else
1479 mask = AC_TID_MASK_TOP_LEFT;
1480
1481 /* for DDX we want to next X pixel, DDY next Y pixel. */
1482 if (op == nir_op_fddx_fine ||
1483 op == nir_op_fddx_coarse ||
1484 op == nir_op_fddx)
1485 idx = 1;
1486 else
1487 idx = 2;
1488
1489 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1490 mask, idx, ctx->lds,
1491 src0);
1492 return result;
1493 }
1494
1495 /*
1496 * this takes an I,J coordinate pair,
1497 * and works out the X and Y derivatives.
1498 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1499 */
1500 static LLVMValueRef emit_ddxy_interp(
1501 struct nir_to_llvm_context *ctx,
1502 LLVMValueRef interp_ij)
1503 {
1504 LLVMValueRef result[4], a;
1505 unsigned i;
1506
1507 for (i = 0; i < 2; i++) {
1508 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1509 LLVMConstInt(ctx->i32, i, false), "");
1510 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1511 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1512 }
1513 return ac_build_gather_values(&ctx->ac, result, 4);
1514 }
1515
1516 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1517 {
1518 LLVMValueRef src[4], result = NULL;
1519 unsigned num_components = instr->dest.dest.ssa.num_components;
1520 unsigned src_components;
1521 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1522
1523 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1524 switch (instr->op) {
1525 case nir_op_vec2:
1526 case nir_op_vec3:
1527 case nir_op_vec4:
1528 src_components = 1;
1529 break;
1530 case nir_op_pack_half_2x16:
1531 src_components = 2;
1532 break;
1533 case nir_op_unpack_half_2x16:
1534 src_components = 1;
1535 break;
1536 default:
1537 src_components = num_components;
1538 break;
1539 }
1540 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1541 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1542
1543 switch (instr->op) {
1544 case nir_op_fmov:
1545 case nir_op_imov:
1546 result = src[0];
1547 break;
1548 case nir_op_fneg:
1549 src[0] = to_float(&ctx->ac, src[0]);
1550 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1551 break;
1552 case nir_op_ineg:
1553 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1554 break;
1555 case nir_op_inot:
1556 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1557 break;
1558 case nir_op_iadd:
1559 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1560 break;
1561 case nir_op_fadd:
1562 src[0] = to_float(&ctx->ac, src[0]);
1563 src[1] = to_float(&ctx->ac, src[1]);
1564 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1565 break;
1566 case nir_op_fsub:
1567 src[0] = to_float(&ctx->ac, src[0]);
1568 src[1] = to_float(&ctx->ac, src[1]);
1569 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1570 break;
1571 case nir_op_isub:
1572 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1573 break;
1574 case nir_op_imul:
1575 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1576 break;
1577 case nir_op_imod:
1578 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1579 break;
1580 case nir_op_umod:
1581 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1582 break;
1583 case nir_op_fmod:
1584 src[0] = to_float(&ctx->ac, src[0]);
1585 src[1] = to_float(&ctx->ac, src[1]);
1586 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1587 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1588 to_float_type(&ctx->ac, def_type), result);
1589 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1590 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1591 break;
1592 case nir_op_frem:
1593 src[0] = to_float(&ctx->ac, src[0]);
1594 src[1] = to_float(&ctx->ac, src[1]);
1595 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1596 break;
1597 case nir_op_irem:
1598 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1599 break;
1600 case nir_op_idiv:
1601 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1602 break;
1603 case nir_op_udiv:
1604 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1605 break;
1606 case nir_op_fmul:
1607 src[0] = to_float(&ctx->ac, src[0]);
1608 src[1] = to_float(&ctx->ac, src[1]);
1609 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1610 break;
1611 case nir_op_fdiv:
1612 src[0] = to_float(&ctx->ac, src[0]);
1613 src[1] = to_float(&ctx->ac, src[1]);
1614 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1615 break;
1616 case nir_op_frcp:
1617 src[0] = to_float(&ctx->ac, src[0]);
1618 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1619 break;
1620 case nir_op_iand:
1621 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1622 break;
1623 case nir_op_ior:
1624 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1625 break;
1626 case nir_op_ixor:
1627 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1628 break;
1629 case nir_op_ishl:
1630 result = LLVMBuildShl(ctx->ac.builder, src[0],
1631 LLVMBuildZExt(ctx->ac.builder, src[1],
1632 LLVMTypeOf(src[0]), ""),
1633 "");
1634 break;
1635 case nir_op_ishr:
1636 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1637 LLVMBuildZExt(ctx->ac.builder, src[1],
1638 LLVMTypeOf(src[0]), ""),
1639 "");
1640 break;
1641 case nir_op_ushr:
1642 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1643 LLVMBuildZExt(ctx->ac.builder, src[1],
1644 LLVMTypeOf(src[0]), ""),
1645 "");
1646 break;
1647 case nir_op_ilt:
1648 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1649 break;
1650 case nir_op_ine:
1651 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1652 break;
1653 case nir_op_ieq:
1654 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1655 break;
1656 case nir_op_ige:
1657 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1658 break;
1659 case nir_op_ult:
1660 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1661 break;
1662 case nir_op_uge:
1663 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1664 break;
1665 case nir_op_feq:
1666 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1667 break;
1668 case nir_op_fne:
1669 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1670 break;
1671 case nir_op_flt:
1672 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1673 break;
1674 case nir_op_fge:
1675 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1676 break;
1677 case nir_op_fabs:
1678 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1679 to_float_type(&ctx->ac, def_type), src[0]);
1680 break;
1681 case nir_op_iabs:
1682 result = emit_iabs(&ctx->ac, src[0]);
1683 break;
1684 case nir_op_imax:
1685 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1686 break;
1687 case nir_op_imin:
1688 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1689 break;
1690 case nir_op_umax:
1691 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1692 break;
1693 case nir_op_umin:
1694 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1695 break;
1696 case nir_op_isign:
1697 result = emit_isign(&ctx->ac, src[0]);
1698 break;
1699 case nir_op_fsign:
1700 src[0] = to_float(&ctx->ac, src[0]);
1701 result = emit_fsign(&ctx->ac, src[0]);
1702 break;
1703 case nir_op_ffloor:
1704 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1705 to_float_type(&ctx->ac, def_type), src[0]);
1706 break;
1707 case nir_op_ftrunc:
1708 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1709 to_float_type(&ctx->ac, def_type), src[0]);
1710 break;
1711 case nir_op_fceil:
1712 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1713 to_float_type(&ctx->ac, def_type), src[0]);
1714 break;
1715 case nir_op_fround_even:
1716 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1717 to_float_type(&ctx->ac, def_type),src[0]);
1718 break;
1719 case nir_op_ffract:
1720 result = emit_ffract(&ctx->ac, src[0]);
1721 break;
1722 case nir_op_fsin:
1723 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1724 to_float_type(&ctx->ac, def_type), src[0]);
1725 break;
1726 case nir_op_fcos:
1727 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1728 to_float_type(&ctx->ac, def_type), src[0]);
1729 break;
1730 case nir_op_fsqrt:
1731 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1732 to_float_type(&ctx->ac, def_type), src[0]);
1733 break;
1734 case nir_op_fexp2:
1735 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1736 to_float_type(&ctx->ac, def_type), src[0]);
1737 break;
1738 case nir_op_flog2:
1739 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1740 to_float_type(&ctx->ac, def_type), src[0]);
1741 break;
1742 case nir_op_frsq:
1743 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1744 to_float_type(&ctx->ac, def_type), src[0]);
1745 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1746 break;
1747 case nir_op_fpow:
1748 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1749 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1750 break;
1751 case nir_op_fmax:
1752 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1753 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1754 if (instr->dest.dest.ssa.bit_size == 32)
1755 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1756 to_float_type(&ctx->ac, def_type),
1757 result);
1758 break;
1759 case nir_op_fmin:
1760 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1761 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1762 if (instr->dest.dest.ssa.bit_size == 32)
1763 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1764 to_float_type(&ctx->ac, def_type),
1765 result);
1766 break;
1767 case nir_op_ffma:
1768 result = emit_intrin_3f_param(&ctx->ac, "llvm.fma",
1769 to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1770 break;
1771 case nir_op_ibitfield_extract:
1772 result = emit_bitfield_extract(&ctx->ac, true, src);
1773 break;
1774 case nir_op_ubitfield_extract:
1775 result = emit_bitfield_extract(&ctx->ac, false, src);
1776 break;
1777 case nir_op_bitfield_insert:
1778 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1779 break;
1780 case nir_op_bitfield_reverse:
1781 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1782 break;
1783 case nir_op_bit_count:
1784 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1785 break;
1786 case nir_op_vec2:
1787 case nir_op_vec3:
1788 case nir_op_vec4:
1789 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1790 src[i] = to_integer(&ctx->ac, src[i]);
1791 result = ac_build_gather_values(&ctx->ac, src, num_components);
1792 break;
1793 case nir_op_f2i32:
1794 case nir_op_f2i64:
1795 src[0] = to_float(&ctx->ac, src[0]);
1796 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1797 break;
1798 case nir_op_f2u32:
1799 case nir_op_f2u64:
1800 src[0] = to_float(&ctx->ac, src[0]);
1801 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1802 break;
1803 case nir_op_i2f32:
1804 case nir_op_i2f64:
1805 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1806 break;
1807 case nir_op_u2f32:
1808 case nir_op_u2f64:
1809 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1810 break;
1811 case nir_op_f2f64:
1812 result = LLVMBuildFPExt(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1813 break;
1814 case nir_op_f2f32:
1815 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1816 break;
1817 case nir_op_u2u32:
1818 case nir_op_u2u64:
1819 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1820 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1821 else
1822 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1823 break;
1824 case nir_op_i2i32:
1825 case nir_op_i2i64:
1826 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1827 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1828 else
1829 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1830 break;
1831 case nir_op_bcsel:
1832 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1833 break;
1834 case nir_op_find_lsb:
1835 result = emit_find_lsb(&ctx->ac, src[0]);
1836 break;
1837 case nir_op_ufind_msb:
1838 result = emit_ufind_msb(&ctx->ac, src[0]);
1839 break;
1840 case nir_op_ifind_msb:
1841 result = emit_ifind_msb(&ctx->ac, src[0]);
1842 break;
1843 case nir_op_uadd_carry:
1844 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1845 break;
1846 case nir_op_usub_borrow:
1847 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1848 break;
1849 case nir_op_b2f:
1850 result = emit_b2f(&ctx->ac, src[0]);
1851 break;
1852 case nir_op_f2b:
1853 result = emit_f2b(&ctx->ac, src[0]);
1854 break;
1855 case nir_op_b2i:
1856 result = emit_b2i(&ctx->ac, src[0]);
1857 break;
1858 case nir_op_i2b:
1859 result = emit_i2b(&ctx->ac, src[0]);
1860 break;
1861 case nir_op_fquantize2f16:
1862 result = emit_f2f16(ctx->nctx, src[0]);
1863 break;
1864 case nir_op_umul_high:
1865 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1866 break;
1867 case nir_op_imul_high:
1868 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1869 break;
1870 case nir_op_pack_half_2x16:
1871 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1872 break;
1873 case nir_op_unpack_half_2x16:
1874 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1875 break;
1876 case nir_op_fddx:
1877 case nir_op_fddy:
1878 case nir_op_fddx_fine:
1879 case nir_op_fddy_fine:
1880 case nir_op_fddx_coarse:
1881 case nir_op_fddy_coarse:
1882 result = emit_ddxy(ctx->nctx, instr->op, src[0]);
1883 break;
1884
1885 case nir_op_unpack_64_2x32_split_x: {
1886 assert(instr->src[0].src.ssa->num_components == 1);
1887 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1888 LLVMVectorType(ctx->ac.i32, 2),
1889 "");
1890 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1891 ctx->ac.i32_0, "");
1892 break;
1893 }
1894
1895 case nir_op_unpack_64_2x32_split_y: {
1896 assert(instr->src[0].src.ssa->num_components == 1);
1897 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1898 LLVMVectorType(ctx->ac.i32, 2),
1899 "");
1900 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1901 ctx->ac.i32_0, "");
1902 break;
1903 }
1904
1905 case nir_op_pack_64_2x32_split: {
1906 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
1907 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1908 src[0], ctx->ac.i32_0, "");
1909 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1910 src[1], ctx->ac.i32_1, "");
1911 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1912 break;
1913 }
1914
1915 default:
1916 fprintf(stderr, "Unknown NIR alu instr: ");
1917 nir_print_instr(&instr->instr, stderr);
1918 fprintf(stderr, "\n");
1919 abort();
1920 }
1921
1922 if (result) {
1923 assert(instr->dest.dest.is_ssa);
1924 result = to_integer(&ctx->ac, result);
1925 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1926 result);
1927 }
1928 }
1929
1930 static void visit_load_const(struct ac_nir_context *ctx,
1931 const nir_load_const_instr *instr)
1932 {
1933 LLVMValueRef values[4], value = NULL;
1934 LLVMTypeRef element_type =
1935 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1936
1937 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1938 switch (instr->def.bit_size) {
1939 case 32:
1940 values[i] = LLVMConstInt(element_type,
1941 instr->value.u32[i], false);
1942 break;
1943 case 64:
1944 values[i] = LLVMConstInt(element_type,
1945 instr->value.u64[i], false);
1946 break;
1947 default:
1948 fprintf(stderr,
1949 "unsupported nir load_const bit_size: %d\n",
1950 instr->def.bit_size);
1951 abort();
1952 }
1953 }
1954 if (instr->def.num_components > 1) {
1955 value = LLVMConstVector(values, instr->def.num_components);
1956 } else
1957 value = values[0];
1958
1959 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1960 }
1961
1962 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1963 LLVMTypeRef type)
1964 {
1965 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1966 return LLVMBuildBitCast(ctx->builder, ptr,
1967 LLVMPointerType(type, addr_space), "");
1968 }
1969
1970 static LLVMValueRef
1971 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1972 {
1973 LLVMValueRef size =
1974 LLVMBuildExtractElement(ctx->builder, descriptor,
1975 LLVMConstInt(ctx->i32, 2, false), "");
1976
1977 /* VI only */
1978 if (ctx->options->chip_class >= VI && in_elements) {
1979 /* On VI, the descriptor contains the size in bytes,
1980 * but TXQ must return the size in elements.
1981 * The stride is always non-zero for resources using TXQ.
1982 */
1983 LLVMValueRef stride =
1984 LLVMBuildExtractElement(ctx->builder, descriptor,
1985 LLVMConstInt(ctx->i32, 1, false), "");
1986 stride = LLVMBuildLShr(ctx->builder, stride,
1987 LLVMConstInt(ctx->i32, 16, false), "");
1988 stride = LLVMBuildAnd(ctx->builder, stride,
1989 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1990
1991 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1992 }
1993 return size;
1994 }
1995
1996 /**
1997 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1998 * intrinsic names).
1999 */
2000 static void build_int_type_name(
2001 LLVMTypeRef type,
2002 char *buf, unsigned bufsize)
2003 {
2004 assert(bufsize >= 6);
2005
2006 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2007 snprintf(buf, bufsize, "v%ui32",
2008 LLVMGetVectorSize(type));
2009 else
2010 strcpy(buf, "i32");
2011 }
2012
2013 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
2014 struct ac_image_args *args,
2015 const nir_tex_instr *instr)
2016 {
2017 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2018 LLVMValueRef coord = args->addr;
2019 LLVMValueRef half_texel[2];
2020 LLVMValueRef compare_cube_wa;
2021 LLVMValueRef result;
2022 int c;
2023 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2024
2025 //TODO Rect
2026 {
2027 struct ac_image_args txq_args = { 0 };
2028
2029 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2030 txq_args.opcode = ac_image_get_resinfo;
2031 txq_args.dmask = 0xf;
2032 txq_args.addr = ctx->i32zero;
2033 txq_args.resource = args->resource;
2034 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
2035
2036 for (c = 0; c < 2; c++) {
2037 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2038 LLVMConstInt(ctx->i32, c, false), "");
2039 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2040 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
2041 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2042 LLVMConstReal(ctx->f32, -0.5), "");
2043 }
2044 }
2045
2046 LLVMValueRef orig_coords = args->addr;
2047
2048 for (c = 0; c < 2; c++) {
2049 LLVMValueRef tmp;
2050 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2051 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2052 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2053 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2054 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2055 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2056 }
2057
2058
2059 /*
2060 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2061 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2062 * workaround by sampling using a scaled type and converting.
2063 * This is taken from amdgpu-pro shaders.
2064 */
2065 /* NOTE this produces some ugly code compared to amdgpu-pro,
2066 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2067 * and then reads them back. -pro generates two selects,
2068 * one s_cmp for the descriptor rewriting
2069 * one v_cmp for the coordinate and result changes.
2070 */
2071 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2072 LLVMValueRef tmp, tmp2;
2073
2074 /* workaround 8/8/8/8 uint/sint cube gather bug */
2075 /* first detect it then change to a scaled read and f2i */
2076 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
2077 tmp2 = tmp;
2078
2079 /* extract the DATA_FORMAT */
2080 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
2081 LLVMConstInt(ctx->i32, 6, false), false);
2082
2083 /* is the DATA_FORMAT == 8_8_8_8 */
2084 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2085
2086 if (stype == GLSL_TYPE_UINT)
2087 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2088 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2089 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2090 else
2091 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2092 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2093 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2094
2095 /* replace the NUM FORMAT in the descriptor */
2096 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2097 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2098
2099 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
2100
2101 /* don't modify the coordinates for this case */
2102 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2103 }
2104 args->addr = coord;
2105 result = ac_build_image_opcode(&ctx->ac, args);
2106
2107 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2108 LLVMValueRef tmp, tmp2;
2109
2110 /* if the cube workaround is in place, f2i the result. */
2111 for (c = 0; c < 4; c++) {
2112 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2113 if (stype == GLSL_TYPE_UINT)
2114 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2115 else
2116 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2117 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2118 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2119 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2120 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2121 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2122 }
2123 }
2124 return result;
2125 }
2126
2127 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
2128 const nir_tex_instr *instr,
2129 bool lod_is_zero,
2130 struct ac_image_args *args)
2131 {
2132 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2133 return ac_build_buffer_load_format(&ctx->ac,
2134 args->resource,
2135 args->addr,
2136 LLVMConstInt(ctx->i32, 0, false),
2137 true);
2138 }
2139
2140 args->opcode = ac_image_sample;
2141 args->compare = instr->is_shadow;
2142
2143 switch (instr->op) {
2144 case nir_texop_txf:
2145 case nir_texop_txf_ms:
2146 case nir_texop_samples_identical:
2147 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2148 args->compare = false;
2149 args->offset = false;
2150 break;
2151 case nir_texop_txb:
2152 args->bias = true;
2153 break;
2154 case nir_texop_txl:
2155 if (lod_is_zero)
2156 args->level_zero = true;
2157 else
2158 args->lod = true;
2159 break;
2160 case nir_texop_txs:
2161 case nir_texop_query_levels:
2162 args->opcode = ac_image_get_resinfo;
2163 break;
2164 case nir_texop_tex:
2165 if (ctx->stage != MESA_SHADER_FRAGMENT)
2166 args->level_zero = true;
2167 break;
2168 case nir_texop_txd:
2169 args->deriv = true;
2170 break;
2171 case nir_texop_tg4:
2172 args->opcode = ac_image_gather4;
2173 args->level_zero = true;
2174 break;
2175 case nir_texop_lod:
2176 args->opcode = ac_image_get_lod;
2177 args->compare = false;
2178 args->offset = false;
2179 break;
2180 default:
2181 break;
2182 }
2183
2184 if (instr->op == nir_texop_tg4) {
2185 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2186 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2187 return radv_lower_gather4_integer(ctx, args, instr);
2188 }
2189 }
2190 return ac_build_image_opcode(&ctx->ac, args);
2191 }
2192
2193 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2194 nir_intrinsic_instr *instr)
2195 {
2196 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2197 unsigned desc_set = nir_intrinsic_desc_set(instr);
2198 unsigned binding = nir_intrinsic_binding(instr);
2199 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2200 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2201 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2202 unsigned base_offset = layout->binding[binding].offset;
2203 LLVMValueRef offset, stride;
2204
2205 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2206 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2207 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2208 layout->binding[binding].dynamic_offset_offset;
2209 desc_ptr = ctx->push_constants;
2210 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2211 stride = LLVMConstInt(ctx->i32, 16, false);
2212 } else
2213 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2214
2215 offset = LLVMConstInt(ctx->i32, base_offset, false);
2216 index = LLVMBuildMul(ctx->builder, index, stride, "");
2217 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2218
2219 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2220 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2221 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2222
2223 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2224 }
2225
2226 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2227 nir_intrinsic_instr *instr)
2228 {
2229 LLVMValueRef ptr, addr;
2230
2231 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2232 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2233
2234 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2235 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2236
2237 return LLVMBuildLoad(ctx->builder, ptr, "");
2238 }
2239
2240 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2241 const nir_intrinsic_instr *instr)
2242 {
2243 LLVMValueRef desc = get_src(ctx->nir, instr->src[0]);
2244
2245 return get_buffer_size(ctx, desc, false);
2246 }
2247 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2248 nir_intrinsic_instr *instr)
2249 {
2250 const char *store_name;
2251 LLVMValueRef src_data = get_src(ctx->nir, instr->src[0]);
2252 LLVMTypeRef data_type = ctx->f32;
2253 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2254 int components_32bit = elem_size_mult * instr->num_components;
2255 unsigned writemask = nir_intrinsic_write_mask(instr);
2256 LLVMValueRef base_data, base_offset;
2257 LLVMValueRef params[6];
2258
2259 if (ctx->stage == MESA_SHADER_FRAGMENT)
2260 ctx->shader_info->fs.writes_memory = true;
2261
2262 params[1] = get_src(ctx->nir, instr->src[1]);
2263 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2264 params[4] = ctx->i1false; /* glc */
2265 params[5] = ctx->i1false; /* slc */
2266
2267 if (components_32bit > 1)
2268 data_type = LLVMVectorType(ctx->f32, components_32bit);
2269
2270 base_data = to_float(&ctx->ac, src_data);
2271 base_data = trim_vector(ctx, base_data, instr->num_components);
2272 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2273 data_type, "");
2274 base_offset = get_src(ctx->nir, instr->src[2]); /* voffset */
2275 while (writemask) {
2276 int start, count;
2277 LLVMValueRef data;
2278 LLVMValueRef offset;
2279 LLVMValueRef tmp;
2280 u_bit_scan_consecutive_range(&writemask, &start, &count);
2281
2282 /* Due to an LLVM limitation, split 3-element writes
2283 * into a 2-element and a 1-element write. */
2284 if (count == 3) {
2285 writemask |= 1 << (start + 2);
2286 count = 2;
2287 }
2288
2289 start *= elem_size_mult;
2290 count *= elem_size_mult;
2291
2292 if (count > 4) {
2293 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2294 count = 4;
2295 }
2296
2297 if (count == 4) {
2298 store_name = "llvm.amdgcn.buffer.store.v4f32";
2299 data = base_data;
2300 } else if (count == 2) {
2301 tmp = LLVMBuildExtractElement(ctx->builder,
2302 base_data, LLVMConstInt(ctx->i32, start, false), "");
2303 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2304 ctx->i32zero, "");
2305
2306 tmp = LLVMBuildExtractElement(ctx->builder,
2307 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2308 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2309 ctx->i32one, "");
2310 store_name = "llvm.amdgcn.buffer.store.v2f32";
2311
2312 } else {
2313 assert(count == 1);
2314 if (get_llvm_num_components(base_data) > 1)
2315 data = LLVMBuildExtractElement(ctx->builder, base_data,
2316 LLVMConstInt(ctx->i32, start, false), "");
2317 else
2318 data = base_data;
2319 store_name = "llvm.amdgcn.buffer.store.f32";
2320 }
2321
2322 offset = base_offset;
2323 if (start != 0) {
2324 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2325 }
2326 params[0] = data;
2327 params[3] = offset;
2328 ac_build_intrinsic(&ctx->ac, store_name,
2329 ctx->voidt, params, 6, 0);
2330 }
2331 }
2332
2333 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2334 const nir_intrinsic_instr *instr)
2335 {
2336 const char *name;
2337 LLVMValueRef params[6];
2338 int arg_count = 0;
2339 if (ctx->stage == MESA_SHADER_FRAGMENT)
2340 ctx->shader_info->fs.writes_memory = true;
2341
2342 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2343 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx->nir, instr->src[3]), 0);
2344 }
2345 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx->nir, instr->src[2]), 0);
2346 params[arg_count++] = get_src(ctx->nir, instr->src[0]);
2347 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2348 params[arg_count++] = get_src(ctx->nir, instr->src[1]); /* voffset */
2349 params[arg_count++] = ctx->i1false; /* slc */
2350
2351 switch (instr->intrinsic) {
2352 case nir_intrinsic_ssbo_atomic_add:
2353 name = "llvm.amdgcn.buffer.atomic.add";
2354 break;
2355 case nir_intrinsic_ssbo_atomic_imin:
2356 name = "llvm.amdgcn.buffer.atomic.smin";
2357 break;
2358 case nir_intrinsic_ssbo_atomic_umin:
2359 name = "llvm.amdgcn.buffer.atomic.umin";
2360 break;
2361 case nir_intrinsic_ssbo_atomic_imax:
2362 name = "llvm.amdgcn.buffer.atomic.smax";
2363 break;
2364 case nir_intrinsic_ssbo_atomic_umax:
2365 name = "llvm.amdgcn.buffer.atomic.umax";
2366 break;
2367 case nir_intrinsic_ssbo_atomic_and:
2368 name = "llvm.amdgcn.buffer.atomic.and";
2369 break;
2370 case nir_intrinsic_ssbo_atomic_or:
2371 name = "llvm.amdgcn.buffer.atomic.or";
2372 break;
2373 case nir_intrinsic_ssbo_atomic_xor:
2374 name = "llvm.amdgcn.buffer.atomic.xor";
2375 break;
2376 case nir_intrinsic_ssbo_atomic_exchange:
2377 name = "llvm.amdgcn.buffer.atomic.swap";
2378 break;
2379 case nir_intrinsic_ssbo_atomic_comp_swap:
2380 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2381 break;
2382 default:
2383 abort();
2384 }
2385
2386 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2387 }
2388
2389 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2390 const nir_intrinsic_instr *instr)
2391 {
2392 LLVMValueRef results[2];
2393 int load_components;
2394 int num_components = instr->num_components;
2395 if (instr->dest.ssa.bit_size == 64)
2396 num_components *= 2;
2397
2398 for (int i = 0; i < num_components; i += load_components) {
2399 load_components = MIN2(num_components - i, 4);
2400 const char *load_name;
2401 LLVMTypeRef data_type = ctx->f32;
2402 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2403 offset = LLVMBuildAdd(ctx->builder, get_src(ctx->nir, instr->src[1]), offset, "");
2404
2405 if (load_components == 3)
2406 data_type = LLVMVectorType(ctx->f32, 4);
2407 else if (load_components > 1)
2408 data_type = LLVMVectorType(ctx->f32, load_components);
2409
2410 if (load_components >= 3)
2411 load_name = "llvm.amdgcn.buffer.load.v4f32";
2412 else if (load_components == 2)
2413 load_name = "llvm.amdgcn.buffer.load.v2f32";
2414 else if (load_components == 1)
2415 load_name = "llvm.amdgcn.buffer.load.f32";
2416 else
2417 unreachable("unhandled number of components");
2418
2419 LLVMValueRef params[] = {
2420 get_src(ctx->nir, instr->src[0]),
2421 LLVMConstInt(ctx->i32, 0, false),
2422 offset,
2423 ctx->i1false,
2424 ctx->i1false,
2425 };
2426
2427 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2428
2429 }
2430
2431 LLVMValueRef ret = results[0];
2432 if (num_components > 4 || num_components == 3) {
2433 LLVMValueRef masks[] = {
2434 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2435 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2436 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2437 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2438 };
2439
2440 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2441 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2442 results[num_components > 4 ? 1 : 0], swizzle, "");
2443 }
2444
2445 return LLVMBuildBitCast(ctx->builder, ret,
2446 get_def_type(ctx->nir, &instr->dest.ssa), "");
2447 }
2448
2449 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2450 const nir_intrinsic_instr *instr)
2451 {
2452 LLVMValueRef results[8], ret;
2453 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2454 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2455 int num_components = instr->num_components;
2456
2457 if (ctx->abi->load_ubo)
2458 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2459
2460 if (instr->dest.ssa.bit_size == 64)
2461 num_components *= 2;
2462
2463 for (unsigned i = 0; i < num_components; ++i) {
2464 LLVMValueRef params[] = {
2465 rsrc,
2466 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2467 offset, "")
2468 };
2469 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2470 params, 2,
2471 AC_FUNC_ATTR_READNONE |
2472 AC_FUNC_ATTR_LEGACY);
2473 }
2474
2475
2476 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2477 return LLVMBuildBitCast(ctx->ac.builder, ret,
2478 get_def_type(ctx, &instr->dest.ssa), "");
2479 }
2480
2481 static void
2482 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2483 bool vs_in, unsigned *vertex_index_out,
2484 LLVMValueRef *vertex_index_ref,
2485 unsigned *const_out, LLVMValueRef *indir_out)
2486 {
2487 unsigned const_offset = 0;
2488 nir_deref *tail = &deref->deref;
2489 LLVMValueRef offset = NULL;
2490
2491 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2492 tail = tail->child;
2493 nir_deref_array *deref_array = nir_deref_as_array(tail);
2494 if (vertex_index_out)
2495 *vertex_index_out = deref_array->base_offset;
2496
2497 if (vertex_index_ref) {
2498 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2499 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2500 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2501 }
2502 *vertex_index_ref = vtx;
2503 }
2504 }
2505
2506 if (deref->var->data.compact) {
2507 assert(tail->child->deref_type == nir_deref_type_array);
2508 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2509 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2510 /* We always lower indirect dereferences for "compact" array vars. */
2511 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2512
2513 const_offset = deref_array->base_offset;
2514 goto out;
2515 }
2516
2517 while (tail->child != NULL) {
2518 const struct glsl_type *parent_type = tail->type;
2519 tail = tail->child;
2520
2521 if (tail->deref_type == nir_deref_type_array) {
2522 nir_deref_array *deref_array = nir_deref_as_array(tail);
2523 LLVMValueRef index, stride, local_offset;
2524 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2525
2526 const_offset += size * deref_array->base_offset;
2527 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2528 continue;
2529
2530 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2531 index = get_src(ctx, deref_array->indirect);
2532 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2533 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2534
2535 if (offset)
2536 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2537 else
2538 offset = local_offset;
2539 } else if (tail->deref_type == nir_deref_type_struct) {
2540 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2541
2542 for (unsigned i = 0; i < deref_struct->index; i++) {
2543 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2544 const_offset += glsl_count_attribute_slots(ft, vs_in);
2545 }
2546 } else
2547 unreachable("unsupported deref type");
2548
2549 }
2550 out:
2551 if (const_offset && offset)
2552 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2553 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2554 "");
2555
2556 *const_out = const_offset;
2557 *indir_out = offset;
2558 }
2559
2560 static LLVMValueRef
2561 lds_load(struct nir_to_llvm_context *ctx,
2562 LLVMValueRef dw_addr)
2563 {
2564 LLVMValueRef value;
2565 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2566 return value;
2567 }
2568
2569 static void
2570 lds_store(struct nir_to_llvm_context *ctx,
2571 LLVMValueRef dw_addr, LLVMValueRef value)
2572 {
2573 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2574 ac_build_indexed_store(&ctx->ac, ctx->lds,
2575 dw_addr, value);
2576 }
2577
2578 /* The offchip buffer layout for TCS->TES is
2579 *
2580 * - attribute 0 of patch 0 vertex 0
2581 * - attribute 0 of patch 0 vertex 1
2582 * - attribute 0 of patch 0 vertex 2
2583 * ...
2584 * - attribute 0 of patch 1 vertex 0
2585 * - attribute 0 of patch 1 vertex 1
2586 * ...
2587 * - attribute 1 of patch 0 vertex 0
2588 * - attribute 1 of patch 0 vertex 1
2589 * ...
2590 * - per patch attribute 0 of patch 0
2591 * - per patch attribute 0 of patch 1
2592 * ...
2593 *
2594 * Note that every attribute has 4 components.
2595 */
2596 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2597 LLVMValueRef vertex_index,
2598 LLVMValueRef param_index)
2599 {
2600 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2601 LLVMValueRef param_stride, constant16;
2602 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2603
2604 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2605 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2606 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2607 num_patches, "");
2608
2609 constant16 = LLVMConstInt(ctx->i32, 16, false);
2610 if (vertex_index) {
2611 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2612 vertices_per_patch, "");
2613
2614 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2615 vertex_index, "");
2616
2617 param_stride = total_vertices;
2618 } else {
2619 base_addr = rel_patch_id;
2620 param_stride = num_patches;
2621 }
2622
2623 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2624 LLVMBuildMul(ctx->builder, param_index,
2625 param_stride, ""), "");
2626
2627 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2628
2629 if (!vertex_index) {
2630 LLVMValueRef patch_data_offset =
2631 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2632
2633 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2634 patch_data_offset, "");
2635 }
2636 return base_addr;
2637 }
2638
2639 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2640 unsigned param,
2641 unsigned const_index,
2642 bool is_compact,
2643 LLVMValueRef vertex_index,
2644 LLVMValueRef indir_index)
2645 {
2646 LLVMValueRef param_index;
2647
2648 if (indir_index)
2649 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2650 indir_index, "");
2651 else {
2652 if (const_index && !is_compact)
2653 param += const_index;
2654 param_index = LLVMConstInt(ctx->i32, param, false);
2655 }
2656 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2657 }
2658
2659 static void
2660 mark_tess_output(struct nir_to_llvm_context *ctx,
2661 bool is_patch, uint32_t param)
2662
2663 {
2664 if (is_patch) {
2665 ctx->tess_patch_outputs_written |= (1ull << param);
2666 } else
2667 ctx->tess_outputs_written |= (1ull << param);
2668 }
2669
2670 static LLVMValueRef
2671 get_dw_address(struct nir_to_llvm_context *ctx,
2672 LLVMValueRef dw_addr,
2673 unsigned param,
2674 unsigned const_index,
2675 bool compact_const_index,
2676 LLVMValueRef vertex_index,
2677 LLVMValueRef stride,
2678 LLVMValueRef indir_index)
2679
2680 {
2681
2682 if (vertex_index) {
2683 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2684 LLVMBuildMul(ctx->builder,
2685 vertex_index,
2686 stride, ""), "");
2687 }
2688
2689 if (indir_index)
2690 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2691 LLVMBuildMul(ctx->builder, indir_index,
2692 LLVMConstInt(ctx->i32, 4, false), ""), "");
2693 else if (const_index && !compact_const_index)
2694 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2695 LLVMConstInt(ctx->i32, const_index, false), "");
2696
2697 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2698 LLVMConstInt(ctx->i32, param * 4, false), "");
2699
2700 if (const_index && compact_const_index)
2701 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2702 LLVMConstInt(ctx->i32, const_index, false), "");
2703 return dw_addr;
2704 }
2705
2706 static LLVMValueRef
2707 load_tcs_input(struct nir_to_llvm_context *ctx,
2708 nir_intrinsic_instr *instr)
2709 {
2710 LLVMValueRef dw_addr, stride;
2711 unsigned const_index;
2712 LLVMValueRef vertex_index;
2713 LLVMValueRef indir_index;
2714 unsigned param;
2715 LLVMValueRef value[4], result;
2716 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2717 const bool is_compact = instr->variables[0]->var->data.compact;
2718 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2719 get_deref_offset(ctx->nir, instr->variables[0],
2720 false, NULL, per_vertex ? &vertex_index : NULL,
2721 &const_index, &indir_index);
2722
2723 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2724 dw_addr = get_tcs_in_current_patch_offset(ctx);
2725 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2726 indir_index);
2727
2728 for (unsigned i = 0; i < instr->num_components; i++) {
2729 value[i] = lds_load(ctx, dw_addr);
2730 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2731 ctx->i32one, "");
2732 }
2733 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2734 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2735 return result;
2736 }
2737
2738 static LLVMValueRef
2739 load_tcs_output(struct nir_to_llvm_context *ctx,
2740 nir_intrinsic_instr *instr)
2741 {
2742 LLVMValueRef dw_addr, stride;
2743 LLVMValueRef value[4], result;
2744 LLVMValueRef vertex_index = NULL;
2745 LLVMValueRef indir_index = NULL;
2746 unsigned const_index = 0;
2747 unsigned param;
2748 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2749 const bool is_compact = instr->variables[0]->var->data.compact;
2750 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2751 get_deref_offset(ctx->nir, instr->variables[0],
2752 false, NULL, per_vertex ? &vertex_index : NULL,
2753 &const_index, &indir_index);
2754
2755 if (!instr->variables[0]->var->data.patch) {
2756 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2757 dw_addr = get_tcs_out_current_patch_offset(ctx);
2758 } else {
2759 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2760 }
2761
2762 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2763 indir_index);
2764
2765 for (unsigned i = 0; i < instr->num_components; i++) {
2766 value[i] = lds_load(ctx, dw_addr);
2767 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2768 ctx->i32one, "");
2769 }
2770 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2771 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2772 return result;
2773 }
2774
2775 static void
2776 store_tcs_output(struct nir_to_llvm_context *ctx,
2777 nir_intrinsic_instr *instr,
2778 LLVMValueRef src,
2779 unsigned writemask)
2780 {
2781 LLVMValueRef stride, dw_addr;
2782 LLVMValueRef buf_addr = NULL;
2783 LLVMValueRef vertex_index = NULL;
2784 LLVMValueRef indir_index = NULL;
2785 unsigned const_index = 0;
2786 unsigned param;
2787 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2788 const bool is_compact = instr->variables[0]->var->data.compact;
2789
2790 get_deref_offset(ctx->nir, instr->variables[0],
2791 false, NULL, per_vertex ? &vertex_index : NULL,
2792 &const_index, &indir_index);
2793
2794 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2795 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2796 is_compact && const_index > 3) {
2797 const_index -= 3;
2798 param++;
2799 }
2800
2801 if (!instr->variables[0]->var->data.patch) {
2802 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2803 dw_addr = get_tcs_out_current_patch_offset(ctx);
2804 } else {
2805 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2806 }
2807
2808 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2809
2810 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2811 indir_index);
2812 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2813 vertex_index, indir_index);
2814
2815 unsigned base = is_compact ? const_index : 0;
2816 for (unsigned chan = 0; chan < 8; chan++) {
2817 bool is_tess_factor = false;
2818 if (!(writemask & (1 << chan)))
2819 continue;
2820 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan);
2821
2822 lds_store(ctx, dw_addr, value);
2823
2824 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2825 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2826 is_tess_factor = true;
2827
2828 if (!is_tess_factor && writemask != 0xF)
2829 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2830 buf_addr, ctx->oc_lds,
2831 4 * (base + chan), 1, 0, true, false);
2832
2833 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2834 ctx->i32one, "");
2835 }
2836
2837 if (writemask == 0xF) {
2838 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2839 buf_addr, ctx->oc_lds,
2840 (base * 4), 1, 0, true, false);
2841 }
2842 }
2843
2844 static LLVMValueRef
2845 load_tes_input(struct nir_to_llvm_context *ctx,
2846 const nir_intrinsic_instr *instr)
2847 {
2848 LLVMValueRef buf_addr;
2849 LLVMValueRef result;
2850 LLVMValueRef vertex_index = NULL;
2851 LLVMValueRef indir_index = NULL;
2852 unsigned const_index = 0;
2853 unsigned param;
2854 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2855 const bool is_compact = instr->variables[0]->var->data.compact;
2856
2857 get_deref_offset(ctx->nir, instr->variables[0],
2858 false, NULL, per_vertex ? &vertex_index : NULL,
2859 &const_index, &indir_index);
2860 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2861 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2862 is_compact && const_index > 3) {
2863 const_index -= 3;
2864 param++;
2865 }
2866 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2867 is_compact, vertex_index, indir_index);
2868
2869 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2870 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2871 result = trim_vector(ctx, result, instr->num_components);
2872 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2873 return result;
2874 }
2875
2876 static LLVMValueRef
2877 load_gs_input(struct nir_to_llvm_context *ctx,
2878 nir_intrinsic_instr *instr)
2879 {
2880 LLVMValueRef indir_index, vtx_offset;
2881 unsigned const_index;
2882 LLVMValueRef args[9];
2883 unsigned param, vtx_offset_param;
2884 LLVMValueRef value[4], result;
2885 unsigned vertex_index;
2886 get_deref_offset(ctx->nir, instr->variables[0],
2887 false, &vertex_index, NULL,
2888 &const_index, &indir_index);
2889 vtx_offset_param = vertex_index;
2890 assert(vtx_offset_param < 6);
2891 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2892 LLVMConstInt(ctx->i32, 4, false), "");
2893
2894 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2895 for (unsigned i = 0; i < instr->num_components; i++) {
2896
2897 args[0] = ctx->esgs_ring;
2898 args[1] = vtx_offset;
2899 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2900 args[3] = ctx->i32zero;
2901 args[4] = ctx->i32one; /* OFFEN */
2902 args[5] = ctx->i32zero; /* IDXEN */
2903 args[6] = ctx->i32one; /* GLC */
2904 args[7] = ctx->i32zero; /* SLC */
2905 args[8] = ctx->i32zero; /* TFE */
2906
2907 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2908 ctx->i32, args, 9,
2909 AC_FUNC_ATTR_READONLY |
2910 AC_FUNC_ATTR_LEGACY);
2911 }
2912 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2913
2914 return result;
2915 }
2916
2917 static LLVMValueRef
2918 build_gep_for_deref(struct ac_nir_context *ctx,
2919 nir_deref_var *deref)
2920 {
2921 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2922 assert(entry->data);
2923 LLVMValueRef val = entry->data;
2924 nir_deref *tail = deref->deref.child;
2925 while (tail != NULL) {
2926 LLVMValueRef offset;
2927 switch (tail->deref_type) {
2928 case nir_deref_type_array: {
2929 nir_deref_array *array = nir_deref_as_array(tail);
2930 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2931 if (array->deref_array_type ==
2932 nir_deref_array_type_indirect) {
2933 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2934 get_src(ctx,
2935 array->indirect),
2936 "");
2937 }
2938 break;
2939 }
2940 case nir_deref_type_struct: {
2941 nir_deref_struct *deref_struct =
2942 nir_deref_as_struct(tail);
2943 offset = LLVMConstInt(ctx->ac.i32,
2944 deref_struct->index, 0);
2945 break;
2946 }
2947 default:
2948 unreachable("bad deref type");
2949 }
2950 val = ac_build_gep0(&ctx->ac, val, offset);
2951 tail = tail->child;
2952 }
2953 return val;
2954 }
2955
2956 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
2957 nir_intrinsic_instr *instr)
2958 {
2959 LLVMValueRef values[8];
2960 int idx = instr->variables[0]->var->data.driver_location;
2961 int ve = instr->dest.ssa.num_components;
2962 LLVMValueRef indir_index;
2963 LLVMValueRef ret;
2964 unsigned const_index;
2965 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2966 instr->variables[0]->var->data.mode == nir_var_shader_in;
2967 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2968 &const_index, &indir_index);
2969
2970 if (instr->dest.ssa.bit_size == 64)
2971 ve *= 2;
2972
2973 switch (instr->variables[0]->var->data.mode) {
2974 case nir_var_shader_in:
2975 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2976 return load_tcs_input(ctx->nctx, instr);
2977 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2978 return load_tes_input(ctx->nctx, instr);
2979 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2980 return load_gs_input(ctx->nctx, instr);
2981 }
2982 for (unsigned chan = 0; chan < ve; chan++) {
2983 if (indir_index) {
2984 unsigned count = glsl_count_attribute_slots(
2985 instr->variables[0]->var->type,
2986 ctx->stage == MESA_SHADER_VERTEX);
2987 count -= chan / 4;
2988 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2989 &ctx->ac, ctx->abi->inputs + idx + chan, count,
2990 4, false);
2991
2992 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
2993 tmp_vec,
2994 indir_index, "");
2995 } else
2996 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
2997 }
2998 break;
2999 case nir_var_local:
3000 for (unsigned chan = 0; chan < ve; chan++) {
3001 if (indir_index) {
3002 unsigned count = glsl_count_attribute_slots(
3003 instr->variables[0]->var->type, false);
3004 count -= chan / 4;
3005 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3006 &ctx->ac, ctx->locals + idx + chan, count,
3007 4, true);
3008
3009 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3010 tmp_vec,
3011 indir_index, "");
3012 } else {
3013 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3014 }
3015 }
3016 break;
3017 case nir_var_shared: {
3018 LLVMValueRef address = build_gep_for_deref(ctx,
3019 instr->variables[0]);
3020 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3021 return LLVMBuildBitCast(ctx->ac.builder, val,
3022 get_def_type(ctx, &instr->dest.ssa),
3023 "");
3024 }
3025 case nir_var_shader_out:
3026 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3027 return load_tcs_output(ctx->nctx, instr);
3028 for (unsigned chan = 0; chan < ve; chan++) {
3029 if (indir_index) {
3030 unsigned count = glsl_count_attribute_slots(
3031 instr->variables[0]->var->type, false);
3032 count -= chan / 4;
3033 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3034 &ctx->ac, ctx->outputs + idx + chan, count,
3035 4, true);
3036
3037 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3038 tmp_vec,
3039 indir_index, "");
3040 } else {
3041 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3042 ctx->outputs[idx + chan + const_index * 4],
3043 "");
3044 }
3045 }
3046 break;
3047 default:
3048 unreachable("unhandle variable mode");
3049 }
3050 ret = ac_build_gather_values(&ctx->ac, values, ve);
3051 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3052 }
3053
3054 static void
3055 visit_store_var(struct ac_nir_context *ctx,
3056 nir_intrinsic_instr *instr)
3057 {
3058 LLVMValueRef temp_ptr, value;
3059 int idx = instr->variables[0]->var->data.driver_location;
3060 LLVMValueRef src = to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3061 int writemask = instr->const_index[0];
3062 LLVMValueRef indir_index;
3063 unsigned const_index;
3064 get_deref_offset(ctx, instr->variables[0], false,
3065 NULL, NULL, &const_index, &indir_index);
3066
3067 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3068 int old_writemask = writemask;
3069
3070 src = LLVMBuildBitCast(ctx->ac.builder, src,
3071 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3072 "");
3073
3074 writemask = 0;
3075 for (unsigned chan = 0; chan < 4; chan++) {
3076 if (old_writemask & (1 << chan))
3077 writemask |= 3u << (2 * chan);
3078 }
3079 }
3080
3081 switch (instr->variables[0]->var->data.mode) {
3082 case nir_var_shader_out:
3083
3084 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3085 store_tcs_output(ctx->nctx, instr, src, writemask);
3086 return;
3087 }
3088
3089 for (unsigned chan = 0; chan < 8; chan++) {
3090 int stride = 4;
3091 if (!(writemask & (1 << chan)))
3092 continue;
3093
3094 value = llvm_extract_elem(&ctx->ac, src, chan);
3095
3096 if (instr->variables[0]->var->data.compact)
3097 stride = 1;
3098 if (indir_index) {
3099 unsigned count = glsl_count_attribute_slots(
3100 instr->variables[0]->var->type, false);
3101 count -= chan / 4;
3102 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3103 &ctx->ac, ctx->outputs + idx + chan, count,
3104 stride, true);
3105
3106 if (get_llvm_num_components(tmp_vec) > 1) {
3107 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3108 value, indir_index, "");
3109 } else
3110 tmp_vec = value;
3111 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3112 count, stride, tmp_vec);
3113
3114 } else {
3115 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3116
3117 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3118 }
3119 }
3120 break;
3121 case nir_var_local:
3122 for (unsigned chan = 0; chan < 8; chan++) {
3123 if (!(writemask & (1 << chan)))
3124 continue;
3125
3126 value = llvm_extract_elem(&ctx->ac, src, chan);
3127 if (indir_index) {
3128 unsigned count = glsl_count_attribute_slots(
3129 instr->variables[0]->var->type, false);
3130 count -= chan / 4;
3131 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3132 &ctx->ac, ctx->locals + idx + chan, count,
3133 4, true);
3134
3135 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3136 value, indir_index, "");
3137 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3138 count, 4, tmp_vec);
3139 } else {
3140 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3141
3142 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3143 }
3144 }
3145 break;
3146 case nir_var_shared: {
3147 int writemask = instr->const_index[0];
3148 LLVMValueRef address = build_gep_for_deref(ctx,
3149 instr->variables[0]);
3150 LLVMValueRef val = get_src(ctx, instr->src[0]);
3151 unsigned components =
3152 glsl_get_vector_elements(
3153 nir_deref_tail(&instr->variables[0]->deref)->type);
3154 if (writemask == (1 << components) - 1) {
3155 val = LLVMBuildBitCast(
3156 ctx->ac.builder, val,
3157 LLVMGetElementType(LLVMTypeOf(address)), "");
3158 LLVMBuildStore(ctx->ac.builder, val, address);
3159 } else {
3160 for (unsigned chan = 0; chan < 4; chan++) {
3161 if (!(writemask & (1 << chan)))
3162 continue;
3163 LLVMValueRef ptr =
3164 LLVMBuildStructGEP(ctx->ac.builder,
3165 address, chan, "");
3166 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3167 chan);
3168 src = LLVMBuildBitCast(
3169 ctx->ac.builder, src,
3170 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3171 LLVMBuildStore(ctx->ac.builder, src, ptr);
3172 }
3173 }
3174 break;
3175 }
3176 default:
3177 break;
3178 }
3179 }
3180
3181 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3182 {
3183 switch (dim) {
3184 case GLSL_SAMPLER_DIM_BUF:
3185 return 1;
3186 case GLSL_SAMPLER_DIM_1D:
3187 return array ? 2 : 1;
3188 case GLSL_SAMPLER_DIM_2D:
3189 return array ? 3 : 2;
3190 case GLSL_SAMPLER_DIM_MS:
3191 return array ? 4 : 3;
3192 case GLSL_SAMPLER_DIM_3D:
3193 case GLSL_SAMPLER_DIM_CUBE:
3194 return 3;
3195 case GLSL_SAMPLER_DIM_RECT:
3196 case GLSL_SAMPLER_DIM_SUBPASS:
3197 return 2;
3198 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3199 return 3;
3200 default:
3201 break;
3202 }
3203 return 0;
3204 }
3205
3206
3207
3208 /* Adjust the sample index according to FMASK.
3209 *
3210 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3211 * which is the identity mapping. Each nibble says which physical sample
3212 * should be fetched to get that sample.
3213 *
3214 * For example, 0x11111100 means there are only 2 samples stored and
3215 * the second sample covers 3/4 of the pixel. When reading samples 0
3216 * and 1, return physical sample 0 (determined by the first two 0s
3217 * in FMASK), otherwise return physical sample 1.
3218 *
3219 * The sample index should be adjusted as follows:
3220 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3221 */
3222 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
3223 LLVMValueRef coord_x, LLVMValueRef coord_y,
3224 LLVMValueRef coord_z,
3225 LLVMValueRef sample_index,
3226 LLVMValueRef fmask_desc_ptr)
3227 {
3228 LLVMValueRef fmask_load_address[4];
3229 LLVMValueRef res;
3230
3231 fmask_load_address[0] = coord_x;
3232 fmask_load_address[1] = coord_y;
3233 if (coord_z) {
3234 fmask_load_address[2] = coord_z;
3235 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3236 }
3237
3238 struct ac_image_args args = {0};
3239
3240 args.opcode = ac_image_load;
3241 args.da = coord_z ? true : false;
3242 args.resource = fmask_desc_ptr;
3243 args.dmask = 0xf;
3244 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
3245
3246 res = ac_build_image_opcode(&ctx->ac, &args);
3247
3248 res = to_integer(&ctx->ac, res);
3249 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3250 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3251
3252 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3253 res,
3254 ctx->i32zero, "");
3255
3256 LLVMValueRef sample_index4 =
3257 LLVMBuildMul(ctx->builder, sample_index, four, "");
3258 LLVMValueRef shifted_fmask =
3259 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3260 LLVMValueRef final_sample =
3261 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3262
3263 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3264 * resource descriptor is 0 (invalid),
3265 */
3266 LLVMValueRef fmask_desc =
3267 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3268 ctx->v8i32, "");
3269
3270 LLVMValueRef fmask_word1 =
3271 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3272 ctx->i32one, "");
3273
3274 LLVMValueRef word1_is_nonzero =
3275 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3276 fmask_word1, ctx->i32zero, "");
3277
3278 /* Replace the MSAA sample index. */
3279 sample_index =
3280 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3281 final_sample, sample_index, "");
3282 return sample_index;
3283 }
3284
3285 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
3286 const nir_intrinsic_instr *instr)
3287 {
3288 const struct glsl_type *type = instr->variables[0]->var->type;
3289 if(instr->variables[0]->deref.child)
3290 type = instr->variables[0]->deref.child->type;
3291
3292 LLVMValueRef src0 = get_src(ctx->nir, instr->src[0]);
3293 LLVMValueRef coords[4];
3294 LLVMValueRef masks[] = {
3295 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
3296 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
3297 };
3298 LLVMValueRef res;
3299 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx->nir, instr->src[1]), 0);
3300
3301 int count;
3302 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3303 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3304 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3305 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3306 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3307
3308 count = image_type_to_components_count(dim,
3309 glsl_sampler_type_is_array(type));
3310
3311 if (is_ms) {
3312 LLVMValueRef fmask_load_address[3];
3313 int chan;
3314
3315 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3316 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
3317 if (glsl_sampler_type_is_array(type))
3318 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
3319 else
3320 fmask_load_address[2] = NULL;
3321 if (add_frag_pos) {
3322 for (chan = 0; chan < 2; ++chan)
3323 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3324 }
3325 sample_index = adjust_sample_index_using_fmask(ctx,
3326 fmask_load_address[0],
3327 fmask_load_address[1],
3328 fmask_load_address[2],
3329 sample_index,
3330 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
3331 }
3332 if (count == 1) {
3333 if (instr->src[0].ssa->num_components)
3334 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3335 else
3336 res = src0;
3337 } else {
3338 int chan;
3339 if (is_ms)
3340 count--;
3341 for (chan = 0; chan < count; ++chan) {
3342 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
3343 }
3344
3345 if (add_frag_pos) {
3346 for (chan = 0; chan < count; ++chan)
3347 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3348 }
3349 if (is_ms) {
3350 coords[count] = sample_index;
3351 count++;
3352 }
3353
3354 if (count == 3) {
3355 coords[3] = LLVMGetUndef(ctx->i32);
3356 count = 4;
3357 }
3358 res = ac_build_gather_values(&ctx->ac, coords, count);
3359 }
3360 return res;
3361 }
3362
3363 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
3364 const nir_intrinsic_instr *instr)
3365 {
3366 LLVMValueRef params[7];
3367 LLVMValueRef res;
3368 char intrinsic_name[64];
3369 const nir_variable *var = instr->variables[0]->var;
3370 const struct glsl_type *type = var->type;
3371 if(instr->variables[0]->deref.child)
3372 type = instr->variables[0]->deref.child->type;
3373
3374 type = glsl_without_array(type);
3375 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3376 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3377 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx->nir, instr->src[0]),
3378 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3379 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3380 params[3] = ctx->i1false; /* glc */
3381 params[4] = ctx->i1false; /* slc */
3382 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
3383 params, 5, 0);
3384
3385 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
3386 res = to_integer(&ctx->ac, res);
3387 } else {
3388 bool is_da = glsl_sampler_type_is_array(type) ||
3389 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3390 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3391 LLVMValueRef glc = ctx->i1false;
3392 LLVMValueRef slc = ctx->i1false;
3393
3394 params[0] = get_image_coords(ctx, instr);
3395 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3396 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3397 if (HAVE_LLVM <= 0x0309) {
3398 params[3] = ctx->i1false; /* r128 */
3399 params[4] = da;
3400 params[5] = glc;
3401 params[6] = slc;
3402 } else {
3403 LLVMValueRef lwe = ctx->i1false;
3404 params[3] = glc;
3405 params[4] = slc;
3406 params[5] = lwe;
3407 params[6] = da;
3408 }
3409
3410 ac_get_image_intr_name("llvm.amdgcn.image.load",
3411 ctx->v4f32, /* vdata */
3412 LLVMTypeOf(params[0]), /* coords */
3413 LLVMTypeOf(params[1]), /* rsrc */
3414 intrinsic_name, sizeof(intrinsic_name));
3415
3416 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
3417 params, 7, AC_FUNC_ATTR_READONLY);
3418 }
3419 return to_integer(&ctx->ac, res);
3420 }
3421
3422 static void visit_image_store(struct nir_to_llvm_context *ctx,
3423 nir_intrinsic_instr *instr)
3424 {
3425 LLVMValueRef params[8];
3426 char intrinsic_name[64];
3427 const nir_variable *var = instr->variables[0]->var;
3428 const struct glsl_type *type = glsl_without_array(var->type);
3429 LLVMValueRef glc = ctx->i1false;
3430 bool force_glc = ctx->options->chip_class == SI;
3431 if (force_glc)
3432 glc = ctx->i1true;
3433 if (ctx->stage == MESA_SHADER_FRAGMENT)
3434 ctx->shader_info->fs.writes_memory = true;
3435
3436 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3437 params[0] = to_float(&ctx->ac, get_src(ctx->nir, instr->src[2])); /* data */
3438 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3439 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx->nir, instr->src[0]),
3440 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3441 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3442 params[4] = glc; /* glc */
3443 params[5] = ctx->i1false; /* slc */
3444 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
3445 params, 6, 0);
3446 } else {
3447 bool is_da = glsl_sampler_type_is_array(type) ||
3448 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3449 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3450 LLVMValueRef slc = ctx->i1false;
3451
3452 params[0] = to_float(&ctx->ac, get_src(ctx->nir, instr->src[2]));
3453 params[1] = get_image_coords(ctx, instr); /* coords */
3454 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3455 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3456 if (HAVE_LLVM <= 0x0309) {
3457 params[4] = ctx->i1false; /* r128 */
3458 params[5] = da;
3459 params[6] = glc;
3460 params[7] = slc;
3461 } else {
3462 LLVMValueRef lwe = ctx->i1false;
3463 params[4] = glc;
3464 params[5] = slc;
3465 params[6] = lwe;
3466 params[7] = da;
3467 }
3468
3469 ac_get_image_intr_name("llvm.amdgcn.image.store",
3470 LLVMTypeOf(params[0]), /* vdata */
3471 LLVMTypeOf(params[1]), /* coords */
3472 LLVMTypeOf(params[2]), /* rsrc */
3473 intrinsic_name, sizeof(intrinsic_name));
3474
3475 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
3476 params, 8, 0);
3477 }
3478
3479 }
3480
3481 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
3482 const nir_intrinsic_instr *instr)
3483 {
3484 LLVMValueRef params[6];
3485 int param_count = 0;
3486 const nir_variable *var = instr->variables[0]->var;
3487
3488 const char *atomic_name;
3489 char intrinsic_name[41];
3490 const struct glsl_type *type = glsl_without_array(var->type);
3491 MAYBE_UNUSED int length;
3492
3493 if (ctx->stage == MESA_SHADER_FRAGMENT)
3494 ctx->shader_info->fs.writes_memory = true;
3495
3496 switch (instr->intrinsic) {
3497 case nir_intrinsic_image_atomic_add:
3498 atomic_name = "add";
3499 break;
3500 case nir_intrinsic_image_atomic_min:
3501 atomic_name = "smin";
3502 break;
3503 case nir_intrinsic_image_atomic_max:
3504 atomic_name = "smax";
3505 break;
3506 case nir_intrinsic_image_atomic_and:
3507 atomic_name = "and";
3508 break;
3509 case nir_intrinsic_image_atomic_or:
3510 atomic_name = "or";
3511 break;
3512 case nir_intrinsic_image_atomic_xor:
3513 atomic_name = "xor";
3514 break;
3515 case nir_intrinsic_image_atomic_exchange:
3516 atomic_name = "swap";
3517 break;
3518 case nir_intrinsic_image_atomic_comp_swap:
3519 atomic_name = "cmpswap";
3520 break;
3521 default:
3522 abort();
3523 }
3524
3525 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3526 params[param_count++] = get_src(ctx->nir, instr->src[3]);
3527 params[param_count++] = get_src(ctx->nir, instr->src[2]);
3528
3529 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3530 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3531 params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx->nir, instr->src[0]),
3532 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3533 params[param_count++] = ctx->i32zero; /* voffset */
3534 params[param_count++] = ctx->i1false; /* slc */
3535
3536 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3537 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3538 } else {
3539 char coords_type[8];
3540
3541 bool da = glsl_sampler_type_is_array(type) ||
3542 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3543
3544 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3545 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3546 params[param_count++] = ctx->i1false; /* r128 */
3547 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
3548 params[param_count++] = ctx->i1false; /* slc */
3549
3550 build_int_type_name(LLVMTypeOf(coords),
3551 coords_type, sizeof(coords_type));
3552
3553 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3554 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3555 }
3556
3557 assert(length < sizeof(intrinsic_name));
3558 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
3559 }
3560
3561 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
3562 const nir_intrinsic_instr *instr)
3563 {
3564 LLVMValueRef res;
3565 const nir_variable *var = instr->variables[0]->var;
3566 const struct glsl_type *type = instr->variables[0]->var->type;
3567 bool da = glsl_sampler_type_is_array(var->type) ||
3568 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3569 if(instr->variables[0]->deref.child)
3570 type = instr->variables[0]->deref.child->type;
3571
3572 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3573 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
3574
3575 struct ac_image_args args = { 0 };
3576
3577 args.da = da;
3578 args.dmask = 0xf;
3579 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3580 args.opcode = ac_image_get_resinfo;
3581 args.addr = ctx->i32zero;
3582
3583 res = ac_build_image_opcode(&ctx->ac, &args);
3584
3585 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3586 glsl_sampler_type_is_array(type)) {
3587 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3588 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3589 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
3590 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3591 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
3592 }
3593 return res;
3594 }
3595
3596 #define NOOP_WAITCNT 0xf7f
3597 #define LGKM_CNT 0x07f
3598 #define VM_CNT 0xf70
3599
3600 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3601 unsigned simm16)
3602 {
3603 LLVMValueRef args[1] = {
3604 LLVMConstInt(ctx->i32, simm16, false),
3605 };
3606 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3607 ctx->voidt, args, 1, 0);
3608 }
3609
3610 static void emit_barrier(struct nir_to_llvm_context *ctx)
3611 {
3612 /* SI only (thanks to a hw bug workaround):
3613 * The real barrier instruction isn’t needed, because an entire patch
3614 * always fits into a single wave.
3615 */
3616 if (ctx->options->chip_class == SI &&
3617 ctx->stage == MESA_SHADER_TESS_CTRL) {
3618 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3619 return;
3620 }
3621 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3622 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3623 }
3624
3625 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3626 const nir_intrinsic_instr *instr)
3627 {
3628 LLVMValueRef cond;
3629 ctx->shader_info->fs.can_discard = true;
3630
3631 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3632 get_src(ctx->nir, instr->src[0]),
3633 ctx->i32zero, "");
3634
3635 cond = LLVMBuildSelect(ctx->builder, cond,
3636 LLVMConstReal(ctx->f32, -1.0f),
3637 ctx->f32zero, "");
3638 ac_build_kill(&ctx->ac, cond);
3639 }
3640
3641 static LLVMValueRef
3642 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3643 {
3644 LLVMValueRef result;
3645 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3646 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3647 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3648
3649 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3650 }
3651
3652 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3653 const nir_intrinsic_instr *instr)
3654 {
3655 LLVMValueRef ptr, result;
3656 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3657 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3658
3659 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3660 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3661 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3662 ptr, src, src1,
3663 LLVMAtomicOrderingSequentiallyConsistent,
3664 LLVMAtomicOrderingSequentiallyConsistent,
3665 false);
3666 } else {
3667 LLVMAtomicRMWBinOp op;
3668 switch (instr->intrinsic) {
3669 case nir_intrinsic_var_atomic_add:
3670 op = LLVMAtomicRMWBinOpAdd;
3671 break;
3672 case nir_intrinsic_var_atomic_umin:
3673 op = LLVMAtomicRMWBinOpUMin;
3674 break;
3675 case nir_intrinsic_var_atomic_umax:
3676 op = LLVMAtomicRMWBinOpUMax;
3677 break;
3678 case nir_intrinsic_var_atomic_imin:
3679 op = LLVMAtomicRMWBinOpMin;
3680 break;
3681 case nir_intrinsic_var_atomic_imax:
3682 op = LLVMAtomicRMWBinOpMax;
3683 break;
3684 case nir_intrinsic_var_atomic_and:
3685 op = LLVMAtomicRMWBinOpAnd;
3686 break;
3687 case nir_intrinsic_var_atomic_or:
3688 op = LLVMAtomicRMWBinOpOr;
3689 break;
3690 case nir_intrinsic_var_atomic_xor:
3691 op = LLVMAtomicRMWBinOpXor;
3692 break;
3693 case nir_intrinsic_var_atomic_exchange:
3694 op = LLVMAtomicRMWBinOpXchg;
3695 break;
3696 default:
3697 return NULL;
3698 }
3699
3700 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(&ctx->ac, src),
3701 LLVMAtomicOrderingSequentiallyConsistent,
3702 false);
3703 }
3704 return result;
3705 }
3706
3707 #define INTERP_CENTER 0
3708 #define INTERP_CENTROID 1
3709 #define INTERP_SAMPLE 2
3710
3711 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3712 enum glsl_interp_mode interp, unsigned location)
3713 {
3714 switch (interp) {
3715 case INTERP_MODE_FLAT:
3716 default:
3717 return NULL;
3718 case INTERP_MODE_SMOOTH:
3719 case INTERP_MODE_NONE:
3720 if (location == INTERP_CENTER)
3721 return ctx->persp_center;
3722 else if (location == INTERP_CENTROID)
3723 return ctx->persp_centroid;
3724 else if (location == INTERP_SAMPLE)
3725 return ctx->persp_sample;
3726 break;
3727 case INTERP_MODE_NOPERSPECTIVE:
3728 if (location == INTERP_CENTER)
3729 return ctx->linear_center;
3730 else if (location == INTERP_CENTROID)
3731 return ctx->linear_centroid;
3732 else if (location == INTERP_SAMPLE)
3733 return ctx->linear_sample;
3734 break;
3735 }
3736 return NULL;
3737 }
3738
3739 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3740 LLVMValueRef sample_id)
3741 {
3742 LLVMValueRef result;
3743 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3744
3745 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3746 const_array(ctx->v2f32, 64), "");
3747
3748 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3749 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3750
3751 return result;
3752 }
3753
3754 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3755 {
3756 LLVMValueRef values[2];
3757
3758 values[0] = emit_ffract(&ctx->ac, ctx->frag_pos[0]);
3759 values[1] = emit_ffract(&ctx->ac, ctx->frag_pos[1]);
3760 return ac_build_gather_values(&ctx->ac, values, 2);
3761 }
3762
3763 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3764 const nir_intrinsic_instr *instr)
3765 {
3766 LLVMValueRef result[2];
3767 LLVMValueRef interp_param, attr_number;
3768 unsigned location;
3769 unsigned chan;
3770 LLVMValueRef src_c0, src_c1;
3771 LLVMValueRef src0;
3772 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3773 switch (instr->intrinsic) {
3774 case nir_intrinsic_interp_var_at_centroid:
3775 location = INTERP_CENTROID;
3776 break;
3777 case nir_intrinsic_interp_var_at_sample:
3778 case nir_intrinsic_interp_var_at_offset:
3779 location = INTERP_CENTER;
3780 src0 = get_src(ctx->nir, instr->src[0]);
3781 break;
3782 default:
3783 break;
3784 }
3785
3786 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3787 src_c0 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3788 src_c1 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3789 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3790 LLVMValueRef sample_position;
3791 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3792
3793 /* fetch sample ID */
3794 sample_position = load_sample_position(ctx, src0);
3795
3796 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3797 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3798 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3799 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3800 }
3801 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3802 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3803
3804 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3805 LLVMValueRef ij_out[2];
3806 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3807
3808 /*
3809 * take the I then J parameters, and the DDX/Y for it, and
3810 * calculate the IJ inputs for the interpolator.
3811 * temp1 = ddx * offset/sample.x + I;
3812 * interp_param.I = ddy * offset/sample.y + temp1;
3813 * temp1 = ddx * offset/sample.x + J;
3814 * interp_param.J = ddy * offset/sample.y + temp1;
3815 */
3816 for (unsigned i = 0; i < 2; i++) {
3817 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3818 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3819 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3820 ddxy_out, ix_ll, "");
3821 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3822 ddxy_out, iy_ll, "");
3823 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3824 interp_param, ix_ll, "");
3825 LLVMValueRef temp1, temp2;
3826
3827 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3828 ctx->f32, "");
3829
3830 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3831 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3832
3833 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3834 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3835
3836 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3837 temp2, ctx->i32, "");
3838 }
3839 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3840
3841 }
3842
3843 for (chan = 0; chan < 2; chan++) {
3844 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3845
3846 if (interp_param) {
3847 interp_param = LLVMBuildBitCast(ctx->builder,
3848 interp_param, LLVMVectorType(ctx->f32, 2), "");
3849 LLVMValueRef i = LLVMBuildExtractElement(
3850 ctx->builder, interp_param, ctx->i32zero, "");
3851 LLVMValueRef j = LLVMBuildExtractElement(
3852 ctx->builder, interp_param, ctx->i32one, "");
3853
3854 result[chan] = ac_build_fs_interp(&ctx->ac,
3855 llvm_chan, attr_number,
3856 ctx->prim_mask, i, j);
3857 } else {
3858 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3859 LLVMConstInt(ctx->i32, 2, false),
3860 llvm_chan, attr_number,
3861 ctx->prim_mask);
3862 }
3863 }
3864 return ac_build_gather_values(&ctx->ac, result, 2);
3865 }
3866
3867 static void
3868 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3869 const nir_intrinsic_instr *instr)
3870 {
3871 LLVMValueRef gs_next_vertex;
3872 LLVMValueRef can_emit, kill;
3873 int idx;
3874
3875 assert(instr->const_index[0] == 0);
3876 /* Write vertex attribute values to GSVS ring */
3877 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3878 ctx->gs_next_vertex,
3879 "");
3880
3881 /* If this thread has already emitted the declared maximum number of
3882 * vertices, kill it: excessive vertex emissions are not supposed to
3883 * have any effect, and GS threads have no externally observable
3884 * effects other than emitting vertices.
3885 */
3886 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3887 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3888
3889 kill = LLVMBuildSelect(ctx->builder, can_emit,
3890 LLVMConstReal(ctx->f32, 1.0f),
3891 LLVMConstReal(ctx->f32, -1.0f), "");
3892 ac_build_kill(&ctx->ac, kill);
3893
3894 /* loop num outputs */
3895 idx = 0;
3896 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3897 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
3898 int length = 4;
3899 int slot = idx;
3900 int slot_inc = 1;
3901
3902 if (!(ctx->output_mask & (1ull << i)))
3903 continue;
3904
3905 if (i == VARYING_SLOT_CLIP_DIST0) {
3906 /* pack clip and cull into a single set of slots */
3907 length = ctx->num_output_clips + ctx->num_output_culls;
3908 if (length > 4)
3909 slot_inc = 2;
3910 }
3911 for (unsigned j = 0; j < length; j++) {
3912 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3913 out_ptr[j], "");
3914 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3915 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3916 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3917
3918 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3919
3920 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3921 out_val, 1,
3922 voffset, ctx->gs2vs_offset, 0,
3923 1, 1, true, true);
3924 }
3925 idx += slot_inc;
3926 }
3927
3928 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3929 ctx->i32one, "");
3930 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3931
3932 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3933 }
3934
3935 static void
3936 visit_end_primitive(struct nir_to_llvm_context *ctx,
3937 const nir_intrinsic_instr *instr)
3938 {
3939 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3940 }
3941
3942 static LLVMValueRef
3943 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3944 const nir_intrinsic_instr *instr)
3945 {
3946 LLVMValueRef coord[4] = {
3947 ctx->tes_u,
3948 ctx->tes_v,
3949 ctx->f32zero,
3950 ctx->f32zero,
3951 };
3952
3953 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3954 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3955 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3956
3957 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3958 return LLVMBuildBitCast(ctx->builder, result,
3959 get_def_type(ctx->nir, &instr->dest.ssa), "");
3960 }
3961
3962 static void visit_intrinsic(struct ac_nir_context *ctx,
3963 nir_intrinsic_instr *instr)
3964 {
3965 LLVMValueRef result = NULL;
3966
3967 switch (instr->intrinsic) {
3968 case nir_intrinsic_load_work_group_id: {
3969 result = ctx->nctx->workgroup_ids;
3970 break;
3971 }
3972 case nir_intrinsic_load_base_vertex: {
3973 result = ctx->abi->base_vertex;
3974 break;
3975 }
3976 case nir_intrinsic_load_vertex_id_zero_base: {
3977 result = ctx->abi->vertex_id;
3978 break;
3979 }
3980 case nir_intrinsic_load_local_invocation_id: {
3981 result = ctx->nctx->local_invocation_ids;
3982 break;
3983 }
3984 case nir_intrinsic_load_base_instance:
3985 result = ctx->abi->start_instance;
3986 break;
3987 case nir_intrinsic_load_draw_id:
3988 result = ctx->abi->draw_id;
3989 break;
3990 case nir_intrinsic_load_invocation_id:
3991 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3992 result = unpack_param(ctx->nctx, ctx->nctx->tcs_rel_ids, 8, 5);
3993 else
3994 result = ctx->nctx->gs_invocation_id;
3995 break;
3996 case nir_intrinsic_load_primitive_id:
3997 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3998 ctx->nctx->shader_info->gs.uses_prim_id = true;
3999 result = ctx->nctx->gs_prim_id;
4000 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4001 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4002 result = ctx->nctx->tcs_patch_id;
4003 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4004 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4005 result = ctx->nctx->tes_patch_id;
4006 } else
4007 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4008 break;
4009 case nir_intrinsic_load_sample_id:
4010 ctx->nctx->shader_info->fs.force_persample = true;
4011 result = unpack_param(ctx->nctx, ctx->nctx->ancillary, 8, 4);
4012 break;
4013 case nir_intrinsic_load_sample_pos:
4014 ctx->nctx->shader_info->fs.force_persample = true;
4015 result = load_sample_pos(ctx->nctx);
4016 break;
4017 case nir_intrinsic_load_sample_mask_in:
4018 result = ctx->nctx->sample_coverage;
4019 break;
4020 case nir_intrinsic_load_front_face:
4021 result = ctx->nctx->front_face;
4022 break;
4023 case nir_intrinsic_load_instance_id:
4024 result = ctx->abi->instance_id;
4025 ctx->nctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4026 ctx->nctx->shader_info->vs.vgpr_comp_cnt);
4027 break;
4028 case nir_intrinsic_load_num_work_groups:
4029 result = ctx->nctx->num_work_groups;
4030 break;
4031 case nir_intrinsic_load_local_invocation_index:
4032 result = visit_load_local_invocation_index(ctx->nctx);
4033 break;
4034 case nir_intrinsic_load_push_constant:
4035 result = visit_load_push_constant(ctx->nctx, instr);
4036 break;
4037 case nir_intrinsic_vulkan_resource_index:
4038 result = visit_vulkan_resource_index(ctx->nctx, instr);
4039 break;
4040 case nir_intrinsic_store_ssbo:
4041 visit_store_ssbo(ctx->nctx, instr);
4042 break;
4043 case nir_intrinsic_load_ssbo:
4044 result = visit_load_buffer(ctx->nctx, instr);
4045 break;
4046 case nir_intrinsic_ssbo_atomic_add:
4047 case nir_intrinsic_ssbo_atomic_imin:
4048 case nir_intrinsic_ssbo_atomic_umin:
4049 case nir_intrinsic_ssbo_atomic_imax:
4050 case nir_intrinsic_ssbo_atomic_umax:
4051 case nir_intrinsic_ssbo_atomic_and:
4052 case nir_intrinsic_ssbo_atomic_or:
4053 case nir_intrinsic_ssbo_atomic_xor:
4054 case nir_intrinsic_ssbo_atomic_exchange:
4055 case nir_intrinsic_ssbo_atomic_comp_swap:
4056 result = visit_atomic_ssbo(ctx->nctx, instr);
4057 break;
4058 case nir_intrinsic_load_ubo:
4059 result = visit_load_ubo_buffer(ctx, instr);
4060 break;
4061 case nir_intrinsic_get_buffer_size:
4062 result = visit_get_buffer_size(ctx->nctx, instr);
4063 break;
4064 case nir_intrinsic_load_var:
4065 result = visit_load_var(ctx, instr);
4066 break;
4067 case nir_intrinsic_store_var:
4068 visit_store_var(ctx, instr);
4069 break;
4070 case nir_intrinsic_image_load:
4071 result = visit_image_load(ctx->nctx, instr);
4072 break;
4073 case nir_intrinsic_image_store:
4074 visit_image_store(ctx->nctx, instr);
4075 break;
4076 case nir_intrinsic_image_atomic_add:
4077 case nir_intrinsic_image_atomic_min:
4078 case nir_intrinsic_image_atomic_max:
4079 case nir_intrinsic_image_atomic_and:
4080 case nir_intrinsic_image_atomic_or:
4081 case nir_intrinsic_image_atomic_xor:
4082 case nir_intrinsic_image_atomic_exchange:
4083 case nir_intrinsic_image_atomic_comp_swap:
4084 result = visit_image_atomic(ctx->nctx, instr);
4085 break;
4086 case nir_intrinsic_image_size:
4087 result = visit_image_size(ctx->nctx, instr);
4088 break;
4089 case nir_intrinsic_discard:
4090 ctx->nctx->shader_info->fs.can_discard = true;
4091 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4092 LLVMVoidTypeInContext(ctx->ac.context),
4093 NULL, 0, AC_FUNC_ATTR_LEGACY);
4094 break;
4095 case nir_intrinsic_discard_if:
4096 emit_discard_if(ctx->nctx, instr);
4097 break;
4098 case nir_intrinsic_memory_barrier:
4099 emit_waitcnt(ctx->nctx, VM_CNT);
4100 break;
4101 case nir_intrinsic_barrier:
4102 emit_barrier(ctx->nctx);
4103 break;
4104 case nir_intrinsic_var_atomic_add:
4105 case nir_intrinsic_var_atomic_imin:
4106 case nir_intrinsic_var_atomic_umin:
4107 case nir_intrinsic_var_atomic_imax:
4108 case nir_intrinsic_var_atomic_umax:
4109 case nir_intrinsic_var_atomic_and:
4110 case nir_intrinsic_var_atomic_or:
4111 case nir_intrinsic_var_atomic_xor:
4112 case nir_intrinsic_var_atomic_exchange:
4113 case nir_intrinsic_var_atomic_comp_swap:
4114 result = visit_var_atomic(ctx->nctx, instr);
4115 break;
4116 case nir_intrinsic_interp_var_at_centroid:
4117 case nir_intrinsic_interp_var_at_sample:
4118 case nir_intrinsic_interp_var_at_offset:
4119 result = visit_interp(ctx->nctx, instr);
4120 break;
4121 case nir_intrinsic_emit_vertex:
4122 visit_emit_vertex(ctx->nctx, instr);
4123 break;
4124 case nir_intrinsic_end_primitive:
4125 visit_end_primitive(ctx->nctx, instr);
4126 break;
4127 case nir_intrinsic_load_tess_coord:
4128 result = visit_load_tess_coord(ctx->nctx, instr);
4129 break;
4130 case nir_intrinsic_load_patch_vertices_in:
4131 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4132 break;
4133 default:
4134 fprintf(stderr, "Unknown intrinsic: ");
4135 nir_print_instr(&instr->instr, stderr);
4136 fprintf(stderr, "\n");
4137 break;
4138 }
4139 if (result) {
4140 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4141 }
4142 }
4143
4144 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
4145 const nir_deref_var *deref,
4146 enum desc_type desc_type)
4147 {
4148 unsigned desc_set = deref->var->data.descriptor_set;
4149 LLVMValueRef list = ctx->descriptor_sets[desc_set];
4150 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4151 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
4152 unsigned offset = binding->offset;
4153 unsigned stride = binding->size;
4154 unsigned type_size;
4155 LLVMBuilderRef builder = ctx->builder;
4156 LLVMTypeRef type;
4157 LLVMValueRef index = NULL;
4158 unsigned constant_index = 0;
4159
4160 assert(deref->var->data.binding < layout->binding_count);
4161
4162 switch (desc_type) {
4163 case DESC_IMAGE:
4164 type = ctx->v8i32;
4165 type_size = 32;
4166 break;
4167 case DESC_FMASK:
4168 type = ctx->v8i32;
4169 offset += 32;
4170 type_size = 32;
4171 break;
4172 case DESC_SAMPLER:
4173 type = ctx->v4i32;
4174 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4175 offset += 64;
4176
4177 type_size = 16;
4178 break;
4179 case DESC_BUFFER:
4180 type = ctx->v4i32;
4181 type_size = 16;
4182 break;
4183 default:
4184 unreachable("invalid desc_type\n");
4185 }
4186
4187 if (deref->deref.child) {
4188 const nir_deref_array *child =
4189 (const nir_deref_array *)deref->deref.child;
4190
4191 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4192 offset += child->base_offset * stride;
4193 if (child->deref_array_type == nir_deref_array_type_indirect) {
4194 index = get_src(ctx->nir, child->indirect);
4195 }
4196
4197 constant_index = child->base_offset;
4198 }
4199 if (desc_type == DESC_SAMPLER && binding->immutable_samplers_offset &&
4200 (!index || binding->immutable_samplers_equal)) {
4201 if (binding->immutable_samplers_equal)
4202 constant_index = 0;
4203
4204 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4205
4206 LLVMValueRef constants[] = {
4207 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4208 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4209 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4210 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4211 };
4212 return ac_build_gather_values(&ctx->ac, constants, 4);
4213 }
4214
4215 assert(stride % type_size == 0);
4216
4217 if (!index)
4218 index = ctx->i32zero;
4219
4220 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4221
4222 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4223 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4224
4225 return ac_build_indexed_load_const(&ctx->ac, list, index);
4226 }
4227
4228 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
4229 struct ac_image_args *args,
4230 const nir_tex_instr *instr,
4231 nir_texop op,
4232 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4233 LLVMValueRef *param, unsigned count,
4234 unsigned dmask)
4235 {
4236 unsigned is_rect = 0;
4237 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4238
4239 if (op == nir_texop_lod)
4240 da = false;
4241 /* Pad to power of two vector */
4242 while (count < util_next_power_of_two(count))
4243 param[count++] = LLVMGetUndef(ctx->i32);
4244
4245 if (count > 1)
4246 args->addr = ac_build_gather_values(&ctx->ac, param, count);
4247 else
4248 args->addr = param[0];
4249
4250 args->resource = res_ptr;
4251 args->sampler = samp_ptr;
4252
4253 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4254 args->addr = param[0];
4255 return;
4256 }
4257
4258 args->dmask = dmask;
4259 args->unorm = is_rect;
4260 args->da = da;
4261 }
4262
4263 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4264 *
4265 * SI-CI:
4266 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4267 * filtering manually. The driver sets img7 to a mask clearing
4268 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4269 * s_and_b32 samp0, samp0, img7
4270 *
4271 * VI:
4272 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4273 */
4274 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
4275 LLVMValueRef res, LLVMValueRef samp)
4276 {
4277 LLVMBuilderRef builder = ctx->builder;
4278 LLVMValueRef img7, samp0;
4279
4280 if (ctx->options->chip_class >= VI)
4281 return samp;
4282
4283 img7 = LLVMBuildExtractElement(builder, res,
4284 LLVMConstInt(ctx->i32, 7, 0), "");
4285 samp0 = LLVMBuildExtractElement(builder, samp,
4286 LLVMConstInt(ctx->i32, 0, 0), "");
4287 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4288 return LLVMBuildInsertElement(builder, samp, samp0,
4289 LLVMConstInt(ctx->i32, 0, 0), "");
4290 }
4291
4292 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
4293 nir_tex_instr *instr,
4294 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4295 LLVMValueRef *fmask_ptr)
4296 {
4297 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4298 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
4299 else
4300 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
4301 if (samp_ptr) {
4302 if (instr->sampler)
4303 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
4304 else
4305 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
4306 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4307 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4308 }
4309 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4310 instr->op == nir_texop_samples_identical))
4311 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
4312 }
4313
4314 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
4315 LLVMValueRef coord)
4316 {
4317 coord = to_float(&ctx->ac, coord);
4318 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4319 coord = to_integer(&ctx->ac, coord);
4320 return coord;
4321 }
4322
4323 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
4324 {
4325 LLVMValueRef result = NULL;
4326 struct ac_image_args args = { 0 };
4327 unsigned dmask = 0xf;
4328 LLVMValueRef address[16];
4329 LLVMValueRef coords[5];
4330 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4331 LLVMValueRef bias = NULL, offsets = NULL;
4332 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4333 LLVMValueRef ddx = NULL, ddy = NULL;
4334 LLVMValueRef derivs[6];
4335 unsigned chan, count = 0;
4336 unsigned const_src = 0, num_deriv_comp = 0;
4337 bool lod_is_zero = false;
4338 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4339
4340 for (unsigned i = 0; i < instr->num_srcs; i++) {
4341 switch (instr->src[i].src_type) {
4342 case nir_tex_src_coord:
4343 coord = get_src(ctx->nir, instr->src[i].src);
4344 break;
4345 case nir_tex_src_projector:
4346 break;
4347 case nir_tex_src_comparator:
4348 comparator = get_src(ctx->nir, instr->src[i].src);
4349 break;
4350 case nir_tex_src_offset:
4351 offsets = get_src(ctx->nir, instr->src[i].src);
4352 const_src = i;
4353 break;
4354 case nir_tex_src_bias:
4355 bias = get_src(ctx->nir, instr->src[i].src);
4356 break;
4357 case nir_tex_src_lod: {
4358 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4359
4360 if (val && val->i32[0] == 0)
4361 lod_is_zero = true;
4362 lod = get_src(ctx->nir, instr->src[i].src);
4363 break;
4364 }
4365 case nir_tex_src_ms_index:
4366 sample_index = get_src(ctx->nir, instr->src[i].src);
4367 break;
4368 case nir_tex_src_ms_mcs:
4369 break;
4370 case nir_tex_src_ddx:
4371 ddx = get_src(ctx->nir, instr->src[i].src);
4372 num_deriv_comp = instr->src[i].src.ssa->num_components;
4373 break;
4374 case nir_tex_src_ddy:
4375 ddy = get_src(ctx->nir, instr->src[i].src);
4376 break;
4377 case nir_tex_src_texture_offset:
4378 case nir_tex_src_sampler_offset:
4379 case nir_tex_src_plane:
4380 default:
4381 break;
4382 }
4383 }
4384
4385 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4386 result = get_buffer_size(ctx, res_ptr, true);
4387 goto write_result;
4388 }
4389
4390 if (instr->op == nir_texop_texture_samples) {
4391 LLVMValueRef res, samples, is_msaa;
4392 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
4393 samples = LLVMBuildExtractElement(ctx->builder, res,
4394 LLVMConstInt(ctx->i32, 3, false), "");
4395 is_msaa = LLVMBuildLShr(ctx->builder, samples,
4396 LLVMConstInt(ctx->i32, 28, false), "");
4397 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
4398 LLVMConstInt(ctx->i32, 0xe, false), "");
4399 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
4400 LLVMConstInt(ctx->i32, 0xe, false), "");
4401
4402 samples = LLVMBuildLShr(ctx->builder, samples,
4403 LLVMConstInt(ctx->i32, 16, false), "");
4404 samples = LLVMBuildAnd(ctx->builder, samples,
4405 LLVMConstInt(ctx->i32, 0xf, false), "");
4406 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
4407 samples, "");
4408 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
4409 ctx->i32one, "");
4410 result = samples;
4411 goto write_result;
4412 }
4413
4414 if (coord)
4415 for (chan = 0; chan < instr->coord_components; chan++)
4416 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4417
4418 if (offsets && instr->op != nir_texop_txf) {
4419 LLVMValueRef offset[3], pack;
4420 for (chan = 0; chan < 3; ++chan)
4421 offset[chan] = ctx->i32zero;
4422
4423 args.offset = true;
4424 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4425 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4426 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
4427 LLVMConstInt(ctx->i32, 0x3f, false), "");
4428 if (chan)
4429 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
4430 LLVMConstInt(ctx->i32, chan * 8, false), "");
4431 }
4432 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
4433 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
4434 address[count++] = pack;
4435
4436 }
4437 /* pack LOD bias value */
4438 if (instr->op == nir_texop_txb && bias) {
4439 address[count++] = bias;
4440 }
4441
4442 /* Pack depth comparison value */
4443 if (instr->is_shadow && comparator) {
4444 address[count++] = llvm_extract_elem(&ctx->ac, comparator, 0);
4445 }
4446
4447 /* pack derivatives */
4448 if (ddx || ddy) {
4449 switch (instr->sampler_dim) {
4450 case GLSL_SAMPLER_DIM_3D:
4451 case GLSL_SAMPLER_DIM_CUBE:
4452 num_deriv_comp = 3;
4453 break;
4454 case GLSL_SAMPLER_DIM_2D:
4455 default:
4456 num_deriv_comp = 2;
4457 break;
4458 case GLSL_SAMPLER_DIM_1D:
4459 num_deriv_comp = 1;
4460 break;
4461 }
4462
4463 for (unsigned i = 0; i < num_deriv_comp; i++) {
4464 derivs[i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4465 derivs[num_deriv_comp + i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4466 }
4467 }
4468
4469 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4470 if (instr->is_array && instr->op != nir_texop_lod)
4471 coords[3] = apply_round_slice(ctx, coords[3]);
4472 for (chan = 0; chan < instr->coord_components; chan++)
4473 coords[chan] = to_float(&ctx->ac, coords[chan]);
4474 if (instr->coord_components == 3)
4475 coords[3] = LLVMGetUndef(ctx->f32);
4476 ac_prepare_cube_coords(&ctx->ac,
4477 instr->op == nir_texop_txd, instr->is_array,
4478 coords, derivs);
4479 if (num_deriv_comp)
4480 num_deriv_comp--;
4481 }
4482
4483 if (ddx || ddy) {
4484 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4485 address[count++] = derivs[i];
4486 }
4487
4488 /* Pack texture coordinates */
4489 if (coord) {
4490 address[count++] = coords[0];
4491 if (instr->coord_components > 1) {
4492 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4493 coords[1] = apply_round_slice(ctx, coords[1]);
4494 }
4495 address[count++] = coords[1];
4496 }
4497 if (instr->coord_components > 2) {
4498 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4499 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4500 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4501 instr->op != nir_texop_txf) {
4502 coords[2] = apply_round_slice(ctx, coords[2]);
4503 }
4504 address[count++] = coords[2];
4505 }
4506 }
4507
4508 /* Pack LOD */
4509 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4510 instr->op == nir_texop_txf)) {
4511 address[count++] = lod;
4512 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4513 address[count++] = sample_index;
4514 } else if(instr->op == nir_texop_txs) {
4515 count = 0;
4516 if (lod)
4517 address[count++] = lod;
4518 else
4519 address[count++] = ctx->i32zero;
4520 }
4521
4522 for (chan = 0; chan < count; chan++) {
4523 address[chan] = LLVMBuildBitCast(ctx->builder,
4524 address[chan], ctx->i32, "");
4525 }
4526
4527 if (instr->op == nir_texop_samples_identical) {
4528 LLVMValueRef txf_address[4];
4529 struct ac_image_args txf_args = { 0 };
4530 unsigned txf_count = count;
4531 memcpy(txf_address, address, sizeof(txf_address));
4532
4533 if (!instr->is_array)
4534 txf_address[2] = ctx->i32zero;
4535 txf_address[3] = ctx->i32zero;
4536
4537 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
4538 fmask_ptr, NULL,
4539 txf_address, txf_count, 0xf);
4540
4541 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4542
4543 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4544 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->i32zero);
4545 goto write_result;
4546 }
4547
4548 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4549 instr->op != nir_texop_txs) {
4550 unsigned sample_chan = instr->is_array ? 3 : 2;
4551 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
4552 address[0],
4553 address[1],
4554 instr->is_array ? address[2] : NULL,
4555 address[sample_chan],
4556 fmask_ptr);
4557 }
4558
4559 if (offsets && instr->op == nir_texop_txf) {
4560 nir_const_value *const_offset =
4561 nir_src_as_const_value(instr->src[const_src].src);
4562 int num_offsets = instr->src[const_src].src.ssa->num_components;
4563 assert(const_offset);
4564 num_offsets = MIN2(num_offsets, instr->coord_components);
4565 if (num_offsets > 2)
4566 address[2] = LLVMBuildAdd(ctx->builder,
4567 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
4568 if (num_offsets > 1)
4569 address[1] = LLVMBuildAdd(ctx->builder,
4570 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
4571 address[0] = LLVMBuildAdd(ctx->builder,
4572 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
4573
4574 }
4575
4576 /* TODO TG4 support */
4577 if (instr->op == nir_texop_tg4) {
4578 if (instr->is_shadow)
4579 dmask = 1;
4580 else
4581 dmask = 1 << instr->component;
4582 }
4583 set_tex_fetch_args(ctx, &args, instr, instr->op,
4584 res_ptr, samp_ptr, address, count, dmask);
4585
4586 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4587
4588 if (instr->op == nir_texop_query_levels)
4589 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
4590 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4591 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4592 else if (instr->op == nir_texop_txs &&
4593 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4594 instr->is_array) {
4595 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
4596 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
4597 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
4598 z = LLVMBuildSDiv(ctx->builder, z, six, "");
4599 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
4600 } else if (instr->dest.ssa.num_components != 4)
4601 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
4602
4603 write_result:
4604 if (result) {
4605 assert(instr->dest.is_ssa);
4606 result = to_integer(&ctx->ac, result);
4607 _mesa_hash_table_insert(ctx->nir->defs, &instr->dest.ssa, result);
4608 }
4609 }
4610
4611
4612 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4613 {
4614 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4615 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4616
4617 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4618 _mesa_hash_table_insert(ctx->phis, instr, result);
4619 }
4620
4621 static void visit_post_phi(struct ac_nir_context *ctx,
4622 nir_phi_instr *instr,
4623 LLVMValueRef llvm_phi)
4624 {
4625 nir_foreach_phi_src(src, instr) {
4626 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4627 LLVMValueRef llvm_src = get_src(ctx, src->src);
4628
4629 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4630 }
4631 }
4632
4633 static void phi_post_pass(struct ac_nir_context *ctx)
4634 {
4635 struct hash_entry *entry;
4636 hash_table_foreach(ctx->phis, entry) {
4637 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4638 (LLVMValueRef)entry->data);
4639 }
4640 }
4641
4642
4643 static void visit_ssa_undef(struct ac_nir_context *ctx,
4644 const nir_ssa_undef_instr *instr)
4645 {
4646 unsigned num_components = instr->def.num_components;
4647 LLVMValueRef undef;
4648
4649 if (num_components == 1)
4650 undef = LLVMGetUndef(ctx->ac.i32);
4651 else {
4652 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4653 }
4654 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4655 }
4656
4657 static void visit_jump(struct ac_nir_context *ctx,
4658 const nir_jump_instr *instr)
4659 {
4660 switch (instr->type) {
4661 case nir_jump_break:
4662 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4663 LLVMClearInsertionPosition(ctx->ac.builder);
4664 break;
4665 case nir_jump_continue:
4666 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4667 LLVMClearInsertionPosition(ctx->ac.builder);
4668 break;
4669 default:
4670 fprintf(stderr, "Unknown NIR jump instr: ");
4671 nir_print_instr(&instr->instr, stderr);
4672 fprintf(stderr, "\n");
4673 abort();
4674 }
4675 }
4676
4677 static void visit_cf_list(struct ac_nir_context *ctx,
4678 struct exec_list *list);
4679
4680 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4681 {
4682 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4683 nir_foreach_instr(instr, block)
4684 {
4685 switch (instr->type) {
4686 case nir_instr_type_alu:
4687 visit_alu(ctx, nir_instr_as_alu(instr));
4688 break;
4689 case nir_instr_type_load_const:
4690 visit_load_const(ctx, nir_instr_as_load_const(instr));
4691 break;
4692 case nir_instr_type_intrinsic:
4693 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4694 break;
4695 case nir_instr_type_tex:
4696 visit_tex(ctx->nctx, nir_instr_as_tex(instr));
4697 break;
4698 case nir_instr_type_phi:
4699 visit_phi(ctx, nir_instr_as_phi(instr));
4700 break;
4701 case nir_instr_type_ssa_undef:
4702 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4703 break;
4704 case nir_instr_type_jump:
4705 visit_jump(ctx, nir_instr_as_jump(instr));
4706 break;
4707 default:
4708 fprintf(stderr, "Unknown NIR instr type: ");
4709 nir_print_instr(instr, stderr);
4710 fprintf(stderr, "\n");
4711 abort();
4712 }
4713 }
4714
4715 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4716 }
4717
4718 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4719 {
4720 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4721
4722 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4723 LLVMBasicBlockRef merge_block =
4724 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4725 LLVMBasicBlockRef if_block =
4726 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4727 LLVMBasicBlockRef else_block = merge_block;
4728 if (!exec_list_is_empty(&if_stmt->else_list))
4729 else_block = LLVMAppendBasicBlockInContext(
4730 ctx->ac.context, fn, "");
4731
4732 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4733 LLVMConstInt(ctx->ac.i32, 0, false), "");
4734 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4735
4736 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4737 visit_cf_list(ctx, &if_stmt->then_list);
4738 if (LLVMGetInsertBlock(ctx->ac.builder))
4739 LLVMBuildBr(ctx->ac.builder, merge_block);
4740
4741 if (!exec_list_is_empty(&if_stmt->else_list)) {
4742 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4743 visit_cf_list(ctx, &if_stmt->else_list);
4744 if (LLVMGetInsertBlock(ctx->ac.builder))
4745 LLVMBuildBr(ctx->ac.builder, merge_block);
4746 }
4747
4748 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4749 }
4750
4751 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4752 {
4753 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4754 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4755 LLVMBasicBlockRef break_parent = ctx->break_block;
4756
4757 ctx->continue_block =
4758 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4759 ctx->break_block =
4760 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4761
4762 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4763 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4764 visit_cf_list(ctx, &loop->body);
4765
4766 if (LLVMGetInsertBlock(ctx->ac.builder))
4767 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4768 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4769
4770 ctx->continue_block = continue_parent;
4771 ctx->break_block = break_parent;
4772 }
4773
4774 static void visit_cf_list(struct ac_nir_context *ctx,
4775 struct exec_list *list)
4776 {
4777 foreach_list_typed(nir_cf_node, node, node, list)
4778 {
4779 switch (node->type) {
4780 case nir_cf_node_block:
4781 visit_block(ctx, nir_cf_node_as_block(node));
4782 break;
4783
4784 case nir_cf_node_if:
4785 visit_if(ctx, nir_cf_node_as_if(node));
4786 break;
4787
4788 case nir_cf_node_loop:
4789 visit_loop(ctx, nir_cf_node_as_loop(node));
4790 break;
4791
4792 default:
4793 assert(0);
4794 }
4795 }
4796 }
4797
4798 static void
4799 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4800 struct nir_variable *variable)
4801 {
4802 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4803 LLVMValueRef t_offset;
4804 LLVMValueRef t_list;
4805 LLVMValueRef input;
4806 LLVMValueRef buffer_index;
4807 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4808 int idx = variable->data.location;
4809 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4810
4811 variable->data.driver_location = idx * 4;
4812
4813 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4814 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
4815 ctx->abi.start_instance, "");
4816 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4817 ctx->shader_info->vs.vgpr_comp_cnt);
4818 } else
4819 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
4820 ctx->abi.base_vertex, "");
4821
4822 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4823 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4824
4825 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4826
4827 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4828 buffer_index,
4829 LLVMConstInt(ctx->i32, 0, false),
4830 true);
4831
4832 for (unsigned chan = 0; chan < 4; chan++) {
4833 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4834 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4835 to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
4836 input, llvm_chan, ""));
4837 }
4838 }
4839 }
4840
4841 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4842 unsigned attr,
4843 LLVMValueRef interp_param,
4844 LLVMValueRef prim_mask,
4845 LLVMValueRef result[4])
4846 {
4847 LLVMValueRef attr_number;
4848 unsigned chan;
4849 LLVMValueRef i, j;
4850 bool interp = interp_param != NULL;
4851
4852 attr_number = LLVMConstInt(ctx->i32, attr, false);
4853
4854 /* fs.constant returns the param from the middle vertex, so it's not
4855 * really useful for flat shading. It's meant to be used for custom
4856 * interpolation (but the intrinsic can't fetch from the other two
4857 * vertices).
4858 *
4859 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4860 * to do the right thing. The only reason we use fs.constant is that
4861 * fs.interp cannot be used on integers, because they can be equal
4862 * to NaN.
4863 */
4864 if (interp) {
4865 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4866 LLVMVectorType(ctx->f32, 2), "");
4867
4868 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4869 ctx->i32zero, "");
4870 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4871 ctx->i32one, "");
4872 }
4873
4874 for (chan = 0; chan < 4; chan++) {
4875 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4876
4877 if (interp) {
4878 result[chan] = ac_build_fs_interp(&ctx->ac,
4879 llvm_chan,
4880 attr_number,
4881 prim_mask, i, j);
4882 } else {
4883 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4884 LLVMConstInt(ctx->i32, 2, false),
4885 llvm_chan,
4886 attr_number,
4887 prim_mask);
4888 }
4889 }
4890 }
4891
4892 static void
4893 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4894 struct nir_variable *variable)
4895 {
4896 int idx = variable->data.location;
4897 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4898 LLVMValueRef interp;
4899
4900 variable->data.driver_location = idx * 4;
4901 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4902
4903 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4904 unsigned interp_type;
4905 if (variable->data.sample) {
4906 interp_type = INTERP_SAMPLE;
4907 ctx->shader_info->fs.force_persample = true;
4908 } else if (variable->data.centroid)
4909 interp_type = INTERP_CENTROID;
4910 else
4911 interp_type = INTERP_CENTER;
4912
4913 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4914 } else
4915 interp = NULL;
4916
4917 for (unsigned i = 0; i < attrib_count; ++i)
4918 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4919
4920 }
4921
4922 static void
4923 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4924 struct nir_variable *variable)
4925 {
4926 switch (ctx->stage) {
4927 case MESA_SHADER_VERTEX:
4928 handle_vs_input_decl(ctx, variable);
4929 break;
4930 case MESA_SHADER_FRAGMENT:
4931 handle_fs_input_decl(ctx, variable);
4932 break;
4933 default:
4934 break;
4935 }
4936
4937 }
4938
4939 static void
4940 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4941 struct nir_shader *nir)
4942 {
4943 unsigned index = 0;
4944 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4945 LLVMValueRef interp_param;
4946 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4947
4948 if (!(ctx->input_mask & (1ull << i)))
4949 continue;
4950
4951 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4952 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4953 interp_param = *inputs;
4954 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4955 inputs);
4956
4957 if (!interp_param)
4958 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4959 ++index;
4960 } else if (i == VARYING_SLOT_POS) {
4961 for(int i = 0; i < 3; ++i)
4962 inputs[i] = ctx->frag_pos[i];
4963
4964 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4965 }
4966 }
4967 ctx->shader_info->fs.num_interp = index;
4968 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4969 ctx->shader_info->fs.has_pcoord = true;
4970 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4971 ctx->shader_info->fs.prim_id_input = true;
4972 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4973 ctx->shader_info->fs.layer_input = true;
4974 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4975 }
4976
4977 static LLVMValueRef
4978 ac_build_alloca(struct ac_llvm_context *ac,
4979 LLVMTypeRef type,
4980 const char *name)
4981 {
4982 LLVMBuilderRef builder = ac->builder;
4983 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4984 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4985 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4986 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4987 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
4988 LLVMValueRef res;
4989
4990 if (first_instr) {
4991 LLVMPositionBuilderBefore(first_builder, first_instr);
4992 } else {
4993 LLVMPositionBuilderAtEnd(first_builder, first_block);
4994 }
4995
4996 res = LLVMBuildAlloca(first_builder, type, name);
4997 LLVMBuildStore(builder, LLVMConstNull(type), res);
4998
4999 LLVMDisposeBuilder(first_builder);
5000
5001 return res;
5002 }
5003
5004 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5005 LLVMTypeRef type,
5006 const char *name)
5007 {
5008 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5009 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5010 return ptr;
5011 }
5012
5013 static void
5014 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5015 struct nir_variable *variable)
5016 {
5017 int idx = variable->data.location + variable->data.index;
5018 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5019 uint64_t mask_attribs;
5020
5021 variable->data.driver_location = idx * 4;
5022
5023 /* tess ctrl has it's own load/store paths for outputs */
5024 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5025 return;
5026
5027 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5028 if (ctx->stage == MESA_SHADER_VERTEX ||
5029 ctx->stage == MESA_SHADER_TESS_EVAL ||
5030 ctx->stage == MESA_SHADER_GEOMETRY) {
5031 if (idx == VARYING_SLOT_CLIP_DIST0) {
5032 int length = ctx->num_output_clips + ctx->num_output_culls;
5033 if (ctx->stage == MESA_SHADER_VERTEX) {
5034 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5035 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5036 }
5037 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5038 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5039 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5040 }
5041
5042 if (length > 4)
5043 attrib_count = 2;
5044 else
5045 attrib_count = 1;
5046 mask_attribs = 1ull << idx;
5047 }
5048 }
5049
5050 ctx->output_mask |= mask_attribs;
5051 }
5052
5053 static void
5054 handle_shader_output_decl(struct ac_nir_context *ctx,
5055 struct nir_shader *nir,
5056 struct nir_variable *variable)
5057 {
5058 unsigned output_loc = variable->data.driver_location / 4;
5059 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5060
5061 /* tess ctrl has it's own load/store paths for outputs */
5062 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5063 return;
5064
5065 if (ctx->stage == MESA_SHADER_VERTEX ||
5066 ctx->stage == MESA_SHADER_TESS_EVAL ||
5067 ctx->stage == MESA_SHADER_GEOMETRY) {
5068 int idx = variable->data.location + variable->data.index;
5069 if (idx == VARYING_SLOT_CLIP_DIST0) {
5070 int length = nir->info.clip_distance_array_size +
5071 nir->info.cull_distance_array_size;
5072
5073 if (length > 4)
5074 attrib_count = 2;
5075 else
5076 attrib_count = 1;
5077 }
5078 }
5079
5080 for (unsigned i = 0; i < attrib_count; ++i) {
5081 for (unsigned chan = 0; chan < 4; chan++) {
5082 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5083 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5084 }
5085 }
5086 }
5087
5088 static LLVMTypeRef
5089 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5090 enum glsl_base_type type)
5091 {
5092 switch (type) {
5093 case GLSL_TYPE_INT:
5094 case GLSL_TYPE_UINT:
5095 case GLSL_TYPE_BOOL:
5096 case GLSL_TYPE_SUBROUTINE:
5097 return ctx->i32;
5098 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5099 return ctx->f32;
5100 case GLSL_TYPE_INT64:
5101 case GLSL_TYPE_UINT64:
5102 return ctx->i64;
5103 case GLSL_TYPE_DOUBLE:
5104 return ctx->f64;
5105 default:
5106 unreachable("unknown GLSL type");
5107 }
5108 }
5109
5110 static LLVMTypeRef
5111 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5112 const struct glsl_type *type)
5113 {
5114 if (glsl_type_is_scalar(type)) {
5115 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5116 }
5117
5118 if (glsl_type_is_vector(type)) {
5119 return LLVMVectorType(
5120 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5121 glsl_get_vector_elements(type));
5122 }
5123
5124 if (glsl_type_is_matrix(type)) {
5125 return LLVMArrayType(
5126 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5127 glsl_get_matrix_columns(type));
5128 }
5129
5130 if (glsl_type_is_array(type)) {
5131 return LLVMArrayType(
5132 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5133 glsl_get_length(type));
5134 }
5135
5136 assert(glsl_type_is_struct(type));
5137
5138 LLVMTypeRef member_types[glsl_get_length(type)];
5139
5140 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5141 member_types[i] =
5142 glsl_to_llvm_type(ctx,
5143 glsl_get_struct_field(type, i));
5144 }
5145
5146 return LLVMStructTypeInContext(ctx->context, member_types,
5147 glsl_get_length(type), false);
5148 }
5149
5150 static void
5151 setup_locals(struct ac_nir_context *ctx,
5152 struct nir_function *func)
5153 {
5154 int i, j;
5155 ctx->num_locals = 0;
5156 nir_foreach_variable(variable, &func->impl->locals) {
5157 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5158 variable->data.driver_location = ctx->num_locals * 4;
5159 ctx->num_locals += attrib_count;
5160 }
5161 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5162 if (!ctx->locals)
5163 return;
5164
5165 for (i = 0; i < ctx->num_locals; i++) {
5166 for (j = 0; j < 4; j++) {
5167 ctx->locals[i * 4 + j] =
5168 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5169 }
5170 }
5171 }
5172
5173 static void
5174 setup_shared(struct ac_nir_context *ctx,
5175 struct nir_shader *nir)
5176 {
5177 nir_foreach_variable(variable, &nir->shared) {
5178 LLVMValueRef shared =
5179 LLVMAddGlobalInAddressSpace(
5180 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5181 variable->name ? variable->name : "",
5182 LOCAL_ADDR_SPACE);
5183 _mesa_hash_table_insert(ctx->vars, variable, shared);
5184 }
5185 }
5186
5187 static LLVMValueRef
5188 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5189 {
5190 v = to_float(ctx, v);
5191 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5192 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5193 }
5194
5195
5196 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5197 LLVMValueRef src0, LLVMValueRef src1)
5198 {
5199 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5200 LLVMValueRef comp[2];
5201
5202 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5203 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5204 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5205 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5206 }
5207
5208 /* Initialize arguments for the shader export intrinsic */
5209 static void
5210 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5211 LLVMValueRef *values,
5212 unsigned target,
5213 struct ac_export_args *args)
5214 {
5215 /* Default is 0xf. Adjusted below depending on the format. */
5216 args->enabled_channels = 0xf;
5217
5218 /* Specify whether the EXEC mask represents the valid mask */
5219 args->valid_mask = 0;
5220
5221 /* Specify whether this is the last export */
5222 args->done = 0;
5223
5224 /* Specify the target we are exporting */
5225 args->target = target;
5226
5227 args->compr = false;
5228 args->out[0] = LLVMGetUndef(ctx->f32);
5229 args->out[1] = LLVMGetUndef(ctx->f32);
5230 args->out[2] = LLVMGetUndef(ctx->f32);
5231 args->out[3] = LLVMGetUndef(ctx->f32);
5232
5233 if (!values)
5234 return;
5235
5236 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5237 LLVMValueRef val[4];
5238 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5239 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5240 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5241
5242 switch(col_format) {
5243 case V_028714_SPI_SHADER_ZERO:
5244 args->enabled_channels = 0; /* writemask */
5245 args->target = V_008DFC_SQ_EXP_NULL;
5246 break;
5247
5248 case V_028714_SPI_SHADER_32_R:
5249 args->enabled_channels = 1;
5250 args->out[0] = values[0];
5251 break;
5252
5253 case V_028714_SPI_SHADER_32_GR:
5254 args->enabled_channels = 0x3;
5255 args->out[0] = values[0];
5256 args->out[1] = values[1];
5257 break;
5258
5259 case V_028714_SPI_SHADER_32_AR:
5260 args->enabled_channels = 0x9;
5261 args->out[0] = values[0];
5262 args->out[3] = values[3];
5263 break;
5264
5265 case V_028714_SPI_SHADER_FP16_ABGR:
5266 args->compr = 1;
5267
5268 for (unsigned chan = 0; chan < 2; chan++) {
5269 LLVMValueRef pack_args[2] = {
5270 values[2 * chan],
5271 values[2 * chan + 1]
5272 };
5273 LLVMValueRef packed;
5274
5275 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5276 args->out[chan] = packed;
5277 }
5278 break;
5279
5280 case V_028714_SPI_SHADER_UNORM16_ABGR:
5281 for (unsigned chan = 0; chan < 4; chan++) {
5282 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5283 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5284 LLVMConstReal(ctx->f32, 65535), "");
5285 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5286 LLVMConstReal(ctx->f32, 0.5), "");
5287 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5288 ctx->i32, "");
5289 }
5290
5291 args->compr = 1;
5292 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5293 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5294 break;
5295
5296 case V_028714_SPI_SHADER_SNORM16_ABGR:
5297 for (unsigned chan = 0; chan < 4; chan++) {
5298 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5299 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5300 LLVMConstReal(ctx->f32, 32767), "");
5301
5302 /* If positive, add 0.5, else add -0.5. */
5303 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5304 LLVMBuildSelect(ctx->builder,
5305 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5306 val[chan], ctx->f32zero, ""),
5307 LLVMConstReal(ctx->f32, 0.5),
5308 LLVMConstReal(ctx->f32, -0.5), ""), "");
5309 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5310 }
5311
5312 args->compr = 1;
5313 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5314 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5315 break;
5316
5317 case V_028714_SPI_SHADER_UINT16_ABGR: {
5318 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
5319
5320 for (unsigned chan = 0; chan < 4; chan++) {
5321 val[chan] = to_integer(&ctx->ac, values[chan]);
5322 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], max);
5323 }
5324
5325 args->compr = 1;
5326 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5327 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5328 break;
5329 }
5330
5331 case V_028714_SPI_SHADER_SINT16_ABGR: {
5332 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5333 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5334
5335 /* Clamp. */
5336 for (unsigned chan = 0; chan < 4; chan++) {
5337 val[chan] = to_integer(&ctx->ac, values[chan]);
5338 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], max);
5339 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], min);
5340 }
5341
5342 args->compr = 1;
5343 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5344 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5345 break;
5346 }
5347
5348 default:
5349 case V_028714_SPI_SHADER_32_ABGR:
5350 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5351 break;
5352 }
5353 } else
5354 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5355
5356 for (unsigned i = 0; i < 4; ++i)
5357 args->out[i] = to_float(&ctx->ac, args->out[i]);
5358 }
5359
5360 static void
5361 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5362 bool export_prim_id,
5363 struct ac_vs_output_info *outinfo)
5364 {
5365 uint32_t param_count = 0;
5366 unsigned target;
5367 unsigned pos_idx, num_pos_exports = 0;
5368 struct ac_export_args args, pos_args[4] = {};
5369 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5370 int i;
5371
5372 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5373 sizeof(outinfo->vs_output_param_offset));
5374
5375 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5376 LLVMValueRef slots[8];
5377 unsigned j;
5378
5379 if (outinfo->cull_dist_mask)
5380 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5381
5382 i = VARYING_SLOT_CLIP_DIST0;
5383 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5384 slots[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5385 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5386
5387 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5388 slots[i] = LLVMGetUndef(ctx->f32);
5389
5390 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5391 target = V_008DFC_SQ_EXP_POS + 3;
5392 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5393 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5394 &args, sizeof(args));
5395 }
5396
5397 target = V_008DFC_SQ_EXP_POS + 2;
5398 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5399 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5400 &args, sizeof(args));
5401
5402 }
5403
5404 LLVMValueRef pos_values[4] = {ctx->f32zero, ctx->f32zero, ctx->f32zero, ctx->f32one};
5405 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5406 for (unsigned j = 0; j < 4; j++)
5407 pos_values[j] = LLVMBuildLoad(ctx->builder,
5408 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5409 }
5410 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5411
5412 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5413 outinfo->writes_pointsize = true;
5414 psize_value = LLVMBuildLoad(ctx->builder,
5415 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5416 }
5417
5418 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5419 outinfo->writes_layer = true;
5420 layer_value = LLVMBuildLoad(ctx->builder,
5421 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5422 }
5423
5424 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5425 outinfo->writes_viewport_index = true;
5426 viewport_index_value = LLVMBuildLoad(ctx->builder,
5427 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5428 }
5429
5430 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5431 (outinfo->writes_layer == true ? 4 : 0) |
5432 (outinfo->writes_viewport_index == true ? 8 : 0));
5433 if (mask) {
5434 pos_args[1].enabled_channels = mask;
5435 pos_args[1].valid_mask = 0;
5436 pos_args[1].done = 0;
5437 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5438 pos_args[1].compr = 0;
5439 pos_args[1].out[0] = ctx->f32zero; /* X */
5440 pos_args[1].out[1] = ctx->f32zero; /* Y */
5441 pos_args[1].out[2] = ctx->f32zero; /* Z */
5442 pos_args[1].out[3] = ctx->f32zero; /* W */
5443
5444 if (outinfo->writes_pointsize == true)
5445 pos_args[1].out[0] = psize_value;
5446 if (outinfo->writes_layer == true)
5447 pos_args[1].out[2] = layer_value;
5448 if (outinfo->writes_viewport_index == true)
5449 pos_args[1].out[3] = viewport_index_value;
5450 }
5451 for (i = 0; i < 4; i++) {
5452 if (pos_args[i].out[0])
5453 num_pos_exports++;
5454 }
5455
5456 pos_idx = 0;
5457 for (i = 0; i < 4; i++) {
5458 if (!pos_args[i].out[0])
5459 continue;
5460
5461 /* Specify the target we are exporting */
5462 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5463 if (pos_idx == num_pos_exports)
5464 pos_args[i].done = 1;
5465 ac_build_export(&ctx->ac, &pos_args[i]);
5466 }
5467
5468 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5469 LLVMValueRef values[4];
5470 if (!(ctx->output_mask & (1ull << i)))
5471 continue;
5472
5473 for (unsigned j = 0; j < 4; j++)
5474 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5475 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5476
5477 if (i == VARYING_SLOT_LAYER) {
5478 target = V_008DFC_SQ_EXP_PARAM + param_count;
5479 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5480 param_count++;
5481 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5482 target = V_008DFC_SQ_EXP_PARAM + param_count;
5483 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5484 param_count++;
5485 } else if (i >= VARYING_SLOT_VAR0) {
5486 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5487 target = V_008DFC_SQ_EXP_PARAM + param_count;
5488 outinfo->vs_output_param_offset[i] = param_count;
5489 param_count++;
5490 } else
5491 continue;
5492
5493 si_llvm_init_export_args(ctx, values, target, &args);
5494
5495 if (target >= V_008DFC_SQ_EXP_POS &&
5496 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5497 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5498 &args, sizeof(args));
5499 } else {
5500 ac_build_export(&ctx->ac, &args);
5501 }
5502 }
5503
5504 if (export_prim_id) {
5505 LLVMValueRef values[4];
5506 target = V_008DFC_SQ_EXP_PARAM + param_count;
5507 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5508 param_count++;
5509
5510 values[0] = ctx->vs_prim_id;
5511 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5512 ctx->shader_info->vs.vgpr_comp_cnt);
5513 for (unsigned j = 1; j < 4; j++)
5514 values[j] = ctx->f32zero;
5515 si_llvm_init_export_args(ctx, values, target, &args);
5516 ac_build_export(&ctx->ac, &args);
5517 outinfo->export_prim_id = true;
5518 }
5519
5520 outinfo->pos_exports = num_pos_exports;
5521 outinfo->param_exports = param_count;
5522 }
5523
5524 static void
5525 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5526 struct ac_es_output_info *outinfo)
5527 {
5528 int j;
5529 uint64_t max_output_written = 0;
5530 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5531 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5532 int param_index;
5533 int length = 4;
5534
5535 if (!(ctx->output_mask & (1ull << i)))
5536 continue;
5537
5538 if (i == VARYING_SLOT_CLIP_DIST0)
5539 length = ctx->num_output_clips + ctx->num_output_culls;
5540
5541 param_index = shader_io_get_unique_index(i);
5542
5543 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5544
5545 for (j = 0; j < length; j++) {
5546 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5547 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5548
5549 ac_build_buffer_store_dword(&ctx->ac,
5550 ctx->esgs_ring,
5551 out_val, 1,
5552 NULL, ctx->es2gs_offset,
5553 (4 * param_index + j) * 4,
5554 1, 1, true, true);
5555 }
5556 }
5557 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5558 }
5559
5560 static void
5561 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5562 {
5563 LLVMValueRef vertex_id = ctx->rel_auto_id;
5564 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5565 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5566 vertex_dw_stride, "");
5567
5568 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5569 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5570 int length = 4;
5571
5572 if (!(ctx->output_mask & (1ull << i)))
5573 continue;
5574
5575 if (i == VARYING_SLOT_CLIP_DIST0)
5576 length = ctx->num_output_clips + ctx->num_output_culls;
5577 int param = shader_io_get_unique_index(i);
5578 mark_tess_output(ctx, false, param);
5579 if (length > 4)
5580 mark_tess_output(ctx, false, param + 1);
5581 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5582 LLVMConstInt(ctx->i32, param * 4, false),
5583 "");
5584 for (unsigned j = 0; j < length; j++) {
5585 lds_store(ctx, dw_addr,
5586 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5587 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5588 }
5589 }
5590 }
5591
5592 struct ac_build_if_state
5593 {
5594 struct nir_to_llvm_context *ctx;
5595 LLVMValueRef condition;
5596 LLVMBasicBlockRef entry_block;
5597 LLVMBasicBlockRef true_block;
5598 LLVMBasicBlockRef false_block;
5599 LLVMBasicBlockRef merge_block;
5600 };
5601
5602 static LLVMBasicBlockRef
5603 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5604 {
5605 LLVMBasicBlockRef current_block;
5606 LLVMBasicBlockRef next_block;
5607 LLVMBasicBlockRef new_block;
5608
5609 /* get current basic block */
5610 current_block = LLVMGetInsertBlock(ctx->builder);
5611
5612 /* chqeck if there's another block after this one */
5613 next_block = LLVMGetNextBasicBlock(current_block);
5614 if (next_block) {
5615 /* insert the new block before the next block */
5616 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5617 }
5618 else {
5619 /* append new block after current block */
5620 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5621 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5622 }
5623 return new_block;
5624 }
5625
5626 static void
5627 ac_nir_build_if(struct ac_build_if_state *ifthen,
5628 struct nir_to_llvm_context *ctx,
5629 LLVMValueRef condition)
5630 {
5631 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5632
5633 memset(ifthen, 0, sizeof *ifthen);
5634 ifthen->ctx = ctx;
5635 ifthen->condition = condition;
5636 ifthen->entry_block = block;
5637
5638 /* create endif/merge basic block for the phi functions */
5639 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5640
5641 /* create/insert true_block before merge_block */
5642 ifthen->true_block =
5643 LLVMInsertBasicBlockInContext(ctx->context,
5644 ifthen->merge_block,
5645 "if-true-block");
5646
5647 /* successive code goes into the true block */
5648 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5649 }
5650
5651 /**
5652 * End a conditional.
5653 */
5654 static void
5655 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5656 {
5657 LLVMBuilderRef builder = ifthen->ctx->builder;
5658
5659 /* Insert branch to the merge block from current block */
5660 LLVMBuildBr(builder, ifthen->merge_block);
5661
5662 /*
5663 * Now patch in the various branch instructions.
5664 */
5665
5666 /* Insert the conditional branch instruction at the end of entry_block */
5667 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5668 if (ifthen->false_block) {
5669 /* we have an else clause */
5670 LLVMBuildCondBr(builder, ifthen->condition,
5671 ifthen->true_block, ifthen->false_block);
5672 }
5673 else {
5674 /* no else clause */
5675 LLVMBuildCondBr(builder, ifthen->condition,
5676 ifthen->true_block, ifthen->merge_block);
5677 }
5678
5679 /* Resume building code at end of the ifthen->merge_block */
5680 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5681 }
5682
5683 static void
5684 write_tess_factors(struct nir_to_llvm_context *ctx)
5685 {
5686 unsigned stride, outer_comps, inner_comps;
5687 struct ac_build_if_state if_ctx, inner_if_ctx;
5688 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5689 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5690 unsigned tess_inner_index, tess_outer_index;
5691 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5692 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5693 int i;
5694 emit_barrier(ctx);
5695
5696 switch (ctx->options->key.tcs.primitive_mode) {
5697 case GL_ISOLINES:
5698 stride = 2;
5699 outer_comps = 2;
5700 inner_comps = 0;
5701 break;
5702 case GL_TRIANGLES:
5703 stride = 4;
5704 outer_comps = 3;
5705 inner_comps = 1;
5706 break;
5707 case GL_QUADS:
5708 stride = 6;
5709 outer_comps = 4;
5710 inner_comps = 2;
5711 break;
5712 default:
5713 return;
5714 }
5715
5716 ac_nir_build_if(&if_ctx, ctx,
5717 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5718 invocation_id, ctx->i32zero, ""));
5719
5720 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5721 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5722
5723 mark_tess_output(ctx, true, tess_inner_index);
5724 mark_tess_output(ctx, true, tess_outer_index);
5725 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5726 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5727 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5728 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5729 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5730
5731 for (i = 0; i < 4; i++) {
5732 inner[i] = LLVMGetUndef(ctx->i32);
5733 outer[i] = LLVMGetUndef(ctx->i32);
5734 }
5735
5736 // LINES reverseal
5737 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5738 outer[0] = out[1] = lds_load(ctx, lds_outer);
5739 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5740 LLVMConstInt(ctx->i32, 1, false), "");
5741 outer[1] = out[0] = lds_load(ctx, lds_outer);
5742 } else {
5743 for (i = 0; i < outer_comps; i++) {
5744 outer[i] = out[i] =
5745 lds_load(ctx, lds_outer);
5746 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5747 LLVMConstInt(ctx->i32, 1, false), "");
5748 }
5749 for (i = 0; i < inner_comps; i++) {
5750 inner[i] = out[outer_comps+i] =
5751 lds_load(ctx, lds_inner);
5752 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5753 LLVMConstInt(ctx->i32, 1, false), "");
5754 }
5755 }
5756
5757 /* Convert the outputs to vectors for stores. */
5758 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5759 vec1 = NULL;
5760
5761 if (stride > 4)
5762 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5763
5764
5765 buffer = ctx->hs_ring_tess_factor;
5766 tf_base = ctx->tess_factor_offset;
5767 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5768 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5769
5770 ac_nir_build_if(&inner_if_ctx, ctx,
5771 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5772 rel_patch_id, ctx->i32zero, ""));
5773
5774 /* Store the dynamic HS control word. */
5775 ac_build_buffer_store_dword(&ctx->ac, buffer,
5776 LLVMConstInt(ctx->i32, 0x80000000, false),
5777 1, ctx->i32zero, tf_base,
5778 0, 1, 0, true, false);
5779 ac_nir_build_endif(&inner_if_ctx);
5780
5781 /* Store the tessellation factors. */
5782 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5783 MIN2(stride, 4), byteoffset, tf_base,
5784 4, 1, 0, true, false);
5785 if (vec1)
5786 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5787 stride - 4, byteoffset, tf_base,
5788 20, 1, 0, true, false);
5789
5790 //TODO store to offchip for TES to read - only if TES reads them
5791 if (1) {
5792 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5793 LLVMValueRef tf_inner_offset;
5794 unsigned param_outer, param_inner;
5795
5796 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5797 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5798 LLVMConstInt(ctx->i32, param_outer, 0));
5799
5800 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5801 util_next_power_of_two(outer_comps));
5802
5803 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5804 outer_comps, tf_outer_offset,
5805 ctx->oc_lds, 0, 1, 0, true, false);
5806 if (inner_comps) {
5807 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5808 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5809 LLVMConstInt(ctx->i32, param_inner, 0));
5810
5811 inner_vec = inner_comps == 1 ? inner[0] :
5812 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5813 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5814 inner_comps, tf_inner_offset,
5815 ctx->oc_lds, 0, 1, 0, true, false);
5816 }
5817 }
5818 ac_nir_build_endif(&if_ctx);
5819 }
5820
5821 static void
5822 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5823 {
5824 write_tess_factors(ctx);
5825 }
5826
5827 static bool
5828 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5829 LLVMValueRef *color, unsigned param, bool is_last,
5830 struct ac_export_args *args)
5831 {
5832 /* Export */
5833 si_llvm_init_export_args(ctx, color, param,
5834 args);
5835
5836 if (is_last) {
5837 args->valid_mask = 1; /* whether the EXEC mask is valid */
5838 args->done = 1; /* DONE bit */
5839 } else if (!args->enabled_channels)
5840 return false; /* unnecessary NULL export */
5841
5842 return true;
5843 }
5844
5845 static void
5846 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5847 LLVMValueRef depth, LLVMValueRef stencil,
5848 LLVMValueRef samplemask)
5849 {
5850 struct ac_export_args args;
5851
5852 args.enabled_channels = 0;
5853 args.valid_mask = 1;
5854 args.done = 1;
5855 args.target = V_008DFC_SQ_EXP_MRTZ;
5856 args.compr = false;
5857
5858 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5859 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5860 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5861 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5862
5863 if (depth) {
5864 args.out[0] = depth;
5865 args.enabled_channels |= 0x1;
5866 }
5867
5868 if (stencil) {
5869 args.out[1] = stencil;
5870 args.enabled_channels |= 0x2;
5871 }
5872
5873 if (samplemask) {
5874 args.out[2] = samplemask;
5875 args.enabled_channels |= 0x4;
5876 }
5877
5878 /* SI (except OLAND and HAINAN) has a bug that it only looks
5879 * at the X writemask component. */
5880 if (ctx->options->chip_class == SI &&
5881 ctx->options->family != CHIP_OLAND &&
5882 ctx->options->family != CHIP_HAINAN)
5883 args.enabled_channels |= 0x1;
5884
5885 ac_build_export(&ctx->ac, &args);
5886 }
5887
5888 static void
5889 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5890 {
5891 unsigned index = 0;
5892 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5893 struct ac_export_args color_args[8];
5894
5895 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5896 LLVMValueRef values[4];
5897
5898 if (!(ctx->output_mask & (1ull << i)))
5899 continue;
5900
5901 if (i == FRAG_RESULT_DEPTH) {
5902 ctx->shader_info->fs.writes_z = true;
5903 depth = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5904 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5905 } else if (i == FRAG_RESULT_STENCIL) {
5906 ctx->shader_info->fs.writes_stencil = true;
5907 stencil = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5908 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5909 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5910 ctx->shader_info->fs.writes_sample_mask = true;
5911 samplemask = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5912 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5913 } else {
5914 bool last = false;
5915 for (unsigned j = 0; j < 4; j++)
5916 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5917 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5918
5919 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5920 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5921
5922 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
5923 if (ret)
5924 index++;
5925 }
5926 }
5927
5928 for (unsigned i = 0; i < index; i++)
5929 ac_build_export(&ctx->ac, &color_args[i]);
5930 if (depth || stencil || samplemask)
5931 si_export_mrt_z(ctx, depth, stencil, samplemask);
5932 else if (!index) {
5933 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
5934 ac_build_export(&ctx->ac, &color_args[0]);
5935 }
5936
5937 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5938 }
5939
5940 static void
5941 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5942 {
5943 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5944 }
5945
5946 static void
5947 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
5948 LLVMValueRef *addrs)
5949 {
5950 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
5951
5952 switch (ctx->stage) {
5953 case MESA_SHADER_VERTEX:
5954 if (ctx->options->key.vs.as_ls)
5955 handle_ls_outputs_post(ctx);
5956 else if (ctx->options->key.vs.as_es)
5957 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5958 else
5959 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
5960 &ctx->shader_info->vs.outinfo);
5961 break;
5962 case MESA_SHADER_FRAGMENT:
5963 handle_fs_outputs_post(ctx);
5964 break;
5965 case MESA_SHADER_GEOMETRY:
5966 emit_gs_epilogue(ctx);
5967 break;
5968 case MESA_SHADER_TESS_CTRL:
5969 handle_tcs_outputs_post(ctx);
5970 break;
5971 case MESA_SHADER_TESS_EVAL:
5972 if (ctx->options->key.tes.as_es)
5973 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
5974 else
5975 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
5976 &ctx->shader_info->tes.outinfo);
5977 break;
5978 default:
5979 break;
5980 }
5981 }
5982
5983 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
5984 {
5985 LLVMPassManagerRef passmgr;
5986 /* Create the pass manager */
5987 passmgr = LLVMCreateFunctionPassManagerForModule(
5988 ctx->module);
5989
5990 /* This pass should eliminate all the load and store instructions */
5991 LLVMAddPromoteMemoryToRegisterPass(passmgr);
5992
5993 /* Add some optimization passes */
5994 LLVMAddScalarReplAggregatesPass(passmgr);
5995 LLVMAddLICMPass(passmgr);
5996 LLVMAddAggressiveDCEPass(passmgr);
5997 LLVMAddCFGSimplificationPass(passmgr);
5998 LLVMAddInstructionCombiningPass(passmgr);
5999
6000 /* Run the pass */
6001 LLVMInitializeFunctionPassManager(passmgr);
6002 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6003 LLVMFinalizeFunctionPassManager(passmgr);
6004
6005 LLVMDisposeBuilder(ctx->builder);
6006 LLVMDisposePassManager(passmgr);
6007 }
6008
6009 static void
6010 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6011 {
6012 struct ac_vs_output_info *outinfo;
6013
6014 switch (ctx->stage) {
6015 case MESA_SHADER_FRAGMENT:
6016 case MESA_SHADER_COMPUTE:
6017 case MESA_SHADER_TESS_CTRL:
6018 case MESA_SHADER_GEOMETRY:
6019 return;
6020 case MESA_SHADER_VERTEX:
6021 if (ctx->options->key.vs.as_ls ||
6022 ctx->options->key.vs.as_es)
6023 return;
6024 outinfo = &ctx->shader_info->vs.outinfo;
6025 break;
6026 case MESA_SHADER_TESS_EVAL:
6027 if (ctx->options->key.vs.as_es)
6028 return;
6029 outinfo = &ctx->shader_info->tes.outinfo;
6030 break;
6031 default:
6032 unreachable("Unhandled shader type");
6033 }
6034
6035 ac_optimize_vs_outputs(&ctx->ac,
6036 ctx->main_function,
6037 outinfo->vs_output_param_offset,
6038 VARYING_SLOT_MAX,
6039 &outinfo->param_exports);
6040 }
6041
6042 static void
6043 ac_setup_rings(struct nir_to_llvm_context *ctx)
6044 {
6045 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6046 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6047 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
6048 }
6049
6050 if (ctx->is_gs_copy_shader) {
6051 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
6052 }
6053 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6054 LLVMValueRef tmp;
6055 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
6056 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
6057
6058 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6059
6060 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
6061 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
6062 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6063 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
6064 }
6065
6066 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6067 ctx->stage == MESA_SHADER_TESS_EVAL) {
6068 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6069 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6070 }
6071 }
6072
6073 static unsigned
6074 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6075 const struct nir_shader *nir)
6076 {
6077 switch (nir->stage) {
6078 case MESA_SHADER_TESS_CTRL:
6079 return chip_class >= CIK ? 128 : 64;
6080 case MESA_SHADER_GEOMETRY:
6081 return 64;
6082 case MESA_SHADER_COMPUTE:
6083 break;
6084 default:
6085 return 0;
6086 }
6087
6088 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6089 nir->info.cs.local_size[1] *
6090 nir->info.cs.local_size[2];
6091 return max_workgroup_size;
6092 }
6093
6094 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6095 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6096 {
6097 struct ac_nir_context ctx = {};
6098 struct nir_function *func;
6099
6100 ctx.ac = *ac;
6101 ctx.abi = abi;
6102
6103 ctx.nctx = nctx;
6104 if (nctx)
6105 nctx->nir = &ctx;
6106
6107 ctx.stage = nir->stage;
6108
6109 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6110
6111 nir_foreach_variable(variable, &nir->outputs)
6112 handle_shader_output_decl(&ctx, nir, variable);
6113
6114 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6115 _mesa_key_pointer_equal);
6116 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6117 _mesa_key_pointer_equal);
6118 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6119 _mesa_key_pointer_equal);
6120
6121 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6122
6123 setup_locals(&ctx, func);
6124
6125 if (nir->stage == MESA_SHADER_COMPUTE)
6126 setup_shared(&ctx, nir);
6127
6128 visit_cf_list(&ctx, &func->impl->body);
6129 phi_post_pass(&ctx);
6130
6131 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6132 ctx.outputs);
6133
6134 free(ctx.locals);
6135 ralloc_free(ctx.defs);
6136 ralloc_free(ctx.phis);
6137 ralloc_free(ctx.vars);
6138
6139 if (nctx)
6140 nctx->nir = NULL;
6141 }
6142
6143 static
6144 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6145 struct nir_shader *nir,
6146 struct ac_shader_variant_info *shader_info,
6147 const struct ac_nir_compiler_options *options)
6148 {
6149 struct nir_to_llvm_context ctx = {0};
6150 unsigned i;
6151 ctx.options = options;
6152 ctx.shader_info = shader_info;
6153 ctx.context = LLVMContextCreate();
6154 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6155
6156 ac_llvm_context_init(&ctx.ac, ctx.context);
6157 ctx.ac.module = ctx.module;
6158
6159 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
6160
6161 memset(shader_info, 0, sizeof(*shader_info));
6162
6163 ac_nir_shader_info_pass(nir, options, &shader_info->info);
6164
6165 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6166
6167 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6168 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6169 LLVMSetDataLayout(ctx.module, data_layout_str);
6170 LLVMDisposeTargetData(data_layout);
6171 LLVMDisposeMessage(data_layout_str);
6172
6173 setup_types(&ctx);
6174
6175 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6176 ctx.ac.builder = ctx.builder;
6177 ctx.stage = nir->stage;
6178 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
6179
6180 for (i = 0; i < AC_UD_MAX_SETS; i++)
6181 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6182 for (i = 0; i < AC_UD_MAX_UD; i++)
6183 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6184
6185 create_function(&ctx);
6186
6187 if (nir->stage == MESA_SHADER_GEOMETRY) {
6188 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.i32, "gs_next_vertex");
6189
6190 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
6191 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
6192 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
6193 }
6194
6195 ac_setup_rings(&ctx);
6196
6197 ctx.num_output_clips = nir->info.clip_distance_array_size;
6198 ctx.num_output_culls = nir->info.cull_distance_array_size;
6199
6200 nir_foreach_variable(variable, &nir->inputs)
6201 handle_shader_input_decl(&ctx, variable);
6202
6203 if (nir->stage == MESA_SHADER_FRAGMENT)
6204 handle_fs_inputs_pre(&ctx, nir);
6205
6206 ctx.abi.chip_class = options->chip_class;
6207 ctx.abi.inputs = &ctx.inputs[0];
6208 ctx.abi.emit_outputs = handle_shader_outputs_post;
6209
6210 nir_foreach_variable(variable, &nir->outputs)
6211 scan_shader_output_decl(&ctx, variable);
6212
6213 ac_nir_translate(&ctx.ac, &ctx.abi, nir, &ctx);
6214
6215 LLVMBuildRetVoid(ctx.builder);
6216
6217 ac_llvm_finalize_module(&ctx);
6218
6219 ac_nir_eliminate_const_vs_outputs(&ctx);
6220
6221 if (nir->stage == MESA_SHADER_GEOMETRY) {
6222 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
6223 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6224 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6225 nir->info.gs.vertices_out;
6226 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
6227 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6228 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6229 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6230 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6231 }
6232
6233 return ctx.module;
6234 }
6235
6236 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6237 {
6238 unsigned *retval = (unsigned *)context;
6239 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6240 char *description = LLVMGetDiagInfoDescription(di);
6241
6242 if (severity == LLVMDSError) {
6243 *retval = 1;
6244 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6245 description);
6246 }
6247
6248 LLVMDisposeMessage(description);
6249 }
6250
6251 static unsigned ac_llvm_compile(LLVMModuleRef M,
6252 struct ac_shader_binary *binary,
6253 LLVMTargetMachineRef tm)
6254 {
6255 unsigned retval = 0;
6256 char *err;
6257 LLVMContextRef llvm_ctx;
6258 LLVMMemoryBufferRef out_buffer;
6259 unsigned buffer_size;
6260 const char *buffer_data;
6261 LLVMBool mem_err;
6262
6263 /* Setup Diagnostic Handler*/
6264 llvm_ctx = LLVMGetModuleContext(M);
6265
6266 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6267 &retval);
6268
6269 /* Compile IR*/
6270 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6271 &err, &out_buffer);
6272
6273 /* Process Errors/Warnings */
6274 if (mem_err) {
6275 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6276 free(err);
6277 retval = 1;
6278 goto out;
6279 }
6280
6281 /* Extract Shader Code*/
6282 buffer_size = LLVMGetBufferSize(out_buffer);
6283 buffer_data = LLVMGetBufferStart(out_buffer);
6284
6285 ac_elf_read(buffer_data, buffer_size, binary);
6286
6287 /* Clean up */
6288 LLVMDisposeMemoryBuffer(out_buffer);
6289
6290 out:
6291 return retval;
6292 }
6293
6294 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6295 LLVMModuleRef llvm_module,
6296 struct ac_shader_binary *binary,
6297 struct ac_shader_config *config,
6298 struct ac_shader_variant_info *shader_info,
6299 gl_shader_stage stage,
6300 bool dump_shader, bool supports_spill)
6301 {
6302 if (dump_shader)
6303 ac_dump_module(llvm_module);
6304
6305 memset(binary, 0, sizeof(*binary));
6306 int v = ac_llvm_compile(llvm_module, binary, tm);
6307 if (v) {
6308 fprintf(stderr, "compile failed\n");
6309 }
6310
6311 if (dump_shader)
6312 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6313
6314 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6315
6316 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6317 LLVMDisposeModule(llvm_module);
6318 LLVMContextDispose(ctx);
6319
6320 if (stage == MESA_SHADER_FRAGMENT) {
6321 shader_info->num_input_vgprs = 0;
6322 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6323 shader_info->num_input_vgprs += 2;
6324 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6325 shader_info->num_input_vgprs += 2;
6326 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6327 shader_info->num_input_vgprs += 2;
6328 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6329 shader_info->num_input_vgprs += 3;
6330 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6331 shader_info->num_input_vgprs += 2;
6332 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6333 shader_info->num_input_vgprs += 2;
6334 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6335 shader_info->num_input_vgprs += 2;
6336 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6337 shader_info->num_input_vgprs += 1;
6338 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6339 shader_info->num_input_vgprs += 1;
6340 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6341 shader_info->num_input_vgprs += 1;
6342 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6343 shader_info->num_input_vgprs += 1;
6344 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6345 shader_info->num_input_vgprs += 1;
6346 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6347 shader_info->num_input_vgprs += 1;
6348 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6349 shader_info->num_input_vgprs += 1;
6350 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6351 shader_info->num_input_vgprs += 1;
6352 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6353 shader_info->num_input_vgprs += 1;
6354 }
6355 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6356
6357 /* +3 for scratch wave offset and VCC */
6358 config->num_sgprs = MAX2(config->num_sgprs,
6359 shader_info->num_input_sgprs + 3);
6360 }
6361
6362 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6363 struct ac_shader_binary *binary,
6364 struct ac_shader_config *config,
6365 struct ac_shader_variant_info *shader_info,
6366 struct nir_shader *nir,
6367 const struct ac_nir_compiler_options *options,
6368 bool dump_shader)
6369 {
6370
6371 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6372 options);
6373
6374 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6375 switch (nir->stage) {
6376 case MESA_SHADER_COMPUTE:
6377 for (int i = 0; i < 3; ++i)
6378 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6379 break;
6380 case MESA_SHADER_FRAGMENT:
6381 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6382 break;
6383 case MESA_SHADER_GEOMETRY:
6384 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6385 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6386 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6387 shader_info->gs.invocations = nir->info.gs.invocations;
6388 break;
6389 case MESA_SHADER_TESS_EVAL:
6390 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6391 shader_info->tes.spacing = nir->info.tess.spacing;
6392 shader_info->tes.ccw = nir->info.tess.ccw;
6393 shader_info->tes.point_mode = nir->info.tess.point_mode;
6394 shader_info->tes.as_es = options->key.tes.as_es;
6395 break;
6396 case MESA_SHADER_TESS_CTRL:
6397 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6398 break;
6399 case MESA_SHADER_VERTEX:
6400 shader_info->vs.as_es = options->key.vs.as_es;
6401 shader_info->vs.as_ls = options->key.vs.as_ls;
6402 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6403 if (options->key.vs.as_ls)
6404 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6405 break;
6406 default:
6407 break;
6408 }
6409 }
6410
6411 static void
6412 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6413 {
6414 LLVMValueRef args[9];
6415 args[0] = ctx->gsvs_ring;
6416 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6417 args[3] = ctx->i32zero;
6418 args[4] = ctx->i32one; /* OFFEN */
6419 args[5] = ctx->i32zero; /* IDXEN */
6420 args[6] = ctx->i32one; /* GLC */
6421 args[7] = ctx->i32one; /* SLC */
6422 args[8] = ctx->i32zero; /* TFE */
6423
6424 int idx = 0;
6425
6426 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6427 int length = 4;
6428 int slot = idx;
6429 int slot_inc = 1;
6430 if (!(ctx->output_mask & (1ull << i)))
6431 continue;
6432
6433 if (i == VARYING_SLOT_CLIP_DIST0) {
6434 /* unpack clip and cull from a single set of slots */
6435 length = ctx->num_output_clips + ctx->num_output_culls;
6436 if (length > 4)
6437 slot_inc = 2;
6438 }
6439
6440 for (unsigned j = 0; j < length; j++) {
6441 LLVMValueRef value;
6442 args[2] = LLVMConstInt(ctx->i32,
6443 (slot * 4 + j) *
6444 ctx->gs_max_out_vertices * 16 * 4, false);
6445
6446 value = ac_build_intrinsic(&ctx->ac,
6447 "llvm.SI.buffer.load.dword.i32.i32",
6448 ctx->i32, args, 9,
6449 AC_FUNC_ATTR_READONLY |
6450 AC_FUNC_ATTR_LEGACY);
6451
6452 LLVMBuildStore(ctx->builder,
6453 to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6454 }
6455 idx += slot_inc;
6456 }
6457 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6458 }
6459
6460 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6461 struct nir_shader *geom_shader,
6462 struct ac_shader_binary *binary,
6463 struct ac_shader_config *config,
6464 struct ac_shader_variant_info *shader_info,
6465 const struct ac_nir_compiler_options *options,
6466 bool dump_shader)
6467 {
6468 struct nir_to_llvm_context ctx = {0};
6469 ctx.context = LLVMContextCreate();
6470 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6471 ctx.options = options;
6472 ctx.shader_info = shader_info;
6473
6474 ac_llvm_context_init(&ctx.ac, ctx.context);
6475 ctx.ac.module = ctx.module;
6476
6477 ctx.is_gs_copy_shader = true;
6478 LLVMSetTarget(ctx.module, "amdgcn--");
6479 setup_types(&ctx);
6480
6481 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6482 ctx.ac.builder = ctx.builder;
6483 ctx.stage = MESA_SHADER_VERTEX;
6484
6485 create_function(&ctx);
6486
6487 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6488 ac_setup_rings(&ctx);
6489
6490 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6491 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6492
6493 struct ac_nir_context nir_ctx = {};
6494 nir_ctx.ac = ctx.ac;
6495 nir_ctx.abi = &ctx.abi;
6496
6497 nir_ctx.nctx = &ctx;
6498 ctx.nir = &nir_ctx;
6499
6500 nir_foreach_variable(variable, &geom_shader->outputs) {
6501 scan_shader_output_decl(&ctx, variable);
6502 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6503 }
6504
6505 ac_gs_copy_shader_emit(&ctx);
6506
6507 ctx.nir = NULL;
6508
6509 LLVMBuildRetVoid(ctx.builder);
6510
6511 ac_llvm_finalize_module(&ctx);
6512
6513 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6514 MESA_SHADER_VERTEX,
6515 dump_shader, options->supports_spill);
6516 }