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radv: fix interpolation at wrong place for offset interp
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef gsvs_ring_stride;
87 LLVMValueRef gsvs_num_entries;
88 LLVMValueRef gs2vs_offset;
89 LLVMValueRef gs_wave_id;
90 LLVMValueRef gs_vtx_offset[6];
91 LLVMValueRef gs_prim_id, gs_invocation_id;
92
93 LLVMValueRef esgs_ring;
94 LLVMValueRef gsvs_ring;
95
96 LLVMValueRef prim_mask;
97 LLVMValueRef sample_positions;
98 LLVMValueRef persp_sample, persp_center, persp_centroid;
99 LLVMValueRef linear_sample, linear_center, linear_centroid;
100 LLVMValueRef front_face;
101 LLVMValueRef ancillary;
102 LLVMValueRef frag_pos[4];
103
104 LLVMBasicBlockRef continue_block;
105 LLVMBasicBlockRef break_block;
106
107 LLVMTypeRef i1;
108 LLVMTypeRef i8;
109 LLVMTypeRef i16;
110 LLVMTypeRef i32;
111 LLVMTypeRef i64;
112 LLVMTypeRef v2i32;
113 LLVMTypeRef v3i32;
114 LLVMTypeRef v4i32;
115 LLVMTypeRef v8i32;
116 LLVMTypeRef f64;
117 LLVMTypeRef f32;
118 LLVMTypeRef f16;
119 LLVMTypeRef v2f32;
120 LLVMTypeRef v4f32;
121 LLVMTypeRef v16i8;
122 LLVMTypeRef voidt;
123
124 LLVMValueRef i32zero;
125 LLVMValueRef i32one;
126 LLVMValueRef f32zero;
127 LLVMValueRef f32one;
128 LLVMValueRef v4f32empty;
129
130 unsigned uniform_md_kind;
131 LLVMValueRef empty_md;
132 gl_shader_stage stage;
133
134 LLVMValueRef lds;
135 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
136 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
137
138 LLVMValueRef shared_memory;
139 uint64_t input_mask;
140 uint64_t output_mask;
141 int num_locals;
142 LLVMValueRef *locals;
143 bool has_ddxy;
144 uint8_t num_input_clips;
145 uint8_t num_input_culls;
146 uint8_t num_output_clips;
147 uint8_t num_output_culls;
148
149 bool has_ds_bpermute;
150
151 bool is_gs_copy_shader;
152 LLVMValueRef gs_next_vertex;
153 unsigned gs_max_out_vertices;
154 };
155
156 struct ac_tex_info {
157 LLVMValueRef args[12];
158 int arg_count;
159 LLVMTypeRef dst_type;
160 bool has_offset;
161 };
162
163 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
164 nir_deref_var *deref,
165 enum desc_type desc_type);
166 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
167 {
168 return (index * 4) + chan;
169 }
170
171 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
172 {
173 if (slot == VARYING_SLOT_POS)
174 return 0;
175 if (slot == VARYING_SLOT_PSIZ)
176 return 1;
177 if (slot == VARYING_SLOT_CLIP_DIST0 ||
178 slot == VARYING_SLOT_CULL_DIST0)
179 return 2;
180 if (slot == VARYING_SLOT_CLIP_DIST1 ||
181 slot == VARYING_SLOT_CULL_DIST1)
182 return 3;
183 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
184 return 4 + (slot - VARYING_SLOT_VAR0);
185 unreachable("illegal slot in get unique index\n");
186 }
187
188 static unsigned llvm_get_type_size(LLVMTypeRef type)
189 {
190 LLVMTypeKind kind = LLVMGetTypeKind(type);
191
192 switch (kind) {
193 case LLVMIntegerTypeKind:
194 return LLVMGetIntTypeWidth(type) / 8;
195 case LLVMFloatTypeKind:
196 return 4;
197 case LLVMPointerTypeKind:
198 return 8;
199 case LLVMVectorTypeKind:
200 return LLVMGetVectorSize(type) *
201 llvm_get_type_size(LLVMGetElementType(type));
202 default:
203 assert(0);
204 return 0;
205 }
206 }
207
208 static void set_llvm_calling_convention(LLVMValueRef func,
209 gl_shader_stage stage)
210 {
211 enum radeon_llvm_calling_convention calling_conv;
212
213 switch (stage) {
214 case MESA_SHADER_VERTEX:
215 case MESA_SHADER_TESS_CTRL:
216 case MESA_SHADER_TESS_EVAL:
217 calling_conv = RADEON_LLVM_AMDGPU_VS;
218 break;
219 case MESA_SHADER_GEOMETRY:
220 calling_conv = RADEON_LLVM_AMDGPU_GS;
221 break;
222 case MESA_SHADER_FRAGMENT:
223 calling_conv = RADEON_LLVM_AMDGPU_PS;
224 break;
225 case MESA_SHADER_COMPUTE:
226 calling_conv = RADEON_LLVM_AMDGPU_CS;
227 break;
228 default:
229 unreachable("Unhandle shader type");
230 }
231
232 LLVMSetFunctionCallConv(func, calling_conv);
233 }
234
235 static LLVMValueRef
236 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
237 LLVMBuilderRef builder, LLVMTypeRef *return_types,
238 unsigned num_return_elems, LLVMTypeRef *param_types,
239 unsigned param_count, unsigned array_params_mask,
240 unsigned sgpr_params, bool unsafe_math)
241 {
242 LLVMTypeRef main_function_type, ret_type;
243 LLVMBasicBlockRef main_function_body;
244
245 if (num_return_elems)
246 ret_type = LLVMStructTypeInContext(ctx, return_types,
247 num_return_elems, true);
248 else
249 ret_type = LLVMVoidTypeInContext(ctx);
250
251 /* Setup the function */
252 main_function_type =
253 LLVMFunctionType(ret_type, param_types, param_count, 0);
254 LLVMValueRef main_function =
255 LLVMAddFunction(module, "main", main_function_type);
256 main_function_body =
257 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
258 LLVMPositionBuilderAtEnd(builder, main_function_body);
259
260 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
261 for (unsigned i = 0; i < sgpr_params; ++i) {
262 if (array_params_mask & (1 << i)) {
263 LLVMValueRef P = LLVMGetParam(main_function, i);
264 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_BYVAL);
265 ac_add_attr_dereferenceable(P, UINT64_MAX);
266 }
267 else {
268 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_INREG);
269 }
270 }
271
272 if (unsafe_math) {
273 /* These were copied from some LLVM test. */
274 LLVMAddTargetDependentFunctionAttr(main_function,
275 "less-precise-fpmad",
276 "true");
277 LLVMAddTargetDependentFunctionAttr(main_function,
278 "no-infs-fp-math",
279 "true");
280 LLVMAddTargetDependentFunctionAttr(main_function,
281 "no-nans-fp-math",
282 "true");
283 LLVMAddTargetDependentFunctionAttr(main_function,
284 "unsafe-fp-math",
285 "true");
286 }
287 return main_function;
288 }
289
290 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
291 {
292 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
293 CONST_ADDR_SPACE);
294 }
295
296 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
297 int idx,
298 LLVMTypeRef type)
299 {
300 LLVMValueRef offset;
301 LLVMValueRef ptr;
302 int addr_space;
303
304 offset = LLVMConstInt(ctx->i32, idx, false);
305
306 ptr = ctx->shared_memory;
307 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
308 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
309 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
310 return ptr;
311 }
312
313 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
314 {
315 if (t == ctx->f16 || t == ctx->i16)
316 return ctx->i16;
317 else if (t == ctx->f32 || t == ctx->i32)
318 return ctx->i32;
319 else if (t == ctx->f64 || t == ctx->i64)
320 return ctx->i64;
321 else
322 unreachable("Unhandled integer size");
323 }
324
325 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
326 {
327 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
328 LLVMTypeRef elem_type = LLVMGetElementType(t);
329 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
330 LLVMGetVectorSize(t));
331 }
332 return to_integer_type_scalar(ctx, t);
333 }
334
335 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
336 {
337 LLVMTypeRef type = LLVMTypeOf(v);
338 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
339 }
340
341 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
342 {
343 if (t == ctx->i16 || t == ctx->f16)
344 return ctx->f16;
345 else if (t == ctx->i32 || t == ctx->f32)
346 return ctx->f32;
347 else if (t == ctx->i64 || t == ctx->f64)
348 return ctx->f64;
349 else
350 unreachable("Unhandled float size");
351 }
352
353 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
354 {
355 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
356 LLVMTypeRef elem_type = LLVMGetElementType(t);
357 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
358 LLVMGetVectorSize(t));
359 }
360 return to_float_type_scalar(ctx, t);
361 }
362
363 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
364 {
365 LLVMTypeRef type = LLVMTypeOf(v);
366 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
367 }
368
369 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
370 {
371 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
372 type = LLVMGetElementType(type);
373
374 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
375 return LLVMGetIntTypeWidth(type);
376
377 if (type == ctx->f16)
378 return 16;
379 if (type == ctx->f32)
380 return 32;
381 if (type == ctx->f64)
382 return 64;
383
384 unreachable("Unhandled type kind in get_elem_bits");
385 }
386
387 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
388 LLVMValueRef param, unsigned rshift,
389 unsigned bitwidth)
390 {
391 LLVMValueRef value = param;
392 if (rshift)
393 value = LLVMBuildLShr(ctx->builder, value,
394 LLVMConstInt(ctx->i32, rshift, false), "");
395
396 if (rshift + bitwidth < 32) {
397 unsigned mask = (1 << bitwidth) - 1;
398 value = LLVMBuildAnd(ctx->builder, value,
399 LLVMConstInt(ctx->i32, mask, false), "");
400 }
401 return value;
402 }
403
404 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
405 {
406 ud_info->sgpr_idx = sgpr_idx;
407 ud_info->num_sgprs = num_sgprs;
408 ud_info->indirect = false;
409 ud_info->indirect_offset = 0;
410 }
411
412 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
413 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
414 {
415 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
416 }
417
418 #if 0
419 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
420 uint32_t indirect_offset)
421 {
422 ud_info->sgpr_idx = sgpr_idx;
423 ud_info->num_sgprs = num_sgprs;
424 ud_info->indirect = true;
425 ud_info->indirect_offset = indirect_offset;
426 }
427 #endif
428
429 static void create_function(struct nir_to_llvm_context *ctx)
430 {
431 LLVMTypeRef arg_types[23];
432 unsigned arg_idx = 0;
433 unsigned array_params_mask = 0;
434 unsigned sgpr_count = 0, user_sgpr_count;
435 unsigned i;
436 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
437 unsigned user_sgpr_idx;
438 bool need_push_constants;
439 bool need_ring_offsets = false;
440
441 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
442 if (ctx->stage == MESA_SHADER_GEOMETRY ||
443 ctx->stage == MESA_SHADER_VERTEX ||
444 ctx->is_gs_copy_shader)
445 need_ring_offsets = true;
446
447 need_push_constants = true;
448 if (!ctx->options->layout)
449 need_push_constants = false;
450 else if (!ctx->options->layout->push_constant_size &&
451 !ctx->options->layout->dynamic_offset_count)
452 need_push_constants = false;
453
454 if (need_ring_offsets && !ctx->options->supports_spill) {
455 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
456 }
457
458 /* 1 for each descriptor set */
459 for (unsigned i = 0; i < num_sets; ++i) {
460 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
461 array_params_mask |= (1 << arg_idx);
462 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
463 }
464 }
465
466 if (need_push_constants) {
467 /* 1 for push constants and dynamic descriptors */
468 array_params_mask |= (1 << arg_idx);
469 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
470 }
471
472 switch (ctx->stage) {
473 case MESA_SHADER_COMPUTE:
474 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
475 user_sgpr_count = arg_idx;
476 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
477 arg_types[arg_idx++] = ctx->i32;
478 sgpr_count = arg_idx;
479
480 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
481 break;
482 case MESA_SHADER_VERTEX:
483 if (!ctx->is_gs_copy_shader) {
484 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
485 arg_types[arg_idx++] = ctx->i32; // base vertex
486 arg_types[arg_idx++] = ctx->i32; // start instance
487 arg_types[arg_idx++] = ctx->i32; // draw index
488 }
489 user_sgpr_count = arg_idx;
490 if (ctx->options->key.vs.as_es)
491 arg_types[arg_idx++] = ctx->i32; //es2gs offset
492 sgpr_count = arg_idx;
493 arg_types[arg_idx++] = ctx->i32; // vertex id
494 if (!ctx->is_gs_copy_shader) {
495 arg_types[arg_idx++] = ctx->i32; // rel auto id
496 arg_types[arg_idx++] = ctx->i32; // vs prim id
497 arg_types[arg_idx++] = ctx->i32; // instance id
498 }
499 break;
500 case MESA_SHADER_GEOMETRY:
501 arg_types[arg_idx++] = ctx->i32; // gsvs stride
502 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
503 user_sgpr_count = arg_idx;
504 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
505 arg_types[arg_idx++] = ctx->i32; // wave id
506 sgpr_count = arg_idx;
507 arg_types[arg_idx++] = ctx->i32; // vtx0
508 arg_types[arg_idx++] = ctx->i32; // vtx1
509 arg_types[arg_idx++] = ctx->i32; // prim id
510 arg_types[arg_idx++] = ctx->i32; // vtx2
511 arg_types[arg_idx++] = ctx->i32; // vtx3
512 arg_types[arg_idx++] = ctx->i32; // vtx4
513 arg_types[arg_idx++] = ctx->i32; // vtx5
514 arg_types[arg_idx++] = ctx->i32; // GS instance id
515 break;
516 case MESA_SHADER_FRAGMENT:
517 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
518 user_sgpr_count = arg_idx;
519 arg_types[arg_idx++] = ctx->i32; /* prim mask */
520 sgpr_count = arg_idx;
521 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
522 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
523 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
524 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
525 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
526 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
527 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
528 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
529 arg_types[arg_idx++] = ctx->f32; /* pos x float */
530 arg_types[arg_idx++] = ctx->f32; /* pos y float */
531 arg_types[arg_idx++] = ctx->f32; /* pos z float */
532 arg_types[arg_idx++] = ctx->f32; /* pos w float */
533 arg_types[arg_idx++] = ctx->i32; /* front face */
534 arg_types[arg_idx++] = ctx->i32; /* ancillary */
535 arg_types[arg_idx++] = ctx->f32; /* sample coverage */
536 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
537 break;
538 default:
539 unreachable("Shader stage not implemented");
540 }
541
542 ctx->main_function = create_llvm_function(
543 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
544 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
545 set_llvm_calling_convention(ctx->main_function, ctx->stage);
546
547 ctx->shader_info->num_input_sgprs = 0;
548 ctx->shader_info->num_input_vgprs = 0;
549
550 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
551 for (i = 0; i < user_sgpr_count; i++)
552 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
553
554 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
555 for (; i < sgpr_count; i++)
556 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
557
558 if (ctx->stage != MESA_SHADER_FRAGMENT)
559 for (; i < arg_idx; ++i)
560 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
561
562 arg_idx = 0;
563 user_sgpr_idx = 0;
564
565 if (ctx->options->supports_spill || need_ring_offsets) {
566 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
567 user_sgpr_idx += 2;
568 if (ctx->options->supports_spill) {
569 ctx->ring_offsets = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
570 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
571 NULL, 0, AC_FUNC_ATTR_READNONE);
572 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
573 const_array(ctx->v16i8, 8), "");
574 } else
575 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
576 }
577
578 for (unsigned i = 0; i < num_sets; ++i) {
579 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
580 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
581 user_sgpr_idx += 2;
582 ctx->descriptor_sets[i] =
583 LLVMGetParam(ctx->main_function, arg_idx++);
584 } else
585 ctx->descriptor_sets[i] = NULL;
586 }
587
588 if (need_push_constants) {
589 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
590 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
591 user_sgpr_idx += 2;
592 }
593
594 switch (ctx->stage) {
595 case MESA_SHADER_COMPUTE:
596 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
597 user_sgpr_idx += 3;
598 ctx->num_work_groups =
599 LLVMGetParam(ctx->main_function, arg_idx++);
600 ctx->workgroup_ids =
601 LLVMGetParam(ctx->main_function, arg_idx++);
602 ctx->tg_size =
603 LLVMGetParam(ctx->main_function, arg_idx++);
604 ctx->local_invocation_ids =
605 LLVMGetParam(ctx->main_function, arg_idx++);
606 break;
607 case MESA_SHADER_VERTEX:
608 if (!ctx->is_gs_copy_shader) {
609 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
610 user_sgpr_idx += 2;
611 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
612 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
613 user_sgpr_idx += 3;
614 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
615 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
616 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
617 }
618 if (ctx->options->key.vs.as_es)
619 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
620 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
621 if (!ctx->is_gs_copy_shader) {
622 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
623 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
624 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
625 }
626 break;
627 case MESA_SHADER_GEOMETRY:
628 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
629 user_sgpr_idx += 2;
630 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
631 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
632 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
633 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
634 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
635 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
636 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
637 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
638 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
639 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
640 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
641 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
642 break;
643 case MESA_SHADER_FRAGMENT:
644 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
645 user_sgpr_idx += 2;
646 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
647 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
648 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
649 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
650 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
651 arg_idx++;
652 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
653 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
654 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
655 arg_idx++; /* line stipple */
656 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
657 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
658 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
659 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
660 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
661 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
662 break;
663 default:
664 unreachable("Shader stage not implemented");
665 }
666 }
667
668 static void setup_types(struct nir_to_llvm_context *ctx)
669 {
670 LLVMValueRef args[4];
671
672 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
673 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
674 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
675 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
676 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
677 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
678 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
679 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
680 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
681 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
682 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
683 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
684 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
685 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
686 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
687 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
688
689 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
690 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
691 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
692 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
693
694 args[0] = ctx->f32zero;
695 args[1] = ctx->f32zero;
696 args[2] = ctx->f32zero;
697 args[3] = ctx->f32one;
698 ctx->v4f32empty = LLVMConstVector(args, 4);
699
700 ctx->uniform_md_kind =
701 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
702 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
703
704 args[0] = LLVMConstReal(ctx->f32, 2.5);
705 }
706
707 static int get_llvm_num_components(LLVMValueRef value)
708 {
709 LLVMTypeRef type = LLVMTypeOf(value);
710 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
711 ? LLVMGetVectorSize(type)
712 : 1;
713 return num_components;
714 }
715
716 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
717 LLVMValueRef value,
718 int index)
719 {
720 int count = get_llvm_num_components(value);
721
722 assert(index < count);
723 if (count == 1)
724 return value;
725
726 return LLVMBuildExtractElement(ctx->builder, value,
727 LLVMConstInt(ctx->i32, index, false), "");
728 }
729
730 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
731 LLVMValueRef value, unsigned count)
732 {
733 unsigned num_components = get_llvm_num_components(value);
734 if (count == num_components)
735 return value;
736
737 LLVMValueRef masks[] = {
738 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
739 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
740
741 if (count == 1)
742 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
743 "");
744
745 LLVMValueRef swizzle = LLVMConstVector(masks, count);
746 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
747 }
748
749 static void
750 build_store_values_extended(struct nir_to_llvm_context *ctx,
751 LLVMValueRef *values,
752 unsigned value_count,
753 unsigned value_stride,
754 LLVMValueRef vec)
755 {
756 LLVMBuilderRef builder = ctx->builder;
757 unsigned i;
758
759 if (value_count == 1) {
760 LLVMBuildStore(builder, vec, values[0]);
761 return;
762 }
763
764 for (i = 0; i < value_count; i++) {
765 LLVMValueRef ptr = values[i * value_stride];
766 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
767 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
768 LLVMBuildStore(builder, value, ptr);
769 }
770 }
771
772 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
773 nir_ssa_def *def)
774 {
775 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
776 if (def->num_components > 1) {
777 type = LLVMVectorType(type, def->num_components);
778 }
779 return type;
780 }
781
782 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
783 {
784 assert(src.is_ssa);
785 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
786 return (LLVMValueRef)entry->data;
787 }
788
789
790 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
791 struct nir_block *b)
792 {
793 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
794 return (LLVMBasicBlockRef)entry->data;
795 }
796
797 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
798 nir_alu_src src,
799 unsigned num_components)
800 {
801 LLVMValueRef value = get_src(ctx, src.src);
802 bool need_swizzle = false;
803
804 assert(value);
805 LLVMTypeRef type = LLVMTypeOf(value);
806 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
807 ? LLVMGetVectorSize(type)
808 : 1;
809
810 for (unsigned i = 0; i < num_components; ++i) {
811 assert(src.swizzle[i] < src_components);
812 if (src.swizzle[i] != i)
813 need_swizzle = true;
814 }
815
816 if (need_swizzle || num_components != src_components) {
817 LLVMValueRef masks[] = {
818 LLVMConstInt(ctx->i32, src.swizzle[0], false),
819 LLVMConstInt(ctx->i32, src.swizzle[1], false),
820 LLVMConstInt(ctx->i32, src.swizzle[2], false),
821 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
822
823 if (src_components > 1 && num_components == 1) {
824 value = LLVMBuildExtractElement(ctx->builder, value,
825 masks[0], "");
826 } else if (src_components == 1 && num_components > 1) {
827 LLVMValueRef values[] = {value, value, value, value};
828 value = ac_build_gather_values(&ctx->ac, values, num_components);
829 } else {
830 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
831 value = LLVMBuildShuffleVector(ctx->builder, value, value,
832 swizzle, "");
833 }
834 }
835 assert(!src.negate);
836 assert(!src.abs);
837 return value;
838 }
839
840 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
841 LLVMIntPredicate pred, LLVMValueRef src0,
842 LLVMValueRef src1)
843 {
844 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
845 return LLVMBuildSelect(ctx->builder, result,
846 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
847 LLVMConstInt(ctx->i32, 0, false), "");
848 }
849
850 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
851 LLVMRealPredicate pred, LLVMValueRef src0,
852 LLVMValueRef src1)
853 {
854 LLVMValueRef result;
855 src0 = to_float(ctx, src0);
856 src1 = to_float(ctx, src1);
857 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
858 return LLVMBuildSelect(ctx->builder, result,
859 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
860 LLVMConstInt(ctx->i32, 0, false), "");
861 }
862
863 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
864 const char *intrin,
865 LLVMTypeRef result_type,
866 LLVMValueRef src0)
867 {
868 char name[64];
869 LLVMValueRef params[] = {
870 to_float(ctx, src0),
871 };
872
873 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
874 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
875 }
876
877 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
878 const char *intrin,
879 LLVMTypeRef result_type,
880 LLVMValueRef src0, LLVMValueRef src1)
881 {
882 char name[64];
883 LLVMValueRef params[] = {
884 to_float(ctx, src0),
885 to_float(ctx, src1),
886 };
887
888 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
889 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
890 }
891
892 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
893 const char *intrin,
894 LLVMTypeRef result_type,
895 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
896 {
897 char name[64];
898 LLVMValueRef params[] = {
899 to_float(ctx, src0),
900 to_float(ctx, src1),
901 to_float(ctx, src2),
902 };
903
904 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
905 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
906 }
907
908 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
909 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
910 {
911 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
912 ctx->i32zero, "");
913 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
914 }
915
916 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
917 LLVMValueRef src0)
918 {
919 LLVMValueRef params[2] = {
920 src0,
921
922 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
923 * add special code to check for x=0. The reason is that
924 * the LLVM behavior for x=0 is different from what we
925 * need here.
926 *
927 * The hardware already implements the correct behavior.
928 */
929 LLVMConstInt(ctx->i32, 1, false),
930 };
931 return ac_emit_llvm_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
932 }
933
934 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
935 LLVMValueRef src0)
936 {
937 return ac_emit_imsb(&ctx->ac, src0, ctx->i32);
938 }
939
940 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
941 LLVMValueRef src0)
942 {
943 return ac_emit_umsb(&ctx->ac, src0, ctx->i32);
944 }
945
946 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
947 LLVMIntPredicate pred,
948 LLVMValueRef src0, LLVMValueRef src1)
949 {
950 return LLVMBuildSelect(ctx->builder,
951 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
952 src0,
953 src1, "");
954
955 }
956 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
957 LLVMValueRef src0)
958 {
959 return emit_minmax_int(ctx, LLVMIntSGT, src0,
960 LLVMBuildNeg(ctx->builder, src0, ""));
961 }
962
963 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
964 LLVMValueRef src0)
965 {
966 LLVMValueRef cmp, val;
967
968 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
969 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
970 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
971 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
972 return val;
973 }
974
975 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
976 LLVMValueRef src0)
977 {
978 LLVMValueRef cmp, val;
979
980 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
981 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
982 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
983 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
984 return val;
985 }
986
987 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
988 LLVMValueRef src0)
989 {
990 const char *intr = "llvm.floor.f32";
991 LLVMValueRef fsrc0 = to_float(ctx, src0);
992 LLVMValueRef params[] = {
993 fsrc0,
994 };
995 LLVMValueRef floor = ac_emit_llvm_intrinsic(&ctx->ac, intr,
996 ctx->f32, params, 1,
997 AC_FUNC_ATTR_READNONE);
998 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
999 }
1000
1001 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1002 const char *intrin,
1003 LLVMValueRef src0, LLVMValueRef src1)
1004 {
1005 LLVMTypeRef ret_type;
1006 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1007 LLVMValueRef res;
1008 LLVMValueRef params[] = { src0, src1 };
1009 ret_type = LLVMStructTypeInContext(ctx->context, types,
1010 2, true);
1011
1012 res = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ret_type,
1013 params, 2, AC_FUNC_ATTR_READNONE);
1014
1015 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1016 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1017 return res;
1018 }
1019
1020 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1021 LLVMValueRef src0)
1022 {
1023 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1024 }
1025
1026 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1027 LLVMValueRef src0, LLVMValueRef src1)
1028 {
1029 LLVMValueRef dst64, result;
1030 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1031 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1032
1033 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1034 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1035 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1036 return result;
1037 }
1038
1039 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1040 LLVMValueRef src0, LLVMValueRef src1)
1041 {
1042 LLVMValueRef dst64, result;
1043 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1044 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1045
1046 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1047 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1048 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1049 return result;
1050 }
1051
1052 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1053 const char *intrin,
1054 LLVMValueRef srcs[3])
1055 {
1056 LLVMValueRef result;
1057 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1058 result = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->i32, srcs, 3, AC_FUNC_ATTR_READNONE);
1059
1060 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1061 return result;
1062 }
1063
1064 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1065 LLVMValueRef src0, LLVMValueRef src1,
1066 LLVMValueRef src2, LLVMValueRef src3)
1067 {
1068 LLVMValueRef bfi_args[3], result;
1069
1070 bfi_args[0] = LLVMBuildShl(ctx->builder,
1071 LLVMBuildSub(ctx->builder,
1072 LLVMBuildShl(ctx->builder,
1073 ctx->i32one,
1074 src3, ""),
1075 ctx->i32one, ""),
1076 src2, "");
1077 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1078 bfi_args[2] = src0;
1079
1080 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1081
1082 /* Calculate:
1083 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1084 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1085 */
1086 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1087 LLVMBuildAnd(ctx->builder, bfi_args[0],
1088 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1089
1090 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1091 return result;
1092 }
1093
1094 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1095 LLVMValueRef src0)
1096 {
1097 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1098 int i;
1099 LLVMValueRef comp[2];
1100
1101 src0 = to_float(ctx, src0);
1102 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1103 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1104 for (i = 0; i < 2; i++) {
1105 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1106 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1107 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1108 }
1109
1110 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1111 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1112
1113 return comp[0];
1114 }
1115
1116 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1117 LLVMValueRef src0)
1118 {
1119 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1120 LLVMValueRef temps[2], result, val;
1121 int i;
1122
1123 for (i = 0; i < 2; i++) {
1124 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1125 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1126 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1127 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1128 }
1129
1130 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1131 ctx->i32zero, "");
1132 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1133 ctx->i32one, "");
1134 return result;
1135 }
1136
1137 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1138 nir_op op,
1139 LLVMValueRef src0)
1140 {
1141 unsigned mask;
1142 int idx;
1143 LLVMValueRef result;
1144 ctx->has_ddxy = true;
1145
1146 if (!ctx->lds && !ctx->has_ds_bpermute)
1147 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1148 LLVMArrayType(ctx->i32, 64),
1149 "ddxy_lds", LOCAL_ADDR_SPACE);
1150
1151 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1152 mask = AC_TID_MASK_LEFT;
1153 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1154 mask = AC_TID_MASK_TOP;
1155 else
1156 mask = AC_TID_MASK_TOP_LEFT;
1157
1158 /* for DDX we want to next X pixel, DDY next Y pixel. */
1159 if (op == nir_op_fddx_fine ||
1160 op == nir_op_fddx_coarse ||
1161 op == nir_op_fddx)
1162 idx = 1;
1163 else
1164 idx = 2;
1165
1166 result = ac_emit_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1167 mask, idx, ctx->lds,
1168 src0);
1169 return result;
1170 }
1171
1172 /*
1173 * this takes an I,J coordinate pair,
1174 * and works out the X and Y derivatives.
1175 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1176 */
1177 static LLVMValueRef emit_ddxy_interp(
1178 struct nir_to_llvm_context *ctx,
1179 LLVMValueRef interp_ij)
1180 {
1181 LLVMValueRef result[4], a;
1182 unsigned i;
1183
1184 for (i = 0; i < 2; i++) {
1185 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1186 LLVMConstInt(ctx->i32, i, false), "");
1187 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1188 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1189 }
1190 return ac_build_gather_values(&ctx->ac, result, 4);
1191 }
1192
1193 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1194 {
1195 LLVMValueRef src[4], result = NULL;
1196 unsigned num_components = instr->dest.dest.ssa.num_components;
1197 unsigned src_components;
1198 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1199
1200 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1201 switch (instr->op) {
1202 case nir_op_vec2:
1203 case nir_op_vec3:
1204 case nir_op_vec4:
1205 src_components = 1;
1206 break;
1207 case nir_op_pack_half_2x16:
1208 src_components = 2;
1209 break;
1210 case nir_op_unpack_half_2x16:
1211 src_components = 1;
1212 break;
1213 default:
1214 src_components = num_components;
1215 break;
1216 }
1217 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1218 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1219
1220 switch (instr->op) {
1221 case nir_op_fmov:
1222 case nir_op_imov:
1223 result = src[0];
1224 break;
1225 case nir_op_fneg:
1226 src[0] = to_float(ctx, src[0]);
1227 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1228 break;
1229 case nir_op_ineg:
1230 result = LLVMBuildNeg(ctx->builder, src[0], "");
1231 break;
1232 case nir_op_inot:
1233 result = LLVMBuildNot(ctx->builder, src[0], "");
1234 break;
1235 case nir_op_iadd:
1236 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1237 break;
1238 case nir_op_fadd:
1239 src[0] = to_float(ctx, src[0]);
1240 src[1] = to_float(ctx, src[1]);
1241 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1242 break;
1243 case nir_op_fsub:
1244 src[0] = to_float(ctx, src[0]);
1245 src[1] = to_float(ctx, src[1]);
1246 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1247 break;
1248 case nir_op_isub:
1249 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1250 break;
1251 case nir_op_imul:
1252 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1253 break;
1254 case nir_op_imod:
1255 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1256 break;
1257 case nir_op_umod:
1258 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1259 break;
1260 case nir_op_fmod:
1261 src[0] = to_float(ctx, src[0]);
1262 src[1] = to_float(ctx, src[1]);
1263 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1264 result = emit_intrin_1f_param(ctx, "llvm.floor",
1265 to_float_type(ctx, def_type), result);
1266 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1267 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1268 break;
1269 case nir_op_frem:
1270 src[0] = to_float(ctx, src[0]);
1271 src[1] = to_float(ctx, src[1]);
1272 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1273 break;
1274 case nir_op_irem:
1275 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1276 break;
1277 case nir_op_idiv:
1278 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1279 break;
1280 case nir_op_udiv:
1281 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1282 break;
1283 case nir_op_fmul:
1284 src[0] = to_float(ctx, src[0]);
1285 src[1] = to_float(ctx, src[1]);
1286 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1287 break;
1288 case nir_op_fdiv:
1289 src[0] = to_float(ctx, src[0]);
1290 src[1] = to_float(ctx, src[1]);
1291 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1292 break;
1293 case nir_op_frcp:
1294 src[0] = to_float(ctx, src[0]);
1295 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, src[0]);
1296 break;
1297 case nir_op_iand:
1298 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1299 break;
1300 case nir_op_ior:
1301 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1302 break;
1303 case nir_op_ixor:
1304 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1305 break;
1306 case nir_op_ishl:
1307 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1308 break;
1309 case nir_op_ishr:
1310 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1311 break;
1312 case nir_op_ushr:
1313 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1314 break;
1315 case nir_op_ilt:
1316 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1317 break;
1318 case nir_op_ine:
1319 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1320 break;
1321 case nir_op_ieq:
1322 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1323 break;
1324 case nir_op_ige:
1325 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1326 break;
1327 case nir_op_ult:
1328 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1329 break;
1330 case nir_op_uge:
1331 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1332 break;
1333 case nir_op_feq:
1334 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1335 break;
1336 case nir_op_fne:
1337 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1338 break;
1339 case nir_op_flt:
1340 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1341 break;
1342 case nir_op_fge:
1343 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1344 break;
1345 case nir_op_fabs:
1346 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1347 to_float_type(ctx, def_type), src[0]);
1348 break;
1349 case nir_op_iabs:
1350 result = emit_iabs(ctx, src[0]);
1351 break;
1352 case nir_op_imax:
1353 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1354 break;
1355 case nir_op_imin:
1356 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1357 break;
1358 case nir_op_umax:
1359 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1360 break;
1361 case nir_op_umin:
1362 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1363 break;
1364 case nir_op_isign:
1365 result = emit_isign(ctx, src[0]);
1366 break;
1367 case nir_op_fsign:
1368 src[0] = to_float(ctx, src[0]);
1369 result = emit_fsign(ctx, src[0]);
1370 break;
1371 case nir_op_ffloor:
1372 result = emit_intrin_1f_param(ctx, "llvm.floor",
1373 to_float_type(ctx, def_type), src[0]);
1374 break;
1375 case nir_op_ftrunc:
1376 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1377 to_float_type(ctx, def_type), src[0]);
1378 break;
1379 case nir_op_fceil:
1380 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1381 to_float_type(ctx, def_type), src[0]);
1382 break;
1383 case nir_op_fround_even:
1384 result = emit_intrin_1f_param(ctx, "llvm.rint",
1385 to_float_type(ctx, def_type),src[0]);
1386 break;
1387 case nir_op_ffract:
1388 result = emit_ffract(ctx, src[0]);
1389 break;
1390 case nir_op_fsin:
1391 result = emit_intrin_1f_param(ctx, "llvm.sin",
1392 to_float_type(ctx, def_type), src[0]);
1393 break;
1394 case nir_op_fcos:
1395 result = emit_intrin_1f_param(ctx, "llvm.cos",
1396 to_float_type(ctx, def_type), src[0]);
1397 break;
1398 case nir_op_fsqrt:
1399 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1400 to_float_type(ctx, def_type), src[0]);
1401 break;
1402 case nir_op_fexp2:
1403 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1404 to_float_type(ctx, def_type), src[0]);
1405 break;
1406 case nir_op_flog2:
1407 result = emit_intrin_1f_param(ctx, "llvm.log2",
1408 to_float_type(ctx, def_type), src[0]);
1409 break;
1410 case nir_op_frsq:
1411 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1412 to_float_type(ctx, def_type), src[0]);
1413 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, result);
1414 break;
1415 case nir_op_fpow:
1416 result = emit_intrin_2f_param(ctx, "llvm.pow",
1417 to_float_type(ctx, def_type), src[0], src[1]);
1418 break;
1419 case nir_op_fmax:
1420 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1421 to_float_type(ctx, def_type), src[0], src[1]);
1422 break;
1423 case nir_op_fmin:
1424 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1425 to_float_type(ctx, def_type), src[0], src[1]);
1426 break;
1427 case nir_op_ffma:
1428 result = emit_intrin_3f_param(ctx, "llvm.fma",
1429 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1430 break;
1431 case nir_op_ibitfield_extract:
1432 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.i32", src);
1433 break;
1434 case nir_op_ubitfield_extract:
1435 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.u32", src);
1436 break;
1437 case nir_op_bitfield_insert:
1438 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1439 break;
1440 case nir_op_bitfield_reverse:
1441 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1442 break;
1443 case nir_op_bit_count:
1444 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1445 break;
1446 case nir_op_vec2:
1447 case nir_op_vec3:
1448 case nir_op_vec4:
1449 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1450 src[i] = to_integer(ctx, src[i]);
1451 result = ac_build_gather_values(&ctx->ac, src, num_components);
1452 break;
1453 case nir_op_d2i:
1454 case nir_op_f2i:
1455 src[0] = to_float(ctx, src[0]);
1456 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1457 break;
1458 case nir_op_d2u:
1459 case nir_op_f2u:
1460 src[0] = to_float(ctx, src[0]);
1461 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1462 break;
1463 case nir_op_i2d:
1464 case nir_op_i2f:
1465 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1466 break;
1467 case nir_op_u2d:
1468 case nir_op_u2f:
1469 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1470 break;
1471 case nir_op_f2d:
1472 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1473 break;
1474 case nir_op_d2f:
1475 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1476 break;
1477 case nir_op_bcsel:
1478 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1479 break;
1480 case nir_op_find_lsb:
1481 result = emit_find_lsb(ctx, src[0]);
1482 break;
1483 case nir_op_ufind_msb:
1484 result = emit_ufind_msb(ctx, src[0]);
1485 break;
1486 case nir_op_ifind_msb:
1487 result = emit_ifind_msb(ctx, src[0]);
1488 break;
1489 case nir_op_uadd_carry:
1490 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1491 break;
1492 case nir_op_usub_borrow:
1493 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1494 break;
1495 case nir_op_b2f:
1496 result = emit_b2f(ctx, src[0]);
1497 break;
1498 case nir_op_fquantize2f16:
1499 src[0] = to_float(ctx, src[0]);
1500 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1501 /* need to convert back up to f32 */
1502 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1503 break;
1504 case nir_op_umul_high:
1505 result = emit_umul_high(ctx, src[0], src[1]);
1506 break;
1507 case nir_op_imul_high:
1508 result = emit_imul_high(ctx, src[0], src[1]);
1509 break;
1510 case nir_op_pack_half_2x16:
1511 result = emit_pack_half_2x16(ctx, src[0]);
1512 break;
1513 case nir_op_unpack_half_2x16:
1514 result = emit_unpack_half_2x16(ctx, src[0]);
1515 break;
1516 case nir_op_fddx:
1517 case nir_op_fddy:
1518 case nir_op_fddx_fine:
1519 case nir_op_fddy_fine:
1520 case nir_op_fddx_coarse:
1521 case nir_op_fddy_coarse:
1522 result = emit_ddxy(ctx, instr->op, src[0]);
1523 break;
1524 default:
1525 fprintf(stderr, "Unknown NIR alu instr: ");
1526 nir_print_instr(&instr->instr, stderr);
1527 fprintf(stderr, "\n");
1528 abort();
1529 }
1530
1531 if (result) {
1532 assert(instr->dest.dest.is_ssa);
1533 result = to_integer(ctx, result);
1534 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1535 result);
1536 }
1537 }
1538
1539 static void visit_load_const(struct nir_to_llvm_context *ctx,
1540 nir_load_const_instr *instr)
1541 {
1542 LLVMValueRef values[4], value = NULL;
1543 LLVMTypeRef element_type =
1544 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1545
1546 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1547 switch (instr->def.bit_size) {
1548 case 32:
1549 values[i] = LLVMConstInt(element_type,
1550 instr->value.u32[i], false);
1551 break;
1552 case 64:
1553 values[i] = LLVMConstInt(element_type,
1554 instr->value.u64[i], false);
1555 break;
1556 default:
1557 fprintf(stderr,
1558 "unsupported nir load_const bit_size: %d\n",
1559 instr->def.bit_size);
1560 abort();
1561 }
1562 }
1563 if (instr->def.num_components > 1) {
1564 value = LLVMConstVector(values, instr->def.num_components);
1565 } else
1566 value = values[0];
1567
1568 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1569 }
1570
1571 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1572 LLVMTypeRef type)
1573 {
1574 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1575 return LLVMBuildBitCast(ctx->builder, ptr,
1576 LLVMPointerType(type, addr_space), "");
1577 }
1578
1579 static LLVMValueRef
1580 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1581 {
1582 LLVMValueRef size =
1583 LLVMBuildExtractElement(ctx->builder, descriptor,
1584 LLVMConstInt(ctx->i32, 2, false), "");
1585
1586 /* VI only */
1587 if (ctx->options->chip_class >= VI && in_elements) {
1588 /* On VI, the descriptor contains the size in bytes,
1589 * but TXQ must return the size in elements.
1590 * The stride is always non-zero for resources using TXQ.
1591 */
1592 LLVMValueRef stride =
1593 LLVMBuildExtractElement(ctx->builder, descriptor,
1594 LLVMConstInt(ctx->i32, 1, false), "");
1595 stride = LLVMBuildLShr(ctx->builder, stride,
1596 LLVMConstInt(ctx->i32, 16, false), "");
1597 stride = LLVMBuildAnd(ctx->builder, stride,
1598 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1599
1600 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1601 }
1602 return size;
1603 }
1604
1605 /**
1606 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1607 * intrinsic names).
1608 */
1609 static void build_int_type_name(
1610 LLVMTypeRef type,
1611 char *buf, unsigned bufsize)
1612 {
1613 assert(bufsize >= 6);
1614
1615 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1616 snprintf(buf, bufsize, "v%ui32",
1617 LLVMGetVectorSize(type));
1618 else
1619 strcpy(buf, "i32");
1620 }
1621
1622 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1623 struct ac_tex_info *tinfo,
1624 nir_tex_instr *instr,
1625 const char *intr_name,
1626 unsigned coord_vgpr_index)
1627 {
1628 LLVMValueRef coord = tinfo->args[0];
1629 LLVMValueRef half_texel[2];
1630 int c;
1631
1632 //TODO Rect
1633 {
1634 LLVMValueRef txq_args[10];
1635 int txq_arg_count = 0;
1636 LLVMValueRef size;
1637 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1638 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, false);
1639 txq_args[txq_arg_count++] = tinfo->args[1];
1640 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0xf, 0); /* dmask */
1641 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* unorm */
1642 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
1643 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
1644 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
1645 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
1646 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
1647 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
1648 size = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
1649 txq_args, txq_arg_count,
1650 AC_FUNC_ATTR_READNONE);
1651
1652 for (c = 0; c < 2; c++) {
1653 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1654 LLVMConstInt(ctx->i32, c, false), "");
1655 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1656 half_texel[c] = ac_emit_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1657 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1658 LLVMConstReal(ctx->f32, -0.5), "");
1659 }
1660 }
1661
1662 for (c = 0; c < 2; c++) {
1663 LLVMValueRef tmp;
1664 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1665 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1666 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1667 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1668 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1669 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1670 }
1671
1672 tinfo->args[0] = coord;
1673 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1674 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1675
1676 }
1677
1678 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1679 nir_tex_instr *instr,
1680 struct ac_tex_info *tinfo)
1681 {
1682 const char *name = "llvm.SI.image.sample";
1683 const char *infix = "";
1684 char intr_name[127];
1685 char type[64];
1686 bool is_shadow = instr->is_shadow;
1687 bool has_offset = tinfo->has_offset;
1688 switch (instr->op) {
1689 case nir_texop_txf:
1690 case nir_texop_txf_ms:
1691 case nir_texop_samples_identical:
1692 name = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? "llvm.SI.image.load" :
1693 instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? "llvm.SI.vs.load.input" :
1694 "llvm.SI.image.load.mip";
1695 is_shadow = false;
1696 has_offset = false;
1697 break;
1698 case nir_texop_txb:
1699 infix = ".b";
1700 break;
1701 case nir_texop_txl:
1702 infix = ".l";
1703 break;
1704 case nir_texop_txs:
1705 name = "llvm.SI.getresinfo";
1706 break;
1707 case nir_texop_query_levels:
1708 name = "llvm.SI.getresinfo";
1709 break;
1710 case nir_texop_tex:
1711 if (ctx->stage != MESA_SHADER_FRAGMENT)
1712 infix = ".lz";
1713 break;
1714 case nir_texop_txd:
1715 infix = ".d";
1716 break;
1717 case nir_texop_tg4:
1718 name = "llvm.SI.gather4";
1719 infix = ".lz";
1720 break;
1721 case nir_texop_lod:
1722 name = "llvm.SI.getlod";
1723 is_shadow = false;
1724 has_offset = false;
1725 break;
1726 default:
1727 break;
1728 }
1729
1730 build_int_type_name(LLVMTypeOf(tinfo->args[0]), type, sizeof(type));
1731 sprintf(intr_name, "%s%s%s%s.%s", name, is_shadow ? ".c" : "", infix,
1732 has_offset ? ".o" : "", type);
1733
1734 if (instr->op == nir_texop_tg4) {
1735 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1736 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1737 return radv_lower_gather4_integer(ctx, tinfo, instr, intr_name,
1738 (int)has_offset + (int)is_shadow);
1739 }
1740 }
1741 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1742 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1743
1744 }
1745
1746 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1747 nir_intrinsic_instr *instr)
1748 {
1749 LLVMValueRef index = get_src(ctx, instr->src[0]);
1750 unsigned desc_set = nir_intrinsic_desc_set(instr);
1751 unsigned binding = nir_intrinsic_binding(instr);
1752 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1753 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
1754 unsigned base_offset = layout->binding[binding].offset;
1755 LLVMValueRef offset, stride;
1756
1757 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1758 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1759 desc_ptr = ctx->push_constants;
1760 base_offset = ctx->options->layout->push_constant_size;
1761 base_offset += 16 * layout->binding[binding].dynamic_offset_offset;
1762 stride = LLVMConstInt(ctx->i32, 16, false);
1763 } else
1764 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1765
1766 offset = LLVMConstInt(ctx->i32, base_offset, false);
1767 index = LLVMBuildMul(ctx->builder, index, stride, "");
1768 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1769
1770 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1771 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1772 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1773
1774 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1775 }
1776
1777 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1778 nir_intrinsic_instr *instr)
1779 {
1780 LLVMValueRef ptr, addr;
1781
1782 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1783 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1784
1785 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
1786 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1787
1788 return LLVMBuildLoad(ctx->builder, ptr, "");
1789 }
1790
1791 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1792 nir_intrinsic_instr *instr)
1793 {
1794 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1795
1796 return get_buffer_size(ctx, desc, false);
1797 }
1798 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1799 nir_intrinsic_instr *instr)
1800 {
1801 const char *store_name;
1802 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
1803 LLVMTypeRef data_type = ctx->f32;
1804 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
1805 int components_32bit = elem_size_mult * instr->num_components;
1806 unsigned writemask = nir_intrinsic_write_mask(instr);
1807 LLVMValueRef base_data, base_offset;
1808 LLVMValueRef params[6];
1809
1810 if (ctx->stage == MESA_SHADER_FRAGMENT)
1811 ctx->shader_info->fs.writes_memory = true;
1812
1813 params[1] = get_src(ctx, instr->src[1]);
1814 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1815 params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
1816 params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1817
1818 if (components_32bit > 1)
1819 data_type = LLVMVectorType(ctx->f32, components_32bit);
1820
1821 base_data = to_float(ctx, src_data);
1822 base_data = trim_vector(ctx, base_data, instr->num_components);
1823 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1824 data_type, "");
1825 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1826 while (writemask) {
1827 int start, count;
1828 LLVMValueRef data;
1829 LLVMValueRef offset;
1830 LLVMValueRef tmp;
1831 u_bit_scan_consecutive_range(&writemask, &start, &count);
1832
1833 /* Due to an LLVM limitation, split 3-element writes
1834 * into a 2-element and a 1-element write. */
1835 if (count == 3) {
1836 writemask |= 1 << (start + 2);
1837 count = 2;
1838 }
1839
1840 start *= elem_size_mult;
1841 count *= elem_size_mult;
1842
1843 if (count > 4) {
1844 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
1845 count = 4;
1846 }
1847
1848 if (count == 4) {
1849 store_name = "llvm.amdgcn.buffer.store.v4f32";
1850 data = base_data;
1851 } else if (count == 2) {
1852 tmp = LLVMBuildExtractElement(ctx->builder,
1853 base_data, LLVMConstInt(ctx->i32, start, false), "");
1854 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
1855 ctx->i32zero, "");
1856
1857 tmp = LLVMBuildExtractElement(ctx->builder,
1858 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
1859 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
1860 ctx->i32one, "");
1861 store_name = "llvm.amdgcn.buffer.store.v2f32";
1862
1863 } else {
1864 assert(count == 1);
1865 if (get_llvm_num_components(base_data) > 1)
1866 data = LLVMBuildExtractElement(ctx->builder, base_data,
1867 LLVMConstInt(ctx->i32, start, false), "");
1868 else
1869 data = base_data;
1870 store_name = "llvm.amdgcn.buffer.store.f32";
1871 }
1872
1873 offset = base_offset;
1874 if (start != 0) {
1875 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
1876 }
1877 params[0] = data;
1878 params[3] = offset;
1879 ac_emit_llvm_intrinsic(&ctx->ac, store_name,
1880 ctx->voidt, params, 6, 0);
1881 }
1882 }
1883
1884 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
1885 nir_intrinsic_instr *instr)
1886 {
1887 const char *name;
1888 LLVMValueRef params[6];
1889 int arg_count = 0;
1890 if (ctx->stage == MESA_SHADER_FRAGMENT)
1891 ctx->shader_info->fs.writes_memory = true;
1892
1893 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
1894 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
1895 }
1896 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
1897 params[arg_count++] = get_src(ctx, instr->src[0]);
1898 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1899 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
1900 params[arg_count++] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1901
1902 switch (instr->intrinsic) {
1903 case nir_intrinsic_ssbo_atomic_add:
1904 name = "llvm.amdgcn.buffer.atomic.add";
1905 break;
1906 case nir_intrinsic_ssbo_atomic_imin:
1907 name = "llvm.amdgcn.buffer.atomic.smin";
1908 break;
1909 case nir_intrinsic_ssbo_atomic_umin:
1910 name = "llvm.amdgcn.buffer.atomic.umin";
1911 break;
1912 case nir_intrinsic_ssbo_atomic_imax:
1913 name = "llvm.amdgcn.buffer.atomic.smax";
1914 break;
1915 case nir_intrinsic_ssbo_atomic_umax:
1916 name = "llvm.amdgcn.buffer.atomic.umax";
1917 break;
1918 case nir_intrinsic_ssbo_atomic_and:
1919 name = "llvm.amdgcn.buffer.atomic.and";
1920 break;
1921 case nir_intrinsic_ssbo_atomic_or:
1922 name = "llvm.amdgcn.buffer.atomic.or";
1923 break;
1924 case nir_intrinsic_ssbo_atomic_xor:
1925 name = "llvm.amdgcn.buffer.atomic.xor";
1926 break;
1927 case nir_intrinsic_ssbo_atomic_exchange:
1928 name = "llvm.amdgcn.buffer.atomic.swap";
1929 break;
1930 case nir_intrinsic_ssbo_atomic_comp_swap:
1931 name = "llvm.amdgcn.buffer.atomic.cmpswap";
1932 break;
1933 default:
1934 abort();
1935 }
1936
1937 return ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
1938 }
1939
1940 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
1941 nir_intrinsic_instr *instr)
1942 {
1943 LLVMValueRef results[2];
1944 int load_components;
1945 int num_components = instr->num_components;
1946 if (instr->dest.ssa.bit_size == 64)
1947 num_components *= 2;
1948
1949 for (int i = 0; i < num_components; i += load_components) {
1950 load_components = MIN2(num_components - i, 4);
1951 const char *load_name;
1952 LLVMTypeRef data_type = ctx->f32;
1953 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
1954 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
1955
1956 if (load_components == 3)
1957 data_type = LLVMVectorType(ctx->f32, 4);
1958 else if (load_components > 1)
1959 data_type = LLVMVectorType(ctx->f32, load_components);
1960
1961 if (load_components >= 3)
1962 load_name = "llvm.amdgcn.buffer.load.v4f32";
1963 else if (load_components == 2)
1964 load_name = "llvm.amdgcn.buffer.load.v2f32";
1965 else if (load_components == 1)
1966 load_name = "llvm.amdgcn.buffer.load.f32";
1967 else
1968 unreachable("unhandled number of components");
1969
1970 LLVMValueRef params[] = {
1971 get_src(ctx, instr->src[0]),
1972 LLVMConstInt(ctx->i32, 0, false),
1973 offset,
1974 LLVMConstInt(ctx->i1, 0, false),
1975 LLVMConstInt(ctx->i1, 0, false),
1976 };
1977
1978 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
1979
1980 }
1981
1982 LLVMValueRef ret = results[0];
1983 if (num_components > 4 || num_components == 3) {
1984 LLVMValueRef masks[] = {
1985 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1986 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
1987 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
1988 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
1989 };
1990
1991 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1992 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
1993 results[num_components > 4 ? 1 : 0], swizzle, "");
1994 }
1995
1996 return LLVMBuildBitCast(ctx->builder, ret,
1997 get_def_type(ctx, &instr->dest.ssa), "");
1998 }
1999
2000 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2001 nir_intrinsic_instr *instr)
2002 {
2003 LLVMValueRef results[8], ret;
2004 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2005 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2006 int num_components = instr->num_components;
2007
2008 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2009
2010 if (instr->dest.ssa.bit_size == 64)
2011 num_components *= 2;
2012
2013 for (unsigned i = 0; i < num_components; ++i) {
2014 LLVMValueRef params[] = {
2015 rsrc,
2016 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2017 offset, "")
2018 };
2019 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2020 params, 2, AC_FUNC_ATTR_READNONE);
2021 }
2022
2023
2024 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2025 return LLVMBuildBitCast(ctx->builder, ret,
2026 get_def_type(ctx, &instr->dest.ssa), "");
2027 }
2028
2029 static void
2030 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2031 bool vs_in, unsigned *vertex_index_out,
2032 unsigned *const_out, LLVMValueRef *indir_out)
2033 {
2034 unsigned const_offset = 0;
2035 LLVMValueRef offset = NULL;
2036
2037 if (vertex_index_out != NULL) {
2038 tail = tail->child;
2039 nir_deref_array *deref_array = nir_deref_as_array(tail);
2040 *vertex_index_out = deref_array->base_offset;
2041 }
2042
2043 while (tail->child != NULL) {
2044 const struct glsl_type *parent_type = tail->type;
2045 tail = tail->child;
2046
2047 if (tail->deref_type == nir_deref_type_array) {
2048 nir_deref_array *deref_array = nir_deref_as_array(tail);
2049 LLVMValueRef index, stride, local_offset;
2050 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2051
2052 const_offset += size * deref_array->base_offset;
2053 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2054 continue;
2055
2056 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2057 index = get_src(ctx, deref_array->indirect);
2058 stride = LLVMConstInt(ctx->i32, size, 0);
2059 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2060
2061 if (offset)
2062 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2063 else
2064 offset = local_offset;
2065 } else if (tail->deref_type == nir_deref_type_struct) {
2066 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2067
2068 for (unsigned i = 0; i < deref_struct->index; i++) {
2069 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2070 const_offset += glsl_count_attribute_slots(ft, vs_in);
2071 }
2072 } else
2073 unreachable("unsupported deref type");
2074
2075 }
2076
2077 if (const_offset && offset)
2078 offset = LLVMBuildAdd(ctx->builder, offset,
2079 LLVMConstInt(ctx->i32, const_offset, 0),
2080 "");
2081
2082 *const_out = const_offset;
2083 *indir_out = offset;
2084 }
2085
2086 static LLVMValueRef
2087 load_gs_input(struct nir_to_llvm_context *ctx,
2088 nir_intrinsic_instr *instr)
2089 {
2090 LLVMValueRef indir_index, vtx_offset;
2091 unsigned const_index;
2092 LLVMValueRef args[9];
2093 unsigned param, vtx_offset_param;
2094 LLVMValueRef value[4], result;
2095 unsigned vertex_index;
2096 unsigned cull_offset = 0;
2097 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2098 false, &vertex_index,
2099 &const_index, &indir_index);
2100 vtx_offset_param = vertex_index;
2101 assert(vtx_offset_param < 6);
2102 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2103 LLVMConstInt(ctx->i32, 4, false), "");
2104
2105 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2106 if (instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2107 cull_offset += ctx->num_input_clips;
2108 for (unsigned i = 0; i < instr->num_components; i++) {
2109
2110 args[0] = ctx->esgs_ring;
2111 args[1] = vtx_offset;
2112 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index + cull_offset) * 256, false);
2113 args[3] = ctx->i32zero;
2114 args[4] = ctx->i32one; /* OFFEN */
2115 args[5] = ctx->i32zero; /* IDXEN */
2116 args[6] = ctx->i32one; /* GLC */
2117 args[7] = ctx->i32zero; /* SLC */
2118 args[8] = ctx->i32zero; /* TFE */
2119
2120 value[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2121 ctx->i32, args, 9, AC_FUNC_ATTR_READONLY);
2122 }
2123 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2124
2125 return result;
2126 }
2127
2128 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2129 nir_intrinsic_instr *instr)
2130 {
2131 LLVMValueRef values[8];
2132 int idx = instr->variables[0]->var->data.driver_location;
2133 int ve = instr->dest.ssa.num_components;
2134 LLVMValueRef indir_index;
2135 LLVMValueRef ret;
2136 unsigned const_index;
2137 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2138 instr->variables[0]->var->data.mode == nir_var_shader_in;
2139 radv_get_deref_offset(ctx, &instr->variables[0]->deref, vs_in, NULL,
2140 &const_index, &indir_index);
2141
2142 if (instr->dest.ssa.bit_size == 64)
2143 ve *= 2;
2144
2145 switch (instr->variables[0]->var->data.mode) {
2146 case nir_var_shader_in:
2147 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2148 return load_gs_input(ctx, instr);
2149 }
2150 for (unsigned chan = 0; chan < ve; chan++) {
2151 if (indir_index) {
2152 unsigned count = glsl_count_attribute_slots(
2153 instr->variables[0]->var->type,
2154 ctx->stage == MESA_SHADER_VERTEX);
2155 count -= chan / 4;
2156 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2157 &ctx->ac, ctx->inputs + idx + chan, count,
2158 4, false);
2159
2160 values[chan] = LLVMBuildExtractElement(ctx->builder,
2161 tmp_vec,
2162 indir_index, "");
2163 } else
2164 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2165 }
2166 break;
2167 case nir_var_local:
2168 for (unsigned chan = 0; chan < ve; chan++) {
2169 if (indir_index) {
2170 unsigned count = glsl_count_attribute_slots(
2171 instr->variables[0]->var->type, false);
2172 count -= chan / 4;
2173 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2174 &ctx->ac, ctx->locals + idx + chan, count,
2175 4, true);
2176
2177 values[chan] = LLVMBuildExtractElement(ctx->builder,
2178 tmp_vec,
2179 indir_index, "");
2180 } else {
2181 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2182 }
2183 }
2184 break;
2185 case nir_var_shader_out:
2186 for (unsigned chan = 0; chan < ve; chan++) {
2187 if (indir_index) {
2188 unsigned count = glsl_count_attribute_slots(
2189 instr->variables[0]->var->type, false);
2190 count -= chan / 4;
2191 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2192 &ctx->ac, ctx->outputs + idx + chan, count,
2193 4, true);
2194
2195 values[chan] = LLVMBuildExtractElement(ctx->builder,
2196 tmp_vec,
2197 indir_index, "");
2198 } else {
2199 values[chan] = LLVMBuildLoad(ctx->builder,
2200 ctx->outputs[idx + chan + const_index * 4],
2201 "");
2202 }
2203 }
2204 break;
2205 case nir_var_shared: {
2206 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2207 LLVMValueRef derived_ptr;
2208
2209 if (indir_index)
2210 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2211
2212 for (unsigned chan = 0; chan < ve; chan++) {
2213 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2214 if (indir_index)
2215 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2216 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2217
2218 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2219 }
2220 break;
2221 }
2222 default:
2223 unreachable("unhandle variable mode");
2224 }
2225 ret = ac_build_gather_values(&ctx->ac, values, ve);
2226 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2227 }
2228
2229 static void
2230 visit_store_var(struct nir_to_llvm_context *ctx,
2231 nir_intrinsic_instr *instr)
2232 {
2233 LLVMValueRef temp_ptr, value;
2234 int idx = instr->variables[0]->var->data.driver_location;
2235 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2236 int writemask = instr->const_index[0];
2237 LLVMValueRef indir_index;
2238 unsigned const_index;
2239 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2240 NULL, &const_index, &indir_index);
2241
2242 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2243 int old_writemask = writemask;
2244
2245 src = LLVMBuildBitCast(ctx->builder, src,
2246 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2247 "");
2248
2249 writemask = 0;
2250 for (unsigned chan = 0; chan < 4; chan++) {
2251 if (old_writemask & (1 << chan))
2252 writemask |= 3u << (2 * chan);
2253 }
2254 }
2255
2256 switch (instr->variables[0]->var->data.mode) {
2257 case nir_var_shader_out:
2258 for (unsigned chan = 0; chan < 8; chan++) {
2259 int stride = 4;
2260 if (!(writemask & (1 << chan)))
2261 continue;
2262
2263 value = llvm_extract_elem(ctx, src, chan);
2264
2265 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2266 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2267 stride = 1;
2268 if (indir_index) {
2269 unsigned count = glsl_count_attribute_slots(
2270 instr->variables[0]->var->type, false);
2271 count -= chan / 4;
2272 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2273 &ctx->ac, ctx->outputs + idx + chan, count,
2274 stride, true);
2275
2276 if (get_llvm_num_components(tmp_vec) > 1) {
2277 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2278 value, indir_index, "");
2279 } else
2280 tmp_vec = value;
2281 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2282 count, stride, tmp_vec);
2283
2284 } else {
2285 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2286
2287 LLVMBuildStore(ctx->builder, value, temp_ptr);
2288 }
2289 }
2290 break;
2291 case nir_var_local:
2292 for (unsigned chan = 0; chan < 8; chan++) {
2293 if (!(writemask & (1 << chan)))
2294 continue;
2295
2296 value = llvm_extract_elem(ctx, src, chan);
2297 if (indir_index) {
2298 unsigned count = glsl_count_attribute_slots(
2299 instr->variables[0]->var->type, false);
2300 count -= chan / 4;
2301 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2302 &ctx->ac, ctx->locals + idx + chan, count,
2303 4, true);
2304
2305 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2306 value, indir_index, "");
2307 build_store_values_extended(ctx, ctx->locals + idx + chan,
2308 count, 4, tmp_vec);
2309 } else {
2310 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2311
2312 LLVMBuildStore(ctx->builder, value, temp_ptr);
2313 }
2314 }
2315 break;
2316 case nir_var_shared: {
2317 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2318
2319 if (indir_index)
2320 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2321
2322 for (unsigned chan = 0; chan < 8; chan++) {
2323 if (!(writemask & (1 << chan)))
2324 continue;
2325 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2326 LLVMValueRef derived_ptr;
2327
2328 if (indir_index)
2329 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2330
2331 value = llvm_extract_elem(ctx, src, chan);
2332 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2333 LLVMBuildStore(ctx->builder,
2334 to_integer(ctx, value), derived_ptr);
2335 }
2336 break;
2337 }
2338 default:
2339 break;
2340 }
2341 }
2342
2343 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2344 {
2345 switch (dim) {
2346 case GLSL_SAMPLER_DIM_BUF:
2347 return 1;
2348 case GLSL_SAMPLER_DIM_1D:
2349 return array ? 2 : 1;
2350 case GLSL_SAMPLER_DIM_2D:
2351 return array ? 3 : 2;
2352 case GLSL_SAMPLER_DIM_MS:
2353 return array ? 4 : 3;
2354 case GLSL_SAMPLER_DIM_3D:
2355 case GLSL_SAMPLER_DIM_CUBE:
2356 return 3;
2357 case GLSL_SAMPLER_DIM_RECT:
2358 case GLSL_SAMPLER_DIM_SUBPASS:
2359 return 2;
2360 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2361 return 3;
2362 default:
2363 break;
2364 }
2365 return 0;
2366 }
2367
2368 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2369 nir_intrinsic_instr *instr)
2370 {
2371 const struct glsl_type *type = instr->variables[0]->var->type;
2372 if(instr->variables[0]->deref.child)
2373 type = instr->variables[0]->deref.child->type;
2374
2375 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2376 LLVMValueRef coords[4];
2377 LLVMValueRef masks[] = {
2378 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2379 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2380 };
2381 LLVMValueRef res;
2382 int count;
2383 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2384 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2385 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2386 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2387 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2388
2389 count = image_type_to_components_count(dim,
2390 glsl_sampler_type_is_array(type));
2391
2392 if (count == 1) {
2393 if (instr->src[0].ssa->num_components)
2394 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2395 else
2396 res = src0;
2397 } else {
2398 int chan;
2399 if (is_ms)
2400 count--;
2401 for (chan = 0; chan < count; ++chan) {
2402 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2403 }
2404
2405 if (add_frag_pos) {
2406 for (chan = 0; chan < count; ++chan)
2407 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2408 }
2409 if (is_ms) {
2410 coords[count] = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2411 count++;
2412 }
2413
2414 if (count == 3) {
2415 coords[3] = LLVMGetUndef(ctx->i32);
2416 count = 4;
2417 }
2418 res = ac_build_gather_values(&ctx->ac, coords, count);
2419 }
2420 return res;
2421 }
2422
2423 static void build_type_name_for_intr(
2424 LLVMTypeRef type,
2425 char *buf, unsigned bufsize)
2426 {
2427 LLVMTypeRef elem_type = type;
2428
2429 assert(bufsize >= 8);
2430
2431 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
2432 int ret = snprintf(buf, bufsize, "v%u",
2433 LLVMGetVectorSize(type));
2434 if (ret < 0) {
2435 char *type_name = LLVMPrintTypeToString(type);
2436 fprintf(stderr, "Error building type name for: %s\n",
2437 type_name);
2438 return;
2439 }
2440 elem_type = LLVMGetElementType(type);
2441 buf += ret;
2442 bufsize -= ret;
2443 }
2444 switch (LLVMGetTypeKind(elem_type)) {
2445 default: break;
2446 case LLVMIntegerTypeKind:
2447 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
2448 break;
2449 case LLVMFloatTypeKind:
2450 snprintf(buf, bufsize, "f32");
2451 break;
2452 case LLVMDoubleTypeKind:
2453 snprintf(buf, bufsize, "f64");
2454 break;
2455 }
2456 }
2457
2458 static void get_image_intr_name(const char *base_name,
2459 LLVMTypeRef data_type,
2460 LLVMTypeRef coords_type,
2461 LLVMTypeRef rsrc_type,
2462 char *out_name, unsigned out_len)
2463 {
2464 char coords_type_name[8];
2465
2466 build_type_name_for_intr(coords_type, coords_type_name,
2467 sizeof(coords_type_name));
2468
2469 if (HAVE_LLVM <= 0x0309) {
2470 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
2471 } else {
2472 char data_type_name[8];
2473 char rsrc_type_name[8];
2474
2475 build_type_name_for_intr(data_type, data_type_name,
2476 sizeof(data_type_name));
2477 build_type_name_for_intr(rsrc_type, rsrc_type_name,
2478 sizeof(rsrc_type_name));
2479 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
2480 data_type_name, coords_type_name, rsrc_type_name);
2481 }
2482 }
2483
2484 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2485 nir_intrinsic_instr *instr)
2486 {
2487 LLVMValueRef params[7];
2488 LLVMValueRef res;
2489 char intrinsic_name[64];
2490 const nir_variable *var = instr->variables[0]->var;
2491 const struct glsl_type *type = var->type;
2492 if(instr->variables[0]->deref.child)
2493 type = instr->variables[0]->deref.child->type;
2494
2495 type = glsl_without_array(type);
2496 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2497 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2498 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2499 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2500 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2501 params[3] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2502 params[4] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2503 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2504 params, 5, 0);
2505
2506 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2507 res = to_integer(ctx, res);
2508 } else {
2509 bool is_da = glsl_sampler_type_is_array(type) ||
2510 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2511 LLVMValueRef da = is_da ? ctx->i32one : ctx->i32zero;
2512 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2513 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2514
2515 params[0] = get_image_coords(ctx, instr);
2516 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2517 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2518 if (HAVE_LLVM <= 0x0309) {
2519 params[3] = LLVMConstInt(ctx->i1, 0, false); /* r128 */
2520 params[4] = da;
2521 params[5] = glc;
2522 params[6] = slc;
2523 } else {
2524 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2525 params[3] = glc;
2526 params[4] = slc;
2527 params[5] = lwe;
2528 params[6] = da;
2529 }
2530
2531 get_image_intr_name("llvm.amdgcn.image.load",
2532 ctx->v4f32, /* vdata */
2533 LLVMTypeOf(params[0]), /* coords */
2534 LLVMTypeOf(params[1]), /* rsrc */
2535 intrinsic_name, sizeof(intrinsic_name));
2536
2537 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2538 params, 7, AC_FUNC_ATTR_READONLY);
2539 }
2540 return to_integer(ctx, res);
2541 }
2542
2543 static void visit_image_store(struct nir_to_llvm_context *ctx,
2544 nir_intrinsic_instr *instr)
2545 {
2546 LLVMValueRef params[8];
2547 char intrinsic_name[64];
2548 const nir_variable *var = instr->variables[0]->var;
2549 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2550 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2551 const struct glsl_type *type = glsl_without_array(var->type);
2552
2553 if (ctx->stage == MESA_SHADER_FRAGMENT)
2554 ctx->shader_info->fs.writes_memory = true;
2555
2556 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2557 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2558 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2559 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2560 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2561 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2562 params[4] = i1false; /* glc */
2563 params[5] = i1false; /* slc */
2564 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2565 params, 6, 0);
2566 } else {
2567 bool is_da = glsl_sampler_type_is_array(type) ||
2568 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2569 LLVMValueRef da = is_da ? i1true : i1false;
2570 LLVMValueRef glc = i1false;
2571 LLVMValueRef slc = i1false;
2572
2573 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2574 params[1] = get_image_coords(ctx, instr); /* coords */
2575 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2576 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2577 if (HAVE_LLVM <= 0x0309) {
2578 params[4] = i1false; /* r128 */
2579 params[5] = da;
2580 params[6] = glc;
2581 params[7] = slc;
2582 } else {
2583 LLVMValueRef lwe = i1false;
2584 params[4] = glc;
2585 params[5] = slc;
2586 params[6] = lwe;
2587 params[7] = da;
2588 }
2589
2590 get_image_intr_name("llvm.amdgcn.image.store",
2591 LLVMTypeOf(params[0]), /* vdata */
2592 LLVMTypeOf(params[1]), /* coords */
2593 LLVMTypeOf(params[2]), /* rsrc */
2594 intrinsic_name, sizeof(intrinsic_name));
2595
2596 ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2597 params, 8, 0);
2598 }
2599
2600 }
2601
2602 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2603 nir_intrinsic_instr *instr)
2604 {
2605 LLVMValueRef params[6];
2606 int param_count = 0;
2607 const nir_variable *var = instr->variables[0]->var;
2608 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2609 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2610 const char *base_name = "llvm.amdgcn.image.atomic";
2611 const char *atomic_name;
2612 LLVMValueRef coords;
2613 char intrinsic_name[32], coords_type[8];
2614 const struct glsl_type *type = glsl_without_array(var->type);
2615
2616 if (ctx->stage == MESA_SHADER_FRAGMENT)
2617 ctx->shader_info->fs.writes_memory = true;
2618
2619 params[param_count++] = get_src(ctx, instr->src[2]);
2620 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2621 params[param_count++] = get_src(ctx, instr->src[3]);
2622
2623 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2624 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2625 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2626 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2627 params[param_count++] = ctx->i32zero; /* voffset */
2628 params[param_count++] = i1false; /* glc */
2629 params[param_count++] = i1false; /* slc */
2630 } else {
2631 bool da = glsl_sampler_type_is_array(type) ||
2632 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2633
2634 coords = params[param_count++] = get_image_coords(ctx, instr);
2635 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2636 params[param_count++] = i1false; /* r128 */
2637 params[param_count++] = da ? i1true : i1false; /* da */
2638 params[param_count++] = i1false; /* slc */
2639 }
2640
2641 switch (instr->intrinsic) {
2642 case nir_intrinsic_image_atomic_add:
2643 atomic_name = "add";
2644 break;
2645 case nir_intrinsic_image_atomic_min:
2646 atomic_name = "smin";
2647 break;
2648 case nir_intrinsic_image_atomic_max:
2649 atomic_name = "smax";
2650 break;
2651 case nir_intrinsic_image_atomic_and:
2652 atomic_name = "and";
2653 break;
2654 case nir_intrinsic_image_atomic_or:
2655 atomic_name = "or";
2656 break;
2657 case nir_intrinsic_image_atomic_xor:
2658 atomic_name = "xor";
2659 break;
2660 case nir_intrinsic_image_atomic_exchange:
2661 atomic_name = "swap";
2662 break;
2663 case nir_intrinsic_image_atomic_comp_swap:
2664 atomic_name = "cmpswap";
2665 break;
2666 default:
2667 abort();
2668 }
2669 build_int_type_name(LLVMTypeOf(coords),
2670 coords_type, sizeof(coords_type));
2671
2672 snprintf(intrinsic_name, sizeof(intrinsic_name),
2673 "%s.%s.%s", base_name, atomic_name, coords_type);
2674 return ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2675 }
2676
2677 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2678 nir_intrinsic_instr *instr)
2679 {
2680 LLVMValueRef res;
2681 LLVMValueRef params[10];
2682 const nir_variable *var = instr->variables[0]->var;
2683 const struct glsl_type *type = instr->variables[0]->var->type;
2684 bool da = glsl_sampler_type_is_array(var->type) ||
2685 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2686 if(instr->variables[0]->deref.child)
2687 type = instr->variables[0]->deref.child->type;
2688
2689 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2690 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2691 params[0] = ctx->i32zero;
2692 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2693 params[2] = LLVMConstInt(ctx->i32, 15, false);
2694 params[3] = ctx->i32zero;
2695 params[4] = ctx->i32zero;
2696 params[5] = da ? ctx->i32one : ctx->i32zero;
2697 params[6] = ctx->i32zero;
2698 params[7] = ctx->i32zero;
2699 params[8] = ctx->i32zero;
2700 params[9] = ctx->i32zero;
2701
2702 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
2703 params, 10, AC_FUNC_ATTR_READNONE);
2704
2705 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2706 glsl_sampler_type_is_array(type)) {
2707 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2708 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2709 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2710 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2711 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2712 }
2713 return res;
2714 }
2715
2716 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2717 {
2718 LLVMValueRef args[1] = {
2719 LLVMConstInt(ctx->i32, 0xf70, false),
2720 };
2721 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2722 ctx->voidt, args, 1, 0);
2723 }
2724
2725 static void emit_barrier(struct nir_to_llvm_context *ctx)
2726 {
2727 // TODO tess
2728 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2729 ctx->voidt, NULL, 0, 0);
2730 }
2731
2732 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2733 nir_intrinsic_instr *instr)
2734 {
2735 LLVMValueRef cond;
2736 ctx->shader_info->fs.can_discard = true;
2737
2738 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2739 get_src(ctx, instr->src[0]),
2740 ctx->i32zero, "");
2741
2742 cond = LLVMBuildSelect(ctx->builder, cond,
2743 LLVMConstReal(ctx->f32, -1.0f),
2744 ctx->f32zero, "");
2745 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
2746 ctx->voidt,
2747 &cond, 1, 0);
2748 }
2749
2750 static LLVMValueRef
2751 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2752 {
2753 LLVMValueRef result;
2754 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
2755 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2756 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2757
2758 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2759 }
2760
2761 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2762 nir_intrinsic_instr *instr)
2763 {
2764 LLVMValueRef ptr, result;
2765 int idx = instr->variables[0]->var->data.driver_location;
2766 LLVMValueRef src = get_src(ctx, instr->src[0]);
2767 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2768
2769 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2770 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2771 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2772 ptr, src, src1,
2773 LLVMAtomicOrderingSequentiallyConsistent,
2774 LLVMAtomicOrderingSequentiallyConsistent,
2775 false);
2776 } else {
2777 LLVMAtomicRMWBinOp op;
2778 switch (instr->intrinsic) {
2779 case nir_intrinsic_var_atomic_add:
2780 op = LLVMAtomicRMWBinOpAdd;
2781 break;
2782 case nir_intrinsic_var_atomic_umin:
2783 op = LLVMAtomicRMWBinOpUMin;
2784 break;
2785 case nir_intrinsic_var_atomic_umax:
2786 op = LLVMAtomicRMWBinOpUMax;
2787 break;
2788 case nir_intrinsic_var_atomic_imin:
2789 op = LLVMAtomicRMWBinOpMin;
2790 break;
2791 case nir_intrinsic_var_atomic_imax:
2792 op = LLVMAtomicRMWBinOpMax;
2793 break;
2794 case nir_intrinsic_var_atomic_and:
2795 op = LLVMAtomicRMWBinOpAnd;
2796 break;
2797 case nir_intrinsic_var_atomic_or:
2798 op = LLVMAtomicRMWBinOpOr;
2799 break;
2800 case nir_intrinsic_var_atomic_xor:
2801 op = LLVMAtomicRMWBinOpXor;
2802 break;
2803 case nir_intrinsic_var_atomic_exchange:
2804 op = LLVMAtomicRMWBinOpXchg;
2805 break;
2806 default:
2807 return NULL;
2808 }
2809
2810 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2811 LLVMAtomicOrderingSequentiallyConsistent,
2812 false);
2813 }
2814 return result;
2815 }
2816
2817 #define INTERP_CENTER 0
2818 #define INTERP_CENTROID 1
2819 #define INTERP_SAMPLE 2
2820
2821 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2822 enum glsl_interp_mode interp, unsigned location)
2823 {
2824 switch (interp) {
2825 case INTERP_MODE_FLAT:
2826 default:
2827 return NULL;
2828 case INTERP_MODE_SMOOTH:
2829 case INTERP_MODE_NONE:
2830 if (location == INTERP_CENTER)
2831 return ctx->persp_center;
2832 else if (location == INTERP_CENTROID)
2833 return ctx->persp_centroid;
2834 else if (location == INTERP_SAMPLE)
2835 return ctx->persp_sample;
2836 break;
2837 case INTERP_MODE_NOPERSPECTIVE:
2838 if (location == INTERP_CENTER)
2839 return ctx->linear_center;
2840 else if (location == INTERP_CENTROID)
2841 return ctx->linear_centroid;
2842 else if (location == INTERP_SAMPLE)
2843 return ctx->linear_sample;
2844 break;
2845 }
2846 return NULL;
2847 }
2848
2849 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
2850 LLVMValueRef sample_id)
2851 {
2852 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2853 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
2854 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
2855 LLVMValueRef result[2];
2856
2857 result[0] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset0);
2858 result[1] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset1);
2859
2860 return ac_build_gather_values(&ctx->ac, result, 2);
2861 }
2862
2863 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
2864 {
2865 LLVMValueRef values[2];
2866
2867 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
2868 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
2869 return ac_build_gather_values(&ctx->ac, values, 2);
2870 }
2871
2872 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
2873 nir_intrinsic_instr *instr)
2874 {
2875 LLVMValueRef result[2];
2876 LLVMValueRef interp_param, attr_number;
2877 unsigned location;
2878 unsigned chan;
2879 LLVMValueRef src_c0, src_c1;
2880 LLVMValueRef src0;
2881 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
2882 switch (instr->intrinsic) {
2883 case nir_intrinsic_interp_var_at_centroid:
2884 location = INTERP_CENTROID;
2885 break;
2886 case nir_intrinsic_interp_var_at_sample:
2887 location = INTERP_SAMPLE;
2888 src0 = get_src(ctx, instr->src[0]);
2889 break;
2890 case nir_intrinsic_interp_var_at_offset:
2891 location = INTERP_CENTER;
2892 src0 = get_src(ctx, instr->src[0]);
2893 default:
2894 break;
2895 }
2896
2897 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
2898 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
2899 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
2900 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
2901 LLVMValueRef sample_position;
2902 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
2903
2904 /* fetch sample ID */
2905 sample_position = load_sample_position(ctx, src0);
2906
2907 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
2908 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
2909 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
2910 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
2911 }
2912 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
2913 attr_number = LLVMConstInt(ctx->i32, input_index, false);
2914
2915 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
2916 LLVMValueRef ij_out[2];
2917 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
2918
2919 /*
2920 * take the I then J parameters, and the DDX/Y for it, and
2921 * calculate the IJ inputs for the interpolator.
2922 * temp1 = ddx * offset/sample.x + I;
2923 * interp_param.I = ddy * offset/sample.y + temp1;
2924 * temp1 = ddx * offset/sample.x + J;
2925 * interp_param.J = ddy * offset/sample.y + temp1;
2926 */
2927 for (unsigned i = 0; i < 2; i++) {
2928 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
2929 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
2930 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
2931 ddxy_out, ix_ll, "");
2932 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
2933 ddxy_out, iy_ll, "");
2934 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
2935 interp_param, ix_ll, "");
2936 LLVMValueRef temp1, temp2;
2937
2938 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
2939 ctx->f32, "");
2940
2941 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
2942 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
2943
2944 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
2945 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
2946
2947 ij_out[i] = LLVMBuildBitCast(ctx->builder,
2948 temp2, ctx->i32, "");
2949 }
2950 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
2951
2952 }
2953
2954 for (chan = 0; chan < 2; chan++) {
2955 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
2956
2957 if (interp_param) {
2958 interp_param = LLVMBuildBitCast(ctx->builder,
2959 interp_param, LLVMVectorType(ctx->f32, 2), "");
2960 LLVMValueRef i = LLVMBuildExtractElement(
2961 ctx->builder, interp_param, ctx->i32zero, "");
2962 LLVMValueRef j = LLVMBuildExtractElement(
2963 ctx->builder, interp_param, ctx->i32one, "");
2964
2965 result[chan] = ac_build_fs_interp(&ctx->ac,
2966 llvm_chan, attr_number,
2967 ctx->prim_mask, i, j);
2968 } else {
2969 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
2970 LLVMConstInt(ctx->i32, 2, false),
2971 llvm_chan, attr_number,
2972 ctx->prim_mask);
2973 }
2974 }
2975 return ac_build_gather_values(&ctx->ac, result, 2);
2976 }
2977
2978 static void
2979 visit_emit_vertex(struct nir_to_llvm_context *ctx,
2980 nir_intrinsic_instr *instr)
2981 {
2982 LLVMValueRef gs_next_vertex;
2983 LLVMValueRef can_emit, kill;
2984 int idx;
2985 int clip_cull_slot = -1;
2986 assert(instr->const_index[0] == 0);
2987 /* Write vertex attribute values to GSVS ring */
2988 gs_next_vertex = LLVMBuildLoad(ctx->builder,
2989 ctx->gs_next_vertex,
2990 "");
2991
2992 /* If this thread has already emitted the declared maximum number of
2993 * vertices, kill it: excessive vertex emissions are not supposed to
2994 * have any effect, and GS threads have no externally observable
2995 * effects other than emitting vertices.
2996 */
2997 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
2998 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
2999
3000 kill = LLVMBuildSelect(ctx->builder, can_emit,
3001 LLVMConstReal(ctx->f32, 1.0f),
3002 LLVMConstReal(ctx->f32, -1.0f), "");
3003 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
3004 ctx->voidt, &kill, 1, 0);
3005
3006 /* loop num outputs */
3007 idx = 0;
3008 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3009 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3010 int length = 4;
3011 int start = 0;
3012 int slot = idx;
3013 int slot_inc = 1;
3014
3015 if (!(ctx->output_mask & (1ull << i)))
3016 continue;
3017
3018 if (i == VARYING_SLOT_CLIP_DIST1 ||
3019 i == VARYING_SLOT_CULL_DIST1)
3020 continue;
3021
3022 if (i == VARYING_SLOT_CLIP_DIST0 ||
3023 i == VARYING_SLOT_CULL_DIST0) {
3024 /* pack clip and cull into a single set of slots */
3025 if (clip_cull_slot == -1) {
3026 clip_cull_slot = idx;
3027 if (ctx->num_output_clips + ctx->num_output_culls > 4)
3028 slot_inc = 2;
3029 } else {
3030 slot = clip_cull_slot;
3031 slot_inc = 0;
3032 }
3033 if (i == VARYING_SLOT_CLIP_DIST0)
3034 length = ctx->num_output_clips;
3035 if (i == VARYING_SLOT_CULL_DIST0) {
3036 start = ctx->num_output_clips;
3037 length = ctx->num_output_culls;
3038 }
3039 }
3040 for (unsigned j = 0; j < length; j++) {
3041 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3042 out_ptr[j], "");
3043 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j + start) * ctx->gs_max_out_vertices, false);
3044 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3045 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3046
3047 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3048
3049 ac_build_tbuffer_store(&ctx->ac, ctx->gsvs_ring,
3050 out_val, 1,
3051 voffset, ctx->gs2vs_offset, 0,
3052 V_008F0C_BUF_DATA_FORMAT_32,
3053 V_008F0C_BUF_NUM_FORMAT_UINT,
3054 1, 0, 1, 1, 0);
3055 }
3056 idx += slot_inc;
3057 }
3058
3059 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3060 ctx->i32one, "");
3061 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3062
3063 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3064 }
3065
3066 static void
3067 visit_end_primitive(struct nir_to_llvm_context *ctx,
3068 nir_intrinsic_instr *instr)
3069 {
3070 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3071 }
3072
3073 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3074 nir_intrinsic_instr *instr)
3075 {
3076 LLVMValueRef result = NULL;
3077
3078 switch (instr->intrinsic) {
3079 case nir_intrinsic_load_work_group_id: {
3080 result = ctx->workgroup_ids;
3081 break;
3082 }
3083 case nir_intrinsic_load_base_vertex: {
3084 result = ctx->base_vertex;
3085 break;
3086 }
3087 case nir_intrinsic_load_vertex_id_zero_base: {
3088 result = ctx->vertex_id;
3089 break;
3090 }
3091 case nir_intrinsic_load_local_invocation_id: {
3092 result = ctx->local_invocation_ids;
3093 break;
3094 }
3095 case nir_intrinsic_load_base_instance:
3096 result = ctx->start_instance;
3097 break;
3098 case nir_intrinsic_load_draw_id:
3099 result = ctx->draw_index;
3100 break;
3101 case nir_intrinsic_load_invocation_id:
3102 result = ctx->gs_invocation_id;
3103 break;
3104 case nir_intrinsic_load_primitive_id:
3105 if (ctx->stage == MESA_SHADER_GEOMETRY)
3106 result = ctx->gs_prim_id;
3107 else
3108 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3109 break;
3110 case nir_intrinsic_load_sample_id:
3111 ctx->shader_info->fs.force_persample = true;
3112 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3113 break;
3114 case nir_intrinsic_load_sample_pos:
3115 ctx->shader_info->fs.force_persample = true;
3116 result = load_sample_pos(ctx);
3117 break;
3118 case nir_intrinsic_load_front_face:
3119 result = ctx->front_face;
3120 break;
3121 case nir_intrinsic_load_instance_id:
3122 result = ctx->instance_id;
3123 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3124 ctx->shader_info->vs.vgpr_comp_cnt);
3125 break;
3126 case nir_intrinsic_load_num_work_groups:
3127 result = ctx->num_work_groups;
3128 break;
3129 case nir_intrinsic_load_local_invocation_index:
3130 result = visit_load_local_invocation_index(ctx);
3131 break;
3132 case nir_intrinsic_load_push_constant:
3133 result = visit_load_push_constant(ctx, instr);
3134 break;
3135 case nir_intrinsic_vulkan_resource_index:
3136 result = visit_vulkan_resource_index(ctx, instr);
3137 break;
3138 case nir_intrinsic_store_ssbo:
3139 visit_store_ssbo(ctx, instr);
3140 break;
3141 case nir_intrinsic_load_ssbo:
3142 result = visit_load_buffer(ctx, instr);
3143 break;
3144 case nir_intrinsic_ssbo_atomic_add:
3145 case nir_intrinsic_ssbo_atomic_imin:
3146 case nir_intrinsic_ssbo_atomic_umin:
3147 case nir_intrinsic_ssbo_atomic_imax:
3148 case nir_intrinsic_ssbo_atomic_umax:
3149 case nir_intrinsic_ssbo_atomic_and:
3150 case nir_intrinsic_ssbo_atomic_or:
3151 case nir_intrinsic_ssbo_atomic_xor:
3152 case nir_intrinsic_ssbo_atomic_exchange:
3153 case nir_intrinsic_ssbo_atomic_comp_swap:
3154 result = visit_atomic_ssbo(ctx, instr);
3155 break;
3156 case nir_intrinsic_load_ubo:
3157 result = visit_load_ubo_buffer(ctx, instr);
3158 break;
3159 case nir_intrinsic_get_buffer_size:
3160 result = visit_get_buffer_size(ctx, instr);
3161 break;
3162 case nir_intrinsic_load_var:
3163 result = visit_load_var(ctx, instr);
3164 break;
3165 case nir_intrinsic_store_var:
3166 visit_store_var(ctx, instr);
3167 break;
3168 case nir_intrinsic_image_load:
3169 result = visit_image_load(ctx, instr);
3170 break;
3171 case nir_intrinsic_image_store:
3172 visit_image_store(ctx, instr);
3173 break;
3174 case nir_intrinsic_image_atomic_add:
3175 case nir_intrinsic_image_atomic_min:
3176 case nir_intrinsic_image_atomic_max:
3177 case nir_intrinsic_image_atomic_and:
3178 case nir_intrinsic_image_atomic_or:
3179 case nir_intrinsic_image_atomic_xor:
3180 case nir_intrinsic_image_atomic_exchange:
3181 case nir_intrinsic_image_atomic_comp_swap:
3182 result = visit_image_atomic(ctx, instr);
3183 break;
3184 case nir_intrinsic_image_size:
3185 result = visit_image_size(ctx, instr);
3186 break;
3187 case nir_intrinsic_discard:
3188 ctx->shader_info->fs.can_discard = true;
3189 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3190 ctx->voidt,
3191 NULL, 0, 0);
3192 break;
3193 case nir_intrinsic_discard_if:
3194 emit_discard_if(ctx, instr);
3195 break;
3196 case nir_intrinsic_memory_barrier:
3197 emit_waitcnt(ctx);
3198 break;
3199 case nir_intrinsic_barrier:
3200 emit_barrier(ctx);
3201 break;
3202 case nir_intrinsic_var_atomic_add:
3203 case nir_intrinsic_var_atomic_imin:
3204 case nir_intrinsic_var_atomic_umin:
3205 case nir_intrinsic_var_atomic_imax:
3206 case nir_intrinsic_var_atomic_umax:
3207 case nir_intrinsic_var_atomic_and:
3208 case nir_intrinsic_var_atomic_or:
3209 case nir_intrinsic_var_atomic_xor:
3210 case nir_intrinsic_var_atomic_exchange:
3211 case nir_intrinsic_var_atomic_comp_swap:
3212 result = visit_var_atomic(ctx, instr);
3213 break;
3214 case nir_intrinsic_interp_var_at_centroid:
3215 case nir_intrinsic_interp_var_at_sample:
3216 case nir_intrinsic_interp_var_at_offset:
3217 result = visit_interp(ctx, instr);
3218 break;
3219 case nir_intrinsic_emit_vertex:
3220 visit_emit_vertex(ctx, instr);
3221 break;
3222 case nir_intrinsic_end_primitive:
3223 visit_end_primitive(ctx, instr);
3224 break;
3225 default:
3226 fprintf(stderr, "Unknown intrinsic: ");
3227 nir_print_instr(&instr->instr, stderr);
3228 fprintf(stderr, "\n");
3229 break;
3230 }
3231 if (result) {
3232 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3233 }
3234 }
3235
3236 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3237 nir_deref_var *deref,
3238 enum desc_type desc_type)
3239 {
3240 unsigned desc_set = deref->var->data.descriptor_set;
3241 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3242 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3243 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3244 unsigned offset = binding->offset;
3245 unsigned stride = binding->size;
3246 unsigned type_size;
3247 LLVMBuilderRef builder = ctx->builder;
3248 LLVMTypeRef type;
3249 LLVMValueRef index = NULL;
3250
3251 assert(deref->var->data.binding < layout->binding_count);
3252
3253 switch (desc_type) {
3254 case DESC_IMAGE:
3255 type = ctx->v8i32;
3256 type_size = 32;
3257 break;
3258 case DESC_FMASK:
3259 type = ctx->v8i32;
3260 offset += 32;
3261 type_size = 32;
3262 break;
3263 case DESC_SAMPLER:
3264 type = ctx->v4i32;
3265 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3266 offset += 64;
3267
3268 type_size = 16;
3269 break;
3270 case DESC_BUFFER:
3271 type = ctx->v4i32;
3272 type_size = 16;
3273 break;
3274 default:
3275 unreachable("invalid desc_type\n");
3276 }
3277
3278 if (deref->deref.child) {
3279 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3280
3281 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3282 offset += child->base_offset * stride;
3283 if (child->deref_array_type == nir_deref_array_type_indirect) {
3284 index = get_src(ctx, child->indirect);
3285 }
3286 }
3287
3288 assert(stride % type_size == 0);
3289
3290 if (!index)
3291 index = ctx->i32zero;
3292
3293 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3294
3295 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
3296 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3297
3298 return ac_build_indexed_load_const(&ctx->ac, list, index);
3299 }
3300
3301 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3302 struct ac_tex_info *tinfo,
3303 nir_tex_instr *instr,
3304 nir_texop op,
3305 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3306 LLVMValueRef *param, unsigned count,
3307 unsigned dmask)
3308 {
3309 int num_args;
3310 unsigned is_rect = 0;
3311 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3312
3313 if (op == nir_texop_lod)
3314 da = false;
3315 /* Pad to power of two vector */
3316 while (count < util_next_power_of_two(count))
3317 param[count++] = LLVMGetUndef(ctx->i32);
3318
3319 if (count > 1)
3320 tinfo->args[0] = ac_build_gather_values(&ctx->ac, param, count);
3321 else
3322 tinfo->args[0] = param[0];
3323
3324 tinfo->args[1] = res_ptr;
3325 num_args = 2;
3326
3327 if (op == nir_texop_txf ||
3328 op == nir_texop_txf_ms ||
3329 op == nir_texop_query_levels ||
3330 op == nir_texop_texture_samples ||
3331 op == nir_texop_txs)
3332 tinfo->dst_type = ctx->v4i32;
3333 else {
3334 tinfo->dst_type = ctx->v4f32;
3335 tinfo->args[num_args++] = samp_ptr;
3336 }
3337
3338 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3339 tinfo->args[0] = res_ptr;
3340 tinfo->args[1] = LLVMConstInt(ctx->i32, 0, false);
3341 tinfo->args[2] = param[0];
3342 tinfo->arg_count = 3;
3343 return;
3344 }
3345
3346 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, dmask, 0);
3347 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, is_rect, 0); /* unorm */
3348 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
3349 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
3350 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
3351 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
3352 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
3353 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
3354
3355 tinfo->arg_count = num_args;
3356 }
3357
3358 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3359 *
3360 * SI-CI:
3361 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3362 * filtering manually. The driver sets img7 to a mask clearing
3363 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3364 * s_and_b32 samp0, samp0, img7
3365 *
3366 * VI:
3367 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3368 */
3369 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3370 LLVMValueRef res, LLVMValueRef samp)
3371 {
3372 LLVMBuilderRef builder = ctx->builder;
3373 LLVMValueRef img7, samp0;
3374
3375 if (ctx->options->chip_class >= VI)
3376 return samp;
3377
3378 img7 = LLVMBuildExtractElement(builder, res,
3379 LLVMConstInt(ctx->i32, 7, 0), "");
3380 samp0 = LLVMBuildExtractElement(builder, samp,
3381 LLVMConstInt(ctx->i32, 0, 0), "");
3382 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3383 return LLVMBuildInsertElement(builder, samp, samp0,
3384 LLVMConstInt(ctx->i32, 0, 0), "");
3385 }
3386
3387 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3388 nir_tex_instr *instr,
3389 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3390 LLVMValueRef *fmask_ptr)
3391 {
3392 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3393 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3394 else
3395 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3396 if (samp_ptr) {
3397 if (instr->sampler)
3398 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3399 else
3400 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3401 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3402 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3403 }
3404 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3405 instr->op == nir_texop_samples_identical))
3406 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3407 }
3408
3409 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
3410 LLVMValueRef coord)
3411 {
3412 coord = to_float(ctx, coord);
3413 coord = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
3414 coord = to_integer(ctx, coord);
3415 return coord;
3416 }
3417
3418 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3419 {
3420 LLVMValueRef result = NULL;
3421 struct ac_tex_info tinfo = { 0 };
3422 unsigned dmask = 0xf;
3423 LLVMValueRef address[16];
3424 LLVMValueRef coords[5];
3425 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3426 LLVMValueRef bias = NULL, offsets = NULL;
3427 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3428 LLVMValueRef ddx = NULL, ddy = NULL;
3429 LLVMValueRef derivs[6];
3430 unsigned chan, count = 0;
3431 unsigned const_src = 0, num_deriv_comp = 0;
3432
3433 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3434
3435 for (unsigned i = 0; i < instr->num_srcs; i++) {
3436 switch (instr->src[i].src_type) {
3437 case nir_tex_src_coord:
3438 coord = get_src(ctx, instr->src[i].src);
3439 break;
3440 case nir_tex_src_projector:
3441 break;
3442 case nir_tex_src_comparator:
3443 comparator = get_src(ctx, instr->src[i].src);
3444 break;
3445 case nir_tex_src_offset:
3446 offsets = get_src(ctx, instr->src[i].src);
3447 const_src = i;
3448 break;
3449 case nir_tex_src_bias:
3450 bias = get_src(ctx, instr->src[i].src);
3451 break;
3452 case nir_tex_src_lod:
3453 lod = get_src(ctx, instr->src[i].src);
3454 break;
3455 case nir_tex_src_ms_index:
3456 sample_index = get_src(ctx, instr->src[i].src);
3457 break;
3458 case nir_tex_src_ms_mcs:
3459 break;
3460 case nir_tex_src_ddx:
3461 ddx = get_src(ctx, instr->src[i].src);
3462 num_deriv_comp = instr->src[i].src.ssa->num_components;
3463 break;
3464 case nir_tex_src_ddy:
3465 ddy = get_src(ctx, instr->src[i].src);
3466 break;
3467 case nir_tex_src_texture_offset:
3468 case nir_tex_src_sampler_offset:
3469 case nir_tex_src_plane:
3470 default:
3471 break;
3472 }
3473 }
3474
3475 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3476 result = get_buffer_size(ctx, res_ptr, false);
3477 goto write_result;
3478 }
3479
3480 if (instr->op == nir_texop_texture_samples) {
3481 LLVMValueRef res, samples, is_msaa;
3482 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3483 samples = LLVMBuildExtractElement(ctx->builder, res,
3484 LLVMConstInt(ctx->i32, 3, false), "");
3485 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3486 LLVMConstInt(ctx->i32, 28, false), "");
3487 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3488 LLVMConstInt(ctx->i32, 0xe, false), "");
3489 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3490 LLVMConstInt(ctx->i32, 0xe, false), "");
3491
3492 samples = LLVMBuildLShr(ctx->builder, samples,
3493 LLVMConstInt(ctx->i32, 16, false), "");
3494 samples = LLVMBuildAnd(ctx->builder, samples,
3495 LLVMConstInt(ctx->i32, 0xf, false), "");
3496 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3497 samples, "");
3498 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3499 ctx->i32one, "");
3500 result = samples;
3501 goto write_result;
3502 }
3503
3504 if (coord)
3505 for (chan = 0; chan < instr->coord_components; chan++)
3506 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3507
3508 if (offsets && instr->op != nir_texop_txf) {
3509 LLVMValueRef offset[3], pack;
3510 for (chan = 0; chan < 3; ++chan)
3511 offset[chan] = ctx->i32zero;
3512
3513 tinfo.has_offset = true;
3514 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3515 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3516 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3517 LLVMConstInt(ctx->i32, 0x3f, false), "");
3518 if (chan)
3519 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3520 LLVMConstInt(ctx->i32, chan * 8, false), "");
3521 }
3522 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3523 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3524 address[count++] = pack;
3525
3526 }
3527 /* pack LOD bias value */
3528 if (instr->op == nir_texop_txb && bias) {
3529 address[count++] = bias;
3530 }
3531
3532 /* Pack depth comparison value */
3533 if (instr->is_shadow && comparator) {
3534 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3535 }
3536
3537 /* pack derivatives */
3538 if (ddx || ddy) {
3539 switch (instr->sampler_dim) {
3540 case GLSL_SAMPLER_DIM_3D:
3541 case GLSL_SAMPLER_DIM_CUBE:
3542 num_deriv_comp = 3;
3543 break;
3544 case GLSL_SAMPLER_DIM_2D:
3545 default:
3546 num_deriv_comp = 2;
3547 break;
3548 case GLSL_SAMPLER_DIM_1D:
3549 num_deriv_comp = 1;
3550 break;
3551 }
3552
3553 for (unsigned i = 0; i < num_deriv_comp; i++) {
3554 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3555 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3556 }
3557 }
3558
3559 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3560 for (chan = 0; chan < instr->coord_components; chan++)
3561 coords[chan] = to_float(ctx, coords[chan]);
3562 if (instr->coord_components == 3)
3563 coords[3] = LLVMGetUndef(ctx->f32);
3564 ac_prepare_cube_coords(&ctx->ac,
3565 instr->op == nir_texop_txd, instr->is_array,
3566 coords, derivs);
3567 if (num_deriv_comp)
3568 num_deriv_comp--;
3569 }
3570
3571 if (ddx || ddy) {
3572 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3573 address[count++] = derivs[i];
3574 }
3575
3576 /* Pack texture coordinates */
3577 if (coord) {
3578 address[count++] = coords[0];
3579 if (instr->coord_components > 1) {
3580 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
3581 coords[1] = apply_round_slice(ctx, coords[1]);
3582 }
3583 address[count++] = coords[1];
3584 }
3585 if (instr->coord_components > 2) {
3586 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3587 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3588 coords[2] = apply_round_slice(ctx, coords[2]);
3589 }
3590 address[count++] = coords[2];
3591 }
3592 }
3593
3594 /* Pack LOD */
3595 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3596 address[count++] = lod;
3597 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3598 address[count++] = sample_index;
3599 } else if(instr->op == nir_texop_txs) {
3600 count = 0;
3601 if (lod)
3602 address[count++] = lod;
3603 else
3604 address[count++] = ctx->i32zero;
3605 }
3606
3607 for (chan = 0; chan < count; chan++) {
3608 address[chan] = LLVMBuildBitCast(ctx->builder,
3609 address[chan], ctx->i32, "");
3610 }
3611
3612 if (instr->op == nir_texop_samples_identical) {
3613 LLVMValueRef txf_address[4];
3614 struct ac_tex_info txf_info = { 0 };
3615 unsigned txf_count = count;
3616 memcpy(txf_address, address, sizeof(txf_address));
3617
3618 if (!instr->is_array)
3619 txf_address[2] = ctx->i32zero;
3620 txf_address[3] = ctx->i32zero;
3621
3622 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3623 fmask_ptr, NULL,
3624 txf_address, txf_count, 0xf);
3625
3626 result = build_tex_intrinsic(ctx, instr, &txf_info);
3627
3628 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3629 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3630 goto write_result;
3631 }
3632
3633 /* Adjust the sample index according to FMASK.
3634 *
3635 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3636 * which is the identity mapping. Each nibble says which physical sample
3637 * should be fetched to get that sample.
3638 *
3639 * For example, 0x11111100 means there are only 2 samples stored and
3640 * the second sample covers 3/4 of the pixel. When reading samples 0
3641 * and 1, return physical sample 0 (determined by the first two 0s
3642 * in FMASK), otherwise return physical sample 1.
3643 *
3644 * The sample index should be adjusted as follows:
3645 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3646 */
3647 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
3648 instr->op != nir_texop_txs) {
3649 LLVMValueRef txf_address[4];
3650 struct ac_tex_info txf_info = { 0 };
3651 unsigned txf_count = count;
3652 memcpy(txf_address, address, sizeof(txf_address));
3653
3654 if (!instr->is_array)
3655 txf_address[2] = ctx->i32zero;
3656 txf_address[3] = ctx->i32zero;
3657
3658 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3659 fmask_ptr, NULL,
3660 txf_address, txf_count, 0xf);
3661
3662 result = build_tex_intrinsic(ctx, instr, &txf_info);
3663 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3664 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3665
3666 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3667 result,
3668 ctx->i32zero, "");
3669
3670 unsigned sample_chan = instr->is_array ? 3 : 2;
3671
3672 LLVMValueRef sample_index4 =
3673 LLVMBuildMul(ctx->builder, address[sample_chan], four, "");
3674 LLVMValueRef shifted_fmask =
3675 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3676 LLVMValueRef final_sample =
3677 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3678
3679 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3680 * resource descriptor is 0 (invalid),
3681 */
3682 LLVMValueRef fmask_desc =
3683 LLVMBuildBitCast(ctx->builder, fmask_ptr,
3684 ctx->v8i32, "");
3685
3686 LLVMValueRef fmask_word1 =
3687 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3688 ctx->i32one, "");
3689
3690 LLVMValueRef word1_is_nonzero =
3691 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3692 fmask_word1, ctx->i32zero, "");
3693
3694 /* Replace the MSAA sample index. */
3695 address[sample_chan] =
3696 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3697 final_sample, address[sample_chan], "");
3698 }
3699
3700 if (offsets && instr->op == nir_texop_txf) {
3701 nir_const_value *const_offset =
3702 nir_src_as_const_value(instr->src[const_src].src);
3703 int num_offsets = instr->src[const_src].src.ssa->num_components;
3704 assert(const_offset);
3705 num_offsets = MIN2(num_offsets, instr->coord_components);
3706 if (num_offsets > 2)
3707 address[2] = LLVMBuildAdd(ctx->builder,
3708 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3709 if (num_offsets > 1)
3710 address[1] = LLVMBuildAdd(ctx->builder,
3711 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3712 address[0] = LLVMBuildAdd(ctx->builder,
3713 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3714
3715 }
3716
3717 /* TODO TG4 support */
3718 if (instr->op == nir_texop_tg4) {
3719 if (instr->is_shadow)
3720 dmask = 1;
3721 else
3722 dmask = 1 << instr->component;
3723 }
3724 set_tex_fetch_args(ctx, &tinfo, instr, instr->op,
3725 res_ptr, samp_ptr, address, count, dmask);
3726
3727 result = build_tex_intrinsic(ctx, instr, &tinfo);
3728
3729 if (instr->op == nir_texop_query_levels)
3730 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3731 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3732 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3733 else if (instr->op == nir_texop_txs &&
3734 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3735 instr->is_array) {
3736 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3737 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3738 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3739 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3740 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3741 } else if (instr->dest.ssa.num_components != 4)
3742 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3743
3744 write_result:
3745 if (result) {
3746 assert(instr->dest.is_ssa);
3747 result = to_integer(ctx, result);
3748 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3749 }
3750 }
3751
3752
3753 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3754 {
3755 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3756 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3757
3758 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3759 _mesa_hash_table_insert(ctx->phis, instr, result);
3760 }
3761
3762 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3763 nir_phi_instr *instr,
3764 LLVMValueRef llvm_phi)
3765 {
3766 nir_foreach_phi_src(src, instr) {
3767 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3768 LLVMValueRef llvm_src = get_src(ctx, src->src);
3769
3770 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3771 }
3772 }
3773
3774 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3775 {
3776 struct hash_entry *entry;
3777 hash_table_foreach(ctx->phis, entry) {
3778 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3779 (LLVMValueRef)entry->data);
3780 }
3781 }
3782
3783
3784 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3785 nir_ssa_undef_instr *instr)
3786 {
3787 unsigned num_components = instr->def.num_components;
3788 LLVMValueRef undef;
3789
3790 if (num_components == 1)
3791 undef = LLVMGetUndef(ctx->i32);
3792 else {
3793 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3794 }
3795 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3796 }
3797
3798 static void visit_jump(struct nir_to_llvm_context *ctx,
3799 nir_jump_instr *instr)
3800 {
3801 switch (instr->type) {
3802 case nir_jump_break:
3803 LLVMBuildBr(ctx->builder, ctx->break_block);
3804 LLVMClearInsertionPosition(ctx->builder);
3805 break;
3806 case nir_jump_continue:
3807 LLVMBuildBr(ctx->builder, ctx->continue_block);
3808 LLVMClearInsertionPosition(ctx->builder);
3809 break;
3810 default:
3811 fprintf(stderr, "Unknown NIR jump instr: ");
3812 nir_print_instr(&instr->instr, stderr);
3813 fprintf(stderr, "\n");
3814 abort();
3815 }
3816 }
3817
3818 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3819 struct exec_list *list);
3820
3821 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3822 {
3823 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3824 nir_foreach_instr(instr, block)
3825 {
3826 switch (instr->type) {
3827 case nir_instr_type_alu:
3828 visit_alu(ctx, nir_instr_as_alu(instr));
3829 break;
3830 case nir_instr_type_load_const:
3831 visit_load_const(ctx, nir_instr_as_load_const(instr));
3832 break;
3833 case nir_instr_type_intrinsic:
3834 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3835 break;
3836 case nir_instr_type_tex:
3837 visit_tex(ctx, nir_instr_as_tex(instr));
3838 break;
3839 case nir_instr_type_phi:
3840 visit_phi(ctx, nir_instr_as_phi(instr));
3841 break;
3842 case nir_instr_type_ssa_undef:
3843 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3844 break;
3845 case nir_instr_type_jump:
3846 visit_jump(ctx, nir_instr_as_jump(instr));
3847 break;
3848 default:
3849 fprintf(stderr, "Unknown NIR instr type: ");
3850 nir_print_instr(instr, stderr);
3851 fprintf(stderr, "\n");
3852 abort();
3853 }
3854 }
3855
3856 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3857 }
3858
3859 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3860 {
3861 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3862
3863 LLVMBasicBlockRef merge_block =
3864 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3865 LLVMBasicBlockRef if_block =
3866 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3867 LLVMBasicBlockRef else_block = merge_block;
3868 if (!exec_list_is_empty(&if_stmt->else_list))
3869 else_block = LLVMAppendBasicBlockInContext(
3870 ctx->context, ctx->main_function, "");
3871
3872 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3873 LLVMConstInt(ctx->i32, 0, false), "");
3874 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3875
3876 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3877 visit_cf_list(ctx, &if_stmt->then_list);
3878 if (LLVMGetInsertBlock(ctx->builder))
3879 LLVMBuildBr(ctx->builder, merge_block);
3880
3881 if (!exec_list_is_empty(&if_stmt->else_list)) {
3882 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3883 visit_cf_list(ctx, &if_stmt->else_list);
3884 if (LLVMGetInsertBlock(ctx->builder))
3885 LLVMBuildBr(ctx->builder, merge_block);
3886 }
3887
3888 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3889 }
3890
3891 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3892 {
3893 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3894 LLVMBasicBlockRef break_parent = ctx->break_block;
3895
3896 ctx->continue_block =
3897 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3898 ctx->break_block =
3899 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3900
3901 LLVMBuildBr(ctx->builder, ctx->continue_block);
3902 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
3903 visit_cf_list(ctx, &loop->body);
3904
3905 if (LLVMGetInsertBlock(ctx->builder))
3906 LLVMBuildBr(ctx->builder, ctx->continue_block);
3907 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
3908
3909 ctx->continue_block = continue_parent;
3910 ctx->break_block = break_parent;
3911 }
3912
3913 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3914 struct exec_list *list)
3915 {
3916 foreach_list_typed(nir_cf_node, node, node, list)
3917 {
3918 switch (node->type) {
3919 case nir_cf_node_block:
3920 visit_block(ctx, nir_cf_node_as_block(node));
3921 break;
3922
3923 case nir_cf_node_if:
3924 visit_if(ctx, nir_cf_node_as_if(node));
3925 break;
3926
3927 case nir_cf_node_loop:
3928 visit_loop(ctx, nir_cf_node_as_loop(node));
3929 break;
3930
3931 default:
3932 assert(0);
3933 }
3934 }
3935 }
3936
3937 static void
3938 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
3939 struct nir_variable *variable)
3940 {
3941 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
3942 LLVMValueRef t_offset;
3943 LLVMValueRef t_list;
3944 LLVMValueRef args[3];
3945 LLVMValueRef input;
3946 LLVMValueRef buffer_index;
3947 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
3948 int idx = variable->data.location;
3949 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
3950
3951 variable->data.driver_location = idx * 4;
3952
3953 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
3954 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
3955 ctx->start_instance, "");
3956 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3957 ctx->shader_info->vs.vgpr_comp_cnt);
3958 } else
3959 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
3960 ctx->base_vertex, "");
3961
3962 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
3963 t_offset = LLVMConstInt(ctx->i32, index + i, false);
3964
3965 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
3966 args[0] = t_list;
3967 args[1] = LLVMConstInt(ctx->i32, 0, false);
3968 args[2] = buffer_index;
3969 input = ac_emit_llvm_intrinsic(&ctx->ac,
3970 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
3971 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
3972
3973 for (unsigned chan = 0; chan < 4; chan++) {
3974 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3975 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
3976 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
3977 input, llvm_chan, ""));
3978 }
3979 }
3980 }
3981
3982 static void
3983 handle_gs_input_decl(struct nir_to_llvm_context *ctx,
3984 struct nir_variable *variable)
3985 {
3986 int idx = variable->data.location;
3987
3988 if (idx == VARYING_SLOT_CLIP_DIST0 ||
3989 idx == VARYING_SLOT_CULL_DIST0) {
3990 int length = glsl_get_length(glsl_get_array_element(variable->type));
3991 if (idx == VARYING_SLOT_CLIP_DIST0)
3992 ctx->num_input_clips = length;
3993 else
3994 ctx->num_input_culls = length;
3995 }
3996 }
3997
3998 static void interp_fs_input(struct nir_to_llvm_context *ctx,
3999 unsigned attr,
4000 LLVMValueRef interp_param,
4001 LLVMValueRef prim_mask,
4002 LLVMValueRef result[4])
4003 {
4004 LLVMValueRef attr_number;
4005 unsigned chan;
4006 LLVMValueRef i, j;
4007 bool interp = interp_param != NULL;
4008
4009 attr_number = LLVMConstInt(ctx->i32, attr, false);
4010
4011 /* fs.constant returns the param from the middle vertex, so it's not
4012 * really useful for flat shading. It's meant to be used for custom
4013 * interpolation (but the intrinsic can't fetch from the other two
4014 * vertices).
4015 *
4016 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4017 * to do the right thing. The only reason we use fs.constant is that
4018 * fs.interp cannot be used on integers, because they can be equal
4019 * to NaN.
4020 */
4021 if (interp) {
4022 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4023 LLVMVectorType(ctx->f32, 2), "");
4024
4025 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4026 ctx->i32zero, "");
4027 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4028 ctx->i32one, "");
4029 }
4030
4031 for (chan = 0; chan < 4; chan++) {
4032 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4033
4034 if (interp) {
4035 result[chan] = ac_build_fs_interp(&ctx->ac,
4036 llvm_chan,
4037 attr_number,
4038 prim_mask, i, j);
4039 } else {
4040 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4041 LLVMConstInt(ctx->i32, 2, false),
4042 llvm_chan,
4043 attr_number,
4044 prim_mask);
4045 }
4046 }
4047 }
4048
4049 static void
4050 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4051 struct nir_variable *variable)
4052 {
4053 int idx = variable->data.location;
4054 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4055 LLVMValueRef interp;
4056
4057 variable->data.driver_location = idx * 4;
4058 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4059
4060 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4061 unsigned interp_type;
4062 if (variable->data.sample) {
4063 interp_type = INTERP_SAMPLE;
4064 ctx->shader_info->fs.force_persample = true;
4065 } else if (variable->data.centroid)
4066 interp_type = INTERP_CENTROID;
4067 else
4068 interp_type = INTERP_CENTER;
4069
4070 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4071 } else
4072 interp = NULL;
4073
4074 for (unsigned i = 0; i < attrib_count; ++i)
4075 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4076
4077 }
4078
4079 static void
4080 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4081 struct nir_variable *variable)
4082 {
4083 switch (ctx->stage) {
4084 case MESA_SHADER_VERTEX:
4085 handle_vs_input_decl(ctx, variable);
4086 break;
4087 case MESA_SHADER_FRAGMENT:
4088 handle_fs_input_decl(ctx, variable);
4089 break;
4090 case MESA_SHADER_GEOMETRY:
4091 handle_gs_input_decl(ctx, variable);
4092 break;
4093 default:
4094 break;
4095 }
4096
4097 }
4098
4099 static void
4100 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4101 struct nir_shader *nir)
4102 {
4103 unsigned index = 0;
4104 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4105 LLVMValueRef interp_param;
4106 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4107
4108 if (!(ctx->input_mask & (1ull << i)))
4109 continue;
4110
4111 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4112 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4113 interp_param = *inputs;
4114 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4115 inputs);
4116
4117 if (!interp_param)
4118 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4119 ++index;
4120 } else if (i == VARYING_SLOT_POS) {
4121 for(int i = 0; i < 3; ++i)
4122 inputs[i] = ctx->frag_pos[i];
4123
4124 inputs[3] = ac_emit_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4125 }
4126 }
4127 ctx->shader_info->fs.num_interp = index;
4128 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4129 ctx->shader_info->fs.has_pcoord = true;
4130 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4131 ctx->shader_info->fs.prim_id_input = true;
4132 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4133 ctx->shader_info->fs.layer_input = true;
4134 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4135 }
4136
4137 static LLVMValueRef
4138 ac_build_alloca(struct nir_to_llvm_context *ctx,
4139 LLVMTypeRef type,
4140 const char *name)
4141 {
4142 LLVMBuilderRef builder = ctx->builder;
4143 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4144 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4145 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4146 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4147 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4148 LLVMValueRef res;
4149
4150 if (first_instr) {
4151 LLVMPositionBuilderBefore(first_builder, first_instr);
4152 } else {
4153 LLVMPositionBuilderAtEnd(first_builder, first_block);
4154 }
4155
4156 res = LLVMBuildAlloca(first_builder, type, name);
4157 LLVMBuildStore(builder, LLVMConstNull(type), res);
4158
4159 LLVMDisposeBuilder(first_builder);
4160
4161 return res;
4162 }
4163
4164 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4165 LLVMTypeRef type,
4166 const char *name)
4167 {
4168 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4169 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4170 return ptr;
4171 }
4172
4173 static void
4174 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4175 struct nir_variable *variable)
4176 {
4177 int idx = variable->data.location + variable->data.index;
4178 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4179
4180 variable->data.driver_location = idx * 4;
4181
4182 if (ctx->stage == MESA_SHADER_VERTEX ||
4183 ctx->stage == MESA_SHADER_GEOMETRY) {
4184 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4185 idx == VARYING_SLOT_CULL_DIST0) {
4186 int length = glsl_get_length(variable->type);
4187 if (idx == VARYING_SLOT_CLIP_DIST0) {
4188 if (ctx->stage == MESA_SHADER_VERTEX)
4189 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
4190 ctx->num_output_clips = length;
4191 } else if (idx == VARYING_SLOT_CULL_DIST0) {
4192 if (ctx->stage == MESA_SHADER_VERTEX)
4193 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
4194 ctx->num_output_culls = length;
4195 }
4196 if (length > 4)
4197 attrib_count = 2;
4198 else
4199 attrib_count = 1;
4200 }
4201 }
4202
4203 for (unsigned i = 0; i < attrib_count; ++i) {
4204 for (unsigned chan = 0; chan < 4; chan++) {
4205 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4206 si_build_alloca_undef(ctx, ctx->f32, "");
4207 }
4208 }
4209 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
4210 }
4211
4212 static void
4213 setup_locals(struct nir_to_llvm_context *ctx,
4214 struct nir_function *func)
4215 {
4216 int i, j;
4217 ctx->num_locals = 0;
4218 nir_foreach_variable(variable, &func->impl->locals) {
4219 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4220 variable->data.driver_location = ctx->num_locals * 4;
4221 ctx->num_locals += attrib_count;
4222 }
4223 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4224 if (!ctx->locals)
4225 return;
4226
4227 for (i = 0; i < ctx->num_locals; i++) {
4228 for (j = 0; j < 4; j++) {
4229 ctx->locals[i * 4 + j] =
4230 si_build_alloca_undef(ctx, ctx->f32, "temp");
4231 }
4232 }
4233 }
4234
4235 static LLVMValueRef
4236 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4237 {
4238 v = to_float(ctx, v);
4239 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4240 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4241 }
4242
4243
4244 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4245 LLVMValueRef src0, LLVMValueRef src1)
4246 {
4247 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4248 LLVMValueRef comp[2];
4249
4250 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4251 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4252 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4253 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4254 }
4255
4256 /* Initialize arguments for the shader export intrinsic */
4257 static void
4258 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4259 LLVMValueRef *values,
4260 unsigned target,
4261 LLVMValueRef *args)
4262 {
4263 /* Default is 0xf. Adjusted below depending on the format. */
4264 args[0] = LLVMConstInt(ctx->i32, target != V_008DFC_SQ_EXP_NULL ? 0xf : 0, false);
4265 /* Specify whether the EXEC mask represents the valid mask */
4266 args[1] = LLVMConstInt(ctx->i32, 0, false);
4267
4268 /* Specify whether this is the last export */
4269 args[2] = LLVMConstInt(ctx->i32, 0, false);
4270 /* Specify the target we are exporting */
4271 args[3] = LLVMConstInt(ctx->i32, target, false);
4272
4273 args[4] = LLVMConstInt(ctx->i32, 0, false); /* COMPR flag */
4274 args[5] = LLVMGetUndef(ctx->f32);
4275 args[6] = LLVMGetUndef(ctx->f32);
4276 args[7] = LLVMGetUndef(ctx->f32);
4277 args[8] = LLVMGetUndef(ctx->f32);
4278
4279 if (!values)
4280 return;
4281
4282 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4283 LLVMValueRef val[4];
4284 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4285 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4286 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4287
4288 switch(col_format) {
4289 case V_028714_SPI_SHADER_ZERO:
4290 args[0] = LLVMConstInt(ctx->i32, 0x0, 0);
4291 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_NULL, 0);
4292 break;
4293
4294 case V_028714_SPI_SHADER_32_R:
4295 args[0] = LLVMConstInt(ctx->i32, 0x1, 0);
4296 args[5] = values[0];
4297 break;
4298
4299 case V_028714_SPI_SHADER_32_GR:
4300 args[0] = LLVMConstInt(ctx->i32, 0x3, 0);
4301 args[5] = values[0];
4302 args[6] = values[1];
4303 break;
4304
4305 case V_028714_SPI_SHADER_32_AR:
4306 args[0] = LLVMConstInt(ctx->i32, 0x9, 0);
4307 args[5] = values[0];
4308 args[8] = values[3];
4309 break;
4310
4311 case V_028714_SPI_SHADER_FP16_ABGR:
4312 args[4] = ctx->i32one;
4313
4314 for (unsigned chan = 0; chan < 2; chan++) {
4315 LLVMValueRef pack_args[2] = {
4316 values[2 * chan],
4317 values[2 * chan + 1]
4318 };
4319 LLVMValueRef packed;
4320
4321 packed = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.packf16",
4322 ctx->i32, pack_args, 2,
4323 AC_FUNC_ATTR_READNONE);
4324 args[chan + 5] = packed;
4325 }
4326 break;
4327
4328 case V_028714_SPI_SHADER_UNORM16_ABGR:
4329 for (unsigned chan = 0; chan < 4; chan++) {
4330 val[chan] = emit_float_saturate(ctx, values[chan], 0, 1);
4331 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4332 LLVMConstReal(ctx->f32, 65535), "");
4333 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4334 LLVMConstReal(ctx->f32, 0.5), "");
4335 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4336 ctx->i32, "");
4337 }
4338
4339 args[4] = ctx->i32one;
4340 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4341 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4342 break;
4343
4344 case V_028714_SPI_SHADER_SNORM16_ABGR:
4345 for (unsigned chan = 0; chan < 4; chan++) {
4346 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4347 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4348 LLVMConstReal(ctx->f32, 32767), "");
4349
4350 /* If positive, add 0.5, else add -0.5. */
4351 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4352 LLVMBuildSelect(ctx->builder,
4353 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4354 val[chan], ctx->f32zero, ""),
4355 LLVMConstReal(ctx->f32, 0.5),
4356 LLVMConstReal(ctx->f32, -0.5), ""), "");
4357 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4358 }
4359
4360 args[4] = ctx->i32one;
4361 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4362 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4363 break;
4364
4365 case V_028714_SPI_SHADER_UINT16_ABGR: {
4366 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4367
4368 for (unsigned chan = 0; chan < 4; chan++) {
4369 val[chan] = to_integer(ctx, values[chan]);
4370 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4371 }
4372
4373 args[4] = ctx->i32one;
4374 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4375 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4376 break;
4377 }
4378
4379 case V_028714_SPI_SHADER_SINT16_ABGR: {
4380 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4381 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4382
4383 /* Clamp. */
4384 for (unsigned chan = 0; chan < 4; chan++) {
4385 val[chan] = to_integer(ctx, values[chan]);
4386 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4387 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4388 }
4389
4390 args[4] = ctx->i32one;
4391 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4392 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4393 break;
4394 }
4395
4396 default:
4397 case V_028714_SPI_SHADER_32_ABGR:
4398 memcpy(&args[5], values, sizeof(values[0]) * 4);
4399 break;
4400 }
4401 } else
4402 memcpy(&args[5], values, sizeof(values[0]) * 4);
4403
4404 for (unsigned i = 5; i < 9; ++i)
4405 args[i] = to_float(ctx, args[i]);
4406 }
4407
4408 static void
4409 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4410 {
4411 uint32_t param_count = 0;
4412 unsigned target;
4413 unsigned pos_idx, num_pos_exports = 0;
4414 LLVMValueRef args[9];
4415 LLVMValueRef pos_args[4][9] = { { 0 } };
4416 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4417 int i;
4418 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4419 (1ull << VARYING_SLOT_CLIP_DIST1) |
4420 (1ull << VARYING_SLOT_CULL_DIST0) |
4421 (1ull << VARYING_SLOT_CULL_DIST1));
4422
4423 ctx->shader_info->vs.prim_id_output = 0xffffffff;
4424 ctx->shader_info->vs.layer_output = 0xffffffff;
4425 if (clip_mask) {
4426 LLVMValueRef slots[8];
4427 unsigned j;
4428
4429 if (ctx->shader_info->vs.cull_dist_mask)
4430 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_output_clips;
4431
4432 i = VARYING_SLOT_CLIP_DIST0;
4433 for (j = 0; j < ctx->num_output_clips; j++)
4434 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4435 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4436 i = VARYING_SLOT_CULL_DIST0;
4437 for (j = 0; j < ctx->num_output_culls; j++)
4438 slots[ctx->num_output_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4439 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4440
4441 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
4442 slots[i] = LLVMGetUndef(ctx->f32);
4443
4444 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
4445 target = V_008DFC_SQ_EXP_POS + 3;
4446 si_llvm_init_export_args(ctx, &slots[4], target, args);
4447 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4448 args, sizeof(args));
4449 }
4450
4451 target = V_008DFC_SQ_EXP_POS + 2;
4452 si_llvm_init_export_args(ctx, &slots[0], target, args);
4453 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4454 args, sizeof(args));
4455
4456 }
4457
4458 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4459 LLVMValueRef values[4];
4460 if (!(ctx->output_mask & (1ull << i)))
4461 continue;
4462
4463 for (unsigned j = 0; j < 4; j++)
4464 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4465 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4466
4467 if (i == VARYING_SLOT_POS) {
4468 target = V_008DFC_SQ_EXP_POS;
4469 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4470 i == VARYING_SLOT_CLIP_DIST1 ||
4471 i == VARYING_SLOT_CULL_DIST0 ||
4472 i == VARYING_SLOT_CULL_DIST1) {
4473 continue;
4474 } else if (i == VARYING_SLOT_PSIZ) {
4475 ctx->shader_info->vs.writes_pointsize = true;
4476 psize_value = values[0];
4477 continue;
4478 } else if (i == VARYING_SLOT_LAYER) {
4479 ctx->shader_info->vs.writes_layer = true;
4480 layer_value = values[0];
4481 ctx->shader_info->vs.layer_output = param_count;
4482 target = V_008DFC_SQ_EXP_PARAM + param_count;
4483 param_count++;
4484 } else if (i == VARYING_SLOT_VIEWPORT) {
4485 ctx->shader_info->vs.writes_viewport_index = true;
4486 viewport_index_value = values[0];
4487 continue;
4488 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
4489 ctx->shader_info->vs.prim_id_output = param_count;
4490 target = V_008DFC_SQ_EXP_PARAM + param_count;
4491 param_count++;
4492 } else if (i >= VARYING_SLOT_VAR0) {
4493 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4494 target = V_008DFC_SQ_EXP_PARAM + param_count;
4495 param_count++;
4496 }
4497
4498 si_llvm_init_export_args(ctx, values, target, args);
4499
4500 if (target >= V_008DFC_SQ_EXP_POS &&
4501 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4502 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4503 args, sizeof(args));
4504 } else {
4505 ac_emit_llvm_intrinsic(&ctx->ac,
4506 "llvm.SI.export",
4507 ctx->voidt,
4508 args, 9, 0);
4509 }
4510 }
4511
4512 /* We need to add the position output manually if it's missing. */
4513 if (!pos_args[0][0]) {
4514 pos_args[0][0] = LLVMConstInt(ctx->i32, 0xf, false);
4515 pos_args[0][1] = ctx->i32zero; /* EXEC mask */
4516 pos_args[0][2] = ctx->i32zero; /* last export? */
4517 pos_args[0][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS, false);
4518 pos_args[0][4] = ctx->i32zero; /* COMPR flag */
4519 pos_args[0][5] = ctx->f32zero; /* X */
4520 pos_args[0][6] = ctx->f32zero; /* Y */
4521 pos_args[0][7] = ctx->f32zero; /* Z */
4522 pos_args[0][8] = ctx->f32one; /* W */
4523 }
4524
4525 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4526 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4527 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4528 if (mask) {
4529 pos_args[1][0] = LLVMConstInt(ctx->i32, mask, false); /* writemask */
4530 pos_args[1][1] = ctx->i32zero; /* EXEC mask */
4531 pos_args[1][2] = ctx->i32zero; /* last export? */
4532 pos_args[1][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + 1, false);
4533 pos_args[1][4] = ctx->i32zero; /* COMPR flag */
4534 pos_args[1][5] = ctx->f32zero; /* X */
4535 pos_args[1][6] = ctx->f32zero; /* Y */
4536 pos_args[1][7] = ctx->f32zero; /* Z */
4537 pos_args[1][8] = ctx->f32zero; /* W */
4538
4539 if (ctx->shader_info->vs.writes_pointsize == true)
4540 pos_args[1][5] = psize_value;
4541 if (ctx->shader_info->vs.writes_layer == true)
4542 pos_args[1][7] = layer_value;
4543 if (ctx->shader_info->vs.writes_viewport_index == true)
4544 pos_args[1][8] = viewport_index_value;
4545 }
4546 for (i = 0; i < 4; i++) {
4547 if (pos_args[i][0])
4548 num_pos_exports++;
4549 }
4550
4551 pos_idx = 0;
4552 for (i = 0; i < 4; i++) {
4553 if (!pos_args[i][0])
4554 continue;
4555
4556 /* Specify the target we are exporting */
4557 pos_args[i][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + pos_idx++, false);
4558 if (pos_idx == num_pos_exports)
4559 pos_args[i][2] = ctx->i32one;
4560 ac_emit_llvm_intrinsic(&ctx->ac,
4561 "llvm.SI.export",
4562 ctx->voidt,
4563 pos_args[i], 9, 0);
4564 }
4565
4566 ctx->shader_info->vs.pos_exports = num_pos_exports;
4567 ctx->shader_info->vs.param_exports = param_count;
4568 }
4569
4570 static void
4571 handle_es_outputs_post(struct nir_to_llvm_context *ctx)
4572 {
4573 int j;
4574 uint64_t max_output_written = 0;
4575 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4576 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
4577 int param_index;
4578 int length = 4;
4579 int start = 0;
4580 if (!(ctx->output_mask & (1ull << i)))
4581 continue;
4582
4583 if (i == VARYING_SLOT_CLIP_DIST0) {
4584 length = ctx->num_output_clips;
4585 } else if (i == VARYING_SLOT_CULL_DIST0) {
4586 start = ctx->num_output_clips;
4587 length = ctx->num_output_culls;
4588 }
4589 param_index = shader_io_get_unique_index(i);
4590
4591 if (param_index > max_output_written)
4592 max_output_written = param_index;
4593
4594 for (j = 0; j < length; j++) {
4595 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
4596 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4597
4598 ac_build_tbuffer_store(&ctx->ac,
4599 ctx->esgs_ring,
4600 out_val, 1,
4601 LLVMGetUndef(ctx->i32), ctx->es2gs_offset,
4602 (4 * param_index + j + start) * 4,
4603 V_008F0C_BUF_DATA_FORMAT_32,
4604 V_008F0C_BUF_NUM_FORMAT_UINT,
4605 0, 0, 1, 1, 0);
4606 }
4607 }
4608 ctx->shader_info->vs.esgs_itemsize = (max_output_written + 1) * 16;
4609 }
4610
4611 static void
4612 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4613 LLVMValueRef *color, unsigned param, bool is_last)
4614 {
4615 LLVMValueRef args[9];
4616 /* Export */
4617 si_llvm_init_export_args(ctx, color, param,
4618 args);
4619
4620 if (is_last) {
4621 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4622 args[2] = ctx->i32one; /* DONE bit */
4623 } else if (args[0] == ctx->i32zero)
4624 return; /* unnecessary NULL export */
4625
4626 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4627 ctx->voidt, args, 9, 0);
4628 }
4629
4630 static void
4631 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4632 LLVMValueRef depth, LLVMValueRef stencil,
4633 LLVMValueRef samplemask)
4634 {
4635 LLVMValueRef args[9];
4636 unsigned mask = 0;
4637 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4638 args[2] = ctx->i32one; /* DONE bit */
4639 /* Specify the target we are exporting */
4640 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_MRTZ, false);
4641
4642 args[4] = ctx->i32zero; /* COMP flag */
4643 args[5] = LLVMGetUndef(ctx->f32); /* R, depth */
4644 args[6] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4645 args[7] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4646 args[8] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4647
4648 if (depth) {
4649 args[5] = depth;
4650 mask |= 0x1;
4651 }
4652
4653 if (stencil) {
4654 args[6] = stencil;
4655 mask |= 0x2;
4656 }
4657
4658 if (samplemask) {
4659 args[7] = samplemask;
4660 mask |= 0x04;
4661 }
4662
4663 /* SI (except OLAND) has a bug that it only looks
4664 * at the X writemask component. */
4665 if (ctx->options->chip_class == SI &&
4666 ctx->options->family != CHIP_OLAND)
4667 mask |= 0x01;
4668
4669 args[0] = LLVMConstInt(ctx->i32, mask, false);
4670 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4671 ctx->voidt, args, 9, 0);
4672 }
4673
4674 static void
4675 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4676 {
4677 unsigned index = 0;
4678 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4679
4680 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4681 LLVMValueRef values[4];
4682
4683 if (!(ctx->output_mask & (1ull << i)))
4684 continue;
4685
4686 if (i == FRAG_RESULT_DEPTH) {
4687 ctx->shader_info->fs.writes_z = true;
4688 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4689 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4690 } else if (i == FRAG_RESULT_STENCIL) {
4691 ctx->shader_info->fs.writes_stencil = true;
4692 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4693 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4694 } else {
4695 bool last = false;
4696 for (unsigned j = 0; j < 4; j++)
4697 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4698 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4699
4700 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil)
4701 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4702
4703 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4704 index++;
4705 }
4706 }
4707
4708 if (depth || stencil)
4709 si_export_mrt_z(ctx, depth, stencil, samplemask);
4710 else if (!index)
4711 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4712
4713 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4714 }
4715
4716 static void
4717 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4718 {
4719 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
4720 }
4721
4722 static void
4723 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4724 {
4725 switch (ctx->stage) {
4726 case MESA_SHADER_VERTEX:
4727 if (ctx->options->key.vs.as_es)
4728 handle_es_outputs_post(ctx);
4729 else
4730 handle_vs_outputs_post(ctx);
4731 break;
4732 case MESA_SHADER_FRAGMENT:
4733 handle_fs_outputs_post(ctx);
4734 break;
4735 case MESA_SHADER_GEOMETRY:
4736 emit_gs_epilogue(ctx);
4737 break;
4738 default:
4739 break;
4740 }
4741 }
4742
4743 static void
4744 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4745 struct nir_variable *variable, uint32_t *offset, int idx)
4746 {
4747 unsigned size = glsl_count_attribute_slots(variable->type, false);
4748 variable->data.driver_location = *offset;
4749 *offset += size;
4750 }
4751
4752 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4753 {
4754 LLVMPassManagerRef passmgr;
4755 /* Create the pass manager */
4756 passmgr = LLVMCreateFunctionPassManagerForModule(
4757 ctx->module);
4758
4759 /* This pass should eliminate all the load and store instructions */
4760 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4761
4762 /* Add some optimization passes */
4763 LLVMAddScalarReplAggregatesPass(passmgr);
4764 LLVMAddLICMPass(passmgr);
4765 LLVMAddAggressiveDCEPass(passmgr);
4766 LLVMAddCFGSimplificationPass(passmgr);
4767 LLVMAddInstructionCombiningPass(passmgr);
4768
4769 /* Run the pass */
4770 LLVMInitializeFunctionPassManager(passmgr);
4771 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4772 LLVMFinalizeFunctionPassManager(passmgr);
4773
4774 LLVMDisposeBuilder(ctx->builder);
4775 LLVMDisposePassManager(passmgr);
4776 }
4777
4778 static void
4779 ac_setup_rings(struct nir_to_llvm_context *ctx)
4780 {
4781 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4782 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, ctx->i32one);
4783 }
4784
4785 if (ctx->is_gs_copy_shader) {
4786 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4787 }
4788 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4789 LLVMValueRef tmp;
4790 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4791 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4792
4793 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4794
4795 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4796 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4797 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4798 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4799
4800 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4801 }
4802 }
4803
4804 static
4805 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4806 struct nir_shader *nir,
4807 struct ac_shader_variant_info *shader_info,
4808 const struct ac_nir_compiler_options *options)
4809 {
4810 struct nir_to_llvm_context ctx = {0};
4811 struct nir_function *func;
4812 unsigned i;
4813 ctx.options = options;
4814 ctx.shader_info = shader_info;
4815 ctx.context = LLVMContextCreate();
4816 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4817
4818 ac_llvm_context_init(&ctx.ac, ctx.context);
4819 ctx.ac.module = ctx.module;
4820
4821 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4822
4823 memset(shader_info, 0, sizeof(*shader_info));
4824
4825 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4826 setup_types(&ctx);
4827
4828 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4829 ctx.ac.builder = ctx.builder;
4830 ctx.stage = nir->stage;
4831
4832 for (i = 0; i < AC_UD_MAX_SETS; i++)
4833 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4834 for (i = 0; i < AC_UD_MAX_UD; i++)
4835 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4836
4837 create_function(&ctx);
4838
4839 if (nir->stage == MESA_SHADER_COMPUTE) {
4840 int num_shared = 0;
4841 nir_foreach_variable(variable, &nir->shared)
4842 num_shared++;
4843 if (num_shared) {
4844 int idx = 0;
4845 uint32_t shared_size = 0;
4846 LLVMValueRef var;
4847 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4848 nir_foreach_variable(variable, &nir->shared) {
4849 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4850 idx++;
4851 }
4852
4853 shared_size *= 16;
4854 var = LLVMAddGlobalInAddressSpace(ctx.module,
4855 LLVMArrayType(ctx.i8, shared_size),
4856 "compute_lds",
4857 LOCAL_ADDR_SPACE);
4858 LLVMSetAlignment(var, 4);
4859 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4860 }
4861 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4862 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4863
4864 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4865 }
4866
4867 ac_setup_rings(&ctx);
4868
4869 nir_foreach_variable(variable, &nir->inputs)
4870 handle_shader_input_decl(&ctx, variable);
4871
4872 if (nir->stage == MESA_SHADER_FRAGMENT)
4873 handle_fs_inputs_pre(&ctx, nir);
4874
4875 nir_foreach_variable(variable, &nir->outputs)
4876 handle_shader_output_decl(&ctx, variable);
4877
4878 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4879 _mesa_key_pointer_equal);
4880 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4881 _mesa_key_pointer_equal);
4882
4883 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4884
4885 setup_locals(&ctx, func);
4886
4887 visit_cf_list(&ctx, &func->impl->body);
4888 phi_post_pass(&ctx);
4889
4890 handle_shader_outputs_post(&ctx);
4891 LLVMBuildRetVoid(ctx.builder);
4892
4893 ac_llvm_finalize_module(&ctx);
4894 free(ctx.locals);
4895 ralloc_free(ctx.defs);
4896 ralloc_free(ctx.phis);
4897
4898 if (nir->stage == MESA_SHADER_GEOMETRY) {
4899 shader_info->gs.gsvs_vertex_size = util_bitcount64(ctx.output_mask) * 16;
4900 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
4901 nir->info->gs.vertices_out;
4902 }
4903 return ctx.module;
4904 }
4905
4906 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4907 {
4908 unsigned *retval = (unsigned *)context;
4909 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4910 char *description = LLVMGetDiagInfoDescription(di);
4911
4912 if (severity == LLVMDSError) {
4913 *retval = 1;
4914 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4915 description);
4916 }
4917
4918 LLVMDisposeMessage(description);
4919 }
4920
4921 static unsigned ac_llvm_compile(LLVMModuleRef M,
4922 struct ac_shader_binary *binary,
4923 LLVMTargetMachineRef tm)
4924 {
4925 unsigned retval = 0;
4926 char *err;
4927 LLVMContextRef llvm_ctx;
4928 LLVMMemoryBufferRef out_buffer;
4929 unsigned buffer_size;
4930 const char *buffer_data;
4931 LLVMBool mem_err;
4932
4933 /* Setup Diagnostic Handler*/
4934 llvm_ctx = LLVMGetModuleContext(M);
4935
4936 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4937 &retval);
4938
4939 /* Compile IR*/
4940 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
4941 &err, &out_buffer);
4942
4943 /* Process Errors/Warnings */
4944 if (mem_err) {
4945 fprintf(stderr, "%s: %s", __FUNCTION__, err);
4946 free(err);
4947 retval = 1;
4948 goto out;
4949 }
4950
4951 /* Extract Shader Code*/
4952 buffer_size = LLVMGetBufferSize(out_buffer);
4953 buffer_data = LLVMGetBufferStart(out_buffer);
4954
4955 ac_elf_read(buffer_data, buffer_size, binary);
4956
4957 /* Clean up */
4958 LLVMDisposeMemoryBuffer(out_buffer);
4959
4960 out:
4961 return retval;
4962 }
4963
4964 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
4965 LLVMModuleRef llvm_module,
4966 struct ac_shader_binary *binary,
4967 struct ac_shader_config *config,
4968 struct ac_shader_variant_info *shader_info,
4969 gl_shader_stage stage,
4970 bool dump_shader, bool supports_spill)
4971 {
4972 if (dump_shader)
4973 ac_dump_module(llvm_module);
4974
4975 memset(binary, 0, sizeof(*binary));
4976 int v = ac_llvm_compile(llvm_module, binary, tm);
4977 if (v) {
4978 fprintf(stderr, "compile failed\n");
4979 }
4980
4981 if (dump_shader)
4982 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
4983
4984 ac_shader_binary_read_config(binary, config, 0, supports_spill);
4985
4986 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4987 LLVMDisposeModule(llvm_module);
4988 LLVMContextDispose(ctx);
4989
4990 if (stage == MESA_SHADER_FRAGMENT) {
4991 shader_info->num_input_vgprs = 0;
4992 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
4993 shader_info->num_input_vgprs += 2;
4994 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
4995 shader_info->num_input_vgprs += 2;
4996 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
4997 shader_info->num_input_vgprs += 2;
4998 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
4999 shader_info->num_input_vgprs += 3;
5000 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
5001 shader_info->num_input_vgprs += 2;
5002 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
5003 shader_info->num_input_vgprs += 2;
5004 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
5005 shader_info->num_input_vgprs += 2;
5006 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
5007 shader_info->num_input_vgprs += 1;
5008 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
5009 shader_info->num_input_vgprs += 1;
5010 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
5011 shader_info->num_input_vgprs += 1;
5012 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5013 shader_info->num_input_vgprs += 1;
5014 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5015 shader_info->num_input_vgprs += 1;
5016 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5017 shader_info->num_input_vgprs += 1;
5018 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5019 shader_info->num_input_vgprs += 1;
5020 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5021 shader_info->num_input_vgprs += 1;
5022 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5023 shader_info->num_input_vgprs += 1;
5024 }
5025 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5026
5027 /* +3 for scratch wave offset and VCC */
5028 config->num_sgprs = MAX2(config->num_sgprs,
5029 shader_info->num_input_sgprs + 3);
5030 }
5031
5032 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5033 struct ac_shader_binary *binary,
5034 struct ac_shader_config *config,
5035 struct ac_shader_variant_info *shader_info,
5036 struct nir_shader *nir,
5037 const struct ac_nir_compiler_options *options,
5038 bool dump_shader)
5039 {
5040
5041 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5042 options);
5043
5044 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5045 switch (nir->stage) {
5046 case MESA_SHADER_COMPUTE:
5047 for (int i = 0; i < 3; ++i)
5048 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5049 break;
5050 case MESA_SHADER_FRAGMENT:
5051 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5052 break;
5053 case MESA_SHADER_GEOMETRY:
5054 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5055 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5056 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5057 shader_info->gs.invocations = nir->info->gs.invocations;
5058 break;
5059 case MESA_SHADER_VERTEX:
5060 shader_info->vs.as_es = options->key.vs.as_es;
5061 break;
5062 default:
5063 break;
5064 }
5065 }
5066
5067 static void
5068 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5069 {
5070 LLVMValueRef args[9];
5071 args[0] = ctx->gsvs_ring;
5072 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5073 args[3] = ctx->i32zero;
5074 args[4] = ctx->i32one; /* OFFEN */
5075 args[5] = ctx->i32zero; /* IDXEN */
5076 args[6] = ctx->i32one; /* GLC */
5077 args[7] = ctx->i32one; /* SLC */
5078 args[8] = ctx->i32zero; /* TFE */
5079
5080 int idx = 0;
5081 int clip_cull_slot = -1;
5082 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5083 int length = 4;
5084 int start = 0;
5085 int slot = idx;
5086 int slot_inc = 1;
5087 if (!(ctx->output_mask & (1ull << i)))
5088 continue;
5089
5090 if (i == VARYING_SLOT_CLIP_DIST1 ||
5091 i == VARYING_SLOT_CULL_DIST1)
5092 continue;
5093
5094 if (i == VARYING_SLOT_CLIP_DIST0 ||
5095 i == VARYING_SLOT_CULL_DIST0) {
5096 /* unpack clip and cull from a single set of slots */
5097 if (clip_cull_slot == -1) {
5098 clip_cull_slot = idx;
5099 if (ctx->num_output_clips + ctx->num_output_culls > 4)
5100 slot_inc = 2;
5101 } else {
5102 slot = clip_cull_slot;
5103 slot_inc = 0;
5104 }
5105 if (i == VARYING_SLOT_CLIP_DIST0)
5106 length = ctx->num_output_clips;
5107 if (i == VARYING_SLOT_CULL_DIST0) {
5108 start = ctx->num_output_clips;
5109 length = ctx->num_output_culls;
5110 }
5111 }
5112
5113 for (unsigned j = 0; j < length; j++) {
5114 LLVMValueRef value;
5115 args[2] = LLVMConstInt(ctx->i32,
5116 (slot * 4 + j + start) *
5117 ctx->gs_max_out_vertices * 16 * 4, false);
5118
5119 value = ac_emit_llvm_intrinsic(&ctx->ac,
5120 "llvm.SI.buffer.load.dword.i32.i32",
5121 ctx->i32, args, 9,
5122 AC_FUNC_ATTR_READONLY);
5123
5124 LLVMBuildStore(ctx->builder,
5125 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
5126 }
5127 idx += slot_inc;
5128 }
5129 handle_vs_outputs_post(ctx);
5130 }
5131
5132 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5133 struct nir_shader *geom_shader,
5134 struct ac_shader_binary *binary,
5135 struct ac_shader_config *config,
5136 struct ac_shader_variant_info *shader_info,
5137 const struct ac_nir_compiler_options *options,
5138 bool dump_shader)
5139 {
5140 struct nir_to_llvm_context ctx = {0};
5141 ctx.context = LLVMContextCreate();
5142 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5143 ctx.options = options;
5144 ctx.shader_info = shader_info;
5145
5146 ac_llvm_context_init(&ctx.ac, ctx.context);
5147 ctx.ac.module = ctx.module;
5148
5149 ctx.is_gs_copy_shader = true;
5150 LLVMSetTarget(ctx.module, "amdgcn--");
5151 setup_types(&ctx);
5152
5153 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5154 ctx.ac.builder = ctx.builder;
5155 ctx.stage = MESA_SHADER_VERTEX;
5156
5157 create_function(&ctx);
5158
5159 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5160 ac_setup_rings(&ctx);
5161
5162 nir_foreach_variable(variable, &geom_shader->outputs)
5163 handle_shader_output_decl(&ctx, variable);
5164
5165 ac_gs_copy_shader_emit(&ctx);
5166
5167 LLVMBuildRetVoid(ctx.builder);
5168
5169 ac_llvm_finalize_module(&ctx);
5170
5171 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5172 MESA_SHADER_VERTEX,
5173 dump_shader, options->supports_spill);
5174 }