2 * Copyright © 2016 Bas Nieuwenhuizen
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
38 enum radeon_llvm_calling_convention
{
39 RADEON_LLVM_AMDGPU_VS
= 87,
40 RADEON_LLVM_AMDGPU_GS
= 88,
41 RADEON_LLVM_AMDGPU_PS
= 89,
42 RADEON_LLVM_AMDGPU_CS
= 90,
43 RADEON_LLVM_AMDGPU_HS
= 93,
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
52 struct nir_to_llvm_context
;
54 struct ac_nir_context
{
55 struct ac_llvm_context ac
;
56 struct ac_shader_abi
*abi
;
58 gl_shader_stage stage
;
60 struct hash_table
*defs
;
61 struct hash_table
*phis
;
62 struct hash_table
*vars
;
64 LLVMValueRef main_function
;
65 LLVMBasicBlockRef continue_block
;
66 LLVMBasicBlockRef break_block
;
68 LLVMValueRef outputs
[RADEON_LLVM_MAX_OUTPUTS
* 4];
73 struct nir_to_llvm_context
*nctx
; /* TODO get rid of this */
76 struct nir_to_llvm_context
{
77 struct ac_llvm_context ac
;
78 const struct ac_nir_compiler_options
*options
;
79 struct ac_shader_variant_info
*shader_info
;
80 struct ac_shader_abi abi
;
81 struct ac_nir_context
*nir
;
83 unsigned max_workgroup_size
;
84 LLVMContextRef context
;
86 LLVMBuilderRef builder
;
87 LLVMValueRef main_function
;
89 struct hash_table
*defs
;
90 struct hash_table
*phis
;
92 LLVMValueRef descriptor_sets
[AC_UD_MAX_SETS
];
93 LLVMValueRef ring_offsets
;
94 LLVMValueRef push_constants
;
95 LLVMValueRef view_index
;
96 LLVMValueRef num_work_groups
;
97 LLVMValueRef workgroup_ids
[3];
98 LLVMValueRef local_invocation_ids
;
101 LLVMValueRef vertex_buffers
;
102 LLVMValueRef rel_auto_id
;
103 LLVMValueRef vs_prim_id
;
104 LLVMValueRef ls_out_layout
;
105 LLVMValueRef es2gs_offset
;
107 LLVMValueRef tcs_offchip_layout
;
108 LLVMValueRef tcs_out_offsets
;
109 LLVMValueRef tcs_out_layout
;
110 LLVMValueRef tcs_in_layout
;
112 LLVMValueRef merged_wave_info
;
113 LLVMValueRef tess_factor_offset
;
114 LLVMValueRef tes_rel_patch_id
;
118 LLVMValueRef gsvs_ring_stride
;
119 LLVMValueRef gsvs_num_entries
;
120 LLVMValueRef gs2vs_offset
;
121 LLVMValueRef gs_wave_id
;
122 LLVMValueRef gs_vtx_offset
[6];
124 LLVMValueRef esgs_ring
;
125 LLVMValueRef gsvs_ring
;
126 LLVMValueRef hs_ring_tess_offchip
;
127 LLVMValueRef hs_ring_tess_factor
;
129 LLVMValueRef prim_mask
;
130 LLVMValueRef sample_pos_offset
;
131 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
132 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
134 gl_shader_stage stage
;
136 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
139 uint64_t output_mask
;
140 uint8_t num_output_clips
;
141 uint8_t num_output_culls
;
143 bool is_gs_copy_shader
;
144 LLVMValueRef gs_next_vertex
;
145 unsigned gs_max_out_vertices
;
147 unsigned tes_primitive_mode
;
148 uint64_t tess_outputs_written
;
149 uint64_t tess_patch_outputs_written
;
151 uint32_t tcs_patch_outputs_read
;
152 uint64_t tcs_outputs_read
;
155 static inline struct nir_to_llvm_context
*
156 nir_to_llvm_context_from_abi(struct ac_shader_abi
*abi
)
158 struct nir_to_llvm_context
*ctx
= NULL
;
159 return container_of(abi
, ctx
, abi
);
163 nir2llvmtype(struct ac_nir_context
*ctx
,
164 const struct glsl_type
*type
)
166 switch (glsl_get_base_type(glsl_without_array(type
))) {
170 case GLSL_TYPE_UINT64
:
171 case GLSL_TYPE_INT64
:
173 case GLSL_TYPE_DOUBLE
:
175 case GLSL_TYPE_FLOAT
:
178 assert(!"Unsupported type in nir2llvmtype()");
184 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
185 const nir_deref_var
*deref
,
186 enum ac_descriptor_type desc_type
,
187 const nir_tex_instr
*instr
,
188 bool image
, bool write
);
190 static unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
)
192 return (index
* 4) + chan
;
195 static unsigned shader_io_get_unique_index(gl_varying_slot slot
)
197 /* handle patch indices separate */
198 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
200 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
202 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
203 return 2 + (slot
- VARYING_SLOT_PATCH0
);
205 if (slot
== VARYING_SLOT_POS
)
207 if (slot
== VARYING_SLOT_PSIZ
)
209 if (slot
== VARYING_SLOT_CLIP_DIST0
)
211 /* 3 is reserved for clip dist as well */
212 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
213 return 4 + (slot
- VARYING_SLOT_VAR0
);
214 unreachable("illegal slot in get unique index\n");
217 static void set_llvm_calling_convention(LLVMValueRef func
,
218 gl_shader_stage stage
)
220 enum radeon_llvm_calling_convention calling_conv
;
223 case MESA_SHADER_VERTEX
:
224 case MESA_SHADER_TESS_EVAL
:
225 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
227 case MESA_SHADER_GEOMETRY
:
228 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
230 case MESA_SHADER_TESS_CTRL
:
231 calling_conv
= HAVE_LLVM
>= 0x0500 ? RADEON_LLVM_AMDGPU_HS
: RADEON_LLVM_AMDGPU_VS
;
233 case MESA_SHADER_FRAGMENT
:
234 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
236 case MESA_SHADER_COMPUTE
:
237 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
240 unreachable("Unhandle shader type");
243 LLVMSetFunctionCallConv(func
, calling_conv
);
248 LLVMTypeRef types
[MAX_ARGS
];
249 LLVMValueRef
*assign
[MAX_ARGS
];
250 unsigned array_params_mask
;
253 uint8_t num_sgprs_used
;
254 uint8_t num_vgprs_used
;
257 enum ac_arg_regfile
{
263 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
264 LLVMValueRef
*param_ptr
)
266 assert(info
->count
< MAX_ARGS
);
268 info
->assign
[info
->count
] = param_ptr
;
269 info
->types
[info
->count
] = type
;
272 if (regfile
== ARG_SGPR
) {
273 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
276 assert(regfile
== ARG_VGPR
);
277 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
282 add_array_arg(struct arg_info
*info
, LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
284 info
->array_params_mask
|= (1 << info
->count
);
285 add_arg(info
, ARG_SGPR
, type
, param_ptr
);
288 static void assign_arguments(LLVMValueRef main_function
,
289 struct arg_info
*info
)
292 for (i
= 0; i
< info
->count
; i
++) {
294 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
299 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
300 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
301 unsigned num_return_elems
,
302 struct arg_info
*args
,
303 unsigned max_workgroup_size
,
306 LLVMTypeRef main_function_type
, ret_type
;
307 LLVMBasicBlockRef main_function_body
;
309 if (num_return_elems
)
310 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
311 num_return_elems
, true);
313 ret_type
= LLVMVoidTypeInContext(ctx
);
315 /* Setup the function */
317 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
318 LLVMValueRef main_function
=
319 LLVMAddFunction(module
, "main", main_function_type
);
321 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
322 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
324 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
325 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
326 if (args
->array_params_mask
& (1 << i
)) {
327 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
328 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_BYVAL
);
329 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
332 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
336 if (max_workgroup_size
) {
337 ac_llvm_add_target_dep_function_attr(main_function
,
338 "amdgpu-max-work-group-size",
342 /* These were copied from some LLVM test. */
343 LLVMAddTargetDependentFunctionAttr(main_function
,
344 "less-precise-fpmad",
346 LLVMAddTargetDependentFunctionAttr(main_function
,
349 LLVMAddTargetDependentFunctionAttr(main_function
,
352 LLVMAddTargetDependentFunctionAttr(main_function
,
355 LLVMAddTargetDependentFunctionAttr(main_function
,
356 "no-signed-zeros-fp-math",
359 return main_function
;
362 static LLVMTypeRef
const_array(LLVMTypeRef elem_type
, int num_elements
)
364 return LLVMPointerType(LLVMArrayType(elem_type
, num_elements
),
368 static int get_elem_bits(struct ac_llvm_context
*ctx
, LLVMTypeRef type
)
370 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
371 type
= LLVMGetElementType(type
);
373 if (LLVMGetTypeKind(type
) == LLVMIntegerTypeKind
)
374 return LLVMGetIntTypeWidth(type
);
376 if (type
== ctx
->f16
)
378 if (type
== ctx
->f32
)
380 if (type
== ctx
->f64
)
383 unreachable("Unhandled type kind in get_elem_bits");
386 static LLVMValueRef
unpack_param(struct ac_llvm_context
*ctx
,
387 LLVMValueRef param
, unsigned rshift
,
390 LLVMValueRef value
= param
;
392 value
= LLVMBuildLShr(ctx
->builder
, value
,
393 LLVMConstInt(ctx
->i32
, rshift
, false), "");
395 if (rshift
+ bitwidth
< 32) {
396 unsigned mask
= (1 << bitwidth
) - 1;
397 value
= LLVMBuildAnd(ctx
->builder
, value
,
398 LLVMConstInt(ctx
->i32
, mask
, false), "");
403 static LLVMValueRef
get_rel_patch_id(struct nir_to_llvm_context
*ctx
)
405 switch (ctx
->stage
) {
406 case MESA_SHADER_TESS_CTRL
:
407 return unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
408 case MESA_SHADER_TESS_EVAL
:
409 return ctx
->tes_rel_patch_id
;
412 unreachable("Illegal stage");
416 /* Tessellation shaders pass outputs to the next shader using LDS.
418 * LS outputs = TCS inputs
419 * TCS outputs = TES inputs
422 * - TCS inputs for patch 0
423 * - TCS inputs for patch 1
424 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
426 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
427 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
428 * - TCS outputs for patch 1
429 * - Per-patch TCS outputs for patch 1
430 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
431 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
434 * All three shaders VS(LS), TCS, TES share the same LDS space.
437 get_tcs_in_patch_stride(struct nir_to_llvm_context
*ctx
)
439 if (ctx
->stage
== MESA_SHADER_VERTEX
)
440 return unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 0, 13);
441 else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
442 return unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 0, 13);
450 get_tcs_out_patch_stride(struct nir_to_llvm_context
*ctx
)
452 return unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 0, 13);
456 get_tcs_out_patch0_offset(struct nir_to_llvm_context
*ctx
)
458 return LLVMBuildMul(ctx
->builder
,
459 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 0, 16),
460 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
464 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context
*ctx
)
466 return LLVMBuildMul(ctx
->builder
,
467 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 16, 16),
468 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
472 get_tcs_in_current_patch_offset(struct nir_to_llvm_context
*ctx
)
474 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
475 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
477 return LLVMBuildMul(ctx
->builder
, patch_stride
, rel_patch_id
, "");
481 get_tcs_out_current_patch_offset(struct nir_to_llvm_context
*ctx
)
483 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
484 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
485 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
487 return LLVMBuildAdd(ctx
->builder
, patch0_offset
,
488 LLVMBuildMul(ctx
->builder
, patch_stride
,
494 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context
*ctx
)
496 LLVMValueRef patch0_patch_data_offset
=
497 get_tcs_out_patch0_patch_data_offset(ctx
);
498 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
499 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
501 return LLVMBuildAdd(ctx
->builder
, patch0_patch_data_offset
,
502 LLVMBuildMul(ctx
->builder
, patch_stride
,
508 set_loc(struct ac_userdata_info
*ud_info
, uint8_t *sgpr_idx
, uint8_t num_sgprs
,
509 uint32_t indirect_offset
)
511 ud_info
->sgpr_idx
= *sgpr_idx
;
512 ud_info
->num_sgprs
= num_sgprs
;
513 ud_info
->indirect
= indirect_offset
> 0;
514 ud_info
->indirect_offset
= indirect_offset
;
515 *sgpr_idx
+= num_sgprs
;
519 set_loc_shader(struct nir_to_llvm_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
522 struct ac_userdata_info
*ud_info
=
523 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
526 set_loc(ud_info
, sgpr_idx
, num_sgprs
, 0);
530 set_loc_desc(struct nir_to_llvm_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
531 uint32_t indirect_offset
)
533 struct ac_userdata_info
*ud_info
=
534 &ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[idx
];
537 set_loc(ud_info
, sgpr_idx
, 2, indirect_offset
);
540 struct user_sgpr_info
{
541 bool need_ring_offsets
;
543 bool indirect_all_descriptor_sets
;
546 static bool needs_view_index_sgpr(struct nir_to_llvm_context
*ctx
,
547 gl_shader_stage stage
)
550 case MESA_SHADER_VERTEX
:
551 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
552 (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
555 case MESA_SHADER_TESS_EVAL
:
556 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
558 case MESA_SHADER_GEOMETRY
:
559 case MESA_SHADER_TESS_CTRL
:
560 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
568 static void allocate_user_sgprs(struct nir_to_llvm_context
*ctx
,
569 gl_shader_stage stage
,
570 bool needs_view_index
,
571 struct user_sgpr_info
*user_sgpr_info
)
573 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
575 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
576 if (stage
== MESA_SHADER_GEOMETRY
||
577 stage
== MESA_SHADER_VERTEX
||
578 stage
== MESA_SHADER_TESS_CTRL
||
579 stage
== MESA_SHADER_TESS_EVAL
||
580 ctx
->is_gs_copy_shader
)
581 user_sgpr_info
->need_ring_offsets
= true;
583 if (stage
== MESA_SHADER_FRAGMENT
&&
584 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
585 user_sgpr_info
->need_ring_offsets
= true;
587 /* 2 user sgprs will nearly always be allocated for scratch/rings */
588 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
589 user_sgpr_info
->sgpr_count
+= 2;
592 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
594 case MESA_SHADER_COMPUTE
:
595 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
596 user_sgpr_info
->sgpr_count
+= 3;
598 case MESA_SHADER_FRAGMENT
:
599 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
601 case MESA_SHADER_VERTEX
:
602 if (!ctx
->is_gs_copy_shader
) {
603 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.vs
.has_vertex_buffers
? 2 : 0;
604 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
605 user_sgpr_info
->sgpr_count
+= 3;
607 user_sgpr_info
->sgpr_count
+= 2;
610 if (ctx
->options
->key
.vs
.as_ls
)
611 user_sgpr_info
->sgpr_count
++;
613 case MESA_SHADER_TESS_CTRL
:
614 user_sgpr_info
->sgpr_count
+= 4;
616 case MESA_SHADER_TESS_EVAL
:
617 user_sgpr_info
->sgpr_count
+= 1;
619 case MESA_SHADER_GEOMETRY
:
620 user_sgpr_info
->sgpr_count
+= 2;
626 if (needs_view_index
)
627 user_sgpr_info
->sgpr_count
++;
629 if (ctx
->shader_info
->info
.loads_push_constants
)
630 user_sgpr_info
->sgpr_count
+= 2;
632 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
? 32 : 16;
633 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_info
->sgpr_count
;
635 if (remaining_sgprs
/ 2 < util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
)) {
636 user_sgpr_info
->sgpr_count
+= 2;
637 user_sgpr_info
->indirect_all_descriptor_sets
= true;
639 user_sgpr_info
->sgpr_count
+= util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
) * 2;
644 declare_global_input_sgprs(struct nir_to_llvm_context
*ctx
,
645 gl_shader_stage stage
,
646 bool has_previous_stage
,
647 gl_shader_stage previous_stage
,
648 const struct user_sgpr_info
*user_sgpr_info
,
649 struct arg_info
*args
,
650 LLVMValueRef
*desc_sets
)
652 LLVMTypeRef type
= const_array(ctx
->ac
.i8
, 1024 * 1024);
653 unsigned num_sets
= ctx
->options
->layout
?
654 ctx
->options
->layout
->num_sets
: 0;
655 unsigned stage_mask
= 1 << stage
;
657 if (has_previous_stage
)
658 stage_mask
|= 1 << previous_stage
;
660 /* 1 for each descriptor set */
661 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
662 for (unsigned i
= 0; i
< num_sets
; ++i
) {
663 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
664 add_array_arg(args
, type
,
665 &ctx
->descriptor_sets
[i
]);
669 add_array_arg(args
, const_array(type
, 32), desc_sets
);
672 if (ctx
->shader_info
->info
.loads_push_constants
) {
673 /* 1 for push constants and dynamic descriptors */
674 add_array_arg(args
, type
, &ctx
->push_constants
);
679 declare_vs_specific_input_sgprs(struct nir_to_llvm_context
*ctx
,
680 gl_shader_stage stage
,
681 bool has_previous_stage
,
682 gl_shader_stage previous_stage
,
683 struct arg_info
*args
)
685 if (!ctx
->is_gs_copy_shader
&&
686 (stage
== MESA_SHADER_VERTEX
||
687 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
688 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
689 add_arg(args
, ARG_SGPR
, const_array(ctx
->ac
.v4i32
, 16),
690 &ctx
->vertex_buffers
);
692 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
693 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
694 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
695 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
701 declare_vs_input_vgprs(struct nir_to_llvm_context
*ctx
, struct arg_info
*args
)
703 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
704 if (!ctx
->is_gs_copy_shader
) {
705 if (ctx
->options
->key
.vs
.as_ls
) {
706 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
707 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
709 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
710 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
712 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
717 declare_tes_input_vgprs(struct nir_to_llvm_context
*ctx
, struct arg_info
*args
)
719 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
720 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
721 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
722 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
726 set_global_input_locs(struct nir_to_llvm_context
*ctx
, gl_shader_stage stage
,
727 bool has_previous_stage
, gl_shader_stage previous_stage
,
728 const struct user_sgpr_info
*user_sgpr_info
,
729 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
731 unsigned num_sets
= ctx
->options
->layout
?
732 ctx
->options
->layout
->num_sets
: 0;
733 unsigned stage_mask
= 1 << stage
;
735 if (has_previous_stage
)
736 stage_mask
|= 1 << previous_stage
;
738 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
739 for (unsigned i
= 0; i
< num_sets
; ++i
) {
740 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
741 set_loc_desc(ctx
, i
, user_sgpr_idx
, 0);
743 ctx
->descriptor_sets
[i
] = NULL
;
746 set_loc_shader(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
749 for (unsigned i
= 0; i
< num_sets
; ++i
) {
750 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
751 set_loc_desc(ctx
, i
, user_sgpr_idx
, i
* 8);
752 ctx
->descriptor_sets
[i
] =
753 ac_build_load_to_sgpr(&ctx
->ac
,
755 LLVMConstInt(ctx
->ac
.i32
, i
, false));
758 ctx
->descriptor_sets
[i
] = NULL
;
760 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
763 if (ctx
->shader_info
->info
.loads_push_constants
) {
764 set_loc_shader(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
, 2);
769 set_vs_specific_input_locs(struct nir_to_llvm_context
*ctx
,
770 gl_shader_stage stage
, bool has_previous_stage
,
771 gl_shader_stage previous_stage
,
772 uint8_t *user_sgpr_idx
)
774 if (!ctx
->is_gs_copy_shader
&&
775 (stage
== MESA_SHADER_VERTEX
||
776 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
777 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
778 set_loc_shader(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
783 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
786 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
787 user_sgpr_idx
, vs_num
);
791 static void create_function(struct nir_to_llvm_context
*ctx
,
792 gl_shader_stage stage
,
793 bool has_previous_stage
,
794 gl_shader_stage previous_stage
)
796 uint8_t user_sgpr_idx
;
797 struct user_sgpr_info user_sgpr_info
;
798 struct arg_info args
= {};
799 LLVMValueRef desc_sets
;
800 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
801 allocate_user_sgprs(ctx
, stage
, needs_view_index
, &user_sgpr_info
);
803 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
804 add_arg(&args
, ARG_SGPR
, const_array(ctx
->ac
.v4i32
, 16),
809 case MESA_SHADER_COMPUTE
:
810 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
811 previous_stage
, &user_sgpr_info
,
814 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
815 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
816 &ctx
->num_work_groups
);
819 for (int i
= 0; i
< 3; i
++) {
820 ctx
->workgroup_ids
[i
] = NULL
;
821 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
822 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
823 &ctx
->workgroup_ids
[i
]);
827 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
828 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->tg_size
);
829 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
830 &ctx
->local_invocation_ids
);
832 case MESA_SHADER_VERTEX
:
833 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
834 previous_stage
, &user_sgpr_info
,
836 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
837 previous_stage
, &args
);
839 if (needs_view_index
)
840 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->view_index
);
841 if (ctx
->options
->key
.vs
.as_es
)
842 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
844 else if (ctx
->options
->key
.vs
.as_ls
)
845 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
846 &ctx
->ls_out_layout
);
848 declare_vs_input_vgprs(ctx
, &args
);
850 case MESA_SHADER_TESS_CTRL
:
851 if (has_previous_stage
) {
852 // First 6 system regs
853 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
854 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
855 &ctx
->merged_wave_info
);
856 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
857 &ctx
->tess_factor_offset
);
859 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
860 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
861 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
863 declare_global_input_sgprs(ctx
, stage
,
866 &user_sgpr_info
, &args
,
868 declare_vs_specific_input_sgprs(ctx
, stage
,
870 previous_stage
, &args
);
872 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
873 &ctx
->ls_out_layout
);
875 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
876 &ctx
->tcs_offchip_layout
);
877 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
878 &ctx
->tcs_out_offsets
);
879 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
880 &ctx
->tcs_out_layout
);
881 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
882 &ctx
->tcs_in_layout
);
883 if (needs_view_index
)
884 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
887 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
888 &ctx
->abi
.tcs_patch_id
);
889 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
890 &ctx
->abi
.tcs_rel_ids
);
892 declare_vs_input_vgprs(ctx
, &args
);
894 declare_global_input_sgprs(ctx
, stage
,
897 &user_sgpr_info
, &args
,
900 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
901 &ctx
->tcs_offchip_layout
);
902 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
903 &ctx
->tcs_out_offsets
);
904 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
905 &ctx
->tcs_out_layout
);
906 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
907 &ctx
->tcs_in_layout
);
908 if (needs_view_index
)
909 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
912 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
913 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
914 &ctx
->tess_factor_offset
);
915 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
916 &ctx
->abi
.tcs_patch_id
);
917 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
918 &ctx
->abi
.tcs_rel_ids
);
921 case MESA_SHADER_TESS_EVAL
:
922 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
923 previous_stage
, &user_sgpr_info
,
926 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->tcs_offchip_layout
);
927 if (needs_view_index
)
928 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->view_index
);
930 if (ctx
->options
->key
.tes
.as_es
) {
931 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
932 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
933 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
936 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
937 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
939 declare_tes_input_vgprs(ctx
, &args
);
941 case MESA_SHADER_GEOMETRY
:
942 if (has_previous_stage
) {
943 // First 6 system regs
944 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
946 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
947 &ctx
->merged_wave_info
);
948 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
950 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
951 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
952 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
954 declare_global_input_sgprs(ctx
, stage
,
957 &user_sgpr_info
, &args
,
960 if (previous_stage
== MESA_SHADER_TESS_EVAL
) {
961 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
962 &ctx
->tcs_offchip_layout
);
964 declare_vs_specific_input_sgprs(ctx
, stage
,
970 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
971 &ctx
->gsvs_ring_stride
);
972 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
973 &ctx
->gsvs_num_entries
);
974 if (needs_view_index
)
975 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
978 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
979 &ctx
->gs_vtx_offset
[0]);
980 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
981 &ctx
->gs_vtx_offset
[2]);
982 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
983 &ctx
->abi
.gs_prim_id
);
984 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
985 &ctx
->abi
.gs_invocation_id
);
986 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
987 &ctx
->gs_vtx_offset
[4]);
989 if (previous_stage
== MESA_SHADER_VERTEX
) {
990 declare_vs_input_vgprs(ctx
, &args
);
992 declare_tes_input_vgprs(ctx
, &args
);
995 declare_global_input_sgprs(ctx
, stage
,
998 &user_sgpr_info
, &args
,
1001 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1002 &ctx
->gsvs_ring_stride
);
1003 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1004 &ctx
->gsvs_num_entries
);
1005 if (needs_view_index
)
1006 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1009 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
1010 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
1011 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1012 &ctx
->gs_vtx_offset
[0]);
1013 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1014 &ctx
->gs_vtx_offset
[1]);
1015 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1016 &ctx
->abi
.gs_prim_id
);
1017 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1018 &ctx
->gs_vtx_offset
[2]);
1019 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1020 &ctx
->gs_vtx_offset
[3]);
1021 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1022 &ctx
->gs_vtx_offset
[4]);
1023 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1024 &ctx
->gs_vtx_offset
[5]);
1025 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1026 &ctx
->abi
.gs_invocation_id
);
1029 case MESA_SHADER_FRAGMENT
:
1030 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
1031 previous_stage
, &user_sgpr_info
,
1034 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
)
1035 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1036 &ctx
->sample_pos_offset
);
1038 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->prim_mask
);
1039 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
1040 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
1041 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
1042 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1043 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
1044 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
1045 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
1046 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1047 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1048 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1049 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1050 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1051 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1052 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1053 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1054 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1057 unreachable("Shader stage not implemented");
1060 ctx
->main_function
= create_llvm_function(
1061 ctx
->context
, ctx
->module
, ctx
->builder
, NULL
, 0, &args
,
1062 ctx
->max_workgroup_size
,
1063 ctx
->options
->unsafe_math
);
1064 set_llvm_calling_convention(ctx
->main_function
, stage
);
1067 ctx
->shader_info
->num_input_vgprs
= 0;
1068 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1070 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1072 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1073 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1075 assign_arguments(ctx
->main_function
, &args
);
1079 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1080 set_loc_shader(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1082 if (ctx
->options
->supports_spill
) {
1083 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1084 LLVMPointerType(ctx
->ac
.i8
, CONST_ADDR_SPACE
),
1085 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1086 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->builder
, ctx
->ring_offsets
,
1087 const_array(ctx
->ac
.v4i32
, 16), "");
1091 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1092 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1093 if (has_previous_stage
)
1096 set_global_input_locs(ctx
, stage
, has_previous_stage
, previous_stage
,
1097 &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1100 case MESA_SHADER_COMPUTE
:
1101 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1102 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1106 case MESA_SHADER_VERTEX
:
1107 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1108 previous_stage
, &user_sgpr_idx
);
1109 if (ctx
->view_index
)
1110 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1111 if (ctx
->options
->key
.vs
.as_ls
) {
1112 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1115 if (ctx
->options
->key
.vs
.as_ls
)
1116 ac_declare_lds_as_pointer(&ctx
->ac
);
1118 case MESA_SHADER_TESS_CTRL
:
1119 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1120 previous_stage
, &user_sgpr_idx
);
1121 if (has_previous_stage
)
1122 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1124 set_loc_shader(ctx
, AC_UD_TCS_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 4);
1125 if (ctx
->view_index
)
1126 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1127 ac_declare_lds_as_pointer(&ctx
->ac
);
1129 case MESA_SHADER_TESS_EVAL
:
1130 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 1);
1131 if (ctx
->view_index
)
1132 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1134 case MESA_SHADER_GEOMETRY
:
1135 if (has_previous_stage
) {
1136 if (previous_stage
== MESA_SHADER_VERTEX
)
1137 set_vs_specific_input_locs(ctx
, stage
,
1142 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
,
1145 set_loc_shader(ctx
, AC_UD_GS_VS_RING_STRIDE_ENTRIES
,
1147 if (ctx
->view_index
)
1148 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1149 if (has_previous_stage
)
1150 ac_declare_lds_as_pointer(&ctx
->ac
);
1152 case MESA_SHADER_FRAGMENT
:
1153 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
) {
1154 set_loc_shader(ctx
, AC_UD_PS_SAMPLE_POS_OFFSET
,
1159 unreachable("Shader stage not implemented");
1162 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1165 static LLVMValueRef
trim_vector(struct ac_llvm_context
*ctx
,
1166 LLVMValueRef value
, unsigned count
)
1168 unsigned num_components
= ac_get_llvm_num_components(value
);
1169 if (count
== num_components
)
1172 LLVMValueRef masks
[] = {
1173 LLVMConstInt(ctx
->i32
, 0, false), LLVMConstInt(ctx
->i32
, 1, false),
1174 LLVMConstInt(ctx
->i32
, 2, false), LLVMConstInt(ctx
->i32
, 3, false)};
1177 return LLVMBuildExtractElement(ctx
->builder
, value
, masks
[0],
1180 LLVMValueRef swizzle
= LLVMConstVector(masks
, count
);
1181 return LLVMBuildShuffleVector(ctx
->builder
, value
, value
, swizzle
, "");
1185 build_store_values_extended(struct ac_llvm_context
*ac
,
1186 LLVMValueRef
*values
,
1187 unsigned value_count
,
1188 unsigned value_stride
,
1191 LLVMBuilderRef builder
= ac
->builder
;
1194 for (i
= 0; i
< value_count
; i
++) {
1195 LLVMValueRef ptr
= values
[i
* value_stride
];
1196 LLVMValueRef index
= LLVMConstInt(ac
->i32
, i
, false);
1197 LLVMValueRef value
= LLVMBuildExtractElement(builder
, vec
, index
, "");
1198 LLVMBuildStore(builder
, value
, ptr
);
1202 static LLVMTypeRef
get_def_type(struct ac_nir_context
*ctx
,
1203 const nir_ssa_def
*def
)
1205 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, def
->bit_size
);
1206 if (def
->num_components
> 1) {
1207 type
= LLVMVectorType(type
, def
->num_components
);
1212 static LLVMValueRef
get_src(struct ac_nir_context
*nir
, nir_src src
)
1215 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, src
.ssa
);
1216 return (LLVMValueRef
)entry
->data
;
1220 static LLVMBasicBlockRef
get_block(struct ac_nir_context
*nir
,
1221 const struct nir_block
*b
)
1223 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, b
);
1224 return (LLVMBasicBlockRef
)entry
->data
;
1227 static LLVMValueRef
get_alu_src(struct ac_nir_context
*ctx
,
1229 unsigned num_components
)
1231 LLVMValueRef value
= get_src(ctx
, src
.src
);
1232 bool need_swizzle
= false;
1235 LLVMTypeRef type
= LLVMTypeOf(value
);
1236 unsigned src_components
= LLVMGetTypeKind(type
) == LLVMVectorTypeKind
1237 ? LLVMGetVectorSize(type
)
1240 for (unsigned i
= 0; i
< num_components
; ++i
) {
1241 assert(src
.swizzle
[i
] < src_components
);
1242 if (src
.swizzle
[i
] != i
)
1243 need_swizzle
= true;
1246 if (need_swizzle
|| num_components
!= src_components
) {
1247 LLVMValueRef masks
[] = {
1248 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[0], false),
1249 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[1], false),
1250 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[2], false),
1251 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[3], false)};
1253 if (src_components
> 1 && num_components
== 1) {
1254 value
= LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
1256 } else if (src_components
== 1 && num_components
> 1) {
1257 LLVMValueRef values
[] = {value
, value
, value
, value
};
1258 value
= ac_build_gather_values(&ctx
->ac
, values
, num_components
);
1260 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
1261 value
= LLVMBuildShuffleVector(ctx
->ac
.builder
, value
, value
,
1265 assert(!src
.negate
);
1270 static LLVMValueRef
emit_int_cmp(struct ac_llvm_context
*ctx
,
1271 LLVMIntPredicate pred
, LLVMValueRef src0
,
1274 LLVMValueRef result
= LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, "");
1275 return LLVMBuildSelect(ctx
->builder
, result
,
1276 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1280 static LLVMValueRef
emit_float_cmp(struct ac_llvm_context
*ctx
,
1281 LLVMRealPredicate pred
, LLVMValueRef src0
,
1284 LLVMValueRef result
;
1285 src0
= ac_to_float(ctx
, src0
);
1286 src1
= ac_to_float(ctx
, src1
);
1287 result
= LLVMBuildFCmp(ctx
->builder
, pred
, src0
, src1
, "");
1288 return LLVMBuildSelect(ctx
->builder
, result
,
1289 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1293 static LLVMValueRef
emit_intrin_1f_param(struct ac_llvm_context
*ctx
,
1295 LLVMTypeRef result_type
,
1299 LLVMValueRef params
[] = {
1300 ac_to_float(ctx
, src0
),
1303 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1304 get_elem_bits(ctx
, result_type
));
1305 assert(length
< sizeof(name
));
1306 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 1, AC_FUNC_ATTR_READNONE
);
1309 static LLVMValueRef
emit_intrin_2f_param(struct ac_llvm_context
*ctx
,
1311 LLVMTypeRef result_type
,
1312 LLVMValueRef src0
, LLVMValueRef src1
)
1315 LLVMValueRef params
[] = {
1316 ac_to_float(ctx
, src0
),
1317 ac_to_float(ctx
, src1
),
1320 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1321 get_elem_bits(ctx
, result_type
));
1322 assert(length
< sizeof(name
));
1323 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 2, AC_FUNC_ATTR_READNONE
);
1326 static LLVMValueRef
emit_intrin_3f_param(struct ac_llvm_context
*ctx
,
1328 LLVMTypeRef result_type
,
1329 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1332 LLVMValueRef params
[] = {
1333 ac_to_float(ctx
, src0
),
1334 ac_to_float(ctx
, src1
),
1335 ac_to_float(ctx
, src2
),
1338 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1339 get_elem_bits(ctx
, result_type
));
1340 assert(length
< sizeof(name
));
1341 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 3, AC_FUNC_ATTR_READNONE
);
1344 static LLVMValueRef
emit_bcsel(struct ac_llvm_context
*ctx
,
1345 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1347 LLVMValueRef v
= LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
,
1349 return LLVMBuildSelect(ctx
->builder
, v
, src1
, src2
, "");
1352 static LLVMValueRef
emit_minmax_int(struct ac_llvm_context
*ctx
,
1353 LLVMIntPredicate pred
,
1354 LLVMValueRef src0
, LLVMValueRef src1
)
1356 return LLVMBuildSelect(ctx
->builder
,
1357 LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, ""),
1362 static LLVMValueRef
emit_iabs(struct ac_llvm_context
*ctx
,
1365 return emit_minmax_int(ctx
, LLVMIntSGT
, src0
,
1366 LLVMBuildNeg(ctx
->builder
, src0
, ""));
1369 static LLVMValueRef
emit_fsign(struct ac_llvm_context
*ctx
,
1373 LLVMValueRef cmp
, val
, zero
, one
;
1376 if (bitsize
== 32) {
1386 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGT
, src0
, zero
, "");
1387 val
= LLVMBuildSelect(ctx
->builder
, cmp
, one
, src0
, "");
1388 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
, val
, zero
, "");
1389 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstReal(type
, -1.0), "");
1393 static LLVMValueRef
emit_isign(struct ac_llvm_context
*ctx
,
1394 LLVMValueRef src0
, unsigned bitsize
)
1396 LLVMValueRef cmp
, val
, zero
, one
;
1399 if (bitsize
== 32) {
1409 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGT
, src0
, zero
, "");
1410 val
= LLVMBuildSelect(ctx
->builder
, cmp
, one
, src0
, "");
1411 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGE
, val
, zero
, "");
1412 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstInt(type
, -1, true), "");
1416 static LLVMValueRef
emit_ffract(struct ac_llvm_context
*ctx
,
1419 const char *intr
= "llvm.floor.f32";
1420 LLVMValueRef fsrc0
= ac_to_float(ctx
, src0
);
1421 LLVMValueRef params
[] = {
1424 LLVMValueRef floor
= ac_build_intrinsic(ctx
, intr
,
1425 ctx
->f32
, params
, 1,
1426 AC_FUNC_ATTR_READNONE
);
1427 return LLVMBuildFSub(ctx
->builder
, fsrc0
, floor
, "");
1430 static LLVMValueRef
emit_uint_carry(struct ac_llvm_context
*ctx
,
1432 LLVMValueRef src0
, LLVMValueRef src1
)
1434 LLVMTypeRef ret_type
;
1435 LLVMTypeRef types
[] = { ctx
->i32
, ctx
->i1
};
1437 LLVMValueRef params
[] = { src0
, src1
};
1438 ret_type
= LLVMStructTypeInContext(ctx
->context
, types
,
1441 res
= ac_build_intrinsic(ctx
, intrin
, ret_type
,
1442 params
, 2, AC_FUNC_ATTR_READNONE
);
1444 res
= LLVMBuildExtractValue(ctx
->builder
, res
, 1, "");
1445 res
= LLVMBuildZExt(ctx
->builder
, res
, ctx
->i32
, "");
1449 static LLVMValueRef
emit_b2f(struct ac_llvm_context
*ctx
,
1452 return LLVMBuildAnd(ctx
->builder
, src0
, LLVMBuildBitCast(ctx
->builder
, LLVMConstReal(ctx
->f32
, 1.0), ctx
->i32
, ""), "");
1455 static LLVMValueRef
emit_f2b(struct ac_llvm_context
*ctx
,
1458 src0
= ac_to_float(ctx
, src0
);
1459 return LLVMBuildSExt(ctx
->builder
,
1460 LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
, src0
, ctx
->f32_0
, ""),
1464 static LLVMValueRef
emit_b2i(struct ac_llvm_context
*ctx
,
1468 LLVMValueRef result
= LLVMBuildAnd(ctx
->builder
, src0
, ctx
->i32_1
, "");
1473 return LLVMBuildZExt(ctx
->builder
, result
, ctx
->i64
, "");
1476 static LLVMValueRef
emit_i2b(struct ac_llvm_context
*ctx
,
1479 return LLVMBuildSExt(ctx
->builder
,
1480 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
, ctx
->i32_0
, ""),
1484 static LLVMValueRef
emit_f2f16(struct nir_to_llvm_context
*ctx
,
1487 LLVMValueRef result
;
1488 LLVMValueRef cond
= NULL
;
1490 src0
= ac_to_float(&ctx
->ac
, src0
);
1491 result
= LLVMBuildFPTrunc(ctx
->builder
, src0
, ctx
->ac
.f16
, "");
1493 if (ctx
->options
->chip_class
>= VI
) {
1494 LLVMValueRef args
[2];
1495 /* Check if the result is a denormal - and flush to 0 if so. */
1497 args
[1] = LLVMConstInt(ctx
->ac
.i32
, N_SUBNORMAL
| P_SUBNORMAL
, false);
1498 cond
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.class.f16", ctx
->ac
.i1
, args
, 2, AC_FUNC_ATTR_READNONE
);
1501 /* need to convert back up to f32 */
1502 result
= LLVMBuildFPExt(ctx
->builder
, result
, ctx
->ac
.f32
, "");
1504 if (ctx
->options
->chip_class
>= VI
)
1505 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->ac
.f32_0
, result
, "");
1508 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1509 * so compare the result and flush to 0 if it's smaller.
1511 LLVMValueRef temp
, cond2
;
1512 temp
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1513 ctx
->ac
.f32
, result
);
1514 cond
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUGT
,
1515 LLVMBuildBitCast(ctx
->builder
, LLVMConstInt(ctx
->ac
.i32
, 0x38800000, false), ctx
->ac
.f32
, ""),
1517 cond2
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
,
1518 temp
, ctx
->ac
.f32_0
, "");
1519 cond
= LLVMBuildAnd(ctx
->builder
, cond
, cond2
, "");
1520 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->ac
.f32_0
, result
, "");
1525 static LLVMValueRef
emit_umul_high(struct ac_llvm_context
*ctx
,
1526 LLVMValueRef src0
, LLVMValueRef src1
)
1528 LLVMValueRef dst64
, result
;
1529 src0
= LLVMBuildZExt(ctx
->builder
, src0
, ctx
->i64
, "");
1530 src1
= LLVMBuildZExt(ctx
->builder
, src1
, ctx
->i64
, "");
1532 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1533 dst64
= LLVMBuildLShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1534 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1538 static LLVMValueRef
emit_imul_high(struct ac_llvm_context
*ctx
,
1539 LLVMValueRef src0
, LLVMValueRef src1
)
1541 LLVMValueRef dst64
, result
;
1542 src0
= LLVMBuildSExt(ctx
->builder
, src0
, ctx
->i64
, "");
1543 src1
= LLVMBuildSExt(ctx
->builder
, src1
, ctx
->i64
, "");
1545 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1546 dst64
= LLVMBuildAShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1547 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1551 static LLVMValueRef
emit_bitfield_extract(struct ac_llvm_context
*ctx
,
1553 const LLVMValueRef srcs
[3])
1555 LLVMValueRef result
;
1556 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, srcs
[2], LLVMConstInt(ctx
->i32
, 32, false), "");
1558 result
= ac_build_bfe(ctx
, srcs
[0], srcs
[1], srcs
[2], is_signed
);
1559 result
= LLVMBuildSelect(ctx
->builder
, icond
, srcs
[0], result
, "");
1563 static LLVMValueRef
emit_bitfield_insert(struct ac_llvm_context
*ctx
,
1564 LLVMValueRef src0
, LLVMValueRef src1
,
1565 LLVMValueRef src2
, LLVMValueRef src3
)
1567 LLVMValueRef bfi_args
[3], result
;
1569 bfi_args
[0] = LLVMBuildShl(ctx
->builder
,
1570 LLVMBuildSub(ctx
->builder
,
1571 LLVMBuildShl(ctx
->builder
,
1576 bfi_args
[1] = LLVMBuildShl(ctx
->builder
, src1
, src2
, "");
1579 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, src3
, LLVMConstInt(ctx
->i32
, 32, false), "");
1582 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1583 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1585 result
= LLVMBuildXor(ctx
->builder
, bfi_args
[2],
1586 LLVMBuildAnd(ctx
->builder
, bfi_args
[0],
1587 LLVMBuildXor(ctx
->builder
, bfi_args
[1], bfi_args
[2], ""), ""), "");
1589 result
= LLVMBuildSelect(ctx
->builder
, icond
, src1
, result
, "");
1593 static LLVMValueRef
emit_pack_half_2x16(struct ac_llvm_context
*ctx
,
1596 LLVMValueRef comp
[2];
1598 src0
= ac_to_float(ctx
, src0
);
1599 comp
[0] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_0
, "");
1600 comp
[1] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_1
, "");
1602 return ac_build_cvt_pkrtz_f16(ctx
, comp
);
1605 static LLVMValueRef
emit_unpack_half_2x16(struct ac_llvm_context
*ctx
,
1608 LLVMValueRef const16
= LLVMConstInt(ctx
->i32
, 16, false);
1609 LLVMValueRef temps
[2], result
, val
;
1612 for (i
= 0; i
< 2; i
++) {
1613 val
= i
== 1 ? LLVMBuildLShr(ctx
->builder
, src0
, const16
, "") : src0
;
1614 val
= LLVMBuildTrunc(ctx
->builder
, val
, ctx
->i16
, "");
1615 val
= LLVMBuildBitCast(ctx
->builder
, val
, ctx
->f16
, "");
1616 temps
[i
] = LLVMBuildFPExt(ctx
->builder
, val
, ctx
->f32
, "");
1619 result
= LLVMBuildInsertElement(ctx
->builder
, LLVMGetUndef(ctx
->v2f32
), temps
[0],
1621 result
= LLVMBuildInsertElement(ctx
->builder
, result
, temps
[1],
1626 static LLVMValueRef
emit_ddxy(struct ac_nir_context
*ctx
,
1632 LLVMValueRef result
;
1634 if (op
== nir_op_fddx_fine
|| op
== nir_op_fddx
)
1635 mask
= AC_TID_MASK_LEFT
;
1636 else if (op
== nir_op_fddy_fine
|| op
== nir_op_fddy
)
1637 mask
= AC_TID_MASK_TOP
;
1639 mask
= AC_TID_MASK_TOP_LEFT
;
1641 /* for DDX we want to next X pixel, DDY next Y pixel. */
1642 if (op
== nir_op_fddx_fine
||
1643 op
== nir_op_fddx_coarse
||
1649 result
= ac_build_ddxy(&ctx
->ac
, mask
, idx
, src0
);
1654 * this takes an I,J coordinate pair,
1655 * and works out the X and Y derivatives.
1656 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1658 static LLVMValueRef
emit_ddxy_interp(
1659 struct ac_nir_context
*ctx
,
1660 LLVMValueRef interp_ij
)
1662 LLVMValueRef result
[4], a
;
1665 for (i
= 0; i
< 2; i
++) {
1666 a
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_ij
,
1667 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
1668 result
[i
] = emit_ddxy(ctx
, nir_op_fddx
, a
);
1669 result
[2+i
] = emit_ddxy(ctx
, nir_op_fddy
, a
);
1671 return ac_build_gather_values(&ctx
->ac
, result
, 4);
1674 static void visit_alu(struct ac_nir_context
*ctx
, const nir_alu_instr
*instr
)
1676 LLVMValueRef src
[4], result
= NULL
;
1677 unsigned num_components
= instr
->dest
.dest
.ssa
.num_components
;
1678 unsigned src_components
;
1679 LLVMTypeRef def_type
= get_def_type(ctx
, &instr
->dest
.dest
.ssa
);
1681 assert(nir_op_infos
[instr
->op
].num_inputs
<= ARRAY_SIZE(src
));
1682 switch (instr
->op
) {
1688 case nir_op_pack_half_2x16
:
1691 case nir_op_unpack_half_2x16
:
1695 src_components
= num_components
;
1698 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1699 src
[i
] = get_alu_src(ctx
, instr
->src
[i
], src_components
);
1701 switch (instr
->op
) {
1707 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1708 result
= LLVMBuildFNeg(ctx
->ac
.builder
, src
[0], "");
1711 result
= LLVMBuildNeg(ctx
->ac
.builder
, src
[0], "");
1714 result
= LLVMBuildNot(ctx
->ac
.builder
, src
[0], "");
1717 result
= LLVMBuildAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1720 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1721 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1722 result
= LLVMBuildFAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1725 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1726 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1727 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1730 result
= LLVMBuildSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1733 result
= LLVMBuildMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1736 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1739 result
= LLVMBuildURem(ctx
->ac
.builder
, src
[0], src
[1], "");
1742 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1743 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1744 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1745 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1746 ac_to_float_type(&ctx
->ac
, def_type
), result
);
1747 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[1] , result
, "");
1748 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], result
, "");
1751 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1752 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1753 result
= LLVMBuildFRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1756 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1759 result
= LLVMBuildSDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1762 result
= LLVMBuildUDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1765 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1766 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1767 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1770 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1771 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1772 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1775 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1776 result
= ac_build_fdiv(&ctx
->ac
, instr
->dest
.dest
.ssa
.bit_size
== 32 ? ctx
->ac
.f32_1
: ctx
->ac
.f64_1
,
1780 result
= LLVMBuildAnd(ctx
->ac
.builder
, src
[0], src
[1], "");
1783 result
= LLVMBuildOr(ctx
->ac
.builder
, src
[0], src
[1], "");
1786 result
= LLVMBuildXor(ctx
->ac
.builder
, src
[0], src
[1], "");
1789 result
= LLVMBuildShl(ctx
->ac
.builder
, src
[0],
1790 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1791 LLVMTypeOf(src
[0]), ""),
1795 result
= LLVMBuildAShr(ctx
->ac
.builder
, src
[0],
1796 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1797 LLVMTypeOf(src
[0]), ""),
1801 result
= LLVMBuildLShr(ctx
->ac
.builder
, src
[0],
1802 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1803 LLVMTypeOf(src
[0]), ""),
1807 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1810 result
= emit_int_cmp(&ctx
->ac
, LLVMIntNE
, src
[0], src
[1]);
1813 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, src
[0], src
[1]);
1816 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSGE
, src
[0], src
[1]);
1819 result
= emit_int_cmp(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1822 result
= emit_int_cmp(&ctx
->ac
, LLVMIntUGE
, src
[0], src
[1]);
1825 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUEQ
, src
[0], src
[1]);
1828 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUNE
, src
[0], src
[1]);
1831 result
= emit_float_cmp(&ctx
->ac
, LLVMRealULT
, src
[0], src
[1]);
1834 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUGE
, src
[0], src
[1]);
1837 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1838 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1841 result
= emit_iabs(&ctx
->ac
, src
[0]);
1844 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, src
[0], src
[1]);
1847 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1850 result
= emit_minmax_int(&ctx
->ac
, LLVMIntUGT
, src
[0], src
[1]);
1853 result
= emit_minmax_int(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1856 result
= emit_isign(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
1859 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1860 result
= emit_fsign(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
1863 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1864 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1867 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.trunc",
1868 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1871 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.ceil",
1872 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1874 case nir_op_fround_even
:
1875 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.rint",
1876 ac_to_float_type(&ctx
->ac
, def_type
),src
[0]);
1879 result
= emit_ffract(&ctx
->ac
, src
[0]);
1882 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sin",
1883 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1886 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.cos",
1887 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1890 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1891 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1894 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.exp2",
1895 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1898 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.log2",
1899 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1902 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1903 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1904 result
= ac_build_fdiv(&ctx
->ac
, instr
->dest
.dest
.ssa
.bit_size
== 32 ? ctx
->ac
.f32_1
: ctx
->ac
.f64_1
,
1908 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.pow",
1909 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1912 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.maxnum",
1913 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1914 if (instr
->dest
.dest
.ssa
.bit_size
== 32)
1915 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1916 ac_to_float_type(&ctx
->ac
, def_type
),
1920 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.minnum",
1921 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1922 if (instr
->dest
.dest
.ssa
.bit_size
== 32)
1923 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1924 ac_to_float_type(&ctx
->ac
, def_type
),
1928 result
= emit_intrin_3f_param(&ctx
->ac
, "llvm.fmuladd",
1929 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1], src
[2]);
1931 case nir_op_ibitfield_extract
:
1932 result
= emit_bitfield_extract(&ctx
->ac
, true, src
);
1934 case nir_op_ubitfield_extract
:
1935 result
= emit_bitfield_extract(&ctx
->ac
, false, src
);
1937 case nir_op_bitfield_insert
:
1938 result
= emit_bitfield_insert(&ctx
->ac
, src
[0], src
[1], src
[2], src
[3]);
1940 case nir_op_bitfield_reverse
:
1941 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.bitreverse.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1943 case nir_op_bit_count
:
1944 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1949 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1950 src
[i
] = ac_to_integer(&ctx
->ac
, src
[i
]);
1951 result
= ac_build_gather_values(&ctx
->ac
, src
, num_components
);
1955 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1956 result
= LLVMBuildFPToSI(ctx
->ac
.builder
, src
[0], def_type
, "");
1960 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1961 result
= LLVMBuildFPToUI(ctx
->ac
.builder
, src
[0], def_type
, "");
1965 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1966 result
= LLVMBuildSIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1970 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1971 result
= LLVMBuildUIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1974 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1975 result
= LLVMBuildFPExt(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1978 result
= LLVMBuildFPTrunc(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1982 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1983 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1984 result
= LLVMBuildZExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1986 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1990 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1991 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1992 result
= LLVMBuildSExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1994 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1997 result
= emit_bcsel(&ctx
->ac
, src
[0], src
[1], src
[2]);
1999 case nir_op_find_lsb
:
2000 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2001 result
= ac_find_lsb(&ctx
->ac
, ctx
->ac
.i32
, src
[0]);
2003 case nir_op_ufind_msb
:
2004 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2005 result
= ac_build_umsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
2007 case nir_op_ifind_msb
:
2008 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2009 result
= ac_build_imsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
2011 case nir_op_uadd_carry
:
2012 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2013 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
2014 result
= emit_uint_carry(&ctx
->ac
, "llvm.uadd.with.overflow.i32", src
[0], src
[1]);
2016 case nir_op_usub_borrow
:
2017 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2018 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
2019 result
= emit_uint_carry(&ctx
->ac
, "llvm.usub.with.overflow.i32", src
[0], src
[1]);
2022 result
= emit_b2f(&ctx
->ac
, src
[0]);
2025 result
= emit_f2b(&ctx
->ac
, src
[0]);
2028 result
= emit_b2i(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
2031 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2032 result
= emit_i2b(&ctx
->ac
, src
[0]);
2034 case nir_op_fquantize2f16
:
2035 result
= emit_f2f16(ctx
->nctx
, src
[0]);
2037 case nir_op_umul_high
:
2038 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2039 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
2040 result
= emit_umul_high(&ctx
->ac
, src
[0], src
[1]);
2042 case nir_op_imul_high
:
2043 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2044 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
2045 result
= emit_imul_high(&ctx
->ac
, src
[0], src
[1]);
2047 case nir_op_pack_half_2x16
:
2048 result
= emit_pack_half_2x16(&ctx
->ac
, src
[0]);
2050 case nir_op_unpack_half_2x16
:
2051 result
= emit_unpack_half_2x16(&ctx
->ac
, src
[0]);
2055 case nir_op_fddx_fine
:
2056 case nir_op_fddy_fine
:
2057 case nir_op_fddx_coarse
:
2058 case nir_op_fddy_coarse
:
2059 result
= emit_ddxy(ctx
, instr
->op
, src
[0]);
2062 case nir_op_unpack_64_2x32_split_x
: {
2063 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
2064 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
2067 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2072 case nir_op_unpack_64_2x32_split_y
: {
2073 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
2074 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
2077 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2082 case nir_op_pack_64_2x32_split
: {
2083 LLVMValueRef tmp
= LLVMGetUndef(ctx
->ac
.v2i32
);
2084 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2085 src
[0], ctx
->ac
.i32_0
, "");
2086 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2087 src
[1], ctx
->ac
.i32_1
, "");
2088 result
= LLVMBuildBitCast(ctx
->ac
.builder
, tmp
, ctx
->ac
.i64
, "");
2093 fprintf(stderr
, "Unknown NIR alu instr: ");
2094 nir_print_instr(&instr
->instr
, stderr
);
2095 fprintf(stderr
, "\n");
2100 assert(instr
->dest
.dest
.is_ssa
);
2101 result
= ac_to_integer(&ctx
->ac
, result
);
2102 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.dest
.ssa
,
2107 static void visit_load_const(struct ac_nir_context
*ctx
,
2108 const nir_load_const_instr
*instr
)
2110 LLVMValueRef values
[4], value
= NULL
;
2111 LLVMTypeRef element_type
=
2112 LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
2114 for (unsigned i
= 0; i
< instr
->def
.num_components
; ++i
) {
2115 switch (instr
->def
.bit_size
) {
2117 values
[i
] = LLVMConstInt(element_type
,
2118 instr
->value
.u32
[i
], false);
2121 values
[i
] = LLVMConstInt(element_type
,
2122 instr
->value
.u64
[i
], false);
2126 "unsupported nir load_const bit_size: %d\n",
2127 instr
->def
.bit_size
);
2131 if (instr
->def
.num_components
> 1) {
2132 value
= LLVMConstVector(values
, instr
->def
.num_components
);
2136 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, value
);
2139 static LLVMValueRef
cast_ptr(struct nir_to_llvm_context
*ctx
, LLVMValueRef ptr
,
2142 int addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
2143 return LLVMBuildBitCast(ctx
->builder
, ptr
,
2144 LLVMPointerType(type
, addr_space
), "");
2148 get_buffer_size(struct ac_nir_context
*ctx
, LLVMValueRef descriptor
, bool in_elements
)
2151 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2152 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
2155 if (ctx
->ac
.chip_class
== VI
&& in_elements
) {
2156 /* On VI, the descriptor contains the size in bytes,
2157 * but TXQ must return the size in elements.
2158 * The stride is always non-zero for resources using TXQ.
2160 LLVMValueRef stride
=
2161 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2163 stride
= LLVMBuildLShr(ctx
->ac
.builder
, stride
,
2164 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
2165 stride
= LLVMBuildAnd(ctx
->ac
.builder
, stride
,
2166 LLVMConstInt(ctx
->ac
.i32
, 0x3fff, false), "");
2168 size
= LLVMBuildUDiv(ctx
->ac
.builder
, size
, stride
, "");
2174 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2177 static void build_int_type_name(
2179 char *buf
, unsigned bufsize
)
2181 assert(bufsize
>= 6);
2183 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
2184 snprintf(buf
, bufsize
, "v%ui32",
2185 LLVMGetVectorSize(type
));
2190 static LLVMValueRef
radv_lower_gather4_integer(struct ac_llvm_context
*ctx
,
2191 struct ac_image_args
*args
,
2192 const nir_tex_instr
*instr
)
2194 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2195 LLVMValueRef coord
= args
->addr
;
2196 LLVMValueRef half_texel
[2];
2197 LLVMValueRef compare_cube_wa
= NULL
;
2198 LLVMValueRef result
;
2200 unsigned coord_vgpr_index
= (unsigned)args
->offset
+ (unsigned)args
->compare
;
2204 struct ac_image_args txq_args
= { 0 };
2206 txq_args
.da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
2207 txq_args
.opcode
= ac_image_get_resinfo
;
2208 txq_args
.dmask
= 0xf;
2209 txq_args
.addr
= ctx
->i32_0
;
2210 txq_args
.resource
= args
->resource
;
2211 LLVMValueRef size
= ac_build_image_opcode(ctx
, &txq_args
);
2213 for (c
= 0; c
< 2; c
++) {
2214 half_texel
[c
] = LLVMBuildExtractElement(ctx
->builder
, size
,
2215 LLVMConstInt(ctx
->i32
, c
, false), "");
2216 half_texel
[c
] = LLVMBuildUIToFP(ctx
->builder
, half_texel
[c
], ctx
->f32
, "");
2217 half_texel
[c
] = ac_build_fdiv(ctx
, ctx
->f32_1
, half_texel
[c
]);
2218 half_texel
[c
] = LLVMBuildFMul(ctx
->builder
, half_texel
[c
],
2219 LLVMConstReal(ctx
->f32
, -0.5), "");
2223 LLVMValueRef orig_coords
= args
->addr
;
2225 for (c
= 0; c
< 2; c
++) {
2227 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, coord_vgpr_index
+ c
, 0);
2228 tmp
= LLVMBuildExtractElement(ctx
->builder
, coord
, index
, "");
2229 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2230 tmp
= LLVMBuildFAdd(ctx
->builder
, tmp
, half_texel
[c
], "");
2231 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2232 coord
= LLVMBuildInsertElement(ctx
->builder
, coord
, tmp
, index
, "");
2237 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2238 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2239 * workaround by sampling using a scaled type and converting.
2240 * This is taken from amdgpu-pro shaders.
2242 /* NOTE this produces some ugly code compared to amdgpu-pro,
2243 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2244 * and then reads them back. -pro generates two selects,
2245 * one s_cmp for the descriptor rewriting
2246 * one v_cmp for the coordinate and result changes.
2248 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2249 LLVMValueRef tmp
, tmp2
;
2251 /* workaround 8/8/8/8 uint/sint cube gather bug */
2252 /* first detect it then change to a scaled read and f2i */
2253 tmp
= LLVMBuildExtractElement(ctx
->builder
, args
->resource
, ctx
->i32_1
, "");
2256 /* extract the DATA_FORMAT */
2257 tmp
= ac_build_bfe(ctx
, tmp
, LLVMConstInt(ctx
->i32
, 20, false),
2258 LLVMConstInt(ctx
->i32
, 6, false), false);
2260 /* is the DATA_FORMAT == 8_8_8_8 */
2261 compare_cube_wa
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, tmp
, LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false), "");
2263 if (stype
== GLSL_TYPE_UINT
)
2264 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2265 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0x8000000, false),
2266 LLVMConstInt(ctx
->i32
, 0x10000000, false), "");
2268 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2269 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0xc000000, false),
2270 LLVMConstInt(ctx
->i32
, 0x14000000, false), "");
2272 /* replace the NUM FORMAT in the descriptor */
2273 tmp2
= LLVMBuildAnd(ctx
->builder
, tmp2
, LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false), "");
2274 tmp2
= LLVMBuildOr(ctx
->builder
, tmp2
, tmp
, "");
2276 args
->resource
= LLVMBuildInsertElement(ctx
->builder
, args
->resource
, tmp2
, ctx
->i32_1
, "");
2278 /* don't modify the coordinates for this case */
2279 coord
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, orig_coords
, coord
, "");
2282 result
= ac_build_image_opcode(ctx
, args
);
2284 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2285 LLVMValueRef tmp
, tmp2
;
2287 /* if the cube workaround is in place, f2i the result. */
2288 for (c
= 0; c
< 4; c
++) {
2289 tmp
= LLVMBuildExtractElement(ctx
->builder
, result
, LLVMConstInt(ctx
->i32
, c
, false), "");
2290 if (stype
== GLSL_TYPE_UINT
)
2291 tmp2
= LLVMBuildFPToUI(ctx
->builder
, tmp
, ctx
->i32
, "");
2293 tmp2
= LLVMBuildFPToSI(ctx
->builder
, tmp
, ctx
->i32
, "");
2294 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2295 tmp2
= LLVMBuildBitCast(ctx
->builder
, tmp2
, ctx
->i32
, "");
2296 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, tmp2
, tmp
, "");
2297 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2298 result
= LLVMBuildInsertElement(ctx
->builder
, result
, tmp
, LLVMConstInt(ctx
->i32
, c
, false), "");
2304 static LLVMValueRef
build_tex_intrinsic(struct ac_nir_context
*ctx
,
2305 const nir_tex_instr
*instr
,
2307 struct ac_image_args
*args
)
2309 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
2310 return ac_build_buffer_load_format(&ctx
->ac
,
2317 args
->opcode
= ac_image_sample
;
2318 args
->compare
= instr
->is_shadow
;
2320 switch (instr
->op
) {
2322 case nir_texop_txf_ms
:
2323 case nir_texop_samples_identical
:
2324 args
->opcode
= lod_is_zero
||
2325 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
?
2326 ac_image_load
: ac_image_load_mip
;
2327 args
->compare
= false;
2328 args
->offset
= false;
2335 args
->level_zero
= true;
2340 case nir_texop_query_levels
:
2341 args
->opcode
= ac_image_get_resinfo
;
2344 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
2345 args
->level_zero
= true;
2351 args
->opcode
= ac_image_gather4
;
2352 args
->level_zero
= true;
2355 args
->opcode
= ac_image_get_lod
;
2356 args
->compare
= false;
2357 args
->offset
= false;
2363 if (instr
->op
== nir_texop_tg4
&& ctx
->ac
.chip_class
<= VI
) {
2364 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2365 if (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
) {
2366 return radv_lower_gather4_integer(&ctx
->ac
, args
, instr
);
2369 return ac_build_image_opcode(&ctx
->ac
, args
);
2372 static LLVMValueRef
visit_vulkan_resource_index(struct nir_to_llvm_context
*ctx
,
2373 nir_intrinsic_instr
*instr
)
2375 LLVMValueRef index
= get_src(ctx
->nir
, instr
->src
[0]);
2376 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
2377 unsigned binding
= nir_intrinsic_binding(instr
);
2378 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
2379 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
2380 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
2381 unsigned base_offset
= layout
->binding
[binding
].offset
;
2382 LLVMValueRef offset
, stride
;
2384 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
2385 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
2386 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
2387 layout
->binding
[binding
].dynamic_offset_offset
;
2388 desc_ptr
= ctx
->push_constants
;
2389 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
2390 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2392 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
2394 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
2395 index
= LLVMBuildMul(ctx
->builder
, index
, stride
, "");
2396 offset
= LLVMBuildAdd(ctx
->builder
, offset
, index
, "");
2398 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
2399 desc_ptr
= cast_ptr(ctx
, desc_ptr
, ctx
->ac
.v4i32
);
2400 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2405 static LLVMValueRef
visit_vulkan_resource_reindex(struct nir_to_llvm_context
*ctx
,
2406 nir_intrinsic_instr
*instr
)
2408 LLVMValueRef ptr
= get_src(ctx
->nir
, instr
->src
[0]);
2409 LLVMValueRef index
= get_src(ctx
->nir
, instr
->src
[1]);
2411 LLVMValueRef result
= LLVMBuildGEP(ctx
->builder
, ptr
, &index
, 1, "");
2412 LLVMSetMetadata(result
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2416 static LLVMValueRef
visit_load_push_constant(struct nir_to_llvm_context
*ctx
,
2417 nir_intrinsic_instr
*instr
)
2419 LLVMValueRef ptr
, addr
;
2421 addr
= LLVMConstInt(ctx
->ac
.i32
, nir_intrinsic_base(instr
), 0);
2422 addr
= LLVMBuildAdd(ctx
->builder
, addr
, get_src(ctx
->nir
, instr
->src
[0]), "");
2424 ptr
= ac_build_gep0(&ctx
->ac
, ctx
->push_constants
, addr
);
2425 ptr
= cast_ptr(ctx
, ptr
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
));
2427 return LLVMBuildLoad(ctx
->builder
, ptr
, "");
2430 static LLVMValueRef
visit_get_buffer_size(struct ac_nir_context
*ctx
,
2431 const nir_intrinsic_instr
*instr
)
2433 LLVMValueRef index
= get_src(ctx
, instr
->src
[0]);
2435 return get_buffer_size(ctx
, ctx
->abi
->load_ssbo(ctx
->abi
, index
, false), false);
2438 static uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2440 uint32_t new_mask
= 0;
2441 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2442 if (mask
& (1u << i
))
2443 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2447 static LLVMValueRef
extract_vector_range(struct ac_llvm_context
*ctx
, LLVMValueRef src
,
2448 unsigned start
, unsigned count
)
2450 LLVMTypeRef type
= LLVMTypeOf(src
);
2452 if (LLVMGetTypeKind(type
) != LLVMVectorTypeKind
) {
2458 unsigned src_elements
= LLVMGetVectorSize(type
);
2459 assert(start
< src_elements
);
2460 assert(start
+ count
<= src_elements
);
2462 if (start
== 0 && count
== src_elements
)
2466 return LLVMBuildExtractElement(ctx
->builder
, src
, LLVMConstInt(ctx
->i32
, start
, false), "");
2469 LLVMValueRef indices
[8];
2470 for (unsigned i
= 0; i
< count
; ++i
)
2471 indices
[i
] = LLVMConstInt(ctx
->i32
, start
+ i
, false);
2473 LLVMValueRef swizzle
= LLVMConstVector(indices
, count
);
2474 return LLVMBuildShuffleVector(ctx
->builder
, src
, src
, swizzle
, "");
2477 static void visit_store_ssbo(struct ac_nir_context
*ctx
,
2478 nir_intrinsic_instr
*instr
)
2480 const char *store_name
;
2481 LLVMValueRef src_data
= get_src(ctx
, instr
->src
[0]);
2482 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2483 int elem_size_mult
= get_elem_bits(&ctx
->ac
, LLVMTypeOf(src_data
)) / 32;
2484 int components_32bit
= elem_size_mult
* instr
->num_components
;
2485 unsigned writemask
= nir_intrinsic_write_mask(instr
);
2486 LLVMValueRef base_data
, base_offset
;
2487 LLVMValueRef params
[6];
2489 params
[1] = ctx
->abi
->load_ssbo(ctx
->abi
,
2490 get_src(ctx
, instr
->src
[1]), true);
2491 params
[2] = ctx
->ac
.i32_0
; /* vindex */
2492 params
[4] = ctx
->ac
.i1false
; /* glc */
2493 params
[5] = ctx
->ac
.i1false
; /* slc */
2495 if (components_32bit
> 1)
2496 data_type
= LLVMVectorType(ctx
->ac
.f32
, components_32bit
);
2498 writemask
= widen_mask(writemask
, elem_size_mult
);
2500 base_data
= ac_to_float(&ctx
->ac
, src_data
);
2501 base_data
= trim_vector(&ctx
->ac
, base_data
, instr
->num_components
);
2502 base_data
= LLVMBuildBitCast(ctx
->ac
.builder
, base_data
,
2504 base_offset
= get_src(ctx
, instr
->src
[2]); /* voffset */
2508 LLVMValueRef offset
;
2510 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
2512 /* Due to an LLVM limitation, split 3-element writes
2513 * into a 2-element and a 1-element write. */
2515 writemask
|= 1 << (start
+ 2);
2520 writemask
|= ((1u << (count
- 4)) - 1u) << (start
+ 4);
2525 store_name
= "llvm.amdgcn.buffer.store.v4f32";
2526 } else if (count
== 2) {
2527 store_name
= "llvm.amdgcn.buffer.store.v2f32";
2531 store_name
= "llvm.amdgcn.buffer.store.f32";
2533 data
= extract_vector_range(&ctx
->ac
, base_data
, start
, count
);
2535 offset
= base_offset
;
2537 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, LLVMConstInt(ctx
->ac
.i32
, start
* 4, false), "");
2541 ac_build_intrinsic(&ctx
->ac
, store_name
,
2542 ctx
->ac
.voidt
, params
, 6, 0);
2546 static LLVMValueRef
visit_atomic_ssbo(struct ac_nir_context
*ctx
,
2547 const nir_intrinsic_instr
*instr
)
2550 LLVMValueRef params
[6];
2553 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
) {
2554 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[3]), 0);
2556 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[2]), 0);
2557 params
[arg_count
++] = ctx
->abi
->load_ssbo(ctx
->abi
,
2558 get_src(ctx
, instr
->src
[0]),
2560 params
[arg_count
++] = ctx
->ac
.i32_0
; /* vindex */
2561 params
[arg_count
++] = get_src(ctx
, instr
->src
[1]); /* voffset */
2562 params
[arg_count
++] = LLVMConstInt(ctx
->ac
.i1
, 0, false); /* slc */
2564 switch (instr
->intrinsic
) {
2565 case nir_intrinsic_ssbo_atomic_add
:
2566 name
= "llvm.amdgcn.buffer.atomic.add";
2568 case nir_intrinsic_ssbo_atomic_imin
:
2569 name
= "llvm.amdgcn.buffer.atomic.smin";
2571 case nir_intrinsic_ssbo_atomic_umin
:
2572 name
= "llvm.amdgcn.buffer.atomic.umin";
2574 case nir_intrinsic_ssbo_atomic_imax
:
2575 name
= "llvm.amdgcn.buffer.atomic.smax";
2577 case nir_intrinsic_ssbo_atomic_umax
:
2578 name
= "llvm.amdgcn.buffer.atomic.umax";
2580 case nir_intrinsic_ssbo_atomic_and
:
2581 name
= "llvm.amdgcn.buffer.atomic.and";
2583 case nir_intrinsic_ssbo_atomic_or
:
2584 name
= "llvm.amdgcn.buffer.atomic.or";
2586 case nir_intrinsic_ssbo_atomic_xor
:
2587 name
= "llvm.amdgcn.buffer.atomic.xor";
2589 case nir_intrinsic_ssbo_atomic_exchange
:
2590 name
= "llvm.amdgcn.buffer.atomic.swap";
2592 case nir_intrinsic_ssbo_atomic_comp_swap
:
2593 name
= "llvm.amdgcn.buffer.atomic.cmpswap";
2599 return ac_build_intrinsic(&ctx
->ac
, name
, ctx
->ac
.i32
, params
, arg_count
, 0);
2602 static LLVMValueRef
visit_load_buffer(struct ac_nir_context
*ctx
,
2603 const nir_intrinsic_instr
*instr
)
2605 LLVMValueRef results
[2];
2606 int load_components
;
2607 int num_components
= instr
->num_components
;
2608 if (instr
->dest
.ssa
.bit_size
== 64)
2609 num_components
*= 2;
2611 for (int i
= 0; i
< num_components
; i
+= load_components
) {
2612 load_components
= MIN2(num_components
- i
, 4);
2613 const char *load_name
;
2614 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2615 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, i
* 4, false);
2616 offset
= LLVMBuildAdd(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[1]), offset
, "");
2618 if (load_components
== 3)
2619 data_type
= LLVMVectorType(ctx
->ac
.f32
, 4);
2620 else if (load_components
> 1)
2621 data_type
= LLVMVectorType(ctx
->ac
.f32
, load_components
);
2623 if (load_components
>= 3)
2624 load_name
= "llvm.amdgcn.buffer.load.v4f32";
2625 else if (load_components
== 2)
2626 load_name
= "llvm.amdgcn.buffer.load.v2f32";
2627 else if (load_components
== 1)
2628 load_name
= "llvm.amdgcn.buffer.load.f32";
2630 unreachable("unhandled number of components");
2632 LLVMValueRef params
[] = {
2633 ctx
->abi
->load_ssbo(ctx
->abi
,
2634 get_src(ctx
, instr
->src
[0]),
2642 results
[i
> 0 ? 1 : 0] = ac_build_intrinsic(&ctx
->ac
, load_name
, data_type
, params
, 5, 0);
2646 LLVMValueRef ret
= results
[0];
2647 if (num_components
> 4 || num_components
== 3) {
2648 LLVMValueRef masks
[] = {
2649 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
2650 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
2651 LLVMConstInt(ctx
->ac
.i32
, 4, false), LLVMConstInt(ctx
->ac
.i32
, 5, false),
2652 LLVMConstInt(ctx
->ac
.i32
, 6, false), LLVMConstInt(ctx
->ac
.i32
, 7, false)
2655 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
2656 ret
= LLVMBuildShuffleVector(ctx
->ac
.builder
, results
[0],
2657 results
[num_components
> 4 ? 1 : 0], swizzle
, "");
2660 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2661 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2664 static LLVMValueRef
visit_load_ubo_buffer(struct ac_nir_context
*ctx
,
2665 const nir_intrinsic_instr
*instr
)
2668 LLVMValueRef rsrc
= get_src(ctx
, instr
->src
[0]);
2669 LLVMValueRef offset
= get_src(ctx
, instr
->src
[1]);
2670 int num_components
= instr
->num_components
;
2672 if (ctx
->abi
->load_ubo
)
2673 rsrc
= ctx
->abi
->load_ubo(ctx
->abi
, rsrc
);
2675 if (instr
->dest
.ssa
.bit_size
== 64)
2676 num_components
*= 2;
2678 ret
= ac_build_buffer_load(&ctx
->ac
, rsrc
, num_components
, NULL
, offset
,
2679 NULL
, 0, false, false, true, true);
2680 ret
= trim_vector(&ctx
->ac
, ret
, num_components
);
2681 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2682 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2686 get_deref_offset(struct ac_nir_context
*ctx
, nir_deref_var
*deref
,
2687 bool vs_in
, unsigned *vertex_index_out
,
2688 LLVMValueRef
*vertex_index_ref
,
2689 unsigned *const_out
, LLVMValueRef
*indir_out
)
2691 unsigned const_offset
= 0;
2692 nir_deref
*tail
= &deref
->deref
;
2693 LLVMValueRef offset
= NULL
;
2695 if (vertex_index_out
!= NULL
|| vertex_index_ref
!= NULL
) {
2697 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2698 if (vertex_index_out
)
2699 *vertex_index_out
= deref_array
->base_offset
;
2701 if (vertex_index_ref
) {
2702 LLVMValueRef vtx
= LLVMConstInt(ctx
->ac
.i32
, deref_array
->base_offset
, false);
2703 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
2704 vtx
= LLVMBuildAdd(ctx
->ac
.builder
, vtx
, get_src(ctx
, deref_array
->indirect
), "");
2706 *vertex_index_ref
= vtx
;
2710 if (deref
->var
->data
.compact
) {
2711 assert(tail
->child
->deref_type
== nir_deref_type_array
);
2712 assert(glsl_type_is_scalar(glsl_without_array(deref
->var
->type
)));
2713 nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
2714 /* We always lower indirect dereferences for "compact" array vars. */
2715 assert(deref_array
->deref_array_type
== nir_deref_array_type_direct
);
2717 const_offset
= deref_array
->base_offset
;
2721 while (tail
->child
!= NULL
) {
2722 const struct glsl_type
*parent_type
= tail
->type
;
2725 if (tail
->deref_type
== nir_deref_type_array
) {
2726 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2727 LLVMValueRef index
, stride
, local_offset
;
2728 unsigned size
= glsl_count_attribute_slots(tail
->type
, vs_in
);
2730 const_offset
+= size
* deref_array
->base_offset
;
2731 if (deref_array
->deref_array_type
== nir_deref_array_type_direct
)
2734 assert(deref_array
->deref_array_type
== nir_deref_array_type_indirect
);
2735 index
= get_src(ctx
, deref_array
->indirect
);
2736 stride
= LLVMConstInt(ctx
->ac
.i32
, size
, 0);
2737 local_offset
= LLVMBuildMul(ctx
->ac
.builder
, stride
, index
, "");
2740 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, local_offset
, "");
2742 offset
= local_offset
;
2743 } else if (tail
->deref_type
== nir_deref_type_struct
) {
2744 nir_deref_struct
*deref_struct
= nir_deref_as_struct(tail
);
2746 for (unsigned i
= 0; i
< deref_struct
->index
; i
++) {
2747 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
2748 const_offset
+= glsl_count_attribute_slots(ft
, vs_in
);
2751 unreachable("unsupported deref type");
2755 if (const_offset
&& offset
)
2756 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
2757 LLVMConstInt(ctx
->ac
.i32
, const_offset
, 0),
2760 *const_out
= const_offset
;
2761 *indir_out
= offset
;
2765 /* The offchip buffer layout for TCS->TES is
2767 * - attribute 0 of patch 0 vertex 0
2768 * - attribute 0 of patch 0 vertex 1
2769 * - attribute 0 of patch 0 vertex 2
2771 * - attribute 0 of patch 1 vertex 0
2772 * - attribute 0 of patch 1 vertex 1
2774 * - attribute 1 of patch 0 vertex 0
2775 * - attribute 1 of patch 0 vertex 1
2777 * - per patch attribute 0 of patch 0
2778 * - per patch attribute 0 of patch 1
2781 * Note that every attribute has 4 components.
2783 static LLVMValueRef
get_tcs_tes_buffer_address(struct nir_to_llvm_context
*ctx
,
2784 LLVMValueRef vertex_index
,
2785 LLVMValueRef param_index
)
2787 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
2788 LLVMValueRef param_stride
, constant16
;
2789 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
2791 vertices_per_patch
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 9, 6);
2792 num_patches
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 0, 9);
2793 total_vertices
= LLVMBuildMul(ctx
->builder
, vertices_per_patch
,
2796 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2798 base_addr
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
2799 vertices_per_patch
, "");
2801 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2804 param_stride
= total_vertices
;
2806 base_addr
= rel_patch_id
;
2807 param_stride
= num_patches
;
2810 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2811 LLVMBuildMul(ctx
->builder
, param_index
,
2812 param_stride
, ""), "");
2814 base_addr
= LLVMBuildMul(ctx
->builder
, base_addr
, constant16
, "");
2816 if (!vertex_index
) {
2817 LLVMValueRef patch_data_offset
=
2818 unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 16, 16);
2820 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2821 patch_data_offset
, "");
2826 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct nir_to_llvm_context
*ctx
,
2828 unsigned const_index
,
2830 LLVMValueRef vertex_index
,
2831 LLVMValueRef indir_index
)
2833 LLVMValueRef param_index
;
2836 param_index
= LLVMBuildAdd(ctx
->builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
2839 if (const_index
&& !is_compact
)
2840 param
+= const_index
;
2841 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
2843 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
2847 mark_tess_output(struct nir_to_llvm_context
*ctx
,
2848 bool is_patch
, uint32_t param
)
2852 ctx
->tess_patch_outputs_written
|= (1ull << param
);
2854 ctx
->tess_outputs_written
|= (1ull << param
);
2858 get_dw_address(struct nir_to_llvm_context
*ctx
,
2859 LLVMValueRef dw_addr
,
2861 unsigned const_index
,
2862 bool compact_const_index
,
2863 LLVMValueRef vertex_index
,
2864 LLVMValueRef stride
,
2865 LLVMValueRef indir_index
)
2870 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2871 LLVMBuildMul(ctx
->builder
,
2877 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2878 LLVMBuildMul(ctx
->builder
, indir_index
,
2879 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
2880 else if (const_index
&& !compact_const_index
)
2881 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2882 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2884 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2885 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
2887 if (const_index
&& compact_const_index
)
2888 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2889 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2894 load_tcs_varyings(struct ac_shader_abi
*abi
,
2895 LLVMValueRef vertex_index
,
2896 LLVMValueRef indir_index
,
2897 unsigned const_index
,
2899 unsigned driver_location
,
2901 unsigned num_components
,
2906 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
2907 LLVMValueRef dw_addr
, stride
;
2908 LLVMValueRef value
[4], result
;
2909 unsigned param
= shader_io_get_unique_index(location
);
2912 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 13, 8);
2913 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
2916 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
2917 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2919 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2924 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2927 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
2928 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2929 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2932 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
2937 store_tcs_output(struct ac_shader_abi
*abi
,
2938 LLVMValueRef vertex_index
,
2939 LLVMValueRef param_index
,
2940 unsigned const_index
,
2942 unsigned driver_location
,
2949 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
2950 LLVMValueRef dw_addr
;
2951 LLVMValueRef stride
= NULL
;
2952 LLVMValueRef buf_addr
= NULL
;
2954 bool store_lds
= true;
2957 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
2960 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
2964 param
= shader_io_get_unique_index(location
);
2965 if (location
== VARYING_SLOT_CLIP_DIST0
&&
2966 is_compact
&& const_index
> 3) {
2972 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
2973 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2975 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2978 mark_tess_output(ctx
, is_patch
, param
);
2980 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2982 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
2983 vertex_index
, param_index
);
2985 bool is_tess_factor
= false;
2986 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
2987 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
2988 is_tess_factor
= true;
2990 unsigned base
= is_compact
? const_index
: 0;
2991 for (unsigned chan
= 0; chan
< 8; chan
++) {
2992 if (!(writemask
& (1 << chan
)))
2994 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
2996 if (store_lds
|| is_tess_factor
) {
2997 LLVMValueRef dw_addr_chan
=
2998 LLVMBuildAdd(ctx
->builder
, dw_addr
,
2999 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
3000 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
3003 if (!is_tess_factor
&& writemask
!= 0xF)
3004 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
3005 buf_addr
, ctx
->oc_lds
,
3006 4 * (base
+ chan
), 1, 0, true, false);
3009 if (writemask
== 0xF) {
3010 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
3011 buf_addr
, ctx
->oc_lds
,
3012 (base
* 4), 1, 0, true, false);
3017 load_tes_input(struct ac_shader_abi
*abi
,
3018 LLVMValueRef vertex_index
,
3019 LLVMValueRef param_index
,
3020 unsigned const_index
,
3022 unsigned driver_location
,
3024 unsigned num_components
,
3029 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
3030 LLVMValueRef buf_addr
;
3031 LLVMValueRef result
;
3032 unsigned param
= shader_io_get_unique_index(location
);
3034 if (location
== VARYING_SLOT_CLIP_DIST0
&& is_compact
&& const_index
> 3) {
3039 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
3040 is_compact
, vertex_index
, param_index
);
3042 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
3043 buf_addr
= LLVMBuildAdd(ctx
->builder
, buf_addr
, comp_offset
, "");
3045 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
3046 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
3047 result
= trim_vector(&ctx
->ac
, result
, num_components
);
3052 load_gs_input(struct ac_shader_abi
*abi
,
3054 unsigned driver_location
,
3056 unsigned num_components
,
3057 unsigned vertex_index
,
3058 unsigned const_index
,
3061 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
3062 LLVMValueRef vtx_offset
;
3063 LLVMValueRef args
[9];
3064 unsigned param
, vtx_offset_param
;
3065 LLVMValueRef value
[4], result
;
3067 vtx_offset_param
= vertex_index
;
3068 assert(vtx_offset_param
< 6);
3069 vtx_offset
= LLVMBuildMul(ctx
->builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
3070 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3072 param
= shader_io_get_unique_index(location
);
3074 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
3075 if (ctx
->ac
.chip_class
>= GFX9
) {
3076 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
3077 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
3078 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
3079 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
3081 args
[0] = ctx
->esgs_ring
;
3082 args
[1] = vtx_offset
;
3083 args
[2] = LLVMConstInt(ctx
->ac
.i32
, (param
* 4 + i
+ const_index
) * 256, false);
3084 args
[3] = ctx
->ac
.i32_0
;
3085 args
[4] = ctx
->ac
.i32_1
; /* OFFEN */
3086 args
[5] = ctx
->ac
.i32_0
; /* IDXEN */
3087 args
[6] = ctx
->ac
.i32_1
; /* GLC */
3088 args
[7] = ctx
->ac
.i32_0
; /* SLC */
3089 args
[8] = ctx
->ac
.i32_0
; /* TFE */
3091 value
[i
] = ac_build_intrinsic(&ctx
->ac
, "llvm.SI.buffer.load.dword.i32.i32",
3092 ctx
->ac
.i32
, args
, 9,
3093 AC_FUNC_ATTR_READONLY
|
3094 AC_FUNC_ATTR_LEGACY
);
3097 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
3103 build_gep_for_deref(struct ac_nir_context
*ctx
,
3104 nir_deref_var
*deref
)
3106 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->vars
, deref
->var
);
3107 assert(entry
->data
);
3108 LLVMValueRef val
= entry
->data
;
3109 nir_deref
*tail
= deref
->deref
.child
;
3110 while (tail
!= NULL
) {
3111 LLVMValueRef offset
;
3112 switch (tail
->deref_type
) {
3113 case nir_deref_type_array
: {
3114 nir_deref_array
*array
= nir_deref_as_array(tail
);
3115 offset
= LLVMConstInt(ctx
->ac
.i32
, array
->base_offset
, 0);
3116 if (array
->deref_array_type
==
3117 nir_deref_array_type_indirect
) {
3118 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
3125 case nir_deref_type_struct
: {
3126 nir_deref_struct
*deref_struct
=
3127 nir_deref_as_struct(tail
);
3128 offset
= LLVMConstInt(ctx
->ac
.i32
,
3129 deref_struct
->index
, 0);
3133 unreachable("bad deref type");
3135 val
= ac_build_gep0(&ctx
->ac
, val
, offset
);
3141 static LLVMValueRef
load_tess_varyings(struct ac_nir_context
*ctx
,
3142 nir_intrinsic_instr
*instr
,
3145 LLVMValueRef result
;
3146 LLVMValueRef vertex_index
= NULL
;
3147 LLVMValueRef indir_index
= NULL
;
3148 unsigned const_index
= 0;
3149 unsigned location
= instr
->variables
[0]->var
->data
.location
;
3150 unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3151 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3152 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3154 get_deref_offset(ctx
, instr
->variables
[0],
3155 false, NULL
, is_patch
? NULL
: &vertex_index
,
3156 &const_index
, &indir_index
);
3158 result
= ctx
->abi
->load_tess_varyings(ctx
->abi
, vertex_index
, indir_index
,
3159 const_index
, location
, driver_location
,
3160 instr
->variables
[0]->var
->data
.location_frac
,
3161 instr
->num_components
,
3162 is_patch
, is_compact
, load_inputs
);
3163 return LLVMBuildBitCast(ctx
->ac
.builder
, result
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3166 static LLVMValueRef
visit_load_var(struct ac_nir_context
*ctx
,
3167 nir_intrinsic_instr
*instr
)
3169 LLVMValueRef values
[8];
3170 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3171 int ve
= instr
->dest
.ssa
.num_components
;
3172 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3173 LLVMValueRef indir_index
;
3175 unsigned const_index
;
3176 unsigned stride
= instr
->variables
[0]->var
->data
.compact
? 1 : 4;
3177 bool vs_in
= ctx
->stage
== MESA_SHADER_VERTEX
&&
3178 instr
->variables
[0]->var
->data
.mode
== nir_var_shader_in
;
3179 get_deref_offset(ctx
, instr
->variables
[0], vs_in
, NULL
, NULL
,
3180 &const_index
, &indir_index
);
3182 if (instr
->dest
.ssa
.bit_size
== 64)
3185 switch (instr
->variables
[0]->var
->data
.mode
) {
3186 case nir_var_shader_in
:
3187 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3188 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3189 return load_tess_varyings(ctx
, instr
, true);
3192 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3193 LLVMValueRef indir_index
;
3194 unsigned const_index
, vertex_index
;
3195 get_deref_offset(ctx
, instr
->variables
[0],
3196 false, &vertex_index
, NULL
,
3197 &const_index
, &indir_index
);
3198 return ctx
->abi
->load_inputs(ctx
->abi
, instr
->variables
[0]->var
->data
.location
,
3199 instr
->variables
[0]->var
->data
.driver_location
,
3200 instr
->variables
[0]->var
->data
.location_frac
, ve
,
3201 vertex_index
, const_index
,
3202 nir2llvmtype(ctx
, instr
->variables
[0]->var
->type
));
3205 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3207 unsigned count
= glsl_count_attribute_slots(
3208 instr
->variables
[0]->var
->type
,
3209 ctx
->stage
== MESA_SHADER_VERTEX
);
3211 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3212 &ctx
->ac
, ctx
->abi
->inputs
+ idx
+ chan
, count
,
3213 stride
, false, true);
3215 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3219 values
[chan
] = ctx
->abi
->inputs
[idx
+ chan
+ const_index
* stride
];
3223 for (unsigned chan
= 0; chan
< ve
; chan
++) {
3225 unsigned count
= glsl_count_attribute_slots(
3226 instr
->variables
[0]->var
->type
, false);
3228 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3229 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3230 stride
, true, true);
3232 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3236 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, ctx
->locals
[idx
+ chan
+ const_index
* stride
], "");
3240 case nir_var_shared
: {
3241 LLVMValueRef address
= build_gep_for_deref(ctx
,
3242 instr
->variables
[0]);
3243 LLVMValueRef val
= LLVMBuildLoad(ctx
->ac
.builder
, address
, "");
3244 return LLVMBuildBitCast(ctx
->ac
.builder
, val
,
3245 get_def_type(ctx
, &instr
->dest
.ssa
),
3248 case nir_var_shader_out
:
3249 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3250 return load_tess_varyings(ctx
, instr
, false);
3253 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3255 unsigned count
= glsl_count_attribute_slots(
3256 instr
->variables
[0]->var
->type
, false);
3258 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3259 &ctx
->ac
, ctx
->outputs
+ idx
+ chan
, count
,
3260 stride
, true, true);
3262 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3266 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
,
3267 ctx
->outputs
[idx
+ chan
+ const_index
* stride
],
3273 unreachable("unhandle variable mode");
3275 ret
= ac_build_varying_gather_values(&ctx
->ac
, values
, ve
, comp
);
3276 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3280 visit_store_var(struct ac_nir_context
*ctx
,
3281 nir_intrinsic_instr
*instr
)
3283 LLVMValueRef temp_ptr
, value
;
3284 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3285 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3286 LLVMValueRef src
= ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
3287 int writemask
= instr
->const_index
[0] << comp
;
3288 LLVMValueRef indir_index
;
3289 unsigned const_index
;
3290 get_deref_offset(ctx
, instr
->variables
[0], false,
3291 NULL
, NULL
, &const_index
, &indir_index
);
3293 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
)) == 64) {
3295 src
= LLVMBuildBitCast(ctx
->ac
.builder
, src
,
3296 LLVMVectorType(ctx
->ac
.f32
, ac_get_llvm_num_components(src
) * 2),
3299 writemask
= widen_mask(writemask
, 2);
3302 switch (instr
->variables
[0]->var
->data
.mode
) {
3303 case nir_var_shader_out
:
3305 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3306 LLVMValueRef vertex_index
= NULL
;
3307 LLVMValueRef indir_index
= NULL
;
3308 unsigned const_index
= 0;
3309 const unsigned location
= instr
->variables
[0]->var
->data
.location
;
3310 const unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3311 const unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3312 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3313 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3315 get_deref_offset(ctx
, instr
->variables
[0],
3316 false, NULL
, is_patch
? NULL
: &vertex_index
,
3317 &const_index
, &indir_index
);
3319 ctx
->abi
->store_tcs_outputs(ctx
->abi
, vertex_index
, indir_index
,
3320 const_index
, location
, driver_location
,
3321 src
, comp
, is_patch
, is_compact
, writemask
);
3325 for (unsigned chan
= 0; chan
< 8; chan
++) {
3327 if (!(writemask
& (1 << chan
)))
3330 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- comp
);
3332 if (instr
->variables
[0]->var
->data
.compact
)
3335 unsigned count
= glsl_count_attribute_slots(
3336 instr
->variables
[0]->var
->type
, false);
3338 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3339 &ctx
->ac
, ctx
->outputs
+ idx
+ chan
, count
,
3340 stride
, true, true);
3342 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3343 value
, indir_index
, "");
3344 build_store_values_extended(&ctx
->ac
, ctx
->outputs
+ idx
+ chan
,
3345 count
, stride
, tmp_vec
);
3348 temp_ptr
= ctx
->outputs
[idx
+ chan
+ const_index
* stride
];
3350 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3355 for (unsigned chan
= 0; chan
< 8; chan
++) {
3356 if (!(writemask
& (1 << chan
)))
3359 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
);
3361 unsigned count
= glsl_count_attribute_slots(
3362 instr
->variables
[0]->var
->type
, false);
3364 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3365 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3368 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3369 value
, indir_index
, "");
3370 build_store_values_extended(&ctx
->ac
, ctx
->locals
+ idx
+ chan
,
3373 temp_ptr
= ctx
->locals
[idx
+ chan
+ const_index
* 4];
3375 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3379 case nir_var_shared
: {
3380 int writemask
= instr
->const_index
[0];
3381 LLVMValueRef address
= build_gep_for_deref(ctx
,
3382 instr
->variables
[0]);
3383 LLVMValueRef val
= get_src(ctx
, instr
->src
[0]);
3384 unsigned components
=
3385 glsl_get_vector_elements(
3386 nir_deref_tail(&instr
->variables
[0]->deref
)->type
);
3387 if (writemask
== (1 << components
) - 1) {
3388 val
= LLVMBuildBitCast(
3389 ctx
->ac
.builder
, val
,
3390 LLVMGetElementType(LLVMTypeOf(address
)), "");
3391 LLVMBuildStore(ctx
->ac
.builder
, val
, address
);
3393 for (unsigned chan
= 0; chan
< 4; chan
++) {
3394 if (!(writemask
& (1 << chan
)))
3397 LLVMBuildStructGEP(ctx
->ac
.builder
,
3399 LLVMValueRef src
= ac_llvm_extract_elem(&ctx
->ac
, val
,
3401 src
= LLVMBuildBitCast(
3402 ctx
->ac
.builder
, src
,
3403 LLVMGetElementType(LLVMTypeOf(ptr
)), "");
3404 LLVMBuildStore(ctx
->ac
.builder
, src
, ptr
);
3414 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
3417 case GLSL_SAMPLER_DIM_BUF
:
3419 case GLSL_SAMPLER_DIM_1D
:
3420 return array
? 2 : 1;
3421 case GLSL_SAMPLER_DIM_2D
:
3422 return array
? 3 : 2;
3423 case GLSL_SAMPLER_DIM_MS
:
3424 return array
? 4 : 3;
3425 case GLSL_SAMPLER_DIM_3D
:
3426 case GLSL_SAMPLER_DIM_CUBE
:
3428 case GLSL_SAMPLER_DIM_RECT
:
3429 case GLSL_SAMPLER_DIM_SUBPASS
:
3431 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
3441 /* Adjust the sample index according to FMASK.
3443 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3444 * which is the identity mapping. Each nibble says which physical sample
3445 * should be fetched to get that sample.
3447 * For example, 0x11111100 means there are only 2 samples stored and
3448 * the second sample covers 3/4 of the pixel. When reading samples 0
3449 * and 1, return physical sample 0 (determined by the first two 0s
3450 * in FMASK), otherwise return physical sample 1.
3452 * The sample index should be adjusted as follows:
3453 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3455 static LLVMValueRef
adjust_sample_index_using_fmask(struct ac_llvm_context
*ctx
,
3456 LLVMValueRef coord_x
, LLVMValueRef coord_y
,
3457 LLVMValueRef coord_z
,
3458 LLVMValueRef sample_index
,
3459 LLVMValueRef fmask_desc_ptr
)
3461 LLVMValueRef fmask_load_address
[4];
3464 fmask_load_address
[0] = coord_x
;
3465 fmask_load_address
[1] = coord_y
;
3467 fmask_load_address
[2] = coord_z
;
3468 fmask_load_address
[3] = LLVMGetUndef(ctx
->i32
);
3471 struct ac_image_args args
= {0};
3473 args
.opcode
= ac_image_load
;
3474 args
.da
= coord_z
? true : false;
3475 args
.resource
= fmask_desc_ptr
;
3477 args
.addr
= ac_build_gather_values(ctx
, fmask_load_address
, coord_z
? 4 : 2);
3479 res
= ac_build_image_opcode(ctx
, &args
);
3481 res
= ac_to_integer(ctx
, res
);
3482 LLVMValueRef four
= LLVMConstInt(ctx
->i32
, 4, false);
3483 LLVMValueRef F
= LLVMConstInt(ctx
->i32
, 0xf, false);
3485 LLVMValueRef fmask
= LLVMBuildExtractElement(ctx
->builder
,
3489 LLVMValueRef sample_index4
=
3490 LLVMBuildMul(ctx
->builder
, sample_index
, four
, "");
3491 LLVMValueRef shifted_fmask
=
3492 LLVMBuildLShr(ctx
->builder
, fmask
, sample_index4
, "");
3493 LLVMValueRef final_sample
=
3494 LLVMBuildAnd(ctx
->builder
, shifted_fmask
, F
, "");
3496 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3497 * resource descriptor is 0 (invalid),
3499 LLVMValueRef fmask_desc
=
3500 LLVMBuildBitCast(ctx
->builder
, fmask_desc_ptr
,
3503 LLVMValueRef fmask_word1
=
3504 LLVMBuildExtractElement(ctx
->builder
, fmask_desc
,
3507 LLVMValueRef word1_is_nonzero
=
3508 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
,
3509 fmask_word1
, ctx
->i32_0
, "");
3511 /* Replace the MSAA sample index. */
3513 LLVMBuildSelect(ctx
->builder
, word1_is_nonzero
,
3514 final_sample
, sample_index
, "");
3515 return sample_index
;
3518 static LLVMValueRef
get_image_coords(struct ac_nir_context
*ctx
,
3519 const nir_intrinsic_instr
*instr
)
3521 const struct glsl_type
*type
= glsl_without_array(instr
->variables
[0]->var
->type
);
3523 LLVMValueRef src0
= get_src(ctx
, instr
->src
[0]);
3524 LLVMValueRef coords
[4];
3525 LLVMValueRef masks
[] = {
3526 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
3527 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
3530 LLVMValueRef sample_index
= ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[1]), 0);
3533 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3534 bool is_array
= glsl_sampler_type_is_array(type
);
3535 bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3536 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3537 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
||
3538 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3539 bool gfx9_1d
= ctx
->ac
.chip_class
>= GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
3540 count
= image_type_to_components_count(dim
, is_array
);
3543 LLVMValueRef fmask_load_address
[3];
3546 fmask_load_address
[0] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3547 fmask_load_address
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[1], "");
3549 fmask_load_address
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[2], "");
3551 fmask_load_address
[2] = NULL
;
3553 for (chan
= 0; chan
< 2; ++chan
)
3554 fmask_load_address
[chan
] =
3555 LLVMBuildAdd(ctx
->ac
.builder
, fmask_load_address
[chan
],
3556 LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3557 ctx
->ac
.i32
, ""), "");
3558 fmask_load_address
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3560 sample_index
= adjust_sample_index_using_fmask(&ctx
->ac
,
3561 fmask_load_address
[0],
3562 fmask_load_address
[1],
3563 fmask_load_address
[2],
3565 get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_FMASK
, NULL
, true, false));
3567 if (count
== 1 && !gfx9_1d
) {
3568 if (instr
->src
[0].ssa
->num_components
)
3569 res
= LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3576 for (chan
= 0; chan
< count
; ++chan
) {
3577 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, src0
, chan
);
3580 for (chan
= 0; chan
< 2; ++chan
)
3581 coords
[chan
] = LLVMBuildAdd(ctx
->ac
.builder
, coords
[chan
], LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3582 ctx
->ac
.i32
, ""), "");
3583 coords
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3589 coords
[2] = coords
[1];
3590 coords
[1] = ctx
->ac
.i32_0
;
3592 coords
[1] = ctx
->ac
.i32_0
;
3597 coords
[count
] = sample_index
;
3602 coords
[3] = LLVMGetUndef(ctx
->ac
.i32
);
3605 res
= ac_build_gather_values(&ctx
->ac
, coords
, count
);
3610 static LLVMValueRef
visit_image_load(struct ac_nir_context
*ctx
,
3611 const nir_intrinsic_instr
*instr
)
3613 LLVMValueRef params
[7];
3615 char intrinsic_name
[64];
3616 const nir_variable
*var
= instr
->variables
[0]->var
;
3617 const struct glsl_type
*type
= var
->type
;
3619 if(instr
->variables
[0]->deref
.child
)
3620 type
= instr
->variables
[0]->deref
.child
->type
;
3622 type
= glsl_without_array(type
);
3623 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3624 params
[0] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, false);
3625 params
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3626 ctx
->ac
.i32_0
, ""); /* vindex */
3627 params
[2] = ctx
->ac
.i32_0
; /* voffset */
3628 params
[3] = ctx
->ac
.i1false
; /* glc */
3629 params
[4] = ctx
->ac
.i1false
; /* slc */
3630 res
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.load.format.v4f32", ctx
->ac
.v4f32
,
3633 res
= trim_vector(&ctx
->ac
, res
, instr
->dest
.ssa
.num_components
);
3634 res
= ac_to_integer(&ctx
->ac
, res
);
3636 bool is_da
= glsl_sampler_type_is_array(type
) ||
3637 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
||
3638 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_3D
||
3639 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_SUBPASS
||
3640 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_SUBPASS_MS
;
3641 LLVMValueRef da
= is_da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3642 LLVMValueRef glc
= ctx
->ac
.i1false
;
3643 LLVMValueRef slc
= ctx
->ac
.i1false
;
3645 params
[0] = get_image_coords(ctx
, instr
);
3646 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3647 params
[2] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3648 if (HAVE_LLVM
<= 0x0309) {
3649 params
[3] = ctx
->ac
.i1false
; /* r128 */
3654 LLVMValueRef lwe
= ctx
->ac
.i1false
;
3661 ac_get_image_intr_name("llvm.amdgcn.image.load",
3662 ctx
->ac
.v4f32
, /* vdata */
3663 LLVMTypeOf(params
[0]), /* coords */
3664 LLVMTypeOf(params
[1]), /* rsrc */
3665 intrinsic_name
, sizeof(intrinsic_name
));
3667 res
= ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.v4f32
,
3668 params
, 7, AC_FUNC_ATTR_READONLY
);
3670 return ac_to_integer(&ctx
->ac
, res
);
3673 static void visit_image_store(struct ac_nir_context
*ctx
,
3674 nir_intrinsic_instr
*instr
)
3676 LLVMValueRef params
[8];
3677 char intrinsic_name
[64];
3678 const nir_variable
*var
= instr
->variables
[0]->var
;
3679 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3680 LLVMValueRef glc
= ctx
->ac
.i1false
;
3681 bool force_glc
= ctx
->ac
.chip_class
== SI
;
3683 glc
= ctx
->ac
.i1true
;
3685 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3686 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2])); /* data */
3687 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, true);
3688 params
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3689 ctx
->ac
.i32_0
, ""); /* vindex */
3690 params
[3] = ctx
->ac
.i32_0
; /* voffset */
3691 params
[4] = glc
; /* glc */
3692 params
[5] = ctx
->ac
.i1false
; /* slc */
3693 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.store.format.v4f32", ctx
->ac
.voidt
,
3696 bool is_da
= glsl_sampler_type_is_array(type
) ||
3697 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
||
3698 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_3D
;
3699 LLVMValueRef da
= is_da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3700 LLVMValueRef slc
= ctx
->ac
.i1false
;
3702 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2]));
3703 params
[1] = get_image_coords(ctx
, instr
); /* coords */
3704 params
[2] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, true);
3705 params
[3] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3706 if (HAVE_LLVM
<= 0x0309) {
3707 params
[4] = ctx
->ac
.i1false
; /* r128 */
3712 LLVMValueRef lwe
= ctx
->ac
.i1false
;
3719 ac_get_image_intr_name("llvm.amdgcn.image.store",
3720 LLVMTypeOf(params
[0]), /* vdata */
3721 LLVMTypeOf(params
[1]), /* coords */
3722 LLVMTypeOf(params
[2]), /* rsrc */
3723 intrinsic_name
, sizeof(intrinsic_name
));
3725 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.voidt
,
3731 static LLVMValueRef
visit_image_atomic(struct ac_nir_context
*ctx
,
3732 const nir_intrinsic_instr
*instr
)
3734 LLVMValueRef params
[7];
3735 int param_count
= 0;
3736 const nir_variable
*var
= instr
->variables
[0]->var
;
3738 const char *atomic_name
;
3739 char intrinsic_name
[41];
3740 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3741 MAYBE_UNUSED
int length
;
3743 bool is_unsigned
= glsl_get_sampler_result_type(type
) == GLSL_TYPE_UINT
;
3745 switch (instr
->intrinsic
) {
3746 case nir_intrinsic_image_atomic_add
:
3747 atomic_name
= "add";
3749 case nir_intrinsic_image_atomic_min
:
3750 atomic_name
= is_unsigned
? "umin" : "smin";
3752 case nir_intrinsic_image_atomic_max
:
3753 atomic_name
= is_unsigned
? "umax" : "smax";
3755 case nir_intrinsic_image_atomic_and
:
3756 atomic_name
= "and";
3758 case nir_intrinsic_image_atomic_or
:
3761 case nir_intrinsic_image_atomic_xor
:
3762 atomic_name
= "xor";
3764 case nir_intrinsic_image_atomic_exchange
:
3765 atomic_name
= "swap";
3767 case nir_intrinsic_image_atomic_comp_swap
:
3768 atomic_name
= "cmpswap";
3774 if (instr
->intrinsic
== nir_intrinsic_image_atomic_comp_swap
)
3775 params
[param_count
++] = get_src(ctx
, instr
->src
[3]);
3776 params
[param_count
++] = get_src(ctx
, instr
->src
[2]);
3778 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3779 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
,
3781 params
[param_count
++] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3782 ctx
->ac
.i32_0
, ""); /* vindex */
3783 params
[param_count
++] = ctx
->ac
.i32_0
; /* voffset */
3784 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3786 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3787 "llvm.amdgcn.buffer.atomic.%s", atomic_name
);
3789 char coords_type
[8];
3791 bool da
= glsl_sampler_type_is_array(type
) ||
3792 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
;
3794 LLVMValueRef coords
= params
[param_count
++] = get_image_coords(ctx
, instr
);
3795 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
,
3797 params
[param_count
++] = ctx
->ac
.i1false
; /* r128 */
3798 params
[param_count
++] = da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
; /* da */
3799 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3801 build_int_type_name(LLVMTypeOf(coords
),
3802 coords_type
, sizeof(coords_type
));
3804 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3805 "llvm.amdgcn.image.atomic.%s.%s", atomic_name
, coords_type
);
3808 assert(length
< sizeof(intrinsic_name
));
3809 return ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.i32
, params
, param_count
, 0);
3812 static LLVMValueRef
visit_image_size(struct ac_nir_context
*ctx
,
3813 const nir_intrinsic_instr
*instr
)
3816 const nir_variable
*var
= instr
->variables
[0]->var
;
3817 const struct glsl_type
*type
= instr
->variables
[0]->var
->type
;
3818 bool da
= glsl_sampler_type_is_array(var
->type
) ||
3819 glsl_get_sampler_dim(var
->type
) == GLSL_SAMPLER_DIM_CUBE
||
3820 glsl_get_sampler_dim(var
->type
) == GLSL_SAMPLER_DIM_3D
;
3821 if(instr
->variables
[0]->deref
.child
)
3822 type
= instr
->variables
[0]->deref
.child
->type
;
3824 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
)
3825 return get_buffer_size(ctx
,
3826 get_sampler_desc(ctx
, instr
->variables
[0],
3827 AC_DESC_BUFFER
, NULL
, true, false), true);
3829 struct ac_image_args args
= { 0 };
3833 args
.resource
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3834 args
.opcode
= ac_image_get_resinfo
;
3835 args
.addr
= ctx
->ac
.i32_0
;
3837 res
= ac_build_image_opcode(&ctx
->ac
, &args
);
3839 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
3841 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
3842 glsl_sampler_type_is_array(type
)) {
3843 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
3844 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3845 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
3846 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, z
, two
, "");
3848 if (ctx
->ac
.chip_class
>= GFX9
&&
3849 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
3850 glsl_sampler_type_is_array(type
)) {
3851 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3852 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, layers
,
3859 #define NOOP_WAITCNT 0xf7f
3860 #define LGKM_CNT 0x07f
3861 #define VM_CNT 0xf70
3863 static void emit_membar(struct nir_to_llvm_context
*ctx
,
3864 const nir_intrinsic_instr
*instr
)
3866 unsigned waitcnt
= NOOP_WAITCNT
;
3868 switch (instr
->intrinsic
) {
3869 case nir_intrinsic_memory_barrier
:
3870 case nir_intrinsic_group_memory_barrier
:
3871 waitcnt
&= VM_CNT
& LGKM_CNT
;
3873 case nir_intrinsic_memory_barrier_atomic_counter
:
3874 case nir_intrinsic_memory_barrier_buffer
:
3875 case nir_intrinsic_memory_barrier_image
:
3878 case nir_intrinsic_memory_barrier_shared
:
3879 waitcnt
&= LGKM_CNT
;
3884 if (waitcnt
!= NOOP_WAITCNT
)
3885 ac_build_waitcnt(&ctx
->ac
, waitcnt
);
3888 static void emit_barrier(struct ac_llvm_context
*ac
, gl_shader_stage stage
)
3890 /* SI only (thanks to a hw bug workaround):
3891 * The real barrier instruction isn’t needed, because an entire patch
3892 * always fits into a single wave.
3894 if (ac
->chip_class
== SI
&& stage
== MESA_SHADER_TESS_CTRL
) {
3895 ac_build_waitcnt(ac
, LGKM_CNT
& VM_CNT
);
3898 ac_build_intrinsic(ac
, "llvm.amdgcn.s.barrier",
3899 ac
->voidt
, NULL
, 0, AC_FUNC_ATTR_CONVERGENT
);
3902 static void emit_discard(struct ac_nir_context
*ctx
,
3903 const nir_intrinsic_instr
*instr
)
3907 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3908 cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3909 get_src(ctx
, instr
->src
[0]),
3912 assert(instr
->intrinsic
== nir_intrinsic_discard
);
3913 cond
= LLVMConstInt(ctx
->ac
.i1
, false, 0);
3916 ac_build_kill_if_false(&ctx
->ac
, cond
);
3920 visit_load_helper_invocation(struct ac_nir_context
*ctx
)
3922 LLVMValueRef result
= ac_build_intrinsic(&ctx
->ac
,
3923 "llvm.amdgcn.ps.live",
3924 ctx
->ac
.i1
, NULL
, 0,
3925 AC_FUNC_ATTR_READNONE
);
3926 result
= LLVMBuildNot(ctx
->ac
.builder
, result
, "");
3927 return LLVMBuildSExt(ctx
->ac
.builder
, result
, ctx
->ac
.i32
, "");
3931 visit_load_local_invocation_index(struct nir_to_llvm_context
*ctx
)
3933 LLVMValueRef result
;
3934 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
->ac
);
3935 result
= LLVMBuildAnd(ctx
->builder
, ctx
->tg_size
,
3936 LLVMConstInt(ctx
->ac
.i32
, 0xfc0, false), "");
3938 return LLVMBuildAdd(ctx
->builder
, result
, thread_id
, "");
3941 static LLVMValueRef
visit_var_atomic(struct nir_to_llvm_context
*ctx
,
3942 const nir_intrinsic_instr
*instr
)
3944 LLVMValueRef ptr
, result
;
3945 LLVMValueRef src
= get_src(ctx
->nir
, instr
->src
[0]);
3946 ptr
= build_gep_for_deref(ctx
->nir
, instr
->variables
[0]);
3948 if (instr
->intrinsic
== nir_intrinsic_var_atomic_comp_swap
) {
3949 LLVMValueRef src1
= get_src(ctx
->nir
, instr
->src
[1]);
3950 result
= LLVMBuildAtomicCmpXchg(ctx
->builder
,
3952 LLVMAtomicOrderingSequentiallyConsistent
,
3953 LLVMAtomicOrderingSequentiallyConsistent
,
3956 LLVMAtomicRMWBinOp op
;
3957 switch (instr
->intrinsic
) {
3958 case nir_intrinsic_var_atomic_add
:
3959 op
= LLVMAtomicRMWBinOpAdd
;
3961 case nir_intrinsic_var_atomic_umin
:
3962 op
= LLVMAtomicRMWBinOpUMin
;
3964 case nir_intrinsic_var_atomic_umax
:
3965 op
= LLVMAtomicRMWBinOpUMax
;
3967 case nir_intrinsic_var_atomic_imin
:
3968 op
= LLVMAtomicRMWBinOpMin
;
3970 case nir_intrinsic_var_atomic_imax
:
3971 op
= LLVMAtomicRMWBinOpMax
;
3973 case nir_intrinsic_var_atomic_and
:
3974 op
= LLVMAtomicRMWBinOpAnd
;
3976 case nir_intrinsic_var_atomic_or
:
3977 op
= LLVMAtomicRMWBinOpOr
;
3979 case nir_intrinsic_var_atomic_xor
:
3980 op
= LLVMAtomicRMWBinOpXor
;
3982 case nir_intrinsic_var_atomic_exchange
:
3983 op
= LLVMAtomicRMWBinOpXchg
;
3989 result
= LLVMBuildAtomicRMW(ctx
->builder
, op
, ptr
, ac_to_integer(&ctx
->ac
, src
),
3990 LLVMAtomicOrderingSequentiallyConsistent
,
3996 #define INTERP_CENTER 0
3997 #define INTERP_CENTROID 1
3998 #define INTERP_SAMPLE 2
4000 static LLVMValueRef
lookup_interp_param(struct nir_to_llvm_context
*ctx
,
4001 enum glsl_interp_mode interp
, unsigned location
)
4004 case INTERP_MODE_FLAT
:
4007 case INTERP_MODE_SMOOTH
:
4008 case INTERP_MODE_NONE
:
4009 if (location
== INTERP_CENTER
)
4010 return ctx
->persp_center
;
4011 else if (location
== INTERP_CENTROID
)
4012 return ctx
->persp_centroid
;
4013 else if (location
== INTERP_SAMPLE
)
4014 return ctx
->persp_sample
;
4016 case INTERP_MODE_NOPERSPECTIVE
:
4017 if (location
== INTERP_CENTER
)
4018 return ctx
->linear_center
;
4019 else if (location
== INTERP_CENTROID
)
4020 return ctx
->linear_centroid
;
4021 else if (location
== INTERP_SAMPLE
)
4022 return ctx
->linear_sample
;
4028 static LLVMValueRef
load_sample_position(struct nir_to_llvm_context
*ctx
,
4029 LLVMValueRef sample_id
)
4031 LLVMValueRef result
;
4032 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false));
4034 ptr
= LLVMBuildBitCast(ctx
->builder
, ptr
,
4035 const_array(ctx
->ac
.v2f32
, 64), "");
4037 sample_id
= LLVMBuildAdd(ctx
->builder
, sample_id
, ctx
->sample_pos_offset
, "");
4038 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
4043 static LLVMValueRef
load_sample_pos(struct ac_nir_context
*ctx
)
4045 LLVMValueRef values
[2];
4047 values
[0] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[0]);
4048 values
[1] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[1]);
4049 return ac_build_gather_values(&ctx
->ac
, values
, 2);
4052 static LLVMValueRef
visit_interp(struct nir_to_llvm_context
*ctx
,
4053 const nir_intrinsic_instr
*instr
)
4055 LLVMValueRef result
[4];
4056 LLVMValueRef interp_param
, attr_number
;
4059 LLVMValueRef src_c0
= NULL
;
4060 LLVMValueRef src_c1
= NULL
;
4061 LLVMValueRef src0
= NULL
;
4062 int input_index
= instr
->variables
[0]->var
->data
.location
- VARYING_SLOT_VAR0
;
4063 switch (instr
->intrinsic
) {
4064 case nir_intrinsic_interp_var_at_centroid
:
4065 location
= INTERP_CENTROID
;
4067 case nir_intrinsic_interp_var_at_sample
:
4068 case nir_intrinsic_interp_var_at_offset
:
4069 location
= INTERP_CENTER
;
4070 src0
= get_src(ctx
->nir
, instr
->src
[0]);
4076 if (instr
->intrinsic
== nir_intrinsic_interp_var_at_offset
) {
4077 src_c0
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->ac
.i32_0
, ""));
4078 src_c1
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->ac
.i32_1
, ""));
4079 } else if (instr
->intrinsic
== nir_intrinsic_interp_var_at_sample
) {
4080 LLVMValueRef sample_position
;
4081 LLVMValueRef halfval
= LLVMConstReal(ctx
->ac
.f32
, 0.5f
);
4083 /* fetch sample ID */
4084 sample_position
= load_sample_position(ctx
, src0
);
4086 src_c0
= LLVMBuildExtractElement(ctx
->builder
, sample_position
, ctx
->ac
.i32_0
, "");
4087 src_c0
= LLVMBuildFSub(ctx
->builder
, src_c0
, halfval
, "");
4088 src_c1
= LLVMBuildExtractElement(ctx
->builder
, sample_position
, ctx
->ac
.i32_1
, "");
4089 src_c1
= LLVMBuildFSub(ctx
->builder
, src_c1
, halfval
, "");
4091 interp_param
= lookup_interp_param(ctx
, instr
->variables
[0]->var
->data
.interpolation
, location
);
4092 attr_number
= LLVMConstInt(ctx
->ac
.i32
, input_index
, false);
4094 if (location
== INTERP_CENTER
) {
4095 LLVMValueRef ij_out
[2];
4096 LLVMValueRef ddxy_out
= emit_ddxy_interp(ctx
->nir
, interp_param
);
4099 * take the I then J parameters, and the DDX/Y for it, and
4100 * calculate the IJ inputs for the interpolator.
4101 * temp1 = ddx * offset/sample.x + I;
4102 * interp_param.I = ddy * offset/sample.y + temp1;
4103 * temp1 = ddx * offset/sample.x + J;
4104 * interp_param.J = ddy * offset/sample.y + temp1;
4106 for (unsigned i
= 0; i
< 2; i
++) {
4107 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->ac
.i32
, i
, false);
4108 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->ac
.i32
, i
+ 2, false);
4109 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->builder
,
4110 ddxy_out
, ix_ll
, "");
4111 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->builder
,
4112 ddxy_out
, iy_ll
, "");
4113 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->builder
,
4114 interp_param
, ix_ll
, "");
4115 LLVMValueRef temp1
, temp2
;
4117 interp_el
= LLVMBuildBitCast(ctx
->builder
, interp_el
,
4120 temp1
= LLVMBuildFMul(ctx
->builder
, ddx_el
, src_c0
, "");
4121 temp1
= LLVMBuildFAdd(ctx
->builder
, temp1
, interp_el
, "");
4123 temp2
= LLVMBuildFMul(ctx
->builder
, ddy_el
, src_c1
, "");
4124 temp2
= LLVMBuildFAdd(ctx
->builder
, temp2
, temp1
, "");
4126 ij_out
[i
] = LLVMBuildBitCast(ctx
->builder
,
4127 temp2
, ctx
->ac
.i32
, "");
4129 interp_param
= ac_build_gather_values(&ctx
->ac
, ij_out
, 2);
4133 for (chan
= 0; chan
< 4; chan
++) {
4134 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
4137 interp_param
= LLVMBuildBitCast(ctx
->builder
,
4138 interp_param
, ctx
->ac
.v2f32
, "");
4139 LLVMValueRef i
= LLVMBuildExtractElement(
4140 ctx
->builder
, interp_param
, ctx
->ac
.i32_0
, "");
4141 LLVMValueRef j
= LLVMBuildExtractElement(
4142 ctx
->builder
, interp_param
, ctx
->ac
.i32_1
, "");
4144 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
4145 llvm_chan
, attr_number
,
4146 ctx
->prim_mask
, i
, j
);
4148 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
4149 LLVMConstInt(ctx
->ac
.i32
, 2, false),
4150 llvm_chan
, attr_number
,
4154 return ac_build_varying_gather_values(&ctx
->ac
, result
, instr
->num_components
,
4155 instr
->variables
[0]->var
->data
.location_frac
);
4159 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
4161 LLVMValueRef gs_next_vertex
;
4162 LLVMValueRef can_emit
;
4164 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4166 assert(stream
== 0);
4168 /* Write vertex attribute values to GSVS ring */
4169 gs_next_vertex
= LLVMBuildLoad(ctx
->builder
,
4170 ctx
->gs_next_vertex
,
4173 /* If this thread has already emitted the declared maximum number of
4174 * vertices, kill it: excessive vertex emissions are not supposed to
4175 * have any effect, and GS threads have no externally observable
4176 * effects other than emitting vertices.
4178 can_emit
= LLVMBuildICmp(ctx
->builder
, LLVMIntULT
, gs_next_vertex
,
4179 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
4180 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
4182 /* loop num outputs */
4184 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
4185 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
4190 if (!(ctx
->output_mask
& (1ull << i
)))
4193 if (i
== VARYING_SLOT_CLIP_DIST0
) {
4194 /* pack clip and cull into a single set of slots */
4195 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
4199 for (unsigned j
= 0; j
< length
; j
++) {
4200 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
,
4202 LLVMValueRef voffset
= LLVMConstInt(ctx
->ac
.i32
, (slot
* 4 + j
) * ctx
->gs_max_out_vertices
, false);
4203 voffset
= LLVMBuildAdd(ctx
->builder
, voffset
, gs_next_vertex
, "");
4204 voffset
= LLVMBuildMul(ctx
->builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4206 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->ac
.i32
, "");
4208 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->gsvs_ring
,
4210 voffset
, ctx
->gs2vs_offset
, 0,
4216 gs_next_vertex
= LLVMBuildAdd(ctx
->builder
, gs_next_vertex
,
4218 LLVMBuildStore(ctx
->builder
, gs_next_vertex
, ctx
->gs_next_vertex
);
4220 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
4224 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
4226 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4227 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
4231 load_tess_coord(struct ac_shader_abi
*abi
, LLVMTypeRef type
,
4232 unsigned num_components
)
4234 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4236 LLVMValueRef coord
[4] = {
4243 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
4244 coord
[2] = LLVMBuildFSub(ctx
->builder
, ctx
->ac
.f32_1
,
4245 LLVMBuildFAdd(ctx
->builder
, coord
[0], coord
[1], ""), "");
4247 LLVMValueRef result
= ac_build_gather_values(&ctx
->ac
, coord
, num_components
);
4248 return LLVMBuildBitCast(ctx
->builder
, result
, type
, "");
4252 load_patch_vertices_in(struct ac_shader_abi
*abi
)
4254 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4255 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
4258 static void visit_intrinsic(struct ac_nir_context
*ctx
,
4259 nir_intrinsic_instr
*instr
)
4261 LLVMValueRef result
= NULL
;
4263 switch (instr
->intrinsic
) {
4264 case nir_intrinsic_ballot
:
4265 result
= ac_build_ballot(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4267 case nir_intrinsic_read_invocation
:
4268 case nir_intrinsic_read_first_invocation
: {
4269 LLVMValueRef args
[2];
4272 args
[0] = get_src(ctx
, instr
->src
[0]);
4275 const char *intr_name
;
4276 if (instr
->intrinsic
== nir_intrinsic_read_invocation
) {
4278 intr_name
= "llvm.amdgcn.readlane";
4281 args
[1] = get_src(ctx
, instr
->src
[1]);
4284 intr_name
= "llvm.amdgcn.readfirstlane";
4287 /* We currently have no other way to prevent LLVM from lifting the icmp
4288 * calls to a dominating basic block.
4290 ac_build_optimization_barrier(&ctx
->ac
, &args
[0]);
4292 result
= ac_build_intrinsic(&ctx
->ac
, intr_name
,
4293 ctx
->ac
.i32
, args
, num_args
,
4294 AC_FUNC_ATTR_READNONE
|
4295 AC_FUNC_ATTR_CONVERGENT
);
4298 case nir_intrinsic_load_subgroup_invocation
:
4299 result
= ac_get_thread_id(&ctx
->ac
);
4301 case nir_intrinsic_load_work_group_id
: {
4302 LLVMValueRef values
[3];
4304 for (int i
= 0; i
< 3; i
++) {
4305 values
[i
] = ctx
->nctx
->workgroup_ids
[i
] ?
4306 ctx
->nctx
->workgroup_ids
[i
] : ctx
->ac
.i32_0
;
4309 result
= ac_build_gather_values(&ctx
->ac
, values
, 3);
4312 case nir_intrinsic_load_base_vertex
: {
4313 result
= ctx
->abi
->base_vertex
;
4316 case nir_intrinsic_load_vertex_id_zero_base
: {
4317 result
= ctx
->abi
->vertex_id
;
4320 case nir_intrinsic_load_local_invocation_id
: {
4321 result
= ctx
->nctx
->local_invocation_ids
;
4324 case nir_intrinsic_load_base_instance
:
4325 result
= ctx
->abi
->start_instance
;
4327 case nir_intrinsic_load_draw_id
:
4328 result
= ctx
->abi
->draw_id
;
4330 case nir_intrinsic_load_view_index
:
4331 result
= ctx
->nctx
->view_index
? ctx
->nctx
->view_index
: ctx
->ac
.i32_0
;
4333 case nir_intrinsic_load_invocation_id
:
4334 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
4335 result
= unpack_param(&ctx
->ac
, ctx
->abi
->tcs_rel_ids
, 8, 5);
4337 result
= ctx
->abi
->gs_invocation_id
;
4339 case nir_intrinsic_load_primitive_id
:
4340 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
4341 result
= ctx
->abi
->gs_prim_id
;
4342 } else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
4343 result
= ctx
->abi
->tcs_patch_id
;
4344 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4345 result
= ctx
->abi
->tes_patch_id
;
4347 fprintf(stderr
, "Unknown primitive id intrinsic: %d", ctx
->stage
);
4349 case nir_intrinsic_load_sample_id
:
4350 result
= unpack_param(&ctx
->ac
, ctx
->abi
->ancillary
, 8, 4);
4352 case nir_intrinsic_load_sample_pos
:
4353 result
= load_sample_pos(ctx
);
4355 case nir_intrinsic_load_sample_mask_in
:
4356 result
= ctx
->abi
->sample_coverage
;
4358 case nir_intrinsic_load_frag_coord
: {
4359 LLVMValueRef values
[4] = {
4360 ctx
->abi
->frag_pos
[0],
4361 ctx
->abi
->frag_pos
[1],
4362 ctx
->abi
->frag_pos
[2],
4363 ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, ctx
->abi
->frag_pos
[3])
4365 result
= ac_build_gather_values(&ctx
->ac
, values
, 4);
4368 case nir_intrinsic_load_front_face
:
4369 result
= ctx
->abi
->front_face
;
4371 case nir_intrinsic_load_helper_invocation
:
4372 result
= visit_load_helper_invocation(ctx
);
4374 case nir_intrinsic_load_instance_id
:
4375 result
= ctx
->abi
->instance_id
;
4377 case nir_intrinsic_load_num_work_groups
:
4378 result
= ctx
->nctx
->num_work_groups
;
4380 case nir_intrinsic_load_local_invocation_index
:
4381 result
= visit_load_local_invocation_index(ctx
->nctx
);
4383 case nir_intrinsic_load_push_constant
:
4384 result
= visit_load_push_constant(ctx
->nctx
, instr
);
4386 case nir_intrinsic_vulkan_resource_index
:
4387 result
= visit_vulkan_resource_index(ctx
->nctx
, instr
);
4389 case nir_intrinsic_vulkan_resource_reindex
:
4390 result
= visit_vulkan_resource_reindex(ctx
->nctx
, instr
);
4392 case nir_intrinsic_store_ssbo
:
4393 visit_store_ssbo(ctx
, instr
);
4395 case nir_intrinsic_load_ssbo
:
4396 result
= visit_load_buffer(ctx
, instr
);
4398 case nir_intrinsic_ssbo_atomic_add
:
4399 case nir_intrinsic_ssbo_atomic_imin
:
4400 case nir_intrinsic_ssbo_atomic_umin
:
4401 case nir_intrinsic_ssbo_atomic_imax
:
4402 case nir_intrinsic_ssbo_atomic_umax
:
4403 case nir_intrinsic_ssbo_atomic_and
:
4404 case nir_intrinsic_ssbo_atomic_or
:
4405 case nir_intrinsic_ssbo_atomic_xor
:
4406 case nir_intrinsic_ssbo_atomic_exchange
:
4407 case nir_intrinsic_ssbo_atomic_comp_swap
:
4408 result
= visit_atomic_ssbo(ctx
, instr
);
4410 case nir_intrinsic_load_ubo
:
4411 result
= visit_load_ubo_buffer(ctx
, instr
);
4413 case nir_intrinsic_get_buffer_size
:
4414 result
= visit_get_buffer_size(ctx
, instr
);
4416 case nir_intrinsic_load_var
:
4417 result
= visit_load_var(ctx
, instr
);
4419 case nir_intrinsic_store_var
:
4420 visit_store_var(ctx
, instr
);
4422 case nir_intrinsic_image_load
:
4423 result
= visit_image_load(ctx
, instr
);
4425 case nir_intrinsic_image_store
:
4426 visit_image_store(ctx
, instr
);
4428 case nir_intrinsic_image_atomic_add
:
4429 case nir_intrinsic_image_atomic_min
:
4430 case nir_intrinsic_image_atomic_max
:
4431 case nir_intrinsic_image_atomic_and
:
4432 case nir_intrinsic_image_atomic_or
:
4433 case nir_intrinsic_image_atomic_xor
:
4434 case nir_intrinsic_image_atomic_exchange
:
4435 case nir_intrinsic_image_atomic_comp_swap
:
4436 result
= visit_image_atomic(ctx
, instr
);
4438 case nir_intrinsic_image_size
:
4439 result
= visit_image_size(ctx
, instr
);
4441 case nir_intrinsic_discard
:
4442 case nir_intrinsic_discard_if
:
4443 emit_discard(ctx
, instr
);
4445 case nir_intrinsic_memory_barrier
:
4446 case nir_intrinsic_group_memory_barrier
:
4447 case nir_intrinsic_memory_barrier_atomic_counter
:
4448 case nir_intrinsic_memory_barrier_buffer
:
4449 case nir_intrinsic_memory_barrier_image
:
4450 case nir_intrinsic_memory_barrier_shared
:
4451 emit_membar(ctx
->nctx
, instr
);
4453 case nir_intrinsic_barrier
:
4454 emit_barrier(&ctx
->ac
, ctx
->stage
);
4456 case nir_intrinsic_var_atomic_add
:
4457 case nir_intrinsic_var_atomic_imin
:
4458 case nir_intrinsic_var_atomic_umin
:
4459 case nir_intrinsic_var_atomic_imax
:
4460 case nir_intrinsic_var_atomic_umax
:
4461 case nir_intrinsic_var_atomic_and
:
4462 case nir_intrinsic_var_atomic_or
:
4463 case nir_intrinsic_var_atomic_xor
:
4464 case nir_intrinsic_var_atomic_exchange
:
4465 case nir_intrinsic_var_atomic_comp_swap
:
4466 result
= visit_var_atomic(ctx
->nctx
, instr
);
4468 case nir_intrinsic_interp_var_at_centroid
:
4469 case nir_intrinsic_interp_var_at_sample
:
4470 case nir_intrinsic_interp_var_at_offset
:
4471 result
= visit_interp(ctx
->nctx
, instr
);
4473 case nir_intrinsic_emit_vertex
:
4474 ctx
->abi
->emit_vertex(ctx
->abi
, nir_intrinsic_stream_id(instr
), ctx
->outputs
);
4476 case nir_intrinsic_end_primitive
:
4477 ctx
->abi
->emit_primitive(ctx
->abi
, nir_intrinsic_stream_id(instr
));
4479 case nir_intrinsic_load_tess_coord
: {
4480 LLVMTypeRef type
= ctx
->nctx
?
4481 get_def_type(ctx
->nctx
->nir
, &instr
->dest
.ssa
) :
4483 result
= ctx
->abi
->load_tess_coord(ctx
->abi
, type
, instr
->num_components
);
4486 case nir_intrinsic_load_tess_level_outer
:
4487 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_OUTER
);
4489 case nir_intrinsic_load_tess_level_inner
:
4490 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_INNER
);
4492 case nir_intrinsic_load_patch_vertices_in
:
4493 result
= ctx
->abi
->load_patch_vertices_in(ctx
->abi
);
4495 case nir_intrinsic_vote_all
: {
4496 LLVMValueRef tmp
= ac_build_vote_all(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4497 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4500 case nir_intrinsic_vote_any
: {
4501 LLVMValueRef tmp
= ac_build_vote_any(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4502 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4505 case nir_intrinsic_vote_eq
: {
4506 LLVMValueRef tmp
= ac_build_vote_eq(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4507 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4511 fprintf(stderr
, "Unknown intrinsic: ");
4512 nir_print_instr(&instr
->instr
, stderr
);
4513 fprintf(stderr
, "\n");
4517 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4521 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
4522 LLVMValueRef buffer_ptr
, bool write
)
4524 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4526 if (write
&& ctx
->stage
== MESA_SHADER_FRAGMENT
)
4527 ctx
->shader_info
->fs
.writes_memory
= true;
4529 return LLVMBuildLoad(ctx
->builder
, buffer_ptr
, "");
4532 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
4534 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4536 return LLVMBuildLoad(ctx
->builder
, buffer_ptr
, "");
4539 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
4540 unsigned descriptor_set
,
4541 unsigned base_index
,
4542 unsigned constant_index
,
4544 enum ac_descriptor_type desc_type
,
4545 bool image
, bool write
)
4547 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4548 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
4549 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
4550 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
4551 unsigned offset
= binding
->offset
;
4552 unsigned stride
= binding
->size
;
4554 LLVMBuilderRef builder
= ctx
->builder
;
4557 assert(base_index
< layout
->binding_count
);
4559 if (write
&& ctx
->stage
== MESA_SHADER_FRAGMENT
)
4560 ctx
->shader_info
->fs
.writes_memory
= true;
4562 switch (desc_type
) {
4564 type
= ctx
->ac
.v8i32
;
4568 type
= ctx
->ac
.v8i32
;
4572 case AC_DESC_SAMPLER
:
4573 type
= ctx
->ac
.v4i32
;
4574 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
4579 case AC_DESC_BUFFER
:
4580 type
= ctx
->ac
.v4i32
;
4584 unreachable("invalid desc_type\n");
4587 offset
+= constant_index
* stride
;
4589 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
4590 (!index
|| binding
->immutable_samplers_equal
)) {
4591 if (binding
->immutable_samplers_equal
)
4594 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
4596 LLVMValueRef constants
[] = {
4597 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
4598 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
4599 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
4600 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
4602 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
4605 assert(stride
% type_size
== 0);
4608 index
= ctx
->ac
.i32_0
;
4610 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
4612 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->ac
.i32
, offset
, 0));
4613 list
= LLVMBuildPointerCast(builder
, list
, const_array(type
, 0), "");
4615 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
4618 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
4619 const nir_deref_var
*deref
,
4620 enum ac_descriptor_type desc_type
,
4621 const nir_tex_instr
*tex_instr
,
4622 bool image
, bool write
)
4624 LLVMValueRef index
= NULL
;
4625 unsigned constant_index
= 0;
4626 unsigned descriptor_set
;
4627 unsigned base_index
;
4630 assert(tex_instr
&& !image
);
4632 base_index
= tex_instr
->sampler_index
;
4634 const nir_deref
*tail
= &deref
->deref
;
4635 while (tail
->child
) {
4636 const nir_deref_array
*child
= nir_deref_as_array(tail
->child
);
4637 unsigned array_size
= glsl_get_aoa_size(tail
->child
->type
);
4642 assert(child
->deref_array_type
!= nir_deref_array_type_wildcard
);
4644 if (child
->deref_array_type
== nir_deref_array_type_indirect
) {
4645 LLVMValueRef indirect
= get_src(ctx
, child
->indirect
);
4647 indirect
= LLVMBuildMul(ctx
->ac
.builder
, indirect
,
4648 LLVMConstInt(ctx
->ac
.i32
, array_size
, false), "");
4653 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
, indirect
, "");
4656 constant_index
+= child
->base_offset
* array_size
;
4658 tail
= &child
->deref
;
4660 descriptor_set
= deref
->var
->data
.descriptor_set
;
4661 base_index
= deref
->var
->data
.binding
;
4664 return ctx
->abi
->load_sampler_desc(ctx
->abi
,
4667 constant_index
, index
,
4668 desc_type
, image
, write
);
4671 static void set_tex_fetch_args(struct ac_llvm_context
*ctx
,
4672 struct ac_image_args
*args
,
4673 const nir_tex_instr
*instr
,
4675 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
4676 LLVMValueRef
*param
, unsigned count
,
4679 unsigned is_rect
= 0;
4680 bool da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
4682 if (op
== nir_texop_lod
)
4684 /* Pad to power of two vector */
4685 while (count
< util_next_power_of_two(count
))
4686 param
[count
++] = LLVMGetUndef(ctx
->i32
);
4689 args
->addr
= ac_build_gather_values(ctx
, param
, count
);
4691 args
->addr
= param
[0];
4693 args
->resource
= res_ptr
;
4694 args
->sampler
= samp_ptr
;
4696 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
&& op
== nir_texop_txf
) {
4697 args
->addr
= param
[0];
4701 args
->dmask
= dmask
;
4702 args
->unorm
= is_rect
;
4706 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4709 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4710 * filtering manually. The driver sets img7 to a mask clearing
4711 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4712 * s_and_b32 samp0, samp0, img7
4715 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4717 static LLVMValueRef
sici_fix_sampler_aniso(struct ac_nir_context
*ctx
,
4718 LLVMValueRef res
, LLVMValueRef samp
)
4720 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4721 LLVMValueRef img7
, samp0
;
4723 if (ctx
->ac
.chip_class
>= VI
)
4726 img7
= LLVMBuildExtractElement(builder
, res
,
4727 LLVMConstInt(ctx
->ac
.i32
, 7, 0), "");
4728 samp0
= LLVMBuildExtractElement(builder
, samp
,
4729 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4730 samp0
= LLVMBuildAnd(builder
, samp0
, img7
, "");
4731 return LLVMBuildInsertElement(builder
, samp
, samp0
,
4732 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4735 static void tex_fetch_ptrs(struct ac_nir_context
*ctx
,
4736 nir_tex_instr
*instr
,
4737 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
4738 LLVMValueRef
*fmask_ptr
)
4740 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4741 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_BUFFER
, instr
, false, false);
4743 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_IMAGE
, instr
, false, false);
4746 *samp_ptr
= get_sampler_desc(ctx
, instr
->sampler
, AC_DESC_SAMPLER
, instr
, false, false);
4748 *samp_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_SAMPLER
, instr
, false, false);
4749 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
)
4750 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
4752 if (fmask_ptr
&& !instr
->sampler
&& (instr
->op
== nir_texop_txf_ms
||
4753 instr
->op
== nir_texop_samples_identical
))
4754 *fmask_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_FMASK
, instr
, false, false);
4757 static LLVMValueRef
apply_round_slice(struct ac_llvm_context
*ctx
,
4760 coord
= ac_to_float(ctx
, coord
);
4761 coord
= ac_build_intrinsic(ctx
, "llvm.rint.f32", ctx
->f32
, &coord
, 1, 0);
4762 coord
= ac_to_integer(ctx
, coord
);
4766 static void visit_tex(struct ac_nir_context
*ctx
, nir_tex_instr
*instr
)
4768 LLVMValueRef result
= NULL
;
4769 struct ac_image_args args
= { 0 };
4770 unsigned dmask
= 0xf;
4771 LLVMValueRef address
[16];
4772 LLVMValueRef coords
[5];
4773 LLVMValueRef coord
= NULL
, lod
= NULL
, comparator
= NULL
;
4774 LLVMValueRef bias
= NULL
, offsets
= NULL
;
4775 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
, sample_index
= NULL
;
4776 LLVMValueRef ddx
= NULL
, ddy
= NULL
;
4777 LLVMValueRef derivs
[6];
4778 unsigned chan
, count
= 0;
4779 unsigned const_src
= 0, num_deriv_comp
= 0;
4780 bool lod_is_zero
= false;
4782 tex_fetch_ptrs(ctx
, instr
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4784 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4785 switch (instr
->src
[i
].src_type
) {
4786 case nir_tex_src_coord
:
4787 coord
= get_src(ctx
, instr
->src
[i
].src
);
4789 case nir_tex_src_projector
:
4791 case nir_tex_src_comparator
:
4792 comparator
= get_src(ctx
, instr
->src
[i
].src
);
4794 case nir_tex_src_offset
:
4795 offsets
= get_src(ctx
, instr
->src
[i
].src
);
4798 case nir_tex_src_bias
:
4799 bias
= get_src(ctx
, instr
->src
[i
].src
);
4801 case nir_tex_src_lod
: {
4802 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
4804 if (val
&& val
->i32
[0] == 0)
4806 lod
= get_src(ctx
, instr
->src
[i
].src
);
4809 case nir_tex_src_ms_index
:
4810 sample_index
= get_src(ctx
, instr
->src
[i
].src
);
4812 case nir_tex_src_ms_mcs
:
4814 case nir_tex_src_ddx
:
4815 ddx
= get_src(ctx
, instr
->src
[i
].src
);
4816 num_deriv_comp
= instr
->src
[i
].src
.ssa
->num_components
;
4818 case nir_tex_src_ddy
:
4819 ddy
= get_src(ctx
, instr
->src
[i
].src
);
4821 case nir_tex_src_texture_offset
:
4822 case nir_tex_src_sampler_offset
:
4823 case nir_tex_src_plane
:
4829 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
4830 result
= get_buffer_size(ctx
, res_ptr
, true);
4834 if (instr
->op
== nir_texop_texture_samples
) {
4835 LLVMValueRef res
, samples
, is_msaa
;
4836 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->ac
.v8i32
, "");
4837 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
4838 LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
4839 is_msaa
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4840 LLVMConstInt(ctx
->ac
.i32
, 28, false), "");
4841 is_msaa
= LLVMBuildAnd(ctx
->ac
.builder
, is_msaa
,
4842 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4843 is_msaa
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, is_msaa
,
4844 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4846 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4847 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
4848 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
4849 LLVMConstInt(ctx
->ac
.i32
, 0xf, false), "");
4850 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->ac
.i32_1
,
4852 samples
= LLVMBuildSelect(ctx
->ac
.builder
, is_msaa
, samples
,
4859 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4860 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, coord
, chan
);
4862 if (offsets
&& instr
->op
!= nir_texop_txf
) {
4863 LLVMValueRef offset
[3], pack
;
4864 for (chan
= 0; chan
< 3; ++chan
)
4865 offset
[chan
] = ctx
->ac
.i32_0
;
4868 for (chan
= 0; chan
< ac_get_llvm_num_components(offsets
); chan
++) {
4869 offset
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, offsets
, chan
);
4870 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
4871 LLVMConstInt(ctx
->ac
.i32
, 0x3f, false), "");
4873 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
4874 LLVMConstInt(ctx
->ac
.i32
, chan
* 8, false), "");
4876 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
4877 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
4878 address
[count
++] = pack
;
4881 /* pack LOD bias value */
4882 if (instr
->op
== nir_texop_txb
&& bias
) {
4883 address
[count
++] = bias
;
4886 /* Pack depth comparison value */
4887 if (instr
->is_shadow
&& comparator
) {
4888 LLVMValueRef z
= ac_to_float(&ctx
->ac
,
4889 ac_llvm_extract_elem(&ctx
->ac
, comparator
, 0));
4891 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4892 * so the depth comparison value isn't clamped for Z16 and
4893 * Z24 anymore. Do it manually here.
4895 * It's unnecessary if the original texture format was
4896 * Z32_FLOAT, but we don't know that here.
4898 if (ctx
->ac
.chip_class
== VI
&& ctx
->abi
->clamp_shadow_reference
)
4899 z
= ac_build_clamp(&ctx
->ac
, z
);
4901 address
[count
++] = z
;
4904 /* pack derivatives */
4906 int num_src_deriv_channels
, num_dest_deriv_channels
;
4907 switch (instr
->sampler_dim
) {
4908 case GLSL_SAMPLER_DIM_3D
:
4909 case GLSL_SAMPLER_DIM_CUBE
:
4911 num_src_deriv_channels
= 3;
4912 num_dest_deriv_channels
= 3;
4914 case GLSL_SAMPLER_DIM_2D
:
4916 num_src_deriv_channels
= 2;
4917 num_dest_deriv_channels
= 2;
4920 case GLSL_SAMPLER_DIM_1D
:
4921 num_src_deriv_channels
= 1;
4922 if (ctx
->ac
.chip_class
>= GFX9
) {
4923 num_dest_deriv_channels
= 2;
4926 num_dest_deriv_channels
= 1;
4932 for (unsigned i
= 0; i
< num_src_deriv_channels
; i
++) {
4933 derivs
[i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddx
, i
));
4934 derivs
[num_dest_deriv_channels
+ i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddy
, i
));
4936 for (unsigned i
= num_src_deriv_channels
; i
< num_dest_deriv_channels
; i
++) {
4937 derivs
[i
] = ctx
->ac
.f32_0
;
4938 derivs
[num_dest_deriv_channels
+ i
] = ctx
->ac
.f32_0
;
4942 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& coord
) {
4943 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4944 coords
[chan
] = ac_to_float(&ctx
->ac
, coords
[chan
]);
4945 if (instr
->coord_components
== 3)
4946 coords
[3] = LLVMGetUndef(ctx
->ac
.f32
);
4947 ac_prepare_cube_coords(&ctx
->ac
,
4948 instr
->op
== nir_texop_txd
, instr
->is_array
,
4949 instr
->op
== nir_texop_lod
, coords
, derivs
);
4955 for (unsigned i
= 0; i
< num_deriv_comp
* 2; i
++)
4956 address
[count
++] = derivs
[i
];
4959 /* Pack texture coordinates */
4961 address
[count
++] = coords
[0];
4962 if (instr
->coord_components
> 1) {
4963 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& instr
->is_array
&& instr
->op
!= nir_texop_txf
) {
4964 coords
[1] = apply_round_slice(&ctx
->ac
, coords
[1]);
4966 address
[count
++] = coords
[1];
4968 if (instr
->coord_components
> 2) {
4969 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4970 if (instr
->sampler_dim
!= GLSL_SAMPLER_DIM_3D
&&
4971 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_CUBE
&&
4972 instr
->op
!= nir_texop_txf
) {
4973 coords
[2] = apply_round_slice(&ctx
->ac
, coords
[2]);
4975 address
[count
++] = coords
[2];
4978 if (ctx
->ac
.chip_class
>= GFX9
) {
4979 LLVMValueRef filler
;
4980 if (instr
->op
== nir_texop_txf
)
4981 filler
= ctx
->ac
.i32_0
;
4983 filler
= LLVMConstReal(ctx
->ac
.f32
, 0.5);
4985 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
) {
4986 /* No nir_texop_lod, because it does not take a slice
4987 * even with array textures. */
4988 if (instr
->is_array
&& instr
->op
!= nir_texop_lod
) {
4989 address
[count
] = address
[count
- 1];
4990 address
[count
- 1] = filler
;
4993 address
[count
++] = filler
;
4999 if (lod
&& ((instr
->op
== nir_texop_txl
&& !lod_is_zero
) ||
5000 instr
->op
== nir_texop_txf
)) {
5001 address
[count
++] = lod
;
5002 } else if (instr
->op
== nir_texop_txf_ms
&& sample_index
) {
5003 address
[count
++] = sample_index
;
5004 } else if(instr
->op
== nir_texop_txs
) {
5007 address
[count
++] = lod
;
5009 address
[count
++] = ctx
->ac
.i32_0
;
5012 for (chan
= 0; chan
< count
; chan
++) {
5013 address
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
,
5014 address
[chan
], ctx
->ac
.i32
, "");
5017 if (instr
->op
== nir_texop_samples_identical
) {
5018 LLVMValueRef txf_address
[4];
5019 struct ac_image_args txf_args
= { 0 };
5020 unsigned txf_count
= count
;
5021 memcpy(txf_address
, address
, sizeof(txf_address
));
5023 if (!instr
->is_array
)
5024 txf_address
[2] = ctx
->ac
.i32_0
;
5025 txf_address
[3] = ctx
->ac
.i32_0
;
5027 set_tex_fetch_args(&ctx
->ac
, &txf_args
, instr
, nir_texop_txf
,
5029 txf_address
, txf_count
, 0xf);
5031 result
= build_tex_intrinsic(ctx
, instr
, false, &txf_args
);
5033 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
5034 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, result
, ctx
->ac
.i32_0
);
5038 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
&&
5039 instr
->op
!= nir_texop_txs
) {
5040 unsigned sample_chan
= instr
->is_array
? 3 : 2;
5041 address
[sample_chan
] = adjust_sample_index_using_fmask(&ctx
->ac
,
5044 instr
->is_array
? address
[2] : NULL
,
5045 address
[sample_chan
],
5049 if (offsets
&& instr
->op
== nir_texop_txf
) {
5050 nir_const_value
*const_offset
=
5051 nir_src_as_const_value(instr
->src
[const_src
].src
);
5052 int num_offsets
= instr
->src
[const_src
].src
.ssa
->num_components
;
5053 assert(const_offset
);
5054 num_offsets
= MIN2(num_offsets
, instr
->coord_components
);
5055 if (num_offsets
> 2)
5056 address
[2] = LLVMBuildAdd(ctx
->ac
.builder
,
5057 address
[2], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[2], false), "");
5058 if (num_offsets
> 1)
5059 address
[1] = LLVMBuildAdd(ctx
->ac
.builder
,
5060 address
[1], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[1], false), "");
5061 address
[0] = LLVMBuildAdd(ctx
->ac
.builder
,
5062 address
[0], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[0], false), "");
5066 /* TODO TG4 support */
5067 if (instr
->op
== nir_texop_tg4
) {
5068 if (instr
->is_shadow
)
5071 dmask
= 1 << instr
->component
;
5073 set_tex_fetch_args(&ctx
->ac
, &args
, instr
, instr
->op
,
5074 res_ptr
, samp_ptr
, address
, count
, dmask
);
5076 result
= build_tex_intrinsic(ctx
, instr
, lod_is_zero
, &args
);
5078 if (instr
->op
== nir_texop_query_levels
)
5079 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
5080 else if (instr
->is_shadow
&& instr
->is_new_style_shadow
&&
5081 instr
->op
!= nir_texop_txs
&& instr
->op
!= nir_texop_lod
&&
5082 instr
->op
!= nir_texop_tg4
)
5083 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
5084 else if (instr
->op
== nir_texop_txs
&&
5085 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
5087 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
5088 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
5089 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
5090 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
5091 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, z
, two
, "");
5092 } else if (ctx
->ac
.chip_class
>= GFX9
&&
5093 instr
->op
== nir_texop_txs
&&
5094 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
5096 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
5097 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
5098 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, layers
,
5100 } else if (instr
->dest
.ssa
.num_components
!= 4)
5101 result
= trim_vector(&ctx
->ac
, result
, instr
->dest
.ssa
.num_components
);
5105 assert(instr
->dest
.is_ssa
);
5106 result
= ac_to_integer(&ctx
->ac
, result
);
5107 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
5112 static void visit_phi(struct ac_nir_context
*ctx
, nir_phi_instr
*instr
)
5114 LLVMTypeRef type
= get_def_type(ctx
, &instr
->dest
.ssa
);
5115 LLVMValueRef result
= LLVMBuildPhi(ctx
->ac
.builder
, type
, "");
5117 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
5118 _mesa_hash_table_insert(ctx
->phis
, instr
, result
);
5121 static void visit_post_phi(struct ac_nir_context
*ctx
,
5122 nir_phi_instr
*instr
,
5123 LLVMValueRef llvm_phi
)
5125 nir_foreach_phi_src(src
, instr
) {
5126 LLVMBasicBlockRef block
= get_block(ctx
, src
->pred
);
5127 LLVMValueRef llvm_src
= get_src(ctx
, src
->src
);
5129 LLVMAddIncoming(llvm_phi
, &llvm_src
, &block
, 1);
5133 static void phi_post_pass(struct ac_nir_context
*ctx
)
5135 struct hash_entry
*entry
;
5136 hash_table_foreach(ctx
->phis
, entry
) {
5137 visit_post_phi(ctx
, (nir_phi_instr
*)entry
->key
,
5138 (LLVMValueRef
)entry
->data
);
5143 static void visit_ssa_undef(struct ac_nir_context
*ctx
,
5144 const nir_ssa_undef_instr
*instr
)
5146 unsigned num_components
= instr
->def
.num_components
;
5147 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
5150 if (num_components
== 1)
5151 undef
= LLVMGetUndef(type
);
5153 undef
= LLVMGetUndef(LLVMVectorType(type
, num_components
));
5155 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, undef
);
5158 static void visit_jump(struct ac_nir_context
*ctx
,
5159 const nir_jump_instr
*instr
)
5161 switch (instr
->type
) {
5162 case nir_jump_break
:
5163 LLVMBuildBr(ctx
->ac
.builder
, ctx
->break_block
);
5164 LLVMClearInsertionPosition(ctx
->ac
.builder
);
5166 case nir_jump_continue
:
5167 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5168 LLVMClearInsertionPosition(ctx
->ac
.builder
);
5171 fprintf(stderr
, "Unknown NIR jump instr: ");
5172 nir_print_instr(&instr
->instr
, stderr
);
5173 fprintf(stderr
, "\n");
5178 static void visit_cf_list(struct ac_nir_context
*ctx
,
5179 struct exec_list
*list
);
5181 static void visit_block(struct ac_nir_context
*ctx
, nir_block
*block
)
5183 LLVMBasicBlockRef llvm_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
5184 nir_foreach_instr(instr
, block
)
5186 switch (instr
->type
) {
5187 case nir_instr_type_alu
:
5188 visit_alu(ctx
, nir_instr_as_alu(instr
));
5190 case nir_instr_type_load_const
:
5191 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
5193 case nir_instr_type_intrinsic
:
5194 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
5196 case nir_instr_type_tex
:
5197 visit_tex(ctx
, nir_instr_as_tex(instr
));
5199 case nir_instr_type_phi
:
5200 visit_phi(ctx
, nir_instr_as_phi(instr
));
5202 case nir_instr_type_ssa_undef
:
5203 visit_ssa_undef(ctx
, nir_instr_as_ssa_undef(instr
));
5205 case nir_instr_type_jump
:
5206 visit_jump(ctx
, nir_instr_as_jump(instr
));
5209 fprintf(stderr
, "Unknown NIR instr type: ");
5210 nir_print_instr(instr
, stderr
);
5211 fprintf(stderr
, "\n");
5216 _mesa_hash_table_insert(ctx
->defs
, block
, llvm_block
);
5219 static void visit_if(struct ac_nir_context
*ctx
, nir_if
*if_stmt
)
5221 LLVMValueRef value
= get_src(ctx
, if_stmt
->condition
);
5223 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
5224 LLVMBasicBlockRef merge_block
=
5225 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5226 LLVMBasicBlockRef if_block
=
5227 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5228 LLVMBasicBlockRef else_block
= merge_block
;
5229 if (!exec_list_is_empty(&if_stmt
->else_list
))
5230 else_block
= LLVMAppendBasicBlockInContext(
5231 ctx
->ac
.context
, fn
, "");
5233 LLVMValueRef cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
, value
,
5235 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, if_block
, else_block
);
5237 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, if_block
);
5238 visit_cf_list(ctx
, &if_stmt
->then_list
);
5239 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5240 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
5242 if (!exec_list_is_empty(&if_stmt
->else_list
)) {
5243 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, else_block
);
5244 visit_cf_list(ctx
, &if_stmt
->else_list
);
5245 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5246 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
5249 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
5252 static void visit_loop(struct ac_nir_context
*ctx
, nir_loop
*loop
)
5254 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
5255 LLVMBasicBlockRef continue_parent
= ctx
->continue_block
;
5256 LLVMBasicBlockRef break_parent
= ctx
->break_block
;
5258 ctx
->continue_block
=
5259 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5261 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5263 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5264 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->continue_block
);
5265 visit_cf_list(ctx
, &loop
->body
);
5267 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5268 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5269 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->break_block
);
5271 ctx
->continue_block
= continue_parent
;
5272 ctx
->break_block
= break_parent
;
5275 static void visit_cf_list(struct ac_nir_context
*ctx
,
5276 struct exec_list
*list
)
5278 foreach_list_typed(nir_cf_node
, node
, node
, list
)
5280 switch (node
->type
) {
5281 case nir_cf_node_block
:
5282 visit_block(ctx
, nir_cf_node_as_block(node
));
5285 case nir_cf_node_if
:
5286 visit_if(ctx
, nir_cf_node_as_if(node
));
5289 case nir_cf_node_loop
:
5290 visit_loop(ctx
, nir_cf_node_as_loop(node
));
5300 handle_vs_input_decl(struct nir_to_llvm_context
*ctx
,
5301 struct nir_variable
*variable
)
5303 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
5304 LLVMValueRef t_offset
;
5305 LLVMValueRef t_list
;
5307 LLVMValueRef buffer_index
;
5308 int index
= variable
->data
.location
- VERT_ATTRIB_GENERIC0
;
5309 int idx
= variable
->data
.location
;
5310 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
5312 variable
->data
.driver_location
= idx
* 4;
5314 for (unsigned i
= 0; i
< attrib_count
; ++i
, ++idx
) {
5315 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << (index
+ i
))) {
5316 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.instance_id
,
5317 ctx
->abi
.start_instance
, "");
5318 if (ctx
->options
->key
.vs
.as_ls
) {
5319 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5320 MAX2(2, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5322 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5323 MAX2(1, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5326 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.vertex_id
,
5327 ctx
->abi
.base_vertex
, "");
5328 t_offset
= LLVMConstInt(ctx
->ac
.i32
, index
+ i
, false);
5330 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
5332 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
5337 for (unsigned chan
= 0; chan
< 4; chan
++) {
5338 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5339 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
, chan
)] =
5340 ac_to_integer(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
,
5341 input
, llvm_chan
, ""));
5346 static void interp_fs_input(struct nir_to_llvm_context
*ctx
,
5348 LLVMValueRef interp_param
,
5349 LLVMValueRef prim_mask
,
5350 LLVMValueRef result
[4])
5352 LLVMValueRef attr_number
;
5355 bool interp
= interp_param
!= NULL
;
5357 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
5359 /* fs.constant returns the param from the middle vertex, so it's not
5360 * really useful for flat shading. It's meant to be used for custom
5361 * interpolation (but the intrinsic can't fetch from the other two
5364 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5365 * to do the right thing. The only reason we use fs.constant is that
5366 * fs.interp cannot be used on integers, because they can be equal
5370 interp_param
= LLVMBuildBitCast(ctx
->builder
, interp_param
,
5373 i
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
5375 j
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
5379 for (chan
= 0; chan
< 4; chan
++) {
5380 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5383 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
5388 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
5389 LLVMConstInt(ctx
->ac
.i32
, 2, false),
5398 handle_fs_input_decl(struct nir_to_llvm_context
*ctx
,
5399 struct nir_variable
*variable
)
5401 int idx
= variable
->data
.location
;
5402 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5403 LLVMValueRef interp
;
5405 variable
->data
.driver_location
= idx
* 4;
5406 ctx
->input_mask
|= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
5408 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
5409 unsigned interp_type
;
5410 if (variable
->data
.sample
) {
5411 interp_type
= INTERP_SAMPLE
;
5412 ctx
->shader_info
->info
.ps
.force_persample
= true;
5413 } else if (variable
->data
.centroid
)
5414 interp_type
= INTERP_CENTROID
;
5416 interp_type
= INTERP_CENTER
;
5418 interp
= lookup_interp_param(ctx
, variable
->data
.interpolation
, interp_type
);
5422 for (unsigned i
= 0; i
< attrib_count
; ++i
)
5423 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
5428 handle_vs_inputs(struct nir_to_llvm_context
*ctx
,
5429 struct nir_shader
*nir
) {
5430 nir_foreach_variable(variable
, &nir
->inputs
)
5431 handle_vs_input_decl(ctx
, variable
);
5435 prepare_interp_optimize(struct nir_to_llvm_context
*ctx
,
5436 struct nir_shader
*nir
)
5438 if (!ctx
->options
->key
.fs
.multisample
)
5441 bool uses_center
= false;
5442 bool uses_centroid
= false;
5443 nir_foreach_variable(variable
, &nir
->inputs
) {
5444 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
5445 variable
->data
.sample
)
5448 if (variable
->data
.centroid
)
5449 uses_centroid
= true;
5454 if (uses_center
&& uses_centroid
) {
5455 LLVMValueRef sel
= LLVMBuildICmp(ctx
->builder
, LLVMIntSLT
, ctx
->prim_mask
, ctx
->ac
.i32_0
, "");
5456 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
5457 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
5462 handle_fs_inputs(struct nir_to_llvm_context
*ctx
,
5463 struct nir_shader
*nir
)
5465 prepare_interp_optimize(ctx
, nir
);
5467 nir_foreach_variable(variable
, &nir
->inputs
)
5468 handle_fs_input_decl(ctx
, variable
);
5472 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
5473 ctx
->shader_info
->info
.needs_multiview_view_index
)
5474 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
5476 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
5477 LLVMValueRef interp_param
;
5478 LLVMValueRef
*inputs
= ctx
->inputs
+radeon_llvm_reg_index_soa(i
, 0);
5480 if (!(ctx
->input_mask
& (1ull << i
)))
5483 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
5484 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
5485 interp_param
= *inputs
;
5486 interp_fs_input(ctx
, index
, interp_param
, ctx
->prim_mask
,
5490 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
5492 } else if (i
== VARYING_SLOT_POS
) {
5493 for(int i
= 0; i
< 3; ++i
)
5494 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
5496 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
5497 ctx
->abi
.frag_pos
[3]);
5500 ctx
->shader_info
->fs
.num_interp
= index
;
5501 if (ctx
->input_mask
& (1 << VARYING_SLOT_PNTC
))
5502 ctx
->shader_info
->fs
.has_pcoord
= true;
5503 if (ctx
->input_mask
& (1 << VARYING_SLOT_PRIMITIVE_ID
))
5504 ctx
->shader_info
->fs
.prim_id_input
= true;
5505 if (ctx
->input_mask
& (1 << VARYING_SLOT_LAYER
))
5506 ctx
->shader_info
->fs
.layer_input
= true;
5507 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
5509 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
5510 ctx
->view_index
= ctx
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5514 ac_build_alloca(struct ac_llvm_context
*ac
,
5518 LLVMBuilderRef builder
= ac
->builder
;
5519 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(builder
);
5520 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
5521 LLVMBasicBlockRef first_block
= LLVMGetEntryBasicBlock(function
);
5522 LLVMValueRef first_instr
= LLVMGetFirstInstruction(first_block
);
5523 LLVMBuilderRef first_builder
= LLVMCreateBuilderInContext(ac
->context
);
5527 LLVMPositionBuilderBefore(first_builder
, first_instr
);
5529 LLVMPositionBuilderAtEnd(first_builder
, first_block
);
5532 res
= LLVMBuildAlloca(first_builder
, type
, name
);
5533 LLVMBuildStore(builder
, LLVMConstNull(type
), res
);
5535 LLVMDisposeBuilder(first_builder
);
5540 static LLVMValueRef
si_build_alloca_undef(struct ac_llvm_context
*ac
,
5544 LLVMValueRef ptr
= ac_build_alloca(ac
, type
, name
);
5545 LLVMBuildStore(ac
->builder
, LLVMGetUndef(type
), ptr
);
5550 scan_shader_output_decl(struct nir_to_llvm_context
*ctx
,
5551 struct nir_variable
*variable
,
5552 struct nir_shader
*shader
,
5553 gl_shader_stage stage
)
5555 int idx
= variable
->data
.location
+ variable
->data
.index
;
5556 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5557 uint64_t mask_attribs
;
5559 variable
->data
.driver_location
= idx
* 4;
5561 /* tess ctrl has it's own load/store paths for outputs */
5562 if (stage
== MESA_SHADER_TESS_CTRL
)
5565 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
5566 if (stage
== MESA_SHADER_VERTEX
||
5567 stage
== MESA_SHADER_TESS_EVAL
||
5568 stage
== MESA_SHADER_GEOMETRY
) {
5569 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5570 int length
= shader
->info
.clip_distance_array_size
+
5571 shader
->info
.cull_distance_array_size
;
5572 if (stage
== MESA_SHADER_VERTEX
) {
5573 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5574 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5576 if (stage
== MESA_SHADER_TESS_EVAL
) {
5577 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5578 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5585 mask_attribs
= 1ull << idx
;
5589 ctx
->output_mask
|= mask_attribs
;
5593 handle_shader_output_decl(struct ac_nir_context
*ctx
,
5594 struct nir_shader
*nir
,
5595 struct nir_variable
*variable
)
5597 unsigned output_loc
= variable
->data
.driver_location
/ 4;
5598 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5600 /* tess ctrl has it's own load/store paths for outputs */
5601 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
5604 if (ctx
->stage
== MESA_SHADER_VERTEX
||
5605 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
5606 ctx
->stage
== MESA_SHADER_GEOMETRY
) {
5607 int idx
= variable
->data
.location
+ variable
->data
.index
;
5608 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5609 int length
= nir
->info
.clip_distance_array_size
+
5610 nir
->info
.cull_distance_array_size
;
5619 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
5620 for (unsigned chan
= 0; chan
< 4; chan
++) {
5621 ctx
->outputs
[radeon_llvm_reg_index_soa(output_loc
+ i
, chan
)] =
5622 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5628 glsl_base_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5629 enum glsl_base_type type
)
5633 case GLSL_TYPE_UINT
:
5634 case GLSL_TYPE_BOOL
:
5635 case GLSL_TYPE_SUBROUTINE
:
5637 case GLSL_TYPE_FLOAT
: /* TODO handle mediump */
5639 case GLSL_TYPE_INT64
:
5640 case GLSL_TYPE_UINT64
:
5642 case GLSL_TYPE_DOUBLE
:
5645 unreachable("unknown GLSL type");
5650 glsl_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5651 const struct glsl_type
*type
)
5653 if (glsl_type_is_scalar(type
)) {
5654 return glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
));
5657 if (glsl_type_is_vector(type
)) {
5658 return LLVMVectorType(
5659 glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
)),
5660 glsl_get_vector_elements(type
));
5663 if (glsl_type_is_matrix(type
)) {
5664 return LLVMArrayType(
5665 glsl_to_llvm_type(ctx
, glsl_get_column_type(type
)),
5666 glsl_get_matrix_columns(type
));
5669 if (glsl_type_is_array(type
)) {
5670 return LLVMArrayType(
5671 glsl_to_llvm_type(ctx
, glsl_get_array_element(type
)),
5672 glsl_get_length(type
));
5675 assert(glsl_type_is_struct(type
));
5677 LLVMTypeRef member_types
[glsl_get_length(type
)];
5679 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
5681 glsl_to_llvm_type(ctx
,
5682 glsl_get_struct_field(type
, i
));
5685 return LLVMStructTypeInContext(ctx
->context
, member_types
,
5686 glsl_get_length(type
), false);
5690 setup_locals(struct ac_nir_context
*ctx
,
5691 struct nir_function
*func
)
5694 ctx
->num_locals
= 0;
5695 nir_foreach_variable(variable
, &func
->impl
->locals
) {
5696 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5697 variable
->data
.driver_location
= ctx
->num_locals
* 4;
5698 variable
->data
.location_frac
= 0;
5699 ctx
->num_locals
+= attrib_count
;
5701 ctx
->locals
= malloc(4 * ctx
->num_locals
* sizeof(LLVMValueRef
));
5705 for (i
= 0; i
< ctx
->num_locals
; i
++) {
5706 for (j
= 0; j
< 4; j
++) {
5707 ctx
->locals
[i
* 4 + j
] =
5708 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "temp");
5714 setup_shared(struct ac_nir_context
*ctx
,
5715 struct nir_shader
*nir
)
5717 nir_foreach_variable(variable
, &nir
->shared
) {
5718 LLVMValueRef shared
=
5719 LLVMAddGlobalInAddressSpace(
5720 ctx
->ac
.module
, glsl_to_llvm_type(ctx
->nctx
, variable
->type
),
5721 variable
->name
? variable
->name
: "",
5723 _mesa_hash_table_insert(ctx
->vars
, variable
, shared
);
5728 emit_float_saturate(struct ac_llvm_context
*ctx
, LLVMValueRef v
, float lo
, float hi
)
5730 v
= ac_to_float(ctx
, v
);
5731 v
= emit_intrin_2f_param(ctx
, "llvm.maxnum", ctx
->f32
, v
, LLVMConstReal(ctx
->f32
, lo
));
5732 return emit_intrin_2f_param(ctx
, "llvm.minnum", ctx
->f32
, v
, LLVMConstReal(ctx
->f32
, hi
));
5736 static LLVMValueRef
emit_pack_int16(struct nir_to_llvm_context
*ctx
,
5737 LLVMValueRef src0
, LLVMValueRef src1
)
5739 LLVMValueRef const16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
5740 LLVMValueRef comp
[2];
5742 comp
[0] = LLVMBuildAnd(ctx
->builder
, src0
, LLVMConstInt(ctx
->ac
.i32
, 65535, 0), "");
5743 comp
[1] = LLVMBuildAnd(ctx
->builder
, src1
, LLVMConstInt(ctx
->ac
.i32
, 65535, 0), "");
5744 comp
[1] = LLVMBuildShl(ctx
->builder
, comp
[1], const16
, "");
5745 return LLVMBuildOr(ctx
->builder
, comp
[0], comp
[1], "");
5748 /* Initialize arguments for the shader export intrinsic */
5750 si_llvm_init_export_args(struct nir_to_llvm_context
*ctx
,
5751 LLVMValueRef
*values
,
5753 struct ac_export_args
*args
)
5755 /* Default is 0xf. Adjusted below depending on the format. */
5756 args
->enabled_channels
= 0xf;
5758 /* Specify whether the EXEC mask represents the valid mask */
5759 args
->valid_mask
= 0;
5761 /* Specify whether this is the last export */
5764 /* Specify the target we are exporting */
5765 args
->target
= target
;
5767 args
->compr
= false;
5768 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
5769 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
5770 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
5771 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
5776 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& target
>= V_008DFC_SQ_EXP_MRT
) {
5777 LLVMValueRef val
[4];
5778 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
5779 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
5780 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
5781 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
5783 switch(col_format
) {
5784 case V_028714_SPI_SHADER_ZERO
:
5785 args
->enabled_channels
= 0; /* writemask */
5786 args
->target
= V_008DFC_SQ_EXP_NULL
;
5789 case V_028714_SPI_SHADER_32_R
:
5790 args
->enabled_channels
= 1;
5791 args
->out
[0] = values
[0];
5794 case V_028714_SPI_SHADER_32_GR
:
5795 args
->enabled_channels
= 0x3;
5796 args
->out
[0] = values
[0];
5797 args
->out
[1] = values
[1];
5800 case V_028714_SPI_SHADER_32_AR
:
5801 args
->enabled_channels
= 0x9;
5802 args
->out
[0] = values
[0];
5803 args
->out
[3] = values
[3];
5806 case V_028714_SPI_SHADER_FP16_ABGR
:
5809 for (unsigned chan
= 0; chan
< 2; chan
++) {
5810 LLVMValueRef pack_args
[2] = {
5812 values
[2 * chan
+ 1]
5814 LLVMValueRef packed
;
5816 packed
= ac_build_cvt_pkrtz_f16(&ctx
->ac
, pack_args
);
5817 args
->out
[chan
] = packed
;
5821 case V_028714_SPI_SHADER_UNORM16_ABGR
:
5822 for (unsigned chan
= 0; chan
< 4; chan
++) {
5823 val
[chan
] = ac_build_clamp(&ctx
->ac
, values
[chan
]);
5824 val
[chan
] = LLVMBuildFMul(ctx
->builder
, val
[chan
],
5825 LLVMConstReal(ctx
->ac
.f32
, 65535), "");
5826 val
[chan
] = LLVMBuildFAdd(ctx
->builder
, val
[chan
],
5827 LLVMConstReal(ctx
->ac
.f32
, 0.5), "");
5828 val
[chan
] = LLVMBuildFPToUI(ctx
->builder
, val
[chan
],
5833 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5834 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5837 case V_028714_SPI_SHADER_SNORM16_ABGR
:
5838 for (unsigned chan
= 0; chan
< 4; chan
++) {
5839 val
[chan
] = emit_float_saturate(&ctx
->ac
, values
[chan
], -1, 1);
5840 val
[chan
] = LLVMBuildFMul(ctx
->builder
, val
[chan
],
5841 LLVMConstReal(ctx
->ac
.f32
, 32767), "");
5843 /* If positive, add 0.5, else add -0.5. */
5844 val
[chan
] = LLVMBuildFAdd(ctx
->builder
, val
[chan
],
5845 LLVMBuildSelect(ctx
->builder
,
5846 LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
,
5847 val
[chan
], ctx
->ac
.f32_0
, ""),
5848 LLVMConstReal(ctx
->ac
.f32
, 0.5),
5849 LLVMConstReal(ctx
->ac
.f32
, -0.5), ""), "");
5850 val
[chan
] = LLVMBuildFPToSI(ctx
->builder
, val
[chan
], ctx
->ac
.i32
, "");
5854 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5855 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5858 case V_028714_SPI_SHADER_UINT16_ABGR
: {
5859 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5860 is_int8
? 255 : is_int10
? 1023 : 65535, 0);
5861 LLVMValueRef max_alpha
= !is_int10
? max_rgb
: LLVMConstInt(ctx
->ac
.i32
, 3, 0);
5863 for (unsigned chan
= 0; chan
< 4; chan
++) {
5864 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
5865 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntULT
, val
[chan
], chan
== 3 ? max_alpha
: max_rgb
);
5869 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5870 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5874 case V_028714_SPI_SHADER_SINT16_ABGR
: {
5875 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5876 is_int8
? 127 : is_int10
? 511 : 32767, 0);
5877 LLVMValueRef min_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5878 is_int8
? -128 : is_int10
? -512 : -32768, 0);
5879 LLVMValueRef max_alpha
= !is_int10
? max_rgb
: ctx
->ac
.i32_1
;
5880 LLVMValueRef min_alpha
= !is_int10
? min_rgb
: LLVMConstInt(ctx
->ac
.i32
, -2, 0);
5883 for (unsigned chan
= 0; chan
< 4; chan
++) {
5884 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
5885 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, val
[chan
], chan
== 3 ? max_alpha
: max_rgb
);
5886 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, val
[chan
], chan
== 3 ? min_alpha
: min_rgb
);
5890 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5891 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5896 case V_028714_SPI_SHADER_32_ABGR
:
5897 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5901 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5903 for (unsigned i
= 0; i
< 4; ++i
)
5904 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
5908 handle_vs_outputs_post(struct nir_to_llvm_context
*ctx
,
5909 bool export_prim_id
,
5910 struct ac_vs_output_info
*outinfo
)
5912 uint32_t param_count
= 0;
5914 unsigned pos_idx
, num_pos_exports
= 0;
5915 struct ac_export_args args
, pos_args
[4] = {};
5916 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
5919 if (ctx
->options
->key
.has_multiview_view_index
) {
5920 LLVMValueRef
* tmp_out
= &ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5922 for(unsigned i
= 0; i
< 4; ++i
)
5923 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
5924 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5927 LLVMBuildStore(ctx
->builder
, ac_to_float(&ctx
->ac
, ctx
->view_index
), *tmp_out
);
5928 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
5931 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
5932 sizeof(outinfo
->vs_output_param_offset
));
5934 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
5935 LLVMValueRef slots
[8];
5938 if (outinfo
->cull_dist_mask
)
5939 outinfo
->cull_dist_mask
<<= ctx
->num_output_clips
;
5941 i
= VARYING_SLOT_CLIP_DIST0
;
5942 for (j
= 0; j
< ctx
->num_output_clips
+ ctx
->num_output_culls
; j
++)
5943 slots
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5944 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
5946 for (i
= ctx
->num_output_clips
+ ctx
->num_output_culls
; i
< 8; i
++)
5947 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
5949 if (ctx
->num_output_clips
+ ctx
->num_output_culls
> 4) {
5950 target
= V_008DFC_SQ_EXP_POS
+ 3;
5951 si_llvm_init_export_args(ctx
, &slots
[4], target
, &args
);
5952 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5953 &args
, sizeof(args
));
5956 target
= V_008DFC_SQ_EXP_POS
+ 2;
5957 si_llvm_init_export_args(ctx
, &slots
[0], target
, &args
);
5958 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5959 &args
, sizeof(args
));
5963 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
5964 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
5965 for (unsigned j
= 0; j
< 4; j
++)
5966 pos_values
[j
] = LLVMBuildLoad(ctx
->builder
,
5967 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_POS
, j
)], "");
5969 si_llvm_init_export_args(ctx
, pos_values
, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
5971 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
5972 outinfo
->writes_pointsize
= true;
5973 psize_value
= LLVMBuildLoad(ctx
->builder
,
5974 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ
, 0)], "");
5977 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
5978 outinfo
->writes_layer
= true;
5979 layer_value
= LLVMBuildLoad(ctx
->builder
,
5980 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)], "");
5983 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
5984 outinfo
->writes_viewport_index
= true;
5985 viewport_index_value
= LLVMBuildLoad(ctx
->builder
,
5986 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT
, 0)], "");
5989 if (outinfo
->writes_pointsize
||
5990 outinfo
->writes_layer
||
5991 outinfo
->writes_viewport_index
) {
5992 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
5993 (outinfo
->writes_layer
== true ? 4 : 0));
5994 pos_args
[1].valid_mask
= 0;
5995 pos_args
[1].done
= 0;
5996 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
5997 pos_args
[1].compr
= 0;
5998 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
5999 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
6000 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
6001 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
6003 if (outinfo
->writes_pointsize
== true)
6004 pos_args
[1].out
[0] = psize_value
;
6005 if (outinfo
->writes_layer
== true)
6006 pos_args
[1].out
[2] = layer_value
;
6007 if (outinfo
->writes_viewport_index
== true) {
6008 if (ctx
->options
->chip_class
>= GFX9
) {
6009 /* GFX9 has the layer in out.z[10:0] and the viewport
6010 * index in out.z[19:16].
6012 LLVMValueRef v
= viewport_index_value
;
6013 v
= ac_to_integer(&ctx
->ac
, v
);
6014 v
= LLVMBuildShl(ctx
->builder
, v
,
6015 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6017 v
= LLVMBuildOr(ctx
->builder
, v
,
6018 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
6020 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
6021 pos_args
[1].enabled_channels
|= 1 << 2;
6023 pos_args
[1].out
[3] = viewport_index_value
;
6024 pos_args
[1].enabled_channels
|= 1 << 3;
6028 for (i
= 0; i
< 4; i
++) {
6029 if (pos_args
[i
].out
[0])
6034 for (i
= 0; i
< 4; i
++) {
6035 if (!pos_args
[i
].out
[0])
6038 /* Specify the target we are exporting */
6039 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
6040 if (pos_idx
== num_pos_exports
)
6041 pos_args
[i
].done
= 1;
6042 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
6045 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6046 LLVMValueRef values
[4];
6047 if (!(ctx
->output_mask
& (1ull << i
)))
6050 for (unsigned j
= 0; j
< 4; j
++)
6051 values
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6052 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
6054 if (i
== VARYING_SLOT_LAYER
) {
6055 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
6056 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = param_count
;
6058 } else if (i
== VARYING_SLOT_PRIMITIVE_ID
) {
6059 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
6060 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
6062 } else if (i
>= VARYING_SLOT_VAR0
) {
6063 outinfo
->export_mask
|= 1u << (i
- VARYING_SLOT_VAR0
);
6064 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
6065 outinfo
->vs_output_param_offset
[i
] = param_count
;
6070 si_llvm_init_export_args(ctx
, values
, target
, &args
);
6072 if (target
>= V_008DFC_SQ_EXP_POS
&&
6073 target
<= (V_008DFC_SQ_EXP_POS
+ 3)) {
6074 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
6075 &args
, sizeof(args
));
6077 ac_build_export(&ctx
->ac
, &args
);
6081 if (export_prim_id
) {
6082 LLVMValueRef values
[4];
6083 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
6084 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
6087 values
[0] = ctx
->vs_prim_id
;
6088 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
6089 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
6090 for (unsigned j
= 1; j
< 4; j
++)
6091 values
[j
] = ctx
->ac
.f32_0
;
6092 si_llvm_init_export_args(ctx
, values
, target
, &args
);
6093 ac_build_export(&ctx
->ac
, &args
);
6094 outinfo
->export_prim_id
= true;
6097 outinfo
->pos_exports
= num_pos_exports
;
6098 outinfo
->param_exports
= param_count
;
6102 handle_es_outputs_post(struct nir_to_llvm_context
*ctx
,
6103 struct ac_es_output_info
*outinfo
)
6106 uint64_t max_output_written
= 0;
6107 LLVMValueRef lds_base
= NULL
;
6109 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6113 if (!(ctx
->output_mask
& (1ull << i
)))
6116 if (i
== VARYING_SLOT_CLIP_DIST0
)
6117 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6119 param_index
= shader_io_get_unique_index(i
);
6121 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
6124 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
6126 if (ctx
->ac
.chip_class
>= GFX9
) {
6127 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
6128 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
6129 LLVMValueRef wave_idx
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6130 LLVMConstInt(ctx
->ac
.i32
, 24, false),
6131 LLVMConstInt(ctx
->ac
.i32
, 4, false), false);
6132 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
6133 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
6134 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
6135 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
6136 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
6139 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6140 LLVMValueRef dw_addr
;
6141 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
6145 if (!(ctx
->output_mask
& (1ull << i
)))
6148 if (i
== VARYING_SLOT_CLIP_DIST0
)
6149 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6151 param_index
= shader_io_get_unique_index(i
);
6154 dw_addr
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6155 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
6158 for (j
= 0; j
< length
; j
++) {
6159 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], "");
6160 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->ac
.i32
, "");
6162 if (ctx
->ac
.chip_class
>= GFX9
) {
6163 ac_lds_store(&ctx
->ac
, dw_addr
,
6164 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
6165 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6167 ac_build_buffer_store_dword(&ctx
->ac
,
6170 NULL
, ctx
->es2gs_offset
,
6171 (4 * param_index
+ j
) * 4,
6179 handle_ls_outputs_post(struct nir_to_llvm_context
*ctx
)
6181 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
6182 LLVMValueRef vertex_dw_stride
= unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 13, 8);
6183 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->builder
, vertex_id
,
6184 vertex_dw_stride
, "");
6186 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6187 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
6190 if (!(ctx
->output_mask
& (1ull << i
)))
6193 if (i
== VARYING_SLOT_CLIP_DIST0
)
6194 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6195 int param
= shader_io_get_unique_index(i
);
6196 mark_tess_output(ctx
, false, param
);
6198 mark_tess_output(ctx
, false, param
+ 1);
6199 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->builder
, base_dw_addr
,
6200 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
6202 for (unsigned j
= 0; j
< length
; j
++) {
6203 ac_lds_store(&ctx
->ac
, dw_addr
,
6204 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
6205 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6210 struct ac_build_if_state
6212 struct nir_to_llvm_context
*ctx
;
6213 LLVMValueRef condition
;
6214 LLVMBasicBlockRef entry_block
;
6215 LLVMBasicBlockRef true_block
;
6216 LLVMBasicBlockRef false_block
;
6217 LLVMBasicBlockRef merge_block
;
6220 static LLVMBasicBlockRef
6221 ac_build_insert_new_block(struct nir_to_llvm_context
*ctx
, const char *name
)
6223 LLVMBasicBlockRef current_block
;
6224 LLVMBasicBlockRef next_block
;
6225 LLVMBasicBlockRef new_block
;
6227 /* get current basic block */
6228 current_block
= LLVMGetInsertBlock(ctx
->builder
);
6230 /* chqeck if there's another block after this one */
6231 next_block
= LLVMGetNextBasicBlock(current_block
);
6233 /* insert the new block before the next block */
6234 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
6237 /* append new block after current block */
6238 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
6239 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
6245 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
6246 struct nir_to_llvm_context
*ctx
,
6247 LLVMValueRef condition
)
6249 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->builder
);
6251 memset(ifthen
, 0, sizeof *ifthen
);
6253 ifthen
->condition
= condition
;
6254 ifthen
->entry_block
= block
;
6256 /* create endif/merge basic block for the phi functions */
6257 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
6259 /* create/insert true_block before merge_block */
6260 ifthen
->true_block
=
6261 LLVMInsertBasicBlockInContext(ctx
->context
,
6262 ifthen
->merge_block
,
6265 /* successive code goes into the true block */
6266 LLVMPositionBuilderAtEnd(ctx
->builder
, ifthen
->true_block
);
6270 * End a conditional.
6273 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
6275 LLVMBuilderRef builder
= ifthen
->ctx
->builder
;
6277 /* Insert branch to the merge block from current block */
6278 LLVMBuildBr(builder
, ifthen
->merge_block
);
6281 * Now patch in the various branch instructions.
6284 /* Insert the conditional branch instruction at the end of entry_block */
6285 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
6286 if (ifthen
->false_block
) {
6287 /* we have an else clause */
6288 LLVMBuildCondBr(builder
, ifthen
->condition
,
6289 ifthen
->true_block
, ifthen
->false_block
);
6292 /* no else clause */
6293 LLVMBuildCondBr(builder
, ifthen
->condition
,
6294 ifthen
->true_block
, ifthen
->merge_block
);
6297 /* Resume building code at end of the ifthen->merge_block */
6298 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
6302 write_tess_factors(struct nir_to_llvm_context
*ctx
)
6304 unsigned stride
, outer_comps
, inner_comps
;
6305 struct ac_build_if_state if_ctx
, inner_if_ctx
;
6306 LLVMValueRef invocation_id
= unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
6307 LLVMValueRef rel_patch_id
= unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
6308 unsigned tess_inner_index
, tess_outer_index
;
6309 LLVMValueRef lds_base
, lds_inner
, lds_outer
, byteoffset
, buffer
;
6310 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
6312 emit_barrier(&ctx
->ac
, ctx
->stage
);
6314 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
6334 ac_nir_build_if(&if_ctx
, ctx
,
6335 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
6336 invocation_id
, ctx
->ac
.i32_0
, ""));
6338 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6339 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6341 mark_tess_output(ctx
, true, tess_inner_index
);
6342 mark_tess_output(ctx
, true, tess_outer_index
);
6343 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
6344 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6345 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
6346 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6347 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
6349 for (i
= 0; i
< 4; i
++) {
6350 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6351 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6355 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
6356 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
6357 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
6359 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
6361 for (i
= 0; i
< outer_comps
; i
++) {
6363 ac_lds_load(&ctx
->ac
, lds_outer
);
6364 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
6367 for (i
= 0; i
< inner_comps
; i
++) {
6368 inner
[i
] = out
[outer_comps
+i
] =
6369 ac_lds_load(&ctx
->ac
, lds_inner
);
6370 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_inner
,
6375 /* Convert the outputs to vectors for stores. */
6376 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
6380 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
6383 buffer
= ctx
->hs_ring_tess_factor
;
6384 tf_base
= ctx
->tess_factor_offset
;
6385 byteoffset
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
6386 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
6387 unsigned tf_offset
= 0;
6389 if (ctx
->options
->chip_class
<= VI
) {
6390 ac_nir_build_if(&inner_if_ctx
, ctx
,
6391 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
6392 rel_patch_id
, ctx
->ac
.i32_0
, ""));
6394 /* Store the dynamic HS control word. */
6395 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
6396 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
6397 1, ctx
->ac
.i32_0
, tf_base
,
6398 0, 1, 0, true, false);
6401 ac_nir_build_endif(&inner_if_ctx
);
6404 /* Store the tessellation factors. */
6405 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
6406 MIN2(stride
, 4), byteoffset
, tf_base
,
6407 tf_offset
, 1, 0, true, false);
6409 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
6410 stride
- 4, byteoffset
, tf_base
,
6411 16 + tf_offset
, 1, 0, true, false);
6413 //store to offchip for TES to read - only if TES reads them
6414 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
6415 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
6416 LLVMValueRef tf_inner_offset
;
6417 unsigned param_outer
, param_inner
;
6419 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6420 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6421 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
6423 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
6424 util_next_power_of_two(outer_comps
));
6426 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
6427 outer_comps
, tf_outer_offset
,
6428 ctx
->oc_lds
, 0, 1, 0, true, false);
6430 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6431 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6432 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
6434 inner_vec
= inner_comps
== 1 ? inner
[0] :
6435 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
6436 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
6437 inner_comps
, tf_inner_offset
,
6438 ctx
->oc_lds
, 0, 1, 0, true, false);
6441 ac_nir_build_endif(&if_ctx
);
6445 handle_tcs_outputs_post(struct nir_to_llvm_context
*ctx
)
6447 write_tess_factors(ctx
);
6451 si_export_mrt_color(struct nir_to_llvm_context
*ctx
,
6452 LLVMValueRef
*color
, unsigned param
, bool is_last
,
6453 struct ac_export_args
*args
)
6456 si_llvm_init_export_args(ctx
, color
, param
,
6460 args
->valid_mask
= 1; /* whether the EXEC mask is valid */
6461 args
->done
= 1; /* DONE bit */
6462 } else if (!args
->enabled_channels
)
6463 return false; /* unnecessary NULL export */
6469 radv_export_mrt_z(struct nir_to_llvm_context
*ctx
,
6470 LLVMValueRef depth
, LLVMValueRef stencil
,
6471 LLVMValueRef samplemask
)
6473 struct ac_export_args args
;
6475 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
6477 ac_build_export(&ctx
->ac
, &args
);
6481 handle_fs_outputs_post(struct nir_to_llvm_context
*ctx
)
6484 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
6485 struct ac_export_args color_args
[8];
6487 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6488 LLVMValueRef values
[4];
6490 if (!(ctx
->output_mask
& (1ull << i
)))
6493 if (i
== FRAG_RESULT_DEPTH
) {
6494 ctx
->shader_info
->fs
.writes_z
= true;
6495 depth
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6496 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6497 } else if (i
== FRAG_RESULT_STENCIL
) {
6498 ctx
->shader_info
->fs
.writes_stencil
= true;
6499 stencil
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6500 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6501 } else if (i
== FRAG_RESULT_SAMPLE_MASK
) {
6502 ctx
->shader_info
->fs
.writes_sample_mask
= true;
6503 samplemask
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6504 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6507 for (unsigned j
= 0; j
< 4; j
++)
6508 values
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6509 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
6511 if (!ctx
->shader_info
->fs
.writes_z
&& !ctx
->shader_info
->fs
.writes_stencil
&& !ctx
->shader_info
->fs
.writes_sample_mask
)
6512 last
= ctx
->output_mask
<= ((1ull << (i
+ 1)) - 1);
6514 bool ret
= si_export_mrt_color(ctx
, values
, V_008DFC_SQ_EXP_MRT
+ (i
- FRAG_RESULT_DATA0
), last
, &color_args
[index
]);
6520 for (unsigned i
= 0; i
< index
; i
++)
6521 ac_build_export(&ctx
->ac
, &color_args
[i
]);
6522 if (depth
|| stencil
|| samplemask
)
6523 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
6525 si_export_mrt_color(ctx
, NULL
, V_008DFC_SQ_EXP_NULL
, true, &color_args
[0]);
6526 ac_build_export(&ctx
->ac
, &color_args
[0]);
6531 emit_gs_epilogue(struct nir_to_llvm_context
*ctx
)
6533 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
6537 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
6538 LLVMValueRef
*addrs
)
6540 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
6542 switch (ctx
->stage
) {
6543 case MESA_SHADER_VERTEX
:
6544 if (ctx
->options
->key
.vs
.as_ls
)
6545 handle_ls_outputs_post(ctx
);
6546 else if (ctx
->options
->key
.vs
.as_es
)
6547 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
6549 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
6550 &ctx
->shader_info
->vs
.outinfo
);
6552 case MESA_SHADER_FRAGMENT
:
6553 handle_fs_outputs_post(ctx
);
6555 case MESA_SHADER_GEOMETRY
:
6556 emit_gs_epilogue(ctx
);
6558 case MESA_SHADER_TESS_CTRL
:
6559 handle_tcs_outputs_post(ctx
);
6561 case MESA_SHADER_TESS_EVAL
:
6562 if (ctx
->options
->key
.tes
.as_es
)
6563 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
6565 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
6566 &ctx
->shader_info
->tes
.outinfo
);
6573 static void ac_llvm_finalize_module(struct nir_to_llvm_context
* ctx
)
6575 LLVMPassManagerRef passmgr
;
6576 /* Create the pass manager */
6577 passmgr
= LLVMCreateFunctionPassManagerForModule(
6580 /* This pass should eliminate all the load and store instructions */
6581 LLVMAddPromoteMemoryToRegisterPass(passmgr
);
6583 /* Add some optimization passes */
6584 LLVMAddScalarReplAggregatesPass(passmgr
);
6585 LLVMAddLICMPass(passmgr
);
6586 LLVMAddAggressiveDCEPass(passmgr
);
6587 LLVMAddCFGSimplificationPass(passmgr
);
6588 LLVMAddInstructionCombiningPass(passmgr
);
6591 LLVMInitializeFunctionPassManager(passmgr
);
6592 LLVMRunFunctionPassManager(passmgr
, ctx
->main_function
);
6593 LLVMFinalizeFunctionPassManager(passmgr
);
6595 LLVMDisposeBuilder(ctx
->builder
);
6596 LLVMDisposePassManager(passmgr
);
6600 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context
*ctx
)
6602 struct ac_vs_output_info
*outinfo
;
6604 switch (ctx
->stage
) {
6605 case MESA_SHADER_FRAGMENT
:
6606 case MESA_SHADER_COMPUTE
:
6607 case MESA_SHADER_TESS_CTRL
:
6608 case MESA_SHADER_GEOMETRY
:
6610 case MESA_SHADER_VERTEX
:
6611 if (ctx
->options
->key
.vs
.as_ls
||
6612 ctx
->options
->key
.vs
.as_es
)
6614 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
6616 case MESA_SHADER_TESS_EVAL
:
6617 if (ctx
->options
->key
.vs
.as_es
)
6619 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
6622 unreachable("Unhandled shader type");
6625 ac_optimize_vs_outputs(&ctx
->ac
,
6627 outinfo
->vs_output_param_offset
,
6629 &outinfo
->param_exports
);
6633 ac_setup_rings(struct nir_to_llvm_context
*ctx
)
6635 if ((ctx
->stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_es
) ||
6636 (ctx
->stage
== MESA_SHADER_TESS_EVAL
&& ctx
->options
->key
.tes
.as_es
)) {
6637 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_VS
, false));
6640 if (ctx
->is_gs_copy_shader
) {
6641 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_VS
, false));
6643 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
6645 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_GS
, false));
6646 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_GS
, false));
6648 ctx
->gsvs_ring
= LLVMBuildBitCast(ctx
->builder
, ctx
->gsvs_ring
, ctx
->ac
.v4i32
, "");
6650 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->gsvs_num_entries
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
6651 tmp
= LLVMBuildExtractElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->ac
.i32_1
, "");
6652 tmp
= LLVMBuildOr(ctx
->builder
, tmp
, ctx
->gsvs_ring_stride
, "");
6653 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, tmp
, ctx
->ac
.i32_1
, "");
6656 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
6657 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
6658 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
6659 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
6664 ac_nir_get_max_workgroup_size(enum chip_class chip_class
,
6665 const struct nir_shader
*nir
)
6667 switch (nir
->info
.stage
) {
6668 case MESA_SHADER_TESS_CTRL
:
6669 return chip_class
>= CIK
? 128 : 64;
6670 case MESA_SHADER_GEOMETRY
:
6671 return chip_class
>= GFX9
? 128 : 64;
6672 case MESA_SHADER_COMPUTE
:
6678 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
6679 nir
->info
.cs
.local_size
[1] *
6680 nir
->info
.cs
.local_size
[2];
6681 return max_workgroup_size
;
6684 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6685 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context
*ctx
)
6687 LLVMValueRef count
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6688 LLVMConstInt(ctx
->ac
.i32
, 8, false),
6689 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6690 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
6692 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
6693 ctx
->vs_prim_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.vertex_id
, ctx
->vs_prim_id
, "");
6694 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
6695 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
6698 static void prepare_gs_input_vgprs(struct nir_to_llvm_context
*ctx
)
6700 for(int i
= 5; i
>= 0; --i
) {
6701 ctx
->gs_vtx_offset
[i
] = ac_build_bfe(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
6702 LLVMConstInt(ctx
->ac
.i32
, (i
& 1) * 16, false),
6703 LLVMConstInt(ctx
->ac
.i32
, 16, false), false);
6706 ctx
->gs_wave_id
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6707 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6708 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6711 void ac_nir_translate(struct ac_llvm_context
*ac
, struct ac_shader_abi
*abi
,
6712 struct nir_shader
*nir
, struct nir_to_llvm_context
*nctx
)
6714 struct ac_nir_context ctx
= {};
6715 struct nir_function
*func
;
6724 ctx
.stage
= nir
->info
.stage
;
6726 ctx
.main_function
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6728 nir_foreach_variable(variable
, &nir
->outputs
)
6729 handle_shader_output_decl(&ctx
, nir
, variable
);
6731 ctx
.defs
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6732 _mesa_key_pointer_equal
);
6733 ctx
.phis
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6734 _mesa_key_pointer_equal
);
6735 ctx
.vars
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6736 _mesa_key_pointer_equal
);
6738 func
= (struct nir_function
*)exec_list_get_head(&nir
->functions
);
6740 setup_locals(&ctx
, func
);
6742 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
6743 setup_shared(&ctx
, nir
);
6745 visit_cf_list(&ctx
, &func
->impl
->body
);
6746 phi_post_pass(&ctx
);
6748 ctx
.abi
->emit_outputs(ctx
.abi
, RADEON_LLVM_MAX_OUTPUTS
,
6752 ralloc_free(ctx
.defs
);
6753 ralloc_free(ctx
.phis
);
6754 ralloc_free(ctx
.vars
);
6761 LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm
,
6762 struct nir_shader
*const *shaders
,
6764 struct ac_shader_variant_info
*shader_info
,
6765 const struct ac_nir_compiler_options
*options
)
6767 struct nir_to_llvm_context ctx
= {0};
6769 ctx
.options
= options
;
6770 ctx
.shader_info
= shader_info
;
6771 ctx
.context
= LLVMContextCreate();
6772 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
6774 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
6776 ctx
.ac
.module
= ctx
.module
;
6777 LLVMSetTarget(ctx
.module
, options
->supports_spill
? "amdgcn-mesa-mesa3d" : "amdgcn--");
6779 LLVMTargetDataRef data_layout
= LLVMCreateTargetDataLayout(tm
);
6780 char *data_layout_str
= LLVMCopyStringRepOfTargetData(data_layout
);
6781 LLVMSetDataLayout(ctx
.module
, data_layout_str
);
6782 LLVMDisposeTargetData(data_layout
);
6783 LLVMDisposeMessage(data_layout_str
);
6785 enum ac_float_mode float_mode
=
6786 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
6787 AC_FLOAT_MODE_DEFAULT
;
6789 ctx
.builder
= ac_create_builder(ctx
.context
, float_mode
);
6790 ctx
.ac
.builder
= ctx
.builder
;
6792 memset(shader_info
, 0, sizeof(*shader_info
));
6794 for(int i
= 0; i
< shader_count
; ++i
)
6795 ac_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
6797 for (i
= 0; i
< AC_UD_MAX_SETS
; i
++)
6798 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
6799 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
6800 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
6802 ctx
.max_workgroup_size
= 0;
6803 for (int i
= 0; i
< shader_count
; ++i
) {
6804 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
6805 ac_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
6809 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
6810 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
6812 ctx
.abi
.inputs
= &ctx
.inputs
[0];
6813 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
6814 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
6815 ctx
.abi
.load_ubo
= radv_load_ubo
;
6816 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
6817 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
6818 ctx
.abi
.clamp_shadow_reference
= false;
6820 if (shader_count
>= 2)
6821 ac_init_exec_full_mask(&ctx
.ac
);
6823 if (ctx
.ac
.chip_class
== GFX9
&&
6824 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
6825 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
6827 for(int i
= 0; i
< shader_count
; ++i
) {
6828 ctx
.stage
= shaders
[i
]->info
.stage
;
6829 ctx
.output_mask
= 0;
6830 ctx
.tess_outputs_written
= 0;
6831 ctx
.num_output_clips
= shaders
[i
]->info
.clip_distance_array_size
;
6832 ctx
.num_output_culls
= shaders
[i
]->info
.cull_distance_array_size
;
6834 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6835 ctx
.gs_next_vertex
= ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "gs_next_vertex");
6836 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
6837 ctx
.abi
.load_inputs
= load_gs_input
;
6838 ctx
.abi
.emit_primitive
= visit_end_primitive
;
6839 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6840 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
6841 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
6842 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
6843 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
6844 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
6845 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
6846 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
6847 ctx
.abi
.load_tess_varyings
= load_tes_input
;
6848 ctx
.abi
.load_tess_coord
= load_tess_coord
;
6849 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
6850 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
6851 if (shader_info
->info
.vs
.needs_instance_id
) {
6852 if (ctx
.options
->key
.vs
.as_ls
) {
6853 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6854 MAX2(2, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6856 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6857 MAX2(1, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6860 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
6861 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
6865 emit_barrier(&ctx
.ac
, ctx
.stage
);
6867 ac_setup_rings(&ctx
);
6869 LLVMBasicBlockRef merge_block
;
6870 if (shader_count
>= 2) {
6871 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6872 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6873 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6875 LLVMValueRef count
= ac_build_bfe(&ctx
.ac
, ctx
.merged_wave_info
,
6876 LLVMConstInt(ctx
.ac
.i32
, 8 * i
, false),
6877 LLVMConstInt(ctx
.ac
.i32
, 8, false), false);
6878 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
6879 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
6880 thread_id
, count
, "");
6881 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
6883 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
6886 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
6887 handle_fs_inputs(&ctx
, shaders
[i
]);
6888 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
6889 handle_vs_inputs(&ctx
, shaders
[i
]);
6890 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
6891 prepare_gs_input_vgprs(&ctx
);
6893 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
6894 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
6896 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
], &ctx
);
6898 if (shader_count
>= 2) {
6899 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
6900 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
6903 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6904 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
6905 shaders
[i
]->info
.cull_distance_array_size
> 4;
6906 shader_info
->gs
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
6907 shader_info
->gs
.max_gsvs_emit_size
= shader_info
->gs
.gsvs_vertex_size
*
6908 shaders
[i
]->info
.gs
.vertices_out
;
6909 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6910 shader_info
->tcs
.outputs_written
= ctx
.tess_outputs_written
;
6911 shader_info
->tcs
.patch_outputs_written
= ctx
.tess_patch_outputs_written
;
6912 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&& ctx
.options
->key
.vs
.as_ls
) {
6913 shader_info
->vs
.outputs_written
= ctx
.tess_outputs_written
;
6917 LLVMBuildRetVoid(ctx
.builder
);
6919 if (options
->dump_preoptir
)
6920 ac_dump_module(ctx
.module
);
6922 ac_llvm_finalize_module(&ctx
);
6924 if (shader_count
== 1)
6925 ac_nir_eliminate_const_vs_outputs(&ctx
);
6930 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
6932 unsigned *retval
= (unsigned *)context
;
6933 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
6934 char *description
= LLVMGetDiagInfoDescription(di
);
6936 if (severity
== LLVMDSError
) {
6938 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
6942 LLVMDisposeMessage(description
);
6945 static unsigned ac_llvm_compile(LLVMModuleRef M
,
6946 struct ac_shader_binary
*binary
,
6947 LLVMTargetMachineRef tm
)
6949 unsigned retval
= 0;
6951 LLVMContextRef llvm_ctx
;
6952 LLVMMemoryBufferRef out_buffer
;
6953 unsigned buffer_size
;
6954 const char *buffer_data
;
6957 /* Setup Diagnostic Handler*/
6958 llvm_ctx
= LLVMGetModuleContext(M
);
6960 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
6964 mem_err
= LLVMTargetMachineEmitToMemoryBuffer(tm
, M
, LLVMObjectFile
,
6967 /* Process Errors/Warnings */
6969 fprintf(stderr
, "%s: %s", __FUNCTION__
, err
);
6975 /* Extract Shader Code*/
6976 buffer_size
= LLVMGetBufferSize(out_buffer
);
6977 buffer_data
= LLVMGetBufferStart(out_buffer
);
6979 ac_elf_read(buffer_data
, buffer_size
, binary
);
6982 LLVMDisposeMemoryBuffer(out_buffer
);
6988 static void ac_compile_llvm_module(LLVMTargetMachineRef tm
,
6989 LLVMModuleRef llvm_module
,
6990 struct ac_shader_binary
*binary
,
6991 struct ac_shader_config
*config
,
6992 struct ac_shader_variant_info
*shader_info
,
6993 gl_shader_stage stage
,
6994 bool dump_shader
, bool supports_spill
)
6997 ac_dump_module(llvm_module
);
6999 memset(binary
, 0, sizeof(*binary
));
7000 int v
= ac_llvm_compile(llvm_module
, binary
, tm
);
7002 fprintf(stderr
, "compile failed\n");
7006 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
7008 ac_shader_binary_read_config(binary
, config
, 0, supports_spill
);
7010 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
7011 LLVMDisposeModule(llvm_module
);
7012 LLVMContextDispose(ctx
);
7014 if (stage
== MESA_SHADER_FRAGMENT
) {
7015 shader_info
->num_input_vgprs
= 0;
7016 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
7017 shader_info
->num_input_vgprs
+= 2;
7018 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
7019 shader_info
->num_input_vgprs
+= 2;
7020 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
7021 shader_info
->num_input_vgprs
+= 2;
7022 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
7023 shader_info
->num_input_vgprs
+= 3;
7024 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
7025 shader_info
->num_input_vgprs
+= 2;
7026 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
7027 shader_info
->num_input_vgprs
+= 2;
7028 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
7029 shader_info
->num_input_vgprs
+= 2;
7030 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
7031 shader_info
->num_input_vgprs
+= 1;
7032 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
7033 shader_info
->num_input_vgprs
+= 1;
7034 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
7035 shader_info
->num_input_vgprs
+= 1;
7036 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
7037 shader_info
->num_input_vgprs
+= 1;
7038 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
7039 shader_info
->num_input_vgprs
+= 1;
7040 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
7041 shader_info
->num_input_vgprs
+= 1;
7042 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
7043 shader_info
->num_input_vgprs
+= 1;
7044 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
7045 shader_info
->num_input_vgprs
+= 1;
7046 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
7047 shader_info
->num_input_vgprs
+= 1;
7049 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
7051 /* +3 for scratch wave offset and VCC */
7052 config
->num_sgprs
= MAX2(config
->num_sgprs
,
7053 shader_info
->num_input_sgprs
+ 3);
7055 /* Enable 64-bit and 16-bit denormals, because there is no performance
7058 * If denormals are enabled, all floating-point output modifiers are
7061 * Don't enable denormals for 32-bit floats, because:
7062 * - Floating-point output modifiers would be ignored by the hw.
7063 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7064 * have to stop using those.
7065 * - SI & CI would be very slow.
7067 config
->float_mode
|= V_00B028_FP_64_DENORMS
;
7071 ac_fill_shader_info(struct ac_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct ac_nir_compiler_options
*options
)
7073 switch (nir
->info
.stage
) {
7074 case MESA_SHADER_COMPUTE
:
7075 for (int i
= 0; i
< 3; ++i
)
7076 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
7078 case MESA_SHADER_FRAGMENT
:
7079 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
7081 case MESA_SHADER_GEOMETRY
:
7082 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
7083 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
7084 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
7085 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
7087 case MESA_SHADER_TESS_EVAL
:
7088 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
7089 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
7090 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
7091 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
7092 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
7094 case MESA_SHADER_TESS_CTRL
:
7095 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
7097 case MESA_SHADER_VERTEX
:
7098 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
7099 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
7100 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7101 if (options
->key
.vs
.as_ls
)
7102 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
7109 void ac_compile_nir_shader(LLVMTargetMachineRef tm
,
7110 struct ac_shader_binary
*binary
,
7111 struct ac_shader_config
*config
,
7112 struct ac_shader_variant_info
*shader_info
,
7113 struct nir_shader
*const *nir
,
7115 const struct ac_nir_compiler_options
*options
,
7119 LLVMModuleRef llvm_module
= ac_translate_nir_to_llvm(tm
, nir
, nir_count
, shader_info
,
7122 ac_compile_llvm_module(tm
, llvm_module
, binary
, config
, shader_info
, nir
[0]->info
.stage
, dump_shader
, options
->supports_spill
);
7123 for (int i
= 0; i
< nir_count
; ++i
)
7124 ac_fill_shader_info(shader_info
, nir
[i
], options
);
7126 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7127 if (options
->chip_class
== GFX9
) {
7128 if (nir_count
== 2 &&
7129 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
7130 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
7136 ac_gs_copy_shader_emit(struct nir_to_llvm_context
*ctx
)
7138 LLVMValueRef args
[9];
7139 args
[0] = ctx
->gsvs_ring
;
7140 args
[1] = LLVMBuildMul(ctx
->builder
, ctx
->abi
.vertex_id
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
7141 args
[3] = ctx
->ac
.i32_0
;
7142 args
[4] = ctx
->ac
.i32_1
; /* OFFEN */
7143 args
[5] = ctx
->ac
.i32_0
; /* IDXEN */
7144 args
[6] = ctx
->ac
.i32_1
; /* GLC */
7145 args
[7] = ctx
->ac
.i32_1
; /* SLC */
7146 args
[8] = ctx
->ac
.i32_0
; /* TFE */
7150 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
7154 if (!(ctx
->output_mask
& (1ull << i
)))
7157 if (i
== VARYING_SLOT_CLIP_DIST0
) {
7158 /* unpack clip and cull from a single set of slots */
7159 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
7164 for (unsigned j
= 0; j
< length
; j
++) {
7166 args
[2] = LLVMConstInt(ctx
->ac
.i32
,
7168 ctx
->gs_max_out_vertices
* 16 * 4, false);
7170 value
= ac_build_intrinsic(&ctx
->ac
,
7171 "llvm.SI.buffer.load.dword.i32.i32",
7172 ctx
->ac
.i32
, args
, 9,
7173 AC_FUNC_ATTR_READONLY
|
7174 AC_FUNC_ATTR_LEGACY
);
7176 LLVMBuildStore(ctx
->builder
,
7177 ac_to_float(&ctx
->ac
, value
), ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)]);
7181 handle_vs_outputs_post(ctx
, false, &ctx
->shader_info
->vs
.outinfo
);
7184 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm
,
7185 struct nir_shader
*geom_shader
,
7186 struct ac_shader_binary
*binary
,
7187 struct ac_shader_config
*config
,
7188 struct ac_shader_variant_info
*shader_info
,
7189 const struct ac_nir_compiler_options
*options
,
7192 struct nir_to_llvm_context ctx
= {0};
7193 ctx
.context
= LLVMContextCreate();
7194 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
7195 ctx
.options
= options
;
7196 ctx
.shader_info
= shader_info
;
7198 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
7200 ctx
.ac
.module
= ctx
.module
;
7202 ctx
.is_gs_copy_shader
= true;
7203 LLVMSetTarget(ctx
.module
, "amdgcn--");
7205 enum ac_float_mode float_mode
=
7206 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
7207 AC_FLOAT_MODE_DEFAULT
;
7209 ctx
.builder
= ac_create_builder(ctx
.context
, float_mode
);
7210 ctx
.ac
.builder
= ctx
.builder
;
7211 ctx
.stage
= MESA_SHADER_VERTEX
;
7213 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
7215 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
7216 ac_setup_rings(&ctx
);
7218 ctx
.num_output_clips
= geom_shader
->info
.clip_distance_array_size
;
7219 ctx
.num_output_culls
= geom_shader
->info
.cull_distance_array_size
;
7221 struct ac_nir_context nir_ctx
= {};
7222 nir_ctx
.ac
= ctx
.ac
;
7223 nir_ctx
.abi
= &ctx
.abi
;
7225 nir_ctx
.nctx
= &ctx
;
7228 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
7229 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
7230 handle_shader_output_decl(&nir_ctx
, geom_shader
, variable
);
7233 ac_gs_copy_shader_emit(&ctx
);
7237 LLVMBuildRetVoid(ctx
.builder
);
7239 ac_llvm_finalize_module(&ctx
);
7241 ac_compile_llvm_module(tm
, ctx
.module
, binary
, config
, shader_info
,
7243 dump_shader
, options
->supports_spill
);