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[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct ac_nir_context {
49 struct ac_llvm_context ac;
50 struct ac_shader_abi *abi;
51
52 gl_shader_stage stage;
53
54 struct hash_table *defs;
55 struct hash_table *phis;
56 struct hash_table *vars;
57
58 LLVMValueRef main_function;
59 LLVMBasicBlockRef continue_block;
60 LLVMBasicBlockRef break_block;
61
62 int num_locals;
63 LLVMValueRef *locals;
64 };
65
66 struct radv_shader_context {
67 struct ac_llvm_context ac;
68 const struct ac_nir_compiler_options *options;
69 struct ac_shader_variant_info *shader_info;
70 struct ac_shader_abi abi;
71
72 unsigned max_workgroup_size;
73 LLVMContextRef context;
74 LLVMValueRef main_function;
75
76 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
77 LLVMValueRef ring_offsets;
78
79 LLVMValueRef vertex_buffers;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef ls_out_layout;
83 LLVMValueRef es2gs_offset;
84
85 LLVMValueRef tcs_offchip_layout;
86 LLVMValueRef tcs_out_offsets;
87 LLVMValueRef tcs_out_layout;
88 LLVMValueRef tcs_in_layout;
89 LLVMValueRef oc_lds;
90 LLVMValueRef merged_wave_info;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tes_rel_patch_id;
93 LLVMValueRef tes_u;
94 LLVMValueRef tes_v;
95
96 LLVMValueRef gsvs_ring_stride;
97 LLVMValueRef gsvs_num_entries;
98 LLVMValueRef gs2vs_offset;
99 LLVMValueRef gs_wave_id;
100 LLVMValueRef gs_vtx_offset[6];
101
102 LLVMValueRef esgs_ring;
103 LLVMValueRef gsvs_ring;
104 LLVMValueRef hs_ring_tess_offchip;
105 LLVMValueRef hs_ring_tess_factor;
106
107 LLVMValueRef sample_pos_offset;
108 LLVMValueRef persp_sample, persp_center, persp_centroid;
109 LLVMValueRef linear_sample, linear_center, linear_centroid;
110
111 gl_shader_stage stage;
112
113 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
114
115 uint64_t input_mask;
116 uint64_t output_mask;
117 uint8_t num_output_clips;
118 uint8_t num_output_culls;
119
120 bool is_gs_copy_shader;
121 LLVMValueRef gs_next_vertex;
122 unsigned gs_max_out_vertices;
123
124 unsigned tes_primitive_mode;
125 uint64_t tess_outputs_written;
126 uint64_t tess_patch_outputs_written;
127
128 uint32_t tcs_patch_outputs_read;
129 uint64_t tcs_outputs_read;
130 uint32_t tcs_vertices_per_patch;
131 };
132
133 static inline struct radv_shader_context *
134 radv_shader_context_from_abi(struct ac_shader_abi *abi)
135 {
136 struct radv_shader_context *ctx = NULL;
137 return container_of(abi, ctx, abi);
138 }
139
140 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
141 const nir_deref_var *deref,
142 enum ac_descriptor_type desc_type,
143 const nir_tex_instr *instr,
144 bool image, bool write);
145
146 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
147 {
148 return (index * 4) + chan;
149 }
150
151 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
152 {
153 /* handle patch indices separate */
154 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
155 return 0;
156 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
157 return 1;
158 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
159 return 2 + (slot - VARYING_SLOT_PATCH0);
160
161 if (slot == VARYING_SLOT_POS)
162 return 0;
163 if (slot == VARYING_SLOT_PSIZ)
164 return 1;
165 if (slot == VARYING_SLOT_CLIP_DIST0)
166 return 2;
167 /* 3 is reserved for clip dist as well */
168 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
169 return 4 + (slot - VARYING_SLOT_VAR0);
170 unreachable("illegal slot in get unique index\n");
171 }
172
173 static void set_llvm_calling_convention(LLVMValueRef func,
174 gl_shader_stage stage)
175 {
176 enum radeon_llvm_calling_convention calling_conv;
177
178 switch (stage) {
179 case MESA_SHADER_VERTEX:
180 case MESA_SHADER_TESS_EVAL:
181 calling_conv = RADEON_LLVM_AMDGPU_VS;
182 break;
183 case MESA_SHADER_GEOMETRY:
184 calling_conv = RADEON_LLVM_AMDGPU_GS;
185 break;
186 case MESA_SHADER_TESS_CTRL:
187 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
188 break;
189 case MESA_SHADER_FRAGMENT:
190 calling_conv = RADEON_LLVM_AMDGPU_PS;
191 break;
192 case MESA_SHADER_COMPUTE:
193 calling_conv = RADEON_LLVM_AMDGPU_CS;
194 break;
195 default:
196 unreachable("Unhandle shader type");
197 }
198
199 LLVMSetFunctionCallConv(func, calling_conv);
200 }
201
202 #define MAX_ARGS 23
203 struct arg_info {
204 LLVMTypeRef types[MAX_ARGS];
205 LLVMValueRef *assign[MAX_ARGS];
206 unsigned array_params_mask;
207 uint8_t count;
208 uint8_t sgpr_count;
209 uint8_t num_sgprs_used;
210 uint8_t num_vgprs_used;
211 };
212
213 enum ac_arg_regfile {
214 ARG_SGPR,
215 ARG_VGPR,
216 };
217
218 static void
219 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
220 LLVMValueRef *param_ptr)
221 {
222 assert(info->count < MAX_ARGS);
223
224 info->assign[info->count] = param_ptr;
225 info->types[info->count] = type;
226 info->count++;
227
228 if (regfile == ARG_SGPR) {
229 info->num_sgprs_used += ac_get_type_size(type) / 4;
230 info->sgpr_count++;
231 } else {
232 assert(regfile == ARG_VGPR);
233 info->num_vgprs_used += ac_get_type_size(type) / 4;
234 }
235 }
236
237 static inline void
238 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
239 {
240 info->array_params_mask |= (1 << info->count);
241 add_arg(info, ARG_SGPR, type, param_ptr);
242 }
243
244 static void assign_arguments(LLVMValueRef main_function,
245 struct arg_info *info)
246 {
247 unsigned i;
248 for (i = 0; i < info->count; i++) {
249 if (info->assign[i])
250 *info->assign[i] = LLVMGetParam(main_function, i);
251 }
252 }
253
254 static LLVMValueRef
255 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
256 LLVMBuilderRef builder, LLVMTypeRef *return_types,
257 unsigned num_return_elems,
258 struct arg_info *args,
259 unsigned max_workgroup_size,
260 bool unsafe_math)
261 {
262 LLVMTypeRef main_function_type, ret_type;
263 LLVMBasicBlockRef main_function_body;
264
265 if (num_return_elems)
266 ret_type = LLVMStructTypeInContext(ctx, return_types,
267 num_return_elems, true);
268 else
269 ret_type = LLVMVoidTypeInContext(ctx);
270
271 /* Setup the function */
272 main_function_type =
273 LLVMFunctionType(ret_type, args->types, args->count, 0);
274 LLVMValueRef main_function =
275 LLVMAddFunction(module, "main", main_function_type);
276 main_function_body =
277 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
278 LLVMPositionBuilderAtEnd(builder, main_function_body);
279
280 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
281 for (unsigned i = 0; i < args->sgpr_count; ++i) {
282 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
283
284 if (args->array_params_mask & (1 << i)) {
285 LLVMValueRef P = LLVMGetParam(main_function, i);
286 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
287 ac_add_attr_dereferenceable(P, UINT64_MAX);
288 }
289 }
290
291 if (max_workgroup_size) {
292 ac_llvm_add_target_dep_function_attr(main_function,
293 "amdgpu-max-work-group-size",
294 max_workgroup_size);
295 }
296 if (unsafe_math) {
297 /* These were copied from some LLVM test. */
298 LLVMAddTargetDependentFunctionAttr(main_function,
299 "less-precise-fpmad",
300 "true");
301 LLVMAddTargetDependentFunctionAttr(main_function,
302 "no-infs-fp-math",
303 "true");
304 LLVMAddTargetDependentFunctionAttr(main_function,
305 "no-nans-fp-math",
306 "true");
307 LLVMAddTargetDependentFunctionAttr(main_function,
308 "unsafe-fp-math",
309 "true");
310 LLVMAddTargetDependentFunctionAttr(main_function,
311 "no-signed-zeros-fp-math",
312 "true");
313 }
314 return main_function;
315 }
316
317 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
318 LLVMValueRef param, unsigned rshift,
319 unsigned bitwidth)
320 {
321 LLVMValueRef value = param;
322 if (rshift)
323 value = LLVMBuildLShr(ctx->builder, value,
324 LLVMConstInt(ctx->i32, rshift, false), "");
325
326 if (rshift + bitwidth < 32) {
327 unsigned mask = (1 << bitwidth) - 1;
328 value = LLVMBuildAnd(ctx->builder, value,
329 LLVMConstInt(ctx->i32, mask, false), "");
330 }
331 return value;
332 }
333
334 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
335 {
336 switch (ctx->stage) {
337 case MESA_SHADER_TESS_CTRL:
338 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
339 case MESA_SHADER_TESS_EVAL:
340 return ctx->tes_rel_patch_id;
341 break;
342 default:
343 unreachable("Illegal stage");
344 }
345 }
346
347 /* Tessellation shaders pass outputs to the next shader using LDS.
348 *
349 * LS outputs = TCS inputs
350 * TCS outputs = TES inputs
351 *
352 * The LDS layout is:
353 * - TCS inputs for patch 0
354 * - TCS inputs for patch 1
355 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
356 * - ...
357 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
358 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
359 * - TCS outputs for patch 1
360 * - Per-patch TCS outputs for patch 1
361 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
362 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
363 * - ...
364 *
365 * All three shaders VS(LS), TCS, TES share the same LDS space.
366 */
367 static LLVMValueRef
368 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
369 {
370 if (ctx->stage == MESA_SHADER_VERTEX)
371 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
372 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
373 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
374 else {
375 assert(0);
376 return NULL;
377 }
378 }
379
380 static LLVMValueRef
381 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
382 {
383 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
384 }
385
386 static LLVMValueRef
387 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
388 {
389 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
390 }
391
392 static LLVMValueRef
393 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
394 {
395 return LLVMBuildMul(ctx->ac.builder,
396 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
397 LLVMConstInt(ctx->ac.i32, 4, false), "");
398 }
399
400 static LLVMValueRef
401 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
402 {
403 return LLVMBuildMul(ctx->ac.builder,
404 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
405 LLVMConstInt(ctx->ac.i32, 4, false), "");
406 }
407
408 static LLVMValueRef
409 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
410 {
411 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
412 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
413
414 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
415 }
416
417 static LLVMValueRef
418 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
419 {
420 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
421 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
422 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
423
424 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
425 LLVMBuildMul(ctx->ac.builder, patch_stride,
426 rel_patch_id, ""),
427 "");
428 }
429
430 static LLVMValueRef
431 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
432 {
433 LLVMValueRef patch0_patch_data_offset =
434 get_tcs_out_patch0_patch_data_offset(ctx);
435 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
436 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
437
438 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
439 LLVMBuildMul(ctx->ac.builder, patch_stride,
440 rel_patch_id, ""),
441 "");
442 }
443
444 static void
445 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
446 uint32_t indirect_offset)
447 {
448 ud_info->sgpr_idx = *sgpr_idx;
449 ud_info->num_sgprs = num_sgprs;
450 ud_info->indirect = indirect_offset > 0;
451 ud_info->indirect_offset = indirect_offset;
452 *sgpr_idx += num_sgprs;
453 }
454
455 static void
456 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
457 uint8_t num_sgprs)
458 {
459 struct ac_userdata_info *ud_info =
460 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
461 assert(ud_info);
462
463 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
464 }
465
466 static void
467 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
468 uint32_t indirect_offset)
469 {
470 struct ac_userdata_info *ud_info =
471 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
472 assert(ud_info);
473
474 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
475 }
476
477 struct user_sgpr_info {
478 bool need_ring_offsets;
479 uint8_t sgpr_count;
480 bool indirect_all_descriptor_sets;
481 };
482
483 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
484 gl_shader_stage stage)
485 {
486 switch (stage) {
487 case MESA_SHADER_VERTEX:
488 if (ctx->shader_info->info.needs_multiview_view_index ||
489 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
490 return true;
491 break;
492 case MESA_SHADER_TESS_EVAL:
493 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
494 return true;
495 break;
496 case MESA_SHADER_GEOMETRY:
497 case MESA_SHADER_TESS_CTRL:
498 if (ctx->shader_info->info.needs_multiview_view_index)
499 return true;
500 break;
501 default:
502 break;
503 }
504 return false;
505 }
506
507 static uint8_t
508 count_vs_user_sgprs(struct radv_shader_context *ctx)
509 {
510 uint8_t count = 0;
511
512 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
513 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
514
515 return count;
516 }
517
518 static void allocate_user_sgprs(struct radv_shader_context *ctx,
519 gl_shader_stage stage,
520 bool has_previous_stage,
521 gl_shader_stage previous_stage,
522 bool needs_view_index,
523 struct user_sgpr_info *user_sgpr_info)
524 {
525 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
526
527 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
528 if (stage == MESA_SHADER_GEOMETRY ||
529 stage == MESA_SHADER_VERTEX ||
530 stage == MESA_SHADER_TESS_CTRL ||
531 stage == MESA_SHADER_TESS_EVAL ||
532 ctx->is_gs_copy_shader)
533 user_sgpr_info->need_ring_offsets = true;
534
535 if (stage == MESA_SHADER_FRAGMENT &&
536 ctx->shader_info->info.ps.needs_sample_positions)
537 user_sgpr_info->need_ring_offsets = true;
538
539 /* 2 user sgprs will nearly always be allocated for scratch/rings */
540 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
541 user_sgpr_info->sgpr_count += 2;
542 }
543
544 switch (stage) {
545 case MESA_SHADER_COMPUTE:
546 if (ctx->shader_info->info.cs.uses_grid_size)
547 user_sgpr_info->sgpr_count += 3;
548 break;
549 case MESA_SHADER_FRAGMENT:
550 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
551 break;
552 case MESA_SHADER_VERTEX:
553 if (!ctx->is_gs_copy_shader)
554 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
555 if (ctx->options->key.vs.as_ls)
556 user_sgpr_info->sgpr_count++;
557 break;
558 case MESA_SHADER_TESS_CTRL:
559 if (has_previous_stage) {
560 if (previous_stage == MESA_SHADER_VERTEX)
561 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
562 user_sgpr_info->sgpr_count++;
563 }
564 user_sgpr_info->sgpr_count += 4;
565 break;
566 case MESA_SHADER_TESS_EVAL:
567 user_sgpr_info->sgpr_count += 1;
568 break;
569 case MESA_SHADER_GEOMETRY:
570 if (has_previous_stage) {
571 if (previous_stage == MESA_SHADER_VERTEX) {
572 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
573 } else {
574 user_sgpr_info->sgpr_count++;
575 }
576 }
577 user_sgpr_info->sgpr_count += 2;
578 break;
579 default:
580 break;
581 }
582
583 if (needs_view_index)
584 user_sgpr_info->sgpr_count++;
585
586 if (ctx->shader_info->info.loads_push_constants)
587 user_sgpr_info->sgpr_count += 2;
588
589 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
590 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
591
592 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
593 user_sgpr_info->sgpr_count += 2;
594 user_sgpr_info->indirect_all_descriptor_sets = true;
595 } else {
596 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
597 }
598 }
599
600 static void
601 declare_global_input_sgprs(struct radv_shader_context *ctx,
602 gl_shader_stage stage,
603 bool has_previous_stage,
604 gl_shader_stage previous_stage,
605 const struct user_sgpr_info *user_sgpr_info,
606 struct arg_info *args,
607 LLVMValueRef *desc_sets)
608 {
609 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
610 unsigned num_sets = ctx->options->layout ?
611 ctx->options->layout->num_sets : 0;
612 unsigned stage_mask = 1 << stage;
613
614 if (has_previous_stage)
615 stage_mask |= 1 << previous_stage;
616
617 /* 1 for each descriptor set */
618 if (!user_sgpr_info->indirect_all_descriptor_sets) {
619 for (unsigned i = 0; i < num_sets; ++i) {
620 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
621 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
622 add_array_arg(args, type,
623 &ctx->descriptor_sets[i]);
624 }
625 }
626 } else {
627 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
628 }
629
630 if (ctx->shader_info->info.loads_push_constants) {
631 /* 1 for push constants and dynamic descriptors */
632 add_array_arg(args, type, &ctx->abi.push_constants);
633 }
634 }
635
636 static void
637 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
638 gl_shader_stage stage,
639 bool has_previous_stage,
640 gl_shader_stage previous_stage,
641 struct arg_info *args)
642 {
643 if (!ctx->is_gs_copy_shader &&
644 (stage == MESA_SHADER_VERTEX ||
645 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
646 if (ctx->shader_info->info.vs.has_vertex_buffers) {
647 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
648 &ctx->vertex_buffers);
649 }
650 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
651 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
652 if (ctx->shader_info->info.vs.needs_draw_id) {
653 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
654 }
655 }
656 }
657
658 static void
659 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
660 {
661 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
662 if (!ctx->is_gs_copy_shader) {
663 if (ctx->options->key.vs.as_ls) {
664 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
665 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
666 } else {
667 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
668 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
669 }
670 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
671 }
672 }
673
674 static void
675 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
676 {
677 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
678 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
679 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
680 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
681 }
682
683 static void
684 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
685 bool has_previous_stage, gl_shader_stage previous_stage,
686 const struct user_sgpr_info *user_sgpr_info,
687 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
688 {
689 unsigned num_sets = ctx->options->layout ?
690 ctx->options->layout->num_sets : 0;
691 unsigned stage_mask = 1 << stage;
692
693 if (has_previous_stage)
694 stage_mask |= 1 << previous_stage;
695
696 if (!user_sgpr_info->indirect_all_descriptor_sets) {
697 for (unsigned i = 0; i < num_sets; ++i) {
698 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
699 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
700 set_loc_desc(ctx, i, user_sgpr_idx, 0);
701 } else
702 ctx->descriptor_sets[i] = NULL;
703 }
704 } else {
705 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
706 user_sgpr_idx, 2);
707
708 for (unsigned i = 0; i < num_sets; ++i) {
709 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
710 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
711 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
712 ctx->descriptor_sets[i] =
713 ac_build_load_to_sgpr(&ctx->ac,
714 desc_sets,
715 LLVMConstInt(ctx->ac.i32, i, false));
716
717 } else
718 ctx->descriptor_sets[i] = NULL;
719 }
720 ctx->shader_info->need_indirect_descriptor_sets = true;
721 }
722
723 if (ctx->shader_info->info.loads_push_constants) {
724 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
725 }
726 }
727
728 static void
729 set_vs_specific_input_locs(struct radv_shader_context *ctx,
730 gl_shader_stage stage, bool has_previous_stage,
731 gl_shader_stage previous_stage,
732 uint8_t *user_sgpr_idx)
733 {
734 if (!ctx->is_gs_copy_shader &&
735 (stage == MESA_SHADER_VERTEX ||
736 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
737 if (ctx->shader_info->info.vs.has_vertex_buffers) {
738 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
739 user_sgpr_idx, 2);
740 }
741
742 unsigned vs_num = 2;
743 if (ctx->shader_info->info.vs.needs_draw_id)
744 vs_num++;
745
746 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
747 user_sgpr_idx, vs_num);
748 }
749 }
750
751 static void create_function(struct radv_shader_context *ctx,
752 gl_shader_stage stage,
753 bool has_previous_stage,
754 gl_shader_stage previous_stage)
755 {
756 uint8_t user_sgpr_idx;
757 struct user_sgpr_info user_sgpr_info;
758 struct arg_info args = {};
759 LLVMValueRef desc_sets;
760 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
761 allocate_user_sgprs(ctx, stage, has_previous_stage,
762 previous_stage, needs_view_index, &user_sgpr_info);
763
764 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
765 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
766 &ctx->ring_offsets);
767 }
768
769 switch (stage) {
770 case MESA_SHADER_COMPUTE:
771 declare_global_input_sgprs(ctx, stage, has_previous_stage,
772 previous_stage, &user_sgpr_info,
773 &args, &desc_sets);
774
775 if (ctx->shader_info->info.cs.uses_grid_size) {
776 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
777 &ctx->abi.num_work_groups);
778 }
779
780 for (int i = 0; i < 3; i++) {
781 ctx->abi.workgroup_ids[i] = NULL;
782 if (ctx->shader_info->info.cs.uses_block_id[i]) {
783 add_arg(&args, ARG_SGPR, ctx->ac.i32,
784 &ctx->abi.workgroup_ids[i]);
785 }
786 }
787
788 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
789 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
790 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
791 &ctx->abi.local_invocation_ids);
792 break;
793 case MESA_SHADER_VERTEX:
794 declare_global_input_sgprs(ctx, stage, has_previous_stage,
795 previous_stage, &user_sgpr_info,
796 &args, &desc_sets);
797 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
798 previous_stage, &args);
799
800 if (needs_view_index)
801 add_arg(&args, ARG_SGPR, ctx->ac.i32,
802 &ctx->abi.view_index);
803 if (ctx->options->key.vs.as_es)
804 add_arg(&args, ARG_SGPR, ctx->ac.i32,
805 &ctx->es2gs_offset);
806 else if (ctx->options->key.vs.as_ls)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32,
808 &ctx->ls_out_layout);
809
810 declare_vs_input_vgprs(ctx, &args);
811 break;
812 case MESA_SHADER_TESS_CTRL:
813 if (has_previous_stage) {
814 // First 6 system regs
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->merged_wave_info);
818 add_arg(&args, ARG_SGPR, ctx->ac.i32,
819 &ctx->tess_factor_offset);
820
821 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
822 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
823 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
824
825 declare_global_input_sgprs(ctx, stage,
826 has_previous_stage,
827 previous_stage,
828 &user_sgpr_info, &args,
829 &desc_sets);
830 declare_vs_specific_input_sgprs(ctx, stage,
831 has_previous_stage,
832 previous_stage, &args);
833
834 add_arg(&args, ARG_SGPR, ctx->ac.i32,
835 &ctx->ls_out_layout);
836
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->tcs_offchip_layout);
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->tcs_out_offsets);
841 add_arg(&args, ARG_SGPR, ctx->ac.i32,
842 &ctx->tcs_out_layout);
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->tcs_in_layout);
845 if (needs_view_index)
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->abi.view_index);
848
849 add_arg(&args, ARG_VGPR, ctx->ac.i32,
850 &ctx->abi.tcs_patch_id);
851 add_arg(&args, ARG_VGPR, ctx->ac.i32,
852 &ctx->abi.tcs_rel_ids);
853
854 declare_vs_input_vgprs(ctx, &args);
855 } else {
856 declare_global_input_sgprs(ctx, stage,
857 has_previous_stage,
858 previous_stage,
859 &user_sgpr_info, &args,
860 &desc_sets);
861
862 add_arg(&args, ARG_SGPR, ctx->ac.i32,
863 &ctx->tcs_offchip_layout);
864 add_arg(&args, ARG_SGPR, ctx->ac.i32,
865 &ctx->tcs_out_offsets);
866 add_arg(&args, ARG_SGPR, ctx->ac.i32,
867 &ctx->tcs_out_layout);
868 add_arg(&args, ARG_SGPR, ctx->ac.i32,
869 &ctx->tcs_in_layout);
870 if (needs_view_index)
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->abi.view_index);
873
874 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tess_factor_offset);
877 add_arg(&args, ARG_VGPR, ctx->ac.i32,
878 &ctx->abi.tcs_patch_id);
879 add_arg(&args, ARG_VGPR, ctx->ac.i32,
880 &ctx->abi.tcs_rel_ids);
881 }
882 break;
883 case MESA_SHADER_TESS_EVAL:
884 declare_global_input_sgprs(ctx, stage, has_previous_stage,
885 previous_stage, &user_sgpr_info,
886 &args, &desc_sets);
887
888 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
889 if (needs_view_index)
890 add_arg(&args, ARG_SGPR, ctx->ac.i32,
891 &ctx->abi.view_index);
892
893 if (ctx->options->key.tes.as_es) {
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
895 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
896 add_arg(&args, ARG_SGPR, ctx->ac.i32,
897 &ctx->es2gs_offset);
898 } else {
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
900 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
901 }
902 declare_tes_input_vgprs(ctx, &args);
903 break;
904 case MESA_SHADER_GEOMETRY:
905 if (has_previous_stage) {
906 // First 6 system regs
907 add_arg(&args, ARG_SGPR, ctx->ac.i32,
908 &ctx->gs2vs_offset);
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->merged_wave_info);
911 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
912
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
915 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
916
917 declare_global_input_sgprs(ctx, stage,
918 has_previous_stage,
919 previous_stage,
920 &user_sgpr_info, &args,
921 &desc_sets);
922
923 if (previous_stage == MESA_SHADER_TESS_EVAL) {
924 add_arg(&args, ARG_SGPR, ctx->ac.i32,
925 &ctx->tcs_offchip_layout);
926 } else {
927 declare_vs_specific_input_sgprs(ctx, stage,
928 has_previous_stage,
929 previous_stage,
930 &args);
931 }
932
933 add_arg(&args, ARG_SGPR, ctx->ac.i32,
934 &ctx->gsvs_ring_stride);
935 add_arg(&args, ARG_SGPR, ctx->ac.i32,
936 &ctx->gsvs_num_entries);
937 if (needs_view_index)
938 add_arg(&args, ARG_SGPR, ctx->ac.i32,
939 &ctx->abi.view_index);
940
941 add_arg(&args, ARG_VGPR, ctx->ac.i32,
942 &ctx->gs_vtx_offset[0]);
943 add_arg(&args, ARG_VGPR, ctx->ac.i32,
944 &ctx->gs_vtx_offset[2]);
945 add_arg(&args, ARG_VGPR, ctx->ac.i32,
946 &ctx->abi.gs_prim_id);
947 add_arg(&args, ARG_VGPR, ctx->ac.i32,
948 &ctx->abi.gs_invocation_id);
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->gs_vtx_offset[4]);
951
952 if (previous_stage == MESA_SHADER_VERTEX) {
953 declare_vs_input_vgprs(ctx, &args);
954 } else {
955 declare_tes_input_vgprs(ctx, &args);
956 }
957 } else {
958 declare_global_input_sgprs(ctx, stage,
959 has_previous_stage,
960 previous_stage,
961 &user_sgpr_info, &args,
962 &desc_sets);
963
964 add_arg(&args, ARG_SGPR, ctx->ac.i32,
965 &ctx->gsvs_ring_stride);
966 add_arg(&args, ARG_SGPR, ctx->ac.i32,
967 &ctx->gsvs_num_entries);
968 if (needs_view_index)
969 add_arg(&args, ARG_SGPR, ctx->ac.i32,
970 &ctx->abi.view_index);
971
972 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
973 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
974 add_arg(&args, ARG_VGPR, ctx->ac.i32,
975 &ctx->gs_vtx_offset[0]);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[1]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->abi.gs_prim_id);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->gs_vtx_offset[2]);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[3]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[4]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[5]);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->abi.gs_invocation_id);
990 }
991 break;
992 case MESA_SHADER_FRAGMENT:
993 declare_global_input_sgprs(ctx, stage, has_previous_stage,
994 previous_stage, &user_sgpr_info,
995 &args, &desc_sets);
996
997 if (ctx->shader_info->info.ps.needs_sample_positions)
998 add_arg(&args, ARG_SGPR, ctx->ac.i32,
999 &ctx->sample_pos_offset);
1000
1001 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1002 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1003 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1005 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1009 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1010 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1014 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1018 break;
1019 default:
1020 unreachable("Shader stage not implemented");
1021 }
1022
1023 ctx->main_function = create_llvm_function(
1024 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1025 ctx->max_workgroup_size,
1026 ctx->options->unsafe_math);
1027 set_llvm_calling_convention(ctx->main_function, stage);
1028
1029
1030 ctx->shader_info->num_input_vgprs = 0;
1031 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1032
1033 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1034
1035 if (ctx->stage != MESA_SHADER_FRAGMENT)
1036 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1037
1038 assign_arguments(ctx->main_function, &args);
1039
1040 user_sgpr_idx = 0;
1041
1042 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1043 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1044 &user_sgpr_idx, 2);
1045 if (ctx->options->supports_spill) {
1046 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1047 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1048 NULL, 0, AC_FUNC_ATTR_READNONE);
1049 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1050 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1051 }
1052 }
1053
1054 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1055 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1056 if (has_previous_stage)
1057 user_sgpr_idx = 0;
1058
1059 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1060 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1061
1062 switch (stage) {
1063 case MESA_SHADER_COMPUTE:
1064 if (ctx->shader_info->info.cs.uses_grid_size) {
1065 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1066 &user_sgpr_idx, 3);
1067 }
1068 break;
1069 case MESA_SHADER_VERTEX:
1070 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1071 previous_stage, &user_sgpr_idx);
1072 if (ctx->abi.view_index)
1073 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1074 if (ctx->options->key.vs.as_ls) {
1075 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1076 &user_sgpr_idx, 1);
1077 }
1078 break;
1079 case MESA_SHADER_TESS_CTRL:
1080 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1081 previous_stage, &user_sgpr_idx);
1082 if (has_previous_stage)
1083 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1084 &user_sgpr_idx, 1);
1085 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1086 if (ctx->abi.view_index)
1087 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1088 break;
1089 case MESA_SHADER_TESS_EVAL:
1090 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1091 if (ctx->abi.view_index)
1092 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1093 break;
1094 case MESA_SHADER_GEOMETRY:
1095 if (has_previous_stage) {
1096 if (previous_stage == MESA_SHADER_VERTEX)
1097 set_vs_specific_input_locs(ctx, stage,
1098 has_previous_stage,
1099 previous_stage,
1100 &user_sgpr_idx);
1101 else
1102 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1103 &user_sgpr_idx, 1);
1104 }
1105 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1106 &user_sgpr_idx, 2);
1107 if (ctx->abi.view_index)
1108 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1109 break;
1110 case MESA_SHADER_FRAGMENT:
1111 if (ctx->shader_info->info.ps.needs_sample_positions) {
1112 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1113 &user_sgpr_idx, 1);
1114 }
1115 break;
1116 default:
1117 unreachable("Shader stage not implemented");
1118 }
1119
1120 if (stage == MESA_SHADER_TESS_CTRL ||
1121 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1122 /* GFX9 has the ESGS ring buffer in LDS. */
1123 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1124 ac_declare_lds_as_pointer(&ctx->ac);
1125 }
1126
1127 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1128 }
1129
1130 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1131 LLVMValueRef value, unsigned count)
1132 {
1133 unsigned num_components = ac_get_llvm_num_components(value);
1134 if (count == num_components)
1135 return value;
1136
1137 LLVMValueRef masks[] = {
1138 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1139 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1140
1141 if (count == 1)
1142 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1143 "");
1144
1145 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1146 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1147 }
1148
1149 static void
1150 build_store_values_extended(struct ac_llvm_context *ac,
1151 LLVMValueRef *values,
1152 unsigned value_count,
1153 unsigned value_stride,
1154 LLVMValueRef vec)
1155 {
1156 LLVMBuilderRef builder = ac->builder;
1157 unsigned i;
1158
1159 for (i = 0; i < value_count; i++) {
1160 LLVMValueRef ptr = values[i * value_stride];
1161 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1162 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1163 LLVMBuildStore(builder, value, ptr);
1164 }
1165 }
1166
1167 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1168 const nir_ssa_def *def)
1169 {
1170 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1171 if (def->num_components > 1) {
1172 type = LLVMVectorType(type, def->num_components);
1173 }
1174 return type;
1175 }
1176
1177 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1178 {
1179 assert(src.is_ssa);
1180 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1181 return (LLVMValueRef)entry->data;
1182 }
1183
1184 static LLVMValueRef
1185 get_memory_ptr(struct ac_nir_context *ctx, nir_src src)
1186 {
1187 LLVMValueRef ptr = get_src(ctx, src);
1188 ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ac.lds, &ptr, 1, "");
1189 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1190
1191 return LLVMBuildBitCast(ctx->ac.builder, ptr,
1192 LLVMPointerType(ctx->ac.i32, addr_space), "");
1193 }
1194
1195 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1196 const struct nir_block *b)
1197 {
1198 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1199 return (LLVMBasicBlockRef)entry->data;
1200 }
1201
1202 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1203 nir_alu_src src,
1204 unsigned num_components)
1205 {
1206 LLVMValueRef value = get_src(ctx, src.src);
1207 bool need_swizzle = false;
1208
1209 assert(value);
1210 unsigned src_components = ac_get_llvm_num_components(value);
1211 for (unsigned i = 0; i < num_components; ++i) {
1212 assert(src.swizzle[i] < src_components);
1213 if (src.swizzle[i] != i)
1214 need_swizzle = true;
1215 }
1216
1217 if (need_swizzle || num_components != src_components) {
1218 LLVMValueRef masks[] = {
1219 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1220 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1221 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1222 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1223
1224 if (src_components > 1 && num_components == 1) {
1225 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1226 masks[0], "");
1227 } else if (src_components == 1 && num_components > 1) {
1228 LLVMValueRef values[] = {value, value, value, value};
1229 value = ac_build_gather_values(&ctx->ac, values, num_components);
1230 } else {
1231 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1232 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1233 swizzle, "");
1234 }
1235 }
1236 assert(!src.negate);
1237 assert(!src.abs);
1238 return value;
1239 }
1240
1241 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1242 LLVMIntPredicate pred, LLVMValueRef src0,
1243 LLVMValueRef src1)
1244 {
1245 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1246 return LLVMBuildSelect(ctx->builder, result,
1247 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1248 ctx->i32_0, "");
1249 }
1250
1251 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1252 LLVMRealPredicate pred, LLVMValueRef src0,
1253 LLVMValueRef src1)
1254 {
1255 LLVMValueRef result;
1256 src0 = ac_to_float(ctx, src0);
1257 src1 = ac_to_float(ctx, src1);
1258 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1259 return LLVMBuildSelect(ctx->builder, result,
1260 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1261 ctx->i32_0, "");
1262 }
1263
1264 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1265 const char *intrin,
1266 LLVMTypeRef result_type,
1267 LLVMValueRef src0)
1268 {
1269 char name[64];
1270 LLVMValueRef params[] = {
1271 ac_to_float(ctx, src0),
1272 };
1273
1274 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1275 ac_get_elem_bits(ctx, result_type));
1276 assert(length < sizeof(name));
1277 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1278 }
1279
1280 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1281 const char *intrin,
1282 LLVMTypeRef result_type,
1283 LLVMValueRef src0, LLVMValueRef src1)
1284 {
1285 char name[64];
1286 LLVMValueRef params[] = {
1287 ac_to_float(ctx, src0),
1288 ac_to_float(ctx, src1),
1289 };
1290
1291 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1292 ac_get_elem_bits(ctx, result_type));
1293 assert(length < sizeof(name));
1294 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1295 }
1296
1297 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1298 const char *intrin,
1299 LLVMTypeRef result_type,
1300 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1301 {
1302 char name[64];
1303 LLVMValueRef params[] = {
1304 ac_to_float(ctx, src0),
1305 ac_to_float(ctx, src1),
1306 ac_to_float(ctx, src2),
1307 };
1308
1309 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1310 ac_get_elem_bits(ctx, result_type));
1311 assert(length < sizeof(name));
1312 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1313 }
1314
1315 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1316 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1317 {
1318 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1319 ctx->i32_0, "");
1320 return LLVMBuildSelect(ctx->builder, v, ac_to_integer(ctx, src1),
1321 ac_to_integer(ctx, src2), "");
1322 }
1323
1324 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1325 LLVMIntPredicate pred,
1326 LLVMValueRef src0, LLVMValueRef src1)
1327 {
1328 return LLVMBuildSelect(ctx->builder,
1329 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1330 src0,
1331 src1, "");
1332
1333 }
1334 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1335 LLVMValueRef src0)
1336 {
1337 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1338 LLVMBuildNeg(ctx->builder, src0, ""));
1339 }
1340
1341 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1342 const char *intrin,
1343 LLVMValueRef src0, LLVMValueRef src1)
1344 {
1345 LLVMTypeRef ret_type;
1346 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1347 LLVMValueRef res;
1348 LLVMValueRef params[] = { src0, src1 };
1349 ret_type = LLVMStructTypeInContext(ctx->context, types,
1350 2, true);
1351
1352 res = ac_build_intrinsic(ctx, intrin, ret_type,
1353 params, 2, AC_FUNC_ATTR_READNONE);
1354
1355 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1356 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1357 return res;
1358 }
1359
1360 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1361 LLVMValueRef src0)
1362 {
1363 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1364 }
1365
1366 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1367 LLVMValueRef src0)
1368 {
1369 src0 = ac_to_float(ctx, src0);
1370 LLVMValueRef zero = LLVMConstNull(LLVMTypeOf(src0));
1371 return LLVMBuildSExt(ctx->builder,
1372 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, zero, ""),
1373 ctx->i32, "");
1374 }
1375
1376 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1377 LLVMValueRef src0,
1378 unsigned bitsize)
1379 {
1380 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1381
1382 if (bitsize == 32)
1383 return result;
1384
1385 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1386 }
1387
1388 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1389 LLVMValueRef src0)
1390 {
1391 LLVMValueRef zero = LLVMConstNull(LLVMTypeOf(src0));
1392 return LLVMBuildSExt(ctx->builder,
1393 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, zero, ""),
1394 ctx->i32, "");
1395 }
1396
1397 static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx,
1398 LLVMValueRef src0)
1399 {
1400 LLVMValueRef result;
1401 LLVMValueRef cond = NULL;
1402
1403 src0 = ac_to_float(ctx, src0);
1404 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1405
1406 if (ctx->chip_class >= VI) {
1407 LLVMValueRef args[2];
1408 /* Check if the result is a denormal - and flush to 0 if so. */
1409 args[0] = result;
1410 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1411 cond = ac_build_intrinsic(ctx, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1412 }
1413
1414 /* need to convert back up to f32 */
1415 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1416
1417 if (ctx->chip_class >= VI)
1418 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1419 else {
1420 /* for SI/CIK */
1421 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1422 * so compare the result and flush to 0 if it's smaller.
1423 */
1424 LLVMValueRef temp, cond2;
1425 temp = emit_intrin_1f_param(ctx, "llvm.fabs", ctx->f32, result);
1426 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1427 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1428 temp, "");
1429 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1430 temp, ctx->f32_0, "");
1431 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1432 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1433 }
1434 return result;
1435 }
1436
1437 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1438 LLVMValueRef src0, LLVMValueRef src1)
1439 {
1440 LLVMValueRef dst64, result;
1441 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1442 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1443
1444 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1445 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1446 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1447 return result;
1448 }
1449
1450 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1451 LLVMValueRef src0, LLVMValueRef src1)
1452 {
1453 LLVMValueRef dst64, result;
1454 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1455 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1456
1457 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1458 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1459 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1460 return result;
1461 }
1462
1463 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1464 bool is_signed,
1465 const LLVMValueRef srcs[3])
1466 {
1467 LLVMValueRef result;
1468 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1469
1470 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1471 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1472 return result;
1473 }
1474
1475 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1476 LLVMValueRef src0, LLVMValueRef src1,
1477 LLVMValueRef src2, LLVMValueRef src3)
1478 {
1479 LLVMValueRef bfi_args[3], result;
1480
1481 bfi_args[0] = LLVMBuildShl(ctx->builder,
1482 LLVMBuildSub(ctx->builder,
1483 LLVMBuildShl(ctx->builder,
1484 ctx->i32_1,
1485 src3, ""),
1486 ctx->i32_1, ""),
1487 src2, "");
1488 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1489 bfi_args[2] = src0;
1490
1491 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1492
1493 /* Calculate:
1494 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1495 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1496 */
1497 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1498 LLVMBuildAnd(ctx->builder, bfi_args[0],
1499 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1500
1501 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1502 return result;
1503 }
1504
1505 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1506 LLVMValueRef src0)
1507 {
1508 LLVMValueRef comp[2];
1509
1510 src0 = ac_to_float(ctx, src0);
1511 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1512 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1513
1514 return ac_build_cvt_pkrtz_f16(ctx, comp);
1515 }
1516
1517 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1518 LLVMValueRef src0)
1519 {
1520 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1521 LLVMValueRef temps[2], result, val;
1522 int i;
1523
1524 for (i = 0; i < 2; i++) {
1525 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1526 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1527 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1528 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1529 }
1530
1531 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1532 ctx->i32_0, "");
1533 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1534 ctx->i32_1, "");
1535 return result;
1536 }
1537
1538 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1539 nir_op op,
1540 LLVMValueRef src0)
1541 {
1542 unsigned mask;
1543 int idx;
1544 LLVMValueRef result;
1545
1546 if (op == nir_op_fddx_fine)
1547 mask = AC_TID_MASK_LEFT;
1548 else if (op == nir_op_fddy_fine)
1549 mask = AC_TID_MASK_TOP;
1550 else
1551 mask = AC_TID_MASK_TOP_LEFT;
1552
1553 /* for DDX we want to next X pixel, DDY next Y pixel. */
1554 if (op == nir_op_fddx_fine ||
1555 op == nir_op_fddx_coarse ||
1556 op == nir_op_fddx)
1557 idx = 1;
1558 else
1559 idx = 2;
1560
1561 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1562 return result;
1563 }
1564
1565 /*
1566 * this takes an I,J coordinate pair,
1567 * and works out the X and Y derivatives.
1568 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1569 */
1570 static LLVMValueRef emit_ddxy_interp(
1571 struct ac_nir_context *ctx,
1572 LLVMValueRef interp_ij)
1573 {
1574 LLVMValueRef result[4], a;
1575 unsigned i;
1576
1577 for (i = 0; i < 2; i++) {
1578 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1579 LLVMConstInt(ctx->ac.i32, i, false), "");
1580 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1581 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1582 }
1583 return ac_build_gather_values(&ctx->ac, result, 4);
1584 }
1585
1586 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1587 {
1588 LLVMValueRef src[4], result = NULL;
1589 unsigned num_components = instr->dest.dest.ssa.num_components;
1590 unsigned src_components;
1591 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1592
1593 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1594 switch (instr->op) {
1595 case nir_op_vec2:
1596 case nir_op_vec3:
1597 case nir_op_vec4:
1598 src_components = 1;
1599 break;
1600 case nir_op_pack_half_2x16:
1601 src_components = 2;
1602 break;
1603 case nir_op_unpack_half_2x16:
1604 src_components = 1;
1605 break;
1606 default:
1607 src_components = num_components;
1608 break;
1609 }
1610 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1611 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1612
1613 switch (instr->op) {
1614 case nir_op_fmov:
1615 case nir_op_imov:
1616 result = src[0];
1617 break;
1618 case nir_op_fneg:
1619 src[0] = ac_to_float(&ctx->ac, src[0]);
1620 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1621 break;
1622 case nir_op_ineg:
1623 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1624 break;
1625 case nir_op_inot:
1626 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1627 break;
1628 case nir_op_iadd:
1629 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1630 break;
1631 case nir_op_fadd:
1632 src[0] = ac_to_float(&ctx->ac, src[0]);
1633 src[1] = ac_to_float(&ctx->ac, src[1]);
1634 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1635 break;
1636 case nir_op_fsub:
1637 src[0] = ac_to_float(&ctx->ac, src[0]);
1638 src[1] = ac_to_float(&ctx->ac, src[1]);
1639 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1640 break;
1641 case nir_op_isub:
1642 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1643 break;
1644 case nir_op_imul:
1645 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1646 break;
1647 case nir_op_imod:
1648 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1649 break;
1650 case nir_op_umod:
1651 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1652 break;
1653 case nir_op_fmod:
1654 src[0] = ac_to_float(&ctx->ac, src[0]);
1655 src[1] = ac_to_float(&ctx->ac, src[1]);
1656 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1657 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1658 ac_to_float_type(&ctx->ac, def_type), result);
1659 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1660 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1661 break;
1662 case nir_op_frem:
1663 src[0] = ac_to_float(&ctx->ac, src[0]);
1664 src[1] = ac_to_float(&ctx->ac, src[1]);
1665 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1666 break;
1667 case nir_op_irem:
1668 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1669 break;
1670 case nir_op_idiv:
1671 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1672 break;
1673 case nir_op_udiv:
1674 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1675 break;
1676 case nir_op_fmul:
1677 src[0] = ac_to_float(&ctx->ac, src[0]);
1678 src[1] = ac_to_float(&ctx->ac, src[1]);
1679 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1680 break;
1681 case nir_op_frcp:
1682 src[0] = ac_to_float(&ctx->ac, src[0]);
1683 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1684 src[0]);
1685 break;
1686 case nir_op_iand:
1687 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1688 break;
1689 case nir_op_ior:
1690 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1691 break;
1692 case nir_op_ixor:
1693 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1694 break;
1695 case nir_op_ishl:
1696 result = LLVMBuildShl(ctx->ac.builder, src[0],
1697 LLVMBuildZExt(ctx->ac.builder, src[1],
1698 LLVMTypeOf(src[0]), ""),
1699 "");
1700 break;
1701 case nir_op_ishr:
1702 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1703 LLVMBuildZExt(ctx->ac.builder, src[1],
1704 LLVMTypeOf(src[0]), ""),
1705 "");
1706 break;
1707 case nir_op_ushr:
1708 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1709 LLVMBuildZExt(ctx->ac.builder, src[1],
1710 LLVMTypeOf(src[0]), ""),
1711 "");
1712 break;
1713 case nir_op_ilt:
1714 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1715 break;
1716 case nir_op_ine:
1717 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1718 break;
1719 case nir_op_ieq:
1720 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1721 break;
1722 case nir_op_ige:
1723 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1724 break;
1725 case nir_op_ult:
1726 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1727 break;
1728 case nir_op_uge:
1729 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1730 break;
1731 case nir_op_feq:
1732 result = emit_float_cmp(&ctx->ac, LLVMRealOEQ, src[0], src[1]);
1733 break;
1734 case nir_op_fne:
1735 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1736 break;
1737 case nir_op_flt:
1738 result = emit_float_cmp(&ctx->ac, LLVMRealOLT, src[0], src[1]);
1739 break;
1740 case nir_op_fge:
1741 result = emit_float_cmp(&ctx->ac, LLVMRealOGE, src[0], src[1]);
1742 break;
1743 case nir_op_fabs:
1744 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1745 ac_to_float_type(&ctx->ac, def_type), src[0]);
1746 break;
1747 case nir_op_iabs:
1748 result = emit_iabs(&ctx->ac, src[0]);
1749 break;
1750 case nir_op_imax:
1751 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1752 break;
1753 case nir_op_imin:
1754 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1755 break;
1756 case nir_op_umax:
1757 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1758 break;
1759 case nir_op_umin:
1760 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1761 break;
1762 case nir_op_isign:
1763 result = ac_build_isign(&ctx->ac, src[0],
1764 instr->dest.dest.ssa.bit_size);
1765 break;
1766 case nir_op_fsign:
1767 src[0] = ac_to_float(&ctx->ac, src[0]);
1768 result = ac_build_fsign(&ctx->ac, src[0],
1769 instr->dest.dest.ssa.bit_size);
1770 break;
1771 case nir_op_ffloor:
1772 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1773 ac_to_float_type(&ctx->ac, def_type), src[0]);
1774 break;
1775 case nir_op_ftrunc:
1776 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1777 ac_to_float_type(&ctx->ac, def_type), src[0]);
1778 break;
1779 case nir_op_fceil:
1780 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1781 ac_to_float_type(&ctx->ac, def_type), src[0]);
1782 break;
1783 case nir_op_fround_even:
1784 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1785 ac_to_float_type(&ctx->ac, def_type),src[0]);
1786 break;
1787 case nir_op_ffract:
1788 src[0] = ac_to_float(&ctx->ac, src[0]);
1789 result = ac_build_fract(&ctx->ac, src[0],
1790 instr->dest.dest.ssa.bit_size);
1791 break;
1792 case nir_op_fsin:
1793 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1794 ac_to_float_type(&ctx->ac, def_type), src[0]);
1795 break;
1796 case nir_op_fcos:
1797 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1798 ac_to_float_type(&ctx->ac, def_type), src[0]);
1799 break;
1800 case nir_op_fsqrt:
1801 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1802 ac_to_float_type(&ctx->ac, def_type), src[0]);
1803 break;
1804 case nir_op_fexp2:
1805 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1806 ac_to_float_type(&ctx->ac, def_type), src[0]);
1807 break;
1808 case nir_op_flog2:
1809 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1810 ac_to_float_type(&ctx->ac, def_type), src[0]);
1811 break;
1812 case nir_op_frsq:
1813 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1814 ac_to_float_type(&ctx->ac, def_type), src[0]);
1815 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1816 result);
1817 break;
1818 case nir_op_fmax:
1819 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1820 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1821 if (ctx->ac.chip_class < GFX9 &&
1822 instr->dest.dest.ssa.bit_size == 32) {
1823 /* Only pre-GFX9 chips do not flush denorms. */
1824 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1825 ac_to_float_type(&ctx->ac, def_type),
1826 result);
1827 }
1828 break;
1829 case nir_op_fmin:
1830 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1831 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1832 if (ctx->ac.chip_class < GFX9 &&
1833 instr->dest.dest.ssa.bit_size == 32) {
1834 /* Only pre-GFX9 chips do not flush denorms. */
1835 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1836 ac_to_float_type(&ctx->ac, def_type),
1837 result);
1838 }
1839 break;
1840 case nir_op_ffma:
1841 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1842 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1843 break;
1844 case nir_op_ldexp:
1845 src[0] = ac_to_float(&ctx->ac, src[0]);
1846 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1847 result = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ldexp.f32", ctx->ac.f32, src, 2, AC_FUNC_ATTR_READNONE);
1848 else
1849 result = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ldexp.f64", ctx->ac.f64, src, 2, AC_FUNC_ATTR_READNONE);
1850 break;
1851 case nir_op_ibitfield_extract:
1852 result = emit_bitfield_extract(&ctx->ac, true, src);
1853 break;
1854 case nir_op_ubitfield_extract:
1855 result = emit_bitfield_extract(&ctx->ac, false, src);
1856 break;
1857 case nir_op_bitfield_insert:
1858 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1859 break;
1860 case nir_op_bitfield_reverse:
1861 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1862 break;
1863 case nir_op_bit_count:
1864 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1865 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1866 else {
1867 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1868 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1869 }
1870 break;
1871 case nir_op_vec2:
1872 case nir_op_vec3:
1873 case nir_op_vec4:
1874 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1875 src[i] = ac_to_integer(&ctx->ac, src[i]);
1876 result = ac_build_gather_values(&ctx->ac, src, num_components);
1877 break;
1878 case nir_op_f2i32:
1879 case nir_op_f2i64:
1880 src[0] = ac_to_float(&ctx->ac, src[0]);
1881 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1882 break;
1883 case nir_op_f2u32:
1884 case nir_op_f2u64:
1885 src[0] = ac_to_float(&ctx->ac, src[0]);
1886 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1887 break;
1888 case nir_op_i2f32:
1889 case nir_op_i2f64:
1890 src[0] = ac_to_integer(&ctx->ac, src[0]);
1891 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1892 break;
1893 case nir_op_u2f32:
1894 case nir_op_u2f64:
1895 src[0] = ac_to_integer(&ctx->ac, src[0]);
1896 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1897 break;
1898 case nir_op_f2f64:
1899 src[0] = ac_to_float(&ctx->ac, src[0]);
1900 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1901 break;
1902 case nir_op_f2f32:
1903 src[0] = ac_to_float(&ctx->ac, src[0]);
1904 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1905 break;
1906 case nir_op_u2u32:
1907 case nir_op_u2u64:
1908 src[0] = ac_to_integer(&ctx->ac, src[0]);
1909 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1910 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1911 else
1912 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1913 break;
1914 case nir_op_i2i32:
1915 case nir_op_i2i64:
1916 src[0] = ac_to_integer(&ctx->ac, src[0]);
1917 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1918 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1919 else
1920 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1921 break;
1922 case nir_op_bcsel:
1923 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1924 break;
1925 case nir_op_find_lsb:
1926 src[0] = ac_to_integer(&ctx->ac, src[0]);
1927 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1928 break;
1929 case nir_op_ufind_msb:
1930 src[0] = ac_to_integer(&ctx->ac, src[0]);
1931 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1932 break;
1933 case nir_op_ifind_msb:
1934 src[0] = ac_to_integer(&ctx->ac, src[0]);
1935 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1936 break;
1937 case nir_op_uadd_carry:
1938 src[0] = ac_to_integer(&ctx->ac, src[0]);
1939 src[1] = ac_to_integer(&ctx->ac, src[1]);
1940 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1941 break;
1942 case nir_op_usub_borrow:
1943 src[0] = ac_to_integer(&ctx->ac, src[0]);
1944 src[1] = ac_to_integer(&ctx->ac, src[1]);
1945 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1946 break;
1947 case nir_op_b2f:
1948 result = emit_b2f(&ctx->ac, src[0]);
1949 break;
1950 case nir_op_f2b:
1951 result = emit_f2b(&ctx->ac, src[0]);
1952 break;
1953 case nir_op_b2i:
1954 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1955 break;
1956 case nir_op_i2b:
1957 src[0] = ac_to_integer(&ctx->ac, src[0]);
1958 result = emit_i2b(&ctx->ac, src[0]);
1959 break;
1960 case nir_op_fquantize2f16:
1961 result = emit_f2f16(&ctx->ac, src[0]);
1962 break;
1963 case nir_op_umul_high:
1964 src[0] = ac_to_integer(&ctx->ac, src[0]);
1965 src[1] = ac_to_integer(&ctx->ac, src[1]);
1966 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1967 break;
1968 case nir_op_imul_high:
1969 src[0] = ac_to_integer(&ctx->ac, src[0]);
1970 src[1] = ac_to_integer(&ctx->ac, src[1]);
1971 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1972 break;
1973 case nir_op_pack_half_2x16:
1974 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1975 break;
1976 case nir_op_unpack_half_2x16:
1977 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1978 break;
1979 case nir_op_fddx:
1980 case nir_op_fddy:
1981 case nir_op_fddx_fine:
1982 case nir_op_fddy_fine:
1983 case nir_op_fddx_coarse:
1984 case nir_op_fddy_coarse:
1985 result = emit_ddxy(ctx, instr->op, src[0]);
1986 break;
1987
1988 case nir_op_unpack_64_2x32_split_x: {
1989 assert(ac_get_llvm_num_components(src[0]) == 1);
1990 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1991 ctx->ac.v2i32,
1992 "");
1993 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1994 ctx->ac.i32_0, "");
1995 break;
1996 }
1997
1998 case nir_op_unpack_64_2x32_split_y: {
1999 assert(ac_get_llvm_num_components(src[0]) == 1);
2000 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2001 ctx->ac.v2i32,
2002 "");
2003 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2004 ctx->ac.i32_1, "");
2005 break;
2006 }
2007
2008 case nir_op_pack_64_2x32_split: {
2009 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2010 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2011 src[0], ctx->ac.i32_0, "");
2012 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2013 src[1], ctx->ac.i32_1, "");
2014 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2015 break;
2016 }
2017
2018 default:
2019 fprintf(stderr, "Unknown NIR alu instr: ");
2020 nir_print_instr(&instr->instr, stderr);
2021 fprintf(stderr, "\n");
2022 abort();
2023 }
2024
2025 if (result) {
2026 assert(instr->dest.dest.is_ssa);
2027 result = ac_to_integer(&ctx->ac, result);
2028 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2029 result);
2030 }
2031 }
2032
2033 static void visit_load_const(struct ac_nir_context *ctx,
2034 const nir_load_const_instr *instr)
2035 {
2036 LLVMValueRef values[4], value = NULL;
2037 LLVMTypeRef element_type =
2038 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2039
2040 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2041 switch (instr->def.bit_size) {
2042 case 32:
2043 values[i] = LLVMConstInt(element_type,
2044 instr->value.u32[i], false);
2045 break;
2046 case 64:
2047 values[i] = LLVMConstInt(element_type,
2048 instr->value.u64[i], false);
2049 break;
2050 default:
2051 fprintf(stderr,
2052 "unsupported nir load_const bit_size: %d\n",
2053 instr->def.bit_size);
2054 abort();
2055 }
2056 }
2057 if (instr->def.num_components > 1) {
2058 value = LLVMConstVector(values, instr->def.num_components);
2059 } else
2060 value = values[0];
2061
2062 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2063 }
2064
2065 static LLVMValueRef cast_ptr(struct ac_llvm_context *ctx, LLVMValueRef ptr,
2066 LLVMTypeRef type)
2067 {
2068 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2069 return LLVMBuildBitCast(ctx->builder, ptr,
2070 LLVMPointerType(type, addr_space), "");
2071 }
2072
2073 static LLVMValueRef
2074 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2075 {
2076 LLVMValueRef size =
2077 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2078 LLVMConstInt(ctx->ac.i32, 2, false), "");
2079
2080 /* VI only */
2081 if (ctx->ac.chip_class == VI && in_elements) {
2082 /* On VI, the descriptor contains the size in bytes,
2083 * but TXQ must return the size in elements.
2084 * The stride is always non-zero for resources using TXQ.
2085 */
2086 LLVMValueRef stride =
2087 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2088 ctx->ac.i32_1, "");
2089 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2090 LLVMConstInt(ctx->ac.i32, 16, false), "");
2091 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2092 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2093
2094 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2095 }
2096 return size;
2097 }
2098
2099 /**
2100 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2101 * intrinsic names).
2102 */
2103 static void build_int_type_name(
2104 LLVMTypeRef type,
2105 char *buf, unsigned bufsize)
2106 {
2107 assert(bufsize >= 6);
2108
2109 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2110 snprintf(buf, bufsize, "v%ui32",
2111 LLVMGetVectorSize(type));
2112 else
2113 strcpy(buf, "i32");
2114 }
2115
2116 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2117 struct ac_image_args *args,
2118 const nir_tex_instr *instr)
2119 {
2120 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2121 LLVMValueRef coord = args->addr;
2122 LLVMValueRef half_texel[2];
2123 LLVMValueRef compare_cube_wa = NULL;
2124 LLVMValueRef result;
2125 int c;
2126 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2127
2128 //TODO Rect
2129 {
2130 struct ac_image_args txq_args = { 0 };
2131
2132 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2133 txq_args.opcode = ac_image_get_resinfo;
2134 txq_args.dmask = 0xf;
2135 txq_args.addr = ctx->i32_0;
2136 txq_args.resource = args->resource;
2137 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2138
2139 for (c = 0; c < 2; c++) {
2140 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2141 LLVMConstInt(ctx->i32, c, false), "");
2142 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2143 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2144 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2145 LLVMConstReal(ctx->f32, -0.5), "");
2146 }
2147 }
2148
2149 LLVMValueRef orig_coords = args->addr;
2150
2151 for (c = 0; c < 2; c++) {
2152 LLVMValueRef tmp;
2153 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2154 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2155 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2156 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2157 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2158 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2159 }
2160
2161
2162 /*
2163 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2164 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2165 * workaround by sampling using a scaled type and converting.
2166 * This is taken from amdgpu-pro shaders.
2167 */
2168 /* NOTE this produces some ugly code compared to amdgpu-pro,
2169 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2170 * and then reads them back. -pro generates two selects,
2171 * one s_cmp for the descriptor rewriting
2172 * one v_cmp for the coordinate and result changes.
2173 */
2174 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2175 LLVMValueRef tmp, tmp2;
2176
2177 /* workaround 8/8/8/8 uint/sint cube gather bug */
2178 /* first detect it then change to a scaled read and f2i */
2179 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2180 tmp2 = tmp;
2181
2182 /* extract the DATA_FORMAT */
2183 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2184 LLVMConstInt(ctx->i32, 6, false), false);
2185
2186 /* is the DATA_FORMAT == 8_8_8_8 */
2187 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2188
2189 if (stype == GLSL_TYPE_UINT)
2190 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2191 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2192 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2193 else
2194 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2195 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2196 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2197
2198 /* replace the NUM FORMAT in the descriptor */
2199 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2200 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2201
2202 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2203
2204 /* don't modify the coordinates for this case */
2205 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2206 }
2207 args->addr = coord;
2208 result = ac_build_image_opcode(ctx, args);
2209
2210 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2211 LLVMValueRef tmp, tmp2;
2212
2213 /* if the cube workaround is in place, f2i the result. */
2214 for (c = 0; c < 4; c++) {
2215 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2216 if (stype == GLSL_TYPE_UINT)
2217 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2218 else
2219 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2220 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2221 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2222 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2223 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2224 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2225 }
2226 }
2227 return result;
2228 }
2229
2230 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2231 const nir_tex_instr *instr,
2232 bool lod_is_zero,
2233 struct ac_image_args *args)
2234 {
2235 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2236 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2237
2238 return ac_build_buffer_load_format(&ctx->ac,
2239 args->resource,
2240 args->addr,
2241 ctx->ac.i32_0,
2242 util_last_bit(mask),
2243 false, true);
2244 }
2245
2246 args->opcode = ac_image_sample;
2247 args->compare = instr->is_shadow;
2248
2249 switch (instr->op) {
2250 case nir_texop_txf:
2251 case nir_texop_txf_ms:
2252 case nir_texop_samples_identical:
2253 args->opcode = lod_is_zero ||
2254 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2255 ac_image_load : ac_image_load_mip;
2256 args->compare = false;
2257 args->offset = false;
2258 break;
2259 case nir_texop_txb:
2260 args->bias = true;
2261 break;
2262 case nir_texop_txl:
2263 if (lod_is_zero)
2264 args->level_zero = true;
2265 else
2266 args->lod = true;
2267 break;
2268 case nir_texop_txs:
2269 case nir_texop_query_levels:
2270 args->opcode = ac_image_get_resinfo;
2271 break;
2272 case nir_texop_tex:
2273 if (ctx->stage != MESA_SHADER_FRAGMENT)
2274 args->level_zero = true;
2275 break;
2276 case nir_texop_txd:
2277 args->deriv = true;
2278 break;
2279 case nir_texop_tg4:
2280 args->opcode = ac_image_gather4;
2281 args->level_zero = true;
2282 break;
2283 case nir_texop_lod:
2284 args->opcode = ac_image_get_lod;
2285 args->compare = false;
2286 args->offset = false;
2287 break;
2288 default:
2289 break;
2290 }
2291
2292 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2293 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2294 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2295 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2296 }
2297 }
2298 return ac_build_image_opcode(&ctx->ac, args);
2299 }
2300
2301 static LLVMValueRef
2302 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2303 unsigned desc_set, unsigned binding)
2304 {
2305 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2306 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2307 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2308 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2309 unsigned base_offset = layout->binding[binding].offset;
2310 LLVMValueRef offset, stride;
2311
2312 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2313 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2314 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2315 layout->binding[binding].dynamic_offset_offset;
2316 desc_ptr = ctx->abi.push_constants;
2317 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2318 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2319 } else
2320 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2321
2322 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2323 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
2324 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
2325
2326 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2327 desc_ptr = cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
2328 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2329
2330 return desc_ptr;
2331 }
2332
2333 static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
2334 nir_intrinsic_instr *instr)
2335 {
2336 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2337 LLVMValueRef index = get_src(ctx, instr->src[1]);
2338
2339 LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
2340 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2341 return result;
2342 }
2343
2344 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
2345 nir_intrinsic_instr *instr)
2346 {
2347 LLVMValueRef ptr, addr;
2348
2349 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2350 addr = LLVMBuildAdd(ctx->ac.builder, addr,
2351 get_src(ctx, instr->src[0]), "");
2352
2353 ptr = ac_build_gep0(&ctx->ac, ctx->abi->push_constants, addr);
2354 ptr = cast_ptr(&ctx->ac, ptr, get_def_type(ctx, &instr->dest.ssa));
2355
2356 return LLVMBuildLoad(ctx->ac.builder, ptr, "");
2357 }
2358
2359 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2360 const nir_intrinsic_instr *instr)
2361 {
2362 LLVMValueRef index = get_src(ctx, instr->src[0]);
2363
2364 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2365 }
2366
2367 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2368 {
2369 uint32_t new_mask = 0;
2370 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2371 if (mask & (1u << i))
2372 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2373 return new_mask;
2374 }
2375
2376 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2377 unsigned start, unsigned count)
2378 {
2379 LLVMTypeRef type = LLVMTypeOf(src);
2380
2381 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2382 assert(start == 0);
2383 assert(count == 1);
2384 return src;
2385 }
2386
2387 unsigned src_elements = LLVMGetVectorSize(type);
2388 assert(start < src_elements);
2389 assert(start + count <= src_elements);
2390
2391 if (start == 0 && count == src_elements)
2392 return src;
2393
2394 if (count == 1)
2395 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2396
2397 assert(count <= 8);
2398 LLVMValueRef indices[8];
2399 for (unsigned i = 0; i < count; ++i)
2400 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2401
2402 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2403 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2404 }
2405
2406 static void visit_store_ssbo(struct ac_nir_context *ctx,
2407 nir_intrinsic_instr *instr)
2408 {
2409 const char *store_name;
2410 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2411 LLVMTypeRef data_type = ctx->ac.f32;
2412 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2413 int components_32bit = elem_size_mult * instr->num_components;
2414 unsigned writemask = nir_intrinsic_write_mask(instr);
2415 LLVMValueRef base_data, base_offset;
2416 LLVMValueRef params[6];
2417
2418 params[1] = ctx->abi->load_ssbo(ctx->abi,
2419 get_src(ctx, instr->src[1]), true);
2420 params[2] = ctx->ac.i32_0; /* vindex */
2421 params[4] = ctx->ac.i1false; /* glc */
2422 params[5] = ctx->ac.i1false; /* slc */
2423
2424 if (components_32bit > 1)
2425 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2426
2427 writemask = widen_mask(writemask, elem_size_mult);
2428
2429 base_data = ac_to_float(&ctx->ac, src_data);
2430 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2431 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2432 data_type, "");
2433 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2434 while (writemask) {
2435 int start, count;
2436 LLVMValueRef data;
2437 LLVMValueRef offset;
2438
2439 u_bit_scan_consecutive_range(&writemask, &start, &count);
2440
2441 /* Due to an LLVM limitation, split 3-element writes
2442 * into a 2-element and a 1-element write. */
2443 if (count == 3) {
2444 writemask |= 1 << (start + 2);
2445 count = 2;
2446 }
2447
2448 if (count > 4) {
2449 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2450 count = 4;
2451 }
2452
2453 if (count == 4) {
2454 store_name = "llvm.amdgcn.buffer.store.v4f32";
2455 } else if (count == 2) {
2456 store_name = "llvm.amdgcn.buffer.store.v2f32";
2457
2458 } else {
2459 assert(count == 1);
2460 store_name = "llvm.amdgcn.buffer.store.f32";
2461 }
2462 data = extract_vector_range(&ctx->ac, base_data, start, count);
2463
2464 offset = base_offset;
2465 if (start != 0) {
2466 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2467 }
2468 params[0] = data;
2469 params[3] = offset;
2470 ac_build_intrinsic(&ctx->ac, store_name,
2471 ctx->ac.voidt, params, 6, 0);
2472 }
2473 }
2474
2475 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2476 const nir_intrinsic_instr *instr)
2477 {
2478 const char *name;
2479 LLVMValueRef params[6];
2480 int arg_count = 0;
2481
2482 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2483 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2484 }
2485 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2486 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2487 get_src(ctx, instr->src[0]),
2488 true);
2489 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2490 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2491 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2492
2493 switch (instr->intrinsic) {
2494 case nir_intrinsic_ssbo_atomic_add:
2495 name = "llvm.amdgcn.buffer.atomic.add";
2496 break;
2497 case nir_intrinsic_ssbo_atomic_imin:
2498 name = "llvm.amdgcn.buffer.atomic.smin";
2499 break;
2500 case nir_intrinsic_ssbo_atomic_umin:
2501 name = "llvm.amdgcn.buffer.atomic.umin";
2502 break;
2503 case nir_intrinsic_ssbo_atomic_imax:
2504 name = "llvm.amdgcn.buffer.atomic.smax";
2505 break;
2506 case nir_intrinsic_ssbo_atomic_umax:
2507 name = "llvm.amdgcn.buffer.atomic.umax";
2508 break;
2509 case nir_intrinsic_ssbo_atomic_and:
2510 name = "llvm.amdgcn.buffer.atomic.and";
2511 break;
2512 case nir_intrinsic_ssbo_atomic_or:
2513 name = "llvm.amdgcn.buffer.atomic.or";
2514 break;
2515 case nir_intrinsic_ssbo_atomic_xor:
2516 name = "llvm.amdgcn.buffer.atomic.xor";
2517 break;
2518 case nir_intrinsic_ssbo_atomic_exchange:
2519 name = "llvm.amdgcn.buffer.atomic.swap";
2520 break;
2521 case nir_intrinsic_ssbo_atomic_comp_swap:
2522 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2523 break;
2524 default:
2525 abort();
2526 }
2527
2528 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2529 }
2530
2531 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2532 const nir_intrinsic_instr *instr)
2533 {
2534 LLVMValueRef results[2];
2535 int load_components;
2536 int num_components = instr->num_components;
2537 if (instr->dest.ssa.bit_size == 64)
2538 num_components *= 2;
2539
2540 for (int i = 0; i < num_components; i += load_components) {
2541 load_components = MIN2(num_components - i, 4);
2542 const char *load_name;
2543 LLVMTypeRef data_type = ctx->ac.f32;
2544 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2545 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2546
2547 if (load_components == 3)
2548 data_type = LLVMVectorType(ctx->ac.f32, 4);
2549 else if (load_components > 1)
2550 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2551
2552 if (load_components >= 3)
2553 load_name = "llvm.amdgcn.buffer.load.v4f32";
2554 else if (load_components == 2)
2555 load_name = "llvm.amdgcn.buffer.load.v2f32";
2556 else if (load_components == 1)
2557 load_name = "llvm.amdgcn.buffer.load.f32";
2558 else
2559 unreachable("unhandled number of components");
2560
2561 LLVMValueRef params[] = {
2562 ctx->abi->load_ssbo(ctx->abi,
2563 get_src(ctx, instr->src[0]),
2564 false),
2565 ctx->ac.i32_0,
2566 offset,
2567 ctx->ac.i1false,
2568 ctx->ac.i1false,
2569 };
2570
2571 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2572 }
2573
2574 assume(results[0]);
2575 LLVMValueRef ret = results[0];
2576 if (num_components > 4 || num_components == 3) {
2577 LLVMValueRef masks[] = {
2578 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2579 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2580 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2581 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2582 };
2583
2584 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2585 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2586 results[num_components > 4 ? 1 : 0], swizzle, "");
2587 }
2588
2589 return LLVMBuildBitCast(ctx->ac.builder, ret,
2590 get_def_type(ctx, &instr->dest.ssa), "");
2591 }
2592
2593 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2594 const nir_intrinsic_instr *instr)
2595 {
2596 LLVMValueRef ret;
2597 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2598 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2599 int num_components = instr->num_components;
2600
2601 if (ctx->abi->load_ubo)
2602 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2603
2604 if (instr->dest.ssa.bit_size == 64)
2605 num_components *= 2;
2606
2607 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2608 NULL, 0, false, false, true, true);
2609 ret = trim_vector(&ctx->ac, ret, num_components);
2610 return LLVMBuildBitCast(ctx->ac.builder, ret,
2611 get_def_type(ctx, &instr->dest.ssa), "");
2612 }
2613
2614 static void
2615 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2616 bool vs_in, unsigned *vertex_index_out,
2617 LLVMValueRef *vertex_index_ref,
2618 unsigned *const_out, LLVMValueRef *indir_out)
2619 {
2620 unsigned const_offset = 0;
2621 nir_deref *tail = &deref->deref;
2622 LLVMValueRef offset = NULL;
2623
2624 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2625 tail = tail->child;
2626 nir_deref_array *deref_array = nir_deref_as_array(tail);
2627 if (vertex_index_out)
2628 *vertex_index_out = deref_array->base_offset;
2629
2630 if (vertex_index_ref) {
2631 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2632 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2633 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2634 }
2635 *vertex_index_ref = vtx;
2636 }
2637 }
2638
2639 if (deref->var->data.compact) {
2640 assert(tail->child->deref_type == nir_deref_type_array);
2641 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2642 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2643 /* We always lower indirect dereferences for "compact" array vars. */
2644 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2645
2646 const_offset = deref_array->base_offset;
2647 goto out;
2648 }
2649
2650 while (tail->child != NULL) {
2651 const struct glsl_type *parent_type = tail->type;
2652 tail = tail->child;
2653
2654 if (tail->deref_type == nir_deref_type_array) {
2655 nir_deref_array *deref_array = nir_deref_as_array(tail);
2656 LLVMValueRef index, stride, local_offset;
2657 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2658
2659 const_offset += size * deref_array->base_offset;
2660 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2661 continue;
2662
2663 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2664 index = get_src(ctx, deref_array->indirect);
2665 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2666 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2667
2668 if (offset)
2669 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2670 else
2671 offset = local_offset;
2672 } else if (tail->deref_type == nir_deref_type_struct) {
2673 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2674
2675 for (unsigned i = 0; i < deref_struct->index; i++) {
2676 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2677 const_offset += glsl_count_attribute_slots(ft, vs_in);
2678 }
2679 } else
2680 unreachable("unsupported deref type");
2681
2682 }
2683 out:
2684 if (const_offset && offset)
2685 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2686 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2687 "");
2688
2689 *const_out = const_offset;
2690 *indir_out = offset;
2691 }
2692
2693
2694 /* The offchip buffer layout for TCS->TES is
2695 *
2696 * - attribute 0 of patch 0 vertex 0
2697 * - attribute 0 of patch 0 vertex 1
2698 * - attribute 0 of patch 0 vertex 2
2699 * ...
2700 * - attribute 0 of patch 1 vertex 0
2701 * - attribute 0 of patch 1 vertex 1
2702 * ...
2703 * - attribute 1 of patch 0 vertex 0
2704 * - attribute 1 of patch 0 vertex 1
2705 * ...
2706 * - per patch attribute 0 of patch 0
2707 * - per patch attribute 0 of patch 1
2708 * ...
2709 *
2710 * Note that every attribute has 4 components.
2711 */
2712 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
2713 LLVMValueRef vertex_index,
2714 LLVMValueRef param_index)
2715 {
2716 LLVMValueRef base_addr, vertices_per_patch, num_patches;
2717 LLVMValueRef param_stride, constant16;
2718 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2719
2720 vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
2721 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2722
2723 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2724 if (vertex_index) {
2725 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2726 vertices_per_patch, "");
2727
2728 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2729 vertex_index, "");
2730
2731 param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
2732 num_patches, "");
2733 } else {
2734 base_addr = rel_patch_id;
2735 param_stride = num_patches;
2736 }
2737
2738 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2739 LLVMBuildMul(ctx->ac.builder, param_index,
2740 param_stride, ""), "");
2741
2742 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
2743
2744 if (!vertex_index) {
2745 LLVMValueRef patch_data_offset =
2746 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2747
2748 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2749 patch_data_offset, "");
2750 }
2751 return base_addr;
2752 }
2753
2754 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
2755 unsigned param,
2756 unsigned const_index,
2757 bool is_compact,
2758 LLVMValueRef vertex_index,
2759 LLVMValueRef indir_index)
2760 {
2761 LLVMValueRef param_index;
2762
2763 if (indir_index)
2764 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
2765 indir_index, "");
2766 else {
2767 if (const_index && !is_compact)
2768 param += const_index;
2769 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2770 }
2771 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2772 }
2773
2774 static void
2775 mark_tess_output(struct radv_shader_context *ctx,
2776 bool is_patch, uint32_t param)
2777
2778 {
2779 if (is_patch) {
2780 ctx->tess_patch_outputs_written |= (1ull << param);
2781 } else
2782 ctx->tess_outputs_written |= (1ull << param);
2783 }
2784
2785 static LLVMValueRef
2786 get_dw_address(struct radv_shader_context *ctx,
2787 LLVMValueRef dw_addr,
2788 unsigned param,
2789 unsigned const_index,
2790 bool compact_const_index,
2791 LLVMValueRef vertex_index,
2792 LLVMValueRef stride,
2793 LLVMValueRef indir_index)
2794
2795 {
2796
2797 if (vertex_index) {
2798 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2799 LLVMBuildMul(ctx->ac.builder,
2800 vertex_index,
2801 stride, ""), "");
2802 }
2803
2804 if (indir_index)
2805 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2806 LLVMBuildMul(ctx->ac.builder, indir_index,
2807 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2808 else if (const_index && !compact_const_index)
2809 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2810 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2811
2812 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2813 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2814
2815 if (const_index && compact_const_index)
2816 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2817 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2818 return dw_addr;
2819 }
2820
2821 static LLVMValueRef
2822 load_tcs_varyings(struct ac_shader_abi *abi,
2823 LLVMTypeRef type,
2824 LLVMValueRef vertex_index,
2825 LLVMValueRef indir_index,
2826 unsigned const_index,
2827 unsigned location,
2828 unsigned driver_location,
2829 unsigned component,
2830 unsigned num_components,
2831 bool is_patch,
2832 bool is_compact,
2833 bool load_input)
2834 {
2835 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2836 LLVMValueRef dw_addr, stride;
2837 LLVMValueRef value[4], result;
2838 unsigned param = shader_io_get_unique_index(location);
2839
2840 if (load_input) {
2841 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2842 dw_addr = get_tcs_in_current_patch_offset(ctx);
2843 } else {
2844 if (!is_patch) {
2845 stride = get_tcs_out_vertex_stride(ctx);
2846 dw_addr = get_tcs_out_current_patch_offset(ctx);
2847 } else {
2848 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2849 stride = NULL;
2850 }
2851 }
2852
2853 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2854 indir_index);
2855
2856 for (unsigned i = 0; i < num_components + component; i++) {
2857 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2858 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2859 ctx->ac.i32_1, "");
2860 }
2861 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2862 return result;
2863 }
2864
2865 static void
2866 store_tcs_output(struct ac_shader_abi *abi,
2867 LLVMValueRef vertex_index,
2868 LLVMValueRef param_index,
2869 unsigned const_index,
2870 unsigned location,
2871 unsigned driver_location,
2872 LLVMValueRef src,
2873 unsigned component,
2874 bool is_patch,
2875 bool is_compact,
2876 unsigned writemask)
2877 {
2878 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2879 LLVMValueRef dw_addr;
2880 LLVMValueRef stride = NULL;
2881 LLVMValueRef buf_addr = NULL;
2882 unsigned param;
2883 bool store_lds = true;
2884
2885 if (is_patch) {
2886 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2887 store_lds = false;
2888 } else {
2889 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2890 store_lds = false;
2891 }
2892
2893 param = shader_io_get_unique_index(location);
2894 if (location == VARYING_SLOT_CLIP_DIST0 &&
2895 is_compact && const_index > 3) {
2896 const_index -= 3;
2897 param++;
2898 }
2899
2900 if (!is_patch) {
2901 stride = get_tcs_out_vertex_stride(ctx);
2902 dw_addr = get_tcs_out_current_patch_offset(ctx);
2903 } else {
2904 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2905 }
2906
2907 mark_tess_output(ctx, is_patch, param);
2908
2909 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2910 param_index);
2911 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2912 vertex_index, param_index);
2913
2914 bool is_tess_factor = false;
2915 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2916 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2917 is_tess_factor = true;
2918
2919 unsigned base = is_compact ? const_index : 0;
2920 for (unsigned chan = 0; chan < 8; chan++) {
2921 if (!(writemask & (1 << chan)))
2922 continue;
2923 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2924
2925 if (store_lds || is_tess_factor) {
2926 LLVMValueRef dw_addr_chan =
2927 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2928 LLVMConstInt(ctx->ac.i32, chan, false), "");
2929 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2930 }
2931
2932 if (!is_tess_factor && writemask != 0xF)
2933 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2934 buf_addr, ctx->oc_lds,
2935 4 * (base + chan), 1, 0, true, false);
2936 }
2937
2938 if (writemask == 0xF) {
2939 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2940 buf_addr, ctx->oc_lds,
2941 (base * 4), 1, 0, true, false);
2942 }
2943 }
2944
2945 static LLVMValueRef
2946 load_tes_input(struct ac_shader_abi *abi,
2947 LLVMTypeRef type,
2948 LLVMValueRef vertex_index,
2949 LLVMValueRef param_index,
2950 unsigned const_index,
2951 unsigned location,
2952 unsigned driver_location,
2953 unsigned component,
2954 unsigned num_components,
2955 bool is_patch,
2956 bool is_compact,
2957 bool load_input)
2958 {
2959 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2960 LLVMValueRef buf_addr;
2961 LLVMValueRef result;
2962 unsigned param = shader_io_get_unique_index(location);
2963
2964 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
2965 const_index -= 3;
2966 param++;
2967 }
2968
2969 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2970 is_compact, vertex_index, param_index);
2971
2972 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
2973 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
2974
2975 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
2976 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2977 result = trim_vector(&ctx->ac, result, num_components);
2978 return result;
2979 }
2980
2981 static LLVMValueRef
2982 load_gs_input(struct ac_shader_abi *abi,
2983 unsigned location,
2984 unsigned driver_location,
2985 unsigned component,
2986 unsigned num_components,
2987 unsigned vertex_index,
2988 unsigned const_index,
2989 LLVMTypeRef type)
2990 {
2991 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2992 LLVMValueRef vtx_offset;
2993 unsigned param, vtx_offset_param;
2994 LLVMValueRef value[4], result;
2995
2996 vtx_offset_param = vertex_index;
2997 assert(vtx_offset_param < 6);
2998 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
2999 LLVMConstInt(ctx->ac.i32, 4, false), "");
3000
3001 param = shader_io_get_unique_index(location);
3002
3003 for (unsigned i = component; i < num_components + component; i++) {
3004 if (ctx->ac.chip_class >= GFX9) {
3005 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3006 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3007 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3008 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3009 } else {
3010 LLVMValueRef soffset =
3011 LLVMConstInt(ctx->ac.i32,
3012 (param * 4 + i + const_index) * 256,
3013 false);
3014
3015 value[i] = ac_build_buffer_load(&ctx->ac,
3016 ctx->esgs_ring, 1,
3017 ctx->ac.i32_0,
3018 vtx_offset, soffset,
3019 0, 1, 0, true, false);
3020
3021 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
3022 type, "");
3023 }
3024 }
3025 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3026 result = ac_to_integer(&ctx->ac, result);
3027 return result;
3028 }
3029
3030 static LLVMValueRef
3031 build_gep_for_deref(struct ac_nir_context *ctx,
3032 nir_deref_var *deref)
3033 {
3034 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3035 assert(entry->data);
3036 LLVMValueRef val = entry->data;
3037 nir_deref *tail = deref->deref.child;
3038 while (tail != NULL) {
3039 LLVMValueRef offset;
3040 switch (tail->deref_type) {
3041 case nir_deref_type_array: {
3042 nir_deref_array *array = nir_deref_as_array(tail);
3043 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3044 if (array->deref_array_type ==
3045 nir_deref_array_type_indirect) {
3046 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3047 get_src(ctx,
3048 array->indirect),
3049 "");
3050 }
3051 break;
3052 }
3053 case nir_deref_type_struct: {
3054 nir_deref_struct *deref_struct =
3055 nir_deref_as_struct(tail);
3056 offset = LLVMConstInt(ctx->ac.i32,
3057 deref_struct->index, 0);
3058 break;
3059 }
3060 default:
3061 unreachable("bad deref type");
3062 }
3063 val = ac_build_gep0(&ctx->ac, val, offset);
3064 tail = tail->child;
3065 }
3066 return val;
3067 }
3068
3069 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3070 nir_intrinsic_instr *instr,
3071 bool load_inputs)
3072 {
3073 LLVMValueRef result;
3074 LLVMValueRef vertex_index = NULL;
3075 LLVMValueRef indir_index = NULL;
3076 unsigned const_index = 0;
3077 unsigned location = instr->variables[0]->var->data.location;
3078 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3079 const bool is_patch = instr->variables[0]->var->data.patch;
3080 const bool is_compact = instr->variables[0]->var->data.compact;
3081
3082 get_deref_offset(ctx, instr->variables[0],
3083 false, NULL, is_patch ? NULL : &vertex_index,
3084 &const_index, &indir_index);
3085
3086 LLVMTypeRef dest_type = get_def_type(ctx, &instr->dest.ssa);
3087
3088 LLVMTypeRef src_component_type;
3089 if (LLVMGetTypeKind(dest_type) == LLVMVectorTypeKind)
3090 src_component_type = LLVMGetElementType(dest_type);
3091 else
3092 src_component_type = dest_type;
3093
3094 result = ctx->abi->load_tess_varyings(ctx->abi, src_component_type,
3095 vertex_index, indir_index,
3096 const_index, location, driver_location,
3097 instr->variables[0]->var->data.location_frac,
3098 instr->num_components,
3099 is_patch, is_compact, load_inputs);
3100 return LLVMBuildBitCast(ctx->ac.builder, result, dest_type, "");
3101 }
3102
3103 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3104 nir_intrinsic_instr *instr)
3105 {
3106 LLVMValueRef values[8];
3107 int idx = instr->variables[0]->var->data.driver_location;
3108 int ve = instr->dest.ssa.num_components;
3109 unsigned comp = instr->variables[0]->var->data.location_frac;
3110 LLVMValueRef indir_index;
3111 LLVMValueRef ret;
3112 unsigned const_index;
3113 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3114 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3115 instr->variables[0]->var->data.mode == nir_var_shader_in;
3116 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3117 &const_index, &indir_index);
3118
3119 if (instr->dest.ssa.bit_size == 64)
3120 ve *= 2;
3121
3122 switch (instr->variables[0]->var->data.mode) {
3123 case nir_var_shader_in:
3124 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3125 ctx->stage == MESA_SHADER_TESS_EVAL) {
3126 return load_tess_varyings(ctx, instr, true);
3127 }
3128
3129 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3130 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3131 LLVMValueRef indir_index;
3132 unsigned const_index, vertex_index;
3133 get_deref_offset(ctx, instr->variables[0],
3134 false, &vertex_index, NULL,
3135 &const_index, &indir_index);
3136
3137 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3138 instr->variables[0]->var->data.driver_location,
3139 instr->variables[0]->var->data.location_frac, ve,
3140 vertex_index, const_index, type);
3141 }
3142
3143 for (unsigned chan = comp; chan < ve + comp; chan++) {
3144 if (indir_index) {
3145 unsigned count = glsl_count_attribute_slots(
3146 instr->variables[0]->var->type,
3147 ctx->stage == MESA_SHADER_VERTEX);
3148 count -= chan / 4;
3149 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3150 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3151 stride, false, true);
3152
3153 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3154 tmp_vec,
3155 indir_index, "");
3156 } else
3157 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3158 }
3159 break;
3160 case nir_var_local:
3161 for (unsigned chan = 0; chan < ve; chan++) {
3162 if (indir_index) {
3163 unsigned count = glsl_count_attribute_slots(
3164 instr->variables[0]->var->type, false);
3165 count -= chan / 4;
3166 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3167 &ctx->ac, ctx->locals + idx + chan, count,
3168 stride, true, true);
3169
3170 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3171 tmp_vec,
3172 indir_index, "");
3173 } else {
3174 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3175 }
3176 }
3177 break;
3178 case nir_var_shared: {
3179 LLVMValueRef address = build_gep_for_deref(ctx,
3180 instr->variables[0]);
3181 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3182 return LLVMBuildBitCast(ctx->ac.builder, val,
3183 get_def_type(ctx, &instr->dest.ssa),
3184 "");
3185 }
3186 case nir_var_shader_out:
3187 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3188 return load_tess_varyings(ctx, instr, false);
3189 }
3190
3191 for (unsigned chan = comp; chan < ve + comp; chan++) {
3192 if (indir_index) {
3193 unsigned count = glsl_count_attribute_slots(
3194 instr->variables[0]->var->type, false);
3195 count -= chan / 4;
3196 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3197 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3198 stride, true, true);
3199
3200 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3201 tmp_vec,
3202 indir_index, "");
3203 } else {
3204 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3205 ctx->abi->outputs[idx + chan + const_index * stride],
3206 "");
3207 }
3208 }
3209 break;
3210 default:
3211 unreachable("unhandle variable mode");
3212 }
3213 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3214 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3215 }
3216
3217 static void
3218 visit_store_var(struct ac_nir_context *ctx,
3219 nir_intrinsic_instr *instr)
3220 {
3221 LLVMValueRef temp_ptr, value;
3222 int idx = instr->variables[0]->var->data.driver_location;
3223 unsigned comp = instr->variables[0]->var->data.location_frac;
3224 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3225 int writemask = instr->const_index[0] << comp;
3226 LLVMValueRef indir_index;
3227 unsigned const_index;
3228 get_deref_offset(ctx, instr->variables[0], false,
3229 NULL, NULL, &const_index, &indir_index);
3230
3231 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3232
3233 src = LLVMBuildBitCast(ctx->ac.builder, src,
3234 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3235 "");
3236
3237 writemask = widen_mask(writemask, 2);
3238 }
3239
3240 switch (instr->variables[0]->var->data.mode) {
3241 case nir_var_shader_out:
3242
3243 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3244 LLVMValueRef vertex_index = NULL;
3245 LLVMValueRef indir_index = NULL;
3246 unsigned const_index = 0;
3247 const unsigned location = instr->variables[0]->var->data.location;
3248 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3249 const unsigned comp = instr->variables[0]->var->data.location_frac;
3250 const bool is_patch = instr->variables[0]->var->data.patch;
3251 const bool is_compact = instr->variables[0]->var->data.compact;
3252
3253 get_deref_offset(ctx, instr->variables[0],
3254 false, NULL, is_patch ? NULL : &vertex_index,
3255 &const_index, &indir_index);
3256
3257 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3258 const_index, location, driver_location,
3259 src, comp, is_patch, is_compact, writemask);
3260 return;
3261 }
3262
3263 for (unsigned chan = 0; chan < 8; chan++) {
3264 int stride = 4;
3265 if (!(writemask & (1 << chan)))
3266 continue;
3267
3268 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3269
3270 if (instr->variables[0]->var->data.compact)
3271 stride = 1;
3272 if (indir_index) {
3273 unsigned count = glsl_count_attribute_slots(
3274 instr->variables[0]->var->type, false);
3275 count -= chan / 4;
3276 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3277 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3278 stride, true, true);
3279
3280 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3281 value, indir_index, "");
3282 build_store_values_extended(&ctx->ac, ctx->abi->outputs + idx + chan,
3283 count, stride, tmp_vec);
3284
3285 } else {
3286 temp_ptr = ctx->abi->outputs[idx + chan + const_index * stride];
3287
3288 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3289 }
3290 }
3291 break;
3292 case nir_var_local:
3293 for (unsigned chan = 0; chan < 8; chan++) {
3294 if (!(writemask & (1 << chan)))
3295 continue;
3296
3297 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3298 if (indir_index) {
3299 unsigned count = glsl_count_attribute_slots(
3300 instr->variables[0]->var->type, false);
3301 count -= chan / 4;
3302 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3303 &ctx->ac, ctx->locals + idx + chan, count,
3304 4, true, true);
3305
3306 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3307 value, indir_index, "");
3308 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3309 count, 4, tmp_vec);
3310 } else {
3311 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3312
3313 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3314 }
3315 }
3316 break;
3317 case nir_var_shared: {
3318 int writemask = instr->const_index[0];
3319 LLVMValueRef address = build_gep_for_deref(ctx,
3320 instr->variables[0]);
3321 LLVMValueRef val = get_src(ctx, instr->src[0]);
3322 unsigned components =
3323 glsl_get_vector_elements(
3324 nir_deref_tail(&instr->variables[0]->deref)->type);
3325 if (writemask == (1 << components) - 1) {
3326 val = LLVMBuildBitCast(
3327 ctx->ac.builder, val,
3328 LLVMGetElementType(LLVMTypeOf(address)), "");
3329 LLVMBuildStore(ctx->ac.builder, val, address);
3330 } else {
3331 for (unsigned chan = 0; chan < 4; chan++) {
3332 if (!(writemask & (1 << chan)))
3333 continue;
3334 LLVMValueRef ptr =
3335 LLVMBuildStructGEP(ctx->ac.builder,
3336 address, chan, "");
3337 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3338 chan);
3339 src = LLVMBuildBitCast(
3340 ctx->ac.builder, src,
3341 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3342 LLVMBuildStore(ctx->ac.builder, src, ptr);
3343 }
3344 }
3345 break;
3346 }
3347 default:
3348 break;
3349 }
3350 }
3351
3352 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3353 {
3354 switch (dim) {
3355 case GLSL_SAMPLER_DIM_BUF:
3356 return 1;
3357 case GLSL_SAMPLER_DIM_1D:
3358 return array ? 2 : 1;
3359 case GLSL_SAMPLER_DIM_2D:
3360 return array ? 3 : 2;
3361 case GLSL_SAMPLER_DIM_MS:
3362 return array ? 4 : 3;
3363 case GLSL_SAMPLER_DIM_3D:
3364 case GLSL_SAMPLER_DIM_CUBE:
3365 return 3;
3366 case GLSL_SAMPLER_DIM_RECT:
3367 case GLSL_SAMPLER_DIM_SUBPASS:
3368 return 2;
3369 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3370 return 3;
3371 default:
3372 break;
3373 }
3374 return 0;
3375 }
3376
3377 static bool
3378 glsl_is_array_image(const struct glsl_type *type)
3379 {
3380 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3381
3382 if (glsl_sampler_type_is_array(type))
3383 return true;
3384
3385 return dim == GLSL_SAMPLER_DIM_CUBE ||
3386 dim == GLSL_SAMPLER_DIM_3D ||
3387 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3388 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3389 }
3390
3391
3392 /* Adjust the sample index according to FMASK.
3393 *
3394 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3395 * which is the identity mapping. Each nibble says which physical sample
3396 * should be fetched to get that sample.
3397 *
3398 * For example, 0x11111100 means there are only 2 samples stored and
3399 * the second sample covers 3/4 of the pixel. When reading samples 0
3400 * and 1, return physical sample 0 (determined by the first two 0s
3401 * in FMASK), otherwise return physical sample 1.
3402 *
3403 * The sample index should be adjusted as follows:
3404 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3405 */
3406 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3407 LLVMValueRef coord_x, LLVMValueRef coord_y,
3408 LLVMValueRef coord_z,
3409 LLVMValueRef sample_index,
3410 LLVMValueRef fmask_desc_ptr)
3411 {
3412 LLVMValueRef fmask_load_address[4];
3413 LLVMValueRef res;
3414
3415 fmask_load_address[0] = coord_x;
3416 fmask_load_address[1] = coord_y;
3417 if (coord_z) {
3418 fmask_load_address[2] = coord_z;
3419 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3420 }
3421
3422 struct ac_image_args args = {0};
3423
3424 args.opcode = ac_image_load;
3425 args.da = coord_z ? true : false;
3426 args.resource = fmask_desc_ptr;
3427 args.dmask = 0xf;
3428 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3429
3430 res = ac_build_image_opcode(ctx, &args);
3431
3432 res = ac_to_integer(ctx, res);
3433 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3434 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3435
3436 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3437 res,
3438 ctx->i32_0, "");
3439
3440 LLVMValueRef sample_index4 =
3441 LLVMBuildMul(ctx->builder, sample_index, four, "");
3442 LLVMValueRef shifted_fmask =
3443 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3444 LLVMValueRef final_sample =
3445 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3446
3447 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3448 * resource descriptor is 0 (invalid),
3449 */
3450 LLVMValueRef fmask_desc =
3451 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3452 ctx->v8i32, "");
3453
3454 LLVMValueRef fmask_word1 =
3455 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3456 ctx->i32_1, "");
3457
3458 LLVMValueRef word1_is_nonzero =
3459 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3460 fmask_word1, ctx->i32_0, "");
3461
3462 /* Replace the MSAA sample index. */
3463 sample_index =
3464 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3465 final_sample, sample_index, "");
3466 return sample_index;
3467 }
3468
3469 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3470 const nir_intrinsic_instr *instr)
3471 {
3472 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3473
3474 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3475 LLVMValueRef coords[4];
3476 LLVMValueRef masks[] = {
3477 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3478 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3479 };
3480 LLVMValueRef res;
3481 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3482
3483 int count;
3484 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3485 bool is_array = glsl_sampler_type_is_array(type);
3486 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3487 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3488 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3489 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3490 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3491 count = image_type_to_components_count(dim, is_array);
3492
3493 if (is_ms) {
3494 LLVMValueRef fmask_load_address[3];
3495 int chan;
3496
3497 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3498 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3499 if (is_array)
3500 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3501 else
3502 fmask_load_address[2] = NULL;
3503 if (add_frag_pos) {
3504 for (chan = 0; chan < 2; ++chan)
3505 fmask_load_address[chan] =
3506 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3507 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3508 ctx->ac.i32, ""), "");
3509 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3510 }
3511 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3512 fmask_load_address[0],
3513 fmask_load_address[1],
3514 fmask_load_address[2],
3515 sample_index,
3516 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3517 }
3518 if (count == 1 && !gfx9_1d) {
3519 if (instr->src[0].ssa->num_components)
3520 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3521 else
3522 res = src0;
3523 } else {
3524 int chan;
3525 if (is_ms)
3526 count--;
3527 for (chan = 0; chan < count; ++chan) {
3528 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3529 }
3530 if (add_frag_pos) {
3531 for (chan = 0; chan < 2; ++chan)
3532 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3533 ctx->ac.i32, ""), "");
3534 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3535 count++;
3536 }
3537
3538 if (gfx9_1d) {
3539 if (is_array) {
3540 coords[2] = coords[1];
3541 coords[1] = ctx->ac.i32_0;
3542 } else
3543 coords[1] = ctx->ac.i32_0;
3544 count++;
3545 }
3546
3547 if (is_ms) {
3548 coords[count] = sample_index;
3549 count++;
3550 }
3551
3552 if (count == 3) {
3553 coords[3] = LLVMGetUndef(ctx->ac.i32);
3554 count = 4;
3555 }
3556 res = ac_build_gather_values(&ctx->ac, coords, count);
3557 }
3558 return res;
3559 }
3560
3561 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3562 const nir_intrinsic_instr *instr)
3563 {
3564 LLVMValueRef params[7];
3565 LLVMValueRef res;
3566 char intrinsic_name[64];
3567 const nir_variable *var = instr->variables[0]->var;
3568 const struct glsl_type *type = var->type;
3569
3570 if(instr->variables[0]->deref.child)
3571 type = instr->variables[0]->deref.child->type;
3572
3573 type = glsl_without_array(type);
3574
3575 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3576 if (dim == GLSL_SAMPLER_DIM_BUF) {
3577 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3578 unsigned num_channels = util_last_bit(mask);
3579 LLVMValueRef rsrc, vindex;
3580
3581 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3582 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3583 ctx->ac.i32_0, "");
3584
3585 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3586 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3587 ctx->ac.i32_0, num_channels,
3588 false, false);
3589 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3590
3591 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3592 res = ac_to_integer(&ctx->ac, res);
3593 } else {
3594 LLVMValueRef da = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false;
3595 LLVMValueRef slc = ctx->ac.i1false;
3596
3597 params[0] = get_image_coords(ctx, instr);
3598 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3599 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3600 params[3] = (var->data.image._volatile || var->data.image.coherent) ?
3601 ctx->ac.i1true : ctx->ac.i1false;
3602 params[4] = slc;
3603 params[5] = ctx->ac.i1false;
3604 params[6] = da;
3605
3606 ac_get_image_intr_name("llvm.amdgcn.image.load",
3607 ctx->ac.v4f32, /* vdata */
3608 LLVMTypeOf(params[0]), /* coords */
3609 LLVMTypeOf(params[1]), /* rsrc */
3610 intrinsic_name, sizeof(intrinsic_name));
3611
3612 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3613 params, 7, AC_FUNC_ATTR_READONLY);
3614 }
3615 return ac_to_integer(&ctx->ac, res);
3616 }
3617
3618 static void visit_image_store(struct ac_nir_context *ctx,
3619 nir_intrinsic_instr *instr)
3620 {
3621 LLVMValueRef params[8];
3622 char intrinsic_name[64];
3623 const nir_variable *var = instr->variables[0]->var;
3624 const struct glsl_type *type = glsl_without_array(var->type);
3625 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3626 LLVMValueRef glc = ctx->ac.i1false;
3627 bool force_glc = ctx->ac.chip_class == SI;
3628 if (force_glc)
3629 glc = ctx->ac.i1true;
3630
3631 if (dim == GLSL_SAMPLER_DIM_BUF) {
3632 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3633 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3634 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3635 ctx->ac.i32_0, ""); /* vindex */
3636 params[3] = ctx->ac.i32_0; /* voffset */
3637 params[4] = glc; /* glc */
3638 params[5] = ctx->ac.i1false; /* slc */
3639 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3640 params, 6, 0);
3641 } else {
3642 LLVMValueRef da = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false;
3643 LLVMValueRef slc = ctx->ac.i1false;
3644
3645 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3646 params[1] = get_image_coords(ctx, instr); /* coords */
3647 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3648 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3649 params[4] = (force_glc || var->data.image._volatile || var->data.image.coherent) ?
3650 ctx->ac.i1true : ctx->ac.i1false;
3651 params[5] = slc;
3652 params[6] = ctx->ac.i1false;
3653 params[7] = da;
3654
3655 ac_get_image_intr_name("llvm.amdgcn.image.store",
3656 LLVMTypeOf(params[0]), /* vdata */
3657 LLVMTypeOf(params[1]), /* coords */
3658 LLVMTypeOf(params[2]), /* rsrc */
3659 intrinsic_name, sizeof(intrinsic_name));
3660
3661 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3662 params, 8, 0);
3663 }
3664
3665 }
3666
3667 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3668 const nir_intrinsic_instr *instr)
3669 {
3670 LLVMValueRef params[7];
3671 int param_count = 0;
3672 const nir_variable *var = instr->variables[0]->var;
3673
3674 const char *atomic_name;
3675 char intrinsic_name[41];
3676 const struct glsl_type *type = glsl_without_array(var->type);
3677 MAYBE_UNUSED int length;
3678
3679 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3680
3681 switch (instr->intrinsic) {
3682 case nir_intrinsic_image_atomic_add:
3683 atomic_name = "add";
3684 break;
3685 case nir_intrinsic_image_atomic_min:
3686 atomic_name = is_unsigned ? "umin" : "smin";
3687 break;
3688 case nir_intrinsic_image_atomic_max:
3689 atomic_name = is_unsigned ? "umax" : "smax";
3690 break;
3691 case nir_intrinsic_image_atomic_and:
3692 atomic_name = "and";
3693 break;
3694 case nir_intrinsic_image_atomic_or:
3695 atomic_name = "or";
3696 break;
3697 case nir_intrinsic_image_atomic_xor:
3698 atomic_name = "xor";
3699 break;
3700 case nir_intrinsic_image_atomic_exchange:
3701 atomic_name = "swap";
3702 break;
3703 case nir_intrinsic_image_atomic_comp_swap:
3704 atomic_name = "cmpswap";
3705 break;
3706 default:
3707 abort();
3708 }
3709
3710 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3711 params[param_count++] = get_src(ctx, instr->src[3]);
3712 params[param_count++] = get_src(ctx, instr->src[2]);
3713
3714 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3715 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3716 NULL, true, true);
3717 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3718 ctx->ac.i32_0, ""); /* vindex */
3719 params[param_count++] = ctx->ac.i32_0; /* voffset */
3720 params[param_count++] = ctx->ac.i1false; /* slc */
3721
3722 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3723 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3724 } else {
3725 char coords_type[8];
3726
3727 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3728 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3729 NULL, true, true);
3730 params[param_count++] = ctx->ac.i1false; /* r128 */
3731 params[param_count++] = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3732 params[param_count++] = ctx->ac.i1false; /* slc */
3733
3734 build_int_type_name(LLVMTypeOf(coords),
3735 coords_type, sizeof(coords_type));
3736
3737 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3738 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3739 }
3740
3741 assert(length < sizeof(intrinsic_name));
3742 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3743 }
3744
3745 static LLVMValueRef visit_image_samples(struct ac_nir_context *ctx,
3746 const nir_intrinsic_instr *instr)
3747 {
3748 const nir_variable *var = instr->variables[0]->var;
3749 const struct glsl_type *type = glsl_without_array(var->type);
3750
3751 struct ac_image_args args = { 0 };
3752 args.da = glsl_is_array_image(type);
3753 args.dmask = 0xf;
3754 args.resource = get_sampler_desc(ctx, instr->variables[0],
3755 AC_DESC_IMAGE, NULL, true, false);
3756 args.opcode = ac_image_get_resinfo;
3757 args.addr = ctx->ac.i32_0;
3758
3759 return ac_build_image_opcode(&ctx->ac, &args);
3760 }
3761
3762 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3763 const nir_intrinsic_instr *instr)
3764 {
3765 LLVMValueRef res;
3766 const nir_variable *var = instr->variables[0]->var;
3767 const struct glsl_type *type = glsl_without_array(var->type);
3768
3769 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3770 return get_buffer_size(ctx,
3771 get_sampler_desc(ctx, instr->variables[0],
3772 AC_DESC_BUFFER, NULL, true, false), true);
3773
3774 struct ac_image_args args = { 0 };
3775
3776 args.da = glsl_is_array_image(type);
3777 args.dmask = 0xf;
3778 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3779 args.opcode = ac_image_get_resinfo;
3780 args.addr = ctx->ac.i32_0;
3781
3782 res = ac_build_image_opcode(&ctx->ac, &args);
3783
3784 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3785
3786 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3787 glsl_sampler_type_is_array(type)) {
3788 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3789 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3790 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3791 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3792 }
3793 if (ctx->ac.chip_class >= GFX9 &&
3794 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3795 glsl_sampler_type_is_array(type)) {
3796 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3797 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3798 ctx->ac.i32_1, "");
3799
3800 }
3801 return res;
3802 }
3803
3804 #define NOOP_WAITCNT 0xf7f
3805 #define LGKM_CNT 0x07f
3806 #define VM_CNT 0xf70
3807
3808 static void emit_membar(struct ac_llvm_context *ac,
3809 const nir_intrinsic_instr *instr)
3810 {
3811 unsigned waitcnt = NOOP_WAITCNT;
3812
3813 switch (instr->intrinsic) {
3814 case nir_intrinsic_memory_barrier:
3815 case nir_intrinsic_group_memory_barrier:
3816 waitcnt &= VM_CNT & LGKM_CNT;
3817 break;
3818 case nir_intrinsic_memory_barrier_atomic_counter:
3819 case nir_intrinsic_memory_barrier_buffer:
3820 case nir_intrinsic_memory_barrier_image:
3821 waitcnt &= VM_CNT;
3822 break;
3823 case nir_intrinsic_memory_barrier_shared:
3824 waitcnt &= LGKM_CNT;
3825 break;
3826 default:
3827 break;
3828 }
3829 if (waitcnt != NOOP_WAITCNT)
3830 ac_build_waitcnt(ac, waitcnt);
3831 }
3832
3833 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3834 {
3835 /* SI only (thanks to a hw bug workaround):
3836 * The real barrier instruction isn’t needed, because an entire patch
3837 * always fits into a single wave.
3838 */
3839 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3840 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3841 return;
3842 }
3843 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3844 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3845 }
3846
3847 static void emit_discard(struct ac_nir_context *ctx,
3848 const nir_intrinsic_instr *instr)
3849 {
3850 LLVMValueRef cond;
3851
3852 if (instr->intrinsic == nir_intrinsic_discard_if) {
3853 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3854 get_src(ctx, instr->src[0]),
3855 ctx->ac.i32_0, "");
3856 } else {
3857 assert(instr->intrinsic == nir_intrinsic_discard);
3858 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3859 }
3860
3861 ac_build_kill_if_false(&ctx->ac, cond);
3862 }
3863
3864 static LLVMValueRef
3865 visit_load_helper_invocation(struct ac_nir_context *ctx)
3866 {
3867 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3868 "llvm.amdgcn.ps.live",
3869 ctx->ac.i1, NULL, 0,
3870 AC_FUNC_ATTR_READNONE);
3871 result = LLVMBuildNot(ctx->ac.builder, result, "");
3872 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3873 }
3874
3875 static LLVMValueRef
3876 visit_load_local_invocation_index(struct ac_nir_context *ctx)
3877 {
3878 LLVMValueRef result;
3879 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3880 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3881 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3882
3883 return LLVMBuildAdd(ctx->ac.builder, result, thread_id, "");
3884 }
3885
3886 static LLVMValueRef
3887 visit_load_shared(struct ac_nir_context *ctx,
3888 const nir_intrinsic_instr *instr)
3889 {
3890 LLVMValueRef values[4], derived_ptr, index, ret;
3891
3892 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
3893
3894 for (int chan = 0; chan < instr->num_components; chan++) {
3895 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3896 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
3897 values[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
3898 }
3899
3900 ret = ac_build_gather_values(&ctx->ac, values, instr->num_components);
3901 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3902 }
3903
3904 static void
3905 visit_store_shared(struct ac_nir_context *ctx,
3906 const nir_intrinsic_instr *instr)
3907 {
3908 LLVMValueRef derived_ptr, data,index;
3909 LLVMBuilderRef builder = ctx->ac.builder;
3910
3911 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
3912 LLVMValueRef src = get_src(ctx, instr->src[0]);
3913
3914 int writemask = nir_intrinsic_write_mask(instr);
3915 for (int chan = 0; chan < 4; chan++) {
3916 if (!(writemask & (1 << chan))) {
3917 continue;
3918 }
3919 data = ac_llvm_extract_elem(&ctx->ac, src, chan);
3920 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3921 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3922 LLVMBuildStore(builder, data, derived_ptr);
3923 }
3924 }
3925
3926 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
3927 const nir_intrinsic_instr *instr,
3928 LLVMValueRef ptr, int src_idx)
3929 {
3930 LLVMValueRef result;
3931 LLVMValueRef src = get_src(ctx, instr->src[src_idx]);
3932
3933 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
3934 instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
3935 LLVMValueRef src1 = get_src(ctx, instr->src[src_idx + 1]);
3936 result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
3937 ptr, src, src1,
3938 LLVMAtomicOrderingSequentiallyConsistent,
3939 LLVMAtomicOrderingSequentiallyConsistent,
3940 false);
3941 } else {
3942 LLVMAtomicRMWBinOp op;
3943 switch (instr->intrinsic) {
3944 case nir_intrinsic_var_atomic_add:
3945 case nir_intrinsic_shared_atomic_add:
3946 op = LLVMAtomicRMWBinOpAdd;
3947 break;
3948 case nir_intrinsic_var_atomic_umin:
3949 case nir_intrinsic_shared_atomic_umin:
3950 op = LLVMAtomicRMWBinOpUMin;
3951 break;
3952 case nir_intrinsic_var_atomic_umax:
3953 case nir_intrinsic_shared_atomic_umax:
3954 op = LLVMAtomicRMWBinOpUMax;
3955 break;
3956 case nir_intrinsic_var_atomic_imin:
3957 case nir_intrinsic_shared_atomic_imin:
3958 op = LLVMAtomicRMWBinOpMin;
3959 break;
3960 case nir_intrinsic_var_atomic_imax:
3961 case nir_intrinsic_shared_atomic_imax:
3962 op = LLVMAtomicRMWBinOpMax;
3963 break;
3964 case nir_intrinsic_var_atomic_and:
3965 case nir_intrinsic_shared_atomic_and:
3966 op = LLVMAtomicRMWBinOpAnd;
3967 break;
3968 case nir_intrinsic_var_atomic_or:
3969 case nir_intrinsic_shared_atomic_or:
3970 op = LLVMAtomicRMWBinOpOr;
3971 break;
3972 case nir_intrinsic_var_atomic_xor:
3973 case nir_intrinsic_shared_atomic_xor:
3974 op = LLVMAtomicRMWBinOpXor;
3975 break;
3976 case nir_intrinsic_var_atomic_exchange:
3977 case nir_intrinsic_shared_atomic_exchange:
3978 op = LLVMAtomicRMWBinOpXchg;
3979 break;
3980 default:
3981 return NULL;
3982 }
3983
3984 result = LLVMBuildAtomicRMW(ctx->ac.builder, op, ptr, ac_to_integer(&ctx->ac, src),
3985 LLVMAtomicOrderingSequentiallyConsistent,
3986 false);
3987 }
3988 return result;
3989 }
3990
3991 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
3992 enum glsl_interp_mode interp, unsigned location)
3993 {
3994 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3995
3996 switch (interp) {
3997 case INTERP_MODE_FLAT:
3998 default:
3999 return NULL;
4000 case INTERP_MODE_SMOOTH:
4001 case INTERP_MODE_NONE:
4002 if (location == INTERP_CENTER)
4003 return ctx->persp_center;
4004 else if (location == INTERP_CENTROID)
4005 return ctx->persp_centroid;
4006 else if (location == INTERP_SAMPLE)
4007 return ctx->persp_sample;
4008 break;
4009 case INTERP_MODE_NOPERSPECTIVE:
4010 if (location == INTERP_CENTER)
4011 return ctx->linear_center;
4012 else if (location == INTERP_CENTROID)
4013 return ctx->linear_centroid;
4014 else if (location == INTERP_SAMPLE)
4015 return ctx->linear_sample;
4016 break;
4017 }
4018 return NULL;
4019 }
4020
4021 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
4022 LLVMValueRef sample_id)
4023 {
4024 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4025
4026 LLVMValueRef result;
4027 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4028
4029 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
4030 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4031
4032 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
4033 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4034
4035 return result;
4036 }
4037
4038 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4039 {
4040 LLVMValueRef values[2];
4041 LLVMValueRef pos[2];
4042
4043 pos[0] = ac_to_float(&ctx->ac, ctx->abi->frag_pos[0]);
4044 pos[1] = ac_to_float(&ctx->ac, ctx->abi->frag_pos[1]);
4045
4046 values[0] = ac_build_fract(&ctx->ac, pos[0], 32);
4047 values[1] = ac_build_fract(&ctx->ac, pos[1], 32);
4048 return ac_build_gather_values(&ctx->ac, values, 2);
4049 }
4050
4051 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4052 {
4053 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4054 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4055 ctx->options->key.fs.log2_num_samples :
4056 ctx->options->key.fs.log2_ps_iter_samples;
4057
4058 /* The bit pattern matches that used by fixed function fragment
4059 * processing. */
4060 static const uint16_t ps_iter_masks[] = {
4061 0xffff, /* not used */
4062 0x5555,
4063 0x1111,
4064 0x0101,
4065 0x0001,
4066 };
4067 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4068
4069 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4070
4071 LLVMValueRef result, sample_id;
4072 sample_id = unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4073 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4074 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4075 return result;
4076 }
4077
4078 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4079 const nir_intrinsic_instr *instr)
4080 {
4081 LLVMValueRef result[4];
4082 LLVMValueRef interp_param, attr_number;
4083 unsigned location;
4084 unsigned chan;
4085 LLVMValueRef src_c0 = NULL;
4086 LLVMValueRef src_c1 = NULL;
4087 LLVMValueRef src0 = NULL;
4088 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4089 switch (instr->intrinsic) {
4090 case nir_intrinsic_interp_var_at_centroid:
4091 location = INTERP_CENTROID;
4092 break;
4093 case nir_intrinsic_interp_var_at_sample:
4094 case nir_intrinsic_interp_var_at_offset:
4095 location = INTERP_CENTER;
4096 src0 = get_src(ctx, instr->src[0]);
4097 break;
4098 default:
4099 break;
4100 }
4101
4102 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4103 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4104 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4105 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4106 LLVMValueRef sample_position;
4107 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4108
4109 /* fetch sample ID */
4110 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4111
4112 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4113 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4114 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4115 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4116 }
4117 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4118 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4119
4120 if (location == INTERP_CENTER) {
4121 LLVMValueRef ij_out[2];
4122 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4123
4124 /*
4125 * take the I then J parameters, and the DDX/Y for it, and
4126 * calculate the IJ inputs for the interpolator.
4127 * temp1 = ddx * offset/sample.x + I;
4128 * interp_param.I = ddy * offset/sample.y + temp1;
4129 * temp1 = ddx * offset/sample.x + J;
4130 * interp_param.J = ddy * offset/sample.y + temp1;
4131 */
4132 for (unsigned i = 0; i < 2; i++) {
4133 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4134 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4135 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4136 ddxy_out, ix_ll, "");
4137 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4138 ddxy_out, iy_ll, "");
4139 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4140 interp_param, ix_ll, "");
4141 LLVMValueRef temp1, temp2;
4142
4143 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4144 ctx->ac.f32, "");
4145
4146 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4147 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4148
4149 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4150 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4151
4152 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4153 temp2, ctx->ac.i32, "");
4154 }
4155 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4156
4157 }
4158
4159 for (chan = 0; chan < 4; chan++) {
4160 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4161
4162 if (interp_param) {
4163 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4164 interp_param, ctx->ac.v2f32, "");
4165 LLVMValueRef i = LLVMBuildExtractElement(
4166 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4167 LLVMValueRef j = LLVMBuildExtractElement(
4168 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4169
4170 result[chan] = ac_build_fs_interp(&ctx->ac,
4171 llvm_chan, attr_number,
4172 ctx->abi->prim_mask, i, j);
4173 } else {
4174 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4175 LLVMConstInt(ctx->ac.i32, 2, false),
4176 llvm_chan, attr_number,
4177 ctx->abi->prim_mask);
4178 }
4179 }
4180 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4181 instr->variables[0]->var->data.location_frac);
4182 }
4183
4184 static void
4185 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4186 {
4187 LLVMValueRef gs_next_vertex;
4188 LLVMValueRef can_emit;
4189 int idx;
4190 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4191
4192 assert(stream == 0);
4193
4194 /* Write vertex attribute values to GSVS ring */
4195 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4196 ctx->gs_next_vertex,
4197 "");
4198
4199 /* If this thread has already emitted the declared maximum number of
4200 * vertices, kill it: excessive vertex emissions are not supposed to
4201 * have any effect, and GS threads have no externally observable
4202 * effects other than emitting vertices.
4203 */
4204 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4205 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4206 ac_build_kill_if_false(&ctx->ac, can_emit);
4207
4208 /* loop num outputs */
4209 idx = 0;
4210 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4211 LLVMValueRef *out_ptr = &addrs[i * 4];
4212 int length = 4;
4213 int slot = idx;
4214 int slot_inc = 1;
4215
4216 if (!(ctx->output_mask & (1ull << i)))
4217 continue;
4218
4219 if (i == VARYING_SLOT_CLIP_DIST0) {
4220 /* pack clip and cull into a single set of slots */
4221 length = ctx->num_output_clips + ctx->num_output_culls;
4222 if (length > 4)
4223 slot_inc = 2;
4224 }
4225 for (unsigned j = 0; j < length; j++) {
4226 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4227 out_ptr[j], "");
4228 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4229 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4230 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4231
4232 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4233
4234 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4235 out_val, 1,
4236 voffset, ctx->gs2vs_offset, 0,
4237 1, 1, true, true);
4238 }
4239 idx += slot_inc;
4240 }
4241
4242 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
4243 ctx->ac.i32_1, "");
4244 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
4245
4246 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4247 }
4248
4249 static void
4250 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4251 {
4252 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4253 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4254 }
4255
4256 static LLVMValueRef
4257 load_tess_coord(struct ac_shader_abi *abi)
4258 {
4259 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4260
4261 LLVMValueRef coord[4] = {
4262 ctx->tes_u,
4263 ctx->tes_v,
4264 ctx->ac.f32_0,
4265 ctx->ac.f32_0,
4266 };
4267
4268 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4269 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
4270 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
4271
4272 return ac_build_gather_values(&ctx->ac, coord, 3);
4273 }
4274
4275 static LLVMValueRef
4276 load_patch_vertices_in(struct ac_shader_abi *abi)
4277 {
4278 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4279 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4280 }
4281
4282 static void visit_intrinsic(struct ac_nir_context *ctx,
4283 nir_intrinsic_instr *instr)
4284 {
4285 LLVMValueRef result = NULL;
4286
4287 switch (instr->intrinsic) {
4288 case nir_intrinsic_ballot:
4289 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4290 break;
4291 case nir_intrinsic_read_invocation:
4292 case nir_intrinsic_read_first_invocation: {
4293 LLVMValueRef args[2];
4294
4295 /* Value */
4296 args[0] = get_src(ctx, instr->src[0]);
4297
4298 unsigned num_args;
4299 const char *intr_name;
4300 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4301 num_args = 2;
4302 intr_name = "llvm.amdgcn.readlane";
4303
4304 /* Invocation */
4305 args[1] = get_src(ctx, instr->src[1]);
4306 } else {
4307 num_args = 1;
4308 intr_name = "llvm.amdgcn.readfirstlane";
4309 }
4310
4311 /* We currently have no other way to prevent LLVM from lifting the icmp
4312 * calls to a dominating basic block.
4313 */
4314 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4315
4316 result = ac_build_intrinsic(&ctx->ac, intr_name,
4317 ctx->ac.i32, args, num_args,
4318 AC_FUNC_ATTR_READNONE |
4319 AC_FUNC_ATTR_CONVERGENT);
4320 break;
4321 }
4322 case nir_intrinsic_load_subgroup_invocation:
4323 result = ac_get_thread_id(&ctx->ac);
4324 break;
4325 case nir_intrinsic_load_work_group_id: {
4326 LLVMValueRef values[3];
4327
4328 for (int i = 0; i < 3; i++) {
4329 values[i] = ctx->abi->workgroup_ids[i] ?
4330 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4331 }
4332
4333 result = ac_build_gather_values(&ctx->ac, values, 3);
4334 break;
4335 }
4336 case nir_intrinsic_load_base_vertex: {
4337 result = ctx->abi->load_base_vertex(ctx->abi);
4338 break;
4339 }
4340 case nir_intrinsic_load_local_group_size:
4341 result = ctx->abi->load_local_group_size(ctx->abi);
4342 break;
4343 case nir_intrinsic_load_vertex_id:
4344 result = LLVMBuildAdd(ctx->ac.builder, ctx->abi->vertex_id,
4345 ctx->abi->base_vertex, "");
4346 break;
4347 case nir_intrinsic_load_vertex_id_zero_base: {
4348 result = ctx->abi->vertex_id;
4349 break;
4350 }
4351 case nir_intrinsic_load_local_invocation_id: {
4352 result = ctx->abi->local_invocation_ids;
4353 break;
4354 }
4355 case nir_intrinsic_load_base_instance:
4356 result = ctx->abi->start_instance;
4357 break;
4358 case nir_intrinsic_load_draw_id:
4359 result = ctx->abi->draw_id;
4360 break;
4361 case nir_intrinsic_load_view_index:
4362 result = ctx->abi->view_index;
4363 break;
4364 case nir_intrinsic_load_invocation_id:
4365 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4366 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4367 else
4368 result = ctx->abi->gs_invocation_id;
4369 break;
4370 case nir_intrinsic_load_primitive_id:
4371 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4372 result = ctx->abi->gs_prim_id;
4373 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4374 result = ctx->abi->tcs_patch_id;
4375 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4376 result = ctx->abi->tes_patch_id;
4377 } else
4378 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4379 break;
4380 case nir_intrinsic_load_sample_id:
4381 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4382 break;
4383 case nir_intrinsic_load_sample_pos:
4384 result = load_sample_pos(ctx);
4385 break;
4386 case nir_intrinsic_load_sample_mask_in:
4387 result = ctx->abi->load_sample_mask_in(ctx->abi);
4388 break;
4389 case nir_intrinsic_load_frag_coord: {
4390 LLVMValueRef values[4] = {
4391 ctx->abi->frag_pos[0],
4392 ctx->abi->frag_pos[1],
4393 ctx->abi->frag_pos[2],
4394 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4395 };
4396 result = ac_build_gather_values(&ctx->ac, values, 4);
4397 break;
4398 }
4399 case nir_intrinsic_load_front_face:
4400 result = ctx->abi->front_face;
4401 break;
4402 case nir_intrinsic_load_helper_invocation:
4403 result = visit_load_helper_invocation(ctx);
4404 break;
4405 case nir_intrinsic_load_instance_id:
4406 result = ctx->abi->instance_id;
4407 break;
4408 case nir_intrinsic_load_num_work_groups:
4409 result = ctx->abi->num_work_groups;
4410 break;
4411 case nir_intrinsic_load_local_invocation_index:
4412 result = visit_load_local_invocation_index(ctx);
4413 break;
4414 case nir_intrinsic_load_push_constant:
4415 result = visit_load_push_constant(ctx, instr);
4416 break;
4417 case nir_intrinsic_vulkan_resource_index: {
4418 LLVMValueRef index = get_src(ctx, instr->src[0]);
4419 unsigned desc_set = nir_intrinsic_desc_set(instr);
4420 unsigned binding = nir_intrinsic_binding(instr);
4421
4422 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4423 binding);
4424 break;
4425 }
4426 case nir_intrinsic_vulkan_resource_reindex:
4427 result = visit_vulkan_resource_reindex(ctx, instr);
4428 break;
4429 case nir_intrinsic_store_ssbo:
4430 visit_store_ssbo(ctx, instr);
4431 break;
4432 case nir_intrinsic_load_ssbo:
4433 result = visit_load_buffer(ctx, instr);
4434 break;
4435 case nir_intrinsic_ssbo_atomic_add:
4436 case nir_intrinsic_ssbo_atomic_imin:
4437 case nir_intrinsic_ssbo_atomic_umin:
4438 case nir_intrinsic_ssbo_atomic_imax:
4439 case nir_intrinsic_ssbo_atomic_umax:
4440 case nir_intrinsic_ssbo_atomic_and:
4441 case nir_intrinsic_ssbo_atomic_or:
4442 case nir_intrinsic_ssbo_atomic_xor:
4443 case nir_intrinsic_ssbo_atomic_exchange:
4444 case nir_intrinsic_ssbo_atomic_comp_swap:
4445 result = visit_atomic_ssbo(ctx, instr);
4446 break;
4447 case nir_intrinsic_load_ubo:
4448 result = visit_load_ubo_buffer(ctx, instr);
4449 break;
4450 case nir_intrinsic_get_buffer_size:
4451 result = visit_get_buffer_size(ctx, instr);
4452 break;
4453 case nir_intrinsic_load_var:
4454 result = visit_load_var(ctx, instr);
4455 break;
4456 case nir_intrinsic_store_var:
4457 visit_store_var(ctx, instr);
4458 break;
4459 case nir_intrinsic_load_shared:
4460 result = visit_load_shared(ctx, instr);
4461 break;
4462 case nir_intrinsic_store_shared:
4463 visit_store_shared(ctx, instr);
4464 break;
4465 case nir_intrinsic_image_samples:
4466 result = visit_image_samples(ctx, instr);
4467 break;
4468 case nir_intrinsic_image_load:
4469 result = visit_image_load(ctx, instr);
4470 break;
4471 case nir_intrinsic_image_store:
4472 visit_image_store(ctx, instr);
4473 break;
4474 case nir_intrinsic_image_atomic_add:
4475 case nir_intrinsic_image_atomic_min:
4476 case nir_intrinsic_image_atomic_max:
4477 case nir_intrinsic_image_atomic_and:
4478 case nir_intrinsic_image_atomic_or:
4479 case nir_intrinsic_image_atomic_xor:
4480 case nir_intrinsic_image_atomic_exchange:
4481 case nir_intrinsic_image_atomic_comp_swap:
4482 result = visit_image_atomic(ctx, instr);
4483 break;
4484 case nir_intrinsic_image_size:
4485 result = visit_image_size(ctx, instr);
4486 break;
4487 case nir_intrinsic_shader_clock:
4488 result = ac_build_shader_clock(&ctx->ac);
4489 break;
4490 case nir_intrinsic_discard:
4491 case nir_intrinsic_discard_if:
4492 emit_discard(ctx, instr);
4493 break;
4494 case nir_intrinsic_memory_barrier:
4495 case nir_intrinsic_group_memory_barrier:
4496 case nir_intrinsic_memory_barrier_atomic_counter:
4497 case nir_intrinsic_memory_barrier_buffer:
4498 case nir_intrinsic_memory_barrier_image:
4499 case nir_intrinsic_memory_barrier_shared:
4500 emit_membar(&ctx->ac, instr);
4501 break;
4502 case nir_intrinsic_barrier:
4503 emit_barrier(&ctx->ac, ctx->stage);
4504 break;
4505 case nir_intrinsic_shared_atomic_add:
4506 case nir_intrinsic_shared_atomic_imin:
4507 case nir_intrinsic_shared_atomic_umin:
4508 case nir_intrinsic_shared_atomic_imax:
4509 case nir_intrinsic_shared_atomic_umax:
4510 case nir_intrinsic_shared_atomic_and:
4511 case nir_intrinsic_shared_atomic_or:
4512 case nir_intrinsic_shared_atomic_xor:
4513 case nir_intrinsic_shared_atomic_exchange:
4514 case nir_intrinsic_shared_atomic_comp_swap: {
4515 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
4516 result = visit_var_atomic(ctx, instr, ptr, 1);
4517 break;
4518 }
4519 case nir_intrinsic_var_atomic_add:
4520 case nir_intrinsic_var_atomic_imin:
4521 case nir_intrinsic_var_atomic_umin:
4522 case nir_intrinsic_var_atomic_imax:
4523 case nir_intrinsic_var_atomic_umax:
4524 case nir_intrinsic_var_atomic_and:
4525 case nir_intrinsic_var_atomic_or:
4526 case nir_intrinsic_var_atomic_xor:
4527 case nir_intrinsic_var_atomic_exchange:
4528 case nir_intrinsic_var_atomic_comp_swap: {
4529 LLVMValueRef ptr = build_gep_for_deref(ctx, instr->variables[0]);
4530 result = visit_var_atomic(ctx, instr, ptr, 0);
4531 break;
4532 }
4533 case nir_intrinsic_interp_var_at_centroid:
4534 case nir_intrinsic_interp_var_at_sample:
4535 case nir_intrinsic_interp_var_at_offset:
4536 result = visit_interp(ctx, instr);
4537 break;
4538 case nir_intrinsic_emit_vertex:
4539 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->abi->outputs);
4540 break;
4541 case nir_intrinsic_end_primitive:
4542 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4543 break;
4544 case nir_intrinsic_load_tess_coord:
4545 result = ctx->abi->load_tess_coord(ctx->abi);
4546 break;
4547 case nir_intrinsic_load_tess_level_outer:
4548 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4549 break;
4550 case nir_intrinsic_load_tess_level_inner:
4551 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4552 break;
4553 case nir_intrinsic_load_patch_vertices_in:
4554 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4555 break;
4556 case nir_intrinsic_vote_all: {
4557 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4558 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4559 break;
4560 }
4561 case nir_intrinsic_vote_any: {
4562 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4563 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4564 break;
4565 }
4566 case nir_intrinsic_vote_eq: {
4567 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4568 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4569 break;
4570 }
4571 default:
4572 fprintf(stderr, "Unknown intrinsic: ");
4573 nir_print_instr(&instr->instr, stderr);
4574 fprintf(stderr, "\n");
4575 break;
4576 }
4577 if (result) {
4578 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4579 }
4580 }
4581
4582 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
4583 {
4584 return abi->base_vertex;
4585 }
4586
4587 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4588 LLVMValueRef buffer_ptr, bool write)
4589 {
4590 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4591 LLVMValueRef result;
4592
4593 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4594
4595 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4596 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4597
4598 return result;
4599 }
4600
4601 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4602 {
4603 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4604 LLVMValueRef result;
4605
4606 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4607
4608 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4609 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4610
4611 return result;
4612 }
4613
4614 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4615 unsigned descriptor_set,
4616 unsigned base_index,
4617 unsigned constant_index,
4618 LLVMValueRef index,
4619 enum ac_descriptor_type desc_type,
4620 bool image, bool write)
4621 {
4622 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4623 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4624 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4625 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4626 unsigned offset = binding->offset;
4627 unsigned stride = binding->size;
4628 unsigned type_size;
4629 LLVMBuilderRef builder = ctx->ac.builder;
4630 LLVMTypeRef type;
4631
4632 assert(base_index < layout->binding_count);
4633
4634 switch (desc_type) {
4635 case AC_DESC_IMAGE:
4636 type = ctx->ac.v8i32;
4637 type_size = 32;
4638 break;
4639 case AC_DESC_FMASK:
4640 type = ctx->ac.v8i32;
4641 offset += 32;
4642 type_size = 32;
4643 break;
4644 case AC_DESC_SAMPLER:
4645 type = ctx->ac.v4i32;
4646 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4647 offset += 64;
4648
4649 type_size = 16;
4650 break;
4651 case AC_DESC_BUFFER:
4652 type = ctx->ac.v4i32;
4653 type_size = 16;
4654 break;
4655 default:
4656 unreachable("invalid desc_type\n");
4657 }
4658
4659 offset += constant_index * stride;
4660
4661 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4662 (!index || binding->immutable_samplers_equal)) {
4663 if (binding->immutable_samplers_equal)
4664 constant_index = 0;
4665
4666 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4667
4668 LLVMValueRef constants[] = {
4669 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4670 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4671 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4672 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4673 };
4674 return ac_build_gather_values(&ctx->ac, constants, 4);
4675 }
4676
4677 assert(stride % type_size == 0);
4678
4679 if (!index)
4680 index = ctx->ac.i32_0;
4681
4682 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4683
4684 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4685 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4686
4687 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4688 }
4689
4690 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4691 const nir_deref_var *deref,
4692 enum ac_descriptor_type desc_type,
4693 const nir_tex_instr *tex_instr,
4694 bool image, bool write)
4695 {
4696 LLVMValueRef index = NULL;
4697 unsigned constant_index = 0;
4698 unsigned descriptor_set;
4699 unsigned base_index;
4700
4701 if (!deref) {
4702 assert(tex_instr && !image);
4703 descriptor_set = 0;
4704 base_index = tex_instr->sampler_index;
4705 } else {
4706 const nir_deref *tail = &deref->deref;
4707 while (tail->child) {
4708 const nir_deref_array *child = nir_deref_as_array(tail->child);
4709 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4710
4711 if (!array_size)
4712 array_size = 1;
4713
4714 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4715
4716 if (child->deref_array_type == nir_deref_array_type_indirect) {
4717 LLVMValueRef indirect = get_src(ctx, child->indirect);
4718
4719 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4720 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4721
4722 if (!index)
4723 index = indirect;
4724 else
4725 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4726 }
4727
4728 constant_index += child->base_offset * array_size;
4729
4730 tail = &child->deref;
4731 }
4732 descriptor_set = deref->var->data.descriptor_set;
4733 base_index = deref->var->data.binding;
4734 }
4735
4736 return ctx->abi->load_sampler_desc(ctx->abi,
4737 descriptor_set,
4738 base_index,
4739 constant_index, index,
4740 desc_type, image, write);
4741 }
4742
4743 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4744 struct ac_image_args *args,
4745 const nir_tex_instr *instr,
4746 nir_texop op,
4747 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4748 LLVMValueRef *param, unsigned count,
4749 unsigned dmask)
4750 {
4751 unsigned is_rect = 0;
4752 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4753
4754 if (op == nir_texop_lod)
4755 da = false;
4756 /* Pad to power of two vector */
4757 while (count < util_next_power_of_two(count))
4758 param[count++] = LLVMGetUndef(ctx->i32);
4759
4760 if (count > 1)
4761 args->addr = ac_build_gather_values(ctx, param, count);
4762 else
4763 args->addr = param[0];
4764
4765 args->resource = res_ptr;
4766 args->sampler = samp_ptr;
4767
4768 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4769 args->addr = param[0];
4770 return;
4771 }
4772
4773 args->dmask = dmask;
4774 args->unorm = is_rect;
4775 args->da = da;
4776 }
4777
4778 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4779 *
4780 * SI-CI:
4781 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4782 * filtering manually. The driver sets img7 to a mask clearing
4783 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4784 * s_and_b32 samp0, samp0, img7
4785 *
4786 * VI:
4787 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4788 */
4789 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4790 LLVMValueRef res, LLVMValueRef samp)
4791 {
4792 LLVMBuilderRef builder = ctx->ac.builder;
4793 LLVMValueRef img7, samp0;
4794
4795 if (ctx->ac.chip_class >= VI)
4796 return samp;
4797
4798 img7 = LLVMBuildExtractElement(builder, res,
4799 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4800 samp0 = LLVMBuildExtractElement(builder, samp,
4801 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4802 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4803 return LLVMBuildInsertElement(builder, samp, samp0,
4804 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4805 }
4806
4807 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4808 nir_tex_instr *instr,
4809 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4810 LLVMValueRef *fmask_ptr)
4811 {
4812 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4813 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4814 else
4815 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4816 if (samp_ptr) {
4817 if (instr->sampler)
4818 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4819 else
4820 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4821 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4822 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4823 }
4824 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4825 instr->op == nir_texop_samples_identical))
4826 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4827 }
4828
4829 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4830 LLVMValueRef coord)
4831 {
4832 coord = ac_to_float(ctx, coord);
4833 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4834 coord = ac_to_integer(ctx, coord);
4835 return coord;
4836 }
4837
4838 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4839 {
4840 LLVMValueRef result = NULL;
4841 struct ac_image_args args = { 0 };
4842 unsigned dmask = 0xf;
4843 LLVMValueRef address[16];
4844 LLVMValueRef coords[5];
4845 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4846 LLVMValueRef bias = NULL, offsets = NULL;
4847 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4848 LLVMValueRef ddx = NULL, ddy = NULL;
4849 LLVMValueRef derivs[6];
4850 unsigned chan, count = 0;
4851 unsigned const_src = 0, num_deriv_comp = 0;
4852 bool lod_is_zero = false;
4853
4854 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4855
4856 for (unsigned i = 0; i < instr->num_srcs; i++) {
4857 switch (instr->src[i].src_type) {
4858 case nir_tex_src_coord:
4859 coord = get_src(ctx, instr->src[i].src);
4860 break;
4861 case nir_tex_src_projector:
4862 break;
4863 case nir_tex_src_comparator:
4864 comparator = get_src(ctx, instr->src[i].src);
4865 break;
4866 case nir_tex_src_offset:
4867 offsets = get_src(ctx, instr->src[i].src);
4868 const_src = i;
4869 break;
4870 case nir_tex_src_bias:
4871 bias = get_src(ctx, instr->src[i].src);
4872 break;
4873 case nir_tex_src_lod: {
4874 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4875
4876 if (val && val->i32[0] == 0)
4877 lod_is_zero = true;
4878 lod = get_src(ctx, instr->src[i].src);
4879 break;
4880 }
4881 case nir_tex_src_ms_index:
4882 sample_index = get_src(ctx, instr->src[i].src);
4883 break;
4884 case nir_tex_src_ms_mcs:
4885 break;
4886 case nir_tex_src_ddx:
4887 ddx = get_src(ctx, instr->src[i].src);
4888 num_deriv_comp = instr->src[i].src.ssa->num_components;
4889 break;
4890 case nir_tex_src_ddy:
4891 ddy = get_src(ctx, instr->src[i].src);
4892 break;
4893 case nir_tex_src_texture_offset:
4894 case nir_tex_src_sampler_offset:
4895 case nir_tex_src_plane:
4896 default:
4897 break;
4898 }
4899 }
4900
4901 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4902 result = get_buffer_size(ctx, res_ptr, true);
4903 goto write_result;
4904 }
4905
4906 if (instr->op == nir_texop_texture_samples) {
4907 LLVMValueRef res, samples, is_msaa;
4908 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4909 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4910 LLVMConstInt(ctx->ac.i32, 3, false), "");
4911 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4912 LLVMConstInt(ctx->ac.i32, 28, false), "");
4913 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4914 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4915 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4916 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4917
4918 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4919 LLVMConstInt(ctx->ac.i32, 16, false), "");
4920 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4921 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4922 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4923 samples, "");
4924 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4925 ctx->ac.i32_1, "");
4926 result = samples;
4927 goto write_result;
4928 }
4929
4930 if (coord)
4931 for (chan = 0; chan < instr->coord_components; chan++)
4932 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4933
4934 if (offsets && instr->op != nir_texop_txf) {
4935 LLVMValueRef offset[3], pack;
4936 for (chan = 0; chan < 3; ++chan)
4937 offset[chan] = ctx->ac.i32_0;
4938
4939 args.offset = true;
4940 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4941 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4942 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4943 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4944 if (chan)
4945 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4946 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4947 }
4948 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4949 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4950 address[count++] = pack;
4951
4952 }
4953 /* pack LOD bias value */
4954 if (instr->op == nir_texop_txb && bias) {
4955 address[count++] = bias;
4956 }
4957
4958 /* Pack depth comparison value */
4959 if (instr->is_shadow && comparator) {
4960 LLVMValueRef z = ac_to_float(&ctx->ac,
4961 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4962
4963 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4964 * so the depth comparison value isn't clamped for Z16 and
4965 * Z24 anymore. Do it manually here.
4966 *
4967 * It's unnecessary if the original texture format was
4968 * Z32_FLOAT, but we don't know that here.
4969 */
4970 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4971 z = ac_build_clamp(&ctx->ac, z);
4972
4973 address[count++] = z;
4974 }
4975
4976 /* pack derivatives */
4977 if (ddx || ddy) {
4978 int num_src_deriv_channels, num_dest_deriv_channels;
4979 switch (instr->sampler_dim) {
4980 case GLSL_SAMPLER_DIM_3D:
4981 case GLSL_SAMPLER_DIM_CUBE:
4982 num_deriv_comp = 3;
4983 num_src_deriv_channels = 3;
4984 num_dest_deriv_channels = 3;
4985 break;
4986 case GLSL_SAMPLER_DIM_2D:
4987 default:
4988 num_src_deriv_channels = 2;
4989 num_dest_deriv_channels = 2;
4990 num_deriv_comp = 2;
4991 break;
4992 case GLSL_SAMPLER_DIM_1D:
4993 num_src_deriv_channels = 1;
4994 if (ctx->ac.chip_class >= GFX9) {
4995 num_dest_deriv_channels = 2;
4996 num_deriv_comp = 2;
4997 } else {
4998 num_dest_deriv_channels = 1;
4999 num_deriv_comp = 1;
5000 }
5001 break;
5002 }
5003
5004 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
5005 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
5006 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
5007 }
5008 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
5009 derivs[i] = ctx->ac.f32_0;
5010 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
5011 }
5012 }
5013
5014 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
5015 for (chan = 0; chan < instr->coord_components; chan++)
5016 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
5017 if (instr->coord_components == 3)
5018 coords[3] = LLVMGetUndef(ctx->ac.f32);
5019 ac_prepare_cube_coords(&ctx->ac,
5020 instr->op == nir_texop_txd, instr->is_array,
5021 instr->op == nir_texop_lod, coords, derivs);
5022 if (num_deriv_comp)
5023 num_deriv_comp--;
5024 }
5025
5026 if (ddx || ddy) {
5027 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
5028 address[count++] = derivs[i];
5029 }
5030
5031 /* Pack texture coordinates */
5032 if (coord) {
5033 address[count++] = coords[0];
5034 if (instr->coord_components > 1) {
5035 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
5036 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
5037 }
5038 address[count++] = coords[1];
5039 }
5040 if (instr->coord_components > 2) {
5041 if ((instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
5042 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
5043 instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
5044 instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
5045 instr->is_array &&
5046 instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
5047 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
5048 }
5049 address[count++] = coords[2];
5050 }
5051
5052 if (ctx->ac.chip_class >= GFX9) {
5053 LLVMValueRef filler;
5054 if (instr->op == nir_texop_txf)
5055 filler = ctx->ac.i32_0;
5056 else
5057 filler = LLVMConstReal(ctx->ac.f32, 0.5);
5058
5059 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
5060 /* No nir_texop_lod, because it does not take a slice
5061 * even with array textures. */
5062 if (instr->is_array && instr->op != nir_texop_lod ) {
5063 address[count] = address[count - 1];
5064 address[count - 1] = filler;
5065 count++;
5066 } else
5067 address[count++] = filler;
5068 }
5069 }
5070 }
5071
5072 /* Pack LOD */
5073 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5074 instr->op == nir_texop_txf)) {
5075 address[count++] = lod;
5076 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5077 address[count++] = sample_index;
5078 } else if(instr->op == nir_texop_txs) {
5079 count = 0;
5080 if (lod)
5081 address[count++] = lod;
5082 else
5083 address[count++] = ctx->ac.i32_0;
5084 }
5085
5086 for (chan = 0; chan < count; chan++) {
5087 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5088 address[chan], ctx->ac.i32, "");
5089 }
5090
5091 if (instr->op == nir_texop_samples_identical) {
5092 LLVMValueRef txf_address[4];
5093 struct ac_image_args txf_args = { 0 };
5094 unsigned txf_count = count;
5095 memcpy(txf_address, address, sizeof(txf_address));
5096
5097 if (!instr->is_array)
5098 txf_address[2] = ctx->ac.i32_0;
5099 txf_address[3] = ctx->ac.i32_0;
5100
5101 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5102 fmask_ptr, NULL,
5103 txf_address, txf_count, 0xf);
5104
5105 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5106
5107 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5108 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5109 goto write_result;
5110 }
5111
5112 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5113 instr->op != nir_texop_txs) {
5114 unsigned sample_chan = instr->is_array ? 3 : 2;
5115 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5116 address[0],
5117 address[1],
5118 instr->is_array ? address[2] : NULL,
5119 address[sample_chan],
5120 fmask_ptr);
5121 }
5122
5123 if (offsets && instr->op == nir_texop_txf) {
5124 nir_const_value *const_offset =
5125 nir_src_as_const_value(instr->src[const_src].src);
5126 int num_offsets = instr->src[const_src].src.ssa->num_components;
5127 assert(const_offset);
5128 num_offsets = MIN2(num_offsets, instr->coord_components);
5129 if (num_offsets > 2)
5130 address[2] = LLVMBuildAdd(ctx->ac.builder,
5131 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5132 if (num_offsets > 1)
5133 address[1] = LLVMBuildAdd(ctx->ac.builder,
5134 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5135 address[0] = LLVMBuildAdd(ctx->ac.builder,
5136 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5137
5138 }
5139
5140 /* TODO TG4 support */
5141 if (instr->op == nir_texop_tg4) {
5142 if (instr->is_shadow)
5143 dmask = 1;
5144 else
5145 dmask = 1 << instr->component;
5146 }
5147 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5148 res_ptr, samp_ptr, address, count, dmask);
5149
5150 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5151
5152 if (instr->op == nir_texop_query_levels)
5153 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5154 else if (instr->is_shadow && instr->is_new_style_shadow &&
5155 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5156 instr->op != nir_texop_tg4)
5157 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5158 else if (instr->op == nir_texop_txs &&
5159 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5160 instr->is_array) {
5161 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5162 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5163 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5164 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5165 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5166 } else if (ctx->ac.chip_class >= GFX9 &&
5167 instr->op == nir_texop_txs &&
5168 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5169 instr->is_array) {
5170 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5171 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5172 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5173 ctx->ac.i32_1, "");
5174 } else if (instr->dest.ssa.num_components != 4)
5175 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5176
5177 write_result:
5178 if (result) {
5179 assert(instr->dest.is_ssa);
5180 result = ac_to_integer(&ctx->ac, result);
5181 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5182 }
5183 }
5184
5185
5186 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5187 {
5188 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5189 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5190
5191 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5192 _mesa_hash_table_insert(ctx->phis, instr, result);
5193 }
5194
5195 static void visit_post_phi(struct ac_nir_context *ctx,
5196 nir_phi_instr *instr,
5197 LLVMValueRef llvm_phi)
5198 {
5199 nir_foreach_phi_src(src, instr) {
5200 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5201 LLVMValueRef llvm_src = get_src(ctx, src->src);
5202
5203 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5204 }
5205 }
5206
5207 static void phi_post_pass(struct ac_nir_context *ctx)
5208 {
5209 struct hash_entry *entry;
5210 hash_table_foreach(ctx->phis, entry) {
5211 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5212 (LLVMValueRef)entry->data);
5213 }
5214 }
5215
5216
5217 static void visit_ssa_undef(struct ac_nir_context *ctx,
5218 const nir_ssa_undef_instr *instr)
5219 {
5220 unsigned num_components = instr->def.num_components;
5221 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5222 LLVMValueRef undef;
5223
5224 if (num_components == 1)
5225 undef = LLVMGetUndef(type);
5226 else {
5227 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5228 }
5229 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5230 }
5231
5232 static void visit_jump(struct ac_nir_context *ctx,
5233 const nir_jump_instr *instr)
5234 {
5235 switch (instr->type) {
5236 case nir_jump_break:
5237 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5238 LLVMClearInsertionPosition(ctx->ac.builder);
5239 break;
5240 case nir_jump_continue:
5241 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5242 LLVMClearInsertionPosition(ctx->ac.builder);
5243 break;
5244 default:
5245 fprintf(stderr, "Unknown NIR jump instr: ");
5246 nir_print_instr(&instr->instr, stderr);
5247 fprintf(stderr, "\n");
5248 abort();
5249 }
5250 }
5251
5252 static void visit_cf_list(struct ac_nir_context *ctx,
5253 struct exec_list *list);
5254
5255 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5256 {
5257 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5258 nir_foreach_instr(instr, block)
5259 {
5260 switch (instr->type) {
5261 case nir_instr_type_alu:
5262 visit_alu(ctx, nir_instr_as_alu(instr));
5263 break;
5264 case nir_instr_type_load_const:
5265 visit_load_const(ctx, nir_instr_as_load_const(instr));
5266 break;
5267 case nir_instr_type_intrinsic:
5268 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5269 break;
5270 case nir_instr_type_tex:
5271 visit_tex(ctx, nir_instr_as_tex(instr));
5272 break;
5273 case nir_instr_type_phi:
5274 visit_phi(ctx, nir_instr_as_phi(instr));
5275 break;
5276 case nir_instr_type_ssa_undef:
5277 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5278 break;
5279 case nir_instr_type_jump:
5280 visit_jump(ctx, nir_instr_as_jump(instr));
5281 break;
5282 default:
5283 fprintf(stderr, "Unknown NIR instr type: ");
5284 nir_print_instr(instr, stderr);
5285 fprintf(stderr, "\n");
5286 abort();
5287 }
5288 }
5289
5290 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5291 }
5292
5293 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5294 {
5295 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5296
5297 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5298 LLVMBasicBlockRef merge_block =
5299 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5300 LLVMBasicBlockRef if_block =
5301 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5302 LLVMBasicBlockRef else_block = merge_block;
5303 if (!exec_list_is_empty(&if_stmt->else_list))
5304 else_block = LLVMAppendBasicBlockInContext(
5305 ctx->ac.context, fn, "");
5306
5307 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5308 ctx->ac.i32_0, "");
5309 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5310
5311 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5312 visit_cf_list(ctx, &if_stmt->then_list);
5313 if (LLVMGetInsertBlock(ctx->ac.builder))
5314 LLVMBuildBr(ctx->ac.builder, merge_block);
5315
5316 if (!exec_list_is_empty(&if_stmt->else_list)) {
5317 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5318 visit_cf_list(ctx, &if_stmt->else_list);
5319 if (LLVMGetInsertBlock(ctx->ac.builder))
5320 LLVMBuildBr(ctx->ac.builder, merge_block);
5321 }
5322
5323 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5324 }
5325
5326 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5327 {
5328 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5329 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5330 LLVMBasicBlockRef break_parent = ctx->break_block;
5331
5332 ctx->continue_block =
5333 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5334 ctx->break_block =
5335 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5336
5337 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5338 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5339 visit_cf_list(ctx, &loop->body);
5340
5341 if (LLVMGetInsertBlock(ctx->ac.builder))
5342 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5343 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5344
5345 ctx->continue_block = continue_parent;
5346 ctx->break_block = break_parent;
5347 }
5348
5349 static void visit_cf_list(struct ac_nir_context *ctx,
5350 struct exec_list *list)
5351 {
5352 foreach_list_typed(nir_cf_node, node, node, list)
5353 {
5354 switch (node->type) {
5355 case nir_cf_node_block:
5356 visit_block(ctx, nir_cf_node_as_block(node));
5357 break;
5358
5359 case nir_cf_node_if:
5360 visit_if(ctx, nir_cf_node_as_if(node));
5361 break;
5362
5363 case nir_cf_node_loop:
5364 visit_loop(ctx, nir_cf_node_as_loop(node));
5365 break;
5366
5367 default:
5368 assert(0);
5369 }
5370 }
5371 }
5372
5373 static void
5374 handle_vs_input_decl(struct radv_shader_context *ctx,
5375 struct nir_variable *variable)
5376 {
5377 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5378 LLVMValueRef t_offset;
5379 LLVMValueRef t_list;
5380 LLVMValueRef input;
5381 LLVMValueRef buffer_index;
5382 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5383 int idx = variable->data.location;
5384 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5385 uint8_t input_usage_mask =
5386 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5387 unsigned num_channels = util_last_bit(input_usage_mask);
5388
5389 variable->data.driver_location = idx * 4;
5390
5391 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5392 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5393 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
5394 ctx->abi.start_instance, "");
5395 if (ctx->options->key.vs.as_ls) {
5396 ctx->shader_info->vs.vgpr_comp_cnt =
5397 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5398 } else {
5399 ctx->shader_info->vs.vgpr_comp_cnt =
5400 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5401 }
5402 } else
5403 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
5404 ctx->abi.base_vertex, "");
5405 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5406
5407 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5408
5409 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5410 buffer_index,
5411 ctx->ac.i32_0,
5412 num_channels, false, true);
5413
5414 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5415
5416 for (unsigned chan = 0; chan < 4; chan++) {
5417 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5418 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5419 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
5420 input, llvm_chan, ""));
5421 }
5422 }
5423 }
5424
5425 static void interp_fs_input(struct radv_shader_context *ctx,
5426 unsigned attr,
5427 LLVMValueRef interp_param,
5428 LLVMValueRef prim_mask,
5429 LLVMValueRef result[4])
5430 {
5431 LLVMValueRef attr_number;
5432 unsigned chan;
5433 LLVMValueRef i, j;
5434 bool interp = interp_param != NULL;
5435
5436 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5437
5438 /* fs.constant returns the param from the middle vertex, so it's not
5439 * really useful for flat shading. It's meant to be used for custom
5440 * interpolation (but the intrinsic can't fetch from the other two
5441 * vertices).
5442 *
5443 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5444 * to do the right thing. The only reason we use fs.constant is that
5445 * fs.interp cannot be used on integers, because they can be equal
5446 * to NaN.
5447 */
5448 if (interp) {
5449 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
5450 ctx->ac.v2f32, "");
5451
5452 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5453 ctx->ac.i32_0, "");
5454 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5455 ctx->ac.i32_1, "");
5456 }
5457
5458 for (chan = 0; chan < 4; chan++) {
5459 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5460
5461 if (interp) {
5462 result[chan] = ac_build_fs_interp(&ctx->ac,
5463 llvm_chan,
5464 attr_number,
5465 prim_mask, i, j);
5466 } else {
5467 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5468 LLVMConstInt(ctx->ac.i32, 2, false),
5469 llvm_chan,
5470 attr_number,
5471 prim_mask);
5472 }
5473 }
5474 }
5475
5476 static void
5477 handle_fs_input_decl(struct radv_shader_context *ctx,
5478 struct nir_variable *variable)
5479 {
5480 int idx = variable->data.location;
5481 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5482 LLVMValueRef interp;
5483
5484 variable->data.driver_location = idx * 4;
5485 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5486
5487 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5488 unsigned interp_type;
5489 if (variable->data.sample)
5490 interp_type = INTERP_SAMPLE;
5491 else if (variable->data.centroid)
5492 interp_type = INTERP_CENTROID;
5493 else
5494 interp_type = INTERP_CENTER;
5495
5496 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5497 } else
5498 interp = NULL;
5499
5500 for (unsigned i = 0; i < attrib_count; ++i)
5501 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5502
5503 }
5504
5505 static void
5506 handle_vs_inputs(struct radv_shader_context *ctx,
5507 struct nir_shader *nir) {
5508 nir_foreach_variable(variable, &nir->inputs)
5509 handle_vs_input_decl(ctx, variable);
5510 }
5511
5512 static void
5513 prepare_interp_optimize(struct radv_shader_context *ctx,
5514 struct nir_shader *nir)
5515 {
5516 if (!ctx->options->key.fs.multisample)
5517 return;
5518
5519 bool uses_center = false;
5520 bool uses_centroid = false;
5521 nir_foreach_variable(variable, &nir->inputs) {
5522 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5523 variable->data.sample)
5524 continue;
5525
5526 if (variable->data.centroid)
5527 uses_centroid = true;
5528 else
5529 uses_center = true;
5530 }
5531
5532 if (uses_center && uses_centroid) {
5533 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5534 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5535 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5536 }
5537 }
5538
5539 static void
5540 handle_fs_inputs(struct radv_shader_context *ctx,
5541 struct nir_shader *nir)
5542 {
5543 prepare_interp_optimize(ctx, nir);
5544
5545 nir_foreach_variable(variable, &nir->inputs)
5546 handle_fs_input_decl(ctx, variable);
5547
5548 unsigned index = 0;
5549
5550 if (ctx->shader_info->info.ps.uses_input_attachments ||
5551 ctx->shader_info->info.needs_multiview_view_index)
5552 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5553
5554 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5555 LLVMValueRef interp_param;
5556 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5557
5558 if (!(ctx->input_mask & (1ull << i)))
5559 continue;
5560
5561 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5562 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5563 interp_param = *inputs;
5564 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5565 inputs);
5566
5567 if (!interp_param)
5568 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5569 ++index;
5570 } else if (i == VARYING_SLOT_POS) {
5571 for(int i = 0; i < 3; ++i)
5572 inputs[i] = ctx->abi.frag_pos[i];
5573
5574 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5575 ctx->abi.frag_pos[3]);
5576 }
5577 }
5578 ctx->shader_info->fs.num_interp = index;
5579 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5580
5581 if (ctx->shader_info->info.needs_multiview_view_index)
5582 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5583 }
5584
5585 static LLVMValueRef
5586 ac_build_alloca(struct ac_llvm_context *ac,
5587 LLVMTypeRef type,
5588 const char *name)
5589 {
5590 LLVMBuilderRef builder = ac->builder;
5591 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5592 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5593 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5594 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5595 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5596 LLVMValueRef res;
5597
5598 if (first_instr) {
5599 LLVMPositionBuilderBefore(first_builder, first_instr);
5600 } else {
5601 LLVMPositionBuilderAtEnd(first_builder, first_block);
5602 }
5603
5604 res = LLVMBuildAlloca(first_builder, type, name);
5605 LLVMBuildStore(builder, LLVMConstNull(type), res);
5606
5607 LLVMDisposeBuilder(first_builder);
5608
5609 return res;
5610 }
5611
5612 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5613 LLVMTypeRef type,
5614 const char *name)
5615 {
5616 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5617 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5618 return ptr;
5619 }
5620
5621 static void
5622 scan_shader_output_decl(struct radv_shader_context *ctx,
5623 struct nir_variable *variable,
5624 struct nir_shader *shader,
5625 gl_shader_stage stage)
5626 {
5627 int idx = variable->data.location + variable->data.index;
5628 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5629 uint64_t mask_attribs;
5630
5631 variable->data.driver_location = idx * 4;
5632
5633 /* tess ctrl has it's own load/store paths for outputs */
5634 if (stage == MESA_SHADER_TESS_CTRL)
5635 return;
5636
5637 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5638 if (stage == MESA_SHADER_VERTEX ||
5639 stage == MESA_SHADER_TESS_EVAL ||
5640 stage == MESA_SHADER_GEOMETRY) {
5641 if (idx == VARYING_SLOT_CLIP_DIST0) {
5642 int length = shader->info.clip_distance_array_size +
5643 shader->info.cull_distance_array_size;
5644 if (stage == MESA_SHADER_VERTEX) {
5645 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5646 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5647 }
5648 if (stage == MESA_SHADER_TESS_EVAL) {
5649 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5650 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5651 }
5652
5653 if (length > 4)
5654 attrib_count = 2;
5655 else
5656 attrib_count = 1;
5657 mask_attribs = 1ull << idx;
5658 }
5659 }
5660
5661 ctx->output_mask |= mask_attribs;
5662 }
5663
5664 static void
5665 handle_shader_output_decl(struct ac_nir_context *ctx,
5666 struct nir_shader *nir,
5667 struct nir_variable *variable)
5668 {
5669 unsigned output_loc = variable->data.driver_location / 4;
5670 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5671
5672 /* tess ctrl has it's own load/store paths for outputs */
5673 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5674 return;
5675
5676 if (ctx->stage == MESA_SHADER_VERTEX ||
5677 ctx->stage == MESA_SHADER_TESS_EVAL ||
5678 ctx->stage == MESA_SHADER_GEOMETRY) {
5679 int idx = variable->data.location + variable->data.index;
5680 if (idx == VARYING_SLOT_CLIP_DIST0) {
5681 int length = nir->info.clip_distance_array_size +
5682 nir->info.cull_distance_array_size;
5683
5684 if (length > 4)
5685 attrib_count = 2;
5686 else
5687 attrib_count = 1;
5688 }
5689 }
5690
5691 for (unsigned i = 0; i < attrib_count; ++i) {
5692 for (unsigned chan = 0; chan < 4; chan++) {
5693 ctx->abi->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5694 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5695 }
5696 }
5697 }
5698
5699 static LLVMTypeRef
5700 glsl_base_to_llvm_type(struct ac_llvm_context *ac,
5701 enum glsl_base_type type)
5702 {
5703 switch (type) {
5704 case GLSL_TYPE_INT:
5705 case GLSL_TYPE_UINT:
5706 case GLSL_TYPE_BOOL:
5707 case GLSL_TYPE_SUBROUTINE:
5708 return ac->i32;
5709 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5710 return ac->f32;
5711 case GLSL_TYPE_INT64:
5712 case GLSL_TYPE_UINT64:
5713 return ac->i64;
5714 case GLSL_TYPE_DOUBLE:
5715 return ac->f64;
5716 default:
5717 unreachable("unknown GLSL type");
5718 }
5719 }
5720
5721 static LLVMTypeRef
5722 glsl_to_llvm_type(struct ac_llvm_context *ac,
5723 const struct glsl_type *type)
5724 {
5725 if (glsl_type_is_scalar(type)) {
5726 return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
5727 }
5728
5729 if (glsl_type_is_vector(type)) {
5730 return LLVMVectorType(
5731 glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
5732 glsl_get_vector_elements(type));
5733 }
5734
5735 if (glsl_type_is_matrix(type)) {
5736 return LLVMArrayType(
5737 glsl_to_llvm_type(ac, glsl_get_column_type(type)),
5738 glsl_get_matrix_columns(type));
5739 }
5740
5741 if (glsl_type_is_array(type)) {
5742 return LLVMArrayType(
5743 glsl_to_llvm_type(ac, glsl_get_array_element(type)),
5744 glsl_get_length(type));
5745 }
5746
5747 assert(glsl_type_is_struct(type));
5748
5749 LLVMTypeRef member_types[glsl_get_length(type)];
5750
5751 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5752 member_types[i] =
5753 glsl_to_llvm_type(ac,
5754 glsl_get_struct_field(type, i));
5755 }
5756
5757 return LLVMStructTypeInContext(ac->context, member_types,
5758 glsl_get_length(type), false);
5759 }
5760
5761 static void
5762 setup_locals(struct ac_nir_context *ctx,
5763 struct nir_function *func)
5764 {
5765 int i, j;
5766 ctx->num_locals = 0;
5767 nir_foreach_variable(variable, &func->impl->locals) {
5768 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5769 variable->data.driver_location = ctx->num_locals * 4;
5770 variable->data.location_frac = 0;
5771 ctx->num_locals += attrib_count;
5772 }
5773 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5774 if (!ctx->locals)
5775 return;
5776
5777 for (i = 0; i < ctx->num_locals; i++) {
5778 for (j = 0; j < 4; j++) {
5779 ctx->locals[i * 4 + j] =
5780 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5781 }
5782 }
5783 }
5784
5785 static void
5786 setup_shared(struct ac_nir_context *ctx,
5787 struct nir_shader *nir)
5788 {
5789 nir_foreach_variable(variable, &nir->shared) {
5790 LLVMValueRef shared =
5791 LLVMAddGlobalInAddressSpace(
5792 ctx->ac.module, glsl_to_llvm_type(&ctx->ac, variable->type),
5793 variable->name ? variable->name : "",
5794 AC_LOCAL_ADDR_SPACE);
5795 _mesa_hash_table_insert(ctx->vars, variable, shared);
5796 }
5797 }
5798
5799 /* Initialize arguments for the shader export intrinsic */
5800 static void
5801 si_llvm_init_export_args(struct radv_shader_context *ctx,
5802 LLVMValueRef *values,
5803 unsigned target,
5804 struct ac_export_args *args)
5805 {
5806 /* Default is 0xf. Adjusted below depending on the format. */
5807 args->enabled_channels = 0xf;
5808
5809 /* Specify whether the EXEC mask represents the valid mask */
5810 args->valid_mask = 0;
5811
5812 /* Specify whether this is the last export */
5813 args->done = 0;
5814
5815 /* Specify the target we are exporting */
5816 args->target = target;
5817
5818 args->compr = false;
5819 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5820 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5821 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5822 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5823
5824 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5825 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5826 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5827 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5828 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5829 unsigned chan;
5830
5831 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5832 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5833 unsigned bits, bool hi) = NULL;
5834
5835 switch(col_format) {
5836 case V_028714_SPI_SHADER_ZERO:
5837 args->enabled_channels = 0; /* writemask */
5838 args->target = V_008DFC_SQ_EXP_NULL;
5839 break;
5840
5841 case V_028714_SPI_SHADER_32_R:
5842 args->enabled_channels = 1;
5843 args->out[0] = values[0];
5844 break;
5845
5846 case V_028714_SPI_SHADER_32_GR:
5847 args->enabled_channels = 0x3;
5848 args->out[0] = values[0];
5849 args->out[1] = values[1];
5850 break;
5851
5852 case V_028714_SPI_SHADER_32_AR:
5853 args->enabled_channels = 0x9;
5854 args->out[0] = values[0];
5855 args->out[3] = values[3];
5856 break;
5857
5858 case V_028714_SPI_SHADER_FP16_ABGR:
5859 packf = ac_build_cvt_pkrtz_f16;
5860 break;
5861
5862 case V_028714_SPI_SHADER_UNORM16_ABGR:
5863 packf = ac_build_cvt_pknorm_u16;
5864 break;
5865
5866 case V_028714_SPI_SHADER_SNORM16_ABGR:
5867 packf = ac_build_cvt_pknorm_i16;
5868 break;
5869
5870 case V_028714_SPI_SHADER_UINT16_ABGR:
5871 packi = ac_build_cvt_pk_u16;
5872 break;
5873
5874 case V_028714_SPI_SHADER_SINT16_ABGR:
5875 packi = ac_build_cvt_pk_i16;
5876 break;
5877
5878 default:
5879 case V_028714_SPI_SHADER_32_ABGR:
5880 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5881 break;
5882 }
5883
5884 /* Pack f16 or norm_i16/u16. */
5885 if (packf) {
5886 for (chan = 0; chan < 2; chan++) {
5887 LLVMValueRef pack_args[2] = {
5888 values[2 * chan],
5889 values[2 * chan + 1]
5890 };
5891 LLVMValueRef packed;
5892
5893 packed = packf(&ctx->ac, pack_args);
5894 args->out[chan] = ac_to_float(&ctx->ac, packed);
5895 }
5896 args->compr = 1; /* COMPR flag */
5897 }
5898
5899 /* Pack i16/u16. */
5900 if (packi) {
5901 for (chan = 0; chan < 2; chan++) {
5902 LLVMValueRef pack_args[2] = {
5903 ac_to_integer(&ctx->ac, values[2 * chan]),
5904 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5905 };
5906 LLVMValueRef packed;
5907
5908 packed = packi(&ctx->ac, pack_args,
5909 is_int8 ? 8 : is_int10 ? 10 : 16,
5910 chan == 1);
5911 args->out[chan] = ac_to_float(&ctx->ac, packed);
5912 }
5913 args->compr = 1; /* COMPR flag */
5914 }
5915 return;
5916 }
5917
5918 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5919
5920 for (unsigned i = 0; i < 4; ++i)
5921 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5922 }
5923
5924 static void
5925 radv_export_param(struct radv_shader_context *ctx, unsigned index,
5926 LLVMValueRef *values)
5927 {
5928 struct ac_export_args args;
5929
5930 si_llvm_init_export_args(ctx, values,
5931 V_008DFC_SQ_EXP_PARAM + index, &args);
5932 ac_build_export(&ctx->ac, &args);
5933 }
5934
5935 static LLVMValueRef
5936 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
5937 {
5938 LLVMValueRef output =
5939 ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
5940
5941 return LLVMBuildLoad(ctx->ac.builder, output, "");
5942 }
5943
5944 static void
5945 handle_vs_outputs_post(struct radv_shader_context *ctx,
5946 bool export_prim_id,
5947 struct ac_vs_output_info *outinfo)
5948 {
5949 uint32_t param_count = 0;
5950 unsigned target;
5951 unsigned pos_idx, num_pos_exports = 0;
5952 struct ac_export_args args, pos_args[4] = {};
5953 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5954 int i;
5955
5956 if (ctx->options->key.has_multiview_view_index) {
5957 LLVMValueRef* tmp_out = &ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5958 if(!*tmp_out) {
5959 for(unsigned i = 0; i < 4; ++i)
5960 ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5961 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5962 }
5963
5964 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
5965 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5966 }
5967
5968 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5969 sizeof(outinfo->vs_output_param_offset));
5970
5971 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5972 LLVMValueRef slots[8];
5973 unsigned j;
5974
5975 if (outinfo->cull_dist_mask)
5976 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5977
5978 i = VARYING_SLOT_CLIP_DIST0;
5979 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5980 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
5981
5982 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5983 slots[i] = LLVMGetUndef(ctx->ac.f32);
5984
5985 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5986 target = V_008DFC_SQ_EXP_POS + 3;
5987 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5988 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5989 &args, sizeof(args));
5990 }
5991
5992 target = V_008DFC_SQ_EXP_POS + 2;
5993 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5994 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5995 &args, sizeof(args));
5996
5997 }
5998
5999 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
6000 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
6001 for (unsigned j = 0; j < 4; j++)
6002 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
6003 }
6004 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
6005
6006 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
6007 outinfo->writes_pointsize = true;
6008 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
6009 }
6010
6011 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
6012 outinfo->writes_layer = true;
6013 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
6014 }
6015
6016 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
6017 outinfo->writes_viewport_index = true;
6018 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
6019 }
6020
6021 if (outinfo->writes_pointsize ||
6022 outinfo->writes_layer ||
6023 outinfo->writes_viewport_index) {
6024 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
6025 (outinfo->writes_layer == true ? 4 : 0));
6026 pos_args[1].valid_mask = 0;
6027 pos_args[1].done = 0;
6028 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6029 pos_args[1].compr = 0;
6030 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6031 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6032 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6033 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6034
6035 if (outinfo->writes_pointsize == true)
6036 pos_args[1].out[0] = psize_value;
6037 if (outinfo->writes_layer == true)
6038 pos_args[1].out[2] = layer_value;
6039 if (outinfo->writes_viewport_index == true) {
6040 if (ctx->options->chip_class >= GFX9) {
6041 /* GFX9 has the layer in out.z[10:0] and the viewport
6042 * index in out.z[19:16].
6043 */
6044 LLVMValueRef v = viewport_index_value;
6045 v = ac_to_integer(&ctx->ac, v);
6046 v = LLVMBuildShl(ctx->ac.builder, v,
6047 LLVMConstInt(ctx->ac.i32, 16, false),
6048 "");
6049 v = LLVMBuildOr(ctx->ac.builder, v,
6050 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6051
6052 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6053 pos_args[1].enabled_channels |= 1 << 2;
6054 } else {
6055 pos_args[1].out[3] = viewport_index_value;
6056 pos_args[1].enabled_channels |= 1 << 3;
6057 }
6058 }
6059 }
6060 for (i = 0; i < 4; i++) {
6061 if (pos_args[i].out[0])
6062 num_pos_exports++;
6063 }
6064
6065 pos_idx = 0;
6066 for (i = 0; i < 4; i++) {
6067 if (!pos_args[i].out[0])
6068 continue;
6069
6070 /* Specify the target we are exporting */
6071 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6072 if (pos_idx == num_pos_exports)
6073 pos_args[i].done = 1;
6074 ac_build_export(&ctx->ac, &pos_args[i]);
6075 }
6076
6077 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6078 LLVMValueRef values[4];
6079 if (!(ctx->output_mask & (1ull << i)))
6080 continue;
6081
6082 if (i != VARYING_SLOT_LAYER &&
6083 i != VARYING_SLOT_PRIMITIVE_ID &&
6084 i < VARYING_SLOT_VAR0)
6085 continue;
6086
6087 for (unsigned j = 0; j < 4; j++)
6088 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6089
6090 radv_export_param(ctx, param_count, values);
6091
6092 outinfo->vs_output_param_offset[i] = param_count++;
6093 }
6094
6095 if (export_prim_id) {
6096 LLVMValueRef values[4];
6097
6098 values[0] = ctx->vs_prim_id;
6099 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6100 ctx->shader_info->vs.vgpr_comp_cnt);
6101 for (unsigned j = 1; j < 4; j++)
6102 values[j] = ctx->ac.f32_0;
6103
6104 radv_export_param(ctx, param_count, values);
6105
6106 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6107 outinfo->export_prim_id = true;
6108 }
6109
6110 outinfo->pos_exports = num_pos_exports;
6111 outinfo->param_exports = param_count;
6112 }
6113
6114 static void
6115 handle_es_outputs_post(struct radv_shader_context *ctx,
6116 struct ac_es_output_info *outinfo)
6117 {
6118 int j;
6119 uint64_t max_output_written = 0;
6120 LLVMValueRef lds_base = NULL;
6121
6122 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6123 int param_index;
6124 int length = 4;
6125
6126 if (!(ctx->output_mask & (1ull << i)))
6127 continue;
6128
6129 if (i == VARYING_SLOT_CLIP_DIST0)
6130 length = ctx->num_output_clips + ctx->num_output_culls;
6131
6132 param_index = shader_io_get_unique_index(i);
6133
6134 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6135 }
6136
6137 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6138
6139 if (ctx->ac.chip_class >= GFX9) {
6140 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6141 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6142 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6143 LLVMConstInt(ctx->ac.i32, 24, false),
6144 LLVMConstInt(ctx->ac.i32, 4, false), false);
6145 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6146 LLVMBuildMul(ctx->ac.builder, wave_idx,
6147 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6148 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6149 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6150 }
6151
6152 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6153 LLVMValueRef dw_addr = NULL;
6154 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6155 int param_index;
6156 int length = 4;
6157
6158 if (!(ctx->output_mask & (1ull << i)))
6159 continue;
6160
6161 if (i == VARYING_SLOT_CLIP_DIST0)
6162 length = ctx->num_output_clips + ctx->num_output_culls;
6163
6164 param_index = shader_io_get_unique_index(i);
6165
6166 if (lds_base) {
6167 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
6168 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6169 "");
6170 }
6171 for (j = 0; j < length; j++) {
6172 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
6173 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
6174
6175 if (ctx->ac.chip_class >= GFX9) {
6176 ac_lds_store(&ctx->ac, dw_addr,
6177 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6178 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6179 } else {
6180 ac_build_buffer_store_dword(&ctx->ac,
6181 ctx->esgs_ring,
6182 out_val, 1,
6183 NULL, ctx->es2gs_offset,
6184 (4 * param_index + j) * 4,
6185 1, 1, true, true);
6186 }
6187 }
6188 }
6189 }
6190
6191 static void
6192 handle_ls_outputs_post(struct radv_shader_context *ctx)
6193 {
6194 LLVMValueRef vertex_id = ctx->rel_auto_id;
6195 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6196 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
6197 vertex_dw_stride, "");
6198
6199 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6200 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6201 int length = 4;
6202
6203 if (!(ctx->output_mask & (1ull << i)))
6204 continue;
6205
6206 if (i == VARYING_SLOT_CLIP_DIST0)
6207 length = ctx->num_output_clips + ctx->num_output_culls;
6208 int param = shader_io_get_unique_index(i);
6209 mark_tess_output(ctx, false, param);
6210 if (length > 4)
6211 mark_tess_output(ctx, false, param + 1);
6212 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
6213 LLVMConstInt(ctx->ac.i32, param * 4, false),
6214 "");
6215 for (unsigned j = 0; j < length; j++) {
6216 ac_lds_store(&ctx->ac, dw_addr,
6217 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6218 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6219 }
6220 }
6221 }
6222
6223 struct ac_build_if_state
6224 {
6225 struct radv_shader_context *ctx;
6226 LLVMValueRef condition;
6227 LLVMBasicBlockRef entry_block;
6228 LLVMBasicBlockRef true_block;
6229 LLVMBasicBlockRef false_block;
6230 LLVMBasicBlockRef merge_block;
6231 };
6232
6233 static LLVMBasicBlockRef
6234 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
6235 {
6236 LLVMBasicBlockRef current_block;
6237 LLVMBasicBlockRef next_block;
6238 LLVMBasicBlockRef new_block;
6239
6240 /* get current basic block */
6241 current_block = LLVMGetInsertBlock(ctx->ac.builder);
6242
6243 /* chqeck if there's another block after this one */
6244 next_block = LLVMGetNextBasicBlock(current_block);
6245 if (next_block) {
6246 /* insert the new block before the next block */
6247 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6248 }
6249 else {
6250 /* append new block after current block */
6251 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6252 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6253 }
6254 return new_block;
6255 }
6256
6257 static void
6258 ac_nir_build_if(struct ac_build_if_state *ifthen,
6259 struct radv_shader_context *ctx,
6260 LLVMValueRef condition)
6261 {
6262 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
6263
6264 memset(ifthen, 0, sizeof *ifthen);
6265 ifthen->ctx = ctx;
6266 ifthen->condition = condition;
6267 ifthen->entry_block = block;
6268
6269 /* create endif/merge basic block for the phi functions */
6270 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6271
6272 /* create/insert true_block before merge_block */
6273 ifthen->true_block =
6274 LLVMInsertBasicBlockInContext(ctx->context,
6275 ifthen->merge_block,
6276 "if-true-block");
6277
6278 /* successive code goes into the true block */
6279 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
6280 }
6281
6282 /**
6283 * End a conditional.
6284 */
6285 static void
6286 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6287 {
6288 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
6289
6290 /* Insert branch to the merge block from current block */
6291 LLVMBuildBr(builder, ifthen->merge_block);
6292
6293 /*
6294 * Now patch in the various branch instructions.
6295 */
6296
6297 /* Insert the conditional branch instruction at the end of entry_block */
6298 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6299 if (ifthen->false_block) {
6300 /* we have an else clause */
6301 LLVMBuildCondBr(builder, ifthen->condition,
6302 ifthen->true_block, ifthen->false_block);
6303 }
6304 else {
6305 /* no else clause */
6306 LLVMBuildCondBr(builder, ifthen->condition,
6307 ifthen->true_block, ifthen->merge_block);
6308 }
6309
6310 /* Resume building code at end of the ifthen->merge_block */
6311 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6312 }
6313
6314 static void
6315 write_tess_factors(struct radv_shader_context *ctx)
6316 {
6317 unsigned stride, outer_comps, inner_comps;
6318 struct ac_build_if_state if_ctx, inner_if_ctx;
6319 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6320 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6321 unsigned tess_inner_index = 0, tess_outer_index;
6322 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
6323 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6324 int i;
6325 emit_barrier(&ctx->ac, ctx->stage);
6326
6327 switch (ctx->options->key.tcs.primitive_mode) {
6328 case GL_ISOLINES:
6329 stride = 2;
6330 outer_comps = 2;
6331 inner_comps = 0;
6332 break;
6333 case GL_TRIANGLES:
6334 stride = 4;
6335 outer_comps = 3;
6336 inner_comps = 1;
6337 break;
6338 case GL_QUADS:
6339 stride = 6;
6340 outer_comps = 4;
6341 inner_comps = 2;
6342 break;
6343 default:
6344 return;
6345 }
6346
6347 ac_nir_build_if(&if_ctx, ctx,
6348 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6349 invocation_id, ctx->ac.i32_0, ""));
6350
6351 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6352
6353 if (inner_comps) {
6354 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6355 mark_tess_output(ctx, true, tess_inner_index);
6356 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
6357 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6358 }
6359
6360 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6361 mark_tess_output(ctx, true, tess_outer_index);
6362 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
6363 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6364
6365 for (i = 0; i < 4; i++) {
6366 inner[i] = LLVMGetUndef(ctx->ac.i32);
6367 outer[i] = LLVMGetUndef(ctx->ac.i32);
6368 }
6369
6370 // LINES reverseal
6371 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6372 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6373 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6374 ctx->ac.i32_1, "");
6375 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6376 } else {
6377 for (i = 0; i < outer_comps; i++) {
6378 outer[i] = out[i] =
6379 ac_lds_load(&ctx->ac, lds_outer);
6380 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6381 ctx->ac.i32_1, "");
6382 }
6383 for (i = 0; i < inner_comps; i++) {
6384 inner[i] = out[outer_comps+i] =
6385 ac_lds_load(&ctx->ac, lds_inner);
6386 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
6387 ctx->ac.i32_1, "");
6388 }
6389 }
6390
6391 /* Convert the outputs to vectors for stores. */
6392 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6393 vec1 = NULL;
6394
6395 if (stride > 4)
6396 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6397
6398
6399 buffer = ctx->hs_ring_tess_factor;
6400 tf_base = ctx->tess_factor_offset;
6401 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
6402 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6403 unsigned tf_offset = 0;
6404
6405 if (ctx->options->chip_class <= VI) {
6406 ac_nir_build_if(&inner_if_ctx, ctx,
6407 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6408 rel_patch_id, ctx->ac.i32_0, ""));
6409
6410 /* Store the dynamic HS control word. */
6411 ac_build_buffer_store_dword(&ctx->ac, buffer,
6412 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6413 1, ctx->ac.i32_0, tf_base,
6414 0, 1, 0, true, false);
6415 tf_offset += 4;
6416
6417 ac_nir_build_endif(&inner_if_ctx);
6418 }
6419
6420 /* Store the tessellation factors. */
6421 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6422 MIN2(stride, 4), byteoffset, tf_base,
6423 tf_offset, 1, 0, true, false);
6424 if (vec1)
6425 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6426 stride - 4, byteoffset, tf_base,
6427 16 + tf_offset, 1, 0, true, false);
6428
6429 //store to offchip for TES to read - only if TES reads them
6430 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6431 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6432 LLVMValueRef tf_inner_offset;
6433 unsigned param_outer, param_inner;
6434
6435 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6436 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6437 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6438
6439 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6440 util_next_power_of_two(outer_comps));
6441
6442 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6443 outer_comps, tf_outer_offset,
6444 ctx->oc_lds, 0, 1, 0, true, false);
6445 if (inner_comps) {
6446 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6447 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6448 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6449
6450 inner_vec = inner_comps == 1 ? inner[0] :
6451 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6452 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6453 inner_comps, tf_inner_offset,
6454 ctx->oc_lds, 0, 1, 0, true, false);
6455 }
6456 }
6457 ac_nir_build_endif(&if_ctx);
6458 }
6459
6460 static void
6461 handle_tcs_outputs_post(struct radv_shader_context *ctx)
6462 {
6463 write_tess_factors(ctx);
6464 }
6465
6466 static bool
6467 si_export_mrt_color(struct radv_shader_context *ctx,
6468 LLVMValueRef *color, unsigned index, bool is_last,
6469 struct ac_export_args *args)
6470 {
6471 /* Export */
6472 si_llvm_init_export_args(ctx, color,
6473 V_008DFC_SQ_EXP_MRT + index, args);
6474
6475 if (is_last) {
6476 args->valid_mask = 1; /* whether the EXEC mask is valid */
6477 args->done = 1; /* DONE bit */
6478 } else if (!args->enabled_channels)
6479 return false; /* unnecessary NULL export */
6480
6481 return true;
6482 }
6483
6484 static void
6485 radv_export_mrt_z(struct radv_shader_context *ctx,
6486 LLVMValueRef depth, LLVMValueRef stencil,
6487 LLVMValueRef samplemask)
6488 {
6489 struct ac_export_args args;
6490
6491 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6492
6493 ac_build_export(&ctx->ac, &args);
6494 }
6495
6496 static void
6497 handle_fs_outputs_post(struct radv_shader_context *ctx)
6498 {
6499 unsigned index = 0;
6500 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6501 struct ac_export_args color_args[8];
6502
6503 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6504 LLVMValueRef values[4];
6505 bool last = false;
6506
6507 if (!(ctx->output_mask & (1ull << i)))
6508 continue;
6509
6510 if (i < FRAG_RESULT_DATA0)
6511 continue;
6512
6513 for (unsigned j = 0; j < 4; j++)
6514 values[j] = ac_to_float(&ctx->ac,
6515 radv_load_output(ctx, i, j));
6516
6517 if (!ctx->shader_info->info.ps.writes_z &&
6518 !ctx->shader_info->info.ps.writes_stencil &&
6519 !ctx->shader_info->info.ps.writes_sample_mask)
6520 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6521
6522 bool ret = si_export_mrt_color(ctx, values,
6523 i - FRAG_RESULT_DATA0,
6524 last, &color_args[index]);
6525 if (ret)
6526 index++;
6527 }
6528
6529 /* Process depth, stencil, samplemask. */
6530 if (ctx->shader_info->info.ps.writes_z) {
6531 depth = ac_to_float(&ctx->ac,
6532 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6533 }
6534 if (ctx->shader_info->info.ps.writes_stencil) {
6535 stencil = ac_to_float(&ctx->ac,
6536 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6537 }
6538 if (ctx->shader_info->info.ps.writes_sample_mask) {
6539 samplemask = ac_to_float(&ctx->ac,
6540 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6541 }
6542
6543 /* Export PS outputs. */
6544 for (unsigned i = 0; i < index; i++)
6545 ac_build_export(&ctx->ac, &color_args[i]);
6546
6547 if (depth || stencil || samplemask)
6548 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6549 else if (!index)
6550 ac_build_export_null(&ctx->ac);
6551 }
6552
6553 static void
6554 emit_gs_epilogue(struct radv_shader_context *ctx)
6555 {
6556 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6557 }
6558
6559 static void
6560 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6561 LLVMValueRef *addrs)
6562 {
6563 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
6564
6565 switch (ctx->stage) {
6566 case MESA_SHADER_VERTEX:
6567 if (ctx->options->key.vs.as_ls)
6568 handle_ls_outputs_post(ctx);
6569 else if (ctx->options->key.vs.as_es)
6570 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6571 else
6572 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6573 &ctx->shader_info->vs.outinfo);
6574 break;
6575 case MESA_SHADER_FRAGMENT:
6576 handle_fs_outputs_post(ctx);
6577 break;
6578 case MESA_SHADER_GEOMETRY:
6579 emit_gs_epilogue(ctx);
6580 break;
6581 case MESA_SHADER_TESS_CTRL:
6582 handle_tcs_outputs_post(ctx);
6583 break;
6584 case MESA_SHADER_TESS_EVAL:
6585 if (ctx->options->key.tes.as_es)
6586 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6587 else
6588 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6589 &ctx->shader_info->tes.outinfo);
6590 break;
6591 default:
6592 break;
6593 }
6594 }
6595
6596 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
6597 {
6598 LLVMPassManagerRef passmgr;
6599 /* Create the pass manager */
6600 passmgr = LLVMCreateFunctionPassManagerForModule(
6601 ctx->ac.module);
6602
6603 /* This pass should eliminate all the load and store instructions */
6604 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6605
6606 /* Add some optimization passes */
6607 LLVMAddScalarReplAggregatesPass(passmgr);
6608 LLVMAddLICMPass(passmgr);
6609 LLVMAddAggressiveDCEPass(passmgr);
6610 LLVMAddCFGSimplificationPass(passmgr);
6611 LLVMAddInstructionCombiningPass(passmgr);
6612
6613 /* Run the pass */
6614 LLVMInitializeFunctionPassManager(passmgr);
6615 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6616 LLVMFinalizeFunctionPassManager(passmgr);
6617
6618 LLVMDisposeBuilder(ctx->ac.builder);
6619 LLVMDisposePassManager(passmgr);
6620 }
6621
6622 static void
6623 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
6624 {
6625 struct ac_vs_output_info *outinfo;
6626
6627 switch (ctx->stage) {
6628 case MESA_SHADER_FRAGMENT:
6629 case MESA_SHADER_COMPUTE:
6630 case MESA_SHADER_TESS_CTRL:
6631 case MESA_SHADER_GEOMETRY:
6632 return;
6633 case MESA_SHADER_VERTEX:
6634 if (ctx->options->key.vs.as_ls ||
6635 ctx->options->key.vs.as_es)
6636 return;
6637 outinfo = &ctx->shader_info->vs.outinfo;
6638 break;
6639 case MESA_SHADER_TESS_EVAL:
6640 if (ctx->options->key.vs.as_es)
6641 return;
6642 outinfo = &ctx->shader_info->tes.outinfo;
6643 break;
6644 default:
6645 unreachable("Unhandled shader type");
6646 }
6647
6648 ac_optimize_vs_outputs(&ctx->ac,
6649 ctx->main_function,
6650 outinfo->vs_output_param_offset,
6651 VARYING_SLOT_MAX,
6652 &outinfo->param_exports);
6653 }
6654
6655 static void
6656 ac_setup_rings(struct radv_shader_context *ctx)
6657 {
6658 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6659 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6660 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6661 }
6662
6663 if (ctx->is_gs_copy_shader) {
6664 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6665 }
6666 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6667 LLVMValueRef tmp;
6668 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6669 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6670
6671 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6672
6673 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6674 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6675 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
6676 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6677 }
6678
6679 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6680 ctx->stage == MESA_SHADER_TESS_EVAL) {
6681 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6682 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6683 }
6684 }
6685
6686 static unsigned
6687 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6688 const struct nir_shader *nir)
6689 {
6690 switch (nir->info.stage) {
6691 case MESA_SHADER_TESS_CTRL:
6692 return chip_class >= CIK ? 128 : 64;
6693 case MESA_SHADER_GEOMETRY:
6694 return chip_class >= GFX9 ? 128 : 64;
6695 case MESA_SHADER_COMPUTE:
6696 break;
6697 default:
6698 return 0;
6699 }
6700
6701 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6702 nir->info.cs.local_size[1] *
6703 nir->info.cs.local_size[2];
6704 return max_workgroup_size;
6705 }
6706
6707 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6708 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
6709 {
6710 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6711 LLVMConstInt(ctx->ac.i32, 8, false),
6712 LLVMConstInt(ctx->ac.i32, 8, false), false);
6713 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6714 ctx->ac.i32_0, "");
6715 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6716 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6717 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6718 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6719 }
6720
6721 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
6722 {
6723 for(int i = 5; i >= 0; --i) {
6724 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6725 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6726 LLVMConstInt(ctx->ac.i32, 16, false), false);
6727 }
6728
6729 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6730 LLVMConstInt(ctx->ac.i32, 16, false),
6731 LLVMConstInt(ctx->ac.i32, 8, false), false);
6732 }
6733
6734 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6735 struct nir_shader *nir)
6736 {
6737 struct ac_nir_context ctx = {};
6738 struct nir_function *func;
6739
6740 ctx.ac = *ac;
6741 ctx.abi = abi;
6742
6743 ctx.stage = nir->info.stage;
6744
6745 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6746
6747 nir_foreach_variable(variable, &nir->outputs)
6748 handle_shader_output_decl(&ctx, nir, variable);
6749
6750 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6751 _mesa_key_pointer_equal);
6752 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6753 _mesa_key_pointer_equal);
6754 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6755 _mesa_key_pointer_equal);
6756
6757 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6758
6759 setup_locals(&ctx, func);
6760
6761 if (nir->info.stage == MESA_SHADER_COMPUTE)
6762 setup_shared(&ctx, nir);
6763
6764 visit_cf_list(&ctx, &func->impl->body);
6765 phi_post_pass(&ctx);
6766
6767 if (nir->info.stage != MESA_SHADER_COMPUTE)
6768 ctx.abi->emit_outputs(ctx.abi, AC_LLVM_MAX_OUTPUTS,
6769 ctx.abi->outputs);
6770
6771 free(ctx.locals);
6772 ralloc_free(ctx.defs);
6773 ralloc_free(ctx.phis);
6774 ralloc_free(ctx.vars);
6775 }
6776
6777 static
6778 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6779 struct nir_shader *const *shaders,
6780 int shader_count,
6781 struct ac_shader_variant_info *shader_info,
6782 const struct ac_nir_compiler_options *options)
6783 {
6784 struct radv_shader_context ctx = {0};
6785 unsigned i;
6786 ctx.options = options;
6787 ctx.shader_info = shader_info;
6788 ctx.context = LLVMContextCreate();
6789
6790 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6791 options->family);
6792 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6793 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6794
6795 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6796 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6797 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
6798 LLVMDisposeTargetData(data_layout);
6799 LLVMDisposeMessage(data_layout_str);
6800
6801 enum ac_float_mode float_mode =
6802 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6803 AC_FLOAT_MODE_DEFAULT;
6804
6805 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
6806
6807 memset(shader_info, 0, sizeof(*shader_info));
6808
6809 for(int i = 0; i < shader_count; ++i)
6810 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6811
6812 for (i = 0; i < AC_UD_MAX_SETS; i++)
6813 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6814 for (i = 0; i < AC_UD_MAX_UD; i++)
6815 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6816
6817 ctx.max_workgroup_size = 0;
6818 for (int i = 0; i < shader_count; ++i) {
6819 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6820 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6821 shaders[i]));
6822 }
6823
6824 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6825 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6826
6827 ctx.abi.inputs = &ctx.inputs[0];
6828 ctx.abi.emit_outputs = handle_shader_outputs_post;
6829 ctx.abi.emit_vertex = visit_emit_vertex;
6830 ctx.abi.load_ubo = radv_load_ubo;
6831 ctx.abi.load_ssbo = radv_load_ssbo;
6832 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6833 ctx.abi.load_resource = radv_load_resource;
6834 ctx.abi.clamp_shadow_reference = false;
6835
6836 if (shader_count >= 2)
6837 ac_init_exec_full_mask(&ctx.ac);
6838
6839 if (ctx.ac.chip_class == GFX9 &&
6840 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6841 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6842
6843 for(int i = 0; i < shader_count; ++i) {
6844 ctx.stage = shaders[i]->info.stage;
6845 ctx.output_mask = 0;
6846 ctx.tess_outputs_written = 0;
6847 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6848 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6849
6850 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6851 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6852 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6853 ctx.abi.load_inputs = load_gs_input;
6854 ctx.abi.emit_primitive = visit_end_primitive;
6855 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6856 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6857 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6858 ctx.abi.load_tess_varyings = load_tcs_varyings;
6859 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6860 ctx.abi.store_tcs_outputs = store_tcs_output;
6861 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6862 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6863 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6864 ctx.abi.load_tess_varyings = load_tes_input;
6865 ctx.abi.load_tess_coord = load_tess_coord;
6866 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6867 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6868 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6869 if (shader_info->info.vs.needs_instance_id) {
6870 if (ctx.options->key.vs.as_ls) {
6871 ctx.shader_info->vs.vgpr_comp_cnt =
6872 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6873 } else {
6874 ctx.shader_info->vs.vgpr_comp_cnt =
6875 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6876 }
6877 }
6878 ctx.abi.load_base_vertex = radv_load_base_vertex;
6879 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6880 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6881 ctx.abi.lookup_interp_param = lookup_interp_param;
6882 ctx.abi.load_sample_position = load_sample_position;
6883 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6884 }
6885
6886 if (i)
6887 emit_barrier(&ctx.ac, ctx.stage);
6888
6889 ac_setup_rings(&ctx);
6890
6891 LLVMBasicBlockRef merge_block;
6892 if (shader_count >= 2) {
6893 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6894 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6895 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6896
6897 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6898 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6899 LLVMConstInt(ctx.ac.i32, 8, false), false);
6900 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6901 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6902 thread_id, count, "");
6903 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6904
6905 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6906 }
6907
6908 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6909 handle_fs_inputs(&ctx, shaders[i]);
6910 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6911 handle_vs_inputs(&ctx, shaders[i]);
6912 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6913 prepare_gs_input_vgprs(&ctx);
6914
6915 nir_foreach_variable(variable, &shaders[i]->outputs)
6916 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6917
6918 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
6919
6920 if (shader_count >= 2) {
6921 LLVMBuildBr(ctx.ac.builder, merge_block);
6922 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6923 }
6924
6925 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6926 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6927 shaders[i]->info.cull_distance_array_size > 4;
6928 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6929 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6930 shaders[i]->info.gs.vertices_out;
6931 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6932 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6933 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6934 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6935 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6936 }
6937 }
6938
6939 LLVMBuildRetVoid(ctx.ac.builder);
6940
6941 if (options->dump_preoptir)
6942 ac_dump_module(ctx.ac.module);
6943
6944 ac_llvm_finalize_module(&ctx);
6945
6946 if (shader_count == 1)
6947 ac_nir_eliminate_const_vs_outputs(&ctx);
6948
6949 return ctx.ac.module;
6950 }
6951
6952 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6953 {
6954 unsigned *retval = (unsigned *)context;
6955 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6956 char *description = LLVMGetDiagInfoDescription(di);
6957
6958 if (severity == LLVMDSError) {
6959 *retval = 1;
6960 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6961 description);
6962 }
6963
6964 LLVMDisposeMessage(description);
6965 }
6966
6967 static unsigned ac_llvm_compile(LLVMModuleRef M,
6968 struct ac_shader_binary *binary,
6969 LLVMTargetMachineRef tm)
6970 {
6971 unsigned retval = 0;
6972 char *err;
6973 LLVMContextRef llvm_ctx;
6974 LLVMMemoryBufferRef out_buffer;
6975 unsigned buffer_size;
6976 const char *buffer_data;
6977 LLVMBool mem_err;
6978
6979 /* Setup Diagnostic Handler*/
6980 llvm_ctx = LLVMGetModuleContext(M);
6981
6982 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6983 &retval);
6984
6985 /* Compile IR*/
6986 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6987 &err, &out_buffer);
6988
6989 /* Process Errors/Warnings */
6990 if (mem_err) {
6991 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6992 free(err);
6993 retval = 1;
6994 goto out;
6995 }
6996
6997 /* Extract Shader Code*/
6998 buffer_size = LLVMGetBufferSize(out_buffer);
6999 buffer_data = LLVMGetBufferStart(out_buffer);
7000
7001 ac_elf_read(buffer_data, buffer_size, binary);
7002
7003 /* Clean up */
7004 LLVMDisposeMemoryBuffer(out_buffer);
7005
7006 out:
7007 return retval;
7008 }
7009
7010 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
7011 LLVMModuleRef llvm_module,
7012 struct ac_shader_binary *binary,
7013 struct ac_shader_config *config,
7014 struct ac_shader_variant_info *shader_info,
7015 gl_shader_stage stage,
7016 bool dump_shader, bool supports_spill)
7017 {
7018 if (dump_shader)
7019 ac_dump_module(llvm_module);
7020
7021 memset(binary, 0, sizeof(*binary));
7022 int v = ac_llvm_compile(llvm_module, binary, tm);
7023 if (v) {
7024 fprintf(stderr, "compile failed\n");
7025 }
7026
7027 if (dump_shader)
7028 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7029
7030 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7031
7032 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7033 LLVMDisposeModule(llvm_module);
7034 LLVMContextDispose(ctx);
7035
7036 if (stage == MESA_SHADER_FRAGMENT) {
7037 shader_info->num_input_vgprs = 0;
7038 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7039 shader_info->num_input_vgprs += 2;
7040 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7041 shader_info->num_input_vgprs += 2;
7042 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7043 shader_info->num_input_vgprs += 2;
7044 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7045 shader_info->num_input_vgprs += 3;
7046 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7047 shader_info->num_input_vgprs += 2;
7048 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7049 shader_info->num_input_vgprs += 2;
7050 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7051 shader_info->num_input_vgprs += 2;
7052 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7053 shader_info->num_input_vgprs += 1;
7054 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7055 shader_info->num_input_vgprs += 1;
7056 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7057 shader_info->num_input_vgprs += 1;
7058 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7059 shader_info->num_input_vgprs += 1;
7060 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7061 shader_info->num_input_vgprs += 1;
7062 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7063 shader_info->num_input_vgprs += 1;
7064 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7065 shader_info->num_input_vgprs += 1;
7066 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7067 shader_info->num_input_vgprs += 1;
7068 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7069 shader_info->num_input_vgprs += 1;
7070 }
7071 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7072
7073 /* +3 for scratch wave offset and VCC */
7074 config->num_sgprs = MAX2(config->num_sgprs,
7075 shader_info->num_input_sgprs + 3);
7076
7077 /* Enable 64-bit and 16-bit denormals, because there is no performance
7078 * cost.
7079 *
7080 * If denormals are enabled, all floating-point output modifiers are
7081 * ignored.
7082 *
7083 * Don't enable denormals for 32-bit floats, because:
7084 * - Floating-point output modifiers would be ignored by the hw.
7085 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7086 * have to stop using those.
7087 * - SI & CI would be very slow.
7088 */
7089 config->float_mode |= V_00B028_FP_64_DENORMS;
7090 }
7091
7092 static void
7093 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7094 {
7095 switch (nir->info.stage) {
7096 case MESA_SHADER_COMPUTE:
7097 for (int i = 0; i < 3; ++i)
7098 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7099 break;
7100 case MESA_SHADER_FRAGMENT:
7101 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7102 break;
7103 case MESA_SHADER_GEOMETRY:
7104 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7105 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7106 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7107 shader_info->gs.invocations = nir->info.gs.invocations;
7108 break;
7109 case MESA_SHADER_TESS_EVAL:
7110 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7111 shader_info->tes.spacing = nir->info.tess.spacing;
7112 shader_info->tes.ccw = nir->info.tess.ccw;
7113 shader_info->tes.point_mode = nir->info.tess.point_mode;
7114 shader_info->tes.as_es = options->key.tes.as_es;
7115 break;
7116 case MESA_SHADER_TESS_CTRL:
7117 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7118 break;
7119 case MESA_SHADER_VERTEX:
7120 shader_info->vs.as_es = options->key.vs.as_es;
7121 shader_info->vs.as_ls = options->key.vs.as_ls;
7122 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7123 if (options->key.vs.as_ls)
7124 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7125 break;
7126 default:
7127 break;
7128 }
7129 }
7130
7131 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7132 struct ac_shader_binary *binary,
7133 struct ac_shader_config *config,
7134 struct ac_shader_variant_info *shader_info,
7135 struct nir_shader *const *nir,
7136 int nir_count,
7137 const struct ac_nir_compiler_options *options,
7138 bool dump_shader)
7139 {
7140
7141 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7142 options);
7143
7144 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7145 for (int i = 0; i < nir_count; ++i)
7146 ac_fill_shader_info(shader_info, nir[i], options);
7147
7148 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7149 if (options->chip_class == GFX9) {
7150 if (nir_count == 2 &&
7151 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7152 shader_info->gs.es_type = nir[0]->info.stage;
7153 }
7154 }
7155 }
7156
7157 static void
7158 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
7159 {
7160 LLVMValueRef vtx_offset =
7161 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
7162 LLVMConstInt(ctx->ac.i32, 4, false), "");
7163 int idx = 0;
7164
7165 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
7166 int length = 4;
7167 int slot = idx;
7168 int slot_inc = 1;
7169 if (!(ctx->output_mask & (1ull << i)))
7170 continue;
7171
7172 if (i == VARYING_SLOT_CLIP_DIST0) {
7173 /* unpack clip and cull from a single set of slots */
7174 length = ctx->num_output_clips + ctx->num_output_culls;
7175 if (length > 4)
7176 slot_inc = 2;
7177 }
7178
7179 for (unsigned j = 0; j < length; j++) {
7180 LLVMValueRef value, soffset;
7181
7182 soffset = LLVMConstInt(ctx->ac.i32,
7183 (slot * 4 + j) *
7184 ctx->gs_max_out_vertices * 16 * 4, false);
7185
7186 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7187 1, ctx->ac.i32_0,
7188 vtx_offset, soffset,
7189 0, 1, 1, true, false);
7190
7191 LLVMBuildStore(ctx->ac.builder,
7192 ac_to_float(&ctx->ac, value), ctx->abi.outputs[radeon_llvm_reg_index_soa(i, j)]);
7193 }
7194 idx += slot_inc;
7195 }
7196 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7197 }
7198
7199 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7200 struct nir_shader *geom_shader,
7201 struct ac_shader_binary *binary,
7202 struct ac_shader_config *config,
7203 struct ac_shader_variant_info *shader_info,
7204 const struct ac_nir_compiler_options *options,
7205 bool dump_shader)
7206 {
7207 struct radv_shader_context ctx = {0};
7208 ctx.context = LLVMContextCreate();
7209 ctx.options = options;
7210 ctx.shader_info = shader_info;
7211
7212 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7213 options->family);
7214 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7215
7216 ctx.is_gs_copy_shader = true;
7217 LLVMSetTarget(ctx.ac.module, "amdgcn--");
7218
7219 enum ac_float_mode float_mode =
7220 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7221 AC_FLOAT_MODE_DEFAULT;
7222
7223 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
7224 ctx.stage = MESA_SHADER_VERTEX;
7225
7226 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7227
7228 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7229 ac_setup_rings(&ctx);
7230
7231 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7232 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7233
7234 struct ac_nir_context nir_ctx = {};
7235 nir_ctx.ac = ctx.ac;
7236 nir_ctx.abi = &ctx.abi;
7237
7238 nir_foreach_variable(variable, &geom_shader->outputs) {
7239 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7240 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7241 }
7242
7243 ac_gs_copy_shader_emit(&ctx);
7244
7245 LLVMBuildRetVoid(ctx.ac.builder);
7246
7247 ac_llvm_finalize_module(&ctx);
7248
7249 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
7250 MESA_SHADER_VERTEX,
7251 dump_shader, options->supports_spill);
7252 }
7253
7254 void
7255 ac_lower_indirect_derefs(struct nir_shader *nir, enum chip_class chip_class)
7256 {
7257 /* While it would be nice not to have this flag, we are constrained
7258 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
7259 * on GFX9.
7260 */
7261 bool llvm_has_working_vgpr_indexing = chip_class <= VI;
7262
7263 /* TODO: Indirect indexing of GS inputs is unimplemented.
7264 *
7265 * TCS and TES load inputs directly from LDS or offchip memory, so
7266 * indirect indexing is trivial.
7267 */
7268 nir_variable_mode indirect_mask = 0;
7269 if (nir->info.stage == MESA_SHADER_GEOMETRY ||
7270 (nir->info.stage != MESA_SHADER_TESS_CTRL &&
7271 nir->info.stage != MESA_SHADER_TESS_EVAL &&
7272 !llvm_has_working_vgpr_indexing)) {
7273 indirect_mask |= nir_var_shader_in;
7274 }
7275 if (!llvm_has_working_vgpr_indexing &&
7276 nir->info.stage != MESA_SHADER_TESS_CTRL)
7277 indirect_mask |= nir_var_shader_out;
7278
7279 /* TODO: We shouldn't need to do this, however LLVM isn't currently
7280 * smart enough to handle indirects without causing excess spilling
7281 * causing the gpu to hang.
7282 *
7283 * See the following thread for more details of the problem:
7284 * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
7285 */
7286 indirect_mask |= nir_var_local;
7287
7288 nir_lower_indirect_derefs(nir, indirect_mask);
7289 }