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[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 };
43
44 #define CONST_ADDR_SPACE 2
45 #define LOCAL_ADDR_SPACE 3
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct nir_to_llvm_context;
51
52 struct ac_nir_context {
53 struct ac_llvm_context ac;
54 struct ac_shader_abi *abi;
55
56 gl_shader_stage stage;
57
58 struct hash_table *defs;
59 struct hash_table *phis;
60 struct hash_table *vars;
61
62 LLVMValueRef main_function;
63 LLVMBasicBlockRef continue_block;
64 LLVMBasicBlockRef break_block;
65
66 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
67
68 int num_locals;
69 LLVMValueRef *locals;
70
71 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
72 };
73
74 struct nir_to_llvm_context {
75 struct ac_llvm_context ac;
76 const struct ac_nir_compiler_options *options;
77 struct ac_shader_variant_info *shader_info;
78 struct ac_shader_abi abi;
79 struct ac_nir_context *nir;
80
81 unsigned max_workgroup_size;
82 LLVMContextRef context;
83 LLVMModuleRef module;
84 LLVMBuilderRef builder;
85 LLVMValueRef main_function;
86
87 struct hash_table *defs;
88 struct hash_table *phis;
89
90 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
91 LLVMValueRef ring_offsets;
92 LLVMValueRef push_constants;
93 LLVMValueRef view_index;
94 LLVMValueRef num_work_groups;
95 LLVMValueRef workgroup_ids;
96 LLVMValueRef local_invocation_ids;
97 LLVMValueRef tg_size;
98
99 LLVMValueRef vertex_buffers;
100 LLVMValueRef rel_auto_id;
101 LLVMValueRef vs_prim_id;
102 LLVMValueRef ls_out_layout;
103 LLVMValueRef es2gs_offset;
104
105 LLVMValueRef tcs_offchip_layout;
106 LLVMValueRef tcs_out_offsets;
107 LLVMValueRef tcs_out_layout;
108 LLVMValueRef tcs_in_layout;
109 LLVMValueRef oc_lds;
110 LLVMValueRef tess_factor_offset;
111 LLVMValueRef tcs_patch_id;
112 LLVMValueRef tcs_rel_ids;
113 LLVMValueRef tes_rel_patch_id;
114 LLVMValueRef tes_patch_id;
115 LLVMValueRef tes_u;
116 LLVMValueRef tes_v;
117
118 LLVMValueRef gsvs_ring_stride;
119 LLVMValueRef gsvs_num_entries;
120 LLVMValueRef gs2vs_offset;
121 LLVMValueRef gs_wave_id;
122 LLVMValueRef gs_vtx_offset[6];
123 LLVMValueRef gs_prim_id, gs_invocation_id;
124
125 LLVMValueRef esgs_ring;
126 LLVMValueRef gsvs_ring;
127 LLVMValueRef hs_ring_tess_offchip;
128 LLVMValueRef hs_ring_tess_factor;
129
130 LLVMValueRef prim_mask;
131 LLVMValueRef sample_pos_offset;
132 LLVMValueRef persp_sample, persp_center, persp_centroid;
133 LLVMValueRef linear_sample, linear_center, linear_centroid;
134
135 LLVMTypeRef i1;
136 LLVMTypeRef i8;
137 LLVMTypeRef i16;
138 LLVMTypeRef i32;
139 LLVMTypeRef i64;
140 LLVMTypeRef v2i32;
141 LLVMTypeRef v3i32;
142 LLVMTypeRef v4i32;
143 LLVMTypeRef v8i32;
144 LLVMTypeRef f64;
145 LLVMTypeRef f32;
146 LLVMTypeRef f16;
147 LLVMTypeRef v2f32;
148 LLVMTypeRef v4f32;
149 LLVMTypeRef voidt;
150
151 LLVMValueRef i1true;
152 LLVMValueRef i1false;
153 LLVMValueRef i32zero;
154 LLVMValueRef i32one;
155 LLVMValueRef f32zero;
156 LLVMValueRef f32one;
157 LLVMValueRef v4f32empty;
158
159 unsigned uniform_md_kind;
160 LLVMValueRef empty_md;
161 gl_shader_stage stage;
162
163 LLVMValueRef lds;
164 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
165
166 uint64_t input_mask;
167 uint64_t output_mask;
168 uint8_t num_output_clips;
169 uint8_t num_output_culls;
170
171 bool is_gs_copy_shader;
172 LLVMValueRef gs_next_vertex;
173 unsigned gs_max_out_vertices;
174
175 unsigned tes_primitive_mode;
176 uint64_t tess_outputs_written;
177 uint64_t tess_patch_outputs_written;
178 };
179
180 static inline struct nir_to_llvm_context *
181 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
182 {
183 struct nir_to_llvm_context *ctx = NULL;
184 return container_of(abi, ctx, abi);
185 }
186
187 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
188 const nir_deref_var *deref,
189 enum ac_descriptor_type desc_type,
190 bool image, bool write);
191
192 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
193 {
194 return (index * 4) + chan;
195 }
196
197 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
198 {
199 /* handle patch indices separate */
200 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
201 return 0;
202 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
203 return 1;
204 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
205 return 2 + (slot - VARYING_SLOT_PATCH0);
206
207 if (slot == VARYING_SLOT_POS)
208 return 0;
209 if (slot == VARYING_SLOT_PSIZ)
210 return 1;
211 if (slot == VARYING_SLOT_CLIP_DIST0)
212 return 2;
213 /* 3 is reserved for clip dist as well */
214 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
215 return 4 + (slot - VARYING_SLOT_VAR0);
216 unreachable("illegal slot in get unique index\n");
217 }
218
219 static void set_llvm_calling_convention(LLVMValueRef func,
220 gl_shader_stage stage)
221 {
222 enum radeon_llvm_calling_convention calling_conv;
223
224 switch (stage) {
225 case MESA_SHADER_VERTEX:
226 case MESA_SHADER_TESS_CTRL:
227 case MESA_SHADER_TESS_EVAL:
228 calling_conv = RADEON_LLVM_AMDGPU_VS;
229 break;
230 case MESA_SHADER_GEOMETRY:
231 calling_conv = RADEON_LLVM_AMDGPU_GS;
232 break;
233 case MESA_SHADER_FRAGMENT:
234 calling_conv = RADEON_LLVM_AMDGPU_PS;
235 break;
236 case MESA_SHADER_COMPUTE:
237 calling_conv = RADEON_LLVM_AMDGPU_CS;
238 break;
239 default:
240 unreachable("Unhandle shader type");
241 }
242
243 LLVMSetFunctionCallConv(func, calling_conv);
244 }
245
246 #define MAX_ARGS 23
247 struct arg_info {
248 LLVMTypeRef types[MAX_ARGS];
249 LLVMValueRef *assign[MAX_ARGS];
250 unsigned array_params_mask;
251 uint8_t count;
252 uint8_t user_sgpr_count;
253 uint8_t sgpr_count;
254 uint8_t num_user_sgprs_used;
255 uint8_t num_sgprs_used;
256 uint8_t num_vgprs_used;
257 };
258
259 static inline void
260 add_argument(struct arg_info *info,
261 LLVMTypeRef type, LLVMValueRef *param_ptr)
262 {
263 assert(info->count < MAX_ARGS);
264 info->assign[info->count] = param_ptr;
265 info->types[info->count] = type;
266 info->count++;
267 }
268
269 static inline void
270 add_sgpr_argument(struct arg_info *info,
271 LLVMTypeRef type, LLVMValueRef *param_ptr)
272 {
273 add_argument(info, type, param_ptr);
274 info->num_sgprs_used += ac_get_type_size(type) / 4;
275 info->sgpr_count++;
276 }
277
278 static inline void
279 add_user_sgpr_argument(struct arg_info *info,
280 LLVMTypeRef type,
281 LLVMValueRef *param_ptr)
282 {
283 add_sgpr_argument(info, type, param_ptr);
284 info->num_user_sgprs_used += ac_get_type_size(type) / 4;
285 info->user_sgpr_count++;
286 }
287
288 static inline void
289 add_vgpr_argument(struct arg_info *info,
290 LLVMTypeRef type,
291 LLVMValueRef *param_ptr)
292 {
293 add_argument(info, type, param_ptr);
294 info->num_vgprs_used += ac_get_type_size(type) / 4;
295 }
296
297 static inline void
298 add_user_sgpr_array_argument(struct arg_info *info,
299 LLVMTypeRef type,
300 LLVMValueRef *param_ptr)
301 {
302 info->array_params_mask |= (1 << info->count);
303 add_user_sgpr_argument(info, type, param_ptr);
304 }
305
306 static void assign_arguments(LLVMValueRef main_function,
307 struct arg_info *info)
308 {
309 unsigned i;
310 for (i = 0; i < info->count; i++) {
311 if (info->assign[i])
312 *info->assign[i] = LLVMGetParam(main_function, i);
313 }
314 }
315
316 static LLVMValueRef
317 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
318 LLVMBuilderRef builder, LLVMTypeRef *return_types,
319 unsigned num_return_elems,
320 struct arg_info *args,
321 unsigned max_workgroup_size,
322 bool unsafe_math)
323 {
324 LLVMTypeRef main_function_type, ret_type;
325 LLVMBasicBlockRef main_function_body;
326
327 if (num_return_elems)
328 ret_type = LLVMStructTypeInContext(ctx, return_types,
329 num_return_elems, true);
330 else
331 ret_type = LLVMVoidTypeInContext(ctx);
332
333 /* Setup the function */
334 main_function_type =
335 LLVMFunctionType(ret_type, args->types, args->count, 0);
336 LLVMValueRef main_function =
337 LLVMAddFunction(module, "main", main_function_type);
338 main_function_body =
339 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
340 LLVMPositionBuilderAtEnd(builder, main_function_body);
341
342 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
343 for (unsigned i = 0; i < args->sgpr_count; ++i) {
344 if (args->array_params_mask & (1 << i)) {
345 LLVMValueRef P = LLVMGetParam(main_function, i);
346 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
347 ac_add_attr_dereferenceable(P, UINT64_MAX);
348 }
349 else {
350 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
351 }
352 }
353
354 if (max_workgroup_size) {
355 ac_llvm_add_target_dep_function_attr(main_function,
356 "amdgpu-max-work-group-size",
357 max_workgroup_size);
358 }
359 if (unsafe_math) {
360 /* These were copied from some LLVM test. */
361 LLVMAddTargetDependentFunctionAttr(main_function,
362 "less-precise-fpmad",
363 "true");
364 LLVMAddTargetDependentFunctionAttr(main_function,
365 "no-infs-fp-math",
366 "true");
367 LLVMAddTargetDependentFunctionAttr(main_function,
368 "no-nans-fp-math",
369 "true");
370 LLVMAddTargetDependentFunctionAttr(main_function,
371 "unsafe-fp-math",
372 "true");
373 }
374 return main_function;
375 }
376
377 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
378 {
379 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
380 CONST_ADDR_SPACE);
381 }
382
383 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
384 {
385 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
386 type = LLVMGetElementType(type);
387
388 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
389 return LLVMGetIntTypeWidth(type);
390
391 if (type == ctx->f16)
392 return 16;
393 if (type == ctx->f32)
394 return 32;
395 if (type == ctx->f64)
396 return 64;
397
398 unreachable("Unhandled type kind in get_elem_bits");
399 }
400
401 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
402 LLVMValueRef param, unsigned rshift,
403 unsigned bitwidth)
404 {
405 LLVMValueRef value = param;
406 if (rshift)
407 value = LLVMBuildLShr(ctx->builder, value,
408 LLVMConstInt(ctx->i32, rshift, false), "");
409
410 if (rshift + bitwidth < 32) {
411 unsigned mask = (1 << bitwidth) - 1;
412 value = LLVMBuildAnd(ctx->builder, value,
413 LLVMConstInt(ctx->i32, mask, false), "");
414 }
415 return value;
416 }
417
418 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
419 {
420 switch (ctx->stage) {
421 case MESA_SHADER_TESS_CTRL:
422 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
423 case MESA_SHADER_TESS_EVAL:
424 return ctx->tes_rel_patch_id;
425 break;
426 default:
427 unreachable("Illegal stage");
428 }
429 }
430
431 /* Tessellation shaders pass outputs to the next shader using LDS.
432 *
433 * LS outputs = TCS inputs
434 * TCS outputs = TES inputs
435 *
436 * The LDS layout is:
437 * - TCS inputs for patch 0
438 * - TCS inputs for patch 1
439 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
440 * - ...
441 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
442 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
443 * - TCS outputs for patch 1
444 * - Per-patch TCS outputs for patch 1
445 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
446 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
447 * - ...
448 *
449 * All three shaders VS(LS), TCS, TES share the same LDS space.
450 */
451 static LLVMValueRef
452 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
453 {
454 if (ctx->stage == MESA_SHADER_VERTEX)
455 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
456 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
457 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
458 else {
459 assert(0);
460 return NULL;
461 }
462 }
463
464 static LLVMValueRef
465 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
466 {
467 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
468 }
469
470 static LLVMValueRef
471 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
472 {
473 return LLVMBuildMul(ctx->builder,
474 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
475 LLVMConstInt(ctx->i32, 4, false), "");
476 }
477
478 static LLVMValueRef
479 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
480 {
481 return LLVMBuildMul(ctx->builder,
482 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
483 LLVMConstInt(ctx->i32, 4, false), "");
484 }
485
486 static LLVMValueRef
487 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
488 {
489 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
490 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
491
492 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
493 }
494
495 static LLVMValueRef
496 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
497 {
498 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
499 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
500 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
501
502 return LLVMBuildAdd(ctx->builder, patch0_offset,
503 LLVMBuildMul(ctx->builder, patch_stride,
504 rel_patch_id, ""),
505 "");
506 }
507
508 static LLVMValueRef
509 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
510 {
511 LLVMValueRef patch0_patch_data_offset =
512 get_tcs_out_patch0_patch_data_offset(ctx);
513 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
514 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
515
516 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
517 LLVMBuildMul(ctx->builder, patch_stride,
518 rel_patch_id, ""),
519 "");
520 }
521
522 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
523 {
524 ud_info->sgpr_idx = *sgpr_idx;
525 ud_info->num_sgprs = num_sgprs;
526 ud_info->indirect = false;
527 ud_info->indirect_offset = 0;
528 *sgpr_idx += num_sgprs;
529 }
530
531 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
532 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
533 {
534 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
535 }
536
537
538 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
539 uint32_t indirect_offset)
540 {
541 ud_info->sgpr_idx = sgpr_idx;
542 ud_info->num_sgprs = num_sgprs;
543 ud_info->indirect = true;
544 ud_info->indirect_offset = indirect_offset;
545 }
546
547 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
548 {
549 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
550 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
551 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
552 "tess_lds");
553 }
554
555 struct user_sgpr_info {
556 bool need_ring_offsets;
557 uint8_t sgpr_count;
558 bool indirect_all_descriptor_sets;
559 };
560
561 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
562 struct user_sgpr_info *user_sgpr_info)
563 {
564 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
565
566 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
567 if (ctx->stage == MESA_SHADER_GEOMETRY ||
568 ctx->stage == MESA_SHADER_VERTEX ||
569 ctx->stage == MESA_SHADER_TESS_CTRL ||
570 ctx->stage == MESA_SHADER_TESS_EVAL ||
571 ctx->is_gs_copy_shader)
572 user_sgpr_info->need_ring_offsets = true;
573
574 if (ctx->stage == MESA_SHADER_FRAGMENT &&
575 ctx->shader_info->info.ps.needs_sample_positions)
576 user_sgpr_info->need_ring_offsets = true;
577
578 /* 2 user sgprs will nearly always be allocated for scratch/rings */
579 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
580 user_sgpr_info->sgpr_count += 2;
581 }
582
583 switch (ctx->stage) {
584 case MESA_SHADER_COMPUTE:
585 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
586 break;
587 case MESA_SHADER_FRAGMENT:
588 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
589 break;
590 case MESA_SHADER_VERTEX:
591 if (!ctx->is_gs_copy_shader) {
592 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
593 if (ctx->shader_info->info.vs.needs_draw_id) {
594 user_sgpr_info->sgpr_count += 3;
595 } else {
596 user_sgpr_info->sgpr_count += 2;
597 }
598 }
599 if (ctx->options->key.vs.as_ls)
600 user_sgpr_info->sgpr_count++;
601 break;
602 case MESA_SHADER_TESS_CTRL:
603 user_sgpr_info->sgpr_count += 4;
604 break;
605 case MESA_SHADER_TESS_EVAL:
606 user_sgpr_info->sgpr_count += 1;
607 break;
608 case MESA_SHADER_GEOMETRY:
609 user_sgpr_info->sgpr_count += 2;
610 break;
611 default:
612 break;
613 }
614
615 if (ctx->shader_info->info.needs_push_constants)
616 user_sgpr_info->sgpr_count += 2;
617
618 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
619 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
620 user_sgpr_info->sgpr_count += 2;
621 user_sgpr_info->indirect_all_descriptor_sets = true;
622 } else {
623 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
624 }
625 }
626
627 static void create_function(struct nir_to_llvm_context *ctx)
628 {
629 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
630 uint8_t user_sgpr_idx;
631 struct user_sgpr_info user_sgpr_info;
632 struct arg_info args = {};
633 LLVMValueRef desc_sets;
634
635 allocate_user_sgprs(ctx, &user_sgpr_info);
636 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
637 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
638 }
639
640 /* 1 for each descriptor set */
641 if (!user_sgpr_info.indirect_all_descriptor_sets) {
642 for (unsigned i = 0; i < num_sets; ++i) {
643 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
644 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
645 }
646 }
647 } else
648 add_user_sgpr_array_argument(&args, const_array(const_array(ctx->i8, 1024 * 1024), 32), &desc_sets);
649
650 if (ctx->shader_info->info.needs_push_constants) {
651 /* 1 for push constants and dynamic descriptors */
652 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
653 }
654
655 switch (ctx->stage) {
656 case MESA_SHADER_COMPUTE:
657 if (ctx->shader_info->info.cs.grid_components_used)
658 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
659 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
660 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
661 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
662 break;
663 case MESA_SHADER_VERTEX:
664 if (!ctx->is_gs_copy_shader) {
665 if (ctx->shader_info->info.vs.has_vertex_buffers)
666 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
667 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.base_vertex); // base vertex
668 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.start_instance);// start instance
669 if (ctx->shader_info->info.vs.needs_draw_id)
670 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.draw_id); // draw id
671 }
672 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
673 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
674 if (ctx->options->key.vs.as_es)
675 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
676 else if (ctx->options->key.vs.as_ls)
677 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
678 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
679 if (!ctx->is_gs_copy_shader) {
680 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
681 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
682 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
683 }
684 break;
685 case MESA_SHADER_TESS_CTRL:
686 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
687 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
688 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
689 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
690 if (ctx->shader_info->info.needs_multiview_view_index)
691 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
692 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
693 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
694 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
695 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
696 break;
697 case MESA_SHADER_TESS_EVAL:
698 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
699 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
700 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
701 if (ctx->options->key.tes.as_es) {
702 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
703 add_sgpr_argument(&args, ctx->i32, NULL); //
704 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
705 } else {
706 add_sgpr_argument(&args, ctx->i32, NULL); //
707 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
708 }
709 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
710 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
711 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
712 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
713 break;
714 case MESA_SHADER_GEOMETRY:
715 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
716 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
717 if (ctx->shader_info->info.needs_multiview_view_index)
718 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
719 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
720 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
721 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
722 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
723 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
724 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
725 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
726 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
727 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
728 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
729 break;
730 case MESA_SHADER_FRAGMENT:
731 if (ctx->shader_info->info.ps.needs_sample_positions)
732 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
733 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
734 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
735 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
736 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
737 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
738 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
739 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
740 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
741 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
742 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[0]); /* pos x float */
743 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[1]); /* pos y float */
744 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[2]); /* pos z float */
745 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[3]); /* pos w float */
746 add_vgpr_argument(&args, ctx->i32, &ctx->abi.front_face); /* front face */
747 add_vgpr_argument(&args, ctx->i32, &ctx->abi.ancillary); /* ancillary */
748 add_vgpr_argument(&args, ctx->i32, &ctx->abi.sample_coverage); /* sample coverage */
749 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
750 break;
751 default:
752 unreachable("Shader stage not implemented");
753 }
754
755 ctx->main_function = create_llvm_function(
756 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
757 ctx->max_workgroup_size,
758 ctx->options->unsafe_math);
759 set_llvm_calling_convention(ctx->main_function, ctx->stage);
760
761
762 ctx->shader_info->num_input_vgprs = 0;
763 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs =
764 ctx->options->supports_spill ? 2 : 0;
765
766 ctx->shader_info->num_user_sgprs += args.num_user_sgprs_used;
767 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
768
769 if (ctx->stage != MESA_SHADER_FRAGMENT)
770 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
771
772 assign_arguments(ctx->main_function, &args);
773
774 user_sgpr_idx = 0;
775
776 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
777 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
778 if (ctx->options->supports_spill) {
779 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
780 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
781 NULL, 0, AC_FUNC_ATTR_READNONE);
782 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
783 const_array(ctx->v4i32, 16), "");
784 }
785 }
786
787 if (!user_sgpr_info.indirect_all_descriptor_sets) {
788 for (unsigned i = 0; i < num_sets; ++i) {
789 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
790 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
791 } else
792 ctx->descriptor_sets[i] = NULL;
793 }
794 } else {
795 uint32_t desc_sgpr_idx = user_sgpr_idx;
796 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
797
798 for (unsigned i = 0; i < num_sets; ++i) {
799 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
800 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
801 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
802
803 } else
804 ctx->descriptor_sets[i] = NULL;
805 }
806 ctx->shader_info->need_indirect_descriptor_sets = true;
807 }
808
809 if (ctx->shader_info->info.needs_push_constants) {
810 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
811 }
812
813 switch (ctx->stage) {
814 case MESA_SHADER_COMPUTE:
815 if (ctx->shader_info->info.cs.grid_components_used) {
816 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
817 }
818 break;
819 case MESA_SHADER_VERTEX:
820 if (!ctx->is_gs_copy_shader) {
821 if (ctx->shader_info->info.vs.has_vertex_buffers) {
822 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
823 }
824 unsigned vs_num = 2;
825 if (ctx->shader_info->info.vs.needs_draw_id)
826 vs_num++;
827
828 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
829 }
830 if (ctx->view_index)
831 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
832 if (ctx->options->key.vs.as_ls) {
833 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
834 }
835 if (ctx->options->key.vs.as_ls)
836 declare_tess_lds(ctx);
837 break;
838 case MESA_SHADER_TESS_CTRL:
839 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
840 if (ctx->view_index)
841 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
842 declare_tess_lds(ctx);
843 break;
844 case MESA_SHADER_TESS_EVAL:
845 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
846 if (ctx->view_index)
847 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
848 break;
849 case MESA_SHADER_GEOMETRY:
850 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
851 if (ctx->view_index)
852 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
853 break;
854 case MESA_SHADER_FRAGMENT:
855 if (ctx->shader_info->info.ps.needs_sample_positions) {
856 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
857 }
858 break;
859 default:
860 unreachable("Shader stage not implemented");
861 }
862 }
863
864 static void setup_types(struct nir_to_llvm_context *ctx)
865 {
866 LLVMValueRef args[4];
867
868 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
869 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
870 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
871 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
872 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
873 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
874 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
875 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
876 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
877 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
878 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
879 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
880 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
881 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
882 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
883
884 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
885 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
886 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
887 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
888 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
889 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
890
891 args[0] = ctx->f32zero;
892 args[1] = ctx->f32zero;
893 args[2] = ctx->f32zero;
894 args[3] = ctx->f32one;
895 ctx->v4f32empty = LLVMConstVector(args, 4);
896
897 ctx->uniform_md_kind =
898 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
899 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
900
901 args[0] = LLVMConstReal(ctx->f32, 2.5);
902 }
903
904 static int get_llvm_num_components(LLVMValueRef value)
905 {
906 LLVMTypeRef type = LLVMTypeOf(value);
907 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
908 ? LLVMGetVectorSize(type)
909 : 1;
910 return num_components;
911 }
912
913 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
914 LLVMValueRef value,
915 int index)
916 {
917 int count = get_llvm_num_components(value);
918
919 assert(index < count);
920 if (count == 1)
921 return value;
922
923 return LLVMBuildExtractElement(ac->builder, value,
924 LLVMConstInt(ac->i32, index, false), "");
925 }
926
927 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
928 LLVMValueRef value, unsigned count)
929 {
930 unsigned num_components = get_llvm_num_components(value);
931 if (count == num_components)
932 return value;
933
934 LLVMValueRef masks[] = {
935 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
936 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
937
938 if (count == 1)
939 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
940 "");
941
942 LLVMValueRef swizzle = LLVMConstVector(masks, count);
943 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
944 }
945
946 static void
947 build_store_values_extended(struct ac_llvm_context *ac,
948 LLVMValueRef *values,
949 unsigned value_count,
950 unsigned value_stride,
951 LLVMValueRef vec)
952 {
953 LLVMBuilderRef builder = ac->builder;
954 unsigned i;
955
956 for (i = 0; i < value_count; i++) {
957 LLVMValueRef ptr = values[i * value_stride];
958 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
959 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
960 LLVMBuildStore(builder, value, ptr);
961 }
962 }
963
964 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
965 const nir_ssa_def *def)
966 {
967 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
968 if (def->num_components > 1) {
969 type = LLVMVectorType(type, def->num_components);
970 }
971 return type;
972 }
973
974 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
975 {
976 assert(src.is_ssa);
977 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
978 return (LLVMValueRef)entry->data;
979 }
980
981
982 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
983 const struct nir_block *b)
984 {
985 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
986 return (LLVMBasicBlockRef)entry->data;
987 }
988
989 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
990 nir_alu_src src,
991 unsigned num_components)
992 {
993 LLVMValueRef value = get_src(ctx, src.src);
994 bool need_swizzle = false;
995
996 assert(value);
997 LLVMTypeRef type = LLVMTypeOf(value);
998 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
999 ? LLVMGetVectorSize(type)
1000 : 1;
1001
1002 for (unsigned i = 0; i < num_components; ++i) {
1003 assert(src.swizzle[i] < src_components);
1004 if (src.swizzle[i] != i)
1005 need_swizzle = true;
1006 }
1007
1008 if (need_swizzle || num_components != src_components) {
1009 LLVMValueRef masks[] = {
1010 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1011 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1012 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1013 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1014
1015 if (src_components > 1 && num_components == 1) {
1016 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1017 masks[0], "");
1018 } else if (src_components == 1 && num_components > 1) {
1019 LLVMValueRef values[] = {value, value, value, value};
1020 value = ac_build_gather_values(&ctx->ac, values, num_components);
1021 } else {
1022 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1023 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1024 swizzle, "");
1025 }
1026 }
1027 assert(!src.negate);
1028 assert(!src.abs);
1029 return value;
1030 }
1031
1032 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1033 LLVMIntPredicate pred, LLVMValueRef src0,
1034 LLVMValueRef src1)
1035 {
1036 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1037 return LLVMBuildSelect(ctx->builder, result,
1038 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1039 LLVMConstInt(ctx->i32, 0, false), "");
1040 }
1041
1042 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1043 LLVMRealPredicate pred, LLVMValueRef src0,
1044 LLVMValueRef src1)
1045 {
1046 LLVMValueRef result;
1047 src0 = ac_to_float(ctx, src0);
1048 src1 = ac_to_float(ctx, src1);
1049 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1050 return LLVMBuildSelect(ctx->builder, result,
1051 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1052 LLVMConstInt(ctx->i32, 0, false), "");
1053 }
1054
1055 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1056 const char *intrin,
1057 LLVMTypeRef result_type,
1058 LLVMValueRef src0)
1059 {
1060 char name[64];
1061 LLVMValueRef params[] = {
1062 ac_to_float(ctx, src0),
1063 };
1064
1065 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1066 get_elem_bits(ctx, result_type));
1067 assert(length < sizeof(name));
1068 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1069 }
1070
1071 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1072 const char *intrin,
1073 LLVMTypeRef result_type,
1074 LLVMValueRef src0, LLVMValueRef src1)
1075 {
1076 char name[64];
1077 LLVMValueRef params[] = {
1078 ac_to_float(ctx, src0),
1079 ac_to_float(ctx, src1),
1080 };
1081
1082 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1083 get_elem_bits(ctx, result_type));
1084 assert(length < sizeof(name));
1085 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1086 }
1087
1088 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1089 const char *intrin,
1090 LLVMTypeRef result_type,
1091 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1092 {
1093 char name[64];
1094 LLVMValueRef params[] = {
1095 ac_to_float(ctx, src0),
1096 ac_to_float(ctx, src1),
1097 ac_to_float(ctx, src2),
1098 };
1099
1100 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1101 get_elem_bits(ctx, result_type));
1102 assert(length < sizeof(name));
1103 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1104 }
1105
1106 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1107 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1108 {
1109 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1110 ctx->i32_0, "");
1111 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1112 }
1113
1114 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1115 LLVMValueRef src0)
1116 {
1117 LLVMValueRef params[2] = {
1118 src0,
1119
1120 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1121 * add special code to check for x=0. The reason is that
1122 * the LLVM behavior for x=0 is different from what we
1123 * need here.
1124 *
1125 * The hardware already implements the correct behavior.
1126 */
1127 LLVMConstInt(ctx->i1, 1, false),
1128 };
1129
1130 LLVMValueRef lsb = ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32,
1131 params, 2,
1132 AC_FUNC_ATTR_READNONE);
1133
1134 /* TODO: We need an intrinsic to skip this conditional. */
1135 /* Check for zero: */
1136 return LLVMBuildSelect(ctx->builder, LLVMBuildICmp(ctx->builder,
1137 LLVMIntEQ, src0,
1138 ctx->i32_0, ""),
1139 LLVMConstInt(ctx->i32, -1, 0), lsb, "");
1140 }
1141
1142 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1143 LLVMValueRef src0)
1144 {
1145 return ac_build_imsb(ctx, src0, ctx->i32);
1146 }
1147
1148 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1149 LLVMValueRef src0)
1150 {
1151 return ac_build_umsb(ctx, src0, ctx->i32);
1152 }
1153
1154 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1155 LLVMIntPredicate pred,
1156 LLVMValueRef src0, LLVMValueRef src1)
1157 {
1158 return LLVMBuildSelect(ctx->builder,
1159 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1160 src0,
1161 src1, "");
1162
1163 }
1164 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1165 LLVMValueRef src0)
1166 {
1167 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1168 LLVMBuildNeg(ctx->builder, src0, ""));
1169 }
1170
1171 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1172 LLVMValueRef src0)
1173 {
1174 LLVMValueRef cmp, val;
1175
1176 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1177 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1178 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1179 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1180 return val;
1181 }
1182
1183 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1184 LLVMValueRef src0)
1185 {
1186 LLVMValueRef cmp, val;
1187
1188 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1189 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1190 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1191 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1192 return val;
1193 }
1194
1195 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1196 LLVMValueRef src0)
1197 {
1198 const char *intr = "llvm.floor.f32";
1199 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1200 LLVMValueRef params[] = {
1201 fsrc0,
1202 };
1203 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1204 ctx->f32, params, 1,
1205 AC_FUNC_ATTR_READNONE);
1206 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1207 }
1208
1209 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1210 const char *intrin,
1211 LLVMValueRef src0, LLVMValueRef src1)
1212 {
1213 LLVMTypeRef ret_type;
1214 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1215 LLVMValueRef res;
1216 LLVMValueRef params[] = { src0, src1 };
1217 ret_type = LLVMStructTypeInContext(ctx->context, types,
1218 2, true);
1219
1220 res = ac_build_intrinsic(ctx, intrin, ret_type,
1221 params, 2, AC_FUNC_ATTR_READNONE);
1222
1223 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1224 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1225 return res;
1226 }
1227
1228 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1229 LLVMValueRef src0)
1230 {
1231 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1232 }
1233
1234 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1235 LLVMValueRef src0)
1236 {
1237 src0 = ac_to_float(ctx, src0);
1238 return LLVMBuildSExt(ctx->builder,
1239 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1240 ctx->i32, "");
1241 }
1242
1243 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1244 LLVMValueRef src0)
1245 {
1246 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1247 }
1248
1249 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1250 LLVMValueRef src0)
1251 {
1252 return LLVMBuildSExt(ctx->builder,
1253 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1254 ctx->i32, "");
1255 }
1256
1257 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1258 LLVMValueRef src0)
1259 {
1260 LLVMValueRef result;
1261 LLVMValueRef cond = NULL;
1262
1263 src0 = ac_to_float(&ctx->ac, src0);
1264 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1265
1266 if (ctx->options->chip_class >= VI) {
1267 LLVMValueRef args[2];
1268 /* Check if the result is a denormal - and flush to 0 if so. */
1269 args[0] = result;
1270 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1271 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1272 }
1273
1274 /* need to convert back up to f32 */
1275 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1276
1277 if (ctx->options->chip_class >= VI)
1278 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1279 else {
1280 /* for SI/CIK */
1281 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1282 * so compare the result and flush to 0 if it's smaller.
1283 */
1284 LLVMValueRef temp, cond2;
1285 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1286 ctx->f32, result);
1287 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1288 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1289 temp, "");
1290 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1291 temp, ctx->f32zero, "");
1292 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1293 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1294 }
1295 return result;
1296 }
1297
1298 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1299 LLVMValueRef src0, LLVMValueRef src1)
1300 {
1301 LLVMValueRef dst64, result;
1302 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1303 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1304
1305 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1306 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1307 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1308 return result;
1309 }
1310
1311 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1312 LLVMValueRef src0, LLVMValueRef src1)
1313 {
1314 LLVMValueRef dst64, result;
1315 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1316 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1317
1318 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1319 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1320 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1321 return result;
1322 }
1323
1324 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1325 bool is_signed,
1326 const LLVMValueRef srcs[3])
1327 {
1328 LLVMValueRef result;
1329 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1330
1331 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1332 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1333 return result;
1334 }
1335
1336 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1337 LLVMValueRef src0, LLVMValueRef src1,
1338 LLVMValueRef src2, LLVMValueRef src3)
1339 {
1340 LLVMValueRef bfi_args[3], result;
1341
1342 bfi_args[0] = LLVMBuildShl(ctx->builder,
1343 LLVMBuildSub(ctx->builder,
1344 LLVMBuildShl(ctx->builder,
1345 ctx->i32_1,
1346 src3, ""),
1347 ctx->i32_1, ""),
1348 src2, "");
1349 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1350 bfi_args[2] = src0;
1351
1352 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1353
1354 /* Calculate:
1355 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1356 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1357 */
1358 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1359 LLVMBuildAnd(ctx->builder, bfi_args[0],
1360 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1361
1362 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1363 return result;
1364 }
1365
1366 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1367 LLVMValueRef src0)
1368 {
1369 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1370 int i;
1371 LLVMValueRef comp[2];
1372
1373 src0 = ac_to_float(ctx, src0);
1374 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1375 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1376 for (i = 0; i < 2; i++) {
1377 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1378 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1379 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1380 }
1381
1382 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1383 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1384
1385 return comp[0];
1386 }
1387
1388 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1389 LLVMValueRef src0)
1390 {
1391 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1392 LLVMValueRef temps[2], result, val;
1393 int i;
1394
1395 for (i = 0; i < 2; i++) {
1396 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1397 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1398 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1399 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1400 }
1401
1402 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1403 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1404 ctx->i32_0, "");
1405 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1406 ctx->i32_1, "");
1407 return result;
1408 }
1409
1410 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1411 nir_op op,
1412 LLVMValueRef src0)
1413 {
1414 unsigned mask;
1415 int idx;
1416 LLVMValueRef result;
1417
1418 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1419 mask = AC_TID_MASK_LEFT;
1420 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1421 mask = AC_TID_MASK_TOP;
1422 else
1423 mask = AC_TID_MASK_TOP_LEFT;
1424
1425 /* for DDX we want to next X pixel, DDY next Y pixel. */
1426 if (op == nir_op_fddx_fine ||
1427 op == nir_op_fddx_coarse ||
1428 op == nir_op_fddx)
1429 idx = 1;
1430 else
1431 idx = 2;
1432
1433 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1434 return result;
1435 }
1436
1437 /*
1438 * this takes an I,J coordinate pair,
1439 * and works out the X and Y derivatives.
1440 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1441 */
1442 static LLVMValueRef emit_ddxy_interp(
1443 struct ac_nir_context *ctx,
1444 LLVMValueRef interp_ij)
1445 {
1446 LLVMValueRef result[4], a;
1447 unsigned i;
1448
1449 for (i = 0; i < 2; i++) {
1450 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1451 LLVMConstInt(ctx->ac.i32, i, false), "");
1452 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1453 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1454 }
1455 return ac_build_gather_values(&ctx->ac, result, 4);
1456 }
1457
1458 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1459 {
1460 LLVMValueRef src[4], result = NULL;
1461 unsigned num_components = instr->dest.dest.ssa.num_components;
1462 unsigned src_components;
1463 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1464
1465 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1466 switch (instr->op) {
1467 case nir_op_vec2:
1468 case nir_op_vec3:
1469 case nir_op_vec4:
1470 src_components = 1;
1471 break;
1472 case nir_op_pack_half_2x16:
1473 src_components = 2;
1474 break;
1475 case nir_op_unpack_half_2x16:
1476 src_components = 1;
1477 break;
1478 default:
1479 src_components = num_components;
1480 break;
1481 }
1482 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1483 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1484
1485 switch (instr->op) {
1486 case nir_op_fmov:
1487 case nir_op_imov:
1488 result = src[0];
1489 break;
1490 case nir_op_fneg:
1491 src[0] = ac_to_float(&ctx->ac, src[0]);
1492 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1493 break;
1494 case nir_op_ineg:
1495 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1496 break;
1497 case nir_op_inot:
1498 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1499 break;
1500 case nir_op_iadd:
1501 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1502 break;
1503 case nir_op_fadd:
1504 src[0] = ac_to_float(&ctx->ac, src[0]);
1505 src[1] = ac_to_float(&ctx->ac, src[1]);
1506 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1507 break;
1508 case nir_op_fsub:
1509 src[0] = ac_to_float(&ctx->ac, src[0]);
1510 src[1] = ac_to_float(&ctx->ac, src[1]);
1511 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1512 break;
1513 case nir_op_isub:
1514 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1515 break;
1516 case nir_op_imul:
1517 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1518 break;
1519 case nir_op_imod:
1520 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1521 break;
1522 case nir_op_umod:
1523 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1524 break;
1525 case nir_op_fmod:
1526 src[0] = ac_to_float(&ctx->ac, src[0]);
1527 src[1] = ac_to_float(&ctx->ac, src[1]);
1528 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1529 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1530 ac_to_float_type(&ctx->ac, def_type), result);
1531 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1532 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1533 break;
1534 case nir_op_frem:
1535 src[0] = ac_to_float(&ctx->ac, src[0]);
1536 src[1] = ac_to_float(&ctx->ac, src[1]);
1537 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1538 break;
1539 case nir_op_irem:
1540 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1541 break;
1542 case nir_op_idiv:
1543 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1544 break;
1545 case nir_op_udiv:
1546 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1547 break;
1548 case nir_op_fmul:
1549 src[0] = ac_to_float(&ctx->ac, src[0]);
1550 src[1] = ac_to_float(&ctx->ac, src[1]);
1551 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1552 break;
1553 case nir_op_fdiv:
1554 src[0] = ac_to_float(&ctx->ac, src[0]);
1555 src[1] = ac_to_float(&ctx->ac, src[1]);
1556 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1557 break;
1558 case nir_op_frcp:
1559 src[0] = ac_to_float(&ctx->ac, src[0]);
1560 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1561 break;
1562 case nir_op_iand:
1563 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1564 break;
1565 case nir_op_ior:
1566 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1567 break;
1568 case nir_op_ixor:
1569 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1570 break;
1571 case nir_op_ishl:
1572 result = LLVMBuildShl(ctx->ac.builder, src[0],
1573 LLVMBuildZExt(ctx->ac.builder, src[1],
1574 LLVMTypeOf(src[0]), ""),
1575 "");
1576 break;
1577 case nir_op_ishr:
1578 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1579 LLVMBuildZExt(ctx->ac.builder, src[1],
1580 LLVMTypeOf(src[0]), ""),
1581 "");
1582 break;
1583 case nir_op_ushr:
1584 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1585 LLVMBuildZExt(ctx->ac.builder, src[1],
1586 LLVMTypeOf(src[0]), ""),
1587 "");
1588 break;
1589 case nir_op_ilt:
1590 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1591 break;
1592 case nir_op_ine:
1593 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1594 break;
1595 case nir_op_ieq:
1596 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1597 break;
1598 case nir_op_ige:
1599 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1600 break;
1601 case nir_op_ult:
1602 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1603 break;
1604 case nir_op_uge:
1605 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1606 break;
1607 case nir_op_feq:
1608 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1609 break;
1610 case nir_op_fne:
1611 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1612 break;
1613 case nir_op_flt:
1614 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1615 break;
1616 case nir_op_fge:
1617 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1618 break;
1619 case nir_op_fabs:
1620 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1621 ac_to_float_type(&ctx->ac, def_type), src[0]);
1622 break;
1623 case nir_op_iabs:
1624 result = emit_iabs(&ctx->ac, src[0]);
1625 break;
1626 case nir_op_imax:
1627 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1628 break;
1629 case nir_op_imin:
1630 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1631 break;
1632 case nir_op_umax:
1633 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1634 break;
1635 case nir_op_umin:
1636 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1637 break;
1638 case nir_op_isign:
1639 result = emit_isign(&ctx->ac, src[0]);
1640 break;
1641 case nir_op_fsign:
1642 src[0] = ac_to_float(&ctx->ac, src[0]);
1643 result = emit_fsign(&ctx->ac, src[0]);
1644 break;
1645 case nir_op_ffloor:
1646 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1647 ac_to_float_type(&ctx->ac, def_type), src[0]);
1648 break;
1649 case nir_op_ftrunc:
1650 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1651 ac_to_float_type(&ctx->ac, def_type), src[0]);
1652 break;
1653 case nir_op_fceil:
1654 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1655 ac_to_float_type(&ctx->ac, def_type), src[0]);
1656 break;
1657 case nir_op_fround_even:
1658 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1659 ac_to_float_type(&ctx->ac, def_type),src[0]);
1660 break;
1661 case nir_op_ffract:
1662 result = emit_ffract(&ctx->ac, src[0]);
1663 break;
1664 case nir_op_fsin:
1665 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1666 ac_to_float_type(&ctx->ac, def_type), src[0]);
1667 break;
1668 case nir_op_fcos:
1669 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1670 ac_to_float_type(&ctx->ac, def_type), src[0]);
1671 break;
1672 case nir_op_fsqrt:
1673 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1674 ac_to_float_type(&ctx->ac, def_type), src[0]);
1675 break;
1676 case nir_op_fexp2:
1677 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1678 ac_to_float_type(&ctx->ac, def_type), src[0]);
1679 break;
1680 case nir_op_flog2:
1681 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1682 ac_to_float_type(&ctx->ac, def_type), src[0]);
1683 break;
1684 case nir_op_frsq:
1685 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1686 ac_to_float_type(&ctx->ac, def_type), src[0]);
1687 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1688 break;
1689 case nir_op_fpow:
1690 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1691 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1692 break;
1693 case nir_op_fmax:
1694 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1695 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1696 if (instr->dest.dest.ssa.bit_size == 32)
1697 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1698 ac_to_float_type(&ctx->ac, def_type),
1699 result);
1700 break;
1701 case nir_op_fmin:
1702 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1703 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1704 if (instr->dest.dest.ssa.bit_size == 32)
1705 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1706 ac_to_float_type(&ctx->ac, def_type),
1707 result);
1708 break;
1709 case nir_op_ffma:
1710 result = emit_intrin_3f_param(&ctx->ac, "llvm.fma",
1711 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1712 break;
1713 case nir_op_ibitfield_extract:
1714 result = emit_bitfield_extract(&ctx->ac, true, src);
1715 break;
1716 case nir_op_ubitfield_extract:
1717 result = emit_bitfield_extract(&ctx->ac, false, src);
1718 break;
1719 case nir_op_bitfield_insert:
1720 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1721 break;
1722 case nir_op_bitfield_reverse:
1723 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1724 break;
1725 case nir_op_bit_count:
1726 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1727 break;
1728 case nir_op_vec2:
1729 case nir_op_vec3:
1730 case nir_op_vec4:
1731 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1732 src[i] = ac_to_integer(&ctx->ac, src[i]);
1733 result = ac_build_gather_values(&ctx->ac, src, num_components);
1734 break;
1735 case nir_op_f2i32:
1736 case nir_op_f2i64:
1737 src[0] = ac_to_float(&ctx->ac, src[0]);
1738 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1739 break;
1740 case nir_op_f2u32:
1741 case nir_op_f2u64:
1742 src[0] = ac_to_float(&ctx->ac, src[0]);
1743 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1744 break;
1745 case nir_op_i2f32:
1746 case nir_op_i2f64:
1747 src[0] = ac_to_integer(&ctx->ac, src[0]);
1748 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1749 break;
1750 case nir_op_u2f32:
1751 case nir_op_u2f64:
1752 src[0] = ac_to_integer(&ctx->ac, src[0]);
1753 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1754 break;
1755 case nir_op_f2f64:
1756 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1757 break;
1758 case nir_op_f2f32:
1759 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1760 break;
1761 case nir_op_u2u32:
1762 case nir_op_u2u64:
1763 src[0] = ac_to_integer(&ctx->ac, src[0]);
1764 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1765 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1766 else
1767 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1768 break;
1769 case nir_op_i2i32:
1770 case nir_op_i2i64:
1771 src[0] = ac_to_integer(&ctx->ac, src[0]);
1772 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1773 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1774 else
1775 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1776 break;
1777 case nir_op_bcsel:
1778 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1779 break;
1780 case nir_op_find_lsb:
1781 src[0] = ac_to_integer(&ctx->ac, src[0]);
1782 result = emit_find_lsb(&ctx->ac, src[0]);
1783 break;
1784 case nir_op_ufind_msb:
1785 src[0] = ac_to_integer(&ctx->ac, src[0]);
1786 result = emit_ufind_msb(&ctx->ac, src[0]);
1787 break;
1788 case nir_op_ifind_msb:
1789 src[0] = ac_to_integer(&ctx->ac, src[0]);
1790 result = emit_ifind_msb(&ctx->ac, src[0]);
1791 break;
1792 case nir_op_uadd_carry:
1793 src[0] = ac_to_integer(&ctx->ac, src[0]);
1794 src[1] = ac_to_integer(&ctx->ac, src[1]);
1795 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1796 break;
1797 case nir_op_usub_borrow:
1798 src[0] = ac_to_integer(&ctx->ac, src[0]);
1799 src[1] = ac_to_integer(&ctx->ac, src[1]);
1800 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1801 break;
1802 case nir_op_b2f:
1803 result = emit_b2f(&ctx->ac, src[0]);
1804 break;
1805 case nir_op_f2b:
1806 result = emit_f2b(&ctx->ac, src[0]);
1807 break;
1808 case nir_op_b2i:
1809 result = emit_b2i(&ctx->ac, src[0]);
1810 break;
1811 case nir_op_i2b:
1812 src[0] = ac_to_integer(&ctx->ac, src[0]);
1813 result = emit_i2b(&ctx->ac, src[0]);
1814 break;
1815 case nir_op_fquantize2f16:
1816 result = emit_f2f16(ctx->nctx, src[0]);
1817 break;
1818 case nir_op_umul_high:
1819 src[0] = ac_to_integer(&ctx->ac, src[0]);
1820 src[1] = ac_to_integer(&ctx->ac, src[1]);
1821 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1822 break;
1823 case nir_op_imul_high:
1824 src[0] = ac_to_integer(&ctx->ac, src[0]);
1825 src[1] = ac_to_integer(&ctx->ac, src[1]);
1826 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1827 break;
1828 case nir_op_pack_half_2x16:
1829 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1830 break;
1831 case nir_op_unpack_half_2x16:
1832 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1833 break;
1834 case nir_op_fddx:
1835 case nir_op_fddy:
1836 case nir_op_fddx_fine:
1837 case nir_op_fddy_fine:
1838 case nir_op_fddx_coarse:
1839 case nir_op_fddy_coarse:
1840 result = emit_ddxy(ctx, instr->op, src[0]);
1841 break;
1842
1843 case nir_op_unpack_64_2x32_split_x: {
1844 assert(instr->src[0].src.ssa->num_components == 1);
1845 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1846 LLVMVectorType(ctx->ac.i32, 2),
1847 "");
1848 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1849 ctx->ac.i32_0, "");
1850 break;
1851 }
1852
1853 case nir_op_unpack_64_2x32_split_y: {
1854 assert(instr->src[0].src.ssa->num_components == 1);
1855 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1856 LLVMVectorType(ctx->ac.i32, 2),
1857 "");
1858 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1859 ctx->ac.i32_1, "");
1860 break;
1861 }
1862
1863 case nir_op_pack_64_2x32_split: {
1864 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
1865 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1866 src[0], ctx->ac.i32_0, "");
1867 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1868 src[1], ctx->ac.i32_1, "");
1869 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1870 break;
1871 }
1872
1873 default:
1874 fprintf(stderr, "Unknown NIR alu instr: ");
1875 nir_print_instr(&instr->instr, stderr);
1876 fprintf(stderr, "\n");
1877 abort();
1878 }
1879
1880 if (result) {
1881 assert(instr->dest.dest.is_ssa);
1882 result = ac_to_integer(&ctx->ac, result);
1883 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1884 result);
1885 }
1886 }
1887
1888 static void visit_load_const(struct ac_nir_context *ctx,
1889 const nir_load_const_instr *instr)
1890 {
1891 LLVMValueRef values[4], value = NULL;
1892 LLVMTypeRef element_type =
1893 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1894
1895 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1896 switch (instr->def.bit_size) {
1897 case 32:
1898 values[i] = LLVMConstInt(element_type,
1899 instr->value.u32[i], false);
1900 break;
1901 case 64:
1902 values[i] = LLVMConstInt(element_type,
1903 instr->value.u64[i], false);
1904 break;
1905 default:
1906 fprintf(stderr,
1907 "unsupported nir load_const bit_size: %d\n",
1908 instr->def.bit_size);
1909 abort();
1910 }
1911 }
1912 if (instr->def.num_components > 1) {
1913 value = LLVMConstVector(values, instr->def.num_components);
1914 } else
1915 value = values[0];
1916
1917 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1918 }
1919
1920 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1921 LLVMTypeRef type)
1922 {
1923 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1924 return LLVMBuildBitCast(ctx->builder, ptr,
1925 LLVMPointerType(type, addr_space), "");
1926 }
1927
1928 static LLVMValueRef
1929 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1930 {
1931 LLVMValueRef size =
1932 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1933 LLVMConstInt(ctx->ac.i32, 2, false), "");
1934
1935 /* VI only */
1936 if (ctx->ac.chip_class == VI && in_elements) {
1937 /* On VI, the descriptor contains the size in bytes,
1938 * but TXQ must return the size in elements.
1939 * The stride is always non-zero for resources using TXQ.
1940 */
1941 LLVMValueRef stride =
1942 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1943 LLVMConstInt(ctx->ac.i32, 1, false), "");
1944 stride = LLVMBuildLShr(ctx->ac.builder, stride,
1945 LLVMConstInt(ctx->ac.i32, 16, false), "");
1946 stride = LLVMBuildAnd(ctx->ac.builder, stride,
1947 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
1948
1949 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
1950 }
1951 return size;
1952 }
1953
1954 /**
1955 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1956 * intrinsic names).
1957 */
1958 static void build_int_type_name(
1959 LLVMTypeRef type,
1960 char *buf, unsigned bufsize)
1961 {
1962 assert(bufsize >= 6);
1963
1964 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1965 snprintf(buf, bufsize, "v%ui32",
1966 LLVMGetVectorSize(type));
1967 else
1968 strcpy(buf, "i32");
1969 }
1970
1971 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
1972 struct ac_image_args *args,
1973 const nir_tex_instr *instr)
1974 {
1975 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1976 LLVMValueRef coord = args->addr;
1977 LLVMValueRef half_texel[2];
1978 LLVMValueRef compare_cube_wa = NULL;
1979 LLVMValueRef result;
1980 int c;
1981 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1982
1983 //TODO Rect
1984 {
1985 struct ac_image_args txq_args = { 0 };
1986
1987 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1988 txq_args.opcode = ac_image_get_resinfo;
1989 txq_args.dmask = 0xf;
1990 txq_args.addr = ctx->i32_0;
1991 txq_args.resource = args->resource;
1992 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
1993
1994 for (c = 0; c < 2; c++) {
1995 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1996 LLVMConstInt(ctx->i32, c, false), "");
1997 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1998 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
1999 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2000 LLVMConstReal(ctx->f32, -0.5), "");
2001 }
2002 }
2003
2004 LLVMValueRef orig_coords = args->addr;
2005
2006 for (c = 0; c < 2; c++) {
2007 LLVMValueRef tmp;
2008 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2009 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2010 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2011 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2012 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2013 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2014 }
2015
2016
2017 /*
2018 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2019 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2020 * workaround by sampling using a scaled type and converting.
2021 * This is taken from amdgpu-pro shaders.
2022 */
2023 /* NOTE this produces some ugly code compared to amdgpu-pro,
2024 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2025 * and then reads them back. -pro generates two selects,
2026 * one s_cmp for the descriptor rewriting
2027 * one v_cmp for the coordinate and result changes.
2028 */
2029 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2030 LLVMValueRef tmp, tmp2;
2031
2032 /* workaround 8/8/8/8 uint/sint cube gather bug */
2033 /* first detect it then change to a scaled read and f2i */
2034 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2035 tmp2 = tmp;
2036
2037 /* extract the DATA_FORMAT */
2038 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2039 LLVMConstInt(ctx->i32, 6, false), false);
2040
2041 /* is the DATA_FORMAT == 8_8_8_8 */
2042 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2043
2044 if (stype == GLSL_TYPE_UINT)
2045 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2046 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2047 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2048 else
2049 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2050 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2051 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2052
2053 /* replace the NUM FORMAT in the descriptor */
2054 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2055 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2056
2057 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2058
2059 /* don't modify the coordinates for this case */
2060 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2061 }
2062 args->addr = coord;
2063 result = ac_build_image_opcode(ctx, args);
2064
2065 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2066 LLVMValueRef tmp, tmp2;
2067
2068 /* if the cube workaround is in place, f2i the result. */
2069 for (c = 0; c < 4; c++) {
2070 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2071 if (stype == GLSL_TYPE_UINT)
2072 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2073 else
2074 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2075 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2076 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2077 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2078 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2079 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2080 }
2081 }
2082 return result;
2083 }
2084
2085 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2086 const nir_tex_instr *instr,
2087 bool lod_is_zero,
2088 struct ac_image_args *args)
2089 {
2090 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2091 return ac_build_buffer_load_format(&ctx->ac,
2092 args->resource,
2093 args->addr,
2094 LLVMConstInt(ctx->ac.i32, 0, false),
2095 true);
2096 }
2097
2098 args->opcode = ac_image_sample;
2099 args->compare = instr->is_shadow;
2100
2101 switch (instr->op) {
2102 case nir_texop_txf:
2103 case nir_texop_txf_ms:
2104 case nir_texop_samples_identical:
2105 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2106 args->compare = false;
2107 args->offset = false;
2108 break;
2109 case nir_texop_txb:
2110 args->bias = true;
2111 break;
2112 case nir_texop_txl:
2113 if (lod_is_zero)
2114 args->level_zero = true;
2115 else
2116 args->lod = true;
2117 break;
2118 case nir_texop_txs:
2119 case nir_texop_query_levels:
2120 args->opcode = ac_image_get_resinfo;
2121 break;
2122 case nir_texop_tex:
2123 if (ctx->stage != MESA_SHADER_FRAGMENT)
2124 args->level_zero = true;
2125 break;
2126 case nir_texop_txd:
2127 args->deriv = true;
2128 break;
2129 case nir_texop_tg4:
2130 args->opcode = ac_image_gather4;
2131 args->level_zero = true;
2132 break;
2133 case nir_texop_lod:
2134 args->opcode = ac_image_get_lod;
2135 args->compare = false;
2136 args->offset = false;
2137 break;
2138 default:
2139 break;
2140 }
2141
2142 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2143 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2144 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2145 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2146 }
2147 }
2148 return ac_build_image_opcode(&ctx->ac, args);
2149 }
2150
2151 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2152 nir_intrinsic_instr *instr)
2153 {
2154 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2155 unsigned desc_set = nir_intrinsic_desc_set(instr);
2156 unsigned binding = nir_intrinsic_binding(instr);
2157 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2158 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2159 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2160 unsigned base_offset = layout->binding[binding].offset;
2161 LLVMValueRef offset, stride;
2162
2163 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2164 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2165 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2166 layout->binding[binding].dynamic_offset_offset;
2167 desc_ptr = ctx->push_constants;
2168 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2169 stride = LLVMConstInt(ctx->i32, 16, false);
2170 } else
2171 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2172
2173 offset = LLVMConstInt(ctx->i32, base_offset, false);
2174 index = LLVMBuildMul(ctx->builder, index, stride, "");
2175 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2176
2177 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2178 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2179 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2180
2181 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2182 }
2183
2184 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2185 nir_intrinsic_instr *instr)
2186 {
2187 LLVMValueRef ptr, addr;
2188
2189 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2190 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2191
2192 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2193 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2194
2195 return LLVMBuildLoad(ctx->builder, ptr, "");
2196 }
2197
2198 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2199 const nir_intrinsic_instr *instr)
2200 {
2201 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2202
2203 return get_buffer_size(ctx, desc, false);
2204 }
2205 static void visit_store_ssbo(struct ac_nir_context *ctx,
2206 nir_intrinsic_instr *instr)
2207 {
2208 const char *store_name;
2209 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2210 LLVMTypeRef data_type = ctx->ac.f32;
2211 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2212 int components_32bit = elem_size_mult * instr->num_components;
2213 unsigned writemask = nir_intrinsic_write_mask(instr);
2214 LLVMValueRef base_data, base_offset;
2215 LLVMValueRef params[6];
2216 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2217
2218 params[1] = ctx->abi->load_ssbo(ctx->abi,
2219 get_src(ctx, instr->src[1]), true);
2220 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2221 params[4] = i1false; /* glc */
2222 params[5] = i1false; /* slc */
2223
2224 if (components_32bit > 1)
2225 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2226
2227 base_data = ac_to_float(&ctx->ac, src_data);
2228 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2229 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2230 data_type, "");
2231 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2232 while (writemask) {
2233 int start, count;
2234 LLVMValueRef data;
2235 LLVMValueRef offset;
2236 LLVMValueRef tmp;
2237 u_bit_scan_consecutive_range(&writemask, &start, &count);
2238
2239 /* Due to an LLVM limitation, split 3-element writes
2240 * into a 2-element and a 1-element write. */
2241 if (count == 3) {
2242 writemask |= 1 << (start + 2);
2243 count = 2;
2244 }
2245
2246 start *= elem_size_mult;
2247 count *= elem_size_mult;
2248
2249 if (count > 4) {
2250 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2251 count = 4;
2252 }
2253
2254 if (count == 4) {
2255 store_name = "llvm.amdgcn.buffer.store.v4f32";
2256 data = base_data;
2257 } else if (count == 2) {
2258 LLVMTypeRef v2f32 = LLVMVectorType(ctx->ac.f32, 2);
2259
2260 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2261 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2262 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(v2f32), tmp,
2263 ctx->ac.i32_0, "");
2264
2265 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2266 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2267 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2268 ctx->ac.i32_1, "");
2269 store_name = "llvm.amdgcn.buffer.store.v2f32";
2270
2271 } else {
2272 assert(count == 1);
2273 if (get_llvm_num_components(base_data) > 1)
2274 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2275 LLVMConstInt(ctx->ac.i32, start, false), "");
2276 else
2277 data = base_data;
2278 store_name = "llvm.amdgcn.buffer.store.f32";
2279 }
2280
2281 offset = base_offset;
2282 if (start != 0) {
2283 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2284 }
2285 params[0] = data;
2286 params[3] = offset;
2287 ac_build_intrinsic(&ctx->ac, store_name,
2288 ctx->ac.voidt, params, 6, 0);
2289 }
2290 }
2291
2292 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2293 const nir_intrinsic_instr *instr)
2294 {
2295 const char *name;
2296 LLVMValueRef params[6];
2297 int arg_count = 0;
2298
2299 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2300 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2301 }
2302 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2303 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2304 get_src(ctx, instr->src[0]),
2305 true);
2306 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2307 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2308 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2309
2310 switch (instr->intrinsic) {
2311 case nir_intrinsic_ssbo_atomic_add:
2312 name = "llvm.amdgcn.buffer.atomic.add";
2313 break;
2314 case nir_intrinsic_ssbo_atomic_imin:
2315 name = "llvm.amdgcn.buffer.atomic.smin";
2316 break;
2317 case nir_intrinsic_ssbo_atomic_umin:
2318 name = "llvm.amdgcn.buffer.atomic.umin";
2319 break;
2320 case nir_intrinsic_ssbo_atomic_imax:
2321 name = "llvm.amdgcn.buffer.atomic.smax";
2322 break;
2323 case nir_intrinsic_ssbo_atomic_umax:
2324 name = "llvm.amdgcn.buffer.atomic.umax";
2325 break;
2326 case nir_intrinsic_ssbo_atomic_and:
2327 name = "llvm.amdgcn.buffer.atomic.and";
2328 break;
2329 case nir_intrinsic_ssbo_atomic_or:
2330 name = "llvm.amdgcn.buffer.atomic.or";
2331 break;
2332 case nir_intrinsic_ssbo_atomic_xor:
2333 name = "llvm.amdgcn.buffer.atomic.xor";
2334 break;
2335 case nir_intrinsic_ssbo_atomic_exchange:
2336 name = "llvm.amdgcn.buffer.atomic.swap";
2337 break;
2338 case nir_intrinsic_ssbo_atomic_comp_swap:
2339 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2340 break;
2341 default:
2342 abort();
2343 }
2344
2345 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2346 }
2347
2348 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2349 const nir_intrinsic_instr *instr)
2350 {
2351 LLVMValueRef results[2];
2352 int load_components;
2353 int num_components = instr->num_components;
2354 if (instr->dest.ssa.bit_size == 64)
2355 num_components *= 2;
2356
2357 for (int i = 0; i < num_components; i += load_components) {
2358 load_components = MIN2(num_components - i, 4);
2359 const char *load_name;
2360 LLVMTypeRef data_type = ctx->ac.f32;
2361 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2362 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2363
2364 if (load_components == 3)
2365 data_type = LLVMVectorType(ctx->ac.f32, 4);
2366 else if (load_components > 1)
2367 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2368
2369 if (load_components >= 3)
2370 load_name = "llvm.amdgcn.buffer.load.v4f32";
2371 else if (load_components == 2)
2372 load_name = "llvm.amdgcn.buffer.load.v2f32";
2373 else if (load_components == 1)
2374 load_name = "llvm.amdgcn.buffer.load.f32";
2375 else
2376 unreachable("unhandled number of components");
2377
2378 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2379 LLVMValueRef params[] = {
2380 ctx->abi->load_ssbo(ctx->abi,
2381 get_src(ctx, instr->src[0]),
2382 false),
2383 LLVMConstInt(ctx->ac.i32, 0, false),
2384 offset,
2385 i1false,
2386 i1false,
2387 };
2388
2389 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2390
2391 }
2392
2393 LLVMValueRef ret = results[0];
2394 if (num_components > 4 || num_components == 3) {
2395 LLVMValueRef masks[] = {
2396 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2397 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2398 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2399 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2400 };
2401
2402 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2403 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2404 results[num_components > 4 ? 1 : 0], swizzle, "");
2405 }
2406
2407 return LLVMBuildBitCast(ctx->ac.builder, ret,
2408 get_def_type(ctx, &instr->dest.ssa), "");
2409 }
2410
2411 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2412 const nir_intrinsic_instr *instr)
2413 {
2414 LLVMValueRef results[8], ret;
2415 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2416 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2417 int num_components = instr->num_components;
2418
2419 if (ctx->abi->load_ubo)
2420 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2421
2422 if (instr->dest.ssa.bit_size == 64)
2423 num_components *= 2;
2424
2425 for (unsigned i = 0; i < num_components; ++i) {
2426 LLVMValueRef params[] = {
2427 rsrc,
2428 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2429 offset, "")
2430 };
2431 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2432 params, 2,
2433 AC_FUNC_ATTR_READNONE |
2434 AC_FUNC_ATTR_LEGACY);
2435 }
2436
2437
2438 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2439 return LLVMBuildBitCast(ctx->ac.builder, ret,
2440 get_def_type(ctx, &instr->dest.ssa), "");
2441 }
2442
2443 static void
2444 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2445 bool vs_in, unsigned *vertex_index_out,
2446 LLVMValueRef *vertex_index_ref,
2447 unsigned *const_out, LLVMValueRef *indir_out)
2448 {
2449 unsigned const_offset = 0;
2450 nir_deref *tail = &deref->deref;
2451 LLVMValueRef offset = NULL;
2452
2453 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2454 tail = tail->child;
2455 nir_deref_array *deref_array = nir_deref_as_array(tail);
2456 if (vertex_index_out)
2457 *vertex_index_out = deref_array->base_offset;
2458
2459 if (vertex_index_ref) {
2460 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2461 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2462 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2463 }
2464 *vertex_index_ref = vtx;
2465 }
2466 }
2467
2468 if (deref->var->data.compact) {
2469 assert(tail->child->deref_type == nir_deref_type_array);
2470 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2471 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2472 /* We always lower indirect dereferences for "compact" array vars. */
2473 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2474
2475 const_offset = deref_array->base_offset;
2476 goto out;
2477 }
2478
2479 while (tail->child != NULL) {
2480 const struct glsl_type *parent_type = tail->type;
2481 tail = tail->child;
2482
2483 if (tail->deref_type == nir_deref_type_array) {
2484 nir_deref_array *deref_array = nir_deref_as_array(tail);
2485 LLVMValueRef index, stride, local_offset;
2486 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2487
2488 const_offset += size * deref_array->base_offset;
2489 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2490 continue;
2491
2492 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2493 index = get_src(ctx, deref_array->indirect);
2494 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2495 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2496
2497 if (offset)
2498 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2499 else
2500 offset = local_offset;
2501 } else if (tail->deref_type == nir_deref_type_struct) {
2502 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2503
2504 for (unsigned i = 0; i < deref_struct->index; i++) {
2505 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2506 const_offset += glsl_count_attribute_slots(ft, vs_in);
2507 }
2508 } else
2509 unreachable("unsupported deref type");
2510
2511 }
2512 out:
2513 if (const_offset && offset)
2514 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2515 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2516 "");
2517
2518 *const_out = const_offset;
2519 *indir_out = offset;
2520 }
2521
2522 static LLVMValueRef
2523 lds_load(struct nir_to_llvm_context *ctx,
2524 LLVMValueRef dw_addr)
2525 {
2526 LLVMValueRef value;
2527 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2528 return value;
2529 }
2530
2531 static void
2532 lds_store(struct nir_to_llvm_context *ctx,
2533 LLVMValueRef dw_addr, LLVMValueRef value)
2534 {
2535 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2536 ac_build_indexed_store(&ctx->ac, ctx->lds,
2537 dw_addr, value);
2538 }
2539
2540 /* The offchip buffer layout for TCS->TES is
2541 *
2542 * - attribute 0 of patch 0 vertex 0
2543 * - attribute 0 of patch 0 vertex 1
2544 * - attribute 0 of patch 0 vertex 2
2545 * ...
2546 * - attribute 0 of patch 1 vertex 0
2547 * - attribute 0 of patch 1 vertex 1
2548 * ...
2549 * - attribute 1 of patch 0 vertex 0
2550 * - attribute 1 of patch 0 vertex 1
2551 * ...
2552 * - per patch attribute 0 of patch 0
2553 * - per patch attribute 0 of patch 1
2554 * ...
2555 *
2556 * Note that every attribute has 4 components.
2557 */
2558 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2559 LLVMValueRef vertex_index,
2560 LLVMValueRef param_index)
2561 {
2562 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2563 LLVMValueRef param_stride, constant16;
2564 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2565
2566 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2567 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2568 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2569 num_patches, "");
2570
2571 constant16 = LLVMConstInt(ctx->i32, 16, false);
2572 if (vertex_index) {
2573 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2574 vertices_per_patch, "");
2575
2576 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2577 vertex_index, "");
2578
2579 param_stride = total_vertices;
2580 } else {
2581 base_addr = rel_patch_id;
2582 param_stride = num_patches;
2583 }
2584
2585 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2586 LLVMBuildMul(ctx->builder, param_index,
2587 param_stride, ""), "");
2588
2589 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2590
2591 if (!vertex_index) {
2592 LLVMValueRef patch_data_offset =
2593 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2594
2595 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2596 patch_data_offset, "");
2597 }
2598 return base_addr;
2599 }
2600
2601 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2602 unsigned param,
2603 unsigned const_index,
2604 bool is_compact,
2605 LLVMValueRef vertex_index,
2606 LLVMValueRef indir_index)
2607 {
2608 LLVMValueRef param_index;
2609
2610 if (indir_index)
2611 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2612 indir_index, "");
2613 else {
2614 if (const_index && !is_compact)
2615 param += const_index;
2616 param_index = LLVMConstInt(ctx->i32, param, false);
2617 }
2618 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2619 }
2620
2621 static void
2622 mark_tess_output(struct nir_to_llvm_context *ctx,
2623 bool is_patch, uint32_t param)
2624
2625 {
2626 if (is_patch) {
2627 ctx->tess_patch_outputs_written |= (1ull << param);
2628 } else
2629 ctx->tess_outputs_written |= (1ull << param);
2630 }
2631
2632 static LLVMValueRef
2633 get_dw_address(struct nir_to_llvm_context *ctx,
2634 LLVMValueRef dw_addr,
2635 unsigned param,
2636 unsigned const_index,
2637 bool compact_const_index,
2638 LLVMValueRef vertex_index,
2639 LLVMValueRef stride,
2640 LLVMValueRef indir_index)
2641
2642 {
2643
2644 if (vertex_index) {
2645 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2646 LLVMBuildMul(ctx->builder,
2647 vertex_index,
2648 stride, ""), "");
2649 }
2650
2651 if (indir_index)
2652 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2653 LLVMBuildMul(ctx->builder, indir_index,
2654 LLVMConstInt(ctx->i32, 4, false), ""), "");
2655 else if (const_index && !compact_const_index)
2656 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2657 LLVMConstInt(ctx->i32, const_index, false), "");
2658
2659 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2660 LLVMConstInt(ctx->i32, param * 4, false), "");
2661
2662 if (const_index && compact_const_index)
2663 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2664 LLVMConstInt(ctx->i32, const_index, false), "");
2665 return dw_addr;
2666 }
2667
2668 static LLVMValueRef
2669 load_tcs_input(struct nir_to_llvm_context *ctx,
2670 nir_intrinsic_instr *instr)
2671 {
2672 LLVMValueRef dw_addr, stride;
2673 unsigned const_index;
2674 LLVMValueRef vertex_index;
2675 LLVMValueRef indir_index;
2676 unsigned param;
2677 LLVMValueRef value[4], result;
2678 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2679 const bool is_compact = instr->variables[0]->var->data.compact;
2680 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2681 get_deref_offset(ctx->nir, instr->variables[0],
2682 false, NULL, per_vertex ? &vertex_index : NULL,
2683 &const_index, &indir_index);
2684
2685 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2686 dw_addr = get_tcs_in_current_patch_offset(ctx);
2687 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2688 indir_index);
2689
2690 for (unsigned i = 0; i < instr->num_components; i++) {
2691 value[i] = lds_load(ctx, dw_addr);
2692 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2693 ctx->i32one, "");
2694 }
2695 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2696 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2697 return result;
2698 }
2699
2700 static LLVMValueRef
2701 load_tcs_output(struct nir_to_llvm_context *ctx,
2702 nir_intrinsic_instr *instr)
2703 {
2704 LLVMValueRef dw_addr;
2705 LLVMValueRef stride = NULL;
2706 LLVMValueRef value[4], result;
2707 LLVMValueRef vertex_index = NULL;
2708 LLVMValueRef indir_index = NULL;
2709 unsigned const_index = 0;
2710 unsigned param;
2711 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2712 const bool is_compact = instr->variables[0]->var->data.compact;
2713 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2714 get_deref_offset(ctx->nir, instr->variables[0],
2715 false, NULL, per_vertex ? &vertex_index : NULL,
2716 &const_index, &indir_index);
2717
2718 if (!instr->variables[0]->var->data.patch) {
2719 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2720 dw_addr = get_tcs_out_current_patch_offset(ctx);
2721 } else {
2722 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2723 }
2724
2725 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2726 indir_index);
2727
2728 for (unsigned i = 0; i < instr->num_components; i++) {
2729 value[i] = lds_load(ctx, dw_addr);
2730 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2731 ctx->i32one, "");
2732 }
2733 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2734 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2735 return result;
2736 }
2737
2738 static void
2739 store_tcs_output(struct nir_to_llvm_context *ctx,
2740 nir_intrinsic_instr *instr,
2741 LLVMValueRef src,
2742 unsigned writemask)
2743 {
2744 LLVMValueRef dw_addr;
2745 LLVMValueRef stride = NULL;
2746 LLVMValueRef buf_addr = NULL;
2747 LLVMValueRef vertex_index = NULL;
2748 LLVMValueRef indir_index = NULL;
2749 unsigned const_index = 0;
2750 unsigned param;
2751 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2752 const bool is_compact = instr->variables[0]->var->data.compact;
2753
2754 get_deref_offset(ctx->nir, instr->variables[0],
2755 false, NULL, per_vertex ? &vertex_index : NULL,
2756 &const_index, &indir_index);
2757
2758 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2759 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2760 is_compact && const_index > 3) {
2761 const_index -= 3;
2762 param++;
2763 }
2764
2765 if (!instr->variables[0]->var->data.patch) {
2766 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2767 dw_addr = get_tcs_out_current_patch_offset(ctx);
2768 } else {
2769 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2770 }
2771
2772 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2773
2774 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2775 indir_index);
2776 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2777 vertex_index, indir_index);
2778
2779 unsigned base = is_compact ? const_index : 0;
2780 for (unsigned chan = 0; chan < 8; chan++) {
2781 bool is_tess_factor = false;
2782 if (!(writemask & (1 << chan)))
2783 continue;
2784 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan);
2785
2786 lds_store(ctx, dw_addr, value);
2787
2788 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2789 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2790 is_tess_factor = true;
2791
2792 if (!is_tess_factor && writemask != 0xF)
2793 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2794 buf_addr, ctx->oc_lds,
2795 4 * (base + chan), 1, 0, true, false);
2796
2797 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2798 ctx->i32one, "");
2799 }
2800
2801 if (writemask == 0xF) {
2802 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2803 buf_addr, ctx->oc_lds,
2804 (base * 4), 1, 0, true, false);
2805 }
2806 }
2807
2808 static LLVMValueRef
2809 load_tes_input(struct nir_to_llvm_context *ctx,
2810 const nir_intrinsic_instr *instr)
2811 {
2812 LLVMValueRef buf_addr;
2813 LLVMValueRef result;
2814 LLVMValueRef vertex_index = NULL;
2815 LLVMValueRef indir_index = NULL;
2816 unsigned const_index = 0;
2817 unsigned param;
2818 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2819 const bool is_compact = instr->variables[0]->var->data.compact;
2820
2821 get_deref_offset(ctx->nir, instr->variables[0],
2822 false, NULL, per_vertex ? &vertex_index : NULL,
2823 &const_index, &indir_index);
2824 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2825 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2826 is_compact && const_index > 3) {
2827 const_index -= 3;
2828 param++;
2829 }
2830 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2831 is_compact, vertex_index, indir_index);
2832
2833 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2834 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2835 result = trim_vector(&ctx->ac, result, instr->num_components);
2836 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2837 return result;
2838 }
2839
2840 static LLVMValueRef
2841 load_gs_input(struct nir_to_llvm_context *ctx,
2842 nir_intrinsic_instr *instr)
2843 {
2844 LLVMValueRef indir_index, vtx_offset;
2845 unsigned const_index;
2846 LLVMValueRef args[9];
2847 unsigned param, vtx_offset_param;
2848 LLVMValueRef value[4], result;
2849 unsigned vertex_index;
2850 get_deref_offset(ctx->nir, instr->variables[0],
2851 false, &vertex_index, NULL,
2852 &const_index, &indir_index);
2853 vtx_offset_param = vertex_index;
2854 assert(vtx_offset_param < 6);
2855 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2856 LLVMConstInt(ctx->i32, 4, false), "");
2857
2858 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2859 for (unsigned i = 0; i < instr->num_components; i++) {
2860
2861 args[0] = ctx->esgs_ring;
2862 args[1] = vtx_offset;
2863 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2864 args[3] = ctx->i32zero;
2865 args[4] = ctx->i32one; /* OFFEN */
2866 args[5] = ctx->i32zero; /* IDXEN */
2867 args[6] = ctx->i32one; /* GLC */
2868 args[7] = ctx->i32zero; /* SLC */
2869 args[8] = ctx->i32zero; /* TFE */
2870
2871 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2872 ctx->i32, args, 9,
2873 AC_FUNC_ATTR_READONLY |
2874 AC_FUNC_ATTR_LEGACY);
2875 }
2876 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2877
2878 return result;
2879 }
2880
2881 static LLVMValueRef
2882 build_gep_for_deref(struct ac_nir_context *ctx,
2883 nir_deref_var *deref)
2884 {
2885 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2886 assert(entry->data);
2887 LLVMValueRef val = entry->data;
2888 nir_deref *tail = deref->deref.child;
2889 while (tail != NULL) {
2890 LLVMValueRef offset;
2891 switch (tail->deref_type) {
2892 case nir_deref_type_array: {
2893 nir_deref_array *array = nir_deref_as_array(tail);
2894 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2895 if (array->deref_array_type ==
2896 nir_deref_array_type_indirect) {
2897 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2898 get_src(ctx,
2899 array->indirect),
2900 "");
2901 }
2902 break;
2903 }
2904 case nir_deref_type_struct: {
2905 nir_deref_struct *deref_struct =
2906 nir_deref_as_struct(tail);
2907 offset = LLVMConstInt(ctx->ac.i32,
2908 deref_struct->index, 0);
2909 break;
2910 }
2911 default:
2912 unreachable("bad deref type");
2913 }
2914 val = ac_build_gep0(&ctx->ac, val, offset);
2915 tail = tail->child;
2916 }
2917 return val;
2918 }
2919
2920 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
2921 nir_intrinsic_instr *instr)
2922 {
2923 LLVMValueRef values[8];
2924 int idx = instr->variables[0]->var->data.driver_location;
2925 int ve = instr->dest.ssa.num_components;
2926 LLVMValueRef indir_index;
2927 LLVMValueRef ret;
2928 unsigned const_index;
2929 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2930 instr->variables[0]->var->data.mode == nir_var_shader_in;
2931 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2932 &const_index, &indir_index);
2933
2934 if (instr->dest.ssa.bit_size == 64)
2935 ve *= 2;
2936
2937 switch (instr->variables[0]->var->data.mode) {
2938 case nir_var_shader_in:
2939 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2940 return load_tcs_input(ctx->nctx, instr);
2941 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2942 return load_tes_input(ctx->nctx, instr);
2943 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2944 return load_gs_input(ctx->nctx, instr);
2945 }
2946 for (unsigned chan = 0; chan < ve; chan++) {
2947 if (indir_index) {
2948 unsigned count = glsl_count_attribute_slots(
2949 instr->variables[0]->var->type,
2950 ctx->stage == MESA_SHADER_VERTEX);
2951 count -= chan / 4;
2952 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2953 &ctx->ac, ctx->abi->inputs + idx + chan, count,
2954 4, false, true);
2955
2956 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
2957 tmp_vec,
2958 indir_index, "");
2959 } else
2960 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
2961 }
2962 break;
2963 case nir_var_local:
2964 for (unsigned chan = 0; chan < ve; chan++) {
2965 if (indir_index) {
2966 unsigned count = glsl_count_attribute_slots(
2967 instr->variables[0]->var->type, false);
2968 count -= chan / 4;
2969 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2970 &ctx->ac, ctx->locals + idx + chan, count,
2971 4, true, true);
2972
2973 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
2974 tmp_vec,
2975 indir_index, "");
2976 } else {
2977 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
2978 }
2979 }
2980 break;
2981 case nir_var_shared: {
2982 LLVMValueRef address = build_gep_for_deref(ctx,
2983 instr->variables[0]);
2984 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
2985 return LLVMBuildBitCast(ctx->ac.builder, val,
2986 get_def_type(ctx, &instr->dest.ssa),
2987 "");
2988 }
2989 case nir_var_shader_out:
2990 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2991 return load_tcs_output(ctx->nctx, instr);
2992 for (unsigned chan = 0; chan < ve; chan++) {
2993 if (indir_index) {
2994 unsigned count = glsl_count_attribute_slots(
2995 instr->variables[0]->var->type, false);
2996 count -= chan / 4;
2997 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2998 &ctx->ac, ctx->outputs + idx + chan, count,
2999 4, true, true);
3000
3001 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3002 tmp_vec,
3003 indir_index, "");
3004 } else {
3005 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3006 ctx->outputs[idx + chan + const_index * 4],
3007 "");
3008 }
3009 }
3010 break;
3011 default:
3012 unreachable("unhandle variable mode");
3013 }
3014 ret = ac_build_gather_values(&ctx->ac, values, ve);
3015 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3016 }
3017
3018 static void
3019 visit_store_var(struct ac_nir_context *ctx,
3020 nir_intrinsic_instr *instr)
3021 {
3022 LLVMValueRef temp_ptr, value;
3023 int idx = instr->variables[0]->var->data.driver_location;
3024 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3025 int writemask = instr->const_index[0];
3026 LLVMValueRef indir_index;
3027 unsigned const_index;
3028 get_deref_offset(ctx, instr->variables[0], false,
3029 NULL, NULL, &const_index, &indir_index);
3030
3031 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3032 int old_writemask = writemask;
3033
3034 src = LLVMBuildBitCast(ctx->ac.builder, src,
3035 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3036 "");
3037
3038 writemask = 0;
3039 for (unsigned chan = 0; chan < 4; chan++) {
3040 if (old_writemask & (1 << chan))
3041 writemask |= 3u << (2 * chan);
3042 }
3043 }
3044
3045 switch (instr->variables[0]->var->data.mode) {
3046 case nir_var_shader_out:
3047
3048 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3049 store_tcs_output(ctx->nctx, instr, src, writemask);
3050 return;
3051 }
3052
3053 for (unsigned chan = 0; chan < 8; chan++) {
3054 int stride = 4;
3055 if (!(writemask & (1 << chan)))
3056 continue;
3057
3058 value = llvm_extract_elem(&ctx->ac, src, chan);
3059
3060 if (instr->variables[0]->var->data.compact)
3061 stride = 1;
3062 if (indir_index) {
3063 unsigned count = glsl_count_attribute_slots(
3064 instr->variables[0]->var->type, false);
3065 count -= chan / 4;
3066 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3067 &ctx->ac, ctx->outputs + idx + chan, count,
3068 stride, true, true);
3069
3070 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3071 value, indir_index, "");
3072 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3073 count, stride, tmp_vec);
3074
3075 } else {
3076 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3077
3078 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3079 }
3080 }
3081 break;
3082 case nir_var_local:
3083 for (unsigned chan = 0; chan < 8; chan++) {
3084 if (!(writemask & (1 << chan)))
3085 continue;
3086
3087 value = llvm_extract_elem(&ctx->ac, src, chan);
3088 if (indir_index) {
3089 unsigned count = glsl_count_attribute_slots(
3090 instr->variables[0]->var->type, false);
3091 count -= chan / 4;
3092 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3093 &ctx->ac, ctx->locals + idx + chan, count,
3094 4, true, true);
3095
3096 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3097 value, indir_index, "");
3098 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3099 count, 4, tmp_vec);
3100 } else {
3101 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3102
3103 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3104 }
3105 }
3106 break;
3107 case nir_var_shared: {
3108 int writemask = instr->const_index[0];
3109 LLVMValueRef address = build_gep_for_deref(ctx,
3110 instr->variables[0]);
3111 LLVMValueRef val = get_src(ctx, instr->src[0]);
3112 unsigned components =
3113 glsl_get_vector_elements(
3114 nir_deref_tail(&instr->variables[0]->deref)->type);
3115 if (writemask == (1 << components) - 1) {
3116 val = LLVMBuildBitCast(
3117 ctx->ac.builder, val,
3118 LLVMGetElementType(LLVMTypeOf(address)), "");
3119 LLVMBuildStore(ctx->ac.builder, val, address);
3120 } else {
3121 for (unsigned chan = 0; chan < 4; chan++) {
3122 if (!(writemask & (1 << chan)))
3123 continue;
3124 LLVMValueRef ptr =
3125 LLVMBuildStructGEP(ctx->ac.builder,
3126 address, chan, "");
3127 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3128 chan);
3129 src = LLVMBuildBitCast(
3130 ctx->ac.builder, src,
3131 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3132 LLVMBuildStore(ctx->ac.builder, src, ptr);
3133 }
3134 }
3135 break;
3136 }
3137 default:
3138 break;
3139 }
3140 }
3141
3142 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3143 {
3144 switch (dim) {
3145 case GLSL_SAMPLER_DIM_BUF:
3146 return 1;
3147 case GLSL_SAMPLER_DIM_1D:
3148 return array ? 2 : 1;
3149 case GLSL_SAMPLER_DIM_2D:
3150 return array ? 3 : 2;
3151 case GLSL_SAMPLER_DIM_MS:
3152 return array ? 4 : 3;
3153 case GLSL_SAMPLER_DIM_3D:
3154 case GLSL_SAMPLER_DIM_CUBE:
3155 return 3;
3156 case GLSL_SAMPLER_DIM_RECT:
3157 case GLSL_SAMPLER_DIM_SUBPASS:
3158 return 2;
3159 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3160 return 3;
3161 default:
3162 break;
3163 }
3164 return 0;
3165 }
3166
3167
3168
3169 /* Adjust the sample index according to FMASK.
3170 *
3171 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3172 * which is the identity mapping. Each nibble says which physical sample
3173 * should be fetched to get that sample.
3174 *
3175 * For example, 0x11111100 means there are only 2 samples stored and
3176 * the second sample covers 3/4 of the pixel. When reading samples 0
3177 * and 1, return physical sample 0 (determined by the first two 0s
3178 * in FMASK), otherwise return physical sample 1.
3179 *
3180 * The sample index should be adjusted as follows:
3181 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3182 */
3183 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3184 LLVMValueRef coord_x, LLVMValueRef coord_y,
3185 LLVMValueRef coord_z,
3186 LLVMValueRef sample_index,
3187 LLVMValueRef fmask_desc_ptr)
3188 {
3189 LLVMValueRef fmask_load_address[4];
3190 LLVMValueRef res;
3191
3192 fmask_load_address[0] = coord_x;
3193 fmask_load_address[1] = coord_y;
3194 if (coord_z) {
3195 fmask_load_address[2] = coord_z;
3196 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3197 }
3198
3199 struct ac_image_args args = {0};
3200
3201 args.opcode = ac_image_load;
3202 args.da = coord_z ? true : false;
3203 args.resource = fmask_desc_ptr;
3204 args.dmask = 0xf;
3205 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3206
3207 res = ac_build_image_opcode(ctx, &args);
3208
3209 res = ac_to_integer(ctx, res);
3210 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3211 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3212
3213 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3214 res,
3215 ctx->i32_0, "");
3216
3217 LLVMValueRef sample_index4 =
3218 LLVMBuildMul(ctx->builder, sample_index, four, "");
3219 LLVMValueRef shifted_fmask =
3220 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3221 LLVMValueRef final_sample =
3222 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3223
3224 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3225 * resource descriptor is 0 (invalid),
3226 */
3227 LLVMValueRef fmask_desc =
3228 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3229 ctx->v8i32, "");
3230
3231 LLVMValueRef fmask_word1 =
3232 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3233 ctx->i32_1, "");
3234
3235 LLVMValueRef word1_is_nonzero =
3236 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3237 fmask_word1, ctx->i32_0, "");
3238
3239 /* Replace the MSAA sample index. */
3240 sample_index =
3241 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3242 final_sample, sample_index, "");
3243 return sample_index;
3244 }
3245
3246 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3247 const nir_intrinsic_instr *instr)
3248 {
3249 const struct glsl_type *type = instr->variables[0]->var->type;
3250 if(instr->variables[0]->deref.child)
3251 type = instr->variables[0]->deref.child->type;
3252
3253 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3254 LLVMValueRef coords[4];
3255 LLVMValueRef masks[] = {
3256 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3257 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3258 };
3259 LLVMValueRef res;
3260 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3261
3262 int count;
3263 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3264 bool is_array = glsl_sampler_type_is_array(type);
3265 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3266 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3267 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3268 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3269 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3270 count = image_type_to_components_count(dim, is_array);
3271
3272 if (is_ms) {
3273 LLVMValueRef fmask_load_address[3];
3274 int chan;
3275
3276 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3277 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3278 if (is_array)
3279 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3280 else
3281 fmask_load_address[2] = NULL;
3282 if (add_frag_pos) {
3283 for (chan = 0; chan < 2; ++chan)
3284 fmask_load_address[chan] =
3285 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3286 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3287 ctx->ac.i32, ""), "");
3288 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3289 }
3290 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3291 fmask_load_address[0],
3292 fmask_load_address[1],
3293 fmask_load_address[2],
3294 sample_index,
3295 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, true, false));
3296 }
3297 if (count == 1 && !gfx9_1d) {
3298 if (instr->src[0].ssa->num_components)
3299 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3300 else
3301 res = src0;
3302 } else {
3303 int chan;
3304 if (is_ms)
3305 count--;
3306 for (chan = 0; chan < count; ++chan) {
3307 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3308 }
3309 if (add_frag_pos) {
3310 for (chan = 0; chan < 2; ++chan)
3311 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3312 ctx->ac.i32, ""), "");
3313 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3314 count++;
3315 }
3316
3317 if (gfx9_1d) {
3318 if (is_array) {
3319 coords[2] = coords[1];
3320 coords[1] = ctx->ac.i32_0;
3321 } else
3322 coords[1] = ctx->ac.i32_0;
3323 count++;
3324 }
3325
3326 if (is_ms) {
3327 coords[count] = sample_index;
3328 count++;
3329 }
3330
3331 if (count == 3) {
3332 coords[3] = LLVMGetUndef(ctx->ac.i32);
3333 count = 4;
3334 }
3335 res = ac_build_gather_values(&ctx->ac, coords, count);
3336 }
3337 return res;
3338 }
3339
3340 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3341 const nir_intrinsic_instr *instr)
3342 {
3343 LLVMValueRef params[7];
3344 LLVMValueRef res;
3345 char intrinsic_name[64];
3346 const nir_variable *var = instr->variables[0]->var;
3347 const struct glsl_type *type = var->type;
3348 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3349 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3350
3351 if(instr->variables[0]->deref.child)
3352 type = instr->variables[0]->deref.child->type;
3353
3354 type = glsl_without_array(type);
3355 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3356 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, false);
3357 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3358 ctx->ac.i32_0, ""); /* vindex */
3359 params[2] = ctx->ac.i32_0; /* voffset */
3360 params[3] = i1false; /* glc */
3361 params[4] = i1false; /* slc */
3362 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3363 params, 5, 0);
3364
3365 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3366 res = ac_to_integer(&ctx->ac, res);
3367 } else {
3368 bool is_da = glsl_sampler_type_is_array(type) ||
3369 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3370 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3371 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3372 LLVMValueRef da = is_da ? i1true : i1false;
3373 LLVMValueRef glc = i1false;
3374 LLVMValueRef slc = i1false;
3375
3376 params[0] = get_image_coords(ctx, instr);
3377 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3378 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3379 if (HAVE_LLVM <= 0x0309) {
3380 params[3] = i1false; /* r128 */
3381 params[4] = da;
3382 params[5] = glc;
3383 params[6] = slc;
3384 } else {
3385 LLVMValueRef lwe = i1false;
3386 params[3] = glc;
3387 params[4] = slc;
3388 params[5] = lwe;
3389 params[6] = da;
3390 }
3391
3392 ac_get_image_intr_name("llvm.amdgcn.image.load",
3393 ctx->ac.v4f32, /* vdata */
3394 LLVMTypeOf(params[0]), /* coords */
3395 LLVMTypeOf(params[1]), /* rsrc */
3396 intrinsic_name, sizeof(intrinsic_name));
3397
3398 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3399 params, 7, AC_FUNC_ATTR_READONLY);
3400 }
3401 return ac_to_integer(&ctx->ac, res);
3402 }
3403
3404 static void visit_image_store(struct ac_nir_context *ctx,
3405 nir_intrinsic_instr *instr)
3406 {
3407 LLVMValueRef params[8];
3408 char intrinsic_name[64];
3409 const nir_variable *var = instr->variables[0]->var;
3410 const struct glsl_type *type = glsl_without_array(var->type);
3411 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3412 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3413 LLVMValueRef glc = i1false;
3414 bool force_glc = ctx->ac.chip_class == SI;
3415 if (force_glc)
3416 glc = i1true;
3417
3418 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3419 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3420 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, true);
3421 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3422 ctx->ac.i32_0, ""); /* vindex */
3423 params[3] = ctx->ac.i32_0; /* voffset */
3424 params[4] = glc; /* glc */
3425 params[5] = i1false; /* slc */
3426 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3427 params, 6, 0);
3428 } else {
3429 bool is_da = glsl_sampler_type_is_array(type) ||
3430 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3431 LLVMValueRef da = is_da ? i1true : i1false;
3432 LLVMValueRef slc = i1false;
3433
3434 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3435 params[1] = get_image_coords(ctx, instr); /* coords */
3436 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, true);
3437 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3438 if (HAVE_LLVM <= 0x0309) {
3439 params[4] = i1false; /* r128 */
3440 params[5] = da;
3441 params[6] = glc;
3442 params[7] = slc;
3443 } else {
3444 LLVMValueRef lwe = i1false;
3445 params[4] = glc;
3446 params[5] = slc;
3447 params[6] = lwe;
3448 params[7] = da;
3449 }
3450
3451 ac_get_image_intr_name("llvm.amdgcn.image.store",
3452 LLVMTypeOf(params[0]), /* vdata */
3453 LLVMTypeOf(params[1]), /* coords */
3454 LLVMTypeOf(params[2]), /* rsrc */
3455 intrinsic_name, sizeof(intrinsic_name));
3456
3457 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3458 params, 8, 0);
3459 }
3460
3461 }
3462
3463 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3464 const nir_intrinsic_instr *instr)
3465 {
3466 LLVMValueRef params[7];
3467 int param_count = 0;
3468 const nir_variable *var = instr->variables[0]->var;
3469
3470 const char *atomic_name;
3471 char intrinsic_name[41];
3472 const struct glsl_type *type = glsl_without_array(var->type);
3473 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3474 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3475 MAYBE_UNUSED int length;
3476
3477 switch (instr->intrinsic) {
3478 case nir_intrinsic_image_atomic_add:
3479 atomic_name = "add";
3480 break;
3481 case nir_intrinsic_image_atomic_min:
3482 atomic_name = "smin";
3483 break;
3484 case nir_intrinsic_image_atomic_max:
3485 atomic_name = "smax";
3486 break;
3487 case nir_intrinsic_image_atomic_and:
3488 atomic_name = "and";
3489 break;
3490 case nir_intrinsic_image_atomic_or:
3491 atomic_name = "or";
3492 break;
3493 case nir_intrinsic_image_atomic_xor:
3494 atomic_name = "xor";
3495 break;
3496 case nir_intrinsic_image_atomic_exchange:
3497 atomic_name = "swap";
3498 break;
3499 case nir_intrinsic_image_atomic_comp_swap:
3500 atomic_name = "cmpswap";
3501 break;
3502 default:
3503 abort();
3504 }
3505
3506 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3507 params[param_count++] = get_src(ctx, instr->src[3]);
3508 params[param_count++] = get_src(ctx, instr->src[2]);
3509
3510 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3511 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3512 true, true);
3513 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3514 ctx->ac.i32_0, ""); /* vindex */
3515 params[param_count++] = ctx->ac.i32_0; /* voffset */
3516 params[param_count++] = i1false; /* slc */
3517
3518 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3519 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3520 } else {
3521 char coords_type[8];
3522
3523 bool da = glsl_sampler_type_is_array(type) ||
3524 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3525
3526 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3527 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3528 true, true);
3529 params[param_count++] = i1false; /* r128 */
3530 params[param_count++] = da ? i1true : i1false; /* da */
3531 params[param_count++] = i1false; /* slc */
3532
3533 build_int_type_name(LLVMTypeOf(coords),
3534 coords_type, sizeof(coords_type));
3535
3536 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3537 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3538 }
3539
3540 assert(length < sizeof(intrinsic_name));
3541 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3542 }
3543
3544 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3545 const nir_intrinsic_instr *instr)
3546 {
3547 LLVMValueRef res;
3548 const nir_variable *var = instr->variables[0]->var;
3549 const struct glsl_type *type = instr->variables[0]->var->type;
3550 bool da = glsl_sampler_type_is_array(var->type) ||
3551 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3552 if(instr->variables[0]->deref.child)
3553 type = instr->variables[0]->deref.child->type;
3554
3555 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3556 return get_buffer_size(ctx,
3557 get_sampler_desc(ctx, instr->variables[0],
3558 AC_DESC_BUFFER, true, false), true);
3559
3560 struct ac_image_args args = { 0 };
3561
3562 args.da = da;
3563 args.dmask = 0xf;
3564 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3565 args.opcode = ac_image_get_resinfo;
3566 args.addr = ctx->ac.i32_0;
3567
3568 res = ac_build_image_opcode(&ctx->ac, &args);
3569
3570 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3571
3572 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3573 glsl_sampler_type_is_array(type)) {
3574 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3575 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3576 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3577 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3578 }
3579 if (ctx->ac.chip_class >= GFX9 &&
3580 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3581 glsl_sampler_type_is_array(type)) {
3582 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3583 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3584 ctx->ac.i32_1, "");
3585
3586 }
3587 return res;
3588 }
3589
3590 #define NOOP_WAITCNT 0xf7f
3591 #define LGKM_CNT 0x07f
3592 #define VM_CNT 0xf70
3593
3594 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3595 unsigned simm16)
3596 {
3597 LLVMValueRef args[1] = {
3598 LLVMConstInt(ctx->i32, simm16, false),
3599 };
3600 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3601 ctx->voidt, args, 1, 0);
3602 }
3603
3604 static void emit_barrier(struct nir_to_llvm_context *ctx)
3605 {
3606 /* SI only (thanks to a hw bug workaround):
3607 * The real barrier instruction isn’t needed, because an entire patch
3608 * always fits into a single wave.
3609 */
3610 if (ctx->options->chip_class == SI &&
3611 ctx->stage == MESA_SHADER_TESS_CTRL) {
3612 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3613 return;
3614 }
3615 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3616 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3617 }
3618
3619 static void emit_discard_if(struct ac_nir_context *ctx,
3620 const nir_intrinsic_instr *instr)
3621 {
3622 LLVMValueRef cond;
3623
3624 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
3625 get_src(ctx, instr->src[0]),
3626 ctx->ac.i32_0, "");
3627
3628 cond = LLVMBuildSelect(ctx->ac.builder, cond,
3629 LLVMConstReal(ctx->ac.f32, -1.0f),
3630 ctx->ac.f32_0, "");
3631 ac_build_kill(&ctx->ac, cond);
3632 }
3633
3634 static LLVMValueRef
3635 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3636 {
3637 LLVMValueRef result;
3638 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3639 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3640 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3641
3642 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3643 }
3644
3645 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3646 const nir_intrinsic_instr *instr)
3647 {
3648 LLVMValueRef ptr, result;
3649 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3650 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3651
3652 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3653 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3654 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3655 ptr, src, src1,
3656 LLVMAtomicOrderingSequentiallyConsistent,
3657 LLVMAtomicOrderingSequentiallyConsistent,
3658 false);
3659 } else {
3660 LLVMAtomicRMWBinOp op;
3661 switch (instr->intrinsic) {
3662 case nir_intrinsic_var_atomic_add:
3663 op = LLVMAtomicRMWBinOpAdd;
3664 break;
3665 case nir_intrinsic_var_atomic_umin:
3666 op = LLVMAtomicRMWBinOpUMin;
3667 break;
3668 case nir_intrinsic_var_atomic_umax:
3669 op = LLVMAtomicRMWBinOpUMax;
3670 break;
3671 case nir_intrinsic_var_atomic_imin:
3672 op = LLVMAtomicRMWBinOpMin;
3673 break;
3674 case nir_intrinsic_var_atomic_imax:
3675 op = LLVMAtomicRMWBinOpMax;
3676 break;
3677 case nir_intrinsic_var_atomic_and:
3678 op = LLVMAtomicRMWBinOpAnd;
3679 break;
3680 case nir_intrinsic_var_atomic_or:
3681 op = LLVMAtomicRMWBinOpOr;
3682 break;
3683 case nir_intrinsic_var_atomic_xor:
3684 op = LLVMAtomicRMWBinOpXor;
3685 break;
3686 case nir_intrinsic_var_atomic_exchange:
3687 op = LLVMAtomicRMWBinOpXchg;
3688 break;
3689 default:
3690 return NULL;
3691 }
3692
3693 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3694 LLVMAtomicOrderingSequentiallyConsistent,
3695 false);
3696 }
3697 return result;
3698 }
3699
3700 #define INTERP_CENTER 0
3701 #define INTERP_CENTROID 1
3702 #define INTERP_SAMPLE 2
3703
3704 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3705 enum glsl_interp_mode interp, unsigned location)
3706 {
3707 switch (interp) {
3708 case INTERP_MODE_FLAT:
3709 default:
3710 return NULL;
3711 case INTERP_MODE_SMOOTH:
3712 case INTERP_MODE_NONE:
3713 if (location == INTERP_CENTER)
3714 return ctx->persp_center;
3715 else if (location == INTERP_CENTROID)
3716 return ctx->persp_centroid;
3717 else if (location == INTERP_SAMPLE)
3718 return ctx->persp_sample;
3719 break;
3720 case INTERP_MODE_NOPERSPECTIVE:
3721 if (location == INTERP_CENTER)
3722 return ctx->linear_center;
3723 else if (location == INTERP_CENTROID)
3724 return ctx->linear_centroid;
3725 else if (location == INTERP_SAMPLE)
3726 return ctx->linear_sample;
3727 break;
3728 }
3729 return NULL;
3730 }
3731
3732 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3733 LLVMValueRef sample_id)
3734 {
3735 LLVMValueRef result;
3736 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3737
3738 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3739 const_array(ctx->v2f32, 64), "");
3740
3741 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3742 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3743
3744 return result;
3745 }
3746
3747 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3748 {
3749 LLVMValueRef values[2];
3750
3751 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3752 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3753 return ac_build_gather_values(&ctx->ac, values, 2);
3754 }
3755
3756 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3757 const nir_intrinsic_instr *instr)
3758 {
3759 LLVMValueRef result[2];
3760 LLVMValueRef interp_param, attr_number;
3761 unsigned location;
3762 unsigned chan;
3763 LLVMValueRef src_c0 = NULL;
3764 LLVMValueRef src_c1 = NULL;
3765 LLVMValueRef src0 = NULL;
3766 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3767 switch (instr->intrinsic) {
3768 case nir_intrinsic_interp_var_at_centroid:
3769 location = INTERP_CENTROID;
3770 break;
3771 case nir_intrinsic_interp_var_at_sample:
3772 case nir_intrinsic_interp_var_at_offset:
3773 location = INTERP_CENTER;
3774 src0 = get_src(ctx->nir, instr->src[0]);
3775 break;
3776 default:
3777 break;
3778 }
3779
3780 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3781 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3782 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3783 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3784 LLVMValueRef sample_position;
3785 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3786
3787 /* fetch sample ID */
3788 sample_position = load_sample_position(ctx, src0);
3789
3790 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3791 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3792 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3793 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3794 }
3795 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3796 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3797
3798 if (location == INTERP_CENTER) {
3799 LLVMValueRef ij_out[2];
3800 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3801
3802 /*
3803 * take the I then J parameters, and the DDX/Y for it, and
3804 * calculate the IJ inputs for the interpolator.
3805 * temp1 = ddx * offset/sample.x + I;
3806 * interp_param.I = ddy * offset/sample.y + temp1;
3807 * temp1 = ddx * offset/sample.x + J;
3808 * interp_param.J = ddy * offset/sample.y + temp1;
3809 */
3810 for (unsigned i = 0; i < 2; i++) {
3811 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3812 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3813 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3814 ddxy_out, ix_ll, "");
3815 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3816 ddxy_out, iy_ll, "");
3817 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3818 interp_param, ix_ll, "");
3819 LLVMValueRef temp1, temp2;
3820
3821 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3822 ctx->f32, "");
3823
3824 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3825 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3826
3827 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3828 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3829
3830 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3831 temp2, ctx->i32, "");
3832 }
3833 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3834
3835 }
3836
3837 for (chan = 0; chan < 2; chan++) {
3838 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3839
3840 if (interp_param) {
3841 interp_param = LLVMBuildBitCast(ctx->builder,
3842 interp_param, LLVMVectorType(ctx->f32, 2), "");
3843 LLVMValueRef i = LLVMBuildExtractElement(
3844 ctx->builder, interp_param, ctx->i32zero, "");
3845 LLVMValueRef j = LLVMBuildExtractElement(
3846 ctx->builder, interp_param, ctx->i32one, "");
3847
3848 result[chan] = ac_build_fs_interp(&ctx->ac,
3849 llvm_chan, attr_number,
3850 ctx->prim_mask, i, j);
3851 } else {
3852 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3853 LLVMConstInt(ctx->i32, 2, false),
3854 llvm_chan, attr_number,
3855 ctx->prim_mask);
3856 }
3857 }
3858 return ac_build_gather_values(&ctx->ac, result, 2);
3859 }
3860
3861 static void
3862 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3863 const nir_intrinsic_instr *instr)
3864 {
3865 LLVMValueRef gs_next_vertex;
3866 LLVMValueRef can_emit, kill;
3867 int idx;
3868
3869 assert(instr->const_index[0] == 0);
3870 /* Write vertex attribute values to GSVS ring */
3871 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3872 ctx->gs_next_vertex,
3873 "");
3874
3875 /* If this thread has already emitted the declared maximum number of
3876 * vertices, kill it: excessive vertex emissions are not supposed to
3877 * have any effect, and GS threads have no externally observable
3878 * effects other than emitting vertices.
3879 */
3880 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3881 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3882
3883 kill = LLVMBuildSelect(ctx->builder, can_emit,
3884 LLVMConstReal(ctx->f32, 1.0f),
3885 LLVMConstReal(ctx->f32, -1.0f), "");
3886 ac_build_kill(&ctx->ac, kill);
3887
3888 /* loop num outputs */
3889 idx = 0;
3890 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3891 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
3892 int length = 4;
3893 int slot = idx;
3894 int slot_inc = 1;
3895
3896 if (!(ctx->output_mask & (1ull << i)))
3897 continue;
3898
3899 if (i == VARYING_SLOT_CLIP_DIST0) {
3900 /* pack clip and cull into a single set of slots */
3901 length = ctx->num_output_clips + ctx->num_output_culls;
3902 if (length > 4)
3903 slot_inc = 2;
3904 }
3905 for (unsigned j = 0; j < length; j++) {
3906 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3907 out_ptr[j], "");
3908 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3909 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3910 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3911
3912 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3913
3914 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3915 out_val, 1,
3916 voffset, ctx->gs2vs_offset, 0,
3917 1, 1, true, true);
3918 }
3919 idx += slot_inc;
3920 }
3921
3922 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3923 ctx->i32one, "");
3924 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3925
3926 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3927 }
3928
3929 static void
3930 visit_end_primitive(struct nir_to_llvm_context *ctx,
3931 const nir_intrinsic_instr *instr)
3932 {
3933 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3934 }
3935
3936 static LLVMValueRef
3937 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3938 const nir_intrinsic_instr *instr)
3939 {
3940 LLVMValueRef coord[4] = {
3941 ctx->tes_u,
3942 ctx->tes_v,
3943 ctx->f32zero,
3944 ctx->f32zero,
3945 };
3946
3947 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3948 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3949 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3950
3951 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3952 return LLVMBuildBitCast(ctx->builder, result,
3953 get_def_type(ctx->nir, &instr->dest.ssa), "");
3954 }
3955
3956 static void visit_intrinsic(struct ac_nir_context *ctx,
3957 nir_intrinsic_instr *instr)
3958 {
3959 LLVMValueRef result = NULL;
3960
3961 switch (instr->intrinsic) {
3962 case nir_intrinsic_load_work_group_id: {
3963 result = ctx->nctx->workgroup_ids;
3964 break;
3965 }
3966 case nir_intrinsic_load_base_vertex: {
3967 result = ctx->abi->base_vertex;
3968 break;
3969 }
3970 case nir_intrinsic_load_vertex_id_zero_base: {
3971 result = ctx->abi->vertex_id;
3972 break;
3973 }
3974 case nir_intrinsic_load_local_invocation_id: {
3975 result = ctx->nctx->local_invocation_ids;
3976 break;
3977 }
3978 case nir_intrinsic_load_base_instance:
3979 result = ctx->abi->start_instance;
3980 break;
3981 case nir_intrinsic_load_draw_id:
3982 result = ctx->abi->draw_id;
3983 break;
3984 case nir_intrinsic_load_view_index:
3985 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
3986 break;
3987 case nir_intrinsic_load_invocation_id:
3988 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3989 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
3990 else
3991 result = ctx->nctx->gs_invocation_id;
3992 break;
3993 case nir_intrinsic_load_primitive_id:
3994 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3995 ctx->nctx->shader_info->gs.uses_prim_id = true;
3996 result = ctx->nctx->gs_prim_id;
3997 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3998 ctx->nctx->shader_info->tcs.uses_prim_id = true;
3999 result = ctx->nctx->tcs_patch_id;
4000 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4001 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4002 result = ctx->nctx->tes_patch_id;
4003 } else
4004 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4005 break;
4006 case nir_intrinsic_load_sample_id:
4007 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4008 break;
4009 case nir_intrinsic_load_sample_pos:
4010 result = load_sample_pos(ctx);
4011 break;
4012 case nir_intrinsic_load_sample_mask_in:
4013 result = ctx->abi->sample_coverage;
4014 break;
4015 case nir_intrinsic_load_frag_coord: {
4016 LLVMValueRef values[4] = {
4017 ctx->abi->frag_pos[0],
4018 ctx->abi->frag_pos[1],
4019 ctx->abi->frag_pos[2],
4020 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4021 };
4022 result = ac_build_gather_values(&ctx->ac, values, 4);
4023 break;
4024 }
4025 case nir_intrinsic_load_front_face:
4026 result = ctx->abi->front_face;
4027 break;
4028 case nir_intrinsic_load_instance_id:
4029 result = ctx->abi->instance_id;
4030 break;
4031 case nir_intrinsic_load_num_work_groups:
4032 result = ctx->nctx->num_work_groups;
4033 break;
4034 case nir_intrinsic_load_local_invocation_index:
4035 result = visit_load_local_invocation_index(ctx->nctx);
4036 break;
4037 case nir_intrinsic_load_push_constant:
4038 result = visit_load_push_constant(ctx->nctx, instr);
4039 break;
4040 case nir_intrinsic_vulkan_resource_index:
4041 result = visit_vulkan_resource_index(ctx->nctx, instr);
4042 break;
4043 case nir_intrinsic_store_ssbo:
4044 visit_store_ssbo(ctx, instr);
4045 break;
4046 case nir_intrinsic_load_ssbo:
4047 result = visit_load_buffer(ctx, instr);
4048 break;
4049 case nir_intrinsic_ssbo_atomic_add:
4050 case nir_intrinsic_ssbo_atomic_imin:
4051 case nir_intrinsic_ssbo_atomic_umin:
4052 case nir_intrinsic_ssbo_atomic_imax:
4053 case nir_intrinsic_ssbo_atomic_umax:
4054 case nir_intrinsic_ssbo_atomic_and:
4055 case nir_intrinsic_ssbo_atomic_or:
4056 case nir_intrinsic_ssbo_atomic_xor:
4057 case nir_intrinsic_ssbo_atomic_exchange:
4058 case nir_intrinsic_ssbo_atomic_comp_swap:
4059 result = visit_atomic_ssbo(ctx, instr);
4060 break;
4061 case nir_intrinsic_load_ubo:
4062 result = visit_load_ubo_buffer(ctx, instr);
4063 break;
4064 case nir_intrinsic_get_buffer_size:
4065 result = visit_get_buffer_size(ctx, instr);
4066 break;
4067 case nir_intrinsic_load_var:
4068 result = visit_load_var(ctx, instr);
4069 break;
4070 case nir_intrinsic_store_var:
4071 visit_store_var(ctx, instr);
4072 break;
4073 case nir_intrinsic_image_load:
4074 result = visit_image_load(ctx, instr);
4075 break;
4076 case nir_intrinsic_image_store:
4077 visit_image_store(ctx, instr);
4078 break;
4079 case nir_intrinsic_image_atomic_add:
4080 case nir_intrinsic_image_atomic_min:
4081 case nir_intrinsic_image_atomic_max:
4082 case nir_intrinsic_image_atomic_and:
4083 case nir_intrinsic_image_atomic_or:
4084 case nir_intrinsic_image_atomic_xor:
4085 case nir_intrinsic_image_atomic_exchange:
4086 case nir_intrinsic_image_atomic_comp_swap:
4087 result = visit_image_atomic(ctx, instr);
4088 break;
4089 case nir_intrinsic_image_size:
4090 result = visit_image_size(ctx, instr);
4091 break;
4092 case nir_intrinsic_discard:
4093 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4094 LLVMVoidTypeInContext(ctx->ac.context),
4095 NULL, 0, AC_FUNC_ATTR_LEGACY);
4096 break;
4097 case nir_intrinsic_discard_if:
4098 emit_discard_if(ctx, instr);
4099 break;
4100 case nir_intrinsic_memory_barrier:
4101 emit_waitcnt(ctx->nctx, VM_CNT);
4102 break;
4103 case nir_intrinsic_barrier:
4104 emit_barrier(ctx->nctx);
4105 break;
4106 case nir_intrinsic_var_atomic_add:
4107 case nir_intrinsic_var_atomic_imin:
4108 case nir_intrinsic_var_atomic_umin:
4109 case nir_intrinsic_var_atomic_imax:
4110 case nir_intrinsic_var_atomic_umax:
4111 case nir_intrinsic_var_atomic_and:
4112 case nir_intrinsic_var_atomic_or:
4113 case nir_intrinsic_var_atomic_xor:
4114 case nir_intrinsic_var_atomic_exchange:
4115 case nir_intrinsic_var_atomic_comp_swap:
4116 result = visit_var_atomic(ctx->nctx, instr);
4117 break;
4118 case nir_intrinsic_interp_var_at_centroid:
4119 case nir_intrinsic_interp_var_at_sample:
4120 case nir_intrinsic_interp_var_at_offset:
4121 result = visit_interp(ctx->nctx, instr);
4122 break;
4123 case nir_intrinsic_emit_vertex:
4124 visit_emit_vertex(ctx->nctx, instr);
4125 break;
4126 case nir_intrinsic_end_primitive:
4127 visit_end_primitive(ctx->nctx, instr);
4128 break;
4129 case nir_intrinsic_load_tess_coord:
4130 result = visit_load_tess_coord(ctx->nctx, instr);
4131 break;
4132 case nir_intrinsic_load_patch_vertices_in:
4133 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4134 break;
4135 default:
4136 fprintf(stderr, "Unknown intrinsic: ");
4137 nir_print_instr(&instr->instr, stderr);
4138 fprintf(stderr, "\n");
4139 break;
4140 }
4141 if (result) {
4142 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4143 }
4144 }
4145
4146 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4147 LLVMValueRef buffer, bool write)
4148 {
4149 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4150
4151 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4152 ctx->shader_info->fs.writes_memory = true;
4153
4154 return buffer;
4155 }
4156
4157 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4158 unsigned descriptor_set,
4159 unsigned base_index,
4160 unsigned constant_index,
4161 LLVMValueRef index,
4162 enum ac_descriptor_type desc_type,
4163 bool image, bool write)
4164 {
4165 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4166 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4167 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4168 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4169 unsigned offset = binding->offset;
4170 unsigned stride = binding->size;
4171 unsigned type_size;
4172 LLVMBuilderRef builder = ctx->builder;
4173 LLVMTypeRef type;
4174
4175 assert(base_index < layout->binding_count);
4176
4177 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4178 ctx->shader_info->fs.writes_memory = true;
4179
4180 switch (desc_type) {
4181 case AC_DESC_IMAGE:
4182 type = ctx->v8i32;
4183 type_size = 32;
4184 break;
4185 case AC_DESC_FMASK:
4186 type = ctx->v8i32;
4187 offset += 32;
4188 type_size = 32;
4189 break;
4190 case AC_DESC_SAMPLER:
4191 type = ctx->v4i32;
4192 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4193 offset += 64;
4194
4195 type_size = 16;
4196 break;
4197 case AC_DESC_BUFFER:
4198 type = ctx->v4i32;
4199 type_size = 16;
4200 break;
4201 default:
4202 unreachable("invalid desc_type\n");
4203 }
4204
4205 offset += constant_index * stride;
4206
4207 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4208 (!index || binding->immutable_samplers_equal)) {
4209 if (binding->immutable_samplers_equal)
4210 constant_index = 0;
4211
4212 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4213
4214 LLVMValueRef constants[] = {
4215 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4216 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4217 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4218 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4219 };
4220 return ac_build_gather_values(&ctx->ac, constants, 4);
4221 }
4222
4223 assert(stride % type_size == 0);
4224
4225 if (!index)
4226 index = ctx->i32zero;
4227
4228 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4229
4230 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4231 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4232
4233 return ac_build_indexed_load_const(&ctx->ac, list, index);
4234 }
4235
4236 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4237 const nir_deref_var *deref,
4238 enum ac_descriptor_type desc_type,
4239 bool image, bool write)
4240 {
4241 LLVMValueRef index = NULL;
4242 unsigned constant_index = 0;
4243 const nir_deref *tail = &deref->deref;
4244
4245 while (tail->child) {
4246 const nir_deref_array *child = nir_deref_as_array(tail->child);
4247 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4248
4249 if (!array_size)
4250 array_size = 1;
4251
4252 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4253
4254 if (child->deref_array_type == nir_deref_array_type_indirect) {
4255 LLVMValueRef indirect = get_src(ctx, child->indirect);
4256
4257 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4258 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4259
4260 if (!index)
4261 index = indirect;
4262 else
4263 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4264 }
4265
4266 constant_index += child->base_offset * array_size;
4267
4268 tail = &child->deref;
4269 }
4270
4271 return ctx->abi->load_sampler_desc(ctx->abi,
4272 deref->var->data.descriptor_set,
4273 deref->var->data.binding,
4274 constant_index, index,
4275 desc_type, image, write);
4276 }
4277
4278 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4279 struct ac_image_args *args,
4280 const nir_tex_instr *instr,
4281 nir_texop op,
4282 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4283 LLVMValueRef *param, unsigned count,
4284 unsigned dmask)
4285 {
4286 unsigned is_rect = 0;
4287 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4288
4289 if (op == nir_texop_lod)
4290 da = false;
4291 /* Pad to power of two vector */
4292 while (count < util_next_power_of_two(count))
4293 param[count++] = LLVMGetUndef(ctx->i32);
4294
4295 if (count > 1)
4296 args->addr = ac_build_gather_values(ctx, param, count);
4297 else
4298 args->addr = param[0];
4299
4300 args->resource = res_ptr;
4301 args->sampler = samp_ptr;
4302
4303 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4304 args->addr = param[0];
4305 return;
4306 }
4307
4308 args->dmask = dmask;
4309 args->unorm = is_rect;
4310 args->da = da;
4311 }
4312
4313 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4314 *
4315 * SI-CI:
4316 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4317 * filtering manually. The driver sets img7 to a mask clearing
4318 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4319 * s_and_b32 samp0, samp0, img7
4320 *
4321 * VI:
4322 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4323 */
4324 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4325 LLVMValueRef res, LLVMValueRef samp)
4326 {
4327 LLVMBuilderRef builder = ctx->ac.builder;
4328 LLVMValueRef img7, samp0;
4329
4330 if (ctx->ac.chip_class >= VI)
4331 return samp;
4332
4333 img7 = LLVMBuildExtractElement(builder, res,
4334 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4335 samp0 = LLVMBuildExtractElement(builder, samp,
4336 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4337 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4338 return LLVMBuildInsertElement(builder, samp, samp0,
4339 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4340 }
4341
4342 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4343 nir_tex_instr *instr,
4344 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4345 LLVMValueRef *fmask_ptr)
4346 {
4347 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4348 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, false, false);
4349 else
4350 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, false, false);
4351 if (samp_ptr) {
4352 if (instr->sampler)
4353 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, false, false);
4354 else
4355 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, false, false);
4356 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4357 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4358 }
4359 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4360 instr->op == nir_texop_samples_identical))
4361 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, false, false);
4362 }
4363
4364 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4365 LLVMValueRef coord)
4366 {
4367 coord = ac_to_float(ctx, coord);
4368 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4369 coord = ac_to_integer(ctx, coord);
4370 return coord;
4371 }
4372
4373 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4374 {
4375 LLVMValueRef result = NULL;
4376 struct ac_image_args args = { 0 };
4377 unsigned dmask = 0xf;
4378 LLVMValueRef address[16];
4379 LLVMValueRef coords[5];
4380 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4381 LLVMValueRef bias = NULL, offsets = NULL;
4382 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4383 LLVMValueRef ddx = NULL, ddy = NULL;
4384 LLVMValueRef derivs[6];
4385 unsigned chan, count = 0;
4386 unsigned const_src = 0, num_deriv_comp = 0;
4387 bool lod_is_zero = false;
4388
4389 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4390
4391 for (unsigned i = 0; i < instr->num_srcs; i++) {
4392 switch (instr->src[i].src_type) {
4393 case nir_tex_src_coord:
4394 coord = get_src(ctx, instr->src[i].src);
4395 break;
4396 case nir_tex_src_projector:
4397 break;
4398 case nir_tex_src_comparator:
4399 comparator = get_src(ctx, instr->src[i].src);
4400 break;
4401 case nir_tex_src_offset:
4402 offsets = get_src(ctx, instr->src[i].src);
4403 const_src = i;
4404 break;
4405 case nir_tex_src_bias:
4406 bias = get_src(ctx, instr->src[i].src);
4407 break;
4408 case nir_tex_src_lod: {
4409 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4410
4411 if (val && val->i32[0] == 0)
4412 lod_is_zero = true;
4413 lod = get_src(ctx, instr->src[i].src);
4414 break;
4415 }
4416 case nir_tex_src_ms_index:
4417 sample_index = get_src(ctx, instr->src[i].src);
4418 break;
4419 case nir_tex_src_ms_mcs:
4420 break;
4421 case nir_tex_src_ddx:
4422 ddx = get_src(ctx, instr->src[i].src);
4423 num_deriv_comp = instr->src[i].src.ssa->num_components;
4424 break;
4425 case nir_tex_src_ddy:
4426 ddy = get_src(ctx, instr->src[i].src);
4427 break;
4428 case nir_tex_src_texture_offset:
4429 case nir_tex_src_sampler_offset:
4430 case nir_tex_src_plane:
4431 default:
4432 break;
4433 }
4434 }
4435
4436 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4437 result = get_buffer_size(ctx, res_ptr, true);
4438 goto write_result;
4439 }
4440
4441 if (instr->op == nir_texop_texture_samples) {
4442 LLVMValueRef res, samples, is_msaa;
4443 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4444 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4445 LLVMConstInt(ctx->ac.i32, 3, false), "");
4446 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4447 LLVMConstInt(ctx->ac.i32, 28, false), "");
4448 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4449 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4450 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4451 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4452
4453 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4454 LLVMConstInt(ctx->ac.i32, 16, false), "");
4455 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4456 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4457 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4458 samples, "");
4459 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4460 ctx->ac.i32_1, "");
4461 result = samples;
4462 goto write_result;
4463 }
4464
4465 if (coord)
4466 for (chan = 0; chan < instr->coord_components; chan++)
4467 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4468
4469 if (offsets && instr->op != nir_texop_txf) {
4470 LLVMValueRef offset[3], pack;
4471 for (chan = 0; chan < 3; ++chan)
4472 offset[chan] = ctx->ac.i32_0;
4473
4474 args.offset = true;
4475 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4476 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4477 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4478 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4479 if (chan)
4480 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4481 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4482 }
4483 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4484 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4485 address[count++] = pack;
4486
4487 }
4488 /* pack LOD bias value */
4489 if (instr->op == nir_texop_txb && bias) {
4490 address[count++] = bias;
4491 }
4492
4493 /* Pack depth comparison value */
4494 if (instr->is_shadow && comparator) {
4495 LLVMValueRef z = ac_to_float(&ctx->ac,
4496 llvm_extract_elem(&ctx->ac, comparator, 0));
4497
4498 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4499 * so the depth comparison value isn't clamped for Z16 and
4500 * Z24 anymore. Do it manually here.
4501 *
4502 * It's unnecessary if the original texture format was
4503 * Z32_FLOAT, but we don't know that here.
4504 */
4505 if (ctx->ac.chip_class == VI)
4506 z = ac_build_clamp(&ctx->ac, z);
4507
4508 address[count++] = z;
4509 }
4510
4511 /* pack derivatives */
4512 if (ddx || ddy) {
4513 int num_src_deriv_channels, num_dest_deriv_channels;
4514 switch (instr->sampler_dim) {
4515 case GLSL_SAMPLER_DIM_3D:
4516 case GLSL_SAMPLER_DIM_CUBE:
4517 num_deriv_comp = 3;
4518 num_src_deriv_channels = 3;
4519 num_dest_deriv_channels = 3;
4520 break;
4521 case GLSL_SAMPLER_DIM_2D:
4522 default:
4523 num_src_deriv_channels = 2;
4524 num_dest_deriv_channels = 2;
4525 num_deriv_comp = 2;
4526 break;
4527 case GLSL_SAMPLER_DIM_1D:
4528 num_src_deriv_channels = 1;
4529 if (ctx->ac.chip_class >= GFX9) {
4530 num_dest_deriv_channels = 2;
4531 num_deriv_comp = 2;
4532 } else {
4533 num_dest_deriv_channels = 1;
4534 num_deriv_comp = 1;
4535 }
4536 break;
4537 }
4538
4539 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4540 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4541 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4542 }
4543 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4544 derivs[i] = ctx->ac.f32_0;
4545 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4546 }
4547 }
4548
4549 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4550 for (chan = 0; chan < instr->coord_components; chan++)
4551 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4552 if (instr->coord_components == 3)
4553 coords[3] = LLVMGetUndef(ctx->ac.f32);
4554 ac_prepare_cube_coords(&ctx->ac,
4555 instr->op == nir_texop_txd, instr->is_array,
4556 instr->op == nir_texop_lod, coords, derivs);
4557 if (num_deriv_comp)
4558 num_deriv_comp--;
4559 }
4560
4561 if (ddx || ddy) {
4562 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4563 address[count++] = derivs[i];
4564 }
4565
4566 /* Pack texture coordinates */
4567 if (coord) {
4568 address[count++] = coords[0];
4569 if (instr->coord_components > 1) {
4570 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4571 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4572 }
4573 address[count++] = coords[1];
4574 }
4575 if (instr->coord_components > 2) {
4576 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4577 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4578 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4579 instr->op != nir_texop_txf) {
4580 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4581 }
4582 address[count++] = coords[2];
4583 }
4584
4585 if (ctx->ac.chip_class >= GFX9) {
4586 LLVMValueRef filler;
4587 if (instr->op == nir_texop_txf)
4588 filler = ctx->ac.i32_0;
4589 else
4590 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4591
4592 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4593 if (instr->is_array) {
4594 address[count] = address[count - 1];
4595 address[count - 1] = filler;
4596 count++;
4597 } else
4598 address[count++] = filler;
4599 }
4600 }
4601 }
4602
4603 /* Pack LOD */
4604 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4605 instr->op == nir_texop_txf)) {
4606 address[count++] = lod;
4607 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4608 address[count++] = sample_index;
4609 } else if(instr->op == nir_texop_txs) {
4610 count = 0;
4611 if (lod)
4612 address[count++] = lod;
4613 else
4614 address[count++] = ctx->ac.i32_0;
4615 }
4616
4617 for (chan = 0; chan < count; chan++) {
4618 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4619 address[chan], ctx->ac.i32, "");
4620 }
4621
4622 if (instr->op == nir_texop_samples_identical) {
4623 LLVMValueRef txf_address[4];
4624 struct ac_image_args txf_args = { 0 };
4625 unsigned txf_count = count;
4626 memcpy(txf_address, address, sizeof(txf_address));
4627
4628 if (!instr->is_array)
4629 txf_address[2] = ctx->ac.i32_0;
4630 txf_address[3] = ctx->ac.i32_0;
4631
4632 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4633 fmask_ptr, NULL,
4634 txf_address, txf_count, 0xf);
4635
4636 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4637
4638 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4639 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4640 goto write_result;
4641 }
4642
4643 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4644 instr->op != nir_texop_txs) {
4645 unsigned sample_chan = instr->is_array ? 3 : 2;
4646 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4647 address[0],
4648 address[1],
4649 instr->is_array ? address[2] : NULL,
4650 address[sample_chan],
4651 fmask_ptr);
4652 }
4653
4654 if (offsets && instr->op == nir_texop_txf) {
4655 nir_const_value *const_offset =
4656 nir_src_as_const_value(instr->src[const_src].src);
4657 int num_offsets = instr->src[const_src].src.ssa->num_components;
4658 assert(const_offset);
4659 num_offsets = MIN2(num_offsets, instr->coord_components);
4660 if (num_offsets > 2)
4661 address[2] = LLVMBuildAdd(ctx->ac.builder,
4662 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4663 if (num_offsets > 1)
4664 address[1] = LLVMBuildAdd(ctx->ac.builder,
4665 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4666 address[0] = LLVMBuildAdd(ctx->ac.builder,
4667 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4668
4669 }
4670
4671 /* TODO TG4 support */
4672 if (instr->op == nir_texop_tg4) {
4673 if (instr->is_shadow)
4674 dmask = 1;
4675 else
4676 dmask = 1 << instr->component;
4677 }
4678 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4679 res_ptr, samp_ptr, address, count, dmask);
4680
4681 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4682
4683 if (instr->op == nir_texop_query_levels)
4684 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4685 else if (instr->is_shadow && instr->is_new_style_shadow &&
4686 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4687 instr->op != nir_texop_tg4)
4688 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4689 else if (instr->op == nir_texop_txs &&
4690 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4691 instr->is_array) {
4692 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4693 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4694 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4695 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4696 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4697 } else if (ctx->ac.chip_class >= GFX9 &&
4698 instr->op == nir_texop_txs &&
4699 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4700 instr->is_array) {
4701 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4702 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4703 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4704 ctx->ac.i32_1, "");
4705 } else if (instr->dest.ssa.num_components != 4)
4706 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4707
4708 write_result:
4709 if (result) {
4710 assert(instr->dest.is_ssa);
4711 result = ac_to_integer(&ctx->ac, result);
4712 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4713 }
4714 }
4715
4716
4717 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4718 {
4719 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4720 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4721
4722 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4723 _mesa_hash_table_insert(ctx->phis, instr, result);
4724 }
4725
4726 static void visit_post_phi(struct ac_nir_context *ctx,
4727 nir_phi_instr *instr,
4728 LLVMValueRef llvm_phi)
4729 {
4730 nir_foreach_phi_src(src, instr) {
4731 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4732 LLVMValueRef llvm_src = get_src(ctx, src->src);
4733
4734 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4735 }
4736 }
4737
4738 static void phi_post_pass(struct ac_nir_context *ctx)
4739 {
4740 struct hash_entry *entry;
4741 hash_table_foreach(ctx->phis, entry) {
4742 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4743 (LLVMValueRef)entry->data);
4744 }
4745 }
4746
4747
4748 static void visit_ssa_undef(struct ac_nir_context *ctx,
4749 const nir_ssa_undef_instr *instr)
4750 {
4751 unsigned num_components = instr->def.num_components;
4752 LLVMValueRef undef;
4753
4754 if (num_components == 1)
4755 undef = LLVMGetUndef(ctx->ac.i32);
4756 else {
4757 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4758 }
4759 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4760 }
4761
4762 static void visit_jump(struct ac_nir_context *ctx,
4763 const nir_jump_instr *instr)
4764 {
4765 switch (instr->type) {
4766 case nir_jump_break:
4767 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4768 LLVMClearInsertionPosition(ctx->ac.builder);
4769 break;
4770 case nir_jump_continue:
4771 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4772 LLVMClearInsertionPosition(ctx->ac.builder);
4773 break;
4774 default:
4775 fprintf(stderr, "Unknown NIR jump instr: ");
4776 nir_print_instr(&instr->instr, stderr);
4777 fprintf(stderr, "\n");
4778 abort();
4779 }
4780 }
4781
4782 static void visit_cf_list(struct ac_nir_context *ctx,
4783 struct exec_list *list);
4784
4785 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4786 {
4787 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4788 nir_foreach_instr(instr, block)
4789 {
4790 switch (instr->type) {
4791 case nir_instr_type_alu:
4792 visit_alu(ctx, nir_instr_as_alu(instr));
4793 break;
4794 case nir_instr_type_load_const:
4795 visit_load_const(ctx, nir_instr_as_load_const(instr));
4796 break;
4797 case nir_instr_type_intrinsic:
4798 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4799 break;
4800 case nir_instr_type_tex:
4801 visit_tex(ctx, nir_instr_as_tex(instr));
4802 break;
4803 case nir_instr_type_phi:
4804 visit_phi(ctx, nir_instr_as_phi(instr));
4805 break;
4806 case nir_instr_type_ssa_undef:
4807 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4808 break;
4809 case nir_instr_type_jump:
4810 visit_jump(ctx, nir_instr_as_jump(instr));
4811 break;
4812 default:
4813 fprintf(stderr, "Unknown NIR instr type: ");
4814 nir_print_instr(instr, stderr);
4815 fprintf(stderr, "\n");
4816 abort();
4817 }
4818 }
4819
4820 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4821 }
4822
4823 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4824 {
4825 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4826
4827 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4828 LLVMBasicBlockRef merge_block =
4829 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4830 LLVMBasicBlockRef if_block =
4831 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4832 LLVMBasicBlockRef else_block = merge_block;
4833 if (!exec_list_is_empty(&if_stmt->else_list))
4834 else_block = LLVMAppendBasicBlockInContext(
4835 ctx->ac.context, fn, "");
4836
4837 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4838 LLVMConstInt(ctx->ac.i32, 0, false), "");
4839 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4840
4841 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4842 visit_cf_list(ctx, &if_stmt->then_list);
4843 if (LLVMGetInsertBlock(ctx->ac.builder))
4844 LLVMBuildBr(ctx->ac.builder, merge_block);
4845
4846 if (!exec_list_is_empty(&if_stmt->else_list)) {
4847 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4848 visit_cf_list(ctx, &if_stmt->else_list);
4849 if (LLVMGetInsertBlock(ctx->ac.builder))
4850 LLVMBuildBr(ctx->ac.builder, merge_block);
4851 }
4852
4853 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4854 }
4855
4856 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4857 {
4858 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4859 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4860 LLVMBasicBlockRef break_parent = ctx->break_block;
4861
4862 ctx->continue_block =
4863 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4864 ctx->break_block =
4865 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4866
4867 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4868 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4869 visit_cf_list(ctx, &loop->body);
4870
4871 if (LLVMGetInsertBlock(ctx->ac.builder))
4872 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4873 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4874
4875 ctx->continue_block = continue_parent;
4876 ctx->break_block = break_parent;
4877 }
4878
4879 static void visit_cf_list(struct ac_nir_context *ctx,
4880 struct exec_list *list)
4881 {
4882 foreach_list_typed(nir_cf_node, node, node, list)
4883 {
4884 switch (node->type) {
4885 case nir_cf_node_block:
4886 visit_block(ctx, nir_cf_node_as_block(node));
4887 break;
4888
4889 case nir_cf_node_if:
4890 visit_if(ctx, nir_cf_node_as_if(node));
4891 break;
4892
4893 case nir_cf_node_loop:
4894 visit_loop(ctx, nir_cf_node_as_loop(node));
4895 break;
4896
4897 default:
4898 assert(0);
4899 }
4900 }
4901 }
4902
4903 static void
4904 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4905 struct nir_variable *variable)
4906 {
4907 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4908 LLVMValueRef t_offset;
4909 LLVMValueRef t_list;
4910 LLVMValueRef input;
4911 LLVMValueRef buffer_index;
4912 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4913 int idx = variable->data.location;
4914 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4915
4916 variable->data.driver_location = idx * 4;
4917
4918 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4919 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
4920 ctx->abi.start_instance, "");
4921 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4922 ctx->shader_info->vs.vgpr_comp_cnt);
4923 } else
4924 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
4925 ctx->abi.base_vertex, "");
4926
4927 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4928 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4929
4930 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4931
4932 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4933 buffer_index,
4934 LLVMConstInt(ctx->i32, 0, false),
4935 true);
4936
4937 for (unsigned chan = 0; chan < 4; chan++) {
4938 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4939 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4940 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
4941 input, llvm_chan, ""));
4942 }
4943 }
4944 }
4945
4946 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4947 unsigned attr,
4948 LLVMValueRef interp_param,
4949 LLVMValueRef prim_mask,
4950 LLVMValueRef result[4])
4951 {
4952 LLVMValueRef attr_number;
4953 unsigned chan;
4954 LLVMValueRef i, j;
4955 bool interp = interp_param != NULL;
4956
4957 attr_number = LLVMConstInt(ctx->i32, attr, false);
4958
4959 /* fs.constant returns the param from the middle vertex, so it's not
4960 * really useful for flat shading. It's meant to be used for custom
4961 * interpolation (but the intrinsic can't fetch from the other two
4962 * vertices).
4963 *
4964 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4965 * to do the right thing. The only reason we use fs.constant is that
4966 * fs.interp cannot be used on integers, because they can be equal
4967 * to NaN.
4968 */
4969 if (interp) {
4970 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4971 LLVMVectorType(ctx->f32, 2), "");
4972
4973 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4974 ctx->i32zero, "");
4975 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4976 ctx->i32one, "");
4977 }
4978
4979 for (chan = 0; chan < 4; chan++) {
4980 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4981
4982 if (interp) {
4983 result[chan] = ac_build_fs_interp(&ctx->ac,
4984 llvm_chan,
4985 attr_number,
4986 prim_mask, i, j);
4987 } else {
4988 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4989 LLVMConstInt(ctx->i32, 2, false),
4990 llvm_chan,
4991 attr_number,
4992 prim_mask);
4993 }
4994 }
4995 }
4996
4997 static void
4998 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4999 struct nir_variable *variable)
5000 {
5001 int idx = variable->data.location;
5002 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5003 LLVMValueRef interp;
5004
5005 variable->data.driver_location = idx * 4;
5006 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5007
5008 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5009 unsigned interp_type;
5010 if (variable->data.sample) {
5011 interp_type = INTERP_SAMPLE;
5012 ctx->shader_info->info.ps.force_persample = true;
5013 } else if (variable->data.centroid)
5014 interp_type = INTERP_CENTROID;
5015 else
5016 interp_type = INTERP_CENTER;
5017
5018 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5019 } else
5020 interp = NULL;
5021
5022 for (unsigned i = 0; i < attrib_count; ++i)
5023 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5024
5025 }
5026
5027 static void
5028 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5029 struct nir_shader *nir) {
5030 nir_foreach_variable(variable, &nir->inputs)
5031 handle_vs_input_decl(ctx, variable);
5032 }
5033
5034 static void
5035 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5036 struct nir_shader *nir)
5037 {
5038 if (!ctx->options->key.fs.multisample)
5039 return;
5040
5041 bool uses_center = false;
5042 bool uses_centroid = false;
5043 nir_foreach_variable(variable, &nir->inputs) {
5044 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5045 variable->data.sample)
5046 continue;
5047
5048 if (variable->data.centroid)
5049 uses_centroid = true;
5050 else
5051 uses_center = true;
5052 }
5053
5054 if (uses_center && uses_centroid) {
5055 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5056 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5057 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5058 }
5059 }
5060
5061 static void
5062 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5063 struct nir_shader *nir)
5064 {
5065 prepare_interp_optimize(ctx, nir);
5066
5067 nir_foreach_variable(variable, &nir->inputs)
5068 handle_fs_input_decl(ctx, variable);
5069
5070 unsigned index = 0;
5071
5072 if (ctx->shader_info->info.ps.uses_input_attachments ||
5073 ctx->shader_info->info.needs_multiview_view_index)
5074 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5075
5076 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5077 LLVMValueRef interp_param;
5078 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5079
5080 if (!(ctx->input_mask & (1ull << i)))
5081 continue;
5082
5083 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5084 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5085 interp_param = *inputs;
5086 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5087 inputs);
5088
5089 if (!interp_param)
5090 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5091 ++index;
5092 } else if (i == VARYING_SLOT_POS) {
5093 for(int i = 0; i < 3; ++i)
5094 inputs[i] = ctx->abi.frag_pos[i];
5095
5096 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one,
5097 ctx->abi.frag_pos[3]);
5098 }
5099 }
5100 ctx->shader_info->fs.num_interp = index;
5101 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5102 ctx->shader_info->fs.has_pcoord = true;
5103 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5104 ctx->shader_info->fs.prim_id_input = true;
5105 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5106 ctx->shader_info->fs.layer_input = true;
5107 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5108
5109 if (ctx->shader_info->info.needs_multiview_view_index)
5110 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5111 }
5112
5113 static LLVMValueRef
5114 ac_build_alloca(struct ac_llvm_context *ac,
5115 LLVMTypeRef type,
5116 const char *name)
5117 {
5118 LLVMBuilderRef builder = ac->builder;
5119 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5120 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5121 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5122 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5123 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5124 LLVMValueRef res;
5125
5126 if (first_instr) {
5127 LLVMPositionBuilderBefore(first_builder, first_instr);
5128 } else {
5129 LLVMPositionBuilderAtEnd(first_builder, first_block);
5130 }
5131
5132 res = LLVMBuildAlloca(first_builder, type, name);
5133 LLVMBuildStore(builder, LLVMConstNull(type), res);
5134
5135 LLVMDisposeBuilder(first_builder);
5136
5137 return res;
5138 }
5139
5140 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5141 LLVMTypeRef type,
5142 const char *name)
5143 {
5144 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5145 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5146 return ptr;
5147 }
5148
5149 static void
5150 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5151 struct nir_variable *variable)
5152 {
5153 int idx = variable->data.location + variable->data.index;
5154 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5155 uint64_t mask_attribs;
5156
5157 variable->data.driver_location = idx * 4;
5158
5159 /* tess ctrl has it's own load/store paths for outputs */
5160 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5161 return;
5162
5163 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5164 if (ctx->stage == MESA_SHADER_VERTEX ||
5165 ctx->stage == MESA_SHADER_TESS_EVAL ||
5166 ctx->stage == MESA_SHADER_GEOMETRY) {
5167 if (idx == VARYING_SLOT_CLIP_DIST0) {
5168 int length = ctx->num_output_clips + ctx->num_output_culls;
5169 if (ctx->stage == MESA_SHADER_VERTEX) {
5170 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5171 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5172 }
5173 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5174 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5175 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5176 }
5177
5178 if (length > 4)
5179 attrib_count = 2;
5180 else
5181 attrib_count = 1;
5182 mask_attribs = 1ull << idx;
5183 }
5184 }
5185
5186 ctx->output_mask |= mask_attribs;
5187 }
5188
5189 static void
5190 handle_shader_output_decl(struct ac_nir_context *ctx,
5191 struct nir_shader *nir,
5192 struct nir_variable *variable)
5193 {
5194 unsigned output_loc = variable->data.driver_location / 4;
5195 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5196
5197 /* tess ctrl has it's own load/store paths for outputs */
5198 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5199 return;
5200
5201 if (ctx->stage == MESA_SHADER_VERTEX ||
5202 ctx->stage == MESA_SHADER_TESS_EVAL ||
5203 ctx->stage == MESA_SHADER_GEOMETRY) {
5204 int idx = variable->data.location + variable->data.index;
5205 if (idx == VARYING_SLOT_CLIP_DIST0) {
5206 int length = nir->info.clip_distance_array_size +
5207 nir->info.cull_distance_array_size;
5208
5209 if (length > 4)
5210 attrib_count = 2;
5211 else
5212 attrib_count = 1;
5213 }
5214 }
5215
5216 for (unsigned i = 0; i < attrib_count; ++i) {
5217 for (unsigned chan = 0; chan < 4; chan++) {
5218 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5219 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5220 }
5221 }
5222 }
5223
5224 static LLVMTypeRef
5225 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5226 enum glsl_base_type type)
5227 {
5228 switch (type) {
5229 case GLSL_TYPE_INT:
5230 case GLSL_TYPE_UINT:
5231 case GLSL_TYPE_BOOL:
5232 case GLSL_TYPE_SUBROUTINE:
5233 return ctx->i32;
5234 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5235 return ctx->f32;
5236 case GLSL_TYPE_INT64:
5237 case GLSL_TYPE_UINT64:
5238 return ctx->i64;
5239 case GLSL_TYPE_DOUBLE:
5240 return ctx->f64;
5241 default:
5242 unreachable("unknown GLSL type");
5243 }
5244 }
5245
5246 static LLVMTypeRef
5247 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5248 const struct glsl_type *type)
5249 {
5250 if (glsl_type_is_scalar(type)) {
5251 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5252 }
5253
5254 if (glsl_type_is_vector(type)) {
5255 return LLVMVectorType(
5256 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5257 glsl_get_vector_elements(type));
5258 }
5259
5260 if (glsl_type_is_matrix(type)) {
5261 return LLVMArrayType(
5262 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5263 glsl_get_matrix_columns(type));
5264 }
5265
5266 if (glsl_type_is_array(type)) {
5267 return LLVMArrayType(
5268 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5269 glsl_get_length(type));
5270 }
5271
5272 assert(glsl_type_is_struct(type));
5273
5274 LLVMTypeRef member_types[glsl_get_length(type)];
5275
5276 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5277 member_types[i] =
5278 glsl_to_llvm_type(ctx,
5279 glsl_get_struct_field(type, i));
5280 }
5281
5282 return LLVMStructTypeInContext(ctx->context, member_types,
5283 glsl_get_length(type), false);
5284 }
5285
5286 static void
5287 setup_locals(struct ac_nir_context *ctx,
5288 struct nir_function *func)
5289 {
5290 int i, j;
5291 ctx->num_locals = 0;
5292 nir_foreach_variable(variable, &func->impl->locals) {
5293 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5294 variable->data.driver_location = ctx->num_locals * 4;
5295 ctx->num_locals += attrib_count;
5296 }
5297 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5298 if (!ctx->locals)
5299 return;
5300
5301 for (i = 0; i < ctx->num_locals; i++) {
5302 for (j = 0; j < 4; j++) {
5303 ctx->locals[i * 4 + j] =
5304 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5305 }
5306 }
5307 }
5308
5309 static void
5310 setup_shared(struct ac_nir_context *ctx,
5311 struct nir_shader *nir)
5312 {
5313 nir_foreach_variable(variable, &nir->shared) {
5314 LLVMValueRef shared =
5315 LLVMAddGlobalInAddressSpace(
5316 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5317 variable->name ? variable->name : "",
5318 LOCAL_ADDR_SPACE);
5319 _mesa_hash_table_insert(ctx->vars, variable, shared);
5320 }
5321 }
5322
5323 static LLVMValueRef
5324 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5325 {
5326 v = ac_to_float(ctx, v);
5327 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5328 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5329 }
5330
5331
5332 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5333 LLVMValueRef src0, LLVMValueRef src1)
5334 {
5335 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5336 LLVMValueRef comp[2];
5337
5338 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5339 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5340 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5341 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5342 }
5343
5344 /* Initialize arguments for the shader export intrinsic */
5345 static void
5346 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5347 LLVMValueRef *values,
5348 unsigned target,
5349 struct ac_export_args *args)
5350 {
5351 /* Default is 0xf. Adjusted below depending on the format. */
5352 args->enabled_channels = 0xf;
5353
5354 /* Specify whether the EXEC mask represents the valid mask */
5355 args->valid_mask = 0;
5356
5357 /* Specify whether this is the last export */
5358 args->done = 0;
5359
5360 /* Specify the target we are exporting */
5361 args->target = target;
5362
5363 args->compr = false;
5364 args->out[0] = LLVMGetUndef(ctx->f32);
5365 args->out[1] = LLVMGetUndef(ctx->f32);
5366 args->out[2] = LLVMGetUndef(ctx->f32);
5367 args->out[3] = LLVMGetUndef(ctx->f32);
5368
5369 if (!values)
5370 return;
5371
5372 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5373 LLVMValueRef val[4];
5374 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5375 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5376 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5377 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5378
5379 switch(col_format) {
5380 case V_028714_SPI_SHADER_ZERO:
5381 args->enabled_channels = 0; /* writemask */
5382 args->target = V_008DFC_SQ_EXP_NULL;
5383 break;
5384
5385 case V_028714_SPI_SHADER_32_R:
5386 args->enabled_channels = 1;
5387 args->out[0] = values[0];
5388 break;
5389
5390 case V_028714_SPI_SHADER_32_GR:
5391 args->enabled_channels = 0x3;
5392 args->out[0] = values[0];
5393 args->out[1] = values[1];
5394 break;
5395
5396 case V_028714_SPI_SHADER_32_AR:
5397 args->enabled_channels = 0x9;
5398 args->out[0] = values[0];
5399 args->out[3] = values[3];
5400 break;
5401
5402 case V_028714_SPI_SHADER_FP16_ABGR:
5403 args->compr = 1;
5404
5405 for (unsigned chan = 0; chan < 2; chan++) {
5406 LLVMValueRef pack_args[2] = {
5407 values[2 * chan],
5408 values[2 * chan + 1]
5409 };
5410 LLVMValueRef packed;
5411
5412 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5413 args->out[chan] = packed;
5414 }
5415 break;
5416
5417 case V_028714_SPI_SHADER_UNORM16_ABGR:
5418 for (unsigned chan = 0; chan < 4; chan++) {
5419 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5420 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5421 LLVMConstReal(ctx->f32, 65535), "");
5422 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5423 LLVMConstReal(ctx->f32, 0.5), "");
5424 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5425 ctx->i32, "");
5426 }
5427
5428 args->compr = 1;
5429 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5430 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5431 break;
5432
5433 case V_028714_SPI_SHADER_SNORM16_ABGR:
5434 for (unsigned chan = 0; chan < 4; chan++) {
5435 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5436 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5437 LLVMConstReal(ctx->f32, 32767), "");
5438
5439 /* If positive, add 0.5, else add -0.5. */
5440 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5441 LLVMBuildSelect(ctx->builder,
5442 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5443 val[chan], ctx->f32zero, ""),
5444 LLVMConstReal(ctx->f32, 0.5),
5445 LLVMConstReal(ctx->f32, -0.5), ""), "");
5446 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5447 }
5448
5449 args->compr = 1;
5450 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5451 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5452 break;
5453
5454 case V_028714_SPI_SHADER_UINT16_ABGR: {
5455 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5456 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5457 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
5458
5459 for (unsigned chan = 0; chan < 4; chan++) {
5460 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5461 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5462 }
5463
5464 args->compr = 1;
5465 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5466 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5467 break;
5468 }
5469
5470 case V_028714_SPI_SHADER_SINT16_ABGR: {
5471 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5472 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5473 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
5474 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5475 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->i32one;
5476 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
5477
5478 /* Clamp. */
5479 for (unsigned chan = 0; chan < 4; chan++) {
5480 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5481 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5482 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5483 }
5484
5485 args->compr = 1;
5486 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5487 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5488 break;
5489 }
5490
5491 default:
5492 case V_028714_SPI_SHADER_32_ABGR:
5493 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5494 break;
5495 }
5496 } else
5497 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5498
5499 for (unsigned i = 0; i < 4; ++i)
5500 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5501 }
5502
5503 static void
5504 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5505 bool export_prim_id,
5506 struct ac_vs_output_info *outinfo)
5507 {
5508 uint32_t param_count = 0;
5509 unsigned target;
5510 unsigned pos_idx, num_pos_exports = 0;
5511 struct ac_export_args args, pos_args[4] = {};
5512 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5513 int i;
5514
5515 if (ctx->options->key.has_multiview_view_index) {
5516 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5517 if(!*tmp_out) {
5518 for(unsigned i = 0; i < 4; ++i)
5519 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5520 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5521 }
5522
5523 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5524 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5525 }
5526
5527 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5528 sizeof(outinfo->vs_output_param_offset));
5529
5530 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5531 LLVMValueRef slots[8];
5532 unsigned j;
5533
5534 if (outinfo->cull_dist_mask)
5535 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5536
5537 i = VARYING_SLOT_CLIP_DIST0;
5538 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5539 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5540 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5541
5542 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5543 slots[i] = LLVMGetUndef(ctx->f32);
5544
5545 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5546 target = V_008DFC_SQ_EXP_POS + 3;
5547 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5548 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5549 &args, sizeof(args));
5550 }
5551
5552 target = V_008DFC_SQ_EXP_POS + 2;
5553 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5554 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5555 &args, sizeof(args));
5556
5557 }
5558
5559 LLVMValueRef pos_values[4] = {ctx->f32zero, ctx->f32zero, ctx->f32zero, ctx->f32one};
5560 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5561 for (unsigned j = 0; j < 4; j++)
5562 pos_values[j] = LLVMBuildLoad(ctx->builder,
5563 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5564 }
5565 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5566
5567 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5568 outinfo->writes_pointsize = true;
5569 psize_value = LLVMBuildLoad(ctx->builder,
5570 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5571 }
5572
5573 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5574 outinfo->writes_layer = true;
5575 layer_value = LLVMBuildLoad(ctx->builder,
5576 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5577 }
5578
5579 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5580 outinfo->writes_viewport_index = true;
5581 viewport_index_value = LLVMBuildLoad(ctx->builder,
5582 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5583 }
5584
5585 if (outinfo->writes_pointsize ||
5586 outinfo->writes_layer ||
5587 outinfo->writes_viewport_index) {
5588 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5589 (outinfo->writes_layer == true ? 4 : 0));
5590 pos_args[1].valid_mask = 0;
5591 pos_args[1].done = 0;
5592 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5593 pos_args[1].compr = 0;
5594 pos_args[1].out[0] = ctx->f32zero; /* X */
5595 pos_args[1].out[1] = ctx->f32zero; /* Y */
5596 pos_args[1].out[2] = ctx->f32zero; /* Z */
5597 pos_args[1].out[3] = ctx->f32zero; /* W */
5598
5599 if (outinfo->writes_pointsize == true)
5600 pos_args[1].out[0] = psize_value;
5601 if (outinfo->writes_layer == true)
5602 pos_args[1].out[2] = layer_value;
5603 if (outinfo->writes_viewport_index == true) {
5604 if (ctx->options->chip_class >= GFX9) {
5605 /* GFX9 has the layer in out.z[10:0] and the viewport
5606 * index in out.z[19:16].
5607 */
5608 LLVMValueRef v = viewport_index_value;
5609 v = ac_to_integer(&ctx->ac, v);
5610 v = LLVMBuildShl(ctx->builder, v,
5611 LLVMConstInt(ctx->i32, 16, false),
5612 "");
5613 v = LLVMBuildOr(ctx->builder, v,
5614 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5615
5616 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5617 pos_args[1].enabled_channels |= 1 << 2;
5618 } else {
5619 pos_args[1].out[3] = viewport_index_value;
5620 pos_args[1].enabled_channels |= 1 << 3;
5621 }
5622 }
5623 }
5624 for (i = 0; i < 4; i++) {
5625 if (pos_args[i].out[0])
5626 num_pos_exports++;
5627 }
5628
5629 pos_idx = 0;
5630 for (i = 0; i < 4; i++) {
5631 if (!pos_args[i].out[0])
5632 continue;
5633
5634 /* Specify the target we are exporting */
5635 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5636 if (pos_idx == num_pos_exports)
5637 pos_args[i].done = 1;
5638 ac_build_export(&ctx->ac, &pos_args[i]);
5639 }
5640
5641 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5642 LLVMValueRef values[4];
5643 if (!(ctx->output_mask & (1ull << i)))
5644 continue;
5645
5646 for (unsigned j = 0; j < 4; j++)
5647 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5648 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5649
5650 if (i == VARYING_SLOT_LAYER) {
5651 target = V_008DFC_SQ_EXP_PARAM + param_count;
5652 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5653 param_count++;
5654 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5655 target = V_008DFC_SQ_EXP_PARAM + param_count;
5656 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5657 param_count++;
5658 } else if (i >= VARYING_SLOT_VAR0) {
5659 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5660 target = V_008DFC_SQ_EXP_PARAM + param_count;
5661 outinfo->vs_output_param_offset[i] = param_count;
5662 param_count++;
5663 } else
5664 continue;
5665
5666 si_llvm_init_export_args(ctx, values, target, &args);
5667
5668 if (target >= V_008DFC_SQ_EXP_POS &&
5669 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5670 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5671 &args, sizeof(args));
5672 } else {
5673 ac_build_export(&ctx->ac, &args);
5674 }
5675 }
5676
5677 if (export_prim_id) {
5678 LLVMValueRef values[4];
5679 target = V_008DFC_SQ_EXP_PARAM + param_count;
5680 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5681 param_count++;
5682
5683 values[0] = ctx->vs_prim_id;
5684 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5685 ctx->shader_info->vs.vgpr_comp_cnt);
5686 for (unsigned j = 1; j < 4; j++)
5687 values[j] = ctx->f32zero;
5688 si_llvm_init_export_args(ctx, values, target, &args);
5689 ac_build_export(&ctx->ac, &args);
5690 outinfo->export_prim_id = true;
5691 }
5692
5693 outinfo->pos_exports = num_pos_exports;
5694 outinfo->param_exports = param_count;
5695 }
5696
5697 static void
5698 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5699 struct ac_es_output_info *outinfo)
5700 {
5701 int j;
5702 uint64_t max_output_written = 0;
5703 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5704 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5705 int param_index;
5706 int length = 4;
5707
5708 if (!(ctx->output_mask & (1ull << i)))
5709 continue;
5710
5711 if (i == VARYING_SLOT_CLIP_DIST0)
5712 length = ctx->num_output_clips + ctx->num_output_culls;
5713
5714 param_index = shader_io_get_unique_index(i);
5715
5716 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5717
5718 for (j = 0; j < length; j++) {
5719 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5720 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5721
5722 ac_build_buffer_store_dword(&ctx->ac,
5723 ctx->esgs_ring,
5724 out_val, 1,
5725 NULL, ctx->es2gs_offset,
5726 (4 * param_index + j) * 4,
5727 1, 1, true, true);
5728 }
5729 }
5730 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5731 }
5732
5733 static void
5734 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5735 {
5736 LLVMValueRef vertex_id = ctx->rel_auto_id;
5737 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5738 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5739 vertex_dw_stride, "");
5740
5741 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5742 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5743 int length = 4;
5744
5745 if (!(ctx->output_mask & (1ull << i)))
5746 continue;
5747
5748 if (i == VARYING_SLOT_CLIP_DIST0)
5749 length = ctx->num_output_clips + ctx->num_output_culls;
5750 int param = shader_io_get_unique_index(i);
5751 mark_tess_output(ctx, false, param);
5752 if (length > 4)
5753 mark_tess_output(ctx, false, param + 1);
5754 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5755 LLVMConstInt(ctx->i32, param * 4, false),
5756 "");
5757 for (unsigned j = 0; j < length; j++) {
5758 lds_store(ctx, dw_addr,
5759 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5760 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5761 }
5762 }
5763 }
5764
5765 struct ac_build_if_state
5766 {
5767 struct nir_to_llvm_context *ctx;
5768 LLVMValueRef condition;
5769 LLVMBasicBlockRef entry_block;
5770 LLVMBasicBlockRef true_block;
5771 LLVMBasicBlockRef false_block;
5772 LLVMBasicBlockRef merge_block;
5773 };
5774
5775 static LLVMBasicBlockRef
5776 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5777 {
5778 LLVMBasicBlockRef current_block;
5779 LLVMBasicBlockRef next_block;
5780 LLVMBasicBlockRef new_block;
5781
5782 /* get current basic block */
5783 current_block = LLVMGetInsertBlock(ctx->builder);
5784
5785 /* chqeck if there's another block after this one */
5786 next_block = LLVMGetNextBasicBlock(current_block);
5787 if (next_block) {
5788 /* insert the new block before the next block */
5789 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5790 }
5791 else {
5792 /* append new block after current block */
5793 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5794 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5795 }
5796 return new_block;
5797 }
5798
5799 static void
5800 ac_nir_build_if(struct ac_build_if_state *ifthen,
5801 struct nir_to_llvm_context *ctx,
5802 LLVMValueRef condition)
5803 {
5804 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5805
5806 memset(ifthen, 0, sizeof *ifthen);
5807 ifthen->ctx = ctx;
5808 ifthen->condition = condition;
5809 ifthen->entry_block = block;
5810
5811 /* create endif/merge basic block for the phi functions */
5812 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5813
5814 /* create/insert true_block before merge_block */
5815 ifthen->true_block =
5816 LLVMInsertBasicBlockInContext(ctx->context,
5817 ifthen->merge_block,
5818 "if-true-block");
5819
5820 /* successive code goes into the true block */
5821 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5822 }
5823
5824 /**
5825 * End a conditional.
5826 */
5827 static void
5828 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5829 {
5830 LLVMBuilderRef builder = ifthen->ctx->builder;
5831
5832 /* Insert branch to the merge block from current block */
5833 LLVMBuildBr(builder, ifthen->merge_block);
5834
5835 /*
5836 * Now patch in the various branch instructions.
5837 */
5838
5839 /* Insert the conditional branch instruction at the end of entry_block */
5840 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5841 if (ifthen->false_block) {
5842 /* we have an else clause */
5843 LLVMBuildCondBr(builder, ifthen->condition,
5844 ifthen->true_block, ifthen->false_block);
5845 }
5846 else {
5847 /* no else clause */
5848 LLVMBuildCondBr(builder, ifthen->condition,
5849 ifthen->true_block, ifthen->merge_block);
5850 }
5851
5852 /* Resume building code at end of the ifthen->merge_block */
5853 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5854 }
5855
5856 static void
5857 write_tess_factors(struct nir_to_llvm_context *ctx)
5858 {
5859 unsigned stride, outer_comps, inner_comps;
5860 struct ac_build_if_state if_ctx, inner_if_ctx;
5861 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
5862 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
5863 unsigned tess_inner_index, tess_outer_index;
5864 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5865 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5866 int i;
5867 emit_barrier(ctx);
5868
5869 switch (ctx->options->key.tcs.primitive_mode) {
5870 case GL_ISOLINES:
5871 stride = 2;
5872 outer_comps = 2;
5873 inner_comps = 0;
5874 break;
5875 case GL_TRIANGLES:
5876 stride = 4;
5877 outer_comps = 3;
5878 inner_comps = 1;
5879 break;
5880 case GL_QUADS:
5881 stride = 6;
5882 outer_comps = 4;
5883 inner_comps = 2;
5884 break;
5885 default:
5886 return;
5887 }
5888
5889 ac_nir_build_if(&if_ctx, ctx,
5890 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5891 invocation_id, ctx->i32zero, ""));
5892
5893 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5894 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5895
5896 mark_tess_output(ctx, true, tess_inner_index);
5897 mark_tess_output(ctx, true, tess_outer_index);
5898 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5899 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5900 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5901 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5902 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5903
5904 for (i = 0; i < 4; i++) {
5905 inner[i] = LLVMGetUndef(ctx->i32);
5906 outer[i] = LLVMGetUndef(ctx->i32);
5907 }
5908
5909 // LINES reverseal
5910 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5911 outer[0] = out[1] = lds_load(ctx, lds_outer);
5912 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5913 LLVMConstInt(ctx->i32, 1, false), "");
5914 outer[1] = out[0] = lds_load(ctx, lds_outer);
5915 } else {
5916 for (i = 0; i < outer_comps; i++) {
5917 outer[i] = out[i] =
5918 lds_load(ctx, lds_outer);
5919 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5920 LLVMConstInt(ctx->i32, 1, false), "");
5921 }
5922 for (i = 0; i < inner_comps; i++) {
5923 inner[i] = out[outer_comps+i] =
5924 lds_load(ctx, lds_inner);
5925 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5926 LLVMConstInt(ctx->i32, 1, false), "");
5927 }
5928 }
5929
5930 /* Convert the outputs to vectors for stores. */
5931 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5932 vec1 = NULL;
5933
5934 if (stride > 4)
5935 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5936
5937
5938 buffer = ctx->hs_ring_tess_factor;
5939 tf_base = ctx->tess_factor_offset;
5940 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5941 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5942
5943 ac_nir_build_if(&inner_if_ctx, ctx,
5944 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5945 rel_patch_id, ctx->i32zero, ""));
5946
5947 /* Store the dynamic HS control word. */
5948 ac_build_buffer_store_dword(&ctx->ac, buffer,
5949 LLVMConstInt(ctx->i32, 0x80000000, false),
5950 1, ctx->i32zero, tf_base,
5951 0, 1, 0, true, false);
5952 ac_nir_build_endif(&inner_if_ctx);
5953
5954 /* Store the tessellation factors. */
5955 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5956 MIN2(stride, 4), byteoffset, tf_base,
5957 4, 1, 0, true, false);
5958 if (vec1)
5959 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5960 stride - 4, byteoffset, tf_base,
5961 20, 1, 0, true, false);
5962
5963 //TODO store to offchip for TES to read - only if TES reads them
5964 if (1) {
5965 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5966 LLVMValueRef tf_inner_offset;
5967 unsigned param_outer, param_inner;
5968
5969 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5970 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5971 LLVMConstInt(ctx->i32, param_outer, 0));
5972
5973 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5974 util_next_power_of_two(outer_comps));
5975
5976 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5977 outer_comps, tf_outer_offset,
5978 ctx->oc_lds, 0, 1, 0, true, false);
5979 if (inner_comps) {
5980 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5981 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5982 LLVMConstInt(ctx->i32, param_inner, 0));
5983
5984 inner_vec = inner_comps == 1 ? inner[0] :
5985 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5986 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5987 inner_comps, tf_inner_offset,
5988 ctx->oc_lds, 0, 1, 0, true, false);
5989 }
5990 }
5991 ac_nir_build_endif(&if_ctx);
5992 }
5993
5994 static void
5995 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5996 {
5997 write_tess_factors(ctx);
5998 }
5999
6000 static bool
6001 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6002 LLVMValueRef *color, unsigned param, bool is_last,
6003 struct ac_export_args *args)
6004 {
6005 /* Export */
6006 si_llvm_init_export_args(ctx, color, param,
6007 args);
6008
6009 if (is_last) {
6010 args->valid_mask = 1; /* whether the EXEC mask is valid */
6011 args->done = 1; /* DONE bit */
6012 } else if (!args->enabled_channels)
6013 return false; /* unnecessary NULL export */
6014
6015 return true;
6016 }
6017
6018 static void
6019 si_export_mrt_z(struct nir_to_llvm_context *ctx,
6020 LLVMValueRef depth, LLVMValueRef stencil,
6021 LLVMValueRef samplemask)
6022 {
6023 struct ac_export_args args;
6024
6025 args.enabled_channels = 0;
6026 args.valid_mask = 1;
6027 args.done = 1;
6028 args.target = V_008DFC_SQ_EXP_MRTZ;
6029 args.compr = false;
6030
6031 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
6032 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
6033 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
6034 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
6035
6036 if (depth) {
6037 args.out[0] = depth;
6038 args.enabled_channels |= 0x1;
6039 }
6040
6041 if (stencil) {
6042 args.out[1] = stencil;
6043 args.enabled_channels |= 0x2;
6044 }
6045
6046 if (samplemask) {
6047 args.out[2] = samplemask;
6048 args.enabled_channels |= 0x4;
6049 }
6050
6051 /* SI (except OLAND and HAINAN) has a bug that it only looks
6052 * at the X writemask component. */
6053 if (ctx->options->chip_class == SI &&
6054 ctx->options->family != CHIP_OLAND &&
6055 ctx->options->family != CHIP_HAINAN)
6056 args.enabled_channels |= 0x1;
6057
6058 ac_build_export(&ctx->ac, &args);
6059 }
6060
6061 static void
6062 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6063 {
6064 unsigned index = 0;
6065 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6066 struct ac_export_args color_args[8];
6067
6068 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6069 LLVMValueRef values[4];
6070
6071 if (!(ctx->output_mask & (1ull << i)))
6072 continue;
6073
6074 if (i == FRAG_RESULT_DEPTH) {
6075 ctx->shader_info->fs.writes_z = true;
6076 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6077 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6078 } else if (i == FRAG_RESULT_STENCIL) {
6079 ctx->shader_info->fs.writes_stencil = true;
6080 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6081 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6082 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6083 ctx->shader_info->fs.writes_sample_mask = true;
6084 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6085 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6086 } else {
6087 bool last = false;
6088 for (unsigned j = 0; j < 4; j++)
6089 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6090 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6091
6092 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6093 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6094
6095 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6096 if (ret)
6097 index++;
6098 }
6099 }
6100
6101 for (unsigned i = 0; i < index; i++)
6102 ac_build_export(&ctx->ac, &color_args[i]);
6103 if (depth || stencil || samplemask)
6104 si_export_mrt_z(ctx, depth, stencil, samplemask);
6105 else if (!index) {
6106 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6107 ac_build_export(&ctx->ac, &color_args[0]);
6108 }
6109
6110 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6111 }
6112
6113 static void
6114 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6115 {
6116 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6117 }
6118
6119 static void
6120 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6121 LLVMValueRef *addrs)
6122 {
6123 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6124
6125 switch (ctx->stage) {
6126 case MESA_SHADER_VERTEX:
6127 if (ctx->options->key.vs.as_ls)
6128 handle_ls_outputs_post(ctx);
6129 else if (ctx->options->key.vs.as_es)
6130 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6131 else
6132 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6133 &ctx->shader_info->vs.outinfo);
6134 break;
6135 case MESA_SHADER_FRAGMENT:
6136 handle_fs_outputs_post(ctx);
6137 break;
6138 case MESA_SHADER_GEOMETRY:
6139 emit_gs_epilogue(ctx);
6140 break;
6141 case MESA_SHADER_TESS_CTRL:
6142 handle_tcs_outputs_post(ctx);
6143 break;
6144 case MESA_SHADER_TESS_EVAL:
6145 if (ctx->options->key.tes.as_es)
6146 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6147 else
6148 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6149 &ctx->shader_info->tes.outinfo);
6150 break;
6151 default:
6152 break;
6153 }
6154 }
6155
6156 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6157 {
6158 LLVMPassManagerRef passmgr;
6159 /* Create the pass manager */
6160 passmgr = LLVMCreateFunctionPassManagerForModule(
6161 ctx->module);
6162
6163 /* This pass should eliminate all the load and store instructions */
6164 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6165
6166 /* Add some optimization passes */
6167 LLVMAddScalarReplAggregatesPass(passmgr);
6168 LLVMAddLICMPass(passmgr);
6169 LLVMAddAggressiveDCEPass(passmgr);
6170 LLVMAddCFGSimplificationPass(passmgr);
6171 LLVMAddInstructionCombiningPass(passmgr);
6172
6173 /* Run the pass */
6174 LLVMInitializeFunctionPassManager(passmgr);
6175 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6176 LLVMFinalizeFunctionPassManager(passmgr);
6177
6178 LLVMDisposeBuilder(ctx->builder);
6179 LLVMDisposePassManager(passmgr);
6180 }
6181
6182 static void
6183 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6184 {
6185 struct ac_vs_output_info *outinfo;
6186
6187 switch (ctx->stage) {
6188 case MESA_SHADER_FRAGMENT:
6189 case MESA_SHADER_COMPUTE:
6190 case MESA_SHADER_TESS_CTRL:
6191 case MESA_SHADER_GEOMETRY:
6192 return;
6193 case MESA_SHADER_VERTEX:
6194 if (ctx->options->key.vs.as_ls ||
6195 ctx->options->key.vs.as_es)
6196 return;
6197 outinfo = &ctx->shader_info->vs.outinfo;
6198 break;
6199 case MESA_SHADER_TESS_EVAL:
6200 if (ctx->options->key.vs.as_es)
6201 return;
6202 outinfo = &ctx->shader_info->tes.outinfo;
6203 break;
6204 default:
6205 unreachable("Unhandled shader type");
6206 }
6207
6208 ac_optimize_vs_outputs(&ctx->ac,
6209 ctx->main_function,
6210 outinfo->vs_output_param_offset,
6211 VARYING_SLOT_MAX,
6212 &outinfo->param_exports);
6213 }
6214
6215 static void
6216 ac_setup_rings(struct nir_to_llvm_context *ctx)
6217 {
6218 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6219 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6220 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
6221 }
6222
6223 if (ctx->is_gs_copy_shader) {
6224 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
6225 }
6226 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6227 LLVMValueRef tmp;
6228 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
6229 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
6230
6231 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6232
6233 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
6234 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
6235 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6236 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
6237 }
6238
6239 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6240 ctx->stage == MESA_SHADER_TESS_EVAL) {
6241 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6242 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6243 }
6244 }
6245
6246 static unsigned
6247 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6248 const struct nir_shader *nir)
6249 {
6250 switch (nir->stage) {
6251 case MESA_SHADER_TESS_CTRL:
6252 return chip_class >= CIK ? 128 : 64;
6253 case MESA_SHADER_GEOMETRY:
6254 return 64;
6255 case MESA_SHADER_COMPUTE:
6256 break;
6257 default:
6258 return 0;
6259 }
6260
6261 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6262 nir->info.cs.local_size[1] *
6263 nir->info.cs.local_size[2];
6264 return max_workgroup_size;
6265 }
6266
6267 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6268 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6269 {
6270 struct ac_nir_context ctx = {};
6271 struct nir_function *func;
6272
6273 ctx.ac = *ac;
6274 ctx.abi = abi;
6275
6276 ctx.nctx = nctx;
6277 if (nctx)
6278 nctx->nir = &ctx;
6279
6280 ctx.stage = nir->stage;
6281
6282 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6283
6284 nir_foreach_variable(variable, &nir->outputs)
6285 handle_shader_output_decl(&ctx, nir, variable);
6286
6287 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6288 _mesa_key_pointer_equal);
6289 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6290 _mesa_key_pointer_equal);
6291 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6292 _mesa_key_pointer_equal);
6293
6294 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6295
6296 setup_locals(&ctx, func);
6297
6298 if (nir->stage == MESA_SHADER_COMPUTE)
6299 setup_shared(&ctx, nir);
6300
6301 visit_cf_list(&ctx, &func->impl->body);
6302 phi_post_pass(&ctx);
6303
6304 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6305 ctx.outputs);
6306
6307 free(ctx.locals);
6308 ralloc_free(ctx.defs);
6309 ralloc_free(ctx.phis);
6310 ralloc_free(ctx.vars);
6311
6312 if (nctx)
6313 nctx->nir = NULL;
6314 }
6315
6316 static
6317 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6318 struct nir_shader *nir,
6319 struct ac_shader_variant_info *shader_info,
6320 const struct ac_nir_compiler_options *options)
6321 {
6322 struct nir_to_llvm_context ctx = {0};
6323 unsigned i;
6324 ctx.options = options;
6325 ctx.shader_info = shader_info;
6326 ctx.context = LLVMContextCreate();
6327 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6328
6329 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6330 ctx.ac.module = ctx.module;
6331
6332 memset(shader_info, 0, sizeof(*shader_info));
6333
6334 ac_nir_shader_info_pass(nir, options, &shader_info->info);
6335
6336 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6337
6338 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6339 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6340 LLVMSetDataLayout(ctx.module, data_layout_str);
6341 LLVMDisposeTargetData(data_layout);
6342 LLVMDisposeMessage(data_layout_str);
6343
6344 setup_types(&ctx);
6345
6346 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6347 ctx.ac.builder = ctx.builder;
6348 ctx.stage = nir->stage;
6349 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
6350
6351 for (i = 0; i < AC_UD_MAX_SETS; i++)
6352 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6353 for (i = 0; i < AC_UD_MAX_UD; i++)
6354 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6355
6356 create_function(&ctx);
6357
6358 if (nir->stage == MESA_SHADER_GEOMETRY) {
6359 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.i32, "gs_next_vertex");
6360
6361 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
6362 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
6363 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
6364 } else if (nir->stage == MESA_SHADER_VERTEX) {
6365 if (shader_info->info.vs.needs_instance_id) {
6366 ctx.shader_info->vs.vgpr_comp_cnt =
6367 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6368 }
6369 } else if (nir->stage == MESA_SHADER_FRAGMENT) {
6370 shader_info->fs.can_discard = nir->info.fs.uses_discard;
6371 }
6372
6373 ac_setup_rings(&ctx);
6374
6375 ctx.num_output_clips = nir->info.clip_distance_array_size;
6376 ctx.num_output_culls = nir->info.cull_distance_array_size;
6377
6378 if (nir->stage == MESA_SHADER_FRAGMENT)
6379 handle_fs_inputs(&ctx, nir);
6380 else if(nir->stage == MESA_SHADER_VERTEX)
6381 handle_vs_inputs(&ctx, nir);
6382
6383 ctx.abi.inputs = &ctx.inputs[0];
6384 ctx.abi.emit_outputs = handle_shader_outputs_post;
6385 ctx.abi.load_ssbo = radv_load_ssbo;
6386 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6387
6388 nir_foreach_variable(variable, &nir->outputs)
6389 scan_shader_output_decl(&ctx, variable);
6390
6391 ac_nir_translate(&ctx.ac, &ctx.abi, nir, &ctx);
6392
6393 LLVMBuildRetVoid(ctx.builder);
6394
6395 ac_llvm_finalize_module(&ctx);
6396
6397 ac_nir_eliminate_const_vs_outputs(&ctx);
6398
6399 if (nir->stage == MESA_SHADER_GEOMETRY) {
6400 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
6401 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6402 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6403 nir->info.gs.vertices_out;
6404 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
6405 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6406 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6407 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6408 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6409 }
6410
6411 return ctx.module;
6412 }
6413
6414 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6415 {
6416 unsigned *retval = (unsigned *)context;
6417 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6418 char *description = LLVMGetDiagInfoDescription(di);
6419
6420 if (severity == LLVMDSError) {
6421 *retval = 1;
6422 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6423 description);
6424 }
6425
6426 LLVMDisposeMessage(description);
6427 }
6428
6429 static unsigned ac_llvm_compile(LLVMModuleRef M,
6430 struct ac_shader_binary *binary,
6431 LLVMTargetMachineRef tm)
6432 {
6433 unsigned retval = 0;
6434 char *err;
6435 LLVMContextRef llvm_ctx;
6436 LLVMMemoryBufferRef out_buffer;
6437 unsigned buffer_size;
6438 const char *buffer_data;
6439 LLVMBool mem_err;
6440
6441 /* Setup Diagnostic Handler*/
6442 llvm_ctx = LLVMGetModuleContext(M);
6443
6444 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6445 &retval);
6446
6447 /* Compile IR*/
6448 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6449 &err, &out_buffer);
6450
6451 /* Process Errors/Warnings */
6452 if (mem_err) {
6453 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6454 free(err);
6455 retval = 1;
6456 goto out;
6457 }
6458
6459 /* Extract Shader Code*/
6460 buffer_size = LLVMGetBufferSize(out_buffer);
6461 buffer_data = LLVMGetBufferStart(out_buffer);
6462
6463 ac_elf_read(buffer_data, buffer_size, binary);
6464
6465 /* Clean up */
6466 LLVMDisposeMemoryBuffer(out_buffer);
6467
6468 out:
6469 return retval;
6470 }
6471
6472 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6473 LLVMModuleRef llvm_module,
6474 struct ac_shader_binary *binary,
6475 struct ac_shader_config *config,
6476 struct ac_shader_variant_info *shader_info,
6477 gl_shader_stage stage,
6478 bool dump_shader, bool supports_spill)
6479 {
6480 if (dump_shader)
6481 ac_dump_module(llvm_module);
6482
6483 memset(binary, 0, sizeof(*binary));
6484 int v = ac_llvm_compile(llvm_module, binary, tm);
6485 if (v) {
6486 fprintf(stderr, "compile failed\n");
6487 }
6488
6489 if (dump_shader)
6490 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6491
6492 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6493
6494 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6495 LLVMDisposeModule(llvm_module);
6496 LLVMContextDispose(ctx);
6497
6498 if (stage == MESA_SHADER_FRAGMENT) {
6499 shader_info->num_input_vgprs = 0;
6500 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6501 shader_info->num_input_vgprs += 2;
6502 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6503 shader_info->num_input_vgprs += 2;
6504 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6505 shader_info->num_input_vgprs += 2;
6506 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6507 shader_info->num_input_vgprs += 3;
6508 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6509 shader_info->num_input_vgprs += 2;
6510 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6511 shader_info->num_input_vgprs += 2;
6512 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6513 shader_info->num_input_vgprs += 2;
6514 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6515 shader_info->num_input_vgprs += 1;
6516 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6517 shader_info->num_input_vgprs += 1;
6518 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6519 shader_info->num_input_vgprs += 1;
6520 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6521 shader_info->num_input_vgprs += 1;
6522 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6523 shader_info->num_input_vgprs += 1;
6524 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6525 shader_info->num_input_vgprs += 1;
6526 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6527 shader_info->num_input_vgprs += 1;
6528 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6529 shader_info->num_input_vgprs += 1;
6530 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6531 shader_info->num_input_vgprs += 1;
6532 }
6533 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6534
6535 /* +3 for scratch wave offset and VCC */
6536 config->num_sgprs = MAX2(config->num_sgprs,
6537 shader_info->num_input_sgprs + 3);
6538 }
6539
6540 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6541 struct ac_shader_binary *binary,
6542 struct ac_shader_config *config,
6543 struct ac_shader_variant_info *shader_info,
6544 struct nir_shader *nir,
6545 const struct ac_nir_compiler_options *options,
6546 bool dump_shader)
6547 {
6548
6549 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6550 options);
6551
6552 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6553 switch (nir->stage) {
6554 case MESA_SHADER_COMPUTE:
6555 for (int i = 0; i < 3; ++i)
6556 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6557 break;
6558 case MESA_SHADER_FRAGMENT:
6559 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6560 break;
6561 case MESA_SHADER_GEOMETRY:
6562 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6563 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6564 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6565 shader_info->gs.invocations = nir->info.gs.invocations;
6566 break;
6567 case MESA_SHADER_TESS_EVAL:
6568 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6569 shader_info->tes.spacing = nir->info.tess.spacing;
6570 shader_info->tes.ccw = nir->info.tess.ccw;
6571 shader_info->tes.point_mode = nir->info.tess.point_mode;
6572 shader_info->tes.as_es = options->key.tes.as_es;
6573 break;
6574 case MESA_SHADER_TESS_CTRL:
6575 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6576 break;
6577 case MESA_SHADER_VERTEX:
6578 shader_info->vs.as_es = options->key.vs.as_es;
6579 shader_info->vs.as_ls = options->key.vs.as_ls;
6580 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6581 if (options->key.vs.as_ls)
6582 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6583 break;
6584 default:
6585 break;
6586 }
6587 }
6588
6589 static void
6590 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6591 {
6592 LLVMValueRef args[9];
6593 args[0] = ctx->gsvs_ring;
6594 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6595 args[3] = ctx->i32zero;
6596 args[4] = ctx->i32one; /* OFFEN */
6597 args[5] = ctx->i32zero; /* IDXEN */
6598 args[6] = ctx->i32one; /* GLC */
6599 args[7] = ctx->i32one; /* SLC */
6600 args[8] = ctx->i32zero; /* TFE */
6601
6602 int idx = 0;
6603
6604 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6605 int length = 4;
6606 int slot = idx;
6607 int slot_inc = 1;
6608 if (!(ctx->output_mask & (1ull << i)))
6609 continue;
6610
6611 if (i == VARYING_SLOT_CLIP_DIST0) {
6612 /* unpack clip and cull from a single set of slots */
6613 length = ctx->num_output_clips + ctx->num_output_culls;
6614 if (length > 4)
6615 slot_inc = 2;
6616 }
6617
6618 for (unsigned j = 0; j < length; j++) {
6619 LLVMValueRef value;
6620 args[2] = LLVMConstInt(ctx->i32,
6621 (slot * 4 + j) *
6622 ctx->gs_max_out_vertices * 16 * 4, false);
6623
6624 value = ac_build_intrinsic(&ctx->ac,
6625 "llvm.SI.buffer.load.dword.i32.i32",
6626 ctx->i32, args, 9,
6627 AC_FUNC_ATTR_READONLY |
6628 AC_FUNC_ATTR_LEGACY);
6629
6630 LLVMBuildStore(ctx->builder,
6631 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6632 }
6633 idx += slot_inc;
6634 }
6635 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6636 }
6637
6638 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6639 struct nir_shader *geom_shader,
6640 struct ac_shader_binary *binary,
6641 struct ac_shader_config *config,
6642 struct ac_shader_variant_info *shader_info,
6643 const struct ac_nir_compiler_options *options,
6644 bool dump_shader)
6645 {
6646 struct nir_to_llvm_context ctx = {0};
6647 ctx.context = LLVMContextCreate();
6648 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6649 ctx.options = options;
6650 ctx.shader_info = shader_info;
6651
6652 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6653 ctx.ac.module = ctx.module;
6654
6655 ctx.is_gs_copy_shader = true;
6656 LLVMSetTarget(ctx.module, "amdgcn--");
6657 setup_types(&ctx);
6658
6659 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6660 ctx.ac.builder = ctx.builder;
6661 ctx.stage = MESA_SHADER_VERTEX;
6662
6663 create_function(&ctx);
6664
6665 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6666 ac_setup_rings(&ctx);
6667
6668 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6669 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6670
6671 struct ac_nir_context nir_ctx = {};
6672 nir_ctx.ac = ctx.ac;
6673 nir_ctx.abi = &ctx.abi;
6674
6675 nir_ctx.nctx = &ctx;
6676 ctx.nir = &nir_ctx;
6677
6678 nir_foreach_variable(variable, &geom_shader->outputs) {
6679 scan_shader_output_decl(&ctx, variable);
6680 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6681 }
6682
6683 ac_gs_copy_shader_emit(&ctx);
6684
6685 ctx.nir = NULL;
6686
6687 LLVMBuildRetVoid(ctx.builder);
6688
6689 ac_llvm_finalize_module(&ctx);
6690
6691 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6692 MESA_SHADER_VERTEX,
6693 dump_shader, options->supports_spill);
6694 }