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ac/nir: remove useless bitcast in load_tess_coord()
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
48
49 struct nir_to_llvm_context;
50
51 struct ac_nir_context {
52 struct ac_llvm_context ac;
53 struct ac_shader_abi *abi;
54
55 gl_shader_stage stage;
56
57 struct hash_table *defs;
58 struct hash_table *phis;
59 struct hash_table *vars;
60
61 LLVMValueRef main_function;
62 LLVMBasicBlockRef continue_block;
63 LLVMBasicBlockRef break_block;
64
65 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
66
67 int num_locals;
68 LLVMValueRef *locals;
69
70 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
71 };
72
73 struct nir_to_llvm_context {
74 struct ac_llvm_context ac;
75 const struct ac_nir_compiler_options *options;
76 struct ac_shader_variant_info *shader_info;
77 struct ac_shader_abi abi;
78 struct ac_nir_context *nir;
79
80 unsigned max_workgroup_size;
81 LLVMContextRef context;
82 LLVMModuleRef module;
83 LLVMBuilderRef builder;
84 LLVMValueRef main_function;
85
86 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
87 LLVMValueRef ring_offsets;
88
89 LLVMValueRef vertex_buffers;
90 LLVMValueRef rel_auto_id;
91 LLVMValueRef vs_prim_id;
92 LLVMValueRef ls_out_layout;
93 LLVMValueRef es2gs_offset;
94
95 LLVMValueRef tcs_offchip_layout;
96 LLVMValueRef tcs_out_offsets;
97 LLVMValueRef tcs_out_layout;
98 LLVMValueRef tcs_in_layout;
99 LLVMValueRef oc_lds;
100 LLVMValueRef merged_wave_info;
101 LLVMValueRef tess_factor_offset;
102 LLVMValueRef tes_rel_patch_id;
103 LLVMValueRef tes_u;
104 LLVMValueRef tes_v;
105
106 LLVMValueRef gsvs_ring_stride;
107 LLVMValueRef gsvs_num_entries;
108 LLVMValueRef gs2vs_offset;
109 LLVMValueRef gs_wave_id;
110 LLVMValueRef gs_vtx_offset[6];
111
112 LLVMValueRef esgs_ring;
113 LLVMValueRef gsvs_ring;
114 LLVMValueRef hs_ring_tess_offchip;
115 LLVMValueRef hs_ring_tess_factor;
116
117 LLVMValueRef sample_pos_offset;
118 LLVMValueRef persp_sample, persp_center, persp_centroid;
119 LLVMValueRef linear_sample, linear_center, linear_centroid;
120
121 gl_shader_stage stage;
122
123 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
124
125 uint64_t input_mask;
126 uint64_t output_mask;
127 uint8_t num_output_clips;
128 uint8_t num_output_culls;
129
130 bool is_gs_copy_shader;
131 LLVMValueRef gs_next_vertex;
132 unsigned gs_max_out_vertices;
133
134 unsigned tes_primitive_mode;
135 uint64_t tess_outputs_written;
136 uint64_t tess_patch_outputs_written;
137
138 uint32_t tcs_patch_outputs_read;
139 uint64_t tcs_outputs_read;
140 };
141
142 static inline struct nir_to_llvm_context *
143 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
144 {
145 struct nir_to_llvm_context *ctx = NULL;
146 return container_of(abi, ctx, abi);
147 }
148
149 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
150 const nir_deref_var *deref,
151 enum ac_descriptor_type desc_type,
152 const nir_tex_instr *instr,
153 bool image, bool write);
154
155 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
156 {
157 return (index * 4) + chan;
158 }
159
160 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
161 {
162 /* handle patch indices separate */
163 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
164 return 0;
165 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
166 return 1;
167 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
168 return 2 + (slot - VARYING_SLOT_PATCH0);
169
170 if (slot == VARYING_SLOT_POS)
171 return 0;
172 if (slot == VARYING_SLOT_PSIZ)
173 return 1;
174 if (slot == VARYING_SLOT_CLIP_DIST0)
175 return 2;
176 /* 3 is reserved for clip dist as well */
177 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
178 return 4 + (slot - VARYING_SLOT_VAR0);
179 unreachable("illegal slot in get unique index\n");
180 }
181
182 static void set_llvm_calling_convention(LLVMValueRef func,
183 gl_shader_stage stage)
184 {
185 enum radeon_llvm_calling_convention calling_conv;
186
187 switch (stage) {
188 case MESA_SHADER_VERTEX:
189 case MESA_SHADER_TESS_EVAL:
190 calling_conv = RADEON_LLVM_AMDGPU_VS;
191 break;
192 case MESA_SHADER_GEOMETRY:
193 calling_conv = RADEON_LLVM_AMDGPU_GS;
194 break;
195 case MESA_SHADER_TESS_CTRL:
196 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
197 break;
198 case MESA_SHADER_FRAGMENT:
199 calling_conv = RADEON_LLVM_AMDGPU_PS;
200 break;
201 case MESA_SHADER_COMPUTE:
202 calling_conv = RADEON_LLVM_AMDGPU_CS;
203 break;
204 default:
205 unreachable("Unhandle shader type");
206 }
207
208 LLVMSetFunctionCallConv(func, calling_conv);
209 }
210
211 #define MAX_ARGS 23
212 struct arg_info {
213 LLVMTypeRef types[MAX_ARGS];
214 LLVMValueRef *assign[MAX_ARGS];
215 unsigned array_params_mask;
216 uint8_t count;
217 uint8_t sgpr_count;
218 uint8_t num_sgprs_used;
219 uint8_t num_vgprs_used;
220 };
221
222 enum ac_arg_regfile {
223 ARG_SGPR,
224 ARG_VGPR,
225 };
226
227 static void
228 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
229 LLVMValueRef *param_ptr)
230 {
231 assert(info->count < MAX_ARGS);
232
233 info->assign[info->count] = param_ptr;
234 info->types[info->count] = type;
235 info->count++;
236
237 if (regfile == ARG_SGPR) {
238 info->num_sgprs_used += ac_get_type_size(type) / 4;
239 info->sgpr_count++;
240 } else {
241 assert(regfile == ARG_VGPR);
242 info->num_vgprs_used += ac_get_type_size(type) / 4;
243 }
244 }
245
246 static inline void
247 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
248 {
249 info->array_params_mask |= (1 << info->count);
250 add_arg(info, ARG_SGPR, type, param_ptr);
251 }
252
253 static void assign_arguments(LLVMValueRef main_function,
254 struct arg_info *info)
255 {
256 unsigned i;
257 for (i = 0; i < info->count; i++) {
258 if (info->assign[i])
259 *info->assign[i] = LLVMGetParam(main_function, i);
260 }
261 }
262
263 static LLVMValueRef
264 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
265 LLVMBuilderRef builder, LLVMTypeRef *return_types,
266 unsigned num_return_elems,
267 struct arg_info *args,
268 unsigned max_workgroup_size,
269 bool unsafe_math)
270 {
271 LLVMTypeRef main_function_type, ret_type;
272 LLVMBasicBlockRef main_function_body;
273
274 if (num_return_elems)
275 ret_type = LLVMStructTypeInContext(ctx, return_types,
276 num_return_elems, true);
277 else
278 ret_type = LLVMVoidTypeInContext(ctx);
279
280 /* Setup the function */
281 main_function_type =
282 LLVMFunctionType(ret_type, args->types, args->count, 0);
283 LLVMValueRef main_function =
284 LLVMAddFunction(module, "main", main_function_type);
285 main_function_body =
286 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
287 LLVMPositionBuilderAtEnd(builder, main_function_body);
288
289 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
290 for (unsigned i = 0; i < args->sgpr_count; ++i) {
291 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
292
293 if (args->array_params_mask & (1 << i)) {
294 LLVMValueRef P = LLVMGetParam(main_function, i);
295 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
296 ac_add_attr_dereferenceable(P, UINT64_MAX);
297 }
298 }
299
300 if (max_workgroup_size) {
301 ac_llvm_add_target_dep_function_attr(main_function,
302 "amdgpu-max-work-group-size",
303 max_workgroup_size);
304 }
305 if (unsafe_math) {
306 /* These were copied from some LLVM test. */
307 LLVMAddTargetDependentFunctionAttr(main_function,
308 "less-precise-fpmad",
309 "true");
310 LLVMAddTargetDependentFunctionAttr(main_function,
311 "no-infs-fp-math",
312 "true");
313 LLVMAddTargetDependentFunctionAttr(main_function,
314 "no-nans-fp-math",
315 "true");
316 LLVMAddTargetDependentFunctionAttr(main_function,
317 "unsafe-fp-math",
318 "true");
319 LLVMAddTargetDependentFunctionAttr(main_function,
320 "no-signed-zeros-fp-math",
321 "true");
322 }
323 return main_function;
324 }
325
326 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
327 LLVMValueRef param, unsigned rshift,
328 unsigned bitwidth)
329 {
330 LLVMValueRef value = param;
331 if (rshift)
332 value = LLVMBuildLShr(ctx->builder, value,
333 LLVMConstInt(ctx->i32, rshift, false), "");
334
335 if (rshift + bitwidth < 32) {
336 unsigned mask = (1 << bitwidth) - 1;
337 value = LLVMBuildAnd(ctx->builder, value,
338 LLVMConstInt(ctx->i32, mask, false), "");
339 }
340 return value;
341 }
342
343 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
344 {
345 switch (ctx->stage) {
346 case MESA_SHADER_TESS_CTRL:
347 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
348 case MESA_SHADER_TESS_EVAL:
349 return ctx->tes_rel_patch_id;
350 break;
351 default:
352 unreachable("Illegal stage");
353 }
354 }
355
356 /* Tessellation shaders pass outputs to the next shader using LDS.
357 *
358 * LS outputs = TCS inputs
359 * TCS outputs = TES inputs
360 *
361 * The LDS layout is:
362 * - TCS inputs for patch 0
363 * - TCS inputs for patch 1
364 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
365 * - ...
366 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
367 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
368 * - TCS outputs for patch 1
369 * - Per-patch TCS outputs for patch 1
370 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
371 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
372 * - ...
373 *
374 * All three shaders VS(LS), TCS, TES share the same LDS space.
375 */
376 static LLVMValueRef
377 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
378 {
379 if (ctx->stage == MESA_SHADER_VERTEX)
380 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
381 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
382 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
383 else {
384 assert(0);
385 return NULL;
386 }
387 }
388
389 static LLVMValueRef
390 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
391 {
392 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
393 }
394
395 static LLVMValueRef
396 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
397 {
398 return LLVMBuildMul(ctx->builder,
399 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
400 LLVMConstInt(ctx->ac.i32, 4, false), "");
401 }
402
403 static LLVMValueRef
404 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
405 {
406 return LLVMBuildMul(ctx->builder,
407 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
408 LLVMConstInt(ctx->ac.i32, 4, false), "");
409 }
410
411 static LLVMValueRef
412 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
413 {
414 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
415 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
416
417 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
418 }
419
420 static LLVMValueRef
421 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
422 {
423 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
424 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
425 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
426
427 return LLVMBuildAdd(ctx->builder, patch0_offset,
428 LLVMBuildMul(ctx->builder, patch_stride,
429 rel_patch_id, ""),
430 "");
431 }
432
433 static LLVMValueRef
434 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
435 {
436 LLVMValueRef patch0_patch_data_offset =
437 get_tcs_out_patch0_patch_data_offset(ctx);
438 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
439 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
440
441 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
442 LLVMBuildMul(ctx->builder, patch_stride,
443 rel_patch_id, ""),
444 "");
445 }
446
447 static void
448 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
449 uint32_t indirect_offset)
450 {
451 ud_info->sgpr_idx = *sgpr_idx;
452 ud_info->num_sgprs = num_sgprs;
453 ud_info->indirect = indirect_offset > 0;
454 ud_info->indirect_offset = indirect_offset;
455 *sgpr_idx += num_sgprs;
456 }
457
458 static void
459 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
460 uint8_t num_sgprs)
461 {
462 struct ac_userdata_info *ud_info =
463 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
464 assert(ud_info);
465
466 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
467 }
468
469 static void
470 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
471 uint32_t indirect_offset)
472 {
473 struct ac_userdata_info *ud_info =
474 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
475 assert(ud_info);
476
477 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
478 }
479
480 struct user_sgpr_info {
481 bool need_ring_offsets;
482 uint8_t sgpr_count;
483 bool indirect_all_descriptor_sets;
484 };
485
486 static bool needs_view_index_sgpr(struct nir_to_llvm_context *ctx,
487 gl_shader_stage stage)
488 {
489 switch (stage) {
490 case MESA_SHADER_VERTEX:
491 if (ctx->shader_info->info.needs_multiview_view_index ||
492 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
493 return true;
494 break;
495 case MESA_SHADER_TESS_EVAL:
496 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
497 return true;
498 break;
499 case MESA_SHADER_GEOMETRY:
500 case MESA_SHADER_TESS_CTRL:
501 if (ctx->shader_info->info.needs_multiview_view_index)
502 return true;
503 break;
504 default:
505 break;
506 }
507 return false;
508 }
509
510 static uint8_t
511 count_vs_user_sgprs(struct nir_to_llvm_context *ctx)
512 {
513 uint8_t count = 0;
514
515 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
516 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
517
518 return count;
519 }
520
521 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
522 gl_shader_stage stage,
523 bool has_previous_stage,
524 gl_shader_stage previous_stage,
525 bool needs_view_index,
526 struct user_sgpr_info *user_sgpr_info)
527 {
528 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
529
530 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
531 if (stage == MESA_SHADER_GEOMETRY ||
532 stage == MESA_SHADER_VERTEX ||
533 stage == MESA_SHADER_TESS_CTRL ||
534 stage == MESA_SHADER_TESS_EVAL ||
535 ctx->is_gs_copy_shader)
536 user_sgpr_info->need_ring_offsets = true;
537
538 if (stage == MESA_SHADER_FRAGMENT &&
539 ctx->shader_info->info.ps.needs_sample_positions)
540 user_sgpr_info->need_ring_offsets = true;
541
542 /* 2 user sgprs will nearly always be allocated for scratch/rings */
543 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
544 user_sgpr_info->sgpr_count += 2;
545 }
546
547 switch (stage) {
548 case MESA_SHADER_COMPUTE:
549 if (ctx->shader_info->info.cs.uses_grid_size)
550 user_sgpr_info->sgpr_count += 3;
551 break;
552 case MESA_SHADER_FRAGMENT:
553 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
554 break;
555 case MESA_SHADER_VERTEX:
556 if (!ctx->is_gs_copy_shader)
557 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
558 if (ctx->options->key.vs.as_ls)
559 user_sgpr_info->sgpr_count++;
560 break;
561 case MESA_SHADER_TESS_CTRL:
562 if (has_previous_stage) {
563 if (previous_stage == MESA_SHADER_VERTEX)
564 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
565 user_sgpr_info->sgpr_count++;
566 }
567 user_sgpr_info->sgpr_count += 4;
568 break;
569 case MESA_SHADER_TESS_EVAL:
570 user_sgpr_info->sgpr_count += 1;
571 break;
572 case MESA_SHADER_GEOMETRY:
573 if (has_previous_stage) {
574 if (previous_stage == MESA_SHADER_VERTEX) {
575 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
576 } else {
577 user_sgpr_info->sgpr_count++;
578 }
579 }
580 user_sgpr_info->sgpr_count += 2;
581 break;
582 default:
583 break;
584 }
585
586 if (needs_view_index)
587 user_sgpr_info->sgpr_count++;
588
589 if (ctx->shader_info->info.loads_push_constants)
590 user_sgpr_info->sgpr_count += 2;
591
592 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
593 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
594
595 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
596 user_sgpr_info->sgpr_count += 2;
597 user_sgpr_info->indirect_all_descriptor_sets = true;
598 } else {
599 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
600 }
601 }
602
603 static void
604 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
605 gl_shader_stage stage,
606 bool has_previous_stage,
607 gl_shader_stage previous_stage,
608 const struct user_sgpr_info *user_sgpr_info,
609 struct arg_info *args,
610 LLVMValueRef *desc_sets)
611 {
612 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
613 unsigned num_sets = ctx->options->layout ?
614 ctx->options->layout->num_sets : 0;
615 unsigned stage_mask = 1 << stage;
616
617 if (has_previous_stage)
618 stage_mask |= 1 << previous_stage;
619
620 /* 1 for each descriptor set */
621 if (!user_sgpr_info->indirect_all_descriptor_sets) {
622 for (unsigned i = 0; i < num_sets; ++i) {
623 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
624 add_array_arg(args, type,
625 &ctx->descriptor_sets[i]);
626 }
627 }
628 } else {
629 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
630 }
631
632 if (ctx->shader_info->info.loads_push_constants) {
633 /* 1 for push constants and dynamic descriptors */
634 add_array_arg(args, type, &ctx->abi.push_constants);
635 }
636 }
637
638 static void
639 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
640 gl_shader_stage stage,
641 bool has_previous_stage,
642 gl_shader_stage previous_stage,
643 struct arg_info *args)
644 {
645 if (!ctx->is_gs_copy_shader &&
646 (stage == MESA_SHADER_VERTEX ||
647 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
648 if (ctx->shader_info->info.vs.has_vertex_buffers) {
649 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
650 &ctx->vertex_buffers);
651 }
652 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
653 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
654 if (ctx->shader_info->info.vs.needs_draw_id) {
655 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
656 }
657 }
658 }
659
660 static void
661 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
662 {
663 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
664 if (!ctx->is_gs_copy_shader) {
665 if (ctx->options->key.vs.as_ls) {
666 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
667 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
668 } else {
669 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
670 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
671 }
672 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
673 }
674 }
675
676 static void
677 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
678 {
679 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
680 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
681 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
682 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
683 }
684
685 static void
686 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
687 bool has_previous_stage, gl_shader_stage previous_stage,
688 const struct user_sgpr_info *user_sgpr_info,
689 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
690 {
691 unsigned num_sets = ctx->options->layout ?
692 ctx->options->layout->num_sets : 0;
693 unsigned stage_mask = 1 << stage;
694
695 if (has_previous_stage)
696 stage_mask |= 1 << previous_stage;
697
698 if (!user_sgpr_info->indirect_all_descriptor_sets) {
699 for (unsigned i = 0; i < num_sets; ++i) {
700 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
701 set_loc_desc(ctx, i, user_sgpr_idx, 0);
702 } else
703 ctx->descriptor_sets[i] = NULL;
704 }
705 } else {
706 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
707 user_sgpr_idx, 2);
708
709 for (unsigned i = 0; i < num_sets; ++i) {
710 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
711 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
712 ctx->descriptor_sets[i] =
713 ac_build_load_to_sgpr(&ctx->ac,
714 desc_sets,
715 LLVMConstInt(ctx->ac.i32, i, false));
716
717 } else
718 ctx->descriptor_sets[i] = NULL;
719 }
720 ctx->shader_info->need_indirect_descriptor_sets = true;
721 }
722
723 if (ctx->shader_info->info.loads_push_constants) {
724 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
725 }
726 }
727
728 static void
729 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
730 gl_shader_stage stage, bool has_previous_stage,
731 gl_shader_stage previous_stage,
732 uint8_t *user_sgpr_idx)
733 {
734 if (!ctx->is_gs_copy_shader &&
735 (stage == MESA_SHADER_VERTEX ||
736 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
737 if (ctx->shader_info->info.vs.has_vertex_buffers) {
738 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
739 user_sgpr_idx, 2);
740 }
741
742 unsigned vs_num = 2;
743 if (ctx->shader_info->info.vs.needs_draw_id)
744 vs_num++;
745
746 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
747 user_sgpr_idx, vs_num);
748 }
749 }
750
751 static void create_function(struct nir_to_llvm_context *ctx,
752 gl_shader_stage stage,
753 bool has_previous_stage,
754 gl_shader_stage previous_stage)
755 {
756 uint8_t user_sgpr_idx;
757 struct user_sgpr_info user_sgpr_info;
758 struct arg_info args = {};
759 LLVMValueRef desc_sets;
760 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
761 allocate_user_sgprs(ctx, stage, has_previous_stage,
762 previous_stage, needs_view_index, &user_sgpr_info);
763
764 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
765 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
766 &ctx->ring_offsets);
767 }
768
769 switch (stage) {
770 case MESA_SHADER_COMPUTE:
771 declare_global_input_sgprs(ctx, stage, has_previous_stage,
772 previous_stage, &user_sgpr_info,
773 &args, &desc_sets);
774
775 if (ctx->shader_info->info.cs.uses_grid_size) {
776 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
777 &ctx->abi.num_work_groups);
778 }
779
780 for (int i = 0; i < 3; i++) {
781 ctx->abi.workgroup_ids[i] = NULL;
782 if (ctx->shader_info->info.cs.uses_block_id[i]) {
783 add_arg(&args, ARG_SGPR, ctx->ac.i32,
784 &ctx->abi.workgroup_ids[i]);
785 }
786 }
787
788 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
789 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
790 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
791 &ctx->abi.local_invocation_ids);
792 break;
793 case MESA_SHADER_VERTEX:
794 declare_global_input_sgprs(ctx, stage, has_previous_stage,
795 previous_stage, &user_sgpr_info,
796 &args, &desc_sets);
797 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
798 previous_stage, &args);
799
800 if (needs_view_index)
801 add_arg(&args, ARG_SGPR, ctx->ac.i32,
802 &ctx->abi.view_index);
803 if (ctx->options->key.vs.as_es)
804 add_arg(&args, ARG_SGPR, ctx->ac.i32,
805 &ctx->es2gs_offset);
806 else if (ctx->options->key.vs.as_ls)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32,
808 &ctx->ls_out_layout);
809
810 declare_vs_input_vgprs(ctx, &args);
811 break;
812 case MESA_SHADER_TESS_CTRL:
813 if (has_previous_stage) {
814 // First 6 system regs
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->merged_wave_info);
818 add_arg(&args, ARG_SGPR, ctx->ac.i32,
819 &ctx->tess_factor_offset);
820
821 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
822 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
823 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
824
825 declare_global_input_sgprs(ctx, stage,
826 has_previous_stage,
827 previous_stage,
828 &user_sgpr_info, &args,
829 &desc_sets);
830 declare_vs_specific_input_sgprs(ctx, stage,
831 has_previous_stage,
832 previous_stage, &args);
833
834 add_arg(&args, ARG_SGPR, ctx->ac.i32,
835 &ctx->ls_out_layout);
836
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->tcs_offchip_layout);
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->tcs_out_offsets);
841 add_arg(&args, ARG_SGPR, ctx->ac.i32,
842 &ctx->tcs_out_layout);
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->tcs_in_layout);
845 if (needs_view_index)
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->abi.view_index);
848
849 add_arg(&args, ARG_VGPR, ctx->ac.i32,
850 &ctx->abi.tcs_patch_id);
851 add_arg(&args, ARG_VGPR, ctx->ac.i32,
852 &ctx->abi.tcs_rel_ids);
853
854 declare_vs_input_vgprs(ctx, &args);
855 } else {
856 declare_global_input_sgprs(ctx, stage,
857 has_previous_stage,
858 previous_stage,
859 &user_sgpr_info, &args,
860 &desc_sets);
861
862 add_arg(&args, ARG_SGPR, ctx->ac.i32,
863 &ctx->tcs_offchip_layout);
864 add_arg(&args, ARG_SGPR, ctx->ac.i32,
865 &ctx->tcs_out_offsets);
866 add_arg(&args, ARG_SGPR, ctx->ac.i32,
867 &ctx->tcs_out_layout);
868 add_arg(&args, ARG_SGPR, ctx->ac.i32,
869 &ctx->tcs_in_layout);
870 if (needs_view_index)
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->abi.view_index);
873
874 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tess_factor_offset);
877 add_arg(&args, ARG_VGPR, ctx->ac.i32,
878 &ctx->abi.tcs_patch_id);
879 add_arg(&args, ARG_VGPR, ctx->ac.i32,
880 &ctx->abi.tcs_rel_ids);
881 }
882 break;
883 case MESA_SHADER_TESS_EVAL:
884 declare_global_input_sgprs(ctx, stage, has_previous_stage,
885 previous_stage, &user_sgpr_info,
886 &args, &desc_sets);
887
888 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
889 if (needs_view_index)
890 add_arg(&args, ARG_SGPR, ctx->ac.i32,
891 &ctx->abi.view_index);
892
893 if (ctx->options->key.tes.as_es) {
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
895 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
896 add_arg(&args, ARG_SGPR, ctx->ac.i32,
897 &ctx->es2gs_offset);
898 } else {
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
900 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
901 }
902 declare_tes_input_vgprs(ctx, &args);
903 break;
904 case MESA_SHADER_GEOMETRY:
905 if (has_previous_stage) {
906 // First 6 system regs
907 add_arg(&args, ARG_SGPR, ctx->ac.i32,
908 &ctx->gs2vs_offset);
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->merged_wave_info);
911 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
912
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
915 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
916
917 declare_global_input_sgprs(ctx, stage,
918 has_previous_stage,
919 previous_stage,
920 &user_sgpr_info, &args,
921 &desc_sets);
922
923 if (previous_stage == MESA_SHADER_TESS_EVAL) {
924 add_arg(&args, ARG_SGPR, ctx->ac.i32,
925 &ctx->tcs_offchip_layout);
926 } else {
927 declare_vs_specific_input_sgprs(ctx, stage,
928 has_previous_stage,
929 previous_stage,
930 &args);
931 }
932
933 add_arg(&args, ARG_SGPR, ctx->ac.i32,
934 &ctx->gsvs_ring_stride);
935 add_arg(&args, ARG_SGPR, ctx->ac.i32,
936 &ctx->gsvs_num_entries);
937 if (needs_view_index)
938 add_arg(&args, ARG_SGPR, ctx->ac.i32,
939 &ctx->abi.view_index);
940
941 add_arg(&args, ARG_VGPR, ctx->ac.i32,
942 &ctx->gs_vtx_offset[0]);
943 add_arg(&args, ARG_VGPR, ctx->ac.i32,
944 &ctx->gs_vtx_offset[2]);
945 add_arg(&args, ARG_VGPR, ctx->ac.i32,
946 &ctx->abi.gs_prim_id);
947 add_arg(&args, ARG_VGPR, ctx->ac.i32,
948 &ctx->abi.gs_invocation_id);
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->gs_vtx_offset[4]);
951
952 if (previous_stage == MESA_SHADER_VERTEX) {
953 declare_vs_input_vgprs(ctx, &args);
954 } else {
955 declare_tes_input_vgprs(ctx, &args);
956 }
957 } else {
958 declare_global_input_sgprs(ctx, stage,
959 has_previous_stage,
960 previous_stage,
961 &user_sgpr_info, &args,
962 &desc_sets);
963
964 add_arg(&args, ARG_SGPR, ctx->ac.i32,
965 &ctx->gsvs_ring_stride);
966 add_arg(&args, ARG_SGPR, ctx->ac.i32,
967 &ctx->gsvs_num_entries);
968 if (needs_view_index)
969 add_arg(&args, ARG_SGPR, ctx->ac.i32,
970 &ctx->abi.view_index);
971
972 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
973 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
974 add_arg(&args, ARG_VGPR, ctx->ac.i32,
975 &ctx->gs_vtx_offset[0]);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[1]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->abi.gs_prim_id);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->gs_vtx_offset[2]);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[3]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[4]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[5]);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->abi.gs_invocation_id);
990 }
991 break;
992 case MESA_SHADER_FRAGMENT:
993 declare_global_input_sgprs(ctx, stage, has_previous_stage,
994 previous_stage, &user_sgpr_info,
995 &args, &desc_sets);
996
997 if (ctx->shader_info->info.ps.needs_sample_positions)
998 add_arg(&args, ARG_SGPR, ctx->ac.i32,
999 &ctx->sample_pos_offset);
1000
1001 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1002 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1003 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1005 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1009 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1010 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1014 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1018 break;
1019 default:
1020 unreachable("Shader stage not implemented");
1021 }
1022
1023 ctx->main_function = create_llvm_function(
1024 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1025 ctx->max_workgroup_size,
1026 ctx->options->unsafe_math);
1027 set_llvm_calling_convention(ctx->main_function, stage);
1028
1029
1030 ctx->shader_info->num_input_vgprs = 0;
1031 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1032
1033 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1034
1035 if (ctx->stage != MESA_SHADER_FRAGMENT)
1036 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1037
1038 assign_arguments(ctx->main_function, &args);
1039
1040 user_sgpr_idx = 0;
1041
1042 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1043 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1044 &user_sgpr_idx, 2);
1045 if (ctx->options->supports_spill) {
1046 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1047 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1048 NULL, 0, AC_FUNC_ATTR_READNONE);
1049 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1050 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1051 }
1052 }
1053
1054 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1055 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1056 if (has_previous_stage)
1057 user_sgpr_idx = 0;
1058
1059 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1060 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1061
1062 switch (stage) {
1063 case MESA_SHADER_COMPUTE:
1064 if (ctx->shader_info->info.cs.uses_grid_size) {
1065 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1066 &user_sgpr_idx, 3);
1067 }
1068 break;
1069 case MESA_SHADER_VERTEX:
1070 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1071 previous_stage, &user_sgpr_idx);
1072 if (ctx->abi.view_index)
1073 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1074 if (ctx->options->key.vs.as_ls) {
1075 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1076 &user_sgpr_idx, 1);
1077 }
1078 if (ctx->options->key.vs.as_ls)
1079 ac_declare_lds_as_pointer(&ctx->ac);
1080 break;
1081 case MESA_SHADER_TESS_CTRL:
1082 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1083 previous_stage, &user_sgpr_idx);
1084 if (has_previous_stage)
1085 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1086 &user_sgpr_idx, 1);
1087 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1088 if (ctx->abi.view_index)
1089 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1090 ac_declare_lds_as_pointer(&ctx->ac);
1091 break;
1092 case MESA_SHADER_TESS_EVAL:
1093 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1094 if (ctx->abi.view_index)
1095 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1096 break;
1097 case MESA_SHADER_GEOMETRY:
1098 if (has_previous_stage) {
1099 if (previous_stage == MESA_SHADER_VERTEX)
1100 set_vs_specific_input_locs(ctx, stage,
1101 has_previous_stage,
1102 previous_stage,
1103 &user_sgpr_idx);
1104 else
1105 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1106 &user_sgpr_idx, 1);
1107 }
1108 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1109 &user_sgpr_idx, 2);
1110 if (ctx->abi.view_index)
1111 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1112 if (has_previous_stage)
1113 ac_declare_lds_as_pointer(&ctx->ac);
1114 break;
1115 case MESA_SHADER_FRAGMENT:
1116 if (ctx->shader_info->info.ps.needs_sample_positions) {
1117 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1118 &user_sgpr_idx, 1);
1119 }
1120 break;
1121 default:
1122 unreachable("Shader stage not implemented");
1123 }
1124
1125 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1126 }
1127
1128 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1129 LLVMValueRef value, unsigned count)
1130 {
1131 unsigned num_components = ac_get_llvm_num_components(value);
1132 if (count == num_components)
1133 return value;
1134
1135 LLVMValueRef masks[] = {
1136 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1137 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1138
1139 if (count == 1)
1140 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1141 "");
1142
1143 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1144 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1145 }
1146
1147 static void
1148 build_store_values_extended(struct ac_llvm_context *ac,
1149 LLVMValueRef *values,
1150 unsigned value_count,
1151 unsigned value_stride,
1152 LLVMValueRef vec)
1153 {
1154 LLVMBuilderRef builder = ac->builder;
1155 unsigned i;
1156
1157 for (i = 0; i < value_count; i++) {
1158 LLVMValueRef ptr = values[i * value_stride];
1159 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1160 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1161 LLVMBuildStore(builder, value, ptr);
1162 }
1163 }
1164
1165 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1166 const nir_ssa_def *def)
1167 {
1168 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1169 if (def->num_components > 1) {
1170 type = LLVMVectorType(type, def->num_components);
1171 }
1172 return type;
1173 }
1174
1175 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1176 {
1177 assert(src.is_ssa);
1178 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1179 return (LLVMValueRef)entry->data;
1180 }
1181
1182
1183 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1184 const struct nir_block *b)
1185 {
1186 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1187 return (LLVMBasicBlockRef)entry->data;
1188 }
1189
1190 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1191 nir_alu_src src,
1192 unsigned num_components)
1193 {
1194 LLVMValueRef value = get_src(ctx, src.src);
1195 bool need_swizzle = false;
1196
1197 assert(value);
1198 LLVMTypeRef type = LLVMTypeOf(value);
1199 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1200 ? LLVMGetVectorSize(type)
1201 : 1;
1202
1203 for (unsigned i = 0; i < num_components; ++i) {
1204 assert(src.swizzle[i] < src_components);
1205 if (src.swizzle[i] != i)
1206 need_swizzle = true;
1207 }
1208
1209 if (need_swizzle || num_components != src_components) {
1210 LLVMValueRef masks[] = {
1211 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1212 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1213 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1214 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1215
1216 if (src_components > 1 && num_components == 1) {
1217 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1218 masks[0], "");
1219 } else if (src_components == 1 && num_components > 1) {
1220 LLVMValueRef values[] = {value, value, value, value};
1221 value = ac_build_gather_values(&ctx->ac, values, num_components);
1222 } else {
1223 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1224 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1225 swizzle, "");
1226 }
1227 }
1228 assert(!src.negate);
1229 assert(!src.abs);
1230 return value;
1231 }
1232
1233 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1234 LLVMIntPredicate pred, LLVMValueRef src0,
1235 LLVMValueRef src1)
1236 {
1237 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1238 return LLVMBuildSelect(ctx->builder, result,
1239 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1240 ctx->i32_0, "");
1241 }
1242
1243 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1244 LLVMRealPredicate pred, LLVMValueRef src0,
1245 LLVMValueRef src1)
1246 {
1247 LLVMValueRef result;
1248 src0 = ac_to_float(ctx, src0);
1249 src1 = ac_to_float(ctx, src1);
1250 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1251 return LLVMBuildSelect(ctx->builder, result,
1252 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1253 ctx->i32_0, "");
1254 }
1255
1256 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1257 const char *intrin,
1258 LLVMTypeRef result_type,
1259 LLVMValueRef src0)
1260 {
1261 char name[64];
1262 LLVMValueRef params[] = {
1263 ac_to_float(ctx, src0),
1264 };
1265
1266 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1267 ac_get_elem_bits(ctx, result_type));
1268 assert(length < sizeof(name));
1269 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1270 }
1271
1272 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1273 const char *intrin,
1274 LLVMTypeRef result_type,
1275 LLVMValueRef src0, LLVMValueRef src1)
1276 {
1277 char name[64];
1278 LLVMValueRef params[] = {
1279 ac_to_float(ctx, src0),
1280 ac_to_float(ctx, src1),
1281 };
1282
1283 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1284 ac_get_elem_bits(ctx, result_type));
1285 assert(length < sizeof(name));
1286 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1287 }
1288
1289 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1290 const char *intrin,
1291 LLVMTypeRef result_type,
1292 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1293 {
1294 char name[64];
1295 LLVMValueRef params[] = {
1296 ac_to_float(ctx, src0),
1297 ac_to_float(ctx, src1),
1298 ac_to_float(ctx, src2),
1299 };
1300
1301 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1302 ac_get_elem_bits(ctx, result_type));
1303 assert(length < sizeof(name));
1304 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1305 }
1306
1307 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1308 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1309 {
1310 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1311 ctx->i32_0, "");
1312 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1313 }
1314
1315 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1316 LLVMIntPredicate pred,
1317 LLVMValueRef src0, LLVMValueRef src1)
1318 {
1319 return LLVMBuildSelect(ctx->builder,
1320 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1321 src0,
1322 src1, "");
1323
1324 }
1325 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1326 LLVMValueRef src0)
1327 {
1328 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1329 LLVMBuildNeg(ctx->builder, src0, ""));
1330 }
1331
1332 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1333 LLVMValueRef src0,
1334 unsigned bitsize)
1335 {
1336 LLVMValueRef cmp, val, zero, one;
1337 LLVMTypeRef type;
1338
1339 if (bitsize == 32) {
1340 type = ctx->f32;
1341 zero = ctx->f32_0;
1342 one = ctx->f32_1;
1343 } else {
1344 type = ctx->f64;
1345 zero = ctx->f64_0;
1346 one = ctx->f64_1;
1347 }
1348
1349 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1350 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1351 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1352 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1353 return val;
1354 }
1355
1356 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1357 LLVMValueRef src0, unsigned bitsize)
1358 {
1359 LLVMValueRef cmp, val, zero, one;
1360 LLVMTypeRef type;
1361
1362 if (bitsize == 32) {
1363 type = ctx->i32;
1364 zero = ctx->i32_0;
1365 one = ctx->i32_1;
1366 } else {
1367 type = ctx->i64;
1368 zero = ctx->i64_0;
1369 one = ctx->i64_1;
1370 }
1371
1372 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1373 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1374 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1375 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1376 return val;
1377 }
1378
1379 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1380 LLVMValueRef src0, unsigned bitsize)
1381 {
1382 LLVMTypeRef type;
1383 char *intr;
1384
1385 if (bitsize == 32) {
1386 intr = "llvm.floor.f32";
1387 type = ctx->f32;
1388 } else {
1389 intr = "llvm.floor.f64";
1390 type = ctx->f64;
1391 }
1392
1393 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1394 LLVMValueRef params[] = {
1395 fsrc0,
1396 };
1397 LLVMValueRef floor = ac_build_intrinsic(ctx, intr, type, params, 1,
1398 AC_FUNC_ATTR_READNONE);
1399 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1400 }
1401
1402 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1403 const char *intrin,
1404 LLVMValueRef src0, LLVMValueRef src1)
1405 {
1406 LLVMTypeRef ret_type;
1407 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1408 LLVMValueRef res;
1409 LLVMValueRef params[] = { src0, src1 };
1410 ret_type = LLVMStructTypeInContext(ctx->context, types,
1411 2, true);
1412
1413 res = ac_build_intrinsic(ctx, intrin, ret_type,
1414 params, 2, AC_FUNC_ATTR_READNONE);
1415
1416 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1417 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1418 return res;
1419 }
1420
1421 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1422 LLVMValueRef src0)
1423 {
1424 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1425 }
1426
1427 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1428 LLVMValueRef src0)
1429 {
1430 src0 = ac_to_float(ctx, src0);
1431 return LLVMBuildSExt(ctx->builder,
1432 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1433 ctx->i32, "");
1434 }
1435
1436 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1437 LLVMValueRef src0,
1438 unsigned bitsize)
1439 {
1440 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1441
1442 if (bitsize == 32)
1443 return result;
1444
1445 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1446 }
1447
1448 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1449 LLVMValueRef src0)
1450 {
1451 return LLVMBuildSExt(ctx->builder,
1452 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1453 ctx->i32, "");
1454 }
1455
1456 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1457 LLVMValueRef src0)
1458 {
1459 LLVMValueRef result;
1460 LLVMValueRef cond = NULL;
1461
1462 src0 = ac_to_float(&ctx->ac, src0);
1463 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1464
1465 if (ctx->options->chip_class >= VI) {
1466 LLVMValueRef args[2];
1467 /* Check if the result is a denormal - and flush to 0 if so. */
1468 args[0] = result;
1469 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1470 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1471 }
1472
1473 /* need to convert back up to f32 */
1474 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1475
1476 if (ctx->options->chip_class >= VI)
1477 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1478 else {
1479 /* for SI/CIK */
1480 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1481 * so compare the result and flush to 0 if it's smaller.
1482 */
1483 LLVMValueRef temp, cond2;
1484 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1485 ctx->ac.f32, result);
1486 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1487 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1488 temp, "");
1489 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1490 temp, ctx->ac.f32_0, "");
1491 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1492 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1493 }
1494 return result;
1495 }
1496
1497 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1498 LLVMValueRef src0, LLVMValueRef src1)
1499 {
1500 LLVMValueRef dst64, result;
1501 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1502 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1503
1504 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1505 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1506 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1507 return result;
1508 }
1509
1510 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1511 LLVMValueRef src0, LLVMValueRef src1)
1512 {
1513 LLVMValueRef dst64, result;
1514 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1515 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1516
1517 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1518 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1519 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1520 return result;
1521 }
1522
1523 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1524 bool is_signed,
1525 const LLVMValueRef srcs[3])
1526 {
1527 LLVMValueRef result;
1528 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1529
1530 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1531 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1532 return result;
1533 }
1534
1535 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1536 LLVMValueRef src0, LLVMValueRef src1,
1537 LLVMValueRef src2, LLVMValueRef src3)
1538 {
1539 LLVMValueRef bfi_args[3], result;
1540
1541 bfi_args[0] = LLVMBuildShl(ctx->builder,
1542 LLVMBuildSub(ctx->builder,
1543 LLVMBuildShl(ctx->builder,
1544 ctx->i32_1,
1545 src3, ""),
1546 ctx->i32_1, ""),
1547 src2, "");
1548 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1549 bfi_args[2] = src0;
1550
1551 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1552
1553 /* Calculate:
1554 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1555 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1556 */
1557 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1558 LLVMBuildAnd(ctx->builder, bfi_args[0],
1559 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1560
1561 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1562 return result;
1563 }
1564
1565 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1566 LLVMValueRef src0)
1567 {
1568 LLVMValueRef comp[2];
1569
1570 src0 = ac_to_float(ctx, src0);
1571 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1572 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1573
1574 return ac_build_cvt_pkrtz_f16(ctx, comp);
1575 }
1576
1577 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1578 LLVMValueRef src0)
1579 {
1580 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1581 LLVMValueRef temps[2], result, val;
1582 int i;
1583
1584 for (i = 0; i < 2; i++) {
1585 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1586 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1587 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1588 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1589 }
1590
1591 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1592 ctx->i32_0, "");
1593 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1594 ctx->i32_1, "");
1595 return result;
1596 }
1597
1598 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1599 nir_op op,
1600 LLVMValueRef src0)
1601 {
1602 unsigned mask;
1603 int idx;
1604 LLVMValueRef result;
1605
1606 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1607 mask = AC_TID_MASK_LEFT;
1608 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1609 mask = AC_TID_MASK_TOP;
1610 else
1611 mask = AC_TID_MASK_TOP_LEFT;
1612
1613 /* for DDX we want to next X pixel, DDY next Y pixel. */
1614 if (op == nir_op_fddx_fine ||
1615 op == nir_op_fddx_coarse ||
1616 op == nir_op_fddx)
1617 idx = 1;
1618 else
1619 idx = 2;
1620
1621 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1622 return result;
1623 }
1624
1625 /*
1626 * this takes an I,J coordinate pair,
1627 * and works out the X and Y derivatives.
1628 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1629 */
1630 static LLVMValueRef emit_ddxy_interp(
1631 struct ac_nir_context *ctx,
1632 LLVMValueRef interp_ij)
1633 {
1634 LLVMValueRef result[4], a;
1635 unsigned i;
1636
1637 for (i = 0; i < 2; i++) {
1638 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1639 LLVMConstInt(ctx->ac.i32, i, false), "");
1640 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1641 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1642 }
1643 return ac_build_gather_values(&ctx->ac, result, 4);
1644 }
1645
1646 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1647 {
1648 LLVMValueRef src[4], result = NULL;
1649 unsigned num_components = instr->dest.dest.ssa.num_components;
1650 unsigned src_components;
1651 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1652
1653 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1654 switch (instr->op) {
1655 case nir_op_vec2:
1656 case nir_op_vec3:
1657 case nir_op_vec4:
1658 src_components = 1;
1659 break;
1660 case nir_op_pack_half_2x16:
1661 src_components = 2;
1662 break;
1663 case nir_op_unpack_half_2x16:
1664 src_components = 1;
1665 break;
1666 default:
1667 src_components = num_components;
1668 break;
1669 }
1670 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1671 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1672
1673 switch (instr->op) {
1674 case nir_op_fmov:
1675 case nir_op_imov:
1676 result = src[0];
1677 break;
1678 case nir_op_fneg:
1679 src[0] = ac_to_float(&ctx->ac, src[0]);
1680 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1681 break;
1682 case nir_op_ineg:
1683 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1684 break;
1685 case nir_op_inot:
1686 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1687 break;
1688 case nir_op_iadd:
1689 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1690 break;
1691 case nir_op_fadd:
1692 src[0] = ac_to_float(&ctx->ac, src[0]);
1693 src[1] = ac_to_float(&ctx->ac, src[1]);
1694 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1695 break;
1696 case nir_op_fsub:
1697 src[0] = ac_to_float(&ctx->ac, src[0]);
1698 src[1] = ac_to_float(&ctx->ac, src[1]);
1699 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1700 break;
1701 case nir_op_isub:
1702 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1703 break;
1704 case nir_op_imul:
1705 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1706 break;
1707 case nir_op_imod:
1708 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1709 break;
1710 case nir_op_umod:
1711 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1712 break;
1713 case nir_op_fmod:
1714 src[0] = ac_to_float(&ctx->ac, src[0]);
1715 src[1] = ac_to_float(&ctx->ac, src[1]);
1716 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1717 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1718 ac_to_float_type(&ctx->ac, def_type), result);
1719 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1720 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1721 break;
1722 case nir_op_frem:
1723 src[0] = ac_to_float(&ctx->ac, src[0]);
1724 src[1] = ac_to_float(&ctx->ac, src[1]);
1725 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1726 break;
1727 case nir_op_irem:
1728 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1729 break;
1730 case nir_op_idiv:
1731 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1732 break;
1733 case nir_op_udiv:
1734 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1735 break;
1736 case nir_op_fmul:
1737 src[0] = ac_to_float(&ctx->ac, src[0]);
1738 src[1] = ac_to_float(&ctx->ac, src[1]);
1739 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1740 break;
1741 case nir_op_frcp:
1742 src[0] = ac_to_float(&ctx->ac, src[0]);
1743 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1744 src[0]);
1745 break;
1746 case nir_op_iand:
1747 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1748 break;
1749 case nir_op_ior:
1750 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1751 break;
1752 case nir_op_ixor:
1753 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1754 break;
1755 case nir_op_ishl:
1756 result = LLVMBuildShl(ctx->ac.builder, src[0],
1757 LLVMBuildZExt(ctx->ac.builder, src[1],
1758 LLVMTypeOf(src[0]), ""),
1759 "");
1760 break;
1761 case nir_op_ishr:
1762 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1763 LLVMBuildZExt(ctx->ac.builder, src[1],
1764 LLVMTypeOf(src[0]), ""),
1765 "");
1766 break;
1767 case nir_op_ushr:
1768 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1769 LLVMBuildZExt(ctx->ac.builder, src[1],
1770 LLVMTypeOf(src[0]), ""),
1771 "");
1772 break;
1773 case nir_op_ilt:
1774 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1775 break;
1776 case nir_op_ine:
1777 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1778 break;
1779 case nir_op_ieq:
1780 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1781 break;
1782 case nir_op_ige:
1783 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1784 break;
1785 case nir_op_ult:
1786 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1787 break;
1788 case nir_op_uge:
1789 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1790 break;
1791 case nir_op_feq:
1792 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1793 break;
1794 case nir_op_fne:
1795 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1796 break;
1797 case nir_op_flt:
1798 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1799 break;
1800 case nir_op_fge:
1801 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1802 break;
1803 case nir_op_fabs:
1804 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1805 ac_to_float_type(&ctx->ac, def_type), src[0]);
1806 break;
1807 case nir_op_iabs:
1808 result = emit_iabs(&ctx->ac, src[0]);
1809 break;
1810 case nir_op_imax:
1811 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1812 break;
1813 case nir_op_imin:
1814 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1815 break;
1816 case nir_op_umax:
1817 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1818 break;
1819 case nir_op_umin:
1820 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1821 break;
1822 case nir_op_isign:
1823 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1824 break;
1825 case nir_op_fsign:
1826 src[0] = ac_to_float(&ctx->ac, src[0]);
1827 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1828 break;
1829 case nir_op_ffloor:
1830 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1831 ac_to_float_type(&ctx->ac, def_type), src[0]);
1832 break;
1833 case nir_op_ftrunc:
1834 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1835 ac_to_float_type(&ctx->ac, def_type), src[0]);
1836 break;
1837 case nir_op_fceil:
1838 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1839 ac_to_float_type(&ctx->ac, def_type), src[0]);
1840 break;
1841 case nir_op_fround_even:
1842 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1843 ac_to_float_type(&ctx->ac, def_type),src[0]);
1844 break;
1845 case nir_op_ffract:
1846 result = emit_ffract(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1847 break;
1848 case nir_op_fsin:
1849 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1850 ac_to_float_type(&ctx->ac, def_type), src[0]);
1851 break;
1852 case nir_op_fcos:
1853 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1854 ac_to_float_type(&ctx->ac, def_type), src[0]);
1855 break;
1856 case nir_op_fsqrt:
1857 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1858 ac_to_float_type(&ctx->ac, def_type), src[0]);
1859 break;
1860 case nir_op_fexp2:
1861 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1862 ac_to_float_type(&ctx->ac, def_type), src[0]);
1863 break;
1864 case nir_op_flog2:
1865 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1866 ac_to_float_type(&ctx->ac, def_type), src[0]);
1867 break;
1868 case nir_op_frsq:
1869 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1870 ac_to_float_type(&ctx->ac, def_type), src[0]);
1871 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1872 result);
1873 break;
1874 case nir_op_fpow:
1875 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1876 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1877 break;
1878 case nir_op_fmax:
1879 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1880 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1881 if (ctx->ac.chip_class < GFX9 &&
1882 instr->dest.dest.ssa.bit_size == 32) {
1883 /* Only pre-GFX9 chips do not flush denorms. */
1884 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1885 ac_to_float_type(&ctx->ac, def_type),
1886 result);
1887 }
1888 break;
1889 case nir_op_fmin:
1890 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1891 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1892 if (ctx->ac.chip_class < GFX9 &&
1893 instr->dest.dest.ssa.bit_size == 32) {
1894 /* Only pre-GFX9 chips do not flush denorms. */
1895 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1896 ac_to_float_type(&ctx->ac, def_type),
1897 result);
1898 }
1899 break;
1900 case nir_op_ffma:
1901 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1902 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1903 break;
1904 case nir_op_ibitfield_extract:
1905 result = emit_bitfield_extract(&ctx->ac, true, src);
1906 break;
1907 case nir_op_ubitfield_extract:
1908 result = emit_bitfield_extract(&ctx->ac, false, src);
1909 break;
1910 case nir_op_bitfield_insert:
1911 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1912 break;
1913 case nir_op_bitfield_reverse:
1914 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1915 break;
1916 case nir_op_bit_count:
1917 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1918 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1919 else {
1920 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1921 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1922 }
1923 break;
1924 case nir_op_vec2:
1925 case nir_op_vec3:
1926 case nir_op_vec4:
1927 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1928 src[i] = ac_to_integer(&ctx->ac, src[i]);
1929 result = ac_build_gather_values(&ctx->ac, src, num_components);
1930 break;
1931 case nir_op_f2i32:
1932 case nir_op_f2i64:
1933 src[0] = ac_to_float(&ctx->ac, src[0]);
1934 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1935 break;
1936 case nir_op_f2u32:
1937 case nir_op_f2u64:
1938 src[0] = ac_to_float(&ctx->ac, src[0]);
1939 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1940 break;
1941 case nir_op_i2f32:
1942 case nir_op_i2f64:
1943 src[0] = ac_to_integer(&ctx->ac, src[0]);
1944 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1945 break;
1946 case nir_op_u2f32:
1947 case nir_op_u2f64:
1948 src[0] = ac_to_integer(&ctx->ac, src[0]);
1949 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1950 break;
1951 case nir_op_f2f64:
1952 src[0] = ac_to_float(&ctx->ac, src[0]);
1953 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1954 break;
1955 case nir_op_f2f32:
1956 src[0] = ac_to_float(&ctx->ac, src[0]);
1957 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1958 break;
1959 case nir_op_u2u32:
1960 case nir_op_u2u64:
1961 src[0] = ac_to_integer(&ctx->ac, src[0]);
1962 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1963 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1964 else
1965 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1966 break;
1967 case nir_op_i2i32:
1968 case nir_op_i2i64:
1969 src[0] = ac_to_integer(&ctx->ac, src[0]);
1970 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1971 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1972 else
1973 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1974 break;
1975 case nir_op_bcsel:
1976 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1977 break;
1978 case nir_op_find_lsb:
1979 src[0] = ac_to_integer(&ctx->ac, src[0]);
1980 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1981 break;
1982 case nir_op_ufind_msb:
1983 src[0] = ac_to_integer(&ctx->ac, src[0]);
1984 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1985 break;
1986 case nir_op_ifind_msb:
1987 src[0] = ac_to_integer(&ctx->ac, src[0]);
1988 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1989 break;
1990 case nir_op_uadd_carry:
1991 src[0] = ac_to_integer(&ctx->ac, src[0]);
1992 src[1] = ac_to_integer(&ctx->ac, src[1]);
1993 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1994 break;
1995 case nir_op_usub_borrow:
1996 src[0] = ac_to_integer(&ctx->ac, src[0]);
1997 src[1] = ac_to_integer(&ctx->ac, src[1]);
1998 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1999 break;
2000 case nir_op_b2f:
2001 result = emit_b2f(&ctx->ac, src[0]);
2002 break;
2003 case nir_op_f2b:
2004 result = emit_f2b(&ctx->ac, src[0]);
2005 break;
2006 case nir_op_b2i:
2007 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2008 break;
2009 case nir_op_i2b:
2010 src[0] = ac_to_integer(&ctx->ac, src[0]);
2011 result = emit_i2b(&ctx->ac, src[0]);
2012 break;
2013 case nir_op_fquantize2f16:
2014 result = emit_f2f16(ctx->nctx, src[0]);
2015 break;
2016 case nir_op_umul_high:
2017 src[0] = ac_to_integer(&ctx->ac, src[0]);
2018 src[1] = ac_to_integer(&ctx->ac, src[1]);
2019 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2020 break;
2021 case nir_op_imul_high:
2022 src[0] = ac_to_integer(&ctx->ac, src[0]);
2023 src[1] = ac_to_integer(&ctx->ac, src[1]);
2024 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2025 break;
2026 case nir_op_pack_half_2x16:
2027 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2028 break;
2029 case nir_op_unpack_half_2x16:
2030 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2031 break;
2032 case nir_op_fddx:
2033 case nir_op_fddy:
2034 case nir_op_fddx_fine:
2035 case nir_op_fddy_fine:
2036 case nir_op_fddx_coarse:
2037 case nir_op_fddy_coarse:
2038 result = emit_ddxy(ctx, instr->op, src[0]);
2039 break;
2040
2041 case nir_op_unpack_64_2x32_split_x: {
2042 assert(ac_get_llvm_num_components(src[0]) == 1);
2043 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2044 ctx->ac.v2i32,
2045 "");
2046 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2047 ctx->ac.i32_0, "");
2048 break;
2049 }
2050
2051 case nir_op_unpack_64_2x32_split_y: {
2052 assert(ac_get_llvm_num_components(src[0]) == 1);
2053 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2054 ctx->ac.v2i32,
2055 "");
2056 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2057 ctx->ac.i32_1, "");
2058 break;
2059 }
2060
2061 case nir_op_pack_64_2x32_split: {
2062 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2063 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2064 src[0], ctx->ac.i32_0, "");
2065 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2066 src[1], ctx->ac.i32_1, "");
2067 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2068 break;
2069 }
2070
2071 default:
2072 fprintf(stderr, "Unknown NIR alu instr: ");
2073 nir_print_instr(&instr->instr, stderr);
2074 fprintf(stderr, "\n");
2075 abort();
2076 }
2077
2078 if (result) {
2079 assert(instr->dest.dest.is_ssa);
2080 result = ac_to_integer(&ctx->ac, result);
2081 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2082 result);
2083 }
2084 }
2085
2086 static void visit_load_const(struct ac_nir_context *ctx,
2087 const nir_load_const_instr *instr)
2088 {
2089 LLVMValueRef values[4], value = NULL;
2090 LLVMTypeRef element_type =
2091 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2092
2093 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2094 switch (instr->def.bit_size) {
2095 case 32:
2096 values[i] = LLVMConstInt(element_type,
2097 instr->value.u32[i], false);
2098 break;
2099 case 64:
2100 values[i] = LLVMConstInt(element_type,
2101 instr->value.u64[i], false);
2102 break;
2103 default:
2104 fprintf(stderr,
2105 "unsupported nir load_const bit_size: %d\n",
2106 instr->def.bit_size);
2107 abort();
2108 }
2109 }
2110 if (instr->def.num_components > 1) {
2111 value = LLVMConstVector(values, instr->def.num_components);
2112 } else
2113 value = values[0];
2114
2115 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2116 }
2117
2118 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2119 LLVMTypeRef type)
2120 {
2121 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2122 return LLVMBuildBitCast(ctx->builder, ptr,
2123 LLVMPointerType(type, addr_space), "");
2124 }
2125
2126 static LLVMValueRef
2127 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2128 {
2129 LLVMValueRef size =
2130 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2131 LLVMConstInt(ctx->ac.i32, 2, false), "");
2132
2133 /* VI only */
2134 if (ctx->ac.chip_class == VI && in_elements) {
2135 /* On VI, the descriptor contains the size in bytes,
2136 * but TXQ must return the size in elements.
2137 * The stride is always non-zero for resources using TXQ.
2138 */
2139 LLVMValueRef stride =
2140 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2141 ctx->ac.i32_1, "");
2142 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2143 LLVMConstInt(ctx->ac.i32, 16, false), "");
2144 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2145 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2146
2147 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2148 }
2149 return size;
2150 }
2151
2152 /**
2153 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2154 * intrinsic names).
2155 */
2156 static void build_int_type_name(
2157 LLVMTypeRef type,
2158 char *buf, unsigned bufsize)
2159 {
2160 assert(bufsize >= 6);
2161
2162 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2163 snprintf(buf, bufsize, "v%ui32",
2164 LLVMGetVectorSize(type));
2165 else
2166 strcpy(buf, "i32");
2167 }
2168
2169 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2170 struct ac_image_args *args,
2171 const nir_tex_instr *instr)
2172 {
2173 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2174 LLVMValueRef coord = args->addr;
2175 LLVMValueRef half_texel[2];
2176 LLVMValueRef compare_cube_wa = NULL;
2177 LLVMValueRef result;
2178 int c;
2179 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2180
2181 //TODO Rect
2182 {
2183 struct ac_image_args txq_args = { 0 };
2184
2185 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2186 txq_args.opcode = ac_image_get_resinfo;
2187 txq_args.dmask = 0xf;
2188 txq_args.addr = ctx->i32_0;
2189 txq_args.resource = args->resource;
2190 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2191
2192 for (c = 0; c < 2; c++) {
2193 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2194 LLVMConstInt(ctx->i32, c, false), "");
2195 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2196 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2197 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2198 LLVMConstReal(ctx->f32, -0.5), "");
2199 }
2200 }
2201
2202 LLVMValueRef orig_coords = args->addr;
2203
2204 for (c = 0; c < 2; c++) {
2205 LLVMValueRef tmp;
2206 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2207 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2208 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2209 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2210 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2211 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2212 }
2213
2214
2215 /*
2216 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2217 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2218 * workaround by sampling using a scaled type and converting.
2219 * This is taken from amdgpu-pro shaders.
2220 */
2221 /* NOTE this produces some ugly code compared to amdgpu-pro,
2222 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2223 * and then reads them back. -pro generates two selects,
2224 * one s_cmp for the descriptor rewriting
2225 * one v_cmp for the coordinate and result changes.
2226 */
2227 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2228 LLVMValueRef tmp, tmp2;
2229
2230 /* workaround 8/8/8/8 uint/sint cube gather bug */
2231 /* first detect it then change to a scaled read and f2i */
2232 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2233 tmp2 = tmp;
2234
2235 /* extract the DATA_FORMAT */
2236 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2237 LLVMConstInt(ctx->i32, 6, false), false);
2238
2239 /* is the DATA_FORMAT == 8_8_8_8 */
2240 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2241
2242 if (stype == GLSL_TYPE_UINT)
2243 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2244 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2245 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2246 else
2247 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2248 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2249 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2250
2251 /* replace the NUM FORMAT in the descriptor */
2252 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2253 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2254
2255 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2256
2257 /* don't modify the coordinates for this case */
2258 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2259 }
2260 args->addr = coord;
2261 result = ac_build_image_opcode(ctx, args);
2262
2263 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2264 LLVMValueRef tmp, tmp2;
2265
2266 /* if the cube workaround is in place, f2i the result. */
2267 for (c = 0; c < 4; c++) {
2268 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2269 if (stype == GLSL_TYPE_UINT)
2270 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2271 else
2272 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2273 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2274 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2275 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2276 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2277 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2278 }
2279 }
2280 return result;
2281 }
2282
2283 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2284 const nir_tex_instr *instr,
2285 bool lod_is_zero,
2286 struct ac_image_args *args)
2287 {
2288 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2289 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2290
2291 return ac_build_buffer_load_format(&ctx->ac,
2292 args->resource,
2293 args->addr,
2294 ctx->ac.i32_0,
2295 util_last_bit(mask),
2296 false, true);
2297 }
2298
2299 args->opcode = ac_image_sample;
2300 args->compare = instr->is_shadow;
2301
2302 switch (instr->op) {
2303 case nir_texop_txf:
2304 case nir_texop_txf_ms:
2305 case nir_texop_samples_identical:
2306 args->opcode = lod_is_zero ||
2307 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2308 ac_image_load : ac_image_load_mip;
2309 args->compare = false;
2310 args->offset = false;
2311 break;
2312 case nir_texop_txb:
2313 args->bias = true;
2314 break;
2315 case nir_texop_txl:
2316 if (lod_is_zero)
2317 args->level_zero = true;
2318 else
2319 args->lod = true;
2320 break;
2321 case nir_texop_txs:
2322 case nir_texop_query_levels:
2323 args->opcode = ac_image_get_resinfo;
2324 break;
2325 case nir_texop_tex:
2326 if (ctx->stage != MESA_SHADER_FRAGMENT)
2327 args->level_zero = true;
2328 break;
2329 case nir_texop_txd:
2330 args->deriv = true;
2331 break;
2332 case nir_texop_tg4:
2333 args->opcode = ac_image_gather4;
2334 args->level_zero = true;
2335 break;
2336 case nir_texop_lod:
2337 args->opcode = ac_image_get_lod;
2338 args->compare = false;
2339 args->offset = false;
2340 break;
2341 default:
2342 break;
2343 }
2344
2345 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2346 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2347 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2348 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2349 }
2350 }
2351 return ac_build_image_opcode(&ctx->ac, args);
2352 }
2353
2354 static LLVMValueRef
2355 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2356 unsigned desc_set, unsigned binding)
2357 {
2358 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2359 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2360 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2361 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2362 unsigned base_offset = layout->binding[binding].offset;
2363 LLVMValueRef offset, stride;
2364
2365 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2366 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2367 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2368 layout->binding[binding].dynamic_offset_offset;
2369 desc_ptr = ctx->abi.push_constants;
2370 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2371 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2372 } else
2373 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2374
2375 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2376 index = LLVMBuildMul(ctx->builder, index, stride, "");
2377 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2378
2379 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2380 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2381 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2382
2383 return desc_ptr;
2384 }
2385
2386 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2387 nir_intrinsic_instr *instr)
2388 {
2389 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2390 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2391
2392 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2393 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2394 return result;
2395 }
2396
2397 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2398 nir_intrinsic_instr *instr)
2399 {
2400 LLVMValueRef ptr, addr;
2401
2402 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2403 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2404
2405 ptr = ac_build_gep0(&ctx->ac, ctx->abi.push_constants, addr);
2406 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2407
2408 return LLVMBuildLoad(ctx->builder, ptr, "");
2409 }
2410
2411 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2412 const nir_intrinsic_instr *instr)
2413 {
2414 LLVMValueRef index = get_src(ctx, instr->src[0]);
2415
2416 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2417 }
2418
2419 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2420 {
2421 uint32_t new_mask = 0;
2422 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2423 if (mask & (1u << i))
2424 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2425 return new_mask;
2426 }
2427
2428 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2429 unsigned start, unsigned count)
2430 {
2431 LLVMTypeRef type = LLVMTypeOf(src);
2432
2433 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2434 assert(start == 0);
2435 assert(count == 1);
2436 return src;
2437 }
2438
2439 unsigned src_elements = LLVMGetVectorSize(type);
2440 assert(start < src_elements);
2441 assert(start + count <= src_elements);
2442
2443 if (start == 0 && count == src_elements)
2444 return src;
2445
2446 if (count == 1)
2447 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2448
2449 assert(count <= 8);
2450 LLVMValueRef indices[8];
2451 for (unsigned i = 0; i < count; ++i)
2452 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2453
2454 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2455 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2456 }
2457
2458 static void visit_store_ssbo(struct ac_nir_context *ctx,
2459 nir_intrinsic_instr *instr)
2460 {
2461 const char *store_name;
2462 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2463 LLVMTypeRef data_type = ctx->ac.f32;
2464 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2465 int components_32bit = elem_size_mult * instr->num_components;
2466 unsigned writemask = nir_intrinsic_write_mask(instr);
2467 LLVMValueRef base_data, base_offset;
2468 LLVMValueRef params[6];
2469
2470 params[1] = ctx->abi->load_ssbo(ctx->abi,
2471 get_src(ctx, instr->src[1]), true);
2472 params[2] = ctx->ac.i32_0; /* vindex */
2473 params[4] = ctx->ac.i1false; /* glc */
2474 params[5] = ctx->ac.i1false; /* slc */
2475
2476 if (components_32bit > 1)
2477 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2478
2479 writemask = widen_mask(writemask, elem_size_mult);
2480
2481 base_data = ac_to_float(&ctx->ac, src_data);
2482 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2483 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2484 data_type, "");
2485 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2486 while (writemask) {
2487 int start, count;
2488 LLVMValueRef data;
2489 LLVMValueRef offset;
2490
2491 u_bit_scan_consecutive_range(&writemask, &start, &count);
2492
2493 /* Due to an LLVM limitation, split 3-element writes
2494 * into a 2-element and a 1-element write. */
2495 if (count == 3) {
2496 writemask |= 1 << (start + 2);
2497 count = 2;
2498 }
2499
2500 if (count > 4) {
2501 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2502 count = 4;
2503 }
2504
2505 if (count == 4) {
2506 store_name = "llvm.amdgcn.buffer.store.v4f32";
2507 } else if (count == 2) {
2508 store_name = "llvm.amdgcn.buffer.store.v2f32";
2509
2510 } else {
2511 assert(count == 1);
2512 store_name = "llvm.amdgcn.buffer.store.f32";
2513 }
2514 data = extract_vector_range(&ctx->ac, base_data, start, count);
2515
2516 offset = base_offset;
2517 if (start != 0) {
2518 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2519 }
2520 params[0] = data;
2521 params[3] = offset;
2522 ac_build_intrinsic(&ctx->ac, store_name,
2523 ctx->ac.voidt, params, 6, 0);
2524 }
2525 }
2526
2527 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2528 const nir_intrinsic_instr *instr)
2529 {
2530 const char *name;
2531 LLVMValueRef params[6];
2532 int arg_count = 0;
2533
2534 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2535 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2536 }
2537 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2538 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2539 get_src(ctx, instr->src[0]),
2540 true);
2541 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2542 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2543 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2544
2545 switch (instr->intrinsic) {
2546 case nir_intrinsic_ssbo_atomic_add:
2547 name = "llvm.amdgcn.buffer.atomic.add";
2548 break;
2549 case nir_intrinsic_ssbo_atomic_imin:
2550 name = "llvm.amdgcn.buffer.atomic.smin";
2551 break;
2552 case nir_intrinsic_ssbo_atomic_umin:
2553 name = "llvm.amdgcn.buffer.atomic.umin";
2554 break;
2555 case nir_intrinsic_ssbo_atomic_imax:
2556 name = "llvm.amdgcn.buffer.atomic.smax";
2557 break;
2558 case nir_intrinsic_ssbo_atomic_umax:
2559 name = "llvm.amdgcn.buffer.atomic.umax";
2560 break;
2561 case nir_intrinsic_ssbo_atomic_and:
2562 name = "llvm.amdgcn.buffer.atomic.and";
2563 break;
2564 case nir_intrinsic_ssbo_atomic_or:
2565 name = "llvm.amdgcn.buffer.atomic.or";
2566 break;
2567 case nir_intrinsic_ssbo_atomic_xor:
2568 name = "llvm.amdgcn.buffer.atomic.xor";
2569 break;
2570 case nir_intrinsic_ssbo_atomic_exchange:
2571 name = "llvm.amdgcn.buffer.atomic.swap";
2572 break;
2573 case nir_intrinsic_ssbo_atomic_comp_swap:
2574 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2575 break;
2576 default:
2577 abort();
2578 }
2579
2580 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2581 }
2582
2583 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2584 const nir_intrinsic_instr *instr)
2585 {
2586 LLVMValueRef results[2];
2587 int load_components;
2588 int num_components = instr->num_components;
2589 if (instr->dest.ssa.bit_size == 64)
2590 num_components *= 2;
2591
2592 for (int i = 0; i < num_components; i += load_components) {
2593 load_components = MIN2(num_components - i, 4);
2594 const char *load_name;
2595 LLVMTypeRef data_type = ctx->ac.f32;
2596 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2597 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2598
2599 if (load_components == 3)
2600 data_type = LLVMVectorType(ctx->ac.f32, 4);
2601 else if (load_components > 1)
2602 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2603
2604 if (load_components >= 3)
2605 load_name = "llvm.amdgcn.buffer.load.v4f32";
2606 else if (load_components == 2)
2607 load_name = "llvm.amdgcn.buffer.load.v2f32";
2608 else if (load_components == 1)
2609 load_name = "llvm.amdgcn.buffer.load.f32";
2610 else
2611 unreachable("unhandled number of components");
2612
2613 LLVMValueRef params[] = {
2614 ctx->abi->load_ssbo(ctx->abi,
2615 get_src(ctx, instr->src[0]),
2616 false),
2617 ctx->ac.i32_0,
2618 offset,
2619 ctx->ac.i1false,
2620 ctx->ac.i1false,
2621 };
2622
2623 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2624 }
2625
2626 assume(results[0]);
2627 LLVMValueRef ret = results[0];
2628 if (num_components > 4 || num_components == 3) {
2629 LLVMValueRef masks[] = {
2630 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2631 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2632 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2633 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2634 };
2635
2636 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2637 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2638 results[num_components > 4 ? 1 : 0], swizzle, "");
2639 }
2640
2641 return LLVMBuildBitCast(ctx->ac.builder, ret,
2642 get_def_type(ctx, &instr->dest.ssa), "");
2643 }
2644
2645 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2646 const nir_intrinsic_instr *instr)
2647 {
2648 LLVMValueRef ret;
2649 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2650 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2651 int num_components = instr->num_components;
2652
2653 if (ctx->abi->load_ubo)
2654 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2655
2656 if (instr->dest.ssa.bit_size == 64)
2657 num_components *= 2;
2658
2659 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2660 NULL, 0, false, false, true, true);
2661 ret = trim_vector(&ctx->ac, ret, num_components);
2662 return LLVMBuildBitCast(ctx->ac.builder, ret,
2663 get_def_type(ctx, &instr->dest.ssa), "");
2664 }
2665
2666 static void
2667 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2668 bool vs_in, unsigned *vertex_index_out,
2669 LLVMValueRef *vertex_index_ref,
2670 unsigned *const_out, LLVMValueRef *indir_out)
2671 {
2672 unsigned const_offset = 0;
2673 nir_deref *tail = &deref->deref;
2674 LLVMValueRef offset = NULL;
2675
2676 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2677 tail = tail->child;
2678 nir_deref_array *deref_array = nir_deref_as_array(tail);
2679 if (vertex_index_out)
2680 *vertex_index_out = deref_array->base_offset;
2681
2682 if (vertex_index_ref) {
2683 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2684 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2685 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2686 }
2687 *vertex_index_ref = vtx;
2688 }
2689 }
2690
2691 if (deref->var->data.compact) {
2692 assert(tail->child->deref_type == nir_deref_type_array);
2693 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2694 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2695 /* We always lower indirect dereferences for "compact" array vars. */
2696 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2697
2698 const_offset = deref_array->base_offset;
2699 goto out;
2700 }
2701
2702 while (tail->child != NULL) {
2703 const struct glsl_type *parent_type = tail->type;
2704 tail = tail->child;
2705
2706 if (tail->deref_type == nir_deref_type_array) {
2707 nir_deref_array *deref_array = nir_deref_as_array(tail);
2708 LLVMValueRef index, stride, local_offset;
2709 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2710
2711 const_offset += size * deref_array->base_offset;
2712 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2713 continue;
2714
2715 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2716 index = get_src(ctx, deref_array->indirect);
2717 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2718 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2719
2720 if (offset)
2721 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2722 else
2723 offset = local_offset;
2724 } else if (tail->deref_type == nir_deref_type_struct) {
2725 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2726
2727 for (unsigned i = 0; i < deref_struct->index; i++) {
2728 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2729 const_offset += glsl_count_attribute_slots(ft, vs_in);
2730 }
2731 } else
2732 unreachable("unsupported deref type");
2733
2734 }
2735 out:
2736 if (const_offset && offset)
2737 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2738 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2739 "");
2740
2741 *const_out = const_offset;
2742 *indir_out = offset;
2743 }
2744
2745
2746 /* The offchip buffer layout for TCS->TES is
2747 *
2748 * - attribute 0 of patch 0 vertex 0
2749 * - attribute 0 of patch 0 vertex 1
2750 * - attribute 0 of patch 0 vertex 2
2751 * ...
2752 * - attribute 0 of patch 1 vertex 0
2753 * - attribute 0 of patch 1 vertex 1
2754 * ...
2755 * - attribute 1 of patch 0 vertex 0
2756 * - attribute 1 of patch 0 vertex 1
2757 * ...
2758 * - per patch attribute 0 of patch 0
2759 * - per patch attribute 0 of patch 1
2760 * ...
2761 *
2762 * Note that every attribute has 4 components.
2763 */
2764 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2765 LLVMValueRef vertex_index,
2766 LLVMValueRef param_index)
2767 {
2768 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2769 LLVMValueRef param_stride, constant16;
2770 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2771
2772 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2773 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2774 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2775 num_patches, "");
2776
2777 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2778 if (vertex_index) {
2779 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2780 vertices_per_patch, "");
2781
2782 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2783 vertex_index, "");
2784
2785 param_stride = total_vertices;
2786 } else {
2787 base_addr = rel_patch_id;
2788 param_stride = num_patches;
2789 }
2790
2791 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2792 LLVMBuildMul(ctx->builder, param_index,
2793 param_stride, ""), "");
2794
2795 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2796
2797 if (!vertex_index) {
2798 LLVMValueRef patch_data_offset =
2799 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2800
2801 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2802 patch_data_offset, "");
2803 }
2804 return base_addr;
2805 }
2806
2807 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2808 unsigned param,
2809 unsigned const_index,
2810 bool is_compact,
2811 LLVMValueRef vertex_index,
2812 LLVMValueRef indir_index)
2813 {
2814 LLVMValueRef param_index;
2815
2816 if (indir_index)
2817 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2818 indir_index, "");
2819 else {
2820 if (const_index && !is_compact)
2821 param += const_index;
2822 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2823 }
2824 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2825 }
2826
2827 static void
2828 mark_tess_output(struct nir_to_llvm_context *ctx,
2829 bool is_patch, uint32_t param)
2830
2831 {
2832 if (is_patch) {
2833 ctx->tess_patch_outputs_written |= (1ull << param);
2834 } else
2835 ctx->tess_outputs_written |= (1ull << param);
2836 }
2837
2838 static LLVMValueRef
2839 get_dw_address(struct nir_to_llvm_context *ctx,
2840 LLVMValueRef dw_addr,
2841 unsigned param,
2842 unsigned const_index,
2843 bool compact_const_index,
2844 LLVMValueRef vertex_index,
2845 LLVMValueRef stride,
2846 LLVMValueRef indir_index)
2847
2848 {
2849
2850 if (vertex_index) {
2851 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2852 LLVMBuildMul(ctx->builder,
2853 vertex_index,
2854 stride, ""), "");
2855 }
2856
2857 if (indir_index)
2858 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2859 LLVMBuildMul(ctx->builder, indir_index,
2860 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2861 else if (const_index && !compact_const_index)
2862 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2863 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2864
2865 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2866 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2867
2868 if (const_index && compact_const_index)
2869 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2870 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2871 return dw_addr;
2872 }
2873
2874 static LLVMValueRef
2875 load_tcs_varyings(struct ac_shader_abi *abi,
2876 LLVMValueRef vertex_index,
2877 LLVMValueRef indir_index,
2878 unsigned const_index,
2879 unsigned location,
2880 unsigned driver_location,
2881 unsigned component,
2882 unsigned num_components,
2883 bool is_patch,
2884 bool is_compact,
2885 bool load_input)
2886 {
2887 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2888 LLVMValueRef dw_addr, stride;
2889 LLVMValueRef value[4], result;
2890 unsigned param = shader_io_get_unique_index(location);
2891
2892 if (load_input) {
2893 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2894 dw_addr = get_tcs_in_current_patch_offset(ctx);
2895 } else {
2896 if (!is_patch) {
2897 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2898 dw_addr = get_tcs_out_current_patch_offset(ctx);
2899 } else {
2900 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2901 stride = NULL;
2902 }
2903 }
2904
2905 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2906 indir_index);
2907
2908 for (unsigned i = 0; i < num_components + component; i++) {
2909 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2910 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2911 ctx->ac.i32_1, "");
2912 }
2913 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2914 return result;
2915 }
2916
2917 static void
2918 store_tcs_output(struct ac_shader_abi *abi,
2919 LLVMValueRef vertex_index,
2920 LLVMValueRef param_index,
2921 unsigned const_index,
2922 unsigned location,
2923 unsigned driver_location,
2924 LLVMValueRef src,
2925 unsigned component,
2926 bool is_patch,
2927 bool is_compact,
2928 unsigned writemask)
2929 {
2930 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2931 LLVMValueRef dw_addr;
2932 LLVMValueRef stride = NULL;
2933 LLVMValueRef buf_addr = NULL;
2934 unsigned param;
2935 bool store_lds = true;
2936
2937 if (is_patch) {
2938 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2939 store_lds = false;
2940 } else {
2941 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2942 store_lds = false;
2943 }
2944
2945 param = shader_io_get_unique_index(location);
2946 if (location == VARYING_SLOT_CLIP_DIST0 &&
2947 is_compact && const_index > 3) {
2948 const_index -= 3;
2949 param++;
2950 }
2951
2952 if (!is_patch) {
2953 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2954 dw_addr = get_tcs_out_current_patch_offset(ctx);
2955 } else {
2956 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2957 }
2958
2959 mark_tess_output(ctx, is_patch, param);
2960
2961 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2962 param_index);
2963 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2964 vertex_index, param_index);
2965
2966 bool is_tess_factor = false;
2967 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2968 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2969 is_tess_factor = true;
2970
2971 unsigned base = is_compact ? const_index : 0;
2972 for (unsigned chan = 0; chan < 8; chan++) {
2973 if (!(writemask & (1 << chan)))
2974 continue;
2975 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2976
2977 if (store_lds || is_tess_factor) {
2978 LLVMValueRef dw_addr_chan =
2979 LLVMBuildAdd(ctx->builder, dw_addr,
2980 LLVMConstInt(ctx->ac.i32, chan, false), "");
2981 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2982 }
2983
2984 if (!is_tess_factor && writemask != 0xF)
2985 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2986 buf_addr, ctx->oc_lds,
2987 4 * (base + chan), 1, 0, true, false);
2988 }
2989
2990 if (writemask == 0xF) {
2991 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2992 buf_addr, ctx->oc_lds,
2993 (base * 4), 1, 0, true, false);
2994 }
2995 }
2996
2997 static LLVMValueRef
2998 load_tes_input(struct ac_shader_abi *abi,
2999 LLVMValueRef vertex_index,
3000 LLVMValueRef param_index,
3001 unsigned const_index,
3002 unsigned location,
3003 unsigned driver_location,
3004 unsigned component,
3005 unsigned num_components,
3006 bool is_patch,
3007 bool is_compact,
3008 bool load_input)
3009 {
3010 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3011 LLVMValueRef buf_addr;
3012 LLVMValueRef result;
3013 unsigned param = shader_io_get_unique_index(location);
3014
3015 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3016 const_index -= 3;
3017 param++;
3018 }
3019
3020 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3021 is_compact, vertex_index, param_index);
3022
3023 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3024 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3025
3026 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3027 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3028 result = trim_vector(&ctx->ac, result, num_components);
3029 return result;
3030 }
3031
3032 static LLVMValueRef
3033 load_gs_input(struct ac_shader_abi *abi,
3034 unsigned location,
3035 unsigned driver_location,
3036 unsigned component,
3037 unsigned num_components,
3038 unsigned vertex_index,
3039 unsigned const_index,
3040 LLVMTypeRef type)
3041 {
3042 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3043 LLVMValueRef vtx_offset;
3044 unsigned param, vtx_offset_param;
3045 LLVMValueRef value[4], result;
3046
3047 vtx_offset_param = vertex_index;
3048 assert(vtx_offset_param < 6);
3049 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3050 LLVMConstInt(ctx->ac.i32, 4, false), "");
3051
3052 param = shader_io_get_unique_index(location);
3053
3054 for (unsigned i = component; i < num_components + component; i++) {
3055 if (ctx->ac.chip_class >= GFX9) {
3056 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3057 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3058 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3059 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3060 } else {
3061 LLVMValueRef soffset =
3062 LLVMConstInt(ctx->ac.i32,
3063 (param * 4 + i + const_index) * 256,
3064 false);
3065
3066 value[i] = ac_build_buffer_load(&ctx->ac,
3067 ctx->esgs_ring, 1,
3068 ctx->ac.i32_0,
3069 vtx_offset, soffset,
3070 0, 1, 0, true, false);
3071
3072 value[i] = LLVMBuildBitCast(ctx->builder, value[i],
3073 type, "");
3074 }
3075 }
3076 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3077 result = ac_to_integer(&ctx->ac, result);
3078 return result;
3079 }
3080
3081 static LLVMValueRef
3082 build_gep_for_deref(struct ac_nir_context *ctx,
3083 nir_deref_var *deref)
3084 {
3085 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3086 assert(entry->data);
3087 LLVMValueRef val = entry->data;
3088 nir_deref *tail = deref->deref.child;
3089 while (tail != NULL) {
3090 LLVMValueRef offset;
3091 switch (tail->deref_type) {
3092 case nir_deref_type_array: {
3093 nir_deref_array *array = nir_deref_as_array(tail);
3094 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3095 if (array->deref_array_type ==
3096 nir_deref_array_type_indirect) {
3097 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3098 get_src(ctx,
3099 array->indirect),
3100 "");
3101 }
3102 break;
3103 }
3104 case nir_deref_type_struct: {
3105 nir_deref_struct *deref_struct =
3106 nir_deref_as_struct(tail);
3107 offset = LLVMConstInt(ctx->ac.i32,
3108 deref_struct->index, 0);
3109 break;
3110 }
3111 default:
3112 unreachable("bad deref type");
3113 }
3114 val = ac_build_gep0(&ctx->ac, val, offset);
3115 tail = tail->child;
3116 }
3117 return val;
3118 }
3119
3120 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3121 nir_intrinsic_instr *instr,
3122 bool load_inputs)
3123 {
3124 LLVMValueRef result;
3125 LLVMValueRef vertex_index = NULL;
3126 LLVMValueRef indir_index = NULL;
3127 unsigned const_index = 0;
3128 unsigned location = instr->variables[0]->var->data.location;
3129 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3130 const bool is_patch = instr->variables[0]->var->data.patch;
3131 const bool is_compact = instr->variables[0]->var->data.compact;
3132
3133 get_deref_offset(ctx, instr->variables[0],
3134 false, NULL, is_patch ? NULL : &vertex_index,
3135 &const_index, &indir_index);
3136
3137 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3138 const_index, location, driver_location,
3139 instr->variables[0]->var->data.location_frac,
3140 instr->num_components,
3141 is_patch, is_compact, load_inputs);
3142 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3143 }
3144
3145 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3146 nir_intrinsic_instr *instr)
3147 {
3148 LLVMValueRef values[8];
3149 int idx = instr->variables[0]->var->data.driver_location;
3150 int ve = instr->dest.ssa.num_components;
3151 unsigned comp = instr->variables[0]->var->data.location_frac;
3152 LLVMValueRef indir_index;
3153 LLVMValueRef ret;
3154 unsigned const_index;
3155 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3156 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3157 instr->variables[0]->var->data.mode == nir_var_shader_in;
3158 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3159 &const_index, &indir_index);
3160
3161 if (instr->dest.ssa.bit_size == 64)
3162 ve *= 2;
3163
3164 switch (instr->variables[0]->var->data.mode) {
3165 case nir_var_shader_in:
3166 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3167 ctx->stage == MESA_SHADER_TESS_EVAL) {
3168 return load_tess_varyings(ctx, instr, true);
3169 }
3170
3171 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3172 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3173 LLVMValueRef indir_index;
3174 unsigned const_index, vertex_index;
3175 get_deref_offset(ctx, instr->variables[0],
3176 false, &vertex_index, NULL,
3177 &const_index, &indir_index);
3178
3179 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3180 instr->variables[0]->var->data.driver_location,
3181 instr->variables[0]->var->data.location_frac, ve,
3182 vertex_index, const_index, type);
3183 }
3184
3185 for (unsigned chan = comp; chan < ve + comp; chan++) {
3186 if (indir_index) {
3187 unsigned count = glsl_count_attribute_slots(
3188 instr->variables[0]->var->type,
3189 ctx->stage == MESA_SHADER_VERTEX);
3190 count -= chan / 4;
3191 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3192 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3193 stride, false, true);
3194
3195 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3196 tmp_vec,
3197 indir_index, "");
3198 } else
3199 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3200 }
3201 break;
3202 case nir_var_local:
3203 for (unsigned chan = 0; chan < ve; chan++) {
3204 if (indir_index) {
3205 unsigned count = glsl_count_attribute_slots(
3206 instr->variables[0]->var->type, false);
3207 count -= chan / 4;
3208 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3209 &ctx->ac, ctx->locals + idx + chan, count,
3210 stride, true, true);
3211
3212 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3213 tmp_vec,
3214 indir_index, "");
3215 } else {
3216 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3217 }
3218 }
3219 break;
3220 case nir_var_shared: {
3221 LLVMValueRef address = build_gep_for_deref(ctx,
3222 instr->variables[0]);
3223 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3224 return LLVMBuildBitCast(ctx->ac.builder, val,
3225 get_def_type(ctx, &instr->dest.ssa),
3226 "");
3227 }
3228 case nir_var_shader_out:
3229 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3230 return load_tess_varyings(ctx, instr, false);
3231 }
3232
3233 for (unsigned chan = comp; chan < ve + comp; chan++) {
3234 if (indir_index) {
3235 unsigned count = glsl_count_attribute_slots(
3236 instr->variables[0]->var->type, false);
3237 count -= chan / 4;
3238 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3239 &ctx->ac, ctx->outputs + idx + chan, count,
3240 stride, true, true);
3241
3242 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3243 tmp_vec,
3244 indir_index, "");
3245 } else {
3246 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3247 ctx->outputs[idx + chan + const_index * stride],
3248 "");
3249 }
3250 }
3251 break;
3252 default:
3253 unreachable("unhandle variable mode");
3254 }
3255 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3256 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3257 }
3258
3259 static void
3260 visit_store_var(struct ac_nir_context *ctx,
3261 nir_intrinsic_instr *instr)
3262 {
3263 LLVMValueRef temp_ptr, value;
3264 int idx = instr->variables[0]->var->data.driver_location;
3265 unsigned comp = instr->variables[0]->var->data.location_frac;
3266 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3267 int writemask = instr->const_index[0] << comp;
3268 LLVMValueRef indir_index;
3269 unsigned const_index;
3270 get_deref_offset(ctx, instr->variables[0], false,
3271 NULL, NULL, &const_index, &indir_index);
3272
3273 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3274
3275 src = LLVMBuildBitCast(ctx->ac.builder, src,
3276 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3277 "");
3278
3279 writemask = widen_mask(writemask, 2);
3280 }
3281
3282 switch (instr->variables[0]->var->data.mode) {
3283 case nir_var_shader_out:
3284
3285 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3286 LLVMValueRef vertex_index = NULL;
3287 LLVMValueRef indir_index = NULL;
3288 unsigned const_index = 0;
3289 const unsigned location = instr->variables[0]->var->data.location;
3290 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3291 const unsigned comp = instr->variables[0]->var->data.location_frac;
3292 const bool is_patch = instr->variables[0]->var->data.patch;
3293 const bool is_compact = instr->variables[0]->var->data.compact;
3294
3295 get_deref_offset(ctx, instr->variables[0],
3296 false, NULL, is_patch ? NULL : &vertex_index,
3297 &const_index, &indir_index);
3298
3299 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3300 const_index, location, driver_location,
3301 src, comp, is_patch, is_compact, writemask);
3302 return;
3303 }
3304
3305 for (unsigned chan = 0; chan < 8; chan++) {
3306 int stride = 4;
3307 if (!(writemask & (1 << chan)))
3308 continue;
3309
3310 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3311
3312 if (instr->variables[0]->var->data.compact)
3313 stride = 1;
3314 if (indir_index) {
3315 unsigned count = glsl_count_attribute_slots(
3316 instr->variables[0]->var->type, false);
3317 count -= chan / 4;
3318 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3319 &ctx->ac, ctx->outputs + idx + chan, count,
3320 stride, true, true);
3321
3322 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3323 value, indir_index, "");
3324 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3325 count, stride, tmp_vec);
3326
3327 } else {
3328 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3329
3330 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3331 }
3332 }
3333 break;
3334 case nir_var_local:
3335 for (unsigned chan = 0; chan < 8; chan++) {
3336 if (!(writemask & (1 << chan)))
3337 continue;
3338
3339 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3340 if (indir_index) {
3341 unsigned count = glsl_count_attribute_slots(
3342 instr->variables[0]->var->type, false);
3343 count -= chan / 4;
3344 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3345 &ctx->ac, ctx->locals + idx + chan, count,
3346 4, true, true);
3347
3348 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3349 value, indir_index, "");
3350 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3351 count, 4, tmp_vec);
3352 } else {
3353 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3354
3355 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3356 }
3357 }
3358 break;
3359 case nir_var_shared: {
3360 int writemask = instr->const_index[0];
3361 LLVMValueRef address = build_gep_for_deref(ctx,
3362 instr->variables[0]);
3363 LLVMValueRef val = get_src(ctx, instr->src[0]);
3364 unsigned components =
3365 glsl_get_vector_elements(
3366 nir_deref_tail(&instr->variables[0]->deref)->type);
3367 if (writemask == (1 << components) - 1) {
3368 val = LLVMBuildBitCast(
3369 ctx->ac.builder, val,
3370 LLVMGetElementType(LLVMTypeOf(address)), "");
3371 LLVMBuildStore(ctx->ac.builder, val, address);
3372 } else {
3373 for (unsigned chan = 0; chan < 4; chan++) {
3374 if (!(writemask & (1 << chan)))
3375 continue;
3376 LLVMValueRef ptr =
3377 LLVMBuildStructGEP(ctx->ac.builder,
3378 address, chan, "");
3379 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3380 chan);
3381 src = LLVMBuildBitCast(
3382 ctx->ac.builder, src,
3383 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3384 LLVMBuildStore(ctx->ac.builder, src, ptr);
3385 }
3386 }
3387 break;
3388 }
3389 default:
3390 break;
3391 }
3392 }
3393
3394 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3395 {
3396 switch (dim) {
3397 case GLSL_SAMPLER_DIM_BUF:
3398 return 1;
3399 case GLSL_SAMPLER_DIM_1D:
3400 return array ? 2 : 1;
3401 case GLSL_SAMPLER_DIM_2D:
3402 return array ? 3 : 2;
3403 case GLSL_SAMPLER_DIM_MS:
3404 return array ? 4 : 3;
3405 case GLSL_SAMPLER_DIM_3D:
3406 case GLSL_SAMPLER_DIM_CUBE:
3407 return 3;
3408 case GLSL_SAMPLER_DIM_RECT:
3409 case GLSL_SAMPLER_DIM_SUBPASS:
3410 return 2;
3411 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3412 return 3;
3413 default:
3414 break;
3415 }
3416 return 0;
3417 }
3418
3419
3420
3421 /* Adjust the sample index according to FMASK.
3422 *
3423 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3424 * which is the identity mapping. Each nibble says which physical sample
3425 * should be fetched to get that sample.
3426 *
3427 * For example, 0x11111100 means there are only 2 samples stored and
3428 * the second sample covers 3/4 of the pixel. When reading samples 0
3429 * and 1, return physical sample 0 (determined by the first two 0s
3430 * in FMASK), otherwise return physical sample 1.
3431 *
3432 * The sample index should be adjusted as follows:
3433 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3434 */
3435 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3436 LLVMValueRef coord_x, LLVMValueRef coord_y,
3437 LLVMValueRef coord_z,
3438 LLVMValueRef sample_index,
3439 LLVMValueRef fmask_desc_ptr)
3440 {
3441 LLVMValueRef fmask_load_address[4];
3442 LLVMValueRef res;
3443
3444 fmask_load_address[0] = coord_x;
3445 fmask_load_address[1] = coord_y;
3446 if (coord_z) {
3447 fmask_load_address[2] = coord_z;
3448 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3449 }
3450
3451 struct ac_image_args args = {0};
3452
3453 args.opcode = ac_image_load;
3454 args.da = coord_z ? true : false;
3455 args.resource = fmask_desc_ptr;
3456 args.dmask = 0xf;
3457 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3458
3459 res = ac_build_image_opcode(ctx, &args);
3460
3461 res = ac_to_integer(ctx, res);
3462 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3463 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3464
3465 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3466 res,
3467 ctx->i32_0, "");
3468
3469 LLVMValueRef sample_index4 =
3470 LLVMBuildMul(ctx->builder, sample_index, four, "");
3471 LLVMValueRef shifted_fmask =
3472 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3473 LLVMValueRef final_sample =
3474 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3475
3476 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3477 * resource descriptor is 0 (invalid),
3478 */
3479 LLVMValueRef fmask_desc =
3480 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3481 ctx->v8i32, "");
3482
3483 LLVMValueRef fmask_word1 =
3484 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3485 ctx->i32_1, "");
3486
3487 LLVMValueRef word1_is_nonzero =
3488 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3489 fmask_word1, ctx->i32_0, "");
3490
3491 /* Replace the MSAA sample index. */
3492 sample_index =
3493 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3494 final_sample, sample_index, "");
3495 return sample_index;
3496 }
3497
3498 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3499 const nir_intrinsic_instr *instr)
3500 {
3501 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3502
3503 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3504 LLVMValueRef coords[4];
3505 LLVMValueRef masks[] = {
3506 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3507 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3508 };
3509 LLVMValueRef res;
3510 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3511
3512 int count;
3513 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3514 bool is_array = glsl_sampler_type_is_array(type);
3515 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3516 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3517 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3518 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3519 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3520 count = image_type_to_components_count(dim, is_array);
3521
3522 if (is_ms) {
3523 LLVMValueRef fmask_load_address[3];
3524 int chan;
3525
3526 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3527 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3528 if (is_array)
3529 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3530 else
3531 fmask_load_address[2] = NULL;
3532 if (add_frag_pos) {
3533 for (chan = 0; chan < 2; ++chan)
3534 fmask_load_address[chan] =
3535 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3536 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3537 ctx->ac.i32, ""), "");
3538 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3539 }
3540 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3541 fmask_load_address[0],
3542 fmask_load_address[1],
3543 fmask_load_address[2],
3544 sample_index,
3545 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3546 }
3547 if (count == 1 && !gfx9_1d) {
3548 if (instr->src[0].ssa->num_components)
3549 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3550 else
3551 res = src0;
3552 } else {
3553 int chan;
3554 if (is_ms)
3555 count--;
3556 for (chan = 0; chan < count; ++chan) {
3557 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3558 }
3559 if (add_frag_pos) {
3560 for (chan = 0; chan < 2; ++chan)
3561 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3562 ctx->ac.i32, ""), "");
3563 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3564 count++;
3565 }
3566
3567 if (gfx9_1d) {
3568 if (is_array) {
3569 coords[2] = coords[1];
3570 coords[1] = ctx->ac.i32_0;
3571 } else
3572 coords[1] = ctx->ac.i32_0;
3573 count++;
3574 }
3575
3576 if (is_ms) {
3577 coords[count] = sample_index;
3578 count++;
3579 }
3580
3581 if (count == 3) {
3582 coords[3] = LLVMGetUndef(ctx->ac.i32);
3583 count = 4;
3584 }
3585 res = ac_build_gather_values(&ctx->ac, coords, count);
3586 }
3587 return res;
3588 }
3589
3590 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3591 const nir_intrinsic_instr *instr)
3592 {
3593 LLVMValueRef params[7];
3594 LLVMValueRef res;
3595 char intrinsic_name[64];
3596 const nir_variable *var = instr->variables[0]->var;
3597 const struct glsl_type *type = var->type;
3598
3599 if(instr->variables[0]->deref.child)
3600 type = instr->variables[0]->deref.child->type;
3601
3602 type = glsl_without_array(type);
3603
3604 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3605 if (dim == GLSL_SAMPLER_DIM_BUF) {
3606 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3607 unsigned num_channels = util_last_bit(mask);
3608 LLVMValueRef rsrc, vindex;
3609
3610 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3611 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3612 ctx->ac.i32_0, "");
3613
3614 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3615 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3616 ctx->ac.i32_0, num_channels,
3617 false, false);
3618 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3619
3620 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3621 res = ac_to_integer(&ctx->ac, res);
3622 } else {
3623 bool is_da = glsl_sampler_type_is_array(type) ||
3624 dim == GLSL_SAMPLER_DIM_CUBE ||
3625 dim == GLSL_SAMPLER_DIM_3D ||
3626 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3627 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3628 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3629 LLVMValueRef glc = ctx->ac.i1false;
3630 LLVMValueRef slc = ctx->ac.i1false;
3631
3632 params[0] = get_image_coords(ctx, instr);
3633 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3634 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3635 params[3] = glc;
3636 params[4] = slc;
3637 params[5] = ctx->ac.i1false;
3638 params[6] = da;
3639
3640 ac_get_image_intr_name("llvm.amdgcn.image.load",
3641 ctx->ac.v4f32, /* vdata */
3642 LLVMTypeOf(params[0]), /* coords */
3643 LLVMTypeOf(params[1]), /* rsrc */
3644 intrinsic_name, sizeof(intrinsic_name));
3645
3646 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3647 params, 7, AC_FUNC_ATTR_READONLY);
3648 }
3649 return ac_to_integer(&ctx->ac, res);
3650 }
3651
3652 static void visit_image_store(struct ac_nir_context *ctx,
3653 nir_intrinsic_instr *instr)
3654 {
3655 LLVMValueRef params[8];
3656 char intrinsic_name[64];
3657 const nir_variable *var = instr->variables[0]->var;
3658 const struct glsl_type *type = glsl_without_array(var->type);
3659 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3660 LLVMValueRef glc = ctx->ac.i1false;
3661 bool force_glc = ctx->ac.chip_class == SI;
3662 if (force_glc)
3663 glc = ctx->ac.i1true;
3664
3665 if (dim == GLSL_SAMPLER_DIM_BUF) {
3666 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3667 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3668 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3669 ctx->ac.i32_0, ""); /* vindex */
3670 params[3] = ctx->ac.i32_0; /* voffset */
3671 params[4] = glc; /* glc */
3672 params[5] = ctx->ac.i1false; /* slc */
3673 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3674 params, 6, 0);
3675 } else {
3676 bool is_da = glsl_sampler_type_is_array(type) ||
3677 dim == GLSL_SAMPLER_DIM_CUBE ||
3678 dim == GLSL_SAMPLER_DIM_3D;
3679 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3680 LLVMValueRef slc = ctx->ac.i1false;
3681
3682 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3683 params[1] = get_image_coords(ctx, instr); /* coords */
3684 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3685 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3686 params[4] = glc;
3687 params[5] = slc;
3688 params[6] = ctx->ac.i1false;
3689 params[7] = da;
3690
3691 ac_get_image_intr_name("llvm.amdgcn.image.store",
3692 LLVMTypeOf(params[0]), /* vdata */
3693 LLVMTypeOf(params[1]), /* coords */
3694 LLVMTypeOf(params[2]), /* rsrc */
3695 intrinsic_name, sizeof(intrinsic_name));
3696
3697 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3698 params, 8, 0);
3699 }
3700
3701 }
3702
3703 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3704 const nir_intrinsic_instr *instr)
3705 {
3706 LLVMValueRef params[7];
3707 int param_count = 0;
3708 const nir_variable *var = instr->variables[0]->var;
3709
3710 const char *atomic_name;
3711 char intrinsic_name[41];
3712 const struct glsl_type *type = glsl_without_array(var->type);
3713 MAYBE_UNUSED int length;
3714
3715 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3716
3717 switch (instr->intrinsic) {
3718 case nir_intrinsic_image_atomic_add:
3719 atomic_name = "add";
3720 break;
3721 case nir_intrinsic_image_atomic_min:
3722 atomic_name = is_unsigned ? "umin" : "smin";
3723 break;
3724 case nir_intrinsic_image_atomic_max:
3725 atomic_name = is_unsigned ? "umax" : "smax";
3726 break;
3727 case nir_intrinsic_image_atomic_and:
3728 atomic_name = "and";
3729 break;
3730 case nir_intrinsic_image_atomic_or:
3731 atomic_name = "or";
3732 break;
3733 case nir_intrinsic_image_atomic_xor:
3734 atomic_name = "xor";
3735 break;
3736 case nir_intrinsic_image_atomic_exchange:
3737 atomic_name = "swap";
3738 break;
3739 case nir_intrinsic_image_atomic_comp_swap:
3740 atomic_name = "cmpswap";
3741 break;
3742 default:
3743 abort();
3744 }
3745
3746 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3747 params[param_count++] = get_src(ctx, instr->src[3]);
3748 params[param_count++] = get_src(ctx, instr->src[2]);
3749
3750 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3751 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3752 NULL, true, true);
3753 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3754 ctx->ac.i32_0, ""); /* vindex */
3755 params[param_count++] = ctx->ac.i32_0; /* voffset */
3756 params[param_count++] = ctx->ac.i1false; /* slc */
3757
3758 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3759 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3760 } else {
3761 char coords_type[8];
3762
3763 bool da = glsl_sampler_type_is_array(type) ||
3764 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3765
3766 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3767 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3768 NULL, true, true);
3769 params[param_count++] = ctx->ac.i1false; /* r128 */
3770 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3771 params[param_count++] = ctx->ac.i1false; /* slc */
3772
3773 build_int_type_name(LLVMTypeOf(coords),
3774 coords_type, sizeof(coords_type));
3775
3776 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3777 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3778 }
3779
3780 assert(length < sizeof(intrinsic_name));
3781 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3782 }
3783
3784 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3785 const nir_intrinsic_instr *instr)
3786 {
3787 LLVMValueRef res;
3788 const nir_variable *var = instr->variables[0]->var;
3789 const struct glsl_type *type = instr->variables[0]->var->type;
3790 bool da = glsl_sampler_type_is_array(var->type) ||
3791 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE ||
3792 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_3D;
3793 if(instr->variables[0]->deref.child)
3794 type = instr->variables[0]->deref.child->type;
3795
3796 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3797 return get_buffer_size(ctx,
3798 get_sampler_desc(ctx, instr->variables[0],
3799 AC_DESC_BUFFER, NULL, true, false), true);
3800
3801 struct ac_image_args args = { 0 };
3802
3803 args.da = da;
3804 args.dmask = 0xf;
3805 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3806 args.opcode = ac_image_get_resinfo;
3807 args.addr = ctx->ac.i32_0;
3808
3809 res = ac_build_image_opcode(&ctx->ac, &args);
3810
3811 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3812
3813 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3814 glsl_sampler_type_is_array(type)) {
3815 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3816 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3817 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3818 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3819 }
3820 if (ctx->ac.chip_class >= GFX9 &&
3821 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3822 glsl_sampler_type_is_array(type)) {
3823 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3824 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3825 ctx->ac.i32_1, "");
3826
3827 }
3828 return res;
3829 }
3830
3831 #define NOOP_WAITCNT 0xf7f
3832 #define LGKM_CNT 0x07f
3833 #define VM_CNT 0xf70
3834
3835 static void emit_membar(struct ac_llvm_context *ac,
3836 const nir_intrinsic_instr *instr)
3837 {
3838 unsigned waitcnt = NOOP_WAITCNT;
3839
3840 switch (instr->intrinsic) {
3841 case nir_intrinsic_memory_barrier:
3842 case nir_intrinsic_group_memory_barrier:
3843 waitcnt &= VM_CNT & LGKM_CNT;
3844 break;
3845 case nir_intrinsic_memory_barrier_atomic_counter:
3846 case nir_intrinsic_memory_barrier_buffer:
3847 case nir_intrinsic_memory_barrier_image:
3848 waitcnt &= VM_CNT;
3849 break;
3850 case nir_intrinsic_memory_barrier_shared:
3851 waitcnt &= LGKM_CNT;
3852 break;
3853 default:
3854 break;
3855 }
3856 if (waitcnt != NOOP_WAITCNT)
3857 ac_build_waitcnt(ac, waitcnt);
3858 }
3859
3860 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3861 {
3862 /* SI only (thanks to a hw bug workaround):
3863 * The real barrier instruction isn’t needed, because an entire patch
3864 * always fits into a single wave.
3865 */
3866 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3867 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3868 return;
3869 }
3870 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3871 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3872 }
3873
3874 static void emit_discard(struct ac_nir_context *ctx,
3875 const nir_intrinsic_instr *instr)
3876 {
3877 LLVMValueRef cond;
3878
3879 if (instr->intrinsic == nir_intrinsic_discard_if) {
3880 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3881 get_src(ctx, instr->src[0]),
3882 ctx->ac.i32_0, "");
3883 } else {
3884 assert(instr->intrinsic == nir_intrinsic_discard);
3885 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3886 }
3887
3888 ac_build_kill_if_false(&ctx->ac, cond);
3889 }
3890
3891 static LLVMValueRef
3892 visit_load_helper_invocation(struct ac_nir_context *ctx)
3893 {
3894 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3895 "llvm.amdgcn.ps.live",
3896 ctx->ac.i1, NULL, 0,
3897 AC_FUNC_ATTR_READNONE);
3898 result = LLVMBuildNot(ctx->ac.builder, result, "");
3899 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3900 }
3901
3902 static LLVMValueRef
3903 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3904 {
3905 LLVMValueRef result;
3906 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3907 result = LLVMBuildAnd(ctx->builder, ctx->abi.tg_size,
3908 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3909
3910 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3911 }
3912
3913 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3914 const nir_intrinsic_instr *instr)
3915 {
3916 LLVMValueRef ptr, result;
3917 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3918 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3919
3920 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3921 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3922 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3923 ptr, src, src1,
3924 LLVMAtomicOrderingSequentiallyConsistent,
3925 LLVMAtomicOrderingSequentiallyConsistent,
3926 false);
3927 } else {
3928 LLVMAtomicRMWBinOp op;
3929 switch (instr->intrinsic) {
3930 case nir_intrinsic_var_atomic_add:
3931 op = LLVMAtomicRMWBinOpAdd;
3932 break;
3933 case nir_intrinsic_var_atomic_umin:
3934 op = LLVMAtomicRMWBinOpUMin;
3935 break;
3936 case nir_intrinsic_var_atomic_umax:
3937 op = LLVMAtomicRMWBinOpUMax;
3938 break;
3939 case nir_intrinsic_var_atomic_imin:
3940 op = LLVMAtomicRMWBinOpMin;
3941 break;
3942 case nir_intrinsic_var_atomic_imax:
3943 op = LLVMAtomicRMWBinOpMax;
3944 break;
3945 case nir_intrinsic_var_atomic_and:
3946 op = LLVMAtomicRMWBinOpAnd;
3947 break;
3948 case nir_intrinsic_var_atomic_or:
3949 op = LLVMAtomicRMWBinOpOr;
3950 break;
3951 case nir_intrinsic_var_atomic_xor:
3952 op = LLVMAtomicRMWBinOpXor;
3953 break;
3954 case nir_intrinsic_var_atomic_exchange:
3955 op = LLVMAtomicRMWBinOpXchg;
3956 break;
3957 default:
3958 return NULL;
3959 }
3960
3961 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3962 LLVMAtomicOrderingSequentiallyConsistent,
3963 false);
3964 }
3965 return result;
3966 }
3967
3968 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
3969 enum glsl_interp_mode interp, unsigned location)
3970 {
3971 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3972
3973 switch (interp) {
3974 case INTERP_MODE_FLAT:
3975 default:
3976 return NULL;
3977 case INTERP_MODE_SMOOTH:
3978 case INTERP_MODE_NONE:
3979 if (location == INTERP_CENTER)
3980 return ctx->persp_center;
3981 else if (location == INTERP_CENTROID)
3982 return ctx->persp_centroid;
3983 else if (location == INTERP_SAMPLE)
3984 return ctx->persp_sample;
3985 break;
3986 case INTERP_MODE_NOPERSPECTIVE:
3987 if (location == INTERP_CENTER)
3988 return ctx->linear_center;
3989 else if (location == INTERP_CENTROID)
3990 return ctx->linear_centroid;
3991 else if (location == INTERP_SAMPLE)
3992 return ctx->linear_sample;
3993 break;
3994 }
3995 return NULL;
3996 }
3997
3998 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
3999 LLVMValueRef sample_id)
4000 {
4001 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4002
4003 LLVMValueRef result;
4004 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4005
4006 ptr = LLVMBuildBitCast(ctx->builder, ptr,
4007 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4008
4009 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
4010 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4011
4012 return result;
4013 }
4014
4015 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4016 {
4017 LLVMValueRef values[2];
4018
4019 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0], 32);
4020 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1], 32);
4021 return ac_build_gather_values(&ctx->ac, values, 2);
4022 }
4023
4024 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4025 {
4026 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4027 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4028 ctx->options->key.fs.log2_num_samples :
4029 ctx->options->key.fs.log2_ps_iter_samples;
4030
4031 /* The bit pattern matches that used by fixed function fragment
4032 * processing. */
4033 static const uint16_t ps_iter_masks[] = {
4034 0xffff, /* not used */
4035 0x5555,
4036 0x1111,
4037 0x0101,
4038 0x0001,
4039 };
4040 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4041
4042 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4043
4044 LLVMValueRef result, sample_id;
4045 sample_id = unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4046 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4047 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4048 return result;
4049 }
4050
4051 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4052 const nir_intrinsic_instr *instr)
4053 {
4054 LLVMValueRef result[4];
4055 LLVMValueRef interp_param, attr_number;
4056 unsigned location;
4057 unsigned chan;
4058 LLVMValueRef src_c0 = NULL;
4059 LLVMValueRef src_c1 = NULL;
4060 LLVMValueRef src0 = NULL;
4061 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4062 switch (instr->intrinsic) {
4063 case nir_intrinsic_interp_var_at_centroid:
4064 location = INTERP_CENTROID;
4065 break;
4066 case nir_intrinsic_interp_var_at_sample:
4067 case nir_intrinsic_interp_var_at_offset:
4068 location = INTERP_CENTER;
4069 src0 = get_src(ctx, instr->src[0]);
4070 break;
4071 default:
4072 break;
4073 }
4074
4075 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4076 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4077 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4078 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4079 LLVMValueRef sample_position;
4080 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4081
4082 /* fetch sample ID */
4083 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4084
4085 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4086 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4087 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4088 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4089 }
4090 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4091 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4092
4093 if (location == INTERP_CENTER) {
4094 LLVMValueRef ij_out[2];
4095 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4096
4097 /*
4098 * take the I then J parameters, and the DDX/Y for it, and
4099 * calculate the IJ inputs for the interpolator.
4100 * temp1 = ddx * offset/sample.x + I;
4101 * interp_param.I = ddy * offset/sample.y + temp1;
4102 * temp1 = ddx * offset/sample.x + J;
4103 * interp_param.J = ddy * offset/sample.y + temp1;
4104 */
4105 for (unsigned i = 0; i < 2; i++) {
4106 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4107 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4108 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4109 ddxy_out, ix_ll, "");
4110 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4111 ddxy_out, iy_ll, "");
4112 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4113 interp_param, ix_ll, "");
4114 LLVMValueRef temp1, temp2;
4115
4116 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4117 ctx->ac.f32, "");
4118
4119 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4120 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4121
4122 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4123 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4124
4125 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4126 temp2, ctx->ac.i32, "");
4127 }
4128 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4129
4130 }
4131
4132 for (chan = 0; chan < 4; chan++) {
4133 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4134
4135 if (interp_param) {
4136 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4137 interp_param, ctx->ac.v2f32, "");
4138 LLVMValueRef i = LLVMBuildExtractElement(
4139 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4140 LLVMValueRef j = LLVMBuildExtractElement(
4141 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4142
4143 result[chan] = ac_build_fs_interp(&ctx->ac,
4144 llvm_chan, attr_number,
4145 ctx->abi->prim_mask, i, j);
4146 } else {
4147 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4148 LLVMConstInt(ctx->ac.i32, 2, false),
4149 llvm_chan, attr_number,
4150 ctx->abi->prim_mask);
4151 }
4152 }
4153 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4154 instr->variables[0]->var->data.location_frac);
4155 }
4156
4157 static void
4158 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4159 {
4160 LLVMValueRef gs_next_vertex;
4161 LLVMValueRef can_emit;
4162 int idx;
4163 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4164
4165 assert(stream == 0);
4166
4167 /* Write vertex attribute values to GSVS ring */
4168 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4169 ctx->gs_next_vertex,
4170 "");
4171
4172 /* If this thread has already emitted the declared maximum number of
4173 * vertices, kill it: excessive vertex emissions are not supposed to
4174 * have any effect, and GS threads have no externally observable
4175 * effects other than emitting vertices.
4176 */
4177 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4178 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4179 ac_build_kill_if_false(&ctx->ac, can_emit);
4180
4181 /* loop num outputs */
4182 idx = 0;
4183 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4184 LLVMValueRef *out_ptr = &addrs[i * 4];
4185 int length = 4;
4186 int slot = idx;
4187 int slot_inc = 1;
4188
4189 if (!(ctx->output_mask & (1ull << i)))
4190 continue;
4191
4192 if (i == VARYING_SLOT_CLIP_DIST0) {
4193 /* pack clip and cull into a single set of slots */
4194 length = ctx->num_output_clips + ctx->num_output_culls;
4195 if (length > 4)
4196 slot_inc = 2;
4197 }
4198 for (unsigned j = 0; j < length; j++) {
4199 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4200 out_ptr[j], "");
4201 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4202 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4203 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4204
4205 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4206
4207 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4208 out_val, 1,
4209 voffset, ctx->gs2vs_offset, 0,
4210 1, 1, true, true);
4211 }
4212 idx += slot_inc;
4213 }
4214
4215 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4216 ctx->ac.i32_1, "");
4217 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4218
4219 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4220 }
4221
4222 static void
4223 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4224 {
4225 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4226 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4227 }
4228
4229 static LLVMValueRef
4230 load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
4231 unsigned num_components)
4232 {
4233 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4234
4235 LLVMValueRef coord[4] = {
4236 ctx->tes_u,
4237 ctx->tes_v,
4238 ctx->ac.f32_0,
4239 ctx->ac.f32_0,
4240 };
4241
4242 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4243 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4244 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4245
4246 return ac_build_gather_values(&ctx->ac, coord, 3);
4247 }
4248
4249 static LLVMValueRef
4250 load_patch_vertices_in(struct ac_shader_abi *abi)
4251 {
4252 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4253 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4254 }
4255
4256 static void visit_intrinsic(struct ac_nir_context *ctx,
4257 nir_intrinsic_instr *instr)
4258 {
4259 LLVMValueRef result = NULL;
4260
4261 switch (instr->intrinsic) {
4262 case nir_intrinsic_ballot:
4263 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4264 break;
4265 case nir_intrinsic_read_invocation:
4266 case nir_intrinsic_read_first_invocation: {
4267 LLVMValueRef args[2];
4268
4269 /* Value */
4270 args[0] = get_src(ctx, instr->src[0]);
4271
4272 unsigned num_args;
4273 const char *intr_name;
4274 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4275 num_args = 2;
4276 intr_name = "llvm.amdgcn.readlane";
4277
4278 /* Invocation */
4279 args[1] = get_src(ctx, instr->src[1]);
4280 } else {
4281 num_args = 1;
4282 intr_name = "llvm.amdgcn.readfirstlane";
4283 }
4284
4285 /* We currently have no other way to prevent LLVM from lifting the icmp
4286 * calls to a dominating basic block.
4287 */
4288 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4289
4290 result = ac_build_intrinsic(&ctx->ac, intr_name,
4291 ctx->ac.i32, args, num_args,
4292 AC_FUNC_ATTR_READNONE |
4293 AC_FUNC_ATTR_CONVERGENT);
4294 break;
4295 }
4296 case nir_intrinsic_load_subgroup_invocation:
4297 result = ac_get_thread_id(&ctx->ac);
4298 break;
4299 case nir_intrinsic_load_work_group_id: {
4300 LLVMValueRef values[3];
4301
4302 for (int i = 0; i < 3; i++) {
4303 values[i] = ctx->abi->workgroup_ids[i] ?
4304 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4305 }
4306
4307 result = ac_build_gather_values(&ctx->ac, values, 3);
4308 break;
4309 }
4310 case nir_intrinsic_load_base_vertex: {
4311 result = ctx->abi->base_vertex;
4312 break;
4313 }
4314 case nir_intrinsic_load_local_group_size:
4315 result = ctx->abi->load_local_group_size(ctx->abi);
4316 break;
4317 case nir_intrinsic_load_vertex_id_zero_base: {
4318 result = ctx->abi->vertex_id;
4319 break;
4320 }
4321 case nir_intrinsic_load_local_invocation_id: {
4322 result = ctx->abi->local_invocation_ids;
4323 break;
4324 }
4325 case nir_intrinsic_load_base_instance:
4326 result = ctx->abi->start_instance;
4327 break;
4328 case nir_intrinsic_load_draw_id:
4329 result = ctx->abi->draw_id;
4330 break;
4331 case nir_intrinsic_load_view_index:
4332 result = ctx->abi->view_index;
4333 break;
4334 case nir_intrinsic_load_invocation_id:
4335 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4336 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4337 else
4338 result = ctx->abi->gs_invocation_id;
4339 break;
4340 case nir_intrinsic_load_primitive_id:
4341 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4342 result = ctx->abi->gs_prim_id;
4343 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4344 result = ctx->abi->tcs_patch_id;
4345 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4346 result = ctx->abi->tes_patch_id;
4347 } else
4348 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4349 break;
4350 case nir_intrinsic_load_sample_id:
4351 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4352 break;
4353 case nir_intrinsic_load_sample_pos:
4354 result = load_sample_pos(ctx);
4355 break;
4356 case nir_intrinsic_load_sample_mask_in:
4357 result = ctx->abi->load_sample_mask_in(ctx->abi);
4358 break;
4359 case nir_intrinsic_load_frag_coord: {
4360 LLVMValueRef values[4] = {
4361 ctx->abi->frag_pos[0],
4362 ctx->abi->frag_pos[1],
4363 ctx->abi->frag_pos[2],
4364 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4365 };
4366 result = ac_build_gather_values(&ctx->ac, values, 4);
4367 break;
4368 }
4369 case nir_intrinsic_load_front_face:
4370 result = ctx->abi->front_face;
4371 break;
4372 case nir_intrinsic_load_helper_invocation:
4373 result = visit_load_helper_invocation(ctx);
4374 break;
4375 case nir_intrinsic_load_instance_id:
4376 result = ctx->abi->instance_id;
4377 break;
4378 case nir_intrinsic_load_num_work_groups:
4379 result = ctx->abi->num_work_groups;
4380 break;
4381 case nir_intrinsic_load_local_invocation_index:
4382 result = visit_load_local_invocation_index(ctx->nctx);
4383 break;
4384 case nir_intrinsic_load_push_constant:
4385 result = visit_load_push_constant(ctx->nctx, instr);
4386 break;
4387 case nir_intrinsic_vulkan_resource_index: {
4388 LLVMValueRef index = get_src(ctx, instr->src[0]);
4389 unsigned desc_set = nir_intrinsic_desc_set(instr);
4390 unsigned binding = nir_intrinsic_binding(instr);
4391
4392 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4393 binding);
4394 break;
4395 }
4396 case nir_intrinsic_vulkan_resource_reindex:
4397 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4398 break;
4399 case nir_intrinsic_store_ssbo:
4400 visit_store_ssbo(ctx, instr);
4401 break;
4402 case nir_intrinsic_load_ssbo:
4403 result = visit_load_buffer(ctx, instr);
4404 break;
4405 case nir_intrinsic_ssbo_atomic_add:
4406 case nir_intrinsic_ssbo_atomic_imin:
4407 case nir_intrinsic_ssbo_atomic_umin:
4408 case nir_intrinsic_ssbo_atomic_imax:
4409 case nir_intrinsic_ssbo_atomic_umax:
4410 case nir_intrinsic_ssbo_atomic_and:
4411 case nir_intrinsic_ssbo_atomic_or:
4412 case nir_intrinsic_ssbo_atomic_xor:
4413 case nir_intrinsic_ssbo_atomic_exchange:
4414 case nir_intrinsic_ssbo_atomic_comp_swap:
4415 result = visit_atomic_ssbo(ctx, instr);
4416 break;
4417 case nir_intrinsic_load_ubo:
4418 result = visit_load_ubo_buffer(ctx, instr);
4419 break;
4420 case nir_intrinsic_get_buffer_size:
4421 result = visit_get_buffer_size(ctx, instr);
4422 break;
4423 case nir_intrinsic_load_var:
4424 result = visit_load_var(ctx, instr);
4425 break;
4426 case nir_intrinsic_store_var:
4427 visit_store_var(ctx, instr);
4428 break;
4429 case nir_intrinsic_image_load:
4430 result = visit_image_load(ctx, instr);
4431 break;
4432 case nir_intrinsic_image_store:
4433 visit_image_store(ctx, instr);
4434 break;
4435 case nir_intrinsic_image_atomic_add:
4436 case nir_intrinsic_image_atomic_min:
4437 case nir_intrinsic_image_atomic_max:
4438 case nir_intrinsic_image_atomic_and:
4439 case nir_intrinsic_image_atomic_or:
4440 case nir_intrinsic_image_atomic_xor:
4441 case nir_intrinsic_image_atomic_exchange:
4442 case nir_intrinsic_image_atomic_comp_swap:
4443 result = visit_image_atomic(ctx, instr);
4444 break;
4445 case nir_intrinsic_image_size:
4446 result = visit_image_size(ctx, instr);
4447 break;
4448 case nir_intrinsic_shader_clock:
4449 result = ac_build_shader_clock(&ctx->ac);
4450 break;
4451 case nir_intrinsic_discard:
4452 case nir_intrinsic_discard_if:
4453 emit_discard(ctx, instr);
4454 break;
4455 case nir_intrinsic_memory_barrier:
4456 case nir_intrinsic_group_memory_barrier:
4457 case nir_intrinsic_memory_barrier_atomic_counter:
4458 case nir_intrinsic_memory_barrier_buffer:
4459 case nir_intrinsic_memory_barrier_image:
4460 case nir_intrinsic_memory_barrier_shared:
4461 emit_membar(&ctx->ac, instr);
4462 break;
4463 case nir_intrinsic_barrier:
4464 emit_barrier(&ctx->ac, ctx->stage);
4465 break;
4466 case nir_intrinsic_var_atomic_add:
4467 case nir_intrinsic_var_atomic_imin:
4468 case nir_intrinsic_var_atomic_umin:
4469 case nir_intrinsic_var_atomic_imax:
4470 case nir_intrinsic_var_atomic_umax:
4471 case nir_intrinsic_var_atomic_and:
4472 case nir_intrinsic_var_atomic_or:
4473 case nir_intrinsic_var_atomic_xor:
4474 case nir_intrinsic_var_atomic_exchange:
4475 case nir_intrinsic_var_atomic_comp_swap:
4476 result = visit_var_atomic(ctx->nctx, instr);
4477 break;
4478 case nir_intrinsic_interp_var_at_centroid:
4479 case nir_intrinsic_interp_var_at_sample:
4480 case nir_intrinsic_interp_var_at_offset:
4481 result = visit_interp(ctx, instr);
4482 break;
4483 case nir_intrinsic_emit_vertex:
4484 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->outputs);
4485 break;
4486 case nir_intrinsic_end_primitive:
4487 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4488 break;
4489 case nir_intrinsic_load_tess_coord:
4490 result = ctx->abi->load_tess_coord(ctx->abi, NULL, 0);
4491 break;
4492 case nir_intrinsic_load_tess_level_outer:
4493 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4494 break;
4495 case nir_intrinsic_load_tess_level_inner:
4496 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4497 break;
4498 case nir_intrinsic_load_patch_vertices_in:
4499 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4500 break;
4501 case nir_intrinsic_vote_all: {
4502 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4503 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4504 break;
4505 }
4506 case nir_intrinsic_vote_any: {
4507 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4508 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4509 break;
4510 }
4511 case nir_intrinsic_vote_eq: {
4512 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4513 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4514 break;
4515 }
4516 default:
4517 fprintf(stderr, "Unknown intrinsic: ");
4518 nir_print_instr(&instr->instr, stderr);
4519 fprintf(stderr, "\n");
4520 break;
4521 }
4522 if (result) {
4523 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4524 }
4525 }
4526
4527 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4528 LLVMValueRef buffer_ptr, bool write)
4529 {
4530 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4531 LLVMValueRef result;
4532
4533 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4534
4535 result = LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4536 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4537
4538 return result;
4539 }
4540
4541 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4542 {
4543 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4544 LLVMValueRef result;
4545
4546 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4547
4548 result = LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4549 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4550
4551 return result;
4552 }
4553
4554 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4555 unsigned descriptor_set,
4556 unsigned base_index,
4557 unsigned constant_index,
4558 LLVMValueRef index,
4559 enum ac_descriptor_type desc_type,
4560 bool image, bool write)
4561 {
4562 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4563 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4564 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4565 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4566 unsigned offset = binding->offset;
4567 unsigned stride = binding->size;
4568 unsigned type_size;
4569 LLVMBuilderRef builder = ctx->builder;
4570 LLVMTypeRef type;
4571
4572 assert(base_index < layout->binding_count);
4573
4574 switch (desc_type) {
4575 case AC_DESC_IMAGE:
4576 type = ctx->ac.v8i32;
4577 type_size = 32;
4578 break;
4579 case AC_DESC_FMASK:
4580 type = ctx->ac.v8i32;
4581 offset += 32;
4582 type_size = 32;
4583 break;
4584 case AC_DESC_SAMPLER:
4585 type = ctx->ac.v4i32;
4586 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4587 offset += 64;
4588
4589 type_size = 16;
4590 break;
4591 case AC_DESC_BUFFER:
4592 type = ctx->ac.v4i32;
4593 type_size = 16;
4594 break;
4595 default:
4596 unreachable("invalid desc_type\n");
4597 }
4598
4599 offset += constant_index * stride;
4600
4601 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4602 (!index || binding->immutable_samplers_equal)) {
4603 if (binding->immutable_samplers_equal)
4604 constant_index = 0;
4605
4606 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4607
4608 LLVMValueRef constants[] = {
4609 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4610 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4611 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4612 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4613 };
4614 return ac_build_gather_values(&ctx->ac, constants, 4);
4615 }
4616
4617 assert(stride % type_size == 0);
4618
4619 if (!index)
4620 index = ctx->ac.i32_0;
4621
4622 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4623
4624 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4625 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4626
4627 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4628 }
4629
4630 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4631 const nir_deref_var *deref,
4632 enum ac_descriptor_type desc_type,
4633 const nir_tex_instr *tex_instr,
4634 bool image, bool write)
4635 {
4636 LLVMValueRef index = NULL;
4637 unsigned constant_index = 0;
4638 unsigned descriptor_set;
4639 unsigned base_index;
4640
4641 if (!deref) {
4642 assert(tex_instr && !image);
4643 descriptor_set = 0;
4644 base_index = tex_instr->sampler_index;
4645 } else {
4646 const nir_deref *tail = &deref->deref;
4647 while (tail->child) {
4648 const nir_deref_array *child = nir_deref_as_array(tail->child);
4649 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4650
4651 if (!array_size)
4652 array_size = 1;
4653
4654 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4655
4656 if (child->deref_array_type == nir_deref_array_type_indirect) {
4657 LLVMValueRef indirect = get_src(ctx, child->indirect);
4658
4659 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4660 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4661
4662 if (!index)
4663 index = indirect;
4664 else
4665 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4666 }
4667
4668 constant_index += child->base_offset * array_size;
4669
4670 tail = &child->deref;
4671 }
4672 descriptor_set = deref->var->data.descriptor_set;
4673 base_index = deref->var->data.binding;
4674 }
4675
4676 return ctx->abi->load_sampler_desc(ctx->abi,
4677 descriptor_set,
4678 base_index,
4679 constant_index, index,
4680 desc_type, image, write);
4681 }
4682
4683 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4684 struct ac_image_args *args,
4685 const nir_tex_instr *instr,
4686 nir_texop op,
4687 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4688 LLVMValueRef *param, unsigned count,
4689 unsigned dmask)
4690 {
4691 unsigned is_rect = 0;
4692 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4693
4694 if (op == nir_texop_lod)
4695 da = false;
4696 /* Pad to power of two vector */
4697 while (count < util_next_power_of_two(count))
4698 param[count++] = LLVMGetUndef(ctx->i32);
4699
4700 if (count > 1)
4701 args->addr = ac_build_gather_values(ctx, param, count);
4702 else
4703 args->addr = param[0];
4704
4705 args->resource = res_ptr;
4706 args->sampler = samp_ptr;
4707
4708 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4709 args->addr = param[0];
4710 return;
4711 }
4712
4713 args->dmask = dmask;
4714 args->unorm = is_rect;
4715 args->da = da;
4716 }
4717
4718 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4719 *
4720 * SI-CI:
4721 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4722 * filtering manually. The driver sets img7 to a mask clearing
4723 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4724 * s_and_b32 samp0, samp0, img7
4725 *
4726 * VI:
4727 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4728 */
4729 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4730 LLVMValueRef res, LLVMValueRef samp)
4731 {
4732 LLVMBuilderRef builder = ctx->ac.builder;
4733 LLVMValueRef img7, samp0;
4734
4735 if (ctx->ac.chip_class >= VI)
4736 return samp;
4737
4738 img7 = LLVMBuildExtractElement(builder, res,
4739 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4740 samp0 = LLVMBuildExtractElement(builder, samp,
4741 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4742 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4743 return LLVMBuildInsertElement(builder, samp, samp0,
4744 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4745 }
4746
4747 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4748 nir_tex_instr *instr,
4749 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4750 LLVMValueRef *fmask_ptr)
4751 {
4752 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4753 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4754 else
4755 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4756 if (samp_ptr) {
4757 if (instr->sampler)
4758 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4759 else
4760 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4761 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4762 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4763 }
4764 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4765 instr->op == nir_texop_samples_identical))
4766 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4767 }
4768
4769 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4770 LLVMValueRef coord)
4771 {
4772 coord = ac_to_float(ctx, coord);
4773 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4774 coord = ac_to_integer(ctx, coord);
4775 return coord;
4776 }
4777
4778 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4779 {
4780 LLVMValueRef result = NULL;
4781 struct ac_image_args args = { 0 };
4782 unsigned dmask = 0xf;
4783 LLVMValueRef address[16];
4784 LLVMValueRef coords[5];
4785 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4786 LLVMValueRef bias = NULL, offsets = NULL;
4787 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4788 LLVMValueRef ddx = NULL, ddy = NULL;
4789 LLVMValueRef derivs[6];
4790 unsigned chan, count = 0;
4791 unsigned const_src = 0, num_deriv_comp = 0;
4792 bool lod_is_zero = false;
4793
4794 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4795
4796 for (unsigned i = 0; i < instr->num_srcs; i++) {
4797 switch (instr->src[i].src_type) {
4798 case nir_tex_src_coord:
4799 coord = get_src(ctx, instr->src[i].src);
4800 break;
4801 case nir_tex_src_projector:
4802 break;
4803 case nir_tex_src_comparator:
4804 comparator = get_src(ctx, instr->src[i].src);
4805 break;
4806 case nir_tex_src_offset:
4807 offsets = get_src(ctx, instr->src[i].src);
4808 const_src = i;
4809 break;
4810 case nir_tex_src_bias:
4811 bias = get_src(ctx, instr->src[i].src);
4812 break;
4813 case nir_tex_src_lod: {
4814 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4815
4816 if (val && val->i32[0] == 0)
4817 lod_is_zero = true;
4818 lod = get_src(ctx, instr->src[i].src);
4819 break;
4820 }
4821 case nir_tex_src_ms_index:
4822 sample_index = get_src(ctx, instr->src[i].src);
4823 break;
4824 case nir_tex_src_ms_mcs:
4825 break;
4826 case nir_tex_src_ddx:
4827 ddx = get_src(ctx, instr->src[i].src);
4828 num_deriv_comp = instr->src[i].src.ssa->num_components;
4829 break;
4830 case nir_tex_src_ddy:
4831 ddy = get_src(ctx, instr->src[i].src);
4832 break;
4833 case nir_tex_src_texture_offset:
4834 case nir_tex_src_sampler_offset:
4835 case nir_tex_src_plane:
4836 default:
4837 break;
4838 }
4839 }
4840
4841 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4842 result = get_buffer_size(ctx, res_ptr, true);
4843 goto write_result;
4844 }
4845
4846 if (instr->op == nir_texop_texture_samples) {
4847 LLVMValueRef res, samples, is_msaa;
4848 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4849 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4850 LLVMConstInt(ctx->ac.i32, 3, false), "");
4851 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4852 LLVMConstInt(ctx->ac.i32, 28, false), "");
4853 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4854 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4855 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4856 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4857
4858 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4859 LLVMConstInt(ctx->ac.i32, 16, false), "");
4860 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4861 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4862 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4863 samples, "");
4864 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4865 ctx->ac.i32_1, "");
4866 result = samples;
4867 goto write_result;
4868 }
4869
4870 if (coord)
4871 for (chan = 0; chan < instr->coord_components; chan++)
4872 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4873
4874 if (offsets && instr->op != nir_texop_txf) {
4875 LLVMValueRef offset[3], pack;
4876 for (chan = 0; chan < 3; ++chan)
4877 offset[chan] = ctx->ac.i32_0;
4878
4879 args.offset = true;
4880 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4881 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4882 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4883 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4884 if (chan)
4885 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4886 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4887 }
4888 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4889 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4890 address[count++] = pack;
4891
4892 }
4893 /* pack LOD bias value */
4894 if (instr->op == nir_texop_txb && bias) {
4895 address[count++] = bias;
4896 }
4897
4898 /* Pack depth comparison value */
4899 if (instr->is_shadow && comparator) {
4900 LLVMValueRef z = ac_to_float(&ctx->ac,
4901 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4902
4903 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4904 * so the depth comparison value isn't clamped for Z16 and
4905 * Z24 anymore. Do it manually here.
4906 *
4907 * It's unnecessary if the original texture format was
4908 * Z32_FLOAT, but we don't know that here.
4909 */
4910 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4911 z = ac_build_clamp(&ctx->ac, z);
4912
4913 address[count++] = z;
4914 }
4915
4916 /* pack derivatives */
4917 if (ddx || ddy) {
4918 int num_src_deriv_channels, num_dest_deriv_channels;
4919 switch (instr->sampler_dim) {
4920 case GLSL_SAMPLER_DIM_3D:
4921 case GLSL_SAMPLER_DIM_CUBE:
4922 num_deriv_comp = 3;
4923 num_src_deriv_channels = 3;
4924 num_dest_deriv_channels = 3;
4925 break;
4926 case GLSL_SAMPLER_DIM_2D:
4927 default:
4928 num_src_deriv_channels = 2;
4929 num_dest_deriv_channels = 2;
4930 num_deriv_comp = 2;
4931 break;
4932 case GLSL_SAMPLER_DIM_1D:
4933 num_src_deriv_channels = 1;
4934 if (ctx->ac.chip_class >= GFX9) {
4935 num_dest_deriv_channels = 2;
4936 num_deriv_comp = 2;
4937 } else {
4938 num_dest_deriv_channels = 1;
4939 num_deriv_comp = 1;
4940 }
4941 break;
4942 }
4943
4944 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4945 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4946 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4947 }
4948 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4949 derivs[i] = ctx->ac.f32_0;
4950 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4951 }
4952 }
4953
4954 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4955 for (chan = 0; chan < instr->coord_components; chan++)
4956 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4957 if (instr->coord_components == 3)
4958 coords[3] = LLVMGetUndef(ctx->ac.f32);
4959 ac_prepare_cube_coords(&ctx->ac,
4960 instr->op == nir_texop_txd, instr->is_array,
4961 instr->op == nir_texop_lod, coords, derivs);
4962 if (num_deriv_comp)
4963 num_deriv_comp--;
4964 }
4965
4966 if (ddx || ddy) {
4967 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4968 address[count++] = derivs[i];
4969 }
4970
4971 /* Pack texture coordinates */
4972 if (coord) {
4973 address[count++] = coords[0];
4974 if (instr->coord_components > 1) {
4975 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4976 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4977 }
4978 address[count++] = coords[1];
4979 }
4980 if (instr->coord_components > 2) {
4981 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4982 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4983 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4984 instr->op != nir_texop_txf) {
4985 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4986 }
4987 address[count++] = coords[2];
4988 }
4989
4990 if (ctx->ac.chip_class >= GFX9) {
4991 LLVMValueRef filler;
4992 if (instr->op == nir_texop_txf)
4993 filler = ctx->ac.i32_0;
4994 else
4995 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4996
4997 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4998 /* No nir_texop_lod, because it does not take a slice
4999 * even with array textures. */
5000 if (instr->is_array && instr->op != nir_texop_lod ) {
5001 address[count] = address[count - 1];
5002 address[count - 1] = filler;
5003 count++;
5004 } else
5005 address[count++] = filler;
5006 }
5007 }
5008 }
5009
5010 /* Pack LOD */
5011 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5012 instr->op == nir_texop_txf)) {
5013 address[count++] = lod;
5014 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5015 address[count++] = sample_index;
5016 } else if(instr->op == nir_texop_txs) {
5017 count = 0;
5018 if (lod)
5019 address[count++] = lod;
5020 else
5021 address[count++] = ctx->ac.i32_0;
5022 }
5023
5024 for (chan = 0; chan < count; chan++) {
5025 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5026 address[chan], ctx->ac.i32, "");
5027 }
5028
5029 if (instr->op == nir_texop_samples_identical) {
5030 LLVMValueRef txf_address[4];
5031 struct ac_image_args txf_args = { 0 };
5032 unsigned txf_count = count;
5033 memcpy(txf_address, address, sizeof(txf_address));
5034
5035 if (!instr->is_array)
5036 txf_address[2] = ctx->ac.i32_0;
5037 txf_address[3] = ctx->ac.i32_0;
5038
5039 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5040 fmask_ptr, NULL,
5041 txf_address, txf_count, 0xf);
5042
5043 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5044
5045 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5046 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5047 goto write_result;
5048 }
5049
5050 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5051 instr->op != nir_texop_txs) {
5052 unsigned sample_chan = instr->is_array ? 3 : 2;
5053 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5054 address[0],
5055 address[1],
5056 instr->is_array ? address[2] : NULL,
5057 address[sample_chan],
5058 fmask_ptr);
5059 }
5060
5061 if (offsets && instr->op == nir_texop_txf) {
5062 nir_const_value *const_offset =
5063 nir_src_as_const_value(instr->src[const_src].src);
5064 int num_offsets = instr->src[const_src].src.ssa->num_components;
5065 assert(const_offset);
5066 num_offsets = MIN2(num_offsets, instr->coord_components);
5067 if (num_offsets > 2)
5068 address[2] = LLVMBuildAdd(ctx->ac.builder,
5069 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5070 if (num_offsets > 1)
5071 address[1] = LLVMBuildAdd(ctx->ac.builder,
5072 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5073 address[0] = LLVMBuildAdd(ctx->ac.builder,
5074 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5075
5076 }
5077
5078 /* TODO TG4 support */
5079 if (instr->op == nir_texop_tg4) {
5080 if (instr->is_shadow)
5081 dmask = 1;
5082 else
5083 dmask = 1 << instr->component;
5084 }
5085 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5086 res_ptr, samp_ptr, address, count, dmask);
5087
5088 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5089
5090 if (instr->op == nir_texop_query_levels)
5091 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5092 else if (instr->is_shadow && instr->is_new_style_shadow &&
5093 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5094 instr->op != nir_texop_tg4)
5095 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5096 else if (instr->op == nir_texop_txs &&
5097 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5098 instr->is_array) {
5099 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5100 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5101 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5102 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5103 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5104 } else if (ctx->ac.chip_class >= GFX9 &&
5105 instr->op == nir_texop_txs &&
5106 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5107 instr->is_array) {
5108 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5109 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5110 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5111 ctx->ac.i32_1, "");
5112 } else if (instr->dest.ssa.num_components != 4)
5113 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5114
5115 write_result:
5116 if (result) {
5117 assert(instr->dest.is_ssa);
5118 result = ac_to_integer(&ctx->ac, result);
5119 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5120 }
5121 }
5122
5123
5124 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5125 {
5126 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5127 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5128
5129 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5130 _mesa_hash_table_insert(ctx->phis, instr, result);
5131 }
5132
5133 static void visit_post_phi(struct ac_nir_context *ctx,
5134 nir_phi_instr *instr,
5135 LLVMValueRef llvm_phi)
5136 {
5137 nir_foreach_phi_src(src, instr) {
5138 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5139 LLVMValueRef llvm_src = get_src(ctx, src->src);
5140
5141 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5142 }
5143 }
5144
5145 static void phi_post_pass(struct ac_nir_context *ctx)
5146 {
5147 struct hash_entry *entry;
5148 hash_table_foreach(ctx->phis, entry) {
5149 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5150 (LLVMValueRef)entry->data);
5151 }
5152 }
5153
5154
5155 static void visit_ssa_undef(struct ac_nir_context *ctx,
5156 const nir_ssa_undef_instr *instr)
5157 {
5158 unsigned num_components = instr->def.num_components;
5159 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5160 LLVMValueRef undef;
5161
5162 if (num_components == 1)
5163 undef = LLVMGetUndef(type);
5164 else {
5165 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5166 }
5167 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5168 }
5169
5170 static void visit_jump(struct ac_nir_context *ctx,
5171 const nir_jump_instr *instr)
5172 {
5173 switch (instr->type) {
5174 case nir_jump_break:
5175 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5176 LLVMClearInsertionPosition(ctx->ac.builder);
5177 break;
5178 case nir_jump_continue:
5179 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5180 LLVMClearInsertionPosition(ctx->ac.builder);
5181 break;
5182 default:
5183 fprintf(stderr, "Unknown NIR jump instr: ");
5184 nir_print_instr(&instr->instr, stderr);
5185 fprintf(stderr, "\n");
5186 abort();
5187 }
5188 }
5189
5190 static void visit_cf_list(struct ac_nir_context *ctx,
5191 struct exec_list *list);
5192
5193 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5194 {
5195 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5196 nir_foreach_instr(instr, block)
5197 {
5198 switch (instr->type) {
5199 case nir_instr_type_alu:
5200 visit_alu(ctx, nir_instr_as_alu(instr));
5201 break;
5202 case nir_instr_type_load_const:
5203 visit_load_const(ctx, nir_instr_as_load_const(instr));
5204 break;
5205 case nir_instr_type_intrinsic:
5206 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5207 break;
5208 case nir_instr_type_tex:
5209 visit_tex(ctx, nir_instr_as_tex(instr));
5210 break;
5211 case nir_instr_type_phi:
5212 visit_phi(ctx, nir_instr_as_phi(instr));
5213 break;
5214 case nir_instr_type_ssa_undef:
5215 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5216 break;
5217 case nir_instr_type_jump:
5218 visit_jump(ctx, nir_instr_as_jump(instr));
5219 break;
5220 default:
5221 fprintf(stderr, "Unknown NIR instr type: ");
5222 nir_print_instr(instr, stderr);
5223 fprintf(stderr, "\n");
5224 abort();
5225 }
5226 }
5227
5228 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5229 }
5230
5231 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5232 {
5233 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5234
5235 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5236 LLVMBasicBlockRef merge_block =
5237 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5238 LLVMBasicBlockRef if_block =
5239 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5240 LLVMBasicBlockRef else_block = merge_block;
5241 if (!exec_list_is_empty(&if_stmt->else_list))
5242 else_block = LLVMAppendBasicBlockInContext(
5243 ctx->ac.context, fn, "");
5244
5245 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5246 ctx->ac.i32_0, "");
5247 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5248
5249 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5250 visit_cf_list(ctx, &if_stmt->then_list);
5251 if (LLVMGetInsertBlock(ctx->ac.builder))
5252 LLVMBuildBr(ctx->ac.builder, merge_block);
5253
5254 if (!exec_list_is_empty(&if_stmt->else_list)) {
5255 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5256 visit_cf_list(ctx, &if_stmt->else_list);
5257 if (LLVMGetInsertBlock(ctx->ac.builder))
5258 LLVMBuildBr(ctx->ac.builder, merge_block);
5259 }
5260
5261 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5262 }
5263
5264 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5265 {
5266 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5267 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5268 LLVMBasicBlockRef break_parent = ctx->break_block;
5269
5270 ctx->continue_block =
5271 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5272 ctx->break_block =
5273 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5274
5275 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5276 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5277 visit_cf_list(ctx, &loop->body);
5278
5279 if (LLVMGetInsertBlock(ctx->ac.builder))
5280 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5281 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5282
5283 ctx->continue_block = continue_parent;
5284 ctx->break_block = break_parent;
5285 }
5286
5287 static void visit_cf_list(struct ac_nir_context *ctx,
5288 struct exec_list *list)
5289 {
5290 foreach_list_typed(nir_cf_node, node, node, list)
5291 {
5292 switch (node->type) {
5293 case nir_cf_node_block:
5294 visit_block(ctx, nir_cf_node_as_block(node));
5295 break;
5296
5297 case nir_cf_node_if:
5298 visit_if(ctx, nir_cf_node_as_if(node));
5299 break;
5300
5301 case nir_cf_node_loop:
5302 visit_loop(ctx, nir_cf_node_as_loop(node));
5303 break;
5304
5305 default:
5306 assert(0);
5307 }
5308 }
5309 }
5310
5311 static void
5312 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5313 struct nir_variable *variable)
5314 {
5315 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5316 LLVMValueRef t_offset;
5317 LLVMValueRef t_list;
5318 LLVMValueRef input;
5319 LLVMValueRef buffer_index;
5320 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5321 int idx = variable->data.location;
5322 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5323 uint8_t input_usage_mask =
5324 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5325 unsigned num_channels = util_last_bit(input_usage_mask);
5326
5327 variable->data.driver_location = idx * 4;
5328
5329 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5330 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5331 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5332 ctx->abi.start_instance, "");
5333 if (ctx->options->key.vs.as_ls) {
5334 ctx->shader_info->vs.vgpr_comp_cnt =
5335 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5336 } else {
5337 ctx->shader_info->vs.vgpr_comp_cnt =
5338 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5339 }
5340 } else
5341 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5342 ctx->abi.base_vertex, "");
5343 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5344
5345 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5346
5347 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5348 buffer_index,
5349 ctx->ac.i32_0,
5350 num_channels, false, true);
5351
5352 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5353
5354 for (unsigned chan = 0; chan < 4; chan++) {
5355 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5356 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5357 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5358 input, llvm_chan, ""));
5359 }
5360 }
5361 }
5362
5363 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5364 unsigned attr,
5365 LLVMValueRef interp_param,
5366 LLVMValueRef prim_mask,
5367 LLVMValueRef result[4])
5368 {
5369 LLVMValueRef attr_number;
5370 unsigned chan;
5371 LLVMValueRef i, j;
5372 bool interp = interp_param != NULL;
5373
5374 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5375
5376 /* fs.constant returns the param from the middle vertex, so it's not
5377 * really useful for flat shading. It's meant to be used for custom
5378 * interpolation (but the intrinsic can't fetch from the other two
5379 * vertices).
5380 *
5381 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5382 * to do the right thing. The only reason we use fs.constant is that
5383 * fs.interp cannot be used on integers, because they can be equal
5384 * to NaN.
5385 */
5386 if (interp) {
5387 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5388 ctx->ac.v2f32, "");
5389
5390 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5391 ctx->ac.i32_0, "");
5392 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5393 ctx->ac.i32_1, "");
5394 }
5395
5396 for (chan = 0; chan < 4; chan++) {
5397 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5398
5399 if (interp) {
5400 result[chan] = ac_build_fs_interp(&ctx->ac,
5401 llvm_chan,
5402 attr_number,
5403 prim_mask, i, j);
5404 } else {
5405 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5406 LLVMConstInt(ctx->ac.i32, 2, false),
5407 llvm_chan,
5408 attr_number,
5409 prim_mask);
5410 }
5411 }
5412 }
5413
5414 static void
5415 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5416 struct nir_variable *variable)
5417 {
5418 int idx = variable->data.location;
5419 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5420 LLVMValueRef interp;
5421
5422 variable->data.driver_location = idx * 4;
5423 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5424
5425 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5426 unsigned interp_type;
5427 if (variable->data.sample) {
5428 interp_type = INTERP_SAMPLE;
5429 ctx->shader_info->info.ps.force_persample = true;
5430 } else if (variable->data.centroid)
5431 interp_type = INTERP_CENTROID;
5432 else
5433 interp_type = INTERP_CENTER;
5434
5435 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5436 } else
5437 interp = NULL;
5438
5439 for (unsigned i = 0; i < attrib_count; ++i)
5440 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5441
5442 }
5443
5444 static void
5445 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5446 struct nir_shader *nir) {
5447 nir_foreach_variable(variable, &nir->inputs)
5448 handle_vs_input_decl(ctx, variable);
5449 }
5450
5451 static void
5452 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5453 struct nir_shader *nir)
5454 {
5455 if (!ctx->options->key.fs.multisample)
5456 return;
5457
5458 bool uses_center = false;
5459 bool uses_centroid = false;
5460 nir_foreach_variable(variable, &nir->inputs) {
5461 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5462 variable->data.sample)
5463 continue;
5464
5465 if (variable->data.centroid)
5466 uses_centroid = true;
5467 else
5468 uses_center = true;
5469 }
5470
5471 if (uses_center && uses_centroid) {
5472 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5473 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5474 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5475 }
5476 }
5477
5478 static void
5479 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5480 struct nir_shader *nir)
5481 {
5482 prepare_interp_optimize(ctx, nir);
5483
5484 nir_foreach_variable(variable, &nir->inputs)
5485 handle_fs_input_decl(ctx, variable);
5486
5487 unsigned index = 0;
5488
5489 if (ctx->shader_info->info.ps.uses_input_attachments ||
5490 ctx->shader_info->info.needs_multiview_view_index)
5491 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5492
5493 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5494 LLVMValueRef interp_param;
5495 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5496
5497 if (!(ctx->input_mask & (1ull << i)))
5498 continue;
5499
5500 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5501 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5502 interp_param = *inputs;
5503 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5504 inputs);
5505
5506 if (!interp_param)
5507 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5508 ++index;
5509 } else if (i == VARYING_SLOT_POS) {
5510 for(int i = 0; i < 3; ++i)
5511 inputs[i] = ctx->abi.frag_pos[i];
5512
5513 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5514 ctx->abi.frag_pos[3]);
5515 }
5516 }
5517 ctx->shader_info->fs.num_interp = index;
5518 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5519 ctx->shader_info->fs.has_pcoord = true;
5520 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5521 ctx->shader_info->fs.prim_id_input = true;
5522 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5523 ctx->shader_info->fs.layer_input = true;
5524 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5525
5526 if (ctx->shader_info->info.needs_multiview_view_index)
5527 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5528 }
5529
5530 static LLVMValueRef
5531 ac_build_alloca(struct ac_llvm_context *ac,
5532 LLVMTypeRef type,
5533 const char *name)
5534 {
5535 LLVMBuilderRef builder = ac->builder;
5536 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5537 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5538 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5539 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5540 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5541 LLVMValueRef res;
5542
5543 if (first_instr) {
5544 LLVMPositionBuilderBefore(first_builder, first_instr);
5545 } else {
5546 LLVMPositionBuilderAtEnd(first_builder, first_block);
5547 }
5548
5549 res = LLVMBuildAlloca(first_builder, type, name);
5550 LLVMBuildStore(builder, LLVMConstNull(type), res);
5551
5552 LLVMDisposeBuilder(first_builder);
5553
5554 return res;
5555 }
5556
5557 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5558 LLVMTypeRef type,
5559 const char *name)
5560 {
5561 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5562 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5563 return ptr;
5564 }
5565
5566 static void
5567 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5568 struct nir_variable *variable,
5569 struct nir_shader *shader,
5570 gl_shader_stage stage)
5571 {
5572 int idx = variable->data.location + variable->data.index;
5573 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5574 uint64_t mask_attribs;
5575
5576 variable->data.driver_location = idx * 4;
5577
5578 /* tess ctrl has it's own load/store paths for outputs */
5579 if (stage == MESA_SHADER_TESS_CTRL)
5580 return;
5581
5582 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5583 if (stage == MESA_SHADER_VERTEX ||
5584 stage == MESA_SHADER_TESS_EVAL ||
5585 stage == MESA_SHADER_GEOMETRY) {
5586 if (idx == VARYING_SLOT_CLIP_DIST0) {
5587 int length = shader->info.clip_distance_array_size +
5588 shader->info.cull_distance_array_size;
5589 if (stage == MESA_SHADER_VERTEX) {
5590 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5591 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5592 }
5593 if (stage == MESA_SHADER_TESS_EVAL) {
5594 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5595 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5596 }
5597
5598 if (length > 4)
5599 attrib_count = 2;
5600 else
5601 attrib_count = 1;
5602 mask_attribs = 1ull << idx;
5603 }
5604 }
5605
5606 ctx->output_mask |= mask_attribs;
5607 }
5608
5609 static void
5610 handle_shader_output_decl(struct ac_nir_context *ctx,
5611 struct nir_shader *nir,
5612 struct nir_variable *variable)
5613 {
5614 unsigned output_loc = variable->data.driver_location / 4;
5615 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5616
5617 /* tess ctrl has it's own load/store paths for outputs */
5618 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5619 return;
5620
5621 if (ctx->stage == MESA_SHADER_VERTEX ||
5622 ctx->stage == MESA_SHADER_TESS_EVAL ||
5623 ctx->stage == MESA_SHADER_GEOMETRY) {
5624 int idx = variable->data.location + variable->data.index;
5625 if (idx == VARYING_SLOT_CLIP_DIST0) {
5626 int length = nir->info.clip_distance_array_size +
5627 nir->info.cull_distance_array_size;
5628
5629 if (length > 4)
5630 attrib_count = 2;
5631 else
5632 attrib_count = 1;
5633 }
5634 }
5635
5636 for (unsigned i = 0; i < attrib_count; ++i) {
5637 for (unsigned chan = 0; chan < 4; chan++) {
5638 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5639 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5640 }
5641 }
5642 }
5643
5644 static LLVMTypeRef
5645 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5646 enum glsl_base_type type)
5647 {
5648 switch (type) {
5649 case GLSL_TYPE_INT:
5650 case GLSL_TYPE_UINT:
5651 case GLSL_TYPE_BOOL:
5652 case GLSL_TYPE_SUBROUTINE:
5653 return ctx->ac.i32;
5654 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5655 return ctx->ac.f32;
5656 case GLSL_TYPE_INT64:
5657 case GLSL_TYPE_UINT64:
5658 return ctx->ac.i64;
5659 case GLSL_TYPE_DOUBLE:
5660 return ctx->ac.f64;
5661 default:
5662 unreachable("unknown GLSL type");
5663 }
5664 }
5665
5666 static LLVMTypeRef
5667 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5668 const struct glsl_type *type)
5669 {
5670 if (glsl_type_is_scalar(type)) {
5671 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5672 }
5673
5674 if (glsl_type_is_vector(type)) {
5675 return LLVMVectorType(
5676 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5677 glsl_get_vector_elements(type));
5678 }
5679
5680 if (glsl_type_is_matrix(type)) {
5681 return LLVMArrayType(
5682 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5683 glsl_get_matrix_columns(type));
5684 }
5685
5686 if (glsl_type_is_array(type)) {
5687 return LLVMArrayType(
5688 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5689 glsl_get_length(type));
5690 }
5691
5692 assert(glsl_type_is_struct(type));
5693
5694 LLVMTypeRef member_types[glsl_get_length(type)];
5695
5696 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5697 member_types[i] =
5698 glsl_to_llvm_type(ctx,
5699 glsl_get_struct_field(type, i));
5700 }
5701
5702 return LLVMStructTypeInContext(ctx->context, member_types,
5703 glsl_get_length(type), false);
5704 }
5705
5706 static void
5707 setup_locals(struct ac_nir_context *ctx,
5708 struct nir_function *func)
5709 {
5710 int i, j;
5711 ctx->num_locals = 0;
5712 nir_foreach_variable(variable, &func->impl->locals) {
5713 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5714 variable->data.driver_location = ctx->num_locals * 4;
5715 variable->data.location_frac = 0;
5716 ctx->num_locals += attrib_count;
5717 }
5718 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5719 if (!ctx->locals)
5720 return;
5721
5722 for (i = 0; i < ctx->num_locals; i++) {
5723 for (j = 0; j < 4; j++) {
5724 ctx->locals[i * 4 + j] =
5725 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5726 }
5727 }
5728 }
5729
5730 static void
5731 setup_shared(struct ac_nir_context *ctx,
5732 struct nir_shader *nir)
5733 {
5734 nir_foreach_variable(variable, &nir->shared) {
5735 LLVMValueRef shared =
5736 LLVMAddGlobalInAddressSpace(
5737 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5738 variable->name ? variable->name : "",
5739 AC_LOCAL_ADDR_SPACE);
5740 _mesa_hash_table_insert(ctx->vars, variable, shared);
5741 }
5742 }
5743
5744 /* Initialize arguments for the shader export intrinsic */
5745 static void
5746 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5747 LLVMValueRef *values,
5748 unsigned target,
5749 struct ac_export_args *args)
5750 {
5751 /* Default is 0xf. Adjusted below depending on the format. */
5752 args->enabled_channels = 0xf;
5753
5754 /* Specify whether the EXEC mask represents the valid mask */
5755 args->valid_mask = 0;
5756
5757 /* Specify whether this is the last export */
5758 args->done = 0;
5759
5760 /* Specify the target we are exporting */
5761 args->target = target;
5762
5763 args->compr = false;
5764 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5765 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5766 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5767 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5768
5769 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5770 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5771 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5772 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5773 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5774 unsigned chan;
5775
5776 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5777 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5778 unsigned bits, bool hi) = NULL;
5779
5780 switch(col_format) {
5781 case V_028714_SPI_SHADER_ZERO:
5782 args->enabled_channels = 0; /* writemask */
5783 args->target = V_008DFC_SQ_EXP_NULL;
5784 break;
5785
5786 case V_028714_SPI_SHADER_32_R:
5787 args->enabled_channels = 1;
5788 args->out[0] = values[0];
5789 break;
5790
5791 case V_028714_SPI_SHADER_32_GR:
5792 args->enabled_channels = 0x3;
5793 args->out[0] = values[0];
5794 args->out[1] = values[1];
5795 break;
5796
5797 case V_028714_SPI_SHADER_32_AR:
5798 args->enabled_channels = 0x9;
5799 args->out[0] = values[0];
5800 args->out[3] = values[3];
5801 break;
5802
5803 case V_028714_SPI_SHADER_FP16_ABGR:
5804 packf = ac_build_cvt_pkrtz_f16;
5805 break;
5806
5807 case V_028714_SPI_SHADER_UNORM16_ABGR:
5808 packf = ac_build_cvt_pknorm_u16;
5809 break;
5810
5811 case V_028714_SPI_SHADER_SNORM16_ABGR:
5812 packf = ac_build_cvt_pknorm_i16;
5813 break;
5814
5815 case V_028714_SPI_SHADER_UINT16_ABGR:
5816 packi = ac_build_cvt_pk_u16;
5817 break;
5818
5819 case V_028714_SPI_SHADER_SINT16_ABGR:
5820 packi = ac_build_cvt_pk_i16;
5821 break;
5822
5823 default:
5824 case V_028714_SPI_SHADER_32_ABGR:
5825 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5826 break;
5827 }
5828
5829 /* Pack f16 or norm_i16/u16. */
5830 if (packf) {
5831 for (chan = 0; chan < 2; chan++) {
5832 LLVMValueRef pack_args[2] = {
5833 values[2 * chan],
5834 values[2 * chan + 1]
5835 };
5836 LLVMValueRef packed;
5837
5838 packed = packf(&ctx->ac, pack_args);
5839 args->out[chan] = ac_to_float(&ctx->ac, packed);
5840 }
5841 args->compr = 1; /* COMPR flag */
5842 }
5843
5844 /* Pack i16/u16. */
5845 if (packi) {
5846 for (chan = 0; chan < 2; chan++) {
5847 LLVMValueRef pack_args[2] = {
5848 ac_to_integer(&ctx->ac, values[2 * chan]),
5849 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5850 };
5851 LLVMValueRef packed;
5852
5853 packed = packi(&ctx->ac, pack_args,
5854 is_int8 ? 8 : is_int10 ? 10 : 16,
5855 chan == 1);
5856 args->out[chan] = ac_to_float(&ctx->ac, packed);
5857 }
5858 args->compr = 1; /* COMPR flag */
5859 }
5860 return;
5861 }
5862
5863 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5864
5865 for (unsigned i = 0; i < 4; ++i)
5866 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5867 }
5868
5869 static void
5870 radv_export_param(struct nir_to_llvm_context *ctx, unsigned index,
5871 LLVMValueRef *values)
5872 {
5873 struct ac_export_args args;
5874
5875 si_llvm_init_export_args(ctx, values,
5876 V_008DFC_SQ_EXP_PARAM + index, &args);
5877 ac_build_export(&ctx->ac, &args);
5878 }
5879
5880 static LLVMValueRef
5881 radv_load_output(struct nir_to_llvm_context *ctx, unsigned index, unsigned chan)
5882 {
5883 LLVMValueRef output =
5884 ctx->nir->outputs[radeon_llvm_reg_index_soa(index, chan)];
5885
5886 return LLVMBuildLoad(ctx->builder, output, "");
5887 }
5888
5889 static void
5890 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5891 bool export_prim_id,
5892 struct ac_vs_output_info *outinfo)
5893 {
5894 uint32_t param_count = 0;
5895 unsigned target;
5896 unsigned pos_idx, num_pos_exports = 0;
5897 struct ac_export_args args, pos_args[4] = {};
5898 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5899 int i;
5900
5901 if (ctx->options->key.has_multiview_view_index) {
5902 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5903 if(!*tmp_out) {
5904 for(unsigned i = 0; i < 4; ++i)
5905 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5906 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5907 }
5908
5909 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
5910 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5911 }
5912
5913 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5914 sizeof(outinfo->vs_output_param_offset));
5915
5916 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5917 LLVMValueRef slots[8];
5918 unsigned j;
5919
5920 if (outinfo->cull_dist_mask)
5921 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5922
5923 i = VARYING_SLOT_CLIP_DIST0;
5924 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5925 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
5926
5927 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5928 slots[i] = LLVMGetUndef(ctx->ac.f32);
5929
5930 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5931 target = V_008DFC_SQ_EXP_POS + 3;
5932 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5933 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5934 &args, sizeof(args));
5935 }
5936
5937 target = V_008DFC_SQ_EXP_POS + 2;
5938 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5939 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5940 &args, sizeof(args));
5941
5942 }
5943
5944 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5945 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5946 for (unsigned j = 0; j < 4; j++)
5947 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
5948 }
5949 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5950
5951 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5952 outinfo->writes_pointsize = true;
5953 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
5954 }
5955
5956 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5957 outinfo->writes_layer = true;
5958 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
5959 }
5960
5961 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5962 outinfo->writes_viewport_index = true;
5963 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
5964 }
5965
5966 if (outinfo->writes_pointsize ||
5967 outinfo->writes_layer ||
5968 outinfo->writes_viewport_index) {
5969 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5970 (outinfo->writes_layer == true ? 4 : 0));
5971 pos_args[1].valid_mask = 0;
5972 pos_args[1].done = 0;
5973 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5974 pos_args[1].compr = 0;
5975 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5976 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5977 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5978 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5979
5980 if (outinfo->writes_pointsize == true)
5981 pos_args[1].out[0] = psize_value;
5982 if (outinfo->writes_layer == true)
5983 pos_args[1].out[2] = layer_value;
5984 if (outinfo->writes_viewport_index == true) {
5985 if (ctx->options->chip_class >= GFX9) {
5986 /* GFX9 has the layer in out.z[10:0] and the viewport
5987 * index in out.z[19:16].
5988 */
5989 LLVMValueRef v = viewport_index_value;
5990 v = ac_to_integer(&ctx->ac, v);
5991 v = LLVMBuildShl(ctx->builder, v,
5992 LLVMConstInt(ctx->ac.i32, 16, false),
5993 "");
5994 v = LLVMBuildOr(ctx->builder, v,
5995 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5996
5997 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5998 pos_args[1].enabled_channels |= 1 << 2;
5999 } else {
6000 pos_args[1].out[3] = viewport_index_value;
6001 pos_args[1].enabled_channels |= 1 << 3;
6002 }
6003 }
6004 }
6005 for (i = 0; i < 4; i++) {
6006 if (pos_args[i].out[0])
6007 num_pos_exports++;
6008 }
6009
6010 pos_idx = 0;
6011 for (i = 0; i < 4; i++) {
6012 if (!pos_args[i].out[0])
6013 continue;
6014
6015 /* Specify the target we are exporting */
6016 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6017 if (pos_idx == num_pos_exports)
6018 pos_args[i].done = 1;
6019 ac_build_export(&ctx->ac, &pos_args[i]);
6020 }
6021
6022 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6023 LLVMValueRef values[4];
6024 if (!(ctx->output_mask & (1ull << i)))
6025 continue;
6026
6027 if (i != VARYING_SLOT_LAYER &&
6028 i != VARYING_SLOT_PRIMITIVE_ID &&
6029 i < VARYING_SLOT_VAR0)
6030 continue;
6031
6032 for (unsigned j = 0; j < 4; j++)
6033 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6034
6035 radv_export_param(ctx, param_count, values);
6036
6037 outinfo->vs_output_param_offset[i] = param_count++;
6038 }
6039
6040 if (export_prim_id) {
6041 LLVMValueRef values[4];
6042
6043 values[0] = ctx->vs_prim_id;
6044 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6045 ctx->shader_info->vs.vgpr_comp_cnt);
6046 for (unsigned j = 1; j < 4; j++)
6047 values[j] = ctx->ac.f32_0;
6048
6049 radv_export_param(ctx, param_count, values);
6050
6051 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6052 outinfo->export_prim_id = true;
6053 }
6054
6055 outinfo->pos_exports = num_pos_exports;
6056 outinfo->param_exports = param_count;
6057 }
6058
6059 static void
6060 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
6061 struct ac_es_output_info *outinfo)
6062 {
6063 int j;
6064 uint64_t max_output_written = 0;
6065 LLVMValueRef lds_base = NULL;
6066
6067 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6068 int param_index;
6069 int length = 4;
6070
6071 if (!(ctx->output_mask & (1ull << i)))
6072 continue;
6073
6074 if (i == VARYING_SLOT_CLIP_DIST0)
6075 length = ctx->num_output_clips + ctx->num_output_culls;
6076
6077 param_index = shader_io_get_unique_index(i);
6078
6079 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6080 }
6081
6082 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6083
6084 if (ctx->ac.chip_class >= GFX9) {
6085 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6086 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6087 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6088 LLVMConstInt(ctx->ac.i32, 24, false),
6089 LLVMConstInt(ctx->ac.i32, 4, false), false);
6090 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6091 LLVMBuildMul(ctx->ac.builder, wave_idx,
6092 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6093 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6094 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6095 }
6096
6097 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6098 LLVMValueRef dw_addr;
6099 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6100 int param_index;
6101 int length = 4;
6102
6103 if (!(ctx->output_mask & (1ull << i)))
6104 continue;
6105
6106 if (i == VARYING_SLOT_CLIP_DIST0)
6107 length = ctx->num_output_clips + ctx->num_output_culls;
6108
6109 param_index = shader_io_get_unique_index(i);
6110
6111 if (lds_base) {
6112 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6113 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6114 "");
6115 }
6116 for (j = 0; j < length; j++) {
6117 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6118 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6119
6120 if (ctx->ac.chip_class >= GFX9) {
6121 ac_lds_store(&ctx->ac, dw_addr,
6122 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6123 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6124 } else {
6125 ac_build_buffer_store_dword(&ctx->ac,
6126 ctx->esgs_ring,
6127 out_val, 1,
6128 NULL, ctx->es2gs_offset,
6129 (4 * param_index + j) * 4,
6130 1, 1, true, true);
6131 }
6132 }
6133 }
6134 }
6135
6136 static void
6137 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6138 {
6139 LLVMValueRef vertex_id = ctx->rel_auto_id;
6140 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6141 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6142 vertex_dw_stride, "");
6143
6144 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6145 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6146 int length = 4;
6147
6148 if (!(ctx->output_mask & (1ull << i)))
6149 continue;
6150
6151 if (i == VARYING_SLOT_CLIP_DIST0)
6152 length = ctx->num_output_clips + ctx->num_output_culls;
6153 int param = shader_io_get_unique_index(i);
6154 mark_tess_output(ctx, false, param);
6155 if (length > 4)
6156 mark_tess_output(ctx, false, param + 1);
6157 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6158 LLVMConstInt(ctx->ac.i32, param * 4, false),
6159 "");
6160 for (unsigned j = 0; j < length; j++) {
6161 ac_lds_store(&ctx->ac, dw_addr,
6162 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6163 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6164 }
6165 }
6166 }
6167
6168 struct ac_build_if_state
6169 {
6170 struct nir_to_llvm_context *ctx;
6171 LLVMValueRef condition;
6172 LLVMBasicBlockRef entry_block;
6173 LLVMBasicBlockRef true_block;
6174 LLVMBasicBlockRef false_block;
6175 LLVMBasicBlockRef merge_block;
6176 };
6177
6178 static LLVMBasicBlockRef
6179 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6180 {
6181 LLVMBasicBlockRef current_block;
6182 LLVMBasicBlockRef next_block;
6183 LLVMBasicBlockRef new_block;
6184
6185 /* get current basic block */
6186 current_block = LLVMGetInsertBlock(ctx->builder);
6187
6188 /* chqeck if there's another block after this one */
6189 next_block = LLVMGetNextBasicBlock(current_block);
6190 if (next_block) {
6191 /* insert the new block before the next block */
6192 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6193 }
6194 else {
6195 /* append new block after current block */
6196 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6197 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6198 }
6199 return new_block;
6200 }
6201
6202 static void
6203 ac_nir_build_if(struct ac_build_if_state *ifthen,
6204 struct nir_to_llvm_context *ctx,
6205 LLVMValueRef condition)
6206 {
6207 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6208
6209 memset(ifthen, 0, sizeof *ifthen);
6210 ifthen->ctx = ctx;
6211 ifthen->condition = condition;
6212 ifthen->entry_block = block;
6213
6214 /* create endif/merge basic block for the phi functions */
6215 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6216
6217 /* create/insert true_block before merge_block */
6218 ifthen->true_block =
6219 LLVMInsertBasicBlockInContext(ctx->context,
6220 ifthen->merge_block,
6221 "if-true-block");
6222
6223 /* successive code goes into the true block */
6224 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6225 }
6226
6227 /**
6228 * End a conditional.
6229 */
6230 static void
6231 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6232 {
6233 LLVMBuilderRef builder = ifthen->ctx->builder;
6234
6235 /* Insert branch to the merge block from current block */
6236 LLVMBuildBr(builder, ifthen->merge_block);
6237
6238 /*
6239 * Now patch in the various branch instructions.
6240 */
6241
6242 /* Insert the conditional branch instruction at the end of entry_block */
6243 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6244 if (ifthen->false_block) {
6245 /* we have an else clause */
6246 LLVMBuildCondBr(builder, ifthen->condition,
6247 ifthen->true_block, ifthen->false_block);
6248 }
6249 else {
6250 /* no else clause */
6251 LLVMBuildCondBr(builder, ifthen->condition,
6252 ifthen->true_block, ifthen->merge_block);
6253 }
6254
6255 /* Resume building code at end of the ifthen->merge_block */
6256 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6257 }
6258
6259 static void
6260 write_tess_factors(struct nir_to_llvm_context *ctx)
6261 {
6262 unsigned stride, outer_comps, inner_comps;
6263 struct ac_build_if_state if_ctx, inner_if_ctx;
6264 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6265 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6266 unsigned tess_inner_index, tess_outer_index;
6267 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6268 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6269 int i;
6270 emit_barrier(&ctx->ac, ctx->stage);
6271
6272 switch (ctx->options->key.tcs.primitive_mode) {
6273 case GL_ISOLINES:
6274 stride = 2;
6275 outer_comps = 2;
6276 inner_comps = 0;
6277 break;
6278 case GL_TRIANGLES:
6279 stride = 4;
6280 outer_comps = 3;
6281 inner_comps = 1;
6282 break;
6283 case GL_QUADS:
6284 stride = 6;
6285 outer_comps = 4;
6286 inner_comps = 2;
6287 break;
6288 default:
6289 return;
6290 }
6291
6292 ac_nir_build_if(&if_ctx, ctx,
6293 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6294 invocation_id, ctx->ac.i32_0, ""));
6295
6296 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6297 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6298
6299 mark_tess_output(ctx, true, tess_inner_index);
6300 mark_tess_output(ctx, true, tess_outer_index);
6301 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6302 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6303 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6304 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6305 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6306
6307 for (i = 0; i < 4; i++) {
6308 inner[i] = LLVMGetUndef(ctx->ac.i32);
6309 outer[i] = LLVMGetUndef(ctx->ac.i32);
6310 }
6311
6312 // LINES reverseal
6313 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6314 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6315 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6316 ctx->ac.i32_1, "");
6317 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6318 } else {
6319 for (i = 0; i < outer_comps; i++) {
6320 outer[i] = out[i] =
6321 ac_lds_load(&ctx->ac, lds_outer);
6322 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6323 ctx->ac.i32_1, "");
6324 }
6325 for (i = 0; i < inner_comps; i++) {
6326 inner[i] = out[outer_comps+i] =
6327 ac_lds_load(&ctx->ac, lds_inner);
6328 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6329 ctx->ac.i32_1, "");
6330 }
6331 }
6332
6333 /* Convert the outputs to vectors for stores. */
6334 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6335 vec1 = NULL;
6336
6337 if (stride > 4)
6338 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6339
6340
6341 buffer = ctx->hs_ring_tess_factor;
6342 tf_base = ctx->tess_factor_offset;
6343 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6344 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6345 unsigned tf_offset = 0;
6346
6347 if (ctx->options->chip_class <= VI) {
6348 ac_nir_build_if(&inner_if_ctx, ctx,
6349 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6350 rel_patch_id, ctx->ac.i32_0, ""));
6351
6352 /* Store the dynamic HS control word. */
6353 ac_build_buffer_store_dword(&ctx->ac, buffer,
6354 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6355 1, ctx->ac.i32_0, tf_base,
6356 0, 1, 0, true, false);
6357 tf_offset += 4;
6358
6359 ac_nir_build_endif(&inner_if_ctx);
6360 }
6361
6362 /* Store the tessellation factors. */
6363 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6364 MIN2(stride, 4), byteoffset, tf_base,
6365 tf_offset, 1, 0, true, false);
6366 if (vec1)
6367 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6368 stride - 4, byteoffset, tf_base,
6369 16 + tf_offset, 1, 0, true, false);
6370
6371 //store to offchip for TES to read - only if TES reads them
6372 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6373 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6374 LLVMValueRef tf_inner_offset;
6375 unsigned param_outer, param_inner;
6376
6377 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6378 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6379 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6380
6381 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6382 util_next_power_of_two(outer_comps));
6383
6384 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6385 outer_comps, tf_outer_offset,
6386 ctx->oc_lds, 0, 1, 0, true, false);
6387 if (inner_comps) {
6388 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6389 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6390 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6391
6392 inner_vec = inner_comps == 1 ? inner[0] :
6393 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6394 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6395 inner_comps, tf_inner_offset,
6396 ctx->oc_lds, 0, 1, 0, true, false);
6397 }
6398 }
6399 ac_nir_build_endif(&if_ctx);
6400 }
6401
6402 static void
6403 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6404 {
6405 write_tess_factors(ctx);
6406 }
6407
6408 static bool
6409 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6410 LLVMValueRef *color, unsigned index, bool is_last,
6411 struct ac_export_args *args)
6412 {
6413 /* Export */
6414 si_llvm_init_export_args(ctx, color,
6415 V_008DFC_SQ_EXP_MRT + index, args);
6416
6417 if (is_last) {
6418 args->valid_mask = 1; /* whether the EXEC mask is valid */
6419 args->done = 1; /* DONE bit */
6420 } else if (!args->enabled_channels)
6421 return false; /* unnecessary NULL export */
6422
6423 return true;
6424 }
6425
6426 static void
6427 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6428 LLVMValueRef depth, LLVMValueRef stencil,
6429 LLVMValueRef samplemask)
6430 {
6431 struct ac_export_args args;
6432
6433 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6434
6435 ac_build_export(&ctx->ac, &args);
6436 }
6437
6438 static void
6439 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6440 {
6441 unsigned index = 0;
6442 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6443 struct ac_export_args color_args[8];
6444
6445 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6446 LLVMValueRef values[4];
6447 bool last = false;
6448
6449 if (!(ctx->output_mask & (1ull << i)))
6450 continue;
6451
6452 if (i < FRAG_RESULT_DATA0)
6453 continue;
6454
6455 for (unsigned j = 0; j < 4; j++)
6456 values[j] = ac_to_float(&ctx->ac,
6457 radv_load_output(ctx, i, j));
6458
6459 if (!ctx->shader_info->info.ps.writes_z &&
6460 !ctx->shader_info->info.ps.writes_stencil &&
6461 !ctx->shader_info->info.ps.writes_sample_mask)
6462 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6463
6464 bool ret = si_export_mrt_color(ctx, values,
6465 i - FRAG_RESULT_DATA0,
6466 last, &color_args[index]);
6467 if (ret)
6468 index++;
6469 }
6470
6471 /* Process depth, stencil, samplemask. */
6472 if (ctx->shader_info->info.ps.writes_z) {
6473 depth = ac_to_float(&ctx->ac,
6474 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6475 }
6476 if (ctx->shader_info->info.ps.writes_stencil) {
6477 stencil = ac_to_float(&ctx->ac,
6478 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6479 }
6480 if (ctx->shader_info->info.ps.writes_sample_mask) {
6481 samplemask = ac_to_float(&ctx->ac,
6482 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6483 }
6484
6485 /* Export PS outputs. */
6486 for (unsigned i = 0; i < index; i++)
6487 ac_build_export(&ctx->ac, &color_args[i]);
6488
6489 if (depth || stencil || samplemask)
6490 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6491 else if (!index)
6492 ac_build_export_null(&ctx->ac);
6493 }
6494
6495 static void
6496 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6497 {
6498 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6499 }
6500
6501 static void
6502 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6503 LLVMValueRef *addrs)
6504 {
6505 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6506
6507 switch (ctx->stage) {
6508 case MESA_SHADER_VERTEX:
6509 if (ctx->options->key.vs.as_ls)
6510 handle_ls_outputs_post(ctx);
6511 else if (ctx->options->key.vs.as_es)
6512 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6513 else
6514 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6515 &ctx->shader_info->vs.outinfo);
6516 break;
6517 case MESA_SHADER_FRAGMENT:
6518 handle_fs_outputs_post(ctx);
6519 break;
6520 case MESA_SHADER_GEOMETRY:
6521 emit_gs_epilogue(ctx);
6522 break;
6523 case MESA_SHADER_TESS_CTRL:
6524 handle_tcs_outputs_post(ctx);
6525 break;
6526 case MESA_SHADER_TESS_EVAL:
6527 if (ctx->options->key.tes.as_es)
6528 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6529 else
6530 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6531 &ctx->shader_info->tes.outinfo);
6532 break;
6533 default:
6534 break;
6535 }
6536 }
6537
6538 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6539 {
6540 LLVMPassManagerRef passmgr;
6541 /* Create the pass manager */
6542 passmgr = LLVMCreateFunctionPassManagerForModule(
6543 ctx->module);
6544
6545 /* This pass should eliminate all the load and store instructions */
6546 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6547
6548 /* Add some optimization passes */
6549 LLVMAddScalarReplAggregatesPass(passmgr);
6550 LLVMAddLICMPass(passmgr);
6551 LLVMAddAggressiveDCEPass(passmgr);
6552 LLVMAddCFGSimplificationPass(passmgr);
6553 LLVMAddInstructionCombiningPass(passmgr);
6554
6555 /* Run the pass */
6556 LLVMInitializeFunctionPassManager(passmgr);
6557 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6558 LLVMFinalizeFunctionPassManager(passmgr);
6559
6560 LLVMDisposeBuilder(ctx->builder);
6561 LLVMDisposePassManager(passmgr);
6562 }
6563
6564 static void
6565 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6566 {
6567 struct ac_vs_output_info *outinfo;
6568
6569 switch (ctx->stage) {
6570 case MESA_SHADER_FRAGMENT:
6571 case MESA_SHADER_COMPUTE:
6572 case MESA_SHADER_TESS_CTRL:
6573 case MESA_SHADER_GEOMETRY:
6574 return;
6575 case MESA_SHADER_VERTEX:
6576 if (ctx->options->key.vs.as_ls ||
6577 ctx->options->key.vs.as_es)
6578 return;
6579 outinfo = &ctx->shader_info->vs.outinfo;
6580 break;
6581 case MESA_SHADER_TESS_EVAL:
6582 if (ctx->options->key.vs.as_es)
6583 return;
6584 outinfo = &ctx->shader_info->tes.outinfo;
6585 break;
6586 default:
6587 unreachable("Unhandled shader type");
6588 }
6589
6590 ac_optimize_vs_outputs(&ctx->ac,
6591 ctx->main_function,
6592 outinfo->vs_output_param_offset,
6593 VARYING_SLOT_MAX,
6594 &outinfo->param_exports);
6595 }
6596
6597 static void
6598 ac_setup_rings(struct nir_to_llvm_context *ctx)
6599 {
6600 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6601 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6602 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6603 }
6604
6605 if (ctx->is_gs_copy_shader) {
6606 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6607 }
6608 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6609 LLVMValueRef tmp;
6610 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6611 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6612
6613 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6614
6615 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6616 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6617 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6618 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6619 }
6620
6621 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6622 ctx->stage == MESA_SHADER_TESS_EVAL) {
6623 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6624 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6625 }
6626 }
6627
6628 static unsigned
6629 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6630 const struct nir_shader *nir)
6631 {
6632 switch (nir->info.stage) {
6633 case MESA_SHADER_TESS_CTRL:
6634 return chip_class >= CIK ? 128 : 64;
6635 case MESA_SHADER_GEOMETRY:
6636 return chip_class >= GFX9 ? 128 : 64;
6637 case MESA_SHADER_COMPUTE:
6638 break;
6639 default:
6640 return 0;
6641 }
6642
6643 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6644 nir->info.cs.local_size[1] *
6645 nir->info.cs.local_size[2];
6646 return max_workgroup_size;
6647 }
6648
6649 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6650 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6651 {
6652 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6653 LLVMConstInt(ctx->ac.i32, 8, false),
6654 LLVMConstInt(ctx->ac.i32, 8, false), false);
6655 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6656 ctx->ac.i32_0, "");
6657 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6658 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6659 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6660 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6661 }
6662
6663 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6664 {
6665 for(int i = 5; i >= 0; --i) {
6666 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6667 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6668 LLVMConstInt(ctx->ac.i32, 16, false), false);
6669 }
6670
6671 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6672 LLVMConstInt(ctx->ac.i32, 16, false),
6673 LLVMConstInt(ctx->ac.i32, 8, false), false);
6674 }
6675
6676 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6677 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6678 {
6679 struct ac_nir_context ctx = {};
6680 struct nir_function *func;
6681
6682 ctx.ac = *ac;
6683 ctx.abi = abi;
6684
6685 ctx.nctx = nctx;
6686 if (nctx)
6687 nctx->nir = &ctx;
6688
6689 ctx.stage = nir->info.stage;
6690
6691 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6692
6693 nir_foreach_variable(variable, &nir->outputs)
6694 handle_shader_output_decl(&ctx, nir, variable);
6695
6696 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6697 _mesa_key_pointer_equal);
6698 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6699 _mesa_key_pointer_equal);
6700 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6701 _mesa_key_pointer_equal);
6702
6703 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6704
6705 setup_locals(&ctx, func);
6706
6707 if (nir->info.stage == MESA_SHADER_COMPUTE)
6708 setup_shared(&ctx, nir);
6709
6710 visit_cf_list(&ctx, &func->impl->body);
6711 phi_post_pass(&ctx);
6712
6713 if (nir->info.stage != MESA_SHADER_COMPUTE)
6714 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6715 ctx.outputs);
6716
6717 free(ctx.locals);
6718 ralloc_free(ctx.defs);
6719 ralloc_free(ctx.phis);
6720 ralloc_free(ctx.vars);
6721
6722 if (nctx)
6723 nctx->nir = NULL;
6724 }
6725
6726 static
6727 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6728 struct nir_shader *const *shaders,
6729 int shader_count,
6730 struct ac_shader_variant_info *shader_info,
6731 const struct ac_nir_compiler_options *options)
6732 {
6733 struct nir_to_llvm_context ctx = {0};
6734 unsigned i;
6735 ctx.options = options;
6736 ctx.shader_info = shader_info;
6737 ctx.context = LLVMContextCreate();
6738 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6739
6740 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6741 options->family);
6742 ctx.ac.module = ctx.module;
6743 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6744
6745 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6746 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6747 LLVMSetDataLayout(ctx.module, data_layout_str);
6748 LLVMDisposeTargetData(data_layout);
6749 LLVMDisposeMessage(data_layout_str);
6750
6751 enum ac_float_mode float_mode =
6752 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6753 AC_FLOAT_MODE_DEFAULT;
6754
6755 ctx.builder = ac_create_builder(ctx.context, float_mode);
6756 ctx.ac.builder = ctx.builder;
6757
6758 memset(shader_info, 0, sizeof(*shader_info));
6759
6760 for(int i = 0; i < shader_count; ++i)
6761 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6762
6763 for (i = 0; i < AC_UD_MAX_SETS; i++)
6764 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6765 for (i = 0; i < AC_UD_MAX_UD; i++)
6766 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6767
6768 ctx.max_workgroup_size = 0;
6769 for (int i = 0; i < shader_count; ++i) {
6770 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6771 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6772 shaders[i]));
6773 }
6774
6775 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6776 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6777
6778 ctx.abi.inputs = &ctx.inputs[0];
6779 ctx.abi.emit_outputs = handle_shader_outputs_post;
6780 ctx.abi.emit_vertex = visit_emit_vertex;
6781 ctx.abi.load_ubo = radv_load_ubo;
6782 ctx.abi.load_ssbo = radv_load_ssbo;
6783 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6784 ctx.abi.load_resource = radv_load_resource;
6785 ctx.abi.clamp_shadow_reference = false;
6786
6787 if (shader_count >= 2)
6788 ac_init_exec_full_mask(&ctx.ac);
6789
6790 if (ctx.ac.chip_class == GFX9 &&
6791 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6792 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6793
6794 for(int i = 0; i < shader_count; ++i) {
6795 ctx.stage = shaders[i]->info.stage;
6796 ctx.output_mask = 0;
6797 ctx.tess_outputs_written = 0;
6798 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6799 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6800
6801 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6802 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6803 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6804 ctx.abi.load_inputs = load_gs_input;
6805 ctx.abi.emit_primitive = visit_end_primitive;
6806 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6807 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6808 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6809 ctx.abi.load_tess_varyings = load_tcs_varyings;
6810 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6811 ctx.abi.store_tcs_outputs = store_tcs_output;
6812 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6813 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6814 ctx.abi.load_tess_varyings = load_tes_input;
6815 ctx.abi.load_tess_coord = load_tess_coord;
6816 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6817 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6818 if (shader_info->info.vs.needs_instance_id) {
6819 if (ctx.options->key.vs.as_ls) {
6820 ctx.shader_info->vs.vgpr_comp_cnt =
6821 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6822 } else {
6823 ctx.shader_info->vs.vgpr_comp_cnt =
6824 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6825 }
6826 }
6827 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6828 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6829 ctx.abi.lookup_interp_param = lookup_interp_param;
6830 ctx.abi.load_sample_position = load_sample_position;
6831 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6832 }
6833
6834 if (i)
6835 emit_barrier(&ctx.ac, ctx.stage);
6836
6837 ac_setup_rings(&ctx);
6838
6839 LLVMBasicBlockRef merge_block;
6840 if (shader_count >= 2) {
6841 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6842 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6843 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6844
6845 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6846 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6847 LLVMConstInt(ctx.ac.i32, 8, false), false);
6848 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6849 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6850 thread_id, count, "");
6851 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6852
6853 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6854 }
6855
6856 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6857 handle_fs_inputs(&ctx, shaders[i]);
6858 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6859 handle_vs_inputs(&ctx, shaders[i]);
6860 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6861 prepare_gs_input_vgprs(&ctx);
6862
6863 nir_foreach_variable(variable, &shaders[i]->outputs)
6864 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6865
6866 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6867
6868 if (shader_count >= 2) {
6869 LLVMBuildBr(ctx.ac.builder, merge_block);
6870 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6871 }
6872
6873 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6874 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6875 shaders[i]->info.cull_distance_array_size > 4;
6876 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6877 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6878 shaders[i]->info.gs.vertices_out;
6879 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6880 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6881 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6882 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6883 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6884 }
6885 }
6886
6887 LLVMBuildRetVoid(ctx.builder);
6888
6889 if (options->dump_preoptir)
6890 ac_dump_module(ctx.module);
6891
6892 ac_llvm_finalize_module(&ctx);
6893
6894 if (shader_count == 1)
6895 ac_nir_eliminate_const_vs_outputs(&ctx);
6896
6897 return ctx.module;
6898 }
6899
6900 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6901 {
6902 unsigned *retval = (unsigned *)context;
6903 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6904 char *description = LLVMGetDiagInfoDescription(di);
6905
6906 if (severity == LLVMDSError) {
6907 *retval = 1;
6908 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6909 description);
6910 }
6911
6912 LLVMDisposeMessage(description);
6913 }
6914
6915 static unsigned ac_llvm_compile(LLVMModuleRef M,
6916 struct ac_shader_binary *binary,
6917 LLVMTargetMachineRef tm)
6918 {
6919 unsigned retval = 0;
6920 char *err;
6921 LLVMContextRef llvm_ctx;
6922 LLVMMemoryBufferRef out_buffer;
6923 unsigned buffer_size;
6924 const char *buffer_data;
6925 LLVMBool mem_err;
6926
6927 /* Setup Diagnostic Handler*/
6928 llvm_ctx = LLVMGetModuleContext(M);
6929
6930 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6931 &retval);
6932
6933 /* Compile IR*/
6934 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6935 &err, &out_buffer);
6936
6937 /* Process Errors/Warnings */
6938 if (mem_err) {
6939 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6940 free(err);
6941 retval = 1;
6942 goto out;
6943 }
6944
6945 /* Extract Shader Code*/
6946 buffer_size = LLVMGetBufferSize(out_buffer);
6947 buffer_data = LLVMGetBufferStart(out_buffer);
6948
6949 ac_elf_read(buffer_data, buffer_size, binary);
6950
6951 /* Clean up */
6952 LLVMDisposeMemoryBuffer(out_buffer);
6953
6954 out:
6955 return retval;
6956 }
6957
6958 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6959 LLVMModuleRef llvm_module,
6960 struct ac_shader_binary *binary,
6961 struct ac_shader_config *config,
6962 struct ac_shader_variant_info *shader_info,
6963 gl_shader_stage stage,
6964 bool dump_shader, bool supports_spill)
6965 {
6966 if (dump_shader)
6967 ac_dump_module(llvm_module);
6968
6969 memset(binary, 0, sizeof(*binary));
6970 int v = ac_llvm_compile(llvm_module, binary, tm);
6971 if (v) {
6972 fprintf(stderr, "compile failed\n");
6973 }
6974
6975 if (dump_shader)
6976 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6977
6978 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6979
6980 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6981 LLVMDisposeModule(llvm_module);
6982 LLVMContextDispose(ctx);
6983
6984 if (stage == MESA_SHADER_FRAGMENT) {
6985 shader_info->num_input_vgprs = 0;
6986 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6987 shader_info->num_input_vgprs += 2;
6988 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6989 shader_info->num_input_vgprs += 2;
6990 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6991 shader_info->num_input_vgprs += 2;
6992 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6993 shader_info->num_input_vgprs += 3;
6994 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6995 shader_info->num_input_vgprs += 2;
6996 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6997 shader_info->num_input_vgprs += 2;
6998 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6999 shader_info->num_input_vgprs += 2;
7000 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7001 shader_info->num_input_vgprs += 1;
7002 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7003 shader_info->num_input_vgprs += 1;
7004 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7005 shader_info->num_input_vgprs += 1;
7006 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7007 shader_info->num_input_vgprs += 1;
7008 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7009 shader_info->num_input_vgprs += 1;
7010 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7011 shader_info->num_input_vgprs += 1;
7012 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7013 shader_info->num_input_vgprs += 1;
7014 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7015 shader_info->num_input_vgprs += 1;
7016 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7017 shader_info->num_input_vgprs += 1;
7018 }
7019 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7020
7021 /* +3 for scratch wave offset and VCC */
7022 config->num_sgprs = MAX2(config->num_sgprs,
7023 shader_info->num_input_sgprs + 3);
7024
7025 /* Enable 64-bit and 16-bit denormals, because there is no performance
7026 * cost.
7027 *
7028 * If denormals are enabled, all floating-point output modifiers are
7029 * ignored.
7030 *
7031 * Don't enable denormals for 32-bit floats, because:
7032 * - Floating-point output modifiers would be ignored by the hw.
7033 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7034 * have to stop using those.
7035 * - SI & CI would be very slow.
7036 */
7037 config->float_mode |= V_00B028_FP_64_DENORMS;
7038 }
7039
7040 static void
7041 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7042 {
7043 switch (nir->info.stage) {
7044 case MESA_SHADER_COMPUTE:
7045 for (int i = 0; i < 3; ++i)
7046 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7047 break;
7048 case MESA_SHADER_FRAGMENT:
7049 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7050 break;
7051 case MESA_SHADER_GEOMETRY:
7052 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7053 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7054 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7055 shader_info->gs.invocations = nir->info.gs.invocations;
7056 break;
7057 case MESA_SHADER_TESS_EVAL:
7058 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7059 shader_info->tes.spacing = nir->info.tess.spacing;
7060 shader_info->tes.ccw = nir->info.tess.ccw;
7061 shader_info->tes.point_mode = nir->info.tess.point_mode;
7062 shader_info->tes.as_es = options->key.tes.as_es;
7063 break;
7064 case MESA_SHADER_TESS_CTRL:
7065 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7066 break;
7067 case MESA_SHADER_VERTEX:
7068 shader_info->vs.as_es = options->key.vs.as_es;
7069 shader_info->vs.as_ls = options->key.vs.as_ls;
7070 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7071 if (options->key.vs.as_ls)
7072 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7073 break;
7074 default:
7075 break;
7076 }
7077 }
7078
7079 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7080 struct ac_shader_binary *binary,
7081 struct ac_shader_config *config,
7082 struct ac_shader_variant_info *shader_info,
7083 struct nir_shader *const *nir,
7084 int nir_count,
7085 const struct ac_nir_compiler_options *options,
7086 bool dump_shader)
7087 {
7088
7089 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7090 options);
7091
7092 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7093 for (int i = 0; i < nir_count; ++i)
7094 ac_fill_shader_info(shader_info, nir[i], options);
7095
7096 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7097 if (options->chip_class == GFX9) {
7098 if (nir_count == 2 &&
7099 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7100 shader_info->gs.es_type = nir[0]->info.stage;
7101 }
7102 }
7103 }
7104
7105 static void
7106 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
7107 {
7108 LLVMValueRef vtx_offset =
7109 LLVMBuildMul(ctx->builder, ctx->abi.vertex_id,
7110 LLVMConstInt(ctx->ac.i32, 4, false), "");
7111 int idx = 0;
7112
7113 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7114 int length = 4;
7115 int slot = idx;
7116 int slot_inc = 1;
7117 if (!(ctx->output_mask & (1ull << i)))
7118 continue;
7119
7120 if (i == VARYING_SLOT_CLIP_DIST0) {
7121 /* unpack clip and cull from a single set of slots */
7122 length = ctx->num_output_clips + ctx->num_output_culls;
7123 if (length > 4)
7124 slot_inc = 2;
7125 }
7126
7127 for (unsigned j = 0; j < length; j++) {
7128 LLVMValueRef value, soffset;
7129
7130 soffset = LLVMConstInt(ctx->ac.i32,
7131 (slot * 4 + j) *
7132 ctx->gs_max_out_vertices * 16 * 4, false);
7133
7134 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7135 1, ctx->ac.i32_0,
7136 vtx_offset, soffset,
7137 0, 1, 1, true, false);
7138
7139 LLVMBuildStore(ctx->builder,
7140 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7141 }
7142 idx += slot_inc;
7143 }
7144 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7145 }
7146
7147 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7148 struct nir_shader *geom_shader,
7149 struct ac_shader_binary *binary,
7150 struct ac_shader_config *config,
7151 struct ac_shader_variant_info *shader_info,
7152 const struct ac_nir_compiler_options *options,
7153 bool dump_shader)
7154 {
7155 struct nir_to_llvm_context ctx = {0};
7156 ctx.context = LLVMContextCreate();
7157 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7158 ctx.options = options;
7159 ctx.shader_info = shader_info;
7160
7161 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7162 options->family);
7163 ctx.ac.module = ctx.module;
7164
7165 ctx.is_gs_copy_shader = true;
7166 LLVMSetTarget(ctx.module, "amdgcn--");
7167
7168 enum ac_float_mode float_mode =
7169 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7170 AC_FLOAT_MODE_DEFAULT;
7171
7172 ctx.builder = ac_create_builder(ctx.context, float_mode);
7173 ctx.ac.builder = ctx.builder;
7174 ctx.stage = MESA_SHADER_VERTEX;
7175
7176 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7177
7178 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7179 ac_setup_rings(&ctx);
7180
7181 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7182 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7183
7184 struct ac_nir_context nir_ctx = {};
7185 nir_ctx.ac = ctx.ac;
7186 nir_ctx.abi = &ctx.abi;
7187
7188 nir_ctx.nctx = &ctx;
7189 ctx.nir = &nir_ctx;
7190
7191 nir_foreach_variable(variable, &geom_shader->outputs) {
7192 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7193 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7194 }
7195
7196 ac_gs_copy_shader_emit(&ctx);
7197
7198 ctx.nir = NULL;
7199
7200 LLVMBuildRetVoid(ctx.builder);
7201
7202 ac_llvm_finalize_module(&ctx);
7203
7204 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7205 MESA_SHADER_VERTEX,
7206 dump_shader, options->supports_spill);
7207 }