2 * Copyright © 2016 Bas Nieuwenhuizen
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
38 enum radeon_llvm_calling_convention
{
39 RADEON_LLVM_AMDGPU_VS
= 87,
40 RADEON_LLVM_AMDGPU_GS
= 88,
41 RADEON_LLVM_AMDGPU_PS
= 89,
42 RADEON_LLVM_AMDGPU_CS
= 90,
43 RADEON_LLVM_AMDGPU_HS
= 93,
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
49 struct nir_to_llvm_context
;
51 struct ac_nir_context
{
52 struct ac_llvm_context ac
;
53 struct ac_shader_abi
*abi
;
55 gl_shader_stage stage
;
57 struct hash_table
*defs
;
58 struct hash_table
*phis
;
59 struct hash_table
*vars
;
61 LLVMValueRef main_function
;
62 LLVMBasicBlockRef continue_block
;
63 LLVMBasicBlockRef break_block
;
65 LLVMValueRef outputs
[RADEON_LLVM_MAX_OUTPUTS
* 4];
70 struct nir_to_llvm_context
*nctx
; /* TODO get rid of this */
73 struct nir_to_llvm_context
{
74 struct ac_llvm_context ac
;
75 const struct ac_nir_compiler_options
*options
;
76 struct ac_shader_variant_info
*shader_info
;
77 struct ac_shader_abi abi
;
78 struct ac_nir_context
*nir
;
80 unsigned max_workgroup_size
;
81 LLVMContextRef context
;
83 LLVMBuilderRef builder
;
84 LLVMValueRef main_function
;
86 struct hash_table
*defs
;
87 struct hash_table
*phis
;
89 LLVMValueRef descriptor_sets
[AC_UD_MAX_SETS
];
90 LLVMValueRef ring_offsets
;
91 LLVMValueRef push_constants
;
92 LLVMValueRef view_index
;
93 LLVMValueRef num_work_groups
;
94 LLVMValueRef workgroup_ids
[3];
95 LLVMValueRef local_invocation_ids
;
98 LLVMValueRef vertex_buffers
;
99 LLVMValueRef rel_auto_id
;
100 LLVMValueRef vs_prim_id
;
101 LLVMValueRef ls_out_layout
;
102 LLVMValueRef es2gs_offset
;
104 LLVMValueRef tcs_offchip_layout
;
105 LLVMValueRef tcs_out_offsets
;
106 LLVMValueRef tcs_out_layout
;
107 LLVMValueRef tcs_in_layout
;
109 LLVMValueRef merged_wave_info
;
110 LLVMValueRef tess_factor_offset
;
111 LLVMValueRef tes_rel_patch_id
;
115 LLVMValueRef gsvs_ring_stride
;
116 LLVMValueRef gsvs_num_entries
;
117 LLVMValueRef gs2vs_offset
;
118 LLVMValueRef gs_wave_id
;
119 LLVMValueRef gs_vtx_offset
[6];
121 LLVMValueRef esgs_ring
;
122 LLVMValueRef gsvs_ring
;
123 LLVMValueRef hs_ring_tess_offchip
;
124 LLVMValueRef hs_ring_tess_factor
;
126 LLVMValueRef prim_mask
;
127 LLVMValueRef sample_pos_offset
;
128 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
129 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
131 gl_shader_stage stage
;
133 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
136 uint64_t output_mask
;
137 uint8_t num_output_clips
;
138 uint8_t num_output_culls
;
140 bool is_gs_copy_shader
;
141 LLVMValueRef gs_next_vertex
;
142 unsigned gs_max_out_vertices
;
144 unsigned tes_primitive_mode
;
145 uint64_t tess_outputs_written
;
146 uint64_t tess_patch_outputs_written
;
148 uint32_t tcs_patch_outputs_read
;
149 uint64_t tcs_outputs_read
;
152 static inline struct nir_to_llvm_context
*
153 nir_to_llvm_context_from_abi(struct ac_shader_abi
*abi
)
155 struct nir_to_llvm_context
*ctx
= NULL
;
156 return container_of(abi
, ctx
, abi
);
160 nir2llvmtype(struct ac_nir_context
*ctx
,
161 const struct glsl_type
*type
)
163 switch (glsl_get_base_type(glsl_without_array(type
))) {
167 case GLSL_TYPE_UINT64
:
168 case GLSL_TYPE_INT64
:
170 case GLSL_TYPE_DOUBLE
:
172 case GLSL_TYPE_FLOAT
:
175 assert(!"Unsupported type in nir2llvmtype()");
181 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
182 const nir_deref_var
*deref
,
183 enum ac_descriptor_type desc_type
,
184 const nir_tex_instr
*instr
,
185 bool image
, bool write
);
187 static unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
)
189 return (index
* 4) + chan
;
192 static unsigned shader_io_get_unique_index(gl_varying_slot slot
)
194 /* handle patch indices separate */
195 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
197 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
199 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
200 return 2 + (slot
- VARYING_SLOT_PATCH0
);
202 if (slot
== VARYING_SLOT_POS
)
204 if (slot
== VARYING_SLOT_PSIZ
)
206 if (slot
== VARYING_SLOT_CLIP_DIST0
)
208 /* 3 is reserved for clip dist as well */
209 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
210 return 4 + (slot
- VARYING_SLOT_VAR0
);
211 unreachable("illegal slot in get unique index\n");
214 static void set_llvm_calling_convention(LLVMValueRef func
,
215 gl_shader_stage stage
)
217 enum radeon_llvm_calling_convention calling_conv
;
220 case MESA_SHADER_VERTEX
:
221 case MESA_SHADER_TESS_EVAL
:
222 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
224 case MESA_SHADER_GEOMETRY
:
225 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
227 case MESA_SHADER_TESS_CTRL
:
228 calling_conv
= HAVE_LLVM
>= 0x0500 ? RADEON_LLVM_AMDGPU_HS
: RADEON_LLVM_AMDGPU_VS
;
230 case MESA_SHADER_FRAGMENT
:
231 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
233 case MESA_SHADER_COMPUTE
:
234 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
237 unreachable("Unhandle shader type");
240 LLVMSetFunctionCallConv(func
, calling_conv
);
245 LLVMTypeRef types
[MAX_ARGS
];
246 LLVMValueRef
*assign
[MAX_ARGS
];
247 unsigned array_params_mask
;
250 uint8_t num_sgprs_used
;
251 uint8_t num_vgprs_used
;
254 enum ac_arg_regfile
{
260 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
261 LLVMValueRef
*param_ptr
)
263 assert(info
->count
< MAX_ARGS
);
265 info
->assign
[info
->count
] = param_ptr
;
266 info
->types
[info
->count
] = type
;
269 if (regfile
== ARG_SGPR
) {
270 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
273 assert(regfile
== ARG_VGPR
);
274 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
279 add_array_arg(struct arg_info
*info
, LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
281 info
->array_params_mask
|= (1 << info
->count
);
282 add_arg(info
, ARG_SGPR
, type
, param_ptr
);
285 static void assign_arguments(LLVMValueRef main_function
,
286 struct arg_info
*info
)
289 for (i
= 0; i
< info
->count
; i
++) {
291 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
296 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
297 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
298 unsigned num_return_elems
,
299 struct arg_info
*args
,
300 unsigned max_workgroup_size
,
303 LLVMTypeRef main_function_type
, ret_type
;
304 LLVMBasicBlockRef main_function_body
;
306 if (num_return_elems
)
307 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
308 num_return_elems
, true);
310 ret_type
= LLVMVoidTypeInContext(ctx
);
312 /* Setup the function */
314 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
315 LLVMValueRef main_function
=
316 LLVMAddFunction(module
, "main", main_function_type
);
318 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
319 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
321 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
322 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
323 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
325 if (args
->array_params_mask
& (1 << i
)) {
326 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
327 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
328 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
332 if (max_workgroup_size
) {
333 ac_llvm_add_target_dep_function_attr(main_function
,
334 "amdgpu-max-work-group-size",
338 /* These were copied from some LLVM test. */
339 LLVMAddTargetDependentFunctionAttr(main_function
,
340 "less-precise-fpmad",
342 LLVMAddTargetDependentFunctionAttr(main_function
,
345 LLVMAddTargetDependentFunctionAttr(main_function
,
348 LLVMAddTargetDependentFunctionAttr(main_function
,
351 LLVMAddTargetDependentFunctionAttr(main_function
,
352 "no-signed-zeros-fp-math",
355 return main_function
;
358 static int get_elem_bits(struct ac_llvm_context
*ctx
, LLVMTypeRef type
)
360 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
361 type
= LLVMGetElementType(type
);
363 if (LLVMGetTypeKind(type
) == LLVMIntegerTypeKind
)
364 return LLVMGetIntTypeWidth(type
);
366 if (type
== ctx
->f16
)
368 if (type
== ctx
->f32
)
370 if (type
== ctx
->f64
)
373 unreachable("Unhandled type kind in get_elem_bits");
376 static LLVMValueRef
unpack_param(struct ac_llvm_context
*ctx
,
377 LLVMValueRef param
, unsigned rshift
,
380 LLVMValueRef value
= param
;
382 value
= LLVMBuildLShr(ctx
->builder
, value
,
383 LLVMConstInt(ctx
->i32
, rshift
, false), "");
385 if (rshift
+ bitwidth
< 32) {
386 unsigned mask
= (1 << bitwidth
) - 1;
387 value
= LLVMBuildAnd(ctx
->builder
, value
,
388 LLVMConstInt(ctx
->i32
, mask
, false), "");
393 static LLVMValueRef
get_rel_patch_id(struct nir_to_llvm_context
*ctx
)
395 switch (ctx
->stage
) {
396 case MESA_SHADER_TESS_CTRL
:
397 return unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
398 case MESA_SHADER_TESS_EVAL
:
399 return ctx
->tes_rel_patch_id
;
402 unreachable("Illegal stage");
406 /* Tessellation shaders pass outputs to the next shader using LDS.
408 * LS outputs = TCS inputs
409 * TCS outputs = TES inputs
412 * - TCS inputs for patch 0
413 * - TCS inputs for patch 1
414 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
416 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
417 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
418 * - TCS outputs for patch 1
419 * - Per-patch TCS outputs for patch 1
420 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
421 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
424 * All three shaders VS(LS), TCS, TES share the same LDS space.
427 get_tcs_in_patch_stride(struct nir_to_llvm_context
*ctx
)
429 if (ctx
->stage
== MESA_SHADER_VERTEX
)
430 return unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 0, 13);
431 else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
432 return unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 0, 13);
440 get_tcs_out_patch_stride(struct nir_to_llvm_context
*ctx
)
442 return unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 0, 13);
446 get_tcs_out_patch0_offset(struct nir_to_llvm_context
*ctx
)
448 return LLVMBuildMul(ctx
->builder
,
449 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 0, 16),
450 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
454 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context
*ctx
)
456 return LLVMBuildMul(ctx
->builder
,
457 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 16, 16),
458 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
462 get_tcs_in_current_patch_offset(struct nir_to_llvm_context
*ctx
)
464 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
465 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
467 return LLVMBuildMul(ctx
->builder
, patch_stride
, rel_patch_id
, "");
471 get_tcs_out_current_patch_offset(struct nir_to_llvm_context
*ctx
)
473 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
474 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
475 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
477 return LLVMBuildAdd(ctx
->builder
, patch0_offset
,
478 LLVMBuildMul(ctx
->builder
, patch_stride
,
484 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context
*ctx
)
486 LLVMValueRef patch0_patch_data_offset
=
487 get_tcs_out_patch0_patch_data_offset(ctx
);
488 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
489 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
491 return LLVMBuildAdd(ctx
->builder
, patch0_patch_data_offset
,
492 LLVMBuildMul(ctx
->builder
, patch_stride
,
498 set_loc(struct ac_userdata_info
*ud_info
, uint8_t *sgpr_idx
, uint8_t num_sgprs
,
499 uint32_t indirect_offset
)
501 ud_info
->sgpr_idx
= *sgpr_idx
;
502 ud_info
->num_sgprs
= num_sgprs
;
503 ud_info
->indirect
= indirect_offset
> 0;
504 ud_info
->indirect_offset
= indirect_offset
;
505 *sgpr_idx
+= num_sgprs
;
509 set_loc_shader(struct nir_to_llvm_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
512 struct ac_userdata_info
*ud_info
=
513 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
516 set_loc(ud_info
, sgpr_idx
, num_sgprs
, 0);
520 set_loc_desc(struct nir_to_llvm_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
521 uint32_t indirect_offset
)
523 struct ac_userdata_info
*ud_info
=
524 &ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[idx
];
527 set_loc(ud_info
, sgpr_idx
, 2, indirect_offset
);
530 struct user_sgpr_info
{
531 bool need_ring_offsets
;
533 bool indirect_all_descriptor_sets
;
536 static bool needs_view_index_sgpr(struct nir_to_llvm_context
*ctx
,
537 gl_shader_stage stage
)
540 case MESA_SHADER_VERTEX
:
541 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
542 (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
545 case MESA_SHADER_TESS_EVAL
:
546 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
549 case MESA_SHADER_GEOMETRY
:
550 case MESA_SHADER_TESS_CTRL
:
551 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
560 static void allocate_user_sgprs(struct nir_to_llvm_context
*ctx
,
561 gl_shader_stage stage
,
562 bool needs_view_index
,
563 struct user_sgpr_info
*user_sgpr_info
)
565 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
567 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
568 if (stage
== MESA_SHADER_GEOMETRY
||
569 stage
== MESA_SHADER_VERTEX
||
570 stage
== MESA_SHADER_TESS_CTRL
||
571 stage
== MESA_SHADER_TESS_EVAL
||
572 ctx
->is_gs_copy_shader
)
573 user_sgpr_info
->need_ring_offsets
= true;
575 if (stage
== MESA_SHADER_FRAGMENT
&&
576 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
577 user_sgpr_info
->need_ring_offsets
= true;
579 /* 2 user sgprs will nearly always be allocated for scratch/rings */
580 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
581 user_sgpr_info
->sgpr_count
+= 2;
584 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
586 case MESA_SHADER_COMPUTE
:
587 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
588 user_sgpr_info
->sgpr_count
+= 3;
590 case MESA_SHADER_FRAGMENT
:
591 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
593 case MESA_SHADER_VERTEX
:
594 if (!ctx
->is_gs_copy_shader
) {
595 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.vs
.has_vertex_buffers
? 2 : 0;
596 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
597 user_sgpr_info
->sgpr_count
+= 3;
599 user_sgpr_info
->sgpr_count
+= 2;
602 if (ctx
->options
->key
.vs
.as_ls
)
603 user_sgpr_info
->sgpr_count
++;
605 case MESA_SHADER_TESS_CTRL
:
606 user_sgpr_info
->sgpr_count
+= 4;
608 case MESA_SHADER_TESS_EVAL
:
609 user_sgpr_info
->sgpr_count
+= 1;
611 case MESA_SHADER_GEOMETRY
:
612 user_sgpr_info
->sgpr_count
+= 2;
618 if (needs_view_index
)
619 user_sgpr_info
->sgpr_count
++;
621 if (ctx
->shader_info
->info
.loads_push_constants
)
622 user_sgpr_info
->sgpr_count
+= 2;
624 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
? 32 : 16;
625 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_info
->sgpr_count
;
627 if (remaining_sgprs
/ 2 < util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
)) {
628 user_sgpr_info
->sgpr_count
+= 2;
629 user_sgpr_info
->indirect_all_descriptor_sets
= true;
631 user_sgpr_info
->sgpr_count
+= util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
) * 2;
636 declare_global_input_sgprs(struct nir_to_llvm_context
*ctx
,
637 gl_shader_stage stage
,
638 bool has_previous_stage
,
639 gl_shader_stage previous_stage
,
640 const struct user_sgpr_info
*user_sgpr_info
,
641 struct arg_info
*args
,
642 LLVMValueRef
*desc_sets
)
644 LLVMTypeRef type
= ac_array_in_const_addr_space(ctx
->ac
.i8
);
645 unsigned num_sets
= ctx
->options
->layout
?
646 ctx
->options
->layout
->num_sets
: 0;
647 unsigned stage_mask
= 1 << stage
;
649 if (has_previous_stage
)
650 stage_mask
|= 1 << previous_stage
;
652 /* 1 for each descriptor set */
653 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
654 for (unsigned i
= 0; i
< num_sets
; ++i
) {
655 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
656 add_array_arg(args
, type
,
657 &ctx
->descriptor_sets
[i
]);
661 add_array_arg(args
, ac_array_in_const_addr_space(type
), desc_sets
);
664 if (ctx
->shader_info
->info
.loads_push_constants
) {
665 /* 1 for push constants and dynamic descriptors */
666 add_array_arg(args
, type
, &ctx
->push_constants
);
671 declare_vs_specific_input_sgprs(struct nir_to_llvm_context
*ctx
,
672 gl_shader_stage stage
,
673 bool has_previous_stage
,
674 gl_shader_stage previous_stage
,
675 struct arg_info
*args
)
677 if (!ctx
->is_gs_copy_shader
&&
678 (stage
== MESA_SHADER_VERTEX
||
679 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
680 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
681 add_arg(args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
682 &ctx
->vertex_buffers
);
684 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
685 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
686 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
687 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
693 declare_vs_input_vgprs(struct nir_to_llvm_context
*ctx
, struct arg_info
*args
)
695 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
696 if (!ctx
->is_gs_copy_shader
) {
697 if (ctx
->options
->key
.vs
.as_ls
) {
698 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
699 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
701 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
702 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
704 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
709 declare_tes_input_vgprs(struct nir_to_llvm_context
*ctx
, struct arg_info
*args
)
711 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
712 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
713 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
714 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
718 set_global_input_locs(struct nir_to_llvm_context
*ctx
, gl_shader_stage stage
,
719 bool has_previous_stage
, gl_shader_stage previous_stage
,
720 const struct user_sgpr_info
*user_sgpr_info
,
721 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
723 unsigned num_sets
= ctx
->options
->layout
?
724 ctx
->options
->layout
->num_sets
: 0;
725 unsigned stage_mask
= 1 << stage
;
727 if (has_previous_stage
)
728 stage_mask
|= 1 << previous_stage
;
730 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
731 for (unsigned i
= 0; i
< num_sets
; ++i
) {
732 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
733 set_loc_desc(ctx
, i
, user_sgpr_idx
, 0);
735 ctx
->descriptor_sets
[i
] = NULL
;
738 set_loc_shader(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
741 for (unsigned i
= 0; i
< num_sets
; ++i
) {
742 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
743 set_loc_desc(ctx
, i
, user_sgpr_idx
, i
* 8);
744 ctx
->descriptor_sets
[i
] =
745 ac_build_load_to_sgpr(&ctx
->ac
,
747 LLVMConstInt(ctx
->ac
.i32
, i
, false));
750 ctx
->descriptor_sets
[i
] = NULL
;
752 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
755 if (ctx
->shader_info
->info
.loads_push_constants
) {
756 set_loc_shader(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
, 2);
761 set_vs_specific_input_locs(struct nir_to_llvm_context
*ctx
,
762 gl_shader_stage stage
, bool has_previous_stage
,
763 gl_shader_stage previous_stage
,
764 uint8_t *user_sgpr_idx
)
766 if (!ctx
->is_gs_copy_shader
&&
767 (stage
== MESA_SHADER_VERTEX
||
768 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
769 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
770 set_loc_shader(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
775 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
778 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
779 user_sgpr_idx
, vs_num
);
783 static void create_function(struct nir_to_llvm_context
*ctx
,
784 gl_shader_stage stage
,
785 bool has_previous_stage
,
786 gl_shader_stage previous_stage
)
788 uint8_t user_sgpr_idx
;
789 struct user_sgpr_info user_sgpr_info
;
790 struct arg_info args
= {};
791 LLVMValueRef desc_sets
;
792 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
793 allocate_user_sgprs(ctx
, stage
, needs_view_index
, &user_sgpr_info
);
795 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
796 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
801 case MESA_SHADER_COMPUTE
:
802 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
803 previous_stage
, &user_sgpr_info
,
806 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
807 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
808 &ctx
->num_work_groups
);
811 for (int i
= 0; i
< 3; i
++) {
812 ctx
->workgroup_ids
[i
] = NULL
;
813 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
814 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
815 &ctx
->workgroup_ids
[i
]);
819 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
820 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->tg_size
);
821 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
822 &ctx
->local_invocation_ids
);
824 case MESA_SHADER_VERTEX
:
825 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
826 previous_stage
, &user_sgpr_info
,
828 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
829 previous_stage
, &args
);
831 if (needs_view_index
)
832 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->view_index
);
833 if (ctx
->options
->key
.vs
.as_es
)
834 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
836 else if (ctx
->options
->key
.vs
.as_ls
)
837 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
838 &ctx
->ls_out_layout
);
840 declare_vs_input_vgprs(ctx
, &args
);
842 case MESA_SHADER_TESS_CTRL
:
843 if (has_previous_stage
) {
844 // First 6 system regs
845 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
846 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
847 &ctx
->merged_wave_info
);
848 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
849 &ctx
->tess_factor_offset
);
851 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
852 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
853 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
855 declare_global_input_sgprs(ctx
, stage
,
858 &user_sgpr_info
, &args
,
860 declare_vs_specific_input_sgprs(ctx
, stage
,
862 previous_stage
, &args
);
864 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
865 &ctx
->ls_out_layout
);
867 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
868 &ctx
->tcs_offchip_layout
);
869 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
870 &ctx
->tcs_out_offsets
);
871 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
872 &ctx
->tcs_out_layout
);
873 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
874 &ctx
->tcs_in_layout
);
875 if (needs_view_index
)
876 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
879 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
880 &ctx
->abi
.tcs_patch_id
);
881 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
882 &ctx
->abi
.tcs_rel_ids
);
884 declare_vs_input_vgprs(ctx
, &args
);
886 declare_global_input_sgprs(ctx
, stage
,
889 &user_sgpr_info
, &args
,
892 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
893 &ctx
->tcs_offchip_layout
);
894 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
895 &ctx
->tcs_out_offsets
);
896 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
897 &ctx
->tcs_out_layout
);
898 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
899 &ctx
->tcs_in_layout
);
900 if (needs_view_index
)
901 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
904 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
905 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
906 &ctx
->tess_factor_offset
);
907 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
908 &ctx
->abi
.tcs_patch_id
);
909 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
910 &ctx
->abi
.tcs_rel_ids
);
913 case MESA_SHADER_TESS_EVAL
:
914 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
915 previous_stage
, &user_sgpr_info
,
918 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->tcs_offchip_layout
);
919 if (needs_view_index
)
920 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->view_index
);
922 if (ctx
->options
->key
.tes
.as_es
) {
923 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
924 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
925 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
928 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
929 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
931 declare_tes_input_vgprs(ctx
, &args
);
933 case MESA_SHADER_GEOMETRY
:
934 if (has_previous_stage
) {
935 // First 6 system regs
936 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
938 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
939 &ctx
->merged_wave_info
);
940 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
942 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
943 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
944 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
946 declare_global_input_sgprs(ctx
, stage
,
949 &user_sgpr_info
, &args
,
952 if (previous_stage
== MESA_SHADER_TESS_EVAL
) {
953 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
954 &ctx
->tcs_offchip_layout
);
956 declare_vs_specific_input_sgprs(ctx
, stage
,
962 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
963 &ctx
->gsvs_ring_stride
);
964 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
965 &ctx
->gsvs_num_entries
);
966 if (needs_view_index
)
967 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
970 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
971 &ctx
->gs_vtx_offset
[0]);
972 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
973 &ctx
->gs_vtx_offset
[2]);
974 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
975 &ctx
->abi
.gs_prim_id
);
976 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
977 &ctx
->abi
.gs_invocation_id
);
978 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
979 &ctx
->gs_vtx_offset
[4]);
981 if (previous_stage
== MESA_SHADER_VERTEX
) {
982 declare_vs_input_vgprs(ctx
, &args
);
984 declare_tes_input_vgprs(ctx
, &args
);
987 declare_global_input_sgprs(ctx
, stage
,
990 &user_sgpr_info
, &args
,
993 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
994 &ctx
->gsvs_ring_stride
);
995 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
996 &ctx
->gsvs_num_entries
);
997 if (needs_view_index
)
998 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1001 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
1002 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
1003 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1004 &ctx
->gs_vtx_offset
[0]);
1005 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1006 &ctx
->gs_vtx_offset
[1]);
1007 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1008 &ctx
->abi
.gs_prim_id
);
1009 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1010 &ctx
->gs_vtx_offset
[2]);
1011 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1012 &ctx
->gs_vtx_offset
[3]);
1013 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1014 &ctx
->gs_vtx_offset
[4]);
1015 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1016 &ctx
->gs_vtx_offset
[5]);
1017 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1018 &ctx
->abi
.gs_invocation_id
);
1021 case MESA_SHADER_FRAGMENT
:
1022 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
1023 previous_stage
, &user_sgpr_info
,
1026 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
)
1027 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1028 &ctx
->sample_pos_offset
);
1030 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->prim_mask
);
1031 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
1032 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
1033 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
1034 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1035 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
1036 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
1037 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
1038 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1039 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1040 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1041 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1042 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1043 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1044 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1045 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1046 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1049 unreachable("Shader stage not implemented");
1052 ctx
->main_function
= create_llvm_function(
1053 ctx
->context
, ctx
->module
, ctx
->builder
, NULL
, 0, &args
,
1054 ctx
->max_workgroup_size
,
1055 ctx
->options
->unsafe_math
);
1056 set_llvm_calling_convention(ctx
->main_function
, stage
);
1059 ctx
->shader_info
->num_input_vgprs
= 0;
1060 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1062 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1064 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1065 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1067 assign_arguments(ctx
->main_function
, &args
);
1071 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1072 set_loc_shader(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1074 if (ctx
->options
->supports_spill
) {
1075 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1076 LLVMPointerType(ctx
->ac
.i8
, AC_CONST_ADDR_SPACE
),
1077 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1078 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->builder
, ctx
->ring_offsets
,
1079 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1083 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1084 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1085 if (has_previous_stage
)
1088 set_global_input_locs(ctx
, stage
, has_previous_stage
, previous_stage
,
1089 &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1092 case MESA_SHADER_COMPUTE
:
1093 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1094 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1098 case MESA_SHADER_VERTEX
:
1099 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1100 previous_stage
, &user_sgpr_idx
);
1101 if (ctx
->view_index
)
1102 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1103 if (ctx
->options
->key
.vs
.as_ls
) {
1104 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1107 if (ctx
->options
->key
.vs
.as_ls
)
1108 ac_declare_lds_as_pointer(&ctx
->ac
);
1110 case MESA_SHADER_TESS_CTRL
:
1111 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1112 previous_stage
, &user_sgpr_idx
);
1113 if (has_previous_stage
)
1114 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1116 set_loc_shader(ctx
, AC_UD_TCS_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 4);
1117 if (ctx
->view_index
)
1118 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1119 ac_declare_lds_as_pointer(&ctx
->ac
);
1121 case MESA_SHADER_TESS_EVAL
:
1122 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 1);
1123 if (ctx
->view_index
)
1124 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1126 case MESA_SHADER_GEOMETRY
:
1127 if (has_previous_stage
) {
1128 if (previous_stage
== MESA_SHADER_VERTEX
)
1129 set_vs_specific_input_locs(ctx
, stage
,
1134 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
,
1137 set_loc_shader(ctx
, AC_UD_GS_VS_RING_STRIDE_ENTRIES
,
1139 if (ctx
->view_index
)
1140 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1141 if (has_previous_stage
)
1142 ac_declare_lds_as_pointer(&ctx
->ac
);
1144 case MESA_SHADER_FRAGMENT
:
1145 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
) {
1146 set_loc_shader(ctx
, AC_UD_PS_SAMPLE_POS_OFFSET
,
1151 unreachable("Shader stage not implemented");
1154 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1157 static LLVMValueRef
trim_vector(struct ac_llvm_context
*ctx
,
1158 LLVMValueRef value
, unsigned count
)
1160 unsigned num_components
= ac_get_llvm_num_components(value
);
1161 if (count
== num_components
)
1164 LLVMValueRef masks
[] = {
1165 LLVMConstInt(ctx
->i32
, 0, false), LLVMConstInt(ctx
->i32
, 1, false),
1166 LLVMConstInt(ctx
->i32
, 2, false), LLVMConstInt(ctx
->i32
, 3, false)};
1169 return LLVMBuildExtractElement(ctx
->builder
, value
, masks
[0],
1172 LLVMValueRef swizzle
= LLVMConstVector(masks
, count
);
1173 return LLVMBuildShuffleVector(ctx
->builder
, value
, value
, swizzle
, "");
1177 build_store_values_extended(struct ac_llvm_context
*ac
,
1178 LLVMValueRef
*values
,
1179 unsigned value_count
,
1180 unsigned value_stride
,
1183 LLVMBuilderRef builder
= ac
->builder
;
1186 for (i
= 0; i
< value_count
; i
++) {
1187 LLVMValueRef ptr
= values
[i
* value_stride
];
1188 LLVMValueRef index
= LLVMConstInt(ac
->i32
, i
, false);
1189 LLVMValueRef value
= LLVMBuildExtractElement(builder
, vec
, index
, "");
1190 LLVMBuildStore(builder
, value
, ptr
);
1194 static LLVMTypeRef
get_def_type(struct ac_nir_context
*ctx
,
1195 const nir_ssa_def
*def
)
1197 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, def
->bit_size
);
1198 if (def
->num_components
> 1) {
1199 type
= LLVMVectorType(type
, def
->num_components
);
1204 static LLVMValueRef
get_src(struct ac_nir_context
*nir
, nir_src src
)
1207 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, src
.ssa
);
1208 return (LLVMValueRef
)entry
->data
;
1212 static LLVMBasicBlockRef
get_block(struct ac_nir_context
*nir
,
1213 const struct nir_block
*b
)
1215 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, b
);
1216 return (LLVMBasicBlockRef
)entry
->data
;
1219 static LLVMValueRef
get_alu_src(struct ac_nir_context
*ctx
,
1221 unsigned num_components
)
1223 LLVMValueRef value
= get_src(ctx
, src
.src
);
1224 bool need_swizzle
= false;
1227 LLVMTypeRef type
= LLVMTypeOf(value
);
1228 unsigned src_components
= LLVMGetTypeKind(type
) == LLVMVectorTypeKind
1229 ? LLVMGetVectorSize(type
)
1232 for (unsigned i
= 0; i
< num_components
; ++i
) {
1233 assert(src
.swizzle
[i
] < src_components
);
1234 if (src
.swizzle
[i
] != i
)
1235 need_swizzle
= true;
1238 if (need_swizzle
|| num_components
!= src_components
) {
1239 LLVMValueRef masks
[] = {
1240 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[0], false),
1241 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[1], false),
1242 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[2], false),
1243 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[3], false)};
1245 if (src_components
> 1 && num_components
== 1) {
1246 value
= LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
1248 } else if (src_components
== 1 && num_components
> 1) {
1249 LLVMValueRef values
[] = {value
, value
, value
, value
};
1250 value
= ac_build_gather_values(&ctx
->ac
, values
, num_components
);
1252 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
1253 value
= LLVMBuildShuffleVector(ctx
->ac
.builder
, value
, value
,
1257 assert(!src
.negate
);
1262 static LLVMValueRef
emit_int_cmp(struct ac_llvm_context
*ctx
,
1263 LLVMIntPredicate pred
, LLVMValueRef src0
,
1266 LLVMValueRef result
= LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, "");
1267 return LLVMBuildSelect(ctx
->builder
, result
,
1268 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1272 static LLVMValueRef
emit_float_cmp(struct ac_llvm_context
*ctx
,
1273 LLVMRealPredicate pred
, LLVMValueRef src0
,
1276 LLVMValueRef result
;
1277 src0
= ac_to_float(ctx
, src0
);
1278 src1
= ac_to_float(ctx
, src1
);
1279 result
= LLVMBuildFCmp(ctx
->builder
, pred
, src0
, src1
, "");
1280 return LLVMBuildSelect(ctx
->builder
, result
,
1281 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1285 static LLVMValueRef
emit_intrin_1f_param(struct ac_llvm_context
*ctx
,
1287 LLVMTypeRef result_type
,
1291 LLVMValueRef params
[] = {
1292 ac_to_float(ctx
, src0
),
1295 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1296 get_elem_bits(ctx
, result_type
));
1297 assert(length
< sizeof(name
));
1298 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 1, AC_FUNC_ATTR_READNONE
);
1301 static LLVMValueRef
emit_intrin_2f_param(struct ac_llvm_context
*ctx
,
1303 LLVMTypeRef result_type
,
1304 LLVMValueRef src0
, LLVMValueRef src1
)
1307 LLVMValueRef params
[] = {
1308 ac_to_float(ctx
, src0
),
1309 ac_to_float(ctx
, src1
),
1312 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1313 get_elem_bits(ctx
, result_type
));
1314 assert(length
< sizeof(name
));
1315 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 2, AC_FUNC_ATTR_READNONE
);
1318 static LLVMValueRef
emit_intrin_3f_param(struct ac_llvm_context
*ctx
,
1320 LLVMTypeRef result_type
,
1321 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1324 LLVMValueRef params
[] = {
1325 ac_to_float(ctx
, src0
),
1326 ac_to_float(ctx
, src1
),
1327 ac_to_float(ctx
, src2
),
1330 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1331 get_elem_bits(ctx
, result_type
));
1332 assert(length
< sizeof(name
));
1333 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 3, AC_FUNC_ATTR_READNONE
);
1336 static LLVMValueRef
emit_bcsel(struct ac_llvm_context
*ctx
,
1337 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1339 LLVMValueRef v
= LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
,
1341 return LLVMBuildSelect(ctx
->builder
, v
, src1
, src2
, "");
1344 static LLVMValueRef
emit_minmax_int(struct ac_llvm_context
*ctx
,
1345 LLVMIntPredicate pred
,
1346 LLVMValueRef src0
, LLVMValueRef src1
)
1348 return LLVMBuildSelect(ctx
->builder
,
1349 LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, ""),
1354 static LLVMValueRef
emit_iabs(struct ac_llvm_context
*ctx
,
1357 return emit_minmax_int(ctx
, LLVMIntSGT
, src0
,
1358 LLVMBuildNeg(ctx
->builder
, src0
, ""));
1361 static LLVMValueRef
emit_fsign(struct ac_llvm_context
*ctx
,
1365 LLVMValueRef cmp
, val
, zero
, one
;
1368 if (bitsize
== 32) {
1378 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGT
, src0
, zero
, "");
1379 val
= LLVMBuildSelect(ctx
->builder
, cmp
, one
, src0
, "");
1380 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
, val
, zero
, "");
1381 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstReal(type
, -1.0), "");
1385 static LLVMValueRef
emit_isign(struct ac_llvm_context
*ctx
,
1386 LLVMValueRef src0
, unsigned bitsize
)
1388 LLVMValueRef cmp
, val
, zero
, one
;
1391 if (bitsize
== 32) {
1401 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGT
, src0
, zero
, "");
1402 val
= LLVMBuildSelect(ctx
->builder
, cmp
, one
, src0
, "");
1403 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGE
, val
, zero
, "");
1404 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstInt(type
, -1, true), "");
1408 static LLVMValueRef
emit_ffract(struct ac_llvm_context
*ctx
,
1411 const char *intr
= "llvm.floor.f32";
1412 LLVMValueRef fsrc0
= ac_to_float(ctx
, src0
);
1413 LLVMValueRef params
[] = {
1416 LLVMValueRef floor
= ac_build_intrinsic(ctx
, intr
,
1417 ctx
->f32
, params
, 1,
1418 AC_FUNC_ATTR_READNONE
);
1419 return LLVMBuildFSub(ctx
->builder
, fsrc0
, floor
, "");
1422 static LLVMValueRef
emit_uint_carry(struct ac_llvm_context
*ctx
,
1424 LLVMValueRef src0
, LLVMValueRef src1
)
1426 LLVMTypeRef ret_type
;
1427 LLVMTypeRef types
[] = { ctx
->i32
, ctx
->i1
};
1429 LLVMValueRef params
[] = { src0
, src1
};
1430 ret_type
= LLVMStructTypeInContext(ctx
->context
, types
,
1433 res
= ac_build_intrinsic(ctx
, intrin
, ret_type
,
1434 params
, 2, AC_FUNC_ATTR_READNONE
);
1436 res
= LLVMBuildExtractValue(ctx
->builder
, res
, 1, "");
1437 res
= LLVMBuildZExt(ctx
->builder
, res
, ctx
->i32
, "");
1441 static LLVMValueRef
emit_b2f(struct ac_llvm_context
*ctx
,
1444 return LLVMBuildAnd(ctx
->builder
, src0
, LLVMBuildBitCast(ctx
->builder
, LLVMConstReal(ctx
->f32
, 1.0), ctx
->i32
, ""), "");
1447 static LLVMValueRef
emit_f2b(struct ac_llvm_context
*ctx
,
1450 src0
= ac_to_float(ctx
, src0
);
1451 return LLVMBuildSExt(ctx
->builder
,
1452 LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
, src0
, ctx
->f32_0
, ""),
1456 static LLVMValueRef
emit_b2i(struct ac_llvm_context
*ctx
,
1460 LLVMValueRef result
= LLVMBuildAnd(ctx
->builder
, src0
, ctx
->i32_1
, "");
1465 return LLVMBuildZExt(ctx
->builder
, result
, ctx
->i64
, "");
1468 static LLVMValueRef
emit_i2b(struct ac_llvm_context
*ctx
,
1471 return LLVMBuildSExt(ctx
->builder
,
1472 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
, ctx
->i32_0
, ""),
1476 static LLVMValueRef
emit_f2f16(struct nir_to_llvm_context
*ctx
,
1479 LLVMValueRef result
;
1480 LLVMValueRef cond
= NULL
;
1482 src0
= ac_to_float(&ctx
->ac
, src0
);
1483 result
= LLVMBuildFPTrunc(ctx
->builder
, src0
, ctx
->ac
.f16
, "");
1485 if (ctx
->options
->chip_class
>= VI
) {
1486 LLVMValueRef args
[2];
1487 /* Check if the result is a denormal - and flush to 0 if so. */
1489 args
[1] = LLVMConstInt(ctx
->ac
.i32
, N_SUBNORMAL
| P_SUBNORMAL
, false);
1490 cond
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.class.f16", ctx
->ac
.i1
, args
, 2, AC_FUNC_ATTR_READNONE
);
1493 /* need to convert back up to f32 */
1494 result
= LLVMBuildFPExt(ctx
->builder
, result
, ctx
->ac
.f32
, "");
1496 if (ctx
->options
->chip_class
>= VI
)
1497 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->ac
.f32_0
, result
, "");
1500 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1501 * so compare the result and flush to 0 if it's smaller.
1503 LLVMValueRef temp
, cond2
;
1504 temp
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1505 ctx
->ac
.f32
, result
);
1506 cond
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUGT
,
1507 LLVMBuildBitCast(ctx
->builder
, LLVMConstInt(ctx
->ac
.i32
, 0x38800000, false), ctx
->ac
.f32
, ""),
1509 cond2
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
,
1510 temp
, ctx
->ac
.f32_0
, "");
1511 cond
= LLVMBuildAnd(ctx
->builder
, cond
, cond2
, "");
1512 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->ac
.f32_0
, result
, "");
1517 static LLVMValueRef
emit_umul_high(struct ac_llvm_context
*ctx
,
1518 LLVMValueRef src0
, LLVMValueRef src1
)
1520 LLVMValueRef dst64
, result
;
1521 src0
= LLVMBuildZExt(ctx
->builder
, src0
, ctx
->i64
, "");
1522 src1
= LLVMBuildZExt(ctx
->builder
, src1
, ctx
->i64
, "");
1524 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1525 dst64
= LLVMBuildLShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1526 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1530 static LLVMValueRef
emit_imul_high(struct ac_llvm_context
*ctx
,
1531 LLVMValueRef src0
, LLVMValueRef src1
)
1533 LLVMValueRef dst64
, result
;
1534 src0
= LLVMBuildSExt(ctx
->builder
, src0
, ctx
->i64
, "");
1535 src1
= LLVMBuildSExt(ctx
->builder
, src1
, ctx
->i64
, "");
1537 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1538 dst64
= LLVMBuildAShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1539 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1543 static LLVMValueRef
emit_bitfield_extract(struct ac_llvm_context
*ctx
,
1545 const LLVMValueRef srcs
[3])
1547 LLVMValueRef result
;
1548 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, srcs
[2], LLVMConstInt(ctx
->i32
, 32, false), "");
1550 result
= ac_build_bfe(ctx
, srcs
[0], srcs
[1], srcs
[2], is_signed
);
1551 result
= LLVMBuildSelect(ctx
->builder
, icond
, srcs
[0], result
, "");
1555 static LLVMValueRef
emit_bitfield_insert(struct ac_llvm_context
*ctx
,
1556 LLVMValueRef src0
, LLVMValueRef src1
,
1557 LLVMValueRef src2
, LLVMValueRef src3
)
1559 LLVMValueRef bfi_args
[3], result
;
1561 bfi_args
[0] = LLVMBuildShl(ctx
->builder
,
1562 LLVMBuildSub(ctx
->builder
,
1563 LLVMBuildShl(ctx
->builder
,
1568 bfi_args
[1] = LLVMBuildShl(ctx
->builder
, src1
, src2
, "");
1571 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, src3
, LLVMConstInt(ctx
->i32
, 32, false), "");
1574 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1575 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1577 result
= LLVMBuildXor(ctx
->builder
, bfi_args
[2],
1578 LLVMBuildAnd(ctx
->builder
, bfi_args
[0],
1579 LLVMBuildXor(ctx
->builder
, bfi_args
[1], bfi_args
[2], ""), ""), "");
1581 result
= LLVMBuildSelect(ctx
->builder
, icond
, src1
, result
, "");
1585 static LLVMValueRef
emit_pack_half_2x16(struct ac_llvm_context
*ctx
,
1588 LLVMValueRef comp
[2];
1590 src0
= ac_to_float(ctx
, src0
);
1591 comp
[0] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_0
, "");
1592 comp
[1] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_1
, "");
1594 return ac_build_cvt_pkrtz_f16(ctx
, comp
);
1597 static LLVMValueRef
emit_unpack_half_2x16(struct ac_llvm_context
*ctx
,
1600 LLVMValueRef const16
= LLVMConstInt(ctx
->i32
, 16, false);
1601 LLVMValueRef temps
[2], result
, val
;
1604 for (i
= 0; i
< 2; i
++) {
1605 val
= i
== 1 ? LLVMBuildLShr(ctx
->builder
, src0
, const16
, "") : src0
;
1606 val
= LLVMBuildTrunc(ctx
->builder
, val
, ctx
->i16
, "");
1607 val
= LLVMBuildBitCast(ctx
->builder
, val
, ctx
->f16
, "");
1608 temps
[i
] = LLVMBuildFPExt(ctx
->builder
, val
, ctx
->f32
, "");
1611 result
= LLVMBuildInsertElement(ctx
->builder
, LLVMGetUndef(ctx
->v2f32
), temps
[0],
1613 result
= LLVMBuildInsertElement(ctx
->builder
, result
, temps
[1],
1618 static LLVMValueRef
emit_ddxy(struct ac_nir_context
*ctx
,
1624 LLVMValueRef result
;
1626 if (op
== nir_op_fddx_fine
|| op
== nir_op_fddx
)
1627 mask
= AC_TID_MASK_LEFT
;
1628 else if (op
== nir_op_fddy_fine
|| op
== nir_op_fddy
)
1629 mask
= AC_TID_MASK_TOP
;
1631 mask
= AC_TID_MASK_TOP_LEFT
;
1633 /* for DDX we want to next X pixel, DDY next Y pixel. */
1634 if (op
== nir_op_fddx_fine
||
1635 op
== nir_op_fddx_coarse
||
1641 result
= ac_build_ddxy(&ctx
->ac
, mask
, idx
, src0
);
1646 * this takes an I,J coordinate pair,
1647 * and works out the X and Y derivatives.
1648 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1650 static LLVMValueRef
emit_ddxy_interp(
1651 struct ac_nir_context
*ctx
,
1652 LLVMValueRef interp_ij
)
1654 LLVMValueRef result
[4], a
;
1657 for (i
= 0; i
< 2; i
++) {
1658 a
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_ij
,
1659 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
1660 result
[i
] = emit_ddxy(ctx
, nir_op_fddx
, a
);
1661 result
[2+i
] = emit_ddxy(ctx
, nir_op_fddy
, a
);
1663 return ac_build_gather_values(&ctx
->ac
, result
, 4);
1666 static void visit_alu(struct ac_nir_context
*ctx
, const nir_alu_instr
*instr
)
1668 LLVMValueRef src
[4], result
= NULL
;
1669 unsigned num_components
= instr
->dest
.dest
.ssa
.num_components
;
1670 unsigned src_components
;
1671 LLVMTypeRef def_type
= get_def_type(ctx
, &instr
->dest
.dest
.ssa
);
1673 assert(nir_op_infos
[instr
->op
].num_inputs
<= ARRAY_SIZE(src
));
1674 switch (instr
->op
) {
1680 case nir_op_pack_half_2x16
:
1683 case nir_op_unpack_half_2x16
:
1687 src_components
= num_components
;
1690 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1691 src
[i
] = get_alu_src(ctx
, instr
->src
[i
], src_components
);
1693 switch (instr
->op
) {
1699 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1700 result
= LLVMBuildFNeg(ctx
->ac
.builder
, src
[0], "");
1703 result
= LLVMBuildNeg(ctx
->ac
.builder
, src
[0], "");
1706 result
= LLVMBuildNot(ctx
->ac
.builder
, src
[0], "");
1709 result
= LLVMBuildAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1712 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1713 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1714 result
= LLVMBuildFAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1717 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1718 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1719 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1722 result
= LLVMBuildSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1725 result
= LLVMBuildMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1728 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1731 result
= LLVMBuildURem(ctx
->ac
.builder
, src
[0], src
[1], "");
1734 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1735 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1736 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1737 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1738 ac_to_float_type(&ctx
->ac
, def_type
), result
);
1739 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[1] , result
, "");
1740 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], result
, "");
1743 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1744 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1745 result
= LLVMBuildFRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1748 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1751 result
= LLVMBuildSDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1754 result
= LLVMBuildUDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1757 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1758 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1759 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1762 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1763 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1764 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1767 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1768 result
= ac_build_fdiv(&ctx
->ac
, instr
->dest
.dest
.ssa
.bit_size
== 32 ? ctx
->ac
.f32_1
: ctx
->ac
.f64_1
,
1772 result
= LLVMBuildAnd(ctx
->ac
.builder
, src
[0], src
[1], "");
1775 result
= LLVMBuildOr(ctx
->ac
.builder
, src
[0], src
[1], "");
1778 result
= LLVMBuildXor(ctx
->ac
.builder
, src
[0], src
[1], "");
1781 result
= LLVMBuildShl(ctx
->ac
.builder
, src
[0],
1782 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1783 LLVMTypeOf(src
[0]), ""),
1787 result
= LLVMBuildAShr(ctx
->ac
.builder
, src
[0],
1788 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1789 LLVMTypeOf(src
[0]), ""),
1793 result
= LLVMBuildLShr(ctx
->ac
.builder
, src
[0],
1794 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1795 LLVMTypeOf(src
[0]), ""),
1799 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1802 result
= emit_int_cmp(&ctx
->ac
, LLVMIntNE
, src
[0], src
[1]);
1805 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, src
[0], src
[1]);
1808 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSGE
, src
[0], src
[1]);
1811 result
= emit_int_cmp(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1814 result
= emit_int_cmp(&ctx
->ac
, LLVMIntUGE
, src
[0], src
[1]);
1817 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUEQ
, src
[0], src
[1]);
1820 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUNE
, src
[0], src
[1]);
1823 result
= emit_float_cmp(&ctx
->ac
, LLVMRealULT
, src
[0], src
[1]);
1826 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUGE
, src
[0], src
[1]);
1829 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1830 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1833 result
= emit_iabs(&ctx
->ac
, src
[0]);
1836 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, src
[0], src
[1]);
1839 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1842 result
= emit_minmax_int(&ctx
->ac
, LLVMIntUGT
, src
[0], src
[1]);
1845 result
= emit_minmax_int(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1848 result
= emit_isign(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
1851 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1852 result
= emit_fsign(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
1855 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1856 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1859 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.trunc",
1860 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1863 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.ceil",
1864 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1866 case nir_op_fround_even
:
1867 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.rint",
1868 ac_to_float_type(&ctx
->ac
, def_type
),src
[0]);
1871 result
= emit_ffract(&ctx
->ac
, src
[0]);
1874 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sin",
1875 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1878 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.cos",
1879 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1882 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1883 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1886 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.exp2",
1887 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1890 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.log2",
1891 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1894 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1895 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1896 result
= ac_build_fdiv(&ctx
->ac
, instr
->dest
.dest
.ssa
.bit_size
== 32 ? ctx
->ac
.f32_1
: ctx
->ac
.f64_1
,
1900 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.pow",
1901 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1904 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.maxnum",
1905 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1906 if (ctx
->ac
.chip_class
< GFX9
&&
1907 instr
->dest
.dest
.ssa
.bit_size
== 32) {
1908 /* Only pre-GFX9 chips do not flush denorms. */
1909 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1910 ac_to_float_type(&ctx
->ac
, def_type
),
1915 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.minnum",
1916 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1917 if (ctx
->ac
.chip_class
< GFX9
&&
1918 instr
->dest
.dest
.ssa
.bit_size
== 32) {
1919 /* Only pre-GFX9 chips do not flush denorms. */
1920 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1921 ac_to_float_type(&ctx
->ac
, def_type
),
1926 result
= emit_intrin_3f_param(&ctx
->ac
, "llvm.fmuladd",
1927 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1], src
[2]);
1929 case nir_op_ibitfield_extract
:
1930 result
= emit_bitfield_extract(&ctx
->ac
, true, src
);
1932 case nir_op_ubitfield_extract
:
1933 result
= emit_bitfield_extract(&ctx
->ac
, false, src
);
1935 case nir_op_bitfield_insert
:
1936 result
= emit_bitfield_insert(&ctx
->ac
, src
[0], src
[1], src
[2], src
[3]);
1938 case nir_op_bitfield_reverse
:
1939 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.bitreverse.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1941 case nir_op_bit_count
:
1942 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1947 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1948 src
[i
] = ac_to_integer(&ctx
->ac
, src
[i
]);
1949 result
= ac_build_gather_values(&ctx
->ac
, src
, num_components
);
1953 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1954 result
= LLVMBuildFPToSI(ctx
->ac
.builder
, src
[0], def_type
, "");
1958 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1959 result
= LLVMBuildFPToUI(ctx
->ac
.builder
, src
[0], def_type
, "");
1963 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1964 result
= LLVMBuildSIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1968 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1969 result
= LLVMBuildUIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1972 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1973 result
= LLVMBuildFPExt(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1976 result
= LLVMBuildFPTrunc(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1980 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1981 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1982 result
= LLVMBuildZExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1984 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1988 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1989 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1990 result
= LLVMBuildSExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1992 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1995 result
= emit_bcsel(&ctx
->ac
, src
[0], src
[1], src
[2]);
1997 case nir_op_find_lsb
:
1998 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1999 result
= ac_find_lsb(&ctx
->ac
, ctx
->ac
.i32
, src
[0]);
2001 case nir_op_ufind_msb
:
2002 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2003 result
= ac_build_umsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
2005 case nir_op_ifind_msb
:
2006 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2007 result
= ac_build_imsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
2009 case nir_op_uadd_carry
:
2010 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2011 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
2012 result
= emit_uint_carry(&ctx
->ac
, "llvm.uadd.with.overflow.i32", src
[0], src
[1]);
2014 case nir_op_usub_borrow
:
2015 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2016 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
2017 result
= emit_uint_carry(&ctx
->ac
, "llvm.usub.with.overflow.i32", src
[0], src
[1]);
2020 result
= emit_b2f(&ctx
->ac
, src
[0]);
2023 result
= emit_f2b(&ctx
->ac
, src
[0]);
2026 result
= emit_b2i(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
2029 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2030 result
= emit_i2b(&ctx
->ac
, src
[0]);
2032 case nir_op_fquantize2f16
:
2033 result
= emit_f2f16(ctx
->nctx
, src
[0]);
2035 case nir_op_umul_high
:
2036 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2037 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
2038 result
= emit_umul_high(&ctx
->ac
, src
[0], src
[1]);
2040 case nir_op_imul_high
:
2041 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2042 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
2043 result
= emit_imul_high(&ctx
->ac
, src
[0], src
[1]);
2045 case nir_op_pack_half_2x16
:
2046 result
= emit_pack_half_2x16(&ctx
->ac
, src
[0]);
2048 case nir_op_unpack_half_2x16
:
2049 result
= emit_unpack_half_2x16(&ctx
->ac
, src
[0]);
2053 case nir_op_fddx_fine
:
2054 case nir_op_fddy_fine
:
2055 case nir_op_fddx_coarse
:
2056 case nir_op_fddy_coarse
:
2057 result
= emit_ddxy(ctx
, instr
->op
, src
[0]);
2060 case nir_op_unpack_64_2x32_split_x
: {
2061 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
2062 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
2065 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2070 case nir_op_unpack_64_2x32_split_y
: {
2071 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
2072 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
2075 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2080 case nir_op_pack_64_2x32_split
: {
2081 LLVMValueRef tmp
= LLVMGetUndef(ctx
->ac
.v2i32
);
2082 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2083 src
[0], ctx
->ac
.i32_0
, "");
2084 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2085 src
[1], ctx
->ac
.i32_1
, "");
2086 result
= LLVMBuildBitCast(ctx
->ac
.builder
, tmp
, ctx
->ac
.i64
, "");
2091 fprintf(stderr
, "Unknown NIR alu instr: ");
2092 nir_print_instr(&instr
->instr
, stderr
);
2093 fprintf(stderr
, "\n");
2098 assert(instr
->dest
.dest
.is_ssa
);
2099 result
= ac_to_integer(&ctx
->ac
, result
);
2100 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.dest
.ssa
,
2105 static void visit_load_const(struct ac_nir_context
*ctx
,
2106 const nir_load_const_instr
*instr
)
2108 LLVMValueRef values
[4], value
= NULL
;
2109 LLVMTypeRef element_type
=
2110 LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
2112 for (unsigned i
= 0; i
< instr
->def
.num_components
; ++i
) {
2113 switch (instr
->def
.bit_size
) {
2115 values
[i
] = LLVMConstInt(element_type
,
2116 instr
->value
.u32
[i
], false);
2119 values
[i
] = LLVMConstInt(element_type
,
2120 instr
->value
.u64
[i
], false);
2124 "unsupported nir load_const bit_size: %d\n",
2125 instr
->def
.bit_size
);
2129 if (instr
->def
.num_components
> 1) {
2130 value
= LLVMConstVector(values
, instr
->def
.num_components
);
2134 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, value
);
2137 static LLVMValueRef
cast_ptr(struct nir_to_llvm_context
*ctx
, LLVMValueRef ptr
,
2140 int addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
2141 return LLVMBuildBitCast(ctx
->builder
, ptr
,
2142 LLVMPointerType(type
, addr_space
), "");
2146 get_buffer_size(struct ac_nir_context
*ctx
, LLVMValueRef descriptor
, bool in_elements
)
2149 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2150 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
2153 if (ctx
->ac
.chip_class
== VI
&& in_elements
) {
2154 /* On VI, the descriptor contains the size in bytes,
2155 * but TXQ must return the size in elements.
2156 * The stride is always non-zero for resources using TXQ.
2158 LLVMValueRef stride
=
2159 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2161 stride
= LLVMBuildLShr(ctx
->ac
.builder
, stride
,
2162 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
2163 stride
= LLVMBuildAnd(ctx
->ac
.builder
, stride
,
2164 LLVMConstInt(ctx
->ac
.i32
, 0x3fff, false), "");
2166 size
= LLVMBuildUDiv(ctx
->ac
.builder
, size
, stride
, "");
2172 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2175 static void build_int_type_name(
2177 char *buf
, unsigned bufsize
)
2179 assert(bufsize
>= 6);
2181 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
2182 snprintf(buf
, bufsize
, "v%ui32",
2183 LLVMGetVectorSize(type
));
2188 static LLVMValueRef
radv_lower_gather4_integer(struct ac_llvm_context
*ctx
,
2189 struct ac_image_args
*args
,
2190 const nir_tex_instr
*instr
)
2192 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2193 LLVMValueRef coord
= args
->addr
;
2194 LLVMValueRef half_texel
[2];
2195 LLVMValueRef compare_cube_wa
= NULL
;
2196 LLVMValueRef result
;
2198 unsigned coord_vgpr_index
= (unsigned)args
->offset
+ (unsigned)args
->compare
;
2202 struct ac_image_args txq_args
= { 0 };
2204 txq_args
.da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
2205 txq_args
.opcode
= ac_image_get_resinfo
;
2206 txq_args
.dmask
= 0xf;
2207 txq_args
.addr
= ctx
->i32_0
;
2208 txq_args
.resource
= args
->resource
;
2209 LLVMValueRef size
= ac_build_image_opcode(ctx
, &txq_args
);
2211 for (c
= 0; c
< 2; c
++) {
2212 half_texel
[c
] = LLVMBuildExtractElement(ctx
->builder
, size
,
2213 LLVMConstInt(ctx
->i32
, c
, false), "");
2214 half_texel
[c
] = LLVMBuildUIToFP(ctx
->builder
, half_texel
[c
], ctx
->f32
, "");
2215 half_texel
[c
] = ac_build_fdiv(ctx
, ctx
->f32_1
, half_texel
[c
]);
2216 half_texel
[c
] = LLVMBuildFMul(ctx
->builder
, half_texel
[c
],
2217 LLVMConstReal(ctx
->f32
, -0.5), "");
2221 LLVMValueRef orig_coords
= args
->addr
;
2223 for (c
= 0; c
< 2; c
++) {
2225 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, coord_vgpr_index
+ c
, 0);
2226 tmp
= LLVMBuildExtractElement(ctx
->builder
, coord
, index
, "");
2227 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2228 tmp
= LLVMBuildFAdd(ctx
->builder
, tmp
, half_texel
[c
], "");
2229 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2230 coord
= LLVMBuildInsertElement(ctx
->builder
, coord
, tmp
, index
, "");
2235 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2236 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2237 * workaround by sampling using a scaled type and converting.
2238 * This is taken from amdgpu-pro shaders.
2240 /* NOTE this produces some ugly code compared to amdgpu-pro,
2241 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2242 * and then reads them back. -pro generates two selects,
2243 * one s_cmp for the descriptor rewriting
2244 * one v_cmp for the coordinate and result changes.
2246 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2247 LLVMValueRef tmp
, tmp2
;
2249 /* workaround 8/8/8/8 uint/sint cube gather bug */
2250 /* first detect it then change to a scaled read and f2i */
2251 tmp
= LLVMBuildExtractElement(ctx
->builder
, args
->resource
, ctx
->i32_1
, "");
2254 /* extract the DATA_FORMAT */
2255 tmp
= ac_build_bfe(ctx
, tmp
, LLVMConstInt(ctx
->i32
, 20, false),
2256 LLVMConstInt(ctx
->i32
, 6, false), false);
2258 /* is the DATA_FORMAT == 8_8_8_8 */
2259 compare_cube_wa
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, tmp
, LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false), "");
2261 if (stype
== GLSL_TYPE_UINT
)
2262 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2263 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0x8000000, false),
2264 LLVMConstInt(ctx
->i32
, 0x10000000, false), "");
2266 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2267 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0xc000000, false),
2268 LLVMConstInt(ctx
->i32
, 0x14000000, false), "");
2270 /* replace the NUM FORMAT in the descriptor */
2271 tmp2
= LLVMBuildAnd(ctx
->builder
, tmp2
, LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false), "");
2272 tmp2
= LLVMBuildOr(ctx
->builder
, tmp2
, tmp
, "");
2274 args
->resource
= LLVMBuildInsertElement(ctx
->builder
, args
->resource
, tmp2
, ctx
->i32_1
, "");
2276 /* don't modify the coordinates for this case */
2277 coord
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, orig_coords
, coord
, "");
2280 result
= ac_build_image_opcode(ctx
, args
);
2282 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2283 LLVMValueRef tmp
, tmp2
;
2285 /* if the cube workaround is in place, f2i the result. */
2286 for (c
= 0; c
< 4; c
++) {
2287 tmp
= LLVMBuildExtractElement(ctx
->builder
, result
, LLVMConstInt(ctx
->i32
, c
, false), "");
2288 if (stype
== GLSL_TYPE_UINT
)
2289 tmp2
= LLVMBuildFPToUI(ctx
->builder
, tmp
, ctx
->i32
, "");
2291 tmp2
= LLVMBuildFPToSI(ctx
->builder
, tmp
, ctx
->i32
, "");
2292 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2293 tmp2
= LLVMBuildBitCast(ctx
->builder
, tmp2
, ctx
->i32
, "");
2294 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, tmp2
, tmp
, "");
2295 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2296 result
= LLVMBuildInsertElement(ctx
->builder
, result
, tmp
, LLVMConstInt(ctx
->i32
, c
, false), "");
2302 static LLVMValueRef
build_tex_intrinsic(struct ac_nir_context
*ctx
,
2303 const nir_tex_instr
*instr
,
2305 struct ac_image_args
*args
)
2307 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
2308 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
2310 return ac_build_buffer_load_format(&ctx
->ac
,
2314 util_last_bit(mask
),
2318 args
->opcode
= ac_image_sample
;
2319 args
->compare
= instr
->is_shadow
;
2321 switch (instr
->op
) {
2323 case nir_texop_txf_ms
:
2324 case nir_texop_samples_identical
:
2325 args
->opcode
= lod_is_zero
||
2326 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
?
2327 ac_image_load
: ac_image_load_mip
;
2328 args
->compare
= false;
2329 args
->offset
= false;
2336 args
->level_zero
= true;
2341 case nir_texop_query_levels
:
2342 args
->opcode
= ac_image_get_resinfo
;
2345 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
2346 args
->level_zero
= true;
2352 args
->opcode
= ac_image_gather4
;
2353 args
->level_zero
= true;
2356 args
->opcode
= ac_image_get_lod
;
2357 args
->compare
= false;
2358 args
->offset
= false;
2364 if (instr
->op
== nir_texop_tg4
&& ctx
->ac
.chip_class
<= VI
) {
2365 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2366 if (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
) {
2367 return radv_lower_gather4_integer(&ctx
->ac
, args
, instr
);
2370 return ac_build_image_opcode(&ctx
->ac
, args
);
2373 static LLVMValueRef
visit_vulkan_resource_index(struct nir_to_llvm_context
*ctx
,
2374 nir_intrinsic_instr
*instr
)
2376 LLVMValueRef index
= get_src(ctx
->nir
, instr
->src
[0]);
2377 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
2378 unsigned binding
= nir_intrinsic_binding(instr
);
2379 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
2380 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
2381 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
2382 unsigned base_offset
= layout
->binding
[binding
].offset
;
2383 LLVMValueRef offset
, stride
;
2385 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
2386 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
2387 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
2388 layout
->binding
[binding
].dynamic_offset_offset
;
2389 desc_ptr
= ctx
->push_constants
;
2390 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
2391 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2393 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
2395 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
2396 index
= LLVMBuildMul(ctx
->builder
, index
, stride
, "");
2397 offset
= LLVMBuildAdd(ctx
->builder
, offset
, index
, "");
2399 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
2400 desc_ptr
= cast_ptr(ctx
, desc_ptr
, ctx
->ac
.v4i32
);
2401 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2406 static LLVMValueRef
visit_vulkan_resource_reindex(struct nir_to_llvm_context
*ctx
,
2407 nir_intrinsic_instr
*instr
)
2409 LLVMValueRef ptr
= get_src(ctx
->nir
, instr
->src
[0]);
2410 LLVMValueRef index
= get_src(ctx
->nir
, instr
->src
[1]);
2412 LLVMValueRef result
= LLVMBuildGEP(ctx
->builder
, ptr
, &index
, 1, "");
2413 LLVMSetMetadata(result
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2417 static LLVMValueRef
visit_load_push_constant(struct nir_to_llvm_context
*ctx
,
2418 nir_intrinsic_instr
*instr
)
2420 LLVMValueRef ptr
, addr
;
2422 addr
= LLVMConstInt(ctx
->ac
.i32
, nir_intrinsic_base(instr
), 0);
2423 addr
= LLVMBuildAdd(ctx
->builder
, addr
, get_src(ctx
->nir
, instr
->src
[0]), "");
2425 ptr
= ac_build_gep0(&ctx
->ac
, ctx
->push_constants
, addr
);
2426 ptr
= cast_ptr(ctx
, ptr
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
));
2428 return LLVMBuildLoad(ctx
->builder
, ptr
, "");
2431 static LLVMValueRef
visit_get_buffer_size(struct ac_nir_context
*ctx
,
2432 const nir_intrinsic_instr
*instr
)
2434 LLVMValueRef index
= get_src(ctx
, instr
->src
[0]);
2436 return get_buffer_size(ctx
, ctx
->abi
->load_ssbo(ctx
->abi
, index
, false), false);
2439 static uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2441 uint32_t new_mask
= 0;
2442 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2443 if (mask
& (1u << i
))
2444 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2448 static LLVMValueRef
extract_vector_range(struct ac_llvm_context
*ctx
, LLVMValueRef src
,
2449 unsigned start
, unsigned count
)
2451 LLVMTypeRef type
= LLVMTypeOf(src
);
2453 if (LLVMGetTypeKind(type
) != LLVMVectorTypeKind
) {
2459 unsigned src_elements
= LLVMGetVectorSize(type
);
2460 assert(start
< src_elements
);
2461 assert(start
+ count
<= src_elements
);
2463 if (start
== 0 && count
== src_elements
)
2467 return LLVMBuildExtractElement(ctx
->builder
, src
, LLVMConstInt(ctx
->i32
, start
, false), "");
2470 LLVMValueRef indices
[8];
2471 for (unsigned i
= 0; i
< count
; ++i
)
2472 indices
[i
] = LLVMConstInt(ctx
->i32
, start
+ i
, false);
2474 LLVMValueRef swizzle
= LLVMConstVector(indices
, count
);
2475 return LLVMBuildShuffleVector(ctx
->builder
, src
, src
, swizzle
, "");
2478 static void visit_store_ssbo(struct ac_nir_context
*ctx
,
2479 nir_intrinsic_instr
*instr
)
2481 const char *store_name
;
2482 LLVMValueRef src_data
= get_src(ctx
, instr
->src
[0]);
2483 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2484 int elem_size_mult
= get_elem_bits(&ctx
->ac
, LLVMTypeOf(src_data
)) / 32;
2485 int components_32bit
= elem_size_mult
* instr
->num_components
;
2486 unsigned writemask
= nir_intrinsic_write_mask(instr
);
2487 LLVMValueRef base_data
, base_offset
;
2488 LLVMValueRef params
[6];
2490 params
[1] = ctx
->abi
->load_ssbo(ctx
->abi
,
2491 get_src(ctx
, instr
->src
[1]), true);
2492 params
[2] = ctx
->ac
.i32_0
; /* vindex */
2493 params
[4] = ctx
->ac
.i1false
; /* glc */
2494 params
[5] = ctx
->ac
.i1false
; /* slc */
2496 if (components_32bit
> 1)
2497 data_type
= LLVMVectorType(ctx
->ac
.f32
, components_32bit
);
2499 writemask
= widen_mask(writemask
, elem_size_mult
);
2501 base_data
= ac_to_float(&ctx
->ac
, src_data
);
2502 base_data
= trim_vector(&ctx
->ac
, base_data
, instr
->num_components
);
2503 base_data
= LLVMBuildBitCast(ctx
->ac
.builder
, base_data
,
2505 base_offset
= get_src(ctx
, instr
->src
[2]); /* voffset */
2509 LLVMValueRef offset
;
2511 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
2513 /* Due to an LLVM limitation, split 3-element writes
2514 * into a 2-element and a 1-element write. */
2516 writemask
|= 1 << (start
+ 2);
2521 writemask
|= ((1u << (count
- 4)) - 1u) << (start
+ 4);
2526 store_name
= "llvm.amdgcn.buffer.store.v4f32";
2527 } else if (count
== 2) {
2528 store_name
= "llvm.amdgcn.buffer.store.v2f32";
2532 store_name
= "llvm.amdgcn.buffer.store.f32";
2534 data
= extract_vector_range(&ctx
->ac
, base_data
, start
, count
);
2536 offset
= base_offset
;
2538 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, LLVMConstInt(ctx
->ac
.i32
, start
* 4, false), "");
2542 ac_build_intrinsic(&ctx
->ac
, store_name
,
2543 ctx
->ac
.voidt
, params
, 6, 0);
2547 static LLVMValueRef
visit_atomic_ssbo(struct ac_nir_context
*ctx
,
2548 const nir_intrinsic_instr
*instr
)
2551 LLVMValueRef params
[6];
2554 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
) {
2555 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[3]), 0);
2557 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[2]), 0);
2558 params
[arg_count
++] = ctx
->abi
->load_ssbo(ctx
->abi
,
2559 get_src(ctx
, instr
->src
[0]),
2561 params
[arg_count
++] = ctx
->ac
.i32_0
; /* vindex */
2562 params
[arg_count
++] = get_src(ctx
, instr
->src
[1]); /* voffset */
2563 params
[arg_count
++] = LLVMConstInt(ctx
->ac
.i1
, 0, false); /* slc */
2565 switch (instr
->intrinsic
) {
2566 case nir_intrinsic_ssbo_atomic_add
:
2567 name
= "llvm.amdgcn.buffer.atomic.add";
2569 case nir_intrinsic_ssbo_atomic_imin
:
2570 name
= "llvm.amdgcn.buffer.atomic.smin";
2572 case nir_intrinsic_ssbo_atomic_umin
:
2573 name
= "llvm.amdgcn.buffer.atomic.umin";
2575 case nir_intrinsic_ssbo_atomic_imax
:
2576 name
= "llvm.amdgcn.buffer.atomic.smax";
2578 case nir_intrinsic_ssbo_atomic_umax
:
2579 name
= "llvm.amdgcn.buffer.atomic.umax";
2581 case nir_intrinsic_ssbo_atomic_and
:
2582 name
= "llvm.amdgcn.buffer.atomic.and";
2584 case nir_intrinsic_ssbo_atomic_or
:
2585 name
= "llvm.amdgcn.buffer.atomic.or";
2587 case nir_intrinsic_ssbo_atomic_xor
:
2588 name
= "llvm.amdgcn.buffer.atomic.xor";
2590 case nir_intrinsic_ssbo_atomic_exchange
:
2591 name
= "llvm.amdgcn.buffer.atomic.swap";
2593 case nir_intrinsic_ssbo_atomic_comp_swap
:
2594 name
= "llvm.amdgcn.buffer.atomic.cmpswap";
2600 return ac_build_intrinsic(&ctx
->ac
, name
, ctx
->ac
.i32
, params
, arg_count
, 0);
2603 static LLVMValueRef
visit_load_buffer(struct ac_nir_context
*ctx
,
2604 const nir_intrinsic_instr
*instr
)
2606 LLVMValueRef results
[2];
2607 int load_components
;
2608 int num_components
= instr
->num_components
;
2609 if (instr
->dest
.ssa
.bit_size
== 64)
2610 num_components
*= 2;
2612 for (int i
= 0; i
< num_components
; i
+= load_components
) {
2613 load_components
= MIN2(num_components
- i
, 4);
2614 const char *load_name
;
2615 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2616 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, i
* 4, false);
2617 offset
= LLVMBuildAdd(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[1]), offset
, "");
2619 if (load_components
== 3)
2620 data_type
= LLVMVectorType(ctx
->ac
.f32
, 4);
2621 else if (load_components
> 1)
2622 data_type
= LLVMVectorType(ctx
->ac
.f32
, load_components
);
2624 if (load_components
>= 3)
2625 load_name
= "llvm.amdgcn.buffer.load.v4f32";
2626 else if (load_components
== 2)
2627 load_name
= "llvm.amdgcn.buffer.load.v2f32";
2628 else if (load_components
== 1)
2629 load_name
= "llvm.amdgcn.buffer.load.f32";
2631 unreachable("unhandled number of components");
2633 LLVMValueRef params
[] = {
2634 ctx
->abi
->load_ssbo(ctx
->abi
,
2635 get_src(ctx
, instr
->src
[0]),
2643 results
[i
> 0 ? 1 : 0] = ac_build_intrinsic(&ctx
->ac
, load_name
, data_type
, params
, 5, 0);
2647 LLVMValueRef ret
= results
[0];
2648 if (num_components
> 4 || num_components
== 3) {
2649 LLVMValueRef masks
[] = {
2650 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
2651 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
2652 LLVMConstInt(ctx
->ac
.i32
, 4, false), LLVMConstInt(ctx
->ac
.i32
, 5, false),
2653 LLVMConstInt(ctx
->ac
.i32
, 6, false), LLVMConstInt(ctx
->ac
.i32
, 7, false)
2656 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
2657 ret
= LLVMBuildShuffleVector(ctx
->ac
.builder
, results
[0],
2658 results
[num_components
> 4 ? 1 : 0], swizzle
, "");
2661 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2662 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2665 static LLVMValueRef
visit_load_ubo_buffer(struct ac_nir_context
*ctx
,
2666 const nir_intrinsic_instr
*instr
)
2669 LLVMValueRef rsrc
= get_src(ctx
, instr
->src
[0]);
2670 LLVMValueRef offset
= get_src(ctx
, instr
->src
[1]);
2671 int num_components
= instr
->num_components
;
2673 if (ctx
->abi
->load_ubo
)
2674 rsrc
= ctx
->abi
->load_ubo(ctx
->abi
, rsrc
);
2676 if (instr
->dest
.ssa
.bit_size
== 64)
2677 num_components
*= 2;
2679 ret
= ac_build_buffer_load(&ctx
->ac
, rsrc
, num_components
, NULL
, offset
,
2680 NULL
, 0, false, false, true, true);
2681 ret
= trim_vector(&ctx
->ac
, ret
, num_components
);
2682 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2683 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2687 get_deref_offset(struct ac_nir_context
*ctx
, nir_deref_var
*deref
,
2688 bool vs_in
, unsigned *vertex_index_out
,
2689 LLVMValueRef
*vertex_index_ref
,
2690 unsigned *const_out
, LLVMValueRef
*indir_out
)
2692 unsigned const_offset
= 0;
2693 nir_deref
*tail
= &deref
->deref
;
2694 LLVMValueRef offset
= NULL
;
2696 if (vertex_index_out
!= NULL
|| vertex_index_ref
!= NULL
) {
2698 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2699 if (vertex_index_out
)
2700 *vertex_index_out
= deref_array
->base_offset
;
2702 if (vertex_index_ref
) {
2703 LLVMValueRef vtx
= LLVMConstInt(ctx
->ac
.i32
, deref_array
->base_offset
, false);
2704 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
2705 vtx
= LLVMBuildAdd(ctx
->ac
.builder
, vtx
, get_src(ctx
, deref_array
->indirect
), "");
2707 *vertex_index_ref
= vtx
;
2711 if (deref
->var
->data
.compact
) {
2712 assert(tail
->child
->deref_type
== nir_deref_type_array
);
2713 assert(glsl_type_is_scalar(glsl_without_array(deref
->var
->type
)));
2714 nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
2715 /* We always lower indirect dereferences for "compact" array vars. */
2716 assert(deref_array
->deref_array_type
== nir_deref_array_type_direct
);
2718 const_offset
= deref_array
->base_offset
;
2722 while (tail
->child
!= NULL
) {
2723 const struct glsl_type
*parent_type
= tail
->type
;
2726 if (tail
->deref_type
== nir_deref_type_array
) {
2727 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2728 LLVMValueRef index
, stride
, local_offset
;
2729 unsigned size
= glsl_count_attribute_slots(tail
->type
, vs_in
);
2731 const_offset
+= size
* deref_array
->base_offset
;
2732 if (deref_array
->deref_array_type
== nir_deref_array_type_direct
)
2735 assert(deref_array
->deref_array_type
== nir_deref_array_type_indirect
);
2736 index
= get_src(ctx
, deref_array
->indirect
);
2737 stride
= LLVMConstInt(ctx
->ac
.i32
, size
, 0);
2738 local_offset
= LLVMBuildMul(ctx
->ac
.builder
, stride
, index
, "");
2741 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, local_offset
, "");
2743 offset
= local_offset
;
2744 } else if (tail
->deref_type
== nir_deref_type_struct
) {
2745 nir_deref_struct
*deref_struct
= nir_deref_as_struct(tail
);
2747 for (unsigned i
= 0; i
< deref_struct
->index
; i
++) {
2748 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
2749 const_offset
+= glsl_count_attribute_slots(ft
, vs_in
);
2752 unreachable("unsupported deref type");
2756 if (const_offset
&& offset
)
2757 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
2758 LLVMConstInt(ctx
->ac
.i32
, const_offset
, 0),
2761 *const_out
= const_offset
;
2762 *indir_out
= offset
;
2766 /* The offchip buffer layout for TCS->TES is
2768 * - attribute 0 of patch 0 vertex 0
2769 * - attribute 0 of patch 0 vertex 1
2770 * - attribute 0 of patch 0 vertex 2
2772 * - attribute 0 of patch 1 vertex 0
2773 * - attribute 0 of patch 1 vertex 1
2775 * - attribute 1 of patch 0 vertex 0
2776 * - attribute 1 of patch 0 vertex 1
2778 * - per patch attribute 0 of patch 0
2779 * - per patch attribute 0 of patch 1
2782 * Note that every attribute has 4 components.
2784 static LLVMValueRef
get_tcs_tes_buffer_address(struct nir_to_llvm_context
*ctx
,
2785 LLVMValueRef vertex_index
,
2786 LLVMValueRef param_index
)
2788 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
2789 LLVMValueRef param_stride
, constant16
;
2790 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
2792 vertices_per_patch
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 9, 6);
2793 num_patches
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 0, 9);
2794 total_vertices
= LLVMBuildMul(ctx
->builder
, vertices_per_patch
,
2797 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2799 base_addr
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
2800 vertices_per_patch
, "");
2802 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2805 param_stride
= total_vertices
;
2807 base_addr
= rel_patch_id
;
2808 param_stride
= num_patches
;
2811 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2812 LLVMBuildMul(ctx
->builder
, param_index
,
2813 param_stride
, ""), "");
2815 base_addr
= LLVMBuildMul(ctx
->builder
, base_addr
, constant16
, "");
2817 if (!vertex_index
) {
2818 LLVMValueRef patch_data_offset
=
2819 unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 16, 16);
2821 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2822 patch_data_offset
, "");
2827 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct nir_to_llvm_context
*ctx
,
2829 unsigned const_index
,
2831 LLVMValueRef vertex_index
,
2832 LLVMValueRef indir_index
)
2834 LLVMValueRef param_index
;
2837 param_index
= LLVMBuildAdd(ctx
->builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
2840 if (const_index
&& !is_compact
)
2841 param
+= const_index
;
2842 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
2844 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
2848 mark_tess_output(struct nir_to_llvm_context
*ctx
,
2849 bool is_patch
, uint32_t param
)
2853 ctx
->tess_patch_outputs_written
|= (1ull << param
);
2855 ctx
->tess_outputs_written
|= (1ull << param
);
2859 get_dw_address(struct nir_to_llvm_context
*ctx
,
2860 LLVMValueRef dw_addr
,
2862 unsigned const_index
,
2863 bool compact_const_index
,
2864 LLVMValueRef vertex_index
,
2865 LLVMValueRef stride
,
2866 LLVMValueRef indir_index
)
2871 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2872 LLVMBuildMul(ctx
->builder
,
2878 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2879 LLVMBuildMul(ctx
->builder
, indir_index
,
2880 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
2881 else if (const_index
&& !compact_const_index
)
2882 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2883 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2885 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2886 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
2888 if (const_index
&& compact_const_index
)
2889 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2890 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2895 load_tcs_varyings(struct ac_shader_abi
*abi
,
2896 LLVMValueRef vertex_index
,
2897 LLVMValueRef indir_index
,
2898 unsigned const_index
,
2900 unsigned driver_location
,
2902 unsigned num_components
,
2907 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
2908 LLVMValueRef dw_addr
, stride
;
2909 LLVMValueRef value
[4], result
;
2910 unsigned param
= shader_io_get_unique_index(location
);
2913 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 13, 8);
2914 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
2917 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
2918 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2920 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2925 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2928 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
2929 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2930 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2933 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
2938 store_tcs_output(struct ac_shader_abi
*abi
,
2939 LLVMValueRef vertex_index
,
2940 LLVMValueRef param_index
,
2941 unsigned const_index
,
2943 unsigned driver_location
,
2950 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
2951 LLVMValueRef dw_addr
;
2952 LLVMValueRef stride
= NULL
;
2953 LLVMValueRef buf_addr
= NULL
;
2955 bool store_lds
= true;
2958 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
2961 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
2965 param
= shader_io_get_unique_index(location
);
2966 if (location
== VARYING_SLOT_CLIP_DIST0
&&
2967 is_compact
&& const_index
> 3) {
2973 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
2974 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2976 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2979 mark_tess_output(ctx
, is_patch
, param
);
2981 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2983 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
2984 vertex_index
, param_index
);
2986 bool is_tess_factor
= false;
2987 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
2988 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
2989 is_tess_factor
= true;
2991 unsigned base
= is_compact
? const_index
: 0;
2992 for (unsigned chan
= 0; chan
< 8; chan
++) {
2993 if (!(writemask
& (1 << chan
)))
2995 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
2997 if (store_lds
|| is_tess_factor
) {
2998 LLVMValueRef dw_addr_chan
=
2999 LLVMBuildAdd(ctx
->builder
, dw_addr
,
3000 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
3001 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
3004 if (!is_tess_factor
&& writemask
!= 0xF)
3005 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
3006 buf_addr
, ctx
->oc_lds
,
3007 4 * (base
+ chan
), 1, 0, true, false);
3010 if (writemask
== 0xF) {
3011 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
3012 buf_addr
, ctx
->oc_lds
,
3013 (base
* 4), 1, 0, true, false);
3018 load_tes_input(struct ac_shader_abi
*abi
,
3019 LLVMValueRef vertex_index
,
3020 LLVMValueRef param_index
,
3021 unsigned const_index
,
3023 unsigned driver_location
,
3025 unsigned num_components
,
3030 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
3031 LLVMValueRef buf_addr
;
3032 LLVMValueRef result
;
3033 unsigned param
= shader_io_get_unique_index(location
);
3035 if (location
== VARYING_SLOT_CLIP_DIST0
&& is_compact
&& const_index
> 3) {
3040 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
3041 is_compact
, vertex_index
, param_index
);
3043 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
3044 buf_addr
= LLVMBuildAdd(ctx
->builder
, buf_addr
, comp_offset
, "");
3046 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
3047 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
3048 result
= trim_vector(&ctx
->ac
, result
, num_components
);
3053 load_gs_input(struct ac_shader_abi
*abi
,
3055 unsigned driver_location
,
3057 unsigned num_components
,
3058 unsigned vertex_index
,
3059 unsigned const_index
,
3062 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
3063 LLVMValueRef vtx_offset
;
3064 LLVMValueRef args
[9];
3065 unsigned param
, vtx_offset_param
;
3066 LLVMValueRef value
[4], result
;
3068 vtx_offset_param
= vertex_index
;
3069 assert(vtx_offset_param
< 6);
3070 vtx_offset
= LLVMBuildMul(ctx
->builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
3071 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3073 param
= shader_io_get_unique_index(location
);
3075 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
3076 if (ctx
->ac
.chip_class
>= GFX9
) {
3077 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
3078 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
3079 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
3080 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
3082 args
[0] = ctx
->esgs_ring
;
3083 args
[1] = vtx_offset
;
3084 args
[2] = LLVMConstInt(ctx
->ac
.i32
, (param
* 4 + i
+ const_index
) * 256, false);
3085 args
[3] = ctx
->ac
.i32_0
;
3086 args
[4] = ctx
->ac
.i32_1
; /* OFFEN */
3087 args
[5] = ctx
->ac
.i32_0
; /* IDXEN */
3088 args
[6] = ctx
->ac
.i32_1
; /* GLC */
3089 args
[7] = ctx
->ac
.i32_0
; /* SLC */
3090 args
[8] = ctx
->ac
.i32_0
; /* TFE */
3092 value
[i
] = ac_build_intrinsic(&ctx
->ac
, "llvm.SI.buffer.load.dword.i32.i32",
3093 ctx
->ac
.i32
, args
, 9,
3094 AC_FUNC_ATTR_READONLY
|
3095 AC_FUNC_ATTR_LEGACY
);
3098 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
3104 build_gep_for_deref(struct ac_nir_context
*ctx
,
3105 nir_deref_var
*deref
)
3107 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->vars
, deref
->var
);
3108 assert(entry
->data
);
3109 LLVMValueRef val
= entry
->data
;
3110 nir_deref
*tail
= deref
->deref
.child
;
3111 while (tail
!= NULL
) {
3112 LLVMValueRef offset
;
3113 switch (tail
->deref_type
) {
3114 case nir_deref_type_array
: {
3115 nir_deref_array
*array
= nir_deref_as_array(tail
);
3116 offset
= LLVMConstInt(ctx
->ac
.i32
, array
->base_offset
, 0);
3117 if (array
->deref_array_type
==
3118 nir_deref_array_type_indirect
) {
3119 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
3126 case nir_deref_type_struct
: {
3127 nir_deref_struct
*deref_struct
=
3128 nir_deref_as_struct(tail
);
3129 offset
= LLVMConstInt(ctx
->ac
.i32
,
3130 deref_struct
->index
, 0);
3134 unreachable("bad deref type");
3136 val
= ac_build_gep0(&ctx
->ac
, val
, offset
);
3142 static LLVMValueRef
load_tess_varyings(struct ac_nir_context
*ctx
,
3143 nir_intrinsic_instr
*instr
,
3146 LLVMValueRef result
;
3147 LLVMValueRef vertex_index
= NULL
;
3148 LLVMValueRef indir_index
= NULL
;
3149 unsigned const_index
= 0;
3150 unsigned location
= instr
->variables
[0]->var
->data
.location
;
3151 unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3152 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3153 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3155 get_deref_offset(ctx
, instr
->variables
[0],
3156 false, NULL
, is_patch
? NULL
: &vertex_index
,
3157 &const_index
, &indir_index
);
3159 result
= ctx
->abi
->load_tess_varyings(ctx
->abi
, vertex_index
, indir_index
,
3160 const_index
, location
, driver_location
,
3161 instr
->variables
[0]->var
->data
.location_frac
,
3162 instr
->num_components
,
3163 is_patch
, is_compact
, load_inputs
);
3164 return LLVMBuildBitCast(ctx
->ac
.builder
, result
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3167 static LLVMValueRef
visit_load_var(struct ac_nir_context
*ctx
,
3168 nir_intrinsic_instr
*instr
)
3170 LLVMValueRef values
[8];
3171 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3172 int ve
= instr
->dest
.ssa
.num_components
;
3173 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3174 LLVMValueRef indir_index
;
3176 unsigned const_index
;
3177 unsigned stride
= instr
->variables
[0]->var
->data
.compact
? 1 : 4;
3178 bool vs_in
= ctx
->stage
== MESA_SHADER_VERTEX
&&
3179 instr
->variables
[0]->var
->data
.mode
== nir_var_shader_in
;
3180 get_deref_offset(ctx
, instr
->variables
[0], vs_in
, NULL
, NULL
,
3181 &const_index
, &indir_index
);
3183 if (instr
->dest
.ssa
.bit_size
== 64)
3186 switch (instr
->variables
[0]->var
->data
.mode
) {
3187 case nir_var_shader_in
:
3188 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3189 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3190 return load_tess_varyings(ctx
, instr
, true);
3193 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3194 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, instr
->dest
.ssa
.bit_size
);
3195 LLVMValueRef indir_index
;
3196 unsigned const_index
, vertex_index
;
3197 get_deref_offset(ctx
, instr
->variables
[0],
3198 false, &vertex_index
, NULL
,
3199 &const_index
, &indir_index
);
3201 return ctx
->abi
->load_inputs(ctx
->abi
, instr
->variables
[0]->var
->data
.location
,
3202 instr
->variables
[0]->var
->data
.driver_location
,
3203 instr
->variables
[0]->var
->data
.location_frac
, ve
,
3204 vertex_index
, const_index
, type
);
3207 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3209 unsigned count
= glsl_count_attribute_slots(
3210 instr
->variables
[0]->var
->type
,
3211 ctx
->stage
== MESA_SHADER_VERTEX
);
3213 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3214 &ctx
->ac
, ctx
->abi
->inputs
+ idx
+ chan
, count
,
3215 stride
, false, true);
3217 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3221 values
[chan
] = ctx
->abi
->inputs
[idx
+ chan
+ const_index
* stride
];
3225 for (unsigned chan
= 0; chan
< ve
; chan
++) {
3227 unsigned count
= glsl_count_attribute_slots(
3228 instr
->variables
[0]->var
->type
, false);
3230 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3231 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3232 stride
, true, true);
3234 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3238 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, ctx
->locals
[idx
+ chan
+ const_index
* stride
], "");
3242 case nir_var_shared
: {
3243 LLVMValueRef address
= build_gep_for_deref(ctx
,
3244 instr
->variables
[0]);
3245 LLVMValueRef val
= LLVMBuildLoad(ctx
->ac
.builder
, address
, "");
3246 return LLVMBuildBitCast(ctx
->ac
.builder
, val
,
3247 get_def_type(ctx
, &instr
->dest
.ssa
),
3250 case nir_var_shader_out
:
3251 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3252 return load_tess_varyings(ctx
, instr
, false);
3255 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3257 unsigned count
= glsl_count_attribute_slots(
3258 instr
->variables
[0]->var
->type
, false);
3260 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3261 &ctx
->ac
, ctx
->outputs
+ idx
+ chan
, count
,
3262 stride
, true, true);
3264 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3268 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
,
3269 ctx
->outputs
[idx
+ chan
+ const_index
* stride
],
3275 unreachable("unhandle variable mode");
3277 ret
= ac_build_varying_gather_values(&ctx
->ac
, values
, ve
, comp
);
3278 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3282 visit_store_var(struct ac_nir_context
*ctx
,
3283 nir_intrinsic_instr
*instr
)
3285 LLVMValueRef temp_ptr
, value
;
3286 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3287 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3288 LLVMValueRef src
= ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
3289 int writemask
= instr
->const_index
[0] << comp
;
3290 LLVMValueRef indir_index
;
3291 unsigned const_index
;
3292 get_deref_offset(ctx
, instr
->variables
[0], false,
3293 NULL
, NULL
, &const_index
, &indir_index
);
3295 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
)) == 64) {
3297 src
= LLVMBuildBitCast(ctx
->ac
.builder
, src
,
3298 LLVMVectorType(ctx
->ac
.f32
, ac_get_llvm_num_components(src
) * 2),
3301 writemask
= widen_mask(writemask
, 2);
3304 switch (instr
->variables
[0]->var
->data
.mode
) {
3305 case nir_var_shader_out
:
3307 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3308 LLVMValueRef vertex_index
= NULL
;
3309 LLVMValueRef indir_index
= NULL
;
3310 unsigned const_index
= 0;
3311 const unsigned location
= instr
->variables
[0]->var
->data
.location
;
3312 const unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3313 const unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3314 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3315 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3317 get_deref_offset(ctx
, instr
->variables
[0],
3318 false, NULL
, is_patch
? NULL
: &vertex_index
,
3319 &const_index
, &indir_index
);
3321 ctx
->abi
->store_tcs_outputs(ctx
->abi
, vertex_index
, indir_index
,
3322 const_index
, location
, driver_location
,
3323 src
, comp
, is_patch
, is_compact
, writemask
);
3327 for (unsigned chan
= 0; chan
< 8; chan
++) {
3329 if (!(writemask
& (1 << chan
)))
3332 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- comp
);
3334 if (instr
->variables
[0]->var
->data
.compact
)
3337 unsigned count
= glsl_count_attribute_slots(
3338 instr
->variables
[0]->var
->type
, false);
3340 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3341 &ctx
->ac
, ctx
->outputs
+ idx
+ chan
, count
,
3342 stride
, true, true);
3344 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3345 value
, indir_index
, "");
3346 build_store_values_extended(&ctx
->ac
, ctx
->outputs
+ idx
+ chan
,
3347 count
, stride
, tmp_vec
);
3350 temp_ptr
= ctx
->outputs
[idx
+ chan
+ const_index
* stride
];
3352 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3357 for (unsigned chan
= 0; chan
< 8; chan
++) {
3358 if (!(writemask
& (1 << chan
)))
3361 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
);
3363 unsigned count
= glsl_count_attribute_slots(
3364 instr
->variables
[0]->var
->type
, false);
3366 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3367 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3370 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3371 value
, indir_index
, "");
3372 build_store_values_extended(&ctx
->ac
, ctx
->locals
+ idx
+ chan
,
3375 temp_ptr
= ctx
->locals
[idx
+ chan
+ const_index
* 4];
3377 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3381 case nir_var_shared
: {
3382 int writemask
= instr
->const_index
[0];
3383 LLVMValueRef address
= build_gep_for_deref(ctx
,
3384 instr
->variables
[0]);
3385 LLVMValueRef val
= get_src(ctx
, instr
->src
[0]);
3386 unsigned components
=
3387 glsl_get_vector_elements(
3388 nir_deref_tail(&instr
->variables
[0]->deref
)->type
);
3389 if (writemask
== (1 << components
) - 1) {
3390 val
= LLVMBuildBitCast(
3391 ctx
->ac
.builder
, val
,
3392 LLVMGetElementType(LLVMTypeOf(address
)), "");
3393 LLVMBuildStore(ctx
->ac
.builder
, val
, address
);
3395 for (unsigned chan
= 0; chan
< 4; chan
++) {
3396 if (!(writemask
& (1 << chan
)))
3399 LLVMBuildStructGEP(ctx
->ac
.builder
,
3401 LLVMValueRef src
= ac_llvm_extract_elem(&ctx
->ac
, val
,
3403 src
= LLVMBuildBitCast(
3404 ctx
->ac
.builder
, src
,
3405 LLVMGetElementType(LLVMTypeOf(ptr
)), "");
3406 LLVMBuildStore(ctx
->ac
.builder
, src
, ptr
);
3416 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
3419 case GLSL_SAMPLER_DIM_BUF
:
3421 case GLSL_SAMPLER_DIM_1D
:
3422 return array
? 2 : 1;
3423 case GLSL_SAMPLER_DIM_2D
:
3424 return array
? 3 : 2;
3425 case GLSL_SAMPLER_DIM_MS
:
3426 return array
? 4 : 3;
3427 case GLSL_SAMPLER_DIM_3D
:
3428 case GLSL_SAMPLER_DIM_CUBE
:
3430 case GLSL_SAMPLER_DIM_RECT
:
3431 case GLSL_SAMPLER_DIM_SUBPASS
:
3433 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
3443 /* Adjust the sample index according to FMASK.
3445 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3446 * which is the identity mapping. Each nibble says which physical sample
3447 * should be fetched to get that sample.
3449 * For example, 0x11111100 means there are only 2 samples stored and
3450 * the second sample covers 3/4 of the pixel. When reading samples 0
3451 * and 1, return physical sample 0 (determined by the first two 0s
3452 * in FMASK), otherwise return physical sample 1.
3454 * The sample index should be adjusted as follows:
3455 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3457 static LLVMValueRef
adjust_sample_index_using_fmask(struct ac_llvm_context
*ctx
,
3458 LLVMValueRef coord_x
, LLVMValueRef coord_y
,
3459 LLVMValueRef coord_z
,
3460 LLVMValueRef sample_index
,
3461 LLVMValueRef fmask_desc_ptr
)
3463 LLVMValueRef fmask_load_address
[4];
3466 fmask_load_address
[0] = coord_x
;
3467 fmask_load_address
[1] = coord_y
;
3469 fmask_load_address
[2] = coord_z
;
3470 fmask_load_address
[3] = LLVMGetUndef(ctx
->i32
);
3473 struct ac_image_args args
= {0};
3475 args
.opcode
= ac_image_load
;
3476 args
.da
= coord_z
? true : false;
3477 args
.resource
= fmask_desc_ptr
;
3479 args
.addr
= ac_build_gather_values(ctx
, fmask_load_address
, coord_z
? 4 : 2);
3481 res
= ac_build_image_opcode(ctx
, &args
);
3483 res
= ac_to_integer(ctx
, res
);
3484 LLVMValueRef four
= LLVMConstInt(ctx
->i32
, 4, false);
3485 LLVMValueRef F
= LLVMConstInt(ctx
->i32
, 0xf, false);
3487 LLVMValueRef fmask
= LLVMBuildExtractElement(ctx
->builder
,
3491 LLVMValueRef sample_index4
=
3492 LLVMBuildMul(ctx
->builder
, sample_index
, four
, "");
3493 LLVMValueRef shifted_fmask
=
3494 LLVMBuildLShr(ctx
->builder
, fmask
, sample_index4
, "");
3495 LLVMValueRef final_sample
=
3496 LLVMBuildAnd(ctx
->builder
, shifted_fmask
, F
, "");
3498 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3499 * resource descriptor is 0 (invalid),
3501 LLVMValueRef fmask_desc
=
3502 LLVMBuildBitCast(ctx
->builder
, fmask_desc_ptr
,
3505 LLVMValueRef fmask_word1
=
3506 LLVMBuildExtractElement(ctx
->builder
, fmask_desc
,
3509 LLVMValueRef word1_is_nonzero
=
3510 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
,
3511 fmask_word1
, ctx
->i32_0
, "");
3513 /* Replace the MSAA sample index. */
3515 LLVMBuildSelect(ctx
->builder
, word1_is_nonzero
,
3516 final_sample
, sample_index
, "");
3517 return sample_index
;
3520 static LLVMValueRef
get_image_coords(struct ac_nir_context
*ctx
,
3521 const nir_intrinsic_instr
*instr
)
3523 const struct glsl_type
*type
= glsl_without_array(instr
->variables
[0]->var
->type
);
3525 LLVMValueRef src0
= get_src(ctx
, instr
->src
[0]);
3526 LLVMValueRef coords
[4];
3527 LLVMValueRef masks
[] = {
3528 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
3529 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
3532 LLVMValueRef sample_index
= ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[1]), 0);
3535 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3536 bool is_array
= glsl_sampler_type_is_array(type
);
3537 bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3538 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3539 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
||
3540 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3541 bool gfx9_1d
= ctx
->ac
.chip_class
>= GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
3542 count
= image_type_to_components_count(dim
, is_array
);
3545 LLVMValueRef fmask_load_address
[3];
3548 fmask_load_address
[0] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3549 fmask_load_address
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[1], "");
3551 fmask_load_address
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[2], "");
3553 fmask_load_address
[2] = NULL
;
3555 for (chan
= 0; chan
< 2; ++chan
)
3556 fmask_load_address
[chan
] =
3557 LLVMBuildAdd(ctx
->ac
.builder
, fmask_load_address
[chan
],
3558 LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3559 ctx
->ac
.i32
, ""), "");
3560 fmask_load_address
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3562 sample_index
= adjust_sample_index_using_fmask(&ctx
->ac
,
3563 fmask_load_address
[0],
3564 fmask_load_address
[1],
3565 fmask_load_address
[2],
3567 get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_FMASK
, NULL
, true, false));
3569 if (count
== 1 && !gfx9_1d
) {
3570 if (instr
->src
[0].ssa
->num_components
)
3571 res
= LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3578 for (chan
= 0; chan
< count
; ++chan
) {
3579 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, src0
, chan
);
3582 for (chan
= 0; chan
< 2; ++chan
)
3583 coords
[chan
] = LLVMBuildAdd(ctx
->ac
.builder
, coords
[chan
], LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3584 ctx
->ac
.i32
, ""), "");
3585 coords
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3591 coords
[2] = coords
[1];
3592 coords
[1] = ctx
->ac
.i32_0
;
3594 coords
[1] = ctx
->ac
.i32_0
;
3599 coords
[count
] = sample_index
;
3604 coords
[3] = LLVMGetUndef(ctx
->ac
.i32
);
3607 res
= ac_build_gather_values(&ctx
->ac
, coords
, count
);
3612 static LLVMValueRef
visit_image_load(struct ac_nir_context
*ctx
,
3613 const nir_intrinsic_instr
*instr
)
3615 LLVMValueRef params
[7];
3617 char intrinsic_name
[64];
3618 const nir_variable
*var
= instr
->variables
[0]->var
;
3619 const struct glsl_type
*type
= var
->type
;
3621 if(instr
->variables
[0]->deref
.child
)
3622 type
= instr
->variables
[0]->deref
.child
->type
;
3624 type
= glsl_without_array(type
);
3626 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3627 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
3628 params
[0] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, false);
3629 params
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3630 ctx
->ac
.i32_0
, ""); /* vindex */
3631 params
[2] = ctx
->ac
.i32_0
; /* voffset */
3632 params
[3] = ctx
->ac
.i1false
; /* glc */
3633 params
[4] = ctx
->ac
.i1false
; /* slc */
3634 res
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.load.format.v4f32", ctx
->ac
.v4f32
,
3637 res
= trim_vector(&ctx
->ac
, res
, instr
->dest
.ssa
.num_components
);
3638 res
= ac_to_integer(&ctx
->ac
, res
);
3640 bool is_da
= glsl_sampler_type_is_array(type
) ||
3641 dim
== GLSL_SAMPLER_DIM_CUBE
||
3642 dim
== GLSL_SAMPLER_DIM_3D
||
3643 dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3644 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
;
3645 LLVMValueRef da
= is_da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3646 LLVMValueRef glc
= ctx
->ac
.i1false
;
3647 LLVMValueRef slc
= ctx
->ac
.i1false
;
3649 params
[0] = get_image_coords(ctx
, instr
);
3650 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3651 params
[2] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3652 if (HAVE_LLVM
<= 0x0309) {
3653 params
[3] = ctx
->ac
.i1false
; /* r128 */
3658 LLVMValueRef lwe
= ctx
->ac
.i1false
;
3665 ac_get_image_intr_name("llvm.amdgcn.image.load",
3666 ctx
->ac
.v4f32
, /* vdata */
3667 LLVMTypeOf(params
[0]), /* coords */
3668 LLVMTypeOf(params
[1]), /* rsrc */
3669 intrinsic_name
, sizeof(intrinsic_name
));
3671 res
= ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.v4f32
,
3672 params
, 7, AC_FUNC_ATTR_READONLY
);
3674 return ac_to_integer(&ctx
->ac
, res
);
3677 static void visit_image_store(struct ac_nir_context
*ctx
,
3678 nir_intrinsic_instr
*instr
)
3680 LLVMValueRef params
[8];
3681 char intrinsic_name
[64];
3682 const nir_variable
*var
= instr
->variables
[0]->var
;
3683 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3684 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3685 LLVMValueRef glc
= ctx
->ac
.i1false
;
3686 bool force_glc
= ctx
->ac
.chip_class
== SI
;
3688 glc
= ctx
->ac
.i1true
;
3690 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
3691 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2])); /* data */
3692 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, true);
3693 params
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3694 ctx
->ac
.i32_0
, ""); /* vindex */
3695 params
[3] = ctx
->ac
.i32_0
; /* voffset */
3696 params
[4] = glc
; /* glc */
3697 params
[5] = ctx
->ac
.i1false
; /* slc */
3698 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.store.format.v4f32", ctx
->ac
.voidt
,
3701 bool is_da
= glsl_sampler_type_is_array(type
) ||
3702 dim
== GLSL_SAMPLER_DIM_CUBE
||
3703 dim
== GLSL_SAMPLER_DIM_3D
;
3704 LLVMValueRef da
= is_da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3705 LLVMValueRef slc
= ctx
->ac
.i1false
;
3707 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2]));
3708 params
[1] = get_image_coords(ctx
, instr
); /* coords */
3709 params
[2] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, true);
3710 params
[3] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3711 if (HAVE_LLVM
<= 0x0309) {
3712 params
[4] = ctx
->ac
.i1false
; /* r128 */
3717 LLVMValueRef lwe
= ctx
->ac
.i1false
;
3724 ac_get_image_intr_name("llvm.amdgcn.image.store",
3725 LLVMTypeOf(params
[0]), /* vdata */
3726 LLVMTypeOf(params
[1]), /* coords */
3727 LLVMTypeOf(params
[2]), /* rsrc */
3728 intrinsic_name
, sizeof(intrinsic_name
));
3730 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.voidt
,
3736 static LLVMValueRef
visit_image_atomic(struct ac_nir_context
*ctx
,
3737 const nir_intrinsic_instr
*instr
)
3739 LLVMValueRef params
[7];
3740 int param_count
= 0;
3741 const nir_variable
*var
= instr
->variables
[0]->var
;
3743 const char *atomic_name
;
3744 char intrinsic_name
[41];
3745 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3746 MAYBE_UNUSED
int length
;
3748 bool is_unsigned
= glsl_get_sampler_result_type(type
) == GLSL_TYPE_UINT
;
3750 switch (instr
->intrinsic
) {
3751 case nir_intrinsic_image_atomic_add
:
3752 atomic_name
= "add";
3754 case nir_intrinsic_image_atomic_min
:
3755 atomic_name
= is_unsigned
? "umin" : "smin";
3757 case nir_intrinsic_image_atomic_max
:
3758 atomic_name
= is_unsigned
? "umax" : "smax";
3760 case nir_intrinsic_image_atomic_and
:
3761 atomic_name
= "and";
3763 case nir_intrinsic_image_atomic_or
:
3766 case nir_intrinsic_image_atomic_xor
:
3767 atomic_name
= "xor";
3769 case nir_intrinsic_image_atomic_exchange
:
3770 atomic_name
= "swap";
3772 case nir_intrinsic_image_atomic_comp_swap
:
3773 atomic_name
= "cmpswap";
3779 if (instr
->intrinsic
== nir_intrinsic_image_atomic_comp_swap
)
3780 params
[param_count
++] = get_src(ctx
, instr
->src
[3]);
3781 params
[param_count
++] = get_src(ctx
, instr
->src
[2]);
3783 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3784 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
,
3786 params
[param_count
++] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3787 ctx
->ac
.i32_0
, ""); /* vindex */
3788 params
[param_count
++] = ctx
->ac
.i32_0
; /* voffset */
3789 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3791 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3792 "llvm.amdgcn.buffer.atomic.%s", atomic_name
);
3794 char coords_type
[8];
3796 bool da
= glsl_sampler_type_is_array(type
) ||
3797 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
;
3799 LLVMValueRef coords
= params
[param_count
++] = get_image_coords(ctx
, instr
);
3800 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
,
3802 params
[param_count
++] = ctx
->ac
.i1false
; /* r128 */
3803 params
[param_count
++] = da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
; /* da */
3804 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3806 build_int_type_name(LLVMTypeOf(coords
),
3807 coords_type
, sizeof(coords_type
));
3809 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3810 "llvm.amdgcn.image.atomic.%s.%s", atomic_name
, coords_type
);
3813 assert(length
< sizeof(intrinsic_name
));
3814 return ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.i32
, params
, param_count
, 0);
3817 static LLVMValueRef
visit_image_size(struct ac_nir_context
*ctx
,
3818 const nir_intrinsic_instr
*instr
)
3821 const nir_variable
*var
= instr
->variables
[0]->var
;
3822 const struct glsl_type
*type
= instr
->variables
[0]->var
->type
;
3823 bool da
= glsl_sampler_type_is_array(var
->type
) ||
3824 glsl_get_sampler_dim(var
->type
) == GLSL_SAMPLER_DIM_CUBE
||
3825 glsl_get_sampler_dim(var
->type
) == GLSL_SAMPLER_DIM_3D
;
3826 if(instr
->variables
[0]->deref
.child
)
3827 type
= instr
->variables
[0]->deref
.child
->type
;
3829 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
)
3830 return get_buffer_size(ctx
,
3831 get_sampler_desc(ctx
, instr
->variables
[0],
3832 AC_DESC_BUFFER
, NULL
, true, false), true);
3834 struct ac_image_args args
= { 0 };
3838 args
.resource
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3839 args
.opcode
= ac_image_get_resinfo
;
3840 args
.addr
= ctx
->ac
.i32_0
;
3842 res
= ac_build_image_opcode(&ctx
->ac
, &args
);
3844 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
3846 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
3847 glsl_sampler_type_is_array(type
)) {
3848 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
3849 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3850 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
3851 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, z
, two
, "");
3853 if (ctx
->ac
.chip_class
>= GFX9
&&
3854 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
3855 glsl_sampler_type_is_array(type
)) {
3856 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3857 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, layers
,
3864 #define NOOP_WAITCNT 0xf7f
3865 #define LGKM_CNT 0x07f
3866 #define VM_CNT 0xf70
3868 static void emit_membar(struct nir_to_llvm_context
*ctx
,
3869 const nir_intrinsic_instr
*instr
)
3871 unsigned waitcnt
= NOOP_WAITCNT
;
3873 switch (instr
->intrinsic
) {
3874 case nir_intrinsic_memory_barrier
:
3875 case nir_intrinsic_group_memory_barrier
:
3876 waitcnt
&= VM_CNT
& LGKM_CNT
;
3878 case nir_intrinsic_memory_barrier_atomic_counter
:
3879 case nir_intrinsic_memory_barrier_buffer
:
3880 case nir_intrinsic_memory_barrier_image
:
3883 case nir_intrinsic_memory_barrier_shared
:
3884 waitcnt
&= LGKM_CNT
;
3889 if (waitcnt
!= NOOP_WAITCNT
)
3890 ac_build_waitcnt(&ctx
->ac
, waitcnt
);
3893 static void emit_barrier(struct ac_llvm_context
*ac
, gl_shader_stage stage
)
3895 /* SI only (thanks to a hw bug workaround):
3896 * The real barrier instruction isn’t needed, because an entire patch
3897 * always fits into a single wave.
3899 if (ac
->chip_class
== SI
&& stage
== MESA_SHADER_TESS_CTRL
) {
3900 ac_build_waitcnt(ac
, LGKM_CNT
& VM_CNT
);
3903 ac_build_intrinsic(ac
, "llvm.amdgcn.s.barrier",
3904 ac
->voidt
, NULL
, 0, AC_FUNC_ATTR_CONVERGENT
);
3907 static void emit_discard(struct ac_nir_context
*ctx
,
3908 const nir_intrinsic_instr
*instr
)
3912 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3913 cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3914 get_src(ctx
, instr
->src
[0]),
3917 assert(instr
->intrinsic
== nir_intrinsic_discard
);
3918 cond
= LLVMConstInt(ctx
->ac
.i1
, false, 0);
3921 ac_build_kill_if_false(&ctx
->ac
, cond
);
3925 visit_load_helper_invocation(struct ac_nir_context
*ctx
)
3927 LLVMValueRef result
= ac_build_intrinsic(&ctx
->ac
,
3928 "llvm.amdgcn.ps.live",
3929 ctx
->ac
.i1
, NULL
, 0,
3930 AC_FUNC_ATTR_READNONE
);
3931 result
= LLVMBuildNot(ctx
->ac
.builder
, result
, "");
3932 return LLVMBuildSExt(ctx
->ac
.builder
, result
, ctx
->ac
.i32
, "");
3936 visit_load_local_invocation_index(struct nir_to_llvm_context
*ctx
)
3938 LLVMValueRef result
;
3939 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
->ac
);
3940 result
= LLVMBuildAnd(ctx
->builder
, ctx
->tg_size
,
3941 LLVMConstInt(ctx
->ac
.i32
, 0xfc0, false), "");
3943 return LLVMBuildAdd(ctx
->builder
, result
, thread_id
, "");
3946 static LLVMValueRef
visit_var_atomic(struct nir_to_llvm_context
*ctx
,
3947 const nir_intrinsic_instr
*instr
)
3949 LLVMValueRef ptr
, result
;
3950 LLVMValueRef src
= get_src(ctx
->nir
, instr
->src
[0]);
3951 ptr
= build_gep_for_deref(ctx
->nir
, instr
->variables
[0]);
3953 if (instr
->intrinsic
== nir_intrinsic_var_atomic_comp_swap
) {
3954 LLVMValueRef src1
= get_src(ctx
->nir
, instr
->src
[1]);
3955 result
= LLVMBuildAtomicCmpXchg(ctx
->builder
,
3957 LLVMAtomicOrderingSequentiallyConsistent
,
3958 LLVMAtomicOrderingSequentiallyConsistent
,
3961 LLVMAtomicRMWBinOp op
;
3962 switch (instr
->intrinsic
) {
3963 case nir_intrinsic_var_atomic_add
:
3964 op
= LLVMAtomicRMWBinOpAdd
;
3966 case nir_intrinsic_var_atomic_umin
:
3967 op
= LLVMAtomicRMWBinOpUMin
;
3969 case nir_intrinsic_var_atomic_umax
:
3970 op
= LLVMAtomicRMWBinOpUMax
;
3972 case nir_intrinsic_var_atomic_imin
:
3973 op
= LLVMAtomicRMWBinOpMin
;
3975 case nir_intrinsic_var_atomic_imax
:
3976 op
= LLVMAtomicRMWBinOpMax
;
3978 case nir_intrinsic_var_atomic_and
:
3979 op
= LLVMAtomicRMWBinOpAnd
;
3981 case nir_intrinsic_var_atomic_or
:
3982 op
= LLVMAtomicRMWBinOpOr
;
3984 case nir_intrinsic_var_atomic_xor
:
3985 op
= LLVMAtomicRMWBinOpXor
;
3987 case nir_intrinsic_var_atomic_exchange
:
3988 op
= LLVMAtomicRMWBinOpXchg
;
3994 result
= LLVMBuildAtomicRMW(ctx
->builder
, op
, ptr
, ac_to_integer(&ctx
->ac
, src
),
3995 LLVMAtomicOrderingSequentiallyConsistent
,
4001 #define INTERP_CENTER 0
4002 #define INTERP_CENTROID 1
4003 #define INTERP_SAMPLE 2
4005 static LLVMValueRef
lookup_interp_param(struct nir_to_llvm_context
*ctx
,
4006 enum glsl_interp_mode interp
, unsigned location
)
4009 case INTERP_MODE_FLAT
:
4012 case INTERP_MODE_SMOOTH
:
4013 case INTERP_MODE_NONE
:
4014 if (location
== INTERP_CENTER
)
4015 return ctx
->persp_center
;
4016 else if (location
== INTERP_CENTROID
)
4017 return ctx
->persp_centroid
;
4018 else if (location
== INTERP_SAMPLE
)
4019 return ctx
->persp_sample
;
4021 case INTERP_MODE_NOPERSPECTIVE
:
4022 if (location
== INTERP_CENTER
)
4023 return ctx
->linear_center
;
4024 else if (location
== INTERP_CENTROID
)
4025 return ctx
->linear_centroid
;
4026 else if (location
== INTERP_SAMPLE
)
4027 return ctx
->linear_sample
;
4033 static LLVMValueRef
load_sample_position(struct nir_to_llvm_context
*ctx
,
4034 LLVMValueRef sample_id
)
4036 LLVMValueRef result
;
4037 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false));
4039 ptr
= LLVMBuildBitCast(ctx
->builder
, ptr
,
4040 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
4042 sample_id
= LLVMBuildAdd(ctx
->builder
, sample_id
, ctx
->sample_pos_offset
, "");
4043 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
4048 static LLVMValueRef
load_sample_pos(struct ac_nir_context
*ctx
)
4050 LLVMValueRef values
[2];
4052 values
[0] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[0]);
4053 values
[1] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[1]);
4054 return ac_build_gather_values(&ctx
->ac
, values
, 2);
4057 static LLVMValueRef
load_sample_mask_in(struct ac_nir_context
*ctx
)
4059 uint8_t log2_ps_iter_samples
= ctx
->nctx
->shader_info
->info
.ps
.force_persample
? ctx
->nctx
->options
->key
.fs
.log2_num_samples
: ctx
->nctx
->options
->key
.fs
.log2_ps_iter_samples
;
4061 /* The bit pattern matches that used by fixed function fragment
4063 static const uint16_t ps_iter_masks
[] = {
4064 0xffff, /* not used */
4070 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
4072 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
4074 LLVMValueRef result
, sample_id
;
4075 sample_id
= unpack_param(&ctx
->ac
, ctx
->abi
->ancillary
, 8, 4);
4076 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
4077 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, ctx
->abi
->sample_coverage
, "");
4081 static LLVMValueRef
visit_interp(struct nir_to_llvm_context
*ctx
,
4082 const nir_intrinsic_instr
*instr
)
4084 LLVMValueRef result
[4];
4085 LLVMValueRef interp_param
, attr_number
;
4088 LLVMValueRef src_c0
= NULL
;
4089 LLVMValueRef src_c1
= NULL
;
4090 LLVMValueRef src0
= NULL
;
4091 int input_index
= instr
->variables
[0]->var
->data
.location
- VARYING_SLOT_VAR0
;
4092 switch (instr
->intrinsic
) {
4093 case nir_intrinsic_interp_var_at_centroid
:
4094 location
= INTERP_CENTROID
;
4096 case nir_intrinsic_interp_var_at_sample
:
4097 case nir_intrinsic_interp_var_at_offset
:
4098 location
= INTERP_CENTER
;
4099 src0
= get_src(ctx
->nir
, instr
->src
[0]);
4105 if (instr
->intrinsic
== nir_intrinsic_interp_var_at_offset
) {
4106 src_c0
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->ac
.i32_0
, ""));
4107 src_c1
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->ac
.i32_1
, ""));
4108 } else if (instr
->intrinsic
== nir_intrinsic_interp_var_at_sample
) {
4109 LLVMValueRef sample_position
;
4110 LLVMValueRef halfval
= LLVMConstReal(ctx
->ac
.f32
, 0.5f
);
4112 /* fetch sample ID */
4113 sample_position
= load_sample_position(ctx
, src0
);
4115 src_c0
= LLVMBuildExtractElement(ctx
->builder
, sample_position
, ctx
->ac
.i32_0
, "");
4116 src_c0
= LLVMBuildFSub(ctx
->builder
, src_c0
, halfval
, "");
4117 src_c1
= LLVMBuildExtractElement(ctx
->builder
, sample_position
, ctx
->ac
.i32_1
, "");
4118 src_c1
= LLVMBuildFSub(ctx
->builder
, src_c1
, halfval
, "");
4120 interp_param
= lookup_interp_param(ctx
, instr
->variables
[0]->var
->data
.interpolation
, location
);
4121 attr_number
= LLVMConstInt(ctx
->ac
.i32
, input_index
, false);
4123 if (location
== INTERP_CENTER
) {
4124 LLVMValueRef ij_out
[2];
4125 LLVMValueRef ddxy_out
= emit_ddxy_interp(ctx
->nir
, interp_param
);
4128 * take the I then J parameters, and the DDX/Y for it, and
4129 * calculate the IJ inputs for the interpolator.
4130 * temp1 = ddx * offset/sample.x + I;
4131 * interp_param.I = ddy * offset/sample.y + temp1;
4132 * temp1 = ddx * offset/sample.x + J;
4133 * interp_param.J = ddy * offset/sample.y + temp1;
4135 for (unsigned i
= 0; i
< 2; i
++) {
4136 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->ac
.i32
, i
, false);
4137 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->ac
.i32
, i
+ 2, false);
4138 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->builder
,
4139 ddxy_out
, ix_ll
, "");
4140 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->builder
,
4141 ddxy_out
, iy_ll
, "");
4142 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->builder
,
4143 interp_param
, ix_ll
, "");
4144 LLVMValueRef temp1
, temp2
;
4146 interp_el
= LLVMBuildBitCast(ctx
->builder
, interp_el
,
4149 temp1
= LLVMBuildFMul(ctx
->builder
, ddx_el
, src_c0
, "");
4150 temp1
= LLVMBuildFAdd(ctx
->builder
, temp1
, interp_el
, "");
4152 temp2
= LLVMBuildFMul(ctx
->builder
, ddy_el
, src_c1
, "");
4153 temp2
= LLVMBuildFAdd(ctx
->builder
, temp2
, temp1
, "");
4155 ij_out
[i
] = LLVMBuildBitCast(ctx
->builder
,
4156 temp2
, ctx
->ac
.i32
, "");
4158 interp_param
= ac_build_gather_values(&ctx
->ac
, ij_out
, 2);
4162 for (chan
= 0; chan
< 4; chan
++) {
4163 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
4166 interp_param
= LLVMBuildBitCast(ctx
->builder
,
4167 interp_param
, ctx
->ac
.v2f32
, "");
4168 LLVMValueRef i
= LLVMBuildExtractElement(
4169 ctx
->builder
, interp_param
, ctx
->ac
.i32_0
, "");
4170 LLVMValueRef j
= LLVMBuildExtractElement(
4171 ctx
->builder
, interp_param
, ctx
->ac
.i32_1
, "");
4173 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
4174 llvm_chan
, attr_number
,
4175 ctx
->prim_mask
, i
, j
);
4177 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
4178 LLVMConstInt(ctx
->ac
.i32
, 2, false),
4179 llvm_chan
, attr_number
,
4183 return ac_build_varying_gather_values(&ctx
->ac
, result
, instr
->num_components
,
4184 instr
->variables
[0]->var
->data
.location_frac
);
4188 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
4190 LLVMValueRef gs_next_vertex
;
4191 LLVMValueRef can_emit
;
4193 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4195 assert(stream
== 0);
4197 /* Write vertex attribute values to GSVS ring */
4198 gs_next_vertex
= LLVMBuildLoad(ctx
->builder
,
4199 ctx
->gs_next_vertex
,
4202 /* If this thread has already emitted the declared maximum number of
4203 * vertices, kill it: excessive vertex emissions are not supposed to
4204 * have any effect, and GS threads have no externally observable
4205 * effects other than emitting vertices.
4207 can_emit
= LLVMBuildICmp(ctx
->builder
, LLVMIntULT
, gs_next_vertex
,
4208 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
4209 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
4211 /* loop num outputs */
4213 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
4214 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
4219 if (!(ctx
->output_mask
& (1ull << i
)))
4222 if (i
== VARYING_SLOT_CLIP_DIST0
) {
4223 /* pack clip and cull into a single set of slots */
4224 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
4228 for (unsigned j
= 0; j
< length
; j
++) {
4229 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
,
4231 LLVMValueRef voffset
= LLVMConstInt(ctx
->ac
.i32
, (slot
* 4 + j
) * ctx
->gs_max_out_vertices
, false);
4232 voffset
= LLVMBuildAdd(ctx
->builder
, voffset
, gs_next_vertex
, "");
4233 voffset
= LLVMBuildMul(ctx
->builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4235 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->ac
.i32
, "");
4237 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->gsvs_ring
,
4239 voffset
, ctx
->gs2vs_offset
, 0,
4245 gs_next_vertex
= LLVMBuildAdd(ctx
->builder
, gs_next_vertex
,
4247 LLVMBuildStore(ctx
->builder
, gs_next_vertex
, ctx
->gs_next_vertex
);
4249 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
4253 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
4255 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4256 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
4260 load_tess_coord(struct ac_shader_abi
*abi
, LLVMTypeRef type
,
4261 unsigned num_components
)
4263 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4265 LLVMValueRef coord
[4] = {
4272 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
4273 coord
[2] = LLVMBuildFSub(ctx
->builder
, ctx
->ac
.f32_1
,
4274 LLVMBuildFAdd(ctx
->builder
, coord
[0], coord
[1], ""), "");
4276 LLVMValueRef result
= ac_build_gather_values(&ctx
->ac
, coord
, num_components
);
4277 return LLVMBuildBitCast(ctx
->builder
, result
, type
, "");
4281 load_patch_vertices_in(struct ac_shader_abi
*abi
)
4283 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4284 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
4287 static void visit_intrinsic(struct ac_nir_context
*ctx
,
4288 nir_intrinsic_instr
*instr
)
4290 LLVMValueRef result
= NULL
;
4292 switch (instr
->intrinsic
) {
4293 case nir_intrinsic_ballot
:
4294 result
= ac_build_ballot(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4296 case nir_intrinsic_read_invocation
:
4297 case nir_intrinsic_read_first_invocation
: {
4298 LLVMValueRef args
[2];
4301 args
[0] = get_src(ctx
, instr
->src
[0]);
4304 const char *intr_name
;
4305 if (instr
->intrinsic
== nir_intrinsic_read_invocation
) {
4307 intr_name
= "llvm.amdgcn.readlane";
4310 args
[1] = get_src(ctx
, instr
->src
[1]);
4313 intr_name
= "llvm.amdgcn.readfirstlane";
4316 /* We currently have no other way to prevent LLVM from lifting the icmp
4317 * calls to a dominating basic block.
4319 ac_build_optimization_barrier(&ctx
->ac
, &args
[0]);
4321 result
= ac_build_intrinsic(&ctx
->ac
, intr_name
,
4322 ctx
->ac
.i32
, args
, num_args
,
4323 AC_FUNC_ATTR_READNONE
|
4324 AC_FUNC_ATTR_CONVERGENT
);
4327 case nir_intrinsic_load_subgroup_invocation
:
4328 result
= ac_get_thread_id(&ctx
->ac
);
4330 case nir_intrinsic_load_work_group_id
: {
4331 LLVMValueRef values
[3];
4333 for (int i
= 0; i
< 3; i
++) {
4334 values
[i
] = ctx
->nctx
->workgroup_ids
[i
] ?
4335 ctx
->nctx
->workgroup_ids
[i
] : ctx
->ac
.i32_0
;
4338 result
= ac_build_gather_values(&ctx
->ac
, values
, 3);
4341 case nir_intrinsic_load_base_vertex
: {
4342 result
= ctx
->abi
->base_vertex
;
4345 case nir_intrinsic_load_vertex_id_zero_base
: {
4346 result
= ctx
->abi
->vertex_id
;
4349 case nir_intrinsic_load_local_invocation_id
: {
4350 result
= ctx
->nctx
->local_invocation_ids
;
4353 case nir_intrinsic_load_base_instance
:
4354 result
= ctx
->abi
->start_instance
;
4356 case nir_intrinsic_load_draw_id
:
4357 result
= ctx
->abi
->draw_id
;
4359 case nir_intrinsic_load_view_index
:
4360 result
= ctx
->nctx
->view_index
? ctx
->nctx
->view_index
: ctx
->ac
.i32_0
;
4362 case nir_intrinsic_load_invocation_id
:
4363 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
4364 result
= unpack_param(&ctx
->ac
, ctx
->abi
->tcs_rel_ids
, 8, 5);
4366 result
= ctx
->abi
->gs_invocation_id
;
4368 case nir_intrinsic_load_primitive_id
:
4369 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
4370 result
= ctx
->abi
->gs_prim_id
;
4371 } else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
4372 result
= ctx
->abi
->tcs_patch_id
;
4373 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4374 result
= ctx
->abi
->tes_patch_id
;
4376 fprintf(stderr
, "Unknown primitive id intrinsic: %d", ctx
->stage
);
4378 case nir_intrinsic_load_sample_id
:
4379 result
= unpack_param(&ctx
->ac
, ctx
->abi
->ancillary
, 8, 4);
4381 case nir_intrinsic_load_sample_pos
:
4382 result
= load_sample_pos(ctx
);
4384 case nir_intrinsic_load_sample_mask_in
:
4386 result
= load_sample_mask_in(ctx
);
4388 result
= ctx
->abi
->sample_coverage
;
4390 case nir_intrinsic_load_frag_coord
: {
4391 LLVMValueRef values
[4] = {
4392 ctx
->abi
->frag_pos
[0],
4393 ctx
->abi
->frag_pos
[1],
4394 ctx
->abi
->frag_pos
[2],
4395 ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, ctx
->abi
->frag_pos
[3])
4397 result
= ac_build_gather_values(&ctx
->ac
, values
, 4);
4400 case nir_intrinsic_load_front_face
:
4401 result
= ctx
->abi
->front_face
;
4403 case nir_intrinsic_load_helper_invocation
:
4404 result
= visit_load_helper_invocation(ctx
);
4406 case nir_intrinsic_load_instance_id
:
4407 result
= ctx
->abi
->instance_id
;
4409 case nir_intrinsic_load_num_work_groups
:
4410 result
= ctx
->nctx
->num_work_groups
;
4412 case nir_intrinsic_load_local_invocation_index
:
4413 result
= visit_load_local_invocation_index(ctx
->nctx
);
4415 case nir_intrinsic_load_push_constant
:
4416 result
= visit_load_push_constant(ctx
->nctx
, instr
);
4418 case nir_intrinsic_vulkan_resource_index
:
4419 result
= visit_vulkan_resource_index(ctx
->nctx
, instr
);
4421 case nir_intrinsic_vulkan_resource_reindex
:
4422 result
= visit_vulkan_resource_reindex(ctx
->nctx
, instr
);
4424 case nir_intrinsic_store_ssbo
:
4425 visit_store_ssbo(ctx
, instr
);
4427 case nir_intrinsic_load_ssbo
:
4428 result
= visit_load_buffer(ctx
, instr
);
4430 case nir_intrinsic_ssbo_atomic_add
:
4431 case nir_intrinsic_ssbo_atomic_imin
:
4432 case nir_intrinsic_ssbo_atomic_umin
:
4433 case nir_intrinsic_ssbo_atomic_imax
:
4434 case nir_intrinsic_ssbo_atomic_umax
:
4435 case nir_intrinsic_ssbo_atomic_and
:
4436 case nir_intrinsic_ssbo_atomic_or
:
4437 case nir_intrinsic_ssbo_atomic_xor
:
4438 case nir_intrinsic_ssbo_atomic_exchange
:
4439 case nir_intrinsic_ssbo_atomic_comp_swap
:
4440 result
= visit_atomic_ssbo(ctx
, instr
);
4442 case nir_intrinsic_load_ubo
:
4443 result
= visit_load_ubo_buffer(ctx
, instr
);
4445 case nir_intrinsic_get_buffer_size
:
4446 result
= visit_get_buffer_size(ctx
, instr
);
4448 case nir_intrinsic_load_var
:
4449 result
= visit_load_var(ctx
, instr
);
4451 case nir_intrinsic_store_var
:
4452 visit_store_var(ctx
, instr
);
4454 case nir_intrinsic_image_load
:
4455 result
= visit_image_load(ctx
, instr
);
4457 case nir_intrinsic_image_store
:
4458 visit_image_store(ctx
, instr
);
4460 case nir_intrinsic_image_atomic_add
:
4461 case nir_intrinsic_image_atomic_min
:
4462 case nir_intrinsic_image_atomic_max
:
4463 case nir_intrinsic_image_atomic_and
:
4464 case nir_intrinsic_image_atomic_or
:
4465 case nir_intrinsic_image_atomic_xor
:
4466 case nir_intrinsic_image_atomic_exchange
:
4467 case nir_intrinsic_image_atomic_comp_swap
:
4468 result
= visit_image_atomic(ctx
, instr
);
4470 case nir_intrinsic_image_size
:
4471 result
= visit_image_size(ctx
, instr
);
4473 case nir_intrinsic_discard
:
4474 case nir_intrinsic_discard_if
:
4475 emit_discard(ctx
, instr
);
4477 case nir_intrinsic_memory_barrier
:
4478 case nir_intrinsic_group_memory_barrier
:
4479 case nir_intrinsic_memory_barrier_atomic_counter
:
4480 case nir_intrinsic_memory_barrier_buffer
:
4481 case nir_intrinsic_memory_barrier_image
:
4482 case nir_intrinsic_memory_barrier_shared
:
4483 emit_membar(ctx
->nctx
, instr
);
4485 case nir_intrinsic_barrier
:
4486 emit_barrier(&ctx
->ac
, ctx
->stage
);
4488 case nir_intrinsic_var_atomic_add
:
4489 case nir_intrinsic_var_atomic_imin
:
4490 case nir_intrinsic_var_atomic_umin
:
4491 case nir_intrinsic_var_atomic_imax
:
4492 case nir_intrinsic_var_atomic_umax
:
4493 case nir_intrinsic_var_atomic_and
:
4494 case nir_intrinsic_var_atomic_or
:
4495 case nir_intrinsic_var_atomic_xor
:
4496 case nir_intrinsic_var_atomic_exchange
:
4497 case nir_intrinsic_var_atomic_comp_swap
:
4498 result
= visit_var_atomic(ctx
->nctx
, instr
);
4500 case nir_intrinsic_interp_var_at_centroid
:
4501 case nir_intrinsic_interp_var_at_sample
:
4502 case nir_intrinsic_interp_var_at_offset
:
4503 result
= visit_interp(ctx
->nctx
, instr
);
4505 case nir_intrinsic_emit_vertex
:
4506 ctx
->abi
->emit_vertex(ctx
->abi
, nir_intrinsic_stream_id(instr
), ctx
->outputs
);
4508 case nir_intrinsic_end_primitive
:
4509 ctx
->abi
->emit_primitive(ctx
->abi
, nir_intrinsic_stream_id(instr
));
4511 case nir_intrinsic_load_tess_coord
: {
4512 LLVMTypeRef type
= ctx
->nctx
?
4513 get_def_type(ctx
->nctx
->nir
, &instr
->dest
.ssa
) :
4515 result
= ctx
->abi
->load_tess_coord(ctx
->abi
, type
, instr
->num_components
);
4518 case nir_intrinsic_load_tess_level_outer
:
4519 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_OUTER
);
4521 case nir_intrinsic_load_tess_level_inner
:
4522 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_INNER
);
4524 case nir_intrinsic_load_patch_vertices_in
:
4525 result
= ctx
->abi
->load_patch_vertices_in(ctx
->abi
);
4527 case nir_intrinsic_vote_all
: {
4528 LLVMValueRef tmp
= ac_build_vote_all(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4529 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4532 case nir_intrinsic_vote_any
: {
4533 LLVMValueRef tmp
= ac_build_vote_any(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4534 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4537 case nir_intrinsic_vote_eq
: {
4538 LLVMValueRef tmp
= ac_build_vote_eq(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4539 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4543 fprintf(stderr
, "Unknown intrinsic: ");
4544 nir_print_instr(&instr
->instr
, stderr
);
4545 fprintf(stderr
, "\n");
4549 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4553 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
4554 LLVMValueRef buffer_ptr
, bool write
)
4556 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4557 LLVMValueRef result
;
4559 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
4561 result
= LLVMBuildLoad(ctx
->builder
, buffer_ptr
, "");
4562 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
4567 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
4569 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4570 LLVMValueRef result
;
4572 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
4574 result
= LLVMBuildLoad(ctx
->builder
, buffer_ptr
, "");
4575 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
4580 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
4581 unsigned descriptor_set
,
4582 unsigned base_index
,
4583 unsigned constant_index
,
4585 enum ac_descriptor_type desc_type
,
4586 bool image
, bool write
)
4588 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4589 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
4590 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
4591 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
4592 unsigned offset
= binding
->offset
;
4593 unsigned stride
= binding
->size
;
4595 LLVMBuilderRef builder
= ctx
->builder
;
4598 assert(base_index
< layout
->binding_count
);
4600 switch (desc_type
) {
4602 type
= ctx
->ac
.v8i32
;
4606 type
= ctx
->ac
.v8i32
;
4610 case AC_DESC_SAMPLER
:
4611 type
= ctx
->ac
.v4i32
;
4612 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
4617 case AC_DESC_BUFFER
:
4618 type
= ctx
->ac
.v4i32
;
4622 unreachable("invalid desc_type\n");
4625 offset
+= constant_index
* stride
;
4627 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
4628 (!index
|| binding
->immutable_samplers_equal
)) {
4629 if (binding
->immutable_samplers_equal
)
4632 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
4634 LLVMValueRef constants
[] = {
4635 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
4636 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
4637 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
4638 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
4640 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
4643 assert(stride
% type_size
== 0);
4646 index
= ctx
->ac
.i32_0
;
4648 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
4650 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->ac
.i32
, offset
, 0));
4651 list
= LLVMBuildPointerCast(builder
, list
, ac_array_in_const_addr_space(type
), "");
4653 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
4656 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
4657 const nir_deref_var
*deref
,
4658 enum ac_descriptor_type desc_type
,
4659 const nir_tex_instr
*tex_instr
,
4660 bool image
, bool write
)
4662 LLVMValueRef index
= NULL
;
4663 unsigned constant_index
= 0;
4664 unsigned descriptor_set
;
4665 unsigned base_index
;
4668 assert(tex_instr
&& !image
);
4670 base_index
= tex_instr
->sampler_index
;
4672 const nir_deref
*tail
= &deref
->deref
;
4673 while (tail
->child
) {
4674 const nir_deref_array
*child
= nir_deref_as_array(tail
->child
);
4675 unsigned array_size
= glsl_get_aoa_size(tail
->child
->type
);
4680 assert(child
->deref_array_type
!= nir_deref_array_type_wildcard
);
4682 if (child
->deref_array_type
== nir_deref_array_type_indirect
) {
4683 LLVMValueRef indirect
= get_src(ctx
, child
->indirect
);
4685 indirect
= LLVMBuildMul(ctx
->ac
.builder
, indirect
,
4686 LLVMConstInt(ctx
->ac
.i32
, array_size
, false), "");
4691 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
, indirect
, "");
4694 constant_index
+= child
->base_offset
* array_size
;
4696 tail
= &child
->deref
;
4698 descriptor_set
= deref
->var
->data
.descriptor_set
;
4699 base_index
= deref
->var
->data
.binding
;
4702 return ctx
->abi
->load_sampler_desc(ctx
->abi
,
4705 constant_index
, index
,
4706 desc_type
, image
, write
);
4709 static void set_tex_fetch_args(struct ac_llvm_context
*ctx
,
4710 struct ac_image_args
*args
,
4711 const nir_tex_instr
*instr
,
4713 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
4714 LLVMValueRef
*param
, unsigned count
,
4717 unsigned is_rect
= 0;
4718 bool da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
4720 if (op
== nir_texop_lod
)
4722 /* Pad to power of two vector */
4723 while (count
< util_next_power_of_two(count
))
4724 param
[count
++] = LLVMGetUndef(ctx
->i32
);
4727 args
->addr
= ac_build_gather_values(ctx
, param
, count
);
4729 args
->addr
= param
[0];
4731 args
->resource
= res_ptr
;
4732 args
->sampler
= samp_ptr
;
4734 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
&& op
== nir_texop_txf
) {
4735 args
->addr
= param
[0];
4739 args
->dmask
= dmask
;
4740 args
->unorm
= is_rect
;
4744 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4747 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4748 * filtering manually. The driver sets img7 to a mask clearing
4749 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4750 * s_and_b32 samp0, samp0, img7
4753 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4755 static LLVMValueRef
sici_fix_sampler_aniso(struct ac_nir_context
*ctx
,
4756 LLVMValueRef res
, LLVMValueRef samp
)
4758 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4759 LLVMValueRef img7
, samp0
;
4761 if (ctx
->ac
.chip_class
>= VI
)
4764 img7
= LLVMBuildExtractElement(builder
, res
,
4765 LLVMConstInt(ctx
->ac
.i32
, 7, 0), "");
4766 samp0
= LLVMBuildExtractElement(builder
, samp
,
4767 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4768 samp0
= LLVMBuildAnd(builder
, samp0
, img7
, "");
4769 return LLVMBuildInsertElement(builder
, samp
, samp0
,
4770 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4773 static void tex_fetch_ptrs(struct ac_nir_context
*ctx
,
4774 nir_tex_instr
*instr
,
4775 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
4776 LLVMValueRef
*fmask_ptr
)
4778 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4779 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_BUFFER
, instr
, false, false);
4781 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_IMAGE
, instr
, false, false);
4784 *samp_ptr
= get_sampler_desc(ctx
, instr
->sampler
, AC_DESC_SAMPLER
, instr
, false, false);
4786 *samp_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_SAMPLER
, instr
, false, false);
4787 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
)
4788 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
4790 if (fmask_ptr
&& !instr
->sampler
&& (instr
->op
== nir_texop_txf_ms
||
4791 instr
->op
== nir_texop_samples_identical
))
4792 *fmask_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_FMASK
, instr
, false, false);
4795 static LLVMValueRef
apply_round_slice(struct ac_llvm_context
*ctx
,
4798 coord
= ac_to_float(ctx
, coord
);
4799 coord
= ac_build_intrinsic(ctx
, "llvm.rint.f32", ctx
->f32
, &coord
, 1, 0);
4800 coord
= ac_to_integer(ctx
, coord
);
4804 static void visit_tex(struct ac_nir_context
*ctx
, nir_tex_instr
*instr
)
4806 LLVMValueRef result
= NULL
;
4807 struct ac_image_args args
= { 0 };
4808 unsigned dmask
= 0xf;
4809 LLVMValueRef address
[16];
4810 LLVMValueRef coords
[5];
4811 LLVMValueRef coord
= NULL
, lod
= NULL
, comparator
= NULL
;
4812 LLVMValueRef bias
= NULL
, offsets
= NULL
;
4813 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
, sample_index
= NULL
;
4814 LLVMValueRef ddx
= NULL
, ddy
= NULL
;
4815 LLVMValueRef derivs
[6];
4816 unsigned chan
, count
= 0;
4817 unsigned const_src
= 0, num_deriv_comp
= 0;
4818 bool lod_is_zero
= false;
4820 tex_fetch_ptrs(ctx
, instr
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4822 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4823 switch (instr
->src
[i
].src_type
) {
4824 case nir_tex_src_coord
:
4825 coord
= get_src(ctx
, instr
->src
[i
].src
);
4827 case nir_tex_src_projector
:
4829 case nir_tex_src_comparator
:
4830 comparator
= get_src(ctx
, instr
->src
[i
].src
);
4832 case nir_tex_src_offset
:
4833 offsets
= get_src(ctx
, instr
->src
[i
].src
);
4836 case nir_tex_src_bias
:
4837 bias
= get_src(ctx
, instr
->src
[i
].src
);
4839 case nir_tex_src_lod
: {
4840 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
4842 if (val
&& val
->i32
[0] == 0)
4844 lod
= get_src(ctx
, instr
->src
[i
].src
);
4847 case nir_tex_src_ms_index
:
4848 sample_index
= get_src(ctx
, instr
->src
[i
].src
);
4850 case nir_tex_src_ms_mcs
:
4852 case nir_tex_src_ddx
:
4853 ddx
= get_src(ctx
, instr
->src
[i
].src
);
4854 num_deriv_comp
= instr
->src
[i
].src
.ssa
->num_components
;
4856 case nir_tex_src_ddy
:
4857 ddy
= get_src(ctx
, instr
->src
[i
].src
);
4859 case nir_tex_src_texture_offset
:
4860 case nir_tex_src_sampler_offset
:
4861 case nir_tex_src_plane
:
4867 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
4868 result
= get_buffer_size(ctx
, res_ptr
, true);
4872 if (instr
->op
== nir_texop_texture_samples
) {
4873 LLVMValueRef res
, samples
, is_msaa
;
4874 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->ac
.v8i32
, "");
4875 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
4876 LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
4877 is_msaa
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4878 LLVMConstInt(ctx
->ac
.i32
, 28, false), "");
4879 is_msaa
= LLVMBuildAnd(ctx
->ac
.builder
, is_msaa
,
4880 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4881 is_msaa
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, is_msaa
,
4882 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4884 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4885 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
4886 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
4887 LLVMConstInt(ctx
->ac
.i32
, 0xf, false), "");
4888 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->ac
.i32_1
,
4890 samples
= LLVMBuildSelect(ctx
->ac
.builder
, is_msaa
, samples
,
4897 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4898 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, coord
, chan
);
4900 if (offsets
&& instr
->op
!= nir_texop_txf
) {
4901 LLVMValueRef offset
[3], pack
;
4902 for (chan
= 0; chan
< 3; ++chan
)
4903 offset
[chan
] = ctx
->ac
.i32_0
;
4906 for (chan
= 0; chan
< ac_get_llvm_num_components(offsets
); chan
++) {
4907 offset
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, offsets
, chan
);
4908 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
4909 LLVMConstInt(ctx
->ac
.i32
, 0x3f, false), "");
4911 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
4912 LLVMConstInt(ctx
->ac
.i32
, chan
* 8, false), "");
4914 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
4915 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
4916 address
[count
++] = pack
;
4919 /* pack LOD bias value */
4920 if (instr
->op
== nir_texop_txb
&& bias
) {
4921 address
[count
++] = bias
;
4924 /* Pack depth comparison value */
4925 if (instr
->is_shadow
&& comparator
) {
4926 LLVMValueRef z
= ac_to_float(&ctx
->ac
,
4927 ac_llvm_extract_elem(&ctx
->ac
, comparator
, 0));
4929 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4930 * so the depth comparison value isn't clamped for Z16 and
4931 * Z24 anymore. Do it manually here.
4933 * It's unnecessary if the original texture format was
4934 * Z32_FLOAT, but we don't know that here.
4936 if (ctx
->ac
.chip_class
== VI
&& ctx
->abi
->clamp_shadow_reference
)
4937 z
= ac_build_clamp(&ctx
->ac
, z
);
4939 address
[count
++] = z
;
4942 /* pack derivatives */
4944 int num_src_deriv_channels
, num_dest_deriv_channels
;
4945 switch (instr
->sampler_dim
) {
4946 case GLSL_SAMPLER_DIM_3D
:
4947 case GLSL_SAMPLER_DIM_CUBE
:
4949 num_src_deriv_channels
= 3;
4950 num_dest_deriv_channels
= 3;
4952 case GLSL_SAMPLER_DIM_2D
:
4954 num_src_deriv_channels
= 2;
4955 num_dest_deriv_channels
= 2;
4958 case GLSL_SAMPLER_DIM_1D
:
4959 num_src_deriv_channels
= 1;
4960 if (ctx
->ac
.chip_class
>= GFX9
) {
4961 num_dest_deriv_channels
= 2;
4964 num_dest_deriv_channels
= 1;
4970 for (unsigned i
= 0; i
< num_src_deriv_channels
; i
++) {
4971 derivs
[i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddx
, i
));
4972 derivs
[num_dest_deriv_channels
+ i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddy
, i
));
4974 for (unsigned i
= num_src_deriv_channels
; i
< num_dest_deriv_channels
; i
++) {
4975 derivs
[i
] = ctx
->ac
.f32_0
;
4976 derivs
[num_dest_deriv_channels
+ i
] = ctx
->ac
.f32_0
;
4980 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& coord
) {
4981 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4982 coords
[chan
] = ac_to_float(&ctx
->ac
, coords
[chan
]);
4983 if (instr
->coord_components
== 3)
4984 coords
[3] = LLVMGetUndef(ctx
->ac
.f32
);
4985 ac_prepare_cube_coords(&ctx
->ac
,
4986 instr
->op
== nir_texop_txd
, instr
->is_array
,
4987 instr
->op
== nir_texop_lod
, coords
, derivs
);
4993 for (unsigned i
= 0; i
< num_deriv_comp
* 2; i
++)
4994 address
[count
++] = derivs
[i
];
4997 /* Pack texture coordinates */
4999 address
[count
++] = coords
[0];
5000 if (instr
->coord_components
> 1) {
5001 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& instr
->is_array
&& instr
->op
!= nir_texop_txf
) {
5002 coords
[1] = apply_round_slice(&ctx
->ac
, coords
[1]);
5004 address
[count
++] = coords
[1];
5006 if (instr
->coord_components
> 2) {
5007 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
5008 if (instr
->sampler_dim
!= GLSL_SAMPLER_DIM_3D
&&
5009 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_CUBE
&&
5010 instr
->op
!= nir_texop_txf
) {
5011 coords
[2] = apply_round_slice(&ctx
->ac
, coords
[2]);
5013 address
[count
++] = coords
[2];
5016 if (ctx
->ac
.chip_class
>= GFX9
) {
5017 LLVMValueRef filler
;
5018 if (instr
->op
== nir_texop_txf
)
5019 filler
= ctx
->ac
.i32_0
;
5021 filler
= LLVMConstReal(ctx
->ac
.f32
, 0.5);
5023 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
) {
5024 /* No nir_texop_lod, because it does not take a slice
5025 * even with array textures. */
5026 if (instr
->is_array
&& instr
->op
!= nir_texop_lod
) {
5027 address
[count
] = address
[count
- 1];
5028 address
[count
- 1] = filler
;
5031 address
[count
++] = filler
;
5037 if (lod
&& ((instr
->op
== nir_texop_txl
&& !lod_is_zero
) ||
5038 instr
->op
== nir_texop_txf
)) {
5039 address
[count
++] = lod
;
5040 } else if (instr
->op
== nir_texop_txf_ms
&& sample_index
) {
5041 address
[count
++] = sample_index
;
5042 } else if(instr
->op
== nir_texop_txs
) {
5045 address
[count
++] = lod
;
5047 address
[count
++] = ctx
->ac
.i32_0
;
5050 for (chan
= 0; chan
< count
; chan
++) {
5051 address
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
,
5052 address
[chan
], ctx
->ac
.i32
, "");
5055 if (instr
->op
== nir_texop_samples_identical
) {
5056 LLVMValueRef txf_address
[4];
5057 struct ac_image_args txf_args
= { 0 };
5058 unsigned txf_count
= count
;
5059 memcpy(txf_address
, address
, sizeof(txf_address
));
5061 if (!instr
->is_array
)
5062 txf_address
[2] = ctx
->ac
.i32_0
;
5063 txf_address
[3] = ctx
->ac
.i32_0
;
5065 set_tex_fetch_args(&ctx
->ac
, &txf_args
, instr
, nir_texop_txf
,
5067 txf_address
, txf_count
, 0xf);
5069 result
= build_tex_intrinsic(ctx
, instr
, false, &txf_args
);
5071 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
5072 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, result
, ctx
->ac
.i32_0
);
5076 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
&&
5077 instr
->op
!= nir_texop_txs
) {
5078 unsigned sample_chan
= instr
->is_array
? 3 : 2;
5079 address
[sample_chan
] = adjust_sample_index_using_fmask(&ctx
->ac
,
5082 instr
->is_array
? address
[2] : NULL
,
5083 address
[sample_chan
],
5087 if (offsets
&& instr
->op
== nir_texop_txf
) {
5088 nir_const_value
*const_offset
=
5089 nir_src_as_const_value(instr
->src
[const_src
].src
);
5090 int num_offsets
= instr
->src
[const_src
].src
.ssa
->num_components
;
5091 assert(const_offset
);
5092 num_offsets
= MIN2(num_offsets
, instr
->coord_components
);
5093 if (num_offsets
> 2)
5094 address
[2] = LLVMBuildAdd(ctx
->ac
.builder
,
5095 address
[2], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[2], false), "");
5096 if (num_offsets
> 1)
5097 address
[1] = LLVMBuildAdd(ctx
->ac
.builder
,
5098 address
[1], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[1], false), "");
5099 address
[0] = LLVMBuildAdd(ctx
->ac
.builder
,
5100 address
[0], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[0], false), "");
5104 /* TODO TG4 support */
5105 if (instr
->op
== nir_texop_tg4
) {
5106 if (instr
->is_shadow
)
5109 dmask
= 1 << instr
->component
;
5111 set_tex_fetch_args(&ctx
->ac
, &args
, instr
, instr
->op
,
5112 res_ptr
, samp_ptr
, address
, count
, dmask
);
5114 result
= build_tex_intrinsic(ctx
, instr
, lod_is_zero
, &args
);
5116 if (instr
->op
== nir_texop_query_levels
)
5117 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
5118 else if (instr
->is_shadow
&& instr
->is_new_style_shadow
&&
5119 instr
->op
!= nir_texop_txs
&& instr
->op
!= nir_texop_lod
&&
5120 instr
->op
!= nir_texop_tg4
)
5121 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
5122 else if (instr
->op
== nir_texop_txs
&&
5123 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
5125 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
5126 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
5127 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
5128 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
5129 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, z
, two
, "");
5130 } else if (ctx
->ac
.chip_class
>= GFX9
&&
5131 instr
->op
== nir_texop_txs
&&
5132 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
5134 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
5135 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
5136 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, layers
,
5138 } else if (instr
->dest
.ssa
.num_components
!= 4)
5139 result
= trim_vector(&ctx
->ac
, result
, instr
->dest
.ssa
.num_components
);
5143 assert(instr
->dest
.is_ssa
);
5144 result
= ac_to_integer(&ctx
->ac
, result
);
5145 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
5150 static void visit_phi(struct ac_nir_context
*ctx
, nir_phi_instr
*instr
)
5152 LLVMTypeRef type
= get_def_type(ctx
, &instr
->dest
.ssa
);
5153 LLVMValueRef result
= LLVMBuildPhi(ctx
->ac
.builder
, type
, "");
5155 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
5156 _mesa_hash_table_insert(ctx
->phis
, instr
, result
);
5159 static void visit_post_phi(struct ac_nir_context
*ctx
,
5160 nir_phi_instr
*instr
,
5161 LLVMValueRef llvm_phi
)
5163 nir_foreach_phi_src(src
, instr
) {
5164 LLVMBasicBlockRef block
= get_block(ctx
, src
->pred
);
5165 LLVMValueRef llvm_src
= get_src(ctx
, src
->src
);
5167 LLVMAddIncoming(llvm_phi
, &llvm_src
, &block
, 1);
5171 static void phi_post_pass(struct ac_nir_context
*ctx
)
5173 struct hash_entry
*entry
;
5174 hash_table_foreach(ctx
->phis
, entry
) {
5175 visit_post_phi(ctx
, (nir_phi_instr
*)entry
->key
,
5176 (LLVMValueRef
)entry
->data
);
5181 static void visit_ssa_undef(struct ac_nir_context
*ctx
,
5182 const nir_ssa_undef_instr
*instr
)
5184 unsigned num_components
= instr
->def
.num_components
;
5185 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
5188 if (num_components
== 1)
5189 undef
= LLVMGetUndef(type
);
5191 undef
= LLVMGetUndef(LLVMVectorType(type
, num_components
));
5193 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, undef
);
5196 static void visit_jump(struct ac_nir_context
*ctx
,
5197 const nir_jump_instr
*instr
)
5199 switch (instr
->type
) {
5200 case nir_jump_break
:
5201 LLVMBuildBr(ctx
->ac
.builder
, ctx
->break_block
);
5202 LLVMClearInsertionPosition(ctx
->ac
.builder
);
5204 case nir_jump_continue
:
5205 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5206 LLVMClearInsertionPosition(ctx
->ac
.builder
);
5209 fprintf(stderr
, "Unknown NIR jump instr: ");
5210 nir_print_instr(&instr
->instr
, stderr
);
5211 fprintf(stderr
, "\n");
5216 static void visit_cf_list(struct ac_nir_context
*ctx
,
5217 struct exec_list
*list
);
5219 static void visit_block(struct ac_nir_context
*ctx
, nir_block
*block
)
5221 LLVMBasicBlockRef llvm_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
5222 nir_foreach_instr(instr
, block
)
5224 switch (instr
->type
) {
5225 case nir_instr_type_alu
:
5226 visit_alu(ctx
, nir_instr_as_alu(instr
));
5228 case nir_instr_type_load_const
:
5229 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
5231 case nir_instr_type_intrinsic
:
5232 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
5234 case nir_instr_type_tex
:
5235 visit_tex(ctx
, nir_instr_as_tex(instr
));
5237 case nir_instr_type_phi
:
5238 visit_phi(ctx
, nir_instr_as_phi(instr
));
5240 case nir_instr_type_ssa_undef
:
5241 visit_ssa_undef(ctx
, nir_instr_as_ssa_undef(instr
));
5243 case nir_instr_type_jump
:
5244 visit_jump(ctx
, nir_instr_as_jump(instr
));
5247 fprintf(stderr
, "Unknown NIR instr type: ");
5248 nir_print_instr(instr
, stderr
);
5249 fprintf(stderr
, "\n");
5254 _mesa_hash_table_insert(ctx
->defs
, block
, llvm_block
);
5257 static void visit_if(struct ac_nir_context
*ctx
, nir_if
*if_stmt
)
5259 LLVMValueRef value
= get_src(ctx
, if_stmt
->condition
);
5261 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
5262 LLVMBasicBlockRef merge_block
=
5263 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5264 LLVMBasicBlockRef if_block
=
5265 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5266 LLVMBasicBlockRef else_block
= merge_block
;
5267 if (!exec_list_is_empty(&if_stmt
->else_list
))
5268 else_block
= LLVMAppendBasicBlockInContext(
5269 ctx
->ac
.context
, fn
, "");
5271 LLVMValueRef cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
, value
,
5273 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, if_block
, else_block
);
5275 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, if_block
);
5276 visit_cf_list(ctx
, &if_stmt
->then_list
);
5277 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5278 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
5280 if (!exec_list_is_empty(&if_stmt
->else_list
)) {
5281 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, else_block
);
5282 visit_cf_list(ctx
, &if_stmt
->else_list
);
5283 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5284 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
5287 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
5290 static void visit_loop(struct ac_nir_context
*ctx
, nir_loop
*loop
)
5292 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
5293 LLVMBasicBlockRef continue_parent
= ctx
->continue_block
;
5294 LLVMBasicBlockRef break_parent
= ctx
->break_block
;
5296 ctx
->continue_block
=
5297 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5299 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5301 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5302 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->continue_block
);
5303 visit_cf_list(ctx
, &loop
->body
);
5305 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5306 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5307 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->break_block
);
5309 ctx
->continue_block
= continue_parent
;
5310 ctx
->break_block
= break_parent
;
5313 static void visit_cf_list(struct ac_nir_context
*ctx
,
5314 struct exec_list
*list
)
5316 foreach_list_typed(nir_cf_node
, node
, node
, list
)
5318 switch (node
->type
) {
5319 case nir_cf_node_block
:
5320 visit_block(ctx
, nir_cf_node_as_block(node
));
5323 case nir_cf_node_if
:
5324 visit_if(ctx
, nir_cf_node_as_if(node
));
5327 case nir_cf_node_loop
:
5328 visit_loop(ctx
, nir_cf_node_as_loop(node
));
5338 handle_vs_input_decl(struct nir_to_llvm_context
*ctx
,
5339 struct nir_variable
*variable
)
5341 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
5342 LLVMValueRef t_offset
;
5343 LLVMValueRef t_list
;
5345 LLVMValueRef buffer_index
;
5346 int index
= variable
->data
.location
- VERT_ATTRIB_GENERIC0
;
5347 int idx
= variable
->data
.location
;
5348 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
5350 variable
->data
.driver_location
= idx
* 4;
5352 for (unsigned i
= 0; i
< attrib_count
; ++i
, ++idx
) {
5353 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << (index
+ i
))) {
5354 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.instance_id
,
5355 ctx
->abi
.start_instance
, "");
5356 if (ctx
->options
->key
.vs
.as_ls
) {
5357 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5358 MAX2(2, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5360 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5361 MAX2(1, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5364 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.vertex_id
,
5365 ctx
->abi
.base_vertex
, "");
5366 t_offset
= LLVMConstInt(ctx
->ac
.i32
, index
+ i
, false);
5368 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
5370 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
5375 for (unsigned chan
= 0; chan
< 4; chan
++) {
5376 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5377 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
, chan
)] =
5378 ac_to_integer(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
,
5379 input
, llvm_chan
, ""));
5384 static void interp_fs_input(struct nir_to_llvm_context
*ctx
,
5386 LLVMValueRef interp_param
,
5387 LLVMValueRef prim_mask
,
5388 LLVMValueRef result
[4])
5390 LLVMValueRef attr_number
;
5393 bool interp
= interp_param
!= NULL
;
5395 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
5397 /* fs.constant returns the param from the middle vertex, so it's not
5398 * really useful for flat shading. It's meant to be used for custom
5399 * interpolation (but the intrinsic can't fetch from the other two
5402 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5403 * to do the right thing. The only reason we use fs.constant is that
5404 * fs.interp cannot be used on integers, because they can be equal
5408 interp_param
= LLVMBuildBitCast(ctx
->builder
, interp_param
,
5411 i
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
5413 j
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
5417 for (chan
= 0; chan
< 4; chan
++) {
5418 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5421 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
5426 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
5427 LLVMConstInt(ctx
->ac
.i32
, 2, false),
5436 handle_fs_input_decl(struct nir_to_llvm_context
*ctx
,
5437 struct nir_variable
*variable
)
5439 int idx
= variable
->data
.location
;
5440 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5441 LLVMValueRef interp
;
5443 variable
->data
.driver_location
= idx
* 4;
5444 ctx
->input_mask
|= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
5446 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
5447 unsigned interp_type
;
5448 if (variable
->data
.sample
) {
5449 interp_type
= INTERP_SAMPLE
;
5450 ctx
->shader_info
->info
.ps
.force_persample
= true;
5451 } else if (variable
->data
.centroid
)
5452 interp_type
= INTERP_CENTROID
;
5454 interp_type
= INTERP_CENTER
;
5456 interp
= lookup_interp_param(ctx
, variable
->data
.interpolation
, interp_type
);
5460 for (unsigned i
= 0; i
< attrib_count
; ++i
)
5461 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
5466 handle_vs_inputs(struct nir_to_llvm_context
*ctx
,
5467 struct nir_shader
*nir
) {
5468 nir_foreach_variable(variable
, &nir
->inputs
)
5469 handle_vs_input_decl(ctx
, variable
);
5473 prepare_interp_optimize(struct nir_to_llvm_context
*ctx
,
5474 struct nir_shader
*nir
)
5476 if (!ctx
->options
->key
.fs
.multisample
)
5479 bool uses_center
= false;
5480 bool uses_centroid
= false;
5481 nir_foreach_variable(variable
, &nir
->inputs
) {
5482 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
5483 variable
->data
.sample
)
5486 if (variable
->data
.centroid
)
5487 uses_centroid
= true;
5492 if (uses_center
&& uses_centroid
) {
5493 LLVMValueRef sel
= LLVMBuildICmp(ctx
->builder
, LLVMIntSLT
, ctx
->prim_mask
, ctx
->ac
.i32_0
, "");
5494 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
5495 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
5500 handle_fs_inputs(struct nir_to_llvm_context
*ctx
,
5501 struct nir_shader
*nir
)
5503 prepare_interp_optimize(ctx
, nir
);
5505 nir_foreach_variable(variable
, &nir
->inputs
)
5506 handle_fs_input_decl(ctx
, variable
);
5510 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
5511 ctx
->shader_info
->info
.needs_multiview_view_index
)
5512 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
5514 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
5515 LLVMValueRef interp_param
;
5516 LLVMValueRef
*inputs
= ctx
->inputs
+radeon_llvm_reg_index_soa(i
, 0);
5518 if (!(ctx
->input_mask
& (1ull << i
)))
5521 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
5522 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
5523 interp_param
= *inputs
;
5524 interp_fs_input(ctx
, index
, interp_param
, ctx
->prim_mask
,
5528 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
5530 } else if (i
== VARYING_SLOT_POS
) {
5531 for(int i
= 0; i
< 3; ++i
)
5532 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
5534 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
5535 ctx
->abi
.frag_pos
[3]);
5538 ctx
->shader_info
->fs
.num_interp
= index
;
5539 if (ctx
->input_mask
& (1 << VARYING_SLOT_PNTC
))
5540 ctx
->shader_info
->fs
.has_pcoord
= true;
5541 if (ctx
->input_mask
& (1 << VARYING_SLOT_PRIMITIVE_ID
))
5542 ctx
->shader_info
->fs
.prim_id_input
= true;
5543 if (ctx
->input_mask
& (1 << VARYING_SLOT_LAYER
))
5544 ctx
->shader_info
->fs
.layer_input
= true;
5545 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
5547 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
5548 ctx
->view_index
= ctx
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5552 ac_build_alloca(struct ac_llvm_context
*ac
,
5556 LLVMBuilderRef builder
= ac
->builder
;
5557 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(builder
);
5558 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
5559 LLVMBasicBlockRef first_block
= LLVMGetEntryBasicBlock(function
);
5560 LLVMValueRef first_instr
= LLVMGetFirstInstruction(first_block
);
5561 LLVMBuilderRef first_builder
= LLVMCreateBuilderInContext(ac
->context
);
5565 LLVMPositionBuilderBefore(first_builder
, first_instr
);
5567 LLVMPositionBuilderAtEnd(first_builder
, first_block
);
5570 res
= LLVMBuildAlloca(first_builder
, type
, name
);
5571 LLVMBuildStore(builder
, LLVMConstNull(type
), res
);
5573 LLVMDisposeBuilder(first_builder
);
5578 static LLVMValueRef
si_build_alloca_undef(struct ac_llvm_context
*ac
,
5582 LLVMValueRef ptr
= ac_build_alloca(ac
, type
, name
);
5583 LLVMBuildStore(ac
->builder
, LLVMGetUndef(type
), ptr
);
5588 scan_shader_output_decl(struct nir_to_llvm_context
*ctx
,
5589 struct nir_variable
*variable
,
5590 struct nir_shader
*shader
,
5591 gl_shader_stage stage
)
5593 int idx
= variable
->data
.location
+ variable
->data
.index
;
5594 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5595 uint64_t mask_attribs
;
5597 variable
->data
.driver_location
= idx
* 4;
5599 /* tess ctrl has it's own load/store paths for outputs */
5600 if (stage
== MESA_SHADER_TESS_CTRL
)
5603 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
5604 if (stage
== MESA_SHADER_VERTEX
||
5605 stage
== MESA_SHADER_TESS_EVAL
||
5606 stage
== MESA_SHADER_GEOMETRY
) {
5607 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5608 int length
= shader
->info
.clip_distance_array_size
+
5609 shader
->info
.cull_distance_array_size
;
5610 if (stage
== MESA_SHADER_VERTEX
) {
5611 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5612 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5614 if (stage
== MESA_SHADER_TESS_EVAL
) {
5615 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5616 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5623 mask_attribs
= 1ull << idx
;
5627 ctx
->output_mask
|= mask_attribs
;
5631 handle_shader_output_decl(struct ac_nir_context
*ctx
,
5632 struct nir_shader
*nir
,
5633 struct nir_variable
*variable
)
5635 unsigned output_loc
= variable
->data
.driver_location
/ 4;
5636 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5638 /* tess ctrl has it's own load/store paths for outputs */
5639 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
5642 if (ctx
->stage
== MESA_SHADER_VERTEX
||
5643 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
5644 ctx
->stage
== MESA_SHADER_GEOMETRY
) {
5645 int idx
= variable
->data
.location
+ variable
->data
.index
;
5646 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5647 int length
= nir
->info
.clip_distance_array_size
+
5648 nir
->info
.cull_distance_array_size
;
5657 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
5658 for (unsigned chan
= 0; chan
< 4; chan
++) {
5659 ctx
->outputs
[radeon_llvm_reg_index_soa(output_loc
+ i
, chan
)] =
5660 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5666 glsl_base_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5667 enum glsl_base_type type
)
5671 case GLSL_TYPE_UINT
:
5672 case GLSL_TYPE_BOOL
:
5673 case GLSL_TYPE_SUBROUTINE
:
5675 case GLSL_TYPE_FLOAT
: /* TODO handle mediump */
5677 case GLSL_TYPE_INT64
:
5678 case GLSL_TYPE_UINT64
:
5680 case GLSL_TYPE_DOUBLE
:
5683 unreachable("unknown GLSL type");
5688 glsl_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5689 const struct glsl_type
*type
)
5691 if (glsl_type_is_scalar(type
)) {
5692 return glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
));
5695 if (glsl_type_is_vector(type
)) {
5696 return LLVMVectorType(
5697 glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
)),
5698 glsl_get_vector_elements(type
));
5701 if (glsl_type_is_matrix(type
)) {
5702 return LLVMArrayType(
5703 glsl_to_llvm_type(ctx
, glsl_get_column_type(type
)),
5704 glsl_get_matrix_columns(type
));
5707 if (glsl_type_is_array(type
)) {
5708 return LLVMArrayType(
5709 glsl_to_llvm_type(ctx
, glsl_get_array_element(type
)),
5710 glsl_get_length(type
));
5713 assert(glsl_type_is_struct(type
));
5715 LLVMTypeRef member_types
[glsl_get_length(type
)];
5717 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
5719 glsl_to_llvm_type(ctx
,
5720 glsl_get_struct_field(type
, i
));
5723 return LLVMStructTypeInContext(ctx
->context
, member_types
,
5724 glsl_get_length(type
), false);
5728 setup_locals(struct ac_nir_context
*ctx
,
5729 struct nir_function
*func
)
5732 ctx
->num_locals
= 0;
5733 nir_foreach_variable(variable
, &func
->impl
->locals
) {
5734 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5735 variable
->data
.driver_location
= ctx
->num_locals
* 4;
5736 variable
->data
.location_frac
= 0;
5737 ctx
->num_locals
+= attrib_count
;
5739 ctx
->locals
= malloc(4 * ctx
->num_locals
* sizeof(LLVMValueRef
));
5743 for (i
= 0; i
< ctx
->num_locals
; i
++) {
5744 for (j
= 0; j
< 4; j
++) {
5745 ctx
->locals
[i
* 4 + j
] =
5746 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "temp");
5752 setup_shared(struct ac_nir_context
*ctx
,
5753 struct nir_shader
*nir
)
5755 nir_foreach_variable(variable
, &nir
->shared
) {
5756 LLVMValueRef shared
=
5757 LLVMAddGlobalInAddressSpace(
5758 ctx
->ac
.module
, glsl_to_llvm_type(ctx
->nctx
, variable
->type
),
5759 variable
->name
? variable
->name
: "",
5760 AC_LOCAL_ADDR_SPACE
);
5761 _mesa_hash_table_insert(ctx
->vars
, variable
, shared
);
5766 emit_float_saturate(struct ac_llvm_context
*ctx
, LLVMValueRef v
, float lo
, float hi
)
5768 v
= ac_to_float(ctx
, v
);
5769 v
= emit_intrin_2f_param(ctx
, "llvm.maxnum", ctx
->f32
, v
, LLVMConstReal(ctx
->f32
, lo
));
5770 return emit_intrin_2f_param(ctx
, "llvm.minnum", ctx
->f32
, v
, LLVMConstReal(ctx
->f32
, hi
));
5774 static LLVMValueRef
emit_pack_int16(struct nir_to_llvm_context
*ctx
,
5775 LLVMValueRef src0
, LLVMValueRef src1
)
5777 LLVMValueRef const16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
5778 LLVMValueRef comp
[2];
5780 comp
[0] = LLVMBuildAnd(ctx
->builder
, src0
, LLVMConstInt(ctx
->ac
.i32
, 65535, 0), "");
5781 comp
[1] = LLVMBuildAnd(ctx
->builder
, src1
, LLVMConstInt(ctx
->ac
.i32
, 65535, 0), "");
5782 comp
[1] = LLVMBuildShl(ctx
->builder
, comp
[1], const16
, "");
5783 return LLVMBuildOr(ctx
->builder
, comp
[0], comp
[1], "");
5786 /* Initialize arguments for the shader export intrinsic */
5788 si_llvm_init_export_args(struct nir_to_llvm_context
*ctx
,
5789 LLVMValueRef
*values
,
5791 struct ac_export_args
*args
)
5793 /* Default is 0xf. Adjusted below depending on the format. */
5794 args
->enabled_channels
= 0xf;
5796 /* Specify whether the EXEC mask represents the valid mask */
5797 args
->valid_mask
= 0;
5799 /* Specify whether this is the last export */
5802 /* Specify the target we are exporting */
5803 args
->target
= target
;
5805 args
->compr
= false;
5806 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
5807 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
5808 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
5809 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
5814 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& target
>= V_008DFC_SQ_EXP_MRT
) {
5815 LLVMValueRef val
[4];
5816 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
5817 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
5818 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
5819 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
5821 switch(col_format
) {
5822 case V_028714_SPI_SHADER_ZERO
:
5823 args
->enabled_channels
= 0; /* writemask */
5824 args
->target
= V_008DFC_SQ_EXP_NULL
;
5827 case V_028714_SPI_SHADER_32_R
:
5828 args
->enabled_channels
= 1;
5829 args
->out
[0] = values
[0];
5832 case V_028714_SPI_SHADER_32_GR
:
5833 args
->enabled_channels
= 0x3;
5834 args
->out
[0] = values
[0];
5835 args
->out
[1] = values
[1];
5838 case V_028714_SPI_SHADER_32_AR
:
5839 args
->enabled_channels
= 0x9;
5840 args
->out
[0] = values
[0];
5841 args
->out
[3] = values
[3];
5844 case V_028714_SPI_SHADER_FP16_ABGR
:
5847 for (unsigned chan
= 0; chan
< 2; chan
++) {
5848 LLVMValueRef pack_args
[2] = {
5850 values
[2 * chan
+ 1]
5852 LLVMValueRef packed
;
5854 packed
= ac_build_cvt_pkrtz_f16(&ctx
->ac
, pack_args
);
5855 args
->out
[chan
] = packed
;
5859 case V_028714_SPI_SHADER_UNORM16_ABGR
:
5860 for (unsigned chan
= 0; chan
< 4; chan
++) {
5861 val
[chan
] = ac_build_clamp(&ctx
->ac
, values
[chan
]);
5862 val
[chan
] = LLVMBuildFMul(ctx
->builder
, val
[chan
],
5863 LLVMConstReal(ctx
->ac
.f32
, 65535), "");
5864 val
[chan
] = LLVMBuildFAdd(ctx
->builder
, val
[chan
],
5865 LLVMConstReal(ctx
->ac
.f32
, 0.5), "");
5866 val
[chan
] = LLVMBuildFPToUI(ctx
->builder
, val
[chan
],
5871 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5872 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5875 case V_028714_SPI_SHADER_SNORM16_ABGR
:
5876 for (unsigned chan
= 0; chan
< 4; chan
++) {
5877 val
[chan
] = emit_float_saturate(&ctx
->ac
, values
[chan
], -1, 1);
5878 val
[chan
] = LLVMBuildFMul(ctx
->builder
, val
[chan
],
5879 LLVMConstReal(ctx
->ac
.f32
, 32767), "");
5881 /* If positive, add 0.5, else add -0.5. */
5882 val
[chan
] = LLVMBuildFAdd(ctx
->builder
, val
[chan
],
5883 LLVMBuildSelect(ctx
->builder
,
5884 LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
,
5885 val
[chan
], ctx
->ac
.f32_0
, ""),
5886 LLVMConstReal(ctx
->ac
.f32
, 0.5),
5887 LLVMConstReal(ctx
->ac
.f32
, -0.5), ""), "");
5888 val
[chan
] = LLVMBuildFPToSI(ctx
->builder
, val
[chan
], ctx
->ac
.i32
, "");
5892 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5893 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5896 case V_028714_SPI_SHADER_UINT16_ABGR
: {
5897 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5898 is_int8
? 255 : is_int10
? 1023 : 65535, 0);
5899 LLVMValueRef max_alpha
= !is_int10
? max_rgb
: LLVMConstInt(ctx
->ac
.i32
, 3, 0);
5901 for (unsigned chan
= 0; chan
< 4; chan
++) {
5902 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
5903 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntULT
, val
[chan
], chan
== 3 ? max_alpha
: max_rgb
);
5907 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5908 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5912 case V_028714_SPI_SHADER_SINT16_ABGR
: {
5913 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5914 is_int8
? 127 : is_int10
? 511 : 32767, 0);
5915 LLVMValueRef min_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5916 is_int8
? -128 : is_int10
? -512 : -32768, 0);
5917 LLVMValueRef max_alpha
= !is_int10
? max_rgb
: ctx
->ac
.i32_1
;
5918 LLVMValueRef min_alpha
= !is_int10
? min_rgb
: LLVMConstInt(ctx
->ac
.i32
, -2, 0);
5921 for (unsigned chan
= 0; chan
< 4; chan
++) {
5922 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
5923 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, val
[chan
], chan
== 3 ? max_alpha
: max_rgb
);
5924 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, val
[chan
], chan
== 3 ? min_alpha
: min_rgb
);
5928 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5929 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5934 case V_028714_SPI_SHADER_32_ABGR
:
5935 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5939 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5941 for (unsigned i
= 0; i
< 4; ++i
)
5942 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
5946 handle_vs_outputs_post(struct nir_to_llvm_context
*ctx
,
5947 bool export_prim_id
,
5948 struct ac_vs_output_info
*outinfo
)
5950 uint32_t param_count
= 0;
5952 unsigned pos_idx
, num_pos_exports
= 0;
5953 struct ac_export_args args
, pos_args
[4] = {};
5954 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
5957 if (ctx
->options
->key
.has_multiview_view_index
) {
5958 LLVMValueRef
* tmp_out
= &ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5960 for(unsigned i
= 0; i
< 4; ++i
)
5961 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
5962 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5965 LLVMBuildStore(ctx
->builder
, ac_to_float(&ctx
->ac
, ctx
->view_index
), *tmp_out
);
5966 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
5969 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
5970 sizeof(outinfo
->vs_output_param_offset
));
5972 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
5973 LLVMValueRef slots
[8];
5976 if (outinfo
->cull_dist_mask
)
5977 outinfo
->cull_dist_mask
<<= ctx
->num_output_clips
;
5979 i
= VARYING_SLOT_CLIP_DIST0
;
5980 for (j
= 0; j
< ctx
->num_output_clips
+ ctx
->num_output_culls
; j
++)
5981 slots
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5982 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
5984 for (i
= ctx
->num_output_clips
+ ctx
->num_output_culls
; i
< 8; i
++)
5985 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
5987 if (ctx
->num_output_clips
+ ctx
->num_output_culls
> 4) {
5988 target
= V_008DFC_SQ_EXP_POS
+ 3;
5989 si_llvm_init_export_args(ctx
, &slots
[4], target
, &args
);
5990 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5991 &args
, sizeof(args
));
5994 target
= V_008DFC_SQ_EXP_POS
+ 2;
5995 si_llvm_init_export_args(ctx
, &slots
[0], target
, &args
);
5996 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5997 &args
, sizeof(args
));
6001 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
6002 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
6003 for (unsigned j
= 0; j
< 4; j
++)
6004 pos_values
[j
] = LLVMBuildLoad(ctx
->builder
,
6005 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_POS
, j
)], "");
6007 si_llvm_init_export_args(ctx
, pos_values
, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
6009 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
6010 outinfo
->writes_pointsize
= true;
6011 psize_value
= LLVMBuildLoad(ctx
->builder
,
6012 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ
, 0)], "");
6015 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
6016 outinfo
->writes_layer
= true;
6017 layer_value
= LLVMBuildLoad(ctx
->builder
,
6018 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)], "");
6021 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
6022 outinfo
->writes_viewport_index
= true;
6023 viewport_index_value
= LLVMBuildLoad(ctx
->builder
,
6024 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT
, 0)], "");
6027 if (outinfo
->writes_pointsize
||
6028 outinfo
->writes_layer
||
6029 outinfo
->writes_viewport_index
) {
6030 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
6031 (outinfo
->writes_layer
== true ? 4 : 0));
6032 pos_args
[1].valid_mask
= 0;
6033 pos_args
[1].done
= 0;
6034 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
6035 pos_args
[1].compr
= 0;
6036 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
6037 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
6038 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
6039 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
6041 if (outinfo
->writes_pointsize
== true)
6042 pos_args
[1].out
[0] = psize_value
;
6043 if (outinfo
->writes_layer
== true)
6044 pos_args
[1].out
[2] = layer_value
;
6045 if (outinfo
->writes_viewport_index
== true) {
6046 if (ctx
->options
->chip_class
>= GFX9
) {
6047 /* GFX9 has the layer in out.z[10:0] and the viewport
6048 * index in out.z[19:16].
6050 LLVMValueRef v
= viewport_index_value
;
6051 v
= ac_to_integer(&ctx
->ac
, v
);
6052 v
= LLVMBuildShl(ctx
->builder
, v
,
6053 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6055 v
= LLVMBuildOr(ctx
->builder
, v
,
6056 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
6058 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
6059 pos_args
[1].enabled_channels
|= 1 << 2;
6061 pos_args
[1].out
[3] = viewport_index_value
;
6062 pos_args
[1].enabled_channels
|= 1 << 3;
6066 for (i
= 0; i
< 4; i
++) {
6067 if (pos_args
[i
].out
[0])
6072 for (i
= 0; i
< 4; i
++) {
6073 if (!pos_args
[i
].out
[0])
6076 /* Specify the target we are exporting */
6077 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
6078 if (pos_idx
== num_pos_exports
)
6079 pos_args
[i
].done
= 1;
6080 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
6083 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6084 LLVMValueRef values
[4];
6085 if (!(ctx
->output_mask
& (1ull << i
)))
6088 for (unsigned j
= 0; j
< 4; j
++)
6089 values
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6090 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
6092 if (i
== VARYING_SLOT_LAYER
) {
6093 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
6094 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = param_count
;
6096 } else if (i
== VARYING_SLOT_PRIMITIVE_ID
) {
6097 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
6098 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
6100 } else if (i
>= VARYING_SLOT_VAR0
) {
6101 outinfo
->export_mask
|= 1u << (i
- VARYING_SLOT_VAR0
);
6102 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
6103 outinfo
->vs_output_param_offset
[i
] = param_count
;
6108 si_llvm_init_export_args(ctx
, values
, target
, &args
);
6110 if (target
>= V_008DFC_SQ_EXP_POS
&&
6111 target
<= (V_008DFC_SQ_EXP_POS
+ 3)) {
6112 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
6113 &args
, sizeof(args
));
6115 ac_build_export(&ctx
->ac
, &args
);
6119 if (export_prim_id
) {
6120 LLVMValueRef values
[4];
6121 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
6122 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
6125 values
[0] = ctx
->vs_prim_id
;
6126 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
6127 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
6128 for (unsigned j
= 1; j
< 4; j
++)
6129 values
[j
] = ctx
->ac
.f32_0
;
6130 si_llvm_init_export_args(ctx
, values
, target
, &args
);
6131 ac_build_export(&ctx
->ac
, &args
);
6132 outinfo
->export_prim_id
= true;
6135 outinfo
->pos_exports
= num_pos_exports
;
6136 outinfo
->param_exports
= param_count
;
6140 handle_es_outputs_post(struct nir_to_llvm_context
*ctx
,
6141 struct ac_es_output_info
*outinfo
)
6144 uint64_t max_output_written
= 0;
6145 LLVMValueRef lds_base
= NULL
;
6147 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6151 if (!(ctx
->output_mask
& (1ull << i
)))
6154 if (i
== VARYING_SLOT_CLIP_DIST0
)
6155 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6157 param_index
= shader_io_get_unique_index(i
);
6159 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
6162 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
6164 if (ctx
->ac
.chip_class
>= GFX9
) {
6165 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
6166 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
6167 LLVMValueRef wave_idx
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6168 LLVMConstInt(ctx
->ac
.i32
, 24, false),
6169 LLVMConstInt(ctx
->ac
.i32
, 4, false), false);
6170 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
6171 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
6172 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
6173 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
6174 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
6177 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6178 LLVMValueRef dw_addr
;
6179 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
6183 if (!(ctx
->output_mask
& (1ull << i
)))
6186 if (i
== VARYING_SLOT_CLIP_DIST0
)
6187 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6189 param_index
= shader_io_get_unique_index(i
);
6192 dw_addr
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6193 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
6196 for (j
= 0; j
< length
; j
++) {
6197 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], "");
6198 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->ac
.i32
, "");
6200 if (ctx
->ac
.chip_class
>= GFX9
) {
6201 ac_lds_store(&ctx
->ac
, dw_addr
,
6202 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
6203 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6205 ac_build_buffer_store_dword(&ctx
->ac
,
6208 NULL
, ctx
->es2gs_offset
,
6209 (4 * param_index
+ j
) * 4,
6217 handle_ls_outputs_post(struct nir_to_llvm_context
*ctx
)
6219 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
6220 LLVMValueRef vertex_dw_stride
= unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 13, 8);
6221 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->builder
, vertex_id
,
6222 vertex_dw_stride
, "");
6224 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6225 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
6228 if (!(ctx
->output_mask
& (1ull << i
)))
6231 if (i
== VARYING_SLOT_CLIP_DIST0
)
6232 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6233 int param
= shader_io_get_unique_index(i
);
6234 mark_tess_output(ctx
, false, param
);
6236 mark_tess_output(ctx
, false, param
+ 1);
6237 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->builder
, base_dw_addr
,
6238 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
6240 for (unsigned j
= 0; j
< length
; j
++) {
6241 ac_lds_store(&ctx
->ac
, dw_addr
,
6242 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
6243 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6248 struct ac_build_if_state
6250 struct nir_to_llvm_context
*ctx
;
6251 LLVMValueRef condition
;
6252 LLVMBasicBlockRef entry_block
;
6253 LLVMBasicBlockRef true_block
;
6254 LLVMBasicBlockRef false_block
;
6255 LLVMBasicBlockRef merge_block
;
6258 static LLVMBasicBlockRef
6259 ac_build_insert_new_block(struct nir_to_llvm_context
*ctx
, const char *name
)
6261 LLVMBasicBlockRef current_block
;
6262 LLVMBasicBlockRef next_block
;
6263 LLVMBasicBlockRef new_block
;
6265 /* get current basic block */
6266 current_block
= LLVMGetInsertBlock(ctx
->builder
);
6268 /* chqeck if there's another block after this one */
6269 next_block
= LLVMGetNextBasicBlock(current_block
);
6271 /* insert the new block before the next block */
6272 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
6275 /* append new block after current block */
6276 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
6277 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
6283 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
6284 struct nir_to_llvm_context
*ctx
,
6285 LLVMValueRef condition
)
6287 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->builder
);
6289 memset(ifthen
, 0, sizeof *ifthen
);
6291 ifthen
->condition
= condition
;
6292 ifthen
->entry_block
= block
;
6294 /* create endif/merge basic block for the phi functions */
6295 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
6297 /* create/insert true_block before merge_block */
6298 ifthen
->true_block
=
6299 LLVMInsertBasicBlockInContext(ctx
->context
,
6300 ifthen
->merge_block
,
6303 /* successive code goes into the true block */
6304 LLVMPositionBuilderAtEnd(ctx
->builder
, ifthen
->true_block
);
6308 * End a conditional.
6311 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
6313 LLVMBuilderRef builder
= ifthen
->ctx
->builder
;
6315 /* Insert branch to the merge block from current block */
6316 LLVMBuildBr(builder
, ifthen
->merge_block
);
6319 * Now patch in the various branch instructions.
6322 /* Insert the conditional branch instruction at the end of entry_block */
6323 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
6324 if (ifthen
->false_block
) {
6325 /* we have an else clause */
6326 LLVMBuildCondBr(builder
, ifthen
->condition
,
6327 ifthen
->true_block
, ifthen
->false_block
);
6330 /* no else clause */
6331 LLVMBuildCondBr(builder
, ifthen
->condition
,
6332 ifthen
->true_block
, ifthen
->merge_block
);
6335 /* Resume building code at end of the ifthen->merge_block */
6336 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
6340 write_tess_factors(struct nir_to_llvm_context
*ctx
)
6342 unsigned stride
, outer_comps
, inner_comps
;
6343 struct ac_build_if_state if_ctx
, inner_if_ctx
;
6344 LLVMValueRef invocation_id
= unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
6345 LLVMValueRef rel_patch_id
= unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
6346 unsigned tess_inner_index
, tess_outer_index
;
6347 LLVMValueRef lds_base
, lds_inner
, lds_outer
, byteoffset
, buffer
;
6348 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
6350 emit_barrier(&ctx
->ac
, ctx
->stage
);
6352 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
6372 ac_nir_build_if(&if_ctx
, ctx
,
6373 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
6374 invocation_id
, ctx
->ac
.i32_0
, ""));
6376 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6377 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6379 mark_tess_output(ctx
, true, tess_inner_index
);
6380 mark_tess_output(ctx
, true, tess_outer_index
);
6381 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
6382 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6383 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
6384 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6385 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
6387 for (i
= 0; i
< 4; i
++) {
6388 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6389 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6393 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
6394 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
6395 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
6397 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
6399 for (i
= 0; i
< outer_comps
; i
++) {
6401 ac_lds_load(&ctx
->ac
, lds_outer
);
6402 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
6405 for (i
= 0; i
< inner_comps
; i
++) {
6406 inner
[i
] = out
[outer_comps
+i
] =
6407 ac_lds_load(&ctx
->ac
, lds_inner
);
6408 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_inner
,
6413 /* Convert the outputs to vectors for stores. */
6414 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
6418 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
6421 buffer
= ctx
->hs_ring_tess_factor
;
6422 tf_base
= ctx
->tess_factor_offset
;
6423 byteoffset
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
6424 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
6425 unsigned tf_offset
= 0;
6427 if (ctx
->options
->chip_class
<= VI
) {
6428 ac_nir_build_if(&inner_if_ctx
, ctx
,
6429 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
6430 rel_patch_id
, ctx
->ac
.i32_0
, ""));
6432 /* Store the dynamic HS control word. */
6433 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
6434 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
6435 1, ctx
->ac
.i32_0
, tf_base
,
6436 0, 1, 0, true, false);
6439 ac_nir_build_endif(&inner_if_ctx
);
6442 /* Store the tessellation factors. */
6443 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
6444 MIN2(stride
, 4), byteoffset
, tf_base
,
6445 tf_offset
, 1, 0, true, false);
6447 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
6448 stride
- 4, byteoffset
, tf_base
,
6449 16 + tf_offset
, 1, 0, true, false);
6451 //store to offchip for TES to read - only if TES reads them
6452 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
6453 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
6454 LLVMValueRef tf_inner_offset
;
6455 unsigned param_outer
, param_inner
;
6457 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6458 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6459 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
6461 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
6462 util_next_power_of_two(outer_comps
));
6464 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
6465 outer_comps
, tf_outer_offset
,
6466 ctx
->oc_lds
, 0, 1, 0, true, false);
6468 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6469 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6470 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
6472 inner_vec
= inner_comps
== 1 ? inner
[0] :
6473 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
6474 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
6475 inner_comps
, tf_inner_offset
,
6476 ctx
->oc_lds
, 0, 1, 0, true, false);
6479 ac_nir_build_endif(&if_ctx
);
6483 handle_tcs_outputs_post(struct nir_to_llvm_context
*ctx
)
6485 write_tess_factors(ctx
);
6489 si_export_mrt_color(struct nir_to_llvm_context
*ctx
,
6490 LLVMValueRef
*color
, unsigned param
, bool is_last
,
6491 struct ac_export_args
*args
)
6494 si_llvm_init_export_args(ctx
, color
, param
,
6498 args
->valid_mask
= 1; /* whether the EXEC mask is valid */
6499 args
->done
= 1; /* DONE bit */
6500 } else if (!args
->enabled_channels
)
6501 return false; /* unnecessary NULL export */
6507 radv_export_mrt_z(struct nir_to_llvm_context
*ctx
,
6508 LLVMValueRef depth
, LLVMValueRef stencil
,
6509 LLVMValueRef samplemask
)
6511 struct ac_export_args args
;
6513 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
6515 ac_build_export(&ctx
->ac
, &args
);
6519 handle_fs_outputs_post(struct nir_to_llvm_context
*ctx
)
6522 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
6523 struct ac_export_args color_args
[8];
6525 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6526 LLVMValueRef values
[4];
6528 if (!(ctx
->output_mask
& (1ull << i
)))
6531 if (i
== FRAG_RESULT_DEPTH
) {
6532 ctx
->shader_info
->fs
.writes_z
= true;
6533 depth
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6534 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6535 } else if (i
== FRAG_RESULT_STENCIL
) {
6536 ctx
->shader_info
->fs
.writes_stencil
= true;
6537 stencil
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6538 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6539 } else if (i
== FRAG_RESULT_SAMPLE_MASK
) {
6540 ctx
->shader_info
->fs
.writes_sample_mask
= true;
6541 samplemask
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6542 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6545 for (unsigned j
= 0; j
< 4; j
++)
6546 values
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6547 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
6549 if (!ctx
->shader_info
->fs
.writes_z
&& !ctx
->shader_info
->fs
.writes_stencil
&& !ctx
->shader_info
->fs
.writes_sample_mask
)
6550 last
= ctx
->output_mask
<= ((1ull << (i
+ 1)) - 1);
6552 bool ret
= si_export_mrt_color(ctx
, values
, V_008DFC_SQ_EXP_MRT
+ (i
- FRAG_RESULT_DATA0
), last
, &color_args
[index
]);
6558 for (unsigned i
= 0; i
< index
; i
++)
6559 ac_build_export(&ctx
->ac
, &color_args
[i
]);
6560 if (depth
|| stencil
|| samplemask
)
6561 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
6563 si_export_mrt_color(ctx
, NULL
, V_008DFC_SQ_EXP_NULL
, true, &color_args
[0]);
6564 ac_build_export(&ctx
->ac
, &color_args
[0]);
6569 emit_gs_epilogue(struct nir_to_llvm_context
*ctx
)
6571 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
6575 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
6576 LLVMValueRef
*addrs
)
6578 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
6580 switch (ctx
->stage
) {
6581 case MESA_SHADER_VERTEX
:
6582 if (ctx
->options
->key
.vs
.as_ls
)
6583 handle_ls_outputs_post(ctx
);
6584 else if (ctx
->options
->key
.vs
.as_es
)
6585 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
6587 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
6588 &ctx
->shader_info
->vs
.outinfo
);
6590 case MESA_SHADER_FRAGMENT
:
6591 handle_fs_outputs_post(ctx
);
6593 case MESA_SHADER_GEOMETRY
:
6594 emit_gs_epilogue(ctx
);
6596 case MESA_SHADER_TESS_CTRL
:
6597 handle_tcs_outputs_post(ctx
);
6599 case MESA_SHADER_TESS_EVAL
:
6600 if (ctx
->options
->key
.tes
.as_es
)
6601 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
6603 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
6604 &ctx
->shader_info
->tes
.outinfo
);
6611 static void ac_llvm_finalize_module(struct nir_to_llvm_context
* ctx
)
6613 LLVMPassManagerRef passmgr
;
6614 /* Create the pass manager */
6615 passmgr
= LLVMCreateFunctionPassManagerForModule(
6618 /* This pass should eliminate all the load and store instructions */
6619 LLVMAddPromoteMemoryToRegisterPass(passmgr
);
6621 /* Add some optimization passes */
6622 LLVMAddScalarReplAggregatesPass(passmgr
);
6623 LLVMAddLICMPass(passmgr
);
6624 LLVMAddAggressiveDCEPass(passmgr
);
6625 LLVMAddCFGSimplificationPass(passmgr
);
6626 LLVMAddInstructionCombiningPass(passmgr
);
6629 LLVMInitializeFunctionPassManager(passmgr
);
6630 LLVMRunFunctionPassManager(passmgr
, ctx
->main_function
);
6631 LLVMFinalizeFunctionPassManager(passmgr
);
6633 LLVMDisposeBuilder(ctx
->builder
);
6634 LLVMDisposePassManager(passmgr
);
6638 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context
*ctx
)
6640 struct ac_vs_output_info
*outinfo
;
6642 switch (ctx
->stage
) {
6643 case MESA_SHADER_FRAGMENT
:
6644 case MESA_SHADER_COMPUTE
:
6645 case MESA_SHADER_TESS_CTRL
:
6646 case MESA_SHADER_GEOMETRY
:
6648 case MESA_SHADER_VERTEX
:
6649 if (ctx
->options
->key
.vs
.as_ls
||
6650 ctx
->options
->key
.vs
.as_es
)
6652 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
6654 case MESA_SHADER_TESS_EVAL
:
6655 if (ctx
->options
->key
.vs
.as_es
)
6657 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
6660 unreachable("Unhandled shader type");
6663 ac_optimize_vs_outputs(&ctx
->ac
,
6665 outinfo
->vs_output_param_offset
,
6667 &outinfo
->param_exports
);
6671 ac_setup_rings(struct nir_to_llvm_context
*ctx
)
6673 if ((ctx
->stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_es
) ||
6674 (ctx
->stage
== MESA_SHADER_TESS_EVAL
&& ctx
->options
->key
.tes
.as_es
)) {
6675 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_VS
, false));
6678 if (ctx
->is_gs_copy_shader
) {
6679 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_VS
, false));
6681 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
6683 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_GS
, false));
6684 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_GS
, false));
6686 ctx
->gsvs_ring
= LLVMBuildBitCast(ctx
->builder
, ctx
->gsvs_ring
, ctx
->ac
.v4i32
, "");
6688 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->gsvs_num_entries
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
6689 tmp
= LLVMBuildExtractElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->ac
.i32_1
, "");
6690 tmp
= LLVMBuildOr(ctx
->builder
, tmp
, ctx
->gsvs_ring_stride
, "");
6691 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, tmp
, ctx
->ac
.i32_1
, "");
6694 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
6695 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
6696 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
6697 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
6702 ac_nir_get_max_workgroup_size(enum chip_class chip_class
,
6703 const struct nir_shader
*nir
)
6705 switch (nir
->info
.stage
) {
6706 case MESA_SHADER_TESS_CTRL
:
6707 return chip_class
>= CIK
? 128 : 64;
6708 case MESA_SHADER_GEOMETRY
:
6709 return chip_class
>= GFX9
? 128 : 64;
6710 case MESA_SHADER_COMPUTE
:
6716 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
6717 nir
->info
.cs
.local_size
[1] *
6718 nir
->info
.cs
.local_size
[2];
6719 return max_workgroup_size
;
6722 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6723 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context
*ctx
)
6725 LLVMValueRef count
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6726 LLVMConstInt(ctx
->ac
.i32
, 8, false),
6727 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6728 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
6730 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
6731 ctx
->vs_prim_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.vertex_id
, ctx
->vs_prim_id
, "");
6732 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
6733 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
6736 static void prepare_gs_input_vgprs(struct nir_to_llvm_context
*ctx
)
6738 for(int i
= 5; i
>= 0; --i
) {
6739 ctx
->gs_vtx_offset
[i
] = ac_build_bfe(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
6740 LLVMConstInt(ctx
->ac
.i32
, (i
& 1) * 16, false),
6741 LLVMConstInt(ctx
->ac
.i32
, 16, false), false);
6744 ctx
->gs_wave_id
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6745 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6746 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6749 void ac_nir_translate(struct ac_llvm_context
*ac
, struct ac_shader_abi
*abi
,
6750 struct nir_shader
*nir
, struct nir_to_llvm_context
*nctx
)
6752 struct ac_nir_context ctx
= {};
6753 struct nir_function
*func
;
6762 ctx
.stage
= nir
->info
.stage
;
6764 ctx
.main_function
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6766 nir_foreach_variable(variable
, &nir
->outputs
)
6767 handle_shader_output_decl(&ctx
, nir
, variable
);
6769 ctx
.defs
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6770 _mesa_key_pointer_equal
);
6771 ctx
.phis
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6772 _mesa_key_pointer_equal
);
6773 ctx
.vars
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6774 _mesa_key_pointer_equal
);
6776 func
= (struct nir_function
*)exec_list_get_head(&nir
->functions
);
6778 setup_locals(&ctx
, func
);
6780 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
6781 setup_shared(&ctx
, nir
);
6783 visit_cf_list(&ctx
, &func
->impl
->body
);
6784 phi_post_pass(&ctx
);
6786 ctx
.abi
->emit_outputs(ctx
.abi
, RADEON_LLVM_MAX_OUTPUTS
,
6790 ralloc_free(ctx
.defs
);
6791 ralloc_free(ctx
.phis
);
6792 ralloc_free(ctx
.vars
);
6799 LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm
,
6800 struct nir_shader
*const *shaders
,
6802 struct ac_shader_variant_info
*shader_info
,
6803 const struct ac_nir_compiler_options
*options
)
6805 struct nir_to_llvm_context ctx
= {0};
6807 ctx
.options
= options
;
6808 ctx
.shader_info
= shader_info
;
6809 ctx
.context
= LLVMContextCreate();
6810 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
6812 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
6814 ctx
.ac
.module
= ctx
.module
;
6815 LLVMSetTarget(ctx
.module
, options
->supports_spill
? "amdgcn-mesa-mesa3d" : "amdgcn--");
6817 LLVMTargetDataRef data_layout
= LLVMCreateTargetDataLayout(tm
);
6818 char *data_layout_str
= LLVMCopyStringRepOfTargetData(data_layout
);
6819 LLVMSetDataLayout(ctx
.module
, data_layout_str
);
6820 LLVMDisposeTargetData(data_layout
);
6821 LLVMDisposeMessage(data_layout_str
);
6823 enum ac_float_mode float_mode
=
6824 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
6825 AC_FLOAT_MODE_DEFAULT
;
6827 ctx
.builder
= ac_create_builder(ctx
.context
, float_mode
);
6828 ctx
.ac
.builder
= ctx
.builder
;
6830 memset(shader_info
, 0, sizeof(*shader_info
));
6832 for(int i
= 0; i
< shader_count
; ++i
)
6833 ac_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
6835 for (i
= 0; i
< AC_UD_MAX_SETS
; i
++)
6836 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
6837 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
6838 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
6840 ctx
.max_workgroup_size
= 0;
6841 for (int i
= 0; i
< shader_count
; ++i
) {
6842 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
6843 ac_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
6847 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
6848 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
6850 ctx
.abi
.inputs
= &ctx
.inputs
[0];
6851 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
6852 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
6853 ctx
.abi
.load_ubo
= radv_load_ubo
;
6854 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
6855 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
6856 ctx
.abi
.clamp_shadow_reference
= false;
6858 if (shader_count
>= 2)
6859 ac_init_exec_full_mask(&ctx
.ac
);
6861 if (ctx
.ac
.chip_class
== GFX9
&&
6862 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
6863 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
6865 for(int i
= 0; i
< shader_count
; ++i
) {
6866 ctx
.stage
= shaders
[i
]->info
.stage
;
6867 ctx
.output_mask
= 0;
6868 ctx
.tess_outputs_written
= 0;
6869 ctx
.num_output_clips
= shaders
[i
]->info
.clip_distance_array_size
;
6870 ctx
.num_output_culls
= shaders
[i
]->info
.cull_distance_array_size
;
6872 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6873 ctx
.gs_next_vertex
= ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "gs_next_vertex");
6874 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
6875 ctx
.abi
.load_inputs
= load_gs_input
;
6876 ctx
.abi
.emit_primitive
= visit_end_primitive
;
6877 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6878 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
6879 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
6880 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
6881 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
6882 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
6883 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
6884 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
6885 ctx
.abi
.load_tess_varyings
= load_tes_input
;
6886 ctx
.abi
.load_tess_coord
= load_tess_coord
;
6887 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
6888 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
6889 if (shader_info
->info
.vs
.needs_instance_id
) {
6890 if (ctx
.options
->key
.vs
.as_ls
) {
6891 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6892 MAX2(2, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6894 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6895 MAX2(1, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6898 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
6899 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
6903 emit_barrier(&ctx
.ac
, ctx
.stage
);
6905 ac_setup_rings(&ctx
);
6907 LLVMBasicBlockRef merge_block
;
6908 if (shader_count
>= 2) {
6909 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6910 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6911 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6913 LLVMValueRef count
= ac_build_bfe(&ctx
.ac
, ctx
.merged_wave_info
,
6914 LLVMConstInt(ctx
.ac
.i32
, 8 * i
, false),
6915 LLVMConstInt(ctx
.ac
.i32
, 8, false), false);
6916 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
6917 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
6918 thread_id
, count
, "");
6919 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
6921 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
6924 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
6925 handle_fs_inputs(&ctx
, shaders
[i
]);
6926 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
6927 handle_vs_inputs(&ctx
, shaders
[i
]);
6928 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
6929 prepare_gs_input_vgprs(&ctx
);
6931 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
6932 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
6934 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
], &ctx
);
6936 if (shader_count
>= 2) {
6937 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
6938 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
6941 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6942 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
6943 shaders
[i
]->info
.cull_distance_array_size
> 4;
6944 shader_info
->gs
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
6945 shader_info
->gs
.max_gsvs_emit_size
= shader_info
->gs
.gsvs_vertex_size
*
6946 shaders
[i
]->info
.gs
.vertices_out
;
6947 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6948 shader_info
->tcs
.outputs_written
= ctx
.tess_outputs_written
;
6949 shader_info
->tcs
.patch_outputs_written
= ctx
.tess_patch_outputs_written
;
6950 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&& ctx
.options
->key
.vs
.as_ls
) {
6951 shader_info
->vs
.outputs_written
= ctx
.tess_outputs_written
;
6955 LLVMBuildRetVoid(ctx
.builder
);
6957 if (options
->dump_preoptir
)
6958 ac_dump_module(ctx
.module
);
6960 ac_llvm_finalize_module(&ctx
);
6962 if (shader_count
== 1)
6963 ac_nir_eliminate_const_vs_outputs(&ctx
);
6968 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
6970 unsigned *retval
= (unsigned *)context
;
6971 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
6972 char *description
= LLVMGetDiagInfoDescription(di
);
6974 if (severity
== LLVMDSError
) {
6976 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
6980 LLVMDisposeMessage(description
);
6983 static unsigned ac_llvm_compile(LLVMModuleRef M
,
6984 struct ac_shader_binary
*binary
,
6985 LLVMTargetMachineRef tm
)
6987 unsigned retval
= 0;
6989 LLVMContextRef llvm_ctx
;
6990 LLVMMemoryBufferRef out_buffer
;
6991 unsigned buffer_size
;
6992 const char *buffer_data
;
6995 /* Setup Diagnostic Handler*/
6996 llvm_ctx
= LLVMGetModuleContext(M
);
6998 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
7002 mem_err
= LLVMTargetMachineEmitToMemoryBuffer(tm
, M
, LLVMObjectFile
,
7005 /* Process Errors/Warnings */
7007 fprintf(stderr
, "%s: %s", __FUNCTION__
, err
);
7013 /* Extract Shader Code*/
7014 buffer_size
= LLVMGetBufferSize(out_buffer
);
7015 buffer_data
= LLVMGetBufferStart(out_buffer
);
7017 ac_elf_read(buffer_data
, buffer_size
, binary
);
7020 LLVMDisposeMemoryBuffer(out_buffer
);
7026 static void ac_compile_llvm_module(LLVMTargetMachineRef tm
,
7027 LLVMModuleRef llvm_module
,
7028 struct ac_shader_binary
*binary
,
7029 struct ac_shader_config
*config
,
7030 struct ac_shader_variant_info
*shader_info
,
7031 gl_shader_stage stage
,
7032 bool dump_shader
, bool supports_spill
)
7035 ac_dump_module(llvm_module
);
7037 memset(binary
, 0, sizeof(*binary
));
7038 int v
= ac_llvm_compile(llvm_module
, binary
, tm
);
7040 fprintf(stderr
, "compile failed\n");
7044 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
7046 ac_shader_binary_read_config(binary
, config
, 0, supports_spill
);
7048 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
7049 LLVMDisposeModule(llvm_module
);
7050 LLVMContextDispose(ctx
);
7052 if (stage
== MESA_SHADER_FRAGMENT
) {
7053 shader_info
->num_input_vgprs
= 0;
7054 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
7055 shader_info
->num_input_vgprs
+= 2;
7056 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
7057 shader_info
->num_input_vgprs
+= 2;
7058 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
7059 shader_info
->num_input_vgprs
+= 2;
7060 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
7061 shader_info
->num_input_vgprs
+= 3;
7062 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
7063 shader_info
->num_input_vgprs
+= 2;
7064 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
7065 shader_info
->num_input_vgprs
+= 2;
7066 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
7067 shader_info
->num_input_vgprs
+= 2;
7068 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
7069 shader_info
->num_input_vgprs
+= 1;
7070 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
7071 shader_info
->num_input_vgprs
+= 1;
7072 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
7073 shader_info
->num_input_vgprs
+= 1;
7074 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
7075 shader_info
->num_input_vgprs
+= 1;
7076 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
7077 shader_info
->num_input_vgprs
+= 1;
7078 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
7079 shader_info
->num_input_vgprs
+= 1;
7080 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
7081 shader_info
->num_input_vgprs
+= 1;
7082 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
7083 shader_info
->num_input_vgprs
+= 1;
7084 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
7085 shader_info
->num_input_vgprs
+= 1;
7087 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
7089 /* +3 for scratch wave offset and VCC */
7090 config
->num_sgprs
= MAX2(config
->num_sgprs
,
7091 shader_info
->num_input_sgprs
+ 3);
7093 /* Enable 64-bit and 16-bit denormals, because there is no performance
7096 * If denormals are enabled, all floating-point output modifiers are
7099 * Don't enable denormals for 32-bit floats, because:
7100 * - Floating-point output modifiers would be ignored by the hw.
7101 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7102 * have to stop using those.
7103 * - SI & CI would be very slow.
7105 config
->float_mode
|= V_00B028_FP_64_DENORMS
;
7109 ac_fill_shader_info(struct ac_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct ac_nir_compiler_options
*options
)
7111 switch (nir
->info
.stage
) {
7112 case MESA_SHADER_COMPUTE
:
7113 for (int i
= 0; i
< 3; ++i
)
7114 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
7116 case MESA_SHADER_FRAGMENT
:
7117 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
7119 case MESA_SHADER_GEOMETRY
:
7120 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
7121 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
7122 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
7123 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
7125 case MESA_SHADER_TESS_EVAL
:
7126 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
7127 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
7128 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
7129 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
7130 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
7132 case MESA_SHADER_TESS_CTRL
:
7133 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
7135 case MESA_SHADER_VERTEX
:
7136 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
7137 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
7138 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7139 if (options
->key
.vs
.as_ls
)
7140 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
7147 void ac_compile_nir_shader(LLVMTargetMachineRef tm
,
7148 struct ac_shader_binary
*binary
,
7149 struct ac_shader_config
*config
,
7150 struct ac_shader_variant_info
*shader_info
,
7151 struct nir_shader
*const *nir
,
7153 const struct ac_nir_compiler_options
*options
,
7157 LLVMModuleRef llvm_module
= ac_translate_nir_to_llvm(tm
, nir
, nir_count
, shader_info
,
7160 ac_compile_llvm_module(tm
, llvm_module
, binary
, config
, shader_info
, nir
[0]->info
.stage
, dump_shader
, options
->supports_spill
);
7161 for (int i
= 0; i
< nir_count
; ++i
)
7162 ac_fill_shader_info(shader_info
, nir
[i
], options
);
7164 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7165 if (options
->chip_class
== GFX9
) {
7166 if (nir_count
== 2 &&
7167 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
7168 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
7174 ac_gs_copy_shader_emit(struct nir_to_llvm_context
*ctx
)
7176 LLVMValueRef args
[9];
7177 args
[0] = ctx
->gsvs_ring
;
7178 args
[1] = LLVMBuildMul(ctx
->builder
, ctx
->abi
.vertex_id
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
7179 args
[3] = ctx
->ac
.i32_0
;
7180 args
[4] = ctx
->ac
.i32_1
; /* OFFEN */
7181 args
[5] = ctx
->ac
.i32_0
; /* IDXEN */
7182 args
[6] = ctx
->ac
.i32_1
; /* GLC */
7183 args
[7] = ctx
->ac
.i32_1
; /* SLC */
7184 args
[8] = ctx
->ac
.i32_0
; /* TFE */
7188 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
7192 if (!(ctx
->output_mask
& (1ull << i
)))
7195 if (i
== VARYING_SLOT_CLIP_DIST0
) {
7196 /* unpack clip and cull from a single set of slots */
7197 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
7202 for (unsigned j
= 0; j
< length
; j
++) {
7204 args
[2] = LLVMConstInt(ctx
->ac
.i32
,
7206 ctx
->gs_max_out_vertices
* 16 * 4, false);
7208 value
= ac_build_intrinsic(&ctx
->ac
,
7209 "llvm.SI.buffer.load.dword.i32.i32",
7210 ctx
->ac
.i32
, args
, 9,
7211 AC_FUNC_ATTR_READONLY
|
7212 AC_FUNC_ATTR_LEGACY
);
7214 LLVMBuildStore(ctx
->builder
,
7215 ac_to_float(&ctx
->ac
, value
), ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)]);
7219 handle_vs_outputs_post(ctx
, false, &ctx
->shader_info
->vs
.outinfo
);
7222 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm
,
7223 struct nir_shader
*geom_shader
,
7224 struct ac_shader_binary
*binary
,
7225 struct ac_shader_config
*config
,
7226 struct ac_shader_variant_info
*shader_info
,
7227 const struct ac_nir_compiler_options
*options
,
7230 struct nir_to_llvm_context ctx
= {0};
7231 ctx
.context
= LLVMContextCreate();
7232 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
7233 ctx
.options
= options
;
7234 ctx
.shader_info
= shader_info
;
7236 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
7238 ctx
.ac
.module
= ctx
.module
;
7240 ctx
.is_gs_copy_shader
= true;
7241 LLVMSetTarget(ctx
.module
, "amdgcn--");
7243 enum ac_float_mode float_mode
=
7244 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
7245 AC_FLOAT_MODE_DEFAULT
;
7247 ctx
.builder
= ac_create_builder(ctx
.context
, float_mode
);
7248 ctx
.ac
.builder
= ctx
.builder
;
7249 ctx
.stage
= MESA_SHADER_VERTEX
;
7251 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
7253 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
7254 ac_setup_rings(&ctx
);
7256 ctx
.num_output_clips
= geom_shader
->info
.clip_distance_array_size
;
7257 ctx
.num_output_culls
= geom_shader
->info
.cull_distance_array_size
;
7259 struct ac_nir_context nir_ctx
= {};
7260 nir_ctx
.ac
= ctx
.ac
;
7261 nir_ctx
.abi
= &ctx
.abi
;
7263 nir_ctx
.nctx
= &ctx
;
7266 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
7267 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
7268 handle_shader_output_decl(&nir_ctx
, geom_shader
, variable
);
7271 ac_gs_copy_shader_emit(&ctx
);
7275 LLVMBuildRetVoid(ctx
.builder
);
7277 ac_llvm_finalize_module(&ctx
);
7279 ac_compile_llvm_module(tm
, ctx
.module
, binary
, config
, shader_info
,
7281 dump_shader
, options
->supports_spill
);