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[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 };
43
44 #define CONST_ADDR_SPACE 2
45 #define LOCAL_ADDR_SPACE 3
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct nir_to_llvm_context;
51
52 struct ac_nir_context {
53 struct ac_llvm_context ac;
54 struct ac_shader_abi *abi;
55
56 gl_shader_stage stage;
57
58 struct hash_table *defs;
59 struct hash_table *phis;
60 struct hash_table *vars;
61
62 LLVMValueRef main_function;
63 LLVMBasicBlockRef continue_block;
64 LLVMBasicBlockRef break_block;
65
66 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
67
68 int num_locals;
69 LLVMValueRef *locals;
70
71 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
72 };
73
74 struct nir_to_llvm_context {
75 struct ac_llvm_context ac;
76 const struct ac_nir_compiler_options *options;
77 struct ac_shader_variant_info *shader_info;
78 struct ac_shader_abi abi;
79 struct ac_nir_context *nir;
80
81 unsigned max_workgroup_size;
82 LLVMContextRef context;
83 LLVMModuleRef module;
84 LLVMBuilderRef builder;
85 LLVMValueRef main_function;
86
87 struct hash_table *defs;
88 struct hash_table *phis;
89
90 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
91 LLVMValueRef ring_offsets;
92 LLVMValueRef push_constants;
93 LLVMValueRef num_work_groups;
94 LLVMValueRef workgroup_ids;
95 LLVMValueRef local_invocation_ids;
96 LLVMValueRef tg_size;
97
98 LLVMValueRef vertex_buffers;
99 LLVMValueRef rel_auto_id;
100 LLVMValueRef vs_prim_id;
101 LLVMValueRef ls_out_layout;
102 LLVMValueRef es2gs_offset;
103
104 LLVMValueRef tcs_offchip_layout;
105 LLVMValueRef tcs_out_offsets;
106 LLVMValueRef tcs_out_layout;
107 LLVMValueRef tcs_in_layout;
108 LLVMValueRef oc_lds;
109 LLVMValueRef tess_factor_offset;
110 LLVMValueRef tcs_patch_id;
111 LLVMValueRef tcs_rel_ids;
112 LLVMValueRef tes_rel_patch_id;
113 LLVMValueRef tes_patch_id;
114 LLVMValueRef tes_u;
115 LLVMValueRef tes_v;
116
117 LLVMValueRef gsvs_ring_stride;
118 LLVMValueRef gsvs_num_entries;
119 LLVMValueRef gs2vs_offset;
120 LLVMValueRef gs_wave_id;
121 LLVMValueRef gs_vtx_offset[6];
122 LLVMValueRef gs_prim_id, gs_invocation_id;
123
124 LLVMValueRef esgs_ring;
125 LLVMValueRef gsvs_ring;
126 LLVMValueRef hs_ring_tess_offchip;
127 LLVMValueRef hs_ring_tess_factor;
128
129 LLVMValueRef prim_mask;
130 LLVMValueRef sample_pos_offset;
131 LLVMValueRef persp_sample, persp_center, persp_centroid;
132 LLVMValueRef linear_sample, linear_center, linear_centroid;
133 LLVMValueRef front_face;
134 LLVMValueRef ancillary;
135 LLVMValueRef sample_coverage;
136 LLVMValueRef frag_pos[4];
137
138 LLVMTypeRef i1;
139 LLVMTypeRef i8;
140 LLVMTypeRef i16;
141 LLVMTypeRef i32;
142 LLVMTypeRef i64;
143 LLVMTypeRef v2i32;
144 LLVMTypeRef v3i32;
145 LLVMTypeRef v4i32;
146 LLVMTypeRef v8i32;
147 LLVMTypeRef f64;
148 LLVMTypeRef f32;
149 LLVMTypeRef f16;
150 LLVMTypeRef v2f32;
151 LLVMTypeRef v4f32;
152 LLVMTypeRef voidt;
153
154 LLVMValueRef i1true;
155 LLVMValueRef i1false;
156 LLVMValueRef i32zero;
157 LLVMValueRef i32one;
158 LLVMValueRef f32zero;
159 LLVMValueRef f32one;
160 LLVMValueRef v4f32empty;
161
162 unsigned uniform_md_kind;
163 LLVMValueRef empty_md;
164 gl_shader_stage stage;
165
166 LLVMValueRef lds;
167 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
168
169 uint64_t input_mask;
170 uint64_t output_mask;
171 uint8_t num_output_clips;
172 uint8_t num_output_culls;
173
174 bool has_ds_bpermute;
175
176 bool is_gs_copy_shader;
177 LLVMValueRef gs_next_vertex;
178 unsigned gs_max_out_vertices;
179
180 unsigned tes_primitive_mode;
181 uint64_t tess_outputs_written;
182 uint64_t tess_patch_outputs_written;
183 };
184
185 static inline struct nir_to_llvm_context *
186 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
187 {
188 struct nir_to_llvm_context *ctx = NULL;
189 return container_of(abi, ctx, abi);
190 }
191
192 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
193 const nir_deref_var *deref,
194 enum ac_descriptor_type desc_type,
195 bool image, bool write);
196
197 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
198 {
199 return (index * 4) + chan;
200 }
201
202 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
203 {
204 /* handle patch indices separate */
205 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
206 return 0;
207 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
208 return 1;
209 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
210 return 2 + (slot - VARYING_SLOT_PATCH0);
211
212 if (slot == VARYING_SLOT_POS)
213 return 0;
214 if (slot == VARYING_SLOT_PSIZ)
215 return 1;
216 if (slot == VARYING_SLOT_CLIP_DIST0)
217 return 2;
218 /* 3 is reserved for clip dist as well */
219 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
220 return 4 + (slot - VARYING_SLOT_VAR0);
221 unreachable("illegal slot in get unique index\n");
222 }
223
224 static unsigned llvm_get_type_size(LLVMTypeRef type)
225 {
226 LLVMTypeKind kind = LLVMGetTypeKind(type);
227
228 switch (kind) {
229 case LLVMIntegerTypeKind:
230 return LLVMGetIntTypeWidth(type) / 8;
231 case LLVMFloatTypeKind:
232 return 4;
233 case LLVMPointerTypeKind:
234 return 8;
235 case LLVMVectorTypeKind:
236 return LLVMGetVectorSize(type) *
237 llvm_get_type_size(LLVMGetElementType(type));
238 default:
239 assert(0);
240 return 0;
241 }
242 }
243
244 static void set_llvm_calling_convention(LLVMValueRef func,
245 gl_shader_stage stage)
246 {
247 enum radeon_llvm_calling_convention calling_conv;
248
249 switch (stage) {
250 case MESA_SHADER_VERTEX:
251 case MESA_SHADER_TESS_CTRL:
252 case MESA_SHADER_TESS_EVAL:
253 calling_conv = RADEON_LLVM_AMDGPU_VS;
254 break;
255 case MESA_SHADER_GEOMETRY:
256 calling_conv = RADEON_LLVM_AMDGPU_GS;
257 break;
258 case MESA_SHADER_FRAGMENT:
259 calling_conv = RADEON_LLVM_AMDGPU_PS;
260 break;
261 case MESA_SHADER_COMPUTE:
262 calling_conv = RADEON_LLVM_AMDGPU_CS;
263 break;
264 default:
265 unreachable("Unhandle shader type");
266 }
267
268 LLVMSetFunctionCallConv(func, calling_conv);
269 }
270
271 #define MAX_ARGS 23
272 struct arg_info {
273 LLVMTypeRef types[MAX_ARGS];
274 LLVMValueRef *assign[MAX_ARGS];
275 unsigned array_params_mask;
276 uint8_t count;
277 uint8_t user_sgpr_count;
278 uint8_t sgpr_count;
279 uint8_t num_user_sgprs_used;
280 uint8_t num_sgprs_used;
281 uint8_t num_vgprs_used;
282 };
283
284 static inline void
285 add_argument(struct arg_info *info,
286 LLVMTypeRef type, LLVMValueRef *param_ptr)
287 {
288 assert(info->count < MAX_ARGS);
289 info->assign[info->count] = param_ptr;
290 info->types[info->count] = type;
291 info->count++;
292 }
293
294 static inline void
295 add_sgpr_argument(struct arg_info *info,
296 LLVMTypeRef type, LLVMValueRef *param_ptr)
297 {
298 add_argument(info, type, param_ptr);
299 info->num_sgprs_used += llvm_get_type_size(type) / 4;
300 info->sgpr_count++;
301 }
302
303 static inline void
304 add_user_sgpr_argument(struct arg_info *info,
305 LLVMTypeRef type,
306 LLVMValueRef *param_ptr)
307 {
308 add_sgpr_argument(info, type, param_ptr);
309 info->num_user_sgprs_used += llvm_get_type_size(type) / 4;
310 info->user_sgpr_count++;
311 }
312
313 static inline void
314 add_vgpr_argument(struct arg_info *info,
315 LLVMTypeRef type,
316 LLVMValueRef *param_ptr)
317 {
318 add_argument(info, type, param_ptr);
319 info->num_vgprs_used += llvm_get_type_size(type) / 4;
320 }
321
322 static inline void
323 add_user_sgpr_array_argument(struct arg_info *info,
324 LLVMTypeRef type,
325 LLVMValueRef *param_ptr)
326 {
327 info->array_params_mask |= (1 << info->count);
328 add_user_sgpr_argument(info, type, param_ptr);
329 }
330
331 static void assign_arguments(LLVMValueRef main_function,
332 struct arg_info *info)
333 {
334 unsigned i;
335 for (i = 0; i < info->count; i++) {
336 if (info->assign[i])
337 *info->assign[i] = LLVMGetParam(main_function, i);
338 }
339 }
340
341 static LLVMValueRef
342 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
343 LLVMBuilderRef builder, LLVMTypeRef *return_types,
344 unsigned num_return_elems,
345 struct arg_info *args,
346 unsigned max_workgroup_size,
347 bool unsafe_math)
348 {
349 LLVMTypeRef main_function_type, ret_type;
350 LLVMBasicBlockRef main_function_body;
351
352 if (num_return_elems)
353 ret_type = LLVMStructTypeInContext(ctx, return_types,
354 num_return_elems, true);
355 else
356 ret_type = LLVMVoidTypeInContext(ctx);
357
358 /* Setup the function */
359 main_function_type =
360 LLVMFunctionType(ret_type, args->types, args->count, 0);
361 LLVMValueRef main_function =
362 LLVMAddFunction(module, "main", main_function_type);
363 main_function_body =
364 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
365 LLVMPositionBuilderAtEnd(builder, main_function_body);
366
367 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
368 for (unsigned i = 0; i < args->sgpr_count; ++i) {
369 if (args->array_params_mask & (1 << i)) {
370 LLVMValueRef P = LLVMGetParam(main_function, i);
371 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
372 ac_add_attr_dereferenceable(P, UINT64_MAX);
373 }
374 else {
375 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
376 }
377 }
378
379 if (max_workgroup_size) {
380 ac_llvm_add_target_dep_function_attr(main_function,
381 "amdgpu-max-work-group-size",
382 max_workgroup_size);
383 }
384 if (unsafe_math) {
385 /* These were copied from some LLVM test. */
386 LLVMAddTargetDependentFunctionAttr(main_function,
387 "less-precise-fpmad",
388 "true");
389 LLVMAddTargetDependentFunctionAttr(main_function,
390 "no-infs-fp-math",
391 "true");
392 LLVMAddTargetDependentFunctionAttr(main_function,
393 "no-nans-fp-math",
394 "true");
395 LLVMAddTargetDependentFunctionAttr(main_function,
396 "unsafe-fp-math",
397 "true");
398 }
399 return main_function;
400 }
401
402 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
403 {
404 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
405 CONST_ADDR_SPACE);
406 }
407
408 static LLVMTypeRef to_integer_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
409 {
410 if (t == ctx->f16 || t == ctx->i16)
411 return ctx->i16;
412 else if (t == ctx->f32 || t == ctx->i32)
413 return ctx->i32;
414 else if (t == ctx->f64 || t == ctx->i64)
415 return ctx->i64;
416 else
417 unreachable("Unhandled integer size");
418 }
419
420 static LLVMTypeRef to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
421 {
422 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
423 LLVMTypeRef elem_type = LLVMGetElementType(t);
424 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
425 LLVMGetVectorSize(t));
426 }
427 return to_integer_type_scalar(ctx, t);
428 }
429
430 static LLVMValueRef to_integer(struct ac_llvm_context *ctx, LLVMValueRef v)
431 {
432 LLVMTypeRef type = LLVMTypeOf(v);
433 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
434 }
435
436 static LLVMTypeRef to_float_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
437 {
438 if (t == ctx->i16 || t == ctx->f16)
439 return ctx->f16;
440 else if (t == ctx->i32 || t == ctx->f32)
441 return ctx->f32;
442 else if (t == ctx->i64 || t == ctx->f64)
443 return ctx->f64;
444 else
445 unreachable("Unhandled float size");
446 }
447
448 static LLVMTypeRef to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
449 {
450 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
451 LLVMTypeRef elem_type = LLVMGetElementType(t);
452 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
453 LLVMGetVectorSize(t));
454 }
455 return to_float_type_scalar(ctx, t);
456 }
457
458 static LLVMValueRef to_float(struct ac_llvm_context *ctx, LLVMValueRef v)
459 {
460 LLVMTypeRef type = LLVMTypeOf(v);
461 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
462 }
463
464 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
465 {
466 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
467 type = LLVMGetElementType(type);
468
469 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
470 return LLVMGetIntTypeWidth(type);
471
472 if (type == ctx->f16)
473 return 16;
474 if (type == ctx->f32)
475 return 32;
476 if (type == ctx->f64)
477 return 64;
478
479 unreachable("Unhandled type kind in get_elem_bits");
480 }
481
482 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
483 LLVMValueRef param, unsigned rshift,
484 unsigned bitwidth)
485 {
486 LLVMValueRef value = param;
487 if (rshift)
488 value = LLVMBuildLShr(ctx->builder, value,
489 LLVMConstInt(ctx->i32, rshift, false), "");
490
491 if (rshift + bitwidth < 32) {
492 unsigned mask = (1 << bitwidth) - 1;
493 value = LLVMBuildAnd(ctx->builder, value,
494 LLVMConstInt(ctx->i32, mask, false), "");
495 }
496 return value;
497 }
498
499 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
500 {
501 switch (ctx->stage) {
502 case MESA_SHADER_TESS_CTRL:
503 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
504 case MESA_SHADER_TESS_EVAL:
505 return ctx->tes_rel_patch_id;
506 break;
507 default:
508 unreachable("Illegal stage");
509 }
510 }
511
512 /* Tessellation shaders pass outputs to the next shader using LDS.
513 *
514 * LS outputs = TCS inputs
515 * TCS outputs = TES inputs
516 *
517 * The LDS layout is:
518 * - TCS inputs for patch 0
519 * - TCS inputs for patch 1
520 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
521 * - ...
522 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
523 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
524 * - TCS outputs for patch 1
525 * - Per-patch TCS outputs for patch 1
526 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
527 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
528 * - ...
529 *
530 * All three shaders VS(LS), TCS, TES share the same LDS space.
531 */
532 static LLVMValueRef
533 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
534 {
535 if (ctx->stage == MESA_SHADER_VERTEX)
536 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
537 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
538 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
539 else {
540 assert(0);
541 return NULL;
542 }
543 }
544
545 static LLVMValueRef
546 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
547 {
548 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
549 }
550
551 static LLVMValueRef
552 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
553 {
554 return LLVMBuildMul(ctx->builder,
555 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
556 LLVMConstInt(ctx->i32, 4, false), "");
557 }
558
559 static LLVMValueRef
560 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
561 {
562 return LLVMBuildMul(ctx->builder,
563 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
564 LLVMConstInt(ctx->i32, 4, false), "");
565 }
566
567 static LLVMValueRef
568 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
569 {
570 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
571 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
572
573 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
574 }
575
576 static LLVMValueRef
577 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
578 {
579 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
580 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
581 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
582
583 return LLVMBuildAdd(ctx->builder, patch0_offset,
584 LLVMBuildMul(ctx->builder, patch_stride,
585 rel_patch_id, ""),
586 "");
587 }
588
589 static LLVMValueRef
590 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
591 {
592 LLVMValueRef patch0_patch_data_offset =
593 get_tcs_out_patch0_patch_data_offset(ctx);
594 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
595 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
596
597 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
598 LLVMBuildMul(ctx->builder, patch_stride,
599 rel_patch_id, ""),
600 "");
601 }
602
603 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
604 {
605 ud_info->sgpr_idx = *sgpr_idx;
606 ud_info->num_sgprs = num_sgprs;
607 ud_info->indirect = false;
608 ud_info->indirect_offset = 0;
609 *sgpr_idx += num_sgprs;
610 }
611
612 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
613 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
614 {
615 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
616 }
617
618
619 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
620 uint32_t indirect_offset)
621 {
622 ud_info->sgpr_idx = sgpr_idx;
623 ud_info->num_sgprs = num_sgprs;
624 ud_info->indirect = true;
625 ud_info->indirect_offset = indirect_offset;
626 }
627
628 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
629 {
630 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
631 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
632 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
633 "tess_lds");
634 }
635
636 struct user_sgpr_info {
637 bool need_ring_offsets;
638 uint8_t sgpr_count;
639 bool indirect_all_descriptor_sets;
640 };
641
642 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
643 struct user_sgpr_info *user_sgpr_info)
644 {
645 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
646
647 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
648 if (ctx->stage == MESA_SHADER_GEOMETRY ||
649 ctx->stage == MESA_SHADER_VERTEX ||
650 ctx->stage == MESA_SHADER_TESS_CTRL ||
651 ctx->stage == MESA_SHADER_TESS_EVAL ||
652 ctx->is_gs_copy_shader)
653 user_sgpr_info->need_ring_offsets = true;
654
655 if (ctx->stage == MESA_SHADER_FRAGMENT &&
656 ctx->shader_info->info.ps.needs_sample_positions)
657 user_sgpr_info->need_ring_offsets = true;
658
659 /* 2 user sgprs will nearly always be allocated for scratch/rings */
660 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
661 user_sgpr_info->sgpr_count += 2;
662 }
663
664 switch (ctx->stage) {
665 case MESA_SHADER_COMPUTE:
666 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
667 break;
668 case MESA_SHADER_FRAGMENT:
669 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
670 break;
671 case MESA_SHADER_VERTEX:
672 if (!ctx->is_gs_copy_shader) {
673 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
674 if (ctx->shader_info->info.vs.needs_draw_id) {
675 user_sgpr_info->sgpr_count += 3;
676 } else {
677 user_sgpr_info->sgpr_count += 2;
678 }
679 }
680 if (ctx->options->key.vs.as_ls)
681 user_sgpr_info->sgpr_count++;
682 break;
683 case MESA_SHADER_TESS_CTRL:
684 user_sgpr_info->sgpr_count += 4;
685 break;
686 case MESA_SHADER_TESS_EVAL:
687 user_sgpr_info->sgpr_count += 1;
688 break;
689 case MESA_SHADER_GEOMETRY:
690 user_sgpr_info->sgpr_count += 2;
691 break;
692 default:
693 break;
694 }
695
696 if (ctx->shader_info->info.needs_push_constants)
697 user_sgpr_info->sgpr_count += 2;
698
699 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
700 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
701 user_sgpr_info->sgpr_count += 2;
702 user_sgpr_info->indirect_all_descriptor_sets = true;
703 } else {
704 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
705 }
706 }
707
708 static void create_function(struct nir_to_llvm_context *ctx)
709 {
710 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
711 uint8_t user_sgpr_idx;
712 struct user_sgpr_info user_sgpr_info;
713 struct arg_info args = {};
714 LLVMValueRef desc_sets;
715
716 allocate_user_sgprs(ctx, &user_sgpr_info);
717 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
718 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
719 }
720
721 /* 1 for each descriptor set */
722 if (!user_sgpr_info.indirect_all_descriptor_sets) {
723 for (unsigned i = 0; i < num_sets; ++i) {
724 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
725 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
726 }
727 }
728 } else
729 add_user_sgpr_array_argument(&args, const_array(const_array(ctx->i8, 1024 * 1024), 32), &desc_sets);
730
731 if (ctx->shader_info->info.needs_push_constants) {
732 /* 1 for push constants and dynamic descriptors */
733 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
734 }
735
736 switch (ctx->stage) {
737 case MESA_SHADER_COMPUTE:
738 if (ctx->shader_info->info.cs.grid_components_used)
739 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
740 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
741 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
742 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
743 break;
744 case MESA_SHADER_VERTEX:
745 if (!ctx->is_gs_copy_shader) {
746 if (ctx->shader_info->info.vs.has_vertex_buffers)
747 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
748 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.base_vertex); // base vertex
749 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.start_instance);// start instance
750 if (ctx->shader_info->info.vs.needs_draw_id)
751 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.draw_id); // draw id
752 }
753 if (ctx->options->key.vs.as_es)
754 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
755 else if (ctx->options->key.vs.as_ls)
756 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
757 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
758 if (!ctx->is_gs_copy_shader) {
759 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
760 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
761 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
762 }
763 break;
764 case MESA_SHADER_TESS_CTRL:
765 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
766 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
767 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
768 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
769 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
770 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
771 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
772 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
773 break;
774 case MESA_SHADER_TESS_EVAL:
775 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
776 if (ctx->options->key.tes.as_es) {
777 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
778 add_sgpr_argument(&args, ctx->i32, NULL); //
779 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
780 } else {
781 add_sgpr_argument(&args, ctx->i32, NULL); //
782 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
783 }
784 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
785 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
786 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
787 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
788 break;
789 case MESA_SHADER_GEOMETRY:
790 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
791 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
792 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
793 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
794 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
795 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
796 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
797 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
798 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
799 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
800 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
801 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
802 break;
803 case MESA_SHADER_FRAGMENT:
804 if (ctx->shader_info->info.ps.needs_sample_positions)
805 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
806 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
807 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
808 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
809 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
810 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
811 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
812 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
813 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
814 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
815 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[0]); /* pos x float */
816 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[1]); /* pos y float */
817 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[2]); /* pos z float */
818 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[3]); /* pos w float */
819 add_vgpr_argument(&args, ctx->i32, &ctx->front_face); /* front face */
820 add_vgpr_argument(&args, ctx->i32, &ctx->ancillary); /* ancillary */
821 add_vgpr_argument(&args, ctx->i32, &ctx->sample_coverage); /* sample coverage */
822 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
823 break;
824 default:
825 unreachable("Shader stage not implemented");
826 }
827
828 ctx->main_function = create_llvm_function(
829 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
830 ctx->max_workgroup_size,
831 ctx->options->unsafe_math);
832 set_llvm_calling_convention(ctx->main_function, ctx->stage);
833
834
835 ctx->shader_info->num_input_vgprs = 0;
836 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs =
837 ctx->options->supports_spill ? 2 : 0;
838
839 ctx->shader_info->num_user_sgprs += args.num_user_sgprs_used;
840 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
841
842 if (ctx->stage != MESA_SHADER_FRAGMENT)
843 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
844
845 assign_arguments(ctx->main_function, &args);
846
847 user_sgpr_idx = 0;
848
849 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
850 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
851 if (ctx->options->supports_spill) {
852 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
853 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
854 NULL, 0, AC_FUNC_ATTR_READNONE);
855 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
856 const_array(ctx->v4i32, 16), "");
857 }
858 }
859
860 if (!user_sgpr_info.indirect_all_descriptor_sets) {
861 for (unsigned i = 0; i < num_sets; ++i) {
862 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
863 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
864 } else
865 ctx->descriptor_sets[i] = NULL;
866 }
867 } else {
868 uint32_t desc_sgpr_idx = user_sgpr_idx;
869 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
870
871 for (unsigned i = 0; i < num_sets; ++i) {
872 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
873 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
874 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
875
876 } else
877 ctx->descriptor_sets[i] = NULL;
878 }
879 ctx->shader_info->need_indirect_descriptor_sets = true;
880 }
881
882 if (ctx->shader_info->info.needs_push_constants) {
883 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
884 }
885
886 switch (ctx->stage) {
887 case MESA_SHADER_COMPUTE:
888 if (ctx->shader_info->info.cs.grid_components_used) {
889 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
890 }
891 break;
892 case MESA_SHADER_VERTEX:
893 if (!ctx->is_gs_copy_shader) {
894 if (ctx->shader_info->info.vs.has_vertex_buffers) {
895 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
896 }
897 unsigned vs_num = 2;
898 if (ctx->shader_info->info.vs.needs_draw_id)
899 vs_num++;
900
901 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
902 }
903 if (ctx->options->key.vs.as_ls) {
904 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
905 }
906 if (ctx->options->key.vs.as_ls)
907 declare_tess_lds(ctx);
908 break;
909 case MESA_SHADER_TESS_CTRL:
910 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
911 declare_tess_lds(ctx);
912 break;
913 case MESA_SHADER_TESS_EVAL:
914 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
915 break;
916 case MESA_SHADER_GEOMETRY:
917 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
918 break;
919 case MESA_SHADER_FRAGMENT:
920 if (ctx->shader_info->info.ps.needs_sample_positions) {
921 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
922 }
923 break;
924 default:
925 unreachable("Shader stage not implemented");
926 }
927 }
928
929 static void setup_types(struct nir_to_llvm_context *ctx)
930 {
931 LLVMValueRef args[4];
932
933 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
934 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
935 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
936 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
937 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
938 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
939 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
940 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
941 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
942 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
943 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
944 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
945 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
946 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
947 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
948
949 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
950 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
951 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
952 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
953 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
954 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
955
956 args[0] = ctx->f32zero;
957 args[1] = ctx->f32zero;
958 args[2] = ctx->f32zero;
959 args[3] = ctx->f32one;
960 ctx->v4f32empty = LLVMConstVector(args, 4);
961
962 ctx->uniform_md_kind =
963 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
964 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
965
966 args[0] = LLVMConstReal(ctx->f32, 2.5);
967 }
968
969 static int get_llvm_num_components(LLVMValueRef value)
970 {
971 LLVMTypeRef type = LLVMTypeOf(value);
972 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
973 ? LLVMGetVectorSize(type)
974 : 1;
975 return num_components;
976 }
977
978 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
979 LLVMValueRef value,
980 int index)
981 {
982 int count = get_llvm_num_components(value);
983
984 assert(index < count);
985 if (count == 1)
986 return value;
987
988 return LLVMBuildExtractElement(ac->builder, value,
989 LLVMConstInt(ac->i32, index, false), "");
990 }
991
992 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
993 LLVMValueRef value, unsigned count)
994 {
995 unsigned num_components = get_llvm_num_components(value);
996 if (count == num_components)
997 return value;
998
999 LLVMValueRef masks[] = {
1000 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1001 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1002
1003 if (count == 1)
1004 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1005 "");
1006
1007 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1008 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1009 }
1010
1011 static void
1012 build_store_values_extended(struct ac_llvm_context *ac,
1013 LLVMValueRef *values,
1014 unsigned value_count,
1015 unsigned value_stride,
1016 LLVMValueRef vec)
1017 {
1018 LLVMBuilderRef builder = ac->builder;
1019 unsigned i;
1020
1021 if (value_count == 1) {
1022 LLVMBuildStore(builder, vec, values[0]);
1023 return;
1024 }
1025
1026 for (i = 0; i < value_count; i++) {
1027 LLVMValueRef ptr = values[i * value_stride];
1028 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1029 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1030 LLVMBuildStore(builder, value, ptr);
1031 }
1032 }
1033
1034 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1035 const nir_ssa_def *def)
1036 {
1037 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1038 if (def->num_components > 1) {
1039 type = LLVMVectorType(type, def->num_components);
1040 }
1041 return type;
1042 }
1043
1044 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1045 {
1046 assert(src.is_ssa);
1047 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1048 return (LLVMValueRef)entry->data;
1049 }
1050
1051
1052 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1053 const struct nir_block *b)
1054 {
1055 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1056 return (LLVMBasicBlockRef)entry->data;
1057 }
1058
1059 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1060 nir_alu_src src,
1061 unsigned num_components)
1062 {
1063 LLVMValueRef value = get_src(ctx, src.src);
1064 bool need_swizzle = false;
1065
1066 assert(value);
1067 LLVMTypeRef type = LLVMTypeOf(value);
1068 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1069 ? LLVMGetVectorSize(type)
1070 : 1;
1071
1072 for (unsigned i = 0; i < num_components; ++i) {
1073 assert(src.swizzle[i] < src_components);
1074 if (src.swizzle[i] != i)
1075 need_swizzle = true;
1076 }
1077
1078 if (need_swizzle || num_components != src_components) {
1079 LLVMValueRef masks[] = {
1080 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1081 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1082 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1083 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1084
1085 if (src_components > 1 && num_components == 1) {
1086 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1087 masks[0], "");
1088 } else if (src_components == 1 && num_components > 1) {
1089 LLVMValueRef values[] = {value, value, value, value};
1090 value = ac_build_gather_values(&ctx->ac, values, num_components);
1091 } else {
1092 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1093 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1094 swizzle, "");
1095 }
1096 }
1097 assert(!src.negate);
1098 assert(!src.abs);
1099 return value;
1100 }
1101
1102 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1103 LLVMIntPredicate pred, LLVMValueRef src0,
1104 LLVMValueRef src1)
1105 {
1106 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1107 return LLVMBuildSelect(ctx->builder, result,
1108 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1109 LLVMConstInt(ctx->i32, 0, false), "");
1110 }
1111
1112 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1113 LLVMRealPredicate pred, LLVMValueRef src0,
1114 LLVMValueRef src1)
1115 {
1116 LLVMValueRef result;
1117 src0 = to_float(ctx, src0);
1118 src1 = to_float(ctx, src1);
1119 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1120 return LLVMBuildSelect(ctx->builder, result,
1121 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1122 LLVMConstInt(ctx->i32, 0, false), "");
1123 }
1124
1125 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1126 const char *intrin,
1127 LLVMTypeRef result_type,
1128 LLVMValueRef src0)
1129 {
1130 char name[64];
1131 LLVMValueRef params[] = {
1132 to_float(ctx, src0),
1133 };
1134
1135 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1136 get_elem_bits(ctx, result_type));
1137 assert(length < sizeof(name));
1138 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1139 }
1140
1141 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1142 const char *intrin,
1143 LLVMTypeRef result_type,
1144 LLVMValueRef src0, LLVMValueRef src1)
1145 {
1146 char name[64];
1147 LLVMValueRef params[] = {
1148 to_float(ctx, src0),
1149 to_float(ctx, src1),
1150 };
1151
1152 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1153 get_elem_bits(ctx, result_type));
1154 assert(length < sizeof(name));
1155 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1156 }
1157
1158 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1159 const char *intrin,
1160 LLVMTypeRef result_type,
1161 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1162 {
1163 char name[64];
1164 LLVMValueRef params[] = {
1165 to_float(ctx, src0),
1166 to_float(ctx, src1),
1167 to_float(ctx, src2),
1168 };
1169
1170 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1171 get_elem_bits(ctx, result_type));
1172 assert(length < sizeof(name));
1173 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1174 }
1175
1176 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1177 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1178 {
1179 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1180 ctx->i32_0, "");
1181 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1182 }
1183
1184 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1185 LLVMValueRef src0)
1186 {
1187 LLVMValueRef params[2] = {
1188 src0,
1189
1190 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1191 * add special code to check for x=0. The reason is that
1192 * the LLVM behavior for x=0 is different from what we
1193 * need here.
1194 *
1195 * The hardware already implements the correct behavior.
1196 */
1197 LLVMConstInt(ctx->i1, 1, false),
1198 };
1199 return ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1200 }
1201
1202 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1203 LLVMValueRef src0)
1204 {
1205 return ac_build_imsb(ctx, src0, ctx->i32);
1206 }
1207
1208 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1209 LLVMValueRef src0)
1210 {
1211 return ac_build_umsb(ctx, src0, ctx->i32);
1212 }
1213
1214 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1215 LLVMIntPredicate pred,
1216 LLVMValueRef src0, LLVMValueRef src1)
1217 {
1218 return LLVMBuildSelect(ctx->builder,
1219 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1220 src0,
1221 src1, "");
1222
1223 }
1224 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1225 LLVMValueRef src0)
1226 {
1227 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1228 LLVMBuildNeg(ctx->builder, src0, ""));
1229 }
1230
1231 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1232 LLVMValueRef src0)
1233 {
1234 LLVMValueRef cmp, val;
1235
1236 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1237 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1238 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1239 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1240 return val;
1241 }
1242
1243 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1244 LLVMValueRef src0)
1245 {
1246 LLVMValueRef cmp, val;
1247
1248 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1249 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1250 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1251 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1252 return val;
1253 }
1254
1255 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1256 LLVMValueRef src0)
1257 {
1258 const char *intr = "llvm.floor.f32";
1259 LLVMValueRef fsrc0 = to_float(ctx, src0);
1260 LLVMValueRef params[] = {
1261 fsrc0,
1262 };
1263 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1264 ctx->f32, params, 1,
1265 AC_FUNC_ATTR_READNONE);
1266 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1267 }
1268
1269 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1270 const char *intrin,
1271 LLVMValueRef src0, LLVMValueRef src1)
1272 {
1273 LLVMTypeRef ret_type;
1274 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1275 LLVMValueRef res;
1276 LLVMValueRef params[] = { src0, src1 };
1277 ret_type = LLVMStructTypeInContext(ctx->context, types,
1278 2, true);
1279
1280 res = ac_build_intrinsic(ctx, intrin, ret_type,
1281 params, 2, AC_FUNC_ATTR_READNONE);
1282
1283 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1284 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1285 return res;
1286 }
1287
1288 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1289 LLVMValueRef src0)
1290 {
1291 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1292 }
1293
1294 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1295 LLVMValueRef src0)
1296 {
1297 src0 = to_float(ctx, src0);
1298 return LLVMBuildSExt(ctx->builder,
1299 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1300 ctx->i32, "");
1301 }
1302
1303 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1304 LLVMValueRef src0)
1305 {
1306 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1307 }
1308
1309 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1310 LLVMValueRef src0)
1311 {
1312 return LLVMBuildSExt(ctx->builder,
1313 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1314 ctx->i32, "");
1315 }
1316
1317 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1318 LLVMValueRef src0)
1319 {
1320 LLVMValueRef result;
1321 LLVMValueRef cond;
1322
1323 src0 = to_float(&ctx->ac, src0);
1324 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1325
1326 /* TODO SI/CIK options here */
1327 if (ctx->options->chip_class >= VI) {
1328 LLVMValueRef args[2];
1329 /* Check if the result is a denormal - and flush to 0 if so. */
1330 args[0] = result;
1331 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1332 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1333 }
1334
1335 /* need to convert back up to f32 */
1336 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1337
1338 if (ctx->options->chip_class >= VI)
1339 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1340
1341 return result;
1342 }
1343
1344 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1345 LLVMValueRef src0, LLVMValueRef src1)
1346 {
1347 LLVMValueRef dst64, result;
1348 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1349 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1350
1351 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1352 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1353 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1354 return result;
1355 }
1356
1357 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1358 LLVMValueRef src0, LLVMValueRef src1)
1359 {
1360 LLVMValueRef dst64, result;
1361 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1362 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1363
1364 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1365 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1366 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1367 return result;
1368 }
1369
1370 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1371 bool is_signed,
1372 const LLVMValueRef srcs[3])
1373 {
1374 LLVMValueRef result;
1375 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1376
1377 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1378 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1379 return result;
1380 }
1381
1382 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1383 LLVMValueRef src0, LLVMValueRef src1,
1384 LLVMValueRef src2, LLVMValueRef src3)
1385 {
1386 LLVMValueRef bfi_args[3], result;
1387
1388 bfi_args[0] = LLVMBuildShl(ctx->builder,
1389 LLVMBuildSub(ctx->builder,
1390 LLVMBuildShl(ctx->builder,
1391 ctx->i32_1,
1392 src3, ""),
1393 ctx->i32_1, ""),
1394 src2, "");
1395 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1396 bfi_args[2] = src0;
1397
1398 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1399
1400 /* Calculate:
1401 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1402 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1403 */
1404 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1405 LLVMBuildAnd(ctx->builder, bfi_args[0],
1406 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1407
1408 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1409 return result;
1410 }
1411
1412 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1413 LLVMValueRef src0)
1414 {
1415 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1416 int i;
1417 LLVMValueRef comp[2];
1418
1419 src0 = to_float(ctx, src0);
1420 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1421 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1422 for (i = 0; i < 2; i++) {
1423 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1424 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1425 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1426 }
1427
1428 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1429 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1430
1431 return comp[0];
1432 }
1433
1434 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1435 LLVMValueRef src0)
1436 {
1437 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1438 LLVMValueRef temps[2], result, val;
1439 int i;
1440
1441 for (i = 0; i < 2; i++) {
1442 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1443 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1444 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1445 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1446 }
1447
1448 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1449 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1450 ctx->i32_0, "");
1451 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1452 ctx->i32_1, "");
1453 return result;
1454 }
1455
1456 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1457 nir_op op,
1458 LLVMValueRef src0)
1459 {
1460 unsigned mask;
1461 int idx;
1462 LLVMValueRef result;
1463
1464 if (!ctx->lds && !ctx->has_ds_bpermute)
1465 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1466 LLVMArrayType(ctx->i32, 64),
1467 "ddxy_lds", LOCAL_ADDR_SPACE);
1468
1469 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1470 mask = AC_TID_MASK_LEFT;
1471 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1472 mask = AC_TID_MASK_TOP;
1473 else
1474 mask = AC_TID_MASK_TOP_LEFT;
1475
1476 /* for DDX we want to next X pixel, DDY next Y pixel. */
1477 if (op == nir_op_fddx_fine ||
1478 op == nir_op_fddx_coarse ||
1479 op == nir_op_fddx)
1480 idx = 1;
1481 else
1482 idx = 2;
1483
1484 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1485 mask, idx, ctx->lds,
1486 src0);
1487 return result;
1488 }
1489
1490 /*
1491 * this takes an I,J coordinate pair,
1492 * and works out the X and Y derivatives.
1493 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1494 */
1495 static LLVMValueRef emit_ddxy_interp(
1496 struct nir_to_llvm_context *ctx,
1497 LLVMValueRef interp_ij)
1498 {
1499 LLVMValueRef result[4], a;
1500 unsigned i;
1501
1502 for (i = 0; i < 2; i++) {
1503 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1504 LLVMConstInt(ctx->i32, i, false), "");
1505 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1506 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1507 }
1508 return ac_build_gather_values(&ctx->ac, result, 4);
1509 }
1510
1511 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1512 {
1513 LLVMValueRef src[4], result = NULL;
1514 unsigned num_components = instr->dest.dest.ssa.num_components;
1515 unsigned src_components;
1516 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1517
1518 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1519 switch (instr->op) {
1520 case nir_op_vec2:
1521 case nir_op_vec3:
1522 case nir_op_vec4:
1523 src_components = 1;
1524 break;
1525 case nir_op_pack_half_2x16:
1526 src_components = 2;
1527 break;
1528 case nir_op_unpack_half_2x16:
1529 src_components = 1;
1530 break;
1531 default:
1532 src_components = num_components;
1533 break;
1534 }
1535 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1536 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1537
1538 switch (instr->op) {
1539 case nir_op_fmov:
1540 case nir_op_imov:
1541 result = src[0];
1542 break;
1543 case nir_op_fneg:
1544 src[0] = to_float(&ctx->ac, src[0]);
1545 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1546 break;
1547 case nir_op_ineg:
1548 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1549 break;
1550 case nir_op_inot:
1551 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1552 break;
1553 case nir_op_iadd:
1554 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1555 break;
1556 case nir_op_fadd:
1557 src[0] = to_float(&ctx->ac, src[0]);
1558 src[1] = to_float(&ctx->ac, src[1]);
1559 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1560 break;
1561 case nir_op_fsub:
1562 src[0] = to_float(&ctx->ac, src[0]);
1563 src[1] = to_float(&ctx->ac, src[1]);
1564 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1565 break;
1566 case nir_op_isub:
1567 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1568 break;
1569 case nir_op_imul:
1570 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1571 break;
1572 case nir_op_imod:
1573 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1574 break;
1575 case nir_op_umod:
1576 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1577 break;
1578 case nir_op_fmod:
1579 src[0] = to_float(&ctx->ac, src[0]);
1580 src[1] = to_float(&ctx->ac, src[1]);
1581 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1582 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1583 to_float_type(&ctx->ac, def_type), result);
1584 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1585 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1586 break;
1587 case nir_op_frem:
1588 src[0] = to_float(&ctx->ac, src[0]);
1589 src[1] = to_float(&ctx->ac, src[1]);
1590 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1591 break;
1592 case nir_op_irem:
1593 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1594 break;
1595 case nir_op_idiv:
1596 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1597 break;
1598 case nir_op_udiv:
1599 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1600 break;
1601 case nir_op_fmul:
1602 src[0] = to_float(&ctx->ac, src[0]);
1603 src[1] = to_float(&ctx->ac, src[1]);
1604 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1605 break;
1606 case nir_op_fdiv:
1607 src[0] = to_float(&ctx->ac, src[0]);
1608 src[1] = to_float(&ctx->ac, src[1]);
1609 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1610 break;
1611 case nir_op_frcp:
1612 src[0] = to_float(&ctx->ac, src[0]);
1613 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1614 break;
1615 case nir_op_iand:
1616 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1617 break;
1618 case nir_op_ior:
1619 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1620 break;
1621 case nir_op_ixor:
1622 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1623 break;
1624 case nir_op_ishl:
1625 result = LLVMBuildShl(ctx->ac.builder, src[0],
1626 LLVMBuildZExt(ctx->ac.builder, src[1],
1627 LLVMTypeOf(src[0]), ""),
1628 "");
1629 break;
1630 case nir_op_ishr:
1631 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1632 LLVMBuildZExt(ctx->ac.builder, src[1],
1633 LLVMTypeOf(src[0]), ""),
1634 "");
1635 break;
1636 case nir_op_ushr:
1637 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1638 LLVMBuildZExt(ctx->ac.builder, src[1],
1639 LLVMTypeOf(src[0]), ""),
1640 "");
1641 break;
1642 case nir_op_ilt:
1643 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1644 break;
1645 case nir_op_ine:
1646 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1647 break;
1648 case nir_op_ieq:
1649 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1650 break;
1651 case nir_op_ige:
1652 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1653 break;
1654 case nir_op_ult:
1655 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1656 break;
1657 case nir_op_uge:
1658 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1659 break;
1660 case nir_op_feq:
1661 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1662 break;
1663 case nir_op_fne:
1664 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1665 break;
1666 case nir_op_flt:
1667 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1668 break;
1669 case nir_op_fge:
1670 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1671 break;
1672 case nir_op_fabs:
1673 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1674 to_float_type(&ctx->ac, def_type), src[0]);
1675 break;
1676 case nir_op_iabs:
1677 result = emit_iabs(&ctx->ac, src[0]);
1678 break;
1679 case nir_op_imax:
1680 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1681 break;
1682 case nir_op_imin:
1683 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1684 break;
1685 case nir_op_umax:
1686 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1687 break;
1688 case nir_op_umin:
1689 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1690 break;
1691 case nir_op_isign:
1692 result = emit_isign(&ctx->ac, src[0]);
1693 break;
1694 case nir_op_fsign:
1695 src[0] = to_float(&ctx->ac, src[0]);
1696 result = emit_fsign(&ctx->ac, src[0]);
1697 break;
1698 case nir_op_ffloor:
1699 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1700 to_float_type(&ctx->ac, def_type), src[0]);
1701 break;
1702 case nir_op_ftrunc:
1703 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1704 to_float_type(&ctx->ac, def_type), src[0]);
1705 break;
1706 case nir_op_fceil:
1707 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1708 to_float_type(&ctx->ac, def_type), src[0]);
1709 break;
1710 case nir_op_fround_even:
1711 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1712 to_float_type(&ctx->ac, def_type),src[0]);
1713 break;
1714 case nir_op_ffract:
1715 result = emit_ffract(&ctx->ac, src[0]);
1716 break;
1717 case nir_op_fsin:
1718 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1719 to_float_type(&ctx->ac, def_type), src[0]);
1720 break;
1721 case nir_op_fcos:
1722 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1723 to_float_type(&ctx->ac, def_type), src[0]);
1724 break;
1725 case nir_op_fsqrt:
1726 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1727 to_float_type(&ctx->ac, def_type), src[0]);
1728 break;
1729 case nir_op_fexp2:
1730 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1731 to_float_type(&ctx->ac, def_type), src[0]);
1732 break;
1733 case nir_op_flog2:
1734 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1735 to_float_type(&ctx->ac, def_type), src[0]);
1736 break;
1737 case nir_op_frsq:
1738 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1739 to_float_type(&ctx->ac, def_type), src[0]);
1740 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1741 break;
1742 case nir_op_fpow:
1743 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1744 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1745 break;
1746 case nir_op_fmax:
1747 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1748 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1749 if (instr->dest.dest.ssa.bit_size == 32)
1750 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1751 to_float_type(&ctx->ac, def_type),
1752 result);
1753 break;
1754 case nir_op_fmin:
1755 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1756 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1757 if (instr->dest.dest.ssa.bit_size == 32)
1758 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1759 to_float_type(&ctx->ac, def_type),
1760 result);
1761 break;
1762 case nir_op_ffma:
1763 result = emit_intrin_3f_param(&ctx->ac, "llvm.fma",
1764 to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1765 break;
1766 case nir_op_ibitfield_extract:
1767 result = emit_bitfield_extract(&ctx->ac, true, src);
1768 break;
1769 case nir_op_ubitfield_extract:
1770 result = emit_bitfield_extract(&ctx->ac, false, src);
1771 break;
1772 case nir_op_bitfield_insert:
1773 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1774 break;
1775 case nir_op_bitfield_reverse:
1776 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1777 break;
1778 case nir_op_bit_count:
1779 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1780 break;
1781 case nir_op_vec2:
1782 case nir_op_vec3:
1783 case nir_op_vec4:
1784 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1785 src[i] = to_integer(&ctx->ac, src[i]);
1786 result = ac_build_gather_values(&ctx->ac, src, num_components);
1787 break;
1788 case nir_op_f2i32:
1789 case nir_op_f2i64:
1790 src[0] = to_float(&ctx->ac, src[0]);
1791 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1792 break;
1793 case nir_op_f2u32:
1794 case nir_op_f2u64:
1795 src[0] = to_float(&ctx->ac, src[0]);
1796 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1797 break;
1798 case nir_op_i2f32:
1799 case nir_op_i2f64:
1800 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1801 break;
1802 case nir_op_u2f32:
1803 case nir_op_u2f64:
1804 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1805 break;
1806 case nir_op_f2f64:
1807 result = LLVMBuildFPExt(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1808 break;
1809 case nir_op_f2f32:
1810 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1811 break;
1812 case nir_op_u2u32:
1813 case nir_op_u2u64:
1814 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1815 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1816 else
1817 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1818 break;
1819 case nir_op_i2i32:
1820 case nir_op_i2i64:
1821 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1822 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1823 else
1824 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1825 break;
1826 case nir_op_bcsel:
1827 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1828 break;
1829 case nir_op_find_lsb:
1830 result = emit_find_lsb(&ctx->ac, src[0]);
1831 break;
1832 case nir_op_ufind_msb:
1833 result = emit_ufind_msb(&ctx->ac, src[0]);
1834 break;
1835 case nir_op_ifind_msb:
1836 result = emit_ifind_msb(&ctx->ac, src[0]);
1837 break;
1838 case nir_op_uadd_carry:
1839 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1840 break;
1841 case nir_op_usub_borrow:
1842 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1843 break;
1844 case nir_op_b2f:
1845 result = emit_b2f(&ctx->ac, src[0]);
1846 break;
1847 case nir_op_f2b:
1848 result = emit_f2b(&ctx->ac, src[0]);
1849 break;
1850 case nir_op_b2i:
1851 result = emit_b2i(&ctx->ac, src[0]);
1852 break;
1853 case nir_op_i2b:
1854 result = emit_i2b(&ctx->ac, src[0]);
1855 break;
1856 case nir_op_fquantize2f16:
1857 result = emit_f2f16(ctx->nctx, src[0]);
1858 break;
1859 case nir_op_umul_high:
1860 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1861 break;
1862 case nir_op_imul_high:
1863 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1864 break;
1865 case nir_op_pack_half_2x16:
1866 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1867 break;
1868 case nir_op_unpack_half_2x16:
1869 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1870 break;
1871 case nir_op_fddx:
1872 case nir_op_fddy:
1873 case nir_op_fddx_fine:
1874 case nir_op_fddy_fine:
1875 case nir_op_fddx_coarse:
1876 case nir_op_fddy_coarse:
1877 result = emit_ddxy(ctx->nctx, instr->op, src[0]);
1878 break;
1879
1880 case nir_op_unpack_64_2x32_split_x: {
1881 assert(instr->src[0].src.ssa->num_components == 1);
1882 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1883 LLVMVectorType(ctx->ac.i32, 2),
1884 "");
1885 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1886 ctx->ac.i32_0, "");
1887 break;
1888 }
1889
1890 case nir_op_unpack_64_2x32_split_y: {
1891 assert(instr->src[0].src.ssa->num_components == 1);
1892 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1893 LLVMVectorType(ctx->ac.i32, 2),
1894 "");
1895 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1896 ctx->ac.i32_0, "");
1897 break;
1898 }
1899
1900 case nir_op_pack_64_2x32_split: {
1901 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
1902 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1903 src[0], ctx->ac.i32_0, "");
1904 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1905 src[1], ctx->ac.i32_1, "");
1906 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1907 break;
1908 }
1909
1910 default:
1911 fprintf(stderr, "Unknown NIR alu instr: ");
1912 nir_print_instr(&instr->instr, stderr);
1913 fprintf(stderr, "\n");
1914 abort();
1915 }
1916
1917 if (result) {
1918 assert(instr->dest.dest.is_ssa);
1919 result = to_integer(&ctx->ac, result);
1920 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1921 result);
1922 }
1923 }
1924
1925 static void visit_load_const(struct ac_nir_context *ctx,
1926 const nir_load_const_instr *instr)
1927 {
1928 LLVMValueRef values[4], value = NULL;
1929 LLVMTypeRef element_type =
1930 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1931
1932 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1933 switch (instr->def.bit_size) {
1934 case 32:
1935 values[i] = LLVMConstInt(element_type,
1936 instr->value.u32[i], false);
1937 break;
1938 case 64:
1939 values[i] = LLVMConstInt(element_type,
1940 instr->value.u64[i], false);
1941 break;
1942 default:
1943 fprintf(stderr,
1944 "unsupported nir load_const bit_size: %d\n",
1945 instr->def.bit_size);
1946 abort();
1947 }
1948 }
1949 if (instr->def.num_components > 1) {
1950 value = LLVMConstVector(values, instr->def.num_components);
1951 } else
1952 value = values[0];
1953
1954 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1955 }
1956
1957 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1958 LLVMTypeRef type)
1959 {
1960 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1961 return LLVMBuildBitCast(ctx->builder, ptr,
1962 LLVMPointerType(type, addr_space), "");
1963 }
1964
1965 static LLVMValueRef
1966 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1967 {
1968 LLVMValueRef size =
1969 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1970 LLVMConstInt(ctx->ac.i32, 2, false), "");
1971
1972 /* VI only */
1973 if (ctx->abi->chip_class >= VI && in_elements) {
1974 /* On VI, the descriptor contains the size in bytes,
1975 * but TXQ must return the size in elements.
1976 * The stride is always non-zero for resources using TXQ.
1977 */
1978 LLVMValueRef stride =
1979 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1980 LLVMConstInt(ctx->ac.i32, 1, false), "");
1981 stride = LLVMBuildLShr(ctx->ac.builder, stride,
1982 LLVMConstInt(ctx->ac.i32, 16, false), "");
1983 stride = LLVMBuildAnd(ctx->ac.builder, stride,
1984 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
1985
1986 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
1987 }
1988 return size;
1989 }
1990
1991 /**
1992 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1993 * intrinsic names).
1994 */
1995 static void build_int_type_name(
1996 LLVMTypeRef type,
1997 char *buf, unsigned bufsize)
1998 {
1999 assert(bufsize >= 6);
2000
2001 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2002 snprintf(buf, bufsize, "v%ui32",
2003 LLVMGetVectorSize(type));
2004 else
2005 strcpy(buf, "i32");
2006 }
2007
2008 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2009 struct ac_image_args *args,
2010 const nir_tex_instr *instr)
2011 {
2012 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2013 LLVMValueRef coord = args->addr;
2014 LLVMValueRef half_texel[2];
2015 LLVMValueRef compare_cube_wa;
2016 LLVMValueRef result;
2017 int c;
2018 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2019
2020 //TODO Rect
2021 {
2022 struct ac_image_args txq_args = { 0 };
2023
2024 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2025 txq_args.opcode = ac_image_get_resinfo;
2026 txq_args.dmask = 0xf;
2027 txq_args.addr = ctx->i32_0;
2028 txq_args.resource = args->resource;
2029 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2030
2031 for (c = 0; c < 2; c++) {
2032 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2033 LLVMConstInt(ctx->i32, c, false), "");
2034 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2035 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2036 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2037 LLVMConstReal(ctx->f32, -0.5), "");
2038 }
2039 }
2040
2041 LLVMValueRef orig_coords = args->addr;
2042
2043 for (c = 0; c < 2; c++) {
2044 LLVMValueRef tmp;
2045 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2046 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2047 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2048 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2049 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2050 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2051 }
2052
2053
2054 /*
2055 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2056 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2057 * workaround by sampling using a scaled type and converting.
2058 * This is taken from amdgpu-pro shaders.
2059 */
2060 /* NOTE this produces some ugly code compared to amdgpu-pro,
2061 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2062 * and then reads them back. -pro generates two selects,
2063 * one s_cmp for the descriptor rewriting
2064 * one v_cmp for the coordinate and result changes.
2065 */
2066 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2067 LLVMValueRef tmp, tmp2;
2068
2069 /* workaround 8/8/8/8 uint/sint cube gather bug */
2070 /* first detect it then change to a scaled read and f2i */
2071 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2072 tmp2 = tmp;
2073
2074 /* extract the DATA_FORMAT */
2075 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2076 LLVMConstInt(ctx->i32, 6, false), false);
2077
2078 /* is the DATA_FORMAT == 8_8_8_8 */
2079 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2080
2081 if (stype == GLSL_TYPE_UINT)
2082 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2083 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2084 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2085 else
2086 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2087 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2088 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2089
2090 /* replace the NUM FORMAT in the descriptor */
2091 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2092 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2093
2094 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2095
2096 /* don't modify the coordinates for this case */
2097 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2098 }
2099 args->addr = coord;
2100 result = ac_build_image_opcode(ctx, args);
2101
2102 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2103 LLVMValueRef tmp, tmp2;
2104
2105 /* if the cube workaround is in place, f2i the result. */
2106 for (c = 0; c < 4; c++) {
2107 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2108 if (stype == GLSL_TYPE_UINT)
2109 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2110 else
2111 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2112 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2113 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2114 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2115 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2116 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2117 }
2118 }
2119 return result;
2120 }
2121
2122 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2123 const nir_tex_instr *instr,
2124 bool lod_is_zero,
2125 struct ac_image_args *args)
2126 {
2127 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2128 return ac_build_buffer_load_format(&ctx->ac,
2129 args->resource,
2130 args->addr,
2131 LLVMConstInt(ctx->ac.i32, 0, false),
2132 true);
2133 }
2134
2135 args->opcode = ac_image_sample;
2136 args->compare = instr->is_shadow;
2137
2138 switch (instr->op) {
2139 case nir_texop_txf:
2140 case nir_texop_txf_ms:
2141 case nir_texop_samples_identical:
2142 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2143 args->compare = false;
2144 args->offset = false;
2145 break;
2146 case nir_texop_txb:
2147 args->bias = true;
2148 break;
2149 case nir_texop_txl:
2150 if (lod_is_zero)
2151 args->level_zero = true;
2152 else
2153 args->lod = true;
2154 break;
2155 case nir_texop_txs:
2156 case nir_texop_query_levels:
2157 args->opcode = ac_image_get_resinfo;
2158 break;
2159 case nir_texop_tex:
2160 if (ctx->stage != MESA_SHADER_FRAGMENT)
2161 args->level_zero = true;
2162 break;
2163 case nir_texop_txd:
2164 args->deriv = true;
2165 break;
2166 case nir_texop_tg4:
2167 args->opcode = ac_image_gather4;
2168 args->level_zero = true;
2169 break;
2170 case nir_texop_lod:
2171 args->opcode = ac_image_get_lod;
2172 args->compare = false;
2173 args->offset = false;
2174 break;
2175 default:
2176 break;
2177 }
2178
2179 if (instr->op == nir_texop_tg4) {
2180 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2181 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2182 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2183 }
2184 }
2185 return ac_build_image_opcode(&ctx->ac, args);
2186 }
2187
2188 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2189 nir_intrinsic_instr *instr)
2190 {
2191 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2192 unsigned desc_set = nir_intrinsic_desc_set(instr);
2193 unsigned binding = nir_intrinsic_binding(instr);
2194 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2195 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2196 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2197 unsigned base_offset = layout->binding[binding].offset;
2198 LLVMValueRef offset, stride;
2199
2200 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2201 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2202 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2203 layout->binding[binding].dynamic_offset_offset;
2204 desc_ptr = ctx->push_constants;
2205 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2206 stride = LLVMConstInt(ctx->i32, 16, false);
2207 } else
2208 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2209
2210 offset = LLVMConstInt(ctx->i32, base_offset, false);
2211 index = LLVMBuildMul(ctx->builder, index, stride, "");
2212 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2213
2214 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2215 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2216 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2217
2218 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2219 }
2220
2221 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2222 nir_intrinsic_instr *instr)
2223 {
2224 LLVMValueRef ptr, addr;
2225
2226 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2227 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2228
2229 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2230 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2231
2232 return LLVMBuildLoad(ctx->builder, ptr, "");
2233 }
2234
2235 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2236 const nir_intrinsic_instr *instr)
2237 {
2238 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2239
2240 return get_buffer_size(ctx, desc, false);
2241 }
2242 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2243 nir_intrinsic_instr *instr)
2244 {
2245 const char *store_name;
2246 LLVMValueRef src_data = get_src(ctx->nir, instr->src[0]);
2247 LLVMTypeRef data_type = ctx->f32;
2248 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2249 int components_32bit = elem_size_mult * instr->num_components;
2250 unsigned writemask = nir_intrinsic_write_mask(instr);
2251 LLVMValueRef base_data, base_offset;
2252 LLVMValueRef params[6];
2253
2254 if (ctx->stage == MESA_SHADER_FRAGMENT)
2255 ctx->shader_info->fs.writes_memory = true;
2256
2257 params[1] = get_src(ctx->nir, instr->src[1]);
2258 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2259 params[4] = ctx->i1false; /* glc */
2260 params[5] = ctx->i1false; /* slc */
2261
2262 if (components_32bit > 1)
2263 data_type = LLVMVectorType(ctx->f32, components_32bit);
2264
2265 base_data = to_float(&ctx->ac, src_data);
2266 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2267 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2268 data_type, "");
2269 base_offset = get_src(ctx->nir, instr->src[2]); /* voffset */
2270 while (writemask) {
2271 int start, count;
2272 LLVMValueRef data;
2273 LLVMValueRef offset;
2274 LLVMValueRef tmp;
2275 u_bit_scan_consecutive_range(&writemask, &start, &count);
2276
2277 /* Due to an LLVM limitation, split 3-element writes
2278 * into a 2-element and a 1-element write. */
2279 if (count == 3) {
2280 writemask |= 1 << (start + 2);
2281 count = 2;
2282 }
2283
2284 start *= elem_size_mult;
2285 count *= elem_size_mult;
2286
2287 if (count > 4) {
2288 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2289 count = 4;
2290 }
2291
2292 if (count == 4) {
2293 store_name = "llvm.amdgcn.buffer.store.v4f32";
2294 data = base_data;
2295 } else if (count == 2) {
2296 tmp = LLVMBuildExtractElement(ctx->builder,
2297 base_data, LLVMConstInt(ctx->i32, start, false), "");
2298 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2299 ctx->i32zero, "");
2300
2301 tmp = LLVMBuildExtractElement(ctx->builder,
2302 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2303 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2304 ctx->i32one, "");
2305 store_name = "llvm.amdgcn.buffer.store.v2f32";
2306
2307 } else {
2308 assert(count == 1);
2309 if (get_llvm_num_components(base_data) > 1)
2310 data = LLVMBuildExtractElement(ctx->builder, base_data,
2311 LLVMConstInt(ctx->i32, start, false), "");
2312 else
2313 data = base_data;
2314 store_name = "llvm.amdgcn.buffer.store.f32";
2315 }
2316
2317 offset = base_offset;
2318 if (start != 0) {
2319 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2320 }
2321 params[0] = data;
2322 params[3] = offset;
2323 ac_build_intrinsic(&ctx->ac, store_name,
2324 ctx->voidt, params, 6, 0);
2325 }
2326 }
2327
2328 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2329 const nir_intrinsic_instr *instr)
2330 {
2331 const char *name;
2332 LLVMValueRef params[6];
2333 int arg_count = 0;
2334 if (ctx->stage == MESA_SHADER_FRAGMENT)
2335 ctx->shader_info->fs.writes_memory = true;
2336
2337 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2338 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx->nir, instr->src[3]), 0);
2339 }
2340 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx->nir, instr->src[2]), 0);
2341 params[arg_count++] = get_src(ctx->nir, instr->src[0]);
2342 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2343 params[arg_count++] = get_src(ctx->nir, instr->src[1]); /* voffset */
2344 params[arg_count++] = ctx->i1false; /* slc */
2345
2346 switch (instr->intrinsic) {
2347 case nir_intrinsic_ssbo_atomic_add:
2348 name = "llvm.amdgcn.buffer.atomic.add";
2349 break;
2350 case nir_intrinsic_ssbo_atomic_imin:
2351 name = "llvm.amdgcn.buffer.atomic.smin";
2352 break;
2353 case nir_intrinsic_ssbo_atomic_umin:
2354 name = "llvm.amdgcn.buffer.atomic.umin";
2355 break;
2356 case nir_intrinsic_ssbo_atomic_imax:
2357 name = "llvm.amdgcn.buffer.atomic.smax";
2358 break;
2359 case nir_intrinsic_ssbo_atomic_umax:
2360 name = "llvm.amdgcn.buffer.atomic.umax";
2361 break;
2362 case nir_intrinsic_ssbo_atomic_and:
2363 name = "llvm.amdgcn.buffer.atomic.and";
2364 break;
2365 case nir_intrinsic_ssbo_atomic_or:
2366 name = "llvm.amdgcn.buffer.atomic.or";
2367 break;
2368 case nir_intrinsic_ssbo_atomic_xor:
2369 name = "llvm.amdgcn.buffer.atomic.xor";
2370 break;
2371 case nir_intrinsic_ssbo_atomic_exchange:
2372 name = "llvm.amdgcn.buffer.atomic.swap";
2373 break;
2374 case nir_intrinsic_ssbo_atomic_comp_swap:
2375 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2376 break;
2377 default:
2378 abort();
2379 }
2380
2381 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2382 }
2383
2384 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2385 const nir_intrinsic_instr *instr)
2386 {
2387 LLVMValueRef results[2];
2388 int load_components;
2389 int num_components = instr->num_components;
2390 if (instr->dest.ssa.bit_size == 64)
2391 num_components *= 2;
2392
2393 for (int i = 0; i < num_components; i += load_components) {
2394 load_components = MIN2(num_components - i, 4);
2395 const char *load_name;
2396 LLVMTypeRef data_type = ctx->f32;
2397 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2398 offset = LLVMBuildAdd(ctx->builder, get_src(ctx->nir, instr->src[1]), offset, "");
2399
2400 if (load_components == 3)
2401 data_type = LLVMVectorType(ctx->f32, 4);
2402 else if (load_components > 1)
2403 data_type = LLVMVectorType(ctx->f32, load_components);
2404
2405 if (load_components >= 3)
2406 load_name = "llvm.amdgcn.buffer.load.v4f32";
2407 else if (load_components == 2)
2408 load_name = "llvm.amdgcn.buffer.load.v2f32";
2409 else if (load_components == 1)
2410 load_name = "llvm.amdgcn.buffer.load.f32";
2411 else
2412 unreachable("unhandled number of components");
2413
2414 LLVMValueRef params[] = {
2415 get_src(ctx->nir, instr->src[0]),
2416 LLVMConstInt(ctx->i32, 0, false),
2417 offset,
2418 ctx->i1false,
2419 ctx->i1false,
2420 };
2421
2422 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2423
2424 }
2425
2426 LLVMValueRef ret = results[0];
2427 if (num_components > 4 || num_components == 3) {
2428 LLVMValueRef masks[] = {
2429 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2430 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2431 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2432 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2433 };
2434
2435 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2436 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2437 results[num_components > 4 ? 1 : 0], swizzle, "");
2438 }
2439
2440 return LLVMBuildBitCast(ctx->builder, ret,
2441 get_def_type(ctx->nir, &instr->dest.ssa), "");
2442 }
2443
2444 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2445 const nir_intrinsic_instr *instr)
2446 {
2447 LLVMValueRef results[8], ret;
2448 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2449 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2450 int num_components = instr->num_components;
2451
2452 if (ctx->abi->load_ubo)
2453 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2454
2455 if (instr->dest.ssa.bit_size == 64)
2456 num_components *= 2;
2457
2458 for (unsigned i = 0; i < num_components; ++i) {
2459 LLVMValueRef params[] = {
2460 rsrc,
2461 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2462 offset, "")
2463 };
2464 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2465 params, 2,
2466 AC_FUNC_ATTR_READNONE |
2467 AC_FUNC_ATTR_LEGACY);
2468 }
2469
2470
2471 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2472 return LLVMBuildBitCast(ctx->ac.builder, ret,
2473 get_def_type(ctx, &instr->dest.ssa), "");
2474 }
2475
2476 static void
2477 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2478 bool vs_in, unsigned *vertex_index_out,
2479 LLVMValueRef *vertex_index_ref,
2480 unsigned *const_out, LLVMValueRef *indir_out)
2481 {
2482 unsigned const_offset = 0;
2483 nir_deref *tail = &deref->deref;
2484 LLVMValueRef offset = NULL;
2485
2486 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2487 tail = tail->child;
2488 nir_deref_array *deref_array = nir_deref_as_array(tail);
2489 if (vertex_index_out)
2490 *vertex_index_out = deref_array->base_offset;
2491
2492 if (vertex_index_ref) {
2493 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2494 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2495 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2496 }
2497 *vertex_index_ref = vtx;
2498 }
2499 }
2500
2501 if (deref->var->data.compact) {
2502 assert(tail->child->deref_type == nir_deref_type_array);
2503 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2504 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2505 /* We always lower indirect dereferences for "compact" array vars. */
2506 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2507
2508 const_offset = deref_array->base_offset;
2509 goto out;
2510 }
2511
2512 while (tail->child != NULL) {
2513 const struct glsl_type *parent_type = tail->type;
2514 tail = tail->child;
2515
2516 if (tail->deref_type == nir_deref_type_array) {
2517 nir_deref_array *deref_array = nir_deref_as_array(tail);
2518 LLVMValueRef index, stride, local_offset;
2519 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2520
2521 const_offset += size * deref_array->base_offset;
2522 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2523 continue;
2524
2525 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2526 index = get_src(ctx, deref_array->indirect);
2527 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2528 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2529
2530 if (offset)
2531 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2532 else
2533 offset = local_offset;
2534 } else if (tail->deref_type == nir_deref_type_struct) {
2535 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2536
2537 for (unsigned i = 0; i < deref_struct->index; i++) {
2538 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2539 const_offset += glsl_count_attribute_slots(ft, vs_in);
2540 }
2541 } else
2542 unreachable("unsupported deref type");
2543
2544 }
2545 out:
2546 if (const_offset && offset)
2547 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2548 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2549 "");
2550
2551 *const_out = const_offset;
2552 *indir_out = offset;
2553 }
2554
2555 static LLVMValueRef
2556 lds_load(struct nir_to_llvm_context *ctx,
2557 LLVMValueRef dw_addr)
2558 {
2559 LLVMValueRef value;
2560 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2561 return value;
2562 }
2563
2564 static void
2565 lds_store(struct nir_to_llvm_context *ctx,
2566 LLVMValueRef dw_addr, LLVMValueRef value)
2567 {
2568 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2569 ac_build_indexed_store(&ctx->ac, ctx->lds,
2570 dw_addr, value);
2571 }
2572
2573 /* The offchip buffer layout for TCS->TES is
2574 *
2575 * - attribute 0 of patch 0 vertex 0
2576 * - attribute 0 of patch 0 vertex 1
2577 * - attribute 0 of patch 0 vertex 2
2578 * ...
2579 * - attribute 0 of patch 1 vertex 0
2580 * - attribute 0 of patch 1 vertex 1
2581 * ...
2582 * - attribute 1 of patch 0 vertex 0
2583 * - attribute 1 of patch 0 vertex 1
2584 * ...
2585 * - per patch attribute 0 of patch 0
2586 * - per patch attribute 0 of patch 1
2587 * ...
2588 *
2589 * Note that every attribute has 4 components.
2590 */
2591 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2592 LLVMValueRef vertex_index,
2593 LLVMValueRef param_index)
2594 {
2595 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2596 LLVMValueRef param_stride, constant16;
2597 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2598
2599 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2600 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2601 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2602 num_patches, "");
2603
2604 constant16 = LLVMConstInt(ctx->i32, 16, false);
2605 if (vertex_index) {
2606 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2607 vertices_per_patch, "");
2608
2609 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2610 vertex_index, "");
2611
2612 param_stride = total_vertices;
2613 } else {
2614 base_addr = rel_patch_id;
2615 param_stride = num_patches;
2616 }
2617
2618 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2619 LLVMBuildMul(ctx->builder, param_index,
2620 param_stride, ""), "");
2621
2622 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2623
2624 if (!vertex_index) {
2625 LLVMValueRef patch_data_offset =
2626 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2627
2628 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2629 patch_data_offset, "");
2630 }
2631 return base_addr;
2632 }
2633
2634 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2635 unsigned param,
2636 unsigned const_index,
2637 bool is_compact,
2638 LLVMValueRef vertex_index,
2639 LLVMValueRef indir_index)
2640 {
2641 LLVMValueRef param_index;
2642
2643 if (indir_index)
2644 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2645 indir_index, "");
2646 else {
2647 if (const_index && !is_compact)
2648 param += const_index;
2649 param_index = LLVMConstInt(ctx->i32, param, false);
2650 }
2651 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2652 }
2653
2654 static void
2655 mark_tess_output(struct nir_to_llvm_context *ctx,
2656 bool is_patch, uint32_t param)
2657
2658 {
2659 if (is_patch) {
2660 ctx->tess_patch_outputs_written |= (1ull << param);
2661 } else
2662 ctx->tess_outputs_written |= (1ull << param);
2663 }
2664
2665 static LLVMValueRef
2666 get_dw_address(struct nir_to_llvm_context *ctx,
2667 LLVMValueRef dw_addr,
2668 unsigned param,
2669 unsigned const_index,
2670 bool compact_const_index,
2671 LLVMValueRef vertex_index,
2672 LLVMValueRef stride,
2673 LLVMValueRef indir_index)
2674
2675 {
2676
2677 if (vertex_index) {
2678 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2679 LLVMBuildMul(ctx->builder,
2680 vertex_index,
2681 stride, ""), "");
2682 }
2683
2684 if (indir_index)
2685 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2686 LLVMBuildMul(ctx->builder, indir_index,
2687 LLVMConstInt(ctx->i32, 4, false), ""), "");
2688 else if (const_index && !compact_const_index)
2689 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2690 LLVMConstInt(ctx->i32, const_index, false), "");
2691
2692 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2693 LLVMConstInt(ctx->i32, param * 4, false), "");
2694
2695 if (const_index && compact_const_index)
2696 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2697 LLVMConstInt(ctx->i32, const_index, false), "");
2698 return dw_addr;
2699 }
2700
2701 static LLVMValueRef
2702 load_tcs_input(struct nir_to_llvm_context *ctx,
2703 nir_intrinsic_instr *instr)
2704 {
2705 LLVMValueRef dw_addr, stride;
2706 unsigned const_index;
2707 LLVMValueRef vertex_index;
2708 LLVMValueRef indir_index;
2709 unsigned param;
2710 LLVMValueRef value[4], result;
2711 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2712 const bool is_compact = instr->variables[0]->var->data.compact;
2713 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2714 get_deref_offset(ctx->nir, instr->variables[0],
2715 false, NULL, per_vertex ? &vertex_index : NULL,
2716 &const_index, &indir_index);
2717
2718 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2719 dw_addr = get_tcs_in_current_patch_offset(ctx);
2720 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2721 indir_index);
2722
2723 for (unsigned i = 0; i < instr->num_components; i++) {
2724 value[i] = lds_load(ctx, dw_addr);
2725 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2726 ctx->i32one, "");
2727 }
2728 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2729 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2730 return result;
2731 }
2732
2733 static LLVMValueRef
2734 load_tcs_output(struct nir_to_llvm_context *ctx,
2735 nir_intrinsic_instr *instr)
2736 {
2737 LLVMValueRef dw_addr, stride;
2738 LLVMValueRef value[4], result;
2739 LLVMValueRef vertex_index = NULL;
2740 LLVMValueRef indir_index = NULL;
2741 unsigned const_index = 0;
2742 unsigned param;
2743 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2744 const bool is_compact = instr->variables[0]->var->data.compact;
2745 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2746 get_deref_offset(ctx->nir, instr->variables[0],
2747 false, NULL, per_vertex ? &vertex_index : NULL,
2748 &const_index, &indir_index);
2749
2750 if (!instr->variables[0]->var->data.patch) {
2751 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2752 dw_addr = get_tcs_out_current_patch_offset(ctx);
2753 } else {
2754 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2755 }
2756
2757 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2758 indir_index);
2759
2760 for (unsigned i = 0; i < instr->num_components; i++) {
2761 value[i] = lds_load(ctx, dw_addr);
2762 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2763 ctx->i32one, "");
2764 }
2765 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2766 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2767 return result;
2768 }
2769
2770 static void
2771 store_tcs_output(struct nir_to_llvm_context *ctx,
2772 nir_intrinsic_instr *instr,
2773 LLVMValueRef src,
2774 unsigned writemask)
2775 {
2776 LLVMValueRef stride, dw_addr;
2777 LLVMValueRef buf_addr = NULL;
2778 LLVMValueRef vertex_index = NULL;
2779 LLVMValueRef indir_index = NULL;
2780 unsigned const_index = 0;
2781 unsigned param;
2782 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2783 const bool is_compact = instr->variables[0]->var->data.compact;
2784
2785 get_deref_offset(ctx->nir, instr->variables[0],
2786 false, NULL, per_vertex ? &vertex_index : NULL,
2787 &const_index, &indir_index);
2788
2789 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2790 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2791 is_compact && const_index > 3) {
2792 const_index -= 3;
2793 param++;
2794 }
2795
2796 if (!instr->variables[0]->var->data.patch) {
2797 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2798 dw_addr = get_tcs_out_current_patch_offset(ctx);
2799 } else {
2800 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2801 }
2802
2803 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2804
2805 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2806 indir_index);
2807 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2808 vertex_index, indir_index);
2809
2810 unsigned base = is_compact ? const_index : 0;
2811 for (unsigned chan = 0; chan < 8; chan++) {
2812 bool is_tess_factor = false;
2813 if (!(writemask & (1 << chan)))
2814 continue;
2815 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan);
2816
2817 lds_store(ctx, dw_addr, value);
2818
2819 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2820 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2821 is_tess_factor = true;
2822
2823 if (!is_tess_factor && writemask != 0xF)
2824 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2825 buf_addr, ctx->oc_lds,
2826 4 * (base + chan), 1, 0, true, false);
2827
2828 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2829 ctx->i32one, "");
2830 }
2831
2832 if (writemask == 0xF) {
2833 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2834 buf_addr, ctx->oc_lds,
2835 (base * 4), 1, 0, true, false);
2836 }
2837 }
2838
2839 static LLVMValueRef
2840 load_tes_input(struct nir_to_llvm_context *ctx,
2841 const nir_intrinsic_instr *instr)
2842 {
2843 LLVMValueRef buf_addr;
2844 LLVMValueRef result;
2845 LLVMValueRef vertex_index = NULL;
2846 LLVMValueRef indir_index = NULL;
2847 unsigned const_index = 0;
2848 unsigned param;
2849 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2850 const bool is_compact = instr->variables[0]->var->data.compact;
2851
2852 get_deref_offset(ctx->nir, instr->variables[0],
2853 false, NULL, per_vertex ? &vertex_index : NULL,
2854 &const_index, &indir_index);
2855 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2856 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2857 is_compact && const_index > 3) {
2858 const_index -= 3;
2859 param++;
2860 }
2861 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2862 is_compact, vertex_index, indir_index);
2863
2864 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2865 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2866 result = trim_vector(&ctx->ac, result, instr->num_components);
2867 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2868 return result;
2869 }
2870
2871 static LLVMValueRef
2872 load_gs_input(struct nir_to_llvm_context *ctx,
2873 nir_intrinsic_instr *instr)
2874 {
2875 LLVMValueRef indir_index, vtx_offset;
2876 unsigned const_index;
2877 LLVMValueRef args[9];
2878 unsigned param, vtx_offset_param;
2879 LLVMValueRef value[4], result;
2880 unsigned vertex_index;
2881 get_deref_offset(ctx->nir, instr->variables[0],
2882 false, &vertex_index, NULL,
2883 &const_index, &indir_index);
2884 vtx_offset_param = vertex_index;
2885 assert(vtx_offset_param < 6);
2886 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2887 LLVMConstInt(ctx->i32, 4, false), "");
2888
2889 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2890 for (unsigned i = 0; i < instr->num_components; i++) {
2891
2892 args[0] = ctx->esgs_ring;
2893 args[1] = vtx_offset;
2894 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2895 args[3] = ctx->i32zero;
2896 args[4] = ctx->i32one; /* OFFEN */
2897 args[5] = ctx->i32zero; /* IDXEN */
2898 args[6] = ctx->i32one; /* GLC */
2899 args[7] = ctx->i32zero; /* SLC */
2900 args[8] = ctx->i32zero; /* TFE */
2901
2902 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2903 ctx->i32, args, 9,
2904 AC_FUNC_ATTR_READONLY |
2905 AC_FUNC_ATTR_LEGACY);
2906 }
2907 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2908
2909 return result;
2910 }
2911
2912 static LLVMValueRef
2913 build_gep_for_deref(struct ac_nir_context *ctx,
2914 nir_deref_var *deref)
2915 {
2916 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2917 assert(entry->data);
2918 LLVMValueRef val = entry->data;
2919 nir_deref *tail = deref->deref.child;
2920 while (tail != NULL) {
2921 LLVMValueRef offset;
2922 switch (tail->deref_type) {
2923 case nir_deref_type_array: {
2924 nir_deref_array *array = nir_deref_as_array(tail);
2925 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2926 if (array->deref_array_type ==
2927 nir_deref_array_type_indirect) {
2928 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2929 get_src(ctx,
2930 array->indirect),
2931 "");
2932 }
2933 break;
2934 }
2935 case nir_deref_type_struct: {
2936 nir_deref_struct *deref_struct =
2937 nir_deref_as_struct(tail);
2938 offset = LLVMConstInt(ctx->ac.i32,
2939 deref_struct->index, 0);
2940 break;
2941 }
2942 default:
2943 unreachable("bad deref type");
2944 }
2945 val = ac_build_gep0(&ctx->ac, val, offset);
2946 tail = tail->child;
2947 }
2948 return val;
2949 }
2950
2951 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
2952 nir_intrinsic_instr *instr)
2953 {
2954 LLVMValueRef values[8];
2955 int idx = instr->variables[0]->var->data.driver_location;
2956 int ve = instr->dest.ssa.num_components;
2957 LLVMValueRef indir_index;
2958 LLVMValueRef ret;
2959 unsigned const_index;
2960 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2961 instr->variables[0]->var->data.mode == nir_var_shader_in;
2962 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2963 &const_index, &indir_index);
2964
2965 if (instr->dest.ssa.bit_size == 64)
2966 ve *= 2;
2967
2968 switch (instr->variables[0]->var->data.mode) {
2969 case nir_var_shader_in:
2970 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2971 return load_tcs_input(ctx->nctx, instr);
2972 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2973 return load_tes_input(ctx->nctx, instr);
2974 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2975 return load_gs_input(ctx->nctx, instr);
2976 }
2977 for (unsigned chan = 0; chan < ve; chan++) {
2978 if (indir_index) {
2979 unsigned count = glsl_count_attribute_slots(
2980 instr->variables[0]->var->type,
2981 ctx->stage == MESA_SHADER_VERTEX);
2982 count -= chan / 4;
2983 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2984 &ctx->ac, ctx->abi->inputs + idx + chan, count,
2985 4, false);
2986
2987 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
2988 tmp_vec,
2989 indir_index, "");
2990 } else
2991 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
2992 }
2993 break;
2994 case nir_var_local:
2995 for (unsigned chan = 0; chan < ve; chan++) {
2996 if (indir_index) {
2997 unsigned count = glsl_count_attribute_slots(
2998 instr->variables[0]->var->type, false);
2999 count -= chan / 4;
3000 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3001 &ctx->ac, ctx->locals + idx + chan, count,
3002 4, true);
3003
3004 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3005 tmp_vec,
3006 indir_index, "");
3007 } else {
3008 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3009 }
3010 }
3011 break;
3012 case nir_var_shared: {
3013 LLVMValueRef address = build_gep_for_deref(ctx,
3014 instr->variables[0]);
3015 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3016 return LLVMBuildBitCast(ctx->ac.builder, val,
3017 get_def_type(ctx, &instr->dest.ssa),
3018 "");
3019 }
3020 case nir_var_shader_out:
3021 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3022 return load_tcs_output(ctx->nctx, instr);
3023 for (unsigned chan = 0; chan < ve; chan++) {
3024 if (indir_index) {
3025 unsigned count = glsl_count_attribute_slots(
3026 instr->variables[0]->var->type, false);
3027 count -= chan / 4;
3028 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3029 &ctx->ac, ctx->outputs + idx + chan, count,
3030 4, true);
3031
3032 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3033 tmp_vec,
3034 indir_index, "");
3035 } else {
3036 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3037 ctx->outputs[idx + chan + const_index * 4],
3038 "");
3039 }
3040 }
3041 break;
3042 default:
3043 unreachable("unhandle variable mode");
3044 }
3045 ret = ac_build_gather_values(&ctx->ac, values, ve);
3046 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3047 }
3048
3049 static void
3050 visit_store_var(struct ac_nir_context *ctx,
3051 nir_intrinsic_instr *instr)
3052 {
3053 LLVMValueRef temp_ptr, value;
3054 int idx = instr->variables[0]->var->data.driver_location;
3055 LLVMValueRef src = to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3056 int writemask = instr->const_index[0];
3057 LLVMValueRef indir_index;
3058 unsigned const_index;
3059 get_deref_offset(ctx, instr->variables[0], false,
3060 NULL, NULL, &const_index, &indir_index);
3061
3062 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3063 int old_writemask = writemask;
3064
3065 src = LLVMBuildBitCast(ctx->ac.builder, src,
3066 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3067 "");
3068
3069 writemask = 0;
3070 for (unsigned chan = 0; chan < 4; chan++) {
3071 if (old_writemask & (1 << chan))
3072 writemask |= 3u << (2 * chan);
3073 }
3074 }
3075
3076 switch (instr->variables[0]->var->data.mode) {
3077 case nir_var_shader_out:
3078
3079 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3080 store_tcs_output(ctx->nctx, instr, src, writemask);
3081 return;
3082 }
3083
3084 for (unsigned chan = 0; chan < 8; chan++) {
3085 int stride = 4;
3086 if (!(writemask & (1 << chan)))
3087 continue;
3088
3089 value = llvm_extract_elem(&ctx->ac, src, chan);
3090
3091 if (instr->variables[0]->var->data.compact)
3092 stride = 1;
3093 if (indir_index) {
3094 unsigned count = glsl_count_attribute_slots(
3095 instr->variables[0]->var->type, false);
3096 count -= chan / 4;
3097 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3098 &ctx->ac, ctx->outputs + idx + chan, count,
3099 stride, true);
3100
3101 if (get_llvm_num_components(tmp_vec) > 1) {
3102 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3103 value, indir_index, "");
3104 } else
3105 tmp_vec = value;
3106 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3107 count, stride, tmp_vec);
3108
3109 } else {
3110 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3111
3112 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3113 }
3114 }
3115 break;
3116 case nir_var_local:
3117 for (unsigned chan = 0; chan < 8; chan++) {
3118 if (!(writemask & (1 << chan)))
3119 continue;
3120
3121 value = llvm_extract_elem(&ctx->ac, src, chan);
3122 if (indir_index) {
3123 unsigned count = glsl_count_attribute_slots(
3124 instr->variables[0]->var->type, false);
3125 count -= chan / 4;
3126 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3127 &ctx->ac, ctx->locals + idx + chan, count,
3128 4, true);
3129
3130 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3131 value, indir_index, "");
3132 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3133 count, 4, tmp_vec);
3134 } else {
3135 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3136
3137 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3138 }
3139 }
3140 break;
3141 case nir_var_shared: {
3142 int writemask = instr->const_index[0];
3143 LLVMValueRef address = build_gep_for_deref(ctx,
3144 instr->variables[0]);
3145 LLVMValueRef val = get_src(ctx, instr->src[0]);
3146 unsigned components =
3147 glsl_get_vector_elements(
3148 nir_deref_tail(&instr->variables[0]->deref)->type);
3149 if (writemask == (1 << components) - 1) {
3150 val = LLVMBuildBitCast(
3151 ctx->ac.builder, val,
3152 LLVMGetElementType(LLVMTypeOf(address)), "");
3153 LLVMBuildStore(ctx->ac.builder, val, address);
3154 } else {
3155 for (unsigned chan = 0; chan < 4; chan++) {
3156 if (!(writemask & (1 << chan)))
3157 continue;
3158 LLVMValueRef ptr =
3159 LLVMBuildStructGEP(ctx->ac.builder,
3160 address, chan, "");
3161 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3162 chan);
3163 src = LLVMBuildBitCast(
3164 ctx->ac.builder, src,
3165 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3166 LLVMBuildStore(ctx->ac.builder, src, ptr);
3167 }
3168 }
3169 break;
3170 }
3171 default:
3172 break;
3173 }
3174 }
3175
3176 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3177 {
3178 switch (dim) {
3179 case GLSL_SAMPLER_DIM_BUF:
3180 return 1;
3181 case GLSL_SAMPLER_DIM_1D:
3182 return array ? 2 : 1;
3183 case GLSL_SAMPLER_DIM_2D:
3184 return array ? 3 : 2;
3185 case GLSL_SAMPLER_DIM_MS:
3186 return array ? 4 : 3;
3187 case GLSL_SAMPLER_DIM_3D:
3188 case GLSL_SAMPLER_DIM_CUBE:
3189 return 3;
3190 case GLSL_SAMPLER_DIM_RECT:
3191 case GLSL_SAMPLER_DIM_SUBPASS:
3192 return 2;
3193 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3194 return 3;
3195 default:
3196 break;
3197 }
3198 return 0;
3199 }
3200
3201
3202
3203 /* Adjust the sample index according to FMASK.
3204 *
3205 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3206 * which is the identity mapping. Each nibble says which physical sample
3207 * should be fetched to get that sample.
3208 *
3209 * For example, 0x11111100 means there are only 2 samples stored and
3210 * the second sample covers 3/4 of the pixel. When reading samples 0
3211 * and 1, return physical sample 0 (determined by the first two 0s
3212 * in FMASK), otherwise return physical sample 1.
3213 *
3214 * The sample index should be adjusted as follows:
3215 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3216 */
3217 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3218 LLVMValueRef coord_x, LLVMValueRef coord_y,
3219 LLVMValueRef coord_z,
3220 LLVMValueRef sample_index,
3221 LLVMValueRef fmask_desc_ptr)
3222 {
3223 LLVMValueRef fmask_load_address[4];
3224 LLVMValueRef res;
3225
3226 fmask_load_address[0] = coord_x;
3227 fmask_load_address[1] = coord_y;
3228 if (coord_z) {
3229 fmask_load_address[2] = coord_z;
3230 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3231 }
3232
3233 struct ac_image_args args = {0};
3234
3235 args.opcode = ac_image_load;
3236 args.da = coord_z ? true : false;
3237 args.resource = fmask_desc_ptr;
3238 args.dmask = 0xf;
3239 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3240
3241 res = ac_build_image_opcode(ctx, &args);
3242
3243 res = to_integer(ctx, res);
3244 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3245 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3246
3247 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3248 res,
3249 ctx->i32_0, "");
3250
3251 LLVMValueRef sample_index4 =
3252 LLVMBuildMul(ctx->builder, sample_index, four, "");
3253 LLVMValueRef shifted_fmask =
3254 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3255 LLVMValueRef final_sample =
3256 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3257
3258 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3259 * resource descriptor is 0 (invalid),
3260 */
3261 LLVMValueRef fmask_desc =
3262 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3263 ctx->v8i32, "");
3264
3265 LLVMValueRef fmask_word1 =
3266 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3267 ctx->i32_1, "");
3268
3269 LLVMValueRef word1_is_nonzero =
3270 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3271 fmask_word1, ctx->i32_0, "");
3272
3273 /* Replace the MSAA sample index. */
3274 sample_index =
3275 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3276 final_sample, sample_index, "");
3277 return sample_index;
3278 }
3279
3280 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3281 const nir_intrinsic_instr *instr)
3282 {
3283 const struct glsl_type *type = instr->variables[0]->var->type;
3284 if(instr->variables[0]->deref.child)
3285 type = instr->variables[0]->deref.child->type;
3286
3287 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3288 LLVMValueRef coords[4];
3289 LLVMValueRef masks[] = {
3290 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3291 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3292 };
3293 LLVMValueRef res;
3294 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3295
3296 int count;
3297 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3298 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3299 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3300 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3301 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3302
3303 count = image_type_to_components_count(dim,
3304 glsl_sampler_type_is_array(type));
3305
3306 if (is_ms) {
3307 LLVMValueRef fmask_load_address[3];
3308 int chan;
3309
3310 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3311 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3312 if (glsl_sampler_type_is_array(type))
3313 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3314 else
3315 fmask_load_address[2] = NULL;
3316 if (add_frag_pos) {
3317 for (chan = 0; chan < 2; ++chan)
3318 fmask_load_address[chan] = LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->nctx->frag_pos[chan], ctx->ac.i32, ""), "");
3319 }
3320 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3321 fmask_load_address[0],
3322 fmask_load_address[1],
3323 fmask_load_address[2],
3324 sample_index,
3325 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, true, false));
3326 }
3327 if (count == 1) {
3328 if (instr->src[0].ssa->num_components)
3329 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3330 else
3331 res = src0;
3332 } else {
3333 int chan;
3334 if (is_ms)
3335 count--;
3336 for (chan = 0; chan < count; ++chan) {
3337 coords[chan] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[chan], "");
3338 }
3339
3340 if (add_frag_pos) {
3341 for (chan = 0; chan < count; ++chan)
3342 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->nctx->frag_pos[chan], ctx->ac.i32, ""), "");
3343 }
3344 if (is_ms) {
3345 coords[count] = sample_index;
3346 count++;
3347 }
3348
3349 if (count == 3) {
3350 coords[3] = LLVMGetUndef(ctx->ac.i32);
3351 count = 4;
3352 }
3353 res = ac_build_gather_values(&ctx->ac, coords, count);
3354 }
3355 return res;
3356 }
3357
3358 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3359 const nir_intrinsic_instr *instr)
3360 {
3361 LLVMValueRef params[7];
3362 LLVMValueRef res;
3363 char intrinsic_name[64];
3364 const nir_variable *var = instr->variables[0]->var;
3365 const struct glsl_type *type = var->type;
3366 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3367 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3368
3369 if(instr->variables[0]->deref.child)
3370 type = instr->variables[0]->deref.child->type;
3371
3372 type = glsl_without_array(type);
3373 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3374 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, false);
3375 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3376 ctx->ac.i32_0, ""); /* vindex */
3377 params[2] = ctx->ac.i32_0; /* voffset */
3378 params[3] = i1false; /* glc */
3379 params[4] = i1false; /* slc */
3380 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3381 params, 5, 0);
3382
3383 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3384 res = to_integer(&ctx->ac, res);
3385 } else {
3386 bool is_da = glsl_sampler_type_is_array(type) ||
3387 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3388 LLVMValueRef da = is_da ? i1true : i1false;
3389 LLVMValueRef glc = i1false;
3390 LLVMValueRef slc = i1false;
3391
3392 params[0] = get_image_coords(ctx, instr);
3393 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3394 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3395 if (HAVE_LLVM <= 0x0309) {
3396 params[3] = i1false; /* r128 */
3397 params[4] = da;
3398 params[5] = glc;
3399 params[6] = slc;
3400 } else {
3401 LLVMValueRef lwe = i1false;
3402 params[3] = glc;
3403 params[4] = slc;
3404 params[5] = lwe;
3405 params[6] = da;
3406 }
3407
3408 ac_get_image_intr_name("llvm.amdgcn.image.load",
3409 ctx->ac.v4f32, /* vdata */
3410 LLVMTypeOf(params[0]), /* coords */
3411 LLVMTypeOf(params[1]), /* rsrc */
3412 intrinsic_name, sizeof(intrinsic_name));
3413
3414 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3415 params, 7, AC_FUNC_ATTR_READONLY);
3416 }
3417 return to_integer(&ctx->ac, res);
3418 }
3419
3420 static void visit_image_store(struct ac_nir_context *ctx,
3421 nir_intrinsic_instr *instr)
3422 {
3423 LLVMValueRef params[8];
3424 char intrinsic_name[64];
3425 const nir_variable *var = instr->variables[0]->var;
3426 const struct glsl_type *type = glsl_without_array(var->type);
3427 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3428 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3429 LLVMValueRef glc = i1false;
3430 bool force_glc = ctx->abi->chip_class == SI;
3431 if (force_glc)
3432 glc = i1true;
3433
3434 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3435 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3436 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, true);
3437 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3438 ctx->ac.i32_0, ""); /* vindex */
3439 params[3] = ctx->ac.i32_0; /* voffset */
3440 params[4] = glc; /* glc */
3441 params[5] = i1false; /* slc */
3442 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3443 params, 6, 0);
3444 } else {
3445 bool is_da = glsl_sampler_type_is_array(type) ||
3446 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3447 LLVMValueRef da = is_da ? i1true : i1false;
3448 LLVMValueRef slc = i1false;
3449
3450 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3451 params[1] = get_image_coords(ctx, instr); /* coords */
3452 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, true);
3453 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3454 if (HAVE_LLVM <= 0x0309) {
3455 params[4] = i1false; /* r128 */
3456 params[5] = da;
3457 params[6] = glc;
3458 params[7] = slc;
3459 } else {
3460 LLVMValueRef lwe = i1false;
3461 params[4] = glc;
3462 params[5] = slc;
3463 params[6] = lwe;
3464 params[7] = da;
3465 }
3466
3467 ac_get_image_intr_name("llvm.amdgcn.image.store",
3468 LLVMTypeOf(params[0]), /* vdata */
3469 LLVMTypeOf(params[1]), /* coords */
3470 LLVMTypeOf(params[2]), /* rsrc */
3471 intrinsic_name, sizeof(intrinsic_name));
3472
3473 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3474 params, 8, 0);
3475 }
3476
3477 }
3478
3479 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3480 const nir_intrinsic_instr *instr)
3481 {
3482 LLVMValueRef params[6];
3483 int param_count = 0;
3484 const nir_variable *var = instr->variables[0]->var;
3485
3486 const char *atomic_name;
3487 char intrinsic_name[41];
3488 const struct glsl_type *type = glsl_without_array(var->type);
3489 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3490 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3491 MAYBE_UNUSED int length;
3492
3493 switch (instr->intrinsic) {
3494 case nir_intrinsic_image_atomic_add:
3495 atomic_name = "add";
3496 break;
3497 case nir_intrinsic_image_atomic_min:
3498 atomic_name = "smin";
3499 break;
3500 case nir_intrinsic_image_atomic_max:
3501 atomic_name = "smax";
3502 break;
3503 case nir_intrinsic_image_atomic_and:
3504 atomic_name = "and";
3505 break;
3506 case nir_intrinsic_image_atomic_or:
3507 atomic_name = "or";
3508 break;
3509 case nir_intrinsic_image_atomic_xor:
3510 atomic_name = "xor";
3511 break;
3512 case nir_intrinsic_image_atomic_exchange:
3513 atomic_name = "swap";
3514 break;
3515 case nir_intrinsic_image_atomic_comp_swap:
3516 atomic_name = "cmpswap";
3517 break;
3518 default:
3519 abort();
3520 }
3521
3522 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3523 params[param_count++] = get_src(ctx, instr->src[3]);
3524 params[param_count++] = get_src(ctx, instr->src[2]);
3525
3526 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3527 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3528 true, true);
3529 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3530 ctx->ac.i32_0, ""); /* vindex */
3531 params[param_count++] = ctx->ac.i32_0; /* voffset */
3532 params[param_count++] = i1false; /* slc */
3533
3534 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3535 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3536 } else {
3537 char coords_type[8];
3538
3539 bool da = glsl_sampler_type_is_array(type) ||
3540 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3541
3542 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3543 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3544 true, true);
3545 params[param_count++] = i1false; /* r128 */
3546 params[param_count++] = da ? i1true : i1false; /* da */
3547 params[param_count++] = i1false; /* slc */
3548
3549 build_int_type_name(LLVMTypeOf(coords),
3550 coords_type, sizeof(coords_type));
3551
3552 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3553 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3554 }
3555
3556 assert(length < sizeof(intrinsic_name));
3557 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3558 }
3559
3560 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3561 const nir_intrinsic_instr *instr)
3562 {
3563 LLVMValueRef res;
3564 const nir_variable *var = instr->variables[0]->var;
3565 const struct glsl_type *type = instr->variables[0]->var->type;
3566 bool da = glsl_sampler_type_is_array(var->type) ||
3567 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3568 if(instr->variables[0]->deref.child)
3569 type = instr->variables[0]->deref.child->type;
3570
3571 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3572 return get_buffer_size(ctx,
3573 get_sampler_desc(ctx, instr->variables[0],
3574 AC_DESC_BUFFER, true, false), true);
3575
3576 struct ac_image_args args = { 0 };
3577
3578 args.da = da;
3579 args.dmask = 0xf;
3580 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3581 args.opcode = ac_image_get_resinfo;
3582 args.addr = ctx->ac.i32_0;
3583
3584 res = ac_build_image_opcode(&ctx->ac, &args);
3585
3586 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3587 glsl_sampler_type_is_array(type)) {
3588 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3589 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3590 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3591 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3592 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3593 }
3594 return res;
3595 }
3596
3597 #define NOOP_WAITCNT 0xf7f
3598 #define LGKM_CNT 0x07f
3599 #define VM_CNT 0xf70
3600
3601 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3602 unsigned simm16)
3603 {
3604 LLVMValueRef args[1] = {
3605 LLVMConstInt(ctx->i32, simm16, false),
3606 };
3607 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3608 ctx->voidt, args, 1, 0);
3609 }
3610
3611 static void emit_barrier(struct nir_to_llvm_context *ctx)
3612 {
3613 /* SI only (thanks to a hw bug workaround):
3614 * The real barrier instruction isn’t needed, because an entire patch
3615 * always fits into a single wave.
3616 */
3617 if (ctx->options->chip_class == SI &&
3618 ctx->stage == MESA_SHADER_TESS_CTRL) {
3619 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3620 return;
3621 }
3622 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3623 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3624 }
3625
3626 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3627 const nir_intrinsic_instr *instr)
3628 {
3629 LLVMValueRef cond;
3630
3631 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3632 get_src(ctx->nir, instr->src[0]),
3633 ctx->i32zero, "");
3634
3635 cond = LLVMBuildSelect(ctx->builder, cond,
3636 LLVMConstReal(ctx->f32, -1.0f),
3637 ctx->f32zero, "");
3638 ac_build_kill(&ctx->ac, cond);
3639 }
3640
3641 static LLVMValueRef
3642 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3643 {
3644 LLVMValueRef result;
3645 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3646 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3647 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3648
3649 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3650 }
3651
3652 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3653 const nir_intrinsic_instr *instr)
3654 {
3655 LLVMValueRef ptr, result;
3656 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3657 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3658
3659 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3660 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3661 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3662 ptr, src, src1,
3663 LLVMAtomicOrderingSequentiallyConsistent,
3664 LLVMAtomicOrderingSequentiallyConsistent,
3665 false);
3666 } else {
3667 LLVMAtomicRMWBinOp op;
3668 switch (instr->intrinsic) {
3669 case nir_intrinsic_var_atomic_add:
3670 op = LLVMAtomicRMWBinOpAdd;
3671 break;
3672 case nir_intrinsic_var_atomic_umin:
3673 op = LLVMAtomicRMWBinOpUMin;
3674 break;
3675 case nir_intrinsic_var_atomic_umax:
3676 op = LLVMAtomicRMWBinOpUMax;
3677 break;
3678 case nir_intrinsic_var_atomic_imin:
3679 op = LLVMAtomicRMWBinOpMin;
3680 break;
3681 case nir_intrinsic_var_atomic_imax:
3682 op = LLVMAtomicRMWBinOpMax;
3683 break;
3684 case nir_intrinsic_var_atomic_and:
3685 op = LLVMAtomicRMWBinOpAnd;
3686 break;
3687 case nir_intrinsic_var_atomic_or:
3688 op = LLVMAtomicRMWBinOpOr;
3689 break;
3690 case nir_intrinsic_var_atomic_xor:
3691 op = LLVMAtomicRMWBinOpXor;
3692 break;
3693 case nir_intrinsic_var_atomic_exchange:
3694 op = LLVMAtomicRMWBinOpXchg;
3695 break;
3696 default:
3697 return NULL;
3698 }
3699
3700 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(&ctx->ac, src),
3701 LLVMAtomicOrderingSequentiallyConsistent,
3702 false);
3703 }
3704 return result;
3705 }
3706
3707 #define INTERP_CENTER 0
3708 #define INTERP_CENTROID 1
3709 #define INTERP_SAMPLE 2
3710
3711 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3712 enum glsl_interp_mode interp, unsigned location)
3713 {
3714 switch (interp) {
3715 case INTERP_MODE_FLAT:
3716 default:
3717 return NULL;
3718 case INTERP_MODE_SMOOTH:
3719 case INTERP_MODE_NONE:
3720 if (location == INTERP_CENTER)
3721 return ctx->persp_center;
3722 else if (location == INTERP_CENTROID)
3723 return ctx->persp_centroid;
3724 else if (location == INTERP_SAMPLE)
3725 return ctx->persp_sample;
3726 break;
3727 case INTERP_MODE_NOPERSPECTIVE:
3728 if (location == INTERP_CENTER)
3729 return ctx->linear_center;
3730 else if (location == INTERP_CENTROID)
3731 return ctx->linear_centroid;
3732 else if (location == INTERP_SAMPLE)
3733 return ctx->linear_sample;
3734 break;
3735 }
3736 return NULL;
3737 }
3738
3739 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3740 LLVMValueRef sample_id)
3741 {
3742 LLVMValueRef result;
3743 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3744
3745 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3746 const_array(ctx->v2f32, 64), "");
3747
3748 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3749 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3750
3751 return result;
3752 }
3753
3754 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3755 {
3756 LLVMValueRef values[2];
3757
3758 values[0] = emit_ffract(&ctx->ac, ctx->frag_pos[0]);
3759 values[1] = emit_ffract(&ctx->ac, ctx->frag_pos[1]);
3760 return ac_build_gather_values(&ctx->ac, values, 2);
3761 }
3762
3763 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3764 const nir_intrinsic_instr *instr)
3765 {
3766 LLVMValueRef result[2];
3767 LLVMValueRef interp_param, attr_number;
3768 unsigned location;
3769 unsigned chan;
3770 LLVMValueRef src_c0, src_c1;
3771 LLVMValueRef src0;
3772 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3773 switch (instr->intrinsic) {
3774 case nir_intrinsic_interp_var_at_centroid:
3775 location = INTERP_CENTROID;
3776 break;
3777 case nir_intrinsic_interp_var_at_sample:
3778 case nir_intrinsic_interp_var_at_offset:
3779 location = INTERP_CENTER;
3780 src0 = get_src(ctx->nir, instr->src[0]);
3781 break;
3782 default:
3783 break;
3784 }
3785
3786 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3787 src_c0 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3788 src_c1 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3789 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3790 LLVMValueRef sample_position;
3791 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3792
3793 /* fetch sample ID */
3794 sample_position = load_sample_position(ctx, src0);
3795
3796 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3797 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3798 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3799 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3800 }
3801 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3802 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3803
3804 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3805 LLVMValueRef ij_out[2];
3806 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3807
3808 /*
3809 * take the I then J parameters, and the DDX/Y for it, and
3810 * calculate the IJ inputs for the interpolator.
3811 * temp1 = ddx * offset/sample.x + I;
3812 * interp_param.I = ddy * offset/sample.y + temp1;
3813 * temp1 = ddx * offset/sample.x + J;
3814 * interp_param.J = ddy * offset/sample.y + temp1;
3815 */
3816 for (unsigned i = 0; i < 2; i++) {
3817 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3818 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3819 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3820 ddxy_out, ix_ll, "");
3821 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3822 ddxy_out, iy_ll, "");
3823 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3824 interp_param, ix_ll, "");
3825 LLVMValueRef temp1, temp2;
3826
3827 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3828 ctx->f32, "");
3829
3830 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3831 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3832
3833 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3834 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3835
3836 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3837 temp2, ctx->i32, "");
3838 }
3839 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3840
3841 }
3842
3843 for (chan = 0; chan < 2; chan++) {
3844 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3845
3846 if (interp_param) {
3847 interp_param = LLVMBuildBitCast(ctx->builder,
3848 interp_param, LLVMVectorType(ctx->f32, 2), "");
3849 LLVMValueRef i = LLVMBuildExtractElement(
3850 ctx->builder, interp_param, ctx->i32zero, "");
3851 LLVMValueRef j = LLVMBuildExtractElement(
3852 ctx->builder, interp_param, ctx->i32one, "");
3853
3854 result[chan] = ac_build_fs_interp(&ctx->ac,
3855 llvm_chan, attr_number,
3856 ctx->prim_mask, i, j);
3857 } else {
3858 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3859 LLVMConstInt(ctx->i32, 2, false),
3860 llvm_chan, attr_number,
3861 ctx->prim_mask);
3862 }
3863 }
3864 return ac_build_gather_values(&ctx->ac, result, 2);
3865 }
3866
3867 static void
3868 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3869 const nir_intrinsic_instr *instr)
3870 {
3871 LLVMValueRef gs_next_vertex;
3872 LLVMValueRef can_emit, kill;
3873 int idx;
3874
3875 assert(instr->const_index[0] == 0);
3876 /* Write vertex attribute values to GSVS ring */
3877 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3878 ctx->gs_next_vertex,
3879 "");
3880
3881 /* If this thread has already emitted the declared maximum number of
3882 * vertices, kill it: excessive vertex emissions are not supposed to
3883 * have any effect, and GS threads have no externally observable
3884 * effects other than emitting vertices.
3885 */
3886 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3887 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3888
3889 kill = LLVMBuildSelect(ctx->builder, can_emit,
3890 LLVMConstReal(ctx->f32, 1.0f),
3891 LLVMConstReal(ctx->f32, -1.0f), "");
3892 ac_build_kill(&ctx->ac, kill);
3893
3894 /* loop num outputs */
3895 idx = 0;
3896 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3897 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
3898 int length = 4;
3899 int slot = idx;
3900 int slot_inc = 1;
3901
3902 if (!(ctx->output_mask & (1ull << i)))
3903 continue;
3904
3905 if (i == VARYING_SLOT_CLIP_DIST0) {
3906 /* pack clip and cull into a single set of slots */
3907 length = ctx->num_output_clips + ctx->num_output_culls;
3908 if (length > 4)
3909 slot_inc = 2;
3910 }
3911 for (unsigned j = 0; j < length; j++) {
3912 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3913 out_ptr[j], "");
3914 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3915 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3916 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3917
3918 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3919
3920 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3921 out_val, 1,
3922 voffset, ctx->gs2vs_offset, 0,
3923 1, 1, true, true);
3924 }
3925 idx += slot_inc;
3926 }
3927
3928 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3929 ctx->i32one, "");
3930 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3931
3932 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3933 }
3934
3935 static void
3936 visit_end_primitive(struct nir_to_llvm_context *ctx,
3937 const nir_intrinsic_instr *instr)
3938 {
3939 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3940 }
3941
3942 static LLVMValueRef
3943 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3944 const nir_intrinsic_instr *instr)
3945 {
3946 LLVMValueRef coord[4] = {
3947 ctx->tes_u,
3948 ctx->tes_v,
3949 ctx->f32zero,
3950 ctx->f32zero,
3951 };
3952
3953 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3954 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3955 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3956
3957 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3958 return LLVMBuildBitCast(ctx->builder, result,
3959 get_def_type(ctx->nir, &instr->dest.ssa), "");
3960 }
3961
3962 static void visit_intrinsic(struct ac_nir_context *ctx,
3963 nir_intrinsic_instr *instr)
3964 {
3965 LLVMValueRef result = NULL;
3966
3967 switch (instr->intrinsic) {
3968 case nir_intrinsic_load_work_group_id: {
3969 result = ctx->nctx->workgroup_ids;
3970 break;
3971 }
3972 case nir_intrinsic_load_base_vertex: {
3973 result = ctx->abi->base_vertex;
3974 break;
3975 }
3976 case nir_intrinsic_load_vertex_id_zero_base: {
3977 result = ctx->abi->vertex_id;
3978 break;
3979 }
3980 case nir_intrinsic_load_local_invocation_id: {
3981 result = ctx->nctx->local_invocation_ids;
3982 break;
3983 }
3984 case nir_intrinsic_load_base_instance:
3985 result = ctx->abi->start_instance;
3986 break;
3987 case nir_intrinsic_load_draw_id:
3988 result = ctx->abi->draw_id;
3989 break;
3990 case nir_intrinsic_load_invocation_id:
3991 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3992 result = unpack_param(ctx->nctx, ctx->nctx->tcs_rel_ids, 8, 5);
3993 else
3994 result = ctx->nctx->gs_invocation_id;
3995 break;
3996 case nir_intrinsic_load_primitive_id:
3997 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3998 ctx->nctx->shader_info->gs.uses_prim_id = true;
3999 result = ctx->nctx->gs_prim_id;
4000 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4001 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4002 result = ctx->nctx->tcs_patch_id;
4003 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4004 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4005 result = ctx->nctx->tes_patch_id;
4006 } else
4007 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4008 break;
4009 case nir_intrinsic_load_sample_id:
4010 ctx->nctx->shader_info->fs.force_persample = true;
4011 result = unpack_param(ctx->nctx, ctx->nctx->ancillary, 8, 4);
4012 break;
4013 case nir_intrinsic_load_sample_pos:
4014 ctx->nctx->shader_info->fs.force_persample = true;
4015 result = load_sample_pos(ctx->nctx);
4016 break;
4017 case nir_intrinsic_load_sample_mask_in:
4018 result = ctx->nctx->sample_coverage;
4019 break;
4020 case nir_intrinsic_load_front_face:
4021 result = ctx->nctx->front_face;
4022 break;
4023 case nir_intrinsic_load_instance_id:
4024 result = ctx->abi->instance_id;
4025 break;
4026 case nir_intrinsic_load_num_work_groups:
4027 result = ctx->nctx->num_work_groups;
4028 break;
4029 case nir_intrinsic_load_local_invocation_index:
4030 result = visit_load_local_invocation_index(ctx->nctx);
4031 break;
4032 case nir_intrinsic_load_push_constant:
4033 result = visit_load_push_constant(ctx->nctx, instr);
4034 break;
4035 case nir_intrinsic_vulkan_resource_index:
4036 result = visit_vulkan_resource_index(ctx->nctx, instr);
4037 break;
4038 case nir_intrinsic_store_ssbo:
4039 visit_store_ssbo(ctx->nctx, instr);
4040 break;
4041 case nir_intrinsic_load_ssbo:
4042 result = visit_load_buffer(ctx->nctx, instr);
4043 break;
4044 case nir_intrinsic_ssbo_atomic_add:
4045 case nir_intrinsic_ssbo_atomic_imin:
4046 case nir_intrinsic_ssbo_atomic_umin:
4047 case nir_intrinsic_ssbo_atomic_imax:
4048 case nir_intrinsic_ssbo_atomic_umax:
4049 case nir_intrinsic_ssbo_atomic_and:
4050 case nir_intrinsic_ssbo_atomic_or:
4051 case nir_intrinsic_ssbo_atomic_xor:
4052 case nir_intrinsic_ssbo_atomic_exchange:
4053 case nir_intrinsic_ssbo_atomic_comp_swap:
4054 result = visit_atomic_ssbo(ctx->nctx, instr);
4055 break;
4056 case nir_intrinsic_load_ubo:
4057 result = visit_load_ubo_buffer(ctx, instr);
4058 break;
4059 case nir_intrinsic_get_buffer_size:
4060 result = visit_get_buffer_size(ctx, instr);
4061 break;
4062 case nir_intrinsic_load_var:
4063 result = visit_load_var(ctx, instr);
4064 break;
4065 case nir_intrinsic_store_var:
4066 visit_store_var(ctx, instr);
4067 break;
4068 case nir_intrinsic_image_load:
4069 result = visit_image_load(ctx, instr);
4070 break;
4071 case nir_intrinsic_image_store:
4072 visit_image_store(ctx, instr);
4073 break;
4074 case nir_intrinsic_image_atomic_add:
4075 case nir_intrinsic_image_atomic_min:
4076 case nir_intrinsic_image_atomic_max:
4077 case nir_intrinsic_image_atomic_and:
4078 case nir_intrinsic_image_atomic_or:
4079 case nir_intrinsic_image_atomic_xor:
4080 case nir_intrinsic_image_atomic_exchange:
4081 case nir_intrinsic_image_atomic_comp_swap:
4082 result = visit_image_atomic(ctx, instr);
4083 break;
4084 case nir_intrinsic_image_size:
4085 result = visit_image_size(ctx, instr);
4086 break;
4087 case nir_intrinsic_discard:
4088 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4089 LLVMVoidTypeInContext(ctx->ac.context),
4090 NULL, 0, AC_FUNC_ATTR_LEGACY);
4091 break;
4092 case nir_intrinsic_discard_if:
4093 emit_discard_if(ctx->nctx, instr);
4094 break;
4095 case nir_intrinsic_memory_barrier:
4096 emit_waitcnt(ctx->nctx, VM_CNT);
4097 break;
4098 case nir_intrinsic_barrier:
4099 emit_barrier(ctx->nctx);
4100 break;
4101 case nir_intrinsic_var_atomic_add:
4102 case nir_intrinsic_var_atomic_imin:
4103 case nir_intrinsic_var_atomic_umin:
4104 case nir_intrinsic_var_atomic_imax:
4105 case nir_intrinsic_var_atomic_umax:
4106 case nir_intrinsic_var_atomic_and:
4107 case nir_intrinsic_var_atomic_or:
4108 case nir_intrinsic_var_atomic_xor:
4109 case nir_intrinsic_var_atomic_exchange:
4110 case nir_intrinsic_var_atomic_comp_swap:
4111 result = visit_var_atomic(ctx->nctx, instr);
4112 break;
4113 case nir_intrinsic_interp_var_at_centroid:
4114 case nir_intrinsic_interp_var_at_sample:
4115 case nir_intrinsic_interp_var_at_offset:
4116 result = visit_interp(ctx->nctx, instr);
4117 break;
4118 case nir_intrinsic_emit_vertex:
4119 visit_emit_vertex(ctx->nctx, instr);
4120 break;
4121 case nir_intrinsic_end_primitive:
4122 visit_end_primitive(ctx->nctx, instr);
4123 break;
4124 case nir_intrinsic_load_tess_coord:
4125 result = visit_load_tess_coord(ctx->nctx, instr);
4126 break;
4127 case nir_intrinsic_load_patch_vertices_in:
4128 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4129 break;
4130 default:
4131 fprintf(stderr, "Unknown intrinsic: ");
4132 nir_print_instr(&instr->instr, stderr);
4133 fprintf(stderr, "\n");
4134 break;
4135 }
4136 if (result) {
4137 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4138 }
4139 }
4140
4141 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4142 unsigned descriptor_set,
4143 unsigned base_index,
4144 unsigned constant_index,
4145 LLVMValueRef index,
4146 enum ac_descriptor_type desc_type,
4147 bool image, bool write)
4148 {
4149 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4150 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4151 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4152 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4153 unsigned offset = binding->offset;
4154 unsigned stride = binding->size;
4155 unsigned type_size;
4156 LLVMBuilderRef builder = ctx->builder;
4157 LLVMTypeRef type;
4158
4159 assert(base_index < layout->binding_count);
4160
4161 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4162 ctx->shader_info->fs.writes_memory = true;
4163
4164 switch (desc_type) {
4165 case AC_DESC_IMAGE:
4166 type = ctx->v8i32;
4167 type_size = 32;
4168 break;
4169 case AC_DESC_FMASK:
4170 type = ctx->v8i32;
4171 offset += 32;
4172 type_size = 32;
4173 break;
4174 case AC_DESC_SAMPLER:
4175 type = ctx->v4i32;
4176 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4177 offset += 64;
4178
4179 type_size = 16;
4180 break;
4181 case AC_DESC_BUFFER:
4182 type = ctx->v4i32;
4183 type_size = 16;
4184 break;
4185 default:
4186 unreachable("invalid desc_type\n");
4187 }
4188
4189 offset += constant_index * stride;
4190
4191 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4192 (!index || binding->immutable_samplers_equal)) {
4193 if (binding->immutable_samplers_equal)
4194 constant_index = 0;
4195
4196 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4197
4198 LLVMValueRef constants[] = {
4199 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4200 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4201 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4202 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4203 };
4204 return ac_build_gather_values(&ctx->ac, constants, 4);
4205 }
4206
4207 assert(stride % type_size == 0);
4208
4209 if (!index)
4210 index = ctx->i32zero;
4211
4212 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4213
4214 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4215 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4216
4217 return ac_build_indexed_load_const(&ctx->ac, list, index);
4218 }
4219
4220 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4221 const nir_deref_var *deref,
4222 enum ac_descriptor_type desc_type,
4223 bool image, bool write)
4224 {
4225 LLVMValueRef index = NULL;
4226 unsigned constant_index = 0;
4227 const nir_deref *tail = &deref->deref;
4228
4229 while (tail->child) {
4230 const nir_deref_array *child = nir_deref_as_array(tail->child);
4231 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4232
4233 if (!array_size)
4234 array_size = 1;
4235
4236 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4237
4238 if (child->deref_array_type == nir_deref_array_type_indirect) {
4239 LLVMValueRef indirect = get_src(ctx, child->indirect);
4240
4241 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4242 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4243
4244 if (!index)
4245 index = indirect;
4246 else
4247 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4248 }
4249
4250 constant_index += child->base_offset * array_size;
4251
4252 tail = &child->deref;
4253 }
4254
4255 return ctx->abi->load_sampler_desc(ctx->abi,
4256 deref->var->data.descriptor_set,
4257 deref->var->data.binding,
4258 constant_index, index,
4259 desc_type, image, write);
4260 }
4261
4262 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4263 struct ac_image_args *args,
4264 const nir_tex_instr *instr,
4265 nir_texop op,
4266 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4267 LLVMValueRef *param, unsigned count,
4268 unsigned dmask)
4269 {
4270 unsigned is_rect = 0;
4271 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4272
4273 if (op == nir_texop_lod)
4274 da = false;
4275 /* Pad to power of two vector */
4276 while (count < util_next_power_of_two(count))
4277 param[count++] = LLVMGetUndef(ctx->i32);
4278
4279 if (count > 1)
4280 args->addr = ac_build_gather_values(ctx, param, count);
4281 else
4282 args->addr = param[0];
4283
4284 args->resource = res_ptr;
4285 args->sampler = samp_ptr;
4286
4287 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4288 args->addr = param[0];
4289 return;
4290 }
4291
4292 args->dmask = dmask;
4293 args->unorm = is_rect;
4294 args->da = da;
4295 }
4296
4297 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4298 *
4299 * SI-CI:
4300 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4301 * filtering manually. The driver sets img7 to a mask clearing
4302 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4303 * s_and_b32 samp0, samp0, img7
4304 *
4305 * VI:
4306 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4307 */
4308 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4309 LLVMValueRef res, LLVMValueRef samp)
4310 {
4311 LLVMBuilderRef builder = ctx->ac.builder;
4312 LLVMValueRef img7, samp0;
4313
4314 if (ctx->abi->chip_class >= VI)
4315 return samp;
4316
4317 img7 = LLVMBuildExtractElement(builder, res,
4318 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4319 samp0 = LLVMBuildExtractElement(builder, samp,
4320 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4321 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4322 return LLVMBuildInsertElement(builder, samp, samp0,
4323 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4324 }
4325
4326 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4327 nir_tex_instr *instr,
4328 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4329 LLVMValueRef *fmask_ptr)
4330 {
4331 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4332 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, false, false);
4333 else
4334 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, false, false);
4335 if (samp_ptr) {
4336 if (instr->sampler)
4337 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, false, false);
4338 else
4339 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, false, false);
4340 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4341 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4342 }
4343 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4344 instr->op == nir_texop_samples_identical))
4345 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, false, false);
4346 }
4347
4348 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4349 LLVMValueRef coord)
4350 {
4351 coord = to_float(ctx, coord);
4352 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4353 coord = to_integer(ctx, coord);
4354 return coord;
4355 }
4356
4357 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4358 {
4359 LLVMValueRef result = NULL;
4360 struct ac_image_args args = { 0 };
4361 unsigned dmask = 0xf;
4362 LLVMValueRef address[16];
4363 LLVMValueRef coords[5];
4364 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4365 LLVMValueRef bias = NULL, offsets = NULL;
4366 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4367 LLVMValueRef ddx = NULL, ddy = NULL;
4368 LLVMValueRef derivs[6];
4369 unsigned chan, count = 0;
4370 unsigned const_src = 0, num_deriv_comp = 0;
4371 bool lod_is_zero = false;
4372
4373 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4374
4375 for (unsigned i = 0; i < instr->num_srcs; i++) {
4376 switch (instr->src[i].src_type) {
4377 case nir_tex_src_coord:
4378 coord = get_src(ctx, instr->src[i].src);
4379 break;
4380 case nir_tex_src_projector:
4381 break;
4382 case nir_tex_src_comparator:
4383 comparator = get_src(ctx, instr->src[i].src);
4384 break;
4385 case nir_tex_src_offset:
4386 offsets = get_src(ctx, instr->src[i].src);
4387 const_src = i;
4388 break;
4389 case nir_tex_src_bias:
4390 bias = get_src(ctx, instr->src[i].src);
4391 break;
4392 case nir_tex_src_lod: {
4393 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4394
4395 if (val && val->i32[0] == 0)
4396 lod_is_zero = true;
4397 lod = get_src(ctx, instr->src[i].src);
4398 break;
4399 }
4400 case nir_tex_src_ms_index:
4401 sample_index = get_src(ctx, instr->src[i].src);
4402 break;
4403 case nir_tex_src_ms_mcs:
4404 break;
4405 case nir_tex_src_ddx:
4406 ddx = get_src(ctx, instr->src[i].src);
4407 num_deriv_comp = instr->src[i].src.ssa->num_components;
4408 break;
4409 case nir_tex_src_ddy:
4410 ddy = get_src(ctx, instr->src[i].src);
4411 break;
4412 case nir_tex_src_texture_offset:
4413 case nir_tex_src_sampler_offset:
4414 case nir_tex_src_plane:
4415 default:
4416 break;
4417 }
4418 }
4419
4420 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4421 result = get_buffer_size(ctx, res_ptr, true);
4422 goto write_result;
4423 }
4424
4425 if (instr->op == nir_texop_texture_samples) {
4426 LLVMValueRef res, samples, is_msaa;
4427 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4428 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4429 LLVMConstInt(ctx->ac.i32, 3, false), "");
4430 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4431 LLVMConstInt(ctx->ac.i32, 28, false), "");
4432 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4433 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4434 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4435 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4436
4437 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4438 LLVMConstInt(ctx->ac.i32, 16, false), "");
4439 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4440 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4441 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4442 samples, "");
4443 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4444 ctx->ac.i32_1, "");
4445 result = samples;
4446 goto write_result;
4447 }
4448
4449 if (coord)
4450 for (chan = 0; chan < instr->coord_components; chan++)
4451 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4452
4453 if (offsets && instr->op != nir_texop_txf) {
4454 LLVMValueRef offset[3], pack;
4455 for (chan = 0; chan < 3; ++chan)
4456 offset[chan] = ctx->ac.i32_0;
4457
4458 args.offset = true;
4459 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4460 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4461 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4462 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4463 if (chan)
4464 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4465 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4466 }
4467 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4468 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4469 address[count++] = pack;
4470
4471 }
4472 /* pack LOD bias value */
4473 if (instr->op == nir_texop_txb && bias) {
4474 address[count++] = bias;
4475 }
4476
4477 /* Pack depth comparison value */
4478 if (instr->is_shadow && comparator) {
4479 address[count++] = llvm_extract_elem(&ctx->ac, comparator, 0);
4480 }
4481
4482 /* pack derivatives */
4483 if (ddx || ddy) {
4484 switch (instr->sampler_dim) {
4485 case GLSL_SAMPLER_DIM_3D:
4486 case GLSL_SAMPLER_DIM_CUBE:
4487 num_deriv_comp = 3;
4488 break;
4489 case GLSL_SAMPLER_DIM_2D:
4490 default:
4491 num_deriv_comp = 2;
4492 break;
4493 case GLSL_SAMPLER_DIM_1D:
4494 num_deriv_comp = 1;
4495 break;
4496 }
4497
4498 for (unsigned i = 0; i < num_deriv_comp; i++) {
4499 derivs[i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4500 derivs[num_deriv_comp + i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4501 }
4502 }
4503
4504 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4505 if (instr->is_array && instr->op != nir_texop_lod)
4506 coords[3] = apply_round_slice(&ctx->ac, coords[3]);
4507 for (chan = 0; chan < instr->coord_components; chan++)
4508 coords[chan] = to_float(&ctx->ac, coords[chan]);
4509 if (instr->coord_components == 3)
4510 coords[3] = LLVMGetUndef(ctx->ac.f32);
4511 ac_prepare_cube_coords(&ctx->ac,
4512 instr->op == nir_texop_txd, instr->is_array,
4513 coords, derivs);
4514 if (num_deriv_comp)
4515 num_deriv_comp--;
4516 }
4517
4518 if (ddx || ddy) {
4519 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4520 address[count++] = derivs[i];
4521 }
4522
4523 /* Pack texture coordinates */
4524 if (coord) {
4525 address[count++] = coords[0];
4526 if (instr->coord_components > 1) {
4527 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4528 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4529 }
4530 address[count++] = coords[1];
4531 }
4532 if (instr->coord_components > 2) {
4533 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4534 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4535 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4536 instr->op != nir_texop_txf) {
4537 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4538 }
4539 address[count++] = coords[2];
4540 }
4541 }
4542
4543 /* Pack LOD */
4544 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4545 instr->op == nir_texop_txf)) {
4546 address[count++] = lod;
4547 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4548 address[count++] = sample_index;
4549 } else if(instr->op == nir_texop_txs) {
4550 count = 0;
4551 if (lod)
4552 address[count++] = lod;
4553 else
4554 address[count++] = ctx->ac.i32_0;
4555 }
4556
4557 for (chan = 0; chan < count; chan++) {
4558 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4559 address[chan], ctx->ac.i32, "");
4560 }
4561
4562 if (instr->op == nir_texop_samples_identical) {
4563 LLVMValueRef txf_address[4];
4564 struct ac_image_args txf_args = { 0 };
4565 unsigned txf_count = count;
4566 memcpy(txf_address, address, sizeof(txf_address));
4567
4568 if (!instr->is_array)
4569 txf_address[2] = ctx->ac.i32_0;
4570 txf_address[3] = ctx->ac.i32_0;
4571
4572 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4573 fmask_ptr, NULL,
4574 txf_address, txf_count, 0xf);
4575
4576 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4577
4578 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4579 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4580 goto write_result;
4581 }
4582
4583 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4584 instr->op != nir_texop_txs) {
4585 unsigned sample_chan = instr->is_array ? 3 : 2;
4586 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4587 address[0],
4588 address[1],
4589 instr->is_array ? address[2] : NULL,
4590 address[sample_chan],
4591 fmask_ptr);
4592 }
4593
4594 if (offsets && instr->op == nir_texop_txf) {
4595 nir_const_value *const_offset =
4596 nir_src_as_const_value(instr->src[const_src].src);
4597 int num_offsets = instr->src[const_src].src.ssa->num_components;
4598 assert(const_offset);
4599 num_offsets = MIN2(num_offsets, instr->coord_components);
4600 if (num_offsets > 2)
4601 address[2] = LLVMBuildAdd(ctx->ac.builder,
4602 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4603 if (num_offsets > 1)
4604 address[1] = LLVMBuildAdd(ctx->ac.builder,
4605 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4606 address[0] = LLVMBuildAdd(ctx->ac.builder,
4607 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4608
4609 }
4610
4611 /* TODO TG4 support */
4612 if (instr->op == nir_texop_tg4) {
4613 if (instr->is_shadow)
4614 dmask = 1;
4615 else
4616 dmask = 1 << instr->component;
4617 }
4618 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4619 res_ptr, samp_ptr, address, count, dmask);
4620
4621 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4622
4623 if (instr->op == nir_texop_query_levels)
4624 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4625 else if (instr->is_shadow && instr->is_new_style_shadow &&
4626 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4627 instr->op != nir_texop_tg4)
4628 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4629 else if (instr->op == nir_texop_txs &&
4630 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4631 instr->is_array) {
4632 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4633 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4634 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4635 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4636 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4637 } else if (instr->dest.ssa.num_components != 4)
4638 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4639
4640 write_result:
4641 if (result) {
4642 assert(instr->dest.is_ssa);
4643 result = to_integer(&ctx->ac, result);
4644 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4645 }
4646 }
4647
4648
4649 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4650 {
4651 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4652 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4653
4654 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4655 _mesa_hash_table_insert(ctx->phis, instr, result);
4656 }
4657
4658 static void visit_post_phi(struct ac_nir_context *ctx,
4659 nir_phi_instr *instr,
4660 LLVMValueRef llvm_phi)
4661 {
4662 nir_foreach_phi_src(src, instr) {
4663 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4664 LLVMValueRef llvm_src = get_src(ctx, src->src);
4665
4666 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4667 }
4668 }
4669
4670 static void phi_post_pass(struct ac_nir_context *ctx)
4671 {
4672 struct hash_entry *entry;
4673 hash_table_foreach(ctx->phis, entry) {
4674 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4675 (LLVMValueRef)entry->data);
4676 }
4677 }
4678
4679
4680 static void visit_ssa_undef(struct ac_nir_context *ctx,
4681 const nir_ssa_undef_instr *instr)
4682 {
4683 unsigned num_components = instr->def.num_components;
4684 LLVMValueRef undef;
4685
4686 if (num_components == 1)
4687 undef = LLVMGetUndef(ctx->ac.i32);
4688 else {
4689 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4690 }
4691 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4692 }
4693
4694 static void visit_jump(struct ac_nir_context *ctx,
4695 const nir_jump_instr *instr)
4696 {
4697 switch (instr->type) {
4698 case nir_jump_break:
4699 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4700 LLVMClearInsertionPosition(ctx->ac.builder);
4701 break;
4702 case nir_jump_continue:
4703 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4704 LLVMClearInsertionPosition(ctx->ac.builder);
4705 break;
4706 default:
4707 fprintf(stderr, "Unknown NIR jump instr: ");
4708 nir_print_instr(&instr->instr, stderr);
4709 fprintf(stderr, "\n");
4710 abort();
4711 }
4712 }
4713
4714 static void visit_cf_list(struct ac_nir_context *ctx,
4715 struct exec_list *list);
4716
4717 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4718 {
4719 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4720 nir_foreach_instr(instr, block)
4721 {
4722 switch (instr->type) {
4723 case nir_instr_type_alu:
4724 visit_alu(ctx, nir_instr_as_alu(instr));
4725 break;
4726 case nir_instr_type_load_const:
4727 visit_load_const(ctx, nir_instr_as_load_const(instr));
4728 break;
4729 case nir_instr_type_intrinsic:
4730 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4731 break;
4732 case nir_instr_type_tex:
4733 visit_tex(ctx, nir_instr_as_tex(instr));
4734 break;
4735 case nir_instr_type_phi:
4736 visit_phi(ctx, nir_instr_as_phi(instr));
4737 break;
4738 case nir_instr_type_ssa_undef:
4739 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4740 break;
4741 case nir_instr_type_jump:
4742 visit_jump(ctx, nir_instr_as_jump(instr));
4743 break;
4744 default:
4745 fprintf(stderr, "Unknown NIR instr type: ");
4746 nir_print_instr(instr, stderr);
4747 fprintf(stderr, "\n");
4748 abort();
4749 }
4750 }
4751
4752 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4753 }
4754
4755 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4756 {
4757 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4758
4759 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4760 LLVMBasicBlockRef merge_block =
4761 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4762 LLVMBasicBlockRef if_block =
4763 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4764 LLVMBasicBlockRef else_block = merge_block;
4765 if (!exec_list_is_empty(&if_stmt->else_list))
4766 else_block = LLVMAppendBasicBlockInContext(
4767 ctx->ac.context, fn, "");
4768
4769 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4770 LLVMConstInt(ctx->ac.i32, 0, false), "");
4771 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4772
4773 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4774 visit_cf_list(ctx, &if_stmt->then_list);
4775 if (LLVMGetInsertBlock(ctx->ac.builder))
4776 LLVMBuildBr(ctx->ac.builder, merge_block);
4777
4778 if (!exec_list_is_empty(&if_stmt->else_list)) {
4779 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4780 visit_cf_list(ctx, &if_stmt->else_list);
4781 if (LLVMGetInsertBlock(ctx->ac.builder))
4782 LLVMBuildBr(ctx->ac.builder, merge_block);
4783 }
4784
4785 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4786 }
4787
4788 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4789 {
4790 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4791 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4792 LLVMBasicBlockRef break_parent = ctx->break_block;
4793
4794 ctx->continue_block =
4795 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4796 ctx->break_block =
4797 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4798
4799 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4800 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4801 visit_cf_list(ctx, &loop->body);
4802
4803 if (LLVMGetInsertBlock(ctx->ac.builder))
4804 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4805 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4806
4807 ctx->continue_block = continue_parent;
4808 ctx->break_block = break_parent;
4809 }
4810
4811 static void visit_cf_list(struct ac_nir_context *ctx,
4812 struct exec_list *list)
4813 {
4814 foreach_list_typed(nir_cf_node, node, node, list)
4815 {
4816 switch (node->type) {
4817 case nir_cf_node_block:
4818 visit_block(ctx, nir_cf_node_as_block(node));
4819 break;
4820
4821 case nir_cf_node_if:
4822 visit_if(ctx, nir_cf_node_as_if(node));
4823 break;
4824
4825 case nir_cf_node_loop:
4826 visit_loop(ctx, nir_cf_node_as_loop(node));
4827 break;
4828
4829 default:
4830 assert(0);
4831 }
4832 }
4833 }
4834
4835 static void
4836 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4837 struct nir_variable *variable)
4838 {
4839 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4840 LLVMValueRef t_offset;
4841 LLVMValueRef t_list;
4842 LLVMValueRef input;
4843 LLVMValueRef buffer_index;
4844 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4845 int idx = variable->data.location;
4846 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4847
4848 variable->data.driver_location = idx * 4;
4849
4850 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4851 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
4852 ctx->abi.start_instance, "");
4853 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4854 ctx->shader_info->vs.vgpr_comp_cnt);
4855 } else
4856 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
4857 ctx->abi.base_vertex, "");
4858
4859 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4860 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4861
4862 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4863
4864 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4865 buffer_index,
4866 LLVMConstInt(ctx->i32, 0, false),
4867 true);
4868
4869 for (unsigned chan = 0; chan < 4; chan++) {
4870 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4871 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4872 to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
4873 input, llvm_chan, ""));
4874 }
4875 }
4876 }
4877
4878 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4879 unsigned attr,
4880 LLVMValueRef interp_param,
4881 LLVMValueRef prim_mask,
4882 LLVMValueRef result[4])
4883 {
4884 LLVMValueRef attr_number;
4885 unsigned chan;
4886 LLVMValueRef i, j;
4887 bool interp = interp_param != NULL;
4888
4889 attr_number = LLVMConstInt(ctx->i32, attr, false);
4890
4891 /* fs.constant returns the param from the middle vertex, so it's not
4892 * really useful for flat shading. It's meant to be used for custom
4893 * interpolation (but the intrinsic can't fetch from the other two
4894 * vertices).
4895 *
4896 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4897 * to do the right thing. The only reason we use fs.constant is that
4898 * fs.interp cannot be used on integers, because they can be equal
4899 * to NaN.
4900 */
4901 if (interp) {
4902 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4903 LLVMVectorType(ctx->f32, 2), "");
4904
4905 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4906 ctx->i32zero, "");
4907 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4908 ctx->i32one, "");
4909 }
4910
4911 for (chan = 0; chan < 4; chan++) {
4912 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4913
4914 if (interp) {
4915 result[chan] = ac_build_fs_interp(&ctx->ac,
4916 llvm_chan,
4917 attr_number,
4918 prim_mask, i, j);
4919 } else {
4920 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4921 LLVMConstInt(ctx->i32, 2, false),
4922 llvm_chan,
4923 attr_number,
4924 prim_mask);
4925 }
4926 }
4927 }
4928
4929 static void
4930 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4931 struct nir_variable *variable)
4932 {
4933 int idx = variable->data.location;
4934 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4935 LLVMValueRef interp;
4936
4937 variable->data.driver_location = idx * 4;
4938 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4939
4940 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4941 unsigned interp_type;
4942 if (variable->data.sample) {
4943 interp_type = INTERP_SAMPLE;
4944 ctx->shader_info->fs.force_persample = true;
4945 } else if (variable->data.centroid)
4946 interp_type = INTERP_CENTROID;
4947 else
4948 interp_type = INTERP_CENTER;
4949
4950 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4951 } else
4952 interp = NULL;
4953
4954 for (unsigned i = 0; i < attrib_count; ++i)
4955 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4956
4957 }
4958
4959 static void
4960 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4961 struct nir_variable *variable)
4962 {
4963 switch (ctx->stage) {
4964 case MESA_SHADER_VERTEX:
4965 handle_vs_input_decl(ctx, variable);
4966 break;
4967 case MESA_SHADER_FRAGMENT:
4968 handle_fs_input_decl(ctx, variable);
4969 break;
4970 default:
4971 break;
4972 }
4973
4974 }
4975
4976 static void
4977 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4978 struct nir_shader *nir)
4979 {
4980 unsigned index = 0;
4981 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4982 LLVMValueRef interp_param;
4983 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4984
4985 if (!(ctx->input_mask & (1ull << i)))
4986 continue;
4987
4988 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4989 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4990 interp_param = *inputs;
4991 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4992 inputs);
4993
4994 if (!interp_param)
4995 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4996 ++index;
4997 } else if (i == VARYING_SLOT_POS) {
4998 for(int i = 0; i < 3; ++i)
4999 inputs[i] = ctx->frag_pos[i];
5000
5001 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
5002 }
5003 }
5004 ctx->shader_info->fs.num_interp = index;
5005 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5006 ctx->shader_info->fs.has_pcoord = true;
5007 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5008 ctx->shader_info->fs.prim_id_input = true;
5009 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5010 ctx->shader_info->fs.layer_input = true;
5011 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5012 }
5013
5014 static LLVMValueRef
5015 ac_build_alloca(struct ac_llvm_context *ac,
5016 LLVMTypeRef type,
5017 const char *name)
5018 {
5019 LLVMBuilderRef builder = ac->builder;
5020 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5021 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5022 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5023 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5024 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5025 LLVMValueRef res;
5026
5027 if (first_instr) {
5028 LLVMPositionBuilderBefore(first_builder, first_instr);
5029 } else {
5030 LLVMPositionBuilderAtEnd(first_builder, first_block);
5031 }
5032
5033 res = LLVMBuildAlloca(first_builder, type, name);
5034 LLVMBuildStore(builder, LLVMConstNull(type), res);
5035
5036 LLVMDisposeBuilder(first_builder);
5037
5038 return res;
5039 }
5040
5041 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5042 LLVMTypeRef type,
5043 const char *name)
5044 {
5045 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5046 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5047 return ptr;
5048 }
5049
5050 static void
5051 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5052 struct nir_variable *variable)
5053 {
5054 int idx = variable->data.location + variable->data.index;
5055 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5056 uint64_t mask_attribs;
5057
5058 variable->data.driver_location = idx * 4;
5059
5060 /* tess ctrl has it's own load/store paths for outputs */
5061 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5062 return;
5063
5064 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5065 if (ctx->stage == MESA_SHADER_VERTEX ||
5066 ctx->stage == MESA_SHADER_TESS_EVAL ||
5067 ctx->stage == MESA_SHADER_GEOMETRY) {
5068 if (idx == VARYING_SLOT_CLIP_DIST0) {
5069 int length = ctx->num_output_clips + ctx->num_output_culls;
5070 if (ctx->stage == MESA_SHADER_VERTEX) {
5071 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5072 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5073 }
5074 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5075 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5076 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5077 }
5078
5079 if (length > 4)
5080 attrib_count = 2;
5081 else
5082 attrib_count = 1;
5083 mask_attribs = 1ull << idx;
5084 }
5085 }
5086
5087 ctx->output_mask |= mask_attribs;
5088 }
5089
5090 static void
5091 handle_shader_output_decl(struct ac_nir_context *ctx,
5092 struct nir_shader *nir,
5093 struct nir_variable *variable)
5094 {
5095 unsigned output_loc = variable->data.driver_location / 4;
5096 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5097
5098 /* tess ctrl has it's own load/store paths for outputs */
5099 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5100 return;
5101
5102 if (ctx->stage == MESA_SHADER_VERTEX ||
5103 ctx->stage == MESA_SHADER_TESS_EVAL ||
5104 ctx->stage == MESA_SHADER_GEOMETRY) {
5105 int idx = variable->data.location + variable->data.index;
5106 if (idx == VARYING_SLOT_CLIP_DIST0) {
5107 int length = nir->info.clip_distance_array_size +
5108 nir->info.cull_distance_array_size;
5109
5110 if (length > 4)
5111 attrib_count = 2;
5112 else
5113 attrib_count = 1;
5114 }
5115 }
5116
5117 for (unsigned i = 0; i < attrib_count; ++i) {
5118 for (unsigned chan = 0; chan < 4; chan++) {
5119 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5120 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5121 }
5122 }
5123 }
5124
5125 static LLVMTypeRef
5126 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5127 enum glsl_base_type type)
5128 {
5129 switch (type) {
5130 case GLSL_TYPE_INT:
5131 case GLSL_TYPE_UINT:
5132 case GLSL_TYPE_BOOL:
5133 case GLSL_TYPE_SUBROUTINE:
5134 return ctx->i32;
5135 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5136 return ctx->f32;
5137 case GLSL_TYPE_INT64:
5138 case GLSL_TYPE_UINT64:
5139 return ctx->i64;
5140 case GLSL_TYPE_DOUBLE:
5141 return ctx->f64;
5142 default:
5143 unreachable("unknown GLSL type");
5144 }
5145 }
5146
5147 static LLVMTypeRef
5148 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5149 const struct glsl_type *type)
5150 {
5151 if (glsl_type_is_scalar(type)) {
5152 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5153 }
5154
5155 if (glsl_type_is_vector(type)) {
5156 return LLVMVectorType(
5157 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5158 glsl_get_vector_elements(type));
5159 }
5160
5161 if (glsl_type_is_matrix(type)) {
5162 return LLVMArrayType(
5163 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5164 glsl_get_matrix_columns(type));
5165 }
5166
5167 if (glsl_type_is_array(type)) {
5168 return LLVMArrayType(
5169 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5170 glsl_get_length(type));
5171 }
5172
5173 assert(glsl_type_is_struct(type));
5174
5175 LLVMTypeRef member_types[glsl_get_length(type)];
5176
5177 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5178 member_types[i] =
5179 glsl_to_llvm_type(ctx,
5180 glsl_get_struct_field(type, i));
5181 }
5182
5183 return LLVMStructTypeInContext(ctx->context, member_types,
5184 glsl_get_length(type), false);
5185 }
5186
5187 static void
5188 setup_locals(struct ac_nir_context *ctx,
5189 struct nir_function *func)
5190 {
5191 int i, j;
5192 ctx->num_locals = 0;
5193 nir_foreach_variable(variable, &func->impl->locals) {
5194 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5195 variable->data.driver_location = ctx->num_locals * 4;
5196 ctx->num_locals += attrib_count;
5197 }
5198 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5199 if (!ctx->locals)
5200 return;
5201
5202 for (i = 0; i < ctx->num_locals; i++) {
5203 for (j = 0; j < 4; j++) {
5204 ctx->locals[i * 4 + j] =
5205 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5206 }
5207 }
5208 }
5209
5210 static void
5211 setup_shared(struct ac_nir_context *ctx,
5212 struct nir_shader *nir)
5213 {
5214 nir_foreach_variable(variable, &nir->shared) {
5215 LLVMValueRef shared =
5216 LLVMAddGlobalInAddressSpace(
5217 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5218 variable->name ? variable->name : "",
5219 LOCAL_ADDR_SPACE);
5220 _mesa_hash_table_insert(ctx->vars, variable, shared);
5221 }
5222 }
5223
5224 static LLVMValueRef
5225 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5226 {
5227 v = to_float(ctx, v);
5228 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5229 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5230 }
5231
5232
5233 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5234 LLVMValueRef src0, LLVMValueRef src1)
5235 {
5236 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5237 LLVMValueRef comp[2];
5238
5239 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5240 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5241 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5242 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5243 }
5244
5245 /* Initialize arguments for the shader export intrinsic */
5246 static void
5247 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5248 LLVMValueRef *values,
5249 unsigned target,
5250 struct ac_export_args *args)
5251 {
5252 /* Default is 0xf. Adjusted below depending on the format. */
5253 args->enabled_channels = 0xf;
5254
5255 /* Specify whether the EXEC mask represents the valid mask */
5256 args->valid_mask = 0;
5257
5258 /* Specify whether this is the last export */
5259 args->done = 0;
5260
5261 /* Specify the target we are exporting */
5262 args->target = target;
5263
5264 args->compr = false;
5265 args->out[0] = LLVMGetUndef(ctx->f32);
5266 args->out[1] = LLVMGetUndef(ctx->f32);
5267 args->out[2] = LLVMGetUndef(ctx->f32);
5268 args->out[3] = LLVMGetUndef(ctx->f32);
5269
5270 if (!values)
5271 return;
5272
5273 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5274 LLVMValueRef val[4];
5275 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5276 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5277 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5278
5279 switch(col_format) {
5280 case V_028714_SPI_SHADER_ZERO:
5281 args->enabled_channels = 0; /* writemask */
5282 args->target = V_008DFC_SQ_EXP_NULL;
5283 break;
5284
5285 case V_028714_SPI_SHADER_32_R:
5286 args->enabled_channels = 1;
5287 args->out[0] = values[0];
5288 break;
5289
5290 case V_028714_SPI_SHADER_32_GR:
5291 args->enabled_channels = 0x3;
5292 args->out[0] = values[0];
5293 args->out[1] = values[1];
5294 break;
5295
5296 case V_028714_SPI_SHADER_32_AR:
5297 args->enabled_channels = 0x9;
5298 args->out[0] = values[0];
5299 args->out[3] = values[3];
5300 break;
5301
5302 case V_028714_SPI_SHADER_FP16_ABGR:
5303 args->compr = 1;
5304
5305 for (unsigned chan = 0; chan < 2; chan++) {
5306 LLVMValueRef pack_args[2] = {
5307 values[2 * chan],
5308 values[2 * chan + 1]
5309 };
5310 LLVMValueRef packed;
5311
5312 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5313 args->out[chan] = packed;
5314 }
5315 break;
5316
5317 case V_028714_SPI_SHADER_UNORM16_ABGR:
5318 for (unsigned chan = 0; chan < 4; chan++) {
5319 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5320 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5321 LLVMConstReal(ctx->f32, 65535), "");
5322 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5323 LLVMConstReal(ctx->f32, 0.5), "");
5324 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5325 ctx->i32, "");
5326 }
5327
5328 args->compr = 1;
5329 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5330 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5331 break;
5332
5333 case V_028714_SPI_SHADER_SNORM16_ABGR:
5334 for (unsigned chan = 0; chan < 4; chan++) {
5335 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5336 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5337 LLVMConstReal(ctx->f32, 32767), "");
5338
5339 /* If positive, add 0.5, else add -0.5. */
5340 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5341 LLVMBuildSelect(ctx->builder,
5342 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5343 val[chan], ctx->f32zero, ""),
5344 LLVMConstReal(ctx->f32, 0.5),
5345 LLVMConstReal(ctx->f32, -0.5), ""), "");
5346 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5347 }
5348
5349 args->compr = 1;
5350 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5351 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5352 break;
5353
5354 case V_028714_SPI_SHADER_UINT16_ABGR: {
5355 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
5356
5357 for (unsigned chan = 0; chan < 4; chan++) {
5358 val[chan] = to_integer(&ctx->ac, values[chan]);
5359 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], max);
5360 }
5361
5362 args->compr = 1;
5363 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5364 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5365 break;
5366 }
5367
5368 case V_028714_SPI_SHADER_SINT16_ABGR: {
5369 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5370 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5371
5372 /* Clamp. */
5373 for (unsigned chan = 0; chan < 4; chan++) {
5374 val[chan] = to_integer(&ctx->ac, values[chan]);
5375 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], max);
5376 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], min);
5377 }
5378
5379 args->compr = 1;
5380 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5381 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5382 break;
5383 }
5384
5385 default:
5386 case V_028714_SPI_SHADER_32_ABGR:
5387 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5388 break;
5389 }
5390 } else
5391 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5392
5393 for (unsigned i = 0; i < 4; ++i)
5394 args->out[i] = to_float(&ctx->ac, args->out[i]);
5395 }
5396
5397 static void
5398 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5399 bool export_prim_id,
5400 struct ac_vs_output_info *outinfo)
5401 {
5402 uint32_t param_count = 0;
5403 unsigned target;
5404 unsigned pos_idx, num_pos_exports = 0;
5405 struct ac_export_args args, pos_args[4] = {};
5406 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5407 int i;
5408
5409 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5410 sizeof(outinfo->vs_output_param_offset));
5411
5412 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5413 LLVMValueRef slots[8];
5414 unsigned j;
5415
5416 if (outinfo->cull_dist_mask)
5417 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5418
5419 i = VARYING_SLOT_CLIP_DIST0;
5420 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5421 slots[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5422 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5423
5424 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5425 slots[i] = LLVMGetUndef(ctx->f32);
5426
5427 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5428 target = V_008DFC_SQ_EXP_POS + 3;
5429 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5430 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5431 &args, sizeof(args));
5432 }
5433
5434 target = V_008DFC_SQ_EXP_POS + 2;
5435 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5436 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5437 &args, sizeof(args));
5438
5439 }
5440
5441 LLVMValueRef pos_values[4] = {ctx->f32zero, ctx->f32zero, ctx->f32zero, ctx->f32one};
5442 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5443 for (unsigned j = 0; j < 4; j++)
5444 pos_values[j] = LLVMBuildLoad(ctx->builder,
5445 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5446 }
5447 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5448
5449 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5450 outinfo->writes_pointsize = true;
5451 psize_value = LLVMBuildLoad(ctx->builder,
5452 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5453 }
5454
5455 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5456 outinfo->writes_layer = true;
5457 layer_value = LLVMBuildLoad(ctx->builder,
5458 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5459 }
5460
5461 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5462 outinfo->writes_viewport_index = true;
5463 viewport_index_value = LLVMBuildLoad(ctx->builder,
5464 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5465 }
5466
5467 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5468 (outinfo->writes_layer == true ? 4 : 0) |
5469 (outinfo->writes_viewport_index == true ? 8 : 0));
5470 if (mask) {
5471 pos_args[1].enabled_channels = mask;
5472 pos_args[1].valid_mask = 0;
5473 pos_args[1].done = 0;
5474 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5475 pos_args[1].compr = 0;
5476 pos_args[1].out[0] = ctx->f32zero; /* X */
5477 pos_args[1].out[1] = ctx->f32zero; /* Y */
5478 pos_args[1].out[2] = ctx->f32zero; /* Z */
5479 pos_args[1].out[3] = ctx->f32zero; /* W */
5480
5481 if (outinfo->writes_pointsize == true)
5482 pos_args[1].out[0] = psize_value;
5483 if (outinfo->writes_layer == true)
5484 pos_args[1].out[2] = layer_value;
5485 if (outinfo->writes_viewport_index == true)
5486 pos_args[1].out[3] = viewport_index_value;
5487 }
5488 for (i = 0; i < 4; i++) {
5489 if (pos_args[i].out[0])
5490 num_pos_exports++;
5491 }
5492
5493 pos_idx = 0;
5494 for (i = 0; i < 4; i++) {
5495 if (!pos_args[i].out[0])
5496 continue;
5497
5498 /* Specify the target we are exporting */
5499 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5500 if (pos_idx == num_pos_exports)
5501 pos_args[i].done = 1;
5502 ac_build_export(&ctx->ac, &pos_args[i]);
5503 }
5504
5505 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5506 LLVMValueRef values[4];
5507 if (!(ctx->output_mask & (1ull << i)))
5508 continue;
5509
5510 for (unsigned j = 0; j < 4; j++)
5511 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5512 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5513
5514 if (i == VARYING_SLOT_LAYER) {
5515 target = V_008DFC_SQ_EXP_PARAM + param_count;
5516 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5517 param_count++;
5518 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5519 target = V_008DFC_SQ_EXP_PARAM + param_count;
5520 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5521 param_count++;
5522 } else if (i >= VARYING_SLOT_VAR0) {
5523 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5524 target = V_008DFC_SQ_EXP_PARAM + param_count;
5525 outinfo->vs_output_param_offset[i] = param_count;
5526 param_count++;
5527 } else
5528 continue;
5529
5530 si_llvm_init_export_args(ctx, values, target, &args);
5531
5532 if (target >= V_008DFC_SQ_EXP_POS &&
5533 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5534 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5535 &args, sizeof(args));
5536 } else {
5537 ac_build_export(&ctx->ac, &args);
5538 }
5539 }
5540
5541 if (export_prim_id) {
5542 LLVMValueRef values[4];
5543 target = V_008DFC_SQ_EXP_PARAM + param_count;
5544 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5545 param_count++;
5546
5547 values[0] = ctx->vs_prim_id;
5548 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5549 ctx->shader_info->vs.vgpr_comp_cnt);
5550 for (unsigned j = 1; j < 4; j++)
5551 values[j] = ctx->f32zero;
5552 si_llvm_init_export_args(ctx, values, target, &args);
5553 ac_build_export(&ctx->ac, &args);
5554 outinfo->export_prim_id = true;
5555 }
5556
5557 outinfo->pos_exports = num_pos_exports;
5558 outinfo->param_exports = param_count;
5559 }
5560
5561 static void
5562 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5563 struct ac_es_output_info *outinfo)
5564 {
5565 int j;
5566 uint64_t max_output_written = 0;
5567 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5568 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5569 int param_index;
5570 int length = 4;
5571
5572 if (!(ctx->output_mask & (1ull << i)))
5573 continue;
5574
5575 if (i == VARYING_SLOT_CLIP_DIST0)
5576 length = ctx->num_output_clips + ctx->num_output_culls;
5577
5578 param_index = shader_io_get_unique_index(i);
5579
5580 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5581
5582 for (j = 0; j < length; j++) {
5583 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5584 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5585
5586 ac_build_buffer_store_dword(&ctx->ac,
5587 ctx->esgs_ring,
5588 out_val, 1,
5589 NULL, ctx->es2gs_offset,
5590 (4 * param_index + j) * 4,
5591 1, 1, true, true);
5592 }
5593 }
5594 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5595 }
5596
5597 static void
5598 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5599 {
5600 LLVMValueRef vertex_id = ctx->rel_auto_id;
5601 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5602 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5603 vertex_dw_stride, "");
5604
5605 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5606 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5607 int length = 4;
5608
5609 if (!(ctx->output_mask & (1ull << i)))
5610 continue;
5611
5612 if (i == VARYING_SLOT_CLIP_DIST0)
5613 length = ctx->num_output_clips + ctx->num_output_culls;
5614 int param = shader_io_get_unique_index(i);
5615 mark_tess_output(ctx, false, param);
5616 if (length > 4)
5617 mark_tess_output(ctx, false, param + 1);
5618 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5619 LLVMConstInt(ctx->i32, param * 4, false),
5620 "");
5621 for (unsigned j = 0; j < length; j++) {
5622 lds_store(ctx, dw_addr,
5623 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5624 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5625 }
5626 }
5627 }
5628
5629 struct ac_build_if_state
5630 {
5631 struct nir_to_llvm_context *ctx;
5632 LLVMValueRef condition;
5633 LLVMBasicBlockRef entry_block;
5634 LLVMBasicBlockRef true_block;
5635 LLVMBasicBlockRef false_block;
5636 LLVMBasicBlockRef merge_block;
5637 };
5638
5639 static LLVMBasicBlockRef
5640 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5641 {
5642 LLVMBasicBlockRef current_block;
5643 LLVMBasicBlockRef next_block;
5644 LLVMBasicBlockRef new_block;
5645
5646 /* get current basic block */
5647 current_block = LLVMGetInsertBlock(ctx->builder);
5648
5649 /* chqeck if there's another block after this one */
5650 next_block = LLVMGetNextBasicBlock(current_block);
5651 if (next_block) {
5652 /* insert the new block before the next block */
5653 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5654 }
5655 else {
5656 /* append new block after current block */
5657 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5658 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5659 }
5660 return new_block;
5661 }
5662
5663 static void
5664 ac_nir_build_if(struct ac_build_if_state *ifthen,
5665 struct nir_to_llvm_context *ctx,
5666 LLVMValueRef condition)
5667 {
5668 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5669
5670 memset(ifthen, 0, sizeof *ifthen);
5671 ifthen->ctx = ctx;
5672 ifthen->condition = condition;
5673 ifthen->entry_block = block;
5674
5675 /* create endif/merge basic block for the phi functions */
5676 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5677
5678 /* create/insert true_block before merge_block */
5679 ifthen->true_block =
5680 LLVMInsertBasicBlockInContext(ctx->context,
5681 ifthen->merge_block,
5682 "if-true-block");
5683
5684 /* successive code goes into the true block */
5685 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5686 }
5687
5688 /**
5689 * End a conditional.
5690 */
5691 static void
5692 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5693 {
5694 LLVMBuilderRef builder = ifthen->ctx->builder;
5695
5696 /* Insert branch to the merge block from current block */
5697 LLVMBuildBr(builder, ifthen->merge_block);
5698
5699 /*
5700 * Now patch in the various branch instructions.
5701 */
5702
5703 /* Insert the conditional branch instruction at the end of entry_block */
5704 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5705 if (ifthen->false_block) {
5706 /* we have an else clause */
5707 LLVMBuildCondBr(builder, ifthen->condition,
5708 ifthen->true_block, ifthen->false_block);
5709 }
5710 else {
5711 /* no else clause */
5712 LLVMBuildCondBr(builder, ifthen->condition,
5713 ifthen->true_block, ifthen->merge_block);
5714 }
5715
5716 /* Resume building code at end of the ifthen->merge_block */
5717 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5718 }
5719
5720 static void
5721 write_tess_factors(struct nir_to_llvm_context *ctx)
5722 {
5723 unsigned stride, outer_comps, inner_comps;
5724 struct ac_build_if_state if_ctx, inner_if_ctx;
5725 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5726 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5727 unsigned tess_inner_index, tess_outer_index;
5728 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5729 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5730 int i;
5731 emit_barrier(ctx);
5732
5733 switch (ctx->options->key.tcs.primitive_mode) {
5734 case GL_ISOLINES:
5735 stride = 2;
5736 outer_comps = 2;
5737 inner_comps = 0;
5738 break;
5739 case GL_TRIANGLES:
5740 stride = 4;
5741 outer_comps = 3;
5742 inner_comps = 1;
5743 break;
5744 case GL_QUADS:
5745 stride = 6;
5746 outer_comps = 4;
5747 inner_comps = 2;
5748 break;
5749 default:
5750 return;
5751 }
5752
5753 ac_nir_build_if(&if_ctx, ctx,
5754 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5755 invocation_id, ctx->i32zero, ""));
5756
5757 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5758 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5759
5760 mark_tess_output(ctx, true, tess_inner_index);
5761 mark_tess_output(ctx, true, tess_outer_index);
5762 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5763 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5764 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5765 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5766 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5767
5768 for (i = 0; i < 4; i++) {
5769 inner[i] = LLVMGetUndef(ctx->i32);
5770 outer[i] = LLVMGetUndef(ctx->i32);
5771 }
5772
5773 // LINES reverseal
5774 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5775 outer[0] = out[1] = lds_load(ctx, lds_outer);
5776 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5777 LLVMConstInt(ctx->i32, 1, false), "");
5778 outer[1] = out[0] = lds_load(ctx, lds_outer);
5779 } else {
5780 for (i = 0; i < outer_comps; i++) {
5781 outer[i] = out[i] =
5782 lds_load(ctx, lds_outer);
5783 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5784 LLVMConstInt(ctx->i32, 1, false), "");
5785 }
5786 for (i = 0; i < inner_comps; i++) {
5787 inner[i] = out[outer_comps+i] =
5788 lds_load(ctx, lds_inner);
5789 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5790 LLVMConstInt(ctx->i32, 1, false), "");
5791 }
5792 }
5793
5794 /* Convert the outputs to vectors for stores. */
5795 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5796 vec1 = NULL;
5797
5798 if (stride > 4)
5799 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5800
5801
5802 buffer = ctx->hs_ring_tess_factor;
5803 tf_base = ctx->tess_factor_offset;
5804 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5805 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5806
5807 ac_nir_build_if(&inner_if_ctx, ctx,
5808 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5809 rel_patch_id, ctx->i32zero, ""));
5810
5811 /* Store the dynamic HS control word. */
5812 ac_build_buffer_store_dword(&ctx->ac, buffer,
5813 LLVMConstInt(ctx->i32, 0x80000000, false),
5814 1, ctx->i32zero, tf_base,
5815 0, 1, 0, true, false);
5816 ac_nir_build_endif(&inner_if_ctx);
5817
5818 /* Store the tessellation factors. */
5819 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5820 MIN2(stride, 4), byteoffset, tf_base,
5821 4, 1, 0, true, false);
5822 if (vec1)
5823 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5824 stride - 4, byteoffset, tf_base,
5825 20, 1, 0, true, false);
5826
5827 //TODO store to offchip for TES to read - only if TES reads them
5828 if (1) {
5829 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5830 LLVMValueRef tf_inner_offset;
5831 unsigned param_outer, param_inner;
5832
5833 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5834 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5835 LLVMConstInt(ctx->i32, param_outer, 0));
5836
5837 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5838 util_next_power_of_two(outer_comps));
5839
5840 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5841 outer_comps, tf_outer_offset,
5842 ctx->oc_lds, 0, 1, 0, true, false);
5843 if (inner_comps) {
5844 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5845 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5846 LLVMConstInt(ctx->i32, param_inner, 0));
5847
5848 inner_vec = inner_comps == 1 ? inner[0] :
5849 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5850 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5851 inner_comps, tf_inner_offset,
5852 ctx->oc_lds, 0, 1, 0, true, false);
5853 }
5854 }
5855 ac_nir_build_endif(&if_ctx);
5856 }
5857
5858 static void
5859 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5860 {
5861 write_tess_factors(ctx);
5862 }
5863
5864 static bool
5865 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5866 LLVMValueRef *color, unsigned param, bool is_last,
5867 struct ac_export_args *args)
5868 {
5869 /* Export */
5870 si_llvm_init_export_args(ctx, color, param,
5871 args);
5872
5873 if (is_last) {
5874 args->valid_mask = 1; /* whether the EXEC mask is valid */
5875 args->done = 1; /* DONE bit */
5876 } else if (!args->enabled_channels)
5877 return false; /* unnecessary NULL export */
5878
5879 return true;
5880 }
5881
5882 static void
5883 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5884 LLVMValueRef depth, LLVMValueRef stencil,
5885 LLVMValueRef samplemask)
5886 {
5887 struct ac_export_args args;
5888
5889 args.enabled_channels = 0;
5890 args.valid_mask = 1;
5891 args.done = 1;
5892 args.target = V_008DFC_SQ_EXP_MRTZ;
5893 args.compr = false;
5894
5895 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5896 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5897 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5898 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5899
5900 if (depth) {
5901 args.out[0] = depth;
5902 args.enabled_channels |= 0x1;
5903 }
5904
5905 if (stencil) {
5906 args.out[1] = stencil;
5907 args.enabled_channels |= 0x2;
5908 }
5909
5910 if (samplemask) {
5911 args.out[2] = samplemask;
5912 args.enabled_channels |= 0x4;
5913 }
5914
5915 /* SI (except OLAND and HAINAN) has a bug that it only looks
5916 * at the X writemask component. */
5917 if (ctx->options->chip_class == SI &&
5918 ctx->options->family != CHIP_OLAND &&
5919 ctx->options->family != CHIP_HAINAN)
5920 args.enabled_channels |= 0x1;
5921
5922 ac_build_export(&ctx->ac, &args);
5923 }
5924
5925 static void
5926 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5927 {
5928 unsigned index = 0;
5929 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5930 struct ac_export_args color_args[8];
5931
5932 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5933 LLVMValueRef values[4];
5934
5935 if (!(ctx->output_mask & (1ull << i)))
5936 continue;
5937
5938 if (i == FRAG_RESULT_DEPTH) {
5939 ctx->shader_info->fs.writes_z = true;
5940 depth = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5941 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5942 } else if (i == FRAG_RESULT_STENCIL) {
5943 ctx->shader_info->fs.writes_stencil = true;
5944 stencil = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5945 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5946 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5947 ctx->shader_info->fs.writes_sample_mask = true;
5948 samplemask = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5949 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5950 } else {
5951 bool last = false;
5952 for (unsigned j = 0; j < 4; j++)
5953 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5954 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5955
5956 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5957 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5958
5959 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
5960 if (ret)
5961 index++;
5962 }
5963 }
5964
5965 for (unsigned i = 0; i < index; i++)
5966 ac_build_export(&ctx->ac, &color_args[i]);
5967 if (depth || stencil || samplemask)
5968 si_export_mrt_z(ctx, depth, stencil, samplemask);
5969 else if (!index) {
5970 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
5971 ac_build_export(&ctx->ac, &color_args[0]);
5972 }
5973
5974 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5975 }
5976
5977 static void
5978 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5979 {
5980 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5981 }
5982
5983 static void
5984 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
5985 LLVMValueRef *addrs)
5986 {
5987 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
5988
5989 switch (ctx->stage) {
5990 case MESA_SHADER_VERTEX:
5991 if (ctx->options->key.vs.as_ls)
5992 handle_ls_outputs_post(ctx);
5993 else if (ctx->options->key.vs.as_es)
5994 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5995 else
5996 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
5997 &ctx->shader_info->vs.outinfo);
5998 break;
5999 case MESA_SHADER_FRAGMENT:
6000 handle_fs_outputs_post(ctx);
6001 break;
6002 case MESA_SHADER_GEOMETRY:
6003 emit_gs_epilogue(ctx);
6004 break;
6005 case MESA_SHADER_TESS_CTRL:
6006 handle_tcs_outputs_post(ctx);
6007 break;
6008 case MESA_SHADER_TESS_EVAL:
6009 if (ctx->options->key.tes.as_es)
6010 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6011 else
6012 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6013 &ctx->shader_info->tes.outinfo);
6014 break;
6015 default:
6016 break;
6017 }
6018 }
6019
6020 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6021 {
6022 LLVMPassManagerRef passmgr;
6023 /* Create the pass manager */
6024 passmgr = LLVMCreateFunctionPassManagerForModule(
6025 ctx->module);
6026
6027 /* This pass should eliminate all the load and store instructions */
6028 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6029
6030 /* Add some optimization passes */
6031 LLVMAddScalarReplAggregatesPass(passmgr);
6032 LLVMAddLICMPass(passmgr);
6033 LLVMAddAggressiveDCEPass(passmgr);
6034 LLVMAddCFGSimplificationPass(passmgr);
6035 LLVMAddInstructionCombiningPass(passmgr);
6036
6037 /* Run the pass */
6038 LLVMInitializeFunctionPassManager(passmgr);
6039 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6040 LLVMFinalizeFunctionPassManager(passmgr);
6041
6042 LLVMDisposeBuilder(ctx->builder);
6043 LLVMDisposePassManager(passmgr);
6044 }
6045
6046 static void
6047 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6048 {
6049 struct ac_vs_output_info *outinfo;
6050
6051 switch (ctx->stage) {
6052 case MESA_SHADER_FRAGMENT:
6053 case MESA_SHADER_COMPUTE:
6054 case MESA_SHADER_TESS_CTRL:
6055 case MESA_SHADER_GEOMETRY:
6056 return;
6057 case MESA_SHADER_VERTEX:
6058 if (ctx->options->key.vs.as_ls ||
6059 ctx->options->key.vs.as_es)
6060 return;
6061 outinfo = &ctx->shader_info->vs.outinfo;
6062 break;
6063 case MESA_SHADER_TESS_EVAL:
6064 if (ctx->options->key.vs.as_es)
6065 return;
6066 outinfo = &ctx->shader_info->tes.outinfo;
6067 break;
6068 default:
6069 unreachable("Unhandled shader type");
6070 }
6071
6072 ac_optimize_vs_outputs(&ctx->ac,
6073 ctx->main_function,
6074 outinfo->vs_output_param_offset,
6075 VARYING_SLOT_MAX,
6076 &outinfo->param_exports);
6077 }
6078
6079 static void
6080 ac_setup_rings(struct nir_to_llvm_context *ctx)
6081 {
6082 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6083 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6084 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
6085 }
6086
6087 if (ctx->is_gs_copy_shader) {
6088 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
6089 }
6090 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6091 LLVMValueRef tmp;
6092 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
6093 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
6094
6095 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6096
6097 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
6098 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
6099 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6100 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
6101 }
6102
6103 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6104 ctx->stage == MESA_SHADER_TESS_EVAL) {
6105 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6106 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6107 }
6108 }
6109
6110 static unsigned
6111 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6112 const struct nir_shader *nir)
6113 {
6114 switch (nir->stage) {
6115 case MESA_SHADER_TESS_CTRL:
6116 return chip_class >= CIK ? 128 : 64;
6117 case MESA_SHADER_GEOMETRY:
6118 return 64;
6119 case MESA_SHADER_COMPUTE:
6120 break;
6121 default:
6122 return 0;
6123 }
6124
6125 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6126 nir->info.cs.local_size[1] *
6127 nir->info.cs.local_size[2];
6128 return max_workgroup_size;
6129 }
6130
6131 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6132 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6133 {
6134 struct ac_nir_context ctx = {};
6135 struct nir_function *func;
6136
6137 ctx.ac = *ac;
6138 ctx.abi = abi;
6139
6140 ctx.nctx = nctx;
6141 if (nctx)
6142 nctx->nir = &ctx;
6143
6144 ctx.stage = nir->stage;
6145
6146 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6147
6148 nir_foreach_variable(variable, &nir->outputs)
6149 handle_shader_output_decl(&ctx, nir, variable);
6150
6151 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6152 _mesa_key_pointer_equal);
6153 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6154 _mesa_key_pointer_equal);
6155 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6156 _mesa_key_pointer_equal);
6157
6158 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6159
6160 setup_locals(&ctx, func);
6161
6162 if (nir->stage == MESA_SHADER_COMPUTE)
6163 setup_shared(&ctx, nir);
6164
6165 visit_cf_list(&ctx, &func->impl->body);
6166 phi_post_pass(&ctx);
6167
6168 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6169 ctx.outputs);
6170
6171 free(ctx.locals);
6172 ralloc_free(ctx.defs);
6173 ralloc_free(ctx.phis);
6174 ralloc_free(ctx.vars);
6175
6176 if (nctx)
6177 nctx->nir = NULL;
6178 }
6179
6180 static
6181 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6182 struct nir_shader *nir,
6183 struct ac_shader_variant_info *shader_info,
6184 const struct ac_nir_compiler_options *options)
6185 {
6186 struct nir_to_llvm_context ctx = {0};
6187 unsigned i;
6188 ctx.options = options;
6189 ctx.shader_info = shader_info;
6190 ctx.context = LLVMContextCreate();
6191 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6192
6193 ac_llvm_context_init(&ctx.ac, ctx.context);
6194 ctx.ac.module = ctx.module;
6195
6196 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
6197
6198 memset(shader_info, 0, sizeof(*shader_info));
6199
6200 ac_nir_shader_info_pass(nir, options, &shader_info->info);
6201
6202 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6203
6204 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6205 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6206 LLVMSetDataLayout(ctx.module, data_layout_str);
6207 LLVMDisposeTargetData(data_layout);
6208 LLVMDisposeMessage(data_layout_str);
6209
6210 setup_types(&ctx);
6211
6212 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6213 ctx.ac.builder = ctx.builder;
6214 ctx.stage = nir->stage;
6215 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
6216
6217 for (i = 0; i < AC_UD_MAX_SETS; i++)
6218 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6219 for (i = 0; i < AC_UD_MAX_UD; i++)
6220 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6221
6222 create_function(&ctx);
6223
6224 if (nir->stage == MESA_SHADER_GEOMETRY) {
6225 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.i32, "gs_next_vertex");
6226
6227 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
6228 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
6229 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
6230 } else if (nir->stage == MESA_SHADER_VERTEX) {
6231 if (shader_info->info.vs.needs_instance_id) {
6232 ctx.shader_info->vs.vgpr_comp_cnt =
6233 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6234 }
6235 } else if (nir->stage == MESA_SHADER_FRAGMENT) {
6236 shader_info->fs.can_discard = nir->info.fs.uses_discard;
6237 }
6238
6239 ac_setup_rings(&ctx);
6240
6241 ctx.num_output_clips = nir->info.clip_distance_array_size;
6242 ctx.num_output_culls = nir->info.cull_distance_array_size;
6243
6244 nir_foreach_variable(variable, &nir->inputs)
6245 handle_shader_input_decl(&ctx, variable);
6246
6247 if (nir->stage == MESA_SHADER_FRAGMENT)
6248 handle_fs_inputs_pre(&ctx, nir);
6249
6250 ctx.abi.chip_class = options->chip_class;
6251 ctx.abi.inputs = &ctx.inputs[0];
6252 ctx.abi.emit_outputs = handle_shader_outputs_post;
6253 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6254
6255 nir_foreach_variable(variable, &nir->outputs)
6256 scan_shader_output_decl(&ctx, variable);
6257
6258 ac_nir_translate(&ctx.ac, &ctx.abi, nir, &ctx);
6259
6260 LLVMBuildRetVoid(ctx.builder);
6261
6262 ac_llvm_finalize_module(&ctx);
6263
6264 ac_nir_eliminate_const_vs_outputs(&ctx);
6265
6266 if (nir->stage == MESA_SHADER_GEOMETRY) {
6267 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
6268 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6269 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6270 nir->info.gs.vertices_out;
6271 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
6272 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6273 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6274 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6275 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6276 }
6277
6278 return ctx.module;
6279 }
6280
6281 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6282 {
6283 unsigned *retval = (unsigned *)context;
6284 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6285 char *description = LLVMGetDiagInfoDescription(di);
6286
6287 if (severity == LLVMDSError) {
6288 *retval = 1;
6289 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6290 description);
6291 }
6292
6293 LLVMDisposeMessage(description);
6294 }
6295
6296 static unsigned ac_llvm_compile(LLVMModuleRef M,
6297 struct ac_shader_binary *binary,
6298 LLVMTargetMachineRef tm)
6299 {
6300 unsigned retval = 0;
6301 char *err;
6302 LLVMContextRef llvm_ctx;
6303 LLVMMemoryBufferRef out_buffer;
6304 unsigned buffer_size;
6305 const char *buffer_data;
6306 LLVMBool mem_err;
6307
6308 /* Setup Diagnostic Handler*/
6309 llvm_ctx = LLVMGetModuleContext(M);
6310
6311 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6312 &retval);
6313
6314 /* Compile IR*/
6315 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6316 &err, &out_buffer);
6317
6318 /* Process Errors/Warnings */
6319 if (mem_err) {
6320 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6321 free(err);
6322 retval = 1;
6323 goto out;
6324 }
6325
6326 /* Extract Shader Code*/
6327 buffer_size = LLVMGetBufferSize(out_buffer);
6328 buffer_data = LLVMGetBufferStart(out_buffer);
6329
6330 ac_elf_read(buffer_data, buffer_size, binary);
6331
6332 /* Clean up */
6333 LLVMDisposeMemoryBuffer(out_buffer);
6334
6335 out:
6336 return retval;
6337 }
6338
6339 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6340 LLVMModuleRef llvm_module,
6341 struct ac_shader_binary *binary,
6342 struct ac_shader_config *config,
6343 struct ac_shader_variant_info *shader_info,
6344 gl_shader_stage stage,
6345 bool dump_shader, bool supports_spill)
6346 {
6347 if (dump_shader)
6348 ac_dump_module(llvm_module);
6349
6350 memset(binary, 0, sizeof(*binary));
6351 int v = ac_llvm_compile(llvm_module, binary, tm);
6352 if (v) {
6353 fprintf(stderr, "compile failed\n");
6354 }
6355
6356 if (dump_shader)
6357 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6358
6359 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6360
6361 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6362 LLVMDisposeModule(llvm_module);
6363 LLVMContextDispose(ctx);
6364
6365 if (stage == MESA_SHADER_FRAGMENT) {
6366 shader_info->num_input_vgprs = 0;
6367 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6368 shader_info->num_input_vgprs += 2;
6369 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6370 shader_info->num_input_vgprs += 2;
6371 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6372 shader_info->num_input_vgprs += 2;
6373 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6374 shader_info->num_input_vgprs += 3;
6375 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6376 shader_info->num_input_vgprs += 2;
6377 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6378 shader_info->num_input_vgprs += 2;
6379 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6380 shader_info->num_input_vgprs += 2;
6381 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6382 shader_info->num_input_vgprs += 1;
6383 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6384 shader_info->num_input_vgprs += 1;
6385 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6386 shader_info->num_input_vgprs += 1;
6387 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6388 shader_info->num_input_vgprs += 1;
6389 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6390 shader_info->num_input_vgprs += 1;
6391 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6392 shader_info->num_input_vgprs += 1;
6393 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6394 shader_info->num_input_vgprs += 1;
6395 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6396 shader_info->num_input_vgprs += 1;
6397 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6398 shader_info->num_input_vgprs += 1;
6399 }
6400 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6401
6402 /* +3 for scratch wave offset and VCC */
6403 config->num_sgprs = MAX2(config->num_sgprs,
6404 shader_info->num_input_sgprs + 3);
6405 }
6406
6407 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6408 struct ac_shader_binary *binary,
6409 struct ac_shader_config *config,
6410 struct ac_shader_variant_info *shader_info,
6411 struct nir_shader *nir,
6412 const struct ac_nir_compiler_options *options,
6413 bool dump_shader)
6414 {
6415
6416 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6417 options);
6418
6419 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6420 switch (nir->stage) {
6421 case MESA_SHADER_COMPUTE:
6422 for (int i = 0; i < 3; ++i)
6423 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6424 break;
6425 case MESA_SHADER_FRAGMENT:
6426 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6427 break;
6428 case MESA_SHADER_GEOMETRY:
6429 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6430 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6431 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6432 shader_info->gs.invocations = nir->info.gs.invocations;
6433 break;
6434 case MESA_SHADER_TESS_EVAL:
6435 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6436 shader_info->tes.spacing = nir->info.tess.spacing;
6437 shader_info->tes.ccw = nir->info.tess.ccw;
6438 shader_info->tes.point_mode = nir->info.tess.point_mode;
6439 shader_info->tes.as_es = options->key.tes.as_es;
6440 break;
6441 case MESA_SHADER_TESS_CTRL:
6442 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6443 break;
6444 case MESA_SHADER_VERTEX:
6445 shader_info->vs.as_es = options->key.vs.as_es;
6446 shader_info->vs.as_ls = options->key.vs.as_ls;
6447 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6448 if (options->key.vs.as_ls)
6449 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6450 break;
6451 default:
6452 break;
6453 }
6454 }
6455
6456 static void
6457 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6458 {
6459 LLVMValueRef args[9];
6460 args[0] = ctx->gsvs_ring;
6461 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6462 args[3] = ctx->i32zero;
6463 args[4] = ctx->i32one; /* OFFEN */
6464 args[5] = ctx->i32zero; /* IDXEN */
6465 args[6] = ctx->i32one; /* GLC */
6466 args[7] = ctx->i32one; /* SLC */
6467 args[8] = ctx->i32zero; /* TFE */
6468
6469 int idx = 0;
6470
6471 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6472 int length = 4;
6473 int slot = idx;
6474 int slot_inc = 1;
6475 if (!(ctx->output_mask & (1ull << i)))
6476 continue;
6477
6478 if (i == VARYING_SLOT_CLIP_DIST0) {
6479 /* unpack clip and cull from a single set of slots */
6480 length = ctx->num_output_clips + ctx->num_output_culls;
6481 if (length > 4)
6482 slot_inc = 2;
6483 }
6484
6485 for (unsigned j = 0; j < length; j++) {
6486 LLVMValueRef value;
6487 args[2] = LLVMConstInt(ctx->i32,
6488 (slot * 4 + j) *
6489 ctx->gs_max_out_vertices * 16 * 4, false);
6490
6491 value = ac_build_intrinsic(&ctx->ac,
6492 "llvm.SI.buffer.load.dword.i32.i32",
6493 ctx->i32, args, 9,
6494 AC_FUNC_ATTR_READONLY |
6495 AC_FUNC_ATTR_LEGACY);
6496
6497 LLVMBuildStore(ctx->builder,
6498 to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6499 }
6500 idx += slot_inc;
6501 }
6502 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6503 }
6504
6505 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6506 struct nir_shader *geom_shader,
6507 struct ac_shader_binary *binary,
6508 struct ac_shader_config *config,
6509 struct ac_shader_variant_info *shader_info,
6510 const struct ac_nir_compiler_options *options,
6511 bool dump_shader)
6512 {
6513 struct nir_to_llvm_context ctx = {0};
6514 ctx.context = LLVMContextCreate();
6515 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6516 ctx.options = options;
6517 ctx.shader_info = shader_info;
6518
6519 ac_llvm_context_init(&ctx.ac, ctx.context);
6520 ctx.ac.module = ctx.module;
6521
6522 ctx.is_gs_copy_shader = true;
6523 LLVMSetTarget(ctx.module, "amdgcn--");
6524 setup_types(&ctx);
6525
6526 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6527 ctx.ac.builder = ctx.builder;
6528 ctx.stage = MESA_SHADER_VERTEX;
6529
6530 create_function(&ctx);
6531
6532 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6533 ac_setup_rings(&ctx);
6534
6535 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6536 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6537
6538 struct ac_nir_context nir_ctx = {};
6539 nir_ctx.ac = ctx.ac;
6540 nir_ctx.abi = &ctx.abi;
6541
6542 nir_ctx.nctx = &ctx;
6543 ctx.nir = &nir_ctx;
6544
6545 nir_foreach_variable(variable, &geom_shader->outputs) {
6546 scan_shader_output_decl(&ctx, variable);
6547 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6548 }
6549
6550 ac_gs_copy_shader_emit(&ctx);
6551
6552 ctx.nir = NULL;
6553
6554 LLVMBuildRetVoid(ctx.builder);
6555
6556 ac_llvm_finalize_module(&ctx);
6557
6558 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6559 MESA_SHADER_VERTEX,
6560 dump_shader, options->supports_spill);
6561 }