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radv/ac: fix multisample subpass image.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_util.h"
26 #include "ac_binary.h"
27 #include "sid.h"
28 #include "nir/nir.h"
29 #include "../vulkan/radv_descriptor_set.h"
30 #include "util/bitscan.h"
31 #include <llvm-c/Transforms/Scalar.h>
32
33 enum radeon_llvm_calling_convention {
34 RADEON_LLVM_AMDGPU_VS = 87,
35 RADEON_LLVM_AMDGPU_GS = 88,
36 RADEON_LLVM_AMDGPU_PS = 89,
37 RADEON_LLVM_AMDGPU_CS = 90,
38 };
39
40 #define CONST_ADDR_SPACE 2
41 #define LOCAL_ADDR_SPACE 3
42
43 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
44 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
45
46 enum desc_type {
47 DESC_IMAGE,
48 DESC_FMASK,
49 DESC_SAMPLER,
50 DESC_BUFFER,
51 };
52
53 struct nir_to_llvm_context {
54 struct ac_llvm_context ac;
55 const struct ac_nir_compiler_options *options;
56 struct ac_shader_variant_info *shader_info;
57
58 LLVMContextRef context;
59 LLVMModuleRef module;
60 LLVMBuilderRef builder;
61 LLVMValueRef main_function;
62
63 struct hash_table *defs;
64 struct hash_table *phis;
65
66 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
67 LLVMValueRef push_constants;
68 LLVMValueRef num_work_groups;
69 LLVMValueRef workgroup_ids;
70 LLVMValueRef local_invocation_ids;
71 LLVMValueRef tg_size;
72
73 LLVMValueRef vertex_buffers;
74 LLVMValueRef base_vertex;
75 LLVMValueRef start_instance;
76 LLVMValueRef vertex_id;
77 LLVMValueRef rel_auto_id;
78 LLVMValueRef vs_prim_id;
79 LLVMValueRef instance_id;
80
81 LLVMValueRef prim_mask;
82 LLVMValueRef sample_positions;
83 LLVMValueRef persp_sample, persp_center, persp_centroid;
84 LLVMValueRef linear_sample, linear_center, linear_centroid;
85 LLVMValueRef front_face;
86 LLVMValueRef ancillary;
87 LLVMValueRef frag_pos[4];
88
89 LLVMBasicBlockRef continue_block;
90 LLVMBasicBlockRef break_block;
91
92 LLVMTypeRef i1;
93 LLVMTypeRef i8;
94 LLVMTypeRef i16;
95 LLVMTypeRef i32;
96 LLVMTypeRef i64;
97 LLVMTypeRef v2i32;
98 LLVMTypeRef v3i32;
99 LLVMTypeRef v4i32;
100 LLVMTypeRef v8i32;
101 LLVMTypeRef f32;
102 LLVMTypeRef f16;
103 LLVMTypeRef v2f32;
104 LLVMTypeRef v4f32;
105 LLVMTypeRef v16i8;
106 LLVMTypeRef voidt;
107
108 LLVMValueRef i32zero;
109 LLVMValueRef i32one;
110 LLVMValueRef f32zero;
111 LLVMValueRef f32one;
112 LLVMValueRef v4f32empty;
113
114 unsigned range_md_kind;
115 unsigned uniform_md_kind;
116 unsigned invariant_load_md_kind;
117 LLVMValueRef empty_md;
118 gl_shader_stage stage;
119
120 LLVMValueRef lds;
121 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
122 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
123
124 LLVMValueRef shared_memory;
125 uint64_t input_mask;
126 uint64_t output_mask;
127 int num_locals;
128 LLVMValueRef *locals;
129 bool has_ddxy;
130 unsigned num_clips;
131 unsigned num_culls;
132
133 bool has_ds_bpermute;
134 };
135
136 struct ac_tex_info {
137 LLVMValueRef args[12];
138 int arg_count;
139 LLVMTypeRef dst_type;
140 bool has_offset;
141 };
142
143 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
144 nir_deref_var *deref,
145 enum desc_type desc_type);
146 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
147 {
148 return (index * 4) + chan;
149 }
150
151 static unsigned llvm_get_type_size(LLVMTypeRef type)
152 {
153 LLVMTypeKind kind = LLVMGetTypeKind(type);
154
155 switch (kind) {
156 case LLVMIntegerTypeKind:
157 return LLVMGetIntTypeWidth(type) / 8;
158 case LLVMFloatTypeKind:
159 return 4;
160 case LLVMPointerTypeKind:
161 return 8;
162 case LLVMVectorTypeKind:
163 return LLVMGetVectorSize(type) *
164 llvm_get_type_size(LLVMGetElementType(type));
165 default:
166 assert(0);
167 return 0;
168 }
169 }
170
171 static void set_llvm_calling_convention(LLVMValueRef func,
172 gl_shader_stage stage)
173 {
174 enum radeon_llvm_calling_convention calling_conv;
175
176 switch (stage) {
177 case MESA_SHADER_VERTEX:
178 case MESA_SHADER_TESS_CTRL:
179 case MESA_SHADER_TESS_EVAL:
180 calling_conv = RADEON_LLVM_AMDGPU_VS;
181 break;
182 case MESA_SHADER_GEOMETRY:
183 calling_conv = RADEON_LLVM_AMDGPU_GS;
184 break;
185 case MESA_SHADER_FRAGMENT:
186 calling_conv = RADEON_LLVM_AMDGPU_PS;
187 break;
188 case MESA_SHADER_COMPUTE:
189 calling_conv = RADEON_LLVM_AMDGPU_CS;
190 break;
191 default:
192 unreachable("Unhandle shader type");
193 }
194
195 LLVMSetFunctionCallConv(func, calling_conv);
196 }
197
198 static LLVMValueRef
199 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
200 LLVMBuilderRef builder, LLVMTypeRef *return_types,
201 unsigned num_return_elems, LLVMTypeRef *param_types,
202 unsigned param_count, unsigned array_params_mask,
203 unsigned sgpr_params, bool unsafe_math)
204 {
205 LLVMTypeRef main_function_type, ret_type;
206 LLVMBasicBlockRef main_function_body;
207
208 if (num_return_elems)
209 ret_type = LLVMStructTypeInContext(ctx, return_types,
210 num_return_elems, true);
211 else
212 ret_type = LLVMVoidTypeInContext(ctx);
213
214 /* Setup the function */
215 main_function_type =
216 LLVMFunctionType(ret_type, param_types, param_count, 0);
217 LLVMValueRef main_function =
218 LLVMAddFunction(module, "main", main_function_type);
219 main_function_body =
220 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
221 LLVMPositionBuilderAtEnd(builder, main_function_body);
222
223 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
224 for (unsigned i = 0; i < sgpr_params; ++i) {
225 if (array_params_mask & (1 << i)) {
226 LLVMValueRef P = LLVMGetParam(main_function, i);
227 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_BYVAL);
228 ac_add_attr_dereferenceable(P, UINT64_MAX);
229 }
230 else {
231 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_INREG);
232 }
233 }
234
235 if (unsafe_math) {
236 /* These were copied from some LLVM test. */
237 LLVMAddTargetDependentFunctionAttr(main_function,
238 "less-precise-fpmad",
239 "true");
240 LLVMAddTargetDependentFunctionAttr(main_function,
241 "no-infs-fp-math",
242 "true");
243 LLVMAddTargetDependentFunctionAttr(main_function,
244 "no-nans-fp-math",
245 "true");
246 LLVMAddTargetDependentFunctionAttr(main_function,
247 "unsafe-fp-math",
248 "true");
249 }
250 return main_function;
251 }
252
253 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
254 {
255 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
256 CONST_ADDR_SPACE);
257 }
258
259 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
260 int idx,
261 LLVMTypeRef type)
262 {
263 LLVMValueRef offset;
264 LLVMValueRef ptr;
265 int addr_space;
266
267 offset = LLVMConstInt(ctx->i32, idx, false);
268
269 ptr = ctx->shared_memory;
270 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
271 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
272 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
273 return ptr;
274 }
275
276 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
277 {
278 LLVMTypeRef type = LLVMTypeOf(v);
279 if (type == ctx->f32) {
280 return LLVMBuildBitCast(ctx->builder, v, ctx->i32, "");
281 } else if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
282 LLVMTypeRef elem_type = LLVMGetElementType(type);
283 if (elem_type == ctx->f32) {
284 LLVMTypeRef nt = LLVMVectorType(ctx->i32, LLVMGetVectorSize(type));
285 return LLVMBuildBitCast(ctx->builder, v, nt, "");
286 }
287 }
288 return v;
289 }
290
291 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
292 {
293 LLVMTypeRef type = LLVMTypeOf(v);
294 if (type == ctx->i32) {
295 return LLVMBuildBitCast(ctx->builder, v, ctx->f32, "");
296 } else if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
297 LLVMTypeRef elem_type = LLVMGetElementType(type);
298 if (elem_type == ctx->i32) {
299 LLVMTypeRef nt = LLVMVectorType(ctx->f32, LLVMGetVectorSize(type));
300 return LLVMBuildBitCast(ctx->builder, v, nt, "");
301 }
302 }
303 return v;
304 }
305
306 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
307 LLVMValueRef param, unsigned rshift,
308 unsigned bitwidth)
309 {
310 LLVMValueRef value = param;
311 if (rshift)
312 value = LLVMBuildLShr(ctx->builder, value,
313 LLVMConstInt(ctx->i32, rshift, false), "");
314
315 if (rshift + bitwidth < 32) {
316 unsigned mask = (1 << bitwidth) - 1;
317 value = LLVMBuildAnd(ctx->builder, value,
318 LLVMConstInt(ctx->i32, mask, false), "");
319 }
320 return value;
321 }
322
323 static LLVMValueRef build_gep0(struct nir_to_llvm_context *ctx,
324 LLVMValueRef base_ptr, LLVMValueRef index)
325 {
326 LLVMValueRef indices[2] = {
327 ctx->i32zero,
328 index,
329 };
330 return LLVMBuildGEP(ctx->builder, base_ptr,
331 indices, 2, "");
332 }
333
334 static LLVMValueRef build_indexed_load(struct nir_to_llvm_context *ctx,
335 LLVMValueRef base_ptr, LLVMValueRef index,
336 bool uniform)
337 {
338 LLVMValueRef pointer;
339 pointer = build_gep0(ctx, base_ptr, index);
340 if (uniform)
341 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
342 return LLVMBuildLoad(ctx->builder, pointer, "");
343 }
344
345 static LLVMValueRef build_indexed_load_const(struct nir_to_llvm_context *ctx,
346 LLVMValueRef base_ptr, LLVMValueRef index)
347 {
348 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
349 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
350 return result;
351 }
352
353 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
354 {
355 ud_info->sgpr_idx = sgpr_idx;
356 ud_info->num_sgprs = num_sgprs;
357 ud_info->indirect = false;
358 ud_info->indirect_offset = 0;
359 }
360
361 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
362 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
363 {
364 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
365 }
366
367 #if 0
368 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
369 uint32_t indirect_offset)
370 {
371 ud_info->sgpr_idx = sgpr_idx;
372 ud_info->num_sgprs = num_sgprs;
373 ud_info->indirect = true;
374 ud_info->indirect_offset = indirect_offset;
375 }
376 #endif
377
378 static void create_function(struct nir_to_llvm_context *ctx)
379 {
380 LLVMTypeRef arg_types[23];
381 unsigned arg_idx = 0;
382 unsigned array_params_mask = 0;
383 unsigned sgpr_count = 0, user_sgpr_count;
384 unsigned i;
385 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
386 unsigned user_sgpr_idx;
387 bool need_push_constants;
388
389 need_push_constants = true;
390 if (!ctx->options->layout)
391 need_push_constants = false;
392 else if (!ctx->options->layout->push_constant_size &&
393 !ctx->options->layout->dynamic_offset_count)
394 need_push_constants = false;
395
396 /* 1 for each descriptor set */
397 for (unsigned i = 0; i < num_sets; ++i) {
398 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
399 array_params_mask |= (1 << arg_idx);
400 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
401 }
402 }
403
404 if (need_push_constants) {
405 /* 1 for push constants and dynamic descriptors */
406 array_params_mask |= (1 << arg_idx);
407 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
408 }
409
410 switch (ctx->stage) {
411 case MESA_SHADER_COMPUTE:
412 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
413 user_sgpr_count = arg_idx;
414 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
415 arg_types[arg_idx++] = ctx->i32;
416 sgpr_count = arg_idx;
417
418 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
419 break;
420 case MESA_SHADER_VERTEX:
421 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
422 arg_types[arg_idx++] = ctx->i32; // base vertex
423 arg_types[arg_idx++] = ctx->i32; // start instance
424 user_sgpr_count = sgpr_count = arg_idx;
425 arg_types[arg_idx++] = ctx->i32; // vertex id
426 arg_types[arg_idx++] = ctx->i32; // rel auto id
427 arg_types[arg_idx++] = ctx->i32; // vs prim id
428 arg_types[arg_idx++] = ctx->i32; // instance id
429 break;
430 case MESA_SHADER_FRAGMENT:
431 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
432 user_sgpr_count = arg_idx;
433 arg_types[arg_idx++] = ctx->i32; /* prim mask */
434 sgpr_count = arg_idx;
435 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
436 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
437 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
438 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
439 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
440 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
441 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
442 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
443 arg_types[arg_idx++] = ctx->f32; /* pos x float */
444 arg_types[arg_idx++] = ctx->f32; /* pos y float */
445 arg_types[arg_idx++] = ctx->f32; /* pos z float */
446 arg_types[arg_idx++] = ctx->f32; /* pos w float */
447 arg_types[arg_idx++] = ctx->i32; /* front face */
448 arg_types[arg_idx++] = ctx->i32; /* ancillary */
449 arg_types[arg_idx++] = ctx->f32; /* sample coverage */
450 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
451 break;
452 default:
453 unreachable("Shader stage not implemented");
454 }
455
456 ctx->main_function = create_llvm_function(
457 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
458 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
459 set_llvm_calling_convention(ctx->main_function, ctx->stage);
460
461 ctx->shader_info->num_input_sgprs = 0;
462 ctx->shader_info->num_input_vgprs = 0;
463
464 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
465 for (i = 0; i < user_sgpr_count; i++)
466 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
467
468 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
469 for (; i < sgpr_count; i++)
470 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
471
472 if (ctx->stage != MESA_SHADER_FRAGMENT)
473 for (; i < arg_idx; ++i)
474 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
475
476 arg_idx = 0;
477 user_sgpr_idx = 0;
478
479 if (ctx->options->supports_spill) {
480 set_userdata_location_shader(ctx, AC_UD_SCRATCH, user_sgpr_idx, 2);
481 user_sgpr_idx += 2;
482 }
483
484 for (unsigned i = 0; i < num_sets; ++i) {
485 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
486 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
487 user_sgpr_idx += 2;
488 ctx->descriptor_sets[i] =
489 LLVMGetParam(ctx->main_function, arg_idx++);
490 } else
491 ctx->descriptor_sets[i] = NULL;
492 }
493
494 if (need_push_constants) {
495 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
496 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
497 user_sgpr_idx += 2;
498 }
499
500 switch (ctx->stage) {
501 case MESA_SHADER_COMPUTE:
502 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
503 user_sgpr_idx += 3;
504 ctx->num_work_groups =
505 LLVMGetParam(ctx->main_function, arg_idx++);
506 ctx->workgroup_ids =
507 LLVMGetParam(ctx->main_function, arg_idx++);
508 ctx->tg_size =
509 LLVMGetParam(ctx->main_function, arg_idx++);
510 ctx->local_invocation_ids =
511 LLVMGetParam(ctx->main_function, arg_idx++);
512 break;
513 case MESA_SHADER_VERTEX:
514 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
515 user_sgpr_idx += 2;
516 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
517 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 2);
518 user_sgpr_idx += 2;
519 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
520 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
521 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
522 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
523 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
524 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
525 break;
526 case MESA_SHADER_FRAGMENT:
527 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
528 user_sgpr_idx += 2;
529 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
530 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
531 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
532 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
533 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
534 arg_idx++;
535 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
536 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
537 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
538 arg_idx++; /* line stipple */
539 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
540 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
541 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
542 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
543 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
544 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
545 break;
546 default:
547 unreachable("Shader stage not implemented");
548 }
549 }
550
551 static void setup_types(struct nir_to_llvm_context *ctx)
552 {
553 LLVMValueRef args[4];
554
555 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
556 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
557 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
558 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
559 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
560 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
561 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
562 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
563 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
564 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
565 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
566 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
567 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
568 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
569 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
570
571 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
572 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
573 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
574 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
575
576 args[0] = ctx->f32zero;
577 args[1] = ctx->f32zero;
578 args[2] = ctx->f32zero;
579 args[3] = ctx->f32one;
580 ctx->v4f32empty = LLVMConstVector(args, 4);
581
582 ctx->range_md_kind = LLVMGetMDKindIDInContext(ctx->context,
583 "range", 5);
584 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(ctx->context,
585 "invariant.load", 14);
586 ctx->uniform_md_kind =
587 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
588 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
589
590 args[0] = LLVMConstReal(ctx->f32, 2.5);
591 }
592
593 static int get_llvm_num_components(LLVMValueRef value)
594 {
595 LLVMTypeRef type = LLVMTypeOf(value);
596 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
597 ? LLVMGetVectorSize(type)
598 : 1;
599 return num_components;
600 }
601
602 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
603 LLVMValueRef value,
604 int index)
605 {
606 int count = get_llvm_num_components(value);
607
608 assert(index < count);
609 if (count == 1)
610 return value;
611
612 return LLVMBuildExtractElement(ctx->builder, value,
613 LLVMConstInt(ctx->i32, index, false), "");
614 }
615
616 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
617 LLVMValueRef value, unsigned count)
618 {
619 unsigned num_components = get_llvm_num_components(value);
620 if (count == num_components)
621 return value;
622
623 LLVMValueRef masks[] = {
624 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
625 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
626
627 if (count == 1)
628 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
629 "");
630
631 LLVMValueRef swizzle = LLVMConstVector(masks, count);
632 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
633 }
634
635 static void
636 build_store_values_extended(struct nir_to_llvm_context *ctx,
637 LLVMValueRef *values,
638 unsigned value_count,
639 unsigned value_stride,
640 LLVMValueRef vec)
641 {
642 LLVMBuilderRef builder = ctx->builder;
643 unsigned i;
644
645 if (value_count == 1) {
646 LLVMBuildStore(builder, vec, values[0]);
647 return;
648 }
649
650 for (i = 0; i < value_count; i++) {
651 LLVMValueRef ptr = values[i * value_stride];
652 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
653 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
654 LLVMBuildStore(builder, value, ptr);
655 }
656 }
657
658 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
659 nir_ssa_def *def)
660 {
661 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
662 if (def->num_components > 1) {
663 type = LLVMVectorType(type, def->num_components);
664 }
665 return type;
666 }
667
668 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
669 {
670 assert(src.is_ssa);
671 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
672 return (LLVMValueRef)entry->data;
673 }
674
675
676 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
677 struct nir_block *b)
678 {
679 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
680 return (LLVMBasicBlockRef)entry->data;
681 }
682
683 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
684 nir_alu_src src,
685 unsigned num_components)
686 {
687 LLVMValueRef value = get_src(ctx, src.src);
688 bool need_swizzle = false;
689
690 assert(value);
691 LLVMTypeRef type = LLVMTypeOf(value);
692 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
693 ? LLVMGetVectorSize(type)
694 : 1;
695
696 for (unsigned i = 0; i < num_components; ++i) {
697 assert(src.swizzle[i] < src_components);
698 if (src.swizzle[i] != i)
699 need_swizzle = true;
700 }
701
702 if (need_swizzle || num_components != src_components) {
703 LLVMValueRef masks[] = {
704 LLVMConstInt(ctx->i32, src.swizzle[0], false),
705 LLVMConstInt(ctx->i32, src.swizzle[1], false),
706 LLVMConstInt(ctx->i32, src.swizzle[2], false),
707 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
708
709 if (src_components > 1 && num_components == 1) {
710 value = LLVMBuildExtractElement(ctx->builder, value,
711 masks[0], "");
712 } else if (src_components == 1 && num_components > 1) {
713 LLVMValueRef values[] = {value, value, value, value};
714 value = ac_build_gather_values(&ctx->ac, values, num_components);
715 } else {
716 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
717 value = LLVMBuildShuffleVector(ctx->builder, value, value,
718 swizzle, "");
719 }
720 }
721 assert(!src.negate);
722 assert(!src.abs);
723 return value;
724 }
725
726 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
727 LLVMIntPredicate pred, LLVMValueRef src0,
728 LLVMValueRef src1)
729 {
730 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
731 return LLVMBuildSelect(ctx->builder, result,
732 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
733 LLVMConstInt(ctx->i32, 0, false), "");
734 }
735
736 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
737 LLVMRealPredicate pred, LLVMValueRef src0,
738 LLVMValueRef src1)
739 {
740 LLVMValueRef result;
741 src0 = to_float(ctx, src0);
742 src1 = to_float(ctx, src1);
743 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
744 return LLVMBuildSelect(ctx->builder, result,
745 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
746 LLVMConstInt(ctx->i32, 0, false), "");
747 }
748
749 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
750 const char *intrin,
751 LLVMValueRef src0)
752 {
753 LLVMValueRef params[] = {
754 to_float(ctx, src0),
755 };
756 return ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->f32, params, 1, AC_FUNC_ATTR_READNONE);
757 }
758
759 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
760 const char *intrin,
761 LLVMValueRef src0, LLVMValueRef src1)
762 {
763 LLVMValueRef params[] = {
764 to_float(ctx, src0),
765 to_float(ctx, src1),
766 };
767 return ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->f32, params, 2, AC_FUNC_ATTR_READNONE);
768 }
769
770 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
771 const char *intrin,
772 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
773 {
774 LLVMValueRef params[] = {
775 to_float(ctx, src0),
776 to_float(ctx, src1),
777 to_float(ctx, src2),
778 };
779 return ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->f32, params, 3, AC_FUNC_ATTR_READNONE);
780 }
781
782 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
783 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
784 {
785 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
786 ctx->i32zero, "");
787 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
788 }
789
790 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
791 LLVMValueRef src0)
792 {
793 LLVMValueRef params[2] = {
794 src0,
795
796 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
797 * add special code to check for x=0. The reason is that
798 * the LLVM behavior for x=0 is different from what we
799 * need here.
800 *
801 * The hardware already implements the correct behavior.
802 */
803 LLVMConstInt(ctx->i32, 1, false),
804 };
805 return ac_emit_llvm_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
806 }
807
808 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
809 LLVMValueRef src0)
810 {
811 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.flbit.i32",
812 ctx->i32, &src0, 1,
813 AC_FUNC_ATTR_READNONE);
814
815 /* The HW returns the last bit index from MSB, but NIR wants
816 * the index from LSB. Invert it by doing "31 - msb". */
817 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
818 msb, "");
819
820 LLVMValueRef all_ones = LLVMConstInt(ctx->i32, -1, true);
821 LLVMValueRef cond = LLVMBuildOr(ctx->builder,
822 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
823 src0, ctx->i32zero, ""),
824 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
825 src0, all_ones, ""), "");
826
827 return LLVMBuildSelect(ctx->builder, cond, all_ones, msb, "");
828 }
829
830 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
831 LLVMValueRef src0)
832 {
833 LLVMValueRef args[2] = {
834 src0,
835 ctx->i32one,
836 };
837 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctlz.i32",
838 ctx->i32, args, ARRAY_SIZE(args),
839 AC_FUNC_ATTR_READNONE);
840
841 /* The HW returns the last bit index from MSB, but NIR wants
842 * the index from LSB. Invert it by doing "31 - msb". */
843 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
844 msb, "");
845
846 return LLVMBuildSelect(ctx->builder,
847 LLVMBuildICmp(ctx->builder, LLVMIntEQ, src0,
848 ctx->i32zero, ""),
849 LLVMConstInt(ctx->i32, -1, true), msb, "");
850 }
851
852 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
853 LLVMIntPredicate pred,
854 LLVMValueRef src0, LLVMValueRef src1)
855 {
856 return LLVMBuildSelect(ctx->builder,
857 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
858 src0,
859 src1, "");
860
861 }
862 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
863 LLVMValueRef src0)
864 {
865 return emit_minmax_int(ctx, LLVMIntSGT, src0,
866 LLVMBuildNeg(ctx->builder, src0, ""));
867 }
868
869 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
870 LLVMValueRef src0)
871 {
872 LLVMValueRef cmp, val;
873
874 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
875 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
876 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
877 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
878 return val;
879 }
880
881 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
882 LLVMValueRef src0)
883 {
884 LLVMValueRef cmp, val;
885
886 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
887 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
888 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
889 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
890 return val;
891 }
892
893 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
894 LLVMValueRef src0)
895 {
896 const char *intr = "llvm.floor.f32";
897 LLVMValueRef fsrc0 = to_float(ctx, src0);
898 LLVMValueRef params[] = {
899 fsrc0,
900 };
901 LLVMValueRef floor = ac_emit_llvm_intrinsic(&ctx->ac, intr,
902 ctx->f32, params, 1,
903 AC_FUNC_ATTR_READNONE);
904 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
905 }
906
907 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
908 const char *intrin,
909 LLVMValueRef src0, LLVMValueRef src1)
910 {
911 LLVMTypeRef ret_type;
912 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
913 LLVMValueRef res;
914 LLVMValueRef params[] = { src0, src1 };
915 ret_type = LLVMStructTypeInContext(ctx->context, types,
916 2, true);
917
918 res = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ret_type,
919 params, 2, AC_FUNC_ATTR_READNONE);
920
921 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
922 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
923 return res;
924 }
925
926 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
927 LLVMValueRef src0)
928 {
929 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
930 }
931
932 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
933 LLVMValueRef src0, LLVMValueRef src1)
934 {
935 LLVMValueRef dst64, result;
936 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
937 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
938
939 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
940 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
941 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
942 return result;
943 }
944
945 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
946 LLVMValueRef src0, LLVMValueRef src1)
947 {
948 LLVMValueRef dst64, result;
949 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
950 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
951
952 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
953 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
954 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
955 return result;
956 }
957
958 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
959 const char *intrin,
960 LLVMValueRef srcs[3])
961 {
962 LLVMValueRef result;
963 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
964 result = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->i32, srcs, 3, AC_FUNC_ATTR_READNONE);
965
966 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
967 return result;
968 }
969
970 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
971 LLVMValueRef src0, LLVMValueRef src1,
972 LLVMValueRef src2, LLVMValueRef src3)
973 {
974 LLVMValueRef bfi_args[3], result;
975
976 bfi_args[0] = LLVMBuildShl(ctx->builder,
977 LLVMBuildSub(ctx->builder,
978 LLVMBuildShl(ctx->builder,
979 ctx->i32one,
980 src3, ""),
981 ctx->i32one, ""),
982 src2, "");
983 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
984 bfi_args[2] = src0;
985
986 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
987
988 /* Calculate:
989 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
990 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
991 */
992 result = LLVMBuildXor(ctx->builder, bfi_args[2],
993 LLVMBuildAnd(ctx->builder, bfi_args[0],
994 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
995
996 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
997 return result;
998 }
999
1000 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1001 LLVMValueRef src0)
1002 {
1003 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1004 int i;
1005 LLVMValueRef comp[2];
1006
1007 src0 = to_float(ctx, src0);
1008 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1009 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1010 for (i = 0; i < 2; i++) {
1011 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1012 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1013 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1014 }
1015
1016 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1017 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1018
1019 return comp[0];
1020 }
1021
1022 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1023 LLVMValueRef src0)
1024 {
1025 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1026 LLVMValueRef temps[2], result, val;
1027 int i;
1028
1029 for (i = 0; i < 2; i++) {
1030 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1031 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1032 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1033 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1034 }
1035
1036 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1037 ctx->i32zero, "");
1038 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1039 ctx->i32one, "");
1040 return result;
1041 }
1042
1043 /**
1044 * Set range metadata on an instruction. This can only be used on load and
1045 * call instructions. If you know an instruction can only produce the values
1046 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1047 * \p lo is the minimum value inclusive.
1048 * \p hi is the maximum value exclusive.
1049 */
1050 static void set_range_metadata(struct nir_to_llvm_context *ctx,
1051 LLVMValueRef value, unsigned lo, unsigned hi)
1052 {
1053 LLVMValueRef range_md, md_args[2];
1054 LLVMTypeRef type = LLVMTypeOf(value);
1055 LLVMContextRef context = LLVMGetTypeContext(type);
1056
1057 md_args[0] = LLVMConstInt(type, lo, false);
1058 md_args[1] = LLVMConstInt(type, hi, false);
1059 range_md = LLVMMDNodeInContext(context, md_args, 2);
1060 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1061 }
1062
1063 static LLVMValueRef get_thread_id(struct nir_to_llvm_context *ctx)
1064 {
1065 LLVMValueRef tid;
1066 LLVMValueRef tid_args[2];
1067 tid_args[0] = LLVMConstInt(ctx->i32, 0xffffffff, false);
1068 tid_args[1] = ctx->i32zero;
1069 tid_args[1] = ac_emit_llvm_intrinsic(&ctx->ac,
1070 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1071 tid_args, 2, AC_FUNC_ATTR_READNONE);
1072
1073 tid = ac_emit_llvm_intrinsic(&ctx->ac,
1074 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1075 tid_args, 2, AC_FUNC_ATTR_READNONE);
1076 set_range_metadata(ctx, tid, 0, 64);
1077 return tid;
1078 }
1079
1080 /*
1081 * SI implements derivatives using the local data store (LDS)
1082 * All writes to the LDS happen in all executing threads at
1083 * the same time. TID is the Thread ID for the current
1084 * thread and is a value between 0 and 63, representing
1085 * the thread's position in the wavefront.
1086 *
1087 * For the pixel shader threads are grouped into quads of four pixels.
1088 * The TIDs of the pixels of a quad are:
1089 *
1090 * +------+------+
1091 * |4n + 0|4n + 1|
1092 * +------+------+
1093 * |4n + 2|4n + 3|
1094 * +------+------+
1095 *
1096 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
1097 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
1098 * the current pixel's column, and masking with 0xfffffffe yields the TID
1099 * of the left pixel of the current pixel's row.
1100 *
1101 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
1102 * adding 2 yields the TID of the pixel below the top pixel.
1103 */
1104 /* masks for thread ID. */
1105 #define TID_MASK_TOP_LEFT 0xfffffffc
1106 #define TID_MASK_TOP 0xfffffffd
1107 #define TID_MASK_LEFT 0xfffffffe
1108 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1109 nir_op op,
1110 LLVMValueRef src0)
1111 {
1112 LLVMValueRef tl, trbl, result;
1113 LLVMValueRef tl_tid, trbl_tid;
1114 LLVMValueRef args[2];
1115 LLVMValueRef thread_id;
1116 unsigned mask;
1117 int idx;
1118 ctx->has_ddxy = true;
1119
1120 if (!ctx->lds && !ctx->has_ds_bpermute)
1121 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1122 LLVMArrayType(ctx->i32, 64),
1123 "ddxy_lds", LOCAL_ADDR_SPACE);
1124
1125 thread_id = get_thread_id(ctx);
1126 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1127 mask = TID_MASK_LEFT;
1128 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1129 mask = TID_MASK_TOP;
1130 else
1131 mask = TID_MASK_TOP_LEFT;
1132
1133 tl_tid = LLVMBuildAnd(ctx->builder, thread_id,
1134 LLVMConstInt(ctx->i32, mask, false), "");
1135 /* for DDX we want to next X pixel, DDY next Y pixel. */
1136 if (op == nir_op_fddx_fine ||
1137 op == nir_op_fddx_coarse ||
1138 op == nir_op_fddx)
1139 idx = 1;
1140 else
1141 idx = 2;
1142
1143 trbl_tid = LLVMBuildAdd(ctx->builder, tl_tid,
1144 LLVMConstInt(ctx->i32, idx, false), "");
1145
1146 if (ctx->has_ds_bpermute) {
1147 args[0] = LLVMBuildMul(ctx->builder, tl_tid,
1148 LLVMConstInt(ctx->i32, 4, false), "");
1149 args[1] = src0;
1150 tl = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.ds.bpermute",
1151 ctx->i32, args, 2,
1152 AC_FUNC_ATTR_READNONE);
1153
1154 args[0] = LLVMBuildMul(ctx->builder, trbl_tid,
1155 LLVMConstInt(ctx->i32, 4, false), "");
1156 trbl = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.ds.bpermute",
1157 ctx->i32, args, 2,
1158 AC_FUNC_ATTR_READNONE);
1159 } else {
1160 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
1161
1162 store_ptr = build_gep0(ctx, ctx->lds, thread_id);
1163 load_ptr0 = build_gep0(ctx, ctx->lds, tl_tid);
1164 load_ptr1 = build_gep0(ctx, ctx->lds, trbl_tid);
1165
1166 LLVMBuildStore(ctx->builder, src0, store_ptr);
1167 tl = LLVMBuildLoad(ctx->builder, load_ptr0, "");
1168 trbl = LLVMBuildLoad(ctx->builder, load_ptr1, "");
1169 }
1170 tl = LLVMBuildBitCast(ctx->builder, tl, ctx->f32, "");
1171 trbl = LLVMBuildBitCast(ctx->builder, trbl, ctx->f32, "");
1172 result = LLVMBuildFSub(ctx->builder, trbl, tl, "");
1173 return result;
1174 }
1175
1176 /*
1177 * this takes an I,J coordinate pair,
1178 * and works out the X and Y derivatives.
1179 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1180 */
1181 static LLVMValueRef emit_ddxy_interp(
1182 struct nir_to_llvm_context *ctx,
1183 LLVMValueRef interp_ij)
1184 {
1185 LLVMValueRef result[4], a;
1186 unsigned i;
1187
1188 for (i = 0; i < 2; i++) {
1189 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1190 LLVMConstInt(ctx->i32, i, false), "");
1191 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1192 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1193 }
1194 return ac_build_gather_values(&ctx->ac, result, 4);
1195 }
1196
1197 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1198 {
1199 LLVMValueRef src[4], result = NULL;
1200 unsigned num_components = instr->dest.dest.ssa.num_components;
1201 unsigned src_components;
1202
1203 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1204 switch (instr->op) {
1205 case nir_op_vec2:
1206 case nir_op_vec3:
1207 case nir_op_vec4:
1208 src_components = 1;
1209 break;
1210 case nir_op_pack_half_2x16:
1211 src_components = 2;
1212 break;
1213 case nir_op_unpack_half_2x16:
1214 src_components = 1;
1215 break;
1216 default:
1217 src_components = num_components;
1218 break;
1219 }
1220 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1221 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1222
1223 switch (instr->op) {
1224 case nir_op_fmov:
1225 case nir_op_imov:
1226 result = src[0];
1227 break;
1228 case nir_op_fneg:
1229 src[0] = to_float(ctx, src[0]);
1230 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1231 break;
1232 case nir_op_ineg:
1233 result = LLVMBuildNeg(ctx->builder, src[0], "");
1234 break;
1235 case nir_op_inot:
1236 result = LLVMBuildNot(ctx->builder, src[0], "");
1237 break;
1238 case nir_op_iadd:
1239 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1240 break;
1241 case nir_op_fadd:
1242 src[0] = to_float(ctx, src[0]);
1243 src[1] = to_float(ctx, src[1]);
1244 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1245 break;
1246 case nir_op_fsub:
1247 src[0] = to_float(ctx, src[0]);
1248 src[1] = to_float(ctx, src[1]);
1249 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1250 break;
1251 case nir_op_isub:
1252 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1253 break;
1254 case nir_op_imul:
1255 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1256 break;
1257 case nir_op_imod:
1258 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1259 break;
1260 case nir_op_umod:
1261 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1262 break;
1263 case nir_op_fmod:
1264 src[0] = to_float(ctx, src[0]);
1265 src[1] = to_float(ctx, src[1]);
1266 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1267 result = emit_intrin_1f_param(ctx, "llvm.floor.f32", result);
1268 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1269 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1270 break;
1271 case nir_op_frem:
1272 src[0] = to_float(ctx, src[0]);
1273 src[1] = to_float(ctx, src[1]);
1274 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1275 break;
1276 case nir_op_idiv:
1277 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1278 break;
1279 case nir_op_udiv:
1280 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1281 break;
1282 case nir_op_fmul:
1283 src[0] = to_float(ctx, src[0]);
1284 src[1] = to_float(ctx, src[1]);
1285 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1286 break;
1287 case nir_op_fdiv:
1288 src[0] = to_float(ctx, src[0]);
1289 src[1] = to_float(ctx, src[1]);
1290 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1291 break;
1292 case nir_op_frcp:
1293 src[0] = to_float(ctx, src[0]);
1294 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, src[0]);
1295 break;
1296 case nir_op_iand:
1297 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1298 break;
1299 case nir_op_ior:
1300 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1301 break;
1302 case nir_op_ixor:
1303 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1304 break;
1305 case nir_op_ishl:
1306 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1307 break;
1308 case nir_op_ishr:
1309 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1310 break;
1311 case nir_op_ushr:
1312 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1313 break;
1314 case nir_op_ilt:
1315 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1316 break;
1317 case nir_op_ine:
1318 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1319 break;
1320 case nir_op_ieq:
1321 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1322 break;
1323 case nir_op_ige:
1324 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1325 break;
1326 case nir_op_ult:
1327 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1328 break;
1329 case nir_op_uge:
1330 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1331 break;
1332 case nir_op_feq:
1333 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1334 break;
1335 case nir_op_fne:
1336 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1337 break;
1338 case nir_op_flt:
1339 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1340 break;
1341 case nir_op_fge:
1342 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1343 break;
1344 case nir_op_fabs:
1345 result = emit_intrin_1f_param(ctx, "llvm.fabs.f32", src[0]);
1346 break;
1347 case nir_op_iabs:
1348 result = emit_iabs(ctx, src[0]);
1349 break;
1350 case nir_op_imax:
1351 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1352 break;
1353 case nir_op_imin:
1354 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1355 break;
1356 case nir_op_umax:
1357 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1358 break;
1359 case nir_op_umin:
1360 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1361 break;
1362 case nir_op_isign:
1363 result = emit_isign(ctx, src[0]);
1364 break;
1365 case nir_op_fsign:
1366 src[0] = to_float(ctx, src[0]);
1367 result = emit_fsign(ctx, src[0]);
1368 break;
1369 case nir_op_ffloor:
1370 result = emit_intrin_1f_param(ctx, "llvm.floor.f32", src[0]);
1371 break;
1372 case nir_op_ftrunc:
1373 result = emit_intrin_1f_param(ctx, "llvm.trunc.f32", src[0]);
1374 break;
1375 case nir_op_fceil:
1376 result = emit_intrin_1f_param(ctx, "llvm.ceil.f32", src[0]);
1377 break;
1378 case nir_op_fround_even:
1379 result = emit_intrin_1f_param(ctx, "llvm.rint.f32", src[0]);
1380 break;
1381 case nir_op_ffract:
1382 result = emit_ffract(ctx, src[0]);
1383 break;
1384 case nir_op_fsin:
1385 result = emit_intrin_1f_param(ctx, "llvm.sin.f32", src[0]);
1386 break;
1387 case nir_op_fcos:
1388 result = emit_intrin_1f_param(ctx, "llvm.cos.f32", src[0]);
1389 break;
1390 case nir_op_fsqrt:
1391 result = emit_intrin_1f_param(ctx, "llvm.sqrt.f32", src[0]);
1392 break;
1393 case nir_op_fexp2:
1394 result = emit_intrin_1f_param(ctx, "llvm.exp2.f32", src[0]);
1395 break;
1396 case nir_op_flog2:
1397 result = emit_intrin_1f_param(ctx, "llvm.log2.f32", src[0]);
1398 break;
1399 case nir_op_frsq:
1400 result = emit_intrin_1f_param(ctx, "llvm.sqrt.f32", src[0]);
1401 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, result);
1402 break;
1403 case nir_op_fpow:
1404 result = emit_intrin_2f_param(ctx, "llvm.pow.f32", src[0], src[1]);
1405 break;
1406 case nir_op_fmax:
1407 result = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", src[0], src[1]);
1408 break;
1409 case nir_op_fmin:
1410 result = emit_intrin_2f_param(ctx, "llvm.minnum.f32", src[0], src[1]);
1411 break;
1412 case nir_op_ffma:
1413 result = emit_intrin_3f_param(ctx, "llvm.fma.f32", src[0], src[1], src[2]);
1414 break;
1415 case nir_op_ibitfield_extract:
1416 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.i32", src);
1417 break;
1418 case nir_op_ubitfield_extract:
1419 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.u32", src);
1420 break;
1421 case nir_op_bitfield_insert:
1422 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1423 break;
1424 case nir_op_bitfield_reverse:
1425 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1426 break;
1427 case nir_op_bit_count:
1428 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1429 break;
1430 case nir_op_vec2:
1431 case nir_op_vec3:
1432 case nir_op_vec4:
1433 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1434 src[i] = to_integer(ctx, src[i]);
1435 result = ac_build_gather_values(&ctx->ac, src, num_components);
1436 break;
1437 case nir_op_f2i:
1438 src[0] = to_float(ctx, src[0]);
1439 result = LLVMBuildFPToSI(ctx->builder, src[0], ctx->i32, "");
1440 break;
1441 case nir_op_f2u:
1442 src[0] = to_float(ctx, src[0]);
1443 result = LLVMBuildFPToUI(ctx->builder, src[0], ctx->i32, "");
1444 break;
1445 case nir_op_i2f:
1446 result = LLVMBuildSIToFP(ctx->builder, src[0], ctx->f32, "");
1447 break;
1448 case nir_op_u2f:
1449 result = LLVMBuildUIToFP(ctx->builder, src[0], ctx->f32, "");
1450 break;
1451 case nir_op_bcsel:
1452 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1453 break;
1454 case nir_op_find_lsb:
1455 result = emit_find_lsb(ctx, src[0]);
1456 break;
1457 case nir_op_ufind_msb:
1458 result = emit_ufind_msb(ctx, src[0]);
1459 break;
1460 case nir_op_ifind_msb:
1461 result = emit_ifind_msb(ctx, src[0]);
1462 break;
1463 case nir_op_uadd_carry:
1464 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1465 break;
1466 case nir_op_usub_borrow:
1467 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1468 break;
1469 case nir_op_b2f:
1470 result = emit_b2f(ctx, src[0]);
1471 break;
1472 case nir_op_fquantize2f16:
1473 src[0] = to_float(ctx, src[0]);
1474 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1475 /* need to convert back up to f32 */
1476 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1477 break;
1478 case nir_op_umul_high:
1479 result = emit_umul_high(ctx, src[0], src[1]);
1480 break;
1481 case nir_op_imul_high:
1482 result = emit_imul_high(ctx, src[0], src[1]);
1483 break;
1484 case nir_op_pack_half_2x16:
1485 result = emit_pack_half_2x16(ctx, src[0]);
1486 break;
1487 case nir_op_unpack_half_2x16:
1488 result = emit_unpack_half_2x16(ctx, src[0]);
1489 break;
1490 case nir_op_fddx:
1491 case nir_op_fddy:
1492 case nir_op_fddx_fine:
1493 case nir_op_fddy_fine:
1494 case nir_op_fddx_coarse:
1495 case nir_op_fddy_coarse:
1496 result = emit_ddxy(ctx, instr->op, src[0]);
1497 break;
1498 default:
1499 fprintf(stderr, "Unknown NIR alu instr: ");
1500 nir_print_instr(&instr->instr, stderr);
1501 fprintf(stderr, "\n");
1502 abort();
1503 }
1504
1505 if (result) {
1506 assert(instr->dest.dest.is_ssa);
1507 result = to_integer(ctx, result);
1508 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1509 result);
1510 }
1511 }
1512
1513 static void visit_load_const(struct nir_to_llvm_context *ctx,
1514 nir_load_const_instr *instr)
1515 {
1516 LLVMValueRef values[4], value = NULL;
1517 LLVMTypeRef element_type =
1518 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1519
1520 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1521 switch (instr->def.bit_size) {
1522 case 32:
1523 values[i] = LLVMConstInt(element_type,
1524 instr->value.u32[i], false);
1525 break;
1526 case 64:
1527 values[i] = LLVMConstInt(element_type,
1528 instr->value.u64[i], false);
1529 break;
1530 default:
1531 fprintf(stderr,
1532 "unsupported nir load_const bit_size: %d\n",
1533 instr->def.bit_size);
1534 abort();
1535 }
1536 }
1537 if (instr->def.num_components > 1) {
1538 value = LLVMConstVector(values, instr->def.num_components);
1539 } else
1540 value = values[0];
1541
1542 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1543 }
1544
1545 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1546 LLVMTypeRef type)
1547 {
1548 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1549 return LLVMBuildBitCast(ctx->builder, ptr,
1550 LLVMPointerType(type, addr_space), "");
1551 }
1552
1553 static LLVMValueRef
1554 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1555 {
1556 LLVMValueRef size =
1557 LLVMBuildExtractElement(ctx->builder, descriptor,
1558 LLVMConstInt(ctx->i32, 2, false), "");
1559
1560 /* VI only */
1561 if (ctx->options->chip_class >= VI && in_elements) {
1562 /* On VI, the descriptor contains the size in bytes,
1563 * but TXQ must return the size in elements.
1564 * The stride is always non-zero for resources using TXQ.
1565 */
1566 LLVMValueRef stride =
1567 LLVMBuildExtractElement(ctx->builder, descriptor,
1568 LLVMConstInt(ctx->i32, 1, false), "");
1569 stride = LLVMBuildLShr(ctx->builder, stride,
1570 LLVMConstInt(ctx->i32, 16, false), "");
1571 stride = LLVMBuildAnd(ctx->builder, stride,
1572 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1573
1574 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1575 }
1576 return size;
1577 }
1578
1579 /**
1580 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1581 * intrinsic names).
1582 */
1583 static void build_int_type_name(
1584 LLVMTypeRef type,
1585 char *buf, unsigned bufsize)
1586 {
1587 assert(bufsize >= 6);
1588
1589 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1590 snprintf(buf, bufsize, "v%ui32",
1591 LLVMGetVectorSize(type));
1592 else
1593 strcpy(buf, "i32");
1594 }
1595
1596 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1597 struct ac_tex_info *tinfo,
1598 nir_tex_instr *instr,
1599 const char *intr_name,
1600 unsigned coord_vgpr_index)
1601 {
1602 LLVMValueRef coord = tinfo->args[0];
1603 LLVMValueRef half_texel[2];
1604 int c;
1605
1606 //TODO Rect
1607 {
1608 LLVMValueRef txq_args[10];
1609 int txq_arg_count = 0;
1610 LLVMValueRef size;
1611 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1612 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, false);
1613 txq_args[txq_arg_count++] = tinfo->args[1];
1614 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0xf, 0); /* dmask */
1615 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* unorm */
1616 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
1617 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
1618 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
1619 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
1620 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
1621 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
1622 size = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
1623 txq_args, txq_arg_count,
1624 AC_FUNC_ATTR_READNONE);
1625
1626 for (c = 0; c < 2; c++) {
1627 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1628 LLVMConstInt(ctx->i32, c, false), "");
1629 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1630 half_texel[c] = ac_emit_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1631 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1632 LLVMConstReal(ctx->f32, -0.5), "");
1633 }
1634 }
1635
1636 for (c = 0; c < 2; c++) {
1637 LLVMValueRef tmp;
1638 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1639 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1640 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1641 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1642 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1643 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1644 }
1645
1646 tinfo->args[0] = coord;
1647 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1648 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1649
1650 }
1651
1652 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1653 nir_tex_instr *instr,
1654 struct ac_tex_info *tinfo)
1655 {
1656 const char *name = "llvm.SI.image.sample";
1657 const char *infix = "";
1658 char intr_name[127];
1659 char type[64];
1660 bool is_shadow = instr->is_shadow;
1661 bool has_offset = tinfo->has_offset;
1662 switch (instr->op) {
1663 case nir_texop_txf:
1664 case nir_texop_txf_ms:
1665 case nir_texop_samples_identical:
1666 name = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? "llvm.SI.image.load" :
1667 instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? "llvm.SI.vs.load.input" :
1668 "llvm.SI.image.load.mip";
1669 is_shadow = false;
1670 has_offset = false;
1671 break;
1672 case nir_texop_txb:
1673 infix = ".b";
1674 break;
1675 case nir_texop_txl:
1676 infix = ".l";
1677 break;
1678 case nir_texop_txs:
1679 name = "llvm.SI.getresinfo";
1680 break;
1681 case nir_texop_query_levels:
1682 name = "llvm.SI.getresinfo";
1683 break;
1684 case nir_texop_tex:
1685 if (ctx->stage != MESA_SHADER_FRAGMENT)
1686 infix = ".lz";
1687 break;
1688 case nir_texop_txd:
1689 infix = ".d";
1690 break;
1691 case nir_texop_tg4:
1692 name = "llvm.SI.gather4";
1693 infix = ".lz";
1694 break;
1695 case nir_texop_lod:
1696 name = "llvm.SI.getlod";
1697 is_shadow = false;
1698 has_offset = false;
1699 break;
1700 default:
1701 break;
1702 }
1703
1704 build_int_type_name(LLVMTypeOf(tinfo->args[0]), type, sizeof(type));
1705 sprintf(intr_name, "%s%s%s%s.%s", name, is_shadow ? ".c" : "", infix,
1706 has_offset ? ".o" : "", type);
1707
1708 if (instr->op == nir_texop_tg4) {
1709 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1710 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1711 return radv_lower_gather4_integer(ctx, tinfo, instr, intr_name,
1712 (int)has_offset + (int)is_shadow);
1713 }
1714 }
1715 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1716 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1717
1718 }
1719
1720 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1721 nir_intrinsic_instr *instr)
1722 {
1723 LLVMValueRef index = get_src(ctx, instr->src[0]);
1724 unsigned desc_set = nir_intrinsic_desc_set(instr);
1725 unsigned binding = nir_intrinsic_binding(instr);
1726 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1727 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
1728 unsigned base_offset = layout->binding[binding].offset;
1729 LLVMValueRef offset, stride;
1730
1731 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1732 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1733 desc_ptr = ctx->push_constants;
1734 base_offset = ctx->options->layout->push_constant_size;
1735 base_offset += 16 * layout->binding[binding].dynamic_offset_offset;
1736 stride = LLVMConstInt(ctx->i32, 16, false);
1737 } else
1738 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1739
1740 offset = LLVMConstInt(ctx->i32, base_offset, false);
1741 index = LLVMBuildMul(ctx->builder, index, stride, "");
1742 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1743
1744 desc_ptr = build_gep0(ctx, desc_ptr, offset);
1745 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1746 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1747
1748 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1749 }
1750
1751 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1752 nir_intrinsic_instr *instr)
1753 {
1754 LLVMValueRef ptr, addr;
1755
1756 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1757 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1758
1759 ptr = build_gep0(ctx, ctx->push_constants, addr);
1760 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1761
1762 return LLVMBuildLoad(ctx->builder, ptr, "");
1763 }
1764
1765 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1766 nir_intrinsic_instr *instr)
1767 {
1768 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1769
1770 return get_buffer_size(ctx, desc, false);
1771 }
1772 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1773 nir_intrinsic_instr *instr)
1774 {
1775 const char *store_name;
1776 LLVMTypeRef data_type = ctx->f32;
1777 unsigned writemask = nir_intrinsic_write_mask(instr);
1778 LLVMValueRef base_data, base_offset;
1779 LLVMValueRef params[6];
1780
1781 if (ctx->stage == MESA_SHADER_FRAGMENT)
1782 ctx->shader_info->fs.writes_memory = true;
1783
1784 params[1] = get_src(ctx, instr->src[1]);
1785 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1786 params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
1787 params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1788
1789 if (instr->num_components > 1)
1790 data_type = LLVMVectorType(ctx->f32, instr->num_components);
1791
1792 base_data = to_float(ctx, get_src(ctx, instr->src[0]));
1793 base_data = trim_vector(ctx, base_data, instr->num_components);
1794 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1795 data_type, "");
1796 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1797 while (writemask) {
1798 int start, count;
1799 LLVMValueRef data;
1800 LLVMValueRef offset;
1801 LLVMValueRef tmp;
1802 u_bit_scan_consecutive_range(&writemask, &start, &count);
1803
1804 /* Due to an LLVM limitation, split 3-element writes
1805 * into a 2-element and a 1-element write. */
1806 if (count == 3) {
1807 writemask |= 1 << (start + 2);
1808 count = 2;
1809 }
1810
1811 if (count == 4) {
1812 store_name = "llvm.amdgcn.buffer.store.v4f32";
1813 data = base_data;
1814 } else if (count == 2) {
1815 tmp = LLVMBuildExtractElement(ctx->builder,
1816 base_data, LLVMConstInt(ctx->i32, start, false), "");
1817 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
1818 ctx->i32zero, "");
1819
1820 tmp = LLVMBuildExtractElement(ctx->builder,
1821 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
1822 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
1823 ctx->i32one, "");
1824 store_name = "llvm.amdgcn.buffer.store.v2f32";
1825
1826 } else {
1827 assert(count == 1);
1828 if (get_llvm_num_components(base_data) > 1)
1829 data = LLVMBuildExtractElement(ctx->builder, base_data,
1830 LLVMConstInt(ctx->i32, start, false), "");
1831 else
1832 data = base_data;
1833 store_name = "llvm.amdgcn.buffer.store.f32";
1834 }
1835
1836 offset = base_offset;
1837 if (start != 0) {
1838 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
1839 }
1840 params[0] = data;
1841 params[3] = offset;
1842 ac_emit_llvm_intrinsic(&ctx->ac, store_name,
1843 ctx->voidt, params, 6, 0);
1844 }
1845 }
1846
1847 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
1848 nir_intrinsic_instr *instr)
1849 {
1850 const char *name;
1851 LLVMValueRef params[6];
1852 int arg_count = 0;
1853 if (ctx->stage == MESA_SHADER_FRAGMENT)
1854 ctx->shader_info->fs.writes_memory = true;
1855
1856 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
1857 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
1858 }
1859 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
1860 params[arg_count++] = get_src(ctx, instr->src[0]);
1861 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1862 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
1863 params[arg_count++] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1864
1865 switch (instr->intrinsic) {
1866 case nir_intrinsic_ssbo_atomic_add:
1867 name = "llvm.amdgcn.buffer.atomic.add";
1868 break;
1869 case nir_intrinsic_ssbo_atomic_imin:
1870 name = "llvm.amdgcn.buffer.atomic.smin";
1871 break;
1872 case nir_intrinsic_ssbo_atomic_umin:
1873 name = "llvm.amdgcn.buffer.atomic.umin";
1874 break;
1875 case nir_intrinsic_ssbo_atomic_imax:
1876 name = "llvm.amdgcn.buffer.atomic.smax";
1877 break;
1878 case nir_intrinsic_ssbo_atomic_umax:
1879 name = "llvm.amdgcn.buffer.atomic.umax";
1880 break;
1881 case nir_intrinsic_ssbo_atomic_and:
1882 name = "llvm.amdgcn.buffer.atomic.and";
1883 break;
1884 case nir_intrinsic_ssbo_atomic_or:
1885 name = "llvm.amdgcn.buffer.atomic.or";
1886 break;
1887 case nir_intrinsic_ssbo_atomic_xor:
1888 name = "llvm.amdgcn.buffer.atomic.xor";
1889 break;
1890 case nir_intrinsic_ssbo_atomic_exchange:
1891 name = "llvm.amdgcn.buffer.atomic.swap";
1892 break;
1893 case nir_intrinsic_ssbo_atomic_comp_swap:
1894 name = "llvm.amdgcn.buffer.atomic.cmpswap";
1895 break;
1896 default:
1897 abort();
1898 }
1899
1900 return ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
1901 }
1902
1903 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
1904 nir_intrinsic_instr *instr)
1905 {
1906 const char *load_name;
1907 LLVMTypeRef data_type = ctx->f32;
1908 if (instr->num_components == 3)
1909 data_type = LLVMVectorType(ctx->f32, 4);
1910 else if (instr->num_components > 1)
1911 data_type = LLVMVectorType(ctx->f32, instr->num_components);
1912
1913 if (instr->num_components == 4 || instr->num_components == 3)
1914 load_name = "llvm.amdgcn.buffer.load.v4f32";
1915 else if (instr->num_components == 2)
1916 load_name = "llvm.amdgcn.buffer.load.v2f32";
1917 else if (instr->num_components == 1)
1918 load_name = "llvm.amdgcn.buffer.load.f32";
1919 else
1920 abort();
1921
1922 LLVMValueRef params[] = {
1923 get_src(ctx, instr->src[0]),
1924 LLVMConstInt(ctx->i32, 0, false),
1925 get_src(ctx, instr->src[1]),
1926 LLVMConstInt(ctx->i1, 0, false),
1927 LLVMConstInt(ctx->i1, 0, false),
1928 };
1929
1930 LLVMValueRef ret =
1931 ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
1932
1933 if (instr->num_components == 3)
1934 ret = trim_vector(ctx, ret, 3);
1935
1936 return LLVMBuildBitCast(ctx->builder, ret,
1937 get_def_type(ctx, &instr->dest.ssa), "");
1938 }
1939
1940 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
1941 nir_intrinsic_instr *instr)
1942 {
1943 LLVMValueRef results[4], ret;
1944 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
1945 LLVMValueRef offset = get_src(ctx, instr->src[1]);
1946
1947 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
1948
1949 for (unsigned i = 0; i < instr->num_components; ++i) {
1950 LLVMValueRef params[] = {
1951 rsrc,
1952 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
1953 offset, "")
1954 };
1955 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
1956 params, 2, AC_FUNC_ATTR_READNONE);
1957 }
1958
1959
1960 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
1961 return LLVMBuildBitCast(ctx->builder, ret,
1962 get_def_type(ctx, &instr->dest.ssa), "");
1963 }
1964
1965 static void
1966 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
1967 bool vs_in, unsigned *const_out, LLVMValueRef *indir_out)
1968 {
1969 unsigned const_offset = 0;
1970 LLVMValueRef offset = NULL;
1971
1972
1973 while (tail->child != NULL) {
1974 const struct glsl_type *parent_type = tail->type;
1975 tail = tail->child;
1976
1977 if (tail->deref_type == nir_deref_type_array) {
1978 nir_deref_array *deref_array = nir_deref_as_array(tail);
1979 LLVMValueRef index, stride, local_offset;
1980 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
1981
1982 const_offset += size * deref_array->base_offset;
1983 if (deref_array->deref_array_type == nir_deref_array_type_direct)
1984 continue;
1985
1986 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
1987 index = get_src(ctx, deref_array->indirect);
1988 stride = LLVMConstInt(ctx->i32, size, 0);
1989 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
1990
1991 if (offset)
1992 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
1993 else
1994 offset = local_offset;
1995 } else if (tail->deref_type == nir_deref_type_struct) {
1996 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
1997
1998 for (unsigned i = 0; i < deref_struct->index; i++) {
1999 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2000 const_offset += glsl_count_attribute_slots(ft, vs_in);
2001 }
2002 } else
2003 unreachable("unsupported deref type");
2004
2005 }
2006
2007 if (const_offset && offset)
2008 offset = LLVMBuildAdd(ctx->builder, offset,
2009 LLVMConstInt(ctx->i32, const_offset, 0),
2010 "");
2011
2012 *const_out = const_offset;
2013 *indir_out = offset;
2014 }
2015
2016 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2017 nir_intrinsic_instr *instr)
2018 {
2019 LLVMValueRef values[4];
2020 int idx = instr->variables[0]->var->data.driver_location;
2021 int ve = instr->dest.ssa.num_components;
2022 LLVMValueRef indir_index;
2023 unsigned const_index;
2024 switch (instr->variables[0]->var->data.mode) {
2025 case nir_var_shader_in:
2026 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2027 ctx->stage == MESA_SHADER_VERTEX,
2028 &const_index, &indir_index);
2029 for (unsigned chan = 0; chan < ve; chan++) {
2030 if (indir_index) {
2031 unsigned count = glsl_count_attribute_slots(
2032 instr->variables[0]->var->type,
2033 ctx->stage == MESA_SHADER_VERTEX);
2034 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2035 &ctx->ac, ctx->inputs + idx + chan, count,
2036 4, false);
2037
2038 values[chan] = LLVMBuildExtractElement(ctx->builder,
2039 tmp_vec,
2040 indir_index, "");
2041 } else
2042 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2043 }
2044 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2045 break;
2046 case nir_var_local:
2047 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2048 &const_index, &indir_index);
2049 for (unsigned chan = 0; chan < ve; chan++) {
2050 if (indir_index) {
2051 unsigned count = glsl_count_attribute_slots(
2052 instr->variables[0]->var->type, false);
2053 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2054 &ctx->ac, ctx->locals + idx + chan, count,
2055 4, true);
2056
2057 values[chan] = LLVMBuildExtractElement(ctx->builder,
2058 tmp_vec,
2059 indir_index, "");
2060 } else {
2061 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2062 }
2063 }
2064 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2065 case nir_var_shader_out:
2066 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2067 &const_index, &indir_index);
2068 for (unsigned chan = 0; chan < ve; chan++) {
2069 if (indir_index) {
2070 unsigned count = glsl_count_attribute_slots(
2071 instr->variables[0]->var->type, false);
2072 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2073 &ctx->ac, ctx->outputs + idx + chan, count,
2074 4, true);
2075
2076 values[chan] = LLVMBuildExtractElement(ctx->builder,
2077 tmp_vec,
2078 indir_index, "");
2079 } else {
2080 values[chan] = LLVMBuildLoad(ctx->builder,
2081 ctx->outputs[idx + chan + const_index * 4],
2082 "");
2083 }
2084 }
2085 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2086 case nir_var_shared: {
2087 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2088 &const_index, &indir_index);
2089 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2090 LLVMValueRef derived_ptr;
2091
2092 for (unsigned chan = 0; chan < ve; chan++) {
2093 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2094 if (indir_index)
2095 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2096 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2097 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2098 }
2099 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2100 }
2101 default:
2102 break;
2103 }
2104 return NULL;
2105 }
2106
2107 static void
2108 visit_store_var(struct nir_to_llvm_context *ctx,
2109 nir_intrinsic_instr *instr)
2110 {
2111 LLVMValueRef temp_ptr, value;
2112 int idx = instr->variables[0]->var->data.driver_location;
2113 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2114 int writemask = instr->const_index[0];
2115 LLVMValueRef indir_index;
2116 unsigned const_index;
2117 switch (instr->variables[0]->var->data.mode) {
2118 case nir_var_shader_out:
2119 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2120 &const_index, &indir_index);
2121 for (unsigned chan = 0; chan < 4; chan++) {
2122 int stride = 4;
2123 if (!(writemask & (1 << chan)))
2124 continue;
2125 if (get_llvm_num_components(src) == 1)
2126 value = src;
2127 else
2128 value = LLVMBuildExtractElement(ctx->builder, src,
2129 LLVMConstInt(ctx->i32,
2130 chan, false),
2131 "");
2132
2133 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2134 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2135 stride = 1;
2136 if (indir_index) {
2137 unsigned count = glsl_count_attribute_slots(
2138 instr->variables[0]->var->type, false);
2139 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2140 &ctx->ac, ctx->outputs + idx + chan, count,
2141 stride, true);
2142
2143 if (get_llvm_num_components(tmp_vec) > 1) {
2144 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2145 value, indir_index, "");
2146 } else
2147 tmp_vec = value;
2148 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2149 count, stride, tmp_vec);
2150
2151 } else {
2152 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2153
2154 LLVMBuildStore(ctx->builder, value, temp_ptr);
2155 }
2156 }
2157 break;
2158 case nir_var_local:
2159 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2160 &const_index, &indir_index);
2161 for (unsigned chan = 0; chan < 4; chan++) {
2162 if (!(writemask & (1 << chan)))
2163 continue;
2164
2165 if (get_llvm_num_components(src) == 1)
2166 value = src;
2167 else
2168 value = LLVMBuildExtractElement(ctx->builder, src,
2169 LLVMConstInt(ctx->i32, chan, false), "");
2170 if (indir_index) {
2171 unsigned count = glsl_count_attribute_slots(
2172 instr->variables[0]->var->type, false);
2173 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2174 &ctx->ac, ctx->locals + idx + chan, count,
2175 4, true);
2176
2177 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2178 value, indir_index, "");
2179 build_store_values_extended(ctx, ctx->locals + idx + chan,
2180 count, 4, tmp_vec);
2181 } else {
2182 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2183
2184 LLVMBuildStore(ctx->builder, value, temp_ptr);
2185 }
2186 }
2187 break;
2188 case nir_var_shared: {
2189 LLVMValueRef ptr;
2190 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2191 &const_index, &indir_index);
2192
2193 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2194 LLVMValueRef derived_ptr;
2195
2196 for (unsigned chan = 0; chan < 4; chan++) {
2197 if (!(writemask & (1 << chan)))
2198 continue;
2199
2200 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2201
2202 if (get_llvm_num_components(src) == 1)
2203 value = src;
2204 else
2205 value = LLVMBuildExtractElement(ctx->builder, src,
2206 LLVMConstInt(ctx->i32,
2207 chan, false),
2208 "");
2209
2210 if (indir_index)
2211 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2212
2213 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2214 LLVMBuildStore(ctx->builder,
2215 to_integer(ctx, value), derived_ptr);
2216 }
2217 break;
2218 }
2219 default:
2220 break;
2221 }
2222 }
2223
2224 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2225 {
2226 switch (dim) {
2227 case GLSL_SAMPLER_DIM_BUF:
2228 return 1;
2229 case GLSL_SAMPLER_DIM_1D:
2230 return array ? 2 : 1;
2231 case GLSL_SAMPLER_DIM_2D:
2232 return array ? 3 : 2;
2233 case GLSL_SAMPLER_DIM_MS:
2234 return array ? 4 : 3;
2235 case GLSL_SAMPLER_DIM_3D:
2236 case GLSL_SAMPLER_DIM_CUBE:
2237 return 3;
2238 case GLSL_SAMPLER_DIM_RECT:
2239 case GLSL_SAMPLER_DIM_SUBPASS:
2240 return 2;
2241 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2242 return 3;
2243 default:
2244 break;
2245 }
2246 return 0;
2247 }
2248
2249 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2250 nir_intrinsic_instr *instr)
2251 {
2252 const struct glsl_type *type = instr->variables[0]->var->type;
2253 if(instr->variables[0]->deref.child)
2254 type = instr->variables[0]->deref.child->type;
2255
2256 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2257 LLVMValueRef coords[4];
2258 LLVMValueRef masks[] = {
2259 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2260 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2261 };
2262 LLVMValueRef res;
2263 int count;
2264 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2265 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2266 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2267 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2268 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2269
2270 count = image_type_to_components_count(dim,
2271 glsl_sampler_type_is_array(type));
2272
2273 if (count == 1) {
2274 if (instr->src[0].ssa->num_components)
2275 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2276 else
2277 res = src0;
2278 } else {
2279 int chan;
2280 if (is_ms)
2281 count--;
2282 for (chan = 0; chan < count; ++chan) {
2283 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2284 }
2285
2286 if (add_frag_pos) {
2287 for (chan = 0; chan < count; ++chan)
2288 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2289 }
2290 if (is_ms) {
2291 coords[count] = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2292 count++;
2293 }
2294
2295 if (count == 3) {
2296 coords[3] = LLVMGetUndef(ctx->i32);
2297 count = 4;
2298 }
2299 res = ac_build_gather_values(&ctx->ac, coords, count);
2300 }
2301 return res;
2302 }
2303
2304 static void build_type_name_for_intr(
2305 LLVMTypeRef type,
2306 char *buf, unsigned bufsize)
2307 {
2308 LLVMTypeRef elem_type = type;
2309
2310 assert(bufsize >= 8);
2311
2312 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
2313 int ret = snprintf(buf, bufsize, "v%u",
2314 LLVMGetVectorSize(type));
2315 if (ret < 0) {
2316 char *type_name = LLVMPrintTypeToString(type);
2317 fprintf(stderr, "Error building type name for: %s\n",
2318 type_name);
2319 return;
2320 }
2321 elem_type = LLVMGetElementType(type);
2322 buf += ret;
2323 bufsize -= ret;
2324 }
2325 switch (LLVMGetTypeKind(elem_type)) {
2326 default: break;
2327 case LLVMIntegerTypeKind:
2328 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
2329 break;
2330 case LLVMFloatTypeKind:
2331 snprintf(buf, bufsize, "f32");
2332 break;
2333 case LLVMDoubleTypeKind:
2334 snprintf(buf, bufsize, "f64");
2335 break;
2336 }
2337 }
2338
2339 static void get_image_intr_name(const char *base_name,
2340 LLVMTypeRef data_type,
2341 LLVMTypeRef coords_type,
2342 LLVMTypeRef rsrc_type,
2343 char *out_name, unsigned out_len)
2344 {
2345 char coords_type_name[8];
2346
2347 build_type_name_for_intr(coords_type, coords_type_name,
2348 sizeof(coords_type_name));
2349
2350 if (HAVE_LLVM <= 0x0309) {
2351 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
2352 } else {
2353 char data_type_name[8];
2354 char rsrc_type_name[8];
2355
2356 build_type_name_for_intr(data_type, data_type_name,
2357 sizeof(data_type_name));
2358 build_type_name_for_intr(rsrc_type, rsrc_type_name,
2359 sizeof(rsrc_type_name));
2360 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
2361 data_type_name, coords_type_name, rsrc_type_name);
2362 }
2363 }
2364
2365 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2366 nir_intrinsic_instr *instr)
2367 {
2368 LLVMValueRef params[7];
2369 LLVMValueRef res;
2370 char intrinsic_name[64];
2371 const nir_variable *var = instr->variables[0]->var;
2372 const struct glsl_type *type = var->type;
2373 if(instr->variables[0]->deref.child)
2374 type = instr->variables[0]->deref.child->type;
2375
2376 type = glsl_without_array(type);
2377 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2378 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2379 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2380 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2381 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2382 params[3] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2383 params[4] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2384 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2385 params, 5, 0);
2386
2387 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2388 res = to_integer(ctx, res);
2389 } else {
2390 bool is_da = glsl_sampler_type_is_array(type) ||
2391 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2392 LLVMValueRef da = is_da ? ctx->i32one : ctx->i32zero;
2393 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2394 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2395
2396 params[0] = get_image_coords(ctx, instr);
2397 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2398 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2399 if (HAVE_LLVM <= 0x0309) {
2400 params[3] = LLVMConstInt(ctx->i1, 0, false); /* r128 */
2401 params[4] = da;
2402 params[5] = glc;
2403 params[6] = slc;
2404 } else {
2405 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2406 params[3] = glc;
2407 params[4] = slc;
2408 params[5] = lwe;
2409 params[6] = da;
2410 }
2411
2412 get_image_intr_name("llvm.amdgcn.image.load",
2413 ctx->v4f32, /* vdata */
2414 LLVMTypeOf(params[0]), /* coords */
2415 LLVMTypeOf(params[1]), /* rsrc */
2416 intrinsic_name, sizeof(intrinsic_name));
2417
2418 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2419 params, 7, AC_FUNC_ATTR_READONLY);
2420 }
2421 return to_integer(ctx, res);
2422 }
2423
2424 static void visit_image_store(struct nir_to_llvm_context *ctx,
2425 nir_intrinsic_instr *instr)
2426 {
2427 LLVMValueRef params[8];
2428 char intrinsic_name[64];
2429 const nir_variable *var = instr->variables[0]->var;
2430 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2431 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2432 const struct glsl_type *type = glsl_without_array(var->type);
2433
2434 if (ctx->stage == MESA_SHADER_FRAGMENT)
2435 ctx->shader_info->fs.writes_memory = true;
2436
2437 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2438 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2439 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2440 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2441 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2442 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2443 params[4] = i1false; /* glc */
2444 params[5] = i1false; /* slc */
2445 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2446 params, 6, 0);
2447 } else {
2448 bool is_da = glsl_sampler_type_is_array(type) ||
2449 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2450 LLVMValueRef da = is_da ? i1true : i1false;
2451 LLVMValueRef glc = i1false;
2452 LLVMValueRef slc = i1false;
2453
2454 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2455 params[1] = get_image_coords(ctx, instr); /* coords */
2456 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2457 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2458 if (HAVE_LLVM <= 0x0309) {
2459 params[4] = i1false; /* r128 */
2460 params[5] = da;
2461 params[6] = glc;
2462 params[7] = slc;
2463 } else {
2464 LLVMValueRef lwe = i1false;
2465 params[4] = glc;
2466 params[5] = slc;
2467 params[6] = lwe;
2468 params[7] = da;
2469 }
2470
2471 get_image_intr_name("llvm.amdgcn.image.store",
2472 LLVMTypeOf(params[0]), /* vdata */
2473 LLVMTypeOf(params[1]), /* coords */
2474 LLVMTypeOf(params[2]), /* rsrc */
2475 intrinsic_name, sizeof(intrinsic_name));
2476
2477 ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2478 params, 8, 0);
2479 }
2480
2481 }
2482
2483 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2484 nir_intrinsic_instr *instr)
2485 {
2486 LLVMValueRef params[6];
2487 int param_count = 0;
2488 const nir_variable *var = instr->variables[0]->var;
2489 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2490 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2491 const char *base_name = "llvm.amdgcn.image.atomic";
2492 const char *atomic_name;
2493 LLVMValueRef coords;
2494 char intrinsic_name[32], coords_type[8];
2495 const struct glsl_type *type = glsl_without_array(var->type);
2496
2497 if (ctx->stage == MESA_SHADER_FRAGMENT)
2498 ctx->shader_info->fs.writes_memory = true;
2499
2500 params[param_count++] = get_src(ctx, instr->src[2]);
2501 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2502 params[param_count++] = get_src(ctx, instr->src[3]);
2503
2504 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2505 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2506 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2507 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2508 params[param_count++] = ctx->i32zero; /* voffset */
2509 params[param_count++] = i1false; /* glc */
2510 params[param_count++] = i1false; /* slc */
2511 } else {
2512 bool da = glsl_sampler_type_is_array(type) ||
2513 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2514
2515 coords = params[param_count++] = get_image_coords(ctx, instr);
2516 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2517 params[param_count++] = i1false; /* r128 */
2518 params[param_count++] = da ? i1true : i1false; /* da */
2519 params[param_count++] = i1false; /* slc */
2520 }
2521
2522 switch (instr->intrinsic) {
2523 case nir_intrinsic_image_atomic_add:
2524 atomic_name = "add";
2525 break;
2526 case nir_intrinsic_image_atomic_min:
2527 atomic_name = "smin";
2528 break;
2529 case nir_intrinsic_image_atomic_max:
2530 atomic_name = "smax";
2531 break;
2532 case nir_intrinsic_image_atomic_and:
2533 atomic_name = "and";
2534 break;
2535 case nir_intrinsic_image_atomic_or:
2536 atomic_name = "or";
2537 break;
2538 case nir_intrinsic_image_atomic_xor:
2539 atomic_name = "xor";
2540 break;
2541 case nir_intrinsic_image_atomic_exchange:
2542 atomic_name = "swap";
2543 break;
2544 case nir_intrinsic_image_atomic_comp_swap:
2545 atomic_name = "cmpswap";
2546 break;
2547 default:
2548 abort();
2549 }
2550 build_int_type_name(LLVMTypeOf(coords),
2551 coords_type, sizeof(coords_type));
2552
2553 snprintf(intrinsic_name, sizeof(intrinsic_name),
2554 "%s.%s.%s", base_name, atomic_name, coords_type);
2555 return ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2556 }
2557
2558 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2559 nir_intrinsic_instr *instr)
2560 {
2561 LLVMValueRef res;
2562 LLVMValueRef params[10];
2563 const nir_variable *var = instr->variables[0]->var;
2564 const struct glsl_type *type = instr->variables[0]->var->type;
2565 bool da = glsl_sampler_type_is_array(var->type) ||
2566 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2567 if(instr->variables[0]->deref.child)
2568 type = instr->variables[0]->deref.child->type;
2569
2570 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2571 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2572 params[0] = ctx->i32zero;
2573 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2574 params[2] = LLVMConstInt(ctx->i32, 15, false);
2575 params[3] = ctx->i32zero;
2576 params[4] = ctx->i32zero;
2577 params[5] = da ? ctx->i32one : ctx->i32zero;
2578 params[6] = ctx->i32zero;
2579 params[7] = ctx->i32zero;
2580 params[8] = ctx->i32zero;
2581 params[9] = ctx->i32zero;
2582
2583 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
2584 params, 10, AC_FUNC_ATTR_READNONE);
2585
2586 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2587 glsl_sampler_type_is_array(type)) {
2588 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2589 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2590 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2591 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2592 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2593 }
2594 return res;
2595 }
2596
2597 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2598 {
2599 LLVMValueRef args[1] = {
2600 LLVMConstInt(ctx->i32, 0xf70, false),
2601 };
2602 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2603 ctx->voidt, args, 1, 0);
2604 }
2605
2606 static void emit_barrier(struct nir_to_llvm_context *ctx)
2607 {
2608 // TODO tess
2609 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2610 ctx->voidt, NULL, 0, 0);
2611 }
2612
2613 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2614 nir_intrinsic_instr *instr)
2615 {
2616 LLVMValueRef cond;
2617 ctx->shader_info->fs.can_discard = true;
2618
2619 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2620 get_src(ctx, instr->src[0]),
2621 ctx->i32zero, "");
2622
2623 cond = LLVMBuildSelect(ctx->builder, cond,
2624 LLVMConstReal(ctx->f32, -1.0f),
2625 ctx->f32zero, "");
2626 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
2627 ctx->voidt,
2628 &cond, 1, 0);
2629 }
2630
2631 static LLVMValueRef
2632 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2633 {
2634 LLVMValueRef result;
2635 LLVMValueRef thread_id = get_thread_id(ctx);
2636 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2637 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2638
2639 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2640 }
2641
2642 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2643 nir_intrinsic_instr *instr)
2644 {
2645 LLVMValueRef ptr, result;
2646 int idx = instr->variables[0]->var->data.driver_location;
2647 LLVMValueRef src = get_src(ctx, instr->src[0]);
2648 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2649
2650 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2651 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2652 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2653 ptr, src, src1,
2654 LLVMAtomicOrderingSequentiallyConsistent,
2655 LLVMAtomicOrderingSequentiallyConsistent,
2656 false);
2657 } else {
2658 LLVMAtomicRMWBinOp op;
2659 switch (instr->intrinsic) {
2660 case nir_intrinsic_var_atomic_add:
2661 op = LLVMAtomicRMWBinOpAdd;
2662 break;
2663 case nir_intrinsic_var_atomic_umin:
2664 op = LLVMAtomicRMWBinOpUMin;
2665 break;
2666 case nir_intrinsic_var_atomic_umax:
2667 op = LLVMAtomicRMWBinOpUMax;
2668 break;
2669 case nir_intrinsic_var_atomic_imin:
2670 op = LLVMAtomicRMWBinOpMin;
2671 break;
2672 case nir_intrinsic_var_atomic_imax:
2673 op = LLVMAtomicRMWBinOpMax;
2674 break;
2675 case nir_intrinsic_var_atomic_and:
2676 op = LLVMAtomicRMWBinOpAnd;
2677 break;
2678 case nir_intrinsic_var_atomic_or:
2679 op = LLVMAtomicRMWBinOpOr;
2680 break;
2681 case nir_intrinsic_var_atomic_xor:
2682 op = LLVMAtomicRMWBinOpXor;
2683 break;
2684 case nir_intrinsic_var_atomic_exchange:
2685 op = LLVMAtomicRMWBinOpXchg;
2686 break;
2687 default:
2688 return NULL;
2689 }
2690
2691 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2692 LLVMAtomicOrderingSequentiallyConsistent,
2693 false);
2694 }
2695 return result;
2696 }
2697
2698 #define INTERP_CENTER 0
2699 #define INTERP_CENTROID 1
2700 #define INTERP_SAMPLE 2
2701
2702 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2703 enum glsl_interp_mode interp, unsigned location)
2704 {
2705 switch (interp) {
2706 case INTERP_MODE_FLAT:
2707 default:
2708 return NULL;
2709 case INTERP_MODE_SMOOTH:
2710 case INTERP_MODE_NONE:
2711 if (location == INTERP_CENTER)
2712 return ctx->persp_center;
2713 else if (location == INTERP_CENTROID)
2714 return ctx->persp_centroid;
2715 else if (location == INTERP_SAMPLE)
2716 return ctx->persp_sample;
2717 break;
2718 case INTERP_MODE_NOPERSPECTIVE:
2719 if (location == INTERP_CENTER)
2720 return ctx->linear_center;
2721 else if (location == INTERP_CENTROID)
2722 return ctx->linear_centroid;
2723 else if (location == INTERP_SAMPLE)
2724 return ctx->linear_sample;
2725 break;
2726 }
2727 return NULL;
2728 }
2729
2730 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
2731 LLVMValueRef sample_id)
2732 {
2733 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2734 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
2735 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
2736 LLVMValueRef result[2];
2737
2738 result[0] = build_indexed_load_const(ctx, ctx->sample_positions, offset0);
2739 result[1] = build_indexed_load_const(ctx, ctx->sample_positions, offset1);
2740
2741 return ac_build_gather_values(&ctx->ac, result, 2);
2742 }
2743
2744 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
2745 {
2746 LLVMValueRef values[2];
2747
2748 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
2749 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
2750 return ac_build_gather_values(&ctx->ac, values, 2);
2751 }
2752
2753 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
2754 nir_intrinsic_instr *instr)
2755 {
2756 LLVMValueRef result[2];
2757 LLVMValueRef interp_param, attr_number;
2758 unsigned location;
2759 unsigned chan;
2760 LLVMValueRef src_c0, src_c1;
2761 const char *intr_name;
2762 LLVMValueRef src0;
2763 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
2764 switch (instr->intrinsic) {
2765 case nir_intrinsic_interp_var_at_centroid:
2766 location = INTERP_CENTROID;
2767 break;
2768 case nir_intrinsic_interp_var_at_sample:
2769 case nir_intrinsic_interp_var_at_offset:
2770 location = INTERP_SAMPLE;
2771 src0 = get_src(ctx, instr->src[0]);
2772 break;
2773 default:
2774 break;
2775 }
2776
2777 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
2778 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
2779 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
2780 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
2781 LLVMValueRef sample_position;
2782 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
2783
2784 /* fetch sample ID */
2785 sample_position = load_sample_position(ctx, src0);
2786
2787 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
2788 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
2789 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
2790 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
2791 }
2792 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
2793 attr_number = LLVMConstInt(ctx->i32, input_index, false);
2794
2795 if (location == INTERP_SAMPLE) {
2796 LLVMValueRef ij_out[2];
2797 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
2798
2799 /*
2800 * take the I then J parameters, and the DDX/Y for it, and
2801 * calculate the IJ inputs for the interpolator.
2802 * temp1 = ddx * offset/sample.x + I;
2803 * interp_param.I = ddy * offset/sample.y + temp1;
2804 * temp1 = ddx * offset/sample.x + J;
2805 * interp_param.J = ddy * offset/sample.y + temp1;
2806 */
2807 for (unsigned i = 0; i < 2; i++) {
2808 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
2809 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
2810 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
2811 ddxy_out, ix_ll, "");
2812 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
2813 ddxy_out, iy_ll, "");
2814 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
2815 interp_param, ix_ll, "");
2816 LLVMValueRef temp1, temp2;
2817
2818 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
2819 ctx->f32, "");
2820
2821 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
2822 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
2823
2824 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
2825 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
2826
2827 ij_out[i] = LLVMBuildBitCast(ctx->builder,
2828 temp2, ctx->i32, "");
2829 }
2830 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
2831
2832 }
2833 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
2834 for (chan = 0; chan < 2; chan++) {
2835 LLVMValueRef args[4];
2836 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
2837
2838 args[0] = llvm_chan;
2839 args[1] = attr_number;
2840 args[2] = ctx->prim_mask;
2841 args[3] = interp_param;
2842 result[chan] = ac_emit_llvm_intrinsic(&ctx->ac, intr_name,
2843 ctx->f32, args, args[3] ? 4 : 3,
2844 AC_FUNC_ATTR_READNONE);
2845 }
2846 return ac_build_gather_values(&ctx->ac, result, 2);
2847 }
2848
2849 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
2850 nir_intrinsic_instr *instr)
2851 {
2852 LLVMValueRef result = NULL;
2853
2854 switch (instr->intrinsic) {
2855 case nir_intrinsic_load_work_group_id: {
2856 result = ctx->workgroup_ids;
2857 break;
2858 }
2859 case nir_intrinsic_load_base_vertex: {
2860 result = ctx->base_vertex;
2861 break;
2862 }
2863 case nir_intrinsic_load_vertex_id_zero_base: {
2864 result = ctx->vertex_id;
2865 break;
2866 }
2867 case nir_intrinsic_load_local_invocation_id: {
2868 result = ctx->local_invocation_ids;
2869 break;
2870 }
2871 case nir_intrinsic_load_base_instance:
2872 result = ctx->start_instance;
2873 break;
2874 case nir_intrinsic_load_sample_id:
2875 ctx->shader_info->fs.force_persample = true;
2876 result = unpack_param(ctx, ctx->ancillary, 8, 4);
2877 break;
2878 case nir_intrinsic_load_sample_pos:
2879 ctx->shader_info->fs.force_persample = true;
2880 result = load_sample_pos(ctx);
2881 break;
2882 case nir_intrinsic_load_front_face:
2883 result = ctx->front_face;
2884 break;
2885 case nir_intrinsic_load_instance_id:
2886 result = ctx->instance_id;
2887 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
2888 ctx->shader_info->vs.vgpr_comp_cnt);
2889 break;
2890 case nir_intrinsic_load_num_work_groups:
2891 result = ctx->num_work_groups;
2892 break;
2893 case nir_intrinsic_load_local_invocation_index:
2894 result = visit_load_local_invocation_index(ctx);
2895 break;
2896 case nir_intrinsic_load_push_constant:
2897 result = visit_load_push_constant(ctx, instr);
2898 break;
2899 case nir_intrinsic_vulkan_resource_index:
2900 result = visit_vulkan_resource_index(ctx, instr);
2901 break;
2902 case nir_intrinsic_store_ssbo:
2903 visit_store_ssbo(ctx, instr);
2904 break;
2905 case nir_intrinsic_load_ssbo:
2906 result = visit_load_buffer(ctx, instr);
2907 break;
2908 case nir_intrinsic_ssbo_atomic_add:
2909 case nir_intrinsic_ssbo_atomic_imin:
2910 case nir_intrinsic_ssbo_atomic_umin:
2911 case nir_intrinsic_ssbo_atomic_imax:
2912 case nir_intrinsic_ssbo_atomic_umax:
2913 case nir_intrinsic_ssbo_atomic_and:
2914 case nir_intrinsic_ssbo_atomic_or:
2915 case nir_intrinsic_ssbo_atomic_xor:
2916 case nir_intrinsic_ssbo_atomic_exchange:
2917 case nir_intrinsic_ssbo_atomic_comp_swap:
2918 result = visit_atomic_ssbo(ctx, instr);
2919 break;
2920 case nir_intrinsic_load_ubo:
2921 result = visit_load_ubo_buffer(ctx, instr);
2922 break;
2923 case nir_intrinsic_get_buffer_size:
2924 result = visit_get_buffer_size(ctx, instr);
2925 break;
2926 case nir_intrinsic_load_var:
2927 result = visit_load_var(ctx, instr);
2928 break;
2929 case nir_intrinsic_store_var:
2930 visit_store_var(ctx, instr);
2931 break;
2932 case nir_intrinsic_image_load:
2933 result = visit_image_load(ctx, instr);
2934 break;
2935 case nir_intrinsic_image_store:
2936 visit_image_store(ctx, instr);
2937 break;
2938 case nir_intrinsic_image_atomic_add:
2939 case nir_intrinsic_image_atomic_min:
2940 case nir_intrinsic_image_atomic_max:
2941 case nir_intrinsic_image_atomic_and:
2942 case nir_intrinsic_image_atomic_or:
2943 case nir_intrinsic_image_atomic_xor:
2944 case nir_intrinsic_image_atomic_exchange:
2945 case nir_intrinsic_image_atomic_comp_swap:
2946 result = visit_image_atomic(ctx, instr);
2947 break;
2948 case nir_intrinsic_image_size:
2949 result = visit_image_size(ctx, instr);
2950 break;
2951 case nir_intrinsic_discard:
2952 ctx->shader_info->fs.can_discard = true;
2953 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
2954 ctx->voidt,
2955 NULL, 0, 0);
2956 break;
2957 case nir_intrinsic_discard_if:
2958 emit_discard_if(ctx, instr);
2959 break;
2960 case nir_intrinsic_memory_barrier:
2961 emit_waitcnt(ctx);
2962 break;
2963 case nir_intrinsic_barrier:
2964 emit_barrier(ctx);
2965 break;
2966 case nir_intrinsic_var_atomic_add:
2967 case nir_intrinsic_var_atomic_imin:
2968 case nir_intrinsic_var_atomic_umin:
2969 case nir_intrinsic_var_atomic_imax:
2970 case nir_intrinsic_var_atomic_umax:
2971 case nir_intrinsic_var_atomic_and:
2972 case nir_intrinsic_var_atomic_or:
2973 case nir_intrinsic_var_atomic_xor:
2974 case nir_intrinsic_var_atomic_exchange:
2975 case nir_intrinsic_var_atomic_comp_swap:
2976 result = visit_var_atomic(ctx, instr);
2977 break;
2978 case nir_intrinsic_interp_var_at_centroid:
2979 case nir_intrinsic_interp_var_at_sample:
2980 case nir_intrinsic_interp_var_at_offset:
2981 result = visit_interp(ctx, instr);
2982 break;
2983 default:
2984 fprintf(stderr, "Unknown intrinsic: ");
2985 nir_print_instr(&instr->instr, stderr);
2986 fprintf(stderr, "\n");
2987 break;
2988 }
2989 if (result) {
2990 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
2991 }
2992 }
2993
2994 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
2995 nir_deref_var *deref,
2996 enum desc_type desc_type)
2997 {
2998 unsigned desc_set = deref->var->data.descriptor_set;
2999 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3000 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3001 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3002 unsigned offset = binding->offset;
3003 unsigned stride = binding->size;
3004 unsigned type_size;
3005 LLVMBuilderRef builder = ctx->builder;
3006 LLVMTypeRef type;
3007 LLVMValueRef index = NULL;
3008
3009 assert(deref->var->data.binding < layout->binding_count);
3010
3011 switch (desc_type) {
3012 case DESC_IMAGE:
3013 type = ctx->v8i32;
3014 type_size = 32;
3015 break;
3016 case DESC_FMASK:
3017 type = ctx->v8i32;
3018 offset += 32;
3019 type_size = 32;
3020 break;
3021 case DESC_SAMPLER:
3022 type = ctx->v4i32;
3023 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3024 offset += 64;
3025
3026 type_size = 16;
3027 break;
3028 case DESC_BUFFER:
3029 type = ctx->v4i32;
3030 type_size = 16;
3031 break;
3032 default:
3033 unreachable("invalid desc_type\n");
3034 }
3035
3036 if (deref->deref.child) {
3037 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3038
3039 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3040 offset += child->base_offset * stride;
3041 if (child->deref_array_type == nir_deref_array_type_indirect) {
3042 index = get_src(ctx, child->indirect);
3043 }
3044 }
3045
3046 assert(stride % type_size == 0);
3047
3048 if (!index)
3049 index = ctx->i32zero;
3050
3051 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3052
3053 list = build_gep0(ctx, list, LLVMConstInt(ctx->i32, offset, 0));
3054 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3055
3056 return build_indexed_load_const(ctx, list, index);
3057 }
3058
3059 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3060 struct ac_tex_info *tinfo,
3061 nir_tex_instr *instr,
3062 nir_texop op,
3063 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3064 LLVMValueRef *param, unsigned count,
3065 unsigned dmask)
3066 {
3067 int num_args;
3068 unsigned is_rect = 0;
3069 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3070
3071 if (op == nir_texop_lod)
3072 da = false;
3073 /* Pad to power of two vector */
3074 while (count < util_next_power_of_two(count))
3075 param[count++] = LLVMGetUndef(ctx->i32);
3076
3077 if (count > 1)
3078 tinfo->args[0] = ac_build_gather_values(&ctx->ac, param, count);
3079 else
3080 tinfo->args[0] = param[0];
3081
3082 tinfo->args[1] = res_ptr;
3083 num_args = 2;
3084
3085 if (op == nir_texop_txf ||
3086 op == nir_texop_txf_ms ||
3087 op == nir_texop_query_levels ||
3088 op == nir_texop_texture_samples ||
3089 op == nir_texop_txs)
3090 tinfo->dst_type = ctx->v4i32;
3091 else {
3092 tinfo->dst_type = ctx->v4f32;
3093 tinfo->args[num_args++] = samp_ptr;
3094 }
3095
3096 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3097 tinfo->args[0] = res_ptr;
3098 tinfo->args[1] = LLVMConstInt(ctx->i32, 0, false);
3099 tinfo->args[2] = param[0];
3100 tinfo->arg_count = 3;
3101 return;
3102 }
3103
3104 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, dmask, 0);
3105 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, is_rect, 0); /* unorm */
3106 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
3107 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
3108 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
3109 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
3110 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
3111 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
3112
3113 tinfo->arg_count = num_args;
3114 }
3115
3116 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3117 *
3118 * SI-CI:
3119 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3120 * filtering manually. The driver sets img7 to a mask clearing
3121 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3122 * s_and_b32 samp0, samp0, img7
3123 *
3124 * VI:
3125 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3126 */
3127 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3128 LLVMValueRef res, LLVMValueRef samp)
3129 {
3130 LLVMBuilderRef builder = ctx->builder;
3131 LLVMValueRef img7, samp0;
3132
3133 if (ctx->options->chip_class >= VI)
3134 return samp;
3135
3136 img7 = LLVMBuildExtractElement(builder, res,
3137 LLVMConstInt(ctx->i32, 7, 0), "");
3138 samp0 = LLVMBuildExtractElement(builder, samp,
3139 LLVMConstInt(ctx->i32, 0, 0), "");
3140 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3141 return LLVMBuildInsertElement(builder, samp, samp0,
3142 LLVMConstInt(ctx->i32, 0, 0), "");
3143 }
3144
3145 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3146 nir_tex_instr *instr,
3147 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3148 LLVMValueRef *fmask_ptr)
3149 {
3150 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3151 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3152 else
3153 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3154 if (samp_ptr) {
3155 if (instr->sampler)
3156 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3157 else
3158 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3159 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3160 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3161 }
3162 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3163 instr->op == nir_texop_samples_identical))
3164 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3165 }
3166
3167 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3168 {
3169 LLVMValueRef result = NULL;
3170 struct ac_tex_info tinfo = { 0 };
3171 unsigned dmask = 0xf;
3172 LLVMValueRef address[16];
3173 LLVMValueRef coords[5];
3174 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3175 LLVMValueRef bias = NULL, offsets = NULL;
3176 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3177 LLVMValueRef ddx = NULL, ddy = NULL;
3178 LLVMValueRef derivs[6];
3179 unsigned chan, count = 0;
3180 unsigned const_src = 0, num_deriv_comp = 0;
3181
3182 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3183
3184 for (unsigned i = 0; i < instr->num_srcs; i++) {
3185 switch (instr->src[i].src_type) {
3186 case nir_tex_src_coord:
3187 coord = get_src(ctx, instr->src[i].src);
3188 break;
3189 case nir_tex_src_projector:
3190 break;
3191 case nir_tex_src_comparator:
3192 comparator = get_src(ctx, instr->src[i].src);
3193 break;
3194 case nir_tex_src_offset:
3195 offsets = get_src(ctx, instr->src[i].src);
3196 const_src = i;
3197 break;
3198 case nir_tex_src_bias:
3199 bias = get_src(ctx, instr->src[i].src);
3200 break;
3201 case nir_tex_src_lod:
3202 lod = get_src(ctx, instr->src[i].src);
3203 break;
3204 case nir_tex_src_ms_index:
3205 sample_index = get_src(ctx, instr->src[i].src);
3206 break;
3207 case nir_tex_src_ms_mcs:
3208 break;
3209 case nir_tex_src_ddx:
3210 ddx = get_src(ctx, instr->src[i].src);
3211 num_deriv_comp = instr->src[i].src.ssa->num_components;
3212 break;
3213 case nir_tex_src_ddy:
3214 ddy = get_src(ctx, instr->src[i].src);
3215 break;
3216 case nir_tex_src_texture_offset:
3217 case nir_tex_src_sampler_offset:
3218 case nir_tex_src_plane:
3219 default:
3220 break;
3221 }
3222 }
3223
3224 if (instr->op == nir_texop_texture_samples) {
3225 LLVMValueRef res, samples, is_msaa;
3226 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3227 samples = LLVMBuildExtractElement(ctx->builder, res,
3228 LLVMConstInt(ctx->i32, 3, false), "");
3229 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3230 LLVMConstInt(ctx->i32, 28, false), "");
3231 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3232 LLVMConstInt(ctx->i32, 0xe, false), "");
3233 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3234 LLVMConstInt(ctx->i32, 0xe, false), "");
3235
3236 samples = LLVMBuildLShr(ctx->builder, samples,
3237 LLVMConstInt(ctx->i32, 16, false), "");
3238 samples = LLVMBuildAnd(ctx->builder, samples,
3239 LLVMConstInt(ctx->i32, 0xf, false), "");
3240 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3241 samples, "");
3242 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3243 ctx->i32one, "");
3244 result = samples;
3245 goto write_result;
3246 }
3247
3248 if (coord)
3249 for (chan = 0; chan < instr->coord_components; chan++)
3250 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3251
3252 if (offsets && instr->op != nir_texop_txf) {
3253 LLVMValueRef offset[3], pack;
3254 for (chan = 0; chan < 3; ++chan)
3255 offset[chan] = ctx->i32zero;
3256
3257 tinfo.has_offset = true;
3258 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3259 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3260 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3261 LLVMConstInt(ctx->i32, 0x3f, false), "");
3262 if (chan)
3263 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3264 LLVMConstInt(ctx->i32, chan * 8, false), "");
3265 }
3266 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3267 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3268 address[count++] = pack;
3269
3270 }
3271 /* pack LOD bias value */
3272 if (instr->op == nir_texop_txb && bias) {
3273 address[count++] = bias;
3274 }
3275
3276 /* Pack depth comparison value */
3277 if (instr->is_shadow && comparator) {
3278 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3279 }
3280
3281 /* pack derivatives */
3282 if (ddx || ddy) {
3283 switch (instr->sampler_dim) {
3284 case GLSL_SAMPLER_DIM_3D:
3285 case GLSL_SAMPLER_DIM_CUBE:
3286 num_deriv_comp = 3;
3287 break;
3288 case GLSL_SAMPLER_DIM_2D:
3289 default:
3290 num_deriv_comp = 2;
3291 break;
3292 case GLSL_SAMPLER_DIM_1D:
3293 num_deriv_comp = 1;
3294 break;
3295 }
3296
3297 for (unsigned i = 0; i < num_deriv_comp; i++) {
3298 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3299 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3300 }
3301 }
3302
3303 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3304 for (chan = 0; chan < instr->coord_components; chan++)
3305 coords[chan] = to_float(ctx, coords[chan]);
3306 if (instr->coord_components == 3)
3307 coords[3] = LLVMGetUndef(ctx->f32);
3308 ac_prepare_cube_coords(&ctx->ac,
3309 instr->op == nir_texop_txd, instr->is_array,
3310 coords, derivs);
3311 if (num_deriv_comp)
3312 num_deriv_comp--;
3313 }
3314
3315 if (ddx || ddy) {
3316 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3317 address[count++] = derivs[i];
3318 }
3319
3320 /* Pack texture coordinates */
3321 if (coord) {
3322 address[count++] = coords[0];
3323 if (instr->coord_components > 1)
3324 address[count++] = coords[1];
3325 if (instr->coord_components > 2) {
3326 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3327 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3328 coords[2] = to_float(ctx, coords[2]);
3329 coords[2] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coords[2],
3330 1, 0);
3331 coords[2] = to_integer(ctx, coords[2]);
3332 }
3333 address[count++] = coords[2];
3334 }
3335 }
3336
3337 /* Pack LOD */
3338 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3339 address[count++] = lod;
3340 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3341 address[count++] = sample_index;
3342 } else if(instr->op == nir_texop_txs) {
3343 count = 0;
3344 if (lod)
3345 address[count++] = lod;
3346 else
3347 address[count++] = ctx->i32zero;
3348 }
3349
3350 for (chan = 0; chan < count; chan++) {
3351 address[chan] = LLVMBuildBitCast(ctx->builder,
3352 address[chan], ctx->i32, "");
3353 }
3354
3355 if (instr->op == nir_texop_samples_identical) {
3356 LLVMValueRef txf_address[4];
3357 struct ac_tex_info txf_info = { 0 };
3358 unsigned txf_count = count;
3359 memcpy(txf_address, address, sizeof(txf_address));
3360
3361 if (!instr->is_array)
3362 txf_address[2] = ctx->i32zero;
3363 txf_address[3] = ctx->i32zero;
3364
3365 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3366 fmask_ptr, NULL,
3367 txf_address, txf_count, 0xf);
3368
3369 result = build_tex_intrinsic(ctx, instr, &txf_info);
3370
3371 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3372 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3373 goto write_result;
3374 }
3375
3376 /* Adjust the sample index according to FMASK.
3377 *
3378 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3379 * which is the identity mapping. Each nibble says which physical sample
3380 * should be fetched to get that sample.
3381 *
3382 * For example, 0x11111100 means there are only 2 samples stored and
3383 * the second sample covers 3/4 of the pixel. When reading samples 0
3384 * and 1, return physical sample 0 (determined by the first two 0s
3385 * in FMASK), otherwise return physical sample 1.
3386 *
3387 * The sample index should be adjusted as follows:
3388 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3389 */
3390 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS) {
3391 LLVMValueRef txf_address[4];
3392 struct ac_tex_info txf_info = { 0 };
3393 unsigned txf_count = count;
3394 memcpy(txf_address, address, sizeof(txf_address));
3395
3396 if (!instr->is_array)
3397 txf_address[2] = ctx->i32zero;
3398 txf_address[3] = ctx->i32zero;
3399
3400 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3401 fmask_ptr, NULL,
3402 txf_address, txf_count, 0xf);
3403
3404 result = build_tex_intrinsic(ctx, instr, &txf_info);
3405 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3406 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3407
3408 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3409 result,
3410 ctx->i32zero, "");
3411
3412 unsigned sample_chan = instr->is_array ? 3 : 2;
3413
3414 LLVMValueRef sample_index4 =
3415 LLVMBuildMul(ctx->builder, address[sample_chan], four, "");
3416 LLVMValueRef shifted_fmask =
3417 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3418 LLVMValueRef final_sample =
3419 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3420
3421 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3422 * resource descriptor is 0 (invalid),
3423 */
3424 LLVMValueRef fmask_desc =
3425 LLVMBuildBitCast(ctx->builder, fmask_ptr,
3426 ctx->v8i32, "");
3427
3428 LLVMValueRef fmask_word1 =
3429 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3430 ctx->i32one, "");
3431
3432 LLVMValueRef word1_is_nonzero =
3433 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3434 fmask_word1, ctx->i32zero, "");
3435
3436 /* Replace the MSAA sample index. */
3437 address[sample_chan] =
3438 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3439 final_sample, address[sample_chan], "");
3440 }
3441
3442 if (offsets && instr->op == nir_texop_txf) {
3443 nir_const_value *const_offset =
3444 nir_src_as_const_value(instr->src[const_src].src);
3445 int num_offsets = instr->src[const_src].src.ssa->num_components;
3446 assert(const_offset);
3447 num_offsets = MIN2(num_offsets, instr->coord_components);
3448 if (num_offsets > 2)
3449 address[2] = LLVMBuildAdd(ctx->builder,
3450 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3451 if (num_offsets > 1)
3452 address[1] = LLVMBuildAdd(ctx->builder,
3453 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3454 address[0] = LLVMBuildAdd(ctx->builder,
3455 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3456
3457 }
3458
3459 /* TODO TG4 support */
3460 if (instr->op == nir_texop_tg4) {
3461 if (instr->is_shadow)
3462 dmask = 1;
3463 else
3464 dmask = 1 << instr->component;
3465 }
3466 set_tex_fetch_args(ctx, &tinfo, instr, instr->op,
3467 res_ptr, samp_ptr, address, count, dmask);
3468
3469 result = build_tex_intrinsic(ctx, instr, &tinfo);
3470
3471 if (instr->op == nir_texop_query_levels)
3472 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3473 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3474 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3475 else if (instr->op == nir_texop_txs &&
3476 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3477 instr->is_array) {
3478 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3479 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3480 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3481 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3482 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3483 } else if (instr->dest.ssa.num_components != 4)
3484 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3485
3486 write_result:
3487 if (result) {
3488 assert(instr->dest.is_ssa);
3489 result = to_integer(ctx, result);
3490 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3491 }
3492 }
3493
3494
3495 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3496 {
3497 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3498 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3499
3500 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3501 _mesa_hash_table_insert(ctx->phis, instr, result);
3502 }
3503
3504 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3505 nir_phi_instr *instr,
3506 LLVMValueRef llvm_phi)
3507 {
3508 nir_foreach_phi_src(src, instr) {
3509 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3510 LLVMValueRef llvm_src = get_src(ctx, src->src);
3511
3512 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3513 }
3514 }
3515
3516 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3517 {
3518 struct hash_entry *entry;
3519 hash_table_foreach(ctx->phis, entry) {
3520 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3521 (LLVMValueRef)entry->data);
3522 }
3523 }
3524
3525
3526 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3527 nir_ssa_undef_instr *instr)
3528 {
3529 unsigned num_components = instr->def.num_components;
3530 LLVMValueRef undef;
3531
3532 if (num_components == 1)
3533 undef = LLVMGetUndef(ctx->i32);
3534 else {
3535 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3536 }
3537 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3538 }
3539
3540 static void visit_jump(struct nir_to_llvm_context *ctx,
3541 nir_jump_instr *instr)
3542 {
3543 switch (instr->type) {
3544 case nir_jump_break:
3545 LLVMBuildBr(ctx->builder, ctx->break_block);
3546 LLVMClearInsertionPosition(ctx->builder);
3547 break;
3548 case nir_jump_continue:
3549 LLVMBuildBr(ctx->builder, ctx->continue_block);
3550 LLVMClearInsertionPosition(ctx->builder);
3551 break;
3552 default:
3553 fprintf(stderr, "Unknown NIR jump instr: ");
3554 nir_print_instr(&instr->instr, stderr);
3555 fprintf(stderr, "\n");
3556 abort();
3557 }
3558 }
3559
3560 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3561 struct exec_list *list);
3562
3563 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3564 {
3565 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3566 nir_foreach_instr(instr, block)
3567 {
3568 switch (instr->type) {
3569 case nir_instr_type_alu:
3570 visit_alu(ctx, nir_instr_as_alu(instr));
3571 break;
3572 case nir_instr_type_load_const:
3573 visit_load_const(ctx, nir_instr_as_load_const(instr));
3574 break;
3575 case nir_instr_type_intrinsic:
3576 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3577 break;
3578 case nir_instr_type_tex:
3579 visit_tex(ctx, nir_instr_as_tex(instr));
3580 break;
3581 case nir_instr_type_phi:
3582 visit_phi(ctx, nir_instr_as_phi(instr));
3583 break;
3584 case nir_instr_type_ssa_undef:
3585 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3586 break;
3587 case nir_instr_type_jump:
3588 visit_jump(ctx, nir_instr_as_jump(instr));
3589 break;
3590 default:
3591 fprintf(stderr, "Unknown NIR instr type: ");
3592 nir_print_instr(instr, stderr);
3593 fprintf(stderr, "\n");
3594 abort();
3595 }
3596 }
3597
3598 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3599 }
3600
3601 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3602 {
3603 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3604
3605 LLVMBasicBlockRef merge_block =
3606 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3607 LLVMBasicBlockRef if_block =
3608 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3609 LLVMBasicBlockRef else_block = merge_block;
3610 if (!exec_list_is_empty(&if_stmt->else_list))
3611 else_block = LLVMAppendBasicBlockInContext(
3612 ctx->context, ctx->main_function, "");
3613
3614 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3615 LLVMConstInt(ctx->i32, 0, false), "");
3616 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3617
3618 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3619 visit_cf_list(ctx, &if_stmt->then_list);
3620 if (LLVMGetInsertBlock(ctx->builder))
3621 LLVMBuildBr(ctx->builder, merge_block);
3622
3623 if (!exec_list_is_empty(&if_stmt->else_list)) {
3624 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3625 visit_cf_list(ctx, &if_stmt->else_list);
3626 if (LLVMGetInsertBlock(ctx->builder))
3627 LLVMBuildBr(ctx->builder, merge_block);
3628 }
3629
3630 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3631 }
3632
3633 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3634 {
3635 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3636 LLVMBasicBlockRef break_parent = ctx->break_block;
3637
3638 ctx->continue_block =
3639 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3640 ctx->break_block =
3641 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3642
3643 LLVMBuildBr(ctx->builder, ctx->continue_block);
3644 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
3645 visit_cf_list(ctx, &loop->body);
3646
3647 if (LLVMGetInsertBlock(ctx->builder))
3648 LLVMBuildBr(ctx->builder, ctx->continue_block);
3649 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
3650
3651 ctx->continue_block = continue_parent;
3652 ctx->break_block = break_parent;
3653 }
3654
3655 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3656 struct exec_list *list)
3657 {
3658 foreach_list_typed(nir_cf_node, node, node, list)
3659 {
3660 switch (node->type) {
3661 case nir_cf_node_block:
3662 visit_block(ctx, nir_cf_node_as_block(node));
3663 break;
3664
3665 case nir_cf_node_if:
3666 visit_if(ctx, nir_cf_node_as_if(node));
3667 break;
3668
3669 case nir_cf_node_loop:
3670 visit_loop(ctx, nir_cf_node_as_loop(node));
3671 break;
3672
3673 default:
3674 assert(0);
3675 }
3676 }
3677 }
3678
3679 static void
3680 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
3681 struct nir_variable *variable)
3682 {
3683 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
3684 LLVMValueRef t_offset;
3685 LLVMValueRef t_list;
3686 LLVMValueRef args[3];
3687 LLVMValueRef input;
3688 LLVMValueRef buffer_index;
3689 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
3690 int idx = variable->data.location;
3691 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
3692
3693 variable->data.driver_location = idx * 4;
3694
3695 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
3696 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
3697 ctx->start_instance, "");
3698 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3699 ctx->shader_info->vs.vgpr_comp_cnt);
3700 } else
3701 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
3702 ctx->base_vertex, "");
3703
3704 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
3705 t_offset = LLVMConstInt(ctx->i32, index + i, false);
3706
3707 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
3708 args[0] = t_list;
3709 args[1] = LLVMConstInt(ctx->i32, 0, false);
3710 args[2] = buffer_index;
3711 input = ac_emit_llvm_intrinsic(&ctx->ac,
3712 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
3713 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
3714
3715 for (unsigned chan = 0; chan < 4; chan++) {
3716 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3717 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
3718 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
3719 input, llvm_chan, ""));
3720 }
3721 }
3722 }
3723
3724
3725 static void interp_fs_input(struct nir_to_llvm_context *ctx,
3726 unsigned attr,
3727 LLVMValueRef interp_param,
3728 LLVMValueRef prim_mask,
3729 LLVMValueRef result[4])
3730 {
3731 const char *intr_name;
3732 LLVMValueRef attr_number;
3733 unsigned chan;
3734
3735 attr_number = LLVMConstInt(ctx->i32, attr, false);
3736
3737 /* fs.constant returns the param from the middle vertex, so it's not
3738 * really useful for flat shading. It's meant to be used for custom
3739 * interpolation (but the intrinsic can't fetch from the other two
3740 * vertices).
3741 *
3742 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
3743 * to do the right thing. The only reason we use fs.constant is that
3744 * fs.interp cannot be used on integers, because they can be equal
3745 * to NaN.
3746 */
3747 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3748
3749 for (chan = 0; chan < 4; chan++) {
3750 LLVMValueRef args[4];
3751 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3752
3753 args[0] = llvm_chan;
3754 args[1] = attr_number;
3755 args[2] = prim_mask;
3756 args[3] = interp_param;
3757 result[chan] = ac_emit_llvm_intrinsic(&ctx->ac, intr_name,
3758 ctx->f32, args, args[3] ? 4 : 3,
3759 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
3760 }
3761 }
3762
3763 static void
3764 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
3765 struct nir_variable *variable)
3766 {
3767 int idx = variable->data.location;
3768 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
3769 LLVMValueRef interp;
3770
3771 variable->data.driver_location = idx * 4;
3772 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
3773
3774 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
3775 unsigned interp_type;
3776 if (variable->data.sample) {
3777 interp_type = INTERP_SAMPLE;
3778 ctx->shader_info->fs.force_persample = true;
3779 } else if (variable->data.centroid)
3780 interp_type = INTERP_CENTROID;
3781 else
3782 interp_type = INTERP_CENTER;
3783
3784 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
3785 } else
3786 interp = NULL;
3787
3788 for (unsigned i = 0; i < attrib_count; ++i)
3789 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
3790
3791 }
3792
3793 static void
3794 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
3795 struct nir_variable *variable)
3796 {
3797 switch (ctx->stage) {
3798 case MESA_SHADER_VERTEX:
3799 handle_vs_input_decl(ctx, variable);
3800 break;
3801 case MESA_SHADER_FRAGMENT:
3802 handle_fs_input_decl(ctx, variable);
3803 break;
3804 default:
3805 break;
3806 }
3807
3808 }
3809
3810 static void
3811 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
3812 struct nir_shader *nir)
3813 {
3814 unsigned index = 0;
3815 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
3816 LLVMValueRef interp_param;
3817 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
3818
3819 if (!(ctx->input_mask & (1ull << i)))
3820 continue;
3821
3822 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC) {
3823 interp_param = *inputs;
3824 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
3825 inputs);
3826
3827 if (!interp_param)
3828 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
3829 ++index;
3830 } else if (i == VARYING_SLOT_POS) {
3831 for(int i = 0; i < 3; ++i)
3832 inputs[i] = ctx->frag_pos[i];
3833
3834 inputs[3] = ac_emit_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
3835 }
3836 }
3837 ctx->shader_info->fs.num_interp = index;
3838 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
3839 ctx->shader_info->fs.has_pcoord = true;
3840 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
3841 }
3842
3843 static LLVMValueRef
3844 ac_build_alloca(struct nir_to_llvm_context *ctx,
3845 LLVMTypeRef type,
3846 const char *name)
3847 {
3848 LLVMBuilderRef builder = ctx->builder;
3849 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
3850 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
3851 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
3852 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
3853 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
3854 LLVMValueRef res;
3855
3856 if (first_instr) {
3857 LLVMPositionBuilderBefore(first_builder, first_instr);
3858 } else {
3859 LLVMPositionBuilderAtEnd(first_builder, first_block);
3860 }
3861
3862 res = LLVMBuildAlloca(first_builder, type, name);
3863 LLVMBuildStore(builder, LLVMConstNull(type), res);
3864
3865 LLVMDisposeBuilder(first_builder);
3866
3867 return res;
3868 }
3869
3870 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
3871 LLVMTypeRef type,
3872 const char *name)
3873 {
3874 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
3875 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
3876 return ptr;
3877 }
3878
3879 static void
3880 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
3881 struct nir_variable *variable)
3882 {
3883 int idx = variable->data.location + variable->data.index;
3884 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
3885
3886 variable->data.driver_location = idx * 4;
3887
3888 if (ctx->stage == MESA_SHADER_VERTEX) {
3889
3890 if (idx == VARYING_SLOT_CLIP_DIST0 ||
3891 idx == VARYING_SLOT_CULL_DIST0) {
3892 int length = glsl_get_length(variable->type);
3893 if (idx == VARYING_SLOT_CLIP_DIST0) {
3894 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
3895 ctx->num_clips = length;
3896 } else if (idx == VARYING_SLOT_CULL_DIST0) {
3897 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
3898 ctx->num_culls = length;
3899 }
3900 if (length > 4)
3901 attrib_count = 2;
3902 else
3903 attrib_count = 1;
3904 }
3905 }
3906
3907 for (unsigned i = 0; i < attrib_count; ++i) {
3908 for (unsigned chan = 0; chan < 4; chan++) {
3909 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
3910 si_build_alloca_undef(ctx, ctx->f32, "");
3911 }
3912 }
3913 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
3914 }
3915
3916 static void
3917 setup_locals(struct nir_to_llvm_context *ctx,
3918 struct nir_function *func)
3919 {
3920 int i, j;
3921 ctx->num_locals = 0;
3922 nir_foreach_variable(variable, &func->impl->locals) {
3923 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
3924 variable->data.driver_location = ctx->num_locals * 4;
3925 ctx->num_locals += attrib_count;
3926 }
3927 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
3928 if (!ctx->locals)
3929 return;
3930
3931 for (i = 0; i < ctx->num_locals; i++) {
3932 for (j = 0; j < 4; j++) {
3933 ctx->locals[i * 4 + j] =
3934 si_build_alloca_undef(ctx, ctx->f32, "temp");
3935 }
3936 }
3937 }
3938
3939 static LLVMValueRef
3940 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
3941 {
3942 v = to_float(ctx, v);
3943 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", v, LLVMConstReal(ctx->f32, lo));
3944 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", v, LLVMConstReal(ctx->f32, hi));
3945 }
3946
3947
3948 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
3949 LLVMValueRef src0, LLVMValueRef src1)
3950 {
3951 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
3952 LLVMValueRef comp[2];
3953
3954 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
3955 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
3956 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
3957 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
3958 }
3959
3960 /* Initialize arguments for the shader export intrinsic */
3961 static void
3962 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
3963 LLVMValueRef *values,
3964 unsigned target,
3965 LLVMValueRef *args)
3966 {
3967 /* Default is 0xf. Adjusted below depending on the format. */
3968 args[0] = LLVMConstInt(ctx->i32, target != V_008DFC_SQ_EXP_NULL ? 0xf : 0, false);
3969 /* Specify whether the EXEC mask represents the valid mask */
3970 args[1] = LLVMConstInt(ctx->i32, 0, false);
3971
3972 /* Specify whether this is the last export */
3973 args[2] = LLVMConstInt(ctx->i32, 0, false);
3974 /* Specify the target we are exporting */
3975 args[3] = LLVMConstInt(ctx->i32, target, false);
3976
3977 args[4] = LLVMConstInt(ctx->i32, 0, false); /* COMPR flag */
3978 args[5] = LLVMGetUndef(ctx->f32);
3979 args[6] = LLVMGetUndef(ctx->f32);
3980 args[7] = LLVMGetUndef(ctx->f32);
3981 args[8] = LLVMGetUndef(ctx->f32);
3982
3983 if (!values)
3984 return;
3985
3986 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
3987 LLVMValueRef val[4];
3988 unsigned index = target - V_008DFC_SQ_EXP_MRT;
3989 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
3990 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
3991
3992 switch(col_format) {
3993 case V_028714_SPI_SHADER_ZERO:
3994 args[0] = LLVMConstInt(ctx->i32, 0x0, 0);
3995 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_NULL, 0);
3996 break;
3997
3998 case V_028714_SPI_SHADER_32_R:
3999 args[0] = LLVMConstInt(ctx->i32, 0x1, 0);
4000 args[5] = values[0];
4001 break;
4002
4003 case V_028714_SPI_SHADER_32_GR:
4004 args[0] = LLVMConstInt(ctx->i32, 0x3, 0);
4005 args[5] = values[0];
4006 args[6] = values[1];
4007 break;
4008
4009 case V_028714_SPI_SHADER_32_AR:
4010 args[0] = LLVMConstInt(ctx->i32, 0x9, 0);
4011 args[5] = values[0];
4012 args[8] = values[3];
4013 break;
4014
4015 case V_028714_SPI_SHADER_FP16_ABGR:
4016 args[4] = ctx->i32one;
4017
4018 for (unsigned chan = 0; chan < 2; chan++) {
4019 LLVMValueRef pack_args[2] = {
4020 values[2 * chan],
4021 values[2 * chan + 1]
4022 };
4023 LLVMValueRef packed;
4024
4025 packed = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.packf16",
4026 ctx->i32, pack_args, 2,
4027 AC_FUNC_ATTR_READNONE);
4028 args[chan + 5] = packed;
4029 }
4030 break;
4031
4032 case V_028714_SPI_SHADER_UNORM16_ABGR:
4033 for (unsigned chan = 0; chan < 4; chan++) {
4034 val[chan] = emit_float_saturate(ctx, values[chan], 0, 1);
4035 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4036 LLVMConstReal(ctx->f32, 65535), "");
4037 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4038 LLVMConstReal(ctx->f32, 0.5), "");
4039 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4040 ctx->i32, "");
4041 }
4042
4043 args[4] = ctx->i32one;
4044 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4045 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4046 break;
4047
4048 case V_028714_SPI_SHADER_SNORM16_ABGR:
4049 for (unsigned chan = 0; chan < 4; chan++) {
4050 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4051 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4052 LLVMConstReal(ctx->f32, 32767), "");
4053
4054 /* If positive, add 0.5, else add -0.5. */
4055 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4056 LLVMBuildSelect(ctx->builder,
4057 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4058 val[chan], ctx->f32zero, ""),
4059 LLVMConstReal(ctx->f32, 0.5),
4060 LLVMConstReal(ctx->f32, -0.5), ""), "");
4061 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4062 }
4063
4064 args[4] = ctx->i32one;
4065 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4066 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4067 break;
4068
4069 case V_028714_SPI_SHADER_UINT16_ABGR: {
4070 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4071
4072 for (unsigned chan = 0; chan < 4; chan++) {
4073 val[chan] = to_integer(ctx, values[chan]);
4074 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4075 }
4076
4077 args[4] = ctx->i32one;
4078 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4079 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4080 break;
4081 }
4082
4083 case V_028714_SPI_SHADER_SINT16_ABGR: {
4084 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4085 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4086
4087 /* Clamp. */
4088 for (unsigned chan = 0; chan < 4; chan++) {
4089 val[chan] = to_integer(ctx, values[chan]);
4090 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4091 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4092 }
4093
4094 args[4] = ctx->i32one;
4095 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4096 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4097 break;
4098 }
4099
4100 default:
4101 case V_028714_SPI_SHADER_32_ABGR:
4102 memcpy(&args[5], values, sizeof(values[0]) * 4);
4103 break;
4104 }
4105 } else
4106 memcpy(&args[5], values, sizeof(values[0]) * 4);
4107
4108 for (unsigned i = 5; i < 9; ++i)
4109 args[i] = to_float(ctx, args[i]);
4110 }
4111
4112 static void
4113 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4114 {
4115 uint32_t param_count = 0;
4116 unsigned target;
4117 unsigned pos_idx, num_pos_exports = 0;
4118 LLVMValueRef args[9];
4119 LLVMValueRef pos_args[4][9] = { { 0 } };
4120 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4121 int i;
4122 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4123 (1ull << VARYING_SLOT_CLIP_DIST1) |
4124 (1ull << VARYING_SLOT_CULL_DIST0) |
4125 (1ull << VARYING_SLOT_CULL_DIST1));
4126
4127 if (clip_mask) {
4128 LLVMValueRef slots[8];
4129 unsigned j;
4130
4131 if (ctx->shader_info->vs.cull_dist_mask)
4132 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_clips;
4133
4134 i = VARYING_SLOT_CLIP_DIST0;
4135 for (j = 0; j < ctx->num_clips; j++)
4136 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4137 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4138 i = VARYING_SLOT_CULL_DIST0;
4139 for (j = 0; j < ctx->num_culls; j++)
4140 slots[ctx->num_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4141 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4142
4143 for (i = ctx->num_clips + ctx->num_culls; i < 8; i++)
4144 slots[i] = LLVMGetUndef(ctx->f32);
4145
4146 if (ctx->num_clips + ctx->num_culls > 4) {
4147 target = V_008DFC_SQ_EXP_POS + 3;
4148 si_llvm_init_export_args(ctx, &slots[4], target, args);
4149 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4150 args, sizeof(args));
4151 }
4152
4153 target = V_008DFC_SQ_EXP_POS + 2;
4154 si_llvm_init_export_args(ctx, &slots[0], target, args);
4155 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4156 args, sizeof(args));
4157
4158 }
4159
4160 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4161 LLVMValueRef values[4];
4162 if (!(ctx->output_mask & (1ull << i)))
4163 continue;
4164
4165 for (unsigned j = 0; j < 4; j++)
4166 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4167 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4168
4169 if (i == VARYING_SLOT_POS) {
4170 target = V_008DFC_SQ_EXP_POS;
4171 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4172 i == VARYING_SLOT_CLIP_DIST1 ||
4173 i == VARYING_SLOT_CULL_DIST0 ||
4174 i == VARYING_SLOT_CULL_DIST1) {
4175 continue;
4176 } else if (i == VARYING_SLOT_PSIZ) {
4177 ctx->shader_info->vs.writes_pointsize = true;
4178 psize_value = values[0];
4179 continue;
4180 } else if (i == VARYING_SLOT_LAYER) {
4181 ctx->shader_info->vs.writes_layer = true;
4182 layer_value = values[0];
4183 continue;
4184 } else if (i == VARYING_SLOT_VIEWPORT) {
4185 ctx->shader_info->vs.writes_viewport_index = true;
4186 viewport_index_value = values[0];
4187 continue;
4188 } else if (i >= VARYING_SLOT_VAR0) {
4189 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4190 target = V_008DFC_SQ_EXP_PARAM + param_count;
4191 param_count++;
4192 }
4193
4194 si_llvm_init_export_args(ctx, values, target, args);
4195
4196 if (target >= V_008DFC_SQ_EXP_POS &&
4197 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4198 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4199 args, sizeof(args));
4200 } else {
4201 ac_emit_llvm_intrinsic(&ctx->ac,
4202 "llvm.SI.export",
4203 ctx->voidt,
4204 args, 9, 0);
4205 }
4206 }
4207
4208 /* We need to add the position output manually if it's missing. */
4209 if (!pos_args[0][0]) {
4210 pos_args[0][0] = LLVMConstInt(ctx->i32, 0xf, false);
4211 pos_args[0][1] = ctx->i32zero; /* EXEC mask */
4212 pos_args[0][2] = ctx->i32zero; /* last export? */
4213 pos_args[0][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS, false);
4214 pos_args[0][4] = ctx->i32zero; /* COMPR flag */
4215 pos_args[0][5] = ctx->f32zero; /* X */
4216 pos_args[0][6] = ctx->f32zero; /* Y */
4217 pos_args[0][7] = ctx->f32zero; /* Z */
4218 pos_args[0][8] = ctx->f32one; /* W */
4219 }
4220
4221 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4222 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4223 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4224 if (mask) {
4225 pos_args[1][0] = LLVMConstInt(ctx->i32, mask, false); /* writemask */
4226 pos_args[1][1] = ctx->i32zero; /* EXEC mask */
4227 pos_args[1][2] = ctx->i32zero; /* last export? */
4228 pos_args[1][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + 1, false);
4229 pos_args[1][4] = ctx->i32zero; /* COMPR flag */
4230 pos_args[1][5] = ctx->f32zero; /* X */
4231 pos_args[1][6] = ctx->f32zero; /* Y */
4232 pos_args[1][7] = ctx->f32zero; /* Z */
4233 pos_args[1][8] = ctx->f32zero; /* W */
4234
4235 if (ctx->shader_info->vs.writes_pointsize == true)
4236 pos_args[1][5] = psize_value;
4237 if (ctx->shader_info->vs.writes_layer == true)
4238 pos_args[1][7] = layer_value;
4239 if (ctx->shader_info->vs.writes_viewport_index == true)
4240 pos_args[1][8] = viewport_index_value;
4241 }
4242 for (i = 0; i < 4; i++) {
4243 if (pos_args[i][0])
4244 num_pos_exports++;
4245 }
4246
4247 pos_idx = 0;
4248 for (i = 0; i < 4; i++) {
4249 if (!pos_args[i][0])
4250 continue;
4251
4252 /* Specify the target we are exporting */
4253 pos_args[i][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + pos_idx++, false);
4254 if (pos_idx == num_pos_exports)
4255 pos_args[i][2] = ctx->i32one;
4256 ac_emit_llvm_intrinsic(&ctx->ac,
4257 "llvm.SI.export",
4258 ctx->voidt,
4259 pos_args[i], 9, 0);
4260 }
4261
4262 ctx->shader_info->vs.pos_exports = num_pos_exports;
4263 ctx->shader_info->vs.param_exports = param_count;
4264 }
4265
4266 static void
4267 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4268 LLVMValueRef *color, unsigned param, bool is_last)
4269 {
4270 LLVMValueRef args[9];
4271 /* Export */
4272 si_llvm_init_export_args(ctx, color, param,
4273 args);
4274
4275 if (is_last) {
4276 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4277 args[2] = ctx->i32one; /* DONE bit */
4278 } else if (args[0] == ctx->i32zero)
4279 return; /* unnecessary NULL export */
4280
4281 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4282 ctx->voidt, args, 9, 0);
4283 }
4284
4285 static void
4286 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4287 LLVMValueRef depth, LLVMValueRef stencil,
4288 LLVMValueRef samplemask)
4289 {
4290 LLVMValueRef args[9];
4291 unsigned mask = 0;
4292 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4293 args[2] = ctx->i32one; /* DONE bit */
4294 /* Specify the target we are exporting */
4295 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_MRTZ, false);
4296
4297 args[4] = ctx->i32zero; /* COMP flag */
4298 args[5] = LLVMGetUndef(ctx->f32); /* R, depth */
4299 args[6] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4300 args[7] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4301 args[8] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4302
4303 if (depth) {
4304 args[5] = depth;
4305 mask |= 0x1;
4306 }
4307
4308 if (stencil) {
4309 args[6] = stencil;
4310 mask |= 0x2;
4311 }
4312
4313 if (samplemask) {
4314 args[7] = samplemask;
4315 mask |= 0x04;
4316 }
4317
4318 /* SI (except OLAND) has a bug that it only looks
4319 * at the X writemask component. */
4320 if (ctx->options->chip_class == SI &&
4321 ctx->options->family != CHIP_OLAND)
4322 mask |= 0x01;
4323
4324 args[0] = LLVMConstInt(ctx->i32, mask, false);
4325 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4326 ctx->voidt, args, 9, 0);
4327 }
4328
4329 static void
4330 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4331 {
4332 unsigned index = 0;
4333 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4334
4335 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4336 LLVMValueRef values[4];
4337
4338 if (!(ctx->output_mask & (1ull << i)))
4339 continue;
4340
4341 if (i == FRAG_RESULT_DEPTH) {
4342 ctx->shader_info->fs.writes_z = true;
4343 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4344 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4345 } else if (i == FRAG_RESULT_STENCIL) {
4346 ctx->shader_info->fs.writes_stencil = true;
4347 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4348 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4349 } else {
4350 bool last = false;
4351 for (unsigned j = 0; j < 4; j++)
4352 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4353 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4354
4355 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil)
4356 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4357
4358 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4359 index++;
4360 }
4361 }
4362
4363 if (depth || stencil)
4364 si_export_mrt_z(ctx, depth, stencil, samplemask);
4365 else if (!index)
4366 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4367
4368 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4369 }
4370
4371 static void
4372 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4373 {
4374 switch (ctx->stage) {
4375 case MESA_SHADER_VERTEX:
4376 handle_vs_outputs_post(ctx);
4377 break;
4378 case MESA_SHADER_FRAGMENT:
4379 handle_fs_outputs_post(ctx);
4380 break;
4381 default:
4382 break;
4383 }
4384 }
4385
4386 static void
4387 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4388 struct nir_variable *variable, uint32_t *offset, int idx)
4389 {
4390 unsigned size = glsl_count_attribute_slots(variable->type, false);
4391 variable->data.driver_location = *offset;
4392 *offset += size;
4393 }
4394
4395 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4396 {
4397 LLVMPassManagerRef passmgr;
4398 /* Create the pass manager */
4399 passmgr = LLVMCreateFunctionPassManagerForModule(
4400 ctx->module);
4401
4402 /* This pass should eliminate all the load and store instructions */
4403 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4404
4405 /* Add some optimization passes */
4406 LLVMAddScalarReplAggregatesPass(passmgr);
4407 LLVMAddLICMPass(passmgr);
4408 LLVMAddAggressiveDCEPass(passmgr);
4409 LLVMAddCFGSimplificationPass(passmgr);
4410 LLVMAddInstructionCombiningPass(passmgr);
4411
4412 /* Run the pass */
4413 LLVMInitializeFunctionPassManager(passmgr);
4414 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4415 LLVMFinalizeFunctionPassManager(passmgr);
4416
4417 LLVMDisposeBuilder(ctx->builder);
4418 LLVMDisposePassManager(passmgr);
4419 }
4420
4421 static
4422 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4423 struct nir_shader *nir,
4424 struct ac_shader_variant_info *shader_info,
4425 const struct ac_nir_compiler_options *options)
4426 {
4427 struct nir_to_llvm_context ctx = {0};
4428 struct nir_function *func;
4429 unsigned i;
4430 ctx.options = options;
4431 ctx.shader_info = shader_info;
4432 ctx.context = LLVMContextCreate();
4433 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4434
4435 ac_llvm_context_init(&ctx.ac, ctx.context);
4436 ctx.ac.module = ctx.module;
4437
4438 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4439
4440 memset(shader_info, 0, sizeof(*shader_info));
4441
4442 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4443 setup_types(&ctx);
4444
4445 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4446 ctx.ac.builder = ctx.builder;
4447 ctx.stage = nir->stage;
4448
4449 for (i = 0; i < AC_UD_MAX_SETS; i++)
4450 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4451 for (i = 0; i < AC_UD_MAX_UD; i++)
4452 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4453
4454 create_function(&ctx);
4455
4456 if (nir->stage == MESA_SHADER_COMPUTE) {
4457 int num_shared = 0;
4458 nir_foreach_variable(variable, &nir->shared)
4459 num_shared++;
4460 if (num_shared) {
4461 int idx = 0;
4462 uint32_t shared_size = 0;
4463 LLVMValueRef var;
4464 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4465 nir_foreach_variable(variable, &nir->shared) {
4466 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4467 idx++;
4468 }
4469
4470 shared_size *= 4;
4471 var = LLVMAddGlobalInAddressSpace(ctx.module,
4472 LLVMArrayType(ctx.i8, shared_size),
4473 "compute_lds",
4474 LOCAL_ADDR_SPACE);
4475 LLVMSetAlignment(var, 4);
4476 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4477 }
4478 }
4479
4480 nir_foreach_variable(variable, &nir->inputs)
4481 handle_shader_input_decl(&ctx, variable);
4482
4483 if (nir->stage == MESA_SHADER_FRAGMENT)
4484 handle_fs_inputs_pre(&ctx, nir);
4485
4486 nir_foreach_variable(variable, &nir->outputs)
4487 handle_shader_output_decl(&ctx, variable);
4488
4489 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4490 _mesa_key_pointer_equal);
4491 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4492 _mesa_key_pointer_equal);
4493
4494 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4495
4496 setup_locals(&ctx, func);
4497
4498 visit_cf_list(&ctx, &func->impl->body);
4499 phi_post_pass(&ctx);
4500
4501 handle_shader_outputs_post(&ctx);
4502 LLVMBuildRetVoid(ctx.builder);
4503
4504 ac_llvm_finalize_module(&ctx);
4505 free(ctx.locals);
4506 ralloc_free(ctx.defs);
4507 ralloc_free(ctx.phis);
4508
4509 return ctx.module;
4510 }
4511
4512 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4513 {
4514 unsigned *retval = (unsigned *)context;
4515 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4516 char *description = LLVMGetDiagInfoDescription(di);
4517
4518 if (severity == LLVMDSError) {
4519 *retval = 1;
4520 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4521 description);
4522 }
4523
4524 LLVMDisposeMessage(description);
4525 }
4526
4527 static unsigned ac_llvm_compile(LLVMModuleRef M,
4528 struct ac_shader_binary *binary,
4529 LLVMTargetMachineRef tm)
4530 {
4531 unsigned retval = 0;
4532 char *err;
4533 LLVMContextRef llvm_ctx;
4534 LLVMMemoryBufferRef out_buffer;
4535 unsigned buffer_size;
4536 const char *buffer_data;
4537 LLVMBool mem_err;
4538
4539 /* Setup Diagnostic Handler*/
4540 llvm_ctx = LLVMGetModuleContext(M);
4541
4542 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4543 &retval);
4544
4545 /* Compile IR*/
4546 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
4547 &err, &out_buffer);
4548
4549 /* Process Errors/Warnings */
4550 if (mem_err) {
4551 fprintf(stderr, "%s: %s", __FUNCTION__, err);
4552 free(err);
4553 retval = 1;
4554 goto out;
4555 }
4556
4557 /* Extract Shader Code*/
4558 buffer_size = LLVMGetBufferSize(out_buffer);
4559 buffer_data = LLVMGetBufferStart(out_buffer);
4560
4561 ac_elf_read(buffer_data, buffer_size, binary);
4562
4563 /* Clean up */
4564 LLVMDisposeMemoryBuffer(out_buffer);
4565
4566 out:
4567 return retval;
4568 }
4569
4570 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
4571 LLVMModuleRef llvm_module,
4572 struct ac_shader_binary *binary,
4573 struct ac_shader_config *config,
4574 struct ac_shader_variant_info *shader_info,
4575 gl_shader_stage stage,
4576 bool dump_shader, bool supports_spill)
4577 {
4578 if (dump_shader)
4579 ac_dump_module(llvm_module);
4580
4581 memset(binary, 0, sizeof(*binary));
4582 int v = ac_llvm_compile(llvm_module, binary, tm);
4583 if (v) {
4584 fprintf(stderr, "compile failed\n");
4585 }
4586
4587 if (dump_shader)
4588 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
4589
4590 ac_shader_binary_read_config(binary, config, 0, supports_spill);
4591
4592 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4593 LLVMDisposeModule(llvm_module);
4594 LLVMContextDispose(ctx);
4595
4596 if (stage == MESA_SHADER_FRAGMENT) {
4597 shader_info->num_input_vgprs = 0;
4598 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
4599 shader_info->num_input_vgprs += 2;
4600 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
4601 shader_info->num_input_vgprs += 2;
4602 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
4603 shader_info->num_input_vgprs += 2;
4604 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
4605 shader_info->num_input_vgprs += 3;
4606 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
4607 shader_info->num_input_vgprs += 2;
4608 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
4609 shader_info->num_input_vgprs += 2;
4610 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
4611 shader_info->num_input_vgprs += 2;
4612 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
4613 shader_info->num_input_vgprs += 1;
4614 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
4615 shader_info->num_input_vgprs += 1;
4616 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
4617 shader_info->num_input_vgprs += 1;
4618 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
4619 shader_info->num_input_vgprs += 1;
4620 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
4621 shader_info->num_input_vgprs += 1;
4622 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
4623 shader_info->num_input_vgprs += 1;
4624 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
4625 shader_info->num_input_vgprs += 1;
4626 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
4627 shader_info->num_input_vgprs += 1;
4628 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
4629 shader_info->num_input_vgprs += 1;
4630 }
4631 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
4632
4633 /* +3 for scratch wave offset and VCC */
4634 config->num_sgprs = MAX2(config->num_sgprs,
4635 shader_info->num_input_sgprs + 3);
4636 }
4637
4638 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
4639 struct ac_shader_binary *binary,
4640 struct ac_shader_config *config,
4641 struct ac_shader_variant_info *shader_info,
4642 struct nir_shader *nir,
4643 const struct ac_nir_compiler_options *options,
4644 bool dump_shader)
4645 {
4646
4647 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
4648 options);
4649
4650 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
4651 switch (nir->stage) {
4652 case MESA_SHADER_COMPUTE:
4653 for (int i = 0; i < 3; ++i)
4654 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
4655 break;
4656 case MESA_SHADER_FRAGMENT:
4657 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
4658 break;
4659 default:
4660 break;
4661 }
4662 }