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radv: get InstanceID from VGPR1 (or VGPR2 for tess) instead of VGPR3
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tes_rel_patch_id;
115 LLVMValueRef tes_u;
116 LLVMValueRef tes_v;
117
118 LLVMValueRef gsvs_ring_stride;
119 LLVMValueRef gsvs_num_entries;
120 LLVMValueRef gs2vs_offset;
121 LLVMValueRef gs_wave_id;
122 LLVMValueRef gs_vtx_offset[6];
123
124 LLVMValueRef esgs_ring;
125 LLVMValueRef gsvs_ring;
126 LLVMValueRef hs_ring_tess_offchip;
127 LLVMValueRef hs_ring_tess_factor;
128
129 LLVMValueRef prim_mask;
130 LLVMValueRef sample_pos_offset;
131 LLVMValueRef persp_sample, persp_center, persp_centroid;
132 LLVMValueRef linear_sample, linear_center, linear_centroid;
133
134 gl_shader_stage stage;
135
136 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
137
138 uint64_t input_mask;
139 uint64_t output_mask;
140 uint8_t num_output_clips;
141 uint8_t num_output_culls;
142
143 bool is_gs_copy_shader;
144 LLVMValueRef gs_next_vertex;
145 unsigned gs_max_out_vertices;
146
147 unsigned tes_primitive_mode;
148 uint64_t tess_outputs_written;
149 uint64_t tess_patch_outputs_written;
150
151 uint32_t tcs_patch_outputs_read;
152 uint64_t tcs_outputs_read;
153 };
154
155 static inline struct nir_to_llvm_context *
156 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
157 {
158 struct nir_to_llvm_context *ctx = NULL;
159 return container_of(abi, ctx, abi);
160 }
161
162 static LLVMTypeRef
163 nir2llvmtype(struct ac_nir_context *ctx,
164 const struct glsl_type *type)
165 {
166 switch (glsl_get_base_type(glsl_without_array(type))) {
167 case GLSL_TYPE_UINT:
168 case GLSL_TYPE_INT:
169 return ctx->ac.i32;
170 case GLSL_TYPE_UINT64:
171 case GLSL_TYPE_INT64:
172 return ctx->ac.i64;
173 case GLSL_TYPE_DOUBLE:
174 return ctx->ac.f64;
175 case GLSL_TYPE_FLOAT:
176 return ctx->ac.f32;
177 default:
178 assert(!"Unsupported type in nir2llvmtype()");
179 break;
180 }
181 return 0;
182 }
183
184 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
185 const nir_deref_var *deref,
186 enum ac_descriptor_type desc_type,
187 const nir_tex_instr *instr,
188 bool image, bool write);
189
190 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
191 {
192 return (index * 4) + chan;
193 }
194
195 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
196 {
197 /* handle patch indices separate */
198 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
199 return 0;
200 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
201 return 1;
202 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
203 return 2 + (slot - VARYING_SLOT_PATCH0);
204
205 if (slot == VARYING_SLOT_POS)
206 return 0;
207 if (slot == VARYING_SLOT_PSIZ)
208 return 1;
209 if (slot == VARYING_SLOT_CLIP_DIST0)
210 return 2;
211 /* 3 is reserved for clip dist as well */
212 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
213 return 4 + (slot - VARYING_SLOT_VAR0);
214 unreachable("illegal slot in get unique index\n");
215 }
216
217 static void set_llvm_calling_convention(LLVMValueRef func,
218 gl_shader_stage stage)
219 {
220 enum radeon_llvm_calling_convention calling_conv;
221
222 switch (stage) {
223 case MESA_SHADER_VERTEX:
224 case MESA_SHADER_TESS_EVAL:
225 calling_conv = RADEON_LLVM_AMDGPU_VS;
226 break;
227 case MESA_SHADER_GEOMETRY:
228 calling_conv = RADEON_LLVM_AMDGPU_GS;
229 break;
230 case MESA_SHADER_TESS_CTRL:
231 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
232 break;
233 case MESA_SHADER_FRAGMENT:
234 calling_conv = RADEON_LLVM_AMDGPU_PS;
235 break;
236 case MESA_SHADER_COMPUTE:
237 calling_conv = RADEON_LLVM_AMDGPU_CS;
238 break;
239 default:
240 unreachable("Unhandle shader type");
241 }
242
243 LLVMSetFunctionCallConv(func, calling_conv);
244 }
245
246 #define MAX_ARGS 23
247 struct arg_info {
248 LLVMTypeRef types[MAX_ARGS];
249 LLVMValueRef *assign[MAX_ARGS];
250 unsigned array_params_mask;
251 uint8_t count;
252 uint8_t sgpr_count;
253 uint8_t num_sgprs_used;
254 uint8_t num_vgprs_used;
255 };
256
257 enum ac_arg_regfile {
258 ARG_SGPR,
259 ARG_VGPR,
260 };
261
262 static void
263 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
264 LLVMValueRef *param_ptr)
265 {
266 assert(info->count < MAX_ARGS);
267
268 info->assign[info->count] = param_ptr;
269 info->types[info->count] = type;
270 info->count++;
271
272 if (regfile == ARG_SGPR) {
273 info->num_sgprs_used += ac_get_type_size(type) / 4;
274 info->sgpr_count++;
275 } else {
276 assert(regfile == ARG_VGPR);
277 info->num_vgprs_used += ac_get_type_size(type) / 4;
278 }
279 }
280
281 static inline void
282 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
283 {
284 info->array_params_mask |= (1 << info->count);
285 add_arg(info, ARG_SGPR, type, param_ptr);
286 }
287
288 static void assign_arguments(LLVMValueRef main_function,
289 struct arg_info *info)
290 {
291 unsigned i;
292 for (i = 0; i < info->count; i++) {
293 if (info->assign[i])
294 *info->assign[i] = LLVMGetParam(main_function, i);
295 }
296 }
297
298 static LLVMValueRef
299 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
300 LLVMBuilderRef builder, LLVMTypeRef *return_types,
301 unsigned num_return_elems,
302 struct arg_info *args,
303 unsigned max_workgroup_size,
304 bool unsafe_math)
305 {
306 LLVMTypeRef main_function_type, ret_type;
307 LLVMBasicBlockRef main_function_body;
308
309 if (num_return_elems)
310 ret_type = LLVMStructTypeInContext(ctx, return_types,
311 num_return_elems, true);
312 else
313 ret_type = LLVMVoidTypeInContext(ctx);
314
315 /* Setup the function */
316 main_function_type =
317 LLVMFunctionType(ret_type, args->types, args->count, 0);
318 LLVMValueRef main_function =
319 LLVMAddFunction(module, "main", main_function_type);
320 main_function_body =
321 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
322 LLVMPositionBuilderAtEnd(builder, main_function_body);
323
324 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
325 for (unsigned i = 0; i < args->sgpr_count; ++i) {
326 if (args->array_params_mask & (1 << i)) {
327 LLVMValueRef P = LLVMGetParam(main_function, i);
328 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
329 ac_add_attr_dereferenceable(P, UINT64_MAX);
330 }
331 else {
332 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
333 }
334 }
335
336 if (max_workgroup_size) {
337 ac_llvm_add_target_dep_function_attr(main_function,
338 "amdgpu-max-work-group-size",
339 max_workgroup_size);
340 }
341 if (unsafe_math) {
342 /* These were copied from some LLVM test. */
343 LLVMAddTargetDependentFunctionAttr(main_function,
344 "less-precise-fpmad",
345 "true");
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "no-infs-fp-math",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-nans-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "unsafe-fp-math",
354 "true");
355 }
356 return main_function;
357 }
358
359 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
360 {
361 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
362 CONST_ADDR_SPACE);
363 }
364
365 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
366 {
367 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
368 type = LLVMGetElementType(type);
369
370 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
371 return LLVMGetIntTypeWidth(type);
372
373 if (type == ctx->f16)
374 return 16;
375 if (type == ctx->f32)
376 return 32;
377 if (type == ctx->f64)
378 return 64;
379
380 unreachable("Unhandled type kind in get_elem_bits");
381 }
382
383 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
384 LLVMValueRef param, unsigned rshift,
385 unsigned bitwidth)
386 {
387 LLVMValueRef value = param;
388 if (rshift)
389 value = LLVMBuildLShr(ctx->builder, value,
390 LLVMConstInt(ctx->i32, rshift, false), "");
391
392 if (rshift + bitwidth < 32) {
393 unsigned mask = (1 << bitwidth) - 1;
394 value = LLVMBuildAnd(ctx->builder, value,
395 LLVMConstInt(ctx->i32, mask, false), "");
396 }
397 return value;
398 }
399
400 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
401 {
402 switch (ctx->stage) {
403 case MESA_SHADER_TESS_CTRL:
404 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
405 case MESA_SHADER_TESS_EVAL:
406 return ctx->tes_rel_patch_id;
407 break;
408 default:
409 unreachable("Illegal stage");
410 }
411 }
412
413 /* Tessellation shaders pass outputs to the next shader using LDS.
414 *
415 * LS outputs = TCS inputs
416 * TCS outputs = TES inputs
417 *
418 * The LDS layout is:
419 * - TCS inputs for patch 0
420 * - TCS inputs for patch 1
421 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
422 * - ...
423 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
424 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
425 * - TCS outputs for patch 1
426 * - Per-patch TCS outputs for patch 1
427 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
428 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
429 * - ...
430 *
431 * All three shaders VS(LS), TCS, TES share the same LDS space.
432 */
433 static LLVMValueRef
434 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
435 {
436 if (ctx->stage == MESA_SHADER_VERTEX)
437 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
438 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
439 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
440 else {
441 assert(0);
442 return NULL;
443 }
444 }
445
446 static LLVMValueRef
447 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
448 {
449 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
450 }
451
452 static LLVMValueRef
453 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
454 {
455 return LLVMBuildMul(ctx->builder,
456 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
457 LLVMConstInt(ctx->ac.i32, 4, false), "");
458 }
459
460 static LLVMValueRef
461 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
462 {
463 return LLVMBuildMul(ctx->builder,
464 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
465 LLVMConstInt(ctx->ac.i32, 4, false), "");
466 }
467
468 static LLVMValueRef
469 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
470 {
471 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
472 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
473
474 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
475 }
476
477 static LLVMValueRef
478 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
479 {
480 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
481 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
482 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
483
484 return LLVMBuildAdd(ctx->builder, patch0_offset,
485 LLVMBuildMul(ctx->builder, patch_stride,
486 rel_patch_id, ""),
487 "");
488 }
489
490 static LLVMValueRef
491 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch0_patch_data_offset =
494 get_tcs_out_patch0_patch_data_offset(ctx);
495 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
496 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
497
498 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
499 LLVMBuildMul(ctx->builder, patch_stride,
500 rel_patch_id, ""),
501 "");
502 }
503
504 static void
505 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
506 uint32_t indirect_offset)
507 {
508 ud_info->sgpr_idx = *sgpr_idx;
509 ud_info->num_sgprs = num_sgprs;
510 ud_info->indirect = indirect_offset > 0;
511 ud_info->indirect_offset = indirect_offset;
512 *sgpr_idx += num_sgprs;
513 }
514
515 static void
516 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
517 uint8_t num_sgprs)
518 {
519 struct ac_userdata_info *ud_info =
520 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
521 assert(ud_info);
522
523 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
524 }
525
526 static void
527 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
528 uint32_t indirect_offset)
529 {
530 struct ac_userdata_info *ud_info =
531 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
532 assert(ud_info);
533
534 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
535 }
536
537 struct user_sgpr_info {
538 bool need_ring_offsets;
539 uint8_t sgpr_count;
540 bool indirect_all_descriptor_sets;
541 };
542
543 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
544 gl_shader_stage stage,
545 struct user_sgpr_info *user_sgpr_info)
546 {
547 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
548
549 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
550 if (stage == MESA_SHADER_GEOMETRY ||
551 stage == MESA_SHADER_VERTEX ||
552 stage == MESA_SHADER_TESS_CTRL ||
553 stage == MESA_SHADER_TESS_EVAL ||
554 ctx->is_gs_copy_shader)
555 user_sgpr_info->need_ring_offsets = true;
556
557 if (stage == MESA_SHADER_FRAGMENT &&
558 ctx->shader_info->info.ps.needs_sample_positions)
559 user_sgpr_info->need_ring_offsets = true;
560
561 /* 2 user sgprs will nearly always be allocated for scratch/rings */
562 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
563 user_sgpr_info->sgpr_count += 2;
564 }
565
566 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
567 switch (stage) {
568 case MESA_SHADER_COMPUTE:
569 if (ctx->shader_info->info.cs.uses_grid_size)
570 user_sgpr_info->sgpr_count += 3;
571 break;
572 case MESA_SHADER_FRAGMENT:
573 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
574 break;
575 case MESA_SHADER_VERTEX:
576 if (!ctx->is_gs_copy_shader) {
577 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
578 if (ctx->shader_info->info.vs.needs_draw_id) {
579 user_sgpr_info->sgpr_count += 3;
580 } else {
581 user_sgpr_info->sgpr_count += 2;
582 }
583 }
584 if (ctx->options->key.vs.as_ls)
585 user_sgpr_info->sgpr_count++;
586 break;
587 case MESA_SHADER_TESS_CTRL:
588 user_sgpr_info->sgpr_count += 4;
589 break;
590 case MESA_SHADER_TESS_EVAL:
591 user_sgpr_info->sgpr_count += 1;
592 break;
593 case MESA_SHADER_GEOMETRY:
594 user_sgpr_info->sgpr_count += 2;
595 break;
596 default:
597 break;
598 }
599
600 if (ctx->shader_info->info.needs_push_constants)
601 user_sgpr_info->sgpr_count += 2;
602
603 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
604 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
605 user_sgpr_info->sgpr_count += 2;
606 user_sgpr_info->indirect_all_descriptor_sets = true;
607 } else {
608 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
609 }
610 }
611
612 static void
613 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
614 gl_shader_stage stage,
615 bool has_previous_stage,
616 gl_shader_stage previous_stage,
617 const struct user_sgpr_info *user_sgpr_info,
618 struct arg_info *args,
619 LLVMValueRef *desc_sets)
620 {
621 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
622 unsigned num_sets = ctx->options->layout ?
623 ctx->options->layout->num_sets : 0;
624 unsigned stage_mask = 1 << stage;
625
626 if (has_previous_stage)
627 stage_mask |= 1 << previous_stage;
628
629 /* 1 for each descriptor set */
630 if (!user_sgpr_info->indirect_all_descriptor_sets) {
631 for (unsigned i = 0; i < num_sets; ++i) {
632 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
633 add_array_arg(args, type,
634 &ctx->descriptor_sets[i]);
635 }
636 }
637 } else {
638 add_array_arg(args, const_array(type, 32), desc_sets);
639 }
640
641 if (ctx->shader_info->info.needs_push_constants) {
642 /* 1 for push constants and dynamic descriptors */
643 add_array_arg(args, type, &ctx->push_constants);
644 }
645 }
646
647 static void
648 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
649 gl_shader_stage stage,
650 bool has_previous_stage,
651 gl_shader_stage previous_stage,
652 struct arg_info *args)
653 {
654 if (!ctx->is_gs_copy_shader &&
655 (stage == MESA_SHADER_VERTEX ||
656 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
657 if (ctx->shader_info->info.vs.has_vertex_buffers) {
658 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
659 &ctx->vertex_buffers);
660 }
661 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
662 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
663 if (ctx->shader_info->info.vs.needs_draw_id) {
664 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
665 }
666 }
667 }
668
669 static void
670 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
671 {
672 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
673 if (!ctx->is_gs_copy_shader) {
674 if (ctx->options->key.vs.as_ls) {
675 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
676 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
677 } else {
678 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
679 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
680 }
681 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
682 }
683 }
684
685 static void
686 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
687 {
688 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
689 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
690 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
691 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
692 }
693
694 static void
695 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
696 bool has_previous_stage, gl_shader_stage previous_stage,
697 const struct user_sgpr_info *user_sgpr_info,
698 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
699 {
700 unsigned num_sets = ctx->options->layout ?
701 ctx->options->layout->num_sets : 0;
702 unsigned stage_mask = 1 << stage;
703
704 if (has_previous_stage)
705 stage_mask |= 1 << previous_stage;
706
707 if (!user_sgpr_info->indirect_all_descriptor_sets) {
708 for (unsigned i = 0; i < num_sets; ++i) {
709 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
710 set_loc_desc(ctx, i, user_sgpr_idx, 0);
711 } else
712 ctx->descriptor_sets[i] = NULL;
713 }
714 } else {
715 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
716 user_sgpr_idx, 2);
717
718 for (unsigned i = 0; i < num_sets; ++i) {
719 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
720 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
721 ctx->descriptor_sets[i] =
722 ac_build_load_to_sgpr(&ctx->ac,
723 desc_sets,
724 LLVMConstInt(ctx->ac.i32, i, false));
725
726 } else
727 ctx->descriptor_sets[i] = NULL;
728 }
729 ctx->shader_info->need_indirect_descriptor_sets = true;
730 }
731
732 if (ctx->shader_info->info.needs_push_constants) {
733 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
734 }
735 }
736
737 static void
738 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
739 gl_shader_stage stage, bool has_previous_stage,
740 gl_shader_stage previous_stage,
741 uint8_t *user_sgpr_idx)
742 {
743 if (!ctx->is_gs_copy_shader &&
744 (stage == MESA_SHADER_VERTEX ||
745 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
746 if (ctx->shader_info->info.vs.has_vertex_buffers) {
747 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
748 user_sgpr_idx, 2);
749 }
750
751 unsigned vs_num = 2;
752 if (ctx->shader_info->info.vs.needs_draw_id)
753 vs_num++;
754
755 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
756 user_sgpr_idx, vs_num);
757 }
758 }
759
760 static void create_function(struct nir_to_llvm_context *ctx,
761 gl_shader_stage stage,
762 bool has_previous_stage,
763 gl_shader_stage previous_stage)
764 {
765 uint8_t user_sgpr_idx;
766 struct user_sgpr_info user_sgpr_info;
767 struct arg_info args = {};
768 LLVMValueRef desc_sets;
769
770 allocate_user_sgprs(ctx, stage, &user_sgpr_info);
771
772 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
773 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
774 &ctx->ring_offsets);
775 }
776
777 switch (stage) {
778 case MESA_SHADER_COMPUTE:
779 declare_global_input_sgprs(ctx, stage, has_previous_stage,
780 previous_stage, &user_sgpr_info,
781 &args, &desc_sets);
782
783 if (ctx->shader_info->info.cs.uses_grid_size) {
784 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
785 &ctx->num_work_groups);
786 }
787
788 for (int i = 0; i < 3; i++) {
789 ctx->workgroup_ids[i] = NULL;
790 if (ctx->shader_info->info.cs.uses_block_id[i]) {
791 add_arg(&args, ARG_SGPR, ctx->ac.i32,
792 &ctx->workgroup_ids[i]);
793 }
794 }
795
796 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
797 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
798 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
799 &ctx->local_invocation_ids);
800 break;
801 case MESA_SHADER_VERTEX:
802 declare_global_input_sgprs(ctx, stage, has_previous_stage,
803 previous_stage, &user_sgpr_info,
804 &args, &desc_sets);
805 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
806 previous_stage, &args);
807
808 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
809 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
810 if (ctx->options->key.vs.as_es)
811 add_arg(&args, ARG_SGPR, ctx->ac.i32,
812 &ctx->es2gs_offset);
813 else if (ctx->options->key.vs.as_ls)
814 add_arg(&args, ARG_SGPR, ctx->ac.i32,
815 &ctx->ls_out_layout);
816
817 declare_vs_input_vgprs(ctx, &args);
818 break;
819 case MESA_SHADER_TESS_CTRL:
820 if (has_previous_stage) {
821 // First 6 system regs
822 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
823 add_arg(&args, ARG_SGPR, ctx->ac.i32,
824 &ctx->merged_wave_info);
825 add_arg(&args, ARG_SGPR, ctx->ac.i32,
826 &ctx->tess_factor_offset);
827
828 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
829 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
830 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
831
832 declare_global_input_sgprs(ctx, stage,
833 has_previous_stage,
834 previous_stage,
835 &user_sgpr_info, &args,
836 &desc_sets);
837 declare_vs_specific_input_sgprs(ctx, stage,
838 has_previous_stage,
839 previous_stage, &args);
840
841 add_arg(&args, ARG_SGPR, ctx->ac.i32,
842 &ctx->ls_out_layout);
843
844 add_arg(&args, ARG_SGPR, ctx->ac.i32,
845 &ctx->tcs_offchip_layout);
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->tcs_out_offsets);
848 add_arg(&args, ARG_SGPR, ctx->ac.i32,
849 &ctx->tcs_out_layout);
850 add_arg(&args, ARG_SGPR, ctx->ac.i32,
851 &ctx->tcs_in_layout);
852 if (ctx->shader_info->info.needs_multiview_view_index)
853 add_arg(&args, ARG_SGPR, ctx->ac.i32,
854 &ctx->view_index);
855
856 add_arg(&args, ARG_VGPR, ctx->ac.i32,
857 &ctx->abi.tcs_patch_id);
858 add_arg(&args, ARG_VGPR, ctx->ac.i32,
859 &ctx->abi.tcs_rel_ids);
860
861 declare_vs_input_vgprs(ctx, &args);
862 } else {
863 declare_global_input_sgprs(ctx, stage,
864 has_previous_stage,
865 previous_stage,
866 &user_sgpr_info, &args,
867 &desc_sets);
868
869 add_arg(&args, ARG_SGPR, ctx->ac.i32,
870 &ctx->tcs_offchip_layout);
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->tcs_out_offsets);
873 add_arg(&args, ARG_SGPR, ctx->ac.i32,
874 &ctx->tcs_out_layout);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tcs_in_layout);
877 if (ctx->shader_info->info.needs_multiview_view_index)
878 add_arg(&args, ARG_SGPR, ctx->ac.i32,
879 &ctx->view_index);
880
881 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
882 add_arg(&args, ARG_SGPR, ctx->ac.i32,
883 &ctx->tess_factor_offset);
884 add_arg(&args, ARG_VGPR, ctx->ac.i32,
885 &ctx->abi.tcs_patch_id);
886 add_arg(&args, ARG_VGPR, ctx->ac.i32,
887 &ctx->abi.tcs_rel_ids);
888 }
889 break;
890 case MESA_SHADER_TESS_EVAL:
891 declare_global_input_sgprs(ctx, stage, has_previous_stage,
892 previous_stage, &user_sgpr_info,
893 &args, &desc_sets);
894
895 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
896 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
897 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
898
899 if (ctx->options->key.tes.as_es) {
900 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
901 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
902 add_arg(&args, ARG_SGPR, ctx->ac.i32,
903 &ctx->es2gs_offset);
904 } else {
905 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
906 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
907 }
908 declare_tes_input_vgprs(ctx, &args);
909 break;
910 case MESA_SHADER_GEOMETRY:
911 if (has_previous_stage) {
912 // First 6 system regs
913 add_arg(&args, ARG_SGPR, ctx->ac.i32,
914 &ctx->gs2vs_offset);
915 add_arg(&args, ARG_SGPR, ctx->ac.i32,
916 &ctx->merged_wave_info);
917 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
918
919 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
920 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
921 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
922
923 declare_global_input_sgprs(ctx, stage,
924 has_previous_stage,
925 previous_stage,
926 &user_sgpr_info, &args,
927 &desc_sets);
928
929 if (previous_stage == MESA_SHADER_TESS_EVAL) {
930 add_arg(&args, ARG_SGPR, ctx->ac.i32,
931 &ctx->tcs_offchip_layout);
932 } else {
933 declare_vs_specific_input_sgprs(ctx, stage,
934 has_previous_stage,
935 previous_stage,
936 &args);
937 }
938
939 add_arg(&args, ARG_SGPR, ctx->ac.i32,
940 &ctx->gsvs_ring_stride);
941 add_arg(&args, ARG_SGPR, ctx->ac.i32,
942 &ctx->gsvs_num_entries);
943 if (ctx->shader_info->info.needs_multiview_view_index)
944 add_arg(&args, ARG_SGPR, ctx->ac.i32,
945 &ctx->view_index);
946
947 add_arg(&args, ARG_VGPR, ctx->ac.i32,
948 &ctx->gs_vtx_offset[0]);
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->gs_vtx_offset[2]);
951 add_arg(&args, ARG_VGPR, ctx->ac.i32,
952 &ctx->abi.gs_prim_id);
953 add_arg(&args, ARG_VGPR, ctx->ac.i32,
954 &ctx->abi.gs_invocation_id);
955 add_arg(&args, ARG_VGPR, ctx->ac.i32,
956 &ctx->gs_vtx_offset[4]);
957
958 if (previous_stage == MESA_SHADER_VERTEX) {
959 declare_vs_input_vgprs(ctx, &args);
960 } else {
961 declare_tes_input_vgprs(ctx, &args);
962 }
963 } else {
964 declare_global_input_sgprs(ctx, stage,
965 has_previous_stage,
966 previous_stage,
967 &user_sgpr_info, &args,
968 &desc_sets);
969
970 add_arg(&args, ARG_SGPR, ctx->ac.i32,
971 &ctx->gsvs_ring_stride);
972 add_arg(&args, ARG_SGPR, ctx->ac.i32,
973 &ctx->gsvs_num_entries);
974 if (ctx->shader_info->info.needs_multiview_view_index)
975 add_arg(&args, ARG_SGPR, ctx->ac.i32,
976 &ctx->view_index);
977
978 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
979 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->gs_vtx_offset[0]);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[1]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->abi.gs_prim_id);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[2]);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->gs_vtx_offset[3]);
990 add_arg(&args, ARG_VGPR, ctx->ac.i32,
991 &ctx->gs_vtx_offset[4]);
992 add_arg(&args, ARG_VGPR, ctx->ac.i32,
993 &ctx->gs_vtx_offset[5]);
994 add_arg(&args, ARG_VGPR, ctx->ac.i32,
995 &ctx->abi.gs_invocation_id);
996 }
997 break;
998 case MESA_SHADER_FRAGMENT:
999 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1000 previous_stage, &user_sgpr_info,
1001 &args, &desc_sets);
1002
1003 if (ctx->shader_info->info.ps.needs_sample_positions)
1004 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1005 &ctx->sample_pos_offset);
1006
1007 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1009 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1010 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1011 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1012 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1013 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1014 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1015 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1016 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1017 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1018 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1019 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1020 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1021 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1022 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1023 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1024 break;
1025 default:
1026 unreachable("Shader stage not implemented");
1027 }
1028
1029 ctx->main_function = create_llvm_function(
1030 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1031 ctx->max_workgroup_size,
1032 ctx->options->unsafe_math);
1033 set_llvm_calling_convention(ctx->main_function, stage);
1034
1035
1036 ctx->shader_info->num_input_vgprs = 0;
1037 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1038
1039 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1040
1041 if (ctx->stage != MESA_SHADER_FRAGMENT)
1042 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1043
1044 assign_arguments(ctx->main_function, &args);
1045
1046 user_sgpr_idx = 0;
1047
1048 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1049 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1050 &user_sgpr_idx, 2);
1051 if (ctx->options->supports_spill) {
1052 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1053 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1054 NULL, 0, AC_FUNC_ATTR_READNONE);
1055 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1056 const_array(ctx->ac.v4i32, 16), "");
1057 }
1058 }
1059
1060 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1061 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1062 if (has_previous_stage)
1063 user_sgpr_idx = 0;
1064
1065 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1066 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1067
1068 switch (stage) {
1069 case MESA_SHADER_COMPUTE:
1070 if (ctx->shader_info->info.cs.uses_grid_size) {
1071 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1072 &user_sgpr_idx, 3);
1073 }
1074 break;
1075 case MESA_SHADER_VERTEX:
1076 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1077 previous_stage, &user_sgpr_idx);
1078 if (ctx->view_index)
1079 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1080 if (ctx->options->key.vs.as_ls) {
1081 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1082 &user_sgpr_idx, 1);
1083 }
1084 if (ctx->options->key.vs.as_ls)
1085 ac_declare_lds_as_pointer(&ctx->ac);
1086 break;
1087 case MESA_SHADER_TESS_CTRL:
1088 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1089 previous_stage, &user_sgpr_idx);
1090 if (has_previous_stage)
1091 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1092 &user_sgpr_idx, 1);
1093 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1094 if (ctx->view_index)
1095 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1096 ac_declare_lds_as_pointer(&ctx->ac);
1097 break;
1098 case MESA_SHADER_TESS_EVAL:
1099 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1100 if (ctx->view_index)
1101 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1102 break;
1103 case MESA_SHADER_GEOMETRY:
1104 if (has_previous_stage) {
1105 if (previous_stage == MESA_SHADER_VERTEX)
1106 set_vs_specific_input_locs(ctx, stage,
1107 has_previous_stage,
1108 previous_stage,
1109 &user_sgpr_idx);
1110 else
1111 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1112 &user_sgpr_idx, 1);
1113 }
1114 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1115 &user_sgpr_idx, 2);
1116 if (ctx->view_index)
1117 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1118 if (has_previous_stage)
1119 ac_declare_lds_as_pointer(&ctx->ac);
1120 break;
1121 case MESA_SHADER_FRAGMENT:
1122 if (ctx->shader_info->info.ps.needs_sample_positions) {
1123 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1124 &user_sgpr_idx, 1);
1125 }
1126 break;
1127 default:
1128 unreachable("Shader stage not implemented");
1129 }
1130
1131 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1132 }
1133
1134 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1135 LLVMValueRef value, unsigned count)
1136 {
1137 unsigned num_components = ac_get_llvm_num_components(value);
1138 if (count == num_components)
1139 return value;
1140
1141 LLVMValueRef masks[] = {
1142 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1143 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1144
1145 if (count == 1)
1146 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1147 "");
1148
1149 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1150 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1151 }
1152
1153 static void
1154 build_store_values_extended(struct ac_llvm_context *ac,
1155 LLVMValueRef *values,
1156 unsigned value_count,
1157 unsigned value_stride,
1158 LLVMValueRef vec)
1159 {
1160 LLVMBuilderRef builder = ac->builder;
1161 unsigned i;
1162
1163 for (i = 0; i < value_count; i++) {
1164 LLVMValueRef ptr = values[i * value_stride];
1165 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1166 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1167 LLVMBuildStore(builder, value, ptr);
1168 }
1169 }
1170
1171 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1172 const nir_ssa_def *def)
1173 {
1174 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1175 if (def->num_components > 1) {
1176 type = LLVMVectorType(type, def->num_components);
1177 }
1178 return type;
1179 }
1180
1181 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1182 {
1183 assert(src.is_ssa);
1184 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1185 return (LLVMValueRef)entry->data;
1186 }
1187
1188
1189 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1190 const struct nir_block *b)
1191 {
1192 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1193 return (LLVMBasicBlockRef)entry->data;
1194 }
1195
1196 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1197 nir_alu_src src,
1198 unsigned num_components)
1199 {
1200 LLVMValueRef value = get_src(ctx, src.src);
1201 bool need_swizzle = false;
1202
1203 assert(value);
1204 LLVMTypeRef type = LLVMTypeOf(value);
1205 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1206 ? LLVMGetVectorSize(type)
1207 : 1;
1208
1209 for (unsigned i = 0; i < num_components; ++i) {
1210 assert(src.swizzle[i] < src_components);
1211 if (src.swizzle[i] != i)
1212 need_swizzle = true;
1213 }
1214
1215 if (need_swizzle || num_components != src_components) {
1216 LLVMValueRef masks[] = {
1217 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1218 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1219 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1220 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1221
1222 if (src_components > 1 && num_components == 1) {
1223 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1224 masks[0], "");
1225 } else if (src_components == 1 && num_components > 1) {
1226 LLVMValueRef values[] = {value, value, value, value};
1227 value = ac_build_gather_values(&ctx->ac, values, num_components);
1228 } else {
1229 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1230 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1231 swizzle, "");
1232 }
1233 }
1234 assert(!src.negate);
1235 assert(!src.abs);
1236 return value;
1237 }
1238
1239 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1240 LLVMIntPredicate pred, LLVMValueRef src0,
1241 LLVMValueRef src1)
1242 {
1243 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1244 return LLVMBuildSelect(ctx->builder, result,
1245 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1246 ctx->i32_0, "");
1247 }
1248
1249 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1250 LLVMRealPredicate pred, LLVMValueRef src0,
1251 LLVMValueRef src1)
1252 {
1253 LLVMValueRef result;
1254 src0 = ac_to_float(ctx, src0);
1255 src1 = ac_to_float(ctx, src1);
1256 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1257 return LLVMBuildSelect(ctx->builder, result,
1258 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1259 ctx->i32_0, "");
1260 }
1261
1262 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1263 const char *intrin,
1264 LLVMTypeRef result_type,
1265 LLVMValueRef src0)
1266 {
1267 char name[64];
1268 LLVMValueRef params[] = {
1269 ac_to_float(ctx, src0),
1270 };
1271
1272 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1273 get_elem_bits(ctx, result_type));
1274 assert(length < sizeof(name));
1275 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1276 }
1277
1278 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1279 const char *intrin,
1280 LLVMTypeRef result_type,
1281 LLVMValueRef src0, LLVMValueRef src1)
1282 {
1283 char name[64];
1284 LLVMValueRef params[] = {
1285 ac_to_float(ctx, src0),
1286 ac_to_float(ctx, src1),
1287 };
1288
1289 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1290 get_elem_bits(ctx, result_type));
1291 assert(length < sizeof(name));
1292 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1293 }
1294
1295 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1296 const char *intrin,
1297 LLVMTypeRef result_type,
1298 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1299 {
1300 char name[64];
1301 LLVMValueRef params[] = {
1302 ac_to_float(ctx, src0),
1303 ac_to_float(ctx, src1),
1304 ac_to_float(ctx, src2),
1305 };
1306
1307 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1308 get_elem_bits(ctx, result_type));
1309 assert(length < sizeof(name));
1310 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1311 }
1312
1313 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1314 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1315 {
1316 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1317 ctx->i32_0, "");
1318 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1319 }
1320
1321 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1322 LLVMIntPredicate pred,
1323 LLVMValueRef src0, LLVMValueRef src1)
1324 {
1325 return LLVMBuildSelect(ctx->builder,
1326 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1327 src0,
1328 src1, "");
1329
1330 }
1331 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1332 LLVMValueRef src0)
1333 {
1334 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1335 LLVMBuildNeg(ctx->builder, src0, ""));
1336 }
1337
1338 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1339 LLVMValueRef src0)
1340 {
1341 LLVMValueRef cmp, val;
1342
1343 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1344 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1345 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1346 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1347 return val;
1348 }
1349
1350 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1351 LLVMValueRef src0)
1352 {
1353 LLVMValueRef cmp, val;
1354
1355 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1356 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1357 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1358 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1359 return val;
1360 }
1361
1362 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1363 LLVMValueRef src0)
1364 {
1365 const char *intr = "llvm.floor.f32";
1366 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1367 LLVMValueRef params[] = {
1368 fsrc0,
1369 };
1370 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1371 ctx->f32, params, 1,
1372 AC_FUNC_ATTR_READNONE);
1373 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1374 }
1375
1376 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1377 const char *intrin,
1378 LLVMValueRef src0, LLVMValueRef src1)
1379 {
1380 LLVMTypeRef ret_type;
1381 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1382 LLVMValueRef res;
1383 LLVMValueRef params[] = { src0, src1 };
1384 ret_type = LLVMStructTypeInContext(ctx->context, types,
1385 2, true);
1386
1387 res = ac_build_intrinsic(ctx, intrin, ret_type,
1388 params, 2, AC_FUNC_ATTR_READNONE);
1389
1390 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1391 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1392 return res;
1393 }
1394
1395 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1396 LLVMValueRef src0)
1397 {
1398 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1399 }
1400
1401 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1402 LLVMValueRef src0)
1403 {
1404 src0 = ac_to_float(ctx, src0);
1405 return LLVMBuildSExt(ctx->builder,
1406 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1407 ctx->i32, "");
1408 }
1409
1410 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1411 LLVMValueRef src0)
1412 {
1413 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1414 }
1415
1416 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1417 LLVMValueRef src0)
1418 {
1419 return LLVMBuildSExt(ctx->builder,
1420 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1421 ctx->i32, "");
1422 }
1423
1424 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1425 LLVMValueRef src0)
1426 {
1427 LLVMValueRef result;
1428 LLVMValueRef cond = NULL;
1429
1430 src0 = ac_to_float(&ctx->ac, src0);
1431 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1432
1433 if (ctx->options->chip_class >= VI) {
1434 LLVMValueRef args[2];
1435 /* Check if the result is a denormal - and flush to 0 if so. */
1436 args[0] = result;
1437 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1438 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1439 }
1440
1441 /* need to convert back up to f32 */
1442 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1443
1444 if (ctx->options->chip_class >= VI)
1445 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1446 else {
1447 /* for SI/CIK */
1448 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1449 * so compare the result and flush to 0 if it's smaller.
1450 */
1451 LLVMValueRef temp, cond2;
1452 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1453 ctx->ac.f32, result);
1454 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1455 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1456 temp, "");
1457 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1458 temp, ctx->ac.f32_0, "");
1459 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1460 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1461 }
1462 return result;
1463 }
1464
1465 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1466 LLVMValueRef src0, LLVMValueRef src1)
1467 {
1468 LLVMValueRef dst64, result;
1469 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1470 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1471
1472 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1473 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1474 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1475 return result;
1476 }
1477
1478 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1479 LLVMValueRef src0, LLVMValueRef src1)
1480 {
1481 LLVMValueRef dst64, result;
1482 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1483 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1484
1485 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1486 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1487 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1488 return result;
1489 }
1490
1491 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1492 bool is_signed,
1493 const LLVMValueRef srcs[3])
1494 {
1495 LLVMValueRef result;
1496 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1497
1498 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1499 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1500 return result;
1501 }
1502
1503 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1504 LLVMValueRef src0, LLVMValueRef src1,
1505 LLVMValueRef src2, LLVMValueRef src3)
1506 {
1507 LLVMValueRef bfi_args[3], result;
1508
1509 bfi_args[0] = LLVMBuildShl(ctx->builder,
1510 LLVMBuildSub(ctx->builder,
1511 LLVMBuildShl(ctx->builder,
1512 ctx->i32_1,
1513 src3, ""),
1514 ctx->i32_1, ""),
1515 src2, "");
1516 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1517 bfi_args[2] = src0;
1518
1519 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1520
1521 /* Calculate:
1522 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1523 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1524 */
1525 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1526 LLVMBuildAnd(ctx->builder, bfi_args[0],
1527 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1528
1529 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1530 return result;
1531 }
1532
1533 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1534 LLVMValueRef src0)
1535 {
1536 LLVMValueRef comp[2];
1537
1538 src0 = ac_to_float(ctx, src0);
1539 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1540 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1541
1542 return ac_build_cvt_pkrtz_f16(ctx, comp);
1543 }
1544
1545 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1546 LLVMValueRef src0)
1547 {
1548 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1549 LLVMValueRef temps[2], result, val;
1550 int i;
1551
1552 for (i = 0; i < 2; i++) {
1553 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1554 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1555 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1556 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1557 }
1558
1559 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1560 ctx->i32_0, "");
1561 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1562 ctx->i32_1, "");
1563 return result;
1564 }
1565
1566 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1567 nir_op op,
1568 LLVMValueRef src0)
1569 {
1570 unsigned mask;
1571 int idx;
1572 LLVMValueRef result;
1573
1574 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1575 mask = AC_TID_MASK_LEFT;
1576 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1577 mask = AC_TID_MASK_TOP;
1578 else
1579 mask = AC_TID_MASK_TOP_LEFT;
1580
1581 /* for DDX we want to next X pixel, DDY next Y pixel. */
1582 if (op == nir_op_fddx_fine ||
1583 op == nir_op_fddx_coarse ||
1584 op == nir_op_fddx)
1585 idx = 1;
1586 else
1587 idx = 2;
1588
1589 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1590 return result;
1591 }
1592
1593 /*
1594 * this takes an I,J coordinate pair,
1595 * and works out the X and Y derivatives.
1596 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1597 */
1598 static LLVMValueRef emit_ddxy_interp(
1599 struct ac_nir_context *ctx,
1600 LLVMValueRef interp_ij)
1601 {
1602 LLVMValueRef result[4], a;
1603 unsigned i;
1604
1605 for (i = 0; i < 2; i++) {
1606 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1607 LLVMConstInt(ctx->ac.i32, i, false), "");
1608 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1609 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1610 }
1611 return ac_build_gather_values(&ctx->ac, result, 4);
1612 }
1613
1614 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1615 {
1616 LLVMValueRef src[4], result = NULL;
1617 unsigned num_components = instr->dest.dest.ssa.num_components;
1618 unsigned src_components;
1619 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1620
1621 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1622 switch (instr->op) {
1623 case nir_op_vec2:
1624 case nir_op_vec3:
1625 case nir_op_vec4:
1626 src_components = 1;
1627 break;
1628 case nir_op_pack_half_2x16:
1629 src_components = 2;
1630 break;
1631 case nir_op_unpack_half_2x16:
1632 src_components = 1;
1633 break;
1634 default:
1635 src_components = num_components;
1636 break;
1637 }
1638 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1639 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1640
1641 switch (instr->op) {
1642 case nir_op_fmov:
1643 case nir_op_imov:
1644 result = src[0];
1645 break;
1646 case nir_op_fneg:
1647 src[0] = ac_to_float(&ctx->ac, src[0]);
1648 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1649 break;
1650 case nir_op_ineg:
1651 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1652 break;
1653 case nir_op_inot:
1654 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1655 break;
1656 case nir_op_iadd:
1657 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1658 break;
1659 case nir_op_fadd:
1660 src[0] = ac_to_float(&ctx->ac, src[0]);
1661 src[1] = ac_to_float(&ctx->ac, src[1]);
1662 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1663 break;
1664 case nir_op_fsub:
1665 src[0] = ac_to_float(&ctx->ac, src[0]);
1666 src[1] = ac_to_float(&ctx->ac, src[1]);
1667 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1668 break;
1669 case nir_op_isub:
1670 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1671 break;
1672 case nir_op_imul:
1673 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1674 break;
1675 case nir_op_imod:
1676 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1677 break;
1678 case nir_op_umod:
1679 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1680 break;
1681 case nir_op_fmod:
1682 src[0] = ac_to_float(&ctx->ac, src[0]);
1683 src[1] = ac_to_float(&ctx->ac, src[1]);
1684 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1685 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1686 ac_to_float_type(&ctx->ac, def_type), result);
1687 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1688 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1689 break;
1690 case nir_op_frem:
1691 src[0] = ac_to_float(&ctx->ac, src[0]);
1692 src[1] = ac_to_float(&ctx->ac, src[1]);
1693 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1694 break;
1695 case nir_op_irem:
1696 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1697 break;
1698 case nir_op_idiv:
1699 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1700 break;
1701 case nir_op_udiv:
1702 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1703 break;
1704 case nir_op_fmul:
1705 src[0] = ac_to_float(&ctx->ac, src[0]);
1706 src[1] = ac_to_float(&ctx->ac, src[1]);
1707 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1708 break;
1709 case nir_op_fdiv:
1710 src[0] = ac_to_float(&ctx->ac, src[0]);
1711 src[1] = ac_to_float(&ctx->ac, src[1]);
1712 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1713 break;
1714 case nir_op_frcp:
1715 src[0] = ac_to_float(&ctx->ac, src[0]);
1716 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1717 break;
1718 case nir_op_iand:
1719 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1720 break;
1721 case nir_op_ior:
1722 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1723 break;
1724 case nir_op_ixor:
1725 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1726 break;
1727 case nir_op_ishl:
1728 result = LLVMBuildShl(ctx->ac.builder, src[0],
1729 LLVMBuildZExt(ctx->ac.builder, src[1],
1730 LLVMTypeOf(src[0]), ""),
1731 "");
1732 break;
1733 case nir_op_ishr:
1734 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1735 LLVMBuildZExt(ctx->ac.builder, src[1],
1736 LLVMTypeOf(src[0]), ""),
1737 "");
1738 break;
1739 case nir_op_ushr:
1740 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1741 LLVMBuildZExt(ctx->ac.builder, src[1],
1742 LLVMTypeOf(src[0]), ""),
1743 "");
1744 break;
1745 case nir_op_ilt:
1746 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1747 break;
1748 case nir_op_ine:
1749 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1750 break;
1751 case nir_op_ieq:
1752 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1753 break;
1754 case nir_op_ige:
1755 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1756 break;
1757 case nir_op_ult:
1758 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1759 break;
1760 case nir_op_uge:
1761 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1762 break;
1763 case nir_op_feq:
1764 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1765 break;
1766 case nir_op_fne:
1767 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1768 break;
1769 case nir_op_flt:
1770 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1771 break;
1772 case nir_op_fge:
1773 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1774 break;
1775 case nir_op_fabs:
1776 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1777 ac_to_float_type(&ctx->ac, def_type), src[0]);
1778 break;
1779 case nir_op_iabs:
1780 result = emit_iabs(&ctx->ac, src[0]);
1781 break;
1782 case nir_op_imax:
1783 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1784 break;
1785 case nir_op_imin:
1786 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1787 break;
1788 case nir_op_umax:
1789 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1790 break;
1791 case nir_op_umin:
1792 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1793 break;
1794 case nir_op_isign:
1795 result = emit_isign(&ctx->ac, src[0]);
1796 break;
1797 case nir_op_fsign:
1798 src[0] = ac_to_float(&ctx->ac, src[0]);
1799 result = emit_fsign(&ctx->ac, src[0]);
1800 break;
1801 case nir_op_ffloor:
1802 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1803 ac_to_float_type(&ctx->ac, def_type), src[0]);
1804 break;
1805 case nir_op_ftrunc:
1806 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1807 ac_to_float_type(&ctx->ac, def_type), src[0]);
1808 break;
1809 case nir_op_fceil:
1810 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1811 ac_to_float_type(&ctx->ac, def_type), src[0]);
1812 break;
1813 case nir_op_fround_even:
1814 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1815 ac_to_float_type(&ctx->ac, def_type),src[0]);
1816 break;
1817 case nir_op_ffract:
1818 result = emit_ffract(&ctx->ac, src[0]);
1819 break;
1820 case nir_op_fsin:
1821 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1822 ac_to_float_type(&ctx->ac, def_type), src[0]);
1823 break;
1824 case nir_op_fcos:
1825 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1826 ac_to_float_type(&ctx->ac, def_type), src[0]);
1827 break;
1828 case nir_op_fsqrt:
1829 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1830 ac_to_float_type(&ctx->ac, def_type), src[0]);
1831 break;
1832 case nir_op_fexp2:
1833 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1834 ac_to_float_type(&ctx->ac, def_type), src[0]);
1835 break;
1836 case nir_op_flog2:
1837 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1838 ac_to_float_type(&ctx->ac, def_type), src[0]);
1839 break;
1840 case nir_op_frsq:
1841 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1842 ac_to_float_type(&ctx->ac, def_type), src[0]);
1843 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1844 break;
1845 case nir_op_fpow:
1846 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1847 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1848 break;
1849 case nir_op_fmax:
1850 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1851 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1852 if (instr->dest.dest.ssa.bit_size == 32)
1853 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1854 ac_to_float_type(&ctx->ac, def_type),
1855 result);
1856 break;
1857 case nir_op_fmin:
1858 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1859 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1860 if (instr->dest.dest.ssa.bit_size == 32)
1861 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1862 ac_to_float_type(&ctx->ac, def_type),
1863 result);
1864 break;
1865 case nir_op_ffma:
1866 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1867 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1868 break;
1869 case nir_op_ibitfield_extract:
1870 result = emit_bitfield_extract(&ctx->ac, true, src);
1871 break;
1872 case nir_op_ubitfield_extract:
1873 result = emit_bitfield_extract(&ctx->ac, false, src);
1874 break;
1875 case nir_op_bitfield_insert:
1876 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1877 break;
1878 case nir_op_bitfield_reverse:
1879 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1880 break;
1881 case nir_op_bit_count:
1882 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1883 break;
1884 case nir_op_vec2:
1885 case nir_op_vec3:
1886 case nir_op_vec4:
1887 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1888 src[i] = ac_to_integer(&ctx->ac, src[i]);
1889 result = ac_build_gather_values(&ctx->ac, src, num_components);
1890 break;
1891 case nir_op_f2i32:
1892 case nir_op_f2i64:
1893 src[0] = ac_to_float(&ctx->ac, src[0]);
1894 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1895 break;
1896 case nir_op_f2u32:
1897 case nir_op_f2u64:
1898 src[0] = ac_to_float(&ctx->ac, src[0]);
1899 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1900 break;
1901 case nir_op_i2f32:
1902 case nir_op_i2f64:
1903 src[0] = ac_to_integer(&ctx->ac, src[0]);
1904 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1905 break;
1906 case nir_op_u2f32:
1907 case nir_op_u2f64:
1908 src[0] = ac_to_integer(&ctx->ac, src[0]);
1909 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1910 break;
1911 case nir_op_f2f64:
1912 src[0] = ac_to_float(&ctx->ac, src[0]);
1913 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1914 break;
1915 case nir_op_f2f32:
1916 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1917 break;
1918 case nir_op_u2u32:
1919 case nir_op_u2u64:
1920 src[0] = ac_to_integer(&ctx->ac, src[0]);
1921 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1922 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1923 else
1924 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1925 break;
1926 case nir_op_i2i32:
1927 case nir_op_i2i64:
1928 src[0] = ac_to_integer(&ctx->ac, src[0]);
1929 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1930 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1931 else
1932 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1933 break;
1934 case nir_op_bcsel:
1935 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1936 break;
1937 case nir_op_find_lsb:
1938 src[0] = ac_to_integer(&ctx->ac, src[0]);
1939 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1940 break;
1941 case nir_op_ufind_msb:
1942 src[0] = ac_to_integer(&ctx->ac, src[0]);
1943 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1944 break;
1945 case nir_op_ifind_msb:
1946 src[0] = ac_to_integer(&ctx->ac, src[0]);
1947 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1948 break;
1949 case nir_op_uadd_carry:
1950 src[0] = ac_to_integer(&ctx->ac, src[0]);
1951 src[1] = ac_to_integer(&ctx->ac, src[1]);
1952 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1953 break;
1954 case nir_op_usub_borrow:
1955 src[0] = ac_to_integer(&ctx->ac, src[0]);
1956 src[1] = ac_to_integer(&ctx->ac, src[1]);
1957 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1958 break;
1959 case nir_op_b2f:
1960 result = emit_b2f(&ctx->ac, src[0]);
1961 break;
1962 case nir_op_f2b:
1963 result = emit_f2b(&ctx->ac, src[0]);
1964 break;
1965 case nir_op_b2i:
1966 result = emit_b2i(&ctx->ac, src[0]);
1967 break;
1968 case nir_op_i2b:
1969 src[0] = ac_to_integer(&ctx->ac, src[0]);
1970 result = emit_i2b(&ctx->ac, src[0]);
1971 break;
1972 case nir_op_fquantize2f16:
1973 result = emit_f2f16(ctx->nctx, src[0]);
1974 break;
1975 case nir_op_umul_high:
1976 src[0] = ac_to_integer(&ctx->ac, src[0]);
1977 src[1] = ac_to_integer(&ctx->ac, src[1]);
1978 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1979 break;
1980 case nir_op_imul_high:
1981 src[0] = ac_to_integer(&ctx->ac, src[0]);
1982 src[1] = ac_to_integer(&ctx->ac, src[1]);
1983 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1984 break;
1985 case nir_op_pack_half_2x16:
1986 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1987 break;
1988 case nir_op_unpack_half_2x16:
1989 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1990 break;
1991 case nir_op_fddx:
1992 case nir_op_fddy:
1993 case nir_op_fddx_fine:
1994 case nir_op_fddy_fine:
1995 case nir_op_fddx_coarse:
1996 case nir_op_fddy_coarse:
1997 result = emit_ddxy(ctx, instr->op, src[0]);
1998 break;
1999
2000 case nir_op_unpack_64_2x32_split_x: {
2001 assert(instr->src[0].src.ssa->num_components == 1);
2002 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2003 ctx->ac.v2i32,
2004 "");
2005 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2006 ctx->ac.i32_0, "");
2007 break;
2008 }
2009
2010 case nir_op_unpack_64_2x32_split_y: {
2011 assert(instr->src[0].src.ssa->num_components == 1);
2012 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2013 ctx->ac.v2i32,
2014 "");
2015 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2016 ctx->ac.i32_1, "");
2017 break;
2018 }
2019
2020 case nir_op_pack_64_2x32_split: {
2021 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2022 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2023 src[0], ctx->ac.i32_0, "");
2024 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2025 src[1], ctx->ac.i32_1, "");
2026 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2027 break;
2028 }
2029
2030 default:
2031 fprintf(stderr, "Unknown NIR alu instr: ");
2032 nir_print_instr(&instr->instr, stderr);
2033 fprintf(stderr, "\n");
2034 abort();
2035 }
2036
2037 if (result) {
2038 assert(instr->dest.dest.is_ssa);
2039 result = ac_to_integer(&ctx->ac, result);
2040 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2041 result);
2042 }
2043 }
2044
2045 static void visit_load_const(struct ac_nir_context *ctx,
2046 const nir_load_const_instr *instr)
2047 {
2048 LLVMValueRef values[4], value = NULL;
2049 LLVMTypeRef element_type =
2050 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2051
2052 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2053 switch (instr->def.bit_size) {
2054 case 32:
2055 values[i] = LLVMConstInt(element_type,
2056 instr->value.u32[i], false);
2057 break;
2058 case 64:
2059 values[i] = LLVMConstInt(element_type,
2060 instr->value.u64[i], false);
2061 break;
2062 default:
2063 fprintf(stderr,
2064 "unsupported nir load_const bit_size: %d\n",
2065 instr->def.bit_size);
2066 abort();
2067 }
2068 }
2069 if (instr->def.num_components > 1) {
2070 value = LLVMConstVector(values, instr->def.num_components);
2071 } else
2072 value = values[0];
2073
2074 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2075 }
2076
2077 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2078 LLVMTypeRef type)
2079 {
2080 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2081 return LLVMBuildBitCast(ctx->builder, ptr,
2082 LLVMPointerType(type, addr_space), "");
2083 }
2084
2085 static LLVMValueRef
2086 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2087 {
2088 LLVMValueRef size =
2089 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2090 LLVMConstInt(ctx->ac.i32, 2, false), "");
2091
2092 /* VI only */
2093 if (ctx->ac.chip_class == VI && in_elements) {
2094 /* On VI, the descriptor contains the size in bytes,
2095 * but TXQ must return the size in elements.
2096 * The stride is always non-zero for resources using TXQ.
2097 */
2098 LLVMValueRef stride =
2099 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2100 ctx->ac.i32_1, "");
2101 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2102 LLVMConstInt(ctx->ac.i32, 16, false), "");
2103 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2104 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2105
2106 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2107 }
2108 return size;
2109 }
2110
2111 /**
2112 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2113 * intrinsic names).
2114 */
2115 static void build_int_type_name(
2116 LLVMTypeRef type,
2117 char *buf, unsigned bufsize)
2118 {
2119 assert(bufsize >= 6);
2120
2121 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2122 snprintf(buf, bufsize, "v%ui32",
2123 LLVMGetVectorSize(type));
2124 else
2125 strcpy(buf, "i32");
2126 }
2127
2128 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2129 struct ac_image_args *args,
2130 const nir_tex_instr *instr)
2131 {
2132 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2133 LLVMValueRef coord = args->addr;
2134 LLVMValueRef half_texel[2];
2135 LLVMValueRef compare_cube_wa = NULL;
2136 LLVMValueRef result;
2137 int c;
2138 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2139
2140 //TODO Rect
2141 {
2142 struct ac_image_args txq_args = { 0 };
2143
2144 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2145 txq_args.opcode = ac_image_get_resinfo;
2146 txq_args.dmask = 0xf;
2147 txq_args.addr = ctx->i32_0;
2148 txq_args.resource = args->resource;
2149 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2150
2151 for (c = 0; c < 2; c++) {
2152 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2153 LLVMConstInt(ctx->i32, c, false), "");
2154 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2155 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2156 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2157 LLVMConstReal(ctx->f32, -0.5), "");
2158 }
2159 }
2160
2161 LLVMValueRef orig_coords = args->addr;
2162
2163 for (c = 0; c < 2; c++) {
2164 LLVMValueRef tmp;
2165 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2166 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2167 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2168 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2169 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2170 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2171 }
2172
2173
2174 /*
2175 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2176 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2177 * workaround by sampling using a scaled type and converting.
2178 * This is taken from amdgpu-pro shaders.
2179 */
2180 /* NOTE this produces some ugly code compared to amdgpu-pro,
2181 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2182 * and then reads them back. -pro generates two selects,
2183 * one s_cmp for the descriptor rewriting
2184 * one v_cmp for the coordinate and result changes.
2185 */
2186 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2187 LLVMValueRef tmp, tmp2;
2188
2189 /* workaround 8/8/8/8 uint/sint cube gather bug */
2190 /* first detect it then change to a scaled read and f2i */
2191 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2192 tmp2 = tmp;
2193
2194 /* extract the DATA_FORMAT */
2195 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2196 LLVMConstInt(ctx->i32, 6, false), false);
2197
2198 /* is the DATA_FORMAT == 8_8_8_8 */
2199 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2200
2201 if (stype == GLSL_TYPE_UINT)
2202 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2203 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2204 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2205 else
2206 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2207 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2208 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2209
2210 /* replace the NUM FORMAT in the descriptor */
2211 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2212 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2213
2214 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2215
2216 /* don't modify the coordinates for this case */
2217 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2218 }
2219 args->addr = coord;
2220 result = ac_build_image_opcode(ctx, args);
2221
2222 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2223 LLVMValueRef tmp, tmp2;
2224
2225 /* if the cube workaround is in place, f2i the result. */
2226 for (c = 0; c < 4; c++) {
2227 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2228 if (stype == GLSL_TYPE_UINT)
2229 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2230 else
2231 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2232 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2233 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2234 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2235 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2236 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2237 }
2238 }
2239 return result;
2240 }
2241
2242 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2243 const nir_tex_instr *instr,
2244 bool lod_is_zero,
2245 struct ac_image_args *args)
2246 {
2247 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2248 return ac_build_buffer_load_format(&ctx->ac,
2249 args->resource,
2250 args->addr,
2251 ctx->ac.i32_0,
2252 true);
2253 }
2254
2255 args->opcode = ac_image_sample;
2256 args->compare = instr->is_shadow;
2257
2258 switch (instr->op) {
2259 case nir_texop_txf:
2260 case nir_texop_txf_ms:
2261 case nir_texop_samples_identical:
2262 args->opcode = lod_is_zero ||
2263 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2264 ac_image_load : ac_image_load_mip;
2265 args->compare = false;
2266 args->offset = false;
2267 break;
2268 case nir_texop_txb:
2269 args->bias = true;
2270 break;
2271 case nir_texop_txl:
2272 if (lod_is_zero)
2273 args->level_zero = true;
2274 else
2275 args->lod = true;
2276 break;
2277 case nir_texop_txs:
2278 case nir_texop_query_levels:
2279 args->opcode = ac_image_get_resinfo;
2280 break;
2281 case nir_texop_tex:
2282 if (ctx->stage != MESA_SHADER_FRAGMENT)
2283 args->level_zero = true;
2284 break;
2285 case nir_texop_txd:
2286 args->deriv = true;
2287 break;
2288 case nir_texop_tg4:
2289 args->opcode = ac_image_gather4;
2290 args->level_zero = true;
2291 break;
2292 case nir_texop_lod:
2293 args->opcode = ac_image_get_lod;
2294 args->compare = false;
2295 args->offset = false;
2296 break;
2297 default:
2298 break;
2299 }
2300
2301 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2302 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2303 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2304 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2305 }
2306 }
2307 return ac_build_image_opcode(&ctx->ac, args);
2308 }
2309
2310 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2311 nir_intrinsic_instr *instr)
2312 {
2313 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2314 unsigned desc_set = nir_intrinsic_desc_set(instr);
2315 unsigned binding = nir_intrinsic_binding(instr);
2316 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2317 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2318 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2319 unsigned base_offset = layout->binding[binding].offset;
2320 LLVMValueRef offset, stride;
2321
2322 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2323 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2324 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2325 layout->binding[binding].dynamic_offset_offset;
2326 desc_ptr = ctx->push_constants;
2327 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2328 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2329 } else
2330 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2331
2332 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2333 index = LLVMBuildMul(ctx->builder, index, stride, "");
2334 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2335
2336 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2337 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2338 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2339
2340 return desc_ptr;
2341 }
2342
2343 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2344 nir_intrinsic_instr *instr)
2345 {
2346 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2347 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2348
2349 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2350 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2351 return result;
2352 }
2353
2354 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2355 nir_intrinsic_instr *instr)
2356 {
2357 LLVMValueRef ptr, addr;
2358
2359 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2360 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2361
2362 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2363 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2364
2365 return LLVMBuildLoad(ctx->builder, ptr, "");
2366 }
2367
2368 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2369 const nir_intrinsic_instr *instr)
2370 {
2371 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2372
2373 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2374 }
2375 static void visit_store_ssbo(struct ac_nir_context *ctx,
2376 nir_intrinsic_instr *instr)
2377 {
2378 const char *store_name;
2379 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2380 LLVMTypeRef data_type = ctx->ac.f32;
2381 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2382 int components_32bit = elem_size_mult * instr->num_components;
2383 unsigned writemask = nir_intrinsic_write_mask(instr);
2384 LLVMValueRef base_data, base_offset;
2385 LLVMValueRef params[6];
2386
2387 params[1] = ctx->abi->load_ssbo(ctx->abi,
2388 get_src(ctx, instr->src[1]), true);
2389 params[2] = ctx->ac.i32_0; /* vindex */
2390 params[4] = ctx->ac.i1false; /* glc */
2391 params[5] = ctx->ac.i1false; /* slc */
2392
2393 if (components_32bit > 1)
2394 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2395
2396 base_data = ac_to_float(&ctx->ac, src_data);
2397 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2398 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2399 data_type, "");
2400 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2401 while (writemask) {
2402 int start, count;
2403 LLVMValueRef data;
2404 LLVMValueRef offset;
2405 LLVMValueRef tmp;
2406 u_bit_scan_consecutive_range(&writemask, &start, &count);
2407
2408 /* Due to an LLVM limitation, split 3-element writes
2409 * into a 2-element and a 1-element write. */
2410 if (count == 3) {
2411 writemask |= 1 << (start + 2);
2412 count = 2;
2413 }
2414
2415 start *= elem_size_mult;
2416 count *= elem_size_mult;
2417
2418 if (count > 4) {
2419 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2420 count = 4;
2421 }
2422
2423 if (count == 4) {
2424 store_name = "llvm.amdgcn.buffer.store.v4f32";
2425 data = base_data;
2426 } else if (count == 2) {
2427 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2428 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2429 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2430 ctx->ac.i32_0, "");
2431
2432 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2433 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2434 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2435 ctx->ac.i32_1, "");
2436 store_name = "llvm.amdgcn.buffer.store.v2f32";
2437
2438 } else {
2439 assert(count == 1);
2440 if (ac_get_llvm_num_components(base_data) > 1)
2441 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2442 LLVMConstInt(ctx->ac.i32, start, false), "");
2443 else
2444 data = base_data;
2445 store_name = "llvm.amdgcn.buffer.store.f32";
2446 }
2447
2448 offset = base_offset;
2449 if (start != 0) {
2450 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2451 }
2452 params[0] = data;
2453 params[3] = offset;
2454 ac_build_intrinsic(&ctx->ac, store_name,
2455 ctx->ac.voidt, params, 6, 0);
2456 }
2457 }
2458
2459 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2460 const nir_intrinsic_instr *instr)
2461 {
2462 const char *name;
2463 LLVMValueRef params[6];
2464 int arg_count = 0;
2465
2466 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2467 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2468 }
2469 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2470 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2471 get_src(ctx, instr->src[0]),
2472 true);
2473 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2474 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2475 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2476
2477 switch (instr->intrinsic) {
2478 case nir_intrinsic_ssbo_atomic_add:
2479 name = "llvm.amdgcn.buffer.atomic.add";
2480 break;
2481 case nir_intrinsic_ssbo_atomic_imin:
2482 name = "llvm.amdgcn.buffer.atomic.smin";
2483 break;
2484 case nir_intrinsic_ssbo_atomic_umin:
2485 name = "llvm.amdgcn.buffer.atomic.umin";
2486 break;
2487 case nir_intrinsic_ssbo_atomic_imax:
2488 name = "llvm.amdgcn.buffer.atomic.smax";
2489 break;
2490 case nir_intrinsic_ssbo_atomic_umax:
2491 name = "llvm.amdgcn.buffer.atomic.umax";
2492 break;
2493 case nir_intrinsic_ssbo_atomic_and:
2494 name = "llvm.amdgcn.buffer.atomic.and";
2495 break;
2496 case nir_intrinsic_ssbo_atomic_or:
2497 name = "llvm.amdgcn.buffer.atomic.or";
2498 break;
2499 case nir_intrinsic_ssbo_atomic_xor:
2500 name = "llvm.amdgcn.buffer.atomic.xor";
2501 break;
2502 case nir_intrinsic_ssbo_atomic_exchange:
2503 name = "llvm.amdgcn.buffer.atomic.swap";
2504 break;
2505 case nir_intrinsic_ssbo_atomic_comp_swap:
2506 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2507 break;
2508 default:
2509 abort();
2510 }
2511
2512 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2513 }
2514
2515 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2516 const nir_intrinsic_instr *instr)
2517 {
2518 LLVMValueRef results[2];
2519 int load_components;
2520 int num_components = instr->num_components;
2521 if (instr->dest.ssa.bit_size == 64)
2522 num_components *= 2;
2523
2524 for (int i = 0; i < num_components; i += load_components) {
2525 load_components = MIN2(num_components - i, 4);
2526 const char *load_name;
2527 LLVMTypeRef data_type = ctx->ac.f32;
2528 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2529 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2530
2531 if (load_components == 3)
2532 data_type = LLVMVectorType(ctx->ac.f32, 4);
2533 else if (load_components > 1)
2534 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2535
2536 if (load_components >= 3)
2537 load_name = "llvm.amdgcn.buffer.load.v4f32";
2538 else if (load_components == 2)
2539 load_name = "llvm.amdgcn.buffer.load.v2f32";
2540 else if (load_components == 1)
2541 load_name = "llvm.amdgcn.buffer.load.f32";
2542 else
2543 unreachable("unhandled number of components");
2544
2545 LLVMValueRef params[] = {
2546 ctx->abi->load_ssbo(ctx->abi,
2547 get_src(ctx, instr->src[0]),
2548 false),
2549 ctx->ac.i32_0,
2550 offset,
2551 ctx->ac.i1false,
2552 ctx->ac.i1false,
2553 };
2554
2555 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2556
2557 }
2558
2559 assume(results[0]);
2560 LLVMValueRef ret = results[0];
2561 if (num_components > 4 || num_components == 3) {
2562 LLVMValueRef masks[] = {
2563 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2564 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2565 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2566 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2567 };
2568
2569 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2570 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2571 results[num_components > 4 ? 1 : 0], swizzle, "");
2572 }
2573
2574 return LLVMBuildBitCast(ctx->ac.builder, ret,
2575 get_def_type(ctx, &instr->dest.ssa), "");
2576 }
2577
2578 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2579 const nir_intrinsic_instr *instr)
2580 {
2581 LLVMValueRef results[8], ret;
2582 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2583 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2584 int num_components = instr->num_components;
2585
2586 if (ctx->abi->load_ubo)
2587 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2588
2589 if (instr->dest.ssa.bit_size == 64)
2590 num_components *= 2;
2591
2592 for (unsigned i = 0; i < num_components; ++i) {
2593 LLVMValueRef params[] = {
2594 rsrc,
2595 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2596 offset, "")
2597 };
2598 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2599 params, 2,
2600 AC_FUNC_ATTR_READNONE |
2601 AC_FUNC_ATTR_LEGACY);
2602 }
2603
2604
2605 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2606 return LLVMBuildBitCast(ctx->ac.builder, ret,
2607 get_def_type(ctx, &instr->dest.ssa), "");
2608 }
2609
2610 static void
2611 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2612 bool vs_in, unsigned *vertex_index_out,
2613 LLVMValueRef *vertex_index_ref,
2614 unsigned *const_out, LLVMValueRef *indir_out)
2615 {
2616 unsigned const_offset = 0;
2617 nir_deref *tail = &deref->deref;
2618 LLVMValueRef offset = NULL;
2619
2620 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2621 tail = tail->child;
2622 nir_deref_array *deref_array = nir_deref_as_array(tail);
2623 if (vertex_index_out)
2624 *vertex_index_out = deref_array->base_offset;
2625
2626 if (vertex_index_ref) {
2627 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2628 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2629 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2630 }
2631 *vertex_index_ref = vtx;
2632 }
2633 }
2634
2635 if (deref->var->data.compact) {
2636 assert(tail->child->deref_type == nir_deref_type_array);
2637 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2638 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2639 /* We always lower indirect dereferences for "compact" array vars. */
2640 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2641
2642 const_offset = deref_array->base_offset;
2643 goto out;
2644 }
2645
2646 while (tail->child != NULL) {
2647 const struct glsl_type *parent_type = tail->type;
2648 tail = tail->child;
2649
2650 if (tail->deref_type == nir_deref_type_array) {
2651 nir_deref_array *deref_array = nir_deref_as_array(tail);
2652 LLVMValueRef index, stride, local_offset;
2653 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2654
2655 const_offset += size * deref_array->base_offset;
2656 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2657 continue;
2658
2659 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2660 index = get_src(ctx, deref_array->indirect);
2661 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2662 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2663
2664 if (offset)
2665 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2666 else
2667 offset = local_offset;
2668 } else if (tail->deref_type == nir_deref_type_struct) {
2669 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2670
2671 for (unsigned i = 0; i < deref_struct->index; i++) {
2672 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2673 const_offset += glsl_count_attribute_slots(ft, vs_in);
2674 }
2675 } else
2676 unreachable("unsupported deref type");
2677
2678 }
2679 out:
2680 if (const_offset && offset)
2681 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2682 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2683 "");
2684
2685 *const_out = const_offset;
2686 *indir_out = offset;
2687 }
2688
2689
2690 /* The offchip buffer layout for TCS->TES is
2691 *
2692 * - attribute 0 of patch 0 vertex 0
2693 * - attribute 0 of patch 0 vertex 1
2694 * - attribute 0 of patch 0 vertex 2
2695 * ...
2696 * - attribute 0 of patch 1 vertex 0
2697 * - attribute 0 of patch 1 vertex 1
2698 * ...
2699 * - attribute 1 of patch 0 vertex 0
2700 * - attribute 1 of patch 0 vertex 1
2701 * ...
2702 * - per patch attribute 0 of patch 0
2703 * - per patch attribute 0 of patch 1
2704 * ...
2705 *
2706 * Note that every attribute has 4 components.
2707 */
2708 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2709 LLVMValueRef vertex_index,
2710 LLVMValueRef param_index)
2711 {
2712 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2713 LLVMValueRef param_stride, constant16;
2714 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2715
2716 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2717 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2718 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2719 num_patches, "");
2720
2721 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2722 if (vertex_index) {
2723 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2724 vertices_per_patch, "");
2725
2726 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2727 vertex_index, "");
2728
2729 param_stride = total_vertices;
2730 } else {
2731 base_addr = rel_patch_id;
2732 param_stride = num_patches;
2733 }
2734
2735 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2736 LLVMBuildMul(ctx->builder, param_index,
2737 param_stride, ""), "");
2738
2739 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2740
2741 if (!vertex_index) {
2742 LLVMValueRef patch_data_offset =
2743 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2744
2745 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2746 patch_data_offset, "");
2747 }
2748 return base_addr;
2749 }
2750
2751 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2752 unsigned param,
2753 unsigned const_index,
2754 bool is_compact,
2755 LLVMValueRef vertex_index,
2756 LLVMValueRef indir_index)
2757 {
2758 LLVMValueRef param_index;
2759
2760 if (indir_index)
2761 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2762 indir_index, "");
2763 else {
2764 if (const_index && !is_compact)
2765 param += const_index;
2766 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2767 }
2768 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2769 }
2770
2771 static void
2772 mark_tess_output(struct nir_to_llvm_context *ctx,
2773 bool is_patch, uint32_t param)
2774
2775 {
2776 if (is_patch) {
2777 ctx->tess_patch_outputs_written |= (1ull << param);
2778 } else
2779 ctx->tess_outputs_written |= (1ull << param);
2780 }
2781
2782 static LLVMValueRef
2783 get_dw_address(struct nir_to_llvm_context *ctx,
2784 LLVMValueRef dw_addr,
2785 unsigned param,
2786 unsigned const_index,
2787 bool compact_const_index,
2788 LLVMValueRef vertex_index,
2789 LLVMValueRef stride,
2790 LLVMValueRef indir_index)
2791
2792 {
2793
2794 if (vertex_index) {
2795 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2796 LLVMBuildMul(ctx->builder,
2797 vertex_index,
2798 stride, ""), "");
2799 }
2800
2801 if (indir_index)
2802 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2803 LLVMBuildMul(ctx->builder, indir_index,
2804 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2805 else if (const_index && !compact_const_index)
2806 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2807 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2808
2809 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2810 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2811
2812 if (const_index && compact_const_index)
2813 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2814 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2815 return dw_addr;
2816 }
2817
2818 static LLVMValueRef
2819 load_tcs_input(struct ac_shader_abi *abi,
2820 LLVMValueRef vertex_index,
2821 LLVMValueRef indir_index,
2822 unsigned const_index,
2823 unsigned location,
2824 unsigned driver_location,
2825 unsigned component,
2826 unsigned num_components,
2827 bool is_patch,
2828 bool is_compact)
2829 {
2830 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2831 LLVMValueRef dw_addr, stride;
2832 LLVMValueRef value[4], result;
2833 unsigned param = shader_io_get_unique_index(location);
2834
2835 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2836 dw_addr = get_tcs_in_current_patch_offset(ctx);
2837 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2838 indir_index);
2839
2840 for (unsigned i = 0; i < num_components + component; i++) {
2841 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2842 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2843 ctx->ac.i32_1, "");
2844 }
2845 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2846 return result;
2847 }
2848
2849 static LLVMValueRef
2850 load_tcs_output(struct nir_to_llvm_context *ctx,
2851 nir_intrinsic_instr *instr)
2852 {
2853 LLVMValueRef dw_addr;
2854 LLVMValueRef stride = NULL;
2855 LLVMValueRef value[4], result;
2856 LLVMValueRef vertex_index = NULL;
2857 LLVMValueRef indir_index = NULL;
2858 unsigned const_index = 0;
2859 unsigned param;
2860 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2861 const bool is_compact = instr->variables[0]->var->data.compact;
2862 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2863 get_deref_offset(ctx->nir, instr->variables[0],
2864 false, NULL, per_vertex ? &vertex_index : NULL,
2865 &const_index, &indir_index);
2866
2867 if (!instr->variables[0]->var->data.patch) {
2868 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2869 dw_addr = get_tcs_out_current_patch_offset(ctx);
2870 } else {
2871 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2872 }
2873
2874 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2875 indir_index);
2876
2877 unsigned comp = instr->variables[0]->var->data.location_frac;
2878 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2879 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2880 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2881 ctx->ac.i32_1, "");
2882 }
2883 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2884 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2885 return result;
2886 }
2887
2888 static void
2889 store_tcs_output(struct ac_shader_abi *abi,
2890 LLVMValueRef vertex_index,
2891 LLVMValueRef param_index,
2892 unsigned const_index,
2893 unsigned location,
2894 unsigned driver_location,
2895 LLVMValueRef src,
2896 unsigned component,
2897 bool is_patch,
2898 bool is_compact,
2899 unsigned writemask)
2900 {
2901 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2902 LLVMValueRef dw_addr;
2903 LLVMValueRef stride = NULL;
2904 LLVMValueRef buf_addr = NULL;
2905 unsigned param;
2906 bool store_lds = true;
2907
2908 if (is_patch) {
2909 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2910 store_lds = false;
2911 } else {
2912 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2913 store_lds = false;
2914 }
2915
2916 param = shader_io_get_unique_index(location);
2917 if (location == VARYING_SLOT_CLIP_DIST0 &&
2918 is_compact && const_index > 3) {
2919 const_index -= 3;
2920 param++;
2921 }
2922
2923 if (!is_patch) {
2924 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2925 dw_addr = get_tcs_out_current_patch_offset(ctx);
2926 } else {
2927 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2928 }
2929
2930 mark_tess_output(ctx, is_patch, param);
2931
2932 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2933 param_index);
2934 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2935 vertex_index, param_index);
2936
2937 bool is_tess_factor = false;
2938 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2939 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2940 is_tess_factor = true;
2941
2942 unsigned base = is_compact ? const_index : 0;
2943 for (unsigned chan = 0; chan < 8; chan++) {
2944 if (!(writemask & (1 << chan)))
2945 continue;
2946 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2947
2948 if (store_lds || is_tess_factor)
2949 ac_lds_store(&ctx->ac, dw_addr, value);
2950
2951 if (!is_tess_factor && writemask != 0xF)
2952 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2953 buf_addr, ctx->oc_lds,
2954 4 * (base + chan), 1, 0, true, false);
2955
2956 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2957 ctx->ac.i32_1, "");
2958 }
2959
2960 if (writemask == 0xF) {
2961 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2962 buf_addr, ctx->oc_lds,
2963 (base * 4), 1, 0, true, false);
2964 }
2965 }
2966
2967 static LLVMValueRef
2968 load_tes_input(struct ac_shader_abi *abi,
2969 LLVMValueRef vertex_index,
2970 LLVMValueRef param_index,
2971 unsigned const_index,
2972 unsigned location,
2973 unsigned driver_location,
2974 unsigned component,
2975 unsigned num_components,
2976 bool is_patch,
2977 bool is_compact)
2978 {
2979 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2980 LLVMValueRef buf_addr;
2981 LLVMValueRef result;
2982 unsigned param = shader_io_get_unique_index(location);
2983
2984 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
2985 const_index -= 3;
2986 param++;
2987 }
2988
2989 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2990 is_compact, vertex_index, param_index);
2991
2992 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
2993 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2994
2995 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
2996 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2997 result = trim_vector(&ctx->ac, result, num_components);
2998 return result;
2999 }
3000
3001 static LLVMValueRef
3002 load_gs_input(struct ac_shader_abi *abi,
3003 unsigned location,
3004 unsigned driver_location,
3005 unsigned component,
3006 unsigned num_components,
3007 unsigned vertex_index,
3008 unsigned const_index,
3009 LLVMTypeRef type)
3010 {
3011 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3012 LLVMValueRef vtx_offset;
3013 LLVMValueRef args[9];
3014 unsigned param, vtx_offset_param;
3015 LLVMValueRef value[4], result;
3016
3017 vtx_offset_param = vertex_index;
3018 assert(vtx_offset_param < 6);
3019 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3020 LLVMConstInt(ctx->ac.i32, 4, false), "");
3021
3022 param = shader_io_get_unique_index(location);
3023
3024 for (unsigned i = component; i < num_components + component; i++) {
3025 if (ctx->ac.chip_class >= GFX9) {
3026 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3027 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3028 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3029 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3030 } else {
3031 args[0] = ctx->esgs_ring;
3032 args[1] = vtx_offset;
3033 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3034 args[3] = ctx->ac.i32_0;
3035 args[4] = ctx->ac.i32_1; /* OFFEN */
3036 args[5] = ctx->ac.i32_0; /* IDXEN */
3037 args[6] = ctx->ac.i32_1; /* GLC */
3038 args[7] = ctx->ac.i32_0; /* SLC */
3039 args[8] = ctx->ac.i32_0; /* TFE */
3040
3041 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3042 ctx->ac.i32, args, 9,
3043 AC_FUNC_ATTR_READONLY |
3044 AC_FUNC_ATTR_LEGACY);
3045 }
3046 }
3047 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3048
3049 return result;
3050 }
3051
3052 static LLVMValueRef
3053 build_gep_for_deref(struct ac_nir_context *ctx,
3054 nir_deref_var *deref)
3055 {
3056 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3057 assert(entry->data);
3058 LLVMValueRef val = entry->data;
3059 nir_deref *tail = deref->deref.child;
3060 while (tail != NULL) {
3061 LLVMValueRef offset;
3062 switch (tail->deref_type) {
3063 case nir_deref_type_array: {
3064 nir_deref_array *array = nir_deref_as_array(tail);
3065 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3066 if (array->deref_array_type ==
3067 nir_deref_array_type_indirect) {
3068 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3069 get_src(ctx,
3070 array->indirect),
3071 "");
3072 }
3073 break;
3074 }
3075 case nir_deref_type_struct: {
3076 nir_deref_struct *deref_struct =
3077 nir_deref_as_struct(tail);
3078 offset = LLVMConstInt(ctx->ac.i32,
3079 deref_struct->index, 0);
3080 break;
3081 }
3082 default:
3083 unreachable("bad deref type");
3084 }
3085 val = ac_build_gep0(&ctx->ac, val, offset);
3086 tail = tail->child;
3087 }
3088 return val;
3089 }
3090
3091 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3092 nir_intrinsic_instr *instr)
3093 {
3094 LLVMValueRef values[8];
3095 int idx = instr->variables[0]->var->data.driver_location;
3096 int ve = instr->dest.ssa.num_components;
3097 unsigned comp = instr->variables[0]->var->data.location_frac;
3098 LLVMValueRef indir_index;
3099 LLVMValueRef ret;
3100 unsigned const_index;
3101 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3102 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3103 instr->variables[0]->var->data.mode == nir_var_shader_in;
3104 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3105 &const_index, &indir_index);
3106
3107 if (instr->dest.ssa.bit_size == 64)
3108 ve *= 2;
3109
3110 switch (instr->variables[0]->var->data.mode) {
3111 case nir_var_shader_in:
3112 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3113 ctx->stage == MESA_SHADER_TESS_EVAL) {
3114 LLVMValueRef result;
3115 LLVMValueRef vertex_index = NULL;
3116 LLVMValueRef indir_index = NULL;
3117 unsigned const_index = 0;
3118 unsigned location = instr->variables[0]->var->data.location;
3119 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3120 const bool is_patch = instr->variables[0]->var->data.patch;
3121 const bool is_compact = instr->variables[0]->var->data.compact;
3122
3123 get_deref_offset(ctx, instr->variables[0],
3124 false, NULL, is_patch ? NULL : &vertex_index,
3125 &const_index, &indir_index);
3126
3127 result = ctx->abi->load_tess_inputs(ctx->abi, vertex_index, indir_index,
3128 const_index, location, driver_location,
3129 instr->variables[0]->var->data.location_frac,
3130 instr->num_components,
3131 is_patch, is_compact);
3132 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3133 }
3134
3135 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3136 LLVMValueRef indir_index;
3137 unsigned const_index, vertex_index;
3138 get_deref_offset(ctx, instr->variables[0],
3139 false, &vertex_index, NULL,
3140 &const_index, &indir_index);
3141 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3142 instr->variables[0]->var->data.driver_location,
3143 instr->variables[0]->var->data.location_frac, ve,
3144 vertex_index, const_index,
3145 nir2llvmtype(ctx, instr->variables[0]->var->type));
3146 }
3147
3148 for (unsigned chan = comp; chan < ve + comp; chan++) {
3149 if (indir_index) {
3150 unsigned count = glsl_count_attribute_slots(
3151 instr->variables[0]->var->type,
3152 ctx->stage == MESA_SHADER_VERTEX);
3153 count -= chan / 4;
3154 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3155 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3156 stride, false, true);
3157
3158 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3159 tmp_vec,
3160 indir_index, "");
3161 } else
3162 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3163 }
3164 break;
3165 case nir_var_local:
3166 for (unsigned chan = 0; chan < ve; chan++) {
3167 if (indir_index) {
3168 unsigned count = glsl_count_attribute_slots(
3169 instr->variables[0]->var->type, false);
3170 count -= chan / 4;
3171 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3172 &ctx->ac, ctx->locals + idx + chan, count,
3173 stride, true, true);
3174
3175 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3176 tmp_vec,
3177 indir_index, "");
3178 } else {
3179 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3180 }
3181 }
3182 break;
3183 case nir_var_shared: {
3184 LLVMValueRef address = build_gep_for_deref(ctx,
3185 instr->variables[0]);
3186 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3187 return LLVMBuildBitCast(ctx->ac.builder, val,
3188 get_def_type(ctx, &instr->dest.ssa),
3189 "");
3190 }
3191 case nir_var_shader_out:
3192 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3193 return load_tcs_output(ctx->nctx, instr);
3194
3195 for (unsigned chan = comp; chan < ve + comp; chan++) {
3196 if (indir_index) {
3197 unsigned count = glsl_count_attribute_slots(
3198 instr->variables[0]->var->type, false);
3199 count -= chan / 4;
3200 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3201 &ctx->ac, ctx->outputs + idx + chan, count,
3202 stride, true, true);
3203
3204 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3205 tmp_vec,
3206 indir_index, "");
3207 } else {
3208 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3209 ctx->outputs[idx + chan + const_index * stride],
3210 "");
3211 }
3212 }
3213 break;
3214 default:
3215 unreachable("unhandle variable mode");
3216 }
3217 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3218 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3219 }
3220
3221 static void
3222 visit_store_var(struct ac_nir_context *ctx,
3223 nir_intrinsic_instr *instr)
3224 {
3225 LLVMValueRef temp_ptr, value;
3226 int idx = instr->variables[0]->var->data.driver_location;
3227 unsigned comp = instr->variables[0]->var->data.location_frac;
3228 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3229 int writemask = instr->const_index[0] << comp;
3230 LLVMValueRef indir_index;
3231 unsigned const_index;
3232 get_deref_offset(ctx, instr->variables[0], false,
3233 NULL, NULL, &const_index, &indir_index);
3234
3235 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3236 int old_writemask = writemask;
3237
3238 src = LLVMBuildBitCast(ctx->ac.builder, src,
3239 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3240 "");
3241
3242 writemask = 0;
3243 for (unsigned chan = 0; chan < 4; chan++) {
3244 if (old_writemask & (1 << chan))
3245 writemask |= 3u << (2 * chan);
3246 }
3247 }
3248
3249 switch (instr->variables[0]->var->data.mode) {
3250 case nir_var_shader_out:
3251
3252 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3253 LLVMValueRef vertex_index = NULL;
3254 LLVMValueRef indir_index = NULL;
3255 unsigned const_index = 0;
3256 const unsigned location = instr->variables[0]->var->data.location;
3257 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3258 const unsigned comp = instr->variables[0]->var->data.location_frac;
3259 const bool is_patch = instr->variables[0]->var->data.patch;
3260 const bool is_compact = instr->variables[0]->var->data.compact;
3261
3262 get_deref_offset(ctx, instr->variables[0],
3263 false, NULL, is_patch ? NULL : &vertex_index,
3264 &const_index, &indir_index);
3265
3266 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3267 const_index, location, driver_location,
3268 src, comp, is_patch, is_compact, writemask);
3269 return;
3270 }
3271
3272 for (unsigned chan = 0; chan < 8; chan++) {
3273 int stride = 4;
3274 if (!(writemask & (1 << chan)))
3275 continue;
3276
3277 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3278
3279 if (instr->variables[0]->var->data.compact)
3280 stride = 1;
3281 if (indir_index) {
3282 unsigned count = glsl_count_attribute_slots(
3283 instr->variables[0]->var->type, false);
3284 count -= chan / 4;
3285 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3286 &ctx->ac, ctx->outputs + idx + chan, count,
3287 stride, true, true);
3288
3289 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3290 value, indir_index, "");
3291 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3292 count, stride, tmp_vec);
3293
3294 } else {
3295 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3296
3297 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3298 }
3299 }
3300 break;
3301 case nir_var_local:
3302 for (unsigned chan = 0; chan < 8; chan++) {
3303 if (!(writemask & (1 << chan)))
3304 continue;
3305
3306 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3307 if (indir_index) {
3308 unsigned count = glsl_count_attribute_slots(
3309 instr->variables[0]->var->type, false);
3310 count -= chan / 4;
3311 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3312 &ctx->ac, ctx->locals + idx + chan, count,
3313 4, true, true);
3314
3315 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3316 value, indir_index, "");
3317 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3318 count, 4, tmp_vec);
3319 } else {
3320 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3321
3322 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3323 }
3324 }
3325 break;
3326 case nir_var_shared: {
3327 int writemask = instr->const_index[0];
3328 LLVMValueRef address = build_gep_for_deref(ctx,
3329 instr->variables[0]);
3330 LLVMValueRef val = get_src(ctx, instr->src[0]);
3331 unsigned components =
3332 glsl_get_vector_elements(
3333 nir_deref_tail(&instr->variables[0]->deref)->type);
3334 if (writemask == (1 << components) - 1) {
3335 val = LLVMBuildBitCast(
3336 ctx->ac.builder, val,
3337 LLVMGetElementType(LLVMTypeOf(address)), "");
3338 LLVMBuildStore(ctx->ac.builder, val, address);
3339 } else {
3340 for (unsigned chan = 0; chan < 4; chan++) {
3341 if (!(writemask & (1 << chan)))
3342 continue;
3343 LLVMValueRef ptr =
3344 LLVMBuildStructGEP(ctx->ac.builder,
3345 address, chan, "");
3346 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3347 chan);
3348 src = LLVMBuildBitCast(
3349 ctx->ac.builder, src,
3350 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3351 LLVMBuildStore(ctx->ac.builder, src, ptr);
3352 }
3353 }
3354 break;
3355 }
3356 default:
3357 break;
3358 }
3359 }
3360
3361 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3362 {
3363 switch (dim) {
3364 case GLSL_SAMPLER_DIM_BUF:
3365 return 1;
3366 case GLSL_SAMPLER_DIM_1D:
3367 return array ? 2 : 1;
3368 case GLSL_SAMPLER_DIM_2D:
3369 return array ? 3 : 2;
3370 case GLSL_SAMPLER_DIM_MS:
3371 return array ? 4 : 3;
3372 case GLSL_SAMPLER_DIM_3D:
3373 case GLSL_SAMPLER_DIM_CUBE:
3374 return 3;
3375 case GLSL_SAMPLER_DIM_RECT:
3376 case GLSL_SAMPLER_DIM_SUBPASS:
3377 return 2;
3378 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3379 return 3;
3380 default:
3381 break;
3382 }
3383 return 0;
3384 }
3385
3386
3387
3388 /* Adjust the sample index according to FMASK.
3389 *
3390 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3391 * which is the identity mapping. Each nibble says which physical sample
3392 * should be fetched to get that sample.
3393 *
3394 * For example, 0x11111100 means there are only 2 samples stored and
3395 * the second sample covers 3/4 of the pixel. When reading samples 0
3396 * and 1, return physical sample 0 (determined by the first two 0s
3397 * in FMASK), otherwise return physical sample 1.
3398 *
3399 * The sample index should be adjusted as follows:
3400 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3401 */
3402 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3403 LLVMValueRef coord_x, LLVMValueRef coord_y,
3404 LLVMValueRef coord_z,
3405 LLVMValueRef sample_index,
3406 LLVMValueRef fmask_desc_ptr)
3407 {
3408 LLVMValueRef fmask_load_address[4];
3409 LLVMValueRef res;
3410
3411 fmask_load_address[0] = coord_x;
3412 fmask_load_address[1] = coord_y;
3413 if (coord_z) {
3414 fmask_load_address[2] = coord_z;
3415 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3416 }
3417
3418 struct ac_image_args args = {0};
3419
3420 args.opcode = ac_image_load;
3421 args.da = coord_z ? true : false;
3422 args.resource = fmask_desc_ptr;
3423 args.dmask = 0xf;
3424 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3425
3426 res = ac_build_image_opcode(ctx, &args);
3427
3428 res = ac_to_integer(ctx, res);
3429 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3430 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3431
3432 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3433 res,
3434 ctx->i32_0, "");
3435
3436 LLVMValueRef sample_index4 =
3437 LLVMBuildMul(ctx->builder, sample_index, four, "");
3438 LLVMValueRef shifted_fmask =
3439 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3440 LLVMValueRef final_sample =
3441 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3442
3443 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3444 * resource descriptor is 0 (invalid),
3445 */
3446 LLVMValueRef fmask_desc =
3447 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3448 ctx->v8i32, "");
3449
3450 LLVMValueRef fmask_word1 =
3451 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3452 ctx->i32_1, "");
3453
3454 LLVMValueRef word1_is_nonzero =
3455 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3456 fmask_word1, ctx->i32_0, "");
3457
3458 /* Replace the MSAA sample index. */
3459 sample_index =
3460 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3461 final_sample, sample_index, "");
3462 return sample_index;
3463 }
3464
3465 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3466 const nir_intrinsic_instr *instr)
3467 {
3468 const struct glsl_type *type = instr->variables[0]->var->type;
3469 if(instr->variables[0]->deref.child)
3470 type = instr->variables[0]->deref.child->type;
3471
3472 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3473 LLVMValueRef coords[4];
3474 LLVMValueRef masks[] = {
3475 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3476 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3477 };
3478 LLVMValueRef res;
3479 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3480
3481 int count;
3482 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3483 bool is_array = glsl_sampler_type_is_array(type);
3484 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3485 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3486 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3487 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3488 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3489 count = image_type_to_components_count(dim, is_array);
3490
3491 if (is_ms) {
3492 LLVMValueRef fmask_load_address[3];
3493 int chan;
3494
3495 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3496 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3497 if (is_array)
3498 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3499 else
3500 fmask_load_address[2] = NULL;
3501 if (add_frag_pos) {
3502 for (chan = 0; chan < 2; ++chan)
3503 fmask_load_address[chan] =
3504 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3505 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3506 ctx->ac.i32, ""), "");
3507 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3508 }
3509 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3510 fmask_load_address[0],
3511 fmask_load_address[1],
3512 fmask_load_address[2],
3513 sample_index,
3514 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3515 }
3516 if (count == 1 && !gfx9_1d) {
3517 if (instr->src[0].ssa->num_components)
3518 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3519 else
3520 res = src0;
3521 } else {
3522 int chan;
3523 if (is_ms)
3524 count--;
3525 for (chan = 0; chan < count; ++chan) {
3526 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3527 }
3528 if (add_frag_pos) {
3529 for (chan = 0; chan < 2; ++chan)
3530 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3531 ctx->ac.i32, ""), "");
3532 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3533 count++;
3534 }
3535
3536 if (gfx9_1d) {
3537 if (is_array) {
3538 coords[2] = coords[1];
3539 coords[1] = ctx->ac.i32_0;
3540 } else
3541 coords[1] = ctx->ac.i32_0;
3542 count++;
3543 }
3544
3545 if (is_ms) {
3546 coords[count] = sample_index;
3547 count++;
3548 }
3549
3550 if (count == 3) {
3551 coords[3] = LLVMGetUndef(ctx->ac.i32);
3552 count = 4;
3553 }
3554 res = ac_build_gather_values(&ctx->ac, coords, count);
3555 }
3556 return res;
3557 }
3558
3559 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3560 const nir_intrinsic_instr *instr)
3561 {
3562 LLVMValueRef params[7];
3563 LLVMValueRef res;
3564 char intrinsic_name[64];
3565 const nir_variable *var = instr->variables[0]->var;
3566 const struct glsl_type *type = var->type;
3567
3568 if(instr->variables[0]->deref.child)
3569 type = instr->variables[0]->deref.child->type;
3570
3571 type = glsl_without_array(type);
3572 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3573 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3574 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3575 ctx->ac.i32_0, ""); /* vindex */
3576 params[2] = ctx->ac.i32_0; /* voffset */
3577 params[3] = ctx->ac.i1false; /* glc */
3578 params[4] = ctx->ac.i1false; /* slc */
3579 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3580 params, 5, 0);
3581
3582 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3583 res = ac_to_integer(&ctx->ac, res);
3584 } else {
3585 bool is_da = glsl_sampler_type_is_array(type) ||
3586 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3587 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3588 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3589 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3590 LLVMValueRef glc = ctx->ac.i1false;
3591 LLVMValueRef slc = ctx->ac.i1false;
3592
3593 params[0] = get_image_coords(ctx, instr);
3594 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3595 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3596 if (HAVE_LLVM <= 0x0309) {
3597 params[3] = ctx->ac.i1false; /* r128 */
3598 params[4] = da;
3599 params[5] = glc;
3600 params[6] = slc;
3601 } else {
3602 LLVMValueRef lwe = ctx->ac.i1false;
3603 params[3] = glc;
3604 params[4] = slc;
3605 params[5] = lwe;
3606 params[6] = da;
3607 }
3608
3609 ac_get_image_intr_name("llvm.amdgcn.image.load",
3610 ctx->ac.v4f32, /* vdata */
3611 LLVMTypeOf(params[0]), /* coords */
3612 LLVMTypeOf(params[1]), /* rsrc */
3613 intrinsic_name, sizeof(intrinsic_name));
3614
3615 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3616 params, 7, AC_FUNC_ATTR_READONLY);
3617 }
3618 return ac_to_integer(&ctx->ac, res);
3619 }
3620
3621 static void visit_image_store(struct ac_nir_context *ctx,
3622 nir_intrinsic_instr *instr)
3623 {
3624 LLVMValueRef params[8];
3625 char intrinsic_name[64];
3626 const nir_variable *var = instr->variables[0]->var;
3627 const struct glsl_type *type = glsl_without_array(var->type);
3628 LLVMValueRef glc = ctx->ac.i1false;
3629 bool force_glc = ctx->ac.chip_class == SI;
3630 if (force_glc)
3631 glc = ctx->ac.i1true;
3632
3633 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3634 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3635 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3636 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3637 ctx->ac.i32_0, ""); /* vindex */
3638 params[3] = ctx->ac.i32_0; /* voffset */
3639 params[4] = glc; /* glc */
3640 params[5] = ctx->ac.i1false; /* slc */
3641 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3642 params, 6, 0);
3643 } else {
3644 bool is_da = glsl_sampler_type_is_array(type) ||
3645 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3646 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3647 LLVMValueRef slc = ctx->ac.i1false;
3648
3649 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3650 params[1] = get_image_coords(ctx, instr); /* coords */
3651 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3652 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3653 if (HAVE_LLVM <= 0x0309) {
3654 params[4] = ctx->ac.i1false; /* r128 */
3655 params[5] = da;
3656 params[6] = glc;
3657 params[7] = slc;
3658 } else {
3659 LLVMValueRef lwe = ctx->ac.i1false;
3660 params[4] = glc;
3661 params[5] = slc;
3662 params[6] = lwe;
3663 params[7] = da;
3664 }
3665
3666 ac_get_image_intr_name("llvm.amdgcn.image.store",
3667 LLVMTypeOf(params[0]), /* vdata */
3668 LLVMTypeOf(params[1]), /* coords */
3669 LLVMTypeOf(params[2]), /* rsrc */
3670 intrinsic_name, sizeof(intrinsic_name));
3671
3672 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3673 params, 8, 0);
3674 }
3675
3676 }
3677
3678 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3679 const nir_intrinsic_instr *instr)
3680 {
3681 LLVMValueRef params[7];
3682 int param_count = 0;
3683 const nir_variable *var = instr->variables[0]->var;
3684
3685 const char *atomic_name;
3686 char intrinsic_name[41];
3687 const struct glsl_type *type = glsl_without_array(var->type);
3688 MAYBE_UNUSED int length;
3689
3690 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3691
3692 switch (instr->intrinsic) {
3693 case nir_intrinsic_image_atomic_add:
3694 atomic_name = "add";
3695 break;
3696 case nir_intrinsic_image_atomic_min:
3697 atomic_name = is_unsigned ? "umin" : "smin";
3698 break;
3699 case nir_intrinsic_image_atomic_max:
3700 atomic_name = is_unsigned ? "umax" : "smax";
3701 break;
3702 case nir_intrinsic_image_atomic_and:
3703 atomic_name = "and";
3704 break;
3705 case nir_intrinsic_image_atomic_or:
3706 atomic_name = "or";
3707 break;
3708 case nir_intrinsic_image_atomic_xor:
3709 atomic_name = "xor";
3710 break;
3711 case nir_intrinsic_image_atomic_exchange:
3712 atomic_name = "swap";
3713 break;
3714 case nir_intrinsic_image_atomic_comp_swap:
3715 atomic_name = "cmpswap";
3716 break;
3717 default:
3718 abort();
3719 }
3720
3721 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3722 params[param_count++] = get_src(ctx, instr->src[3]);
3723 params[param_count++] = get_src(ctx, instr->src[2]);
3724
3725 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3726 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3727 NULL, true, true);
3728 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3729 ctx->ac.i32_0, ""); /* vindex */
3730 params[param_count++] = ctx->ac.i32_0; /* voffset */
3731 params[param_count++] = ctx->ac.i1false; /* slc */
3732
3733 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3734 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3735 } else {
3736 char coords_type[8];
3737
3738 bool da = glsl_sampler_type_is_array(type) ||
3739 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3740
3741 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3742 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3743 NULL, true, true);
3744 params[param_count++] = ctx->ac.i1false; /* r128 */
3745 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3746 params[param_count++] = ctx->ac.i1false; /* slc */
3747
3748 build_int_type_name(LLVMTypeOf(coords),
3749 coords_type, sizeof(coords_type));
3750
3751 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3752 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3753 }
3754
3755 assert(length < sizeof(intrinsic_name));
3756 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3757 }
3758
3759 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3760 const nir_intrinsic_instr *instr)
3761 {
3762 LLVMValueRef res;
3763 const nir_variable *var = instr->variables[0]->var;
3764 const struct glsl_type *type = instr->variables[0]->var->type;
3765 bool da = glsl_sampler_type_is_array(var->type) ||
3766 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3767 if(instr->variables[0]->deref.child)
3768 type = instr->variables[0]->deref.child->type;
3769
3770 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3771 return get_buffer_size(ctx,
3772 get_sampler_desc(ctx, instr->variables[0],
3773 AC_DESC_BUFFER, NULL, true, false), true);
3774
3775 struct ac_image_args args = { 0 };
3776
3777 args.da = da;
3778 args.dmask = 0xf;
3779 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3780 args.opcode = ac_image_get_resinfo;
3781 args.addr = ctx->ac.i32_0;
3782
3783 res = ac_build_image_opcode(&ctx->ac, &args);
3784
3785 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3786
3787 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3788 glsl_sampler_type_is_array(type)) {
3789 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3790 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3791 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3792 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3793 }
3794 if (ctx->ac.chip_class >= GFX9 &&
3795 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3796 glsl_sampler_type_is_array(type)) {
3797 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3798 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3799 ctx->ac.i32_1, "");
3800
3801 }
3802 return res;
3803 }
3804
3805 #define NOOP_WAITCNT 0xf7f
3806 #define LGKM_CNT 0x07f
3807 #define VM_CNT 0xf70
3808
3809 static void emit_membar(struct nir_to_llvm_context *ctx,
3810 const nir_intrinsic_instr *instr)
3811 {
3812 unsigned waitcnt = NOOP_WAITCNT;
3813
3814 switch (instr->intrinsic) {
3815 case nir_intrinsic_memory_barrier:
3816 case nir_intrinsic_group_memory_barrier:
3817 waitcnt &= VM_CNT & LGKM_CNT;
3818 break;
3819 case nir_intrinsic_memory_barrier_atomic_counter:
3820 case nir_intrinsic_memory_barrier_buffer:
3821 case nir_intrinsic_memory_barrier_image:
3822 waitcnt &= VM_CNT;
3823 break;
3824 case nir_intrinsic_memory_barrier_shared:
3825 waitcnt &= LGKM_CNT;
3826 break;
3827 default:
3828 break;
3829 }
3830 if (waitcnt != NOOP_WAITCNT)
3831 ac_build_waitcnt(&ctx->ac, waitcnt);
3832 }
3833
3834 static void emit_barrier(struct nir_to_llvm_context *ctx)
3835 {
3836 /* SI only (thanks to a hw bug workaround):
3837 * The real barrier instruction isn’t needed, because an entire patch
3838 * always fits into a single wave.
3839 */
3840 if (ctx->options->chip_class == SI &&
3841 ctx->stage == MESA_SHADER_TESS_CTRL) {
3842 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
3843 return;
3844 }
3845 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3846 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3847 }
3848
3849 static void emit_discard_if(struct ac_nir_context *ctx,
3850 const nir_intrinsic_instr *instr)
3851 {
3852 LLVMValueRef cond;
3853
3854 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3855 get_src(ctx, instr->src[0]),
3856 ctx->ac.i32_0, "");
3857 ac_build_kill_if_false(&ctx->ac, cond);
3858 }
3859
3860 static LLVMValueRef
3861 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3862 {
3863 LLVMValueRef result;
3864 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3865 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3866 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3867
3868 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3869 }
3870
3871 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3872 const nir_intrinsic_instr *instr)
3873 {
3874 LLVMValueRef ptr, result;
3875 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3876 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3877
3878 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3879 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3880 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3881 ptr, src, src1,
3882 LLVMAtomicOrderingSequentiallyConsistent,
3883 LLVMAtomicOrderingSequentiallyConsistent,
3884 false);
3885 } else {
3886 LLVMAtomicRMWBinOp op;
3887 switch (instr->intrinsic) {
3888 case nir_intrinsic_var_atomic_add:
3889 op = LLVMAtomicRMWBinOpAdd;
3890 break;
3891 case nir_intrinsic_var_atomic_umin:
3892 op = LLVMAtomicRMWBinOpUMin;
3893 break;
3894 case nir_intrinsic_var_atomic_umax:
3895 op = LLVMAtomicRMWBinOpUMax;
3896 break;
3897 case nir_intrinsic_var_atomic_imin:
3898 op = LLVMAtomicRMWBinOpMin;
3899 break;
3900 case nir_intrinsic_var_atomic_imax:
3901 op = LLVMAtomicRMWBinOpMax;
3902 break;
3903 case nir_intrinsic_var_atomic_and:
3904 op = LLVMAtomicRMWBinOpAnd;
3905 break;
3906 case nir_intrinsic_var_atomic_or:
3907 op = LLVMAtomicRMWBinOpOr;
3908 break;
3909 case nir_intrinsic_var_atomic_xor:
3910 op = LLVMAtomicRMWBinOpXor;
3911 break;
3912 case nir_intrinsic_var_atomic_exchange:
3913 op = LLVMAtomicRMWBinOpXchg;
3914 break;
3915 default:
3916 return NULL;
3917 }
3918
3919 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3920 LLVMAtomicOrderingSequentiallyConsistent,
3921 false);
3922 }
3923 return result;
3924 }
3925
3926 #define INTERP_CENTER 0
3927 #define INTERP_CENTROID 1
3928 #define INTERP_SAMPLE 2
3929
3930 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3931 enum glsl_interp_mode interp, unsigned location)
3932 {
3933 switch (interp) {
3934 case INTERP_MODE_FLAT:
3935 default:
3936 return NULL;
3937 case INTERP_MODE_SMOOTH:
3938 case INTERP_MODE_NONE:
3939 if (location == INTERP_CENTER)
3940 return ctx->persp_center;
3941 else if (location == INTERP_CENTROID)
3942 return ctx->persp_centroid;
3943 else if (location == INTERP_SAMPLE)
3944 return ctx->persp_sample;
3945 break;
3946 case INTERP_MODE_NOPERSPECTIVE:
3947 if (location == INTERP_CENTER)
3948 return ctx->linear_center;
3949 else if (location == INTERP_CENTROID)
3950 return ctx->linear_centroid;
3951 else if (location == INTERP_SAMPLE)
3952 return ctx->linear_sample;
3953 break;
3954 }
3955 return NULL;
3956 }
3957
3958 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3959 LLVMValueRef sample_id)
3960 {
3961 LLVMValueRef result;
3962 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3963
3964 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3965 const_array(ctx->ac.v2f32, 64), "");
3966
3967 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3968 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3969
3970 return result;
3971 }
3972
3973 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3974 {
3975 LLVMValueRef values[2];
3976
3977 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3978 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3979 return ac_build_gather_values(&ctx->ac, values, 2);
3980 }
3981
3982 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3983 const nir_intrinsic_instr *instr)
3984 {
3985 LLVMValueRef result[4];
3986 LLVMValueRef interp_param, attr_number;
3987 unsigned location;
3988 unsigned chan;
3989 LLVMValueRef src_c0 = NULL;
3990 LLVMValueRef src_c1 = NULL;
3991 LLVMValueRef src0 = NULL;
3992 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3993 switch (instr->intrinsic) {
3994 case nir_intrinsic_interp_var_at_centroid:
3995 location = INTERP_CENTROID;
3996 break;
3997 case nir_intrinsic_interp_var_at_sample:
3998 case nir_intrinsic_interp_var_at_offset:
3999 location = INTERP_CENTER;
4000 src0 = get_src(ctx->nir, instr->src[0]);
4001 break;
4002 default:
4003 break;
4004 }
4005
4006 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4007 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
4008 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
4009 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4010 LLVMValueRef sample_position;
4011 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4012
4013 /* fetch sample ID */
4014 sample_position = load_sample_position(ctx, src0);
4015
4016 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4017 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4018 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4019 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4020 }
4021 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4022 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4023
4024 if (location == INTERP_CENTER) {
4025 LLVMValueRef ij_out[2];
4026 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4027
4028 /*
4029 * take the I then J parameters, and the DDX/Y for it, and
4030 * calculate the IJ inputs for the interpolator.
4031 * temp1 = ddx * offset/sample.x + I;
4032 * interp_param.I = ddy * offset/sample.y + temp1;
4033 * temp1 = ddx * offset/sample.x + J;
4034 * interp_param.J = ddy * offset/sample.y + temp1;
4035 */
4036 for (unsigned i = 0; i < 2; i++) {
4037 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4038 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4039 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4040 ddxy_out, ix_ll, "");
4041 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4042 ddxy_out, iy_ll, "");
4043 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4044 interp_param, ix_ll, "");
4045 LLVMValueRef temp1, temp2;
4046
4047 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4048 ctx->ac.f32, "");
4049
4050 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4051 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4052
4053 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4054 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4055
4056 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4057 temp2, ctx->ac.i32, "");
4058 }
4059 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4060
4061 }
4062
4063 for (chan = 0; chan < 4; chan++) {
4064 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4065
4066 if (interp_param) {
4067 interp_param = LLVMBuildBitCast(ctx->builder,
4068 interp_param, ctx->ac.v2f32, "");
4069 LLVMValueRef i = LLVMBuildExtractElement(
4070 ctx->builder, interp_param, ctx->ac.i32_0, "");
4071 LLVMValueRef j = LLVMBuildExtractElement(
4072 ctx->builder, interp_param, ctx->ac.i32_1, "");
4073
4074 result[chan] = ac_build_fs_interp(&ctx->ac,
4075 llvm_chan, attr_number,
4076 ctx->prim_mask, i, j);
4077 } else {
4078 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4079 LLVMConstInt(ctx->ac.i32, 2, false),
4080 llvm_chan, attr_number,
4081 ctx->prim_mask);
4082 }
4083 }
4084 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4085 instr->variables[0]->var->data.location_frac);
4086 }
4087
4088 static void
4089 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4090 {
4091 LLVMValueRef gs_next_vertex;
4092 LLVMValueRef can_emit;
4093 int idx;
4094 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4095
4096 /* Write vertex attribute values to GSVS ring */
4097 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4098 ctx->gs_next_vertex,
4099 "");
4100
4101 /* If this thread has already emitted the declared maximum number of
4102 * vertices, kill it: excessive vertex emissions are not supposed to
4103 * have any effect, and GS threads have no externally observable
4104 * effects other than emitting vertices.
4105 */
4106 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4107 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4108 ac_build_kill_if_false(&ctx->ac, can_emit);
4109
4110 /* loop num outputs */
4111 idx = 0;
4112 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4113 LLVMValueRef *out_ptr = &addrs[i * 4];
4114 int length = 4;
4115 int slot = idx;
4116 int slot_inc = 1;
4117
4118 if (!(ctx->output_mask & (1ull << i)))
4119 continue;
4120
4121 if (i == VARYING_SLOT_CLIP_DIST0) {
4122 /* pack clip and cull into a single set of slots */
4123 length = ctx->num_output_clips + ctx->num_output_culls;
4124 if (length > 4)
4125 slot_inc = 2;
4126 }
4127 for (unsigned j = 0; j < length; j++) {
4128 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4129 out_ptr[j], "");
4130 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4131 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4132 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4133
4134 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4135
4136 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4137 out_val, 1,
4138 voffset, ctx->gs2vs_offset, 0,
4139 1, 1, true, true);
4140 }
4141 idx += slot_inc;
4142 }
4143
4144 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4145 ctx->ac.i32_1, "");
4146 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4147
4148 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4149 }
4150
4151 static void
4152 visit_end_primitive(struct nir_to_llvm_context *ctx,
4153 const nir_intrinsic_instr *instr)
4154 {
4155 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4156 }
4157
4158 static LLVMValueRef
4159 load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
4160 unsigned num_components)
4161 {
4162 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4163
4164 LLVMValueRef coord[4] = {
4165 ctx->tes_u,
4166 ctx->tes_v,
4167 ctx->ac.f32_0,
4168 ctx->ac.f32_0,
4169 };
4170
4171 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4172 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4173 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4174
4175 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, num_components);
4176 return LLVMBuildBitCast(ctx->builder, result, type, "");
4177 }
4178
4179 static void visit_intrinsic(struct ac_nir_context *ctx,
4180 nir_intrinsic_instr *instr)
4181 {
4182 LLVMValueRef result = NULL;
4183
4184 switch (instr->intrinsic) {
4185 case nir_intrinsic_load_work_group_id: {
4186 LLVMValueRef values[3];
4187
4188 for (int i = 0; i < 3; i++) {
4189 values[i] = ctx->nctx->workgroup_ids[i] ?
4190 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4191 }
4192
4193 result = ac_build_gather_values(&ctx->ac, values, 3);
4194 break;
4195 }
4196 case nir_intrinsic_load_base_vertex: {
4197 result = ctx->abi->base_vertex;
4198 break;
4199 }
4200 case nir_intrinsic_load_vertex_id_zero_base: {
4201 result = ctx->abi->vertex_id;
4202 break;
4203 }
4204 case nir_intrinsic_load_local_invocation_id: {
4205 result = ctx->nctx->local_invocation_ids;
4206 break;
4207 }
4208 case nir_intrinsic_load_base_instance:
4209 result = ctx->abi->start_instance;
4210 break;
4211 case nir_intrinsic_load_draw_id:
4212 result = ctx->abi->draw_id;
4213 break;
4214 case nir_intrinsic_load_view_index:
4215 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4216 break;
4217 case nir_intrinsic_load_invocation_id:
4218 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4219 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4220 else
4221 result = ctx->abi->gs_invocation_id;
4222 break;
4223 case nir_intrinsic_load_primitive_id:
4224 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4225 result = ctx->abi->gs_prim_id;
4226 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4227 result = ctx->abi->tcs_patch_id;
4228 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4229 result = ctx->abi->tes_patch_id;
4230 } else
4231 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4232 break;
4233 case nir_intrinsic_load_sample_id:
4234 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4235 break;
4236 case nir_intrinsic_load_sample_pos:
4237 result = load_sample_pos(ctx);
4238 break;
4239 case nir_intrinsic_load_sample_mask_in:
4240 result = ctx->abi->sample_coverage;
4241 break;
4242 case nir_intrinsic_load_frag_coord: {
4243 LLVMValueRef values[4] = {
4244 ctx->abi->frag_pos[0],
4245 ctx->abi->frag_pos[1],
4246 ctx->abi->frag_pos[2],
4247 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4248 };
4249 result = ac_build_gather_values(&ctx->ac, values, 4);
4250 break;
4251 }
4252 case nir_intrinsic_load_front_face:
4253 result = ctx->abi->front_face;
4254 break;
4255 case nir_intrinsic_load_instance_id:
4256 result = ctx->abi->instance_id;
4257 break;
4258 case nir_intrinsic_load_num_work_groups:
4259 result = ctx->nctx->num_work_groups;
4260 break;
4261 case nir_intrinsic_load_local_invocation_index:
4262 result = visit_load_local_invocation_index(ctx->nctx);
4263 break;
4264 case nir_intrinsic_load_push_constant:
4265 result = visit_load_push_constant(ctx->nctx, instr);
4266 break;
4267 case nir_intrinsic_vulkan_resource_index:
4268 result = visit_vulkan_resource_index(ctx->nctx, instr);
4269 break;
4270 case nir_intrinsic_vulkan_resource_reindex:
4271 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4272 break;
4273 case nir_intrinsic_store_ssbo:
4274 visit_store_ssbo(ctx, instr);
4275 break;
4276 case nir_intrinsic_load_ssbo:
4277 result = visit_load_buffer(ctx, instr);
4278 break;
4279 case nir_intrinsic_ssbo_atomic_add:
4280 case nir_intrinsic_ssbo_atomic_imin:
4281 case nir_intrinsic_ssbo_atomic_umin:
4282 case nir_intrinsic_ssbo_atomic_imax:
4283 case nir_intrinsic_ssbo_atomic_umax:
4284 case nir_intrinsic_ssbo_atomic_and:
4285 case nir_intrinsic_ssbo_atomic_or:
4286 case nir_intrinsic_ssbo_atomic_xor:
4287 case nir_intrinsic_ssbo_atomic_exchange:
4288 case nir_intrinsic_ssbo_atomic_comp_swap:
4289 result = visit_atomic_ssbo(ctx, instr);
4290 break;
4291 case nir_intrinsic_load_ubo:
4292 result = visit_load_ubo_buffer(ctx, instr);
4293 break;
4294 case nir_intrinsic_get_buffer_size:
4295 result = visit_get_buffer_size(ctx, instr);
4296 break;
4297 case nir_intrinsic_load_var:
4298 result = visit_load_var(ctx, instr);
4299 break;
4300 case nir_intrinsic_store_var:
4301 visit_store_var(ctx, instr);
4302 break;
4303 case nir_intrinsic_image_load:
4304 result = visit_image_load(ctx, instr);
4305 break;
4306 case nir_intrinsic_image_store:
4307 visit_image_store(ctx, instr);
4308 break;
4309 case nir_intrinsic_image_atomic_add:
4310 case nir_intrinsic_image_atomic_min:
4311 case nir_intrinsic_image_atomic_max:
4312 case nir_intrinsic_image_atomic_and:
4313 case nir_intrinsic_image_atomic_or:
4314 case nir_intrinsic_image_atomic_xor:
4315 case nir_intrinsic_image_atomic_exchange:
4316 case nir_intrinsic_image_atomic_comp_swap:
4317 result = visit_image_atomic(ctx, instr);
4318 break;
4319 case nir_intrinsic_image_size:
4320 result = visit_image_size(ctx, instr);
4321 break;
4322 case nir_intrinsic_discard:
4323 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4324 LLVMVoidTypeInContext(ctx->ac.context),
4325 NULL, 0, AC_FUNC_ATTR_LEGACY);
4326 break;
4327 case nir_intrinsic_discard_if:
4328 emit_discard_if(ctx, instr);
4329 break;
4330 case nir_intrinsic_memory_barrier:
4331 case nir_intrinsic_group_memory_barrier:
4332 case nir_intrinsic_memory_barrier_atomic_counter:
4333 case nir_intrinsic_memory_barrier_buffer:
4334 case nir_intrinsic_memory_barrier_image:
4335 case nir_intrinsic_memory_barrier_shared:
4336 emit_membar(ctx->nctx, instr);
4337 break;
4338 case nir_intrinsic_barrier:
4339 emit_barrier(ctx->nctx);
4340 break;
4341 case nir_intrinsic_var_atomic_add:
4342 case nir_intrinsic_var_atomic_imin:
4343 case nir_intrinsic_var_atomic_umin:
4344 case nir_intrinsic_var_atomic_imax:
4345 case nir_intrinsic_var_atomic_umax:
4346 case nir_intrinsic_var_atomic_and:
4347 case nir_intrinsic_var_atomic_or:
4348 case nir_intrinsic_var_atomic_xor:
4349 case nir_intrinsic_var_atomic_exchange:
4350 case nir_intrinsic_var_atomic_comp_swap:
4351 result = visit_var_atomic(ctx->nctx, instr);
4352 break;
4353 case nir_intrinsic_interp_var_at_centroid:
4354 case nir_intrinsic_interp_var_at_sample:
4355 case nir_intrinsic_interp_var_at_offset:
4356 result = visit_interp(ctx->nctx, instr);
4357 break;
4358 case nir_intrinsic_emit_vertex:
4359 assert(instr->const_index[0] == 0);
4360 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4361 break;
4362 case nir_intrinsic_end_primitive:
4363 visit_end_primitive(ctx->nctx, instr);
4364 break;
4365 case nir_intrinsic_load_tess_coord: {
4366 LLVMTypeRef type = ctx->nctx ?
4367 get_def_type(ctx->nctx->nir, &instr->dest.ssa) :
4368 NULL;
4369 result = ctx->abi->load_tess_coord(ctx->abi, type, instr->num_components);
4370 break;
4371 }
4372 case nir_intrinsic_load_patch_vertices_in:
4373 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4374 break;
4375 default:
4376 fprintf(stderr, "Unknown intrinsic: ");
4377 nir_print_instr(&instr->instr, stderr);
4378 fprintf(stderr, "\n");
4379 break;
4380 }
4381 if (result) {
4382 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4383 }
4384 }
4385
4386 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4387 LLVMValueRef buffer_ptr, bool write)
4388 {
4389 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4390
4391 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4392 ctx->shader_info->fs.writes_memory = true;
4393
4394 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4395 }
4396
4397 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4398 {
4399 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4400
4401 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4402 }
4403
4404 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4405 unsigned descriptor_set,
4406 unsigned base_index,
4407 unsigned constant_index,
4408 LLVMValueRef index,
4409 enum ac_descriptor_type desc_type,
4410 bool image, bool write)
4411 {
4412 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4413 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4414 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4415 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4416 unsigned offset = binding->offset;
4417 unsigned stride = binding->size;
4418 unsigned type_size;
4419 LLVMBuilderRef builder = ctx->builder;
4420 LLVMTypeRef type;
4421
4422 assert(base_index < layout->binding_count);
4423
4424 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4425 ctx->shader_info->fs.writes_memory = true;
4426
4427 switch (desc_type) {
4428 case AC_DESC_IMAGE:
4429 type = ctx->ac.v8i32;
4430 type_size = 32;
4431 break;
4432 case AC_DESC_FMASK:
4433 type = ctx->ac.v8i32;
4434 offset += 32;
4435 type_size = 32;
4436 break;
4437 case AC_DESC_SAMPLER:
4438 type = ctx->ac.v4i32;
4439 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4440 offset += 64;
4441
4442 type_size = 16;
4443 break;
4444 case AC_DESC_BUFFER:
4445 type = ctx->ac.v4i32;
4446 type_size = 16;
4447 break;
4448 default:
4449 unreachable("invalid desc_type\n");
4450 }
4451
4452 offset += constant_index * stride;
4453
4454 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4455 (!index || binding->immutable_samplers_equal)) {
4456 if (binding->immutable_samplers_equal)
4457 constant_index = 0;
4458
4459 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4460
4461 LLVMValueRef constants[] = {
4462 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4463 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4464 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4465 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4466 };
4467 return ac_build_gather_values(&ctx->ac, constants, 4);
4468 }
4469
4470 assert(stride % type_size == 0);
4471
4472 if (!index)
4473 index = ctx->ac.i32_0;
4474
4475 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4476
4477 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4478 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4479
4480 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4481 }
4482
4483 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4484 const nir_deref_var *deref,
4485 enum ac_descriptor_type desc_type,
4486 const nir_tex_instr *tex_instr,
4487 bool image, bool write)
4488 {
4489 LLVMValueRef index = NULL;
4490 unsigned constant_index = 0;
4491 unsigned descriptor_set;
4492 unsigned base_index;
4493
4494 if (!deref) {
4495 assert(tex_instr && !image);
4496 descriptor_set = 0;
4497 base_index = tex_instr->sampler_index;
4498 } else {
4499 const nir_deref *tail = &deref->deref;
4500 while (tail->child) {
4501 const nir_deref_array *child = nir_deref_as_array(tail->child);
4502 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4503
4504 if (!array_size)
4505 array_size = 1;
4506
4507 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4508
4509 if (child->deref_array_type == nir_deref_array_type_indirect) {
4510 LLVMValueRef indirect = get_src(ctx, child->indirect);
4511
4512 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4513 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4514
4515 if (!index)
4516 index = indirect;
4517 else
4518 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4519 }
4520
4521 constant_index += child->base_offset * array_size;
4522
4523 tail = &child->deref;
4524 }
4525 descriptor_set = deref->var->data.descriptor_set;
4526 base_index = deref->var->data.binding;
4527 }
4528
4529 return ctx->abi->load_sampler_desc(ctx->abi,
4530 descriptor_set,
4531 base_index,
4532 constant_index, index,
4533 desc_type, image, write);
4534 }
4535
4536 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4537 struct ac_image_args *args,
4538 const nir_tex_instr *instr,
4539 nir_texop op,
4540 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4541 LLVMValueRef *param, unsigned count,
4542 unsigned dmask)
4543 {
4544 unsigned is_rect = 0;
4545 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4546
4547 if (op == nir_texop_lod)
4548 da = false;
4549 /* Pad to power of two vector */
4550 while (count < util_next_power_of_two(count))
4551 param[count++] = LLVMGetUndef(ctx->i32);
4552
4553 if (count > 1)
4554 args->addr = ac_build_gather_values(ctx, param, count);
4555 else
4556 args->addr = param[0];
4557
4558 args->resource = res_ptr;
4559 args->sampler = samp_ptr;
4560
4561 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4562 args->addr = param[0];
4563 return;
4564 }
4565
4566 args->dmask = dmask;
4567 args->unorm = is_rect;
4568 args->da = da;
4569 }
4570
4571 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4572 *
4573 * SI-CI:
4574 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4575 * filtering manually. The driver sets img7 to a mask clearing
4576 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4577 * s_and_b32 samp0, samp0, img7
4578 *
4579 * VI:
4580 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4581 */
4582 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4583 LLVMValueRef res, LLVMValueRef samp)
4584 {
4585 LLVMBuilderRef builder = ctx->ac.builder;
4586 LLVMValueRef img7, samp0;
4587
4588 if (ctx->ac.chip_class >= VI)
4589 return samp;
4590
4591 img7 = LLVMBuildExtractElement(builder, res,
4592 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4593 samp0 = LLVMBuildExtractElement(builder, samp,
4594 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4595 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4596 return LLVMBuildInsertElement(builder, samp, samp0,
4597 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4598 }
4599
4600 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4601 nir_tex_instr *instr,
4602 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4603 LLVMValueRef *fmask_ptr)
4604 {
4605 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4606 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4607 else
4608 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4609 if (samp_ptr) {
4610 if (instr->sampler)
4611 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4612 else
4613 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4614 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4615 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4616 }
4617 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4618 instr->op == nir_texop_samples_identical))
4619 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4620 }
4621
4622 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4623 LLVMValueRef coord)
4624 {
4625 coord = ac_to_float(ctx, coord);
4626 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4627 coord = ac_to_integer(ctx, coord);
4628 return coord;
4629 }
4630
4631 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4632 {
4633 LLVMValueRef result = NULL;
4634 struct ac_image_args args = { 0 };
4635 unsigned dmask = 0xf;
4636 LLVMValueRef address[16];
4637 LLVMValueRef coords[5];
4638 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4639 LLVMValueRef bias = NULL, offsets = NULL;
4640 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4641 LLVMValueRef ddx = NULL, ddy = NULL;
4642 LLVMValueRef derivs[6];
4643 unsigned chan, count = 0;
4644 unsigned const_src = 0, num_deriv_comp = 0;
4645 bool lod_is_zero = false;
4646
4647 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4648
4649 for (unsigned i = 0; i < instr->num_srcs; i++) {
4650 switch (instr->src[i].src_type) {
4651 case nir_tex_src_coord:
4652 coord = get_src(ctx, instr->src[i].src);
4653 break;
4654 case nir_tex_src_projector:
4655 break;
4656 case nir_tex_src_comparator:
4657 comparator = get_src(ctx, instr->src[i].src);
4658 break;
4659 case nir_tex_src_offset:
4660 offsets = get_src(ctx, instr->src[i].src);
4661 const_src = i;
4662 break;
4663 case nir_tex_src_bias:
4664 bias = get_src(ctx, instr->src[i].src);
4665 break;
4666 case nir_tex_src_lod: {
4667 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4668
4669 if (val && val->i32[0] == 0)
4670 lod_is_zero = true;
4671 lod = get_src(ctx, instr->src[i].src);
4672 break;
4673 }
4674 case nir_tex_src_ms_index:
4675 sample_index = get_src(ctx, instr->src[i].src);
4676 break;
4677 case nir_tex_src_ms_mcs:
4678 break;
4679 case nir_tex_src_ddx:
4680 ddx = get_src(ctx, instr->src[i].src);
4681 num_deriv_comp = instr->src[i].src.ssa->num_components;
4682 break;
4683 case nir_tex_src_ddy:
4684 ddy = get_src(ctx, instr->src[i].src);
4685 break;
4686 case nir_tex_src_texture_offset:
4687 case nir_tex_src_sampler_offset:
4688 case nir_tex_src_plane:
4689 default:
4690 break;
4691 }
4692 }
4693
4694 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4695 result = get_buffer_size(ctx, res_ptr, true);
4696 goto write_result;
4697 }
4698
4699 if (instr->op == nir_texop_texture_samples) {
4700 LLVMValueRef res, samples, is_msaa;
4701 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4702 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4703 LLVMConstInt(ctx->ac.i32, 3, false), "");
4704 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4705 LLVMConstInt(ctx->ac.i32, 28, false), "");
4706 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4707 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4708 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4709 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4710
4711 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4712 LLVMConstInt(ctx->ac.i32, 16, false), "");
4713 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4714 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4715 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4716 samples, "");
4717 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4718 ctx->ac.i32_1, "");
4719 result = samples;
4720 goto write_result;
4721 }
4722
4723 if (coord)
4724 for (chan = 0; chan < instr->coord_components; chan++)
4725 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4726
4727 if (offsets && instr->op != nir_texop_txf) {
4728 LLVMValueRef offset[3], pack;
4729 for (chan = 0; chan < 3; ++chan)
4730 offset[chan] = ctx->ac.i32_0;
4731
4732 args.offset = true;
4733 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4734 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4735 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4736 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4737 if (chan)
4738 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4739 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4740 }
4741 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4742 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4743 address[count++] = pack;
4744
4745 }
4746 /* pack LOD bias value */
4747 if (instr->op == nir_texop_txb && bias) {
4748 address[count++] = bias;
4749 }
4750
4751 /* Pack depth comparison value */
4752 if (instr->is_shadow && comparator) {
4753 LLVMValueRef z = ac_to_float(&ctx->ac,
4754 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4755
4756 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4757 * so the depth comparison value isn't clamped for Z16 and
4758 * Z24 anymore. Do it manually here.
4759 *
4760 * It's unnecessary if the original texture format was
4761 * Z32_FLOAT, but we don't know that here.
4762 */
4763 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4764 z = ac_build_clamp(&ctx->ac, z);
4765
4766 address[count++] = z;
4767 }
4768
4769 /* pack derivatives */
4770 if (ddx || ddy) {
4771 int num_src_deriv_channels, num_dest_deriv_channels;
4772 switch (instr->sampler_dim) {
4773 case GLSL_SAMPLER_DIM_3D:
4774 case GLSL_SAMPLER_DIM_CUBE:
4775 num_deriv_comp = 3;
4776 num_src_deriv_channels = 3;
4777 num_dest_deriv_channels = 3;
4778 break;
4779 case GLSL_SAMPLER_DIM_2D:
4780 default:
4781 num_src_deriv_channels = 2;
4782 num_dest_deriv_channels = 2;
4783 num_deriv_comp = 2;
4784 break;
4785 case GLSL_SAMPLER_DIM_1D:
4786 num_src_deriv_channels = 1;
4787 if (ctx->ac.chip_class >= GFX9) {
4788 num_dest_deriv_channels = 2;
4789 num_deriv_comp = 2;
4790 } else {
4791 num_dest_deriv_channels = 1;
4792 num_deriv_comp = 1;
4793 }
4794 break;
4795 }
4796
4797 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4798 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4799 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4800 }
4801 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4802 derivs[i] = ctx->ac.f32_0;
4803 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4804 }
4805 }
4806
4807 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4808 for (chan = 0; chan < instr->coord_components; chan++)
4809 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4810 if (instr->coord_components == 3)
4811 coords[3] = LLVMGetUndef(ctx->ac.f32);
4812 ac_prepare_cube_coords(&ctx->ac,
4813 instr->op == nir_texop_txd, instr->is_array,
4814 instr->op == nir_texop_lod, coords, derivs);
4815 if (num_deriv_comp)
4816 num_deriv_comp--;
4817 }
4818
4819 if (ddx || ddy) {
4820 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4821 address[count++] = derivs[i];
4822 }
4823
4824 /* Pack texture coordinates */
4825 if (coord) {
4826 address[count++] = coords[0];
4827 if (instr->coord_components > 1) {
4828 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4829 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4830 }
4831 address[count++] = coords[1];
4832 }
4833 if (instr->coord_components > 2) {
4834 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4835 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4836 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4837 instr->op != nir_texop_txf) {
4838 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4839 }
4840 address[count++] = coords[2];
4841 }
4842
4843 if (ctx->ac.chip_class >= GFX9) {
4844 LLVMValueRef filler;
4845 if (instr->op == nir_texop_txf)
4846 filler = ctx->ac.i32_0;
4847 else
4848 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4849
4850 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4851 /* No nir_texop_lod, because it does not take a slice
4852 * even with array textures. */
4853 if (instr->is_array && instr->op != nir_texop_lod ) {
4854 address[count] = address[count - 1];
4855 address[count - 1] = filler;
4856 count++;
4857 } else
4858 address[count++] = filler;
4859 }
4860 }
4861 }
4862
4863 /* Pack LOD */
4864 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4865 instr->op == nir_texop_txf)) {
4866 address[count++] = lod;
4867 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4868 address[count++] = sample_index;
4869 } else if(instr->op == nir_texop_txs) {
4870 count = 0;
4871 if (lod)
4872 address[count++] = lod;
4873 else
4874 address[count++] = ctx->ac.i32_0;
4875 }
4876
4877 for (chan = 0; chan < count; chan++) {
4878 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4879 address[chan], ctx->ac.i32, "");
4880 }
4881
4882 if (instr->op == nir_texop_samples_identical) {
4883 LLVMValueRef txf_address[4];
4884 struct ac_image_args txf_args = { 0 };
4885 unsigned txf_count = count;
4886 memcpy(txf_address, address, sizeof(txf_address));
4887
4888 if (!instr->is_array)
4889 txf_address[2] = ctx->ac.i32_0;
4890 txf_address[3] = ctx->ac.i32_0;
4891
4892 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4893 fmask_ptr, NULL,
4894 txf_address, txf_count, 0xf);
4895
4896 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4897
4898 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4899 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4900 goto write_result;
4901 }
4902
4903 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4904 instr->op != nir_texop_txs) {
4905 unsigned sample_chan = instr->is_array ? 3 : 2;
4906 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4907 address[0],
4908 address[1],
4909 instr->is_array ? address[2] : NULL,
4910 address[sample_chan],
4911 fmask_ptr);
4912 }
4913
4914 if (offsets && instr->op == nir_texop_txf) {
4915 nir_const_value *const_offset =
4916 nir_src_as_const_value(instr->src[const_src].src);
4917 int num_offsets = instr->src[const_src].src.ssa->num_components;
4918 assert(const_offset);
4919 num_offsets = MIN2(num_offsets, instr->coord_components);
4920 if (num_offsets > 2)
4921 address[2] = LLVMBuildAdd(ctx->ac.builder,
4922 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4923 if (num_offsets > 1)
4924 address[1] = LLVMBuildAdd(ctx->ac.builder,
4925 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4926 address[0] = LLVMBuildAdd(ctx->ac.builder,
4927 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4928
4929 }
4930
4931 /* TODO TG4 support */
4932 if (instr->op == nir_texop_tg4) {
4933 if (instr->is_shadow)
4934 dmask = 1;
4935 else
4936 dmask = 1 << instr->component;
4937 }
4938 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4939 res_ptr, samp_ptr, address, count, dmask);
4940
4941 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4942
4943 if (instr->op == nir_texop_query_levels)
4944 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4945 else if (instr->is_shadow && instr->is_new_style_shadow &&
4946 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4947 instr->op != nir_texop_tg4)
4948 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4949 else if (instr->op == nir_texop_txs &&
4950 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4951 instr->is_array) {
4952 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4953 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4954 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4955 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4956 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4957 } else if (ctx->ac.chip_class >= GFX9 &&
4958 instr->op == nir_texop_txs &&
4959 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4960 instr->is_array) {
4961 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4962 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4963 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4964 ctx->ac.i32_1, "");
4965 } else if (instr->dest.ssa.num_components != 4)
4966 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4967
4968 write_result:
4969 if (result) {
4970 assert(instr->dest.is_ssa);
4971 result = ac_to_integer(&ctx->ac, result);
4972 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4973 }
4974 }
4975
4976
4977 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4978 {
4979 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4980 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4981
4982 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4983 _mesa_hash_table_insert(ctx->phis, instr, result);
4984 }
4985
4986 static void visit_post_phi(struct ac_nir_context *ctx,
4987 nir_phi_instr *instr,
4988 LLVMValueRef llvm_phi)
4989 {
4990 nir_foreach_phi_src(src, instr) {
4991 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4992 LLVMValueRef llvm_src = get_src(ctx, src->src);
4993
4994 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4995 }
4996 }
4997
4998 static void phi_post_pass(struct ac_nir_context *ctx)
4999 {
5000 struct hash_entry *entry;
5001 hash_table_foreach(ctx->phis, entry) {
5002 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5003 (LLVMValueRef)entry->data);
5004 }
5005 }
5006
5007
5008 static void visit_ssa_undef(struct ac_nir_context *ctx,
5009 const nir_ssa_undef_instr *instr)
5010 {
5011 unsigned num_components = instr->def.num_components;
5012 LLVMValueRef undef;
5013
5014 if (num_components == 1)
5015 undef = LLVMGetUndef(ctx->ac.i32);
5016 else {
5017 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
5018 }
5019 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5020 }
5021
5022 static void visit_jump(struct ac_nir_context *ctx,
5023 const nir_jump_instr *instr)
5024 {
5025 switch (instr->type) {
5026 case nir_jump_break:
5027 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5028 LLVMClearInsertionPosition(ctx->ac.builder);
5029 break;
5030 case nir_jump_continue:
5031 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5032 LLVMClearInsertionPosition(ctx->ac.builder);
5033 break;
5034 default:
5035 fprintf(stderr, "Unknown NIR jump instr: ");
5036 nir_print_instr(&instr->instr, stderr);
5037 fprintf(stderr, "\n");
5038 abort();
5039 }
5040 }
5041
5042 static void visit_cf_list(struct ac_nir_context *ctx,
5043 struct exec_list *list);
5044
5045 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5046 {
5047 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5048 nir_foreach_instr(instr, block)
5049 {
5050 switch (instr->type) {
5051 case nir_instr_type_alu:
5052 visit_alu(ctx, nir_instr_as_alu(instr));
5053 break;
5054 case nir_instr_type_load_const:
5055 visit_load_const(ctx, nir_instr_as_load_const(instr));
5056 break;
5057 case nir_instr_type_intrinsic:
5058 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5059 break;
5060 case nir_instr_type_tex:
5061 visit_tex(ctx, nir_instr_as_tex(instr));
5062 break;
5063 case nir_instr_type_phi:
5064 visit_phi(ctx, nir_instr_as_phi(instr));
5065 break;
5066 case nir_instr_type_ssa_undef:
5067 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5068 break;
5069 case nir_instr_type_jump:
5070 visit_jump(ctx, nir_instr_as_jump(instr));
5071 break;
5072 default:
5073 fprintf(stderr, "Unknown NIR instr type: ");
5074 nir_print_instr(instr, stderr);
5075 fprintf(stderr, "\n");
5076 abort();
5077 }
5078 }
5079
5080 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5081 }
5082
5083 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5084 {
5085 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5086
5087 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5088 LLVMBasicBlockRef merge_block =
5089 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5090 LLVMBasicBlockRef if_block =
5091 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5092 LLVMBasicBlockRef else_block = merge_block;
5093 if (!exec_list_is_empty(&if_stmt->else_list))
5094 else_block = LLVMAppendBasicBlockInContext(
5095 ctx->ac.context, fn, "");
5096
5097 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5098 ctx->ac.i32_0, "");
5099 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5100
5101 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5102 visit_cf_list(ctx, &if_stmt->then_list);
5103 if (LLVMGetInsertBlock(ctx->ac.builder))
5104 LLVMBuildBr(ctx->ac.builder, merge_block);
5105
5106 if (!exec_list_is_empty(&if_stmt->else_list)) {
5107 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5108 visit_cf_list(ctx, &if_stmt->else_list);
5109 if (LLVMGetInsertBlock(ctx->ac.builder))
5110 LLVMBuildBr(ctx->ac.builder, merge_block);
5111 }
5112
5113 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5114 }
5115
5116 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5117 {
5118 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5119 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5120 LLVMBasicBlockRef break_parent = ctx->break_block;
5121
5122 ctx->continue_block =
5123 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5124 ctx->break_block =
5125 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5126
5127 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5128 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5129 visit_cf_list(ctx, &loop->body);
5130
5131 if (LLVMGetInsertBlock(ctx->ac.builder))
5132 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5133 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5134
5135 ctx->continue_block = continue_parent;
5136 ctx->break_block = break_parent;
5137 }
5138
5139 static void visit_cf_list(struct ac_nir_context *ctx,
5140 struct exec_list *list)
5141 {
5142 foreach_list_typed(nir_cf_node, node, node, list)
5143 {
5144 switch (node->type) {
5145 case nir_cf_node_block:
5146 visit_block(ctx, nir_cf_node_as_block(node));
5147 break;
5148
5149 case nir_cf_node_if:
5150 visit_if(ctx, nir_cf_node_as_if(node));
5151 break;
5152
5153 case nir_cf_node_loop:
5154 visit_loop(ctx, nir_cf_node_as_loop(node));
5155 break;
5156
5157 default:
5158 assert(0);
5159 }
5160 }
5161 }
5162
5163 static void
5164 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5165 struct nir_variable *variable)
5166 {
5167 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5168 LLVMValueRef t_offset;
5169 LLVMValueRef t_list;
5170 LLVMValueRef input;
5171 LLVMValueRef buffer_index;
5172 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5173 int idx = variable->data.location;
5174 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5175
5176 variable->data.driver_location = idx * 4;
5177
5178 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5179 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5180 ctx->abi.start_instance, "");
5181 if (ctx->options->key.vs.as_ls) {
5182 ctx->shader_info->vs.vgpr_comp_cnt =
5183 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5184 } else {
5185 ctx->shader_info->vs.vgpr_comp_cnt =
5186 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5187 }
5188 } else
5189 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5190 ctx->abi.base_vertex, "");
5191
5192 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5193 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5194
5195 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5196
5197 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5198 buffer_index,
5199 ctx->ac.i32_0,
5200 true);
5201
5202 for (unsigned chan = 0; chan < 4; chan++) {
5203 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5204 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5205 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5206 input, llvm_chan, ""));
5207 }
5208 }
5209 }
5210
5211 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5212 unsigned attr,
5213 LLVMValueRef interp_param,
5214 LLVMValueRef prim_mask,
5215 LLVMValueRef result[4])
5216 {
5217 LLVMValueRef attr_number;
5218 unsigned chan;
5219 LLVMValueRef i, j;
5220 bool interp = interp_param != NULL;
5221
5222 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5223
5224 /* fs.constant returns the param from the middle vertex, so it's not
5225 * really useful for flat shading. It's meant to be used for custom
5226 * interpolation (but the intrinsic can't fetch from the other two
5227 * vertices).
5228 *
5229 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5230 * to do the right thing. The only reason we use fs.constant is that
5231 * fs.interp cannot be used on integers, because they can be equal
5232 * to NaN.
5233 */
5234 if (interp) {
5235 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5236 ctx->ac.v2f32, "");
5237
5238 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5239 ctx->ac.i32_0, "");
5240 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5241 ctx->ac.i32_1, "");
5242 }
5243
5244 for (chan = 0; chan < 4; chan++) {
5245 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5246
5247 if (interp) {
5248 result[chan] = ac_build_fs_interp(&ctx->ac,
5249 llvm_chan,
5250 attr_number,
5251 prim_mask, i, j);
5252 } else {
5253 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5254 LLVMConstInt(ctx->ac.i32, 2, false),
5255 llvm_chan,
5256 attr_number,
5257 prim_mask);
5258 }
5259 }
5260 }
5261
5262 static void
5263 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5264 struct nir_variable *variable)
5265 {
5266 int idx = variable->data.location;
5267 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5268 LLVMValueRef interp;
5269
5270 variable->data.driver_location = idx * 4;
5271 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5272
5273 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5274 unsigned interp_type;
5275 if (variable->data.sample) {
5276 interp_type = INTERP_SAMPLE;
5277 ctx->shader_info->info.ps.force_persample = true;
5278 } else if (variable->data.centroid)
5279 interp_type = INTERP_CENTROID;
5280 else
5281 interp_type = INTERP_CENTER;
5282
5283 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5284 } else
5285 interp = NULL;
5286
5287 for (unsigned i = 0; i < attrib_count; ++i)
5288 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5289
5290 }
5291
5292 static void
5293 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5294 struct nir_shader *nir) {
5295 nir_foreach_variable(variable, &nir->inputs)
5296 handle_vs_input_decl(ctx, variable);
5297 }
5298
5299 static void
5300 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5301 struct nir_shader *nir)
5302 {
5303 if (!ctx->options->key.fs.multisample)
5304 return;
5305
5306 bool uses_center = false;
5307 bool uses_centroid = false;
5308 nir_foreach_variable(variable, &nir->inputs) {
5309 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5310 variable->data.sample)
5311 continue;
5312
5313 if (variable->data.centroid)
5314 uses_centroid = true;
5315 else
5316 uses_center = true;
5317 }
5318
5319 if (uses_center && uses_centroid) {
5320 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5321 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5322 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5323 }
5324 }
5325
5326 static void
5327 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5328 struct nir_shader *nir)
5329 {
5330 prepare_interp_optimize(ctx, nir);
5331
5332 nir_foreach_variable(variable, &nir->inputs)
5333 handle_fs_input_decl(ctx, variable);
5334
5335 unsigned index = 0;
5336
5337 if (ctx->shader_info->info.ps.uses_input_attachments ||
5338 ctx->shader_info->info.needs_multiview_view_index)
5339 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5340
5341 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5342 LLVMValueRef interp_param;
5343 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5344
5345 if (!(ctx->input_mask & (1ull << i)))
5346 continue;
5347
5348 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5349 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5350 interp_param = *inputs;
5351 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5352 inputs);
5353
5354 if (!interp_param)
5355 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5356 ++index;
5357 } else if (i == VARYING_SLOT_POS) {
5358 for(int i = 0; i < 3; ++i)
5359 inputs[i] = ctx->abi.frag_pos[i];
5360
5361 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5362 ctx->abi.frag_pos[3]);
5363 }
5364 }
5365 ctx->shader_info->fs.num_interp = index;
5366 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5367 ctx->shader_info->fs.has_pcoord = true;
5368 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5369 ctx->shader_info->fs.prim_id_input = true;
5370 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5371 ctx->shader_info->fs.layer_input = true;
5372 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5373
5374 if (ctx->shader_info->info.needs_multiview_view_index)
5375 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5376 }
5377
5378 static LLVMValueRef
5379 ac_build_alloca(struct ac_llvm_context *ac,
5380 LLVMTypeRef type,
5381 const char *name)
5382 {
5383 LLVMBuilderRef builder = ac->builder;
5384 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5385 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5386 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5387 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5388 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5389 LLVMValueRef res;
5390
5391 if (first_instr) {
5392 LLVMPositionBuilderBefore(first_builder, first_instr);
5393 } else {
5394 LLVMPositionBuilderAtEnd(first_builder, first_block);
5395 }
5396
5397 res = LLVMBuildAlloca(first_builder, type, name);
5398 LLVMBuildStore(builder, LLVMConstNull(type), res);
5399
5400 LLVMDisposeBuilder(first_builder);
5401
5402 return res;
5403 }
5404
5405 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5406 LLVMTypeRef type,
5407 const char *name)
5408 {
5409 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5410 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5411 return ptr;
5412 }
5413
5414 static void
5415 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5416 struct nir_variable *variable,
5417 struct nir_shader *shader,
5418 gl_shader_stage stage)
5419 {
5420 int idx = variable->data.location + variable->data.index;
5421 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5422 uint64_t mask_attribs;
5423
5424 variable->data.driver_location = idx * 4;
5425
5426 /* tess ctrl has it's own load/store paths for outputs */
5427 if (stage == MESA_SHADER_TESS_CTRL)
5428 return;
5429
5430 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5431 if (stage == MESA_SHADER_VERTEX ||
5432 stage == MESA_SHADER_TESS_EVAL ||
5433 stage == MESA_SHADER_GEOMETRY) {
5434 if (idx == VARYING_SLOT_CLIP_DIST0) {
5435 int length = shader->info.clip_distance_array_size +
5436 shader->info.cull_distance_array_size;
5437 if (stage == MESA_SHADER_VERTEX) {
5438 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5439 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5440 }
5441 if (stage == MESA_SHADER_TESS_EVAL) {
5442 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5443 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5444 }
5445
5446 if (length > 4)
5447 attrib_count = 2;
5448 else
5449 attrib_count = 1;
5450 mask_attribs = 1ull << idx;
5451 }
5452 }
5453
5454 ctx->output_mask |= mask_attribs;
5455 }
5456
5457 static void
5458 handle_shader_output_decl(struct ac_nir_context *ctx,
5459 struct nir_shader *nir,
5460 struct nir_variable *variable)
5461 {
5462 unsigned output_loc = variable->data.driver_location / 4;
5463 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5464
5465 /* tess ctrl has it's own load/store paths for outputs */
5466 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5467 return;
5468
5469 if (ctx->stage == MESA_SHADER_VERTEX ||
5470 ctx->stage == MESA_SHADER_TESS_EVAL ||
5471 ctx->stage == MESA_SHADER_GEOMETRY) {
5472 int idx = variable->data.location + variable->data.index;
5473 if (idx == VARYING_SLOT_CLIP_DIST0) {
5474 int length = nir->info.clip_distance_array_size +
5475 nir->info.cull_distance_array_size;
5476
5477 if (length > 4)
5478 attrib_count = 2;
5479 else
5480 attrib_count = 1;
5481 }
5482 }
5483
5484 for (unsigned i = 0; i < attrib_count; ++i) {
5485 for (unsigned chan = 0; chan < 4; chan++) {
5486 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5487 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5488 }
5489 }
5490 }
5491
5492 static LLVMTypeRef
5493 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5494 enum glsl_base_type type)
5495 {
5496 switch (type) {
5497 case GLSL_TYPE_INT:
5498 case GLSL_TYPE_UINT:
5499 case GLSL_TYPE_BOOL:
5500 case GLSL_TYPE_SUBROUTINE:
5501 return ctx->ac.i32;
5502 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5503 return ctx->ac.f32;
5504 case GLSL_TYPE_INT64:
5505 case GLSL_TYPE_UINT64:
5506 return ctx->ac.i64;
5507 case GLSL_TYPE_DOUBLE:
5508 return ctx->ac.f64;
5509 default:
5510 unreachable("unknown GLSL type");
5511 }
5512 }
5513
5514 static LLVMTypeRef
5515 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5516 const struct glsl_type *type)
5517 {
5518 if (glsl_type_is_scalar(type)) {
5519 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5520 }
5521
5522 if (glsl_type_is_vector(type)) {
5523 return LLVMVectorType(
5524 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5525 glsl_get_vector_elements(type));
5526 }
5527
5528 if (glsl_type_is_matrix(type)) {
5529 return LLVMArrayType(
5530 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5531 glsl_get_matrix_columns(type));
5532 }
5533
5534 if (glsl_type_is_array(type)) {
5535 return LLVMArrayType(
5536 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5537 glsl_get_length(type));
5538 }
5539
5540 assert(glsl_type_is_struct(type));
5541
5542 LLVMTypeRef member_types[glsl_get_length(type)];
5543
5544 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5545 member_types[i] =
5546 glsl_to_llvm_type(ctx,
5547 glsl_get_struct_field(type, i));
5548 }
5549
5550 return LLVMStructTypeInContext(ctx->context, member_types,
5551 glsl_get_length(type), false);
5552 }
5553
5554 static void
5555 setup_locals(struct ac_nir_context *ctx,
5556 struct nir_function *func)
5557 {
5558 int i, j;
5559 ctx->num_locals = 0;
5560 nir_foreach_variable(variable, &func->impl->locals) {
5561 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5562 variable->data.driver_location = ctx->num_locals * 4;
5563 ctx->num_locals += attrib_count;
5564 }
5565 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5566 if (!ctx->locals)
5567 return;
5568
5569 for (i = 0; i < ctx->num_locals; i++) {
5570 for (j = 0; j < 4; j++) {
5571 ctx->locals[i * 4 + j] =
5572 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5573 }
5574 }
5575 }
5576
5577 static void
5578 setup_shared(struct ac_nir_context *ctx,
5579 struct nir_shader *nir)
5580 {
5581 nir_foreach_variable(variable, &nir->shared) {
5582 LLVMValueRef shared =
5583 LLVMAddGlobalInAddressSpace(
5584 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5585 variable->name ? variable->name : "",
5586 LOCAL_ADDR_SPACE);
5587 _mesa_hash_table_insert(ctx->vars, variable, shared);
5588 }
5589 }
5590
5591 static LLVMValueRef
5592 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5593 {
5594 v = ac_to_float(ctx, v);
5595 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5596 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5597 }
5598
5599
5600 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5601 LLVMValueRef src0, LLVMValueRef src1)
5602 {
5603 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5604 LLVMValueRef comp[2];
5605
5606 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5607 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5608 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5609 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5610 }
5611
5612 /* Initialize arguments for the shader export intrinsic */
5613 static void
5614 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5615 LLVMValueRef *values,
5616 unsigned target,
5617 struct ac_export_args *args)
5618 {
5619 /* Default is 0xf. Adjusted below depending on the format. */
5620 args->enabled_channels = 0xf;
5621
5622 /* Specify whether the EXEC mask represents the valid mask */
5623 args->valid_mask = 0;
5624
5625 /* Specify whether this is the last export */
5626 args->done = 0;
5627
5628 /* Specify the target we are exporting */
5629 args->target = target;
5630
5631 args->compr = false;
5632 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5633 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5634 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5635 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5636
5637 if (!values)
5638 return;
5639
5640 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5641 LLVMValueRef val[4];
5642 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5643 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5644 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5645 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5646
5647 switch(col_format) {
5648 case V_028714_SPI_SHADER_ZERO:
5649 args->enabled_channels = 0; /* writemask */
5650 args->target = V_008DFC_SQ_EXP_NULL;
5651 break;
5652
5653 case V_028714_SPI_SHADER_32_R:
5654 args->enabled_channels = 1;
5655 args->out[0] = values[0];
5656 break;
5657
5658 case V_028714_SPI_SHADER_32_GR:
5659 args->enabled_channels = 0x3;
5660 args->out[0] = values[0];
5661 args->out[1] = values[1];
5662 break;
5663
5664 case V_028714_SPI_SHADER_32_AR:
5665 args->enabled_channels = 0x9;
5666 args->out[0] = values[0];
5667 args->out[3] = values[3];
5668 break;
5669
5670 case V_028714_SPI_SHADER_FP16_ABGR:
5671 args->compr = 1;
5672
5673 for (unsigned chan = 0; chan < 2; chan++) {
5674 LLVMValueRef pack_args[2] = {
5675 values[2 * chan],
5676 values[2 * chan + 1]
5677 };
5678 LLVMValueRef packed;
5679
5680 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5681 args->out[chan] = packed;
5682 }
5683 break;
5684
5685 case V_028714_SPI_SHADER_UNORM16_ABGR:
5686 for (unsigned chan = 0; chan < 4; chan++) {
5687 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5688 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5689 LLVMConstReal(ctx->ac.f32, 65535), "");
5690 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5691 LLVMConstReal(ctx->ac.f32, 0.5), "");
5692 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5693 ctx->ac.i32, "");
5694 }
5695
5696 args->compr = 1;
5697 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5698 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5699 break;
5700
5701 case V_028714_SPI_SHADER_SNORM16_ABGR:
5702 for (unsigned chan = 0; chan < 4; chan++) {
5703 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5704 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5705 LLVMConstReal(ctx->ac.f32, 32767), "");
5706
5707 /* If positive, add 0.5, else add -0.5. */
5708 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5709 LLVMBuildSelect(ctx->builder,
5710 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5711 val[chan], ctx->ac.f32_0, ""),
5712 LLVMConstReal(ctx->ac.f32, 0.5),
5713 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5714 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5715 }
5716
5717 args->compr = 1;
5718 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5719 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5720 break;
5721
5722 case V_028714_SPI_SHADER_UINT16_ABGR: {
5723 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5724 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5725 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5726
5727 for (unsigned chan = 0; chan < 4; chan++) {
5728 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5729 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5730 }
5731
5732 args->compr = 1;
5733 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5734 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5735 break;
5736 }
5737
5738 case V_028714_SPI_SHADER_SINT16_ABGR: {
5739 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5740 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5741 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5742 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5743 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5744 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5745
5746 /* Clamp. */
5747 for (unsigned chan = 0; chan < 4; chan++) {
5748 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5749 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5750 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5751 }
5752
5753 args->compr = 1;
5754 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5755 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5756 break;
5757 }
5758
5759 default:
5760 case V_028714_SPI_SHADER_32_ABGR:
5761 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5762 break;
5763 }
5764 } else
5765 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5766
5767 for (unsigned i = 0; i < 4; ++i)
5768 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5769 }
5770
5771 static void
5772 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5773 bool export_prim_id,
5774 struct ac_vs_output_info *outinfo)
5775 {
5776 uint32_t param_count = 0;
5777 unsigned target;
5778 unsigned pos_idx, num_pos_exports = 0;
5779 struct ac_export_args args, pos_args[4] = {};
5780 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5781 int i;
5782
5783 if (ctx->options->key.has_multiview_view_index) {
5784 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5785 if(!*tmp_out) {
5786 for(unsigned i = 0; i < 4; ++i)
5787 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5788 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5789 }
5790
5791 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5792 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5793 }
5794
5795 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5796 sizeof(outinfo->vs_output_param_offset));
5797
5798 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5799 LLVMValueRef slots[8];
5800 unsigned j;
5801
5802 if (outinfo->cull_dist_mask)
5803 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5804
5805 i = VARYING_SLOT_CLIP_DIST0;
5806 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5807 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5808 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5809
5810 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5811 slots[i] = LLVMGetUndef(ctx->ac.f32);
5812
5813 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5814 target = V_008DFC_SQ_EXP_POS + 3;
5815 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5816 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5817 &args, sizeof(args));
5818 }
5819
5820 target = V_008DFC_SQ_EXP_POS + 2;
5821 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5822 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5823 &args, sizeof(args));
5824
5825 }
5826
5827 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5828 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5829 for (unsigned j = 0; j < 4; j++)
5830 pos_values[j] = LLVMBuildLoad(ctx->builder,
5831 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5832 }
5833 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5834
5835 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5836 outinfo->writes_pointsize = true;
5837 psize_value = LLVMBuildLoad(ctx->builder,
5838 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5839 }
5840
5841 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5842 outinfo->writes_layer = true;
5843 layer_value = LLVMBuildLoad(ctx->builder,
5844 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5845 }
5846
5847 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5848 outinfo->writes_viewport_index = true;
5849 viewport_index_value = LLVMBuildLoad(ctx->builder,
5850 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5851 }
5852
5853 if (outinfo->writes_pointsize ||
5854 outinfo->writes_layer ||
5855 outinfo->writes_viewport_index) {
5856 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5857 (outinfo->writes_layer == true ? 4 : 0));
5858 pos_args[1].valid_mask = 0;
5859 pos_args[1].done = 0;
5860 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5861 pos_args[1].compr = 0;
5862 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5863 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5864 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5865 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5866
5867 if (outinfo->writes_pointsize == true)
5868 pos_args[1].out[0] = psize_value;
5869 if (outinfo->writes_layer == true)
5870 pos_args[1].out[2] = layer_value;
5871 if (outinfo->writes_viewport_index == true) {
5872 if (ctx->options->chip_class >= GFX9) {
5873 /* GFX9 has the layer in out.z[10:0] and the viewport
5874 * index in out.z[19:16].
5875 */
5876 LLVMValueRef v = viewport_index_value;
5877 v = ac_to_integer(&ctx->ac, v);
5878 v = LLVMBuildShl(ctx->builder, v,
5879 LLVMConstInt(ctx->ac.i32, 16, false),
5880 "");
5881 v = LLVMBuildOr(ctx->builder, v,
5882 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5883
5884 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5885 pos_args[1].enabled_channels |= 1 << 2;
5886 } else {
5887 pos_args[1].out[3] = viewport_index_value;
5888 pos_args[1].enabled_channels |= 1 << 3;
5889 }
5890 }
5891 }
5892 for (i = 0; i < 4; i++) {
5893 if (pos_args[i].out[0])
5894 num_pos_exports++;
5895 }
5896
5897 pos_idx = 0;
5898 for (i = 0; i < 4; i++) {
5899 if (!pos_args[i].out[0])
5900 continue;
5901
5902 /* Specify the target we are exporting */
5903 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5904 if (pos_idx == num_pos_exports)
5905 pos_args[i].done = 1;
5906 ac_build_export(&ctx->ac, &pos_args[i]);
5907 }
5908
5909 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5910 LLVMValueRef values[4];
5911 if (!(ctx->output_mask & (1ull << i)))
5912 continue;
5913
5914 for (unsigned j = 0; j < 4; j++)
5915 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5916 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5917
5918 if (i == VARYING_SLOT_LAYER) {
5919 target = V_008DFC_SQ_EXP_PARAM + param_count;
5920 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5921 param_count++;
5922 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5923 target = V_008DFC_SQ_EXP_PARAM + param_count;
5924 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5925 param_count++;
5926 } else if (i >= VARYING_SLOT_VAR0) {
5927 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5928 target = V_008DFC_SQ_EXP_PARAM + param_count;
5929 outinfo->vs_output_param_offset[i] = param_count;
5930 param_count++;
5931 } else
5932 continue;
5933
5934 si_llvm_init_export_args(ctx, values, target, &args);
5935
5936 if (target >= V_008DFC_SQ_EXP_POS &&
5937 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5938 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5939 &args, sizeof(args));
5940 } else {
5941 ac_build_export(&ctx->ac, &args);
5942 }
5943 }
5944
5945 if (export_prim_id) {
5946 LLVMValueRef values[4];
5947 target = V_008DFC_SQ_EXP_PARAM + param_count;
5948 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5949 param_count++;
5950
5951 values[0] = ctx->vs_prim_id;
5952 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5953 ctx->shader_info->vs.vgpr_comp_cnt);
5954 for (unsigned j = 1; j < 4; j++)
5955 values[j] = ctx->ac.f32_0;
5956 si_llvm_init_export_args(ctx, values, target, &args);
5957 ac_build_export(&ctx->ac, &args);
5958 outinfo->export_prim_id = true;
5959 }
5960
5961 outinfo->pos_exports = num_pos_exports;
5962 outinfo->param_exports = param_count;
5963 }
5964
5965 static void
5966 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5967 struct ac_es_output_info *outinfo)
5968 {
5969 int j;
5970 uint64_t max_output_written = 0;
5971 LLVMValueRef lds_base = NULL;
5972
5973 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5974 int param_index;
5975 int length = 4;
5976
5977 if (!(ctx->output_mask & (1ull << i)))
5978 continue;
5979
5980 if (i == VARYING_SLOT_CLIP_DIST0)
5981 length = ctx->num_output_clips + ctx->num_output_culls;
5982
5983 param_index = shader_io_get_unique_index(i);
5984
5985 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5986 }
5987
5988 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5989
5990 if (ctx->ac.chip_class >= GFX9) {
5991 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5992 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5993 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5994 LLVMConstInt(ctx->ac.i32, 24, false),
5995 LLVMConstInt(ctx->ac.i32, 4, false), false);
5996 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5997 LLVMBuildMul(ctx->ac.builder, wave_idx,
5998 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5999 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6000 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6001 }
6002
6003 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6004 LLVMValueRef dw_addr;
6005 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6006 int param_index;
6007 int length = 4;
6008
6009 if (!(ctx->output_mask & (1ull << i)))
6010 continue;
6011
6012 if (i == VARYING_SLOT_CLIP_DIST0)
6013 length = ctx->num_output_clips + ctx->num_output_culls;
6014
6015 param_index = shader_io_get_unique_index(i);
6016
6017 if (lds_base) {
6018 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6019 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6020 "");
6021 }
6022 for (j = 0; j < length; j++) {
6023 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6024 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6025
6026 if (ctx->ac.chip_class >= GFX9) {
6027 ac_lds_store(&ctx->ac, dw_addr,
6028 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6029 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6030 } else {
6031 ac_build_buffer_store_dword(&ctx->ac,
6032 ctx->esgs_ring,
6033 out_val, 1,
6034 NULL, ctx->es2gs_offset,
6035 (4 * param_index + j) * 4,
6036 1, 1, true, true);
6037 }
6038 }
6039 }
6040 }
6041
6042 static void
6043 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6044 {
6045 LLVMValueRef vertex_id = ctx->rel_auto_id;
6046 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6047 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6048 vertex_dw_stride, "");
6049
6050 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6051 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6052 int length = 4;
6053
6054 if (!(ctx->output_mask & (1ull << i)))
6055 continue;
6056
6057 if (i == VARYING_SLOT_CLIP_DIST0)
6058 length = ctx->num_output_clips + ctx->num_output_culls;
6059 int param = shader_io_get_unique_index(i);
6060 mark_tess_output(ctx, false, param);
6061 if (length > 4)
6062 mark_tess_output(ctx, false, param + 1);
6063 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6064 LLVMConstInt(ctx->ac.i32, param * 4, false),
6065 "");
6066 for (unsigned j = 0; j < length; j++) {
6067 ac_lds_store(&ctx->ac, dw_addr,
6068 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6069 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6070 }
6071 }
6072 }
6073
6074 struct ac_build_if_state
6075 {
6076 struct nir_to_llvm_context *ctx;
6077 LLVMValueRef condition;
6078 LLVMBasicBlockRef entry_block;
6079 LLVMBasicBlockRef true_block;
6080 LLVMBasicBlockRef false_block;
6081 LLVMBasicBlockRef merge_block;
6082 };
6083
6084 static LLVMBasicBlockRef
6085 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6086 {
6087 LLVMBasicBlockRef current_block;
6088 LLVMBasicBlockRef next_block;
6089 LLVMBasicBlockRef new_block;
6090
6091 /* get current basic block */
6092 current_block = LLVMGetInsertBlock(ctx->builder);
6093
6094 /* chqeck if there's another block after this one */
6095 next_block = LLVMGetNextBasicBlock(current_block);
6096 if (next_block) {
6097 /* insert the new block before the next block */
6098 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6099 }
6100 else {
6101 /* append new block after current block */
6102 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6103 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6104 }
6105 return new_block;
6106 }
6107
6108 static void
6109 ac_nir_build_if(struct ac_build_if_state *ifthen,
6110 struct nir_to_llvm_context *ctx,
6111 LLVMValueRef condition)
6112 {
6113 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6114
6115 memset(ifthen, 0, sizeof *ifthen);
6116 ifthen->ctx = ctx;
6117 ifthen->condition = condition;
6118 ifthen->entry_block = block;
6119
6120 /* create endif/merge basic block for the phi functions */
6121 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6122
6123 /* create/insert true_block before merge_block */
6124 ifthen->true_block =
6125 LLVMInsertBasicBlockInContext(ctx->context,
6126 ifthen->merge_block,
6127 "if-true-block");
6128
6129 /* successive code goes into the true block */
6130 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6131 }
6132
6133 /**
6134 * End a conditional.
6135 */
6136 static void
6137 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6138 {
6139 LLVMBuilderRef builder = ifthen->ctx->builder;
6140
6141 /* Insert branch to the merge block from current block */
6142 LLVMBuildBr(builder, ifthen->merge_block);
6143
6144 /*
6145 * Now patch in the various branch instructions.
6146 */
6147
6148 /* Insert the conditional branch instruction at the end of entry_block */
6149 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6150 if (ifthen->false_block) {
6151 /* we have an else clause */
6152 LLVMBuildCondBr(builder, ifthen->condition,
6153 ifthen->true_block, ifthen->false_block);
6154 }
6155 else {
6156 /* no else clause */
6157 LLVMBuildCondBr(builder, ifthen->condition,
6158 ifthen->true_block, ifthen->merge_block);
6159 }
6160
6161 /* Resume building code at end of the ifthen->merge_block */
6162 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6163 }
6164
6165 static void
6166 write_tess_factors(struct nir_to_llvm_context *ctx)
6167 {
6168 unsigned stride, outer_comps, inner_comps;
6169 struct ac_build_if_state if_ctx, inner_if_ctx;
6170 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6171 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6172 unsigned tess_inner_index, tess_outer_index;
6173 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6174 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6175 int i;
6176 emit_barrier(ctx);
6177
6178 switch (ctx->options->key.tcs.primitive_mode) {
6179 case GL_ISOLINES:
6180 stride = 2;
6181 outer_comps = 2;
6182 inner_comps = 0;
6183 break;
6184 case GL_TRIANGLES:
6185 stride = 4;
6186 outer_comps = 3;
6187 inner_comps = 1;
6188 break;
6189 case GL_QUADS:
6190 stride = 6;
6191 outer_comps = 4;
6192 inner_comps = 2;
6193 break;
6194 default:
6195 return;
6196 }
6197
6198 ac_nir_build_if(&if_ctx, ctx,
6199 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6200 invocation_id, ctx->ac.i32_0, ""));
6201
6202 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6203 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6204
6205 mark_tess_output(ctx, true, tess_inner_index);
6206 mark_tess_output(ctx, true, tess_outer_index);
6207 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6208 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6209 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6210 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6211 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6212
6213 for (i = 0; i < 4; i++) {
6214 inner[i] = LLVMGetUndef(ctx->ac.i32);
6215 outer[i] = LLVMGetUndef(ctx->ac.i32);
6216 }
6217
6218 // LINES reverseal
6219 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6220 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6221 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6222 ctx->ac.i32_1, "");
6223 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6224 } else {
6225 for (i = 0; i < outer_comps; i++) {
6226 outer[i] = out[i] =
6227 ac_lds_load(&ctx->ac, lds_outer);
6228 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6229 ctx->ac.i32_1, "");
6230 }
6231 for (i = 0; i < inner_comps; i++) {
6232 inner[i] = out[outer_comps+i] =
6233 ac_lds_load(&ctx->ac, lds_inner);
6234 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6235 ctx->ac.i32_1, "");
6236 }
6237 }
6238
6239 /* Convert the outputs to vectors for stores. */
6240 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6241 vec1 = NULL;
6242
6243 if (stride > 4)
6244 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6245
6246
6247 buffer = ctx->hs_ring_tess_factor;
6248 tf_base = ctx->tess_factor_offset;
6249 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6250 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6251 unsigned tf_offset = 0;
6252
6253 if (ctx->options->chip_class <= VI) {
6254 ac_nir_build_if(&inner_if_ctx, ctx,
6255 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6256 rel_patch_id, ctx->ac.i32_0, ""));
6257
6258 /* Store the dynamic HS control word. */
6259 ac_build_buffer_store_dword(&ctx->ac, buffer,
6260 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6261 1, ctx->ac.i32_0, tf_base,
6262 0, 1, 0, true, false);
6263 tf_offset += 4;
6264
6265 ac_nir_build_endif(&inner_if_ctx);
6266 }
6267
6268 /* Store the tessellation factors. */
6269 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6270 MIN2(stride, 4), byteoffset, tf_base,
6271 tf_offset, 1, 0, true, false);
6272 if (vec1)
6273 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6274 stride - 4, byteoffset, tf_base,
6275 16 + tf_offset, 1, 0, true, false);
6276
6277 //store to offchip for TES to read - only if TES reads them
6278 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6279 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6280 LLVMValueRef tf_inner_offset;
6281 unsigned param_outer, param_inner;
6282
6283 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6284 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6285 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6286
6287 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6288 util_next_power_of_two(outer_comps));
6289
6290 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6291 outer_comps, tf_outer_offset,
6292 ctx->oc_lds, 0, 1, 0, true, false);
6293 if (inner_comps) {
6294 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6295 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6296 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6297
6298 inner_vec = inner_comps == 1 ? inner[0] :
6299 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6300 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6301 inner_comps, tf_inner_offset,
6302 ctx->oc_lds, 0, 1, 0, true, false);
6303 }
6304 }
6305 ac_nir_build_endif(&if_ctx);
6306 }
6307
6308 static void
6309 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6310 {
6311 write_tess_factors(ctx);
6312 }
6313
6314 static bool
6315 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6316 LLVMValueRef *color, unsigned param, bool is_last,
6317 struct ac_export_args *args)
6318 {
6319 /* Export */
6320 si_llvm_init_export_args(ctx, color, param,
6321 args);
6322
6323 if (is_last) {
6324 args->valid_mask = 1; /* whether the EXEC mask is valid */
6325 args->done = 1; /* DONE bit */
6326 } else if (!args->enabled_channels)
6327 return false; /* unnecessary NULL export */
6328
6329 return true;
6330 }
6331
6332 static void
6333 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6334 LLVMValueRef depth, LLVMValueRef stencil,
6335 LLVMValueRef samplemask)
6336 {
6337 struct ac_export_args args;
6338
6339 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6340
6341 ac_build_export(&ctx->ac, &args);
6342 }
6343
6344 static void
6345 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6346 {
6347 unsigned index = 0;
6348 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6349 struct ac_export_args color_args[8];
6350
6351 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6352 LLVMValueRef values[4];
6353
6354 if (!(ctx->output_mask & (1ull << i)))
6355 continue;
6356
6357 if (i == FRAG_RESULT_DEPTH) {
6358 ctx->shader_info->fs.writes_z = true;
6359 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6360 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6361 } else if (i == FRAG_RESULT_STENCIL) {
6362 ctx->shader_info->fs.writes_stencil = true;
6363 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6364 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6365 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6366 ctx->shader_info->fs.writes_sample_mask = true;
6367 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6368 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6369 } else {
6370 bool last = false;
6371 for (unsigned j = 0; j < 4; j++)
6372 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6373 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6374
6375 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6376 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6377
6378 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6379 if (ret)
6380 index++;
6381 }
6382 }
6383
6384 for (unsigned i = 0; i < index; i++)
6385 ac_build_export(&ctx->ac, &color_args[i]);
6386 if (depth || stencil || samplemask)
6387 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6388 else if (!index) {
6389 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6390 ac_build_export(&ctx->ac, &color_args[0]);
6391 }
6392
6393 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6394 }
6395
6396 static void
6397 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6398 {
6399 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6400 }
6401
6402 static void
6403 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6404 LLVMValueRef *addrs)
6405 {
6406 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6407
6408 switch (ctx->stage) {
6409 case MESA_SHADER_VERTEX:
6410 if (ctx->options->key.vs.as_ls)
6411 handle_ls_outputs_post(ctx);
6412 else if (ctx->options->key.vs.as_es)
6413 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6414 else
6415 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6416 &ctx->shader_info->vs.outinfo);
6417 break;
6418 case MESA_SHADER_FRAGMENT:
6419 handle_fs_outputs_post(ctx);
6420 break;
6421 case MESA_SHADER_GEOMETRY:
6422 emit_gs_epilogue(ctx);
6423 break;
6424 case MESA_SHADER_TESS_CTRL:
6425 handle_tcs_outputs_post(ctx);
6426 break;
6427 case MESA_SHADER_TESS_EVAL:
6428 if (ctx->options->key.tes.as_es)
6429 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6430 else
6431 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6432 &ctx->shader_info->tes.outinfo);
6433 break;
6434 default:
6435 break;
6436 }
6437 }
6438
6439 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6440 {
6441 LLVMPassManagerRef passmgr;
6442 /* Create the pass manager */
6443 passmgr = LLVMCreateFunctionPassManagerForModule(
6444 ctx->module);
6445
6446 /* This pass should eliminate all the load and store instructions */
6447 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6448
6449 /* Add some optimization passes */
6450 LLVMAddScalarReplAggregatesPass(passmgr);
6451 LLVMAddLICMPass(passmgr);
6452 LLVMAddAggressiveDCEPass(passmgr);
6453 LLVMAddCFGSimplificationPass(passmgr);
6454 LLVMAddInstructionCombiningPass(passmgr);
6455
6456 /* Run the pass */
6457 LLVMInitializeFunctionPassManager(passmgr);
6458 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6459 LLVMFinalizeFunctionPassManager(passmgr);
6460
6461 LLVMDisposeBuilder(ctx->builder);
6462 LLVMDisposePassManager(passmgr);
6463 }
6464
6465 static void
6466 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6467 {
6468 struct ac_vs_output_info *outinfo;
6469
6470 switch (ctx->stage) {
6471 case MESA_SHADER_FRAGMENT:
6472 case MESA_SHADER_COMPUTE:
6473 case MESA_SHADER_TESS_CTRL:
6474 case MESA_SHADER_GEOMETRY:
6475 return;
6476 case MESA_SHADER_VERTEX:
6477 if (ctx->options->key.vs.as_ls ||
6478 ctx->options->key.vs.as_es)
6479 return;
6480 outinfo = &ctx->shader_info->vs.outinfo;
6481 break;
6482 case MESA_SHADER_TESS_EVAL:
6483 if (ctx->options->key.vs.as_es)
6484 return;
6485 outinfo = &ctx->shader_info->tes.outinfo;
6486 break;
6487 default:
6488 unreachable("Unhandled shader type");
6489 }
6490
6491 ac_optimize_vs_outputs(&ctx->ac,
6492 ctx->main_function,
6493 outinfo->vs_output_param_offset,
6494 VARYING_SLOT_MAX,
6495 &outinfo->param_exports);
6496 }
6497
6498 static void
6499 ac_setup_rings(struct nir_to_llvm_context *ctx)
6500 {
6501 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6502 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6503 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6504 }
6505
6506 if (ctx->is_gs_copy_shader) {
6507 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6508 }
6509 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6510 LLVMValueRef tmp;
6511 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6512 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6513
6514 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6515
6516 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6517 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6518 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6519 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6520 }
6521
6522 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6523 ctx->stage == MESA_SHADER_TESS_EVAL) {
6524 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6525 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6526 }
6527 }
6528
6529 static unsigned
6530 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6531 const struct nir_shader *nir)
6532 {
6533 switch (nir->info.stage) {
6534 case MESA_SHADER_TESS_CTRL:
6535 return chip_class >= CIK ? 128 : 64;
6536 case MESA_SHADER_GEOMETRY:
6537 return chip_class >= GFX9 ? 128 : 64;
6538 case MESA_SHADER_COMPUTE:
6539 break;
6540 default:
6541 return 0;
6542 }
6543
6544 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6545 nir->info.cs.local_size[1] *
6546 nir->info.cs.local_size[2];
6547 return max_workgroup_size;
6548 }
6549
6550 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6551 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6552 {
6553 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6554 LLVMConstInt(ctx->ac.i32, 8, false),
6555 LLVMConstInt(ctx->ac.i32, 8, false), false);
6556 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6557 ctx->ac.i32_0, "");
6558 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6559 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6560 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6561 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6562 }
6563
6564 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6565 {
6566 for(int i = 5; i >= 0; --i) {
6567 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6568 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6569 LLVMConstInt(ctx->ac.i32, 16, false), false);
6570 }
6571
6572 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6573 LLVMConstInt(ctx->ac.i32, 16, false),
6574 LLVMConstInt(ctx->ac.i32, 8, false), false);
6575 }
6576
6577 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6578 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6579 {
6580 struct ac_nir_context ctx = {};
6581 struct nir_function *func;
6582
6583 ctx.ac = *ac;
6584 ctx.abi = abi;
6585
6586 ctx.nctx = nctx;
6587 if (nctx)
6588 nctx->nir = &ctx;
6589
6590 ctx.stage = nir->info.stage;
6591
6592 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6593
6594 nir_foreach_variable(variable, &nir->outputs)
6595 handle_shader_output_decl(&ctx, nir, variable);
6596
6597 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6598 _mesa_key_pointer_equal);
6599 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6600 _mesa_key_pointer_equal);
6601 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6602 _mesa_key_pointer_equal);
6603
6604 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6605
6606 setup_locals(&ctx, func);
6607
6608 if (nir->info.stage == MESA_SHADER_COMPUTE)
6609 setup_shared(&ctx, nir);
6610
6611 visit_cf_list(&ctx, &func->impl->body);
6612 phi_post_pass(&ctx);
6613
6614 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6615 ctx.outputs);
6616
6617 free(ctx.locals);
6618 ralloc_free(ctx.defs);
6619 ralloc_free(ctx.phis);
6620 ralloc_free(ctx.vars);
6621
6622 if (nctx)
6623 nctx->nir = NULL;
6624 }
6625
6626 static
6627 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6628 struct nir_shader *const *shaders,
6629 int shader_count,
6630 struct ac_shader_variant_info *shader_info,
6631 const struct ac_nir_compiler_options *options)
6632 {
6633 struct nir_to_llvm_context ctx = {0};
6634 unsigned i;
6635 ctx.options = options;
6636 ctx.shader_info = shader_info;
6637 ctx.context = LLVMContextCreate();
6638 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6639
6640 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6641 options->family);
6642 ctx.ac.module = ctx.module;
6643 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6644
6645 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6646 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6647 LLVMSetDataLayout(ctx.module, data_layout_str);
6648 LLVMDisposeTargetData(data_layout);
6649 LLVMDisposeMessage(data_layout_str);
6650
6651 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6652 ctx.ac.builder = ctx.builder;
6653
6654 memset(shader_info, 0, sizeof(*shader_info));
6655
6656 for(int i = 0; i < shader_count; ++i)
6657 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6658
6659 for (i = 0; i < AC_UD_MAX_SETS; i++)
6660 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6661 for (i = 0; i < AC_UD_MAX_UD; i++)
6662 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6663
6664 ctx.max_workgroup_size = 0;
6665 for (int i = 0; i < shader_count; ++i) {
6666 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6667 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6668 shaders[i]));
6669 }
6670
6671 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6672 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6673
6674 ctx.abi.inputs = &ctx.inputs[0];
6675 ctx.abi.emit_outputs = handle_shader_outputs_post;
6676 ctx.abi.emit_vertex = visit_emit_vertex;
6677 ctx.abi.load_ubo = radv_load_ubo;
6678 ctx.abi.load_ssbo = radv_load_ssbo;
6679 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6680 ctx.abi.clamp_shadow_reference = false;
6681
6682 if (shader_count >= 2)
6683 ac_init_exec_full_mask(&ctx.ac);
6684
6685 if (ctx.ac.chip_class == GFX9 &&
6686 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6687 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6688
6689 for(int i = 0; i < shader_count; ++i) {
6690 ctx.stage = shaders[i]->info.stage;
6691 ctx.output_mask = 0;
6692 ctx.tess_outputs_written = 0;
6693 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6694 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6695
6696 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6697 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6698 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6699 ctx.abi.load_inputs = load_gs_input;
6700 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6701 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6702 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6703 ctx.abi.load_tess_inputs = load_tcs_input;
6704 ctx.abi.store_tcs_outputs = store_tcs_output;
6705 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6706 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6707 ctx.abi.load_tess_inputs = load_tes_input;
6708 ctx.abi.load_tess_coord = load_tess_coord;
6709 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6710 if (shader_info->info.vs.needs_instance_id) {
6711 if (ctx.ac.chip_class == GFX9 &&
6712 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL) {
6713 ctx.shader_info->vs.vgpr_comp_cnt =
6714 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6715 } else {
6716 ctx.shader_info->vs.vgpr_comp_cnt =
6717 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6718 }
6719 }
6720 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6721 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6722 }
6723
6724 if (i)
6725 emit_barrier(&ctx);
6726
6727 ac_setup_rings(&ctx);
6728
6729 LLVMBasicBlockRef merge_block;
6730 if (shader_count >= 2) {
6731 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6732 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6733 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6734
6735 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6736 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6737 LLVMConstInt(ctx.ac.i32, 8, false), false);
6738 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6739 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6740 thread_id, count, "");
6741 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6742
6743 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6744 }
6745
6746 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6747 handle_fs_inputs(&ctx, shaders[i]);
6748 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6749 handle_vs_inputs(&ctx, shaders[i]);
6750 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6751 prepare_gs_input_vgprs(&ctx);
6752
6753 nir_foreach_variable(variable, &shaders[i]->outputs)
6754 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6755
6756 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6757
6758 if (shader_count >= 2) {
6759 LLVMBuildBr(ctx.ac.builder, merge_block);
6760 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6761 }
6762
6763 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6764 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6765 shaders[i]->info.cull_distance_array_size > 4;
6766 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6767 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6768 shaders[i]->info.gs.vertices_out;
6769 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6770 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6771 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6772 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6773 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6774 }
6775 }
6776
6777 LLVMBuildRetVoid(ctx.builder);
6778
6779 ac_llvm_finalize_module(&ctx);
6780
6781 if (shader_count == 1)
6782 ac_nir_eliminate_const_vs_outputs(&ctx);
6783
6784 return ctx.module;
6785 }
6786
6787 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6788 {
6789 unsigned *retval = (unsigned *)context;
6790 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6791 char *description = LLVMGetDiagInfoDescription(di);
6792
6793 if (severity == LLVMDSError) {
6794 *retval = 1;
6795 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6796 description);
6797 }
6798
6799 LLVMDisposeMessage(description);
6800 }
6801
6802 static unsigned ac_llvm_compile(LLVMModuleRef M,
6803 struct ac_shader_binary *binary,
6804 LLVMTargetMachineRef tm)
6805 {
6806 unsigned retval = 0;
6807 char *err;
6808 LLVMContextRef llvm_ctx;
6809 LLVMMemoryBufferRef out_buffer;
6810 unsigned buffer_size;
6811 const char *buffer_data;
6812 LLVMBool mem_err;
6813
6814 /* Setup Diagnostic Handler*/
6815 llvm_ctx = LLVMGetModuleContext(M);
6816
6817 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6818 &retval);
6819
6820 /* Compile IR*/
6821 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6822 &err, &out_buffer);
6823
6824 /* Process Errors/Warnings */
6825 if (mem_err) {
6826 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6827 free(err);
6828 retval = 1;
6829 goto out;
6830 }
6831
6832 /* Extract Shader Code*/
6833 buffer_size = LLVMGetBufferSize(out_buffer);
6834 buffer_data = LLVMGetBufferStart(out_buffer);
6835
6836 ac_elf_read(buffer_data, buffer_size, binary);
6837
6838 /* Clean up */
6839 LLVMDisposeMemoryBuffer(out_buffer);
6840
6841 out:
6842 return retval;
6843 }
6844
6845 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6846 LLVMModuleRef llvm_module,
6847 struct ac_shader_binary *binary,
6848 struct ac_shader_config *config,
6849 struct ac_shader_variant_info *shader_info,
6850 gl_shader_stage stage,
6851 bool dump_shader, bool supports_spill)
6852 {
6853 if (dump_shader)
6854 ac_dump_module(llvm_module);
6855
6856 memset(binary, 0, sizeof(*binary));
6857 int v = ac_llvm_compile(llvm_module, binary, tm);
6858 if (v) {
6859 fprintf(stderr, "compile failed\n");
6860 }
6861
6862 if (dump_shader)
6863 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6864
6865 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6866
6867 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6868 LLVMDisposeModule(llvm_module);
6869 LLVMContextDispose(ctx);
6870
6871 if (stage == MESA_SHADER_FRAGMENT) {
6872 shader_info->num_input_vgprs = 0;
6873 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6874 shader_info->num_input_vgprs += 2;
6875 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6876 shader_info->num_input_vgprs += 2;
6877 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6878 shader_info->num_input_vgprs += 2;
6879 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6880 shader_info->num_input_vgprs += 3;
6881 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6882 shader_info->num_input_vgprs += 2;
6883 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6884 shader_info->num_input_vgprs += 2;
6885 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6886 shader_info->num_input_vgprs += 2;
6887 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6888 shader_info->num_input_vgprs += 1;
6889 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6890 shader_info->num_input_vgprs += 1;
6891 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6892 shader_info->num_input_vgprs += 1;
6893 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6894 shader_info->num_input_vgprs += 1;
6895 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6896 shader_info->num_input_vgprs += 1;
6897 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6898 shader_info->num_input_vgprs += 1;
6899 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6900 shader_info->num_input_vgprs += 1;
6901 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6902 shader_info->num_input_vgprs += 1;
6903 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6904 shader_info->num_input_vgprs += 1;
6905 }
6906 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6907
6908 /* +3 for scratch wave offset and VCC */
6909 config->num_sgprs = MAX2(config->num_sgprs,
6910 shader_info->num_input_sgprs + 3);
6911
6912 /* Enable 64-bit and 16-bit denormals, because there is no performance
6913 * cost.
6914 *
6915 * If denormals are enabled, all floating-point output modifiers are
6916 * ignored.
6917 *
6918 * Don't enable denormals for 32-bit floats, because:
6919 * - Floating-point output modifiers would be ignored by the hw.
6920 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6921 * have to stop using those.
6922 * - SI & CI would be very slow.
6923 */
6924 config->float_mode |= V_00B028_FP_64_DENORMS;
6925 }
6926
6927 static void
6928 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6929 {
6930 switch (nir->info.stage) {
6931 case MESA_SHADER_COMPUTE:
6932 for (int i = 0; i < 3; ++i)
6933 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6934 break;
6935 case MESA_SHADER_FRAGMENT:
6936 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6937 break;
6938 case MESA_SHADER_GEOMETRY:
6939 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6940 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6941 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6942 shader_info->gs.invocations = nir->info.gs.invocations;
6943 break;
6944 case MESA_SHADER_TESS_EVAL:
6945 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6946 shader_info->tes.spacing = nir->info.tess.spacing;
6947 shader_info->tes.ccw = nir->info.tess.ccw;
6948 shader_info->tes.point_mode = nir->info.tess.point_mode;
6949 shader_info->tes.as_es = options->key.tes.as_es;
6950 break;
6951 case MESA_SHADER_TESS_CTRL:
6952 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6953 break;
6954 case MESA_SHADER_VERTEX:
6955 shader_info->vs.as_es = options->key.vs.as_es;
6956 shader_info->vs.as_ls = options->key.vs.as_ls;
6957 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
6958 if (options->key.vs.as_ls)
6959 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6960 break;
6961 default:
6962 break;
6963 }
6964 }
6965
6966 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6967 struct ac_shader_binary *binary,
6968 struct ac_shader_config *config,
6969 struct ac_shader_variant_info *shader_info,
6970 struct nir_shader *const *nir,
6971 int nir_count,
6972 const struct ac_nir_compiler_options *options,
6973 bool dump_shader)
6974 {
6975
6976 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6977 options);
6978
6979 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6980 for (int i = 0; i < nir_count; ++i)
6981 ac_fill_shader_info(shader_info, nir[i], options);
6982 }
6983
6984 static void
6985 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6986 {
6987 LLVMValueRef args[9];
6988 args[0] = ctx->gsvs_ring;
6989 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6990 args[3] = ctx->ac.i32_0;
6991 args[4] = ctx->ac.i32_1; /* OFFEN */
6992 args[5] = ctx->ac.i32_0; /* IDXEN */
6993 args[6] = ctx->ac.i32_1; /* GLC */
6994 args[7] = ctx->ac.i32_1; /* SLC */
6995 args[8] = ctx->ac.i32_0; /* TFE */
6996
6997 int idx = 0;
6998
6999 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7000 int length = 4;
7001 int slot = idx;
7002 int slot_inc = 1;
7003 if (!(ctx->output_mask & (1ull << i)))
7004 continue;
7005
7006 if (i == VARYING_SLOT_CLIP_DIST0) {
7007 /* unpack clip and cull from a single set of slots */
7008 length = ctx->num_output_clips + ctx->num_output_culls;
7009 if (length > 4)
7010 slot_inc = 2;
7011 }
7012
7013 for (unsigned j = 0; j < length; j++) {
7014 LLVMValueRef value;
7015 args[2] = LLVMConstInt(ctx->ac.i32,
7016 (slot * 4 + j) *
7017 ctx->gs_max_out_vertices * 16 * 4, false);
7018
7019 value = ac_build_intrinsic(&ctx->ac,
7020 "llvm.SI.buffer.load.dword.i32.i32",
7021 ctx->ac.i32, args, 9,
7022 AC_FUNC_ATTR_READONLY |
7023 AC_FUNC_ATTR_LEGACY);
7024
7025 LLVMBuildStore(ctx->builder,
7026 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7027 }
7028 idx += slot_inc;
7029 }
7030 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7031 }
7032
7033 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7034 struct nir_shader *geom_shader,
7035 struct ac_shader_binary *binary,
7036 struct ac_shader_config *config,
7037 struct ac_shader_variant_info *shader_info,
7038 const struct ac_nir_compiler_options *options,
7039 bool dump_shader)
7040 {
7041 struct nir_to_llvm_context ctx = {0};
7042 ctx.context = LLVMContextCreate();
7043 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7044 ctx.options = options;
7045 ctx.shader_info = shader_info;
7046
7047 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7048 options->family);
7049 ctx.ac.module = ctx.module;
7050
7051 ctx.is_gs_copy_shader = true;
7052 LLVMSetTarget(ctx.module, "amdgcn--");
7053
7054 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
7055 ctx.ac.builder = ctx.builder;
7056 ctx.stage = MESA_SHADER_VERTEX;
7057
7058 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7059
7060 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7061 ac_setup_rings(&ctx);
7062
7063 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7064 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7065
7066 struct ac_nir_context nir_ctx = {};
7067 nir_ctx.ac = ctx.ac;
7068 nir_ctx.abi = &ctx.abi;
7069
7070 nir_ctx.nctx = &ctx;
7071 ctx.nir = &nir_ctx;
7072
7073 nir_foreach_variable(variable, &geom_shader->outputs) {
7074 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7075 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7076 }
7077
7078 ac_gs_copy_shader_emit(&ctx);
7079
7080 ctx.nir = NULL;
7081
7082 LLVMBuildRetVoid(ctx.builder);
7083
7084 ac_llvm_finalize_module(&ctx);
7085
7086 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7087 MESA_SHADER_VERTEX,
7088 dump_shader, options->supports_spill);
7089 }