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ac/radeonsi: add load_tess_coord() to the abi
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tes_rel_patch_id;
115 LLVMValueRef tes_u;
116 LLVMValueRef tes_v;
117
118 LLVMValueRef gsvs_ring_stride;
119 LLVMValueRef gsvs_num_entries;
120 LLVMValueRef gs2vs_offset;
121 LLVMValueRef gs_wave_id;
122 LLVMValueRef gs_vtx_offset[6];
123
124 LLVMValueRef esgs_ring;
125 LLVMValueRef gsvs_ring;
126 LLVMValueRef hs_ring_tess_offchip;
127 LLVMValueRef hs_ring_tess_factor;
128
129 LLVMValueRef prim_mask;
130 LLVMValueRef sample_pos_offset;
131 LLVMValueRef persp_sample, persp_center, persp_centroid;
132 LLVMValueRef linear_sample, linear_center, linear_centroid;
133
134 gl_shader_stage stage;
135
136 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
137
138 uint64_t input_mask;
139 uint64_t output_mask;
140 uint8_t num_output_clips;
141 uint8_t num_output_culls;
142
143 bool is_gs_copy_shader;
144 LLVMValueRef gs_next_vertex;
145 unsigned gs_max_out_vertices;
146
147 unsigned tes_primitive_mode;
148 uint64_t tess_outputs_written;
149 uint64_t tess_patch_outputs_written;
150
151 uint32_t tcs_patch_outputs_read;
152 uint64_t tcs_outputs_read;
153 };
154
155 static inline struct nir_to_llvm_context *
156 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
157 {
158 struct nir_to_llvm_context *ctx = NULL;
159 return container_of(abi, ctx, abi);
160 }
161
162 static LLVMTypeRef
163 nir2llvmtype(struct ac_nir_context *ctx,
164 const struct glsl_type *type)
165 {
166 switch (glsl_get_base_type(glsl_without_array(type))) {
167 case GLSL_TYPE_UINT:
168 case GLSL_TYPE_INT:
169 return ctx->ac.i32;
170 case GLSL_TYPE_UINT64:
171 case GLSL_TYPE_INT64:
172 return ctx->ac.i64;
173 case GLSL_TYPE_DOUBLE:
174 return ctx->ac.f64;
175 case GLSL_TYPE_FLOAT:
176 return ctx->ac.f32;
177 default:
178 assert(!"Unsupported type in nir2llvmtype()");
179 break;
180 }
181 return 0;
182 }
183
184 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
185 const nir_deref_var *deref,
186 enum ac_descriptor_type desc_type,
187 const nir_tex_instr *instr,
188 bool image, bool write);
189
190 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
191 {
192 return (index * 4) + chan;
193 }
194
195 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
196 {
197 /* handle patch indices separate */
198 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
199 return 0;
200 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
201 return 1;
202 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
203 return 2 + (slot - VARYING_SLOT_PATCH0);
204
205 if (slot == VARYING_SLOT_POS)
206 return 0;
207 if (slot == VARYING_SLOT_PSIZ)
208 return 1;
209 if (slot == VARYING_SLOT_CLIP_DIST0)
210 return 2;
211 /* 3 is reserved for clip dist as well */
212 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
213 return 4 + (slot - VARYING_SLOT_VAR0);
214 unreachable("illegal slot in get unique index\n");
215 }
216
217 static void set_llvm_calling_convention(LLVMValueRef func,
218 gl_shader_stage stage)
219 {
220 enum radeon_llvm_calling_convention calling_conv;
221
222 switch (stage) {
223 case MESA_SHADER_VERTEX:
224 case MESA_SHADER_TESS_EVAL:
225 calling_conv = RADEON_LLVM_AMDGPU_VS;
226 break;
227 case MESA_SHADER_GEOMETRY:
228 calling_conv = RADEON_LLVM_AMDGPU_GS;
229 break;
230 case MESA_SHADER_TESS_CTRL:
231 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
232 break;
233 case MESA_SHADER_FRAGMENT:
234 calling_conv = RADEON_LLVM_AMDGPU_PS;
235 break;
236 case MESA_SHADER_COMPUTE:
237 calling_conv = RADEON_LLVM_AMDGPU_CS;
238 break;
239 default:
240 unreachable("Unhandle shader type");
241 }
242
243 LLVMSetFunctionCallConv(func, calling_conv);
244 }
245
246 #define MAX_ARGS 23
247 struct arg_info {
248 LLVMTypeRef types[MAX_ARGS];
249 LLVMValueRef *assign[MAX_ARGS];
250 unsigned array_params_mask;
251 uint8_t count;
252 uint8_t sgpr_count;
253 uint8_t num_sgprs_used;
254 uint8_t num_vgprs_used;
255 };
256
257 enum ac_arg_regfile {
258 ARG_SGPR,
259 ARG_VGPR,
260 };
261
262 static void
263 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
264 LLVMValueRef *param_ptr)
265 {
266 assert(info->count < MAX_ARGS);
267
268 info->assign[info->count] = param_ptr;
269 info->types[info->count] = type;
270 info->count++;
271
272 if (regfile == ARG_SGPR) {
273 info->num_sgprs_used += ac_get_type_size(type) / 4;
274 info->sgpr_count++;
275 } else {
276 assert(regfile == ARG_VGPR);
277 info->num_vgprs_used += ac_get_type_size(type) / 4;
278 }
279 }
280
281 static inline void
282 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
283 {
284 info->array_params_mask |= (1 << info->count);
285 add_arg(info, ARG_SGPR, type, param_ptr);
286 }
287
288 static void assign_arguments(LLVMValueRef main_function,
289 struct arg_info *info)
290 {
291 unsigned i;
292 for (i = 0; i < info->count; i++) {
293 if (info->assign[i])
294 *info->assign[i] = LLVMGetParam(main_function, i);
295 }
296 }
297
298 static LLVMValueRef
299 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
300 LLVMBuilderRef builder, LLVMTypeRef *return_types,
301 unsigned num_return_elems,
302 struct arg_info *args,
303 unsigned max_workgroup_size,
304 bool unsafe_math)
305 {
306 LLVMTypeRef main_function_type, ret_type;
307 LLVMBasicBlockRef main_function_body;
308
309 if (num_return_elems)
310 ret_type = LLVMStructTypeInContext(ctx, return_types,
311 num_return_elems, true);
312 else
313 ret_type = LLVMVoidTypeInContext(ctx);
314
315 /* Setup the function */
316 main_function_type =
317 LLVMFunctionType(ret_type, args->types, args->count, 0);
318 LLVMValueRef main_function =
319 LLVMAddFunction(module, "main", main_function_type);
320 main_function_body =
321 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
322 LLVMPositionBuilderAtEnd(builder, main_function_body);
323
324 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
325 for (unsigned i = 0; i < args->sgpr_count; ++i) {
326 if (args->array_params_mask & (1 << i)) {
327 LLVMValueRef P = LLVMGetParam(main_function, i);
328 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
329 ac_add_attr_dereferenceable(P, UINT64_MAX);
330 }
331 else {
332 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
333 }
334 }
335
336 if (max_workgroup_size) {
337 ac_llvm_add_target_dep_function_attr(main_function,
338 "amdgpu-max-work-group-size",
339 max_workgroup_size);
340 }
341 if (unsafe_math) {
342 /* These were copied from some LLVM test. */
343 LLVMAddTargetDependentFunctionAttr(main_function,
344 "less-precise-fpmad",
345 "true");
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "no-infs-fp-math",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-nans-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "unsafe-fp-math",
354 "true");
355 }
356 return main_function;
357 }
358
359 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
360 {
361 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
362 CONST_ADDR_SPACE);
363 }
364
365 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
366 {
367 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
368 type = LLVMGetElementType(type);
369
370 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
371 return LLVMGetIntTypeWidth(type);
372
373 if (type == ctx->f16)
374 return 16;
375 if (type == ctx->f32)
376 return 32;
377 if (type == ctx->f64)
378 return 64;
379
380 unreachable("Unhandled type kind in get_elem_bits");
381 }
382
383 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
384 LLVMValueRef param, unsigned rshift,
385 unsigned bitwidth)
386 {
387 LLVMValueRef value = param;
388 if (rshift)
389 value = LLVMBuildLShr(ctx->builder, value,
390 LLVMConstInt(ctx->i32, rshift, false), "");
391
392 if (rshift + bitwidth < 32) {
393 unsigned mask = (1 << bitwidth) - 1;
394 value = LLVMBuildAnd(ctx->builder, value,
395 LLVMConstInt(ctx->i32, mask, false), "");
396 }
397 return value;
398 }
399
400 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
401 {
402 switch (ctx->stage) {
403 case MESA_SHADER_TESS_CTRL:
404 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
405 case MESA_SHADER_TESS_EVAL:
406 return ctx->tes_rel_patch_id;
407 break;
408 default:
409 unreachable("Illegal stage");
410 }
411 }
412
413 /* Tessellation shaders pass outputs to the next shader using LDS.
414 *
415 * LS outputs = TCS inputs
416 * TCS outputs = TES inputs
417 *
418 * The LDS layout is:
419 * - TCS inputs for patch 0
420 * - TCS inputs for patch 1
421 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
422 * - ...
423 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
424 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
425 * - TCS outputs for patch 1
426 * - Per-patch TCS outputs for patch 1
427 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
428 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
429 * - ...
430 *
431 * All three shaders VS(LS), TCS, TES share the same LDS space.
432 */
433 static LLVMValueRef
434 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
435 {
436 if (ctx->stage == MESA_SHADER_VERTEX)
437 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
438 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
439 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
440 else {
441 assert(0);
442 return NULL;
443 }
444 }
445
446 static LLVMValueRef
447 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
448 {
449 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
450 }
451
452 static LLVMValueRef
453 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
454 {
455 return LLVMBuildMul(ctx->builder,
456 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
457 LLVMConstInt(ctx->ac.i32, 4, false), "");
458 }
459
460 static LLVMValueRef
461 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
462 {
463 return LLVMBuildMul(ctx->builder,
464 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
465 LLVMConstInt(ctx->ac.i32, 4, false), "");
466 }
467
468 static LLVMValueRef
469 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
470 {
471 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
472 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
473
474 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
475 }
476
477 static LLVMValueRef
478 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
479 {
480 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
481 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
482 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
483
484 return LLVMBuildAdd(ctx->builder, patch0_offset,
485 LLVMBuildMul(ctx->builder, patch_stride,
486 rel_patch_id, ""),
487 "");
488 }
489
490 static LLVMValueRef
491 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch0_patch_data_offset =
494 get_tcs_out_patch0_patch_data_offset(ctx);
495 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
496 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
497
498 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
499 LLVMBuildMul(ctx->builder, patch_stride,
500 rel_patch_id, ""),
501 "");
502 }
503
504 static void
505 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
506 uint32_t indirect_offset)
507 {
508 ud_info->sgpr_idx = *sgpr_idx;
509 ud_info->num_sgprs = num_sgprs;
510 ud_info->indirect = indirect_offset > 0;
511 ud_info->indirect_offset = indirect_offset;
512 *sgpr_idx += num_sgprs;
513 }
514
515 static void
516 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
517 uint8_t num_sgprs)
518 {
519 struct ac_userdata_info *ud_info =
520 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
521 assert(ud_info);
522
523 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
524 }
525
526 static void
527 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
528 uint32_t indirect_offset)
529 {
530 struct ac_userdata_info *ud_info =
531 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
532 assert(ud_info);
533
534 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
535 }
536
537 struct user_sgpr_info {
538 bool need_ring_offsets;
539 uint8_t sgpr_count;
540 bool indirect_all_descriptor_sets;
541 };
542
543 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
544 struct user_sgpr_info *user_sgpr_info)
545 {
546 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
547
548 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
549 if (ctx->stage == MESA_SHADER_GEOMETRY ||
550 ctx->stage == MESA_SHADER_VERTEX ||
551 ctx->stage == MESA_SHADER_TESS_CTRL ||
552 ctx->stage == MESA_SHADER_TESS_EVAL ||
553 ctx->is_gs_copy_shader)
554 user_sgpr_info->need_ring_offsets = true;
555
556 if (ctx->stage == MESA_SHADER_FRAGMENT &&
557 ctx->shader_info->info.ps.needs_sample_positions)
558 user_sgpr_info->need_ring_offsets = true;
559
560 /* 2 user sgprs will nearly always be allocated for scratch/rings */
561 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
562 user_sgpr_info->sgpr_count += 2;
563 }
564
565 switch (ctx->stage) {
566 case MESA_SHADER_COMPUTE:
567 if (ctx->shader_info->info.cs.uses_grid_size)
568 user_sgpr_info->sgpr_count += 3;
569 break;
570 case MESA_SHADER_FRAGMENT:
571 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
572 break;
573 case MESA_SHADER_VERTEX:
574 if (!ctx->is_gs_copy_shader) {
575 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
576 if (ctx->shader_info->info.vs.needs_draw_id) {
577 user_sgpr_info->sgpr_count += 3;
578 } else {
579 user_sgpr_info->sgpr_count += 2;
580 }
581 }
582 if (ctx->options->key.vs.as_ls)
583 user_sgpr_info->sgpr_count++;
584 break;
585 case MESA_SHADER_TESS_CTRL:
586 user_sgpr_info->sgpr_count += 4;
587 break;
588 case MESA_SHADER_TESS_EVAL:
589 user_sgpr_info->sgpr_count += 1;
590 break;
591 case MESA_SHADER_GEOMETRY:
592 user_sgpr_info->sgpr_count += 2;
593 break;
594 default:
595 break;
596 }
597
598 if (ctx->shader_info->info.needs_push_constants)
599 user_sgpr_info->sgpr_count += 2;
600
601 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
602 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
603 user_sgpr_info->sgpr_count += 2;
604 user_sgpr_info->indirect_all_descriptor_sets = true;
605 } else {
606 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
607 }
608 }
609
610 static void
611 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
612 gl_shader_stage stage,
613 bool has_previous_stage,
614 gl_shader_stage previous_stage,
615 const struct user_sgpr_info *user_sgpr_info,
616 struct arg_info *args,
617 LLVMValueRef *desc_sets)
618 {
619 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
620 unsigned num_sets = ctx->options->layout ?
621 ctx->options->layout->num_sets : 0;
622 unsigned stage_mask = 1 << stage;
623
624 if (has_previous_stage)
625 stage_mask |= 1 << previous_stage;
626
627 /* 1 for each descriptor set */
628 if (!user_sgpr_info->indirect_all_descriptor_sets) {
629 for (unsigned i = 0; i < num_sets; ++i) {
630 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
631 add_array_arg(args, type,
632 &ctx->descriptor_sets[i]);
633 }
634 }
635 } else {
636 add_array_arg(args, const_array(type, 32), desc_sets);
637 }
638
639 if (ctx->shader_info->info.needs_push_constants) {
640 /* 1 for push constants and dynamic descriptors */
641 add_array_arg(args, type, &ctx->push_constants);
642 }
643 }
644
645 static void
646 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
647 gl_shader_stage stage,
648 bool has_previous_stage,
649 gl_shader_stage previous_stage,
650 struct arg_info *args)
651 {
652 if (!ctx->is_gs_copy_shader &&
653 (stage == MESA_SHADER_VERTEX ||
654 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
655 if (ctx->shader_info->info.vs.has_vertex_buffers) {
656 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
657 &ctx->vertex_buffers);
658 }
659 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
660 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
661 if (ctx->shader_info->info.vs.needs_draw_id) {
662 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
663 }
664 }
665 }
666
667 static void
668 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
669 {
670 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
671 if (!ctx->is_gs_copy_shader) {
672 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
673 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
674 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
675 }
676 }
677
678 static void
679 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
680 {
681 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
682 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
683 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
684 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
685 }
686
687 static void
688 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
689 bool has_previous_stage, gl_shader_stage previous_stage,
690 const struct user_sgpr_info *user_sgpr_info,
691 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
692 {
693 unsigned num_sets = ctx->options->layout ?
694 ctx->options->layout->num_sets : 0;
695 unsigned stage_mask = 1 << stage;
696
697 if (has_previous_stage)
698 stage_mask |= 1 << previous_stage;
699
700 if (!user_sgpr_info->indirect_all_descriptor_sets) {
701 for (unsigned i = 0; i < num_sets; ++i) {
702 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
703 set_loc_desc(ctx, i, user_sgpr_idx, 0);
704 } else
705 ctx->descriptor_sets[i] = NULL;
706 }
707 } else {
708 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
709 user_sgpr_idx, 2);
710
711 for (unsigned i = 0; i < num_sets; ++i) {
712 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
713 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
714 ctx->descriptor_sets[i] =
715 ac_build_load_to_sgpr(&ctx->ac,
716 desc_sets,
717 LLVMConstInt(ctx->ac.i32, i, false));
718
719 } else
720 ctx->descriptor_sets[i] = NULL;
721 }
722 ctx->shader_info->need_indirect_descriptor_sets = true;
723 }
724
725 if (ctx->shader_info->info.needs_push_constants) {
726 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
727 }
728 }
729
730 static void
731 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
732 gl_shader_stage stage, bool has_previous_stage,
733 gl_shader_stage previous_stage,
734 uint8_t *user_sgpr_idx)
735 {
736 if (!ctx->is_gs_copy_shader &&
737 (stage == MESA_SHADER_VERTEX ||
738 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
739 if (ctx->shader_info->info.vs.has_vertex_buffers) {
740 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
741 user_sgpr_idx, 2);
742 }
743
744 unsigned vs_num = 2;
745 if (ctx->shader_info->info.vs.needs_draw_id)
746 vs_num++;
747
748 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
749 user_sgpr_idx, vs_num);
750 }
751 }
752
753 static void create_function(struct nir_to_llvm_context *ctx,
754 gl_shader_stage stage,
755 bool has_previous_stage,
756 gl_shader_stage previous_stage)
757 {
758 uint8_t user_sgpr_idx;
759 struct user_sgpr_info user_sgpr_info;
760 struct arg_info args = {};
761 LLVMValueRef desc_sets;
762
763 allocate_user_sgprs(ctx, &user_sgpr_info);
764
765 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
766 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
767 &ctx->ring_offsets);
768 }
769
770 switch (stage) {
771 case MESA_SHADER_COMPUTE:
772 declare_global_input_sgprs(ctx, stage, has_previous_stage,
773 previous_stage, &user_sgpr_info,
774 &args, &desc_sets);
775
776 if (ctx->shader_info->info.cs.uses_grid_size) {
777 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
778 &ctx->num_work_groups);
779 }
780
781 for (int i = 0; i < 3; i++) {
782 ctx->workgroup_ids[i] = NULL;
783 if (ctx->shader_info->info.cs.uses_block_id[i]) {
784 add_arg(&args, ARG_SGPR, ctx->ac.i32,
785 &ctx->workgroup_ids[i]);
786 }
787 }
788
789 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
790 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
791 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
792 &ctx->local_invocation_ids);
793 break;
794 case MESA_SHADER_VERTEX:
795 declare_global_input_sgprs(ctx, stage, has_previous_stage,
796 previous_stage, &user_sgpr_info,
797 &args, &desc_sets);
798 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
799 previous_stage, &args);
800
801 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
802 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
803 if (ctx->options->key.vs.as_es)
804 add_arg(&args, ARG_SGPR, ctx->ac.i32,
805 &ctx->es2gs_offset);
806 else if (ctx->options->key.vs.as_ls)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32,
808 &ctx->ls_out_layout);
809
810 declare_vs_input_vgprs(ctx, &args);
811 break;
812 case MESA_SHADER_TESS_CTRL:
813 if (has_previous_stage) {
814 // First 6 system regs
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->merged_wave_info);
818 add_arg(&args, ARG_SGPR, ctx->ac.i32,
819 &ctx->tess_factor_offset);
820
821 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
822 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
823 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
824
825 declare_global_input_sgprs(ctx, stage,
826 has_previous_stage,
827 previous_stage,
828 &user_sgpr_info, &args,
829 &desc_sets);
830 declare_vs_specific_input_sgprs(ctx, stage,
831 has_previous_stage,
832 previous_stage, &args);
833
834 add_arg(&args, ARG_SGPR, ctx->ac.i32,
835 &ctx->ls_out_layout);
836
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->tcs_offchip_layout);
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->tcs_out_offsets);
841 add_arg(&args, ARG_SGPR, ctx->ac.i32,
842 &ctx->tcs_out_layout);
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->tcs_in_layout);
845 if (ctx->shader_info->info.needs_multiview_view_index)
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->view_index);
848
849 add_arg(&args, ARG_VGPR, ctx->ac.i32,
850 &ctx->abi.tcs_patch_id);
851 add_arg(&args, ARG_VGPR, ctx->ac.i32,
852 &ctx->abi.tcs_rel_ids);
853
854 declare_vs_input_vgprs(ctx, &args);
855 } else {
856 declare_global_input_sgprs(ctx, stage,
857 has_previous_stage,
858 previous_stage,
859 &user_sgpr_info, &args,
860 &desc_sets);
861
862 add_arg(&args, ARG_SGPR, ctx->ac.i32,
863 &ctx->tcs_offchip_layout);
864 add_arg(&args, ARG_SGPR, ctx->ac.i32,
865 &ctx->tcs_out_offsets);
866 add_arg(&args, ARG_SGPR, ctx->ac.i32,
867 &ctx->tcs_out_layout);
868 add_arg(&args, ARG_SGPR, ctx->ac.i32,
869 &ctx->tcs_in_layout);
870 if (ctx->shader_info->info.needs_multiview_view_index)
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->view_index);
873
874 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tess_factor_offset);
877 add_arg(&args, ARG_VGPR, ctx->ac.i32,
878 &ctx->abi.tcs_patch_id);
879 add_arg(&args, ARG_VGPR, ctx->ac.i32,
880 &ctx->abi.tcs_rel_ids);
881 }
882 break;
883 case MESA_SHADER_TESS_EVAL:
884 declare_global_input_sgprs(ctx, stage, has_previous_stage,
885 previous_stage, &user_sgpr_info,
886 &args, &desc_sets);
887
888 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
889 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
890 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
891
892 if (ctx->options->key.tes.as_es) {
893 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
895 add_arg(&args, ARG_SGPR, ctx->ac.i32,
896 &ctx->es2gs_offset);
897 } else {
898 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
900 }
901 declare_tes_input_vgprs(ctx, &args);
902 break;
903 case MESA_SHADER_GEOMETRY:
904 if (has_previous_stage) {
905 // First 6 system regs
906 add_arg(&args, ARG_SGPR, ctx->ac.i32,
907 &ctx->gs2vs_offset);
908 add_arg(&args, ARG_SGPR, ctx->ac.i32,
909 &ctx->merged_wave_info);
910 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
911
912 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
915
916 declare_global_input_sgprs(ctx, stage,
917 has_previous_stage,
918 previous_stage,
919 &user_sgpr_info, &args,
920 &desc_sets);
921
922 if (previous_stage == MESA_SHADER_TESS_EVAL) {
923 add_arg(&args, ARG_SGPR, ctx->ac.i32,
924 &ctx->tcs_offchip_layout);
925 } else {
926 declare_vs_specific_input_sgprs(ctx, stage,
927 has_previous_stage,
928 previous_stage,
929 &args);
930 }
931
932 add_arg(&args, ARG_SGPR, ctx->ac.i32,
933 &ctx->gsvs_ring_stride);
934 add_arg(&args, ARG_SGPR, ctx->ac.i32,
935 &ctx->gsvs_num_entries);
936 if (ctx->shader_info->info.needs_multiview_view_index)
937 add_arg(&args, ARG_SGPR, ctx->ac.i32,
938 &ctx->view_index);
939
940 add_arg(&args, ARG_VGPR, ctx->ac.i32,
941 &ctx->gs_vtx_offset[0]);
942 add_arg(&args, ARG_VGPR, ctx->ac.i32,
943 &ctx->gs_vtx_offset[2]);
944 add_arg(&args, ARG_VGPR, ctx->ac.i32,
945 &ctx->abi.gs_prim_id);
946 add_arg(&args, ARG_VGPR, ctx->ac.i32,
947 &ctx->abi.gs_invocation_id);
948 add_arg(&args, ARG_VGPR, ctx->ac.i32,
949 &ctx->gs_vtx_offset[4]);
950
951 if (previous_stage == MESA_SHADER_VERTEX) {
952 declare_vs_input_vgprs(ctx, &args);
953 } else {
954 declare_tes_input_vgprs(ctx, &args);
955 }
956 } else {
957 declare_global_input_sgprs(ctx, stage,
958 has_previous_stage,
959 previous_stage,
960 &user_sgpr_info, &args,
961 &desc_sets);
962
963 add_arg(&args, ARG_SGPR, ctx->ac.i32,
964 &ctx->gsvs_ring_stride);
965 add_arg(&args, ARG_SGPR, ctx->ac.i32,
966 &ctx->gsvs_num_entries);
967 if (ctx->shader_info->info.needs_multiview_view_index)
968 add_arg(&args, ARG_SGPR, ctx->ac.i32,
969 &ctx->view_index);
970
971 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
972 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
973 add_arg(&args, ARG_VGPR, ctx->ac.i32,
974 &ctx->gs_vtx_offset[0]);
975 add_arg(&args, ARG_VGPR, ctx->ac.i32,
976 &ctx->gs_vtx_offset[1]);
977 add_arg(&args, ARG_VGPR, ctx->ac.i32,
978 &ctx->abi.gs_prim_id);
979 add_arg(&args, ARG_VGPR, ctx->ac.i32,
980 &ctx->gs_vtx_offset[2]);
981 add_arg(&args, ARG_VGPR, ctx->ac.i32,
982 &ctx->gs_vtx_offset[3]);
983 add_arg(&args, ARG_VGPR, ctx->ac.i32,
984 &ctx->gs_vtx_offset[4]);
985 add_arg(&args, ARG_VGPR, ctx->ac.i32,
986 &ctx->gs_vtx_offset[5]);
987 add_arg(&args, ARG_VGPR, ctx->ac.i32,
988 &ctx->abi.gs_invocation_id);
989 }
990 break;
991 case MESA_SHADER_FRAGMENT:
992 declare_global_input_sgprs(ctx, stage, has_previous_stage,
993 previous_stage, &user_sgpr_info,
994 &args, &desc_sets);
995
996 if (ctx->shader_info->info.ps.needs_sample_positions)
997 add_arg(&args, ARG_SGPR, ctx->ac.i32,
998 &ctx->sample_pos_offset);
999
1000 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1001 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1002 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1003 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1005 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1008 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1009 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1010 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1014 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1017 break;
1018 default:
1019 unreachable("Shader stage not implemented");
1020 }
1021
1022 ctx->main_function = create_llvm_function(
1023 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1024 ctx->max_workgroup_size,
1025 ctx->options->unsafe_math);
1026 set_llvm_calling_convention(ctx->main_function, stage);
1027
1028
1029 ctx->shader_info->num_input_vgprs = 0;
1030 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1031
1032 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1033
1034 if (ctx->stage != MESA_SHADER_FRAGMENT)
1035 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1036
1037 assign_arguments(ctx->main_function, &args);
1038
1039 user_sgpr_idx = 0;
1040
1041 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1042 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1043 &user_sgpr_idx, 2);
1044 if (ctx->options->supports_spill) {
1045 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1046 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1047 NULL, 0, AC_FUNC_ATTR_READNONE);
1048 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1049 const_array(ctx->ac.v4i32, 16), "");
1050 }
1051 }
1052
1053 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1054 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1055 if (has_previous_stage)
1056 user_sgpr_idx = 0;
1057
1058 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1059 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1060
1061 switch (stage) {
1062 case MESA_SHADER_COMPUTE:
1063 if (ctx->shader_info->info.cs.uses_grid_size) {
1064 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1065 &user_sgpr_idx, 3);
1066 }
1067 break;
1068 case MESA_SHADER_VERTEX:
1069 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1070 previous_stage, &user_sgpr_idx);
1071 if (ctx->view_index)
1072 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1073 if (ctx->options->key.vs.as_ls) {
1074 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1075 &user_sgpr_idx, 1);
1076 }
1077 if (ctx->options->key.vs.as_ls)
1078 ac_declare_lds_as_pointer(&ctx->ac);
1079 break;
1080 case MESA_SHADER_TESS_CTRL:
1081 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1082 previous_stage, &user_sgpr_idx);
1083 if (has_previous_stage)
1084 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1085 &user_sgpr_idx, 1);
1086 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1087 if (ctx->view_index)
1088 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1089 ac_declare_lds_as_pointer(&ctx->ac);
1090 break;
1091 case MESA_SHADER_TESS_EVAL:
1092 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1093 if (ctx->view_index)
1094 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1095 break;
1096 case MESA_SHADER_GEOMETRY:
1097 if (has_previous_stage) {
1098 if (previous_stage == MESA_SHADER_VERTEX)
1099 set_vs_specific_input_locs(ctx, stage,
1100 has_previous_stage,
1101 previous_stage,
1102 &user_sgpr_idx);
1103 else
1104 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1105 &user_sgpr_idx, 1);
1106 }
1107 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1108 &user_sgpr_idx, 2);
1109 if (ctx->view_index)
1110 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1111 if (has_previous_stage)
1112 ac_declare_lds_as_pointer(&ctx->ac);
1113 break;
1114 case MESA_SHADER_FRAGMENT:
1115 if (ctx->shader_info->info.ps.needs_sample_positions) {
1116 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1117 &user_sgpr_idx, 1);
1118 }
1119 break;
1120 default:
1121 unreachable("Shader stage not implemented");
1122 }
1123
1124 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1125 }
1126
1127 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1128 LLVMValueRef value, unsigned count)
1129 {
1130 unsigned num_components = ac_get_llvm_num_components(value);
1131 if (count == num_components)
1132 return value;
1133
1134 LLVMValueRef masks[] = {
1135 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1136 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1137
1138 if (count == 1)
1139 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1140 "");
1141
1142 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1143 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1144 }
1145
1146 static void
1147 build_store_values_extended(struct ac_llvm_context *ac,
1148 LLVMValueRef *values,
1149 unsigned value_count,
1150 unsigned value_stride,
1151 LLVMValueRef vec)
1152 {
1153 LLVMBuilderRef builder = ac->builder;
1154 unsigned i;
1155
1156 for (i = 0; i < value_count; i++) {
1157 LLVMValueRef ptr = values[i * value_stride];
1158 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1159 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1160 LLVMBuildStore(builder, value, ptr);
1161 }
1162 }
1163
1164 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1165 const nir_ssa_def *def)
1166 {
1167 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1168 if (def->num_components > 1) {
1169 type = LLVMVectorType(type, def->num_components);
1170 }
1171 return type;
1172 }
1173
1174 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1175 {
1176 assert(src.is_ssa);
1177 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1178 return (LLVMValueRef)entry->data;
1179 }
1180
1181
1182 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1183 const struct nir_block *b)
1184 {
1185 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1186 return (LLVMBasicBlockRef)entry->data;
1187 }
1188
1189 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1190 nir_alu_src src,
1191 unsigned num_components)
1192 {
1193 LLVMValueRef value = get_src(ctx, src.src);
1194 bool need_swizzle = false;
1195
1196 assert(value);
1197 LLVMTypeRef type = LLVMTypeOf(value);
1198 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1199 ? LLVMGetVectorSize(type)
1200 : 1;
1201
1202 for (unsigned i = 0; i < num_components; ++i) {
1203 assert(src.swizzle[i] < src_components);
1204 if (src.swizzle[i] != i)
1205 need_swizzle = true;
1206 }
1207
1208 if (need_swizzle || num_components != src_components) {
1209 LLVMValueRef masks[] = {
1210 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1211 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1212 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1213 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1214
1215 if (src_components > 1 && num_components == 1) {
1216 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1217 masks[0], "");
1218 } else if (src_components == 1 && num_components > 1) {
1219 LLVMValueRef values[] = {value, value, value, value};
1220 value = ac_build_gather_values(&ctx->ac, values, num_components);
1221 } else {
1222 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1223 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1224 swizzle, "");
1225 }
1226 }
1227 assert(!src.negate);
1228 assert(!src.abs);
1229 return value;
1230 }
1231
1232 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1233 LLVMIntPredicate pred, LLVMValueRef src0,
1234 LLVMValueRef src1)
1235 {
1236 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1237 return LLVMBuildSelect(ctx->builder, result,
1238 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1239 ctx->i32_0, "");
1240 }
1241
1242 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1243 LLVMRealPredicate pred, LLVMValueRef src0,
1244 LLVMValueRef src1)
1245 {
1246 LLVMValueRef result;
1247 src0 = ac_to_float(ctx, src0);
1248 src1 = ac_to_float(ctx, src1);
1249 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1250 return LLVMBuildSelect(ctx->builder, result,
1251 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1252 ctx->i32_0, "");
1253 }
1254
1255 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1256 const char *intrin,
1257 LLVMTypeRef result_type,
1258 LLVMValueRef src0)
1259 {
1260 char name[64];
1261 LLVMValueRef params[] = {
1262 ac_to_float(ctx, src0),
1263 };
1264
1265 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1266 get_elem_bits(ctx, result_type));
1267 assert(length < sizeof(name));
1268 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1269 }
1270
1271 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1272 const char *intrin,
1273 LLVMTypeRef result_type,
1274 LLVMValueRef src0, LLVMValueRef src1)
1275 {
1276 char name[64];
1277 LLVMValueRef params[] = {
1278 ac_to_float(ctx, src0),
1279 ac_to_float(ctx, src1),
1280 };
1281
1282 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1283 get_elem_bits(ctx, result_type));
1284 assert(length < sizeof(name));
1285 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1286 }
1287
1288 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1289 const char *intrin,
1290 LLVMTypeRef result_type,
1291 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1292 {
1293 char name[64];
1294 LLVMValueRef params[] = {
1295 ac_to_float(ctx, src0),
1296 ac_to_float(ctx, src1),
1297 ac_to_float(ctx, src2),
1298 };
1299
1300 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1301 get_elem_bits(ctx, result_type));
1302 assert(length < sizeof(name));
1303 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1304 }
1305
1306 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1307 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1308 {
1309 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1310 ctx->i32_0, "");
1311 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1312 }
1313
1314 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1315 LLVMIntPredicate pred,
1316 LLVMValueRef src0, LLVMValueRef src1)
1317 {
1318 return LLVMBuildSelect(ctx->builder,
1319 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1320 src0,
1321 src1, "");
1322
1323 }
1324 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1325 LLVMValueRef src0)
1326 {
1327 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1328 LLVMBuildNeg(ctx->builder, src0, ""));
1329 }
1330
1331 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1332 LLVMValueRef src0)
1333 {
1334 LLVMValueRef cmp, val;
1335
1336 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1337 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1338 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1339 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1340 return val;
1341 }
1342
1343 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1344 LLVMValueRef src0)
1345 {
1346 LLVMValueRef cmp, val;
1347
1348 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1349 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1350 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1351 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1352 return val;
1353 }
1354
1355 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1356 LLVMValueRef src0)
1357 {
1358 const char *intr = "llvm.floor.f32";
1359 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1360 LLVMValueRef params[] = {
1361 fsrc0,
1362 };
1363 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1364 ctx->f32, params, 1,
1365 AC_FUNC_ATTR_READNONE);
1366 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1367 }
1368
1369 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1370 const char *intrin,
1371 LLVMValueRef src0, LLVMValueRef src1)
1372 {
1373 LLVMTypeRef ret_type;
1374 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1375 LLVMValueRef res;
1376 LLVMValueRef params[] = { src0, src1 };
1377 ret_type = LLVMStructTypeInContext(ctx->context, types,
1378 2, true);
1379
1380 res = ac_build_intrinsic(ctx, intrin, ret_type,
1381 params, 2, AC_FUNC_ATTR_READNONE);
1382
1383 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1384 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1385 return res;
1386 }
1387
1388 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1389 LLVMValueRef src0)
1390 {
1391 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1392 }
1393
1394 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1395 LLVMValueRef src0)
1396 {
1397 src0 = ac_to_float(ctx, src0);
1398 return LLVMBuildSExt(ctx->builder,
1399 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1400 ctx->i32, "");
1401 }
1402
1403 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1404 LLVMValueRef src0)
1405 {
1406 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1407 }
1408
1409 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1410 LLVMValueRef src0)
1411 {
1412 return LLVMBuildSExt(ctx->builder,
1413 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1414 ctx->i32, "");
1415 }
1416
1417 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1418 LLVMValueRef src0)
1419 {
1420 LLVMValueRef result;
1421 LLVMValueRef cond = NULL;
1422
1423 src0 = ac_to_float(&ctx->ac, src0);
1424 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1425
1426 if (ctx->options->chip_class >= VI) {
1427 LLVMValueRef args[2];
1428 /* Check if the result is a denormal - and flush to 0 if so. */
1429 args[0] = result;
1430 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1431 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1432 }
1433
1434 /* need to convert back up to f32 */
1435 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1436
1437 if (ctx->options->chip_class >= VI)
1438 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1439 else {
1440 /* for SI/CIK */
1441 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1442 * so compare the result and flush to 0 if it's smaller.
1443 */
1444 LLVMValueRef temp, cond2;
1445 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1446 ctx->ac.f32, result);
1447 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1448 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1449 temp, "");
1450 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1451 temp, ctx->ac.f32_0, "");
1452 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1453 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1454 }
1455 return result;
1456 }
1457
1458 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1459 LLVMValueRef src0, LLVMValueRef src1)
1460 {
1461 LLVMValueRef dst64, result;
1462 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1463 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1464
1465 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1466 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1467 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1468 return result;
1469 }
1470
1471 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1472 LLVMValueRef src0, LLVMValueRef src1)
1473 {
1474 LLVMValueRef dst64, result;
1475 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1476 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1477
1478 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1479 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1480 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1481 return result;
1482 }
1483
1484 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1485 bool is_signed,
1486 const LLVMValueRef srcs[3])
1487 {
1488 LLVMValueRef result;
1489 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1490
1491 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1492 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1493 return result;
1494 }
1495
1496 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1497 LLVMValueRef src0, LLVMValueRef src1,
1498 LLVMValueRef src2, LLVMValueRef src3)
1499 {
1500 LLVMValueRef bfi_args[3], result;
1501
1502 bfi_args[0] = LLVMBuildShl(ctx->builder,
1503 LLVMBuildSub(ctx->builder,
1504 LLVMBuildShl(ctx->builder,
1505 ctx->i32_1,
1506 src3, ""),
1507 ctx->i32_1, ""),
1508 src2, "");
1509 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1510 bfi_args[2] = src0;
1511
1512 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1513
1514 /* Calculate:
1515 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1516 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1517 */
1518 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1519 LLVMBuildAnd(ctx->builder, bfi_args[0],
1520 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1521
1522 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1523 return result;
1524 }
1525
1526 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1527 LLVMValueRef src0)
1528 {
1529 LLVMValueRef comp[2];
1530
1531 src0 = ac_to_float(ctx, src0);
1532 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1533 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1534
1535 return ac_build_cvt_pkrtz_f16(ctx, comp);
1536 }
1537
1538 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1539 LLVMValueRef src0)
1540 {
1541 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1542 LLVMValueRef temps[2], result, val;
1543 int i;
1544
1545 for (i = 0; i < 2; i++) {
1546 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1547 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1548 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1549 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1550 }
1551
1552 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1553 ctx->i32_0, "");
1554 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1555 ctx->i32_1, "");
1556 return result;
1557 }
1558
1559 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1560 nir_op op,
1561 LLVMValueRef src0)
1562 {
1563 unsigned mask;
1564 int idx;
1565 LLVMValueRef result;
1566
1567 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1568 mask = AC_TID_MASK_LEFT;
1569 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1570 mask = AC_TID_MASK_TOP;
1571 else
1572 mask = AC_TID_MASK_TOP_LEFT;
1573
1574 /* for DDX we want to next X pixel, DDY next Y pixel. */
1575 if (op == nir_op_fddx_fine ||
1576 op == nir_op_fddx_coarse ||
1577 op == nir_op_fddx)
1578 idx = 1;
1579 else
1580 idx = 2;
1581
1582 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1583 return result;
1584 }
1585
1586 /*
1587 * this takes an I,J coordinate pair,
1588 * and works out the X and Y derivatives.
1589 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1590 */
1591 static LLVMValueRef emit_ddxy_interp(
1592 struct ac_nir_context *ctx,
1593 LLVMValueRef interp_ij)
1594 {
1595 LLVMValueRef result[4], a;
1596 unsigned i;
1597
1598 for (i = 0; i < 2; i++) {
1599 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1600 LLVMConstInt(ctx->ac.i32, i, false), "");
1601 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1602 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1603 }
1604 return ac_build_gather_values(&ctx->ac, result, 4);
1605 }
1606
1607 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1608 {
1609 LLVMValueRef src[4], result = NULL;
1610 unsigned num_components = instr->dest.dest.ssa.num_components;
1611 unsigned src_components;
1612 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1613
1614 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1615 switch (instr->op) {
1616 case nir_op_vec2:
1617 case nir_op_vec3:
1618 case nir_op_vec4:
1619 src_components = 1;
1620 break;
1621 case nir_op_pack_half_2x16:
1622 src_components = 2;
1623 break;
1624 case nir_op_unpack_half_2x16:
1625 src_components = 1;
1626 break;
1627 default:
1628 src_components = num_components;
1629 break;
1630 }
1631 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1632 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1633
1634 switch (instr->op) {
1635 case nir_op_fmov:
1636 case nir_op_imov:
1637 result = src[0];
1638 break;
1639 case nir_op_fneg:
1640 src[0] = ac_to_float(&ctx->ac, src[0]);
1641 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1642 break;
1643 case nir_op_ineg:
1644 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1645 break;
1646 case nir_op_inot:
1647 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1648 break;
1649 case nir_op_iadd:
1650 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1651 break;
1652 case nir_op_fadd:
1653 src[0] = ac_to_float(&ctx->ac, src[0]);
1654 src[1] = ac_to_float(&ctx->ac, src[1]);
1655 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1656 break;
1657 case nir_op_fsub:
1658 src[0] = ac_to_float(&ctx->ac, src[0]);
1659 src[1] = ac_to_float(&ctx->ac, src[1]);
1660 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1661 break;
1662 case nir_op_isub:
1663 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1664 break;
1665 case nir_op_imul:
1666 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1667 break;
1668 case nir_op_imod:
1669 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1670 break;
1671 case nir_op_umod:
1672 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1673 break;
1674 case nir_op_fmod:
1675 src[0] = ac_to_float(&ctx->ac, src[0]);
1676 src[1] = ac_to_float(&ctx->ac, src[1]);
1677 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1678 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1679 ac_to_float_type(&ctx->ac, def_type), result);
1680 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1681 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1682 break;
1683 case nir_op_frem:
1684 src[0] = ac_to_float(&ctx->ac, src[0]);
1685 src[1] = ac_to_float(&ctx->ac, src[1]);
1686 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1687 break;
1688 case nir_op_irem:
1689 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1690 break;
1691 case nir_op_idiv:
1692 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1693 break;
1694 case nir_op_udiv:
1695 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1696 break;
1697 case nir_op_fmul:
1698 src[0] = ac_to_float(&ctx->ac, src[0]);
1699 src[1] = ac_to_float(&ctx->ac, src[1]);
1700 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1701 break;
1702 case nir_op_fdiv:
1703 src[0] = ac_to_float(&ctx->ac, src[0]);
1704 src[1] = ac_to_float(&ctx->ac, src[1]);
1705 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1706 break;
1707 case nir_op_frcp:
1708 src[0] = ac_to_float(&ctx->ac, src[0]);
1709 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1710 break;
1711 case nir_op_iand:
1712 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1713 break;
1714 case nir_op_ior:
1715 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1716 break;
1717 case nir_op_ixor:
1718 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1719 break;
1720 case nir_op_ishl:
1721 result = LLVMBuildShl(ctx->ac.builder, src[0],
1722 LLVMBuildZExt(ctx->ac.builder, src[1],
1723 LLVMTypeOf(src[0]), ""),
1724 "");
1725 break;
1726 case nir_op_ishr:
1727 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1728 LLVMBuildZExt(ctx->ac.builder, src[1],
1729 LLVMTypeOf(src[0]), ""),
1730 "");
1731 break;
1732 case nir_op_ushr:
1733 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1734 LLVMBuildZExt(ctx->ac.builder, src[1],
1735 LLVMTypeOf(src[0]), ""),
1736 "");
1737 break;
1738 case nir_op_ilt:
1739 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1740 break;
1741 case nir_op_ine:
1742 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1743 break;
1744 case nir_op_ieq:
1745 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1746 break;
1747 case nir_op_ige:
1748 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1749 break;
1750 case nir_op_ult:
1751 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1752 break;
1753 case nir_op_uge:
1754 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1755 break;
1756 case nir_op_feq:
1757 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1758 break;
1759 case nir_op_fne:
1760 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1761 break;
1762 case nir_op_flt:
1763 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1764 break;
1765 case nir_op_fge:
1766 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1767 break;
1768 case nir_op_fabs:
1769 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1770 ac_to_float_type(&ctx->ac, def_type), src[0]);
1771 break;
1772 case nir_op_iabs:
1773 result = emit_iabs(&ctx->ac, src[0]);
1774 break;
1775 case nir_op_imax:
1776 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1777 break;
1778 case nir_op_imin:
1779 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1780 break;
1781 case nir_op_umax:
1782 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1783 break;
1784 case nir_op_umin:
1785 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1786 break;
1787 case nir_op_isign:
1788 result = emit_isign(&ctx->ac, src[0]);
1789 break;
1790 case nir_op_fsign:
1791 src[0] = ac_to_float(&ctx->ac, src[0]);
1792 result = emit_fsign(&ctx->ac, src[0]);
1793 break;
1794 case nir_op_ffloor:
1795 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1796 ac_to_float_type(&ctx->ac, def_type), src[0]);
1797 break;
1798 case nir_op_ftrunc:
1799 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1800 ac_to_float_type(&ctx->ac, def_type), src[0]);
1801 break;
1802 case nir_op_fceil:
1803 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1804 ac_to_float_type(&ctx->ac, def_type), src[0]);
1805 break;
1806 case nir_op_fround_even:
1807 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1808 ac_to_float_type(&ctx->ac, def_type),src[0]);
1809 break;
1810 case nir_op_ffract:
1811 result = emit_ffract(&ctx->ac, src[0]);
1812 break;
1813 case nir_op_fsin:
1814 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1815 ac_to_float_type(&ctx->ac, def_type), src[0]);
1816 break;
1817 case nir_op_fcos:
1818 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1819 ac_to_float_type(&ctx->ac, def_type), src[0]);
1820 break;
1821 case nir_op_fsqrt:
1822 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1823 ac_to_float_type(&ctx->ac, def_type), src[0]);
1824 break;
1825 case nir_op_fexp2:
1826 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1827 ac_to_float_type(&ctx->ac, def_type), src[0]);
1828 break;
1829 case nir_op_flog2:
1830 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1831 ac_to_float_type(&ctx->ac, def_type), src[0]);
1832 break;
1833 case nir_op_frsq:
1834 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1835 ac_to_float_type(&ctx->ac, def_type), src[0]);
1836 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1837 break;
1838 case nir_op_fpow:
1839 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1840 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1841 break;
1842 case nir_op_fmax:
1843 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1844 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1845 if (instr->dest.dest.ssa.bit_size == 32)
1846 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1847 ac_to_float_type(&ctx->ac, def_type),
1848 result);
1849 break;
1850 case nir_op_fmin:
1851 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1852 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1853 if (instr->dest.dest.ssa.bit_size == 32)
1854 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1855 ac_to_float_type(&ctx->ac, def_type),
1856 result);
1857 break;
1858 case nir_op_ffma:
1859 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1860 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1861 break;
1862 case nir_op_ibitfield_extract:
1863 result = emit_bitfield_extract(&ctx->ac, true, src);
1864 break;
1865 case nir_op_ubitfield_extract:
1866 result = emit_bitfield_extract(&ctx->ac, false, src);
1867 break;
1868 case nir_op_bitfield_insert:
1869 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1870 break;
1871 case nir_op_bitfield_reverse:
1872 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1873 break;
1874 case nir_op_bit_count:
1875 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1876 break;
1877 case nir_op_vec2:
1878 case nir_op_vec3:
1879 case nir_op_vec4:
1880 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1881 src[i] = ac_to_integer(&ctx->ac, src[i]);
1882 result = ac_build_gather_values(&ctx->ac, src, num_components);
1883 break;
1884 case nir_op_f2i32:
1885 case nir_op_f2i64:
1886 src[0] = ac_to_float(&ctx->ac, src[0]);
1887 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1888 break;
1889 case nir_op_f2u32:
1890 case nir_op_f2u64:
1891 src[0] = ac_to_float(&ctx->ac, src[0]);
1892 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1893 break;
1894 case nir_op_i2f32:
1895 case nir_op_i2f64:
1896 src[0] = ac_to_integer(&ctx->ac, src[0]);
1897 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1898 break;
1899 case nir_op_u2f32:
1900 case nir_op_u2f64:
1901 src[0] = ac_to_integer(&ctx->ac, src[0]);
1902 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1903 break;
1904 case nir_op_f2f64:
1905 src[0] = ac_to_float(&ctx->ac, src[0]);
1906 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1907 break;
1908 case nir_op_f2f32:
1909 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1910 break;
1911 case nir_op_u2u32:
1912 case nir_op_u2u64:
1913 src[0] = ac_to_integer(&ctx->ac, src[0]);
1914 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1915 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1916 else
1917 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1918 break;
1919 case nir_op_i2i32:
1920 case nir_op_i2i64:
1921 src[0] = ac_to_integer(&ctx->ac, src[0]);
1922 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1923 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1924 else
1925 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1926 break;
1927 case nir_op_bcsel:
1928 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1929 break;
1930 case nir_op_find_lsb:
1931 src[0] = ac_to_integer(&ctx->ac, src[0]);
1932 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1933 break;
1934 case nir_op_ufind_msb:
1935 src[0] = ac_to_integer(&ctx->ac, src[0]);
1936 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1937 break;
1938 case nir_op_ifind_msb:
1939 src[0] = ac_to_integer(&ctx->ac, src[0]);
1940 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1941 break;
1942 case nir_op_uadd_carry:
1943 src[0] = ac_to_integer(&ctx->ac, src[0]);
1944 src[1] = ac_to_integer(&ctx->ac, src[1]);
1945 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1946 break;
1947 case nir_op_usub_borrow:
1948 src[0] = ac_to_integer(&ctx->ac, src[0]);
1949 src[1] = ac_to_integer(&ctx->ac, src[1]);
1950 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1951 break;
1952 case nir_op_b2f:
1953 result = emit_b2f(&ctx->ac, src[0]);
1954 break;
1955 case nir_op_f2b:
1956 result = emit_f2b(&ctx->ac, src[0]);
1957 break;
1958 case nir_op_b2i:
1959 result = emit_b2i(&ctx->ac, src[0]);
1960 break;
1961 case nir_op_i2b:
1962 src[0] = ac_to_integer(&ctx->ac, src[0]);
1963 result = emit_i2b(&ctx->ac, src[0]);
1964 break;
1965 case nir_op_fquantize2f16:
1966 result = emit_f2f16(ctx->nctx, src[0]);
1967 break;
1968 case nir_op_umul_high:
1969 src[0] = ac_to_integer(&ctx->ac, src[0]);
1970 src[1] = ac_to_integer(&ctx->ac, src[1]);
1971 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1972 break;
1973 case nir_op_imul_high:
1974 src[0] = ac_to_integer(&ctx->ac, src[0]);
1975 src[1] = ac_to_integer(&ctx->ac, src[1]);
1976 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1977 break;
1978 case nir_op_pack_half_2x16:
1979 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1980 break;
1981 case nir_op_unpack_half_2x16:
1982 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1983 break;
1984 case nir_op_fddx:
1985 case nir_op_fddy:
1986 case nir_op_fddx_fine:
1987 case nir_op_fddy_fine:
1988 case nir_op_fddx_coarse:
1989 case nir_op_fddy_coarse:
1990 result = emit_ddxy(ctx, instr->op, src[0]);
1991 break;
1992
1993 case nir_op_unpack_64_2x32_split_x: {
1994 assert(instr->src[0].src.ssa->num_components == 1);
1995 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1996 ctx->ac.v2i32,
1997 "");
1998 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1999 ctx->ac.i32_0, "");
2000 break;
2001 }
2002
2003 case nir_op_unpack_64_2x32_split_y: {
2004 assert(instr->src[0].src.ssa->num_components == 1);
2005 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2006 ctx->ac.v2i32,
2007 "");
2008 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2009 ctx->ac.i32_1, "");
2010 break;
2011 }
2012
2013 case nir_op_pack_64_2x32_split: {
2014 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2015 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2016 src[0], ctx->ac.i32_0, "");
2017 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2018 src[1], ctx->ac.i32_1, "");
2019 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2020 break;
2021 }
2022
2023 default:
2024 fprintf(stderr, "Unknown NIR alu instr: ");
2025 nir_print_instr(&instr->instr, stderr);
2026 fprintf(stderr, "\n");
2027 abort();
2028 }
2029
2030 if (result) {
2031 assert(instr->dest.dest.is_ssa);
2032 result = ac_to_integer(&ctx->ac, result);
2033 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2034 result);
2035 }
2036 }
2037
2038 static void visit_load_const(struct ac_nir_context *ctx,
2039 const nir_load_const_instr *instr)
2040 {
2041 LLVMValueRef values[4], value = NULL;
2042 LLVMTypeRef element_type =
2043 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2044
2045 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2046 switch (instr->def.bit_size) {
2047 case 32:
2048 values[i] = LLVMConstInt(element_type,
2049 instr->value.u32[i], false);
2050 break;
2051 case 64:
2052 values[i] = LLVMConstInt(element_type,
2053 instr->value.u64[i], false);
2054 break;
2055 default:
2056 fprintf(stderr,
2057 "unsupported nir load_const bit_size: %d\n",
2058 instr->def.bit_size);
2059 abort();
2060 }
2061 }
2062 if (instr->def.num_components > 1) {
2063 value = LLVMConstVector(values, instr->def.num_components);
2064 } else
2065 value = values[0];
2066
2067 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2068 }
2069
2070 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2071 LLVMTypeRef type)
2072 {
2073 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2074 return LLVMBuildBitCast(ctx->builder, ptr,
2075 LLVMPointerType(type, addr_space), "");
2076 }
2077
2078 static LLVMValueRef
2079 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2080 {
2081 LLVMValueRef size =
2082 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2083 LLVMConstInt(ctx->ac.i32, 2, false), "");
2084
2085 /* VI only */
2086 if (ctx->ac.chip_class == VI && in_elements) {
2087 /* On VI, the descriptor contains the size in bytes,
2088 * but TXQ must return the size in elements.
2089 * The stride is always non-zero for resources using TXQ.
2090 */
2091 LLVMValueRef stride =
2092 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2093 ctx->ac.i32_1, "");
2094 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2095 LLVMConstInt(ctx->ac.i32, 16, false), "");
2096 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2097 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2098
2099 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2100 }
2101 return size;
2102 }
2103
2104 /**
2105 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2106 * intrinsic names).
2107 */
2108 static void build_int_type_name(
2109 LLVMTypeRef type,
2110 char *buf, unsigned bufsize)
2111 {
2112 assert(bufsize >= 6);
2113
2114 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2115 snprintf(buf, bufsize, "v%ui32",
2116 LLVMGetVectorSize(type));
2117 else
2118 strcpy(buf, "i32");
2119 }
2120
2121 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2122 struct ac_image_args *args,
2123 const nir_tex_instr *instr)
2124 {
2125 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2126 LLVMValueRef coord = args->addr;
2127 LLVMValueRef half_texel[2];
2128 LLVMValueRef compare_cube_wa = NULL;
2129 LLVMValueRef result;
2130 int c;
2131 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2132
2133 //TODO Rect
2134 {
2135 struct ac_image_args txq_args = { 0 };
2136
2137 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2138 txq_args.opcode = ac_image_get_resinfo;
2139 txq_args.dmask = 0xf;
2140 txq_args.addr = ctx->i32_0;
2141 txq_args.resource = args->resource;
2142 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2143
2144 for (c = 0; c < 2; c++) {
2145 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2146 LLVMConstInt(ctx->i32, c, false), "");
2147 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2148 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2149 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2150 LLVMConstReal(ctx->f32, -0.5), "");
2151 }
2152 }
2153
2154 LLVMValueRef orig_coords = args->addr;
2155
2156 for (c = 0; c < 2; c++) {
2157 LLVMValueRef tmp;
2158 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2159 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2160 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2161 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2162 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2163 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2164 }
2165
2166
2167 /*
2168 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2169 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2170 * workaround by sampling using a scaled type and converting.
2171 * This is taken from amdgpu-pro shaders.
2172 */
2173 /* NOTE this produces some ugly code compared to amdgpu-pro,
2174 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2175 * and then reads them back. -pro generates two selects,
2176 * one s_cmp for the descriptor rewriting
2177 * one v_cmp for the coordinate and result changes.
2178 */
2179 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2180 LLVMValueRef tmp, tmp2;
2181
2182 /* workaround 8/8/8/8 uint/sint cube gather bug */
2183 /* first detect it then change to a scaled read and f2i */
2184 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2185 tmp2 = tmp;
2186
2187 /* extract the DATA_FORMAT */
2188 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2189 LLVMConstInt(ctx->i32, 6, false), false);
2190
2191 /* is the DATA_FORMAT == 8_8_8_8 */
2192 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2193
2194 if (stype == GLSL_TYPE_UINT)
2195 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2196 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2197 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2198 else
2199 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2200 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2201 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2202
2203 /* replace the NUM FORMAT in the descriptor */
2204 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2205 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2206
2207 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2208
2209 /* don't modify the coordinates for this case */
2210 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2211 }
2212 args->addr = coord;
2213 result = ac_build_image_opcode(ctx, args);
2214
2215 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2216 LLVMValueRef tmp, tmp2;
2217
2218 /* if the cube workaround is in place, f2i the result. */
2219 for (c = 0; c < 4; c++) {
2220 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2221 if (stype == GLSL_TYPE_UINT)
2222 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2223 else
2224 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2225 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2226 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2227 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2228 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2229 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2230 }
2231 }
2232 return result;
2233 }
2234
2235 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2236 const nir_tex_instr *instr,
2237 bool lod_is_zero,
2238 struct ac_image_args *args)
2239 {
2240 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2241 return ac_build_buffer_load_format(&ctx->ac,
2242 args->resource,
2243 args->addr,
2244 ctx->ac.i32_0,
2245 true);
2246 }
2247
2248 args->opcode = ac_image_sample;
2249 args->compare = instr->is_shadow;
2250
2251 switch (instr->op) {
2252 case nir_texop_txf:
2253 case nir_texop_txf_ms:
2254 case nir_texop_samples_identical:
2255 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2256 args->compare = false;
2257 args->offset = false;
2258 break;
2259 case nir_texop_txb:
2260 args->bias = true;
2261 break;
2262 case nir_texop_txl:
2263 if (lod_is_zero)
2264 args->level_zero = true;
2265 else
2266 args->lod = true;
2267 break;
2268 case nir_texop_txs:
2269 case nir_texop_query_levels:
2270 args->opcode = ac_image_get_resinfo;
2271 break;
2272 case nir_texop_tex:
2273 if (ctx->stage != MESA_SHADER_FRAGMENT)
2274 args->level_zero = true;
2275 break;
2276 case nir_texop_txd:
2277 args->deriv = true;
2278 break;
2279 case nir_texop_tg4:
2280 args->opcode = ac_image_gather4;
2281 args->level_zero = true;
2282 break;
2283 case nir_texop_lod:
2284 args->opcode = ac_image_get_lod;
2285 args->compare = false;
2286 args->offset = false;
2287 break;
2288 default:
2289 break;
2290 }
2291
2292 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2293 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2294 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2295 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2296 }
2297 }
2298 return ac_build_image_opcode(&ctx->ac, args);
2299 }
2300
2301 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2302 nir_intrinsic_instr *instr)
2303 {
2304 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2305 unsigned desc_set = nir_intrinsic_desc_set(instr);
2306 unsigned binding = nir_intrinsic_binding(instr);
2307 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2308 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2309 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2310 unsigned base_offset = layout->binding[binding].offset;
2311 LLVMValueRef offset, stride;
2312
2313 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2314 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2315 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2316 layout->binding[binding].dynamic_offset_offset;
2317 desc_ptr = ctx->push_constants;
2318 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2319 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2320 } else
2321 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2322
2323 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2324 index = LLVMBuildMul(ctx->builder, index, stride, "");
2325 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2326
2327 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2328 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2329 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2330
2331 return desc_ptr;
2332 }
2333
2334 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2335 nir_intrinsic_instr *instr)
2336 {
2337 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2338 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2339
2340 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2341 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2342 return result;
2343 }
2344
2345 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2346 nir_intrinsic_instr *instr)
2347 {
2348 LLVMValueRef ptr, addr;
2349
2350 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2351 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2352
2353 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2354 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2355
2356 return LLVMBuildLoad(ctx->builder, ptr, "");
2357 }
2358
2359 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2360 const nir_intrinsic_instr *instr)
2361 {
2362 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2363
2364 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2365 }
2366 static void visit_store_ssbo(struct ac_nir_context *ctx,
2367 nir_intrinsic_instr *instr)
2368 {
2369 const char *store_name;
2370 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2371 LLVMTypeRef data_type = ctx->ac.f32;
2372 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2373 int components_32bit = elem_size_mult * instr->num_components;
2374 unsigned writemask = nir_intrinsic_write_mask(instr);
2375 LLVMValueRef base_data, base_offset;
2376 LLVMValueRef params[6];
2377
2378 params[1] = ctx->abi->load_ssbo(ctx->abi,
2379 get_src(ctx, instr->src[1]), true);
2380 params[2] = ctx->ac.i32_0; /* vindex */
2381 params[4] = ctx->ac.i1false; /* glc */
2382 params[5] = ctx->ac.i1false; /* slc */
2383
2384 if (components_32bit > 1)
2385 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2386
2387 base_data = ac_to_float(&ctx->ac, src_data);
2388 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2389 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2390 data_type, "");
2391 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2392 while (writemask) {
2393 int start, count;
2394 LLVMValueRef data;
2395 LLVMValueRef offset;
2396 LLVMValueRef tmp;
2397 u_bit_scan_consecutive_range(&writemask, &start, &count);
2398
2399 /* Due to an LLVM limitation, split 3-element writes
2400 * into a 2-element and a 1-element write. */
2401 if (count == 3) {
2402 writemask |= 1 << (start + 2);
2403 count = 2;
2404 }
2405
2406 start *= elem_size_mult;
2407 count *= elem_size_mult;
2408
2409 if (count > 4) {
2410 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2411 count = 4;
2412 }
2413
2414 if (count == 4) {
2415 store_name = "llvm.amdgcn.buffer.store.v4f32";
2416 data = base_data;
2417 } else if (count == 2) {
2418 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2419 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2420 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2421 ctx->ac.i32_0, "");
2422
2423 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2424 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2425 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2426 ctx->ac.i32_1, "");
2427 store_name = "llvm.amdgcn.buffer.store.v2f32";
2428
2429 } else {
2430 assert(count == 1);
2431 if (ac_get_llvm_num_components(base_data) > 1)
2432 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2433 LLVMConstInt(ctx->ac.i32, start, false), "");
2434 else
2435 data = base_data;
2436 store_name = "llvm.amdgcn.buffer.store.f32";
2437 }
2438
2439 offset = base_offset;
2440 if (start != 0) {
2441 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2442 }
2443 params[0] = data;
2444 params[3] = offset;
2445 ac_build_intrinsic(&ctx->ac, store_name,
2446 ctx->ac.voidt, params, 6, 0);
2447 }
2448 }
2449
2450 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2451 const nir_intrinsic_instr *instr)
2452 {
2453 const char *name;
2454 LLVMValueRef params[6];
2455 int arg_count = 0;
2456
2457 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2458 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2459 }
2460 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2461 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2462 get_src(ctx, instr->src[0]),
2463 true);
2464 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2465 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2466 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2467
2468 switch (instr->intrinsic) {
2469 case nir_intrinsic_ssbo_atomic_add:
2470 name = "llvm.amdgcn.buffer.atomic.add";
2471 break;
2472 case nir_intrinsic_ssbo_atomic_imin:
2473 name = "llvm.amdgcn.buffer.atomic.smin";
2474 break;
2475 case nir_intrinsic_ssbo_atomic_umin:
2476 name = "llvm.amdgcn.buffer.atomic.umin";
2477 break;
2478 case nir_intrinsic_ssbo_atomic_imax:
2479 name = "llvm.amdgcn.buffer.atomic.smax";
2480 break;
2481 case nir_intrinsic_ssbo_atomic_umax:
2482 name = "llvm.amdgcn.buffer.atomic.umax";
2483 break;
2484 case nir_intrinsic_ssbo_atomic_and:
2485 name = "llvm.amdgcn.buffer.atomic.and";
2486 break;
2487 case nir_intrinsic_ssbo_atomic_or:
2488 name = "llvm.amdgcn.buffer.atomic.or";
2489 break;
2490 case nir_intrinsic_ssbo_atomic_xor:
2491 name = "llvm.amdgcn.buffer.atomic.xor";
2492 break;
2493 case nir_intrinsic_ssbo_atomic_exchange:
2494 name = "llvm.amdgcn.buffer.atomic.swap";
2495 break;
2496 case nir_intrinsic_ssbo_atomic_comp_swap:
2497 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2498 break;
2499 default:
2500 abort();
2501 }
2502
2503 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2504 }
2505
2506 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2507 const nir_intrinsic_instr *instr)
2508 {
2509 LLVMValueRef results[2];
2510 int load_components;
2511 int num_components = instr->num_components;
2512 if (instr->dest.ssa.bit_size == 64)
2513 num_components *= 2;
2514
2515 for (int i = 0; i < num_components; i += load_components) {
2516 load_components = MIN2(num_components - i, 4);
2517 const char *load_name;
2518 LLVMTypeRef data_type = ctx->ac.f32;
2519 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2520 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2521
2522 if (load_components == 3)
2523 data_type = LLVMVectorType(ctx->ac.f32, 4);
2524 else if (load_components > 1)
2525 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2526
2527 if (load_components >= 3)
2528 load_name = "llvm.amdgcn.buffer.load.v4f32";
2529 else if (load_components == 2)
2530 load_name = "llvm.amdgcn.buffer.load.v2f32";
2531 else if (load_components == 1)
2532 load_name = "llvm.amdgcn.buffer.load.f32";
2533 else
2534 unreachable("unhandled number of components");
2535
2536 LLVMValueRef params[] = {
2537 ctx->abi->load_ssbo(ctx->abi,
2538 get_src(ctx, instr->src[0]),
2539 false),
2540 ctx->ac.i32_0,
2541 offset,
2542 ctx->ac.i1false,
2543 ctx->ac.i1false,
2544 };
2545
2546 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2547
2548 }
2549
2550 assume(results[0]);
2551 LLVMValueRef ret = results[0];
2552 if (num_components > 4 || num_components == 3) {
2553 LLVMValueRef masks[] = {
2554 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2555 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2556 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2557 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2558 };
2559
2560 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2561 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2562 results[num_components > 4 ? 1 : 0], swizzle, "");
2563 }
2564
2565 return LLVMBuildBitCast(ctx->ac.builder, ret,
2566 get_def_type(ctx, &instr->dest.ssa), "");
2567 }
2568
2569 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2570 const nir_intrinsic_instr *instr)
2571 {
2572 LLVMValueRef results[8], ret;
2573 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2574 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2575 int num_components = instr->num_components;
2576
2577 if (ctx->abi->load_ubo)
2578 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2579
2580 if (instr->dest.ssa.bit_size == 64)
2581 num_components *= 2;
2582
2583 for (unsigned i = 0; i < num_components; ++i) {
2584 LLVMValueRef params[] = {
2585 rsrc,
2586 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2587 offset, "")
2588 };
2589 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2590 params, 2,
2591 AC_FUNC_ATTR_READNONE |
2592 AC_FUNC_ATTR_LEGACY);
2593 }
2594
2595
2596 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2597 return LLVMBuildBitCast(ctx->ac.builder, ret,
2598 get_def_type(ctx, &instr->dest.ssa), "");
2599 }
2600
2601 static void
2602 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2603 bool vs_in, unsigned *vertex_index_out,
2604 LLVMValueRef *vertex_index_ref,
2605 unsigned *const_out, LLVMValueRef *indir_out)
2606 {
2607 unsigned const_offset = 0;
2608 nir_deref *tail = &deref->deref;
2609 LLVMValueRef offset = NULL;
2610
2611 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2612 tail = tail->child;
2613 nir_deref_array *deref_array = nir_deref_as_array(tail);
2614 if (vertex_index_out)
2615 *vertex_index_out = deref_array->base_offset;
2616
2617 if (vertex_index_ref) {
2618 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2619 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2620 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2621 }
2622 *vertex_index_ref = vtx;
2623 }
2624 }
2625
2626 if (deref->var->data.compact) {
2627 assert(tail->child->deref_type == nir_deref_type_array);
2628 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2629 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2630 /* We always lower indirect dereferences for "compact" array vars. */
2631 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2632
2633 const_offset = deref_array->base_offset;
2634 goto out;
2635 }
2636
2637 while (tail->child != NULL) {
2638 const struct glsl_type *parent_type = tail->type;
2639 tail = tail->child;
2640
2641 if (tail->deref_type == nir_deref_type_array) {
2642 nir_deref_array *deref_array = nir_deref_as_array(tail);
2643 LLVMValueRef index, stride, local_offset;
2644 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2645
2646 const_offset += size * deref_array->base_offset;
2647 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2648 continue;
2649
2650 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2651 index = get_src(ctx, deref_array->indirect);
2652 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2653 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2654
2655 if (offset)
2656 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2657 else
2658 offset = local_offset;
2659 } else if (tail->deref_type == nir_deref_type_struct) {
2660 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2661
2662 for (unsigned i = 0; i < deref_struct->index; i++) {
2663 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2664 const_offset += glsl_count_attribute_slots(ft, vs_in);
2665 }
2666 } else
2667 unreachable("unsupported deref type");
2668
2669 }
2670 out:
2671 if (const_offset && offset)
2672 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2673 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2674 "");
2675
2676 *const_out = const_offset;
2677 *indir_out = offset;
2678 }
2679
2680
2681 /* The offchip buffer layout for TCS->TES is
2682 *
2683 * - attribute 0 of patch 0 vertex 0
2684 * - attribute 0 of patch 0 vertex 1
2685 * - attribute 0 of patch 0 vertex 2
2686 * ...
2687 * - attribute 0 of patch 1 vertex 0
2688 * - attribute 0 of patch 1 vertex 1
2689 * ...
2690 * - attribute 1 of patch 0 vertex 0
2691 * - attribute 1 of patch 0 vertex 1
2692 * ...
2693 * - per patch attribute 0 of patch 0
2694 * - per patch attribute 0 of patch 1
2695 * ...
2696 *
2697 * Note that every attribute has 4 components.
2698 */
2699 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2700 LLVMValueRef vertex_index,
2701 LLVMValueRef param_index)
2702 {
2703 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2704 LLVMValueRef param_stride, constant16;
2705 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2706
2707 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2708 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2709 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2710 num_patches, "");
2711
2712 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2713 if (vertex_index) {
2714 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2715 vertices_per_patch, "");
2716
2717 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2718 vertex_index, "");
2719
2720 param_stride = total_vertices;
2721 } else {
2722 base_addr = rel_patch_id;
2723 param_stride = num_patches;
2724 }
2725
2726 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2727 LLVMBuildMul(ctx->builder, param_index,
2728 param_stride, ""), "");
2729
2730 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2731
2732 if (!vertex_index) {
2733 LLVMValueRef patch_data_offset =
2734 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2735
2736 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2737 patch_data_offset, "");
2738 }
2739 return base_addr;
2740 }
2741
2742 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2743 unsigned param,
2744 unsigned const_index,
2745 bool is_compact,
2746 LLVMValueRef vertex_index,
2747 LLVMValueRef indir_index)
2748 {
2749 LLVMValueRef param_index;
2750
2751 if (indir_index)
2752 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2753 indir_index, "");
2754 else {
2755 if (const_index && !is_compact)
2756 param += const_index;
2757 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2758 }
2759 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2760 }
2761
2762 static void
2763 mark_tess_output(struct nir_to_llvm_context *ctx,
2764 bool is_patch, uint32_t param)
2765
2766 {
2767 if (is_patch) {
2768 ctx->tess_patch_outputs_written |= (1ull << param);
2769 } else
2770 ctx->tess_outputs_written |= (1ull << param);
2771 }
2772
2773 static LLVMValueRef
2774 get_dw_address(struct nir_to_llvm_context *ctx,
2775 LLVMValueRef dw_addr,
2776 unsigned param,
2777 unsigned const_index,
2778 bool compact_const_index,
2779 LLVMValueRef vertex_index,
2780 LLVMValueRef stride,
2781 LLVMValueRef indir_index)
2782
2783 {
2784
2785 if (vertex_index) {
2786 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2787 LLVMBuildMul(ctx->builder,
2788 vertex_index,
2789 stride, ""), "");
2790 }
2791
2792 if (indir_index)
2793 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2794 LLVMBuildMul(ctx->builder, indir_index,
2795 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2796 else if (const_index && !compact_const_index)
2797 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2798 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2799
2800 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2801 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2802
2803 if (const_index && compact_const_index)
2804 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2805 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2806 return dw_addr;
2807 }
2808
2809 static LLVMValueRef
2810 load_tcs_input(struct ac_shader_abi *abi,
2811 LLVMValueRef vertex_index,
2812 LLVMValueRef indir_index,
2813 unsigned const_index,
2814 unsigned location,
2815 unsigned driver_location,
2816 unsigned component,
2817 unsigned num_components,
2818 bool is_patch,
2819 bool is_compact)
2820 {
2821 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2822 LLVMValueRef dw_addr, stride;
2823 LLVMValueRef value[4], result;
2824 unsigned param = shader_io_get_unique_index(location);
2825
2826 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2827 dw_addr = get_tcs_in_current_patch_offset(ctx);
2828 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2829 indir_index);
2830
2831 for (unsigned i = 0; i < num_components + component; i++) {
2832 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2833 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2834 ctx->ac.i32_1, "");
2835 }
2836 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2837 return result;
2838 }
2839
2840 static LLVMValueRef
2841 load_tcs_output(struct nir_to_llvm_context *ctx,
2842 nir_intrinsic_instr *instr)
2843 {
2844 LLVMValueRef dw_addr;
2845 LLVMValueRef stride = NULL;
2846 LLVMValueRef value[4], result;
2847 LLVMValueRef vertex_index = NULL;
2848 LLVMValueRef indir_index = NULL;
2849 unsigned const_index = 0;
2850 unsigned param;
2851 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2852 const bool is_compact = instr->variables[0]->var->data.compact;
2853 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2854 get_deref_offset(ctx->nir, instr->variables[0],
2855 false, NULL, per_vertex ? &vertex_index : NULL,
2856 &const_index, &indir_index);
2857
2858 if (!instr->variables[0]->var->data.patch) {
2859 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2860 dw_addr = get_tcs_out_current_patch_offset(ctx);
2861 } else {
2862 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2863 }
2864
2865 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2866 indir_index);
2867
2868 unsigned comp = instr->variables[0]->var->data.location_frac;
2869 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2870 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2871 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2872 ctx->ac.i32_1, "");
2873 }
2874 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2875 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2876 return result;
2877 }
2878
2879 static void
2880 store_tcs_output(struct ac_shader_abi *abi,
2881 LLVMValueRef vertex_index,
2882 LLVMValueRef param_index,
2883 unsigned const_index,
2884 unsigned location,
2885 unsigned driver_location,
2886 LLVMValueRef src,
2887 unsigned component,
2888 bool is_patch,
2889 bool is_compact,
2890 unsigned writemask)
2891 {
2892 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2893 LLVMValueRef dw_addr;
2894 LLVMValueRef stride = NULL;
2895 LLVMValueRef buf_addr = NULL;
2896 unsigned param;
2897 bool store_lds = true;
2898
2899 if (is_patch) {
2900 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2901 store_lds = false;
2902 } else {
2903 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2904 store_lds = false;
2905 }
2906
2907 param = shader_io_get_unique_index(location);
2908 if (location == VARYING_SLOT_CLIP_DIST0 &&
2909 is_compact && const_index > 3) {
2910 const_index -= 3;
2911 param++;
2912 }
2913
2914 if (!is_patch) {
2915 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2916 dw_addr = get_tcs_out_current_patch_offset(ctx);
2917 } else {
2918 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2919 }
2920
2921 mark_tess_output(ctx, is_patch, param);
2922
2923 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2924 param_index);
2925 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2926 vertex_index, param_index);
2927
2928 bool is_tess_factor = false;
2929 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2930 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2931 is_tess_factor = true;
2932
2933 unsigned base = is_compact ? const_index : 0;
2934 for (unsigned chan = 0; chan < 8; chan++) {
2935 if (!(writemask & (1 << chan)))
2936 continue;
2937 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2938
2939 if (store_lds || is_tess_factor)
2940 ac_lds_store(&ctx->ac, dw_addr, value);
2941
2942 if (!is_tess_factor && writemask != 0xF)
2943 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2944 buf_addr, ctx->oc_lds,
2945 4 * (base + chan), 1, 0, true, false);
2946
2947 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2948 ctx->ac.i32_1, "");
2949 }
2950
2951 if (writemask == 0xF) {
2952 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2953 buf_addr, ctx->oc_lds,
2954 (base * 4), 1, 0, true, false);
2955 }
2956 }
2957
2958 static LLVMValueRef
2959 load_tes_input(struct ac_shader_abi *abi,
2960 LLVMValueRef vertex_index,
2961 LLVMValueRef param_index,
2962 unsigned const_index,
2963 unsigned location,
2964 unsigned driver_location,
2965 unsigned component,
2966 unsigned num_components,
2967 bool is_patch,
2968 bool is_compact)
2969 {
2970 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2971 LLVMValueRef buf_addr;
2972 LLVMValueRef result;
2973 unsigned param = shader_io_get_unique_index(location);
2974
2975 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
2976 const_index -= 3;
2977 param++;
2978 }
2979
2980 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2981 is_compact, vertex_index, param_index);
2982
2983 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
2984 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2985
2986 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
2987 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2988 result = trim_vector(&ctx->ac, result, num_components);
2989 return result;
2990 }
2991
2992 static LLVMValueRef
2993 load_gs_input(struct ac_shader_abi *abi,
2994 unsigned location,
2995 unsigned driver_location,
2996 unsigned component,
2997 unsigned num_components,
2998 unsigned vertex_index,
2999 unsigned const_index,
3000 LLVMTypeRef type)
3001 {
3002 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3003 LLVMValueRef vtx_offset;
3004 LLVMValueRef args[9];
3005 unsigned param, vtx_offset_param;
3006 LLVMValueRef value[4], result;
3007
3008 vtx_offset_param = vertex_index;
3009 assert(vtx_offset_param < 6);
3010 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3011 LLVMConstInt(ctx->ac.i32, 4, false), "");
3012
3013 param = shader_io_get_unique_index(location);
3014
3015 for (unsigned i = component; i < num_components + component; i++) {
3016 if (ctx->ac.chip_class >= GFX9) {
3017 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3018 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3019 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3020 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3021 } else {
3022 args[0] = ctx->esgs_ring;
3023 args[1] = vtx_offset;
3024 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3025 args[3] = ctx->ac.i32_0;
3026 args[4] = ctx->ac.i32_1; /* OFFEN */
3027 args[5] = ctx->ac.i32_0; /* IDXEN */
3028 args[6] = ctx->ac.i32_1; /* GLC */
3029 args[7] = ctx->ac.i32_0; /* SLC */
3030 args[8] = ctx->ac.i32_0; /* TFE */
3031
3032 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3033 ctx->ac.i32, args, 9,
3034 AC_FUNC_ATTR_READONLY |
3035 AC_FUNC_ATTR_LEGACY);
3036 }
3037 }
3038 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3039
3040 return result;
3041 }
3042
3043 static LLVMValueRef
3044 build_gep_for_deref(struct ac_nir_context *ctx,
3045 nir_deref_var *deref)
3046 {
3047 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3048 assert(entry->data);
3049 LLVMValueRef val = entry->data;
3050 nir_deref *tail = deref->deref.child;
3051 while (tail != NULL) {
3052 LLVMValueRef offset;
3053 switch (tail->deref_type) {
3054 case nir_deref_type_array: {
3055 nir_deref_array *array = nir_deref_as_array(tail);
3056 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3057 if (array->deref_array_type ==
3058 nir_deref_array_type_indirect) {
3059 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3060 get_src(ctx,
3061 array->indirect),
3062 "");
3063 }
3064 break;
3065 }
3066 case nir_deref_type_struct: {
3067 nir_deref_struct *deref_struct =
3068 nir_deref_as_struct(tail);
3069 offset = LLVMConstInt(ctx->ac.i32,
3070 deref_struct->index, 0);
3071 break;
3072 }
3073 default:
3074 unreachable("bad deref type");
3075 }
3076 val = ac_build_gep0(&ctx->ac, val, offset);
3077 tail = tail->child;
3078 }
3079 return val;
3080 }
3081
3082 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3083 nir_intrinsic_instr *instr)
3084 {
3085 LLVMValueRef values[8];
3086 int idx = instr->variables[0]->var->data.driver_location;
3087 int ve = instr->dest.ssa.num_components;
3088 unsigned comp = instr->variables[0]->var->data.location_frac;
3089 LLVMValueRef indir_index;
3090 LLVMValueRef ret;
3091 unsigned const_index;
3092 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3093 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3094 instr->variables[0]->var->data.mode == nir_var_shader_in;
3095 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3096 &const_index, &indir_index);
3097
3098 if (instr->dest.ssa.bit_size == 64)
3099 ve *= 2;
3100
3101 switch (instr->variables[0]->var->data.mode) {
3102 case nir_var_shader_in:
3103 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3104 ctx->stage == MESA_SHADER_TESS_EVAL) {
3105 LLVMValueRef result;
3106 LLVMValueRef vertex_index = NULL;
3107 LLVMValueRef indir_index = NULL;
3108 unsigned const_index = 0;
3109 unsigned location = instr->variables[0]->var->data.location;
3110 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3111 const bool is_patch = instr->variables[0]->var->data.patch;
3112 const bool is_compact = instr->variables[0]->var->data.compact;
3113
3114 get_deref_offset(ctx, instr->variables[0],
3115 false, NULL, is_patch ? NULL : &vertex_index,
3116 &const_index, &indir_index);
3117
3118 result = ctx->abi->load_tess_inputs(ctx->abi, vertex_index, indir_index,
3119 const_index, location, driver_location,
3120 instr->variables[0]->var->data.location_frac,
3121 instr->num_components,
3122 is_patch, is_compact);
3123 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3124 }
3125
3126 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3127 LLVMValueRef indir_index;
3128 unsigned const_index, vertex_index;
3129 get_deref_offset(ctx, instr->variables[0],
3130 false, &vertex_index, NULL,
3131 &const_index, &indir_index);
3132 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3133 instr->variables[0]->var->data.driver_location,
3134 instr->variables[0]->var->data.location_frac, ve,
3135 vertex_index, const_index,
3136 nir2llvmtype(ctx, instr->variables[0]->var->type));
3137 }
3138
3139 for (unsigned chan = comp; chan < ve + comp; chan++) {
3140 if (indir_index) {
3141 unsigned count = glsl_count_attribute_slots(
3142 instr->variables[0]->var->type,
3143 ctx->stage == MESA_SHADER_VERTEX);
3144 count -= chan / 4;
3145 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3146 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3147 stride, false, true);
3148
3149 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3150 tmp_vec,
3151 indir_index, "");
3152 } else
3153 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3154 }
3155 break;
3156 case nir_var_local:
3157 for (unsigned chan = 0; chan < ve; chan++) {
3158 if (indir_index) {
3159 unsigned count = glsl_count_attribute_slots(
3160 instr->variables[0]->var->type, false);
3161 count -= chan / 4;
3162 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3163 &ctx->ac, ctx->locals + idx + chan, count,
3164 stride, true, true);
3165
3166 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3167 tmp_vec,
3168 indir_index, "");
3169 } else {
3170 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3171 }
3172 }
3173 break;
3174 case nir_var_shared: {
3175 LLVMValueRef address = build_gep_for_deref(ctx,
3176 instr->variables[0]);
3177 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3178 return LLVMBuildBitCast(ctx->ac.builder, val,
3179 get_def_type(ctx, &instr->dest.ssa),
3180 "");
3181 }
3182 case nir_var_shader_out:
3183 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3184 return load_tcs_output(ctx->nctx, instr);
3185
3186 for (unsigned chan = comp; chan < ve + comp; chan++) {
3187 if (indir_index) {
3188 unsigned count = glsl_count_attribute_slots(
3189 instr->variables[0]->var->type, false);
3190 count -= chan / 4;
3191 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3192 &ctx->ac, ctx->outputs + idx + chan, count,
3193 stride, true, true);
3194
3195 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3196 tmp_vec,
3197 indir_index, "");
3198 } else {
3199 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3200 ctx->outputs[idx + chan + const_index * stride],
3201 "");
3202 }
3203 }
3204 break;
3205 default:
3206 unreachable("unhandle variable mode");
3207 }
3208 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3209 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3210 }
3211
3212 static void
3213 visit_store_var(struct ac_nir_context *ctx,
3214 nir_intrinsic_instr *instr)
3215 {
3216 LLVMValueRef temp_ptr, value;
3217 int idx = instr->variables[0]->var->data.driver_location;
3218 unsigned comp = instr->variables[0]->var->data.location_frac;
3219 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3220 int writemask = instr->const_index[0] << comp;
3221 LLVMValueRef indir_index;
3222 unsigned const_index;
3223 get_deref_offset(ctx, instr->variables[0], false,
3224 NULL, NULL, &const_index, &indir_index);
3225
3226 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3227 int old_writemask = writemask;
3228
3229 src = LLVMBuildBitCast(ctx->ac.builder, src,
3230 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3231 "");
3232
3233 writemask = 0;
3234 for (unsigned chan = 0; chan < 4; chan++) {
3235 if (old_writemask & (1 << chan))
3236 writemask |= 3u << (2 * chan);
3237 }
3238 }
3239
3240 switch (instr->variables[0]->var->data.mode) {
3241 case nir_var_shader_out:
3242
3243 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3244 LLVMValueRef vertex_index = NULL;
3245 LLVMValueRef indir_index = NULL;
3246 unsigned const_index = 0;
3247 const unsigned location = instr->variables[0]->var->data.location;
3248 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3249 const unsigned comp = instr->variables[0]->var->data.location_frac;
3250 const bool is_patch = instr->variables[0]->var->data.patch;
3251 const bool is_compact = instr->variables[0]->var->data.compact;
3252
3253 get_deref_offset(ctx, instr->variables[0],
3254 false, NULL, is_patch ? NULL : &vertex_index,
3255 &const_index, &indir_index);
3256
3257 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3258 const_index, location, driver_location,
3259 src, comp, is_patch, is_compact, writemask);
3260 return;
3261 }
3262
3263 for (unsigned chan = 0; chan < 8; chan++) {
3264 int stride = 4;
3265 if (!(writemask & (1 << chan)))
3266 continue;
3267
3268 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3269
3270 if (instr->variables[0]->var->data.compact)
3271 stride = 1;
3272 if (indir_index) {
3273 unsigned count = glsl_count_attribute_slots(
3274 instr->variables[0]->var->type, false);
3275 count -= chan / 4;
3276 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3277 &ctx->ac, ctx->outputs + idx + chan, count,
3278 stride, true, true);
3279
3280 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3281 value, indir_index, "");
3282 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3283 count, stride, tmp_vec);
3284
3285 } else {
3286 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3287
3288 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3289 }
3290 }
3291 break;
3292 case nir_var_local:
3293 for (unsigned chan = 0; chan < 8; chan++) {
3294 if (!(writemask & (1 << chan)))
3295 continue;
3296
3297 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3298 if (indir_index) {
3299 unsigned count = glsl_count_attribute_slots(
3300 instr->variables[0]->var->type, false);
3301 count -= chan / 4;
3302 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3303 &ctx->ac, ctx->locals + idx + chan, count,
3304 4, true, true);
3305
3306 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3307 value, indir_index, "");
3308 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3309 count, 4, tmp_vec);
3310 } else {
3311 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3312
3313 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3314 }
3315 }
3316 break;
3317 case nir_var_shared: {
3318 int writemask = instr->const_index[0];
3319 LLVMValueRef address = build_gep_for_deref(ctx,
3320 instr->variables[0]);
3321 LLVMValueRef val = get_src(ctx, instr->src[0]);
3322 unsigned components =
3323 glsl_get_vector_elements(
3324 nir_deref_tail(&instr->variables[0]->deref)->type);
3325 if (writemask == (1 << components) - 1) {
3326 val = LLVMBuildBitCast(
3327 ctx->ac.builder, val,
3328 LLVMGetElementType(LLVMTypeOf(address)), "");
3329 LLVMBuildStore(ctx->ac.builder, val, address);
3330 } else {
3331 for (unsigned chan = 0; chan < 4; chan++) {
3332 if (!(writemask & (1 << chan)))
3333 continue;
3334 LLVMValueRef ptr =
3335 LLVMBuildStructGEP(ctx->ac.builder,
3336 address, chan, "");
3337 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3338 chan);
3339 src = LLVMBuildBitCast(
3340 ctx->ac.builder, src,
3341 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3342 LLVMBuildStore(ctx->ac.builder, src, ptr);
3343 }
3344 }
3345 break;
3346 }
3347 default:
3348 break;
3349 }
3350 }
3351
3352 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3353 {
3354 switch (dim) {
3355 case GLSL_SAMPLER_DIM_BUF:
3356 return 1;
3357 case GLSL_SAMPLER_DIM_1D:
3358 return array ? 2 : 1;
3359 case GLSL_SAMPLER_DIM_2D:
3360 return array ? 3 : 2;
3361 case GLSL_SAMPLER_DIM_MS:
3362 return array ? 4 : 3;
3363 case GLSL_SAMPLER_DIM_3D:
3364 case GLSL_SAMPLER_DIM_CUBE:
3365 return 3;
3366 case GLSL_SAMPLER_DIM_RECT:
3367 case GLSL_SAMPLER_DIM_SUBPASS:
3368 return 2;
3369 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3370 return 3;
3371 default:
3372 break;
3373 }
3374 return 0;
3375 }
3376
3377
3378
3379 /* Adjust the sample index according to FMASK.
3380 *
3381 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3382 * which is the identity mapping. Each nibble says which physical sample
3383 * should be fetched to get that sample.
3384 *
3385 * For example, 0x11111100 means there are only 2 samples stored and
3386 * the second sample covers 3/4 of the pixel. When reading samples 0
3387 * and 1, return physical sample 0 (determined by the first two 0s
3388 * in FMASK), otherwise return physical sample 1.
3389 *
3390 * The sample index should be adjusted as follows:
3391 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3392 */
3393 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3394 LLVMValueRef coord_x, LLVMValueRef coord_y,
3395 LLVMValueRef coord_z,
3396 LLVMValueRef sample_index,
3397 LLVMValueRef fmask_desc_ptr)
3398 {
3399 LLVMValueRef fmask_load_address[4];
3400 LLVMValueRef res;
3401
3402 fmask_load_address[0] = coord_x;
3403 fmask_load_address[1] = coord_y;
3404 if (coord_z) {
3405 fmask_load_address[2] = coord_z;
3406 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3407 }
3408
3409 struct ac_image_args args = {0};
3410
3411 args.opcode = ac_image_load;
3412 args.da = coord_z ? true : false;
3413 args.resource = fmask_desc_ptr;
3414 args.dmask = 0xf;
3415 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3416
3417 res = ac_build_image_opcode(ctx, &args);
3418
3419 res = ac_to_integer(ctx, res);
3420 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3421 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3422
3423 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3424 res,
3425 ctx->i32_0, "");
3426
3427 LLVMValueRef sample_index4 =
3428 LLVMBuildMul(ctx->builder, sample_index, four, "");
3429 LLVMValueRef shifted_fmask =
3430 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3431 LLVMValueRef final_sample =
3432 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3433
3434 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3435 * resource descriptor is 0 (invalid),
3436 */
3437 LLVMValueRef fmask_desc =
3438 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3439 ctx->v8i32, "");
3440
3441 LLVMValueRef fmask_word1 =
3442 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3443 ctx->i32_1, "");
3444
3445 LLVMValueRef word1_is_nonzero =
3446 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3447 fmask_word1, ctx->i32_0, "");
3448
3449 /* Replace the MSAA sample index. */
3450 sample_index =
3451 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3452 final_sample, sample_index, "");
3453 return sample_index;
3454 }
3455
3456 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3457 const nir_intrinsic_instr *instr)
3458 {
3459 const struct glsl_type *type = instr->variables[0]->var->type;
3460 if(instr->variables[0]->deref.child)
3461 type = instr->variables[0]->deref.child->type;
3462
3463 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3464 LLVMValueRef coords[4];
3465 LLVMValueRef masks[] = {
3466 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3467 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3468 };
3469 LLVMValueRef res;
3470 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3471
3472 int count;
3473 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3474 bool is_array = glsl_sampler_type_is_array(type);
3475 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3476 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3477 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3478 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3479 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3480 count = image_type_to_components_count(dim, is_array);
3481
3482 if (is_ms) {
3483 LLVMValueRef fmask_load_address[3];
3484 int chan;
3485
3486 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3487 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3488 if (is_array)
3489 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3490 else
3491 fmask_load_address[2] = NULL;
3492 if (add_frag_pos) {
3493 for (chan = 0; chan < 2; ++chan)
3494 fmask_load_address[chan] =
3495 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3496 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3497 ctx->ac.i32, ""), "");
3498 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3499 }
3500 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3501 fmask_load_address[0],
3502 fmask_load_address[1],
3503 fmask_load_address[2],
3504 sample_index,
3505 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3506 }
3507 if (count == 1 && !gfx9_1d) {
3508 if (instr->src[0].ssa->num_components)
3509 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3510 else
3511 res = src0;
3512 } else {
3513 int chan;
3514 if (is_ms)
3515 count--;
3516 for (chan = 0; chan < count; ++chan) {
3517 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3518 }
3519 if (add_frag_pos) {
3520 for (chan = 0; chan < 2; ++chan)
3521 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3522 ctx->ac.i32, ""), "");
3523 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3524 count++;
3525 }
3526
3527 if (gfx9_1d) {
3528 if (is_array) {
3529 coords[2] = coords[1];
3530 coords[1] = ctx->ac.i32_0;
3531 } else
3532 coords[1] = ctx->ac.i32_0;
3533 count++;
3534 }
3535
3536 if (is_ms) {
3537 coords[count] = sample_index;
3538 count++;
3539 }
3540
3541 if (count == 3) {
3542 coords[3] = LLVMGetUndef(ctx->ac.i32);
3543 count = 4;
3544 }
3545 res = ac_build_gather_values(&ctx->ac, coords, count);
3546 }
3547 return res;
3548 }
3549
3550 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3551 const nir_intrinsic_instr *instr)
3552 {
3553 LLVMValueRef params[7];
3554 LLVMValueRef res;
3555 char intrinsic_name[64];
3556 const nir_variable *var = instr->variables[0]->var;
3557 const struct glsl_type *type = var->type;
3558
3559 if(instr->variables[0]->deref.child)
3560 type = instr->variables[0]->deref.child->type;
3561
3562 type = glsl_without_array(type);
3563 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3564 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3565 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3566 ctx->ac.i32_0, ""); /* vindex */
3567 params[2] = ctx->ac.i32_0; /* voffset */
3568 params[3] = ctx->ac.i1false; /* glc */
3569 params[4] = ctx->ac.i1false; /* slc */
3570 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3571 params, 5, 0);
3572
3573 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3574 res = ac_to_integer(&ctx->ac, res);
3575 } else {
3576 bool is_da = glsl_sampler_type_is_array(type) ||
3577 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3578 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3579 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3580 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3581 LLVMValueRef glc = ctx->ac.i1false;
3582 LLVMValueRef slc = ctx->ac.i1false;
3583
3584 params[0] = get_image_coords(ctx, instr);
3585 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3586 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3587 if (HAVE_LLVM <= 0x0309) {
3588 params[3] = ctx->ac.i1false; /* r128 */
3589 params[4] = da;
3590 params[5] = glc;
3591 params[6] = slc;
3592 } else {
3593 LLVMValueRef lwe = ctx->ac.i1false;
3594 params[3] = glc;
3595 params[4] = slc;
3596 params[5] = lwe;
3597 params[6] = da;
3598 }
3599
3600 ac_get_image_intr_name("llvm.amdgcn.image.load",
3601 ctx->ac.v4f32, /* vdata */
3602 LLVMTypeOf(params[0]), /* coords */
3603 LLVMTypeOf(params[1]), /* rsrc */
3604 intrinsic_name, sizeof(intrinsic_name));
3605
3606 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3607 params, 7, AC_FUNC_ATTR_READONLY);
3608 }
3609 return ac_to_integer(&ctx->ac, res);
3610 }
3611
3612 static void visit_image_store(struct ac_nir_context *ctx,
3613 nir_intrinsic_instr *instr)
3614 {
3615 LLVMValueRef params[8];
3616 char intrinsic_name[64];
3617 const nir_variable *var = instr->variables[0]->var;
3618 const struct glsl_type *type = glsl_without_array(var->type);
3619 LLVMValueRef glc = ctx->ac.i1false;
3620 bool force_glc = ctx->ac.chip_class == SI;
3621 if (force_glc)
3622 glc = ctx->ac.i1true;
3623
3624 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3625 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3626 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3627 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3628 ctx->ac.i32_0, ""); /* vindex */
3629 params[3] = ctx->ac.i32_0; /* voffset */
3630 params[4] = glc; /* glc */
3631 params[5] = ctx->ac.i1false; /* slc */
3632 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3633 params, 6, 0);
3634 } else {
3635 bool is_da = glsl_sampler_type_is_array(type) ||
3636 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3637 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3638 LLVMValueRef slc = ctx->ac.i1false;
3639
3640 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3641 params[1] = get_image_coords(ctx, instr); /* coords */
3642 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3643 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3644 if (HAVE_LLVM <= 0x0309) {
3645 params[4] = ctx->ac.i1false; /* r128 */
3646 params[5] = da;
3647 params[6] = glc;
3648 params[7] = slc;
3649 } else {
3650 LLVMValueRef lwe = ctx->ac.i1false;
3651 params[4] = glc;
3652 params[5] = slc;
3653 params[6] = lwe;
3654 params[7] = da;
3655 }
3656
3657 ac_get_image_intr_name("llvm.amdgcn.image.store",
3658 LLVMTypeOf(params[0]), /* vdata */
3659 LLVMTypeOf(params[1]), /* coords */
3660 LLVMTypeOf(params[2]), /* rsrc */
3661 intrinsic_name, sizeof(intrinsic_name));
3662
3663 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3664 params, 8, 0);
3665 }
3666
3667 }
3668
3669 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3670 const nir_intrinsic_instr *instr)
3671 {
3672 LLVMValueRef params[7];
3673 int param_count = 0;
3674 const nir_variable *var = instr->variables[0]->var;
3675
3676 const char *atomic_name;
3677 char intrinsic_name[41];
3678 const struct glsl_type *type = glsl_without_array(var->type);
3679 MAYBE_UNUSED int length;
3680
3681 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3682
3683 switch (instr->intrinsic) {
3684 case nir_intrinsic_image_atomic_add:
3685 atomic_name = "add";
3686 break;
3687 case nir_intrinsic_image_atomic_min:
3688 atomic_name = is_unsigned ? "umin" : "smin";
3689 break;
3690 case nir_intrinsic_image_atomic_max:
3691 atomic_name = is_unsigned ? "umax" : "smax";
3692 break;
3693 case nir_intrinsic_image_atomic_and:
3694 atomic_name = "and";
3695 break;
3696 case nir_intrinsic_image_atomic_or:
3697 atomic_name = "or";
3698 break;
3699 case nir_intrinsic_image_atomic_xor:
3700 atomic_name = "xor";
3701 break;
3702 case nir_intrinsic_image_atomic_exchange:
3703 atomic_name = "swap";
3704 break;
3705 case nir_intrinsic_image_atomic_comp_swap:
3706 atomic_name = "cmpswap";
3707 break;
3708 default:
3709 abort();
3710 }
3711
3712 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3713 params[param_count++] = get_src(ctx, instr->src[3]);
3714 params[param_count++] = get_src(ctx, instr->src[2]);
3715
3716 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3717 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3718 NULL, true, true);
3719 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3720 ctx->ac.i32_0, ""); /* vindex */
3721 params[param_count++] = ctx->ac.i32_0; /* voffset */
3722 params[param_count++] = ctx->ac.i1false; /* slc */
3723
3724 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3725 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3726 } else {
3727 char coords_type[8];
3728
3729 bool da = glsl_sampler_type_is_array(type) ||
3730 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3731
3732 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3733 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3734 NULL, true, true);
3735 params[param_count++] = ctx->ac.i1false; /* r128 */
3736 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3737 params[param_count++] = ctx->ac.i1false; /* slc */
3738
3739 build_int_type_name(LLVMTypeOf(coords),
3740 coords_type, sizeof(coords_type));
3741
3742 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3743 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3744 }
3745
3746 assert(length < sizeof(intrinsic_name));
3747 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3748 }
3749
3750 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3751 const nir_intrinsic_instr *instr)
3752 {
3753 LLVMValueRef res;
3754 const nir_variable *var = instr->variables[0]->var;
3755 const struct glsl_type *type = instr->variables[0]->var->type;
3756 bool da = glsl_sampler_type_is_array(var->type) ||
3757 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3758 if(instr->variables[0]->deref.child)
3759 type = instr->variables[0]->deref.child->type;
3760
3761 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3762 return get_buffer_size(ctx,
3763 get_sampler_desc(ctx, instr->variables[0],
3764 AC_DESC_BUFFER, NULL, true, false), true);
3765
3766 struct ac_image_args args = { 0 };
3767
3768 args.da = da;
3769 args.dmask = 0xf;
3770 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3771 args.opcode = ac_image_get_resinfo;
3772 args.addr = ctx->ac.i32_0;
3773
3774 res = ac_build_image_opcode(&ctx->ac, &args);
3775
3776 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3777
3778 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3779 glsl_sampler_type_is_array(type)) {
3780 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3781 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3782 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3783 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3784 }
3785 if (ctx->ac.chip_class >= GFX9 &&
3786 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3787 glsl_sampler_type_is_array(type)) {
3788 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3789 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3790 ctx->ac.i32_1, "");
3791
3792 }
3793 return res;
3794 }
3795
3796 #define NOOP_WAITCNT 0xf7f
3797 #define LGKM_CNT 0x07f
3798 #define VM_CNT 0xf70
3799
3800 static void emit_membar(struct nir_to_llvm_context *ctx,
3801 const nir_intrinsic_instr *instr)
3802 {
3803 unsigned waitcnt = NOOP_WAITCNT;
3804
3805 switch (instr->intrinsic) {
3806 case nir_intrinsic_memory_barrier:
3807 case nir_intrinsic_group_memory_barrier:
3808 waitcnt &= VM_CNT & LGKM_CNT;
3809 break;
3810 case nir_intrinsic_memory_barrier_atomic_counter:
3811 case nir_intrinsic_memory_barrier_buffer:
3812 case nir_intrinsic_memory_barrier_image:
3813 waitcnt &= VM_CNT;
3814 break;
3815 case nir_intrinsic_memory_barrier_shared:
3816 waitcnt &= LGKM_CNT;
3817 break;
3818 default:
3819 break;
3820 }
3821 if (waitcnt != NOOP_WAITCNT)
3822 ac_build_waitcnt(&ctx->ac, waitcnt);
3823 }
3824
3825 static void emit_barrier(struct nir_to_llvm_context *ctx)
3826 {
3827 /* SI only (thanks to a hw bug workaround):
3828 * The real barrier instruction isn’t needed, because an entire patch
3829 * always fits into a single wave.
3830 */
3831 if (ctx->options->chip_class == SI &&
3832 ctx->stage == MESA_SHADER_TESS_CTRL) {
3833 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
3834 return;
3835 }
3836 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3837 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3838 }
3839
3840 static void emit_discard_if(struct ac_nir_context *ctx,
3841 const nir_intrinsic_instr *instr)
3842 {
3843 LLVMValueRef cond;
3844
3845 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3846 get_src(ctx, instr->src[0]),
3847 ctx->ac.i32_0, "");
3848 ac_build_kill_if_false(&ctx->ac, cond);
3849 }
3850
3851 static LLVMValueRef
3852 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3853 {
3854 LLVMValueRef result;
3855 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3856 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3857 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3858
3859 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3860 }
3861
3862 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3863 const nir_intrinsic_instr *instr)
3864 {
3865 LLVMValueRef ptr, result;
3866 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3867 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3868
3869 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3870 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3871 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3872 ptr, src, src1,
3873 LLVMAtomicOrderingSequentiallyConsistent,
3874 LLVMAtomicOrderingSequentiallyConsistent,
3875 false);
3876 } else {
3877 LLVMAtomicRMWBinOp op;
3878 switch (instr->intrinsic) {
3879 case nir_intrinsic_var_atomic_add:
3880 op = LLVMAtomicRMWBinOpAdd;
3881 break;
3882 case nir_intrinsic_var_atomic_umin:
3883 op = LLVMAtomicRMWBinOpUMin;
3884 break;
3885 case nir_intrinsic_var_atomic_umax:
3886 op = LLVMAtomicRMWBinOpUMax;
3887 break;
3888 case nir_intrinsic_var_atomic_imin:
3889 op = LLVMAtomicRMWBinOpMin;
3890 break;
3891 case nir_intrinsic_var_atomic_imax:
3892 op = LLVMAtomicRMWBinOpMax;
3893 break;
3894 case nir_intrinsic_var_atomic_and:
3895 op = LLVMAtomicRMWBinOpAnd;
3896 break;
3897 case nir_intrinsic_var_atomic_or:
3898 op = LLVMAtomicRMWBinOpOr;
3899 break;
3900 case nir_intrinsic_var_atomic_xor:
3901 op = LLVMAtomicRMWBinOpXor;
3902 break;
3903 case nir_intrinsic_var_atomic_exchange:
3904 op = LLVMAtomicRMWBinOpXchg;
3905 break;
3906 default:
3907 return NULL;
3908 }
3909
3910 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3911 LLVMAtomicOrderingSequentiallyConsistent,
3912 false);
3913 }
3914 return result;
3915 }
3916
3917 #define INTERP_CENTER 0
3918 #define INTERP_CENTROID 1
3919 #define INTERP_SAMPLE 2
3920
3921 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3922 enum glsl_interp_mode interp, unsigned location)
3923 {
3924 switch (interp) {
3925 case INTERP_MODE_FLAT:
3926 default:
3927 return NULL;
3928 case INTERP_MODE_SMOOTH:
3929 case INTERP_MODE_NONE:
3930 if (location == INTERP_CENTER)
3931 return ctx->persp_center;
3932 else if (location == INTERP_CENTROID)
3933 return ctx->persp_centroid;
3934 else if (location == INTERP_SAMPLE)
3935 return ctx->persp_sample;
3936 break;
3937 case INTERP_MODE_NOPERSPECTIVE:
3938 if (location == INTERP_CENTER)
3939 return ctx->linear_center;
3940 else if (location == INTERP_CENTROID)
3941 return ctx->linear_centroid;
3942 else if (location == INTERP_SAMPLE)
3943 return ctx->linear_sample;
3944 break;
3945 }
3946 return NULL;
3947 }
3948
3949 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3950 LLVMValueRef sample_id)
3951 {
3952 LLVMValueRef result;
3953 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3954
3955 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3956 const_array(ctx->ac.v2f32, 64), "");
3957
3958 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3959 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3960
3961 return result;
3962 }
3963
3964 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3965 {
3966 LLVMValueRef values[2];
3967
3968 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3969 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3970 return ac_build_gather_values(&ctx->ac, values, 2);
3971 }
3972
3973 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3974 const nir_intrinsic_instr *instr)
3975 {
3976 LLVMValueRef result[4];
3977 LLVMValueRef interp_param, attr_number;
3978 unsigned location;
3979 unsigned chan;
3980 LLVMValueRef src_c0 = NULL;
3981 LLVMValueRef src_c1 = NULL;
3982 LLVMValueRef src0 = NULL;
3983 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3984 switch (instr->intrinsic) {
3985 case nir_intrinsic_interp_var_at_centroid:
3986 location = INTERP_CENTROID;
3987 break;
3988 case nir_intrinsic_interp_var_at_sample:
3989 case nir_intrinsic_interp_var_at_offset:
3990 location = INTERP_CENTER;
3991 src0 = get_src(ctx->nir, instr->src[0]);
3992 break;
3993 default:
3994 break;
3995 }
3996
3997 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3998 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3999 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
4000 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4001 LLVMValueRef sample_position;
4002 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4003
4004 /* fetch sample ID */
4005 sample_position = load_sample_position(ctx, src0);
4006
4007 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4008 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4009 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4010 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4011 }
4012 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4013 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4014
4015 if (location == INTERP_CENTER) {
4016 LLVMValueRef ij_out[2];
4017 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4018
4019 /*
4020 * take the I then J parameters, and the DDX/Y for it, and
4021 * calculate the IJ inputs for the interpolator.
4022 * temp1 = ddx * offset/sample.x + I;
4023 * interp_param.I = ddy * offset/sample.y + temp1;
4024 * temp1 = ddx * offset/sample.x + J;
4025 * interp_param.J = ddy * offset/sample.y + temp1;
4026 */
4027 for (unsigned i = 0; i < 2; i++) {
4028 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4029 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4030 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4031 ddxy_out, ix_ll, "");
4032 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4033 ddxy_out, iy_ll, "");
4034 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4035 interp_param, ix_ll, "");
4036 LLVMValueRef temp1, temp2;
4037
4038 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4039 ctx->ac.f32, "");
4040
4041 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4042 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4043
4044 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4045 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4046
4047 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4048 temp2, ctx->ac.i32, "");
4049 }
4050 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4051
4052 }
4053
4054 for (chan = 0; chan < 4; chan++) {
4055 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4056
4057 if (interp_param) {
4058 interp_param = LLVMBuildBitCast(ctx->builder,
4059 interp_param, ctx->ac.v2f32, "");
4060 LLVMValueRef i = LLVMBuildExtractElement(
4061 ctx->builder, interp_param, ctx->ac.i32_0, "");
4062 LLVMValueRef j = LLVMBuildExtractElement(
4063 ctx->builder, interp_param, ctx->ac.i32_1, "");
4064
4065 result[chan] = ac_build_fs_interp(&ctx->ac,
4066 llvm_chan, attr_number,
4067 ctx->prim_mask, i, j);
4068 } else {
4069 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4070 LLVMConstInt(ctx->ac.i32, 2, false),
4071 llvm_chan, attr_number,
4072 ctx->prim_mask);
4073 }
4074 }
4075 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4076 instr->variables[0]->var->data.location_frac);
4077 }
4078
4079 static void
4080 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4081 {
4082 LLVMValueRef gs_next_vertex;
4083 LLVMValueRef can_emit;
4084 int idx;
4085 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4086
4087 /* Write vertex attribute values to GSVS ring */
4088 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4089 ctx->gs_next_vertex,
4090 "");
4091
4092 /* If this thread has already emitted the declared maximum number of
4093 * vertices, kill it: excessive vertex emissions are not supposed to
4094 * have any effect, and GS threads have no externally observable
4095 * effects other than emitting vertices.
4096 */
4097 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4098 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4099 ac_build_kill_if_false(&ctx->ac, can_emit);
4100
4101 /* loop num outputs */
4102 idx = 0;
4103 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4104 LLVMValueRef *out_ptr = &addrs[i * 4];
4105 int length = 4;
4106 int slot = idx;
4107 int slot_inc = 1;
4108
4109 if (!(ctx->output_mask & (1ull << i)))
4110 continue;
4111
4112 if (i == VARYING_SLOT_CLIP_DIST0) {
4113 /* pack clip and cull into a single set of slots */
4114 length = ctx->num_output_clips + ctx->num_output_culls;
4115 if (length > 4)
4116 slot_inc = 2;
4117 }
4118 for (unsigned j = 0; j < length; j++) {
4119 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4120 out_ptr[j], "");
4121 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4122 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4123 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4124
4125 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4126
4127 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4128 out_val, 1,
4129 voffset, ctx->gs2vs_offset, 0,
4130 1, 1, true, true);
4131 }
4132 idx += slot_inc;
4133 }
4134
4135 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4136 ctx->ac.i32_1, "");
4137 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4138
4139 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4140 }
4141
4142 static void
4143 visit_end_primitive(struct nir_to_llvm_context *ctx,
4144 const nir_intrinsic_instr *instr)
4145 {
4146 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4147 }
4148
4149 static LLVMValueRef
4150 load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
4151 unsigned num_components)
4152 {
4153 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4154
4155 LLVMValueRef coord[4] = {
4156 ctx->tes_u,
4157 ctx->tes_v,
4158 ctx->ac.f32_0,
4159 ctx->ac.f32_0,
4160 };
4161
4162 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4163 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4164 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4165
4166 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, num_components);
4167 return LLVMBuildBitCast(ctx->builder, result, type, "");
4168 }
4169
4170 static void visit_intrinsic(struct ac_nir_context *ctx,
4171 nir_intrinsic_instr *instr)
4172 {
4173 LLVMValueRef result = NULL;
4174
4175 switch (instr->intrinsic) {
4176 case nir_intrinsic_load_work_group_id: {
4177 LLVMValueRef values[3];
4178
4179 for (int i = 0; i < 3; i++) {
4180 values[i] = ctx->nctx->workgroup_ids[i] ?
4181 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4182 }
4183
4184 result = ac_build_gather_values(&ctx->ac, values, 3);
4185 break;
4186 }
4187 case nir_intrinsic_load_base_vertex: {
4188 result = ctx->abi->base_vertex;
4189 break;
4190 }
4191 case nir_intrinsic_load_vertex_id_zero_base: {
4192 result = ctx->abi->vertex_id;
4193 break;
4194 }
4195 case nir_intrinsic_load_local_invocation_id: {
4196 result = ctx->nctx->local_invocation_ids;
4197 break;
4198 }
4199 case nir_intrinsic_load_base_instance:
4200 result = ctx->abi->start_instance;
4201 break;
4202 case nir_intrinsic_load_draw_id:
4203 result = ctx->abi->draw_id;
4204 break;
4205 case nir_intrinsic_load_view_index:
4206 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4207 break;
4208 case nir_intrinsic_load_invocation_id:
4209 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4210 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4211 else
4212 result = ctx->abi->gs_invocation_id;
4213 break;
4214 case nir_intrinsic_load_primitive_id:
4215 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4216 result = ctx->abi->gs_prim_id;
4217 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4218 result = ctx->abi->tcs_patch_id;
4219 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4220 result = ctx->abi->tes_patch_id;
4221 } else
4222 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4223 break;
4224 case nir_intrinsic_load_sample_id:
4225 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4226 break;
4227 case nir_intrinsic_load_sample_pos:
4228 result = load_sample_pos(ctx);
4229 break;
4230 case nir_intrinsic_load_sample_mask_in:
4231 result = ctx->abi->sample_coverage;
4232 break;
4233 case nir_intrinsic_load_frag_coord: {
4234 LLVMValueRef values[4] = {
4235 ctx->abi->frag_pos[0],
4236 ctx->abi->frag_pos[1],
4237 ctx->abi->frag_pos[2],
4238 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4239 };
4240 result = ac_build_gather_values(&ctx->ac, values, 4);
4241 break;
4242 }
4243 case nir_intrinsic_load_front_face:
4244 result = ctx->abi->front_face;
4245 break;
4246 case nir_intrinsic_load_instance_id:
4247 result = ctx->abi->instance_id;
4248 break;
4249 case nir_intrinsic_load_num_work_groups:
4250 result = ctx->nctx->num_work_groups;
4251 break;
4252 case nir_intrinsic_load_local_invocation_index:
4253 result = visit_load_local_invocation_index(ctx->nctx);
4254 break;
4255 case nir_intrinsic_load_push_constant:
4256 result = visit_load_push_constant(ctx->nctx, instr);
4257 break;
4258 case nir_intrinsic_vulkan_resource_index:
4259 result = visit_vulkan_resource_index(ctx->nctx, instr);
4260 break;
4261 case nir_intrinsic_vulkan_resource_reindex:
4262 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4263 break;
4264 case nir_intrinsic_store_ssbo:
4265 visit_store_ssbo(ctx, instr);
4266 break;
4267 case nir_intrinsic_load_ssbo:
4268 result = visit_load_buffer(ctx, instr);
4269 break;
4270 case nir_intrinsic_ssbo_atomic_add:
4271 case nir_intrinsic_ssbo_atomic_imin:
4272 case nir_intrinsic_ssbo_atomic_umin:
4273 case nir_intrinsic_ssbo_atomic_imax:
4274 case nir_intrinsic_ssbo_atomic_umax:
4275 case nir_intrinsic_ssbo_atomic_and:
4276 case nir_intrinsic_ssbo_atomic_or:
4277 case nir_intrinsic_ssbo_atomic_xor:
4278 case nir_intrinsic_ssbo_atomic_exchange:
4279 case nir_intrinsic_ssbo_atomic_comp_swap:
4280 result = visit_atomic_ssbo(ctx, instr);
4281 break;
4282 case nir_intrinsic_load_ubo:
4283 result = visit_load_ubo_buffer(ctx, instr);
4284 break;
4285 case nir_intrinsic_get_buffer_size:
4286 result = visit_get_buffer_size(ctx, instr);
4287 break;
4288 case nir_intrinsic_load_var:
4289 result = visit_load_var(ctx, instr);
4290 break;
4291 case nir_intrinsic_store_var:
4292 visit_store_var(ctx, instr);
4293 break;
4294 case nir_intrinsic_image_load:
4295 result = visit_image_load(ctx, instr);
4296 break;
4297 case nir_intrinsic_image_store:
4298 visit_image_store(ctx, instr);
4299 break;
4300 case nir_intrinsic_image_atomic_add:
4301 case nir_intrinsic_image_atomic_min:
4302 case nir_intrinsic_image_atomic_max:
4303 case nir_intrinsic_image_atomic_and:
4304 case nir_intrinsic_image_atomic_or:
4305 case nir_intrinsic_image_atomic_xor:
4306 case nir_intrinsic_image_atomic_exchange:
4307 case nir_intrinsic_image_atomic_comp_swap:
4308 result = visit_image_atomic(ctx, instr);
4309 break;
4310 case nir_intrinsic_image_size:
4311 result = visit_image_size(ctx, instr);
4312 break;
4313 case nir_intrinsic_discard:
4314 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4315 LLVMVoidTypeInContext(ctx->ac.context),
4316 NULL, 0, AC_FUNC_ATTR_LEGACY);
4317 break;
4318 case nir_intrinsic_discard_if:
4319 emit_discard_if(ctx, instr);
4320 break;
4321 case nir_intrinsic_memory_barrier:
4322 case nir_intrinsic_group_memory_barrier:
4323 case nir_intrinsic_memory_barrier_atomic_counter:
4324 case nir_intrinsic_memory_barrier_buffer:
4325 case nir_intrinsic_memory_barrier_image:
4326 case nir_intrinsic_memory_barrier_shared:
4327 emit_membar(ctx->nctx, instr);
4328 break;
4329 case nir_intrinsic_barrier:
4330 emit_barrier(ctx->nctx);
4331 break;
4332 case nir_intrinsic_var_atomic_add:
4333 case nir_intrinsic_var_atomic_imin:
4334 case nir_intrinsic_var_atomic_umin:
4335 case nir_intrinsic_var_atomic_imax:
4336 case nir_intrinsic_var_atomic_umax:
4337 case nir_intrinsic_var_atomic_and:
4338 case nir_intrinsic_var_atomic_or:
4339 case nir_intrinsic_var_atomic_xor:
4340 case nir_intrinsic_var_atomic_exchange:
4341 case nir_intrinsic_var_atomic_comp_swap:
4342 result = visit_var_atomic(ctx->nctx, instr);
4343 break;
4344 case nir_intrinsic_interp_var_at_centroid:
4345 case nir_intrinsic_interp_var_at_sample:
4346 case nir_intrinsic_interp_var_at_offset:
4347 result = visit_interp(ctx->nctx, instr);
4348 break;
4349 case nir_intrinsic_emit_vertex:
4350 assert(instr->const_index[0] == 0);
4351 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4352 break;
4353 case nir_intrinsic_end_primitive:
4354 visit_end_primitive(ctx->nctx, instr);
4355 break;
4356 case nir_intrinsic_load_tess_coord: {
4357 LLVMTypeRef type = ctx->nctx ?
4358 get_def_type(ctx->nctx->nir, &instr->dest.ssa) :
4359 NULL;
4360 result = ctx->abi->load_tess_coord(ctx->abi, type, instr->num_components);
4361 break;
4362 }
4363 case nir_intrinsic_load_patch_vertices_in:
4364 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4365 break;
4366 default:
4367 fprintf(stderr, "Unknown intrinsic: ");
4368 nir_print_instr(&instr->instr, stderr);
4369 fprintf(stderr, "\n");
4370 break;
4371 }
4372 if (result) {
4373 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4374 }
4375 }
4376
4377 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4378 LLVMValueRef buffer_ptr, bool write)
4379 {
4380 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4381
4382 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4383 ctx->shader_info->fs.writes_memory = true;
4384
4385 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4386 }
4387
4388 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4389 {
4390 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4391
4392 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4393 }
4394
4395 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4396 unsigned descriptor_set,
4397 unsigned base_index,
4398 unsigned constant_index,
4399 LLVMValueRef index,
4400 enum ac_descriptor_type desc_type,
4401 bool image, bool write)
4402 {
4403 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4404 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4405 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4406 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4407 unsigned offset = binding->offset;
4408 unsigned stride = binding->size;
4409 unsigned type_size;
4410 LLVMBuilderRef builder = ctx->builder;
4411 LLVMTypeRef type;
4412
4413 assert(base_index < layout->binding_count);
4414
4415 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4416 ctx->shader_info->fs.writes_memory = true;
4417
4418 switch (desc_type) {
4419 case AC_DESC_IMAGE:
4420 type = ctx->ac.v8i32;
4421 type_size = 32;
4422 break;
4423 case AC_DESC_FMASK:
4424 type = ctx->ac.v8i32;
4425 offset += 32;
4426 type_size = 32;
4427 break;
4428 case AC_DESC_SAMPLER:
4429 type = ctx->ac.v4i32;
4430 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4431 offset += 64;
4432
4433 type_size = 16;
4434 break;
4435 case AC_DESC_BUFFER:
4436 type = ctx->ac.v4i32;
4437 type_size = 16;
4438 break;
4439 default:
4440 unreachable("invalid desc_type\n");
4441 }
4442
4443 offset += constant_index * stride;
4444
4445 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4446 (!index || binding->immutable_samplers_equal)) {
4447 if (binding->immutable_samplers_equal)
4448 constant_index = 0;
4449
4450 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4451
4452 LLVMValueRef constants[] = {
4453 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4454 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4455 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4456 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4457 };
4458 return ac_build_gather_values(&ctx->ac, constants, 4);
4459 }
4460
4461 assert(stride % type_size == 0);
4462
4463 if (!index)
4464 index = ctx->ac.i32_0;
4465
4466 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4467
4468 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4469 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4470
4471 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4472 }
4473
4474 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4475 const nir_deref_var *deref,
4476 enum ac_descriptor_type desc_type,
4477 const nir_tex_instr *tex_instr,
4478 bool image, bool write)
4479 {
4480 LLVMValueRef index = NULL;
4481 unsigned constant_index = 0;
4482 unsigned descriptor_set;
4483 unsigned base_index;
4484
4485 if (!deref) {
4486 assert(tex_instr && !image);
4487 descriptor_set = 0;
4488 base_index = tex_instr->sampler_index;
4489 } else {
4490 const nir_deref *tail = &deref->deref;
4491 while (tail->child) {
4492 const nir_deref_array *child = nir_deref_as_array(tail->child);
4493 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4494
4495 if (!array_size)
4496 array_size = 1;
4497
4498 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4499
4500 if (child->deref_array_type == nir_deref_array_type_indirect) {
4501 LLVMValueRef indirect = get_src(ctx, child->indirect);
4502
4503 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4504 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4505
4506 if (!index)
4507 index = indirect;
4508 else
4509 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4510 }
4511
4512 constant_index += child->base_offset * array_size;
4513
4514 tail = &child->deref;
4515 }
4516 descriptor_set = deref->var->data.descriptor_set;
4517 base_index = deref->var->data.binding;
4518 }
4519
4520 return ctx->abi->load_sampler_desc(ctx->abi,
4521 descriptor_set,
4522 base_index,
4523 constant_index, index,
4524 desc_type, image, write);
4525 }
4526
4527 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4528 struct ac_image_args *args,
4529 const nir_tex_instr *instr,
4530 nir_texop op,
4531 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4532 LLVMValueRef *param, unsigned count,
4533 unsigned dmask)
4534 {
4535 unsigned is_rect = 0;
4536 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4537
4538 if (op == nir_texop_lod)
4539 da = false;
4540 /* Pad to power of two vector */
4541 while (count < util_next_power_of_two(count))
4542 param[count++] = LLVMGetUndef(ctx->i32);
4543
4544 if (count > 1)
4545 args->addr = ac_build_gather_values(ctx, param, count);
4546 else
4547 args->addr = param[0];
4548
4549 args->resource = res_ptr;
4550 args->sampler = samp_ptr;
4551
4552 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4553 args->addr = param[0];
4554 return;
4555 }
4556
4557 args->dmask = dmask;
4558 args->unorm = is_rect;
4559 args->da = da;
4560 }
4561
4562 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4563 *
4564 * SI-CI:
4565 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4566 * filtering manually. The driver sets img7 to a mask clearing
4567 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4568 * s_and_b32 samp0, samp0, img7
4569 *
4570 * VI:
4571 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4572 */
4573 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4574 LLVMValueRef res, LLVMValueRef samp)
4575 {
4576 LLVMBuilderRef builder = ctx->ac.builder;
4577 LLVMValueRef img7, samp0;
4578
4579 if (ctx->ac.chip_class >= VI)
4580 return samp;
4581
4582 img7 = LLVMBuildExtractElement(builder, res,
4583 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4584 samp0 = LLVMBuildExtractElement(builder, samp,
4585 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4586 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4587 return LLVMBuildInsertElement(builder, samp, samp0,
4588 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4589 }
4590
4591 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4592 nir_tex_instr *instr,
4593 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4594 LLVMValueRef *fmask_ptr)
4595 {
4596 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4597 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4598 else
4599 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4600 if (samp_ptr) {
4601 if (instr->sampler)
4602 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4603 else
4604 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4605 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4606 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4607 }
4608 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4609 instr->op == nir_texop_samples_identical))
4610 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4611 }
4612
4613 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4614 LLVMValueRef coord)
4615 {
4616 coord = ac_to_float(ctx, coord);
4617 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4618 coord = ac_to_integer(ctx, coord);
4619 return coord;
4620 }
4621
4622 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4623 {
4624 LLVMValueRef result = NULL;
4625 struct ac_image_args args = { 0 };
4626 unsigned dmask = 0xf;
4627 LLVMValueRef address[16];
4628 LLVMValueRef coords[5];
4629 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4630 LLVMValueRef bias = NULL, offsets = NULL;
4631 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4632 LLVMValueRef ddx = NULL, ddy = NULL;
4633 LLVMValueRef derivs[6];
4634 unsigned chan, count = 0;
4635 unsigned const_src = 0, num_deriv_comp = 0;
4636 bool lod_is_zero = false;
4637
4638 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4639
4640 for (unsigned i = 0; i < instr->num_srcs; i++) {
4641 switch (instr->src[i].src_type) {
4642 case nir_tex_src_coord:
4643 coord = get_src(ctx, instr->src[i].src);
4644 break;
4645 case nir_tex_src_projector:
4646 break;
4647 case nir_tex_src_comparator:
4648 comparator = get_src(ctx, instr->src[i].src);
4649 break;
4650 case nir_tex_src_offset:
4651 offsets = get_src(ctx, instr->src[i].src);
4652 const_src = i;
4653 break;
4654 case nir_tex_src_bias:
4655 bias = get_src(ctx, instr->src[i].src);
4656 break;
4657 case nir_tex_src_lod: {
4658 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4659
4660 if (val && val->i32[0] == 0)
4661 lod_is_zero = true;
4662 lod = get_src(ctx, instr->src[i].src);
4663 break;
4664 }
4665 case nir_tex_src_ms_index:
4666 sample_index = get_src(ctx, instr->src[i].src);
4667 break;
4668 case nir_tex_src_ms_mcs:
4669 break;
4670 case nir_tex_src_ddx:
4671 ddx = get_src(ctx, instr->src[i].src);
4672 num_deriv_comp = instr->src[i].src.ssa->num_components;
4673 break;
4674 case nir_tex_src_ddy:
4675 ddy = get_src(ctx, instr->src[i].src);
4676 break;
4677 case nir_tex_src_texture_offset:
4678 case nir_tex_src_sampler_offset:
4679 case nir_tex_src_plane:
4680 default:
4681 break;
4682 }
4683 }
4684
4685 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4686 result = get_buffer_size(ctx, res_ptr, true);
4687 goto write_result;
4688 }
4689
4690 if (instr->op == nir_texop_texture_samples) {
4691 LLVMValueRef res, samples, is_msaa;
4692 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4693 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4694 LLVMConstInt(ctx->ac.i32, 3, false), "");
4695 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4696 LLVMConstInt(ctx->ac.i32, 28, false), "");
4697 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4698 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4699 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4700 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4701
4702 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4703 LLVMConstInt(ctx->ac.i32, 16, false), "");
4704 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4705 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4706 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4707 samples, "");
4708 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4709 ctx->ac.i32_1, "");
4710 result = samples;
4711 goto write_result;
4712 }
4713
4714 if (coord)
4715 for (chan = 0; chan < instr->coord_components; chan++)
4716 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4717
4718 if (offsets && instr->op != nir_texop_txf) {
4719 LLVMValueRef offset[3], pack;
4720 for (chan = 0; chan < 3; ++chan)
4721 offset[chan] = ctx->ac.i32_0;
4722
4723 args.offset = true;
4724 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4725 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4726 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4727 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4728 if (chan)
4729 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4730 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4731 }
4732 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4733 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4734 address[count++] = pack;
4735
4736 }
4737 /* pack LOD bias value */
4738 if (instr->op == nir_texop_txb && bias) {
4739 address[count++] = bias;
4740 }
4741
4742 /* Pack depth comparison value */
4743 if (instr->is_shadow && comparator) {
4744 LLVMValueRef z = ac_to_float(&ctx->ac,
4745 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4746
4747 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4748 * so the depth comparison value isn't clamped for Z16 and
4749 * Z24 anymore. Do it manually here.
4750 *
4751 * It's unnecessary if the original texture format was
4752 * Z32_FLOAT, but we don't know that here.
4753 */
4754 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4755 z = ac_build_clamp(&ctx->ac, z);
4756
4757 address[count++] = z;
4758 }
4759
4760 /* pack derivatives */
4761 if (ddx || ddy) {
4762 int num_src_deriv_channels, num_dest_deriv_channels;
4763 switch (instr->sampler_dim) {
4764 case GLSL_SAMPLER_DIM_3D:
4765 case GLSL_SAMPLER_DIM_CUBE:
4766 num_deriv_comp = 3;
4767 num_src_deriv_channels = 3;
4768 num_dest_deriv_channels = 3;
4769 break;
4770 case GLSL_SAMPLER_DIM_2D:
4771 default:
4772 num_src_deriv_channels = 2;
4773 num_dest_deriv_channels = 2;
4774 num_deriv_comp = 2;
4775 break;
4776 case GLSL_SAMPLER_DIM_1D:
4777 num_src_deriv_channels = 1;
4778 if (ctx->ac.chip_class >= GFX9) {
4779 num_dest_deriv_channels = 2;
4780 num_deriv_comp = 2;
4781 } else {
4782 num_dest_deriv_channels = 1;
4783 num_deriv_comp = 1;
4784 }
4785 break;
4786 }
4787
4788 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4789 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4790 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4791 }
4792 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4793 derivs[i] = ctx->ac.f32_0;
4794 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4795 }
4796 }
4797
4798 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4799 for (chan = 0; chan < instr->coord_components; chan++)
4800 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4801 if (instr->coord_components == 3)
4802 coords[3] = LLVMGetUndef(ctx->ac.f32);
4803 ac_prepare_cube_coords(&ctx->ac,
4804 instr->op == nir_texop_txd, instr->is_array,
4805 instr->op == nir_texop_lod, coords, derivs);
4806 if (num_deriv_comp)
4807 num_deriv_comp--;
4808 }
4809
4810 if (ddx || ddy) {
4811 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4812 address[count++] = derivs[i];
4813 }
4814
4815 /* Pack texture coordinates */
4816 if (coord) {
4817 address[count++] = coords[0];
4818 if (instr->coord_components > 1) {
4819 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4820 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4821 }
4822 address[count++] = coords[1];
4823 }
4824 if (instr->coord_components > 2) {
4825 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4826 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4827 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4828 instr->op != nir_texop_txf) {
4829 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4830 }
4831 address[count++] = coords[2];
4832 }
4833
4834 if (ctx->ac.chip_class >= GFX9) {
4835 LLVMValueRef filler;
4836 if (instr->op == nir_texop_txf)
4837 filler = ctx->ac.i32_0;
4838 else
4839 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4840
4841 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4842 /* No nir_texop_lod, because it does not take a slice
4843 * even with array textures. */
4844 if (instr->is_array && instr->op != nir_texop_lod ) {
4845 address[count] = address[count - 1];
4846 address[count - 1] = filler;
4847 count++;
4848 } else
4849 address[count++] = filler;
4850 }
4851 }
4852 }
4853
4854 /* Pack LOD */
4855 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4856 instr->op == nir_texop_txf)) {
4857 address[count++] = lod;
4858 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4859 address[count++] = sample_index;
4860 } else if(instr->op == nir_texop_txs) {
4861 count = 0;
4862 if (lod)
4863 address[count++] = lod;
4864 else
4865 address[count++] = ctx->ac.i32_0;
4866 }
4867
4868 for (chan = 0; chan < count; chan++) {
4869 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4870 address[chan], ctx->ac.i32, "");
4871 }
4872
4873 if (instr->op == nir_texop_samples_identical) {
4874 LLVMValueRef txf_address[4];
4875 struct ac_image_args txf_args = { 0 };
4876 unsigned txf_count = count;
4877 memcpy(txf_address, address, sizeof(txf_address));
4878
4879 if (!instr->is_array)
4880 txf_address[2] = ctx->ac.i32_0;
4881 txf_address[3] = ctx->ac.i32_0;
4882
4883 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4884 fmask_ptr, NULL,
4885 txf_address, txf_count, 0xf);
4886
4887 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4888
4889 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4890 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4891 goto write_result;
4892 }
4893
4894 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4895 instr->op != nir_texop_txs) {
4896 unsigned sample_chan = instr->is_array ? 3 : 2;
4897 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4898 address[0],
4899 address[1],
4900 instr->is_array ? address[2] : NULL,
4901 address[sample_chan],
4902 fmask_ptr);
4903 }
4904
4905 if (offsets && instr->op == nir_texop_txf) {
4906 nir_const_value *const_offset =
4907 nir_src_as_const_value(instr->src[const_src].src);
4908 int num_offsets = instr->src[const_src].src.ssa->num_components;
4909 assert(const_offset);
4910 num_offsets = MIN2(num_offsets, instr->coord_components);
4911 if (num_offsets > 2)
4912 address[2] = LLVMBuildAdd(ctx->ac.builder,
4913 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4914 if (num_offsets > 1)
4915 address[1] = LLVMBuildAdd(ctx->ac.builder,
4916 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4917 address[0] = LLVMBuildAdd(ctx->ac.builder,
4918 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4919
4920 }
4921
4922 /* TODO TG4 support */
4923 if (instr->op == nir_texop_tg4) {
4924 if (instr->is_shadow)
4925 dmask = 1;
4926 else
4927 dmask = 1 << instr->component;
4928 }
4929 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4930 res_ptr, samp_ptr, address, count, dmask);
4931
4932 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4933
4934 if (instr->op == nir_texop_query_levels)
4935 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4936 else if (instr->is_shadow && instr->is_new_style_shadow &&
4937 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4938 instr->op != nir_texop_tg4)
4939 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4940 else if (instr->op == nir_texop_txs &&
4941 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4942 instr->is_array) {
4943 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4944 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4945 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4946 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4947 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4948 } else if (ctx->ac.chip_class >= GFX9 &&
4949 instr->op == nir_texop_txs &&
4950 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4951 instr->is_array) {
4952 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4953 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4954 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4955 ctx->ac.i32_1, "");
4956 } else if (instr->dest.ssa.num_components != 4)
4957 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4958
4959 write_result:
4960 if (result) {
4961 assert(instr->dest.is_ssa);
4962 result = ac_to_integer(&ctx->ac, result);
4963 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4964 }
4965 }
4966
4967
4968 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4969 {
4970 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4971 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4972
4973 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4974 _mesa_hash_table_insert(ctx->phis, instr, result);
4975 }
4976
4977 static void visit_post_phi(struct ac_nir_context *ctx,
4978 nir_phi_instr *instr,
4979 LLVMValueRef llvm_phi)
4980 {
4981 nir_foreach_phi_src(src, instr) {
4982 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4983 LLVMValueRef llvm_src = get_src(ctx, src->src);
4984
4985 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4986 }
4987 }
4988
4989 static void phi_post_pass(struct ac_nir_context *ctx)
4990 {
4991 struct hash_entry *entry;
4992 hash_table_foreach(ctx->phis, entry) {
4993 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4994 (LLVMValueRef)entry->data);
4995 }
4996 }
4997
4998
4999 static void visit_ssa_undef(struct ac_nir_context *ctx,
5000 const nir_ssa_undef_instr *instr)
5001 {
5002 unsigned num_components = instr->def.num_components;
5003 LLVMValueRef undef;
5004
5005 if (num_components == 1)
5006 undef = LLVMGetUndef(ctx->ac.i32);
5007 else {
5008 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
5009 }
5010 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5011 }
5012
5013 static void visit_jump(struct ac_nir_context *ctx,
5014 const nir_jump_instr *instr)
5015 {
5016 switch (instr->type) {
5017 case nir_jump_break:
5018 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5019 LLVMClearInsertionPosition(ctx->ac.builder);
5020 break;
5021 case nir_jump_continue:
5022 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5023 LLVMClearInsertionPosition(ctx->ac.builder);
5024 break;
5025 default:
5026 fprintf(stderr, "Unknown NIR jump instr: ");
5027 nir_print_instr(&instr->instr, stderr);
5028 fprintf(stderr, "\n");
5029 abort();
5030 }
5031 }
5032
5033 static void visit_cf_list(struct ac_nir_context *ctx,
5034 struct exec_list *list);
5035
5036 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5037 {
5038 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5039 nir_foreach_instr(instr, block)
5040 {
5041 switch (instr->type) {
5042 case nir_instr_type_alu:
5043 visit_alu(ctx, nir_instr_as_alu(instr));
5044 break;
5045 case nir_instr_type_load_const:
5046 visit_load_const(ctx, nir_instr_as_load_const(instr));
5047 break;
5048 case nir_instr_type_intrinsic:
5049 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5050 break;
5051 case nir_instr_type_tex:
5052 visit_tex(ctx, nir_instr_as_tex(instr));
5053 break;
5054 case nir_instr_type_phi:
5055 visit_phi(ctx, nir_instr_as_phi(instr));
5056 break;
5057 case nir_instr_type_ssa_undef:
5058 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5059 break;
5060 case nir_instr_type_jump:
5061 visit_jump(ctx, nir_instr_as_jump(instr));
5062 break;
5063 default:
5064 fprintf(stderr, "Unknown NIR instr type: ");
5065 nir_print_instr(instr, stderr);
5066 fprintf(stderr, "\n");
5067 abort();
5068 }
5069 }
5070
5071 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5072 }
5073
5074 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5075 {
5076 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5077
5078 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5079 LLVMBasicBlockRef merge_block =
5080 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5081 LLVMBasicBlockRef if_block =
5082 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5083 LLVMBasicBlockRef else_block = merge_block;
5084 if (!exec_list_is_empty(&if_stmt->else_list))
5085 else_block = LLVMAppendBasicBlockInContext(
5086 ctx->ac.context, fn, "");
5087
5088 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5089 ctx->ac.i32_0, "");
5090 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5091
5092 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5093 visit_cf_list(ctx, &if_stmt->then_list);
5094 if (LLVMGetInsertBlock(ctx->ac.builder))
5095 LLVMBuildBr(ctx->ac.builder, merge_block);
5096
5097 if (!exec_list_is_empty(&if_stmt->else_list)) {
5098 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5099 visit_cf_list(ctx, &if_stmt->else_list);
5100 if (LLVMGetInsertBlock(ctx->ac.builder))
5101 LLVMBuildBr(ctx->ac.builder, merge_block);
5102 }
5103
5104 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5105 }
5106
5107 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5108 {
5109 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5110 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5111 LLVMBasicBlockRef break_parent = ctx->break_block;
5112
5113 ctx->continue_block =
5114 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5115 ctx->break_block =
5116 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5117
5118 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5119 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5120 visit_cf_list(ctx, &loop->body);
5121
5122 if (LLVMGetInsertBlock(ctx->ac.builder))
5123 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5124 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5125
5126 ctx->continue_block = continue_parent;
5127 ctx->break_block = break_parent;
5128 }
5129
5130 static void visit_cf_list(struct ac_nir_context *ctx,
5131 struct exec_list *list)
5132 {
5133 foreach_list_typed(nir_cf_node, node, node, list)
5134 {
5135 switch (node->type) {
5136 case nir_cf_node_block:
5137 visit_block(ctx, nir_cf_node_as_block(node));
5138 break;
5139
5140 case nir_cf_node_if:
5141 visit_if(ctx, nir_cf_node_as_if(node));
5142 break;
5143
5144 case nir_cf_node_loop:
5145 visit_loop(ctx, nir_cf_node_as_loop(node));
5146 break;
5147
5148 default:
5149 assert(0);
5150 }
5151 }
5152 }
5153
5154 static void
5155 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5156 struct nir_variable *variable)
5157 {
5158 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5159 LLVMValueRef t_offset;
5160 LLVMValueRef t_list;
5161 LLVMValueRef input;
5162 LLVMValueRef buffer_index;
5163 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5164 int idx = variable->data.location;
5165 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5166
5167 variable->data.driver_location = idx * 4;
5168
5169 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5170 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5171 ctx->abi.start_instance, "");
5172 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5173 ctx->shader_info->vs.vgpr_comp_cnt);
5174 } else
5175 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5176 ctx->abi.base_vertex, "");
5177
5178 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5179 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5180
5181 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5182
5183 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5184 buffer_index,
5185 ctx->ac.i32_0,
5186 true);
5187
5188 for (unsigned chan = 0; chan < 4; chan++) {
5189 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5190 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5191 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5192 input, llvm_chan, ""));
5193 }
5194 }
5195 }
5196
5197 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5198 unsigned attr,
5199 LLVMValueRef interp_param,
5200 LLVMValueRef prim_mask,
5201 LLVMValueRef result[4])
5202 {
5203 LLVMValueRef attr_number;
5204 unsigned chan;
5205 LLVMValueRef i, j;
5206 bool interp = interp_param != NULL;
5207
5208 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5209
5210 /* fs.constant returns the param from the middle vertex, so it's not
5211 * really useful for flat shading. It's meant to be used for custom
5212 * interpolation (but the intrinsic can't fetch from the other two
5213 * vertices).
5214 *
5215 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5216 * to do the right thing. The only reason we use fs.constant is that
5217 * fs.interp cannot be used on integers, because they can be equal
5218 * to NaN.
5219 */
5220 if (interp) {
5221 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5222 ctx->ac.v2f32, "");
5223
5224 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5225 ctx->ac.i32_0, "");
5226 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5227 ctx->ac.i32_1, "");
5228 }
5229
5230 for (chan = 0; chan < 4; chan++) {
5231 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5232
5233 if (interp) {
5234 result[chan] = ac_build_fs_interp(&ctx->ac,
5235 llvm_chan,
5236 attr_number,
5237 prim_mask, i, j);
5238 } else {
5239 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5240 LLVMConstInt(ctx->ac.i32, 2, false),
5241 llvm_chan,
5242 attr_number,
5243 prim_mask);
5244 }
5245 }
5246 }
5247
5248 static void
5249 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5250 struct nir_variable *variable)
5251 {
5252 int idx = variable->data.location;
5253 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5254 LLVMValueRef interp;
5255
5256 variable->data.driver_location = idx * 4;
5257 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5258
5259 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5260 unsigned interp_type;
5261 if (variable->data.sample) {
5262 interp_type = INTERP_SAMPLE;
5263 ctx->shader_info->info.ps.force_persample = true;
5264 } else if (variable->data.centroid)
5265 interp_type = INTERP_CENTROID;
5266 else
5267 interp_type = INTERP_CENTER;
5268
5269 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5270 } else
5271 interp = NULL;
5272
5273 for (unsigned i = 0; i < attrib_count; ++i)
5274 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5275
5276 }
5277
5278 static void
5279 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5280 struct nir_shader *nir) {
5281 nir_foreach_variable(variable, &nir->inputs)
5282 handle_vs_input_decl(ctx, variable);
5283 }
5284
5285 static void
5286 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5287 struct nir_shader *nir)
5288 {
5289 if (!ctx->options->key.fs.multisample)
5290 return;
5291
5292 bool uses_center = false;
5293 bool uses_centroid = false;
5294 nir_foreach_variable(variable, &nir->inputs) {
5295 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5296 variable->data.sample)
5297 continue;
5298
5299 if (variable->data.centroid)
5300 uses_centroid = true;
5301 else
5302 uses_center = true;
5303 }
5304
5305 if (uses_center && uses_centroid) {
5306 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5307 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5308 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5309 }
5310 }
5311
5312 static void
5313 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5314 struct nir_shader *nir)
5315 {
5316 prepare_interp_optimize(ctx, nir);
5317
5318 nir_foreach_variable(variable, &nir->inputs)
5319 handle_fs_input_decl(ctx, variable);
5320
5321 unsigned index = 0;
5322
5323 if (ctx->shader_info->info.ps.uses_input_attachments ||
5324 ctx->shader_info->info.needs_multiview_view_index)
5325 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5326
5327 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5328 LLVMValueRef interp_param;
5329 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5330
5331 if (!(ctx->input_mask & (1ull << i)))
5332 continue;
5333
5334 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5335 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5336 interp_param = *inputs;
5337 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5338 inputs);
5339
5340 if (!interp_param)
5341 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5342 ++index;
5343 } else if (i == VARYING_SLOT_POS) {
5344 for(int i = 0; i < 3; ++i)
5345 inputs[i] = ctx->abi.frag_pos[i];
5346
5347 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5348 ctx->abi.frag_pos[3]);
5349 }
5350 }
5351 ctx->shader_info->fs.num_interp = index;
5352 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5353 ctx->shader_info->fs.has_pcoord = true;
5354 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5355 ctx->shader_info->fs.prim_id_input = true;
5356 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5357 ctx->shader_info->fs.layer_input = true;
5358 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5359
5360 if (ctx->shader_info->info.needs_multiview_view_index)
5361 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5362 }
5363
5364 static LLVMValueRef
5365 ac_build_alloca(struct ac_llvm_context *ac,
5366 LLVMTypeRef type,
5367 const char *name)
5368 {
5369 LLVMBuilderRef builder = ac->builder;
5370 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5371 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5372 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5373 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5374 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5375 LLVMValueRef res;
5376
5377 if (first_instr) {
5378 LLVMPositionBuilderBefore(first_builder, first_instr);
5379 } else {
5380 LLVMPositionBuilderAtEnd(first_builder, first_block);
5381 }
5382
5383 res = LLVMBuildAlloca(first_builder, type, name);
5384 LLVMBuildStore(builder, LLVMConstNull(type), res);
5385
5386 LLVMDisposeBuilder(first_builder);
5387
5388 return res;
5389 }
5390
5391 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5392 LLVMTypeRef type,
5393 const char *name)
5394 {
5395 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5396 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5397 return ptr;
5398 }
5399
5400 static void
5401 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5402 struct nir_variable *variable,
5403 struct nir_shader *shader,
5404 gl_shader_stage stage)
5405 {
5406 int idx = variable->data.location + variable->data.index;
5407 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5408 uint64_t mask_attribs;
5409
5410 variable->data.driver_location = idx * 4;
5411
5412 /* tess ctrl has it's own load/store paths for outputs */
5413 if (stage == MESA_SHADER_TESS_CTRL)
5414 return;
5415
5416 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5417 if (stage == MESA_SHADER_VERTEX ||
5418 stage == MESA_SHADER_TESS_EVAL ||
5419 stage == MESA_SHADER_GEOMETRY) {
5420 if (idx == VARYING_SLOT_CLIP_DIST0) {
5421 int length = shader->info.clip_distance_array_size +
5422 shader->info.cull_distance_array_size;
5423 if (stage == MESA_SHADER_VERTEX) {
5424 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5425 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5426 }
5427 if (stage == MESA_SHADER_TESS_EVAL) {
5428 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5429 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5430 }
5431
5432 if (length > 4)
5433 attrib_count = 2;
5434 else
5435 attrib_count = 1;
5436 mask_attribs = 1ull << idx;
5437 }
5438 }
5439
5440 ctx->output_mask |= mask_attribs;
5441 }
5442
5443 static void
5444 handle_shader_output_decl(struct ac_nir_context *ctx,
5445 struct nir_shader *nir,
5446 struct nir_variable *variable)
5447 {
5448 unsigned output_loc = variable->data.driver_location / 4;
5449 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5450
5451 /* tess ctrl has it's own load/store paths for outputs */
5452 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5453 return;
5454
5455 if (ctx->stage == MESA_SHADER_VERTEX ||
5456 ctx->stage == MESA_SHADER_TESS_EVAL ||
5457 ctx->stage == MESA_SHADER_GEOMETRY) {
5458 int idx = variable->data.location + variable->data.index;
5459 if (idx == VARYING_SLOT_CLIP_DIST0) {
5460 int length = nir->info.clip_distance_array_size +
5461 nir->info.cull_distance_array_size;
5462
5463 if (length > 4)
5464 attrib_count = 2;
5465 else
5466 attrib_count = 1;
5467 }
5468 }
5469
5470 for (unsigned i = 0; i < attrib_count; ++i) {
5471 for (unsigned chan = 0; chan < 4; chan++) {
5472 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5473 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5474 }
5475 }
5476 }
5477
5478 static LLVMTypeRef
5479 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5480 enum glsl_base_type type)
5481 {
5482 switch (type) {
5483 case GLSL_TYPE_INT:
5484 case GLSL_TYPE_UINT:
5485 case GLSL_TYPE_BOOL:
5486 case GLSL_TYPE_SUBROUTINE:
5487 return ctx->ac.i32;
5488 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5489 return ctx->ac.f32;
5490 case GLSL_TYPE_INT64:
5491 case GLSL_TYPE_UINT64:
5492 return ctx->ac.i64;
5493 case GLSL_TYPE_DOUBLE:
5494 return ctx->ac.f64;
5495 default:
5496 unreachable("unknown GLSL type");
5497 }
5498 }
5499
5500 static LLVMTypeRef
5501 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5502 const struct glsl_type *type)
5503 {
5504 if (glsl_type_is_scalar(type)) {
5505 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5506 }
5507
5508 if (glsl_type_is_vector(type)) {
5509 return LLVMVectorType(
5510 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5511 glsl_get_vector_elements(type));
5512 }
5513
5514 if (glsl_type_is_matrix(type)) {
5515 return LLVMArrayType(
5516 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5517 glsl_get_matrix_columns(type));
5518 }
5519
5520 if (glsl_type_is_array(type)) {
5521 return LLVMArrayType(
5522 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5523 glsl_get_length(type));
5524 }
5525
5526 assert(glsl_type_is_struct(type));
5527
5528 LLVMTypeRef member_types[glsl_get_length(type)];
5529
5530 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5531 member_types[i] =
5532 glsl_to_llvm_type(ctx,
5533 glsl_get_struct_field(type, i));
5534 }
5535
5536 return LLVMStructTypeInContext(ctx->context, member_types,
5537 glsl_get_length(type), false);
5538 }
5539
5540 static void
5541 setup_locals(struct ac_nir_context *ctx,
5542 struct nir_function *func)
5543 {
5544 int i, j;
5545 ctx->num_locals = 0;
5546 nir_foreach_variable(variable, &func->impl->locals) {
5547 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5548 variable->data.driver_location = ctx->num_locals * 4;
5549 ctx->num_locals += attrib_count;
5550 }
5551 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5552 if (!ctx->locals)
5553 return;
5554
5555 for (i = 0; i < ctx->num_locals; i++) {
5556 for (j = 0; j < 4; j++) {
5557 ctx->locals[i * 4 + j] =
5558 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5559 }
5560 }
5561 }
5562
5563 static void
5564 setup_shared(struct ac_nir_context *ctx,
5565 struct nir_shader *nir)
5566 {
5567 nir_foreach_variable(variable, &nir->shared) {
5568 LLVMValueRef shared =
5569 LLVMAddGlobalInAddressSpace(
5570 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5571 variable->name ? variable->name : "",
5572 LOCAL_ADDR_SPACE);
5573 _mesa_hash_table_insert(ctx->vars, variable, shared);
5574 }
5575 }
5576
5577 static LLVMValueRef
5578 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5579 {
5580 v = ac_to_float(ctx, v);
5581 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5582 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5583 }
5584
5585
5586 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5587 LLVMValueRef src0, LLVMValueRef src1)
5588 {
5589 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5590 LLVMValueRef comp[2];
5591
5592 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5593 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5594 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5595 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5596 }
5597
5598 /* Initialize arguments for the shader export intrinsic */
5599 static void
5600 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5601 LLVMValueRef *values,
5602 unsigned target,
5603 struct ac_export_args *args)
5604 {
5605 /* Default is 0xf. Adjusted below depending on the format. */
5606 args->enabled_channels = 0xf;
5607
5608 /* Specify whether the EXEC mask represents the valid mask */
5609 args->valid_mask = 0;
5610
5611 /* Specify whether this is the last export */
5612 args->done = 0;
5613
5614 /* Specify the target we are exporting */
5615 args->target = target;
5616
5617 args->compr = false;
5618 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5619 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5620 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5621 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5622
5623 if (!values)
5624 return;
5625
5626 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5627 LLVMValueRef val[4];
5628 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5629 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5630 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5631 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5632
5633 switch(col_format) {
5634 case V_028714_SPI_SHADER_ZERO:
5635 args->enabled_channels = 0; /* writemask */
5636 args->target = V_008DFC_SQ_EXP_NULL;
5637 break;
5638
5639 case V_028714_SPI_SHADER_32_R:
5640 args->enabled_channels = 1;
5641 args->out[0] = values[0];
5642 break;
5643
5644 case V_028714_SPI_SHADER_32_GR:
5645 args->enabled_channels = 0x3;
5646 args->out[0] = values[0];
5647 args->out[1] = values[1];
5648 break;
5649
5650 case V_028714_SPI_SHADER_32_AR:
5651 args->enabled_channels = 0x9;
5652 args->out[0] = values[0];
5653 args->out[3] = values[3];
5654 break;
5655
5656 case V_028714_SPI_SHADER_FP16_ABGR:
5657 args->compr = 1;
5658
5659 for (unsigned chan = 0; chan < 2; chan++) {
5660 LLVMValueRef pack_args[2] = {
5661 values[2 * chan],
5662 values[2 * chan + 1]
5663 };
5664 LLVMValueRef packed;
5665
5666 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5667 args->out[chan] = packed;
5668 }
5669 break;
5670
5671 case V_028714_SPI_SHADER_UNORM16_ABGR:
5672 for (unsigned chan = 0; chan < 4; chan++) {
5673 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5674 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5675 LLVMConstReal(ctx->ac.f32, 65535), "");
5676 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5677 LLVMConstReal(ctx->ac.f32, 0.5), "");
5678 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5679 ctx->ac.i32, "");
5680 }
5681
5682 args->compr = 1;
5683 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5684 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5685 break;
5686
5687 case V_028714_SPI_SHADER_SNORM16_ABGR:
5688 for (unsigned chan = 0; chan < 4; chan++) {
5689 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5690 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5691 LLVMConstReal(ctx->ac.f32, 32767), "");
5692
5693 /* If positive, add 0.5, else add -0.5. */
5694 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5695 LLVMBuildSelect(ctx->builder,
5696 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5697 val[chan], ctx->ac.f32_0, ""),
5698 LLVMConstReal(ctx->ac.f32, 0.5),
5699 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5700 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5701 }
5702
5703 args->compr = 1;
5704 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5705 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5706 break;
5707
5708 case V_028714_SPI_SHADER_UINT16_ABGR: {
5709 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5710 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5711 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5712
5713 for (unsigned chan = 0; chan < 4; chan++) {
5714 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5715 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5716 }
5717
5718 args->compr = 1;
5719 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5720 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5721 break;
5722 }
5723
5724 case V_028714_SPI_SHADER_SINT16_ABGR: {
5725 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5726 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5727 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5728 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5729 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5730 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5731
5732 /* Clamp. */
5733 for (unsigned chan = 0; chan < 4; chan++) {
5734 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5735 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5736 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5737 }
5738
5739 args->compr = 1;
5740 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5741 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5742 break;
5743 }
5744
5745 default:
5746 case V_028714_SPI_SHADER_32_ABGR:
5747 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5748 break;
5749 }
5750 } else
5751 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5752
5753 for (unsigned i = 0; i < 4; ++i)
5754 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5755 }
5756
5757 static void
5758 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5759 bool export_prim_id,
5760 struct ac_vs_output_info *outinfo)
5761 {
5762 uint32_t param_count = 0;
5763 unsigned target;
5764 unsigned pos_idx, num_pos_exports = 0;
5765 struct ac_export_args args, pos_args[4] = {};
5766 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5767 int i;
5768
5769 if (ctx->options->key.has_multiview_view_index) {
5770 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5771 if(!*tmp_out) {
5772 for(unsigned i = 0; i < 4; ++i)
5773 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5774 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5775 }
5776
5777 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5778 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5779 }
5780
5781 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5782 sizeof(outinfo->vs_output_param_offset));
5783
5784 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5785 LLVMValueRef slots[8];
5786 unsigned j;
5787
5788 if (outinfo->cull_dist_mask)
5789 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5790
5791 i = VARYING_SLOT_CLIP_DIST0;
5792 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5793 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5794 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5795
5796 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5797 slots[i] = LLVMGetUndef(ctx->ac.f32);
5798
5799 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5800 target = V_008DFC_SQ_EXP_POS + 3;
5801 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5802 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5803 &args, sizeof(args));
5804 }
5805
5806 target = V_008DFC_SQ_EXP_POS + 2;
5807 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5808 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5809 &args, sizeof(args));
5810
5811 }
5812
5813 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5814 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5815 for (unsigned j = 0; j < 4; j++)
5816 pos_values[j] = LLVMBuildLoad(ctx->builder,
5817 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5818 }
5819 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5820
5821 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5822 outinfo->writes_pointsize = true;
5823 psize_value = LLVMBuildLoad(ctx->builder,
5824 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5825 }
5826
5827 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5828 outinfo->writes_layer = true;
5829 layer_value = LLVMBuildLoad(ctx->builder,
5830 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5831 }
5832
5833 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5834 outinfo->writes_viewport_index = true;
5835 viewport_index_value = LLVMBuildLoad(ctx->builder,
5836 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5837 }
5838
5839 if (outinfo->writes_pointsize ||
5840 outinfo->writes_layer ||
5841 outinfo->writes_viewport_index) {
5842 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5843 (outinfo->writes_layer == true ? 4 : 0));
5844 pos_args[1].valid_mask = 0;
5845 pos_args[1].done = 0;
5846 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5847 pos_args[1].compr = 0;
5848 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5849 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5850 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5851 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5852
5853 if (outinfo->writes_pointsize == true)
5854 pos_args[1].out[0] = psize_value;
5855 if (outinfo->writes_layer == true)
5856 pos_args[1].out[2] = layer_value;
5857 if (outinfo->writes_viewport_index == true) {
5858 if (ctx->options->chip_class >= GFX9) {
5859 /* GFX9 has the layer in out.z[10:0] and the viewport
5860 * index in out.z[19:16].
5861 */
5862 LLVMValueRef v = viewport_index_value;
5863 v = ac_to_integer(&ctx->ac, v);
5864 v = LLVMBuildShl(ctx->builder, v,
5865 LLVMConstInt(ctx->ac.i32, 16, false),
5866 "");
5867 v = LLVMBuildOr(ctx->builder, v,
5868 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5869
5870 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5871 pos_args[1].enabled_channels |= 1 << 2;
5872 } else {
5873 pos_args[1].out[3] = viewport_index_value;
5874 pos_args[1].enabled_channels |= 1 << 3;
5875 }
5876 }
5877 }
5878 for (i = 0; i < 4; i++) {
5879 if (pos_args[i].out[0])
5880 num_pos_exports++;
5881 }
5882
5883 pos_idx = 0;
5884 for (i = 0; i < 4; i++) {
5885 if (!pos_args[i].out[0])
5886 continue;
5887
5888 /* Specify the target we are exporting */
5889 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5890 if (pos_idx == num_pos_exports)
5891 pos_args[i].done = 1;
5892 ac_build_export(&ctx->ac, &pos_args[i]);
5893 }
5894
5895 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5896 LLVMValueRef values[4];
5897 if (!(ctx->output_mask & (1ull << i)))
5898 continue;
5899
5900 for (unsigned j = 0; j < 4; j++)
5901 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5902 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5903
5904 if (i == VARYING_SLOT_LAYER) {
5905 target = V_008DFC_SQ_EXP_PARAM + param_count;
5906 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5907 param_count++;
5908 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5909 target = V_008DFC_SQ_EXP_PARAM + param_count;
5910 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5911 param_count++;
5912 } else if (i >= VARYING_SLOT_VAR0) {
5913 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5914 target = V_008DFC_SQ_EXP_PARAM + param_count;
5915 outinfo->vs_output_param_offset[i] = param_count;
5916 param_count++;
5917 } else
5918 continue;
5919
5920 si_llvm_init_export_args(ctx, values, target, &args);
5921
5922 if (target >= V_008DFC_SQ_EXP_POS &&
5923 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5924 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5925 &args, sizeof(args));
5926 } else {
5927 ac_build_export(&ctx->ac, &args);
5928 }
5929 }
5930
5931 if (export_prim_id) {
5932 LLVMValueRef values[4];
5933 target = V_008DFC_SQ_EXP_PARAM + param_count;
5934 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5935 param_count++;
5936
5937 values[0] = ctx->vs_prim_id;
5938 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5939 ctx->shader_info->vs.vgpr_comp_cnt);
5940 for (unsigned j = 1; j < 4; j++)
5941 values[j] = ctx->ac.f32_0;
5942 si_llvm_init_export_args(ctx, values, target, &args);
5943 ac_build_export(&ctx->ac, &args);
5944 outinfo->export_prim_id = true;
5945 }
5946
5947 outinfo->pos_exports = num_pos_exports;
5948 outinfo->param_exports = param_count;
5949 }
5950
5951 static void
5952 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5953 struct ac_es_output_info *outinfo)
5954 {
5955 int j;
5956 uint64_t max_output_written = 0;
5957 LLVMValueRef lds_base = NULL;
5958
5959 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5960 int param_index;
5961 int length = 4;
5962
5963 if (!(ctx->output_mask & (1ull << i)))
5964 continue;
5965
5966 if (i == VARYING_SLOT_CLIP_DIST0)
5967 length = ctx->num_output_clips + ctx->num_output_culls;
5968
5969 param_index = shader_io_get_unique_index(i);
5970
5971 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5972 }
5973
5974 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5975
5976 if (ctx->ac.chip_class >= GFX9) {
5977 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5978 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5979 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5980 LLVMConstInt(ctx->ac.i32, 24, false),
5981 LLVMConstInt(ctx->ac.i32, 4, false), false);
5982 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5983 LLVMBuildMul(ctx->ac.builder, wave_idx,
5984 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5985 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5986 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5987 }
5988
5989 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5990 LLVMValueRef dw_addr;
5991 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5992 int param_index;
5993 int length = 4;
5994
5995 if (!(ctx->output_mask & (1ull << i)))
5996 continue;
5997
5998 if (i == VARYING_SLOT_CLIP_DIST0)
5999 length = ctx->num_output_clips + ctx->num_output_culls;
6000
6001 param_index = shader_io_get_unique_index(i);
6002
6003 if (lds_base) {
6004 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6005 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6006 "");
6007 }
6008 for (j = 0; j < length; j++) {
6009 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6010 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6011
6012 if (ctx->ac.chip_class >= GFX9) {
6013 ac_lds_store(&ctx->ac, dw_addr,
6014 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6015 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6016 } else {
6017 ac_build_buffer_store_dword(&ctx->ac,
6018 ctx->esgs_ring,
6019 out_val, 1,
6020 NULL, ctx->es2gs_offset,
6021 (4 * param_index + j) * 4,
6022 1, 1, true, true);
6023 }
6024 }
6025 }
6026 }
6027
6028 static void
6029 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6030 {
6031 LLVMValueRef vertex_id = ctx->rel_auto_id;
6032 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6033 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6034 vertex_dw_stride, "");
6035
6036 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6037 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6038 int length = 4;
6039
6040 if (!(ctx->output_mask & (1ull << i)))
6041 continue;
6042
6043 if (i == VARYING_SLOT_CLIP_DIST0)
6044 length = ctx->num_output_clips + ctx->num_output_culls;
6045 int param = shader_io_get_unique_index(i);
6046 mark_tess_output(ctx, false, param);
6047 if (length > 4)
6048 mark_tess_output(ctx, false, param + 1);
6049 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6050 LLVMConstInt(ctx->ac.i32, param * 4, false),
6051 "");
6052 for (unsigned j = 0; j < length; j++) {
6053 ac_lds_store(&ctx->ac, dw_addr,
6054 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6055 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6056 }
6057 }
6058 }
6059
6060 struct ac_build_if_state
6061 {
6062 struct nir_to_llvm_context *ctx;
6063 LLVMValueRef condition;
6064 LLVMBasicBlockRef entry_block;
6065 LLVMBasicBlockRef true_block;
6066 LLVMBasicBlockRef false_block;
6067 LLVMBasicBlockRef merge_block;
6068 };
6069
6070 static LLVMBasicBlockRef
6071 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6072 {
6073 LLVMBasicBlockRef current_block;
6074 LLVMBasicBlockRef next_block;
6075 LLVMBasicBlockRef new_block;
6076
6077 /* get current basic block */
6078 current_block = LLVMGetInsertBlock(ctx->builder);
6079
6080 /* chqeck if there's another block after this one */
6081 next_block = LLVMGetNextBasicBlock(current_block);
6082 if (next_block) {
6083 /* insert the new block before the next block */
6084 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6085 }
6086 else {
6087 /* append new block after current block */
6088 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6089 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6090 }
6091 return new_block;
6092 }
6093
6094 static void
6095 ac_nir_build_if(struct ac_build_if_state *ifthen,
6096 struct nir_to_llvm_context *ctx,
6097 LLVMValueRef condition)
6098 {
6099 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6100
6101 memset(ifthen, 0, sizeof *ifthen);
6102 ifthen->ctx = ctx;
6103 ifthen->condition = condition;
6104 ifthen->entry_block = block;
6105
6106 /* create endif/merge basic block for the phi functions */
6107 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6108
6109 /* create/insert true_block before merge_block */
6110 ifthen->true_block =
6111 LLVMInsertBasicBlockInContext(ctx->context,
6112 ifthen->merge_block,
6113 "if-true-block");
6114
6115 /* successive code goes into the true block */
6116 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6117 }
6118
6119 /**
6120 * End a conditional.
6121 */
6122 static void
6123 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6124 {
6125 LLVMBuilderRef builder = ifthen->ctx->builder;
6126
6127 /* Insert branch to the merge block from current block */
6128 LLVMBuildBr(builder, ifthen->merge_block);
6129
6130 /*
6131 * Now patch in the various branch instructions.
6132 */
6133
6134 /* Insert the conditional branch instruction at the end of entry_block */
6135 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6136 if (ifthen->false_block) {
6137 /* we have an else clause */
6138 LLVMBuildCondBr(builder, ifthen->condition,
6139 ifthen->true_block, ifthen->false_block);
6140 }
6141 else {
6142 /* no else clause */
6143 LLVMBuildCondBr(builder, ifthen->condition,
6144 ifthen->true_block, ifthen->merge_block);
6145 }
6146
6147 /* Resume building code at end of the ifthen->merge_block */
6148 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6149 }
6150
6151 static void
6152 write_tess_factors(struct nir_to_llvm_context *ctx)
6153 {
6154 unsigned stride, outer_comps, inner_comps;
6155 struct ac_build_if_state if_ctx, inner_if_ctx;
6156 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6157 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6158 unsigned tess_inner_index, tess_outer_index;
6159 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6160 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6161 int i;
6162 emit_barrier(ctx);
6163
6164 switch (ctx->options->key.tcs.primitive_mode) {
6165 case GL_ISOLINES:
6166 stride = 2;
6167 outer_comps = 2;
6168 inner_comps = 0;
6169 break;
6170 case GL_TRIANGLES:
6171 stride = 4;
6172 outer_comps = 3;
6173 inner_comps = 1;
6174 break;
6175 case GL_QUADS:
6176 stride = 6;
6177 outer_comps = 4;
6178 inner_comps = 2;
6179 break;
6180 default:
6181 return;
6182 }
6183
6184 ac_nir_build_if(&if_ctx, ctx,
6185 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6186 invocation_id, ctx->ac.i32_0, ""));
6187
6188 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6189 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6190
6191 mark_tess_output(ctx, true, tess_inner_index);
6192 mark_tess_output(ctx, true, tess_outer_index);
6193 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6194 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6195 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6196 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6197 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6198
6199 for (i = 0; i < 4; i++) {
6200 inner[i] = LLVMGetUndef(ctx->ac.i32);
6201 outer[i] = LLVMGetUndef(ctx->ac.i32);
6202 }
6203
6204 // LINES reverseal
6205 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6206 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6207 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6208 ctx->ac.i32_1, "");
6209 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6210 } else {
6211 for (i = 0; i < outer_comps; i++) {
6212 outer[i] = out[i] =
6213 ac_lds_load(&ctx->ac, lds_outer);
6214 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6215 ctx->ac.i32_1, "");
6216 }
6217 for (i = 0; i < inner_comps; i++) {
6218 inner[i] = out[outer_comps+i] =
6219 ac_lds_load(&ctx->ac, lds_inner);
6220 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6221 ctx->ac.i32_1, "");
6222 }
6223 }
6224
6225 /* Convert the outputs to vectors for stores. */
6226 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6227 vec1 = NULL;
6228
6229 if (stride > 4)
6230 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6231
6232
6233 buffer = ctx->hs_ring_tess_factor;
6234 tf_base = ctx->tess_factor_offset;
6235 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6236 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6237 unsigned tf_offset = 0;
6238
6239 if (ctx->options->chip_class <= VI) {
6240 ac_nir_build_if(&inner_if_ctx, ctx,
6241 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6242 rel_patch_id, ctx->ac.i32_0, ""));
6243
6244 /* Store the dynamic HS control word. */
6245 ac_build_buffer_store_dword(&ctx->ac, buffer,
6246 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6247 1, ctx->ac.i32_0, tf_base,
6248 0, 1, 0, true, false);
6249 tf_offset += 4;
6250
6251 ac_nir_build_endif(&inner_if_ctx);
6252 }
6253
6254 /* Store the tessellation factors. */
6255 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6256 MIN2(stride, 4), byteoffset, tf_base,
6257 tf_offset, 1, 0, true, false);
6258 if (vec1)
6259 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6260 stride - 4, byteoffset, tf_base,
6261 16 + tf_offset, 1, 0, true, false);
6262
6263 //store to offchip for TES to read - only if TES reads them
6264 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6265 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6266 LLVMValueRef tf_inner_offset;
6267 unsigned param_outer, param_inner;
6268
6269 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6270 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6271 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6272
6273 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6274 util_next_power_of_two(outer_comps));
6275
6276 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6277 outer_comps, tf_outer_offset,
6278 ctx->oc_lds, 0, 1, 0, true, false);
6279 if (inner_comps) {
6280 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6281 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6282 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6283
6284 inner_vec = inner_comps == 1 ? inner[0] :
6285 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6286 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6287 inner_comps, tf_inner_offset,
6288 ctx->oc_lds, 0, 1, 0, true, false);
6289 }
6290 }
6291 ac_nir_build_endif(&if_ctx);
6292 }
6293
6294 static void
6295 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6296 {
6297 write_tess_factors(ctx);
6298 }
6299
6300 static bool
6301 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6302 LLVMValueRef *color, unsigned param, bool is_last,
6303 struct ac_export_args *args)
6304 {
6305 /* Export */
6306 si_llvm_init_export_args(ctx, color, param,
6307 args);
6308
6309 if (is_last) {
6310 args->valid_mask = 1; /* whether the EXEC mask is valid */
6311 args->done = 1; /* DONE bit */
6312 } else if (!args->enabled_channels)
6313 return false; /* unnecessary NULL export */
6314
6315 return true;
6316 }
6317
6318 static void
6319 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6320 LLVMValueRef depth, LLVMValueRef stencil,
6321 LLVMValueRef samplemask)
6322 {
6323 struct ac_export_args args;
6324
6325 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6326
6327 ac_build_export(&ctx->ac, &args);
6328 }
6329
6330 static void
6331 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6332 {
6333 unsigned index = 0;
6334 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6335 struct ac_export_args color_args[8];
6336
6337 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6338 LLVMValueRef values[4];
6339
6340 if (!(ctx->output_mask & (1ull << i)))
6341 continue;
6342
6343 if (i == FRAG_RESULT_DEPTH) {
6344 ctx->shader_info->fs.writes_z = true;
6345 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6346 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6347 } else if (i == FRAG_RESULT_STENCIL) {
6348 ctx->shader_info->fs.writes_stencil = true;
6349 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6350 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6351 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6352 ctx->shader_info->fs.writes_sample_mask = true;
6353 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6354 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6355 } else {
6356 bool last = false;
6357 for (unsigned j = 0; j < 4; j++)
6358 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6359 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6360
6361 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6362 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6363
6364 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6365 if (ret)
6366 index++;
6367 }
6368 }
6369
6370 for (unsigned i = 0; i < index; i++)
6371 ac_build_export(&ctx->ac, &color_args[i]);
6372 if (depth || stencil || samplemask)
6373 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6374 else if (!index) {
6375 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6376 ac_build_export(&ctx->ac, &color_args[0]);
6377 }
6378
6379 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6380 }
6381
6382 static void
6383 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6384 {
6385 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6386 }
6387
6388 static void
6389 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6390 LLVMValueRef *addrs)
6391 {
6392 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6393
6394 switch (ctx->stage) {
6395 case MESA_SHADER_VERTEX:
6396 if (ctx->options->key.vs.as_ls)
6397 handle_ls_outputs_post(ctx);
6398 else if (ctx->options->key.vs.as_es)
6399 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6400 else
6401 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6402 &ctx->shader_info->vs.outinfo);
6403 break;
6404 case MESA_SHADER_FRAGMENT:
6405 handle_fs_outputs_post(ctx);
6406 break;
6407 case MESA_SHADER_GEOMETRY:
6408 emit_gs_epilogue(ctx);
6409 break;
6410 case MESA_SHADER_TESS_CTRL:
6411 handle_tcs_outputs_post(ctx);
6412 break;
6413 case MESA_SHADER_TESS_EVAL:
6414 if (ctx->options->key.tes.as_es)
6415 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6416 else
6417 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6418 &ctx->shader_info->tes.outinfo);
6419 break;
6420 default:
6421 break;
6422 }
6423 }
6424
6425 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6426 {
6427 LLVMPassManagerRef passmgr;
6428 /* Create the pass manager */
6429 passmgr = LLVMCreateFunctionPassManagerForModule(
6430 ctx->module);
6431
6432 /* This pass should eliminate all the load and store instructions */
6433 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6434
6435 /* Add some optimization passes */
6436 LLVMAddScalarReplAggregatesPass(passmgr);
6437 LLVMAddLICMPass(passmgr);
6438 LLVMAddAggressiveDCEPass(passmgr);
6439 LLVMAddCFGSimplificationPass(passmgr);
6440 LLVMAddInstructionCombiningPass(passmgr);
6441
6442 /* Run the pass */
6443 LLVMInitializeFunctionPassManager(passmgr);
6444 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6445 LLVMFinalizeFunctionPassManager(passmgr);
6446
6447 LLVMDisposeBuilder(ctx->builder);
6448 LLVMDisposePassManager(passmgr);
6449 }
6450
6451 static void
6452 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6453 {
6454 struct ac_vs_output_info *outinfo;
6455
6456 switch (ctx->stage) {
6457 case MESA_SHADER_FRAGMENT:
6458 case MESA_SHADER_COMPUTE:
6459 case MESA_SHADER_TESS_CTRL:
6460 case MESA_SHADER_GEOMETRY:
6461 return;
6462 case MESA_SHADER_VERTEX:
6463 if (ctx->options->key.vs.as_ls ||
6464 ctx->options->key.vs.as_es)
6465 return;
6466 outinfo = &ctx->shader_info->vs.outinfo;
6467 break;
6468 case MESA_SHADER_TESS_EVAL:
6469 if (ctx->options->key.vs.as_es)
6470 return;
6471 outinfo = &ctx->shader_info->tes.outinfo;
6472 break;
6473 default:
6474 unreachable("Unhandled shader type");
6475 }
6476
6477 ac_optimize_vs_outputs(&ctx->ac,
6478 ctx->main_function,
6479 outinfo->vs_output_param_offset,
6480 VARYING_SLOT_MAX,
6481 &outinfo->param_exports);
6482 }
6483
6484 static void
6485 ac_setup_rings(struct nir_to_llvm_context *ctx)
6486 {
6487 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6488 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6489 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6490 }
6491
6492 if (ctx->is_gs_copy_shader) {
6493 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6494 }
6495 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6496 LLVMValueRef tmp;
6497 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6498 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6499
6500 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6501
6502 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6503 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6504 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6505 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6506 }
6507
6508 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6509 ctx->stage == MESA_SHADER_TESS_EVAL) {
6510 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6511 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6512 }
6513 }
6514
6515 static unsigned
6516 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6517 const struct nir_shader *nir)
6518 {
6519 switch (nir->info.stage) {
6520 case MESA_SHADER_TESS_CTRL:
6521 return chip_class >= CIK ? 128 : 64;
6522 case MESA_SHADER_GEOMETRY:
6523 return chip_class >= GFX9 ? 128 : 64;
6524 case MESA_SHADER_COMPUTE:
6525 break;
6526 default:
6527 return 0;
6528 }
6529
6530 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6531 nir->info.cs.local_size[1] *
6532 nir->info.cs.local_size[2];
6533 return max_workgroup_size;
6534 }
6535
6536 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6537 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6538 {
6539 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6540 LLVMConstInt(ctx->ac.i32, 8, false),
6541 LLVMConstInt(ctx->ac.i32, 8, false), false);
6542 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6543 ctx->ac.i32_0, "");
6544 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6545 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6546 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6547 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6548 }
6549
6550 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6551 {
6552 for(int i = 5; i >= 0; --i) {
6553 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6554 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6555 LLVMConstInt(ctx->ac.i32, 16, false), false);
6556 }
6557
6558 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6559 LLVMConstInt(ctx->ac.i32, 16, false),
6560 LLVMConstInt(ctx->ac.i32, 8, false), false);
6561 }
6562
6563 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6564 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6565 {
6566 struct ac_nir_context ctx = {};
6567 struct nir_function *func;
6568
6569 ctx.ac = *ac;
6570 ctx.abi = abi;
6571
6572 ctx.nctx = nctx;
6573 if (nctx)
6574 nctx->nir = &ctx;
6575
6576 ctx.stage = nir->info.stage;
6577
6578 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6579
6580 nir_foreach_variable(variable, &nir->outputs)
6581 handle_shader_output_decl(&ctx, nir, variable);
6582
6583 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6584 _mesa_key_pointer_equal);
6585 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6586 _mesa_key_pointer_equal);
6587 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6588 _mesa_key_pointer_equal);
6589
6590 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6591
6592 setup_locals(&ctx, func);
6593
6594 if (nir->info.stage == MESA_SHADER_COMPUTE)
6595 setup_shared(&ctx, nir);
6596
6597 visit_cf_list(&ctx, &func->impl->body);
6598 phi_post_pass(&ctx);
6599
6600 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6601 ctx.outputs);
6602
6603 free(ctx.locals);
6604 ralloc_free(ctx.defs);
6605 ralloc_free(ctx.phis);
6606 ralloc_free(ctx.vars);
6607
6608 if (nctx)
6609 nctx->nir = NULL;
6610 }
6611
6612 static
6613 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6614 struct nir_shader *const *shaders,
6615 int shader_count,
6616 struct ac_shader_variant_info *shader_info,
6617 const struct ac_nir_compiler_options *options)
6618 {
6619 struct nir_to_llvm_context ctx = {0};
6620 unsigned i;
6621 ctx.options = options;
6622 ctx.shader_info = shader_info;
6623 ctx.context = LLVMContextCreate();
6624 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6625
6626 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6627 options->family);
6628 ctx.ac.module = ctx.module;
6629 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6630
6631 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6632 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6633 LLVMSetDataLayout(ctx.module, data_layout_str);
6634 LLVMDisposeTargetData(data_layout);
6635 LLVMDisposeMessage(data_layout_str);
6636
6637 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6638 ctx.ac.builder = ctx.builder;
6639
6640 memset(shader_info, 0, sizeof(*shader_info));
6641
6642 for(int i = 0; i < shader_count; ++i)
6643 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6644
6645 for (i = 0; i < AC_UD_MAX_SETS; i++)
6646 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6647 for (i = 0; i < AC_UD_MAX_UD; i++)
6648 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6649
6650 ctx.max_workgroup_size = 0;
6651 for (int i = 0; i < shader_count; ++i) {
6652 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6653 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6654 shaders[i]));
6655 }
6656
6657 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6658 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6659
6660 ctx.abi.inputs = &ctx.inputs[0];
6661 ctx.abi.emit_outputs = handle_shader_outputs_post;
6662 ctx.abi.emit_vertex = visit_emit_vertex;
6663 ctx.abi.load_ubo = radv_load_ubo;
6664 ctx.abi.load_ssbo = radv_load_ssbo;
6665 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6666 ctx.abi.clamp_shadow_reference = false;
6667
6668 if (shader_count >= 2)
6669 ac_init_exec_full_mask(&ctx.ac);
6670
6671 if (ctx.ac.chip_class == GFX9 &&
6672 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6673 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6674
6675 for(int i = 0; i < shader_count; ++i) {
6676 ctx.stage = shaders[i]->info.stage;
6677 ctx.output_mask = 0;
6678 ctx.tess_outputs_written = 0;
6679 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6680 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6681
6682 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6683 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6684 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6685 ctx.abi.load_inputs = load_gs_input;
6686 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6687 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6688 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6689 ctx.abi.load_tess_inputs = load_tcs_input;
6690 ctx.abi.store_tcs_outputs = store_tcs_output;
6691 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6692 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6693 ctx.abi.load_tess_inputs = load_tes_input;
6694 ctx.abi.load_tess_coord = load_tess_coord;
6695 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6696 if (shader_info->info.vs.needs_instance_id) {
6697 ctx.shader_info->vs.vgpr_comp_cnt =
6698 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6699 }
6700 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6701 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6702 }
6703
6704 if (i)
6705 emit_barrier(&ctx);
6706
6707 ac_setup_rings(&ctx);
6708
6709 LLVMBasicBlockRef merge_block;
6710 if (shader_count >= 2) {
6711 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6712 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6713 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6714
6715 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6716 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6717 LLVMConstInt(ctx.ac.i32, 8, false), false);
6718 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6719 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6720 thread_id, count, "");
6721 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6722
6723 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6724 }
6725
6726 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6727 handle_fs_inputs(&ctx, shaders[i]);
6728 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6729 handle_vs_inputs(&ctx, shaders[i]);
6730 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6731 prepare_gs_input_vgprs(&ctx);
6732
6733 nir_foreach_variable(variable, &shaders[i]->outputs)
6734 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6735
6736 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6737
6738 if (shader_count >= 2) {
6739 LLVMBuildBr(ctx.ac.builder, merge_block);
6740 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6741 }
6742
6743 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6744 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6745 shaders[i]->info.cull_distance_array_size > 4;
6746 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6747 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6748 shaders[i]->info.gs.vertices_out;
6749 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6750 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6751 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6752 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6753 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6754 }
6755 }
6756
6757 LLVMBuildRetVoid(ctx.builder);
6758
6759 ac_llvm_finalize_module(&ctx);
6760
6761 if (shader_count == 1)
6762 ac_nir_eliminate_const_vs_outputs(&ctx);
6763
6764 return ctx.module;
6765 }
6766
6767 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6768 {
6769 unsigned *retval = (unsigned *)context;
6770 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6771 char *description = LLVMGetDiagInfoDescription(di);
6772
6773 if (severity == LLVMDSError) {
6774 *retval = 1;
6775 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6776 description);
6777 }
6778
6779 LLVMDisposeMessage(description);
6780 }
6781
6782 static unsigned ac_llvm_compile(LLVMModuleRef M,
6783 struct ac_shader_binary *binary,
6784 LLVMTargetMachineRef tm)
6785 {
6786 unsigned retval = 0;
6787 char *err;
6788 LLVMContextRef llvm_ctx;
6789 LLVMMemoryBufferRef out_buffer;
6790 unsigned buffer_size;
6791 const char *buffer_data;
6792 LLVMBool mem_err;
6793
6794 /* Setup Diagnostic Handler*/
6795 llvm_ctx = LLVMGetModuleContext(M);
6796
6797 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6798 &retval);
6799
6800 /* Compile IR*/
6801 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6802 &err, &out_buffer);
6803
6804 /* Process Errors/Warnings */
6805 if (mem_err) {
6806 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6807 free(err);
6808 retval = 1;
6809 goto out;
6810 }
6811
6812 /* Extract Shader Code*/
6813 buffer_size = LLVMGetBufferSize(out_buffer);
6814 buffer_data = LLVMGetBufferStart(out_buffer);
6815
6816 ac_elf_read(buffer_data, buffer_size, binary);
6817
6818 /* Clean up */
6819 LLVMDisposeMemoryBuffer(out_buffer);
6820
6821 out:
6822 return retval;
6823 }
6824
6825 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6826 LLVMModuleRef llvm_module,
6827 struct ac_shader_binary *binary,
6828 struct ac_shader_config *config,
6829 struct ac_shader_variant_info *shader_info,
6830 gl_shader_stage stage,
6831 bool dump_shader, bool supports_spill)
6832 {
6833 if (dump_shader)
6834 ac_dump_module(llvm_module);
6835
6836 memset(binary, 0, sizeof(*binary));
6837 int v = ac_llvm_compile(llvm_module, binary, tm);
6838 if (v) {
6839 fprintf(stderr, "compile failed\n");
6840 }
6841
6842 if (dump_shader)
6843 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6844
6845 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6846
6847 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6848 LLVMDisposeModule(llvm_module);
6849 LLVMContextDispose(ctx);
6850
6851 if (stage == MESA_SHADER_FRAGMENT) {
6852 shader_info->num_input_vgprs = 0;
6853 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6854 shader_info->num_input_vgprs += 2;
6855 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6856 shader_info->num_input_vgprs += 2;
6857 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6858 shader_info->num_input_vgprs += 2;
6859 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6860 shader_info->num_input_vgprs += 3;
6861 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6862 shader_info->num_input_vgprs += 2;
6863 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6864 shader_info->num_input_vgprs += 2;
6865 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6866 shader_info->num_input_vgprs += 2;
6867 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6868 shader_info->num_input_vgprs += 1;
6869 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6870 shader_info->num_input_vgprs += 1;
6871 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6872 shader_info->num_input_vgprs += 1;
6873 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6874 shader_info->num_input_vgprs += 1;
6875 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6876 shader_info->num_input_vgprs += 1;
6877 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6878 shader_info->num_input_vgprs += 1;
6879 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6880 shader_info->num_input_vgprs += 1;
6881 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6882 shader_info->num_input_vgprs += 1;
6883 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6884 shader_info->num_input_vgprs += 1;
6885 }
6886 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6887
6888 /* +3 for scratch wave offset and VCC */
6889 config->num_sgprs = MAX2(config->num_sgprs,
6890 shader_info->num_input_sgprs + 3);
6891 }
6892
6893 static void
6894 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6895 {
6896 switch (nir->info.stage) {
6897 case MESA_SHADER_COMPUTE:
6898 for (int i = 0; i < 3; ++i)
6899 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6900 break;
6901 case MESA_SHADER_FRAGMENT:
6902 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6903 break;
6904 case MESA_SHADER_GEOMETRY:
6905 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6906 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6907 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6908 shader_info->gs.invocations = nir->info.gs.invocations;
6909 break;
6910 case MESA_SHADER_TESS_EVAL:
6911 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6912 shader_info->tes.spacing = nir->info.tess.spacing;
6913 shader_info->tes.ccw = nir->info.tess.ccw;
6914 shader_info->tes.point_mode = nir->info.tess.point_mode;
6915 shader_info->tes.as_es = options->key.tes.as_es;
6916 break;
6917 case MESA_SHADER_TESS_CTRL:
6918 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6919 break;
6920 case MESA_SHADER_VERTEX:
6921 shader_info->vs.as_es = options->key.vs.as_es;
6922 shader_info->vs.as_ls = options->key.vs.as_ls;
6923 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6924 if (options->key.vs.as_ls)
6925 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6926 break;
6927 default:
6928 break;
6929 }
6930 }
6931
6932 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6933 struct ac_shader_binary *binary,
6934 struct ac_shader_config *config,
6935 struct ac_shader_variant_info *shader_info,
6936 struct nir_shader *const *nir,
6937 int nir_count,
6938 const struct ac_nir_compiler_options *options,
6939 bool dump_shader)
6940 {
6941
6942 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6943 options);
6944
6945 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6946 for (int i = 0; i < nir_count; ++i)
6947 ac_fill_shader_info(shader_info, nir[i], options);
6948 }
6949
6950 static void
6951 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6952 {
6953 LLVMValueRef args[9];
6954 args[0] = ctx->gsvs_ring;
6955 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6956 args[3] = ctx->ac.i32_0;
6957 args[4] = ctx->ac.i32_1; /* OFFEN */
6958 args[5] = ctx->ac.i32_0; /* IDXEN */
6959 args[6] = ctx->ac.i32_1; /* GLC */
6960 args[7] = ctx->ac.i32_1; /* SLC */
6961 args[8] = ctx->ac.i32_0; /* TFE */
6962
6963 int idx = 0;
6964
6965 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6966 int length = 4;
6967 int slot = idx;
6968 int slot_inc = 1;
6969 if (!(ctx->output_mask & (1ull << i)))
6970 continue;
6971
6972 if (i == VARYING_SLOT_CLIP_DIST0) {
6973 /* unpack clip and cull from a single set of slots */
6974 length = ctx->num_output_clips + ctx->num_output_culls;
6975 if (length > 4)
6976 slot_inc = 2;
6977 }
6978
6979 for (unsigned j = 0; j < length; j++) {
6980 LLVMValueRef value;
6981 args[2] = LLVMConstInt(ctx->ac.i32,
6982 (slot * 4 + j) *
6983 ctx->gs_max_out_vertices * 16 * 4, false);
6984
6985 value = ac_build_intrinsic(&ctx->ac,
6986 "llvm.SI.buffer.load.dword.i32.i32",
6987 ctx->ac.i32, args, 9,
6988 AC_FUNC_ATTR_READONLY |
6989 AC_FUNC_ATTR_LEGACY);
6990
6991 LLVMBuildStore(ctx->builder,
6992 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6993 }
6994 idx += slot_inc;
6995 }
6996 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6997 }
6998
6999 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7000 struct nir_shader *geom_shader,
7001 struct ac_shader_binary *binary,
7002 struct ac_shader_config *config,
7003 struct ac_shader_variant_info *shader_info,
7004 const struct ac_nir_compiler_options *options,
7005 bool dump_shader)
7006 {
7007 struct nir_to_llvm_context ctx = {0};
7008 ctx.context = LLVMContextCreate();
7009 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7010 ctx.options = options;
7011 ctx.shader_info = shader_info;
7012
7013 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7014 options->family);
7015 ctx.ac.module = ctx.module;
7016
7017 ctx.is_gs_copy_shader = true;
7018 LLVMSetTarget(ctx.module, "amdgcn--");
7019
7020 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
7021 ctx.ac.builder = ctx.builder;
7022 ctx.stage = MESA_SHADER_VERTEX;
7023
7024 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7025
7026 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7027 ac_setup_rings(&ctx);
7028
7029 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7030 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7031
7032 struct ac_nir_context nir_ctx = {};
7033 nir_ctx.ac = ctx.ac;
7034 nir_ctx.abi = &ctx.abi;
7035
7036 nir_ctx.nctx = &ctx;
7037 ctx.nir = &nir_ctx;
7038
7039 nir_foreach_variable(variable, &geom_shader->outputs) {
7040 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7041 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7042 }
7043
7044 ac_gs_copy_shader_emit(&ctx);
7045
7046 ctx.nir = NULL;
7047
7048 LLVMBuildRetVoid(ctx.builder);
7049
7050 ac_llvm_finalize_module(&ctx);
7051
7052 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7053 MESA_SHADER_VERTEX,
7054 dump_shader, options->supports_spill);
7055 }