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ac/nir: move ac_declare_lds_as_pointer() outside of the switch
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct ac_nir_context {
49 struct ac_llvm_context ac;
50 struct ac_shader_abi *abi;
51
52 gl_shader_stage stage;
53
54 struct hash_table *defs;
55 struct hash_table *phis;
56 struct hash_table *vars;
57
58 LLVMValueRef main_function;
59 LLVMBasicBlockRef continue_block;
60 LLVMBasicBlockRef break_block;
61
62 int num_locals;
63 LLVMValueRef *locals;
64 };
65
66 struct radv_shader_context {
67 struct ac_llvm_context ac;
68 const struct ac_nir_compiler_options *options;
69 struct ac_shader_variant_info *shader_info;
70 struct ac_shader_abi abi;
71
72 unsigned max_workgroup_size;
73 LLVMContextRef context;
74 LLVMValueRef main_function;
75
76 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
77 LLVMValueRef ring_offsets;
78
79 LLVMValueRef vertex_buffers;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef ls_out_layout;
83 LLVMValueRef es2gs_offset;
84
85 LLVMValueRef tcs_offchip_layout;
86 LLVMValueRef tcs_out_offsets;
87 LLVMValueRef tcs_out_layout;
88 LLVMValueRef tcs_in_layout;
89 LLVMValueRef oc_lds;
90 LLVMValueRef merged_wave_info;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tes_rel_patch_id;
93 LLVMValueRef tes_u;
94 LLVMValueRef tes_v;
95
96 LLVMValueRef gsvs_ring_stride;
97 LLVMValueRef gsvs_num_entries;
98 LLVMValueRef gs2vs_offset;
99 LLVMValueRef gs_wave_id;
100 LLVMValueRef gs_vtx_offset[6];
101
102 LLVMValueRef esgs_ring;
103 LLVMValueRef gsvs_ring;
104 LLVMValueRef hs_ring_tess_offchip;
105 LLVMValueRef hs_ring_tess_factor;
106
107 LLVMValueRef sample_pos_offset;
108 LLVMValueRef persp_sample, persp_center, persp_centroid;
109 LLVMValueRef linear_sample, linear_center, linear_centroid;
110
111 gl_shader_stage stage;
112
113 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
114
115 uint64_t input_mask;
116 uint64_t output_mask;
117 uint8_t num_output_clips;
118 uint8_t num_output_culls;
119
120 bool is_gs_copy_shader;
121 LLVMValueRef gs_next_vertex;
122 unsigned gs_max_out_vertices;
123
124 unsigned tes_primitive_mode;
125 uint64_t tess_outputs_written;
126 uint64_t tess_patch_outputs_written;
127
128 uint32_t tcs_patch_outputs_read;
129 uint64_t tcs_outputs_read;
130 };
131
132 static inline struct radv_shader_context *
133 radv_shader_context_from_abi(struct ac_shader_abi *abi)
134 {
135 struct radv_shader_context *ctx = NULL;
136 return container_of(abi, ctx, abi);
137 }
138
139 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
140 const nir_deref_var *deref,
141 enum ac_descriptor_type desc_type,
142 const nir_tex_instr *instr,
143 bool image, bool write);
144
145 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
146 {
147 return (index * 4) + chan;
148 }
149
150 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
151 {
152 /* handle patch indices separate */
153 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
154 return 0;
155 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
156 return 1;
157 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
158 return 2 + (slot - VARYING_SLOT_PATCH0);
159
160 if (slot == VARYING_SLOT_POS)
161 return 0;
162 if (slot == VARYING_SLOT_PSIZ)
163 return 1;
164 if (slot == VARYING_SLOT_CLIP_DIST0)
165 return 2;
166 /* 3 is reserved for clip dist as well */
167 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
168 return 4 + (slot - VARYING_SLOT_VAR0);
169 unreachable("illegal slot in get unique index\n");
170 }
171
172 static void set_llvm_calling_convention(LLVMValueRef func,
173 gl_shader_stage stage)
174 {
175 enum radeon_llvm_calling_convention calling_conv;
176
177 switch (stage) {
178 case MESA_SHADER_VERTEX:
179 case MESA_SHADER_TESS_EVAL:
180 calling_conv = RADEON_LLVM_AMDGPU_VS;
181 break;
182 case MESA_SHADER_GEOMETRY:
183 calling_conv = RADEON_LLVM_AMDGPU_GS;
184 break;
185 case MESA_SHADER_TESS_CTRL:
186 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
187 break;
188 case MESA_SHADER_FRAGMENT:
189 calling_conv = RADEON_LLVM_AMDGPU_PS;
190 break;
191 case MESA_SHADER_COMPUTE:
192 calling_conv = RADEON_LLVM_AMDGPU_CS;
193 break;
194 default:
195 unreachable("Unhandle shader type");
196 }
197
198 LLVMSetFunctionCallConv(func, calling_conv);
199 }
200
201 #define MAX_ARGS 23
202 struct arg_info {
203 LLVMTypeRef types[MAX_ARGS];
204 LLVMValueRef *assign[MAX_ARGS];
205 unsigned array_params_mask;
206 uint8_t count;
207 uint8_t sgpr_count;
208 uint8_t num_sgprs_used;
209 uint8_t num_vgprs_used;
210 };
211
212 enum ac_arg_regfile {
213 ARG_SGPR,
214 ARG_VGPR,
215 };
216
217 static void
218 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
219 LLVMValueRef *param_ptr)
220 {
221 assert(info->count < MAX_ARGS);
222
223 info->assign[info->count] = param_ptr;
224 info->types[info->count] = type;
225 info->count++;
226
227 if (regfile == ARG_SGPR) {
228 info->num_sgprs_used += ac_get_type_size(type) / 4;
229 info->sgpr_count++;
230 } else {
231 assert(regfile == ARG_VGPR);
232 info->num_vgprs_used += ac_get_type_size(type) / 4;
233 }
234 }
235
236 static inline void
237 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
238 {
239 info->array_params_mask |= (1 << info->count);
240 add_arg(info, ARG_SGPR, type, param_ptr);
241 }
242
243 static void assign_arguments(LLVMValueRef main_function,
244 struct arg_info *info)
245 {
246 unsigned i;
247 for (i = 0; i < info->count; i++) {
248 if (info->assign[i])
249 *info->assign[i] = LLVMGetParam(main_function, i);
250 }
251 }
252
253 static LLVMValueRef
254 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
255 LLVMBuilderRef builder, LLVMTypeRef *return_types,
256 unsigned num_return_elems,
257 struct arg_info *args,
258 unsigned max_workgroup_size,
259 bool unsafe_math)
260 {
261 LLVMTypeRef main_function_type, ret_type;
262 LLVMBasicBlockRef main_function_body;
263
264 if (num_return_elems)
265 ret_type = LLVMStructTypeInContext(ctx, return_types,
266 num_return_elems, true);
267 else
268 ret_type = LLVMVoidTypeInContext(ctx);
269
270 /* Setup the function */
271 main_function_type =
272 LLVMFunctionType(ret_type, args->types, args->count, 0);
273 LLVMValueRef main_function =
274 LLVMAddFunction(module, "main", main_function_type);
275 main_function_body =
276 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
277 LLVMPositionBuilderAtEnd(builder, main_function_body);
278
279 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
280 for (unsigned i = 0; i < args->sgpr_count; ++i) {
281 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
282
283 if (args->array_params_mask & (1 << i)) {
284 LLVMValueRef P = LLVMGetParam(main_function, i);
285 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
286 ac_add_attr_dereferenceable(P, UINT64_MAX);
287 }
288 }
289
290 if (max_workgroup_size) {
291 ac_llvm_add_target_dep_function_attr(main_function,
292 "amdgpu-max-work-group-size",
293 max_workgroup_size);
294 }
295 if (unsafe_math) {
296 /* These were copied from some LLVM test. */
297 LLVMAddTargetDependentFunctionAttr(main_function,
298 "less-precise-fpmad",
299 "true");
300 LLVMAddTargetDependentFunctionAttr(main_function,
301 "no-infs-fp-math",
302 "true");
303 LLVMAddTargetDependentFunctionAttr(main_function,
304 "no-nans-fp-math",
305 "true");
306 LLVMAddTargetDependentFunctionAttr(main_function,
307 "unsafe-fp-math",
308 "true");
309 LLVMAddTargetDependentFunctionAttr(main_function,
310 "no-signed-zeros-fp-math",
311 "true");
312 }
313 return main_function;
314 }
315
316 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
317 LLVMValueRef param, unsigned rshift,
318 unsigned bitwidth)
319 {
320 LLVMValueRef value = param;
321 if (rshift)
322 value = LLVMBuildLShr(ctx->builder, value,
323 LLVMConstInt(ctx->i32, rshift, false), "");
324
325 if (rshift + bitwidth < 32) {
326 unsigned mask = (1 << bitwidth) - 1;
327 value = LLVMBuildAnd(ctx->builder, value,
328 LLVMConstInt(ctx->i32, mask, false), "");
329 }
330 return value;
331 }
332
333 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
334 {
335 switch (ctx->stage) {
336 case MESA_SHADER_TESS_CTRL:
337 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
338 case MESA_SHADER_TESS_EVAL:
339 return ctx->tes_rel_patch_id;
340 break;
341 default:
342 unreachable("Illegal stage");
343 }
344 }
345
346 /* Tessellation shaders pass outputs to the next shader using LDS.
347 *
348 * LS outputs = TCS inputs
349 * TCS outputs = TES inputs
350 *
351 * The LDS layout is:
352 * - TCS inputs for patch 0
353 * - TCS inputs for patch 1
354 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
355 * - ...
356 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
357 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
358 * - TCS outputs for patch 1
359 * - Per-patch TCS outputs for patch 1
360 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
361 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
362 * - ...
363 *
364 * All three shaders VS(LS), TCS, TES share the same LDS space.
365 */
366 static LLVMValueRef
367 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
368 {
369 if (ctx->stage == MESA_SHADER_VERTEX)
370 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
371 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
372 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
373 else {
374 assert(0);
375 return NULL;
376 }
377 }
378
379 static LLVMValueRef
380 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
381 {
382 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
383 }
384
385 static LLVMValueRef
386 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
387 {
388 return LLVMBuildMul(ctx->ac.builder,
389 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
390 LLVMConstInt(ctx->ac.i32, 4, false), "");
391 }
392
393 static LLVMValueRef
394 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
395 {
396 return LLVMBuildMul(ctx->ac.builder,
397 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
398 LLVMConstInt(ctx->ac.i32, 4, false), "");
399 }
400
401 static LLVMValueRef
402 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
403 {
404 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
405 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
406
407 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
408 }
409
410 static LLVMValueRef
411 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
412 {
413 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
414 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
415 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
416
417 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
418 LLVMBuildMul(ctx->ac.builder, patch_stride,
419 rel_patch_id, ""),
420 "");
421 }
422
423 static LLVMValueRef
424 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
425 {
426 LLVMValueRef patch0_patch_data_offset =
427 get_tcs_out_patch0_patch_data_offset(ctx);
428 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
429 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
430
431 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
432 LLVMBuildMul(ctx->ac.builder, patch_stride,
433 rel_patch_id, ""),
434 "");
435 }
436
437 static void
438 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
439 uint32_t indirect_offset)
440 {
441 ud_info->sgpr_idx = *sgpr_idx;
442 ud_info->num_sgprs = num_sgprs;
443 ud_info->indirect = indirect_offset > 0;
444 ud_info->indirect_offset = indirect_offset;
445 *sgpr_idx += num_sgprs;
446 }
447
448 static void
449 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
450 uint8_t num_sgprs)
451 {
452 struct ac_userdata_info *ud_info =
453 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
454 assert(ud_info);
455
456 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
457 }
458
459 static void
460 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
461 uint32_t indirect_offset)
462 {
463 struct ac_userdata_info *ud_info =
464 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
465 assert(ud_info);
466
467 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
468 }
469
470 struct user_sgpr_info {
471 bool need_ring_offsets;
472 uint8_t sgpr_count;
473 bool indirect_all_descriptor_sets;
474 };
475
476 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
477 gl_shader_stage stage)
478 {
479 switch (stage) {
480 case MESA_SHADER_VERTEX:
481 if (ctx->shader_info->info.needs_multiview_view_index ||
482 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
483 return true;
484 break;
485 case MESA_SHADER_TESS_EVAL:
486 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
487 return true;
488 break;
489 case MESA_SHADER_GEOMETRY:
490 case MESA_SHADER_TESS_CTRL:
491 if (ctx->shader_info->info.needs_multiview_view_index)
492 return true;
493 break;
494 default:
495 break;
496 }
497 return false;
498 }
499
500 static uint8_t
501 count_vs_user_sgprs(struct radv_shader_context *ctx)
502 {
503 uint8_t count = 0;
504
505 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
506 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
507
508 return count;
509 }
510
511 static void allocate_user_sgprs(struct radv_shader_context *ctx,
512 gl_shader_stage stage,
513 bool has_previous_stage,
514 gl_shader_stage previous_stage,
515 bool needs_view_index,
516 struct user_sgpr_info *user_sgpr_info)
517 {
518 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
519
520 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
521 if (stage == MESA_SHADER_GEOMETRY ||
522 stage == MESA_SHADER_VERTEX ||
523 stage == MESA_SHADER_TESS_CTRL ||
524 stage == MESA_SHADER_TESS_EVAL ||
525 ctx->is_gs_copy_shader)
526 user_sgpr_info->need_ring_offsets = true;
527
528 if (stage == MESA_SHADER_FRAGMENT &&
529 ctx->shader_info->info.ps.needs_sample_positions)
530 user_sgpr_info->need_ring_offsets = true;
531
532 /* 2 user sgprs will nearly always be allocated for scratch/rings */
533 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
534 user_sgpr_info->sgpr_count += 2;
535 }
536
537 switch (stage) {
538 case MESA_SHADER_COMPUTE:
539 if (ctx->shader_info->info.cs.uses_grid_size)
540 user_sgpr_info->sgpr_count += 3;
541 break;
542 case MESA_SHADER_FRAGMENT:
543 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
544 break;
545 case MESA_SHADER_VERTEX:
546 if (!ctx->is_gs_copy_shader)
547 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
548 if (ctx->options->key.vs.as_ls)
549 user_sgpr_info->sgpr_count++;
550 break;
551 case MESA_SHADER_TESS_CTRL:
552 if (has_previous_stage) {
553 if (previous_stage == MESA_SHADER_VERTEX)
554 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
555 user_sgpr_info->sgpr_count++;
556 }
557 user_sgpr_info->sgpr_count += 4;
558 break;
559 case MESA_SHADER_TESS_EVAL:
560 user_sgpr_info->sgpr_count += 1;
561 break;
562 case MESA_SHADER_GEOMETRY:
563 if (has_previous_stage) {
564 if (previous_stage == MESA_SHADER_VERTEX) {
565 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
566 } else {
567 user_sgpr_info->sgpr_count++;
568 }
569 }
570 user_sgpr_info->sgpr_count += 2;
571 break;
572 default:
573 break;
574 }
575
576 if (needs_view_index)
577 user_sgpr_info->sgpr_count++;
578
579 if (ctx->shader_info->info.loads_push_constants)
580 user_sgpr_info->sgpr_count += 2;
581
582 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
583 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
584
585 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
586 user_sgpr_info->sgpr_count += 2;
587 user_sgpr_info->indirect_all_descriptor_sets = true;
588 } else {
589 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
590 }
591 }
592
593 static void
594 declare_global_input_sgprs(struct radv_shader_context *ctx,
595 gl_shader_stage stage,
596 bool has_previous_stage,
597 gl_shader_stage previous_stage,
598 const struct user_sgpr_info *user_sgpr_info,
599 struct arg_info *args,
600 LLVMValueRef *desc_sets)
601 {
602 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
603 unsigned num_sets = ctx->options->layout ?
604 ctx->options->layout->num_sets : 0;
605 unsigned stage_mask = 1 << stage;
606
607 if (has_previous_stage)
608 stage_mask |= 1 << previous_stage;
609
610 /* 1 for each descriptor set */
611 if (!user_sgpr_info->indirect_all_descriptor_sets) {
612 for (unsigned i = 0; i < num_sets; ++i) {
613 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
614 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
615 add_array_arg(args, type,
616 &ctx->descriptor_sets[i]);
617 }
618 }
619 } else {
620 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
621 }
622
623 if (ctx->shader_info->info.loads_push_constants) {
624 /* 1 for push constants and dynamic descriptors */
625 add_array_arg(args, type, &ctx->abi.push_constants);
626 }
627 }
628
629 static void
630 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
631 gl_shader_stage stage,
632 bool has_previous_stage,
633 gl_shader_stage previous_stage,
634 struct arg_info *args)
635 {
636 if (!ctx->is_gs_copy_shader &&
637 (stage == MESA_SHADER_VERTEX ||
638 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
639 if (ctx->shader_info->info.vs.has_vertex_buffers) {
640 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
641 &ctx->vertex_buffers);
642 }
643 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
644 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
645 if (ctx->shader_info->info.vs.needs_draw_id) {
646 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
647 }
648 }
649 }
650
651 static void
652 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
653 {
654 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
655 if (!ctx->is_gs_copy_shader) {
656 if (ctx->options->key.vs.as_ls) {
657 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
658 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
659 } else {
660 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
661 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
662 }
663 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
664 }
665 }
666
667 static void
668 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
669 {
670 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
671 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
672 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
673 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
674 }
675
676 static void
677 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
678 bool has_previous_stage, gl_shader_stage previous_stage,
679 const struct user_sgpr_info *user_sgpr_info,
680 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
681 {
682 unsigned num_sets = ctx->options->layout ?
683 ctx->options->layout->num_sets : 0;
684 unsigned stage_mask = 1 << stage;
685
686 if (has_previous_stage)
687 stage_mask |= 1 << previous_stage;
688
689 if (!user_sgpr_info->indirect_all_descriptor_sets) {
690 for (unsigned i = 0; i < num_sets; ++i) {
691 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
692 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
693 set_loc_desc(ctx, i, user_sgpr_idx, 0);
694 } else
695 ctx->descriptor_sets[i] = NULL;
696 }
697 } else {
698 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
699 user_sgpr_idx, 2);
700
701 for (unsigned i = 0; i < num_sets; ++i) {
702 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
703 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
704 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
705 ctx->descriptor_sets[i] =
706 ac_build_load_to_sgpr(&ctx->ac,
707 desc_sets,
708 LLVMConstInt(ctx->ac.i32, i, false));
709
710 } else
711 ctx->descriptor_sets[i] = NULL;
712 }
713 ctx->shader_info->need_indirect_descriptor_sets = true;
714 }
715
716 if (ctx->shader_info->info.loads_push_constants) {
717 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
718 }
719 }
720
721 static void
722 set_vs_specific_input_locs(struct radv_shader_context *ctx,
723 gl_shader_stage stage, bool has_previous_stage,
724 gl_shader_stage previous_stage,
725 uint8_t *user_sgpr_idx)
726 {
727 if (!ctx->is_gs_copy_shader &&
728 (stage == MESA_SHADER_VERTEX ||
729 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
730 if (ctx->shader_info->info.vs.has_vertex_buffers) {
731 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
732 user_sgpr_idx, 2);
733 }
734
735 unsigned vs_num = 2;
736 if (ctx->shader_info->info.vs.needs_draw_id)
737 vs_num++;
738
739 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
740 user_sgpr_idx, vs_num);
741 }
742 }
743
744 static void create_function(struct radv_shader_context *ctx,
745 gl_shader_stage stage,
746 bool has_previous_stage,
747 gl_shader_stage previous_stage)
748 {
749 uint8_t user_sgpr_idx;
750 struct user_sgpr_info user_sgpr_info;
751 struct arg_info args = {};
752 LLVMValueRef desc_sets;
753 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
754 allocate_user_sgprs(ctx, stage, has_previous_stage,
755 previous_stage, needs_view_index, &user_sgpr_info);
756
757 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
758 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
759 &ctx->ring_offsets);
760 }
761
762 switch (stage) {
763 case MESA_SHADER_COMPUTE:
764 declare_global_input_sgprs(ctx, stage, has_previous_stage,
765 previous_stage, &user_sgpr_info,
766 &args, &desc_sets);
767
768 if (ctx->shader_info->info.cs.uses_grid_size) {
769 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
770 &ctx->abi.num_work_groups);
771 }
772
773 for (int i = 0; i < 3; i++) {
774 ctx->abi.workgroup_ids[i] = NULL;
775 if (ctx->shader_info->info.cs.uses_block_id[i]) {
776 add_arg(&args, ARG_SGPR, ctx->ac.i32,
777 &ctx->abi.workgroup_ids[i]);
778 }
779 }
780
781 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
782 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
783 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
784 &ctx->abi.local_invocation_ids);
785 break;
786 case MESA_SHADER_VERTEX:
787 declare_global_input_sgprs(ctx, stage, has_previous_stage,
788 previous_stage, &user_sgpr_info,
789 &args, &desc_sets);
790 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
791 previous_stage, &args);
792
793 if (needs_view_index)
794 add_arg(&args, ARG_SGPR, ctx->ac.i32,
795 &ctx->abi.view_index);
796 if (ctx->options->key.vs.as_es)
797 add_arg(&args, ARG_SGPR, ctx->ac.i32,
798 &ctx->es2gs_offset);
799 else if (ctx->options->key.vs.as_ls)
800 add_arg(&args, ARG_SGPR, ctx->ac.i32,
801 &ctx->ls_out_layout);
802
803 declare_vs_input_vgprs(ctx, &args);
804 break;
805 case MESA_SHADER_TESS_CTRL:
806 if (has_previous_stage) {
807 // First 6 system regs
808 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
809 add_arg(&args, ARG_SGPR, ctx->ac.i32,
810 &ctx->merged_wave_info);
811 add_arg(&args, ARG_SGPR, ctx->ac.i32,
812 &ctx->tess_factor_offset);
813
814 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
816 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
817
818 declare_global_input_sgprs(ctx, stage,
819 has_previous_stage,
820 previous_stage,
821 &user_sgpr_info, &args,
822 &desc_sets);
823 declare_vs_specific_input_sgprs(ctx, stage,
824 has_previous_stage,
825 previous_stage, &args);
826
827 add_arg(&args, ARG_SGPR, ctx->ac.i32,
828 &ctx->ls_out_layout);
829
830 add_arg(&args, ARG_SGPR, ctx->ac.i32,
831 &ctx->tcs_offchip_layout);
832 add_arg(&args, ARG_SGPR, ctx->ac.i32,
833 &ctx->tcs_out_offsets);
834 add_arg(&args, ARG_SGPR, ctx->ac.i32,
835 &ctx->tcs_out_layout);
836 add_arg(&args, ARG_SGPR, ctx->ac.i32,
837 &ctx->tcs_in_layout);
838 if (needs_view_index)
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->abi.view_index);
841
842 add_arg(&args, ARG_VGPR, ctx->ac.i32,
843 &ctx->abi.tcs_patch_id);
844 add_arg(&args, ARG_VGPR, ctx->ac.i32,
845 &ctx->abi.tcs_rel_ids);
846
847 declare_vs_input_vgprs(ctx, &args);
848 } else {
849 declare_global_input_sgprs(ctx, stage,
850 has_previous_stage,
851 previous_stage,
852 &user_sgpr_info, &args,
853 &desc_sets);
854
855 add_arg(&args, ARG_SGPR, ctx->ac.i32,
856 &ctx->tcs_offchip_layout);
857 add_arg(&args, ARG_SGPR, ctx->ac.i32,
858 &ctx->tcs_out_offsets);
859 add_arg(&args, ARG_SGPR, ctx->ac.i32,
860 &ctx->tcs_out_layout);
861 add_arg(&args, ARG_SGPR, ctx->ac.i32,
862 &ctx->tcs_in_layout);
863 if (needs_view_index)
864 add_arg(&args, ARG_SGPR, ctx->ac.i32,
865 &ctx->abi.view_index);
866
867 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
868 add_arg(&args, ARG_SGPR, ctx->ac.i32,
869 &ctx->tess_factor_offset);
870 add_arg(&args, ARG_VGPR, ctx->ac.i32,
871 &ctx->abi.tcs_patch_id);
872 add_arg(&args, ARG_VGPR, ctx->ac.i32,
873 &ctx->abi.tcs_rel_ids);
874 }
875 break;
876 case MESA_SHADER_TESS_EVAL:
877 declare_global_input_sgprs(ctx, stage, has_previous_stage,
878 previous_stage, &user_sgpr_info,
879 &args, &desc_sets);
880
881 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
882 if (needs_view_index)
883 add_arg(&args, ARG_SGPR, ctx->ac.i32,
884 &ctx->abi.view_index);
885
886 if (ctx->options->key.tes.as_es) {
887 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
888 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
889 add_arg(&args, ARG_SGPR, ctx->ac.i32,
890 &ctx->es2gs_offset);
891 } else {
892 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
893 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
894 }
895 declare_tes_input_vgprs(ctx, &args);
896 break;
897 case MESA_SHADER_GEOMETRY:
898 if (has_previous_stage) {
899 // First 6 system regs
900 add_arg(&args, ARG_SGPR, ctx->ac.i32,
901 &ctx->gs2vs_offset);
902 add_arg(&args, ARG_SGPR, ctx->ac.i32,
903 &ctx->merged_wave_info);
904 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
905
906 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
907 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
908 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
909
910 declare_global_input_sgprs(ctx, stage,
911 has_previous_stage,
912 previous_stage,
913 &user_sgpr_info, &args,
914 &desc_sets);
915
916 if (previous_stage == MESA_SHADER_TESS_EVAL) {
917 add_arg(&args, ARG_SGPR, ctx->ac.i32,
918 &ctx->tcs_offchip_layout);
919 } else {
920 declare_vs_specific_input_sgprs(ctx, stage,
921 has_previous_stage,
922 previous_stage,
923 &args);
924 }
925
926 add_arg(&args, ARG_SGPR, ctx->ac.i32,
927 &ctx->gsvs_ring_stride);
928 add_arg(&args, ARG_SGPR, ctx->ac.i32,
929 &ctx->gsvs_num_entries);
930 if (needs_view_index)
931 add_arg(&args, ARG_SGPR, ctx->ac.i32,
932 &ctx->abi.view_index);
933
934 add_arg(&args, ARG_VGPR, ctx->ac.i32,
935 &ctx->gs_vtx_offset[0]);
936 add_arg(&args, ARG_VGPR, ctx->ac.i32,
937 &ctx->gs_vtx_offset[2]);
938 add_arg(&args, ARG_VGPR, ctx->ac.i32,
939 &ctx->abi.gs_prim_id);
940 add_arg(&args, ARG_VGPR, ctx->ac.i32,
941 &ctx->abi.gs_invocation_id);
942 add_arg(&args, ARG_VGPR, ctx->ac.i32,
943 &ctx->gs_vtx_offset[4]);
944
945 if (previous_stage == MESA_SHADER_VERTEX) {
946 declare_vs_input_vgprs(ctx, &args);
947 } else {
948 declare_tes_input_vgprs(ctx, &args);
949 }
950 } else {
951 declare_global_input_sgprs(ctx, stage,
952 has_previous_stage,
953 previous_stage,
954 &user_sgpr_info, &args,
955 &desc_sets);
956
957 add_arg(&args, ARG_SGPR, ctx->ac.i32,
958 &ctx->gsvs_ring_stride);
959 add_arg(&args, ARG_SGPR, ctx->ac.i32,
960 &ctx->gsvs_num_entries);
961 if (needs_view_index)
962 add_arg(&args, ARG_SGPR, ctx->ac.i32,
963 &ctx->abi.view_index);
964
965 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
966 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
967 add_arg(&args, ARG_VGPR, ctx->ac.i32,
968 &ctx->gs_vtx_offset[0]);
969 add_arg(&args, ARG_VGPR, ctx->ac.i32,
970 &ctx->gs_vtx_offset[1]);
971 add_arg(&args, ARG_VGPR, ctx->ac.i32,
972 &ctx->abi.gs_prim_id);
973 add_arg(&args, ARG_VGPR, ctx->ac.i32,
974 &ctx->gs_vtx_offset[2]);
975 add_arg(&args, ARG_VGPR, ctx->ac.i32,
976 &ctx->gs_vtx_offset[3]);
977 add_arg(&args, ARG_VGPR, ctx->ac.i32,
978 &ctx->gs_vtx_offset[4]);
979 add_arg(&args, ARG_VGPR, ctx->ac.i32,
980 &ctx->gs_vtx_offset[5]);
981 add_arg(&args, ARG_VGPR, ctx->ac.i32,
982 &ctx->abi.gs_invocation_id);
983 }
984 break;
985 case MESA_SHADER_FRAGMENT:
986 declare_global_input_sgprs(ctx, stage, has_previous_stage,
987 previous_stage, &user_sgpr_info,
988 &args, &desc_sets);
989
990 if (ctx->shader_info->info.ps.needs_sample_positions)
991 add_arg(&args, ARG_SGPR, ctx->ac.i32,
992 &ctx->sample_pos_offset);
993
994 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
995 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
996 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
997 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
998 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
999 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1000 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1001 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1002 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1003 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1004 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1005 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1006 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1007 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1008 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1009 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1010 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1011 break;
1012 default:
1013 unreachable("Shader stage not implemented");
1014 }
1015
1016 ctx->main_function = create_llvm_function(
1017 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1018 ctx->max_workgroup_size,
1019 ctx->options->unsafe_math);
1020 set_llvm_calling_convention(ctx->main_function, stage);
1021
1022
1023 ctx->shader_info->num_input_vgprs = 0;
1024 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1025
1026 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1027
1028 if (ctx->stage != MESA_SHADER_FRAGMENT)
1029 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1030
1031 assign_arguments(ctx->main_function, &args);
1032
1033 user_sgpr_idx = 0;
1034
1035 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1036 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1037 &user_sgpr_idx, 2);
1038 if (ctx->options->supports_spill) {
1039 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1040 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1041 NULL, 0, AC_FUNC_ATTR_READNONE);
1042 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1043 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1044 }
1045 }
1046
1047 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1048 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1049 if (has_previous_stage)
1050 user_sgpr_idx = 0;
1051
1052 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1053 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1054
1055 switch (stage) {
1056 case MESA_SHADER_COMPUTE:
1057 if (ctx->shader_info->info.cs.uses_grid_size) {
1058 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1059 &user_sgpr_idx, 3);
1060 }
1061 break;
1062 case MESA_SHADER_VERTEX:
1063 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1064 previous_stage, &user_sgpr_idx);
1065 if (ctx->abi.view_index)
1066 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1067 if (ctx->options->key.vs.as_ls) {
1068 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1069 &user_sgpr_idx, 1);
1070 }
1071 break;
1072 case MESA_SHADER_TESS_CTRL:
1073 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1074 previous_stage, &user_sgpr_idx);
1075 if (has_previous_stage)
1076 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1077 &user_sgpr_idx, 1);
1078 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1079 if (ctx->abi.view_index)
1080 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1081 break;
1082 case MESA_SHADER_TESS_EVAL:
1083 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1084 if (ctx->abi.view_index)
1085 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1086 break;
1087 case MESA_SHADER_GEOMETRY:
1088 if (has_previous_stage) {
1089 if (previous_stage == MESA_SHADER_VERTEX)
1090 set_vs_specific_input_locs(ctx, stage,
1091 has_previous_stage,
1092 previous_stage,
1093 &user_sgpr_idx);
1094 else
1095 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1096 &user_sgpr_idx, 1);
1097 }
1098 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1099 &user_sgpr_idx, 2);
1100 if (ctx->abi.view_index)
1101 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1102 break;
1103 case MESA_SHADER_FRAGMENT:
1104 if (ctx->shader_info->info.ps.needs_sample_positions) {
1105 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1106 &user_sgpr_idx, 1);
1107 }
1108 break;
1109 default:
1110 unreachable("Shader stage not implemented");
1111 }
1112
1113 if (stage == MESA_SHADER_TESS_CTRL ||
1114 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1115 /* GFX9 has the ESGS ring buffer in LDS. */
1116 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1117 ac_declare_lds_as_pointer(&ctx->ac);
1118 }
1119
1120 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1121 }
1122
1123 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1124 LLVMValueRef value, unsigned count)
1125 {
1126 unsigned num_components = ac_get_llvm_num_components(value);
1127 if (count == num_components)
1128 return value;
1129
1130 LLVMValueRef masks[] = {
1131 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1132 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1133
1134 if (count == 1)
1135 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1136 "");
1137
1138 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1139 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1140 }
1141
1142 static void
1143 build_store_values_extended(struct ac_llvm_context *ac,
1144 LLVMValueRef *values,
1145 unsigned value_count,
1146 unsigned value_stride,
1147 LLVMValueRef vec)
1148 {
1149 LLVMBuilderRef builder = ac->builder;
1150 unsigned i;
1151
1152 for (i = 0; i < value_count; i++) {
1153 LLVMValueRef ptr = values[i * value_stride];
1154 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1155 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1156 LLVMBuildStore(builder, value, ptr);
1157 }
1158 }
1159
1160 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1161 const nir_ssa_def *def)
1162 {
1163 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1164 if (def->num_components > 1) {
1165 type = LLVMVectorType(type, def->num_components);
1166 }
1167 return type;
1168 }
1169
1170 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1171 {
1172 assert(src.is_ssa);
1173 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1174 return (LLVMValueRef)entry->data;
1175 }
1176
1177 static LLVMValueRef
1178 get_memory_ptr(struct ac_nir_context *ctx, nir_src src)
1179 {
1180 LLVMValueRef ptr = get_src(ctx, src);
1181 ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ac.lds, &ptr, 1, "");
1182 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1183
1184 return LLVMBuildBitCast(ctx->ac.builder, ptr,
1185 LLVMPointerType(ctx->ac.i32, addr_space), "");
1186 }
1187
1188 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1189 const struct nir_block *b)
1190 {
1191 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1192 return (LLVMBasicBlockRef)entry->data;
1193 }
1194
1195 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1196 nir_alu_src src,
1197 unsigned num_components)
1198 {
1199 LLVMValueRef value = get_src(ctx, src.src);
1200 bool need_swizzle = false;
1201
1202 assert(value);
1203 LLVMTypeRef type = LLVMTypeOf(value);
1204 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1205 ? LLVMGetVectorSize(type)
1206 : 1;
1207
1208 for (unsigned i = 0; i < num_components; ++i) {
1209 assert(src.swizzle[i] < src_components);
1210 if (src.swizzle[i] != i)
1211 need_swizzle = true;
1212 }
1213
1214 if (need_swizzle || num_components != src_components) {
1215 LLVMValueRef masks[] = {
1216 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1217 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1218 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1219 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1220
1221 if (src_components > 1 && num_components == 1) {
1222 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1223 masks[0], "");
1224 } else if (src_components == 1 && num_components > 1) {
1225 LLVMValueRef values[] = {value, value, value, value};
1226 value = ac_build_gather_values(&ctx->ac, values, num_components);
1227 } else {
1228 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1229 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1230 swizzle, "");
1231 }
1232 }
1233 assert(!src.negate);
1234 assert(!src.abs);
1235 return value;
1236 }
1237
1238 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1239 LLVMIntPredicate pred, LLVMValueRef src0,
1240 LLVMValueRef src1)
1241 {
1242 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1243 return LLVMBuildSelect(ctx->builder, result,
1244 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1245 ctx->i32_0, "");
1246 }
1247
1248 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1249 LLVMRealPredicate pred, LLVMValueRef src0,
1250 LLVMValueRef src1)
1251 {
1252 LLVMValueRef result;
1253 src0 = ac_to_float(ctx, src0);
1254 src1 = ac_to_float(ctx, src1);
1255 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1256 return LLVMBuildSelect(ctx->builder, result,
1257 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1258 ctx->i32_0, "");
1259 }
1260
1261 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1262 const char *intrin,
1263 LLVMTypeRef result_type,
1264 LLVMValueRef src0)
1265 {
1266 char name[64];
1267 LLVMValueRef params[] = {
1268 ac_to_float(ctx, src0),
1269 };
1270
1271 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1272 ac_get_elem_bits(ctx, result_type));
1273 assert(length < sizeof(name));
1274 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1275 }
1276
1277 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1278 const char *intrin,
1279 LLVMTypeRef result_type,
1280 LLVMValueRef src0, LLVMValueRef src1)
1281 {
1282 char name[64];
1283 LLVMValueRef params[] = {
1284 ac_to_float(ctx, src0),
1285 ac_to_float(ctx, src1),
1286 };
1287
1288 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1289 ac_get_elem_bits(ctx, result_type));
1290 assert(length < sizeof(name));
1291 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1292 }
1293
1294 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1295 const char *intrin,
1296 LLVMTypeRef result_type,
1297 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1298 {
1299 char name[64];
1300 LLVMValueRef params[] = {
1301 ac_to_float(ctx, src0),
1302 ac_to_float(ctx, src1),
1303 ac_to_float(ctx, src2),
1304 };
1305
1306 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1307 ac_get_elem_bits(ctx, result_type));
1308 assert(length < sizeof(name));
1309 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1310 }
1311
1312 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1313 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1314 {
1315 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1316 ctx->i32_0, "");
1317 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1318 }
1319
1320 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1321 LLVMIntPredicate pred,
1322 LLVMValueRef src0, LLVMValueRef src1)
1323 {
1324 return LLVMBuildSelect(ctx->builder,
1325 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1326 src0,
1327 src1, "");
1328
1329 }
1330 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1331 LLVMValueRef src0)
1332 {
1333 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1334 LLVMBuildNeg(ctx->builder, src0, ""));
1335 }
1336
1337 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1338 LLVMValueRef src0,
1339 unsigned bitsize)
1340 {
1341 LLVMValueRef cmp, val, zero, one;
1342 LLVMTypeRef type;
1343
1344 if (bitsize == 32) {
1345 type = ctx->f32;
1346 zero = ctx->f32_0;
1347 one = ctx->f32_1;
1348 } else {
1349 type = ctx->f64;
1350 zero = ctx->f64_0;
1351 one = ctx->f64_1;
1352 }
1353
1354 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1355 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1356 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1357 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1358 return val;
1359 }
1360
1361 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1362 LLVMValueRef src0, unsigned bitsize)
1363 {
1364 LLVMValueRef cmp, val, zero, one;
1365 LLVMTypeRef type;
1366
1367 if (bitsize == 32) {
1368 type = ctx->i32;
1369 zero = ctx->i32_0;
1370 one = ctx->i32_1;
1371 } else {
1372 type = ctx->i64;
1373 zero = ctx->i64_0;
1374 one = ctx->i64_1;
1375 }
1376
1377 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1378 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1379 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1380 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1381 return val;
1382 }
1383
1384 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1385 LLVMValueRef src0, unsigned bitsize)
1386 {
1387 LLVMTypeRef type;
1388 char *intr;
1389
1390 if (bitsize == 32) {
1391 intr = "llvm.floor.f32";
1392 type = ctx->f32;
1393 } else {
1394 intr = "llvm.floor.f64";
1395 type = ctx->f64;
1396 }
1397
1398 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1399 LLVMValueRef params[] = {
1400 fsrc0,
1401 };
1402 LLVMValueRef floor = ac_build_intrinsic(ctx, intr, type, params, 1,
1403 AC_FUNC_ATTR_READNONE);
1404 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1405 }
1406
1407 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1408 const char *intrin,
1409 LLVMValueRef src0, LLVMValueRef src1)
1410 {
1411 LLVMTypeRef ret_type;
1412 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1413 LLVMValueRef res;
1414 LLVMValueRef params[] = { src0, src1 };
1415 ret_type = LLVMStructTypeInContext(ctx->context, types,
1416 2, true);
1417
1418 res = ac_build_intrinsic(ctx, intrin, ret_type,
1419 params, 2, AC_FUNC_ATTR_READNONE);
1420
1421 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1422 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1423 return res;
1424 }
1425
1426 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1427 LLVMValueRef src0)
1428 {
1429 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1430 }
1431
1432 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1433 LLVMValueRef src0)
1434 {
1435 src0 = ac_to_float(ctx, src0);
1436 return LLVMBuildSExt(ctx->builder,
1437 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1438 ctx->i32, "");
1439 }
1440
1441 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1442 LLVMValueRef src0,
1443 unsigned bitsize)
1444 {
1445 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1446
1447 if (bitsize == 32)
1448 return result;
1449
1450 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1451 }
1452
1453 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1454 LLVMValueRef src0)
1455 {
1456 return LLVMBuildSExt(ctx->builder,
1457 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1458 ctx->i32, "");
1459 }
1460
1461 static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx,
1462 LLVMValueRef src0)
1463 {
1464 LLVMValueRef result;
1465 LLVMValueRef cond = NULL;
1466
1467 src0 = ac_to_float(ctx, src0);
1468 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1469
1470 if (ctx->chip_class >= VI) {
1471 LLVMValueRef args[2];
1472 /* Check if the result is a denormal - and flush to 0 if so. */
1473 args[0] = result;
1474 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1475 cond = ac_build_intrinsic(ctx, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1476 }
1477
1478 /* need to convert back up to f32 */
1479 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1480
1481 if (ctx->chip_class >= VI)
1482 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1483 else {
1484 /* for SI/CIK */
1485 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1486 * so compare the result and flush to 0 if it's smaller.
1487 */
1488 LLVMValueRef temp, cond2;
1489 temp = emit_intrin_1f_param(ctx, "llvm.fabs", ctx->f32, result);
1490 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1491 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1492 temp, "");
1493 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1494 temp, ctx->f32_0, "");
1495 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1496 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1497 }
1498 return result;
1499 }
1500
1501 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1502 LLVMValueRef src0, LLVMValueRef src1)
1503 {
1504 LLVMValueRef dst64, result;
1505 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1506 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1507
1508 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1509 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1510 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1511 return result;
1512 }
1513
1514 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1515 LLVMValueRef src0, LLVMValueRef src1)
1516 {
1517 LLVMValueRef dst64, result;
1518 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1519 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1520
1521 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1522 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1523 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1524 return result;
1525 }
1526
1527 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1528 bool is_signed,
1529 const LLVMValueRef srcs[3])
1530 {
1531 LLVMValueRef result;
1532 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1533
1534 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1535 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1536 return result;
1537 }
1538
1539 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1540 LLVMValueRef src0, LLVMValueRef src1,
1541 LLVMValueRef src2, LLVMValueRef src3)
1542 {
1543 LLVMValueRef bfi_args[3], result;
1544
1545 bfi_args[0] = LLVMBuildShl(ctx->builder,
1546 LLVMBuildSub(ctx->builder,
1547 LLVMBuildShl(ctx->builder,
1548 ctx->i32_1,
1549 src3, ""),
1550 ctx->i32_1, ""),
1551 src2, "");
1552 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1553 bfi_args[2] = src0;
1554
1555 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1556
1557 /* Calculate:
1558 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1559 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1560 */
1561 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1562 LLVMBuildAnd(ctx->builder, bfi_args[0],
1563 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1564
1565 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1566 return result;
1567 }
1568
1569 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1570 LLVMValueRef src0)
1571 {
1572 LLVMValueRef comp[2];
1573
1574 src0 = ac_to_float(ctx, src0);
1575 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1576 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1577
1578 return ac_build_cvt_pkrtz_f16(ctx, comp);
1579 }
1580
1581 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1582 LLVMValueRef src0)
1583 {
1584 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1585 LLVMValueRef temps[2], result, val;
1586 int i;
1587
1588 for (i = 0; i < 2; i++) {
1589 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1590 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1591 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1592 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1593 }
1594
1595 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1596 ctx->i32_0, "");
1597 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1598 ctx->i32_1, "");
1599 return result;
1600 }
1601
1602 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1603 nir_op op,
1604 LLVMValueRef src0)
1605 {
1606 unsigned mask;
1607 int idx;
1608 LLVMValueRef result;
1609
1610 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1611 mask = AC_TID_MASK_LEFT;
1612 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1613 mask = AC_TID_MASK_TOP;
1614 else
1615 mask = AC_TID_MASK_TOP_LEFT;
1616
1617 /* for DDX we want to next X pixel, DDY next Y pixel. */
1618 if (op == nir_op_fddx_fine ||
1619 op == nir_op_fddx_coarse ||
1620 op == nir_op_fddx)
1621 idx = 1;
1622 else
1623 idx = 2;
1624
1625 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1626 return result;
1627 }
1628
1629 /*
1630 * this takes an I,J coordinate pair,
1631 * and works out the X and Y derivatives.
1632 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1633 */
1634 static LLVMValueRef emit_ddxy_interp(
1635 struct ac_nir_context *ctx,
1636 LLVMValueRef interp_ij)
1637 {
1638 LLVMValueRef result[4], a;
1639 unsigned i;
1640
1641 for (i = 0; i < 2; i++) {
1642 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1643 LLVMConstInt(ctx->ac.i32, i, false), "");
1644 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1645 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1646 }
1647 return ac_build_gather_values(&ctx->ac, result, 4);
1648 }
1649
1650 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1651 {
1652 LLVMValueRef src[4], result = NULL;
1653 unsigned num_components = instr->dest.dest.ssa.num_components;
1654 unsigned src_components;
1655 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1656
1657 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1658 switch (instr->op) {
1659 case nir_op_vec2:
1660 case nir_op_vec3:
1661 case nir_op_vec4:
1662 src_components = 1;
1663 break;
1664 case nir_op_pack_half_2x16:
1665 src_components = 2;
1666 break;
1667 case nir_op_unpack_half_2x16:
1668 src_components = 1;
1669 break;
1670 default:
1671 src_components = num_components;
1672 break;
1673 }
1674 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1675 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1676
1677 switch (instr->op) {
1678 case nir_op_fmov:
1679 case nir_op_imov:
1680 result = src[0];
1681 break;
1682 case nir_op_fneg:
1683 src[0] = ac_to_float(&ctx->ac, src[0]);
1684 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1685 break;
1686 case nir_op_ineg:
1687 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1688 break;
1689 case nir_op_inot:
1690 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1691 break;
1692 case nir_op_iadd:
1693 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1694 break;
1695 case nir_op_fadd:
1696 src[0] = ac_to_float(&ctx->ac, src[0]);
1697 src[1] = ac_to_float(&ctx->ac, src[1]);
1698 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1699 break;
1700 case nir_op_fsub:
1701 src[0] = ac_to_float(&ctx->ac, src[0]);
1702 src[1] = ac_to_float(&ctx->ac, src[1]);
1703 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1704 break;
1705 case nir_op_isub:
1706 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1707 break;
1708 case nir_op_imul:
1709 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1710 break;
1711 case nir_op_imod:
1712 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1713 break;
1714 case nir_op_umod:
1715 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1716 break;
1717 case nir_op_fmod:
1718 src[0] = ac_to_float(&ctx->ac, src[0]);
1719 src[1] = ac_to_float(&ctx->ac, src[1]);
1720 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1721 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1722 ac_to_float_type(&ctx->ac, def_type), result);
1723 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1724 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1725 break;
1726 case nir_op_frem:
1727 src[0] = ac_to_float(&ctx->ac, src[0]);
1728 src[1] = ac_to_float(&ctx->ac, src[1]);
1729 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1730 break;
1731 case nir_op_irem:
1732 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1733 break;
1734 case nir_op_idiv:
1735 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1736 break;
1737 case nir_op_udiv:
1738 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1739 break;
1740 case nir_op_fmul:
1741 src[0] = ac_to_float(&ctx->ac, src[0]);
1742 src[1] = ac_to_float(&ctx->ac, src[1]);
1743 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1744 break;
1745 case nir_op_frcp:
1746 src[0] = ac_to_float(&ctx->ac, src[0]);
1747 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1748 src[0]);
1749 break;
1750 case nir_op_iand:
1751 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1752 break;
1753 case nir_op_ior:
1754 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1755 break;
1756 case nir_op_ixor:
1757 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1758 break;
1759 case nir_op_ishl:
1760 result = LLVMBuildShl(ctx->ac.builder, src[0],
1761 LLVMBuildZExt(ctx->ac.builder, src[1],
1762 LLVMTypeOf(src[0]), ""),
1763 "");
1764 break;
1765 case nir_op_ishr:
1766 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1767 LLVMBuildZExt(ctx->ac.builder, src[1],
1768 LLVMTypeOf(src[0]), ""),
1769 "");
1770 break;
1771 case nir_op_ushr:
1772 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1773 LLVMBuildZExt(ctx->ac.builder, src[1],
1774 LLVMTypeOf(src[0]), ""),
1775 "");
1776 break;
1777 case nir_op_ilt:
1778 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1779 break;
1780 case nir_op_ine:
1781 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1782 break;
1783 case nir_op_ieq:
1784 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1785 break;
1786 case nir_op_ige:
1787 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1788 break;
1789 case nir_op_ult:
1790 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1791 break;
1792 case nir_op_uge:
1793 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1794 break;
1795 case nir_op_feq:
1796 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1797 break;
1798 case nir_op_fne:
1799 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1800 break;
1801 case nir_op_flt:
1802 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1803 break;
1804 case nir_op_fge:
1805 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1806 break;
1807 case nir_op_fabs:
1808 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1809 ac_to_float_type(&ctx->ac, def_type), src[0]);
1810 break;
1811 case nir_op_iabs:
1812 result = emit_iabs(&ctx->ac, src[0]);
1813 break;
1814 case nir_op_imax:
1815 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1816 break;
1817 case nir_op_imin:
1818 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1819 break;
1820 case nir_op_umax:
1821 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1822 break;
1823 case nir_op_umin:
1824 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1825 break;
1826 case nir_op_isign:
1827 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1828 break;
1829 case nir_op_fsign:
1830 src[0] = ac_to_float(&ctx->ac, src[0]);
1831 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1832 break;
1833 case nir_op_ffloor:
1834 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1835 ac_to_float_type(&ctx->ac, def_type), src[0]);
1836 break;
1837 case nir_op_ftrunc:
1838 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1839 ac_to_float_type(&ctx->ac, def_type), src[0]);
1840 break;
1841 case nir_op_fceil:
1842 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1843 ac_to_float_type(&ctx->ac, def_type), src[0]);
1844 break;
1845 case nir_op_fround_even:
1846 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1847 ac_to_float_type(&ctx->ac, def_type),src[0]);
1848 break;
1849 case nir_op_ffract:
1850 result = emit_ffract(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1851 break;
1852 case nir_op_fsin:
1853 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1854 ac_to_float_type(&ctx->ac, def_type), src[0]);
1855 break;
1856 case nir_op_fcos:
1857 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1858 ac_to_float_type(&ctx->ac, def_type), src[0]);
1859 break;
1860 case nir_op_fsqrt:
1861 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1862 ac_to_float_type(&ctx->ac, def_type), src[0]);
1863 break;
1864 case nir_op_fexp2:
1865 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1866 ac_to_float_type(&ctx->ac, def_type), src[0]);
1867 break;
1868 case nir_op_flog2:
1869 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1870 ac_to_float_type(&ctx->ac, def_type), src[0]);
1871 break;
1872 case nir_op_frsq:
1873 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1874 ac_to_float_type(&ctx->ac, def_type), src[0]);
1875 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1876 result);
1877 break;
1878 case nir_op_fpow:
1879 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1880 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1881 break;
1882 case nir_op_fmax:
1883 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1884 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1885 if (ctx->ac.chip_class < GFX9 &&
1886 instr->dest.dest.ssa.bit_size == 32) {
1887 /* Only pre-GFX9 chips do not flush denorms. */
1888 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1889 ac_to_float_type(&ctx->ac, def_type),
1890 result);
1891 }
1892 break;
1893 case nir_op_fmin:
1894 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1895 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1896 if (ctx->ac.chip_class < GFX9 &&
1897 instr->dest.dest.ssa.bit_size == 32) {
1898 /* Only pre-GFX9 chips do not flush denorms. */
1899 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1900 ac_to_float_type(&ctx->ac, def_type),
1901 result);
1902 }
1903 break;
1904 case nir_op_ffma:
1905 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1906 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1907 break;
1908 case nir_op_ibitfield_extract:
1909 result = emit_bitfield_extract(&ctx->ac, true, src);
1910 break;
1911 case nir_op_ubitfield_extract:
1912 result = emit_bitfield_extract(&ctx->ac, false, src);
1913 break;
1914 case nir_op_bitfield_insert:
1915 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1916 break;
1917 case nir_op_bitfield_reverse:
1918 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1919 break;
1920 case nir_op_bit_count:
1921 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1922 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1923 else {
1924 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1925 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1926 }
1927 break;
1928 case nir_op_vec2:
1929 case nir_op_vec3:
1930 case nir_op_vec4:
1931 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1932 src[i] = ac_to_integer(&ctx->ac, src[i]);
1933 result = ac_build_gather_values(&ctx->ac, src, num_components);
1934 break;
1935 case nir_op_f2i32:
1936 case nir_op_f2i64:
1937 src[0] = ac_to_float(&ctx->ac, src[0]);
1938 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1939 break;
1940 case nir_op_f2u32:
1941 case nir_op_f2u64:
1942 src[0] = ac_to_float(&ctx->ac, src[0]);
1943 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1944 break;
1945 case nir_op_i2f32:
1946 case nir_op_i2f64:
1947 src[0] = ac_to_integer(&ctx->ac, src[0]);
1948 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1949 break;
1950 case nir_op_u2f32:
1951 case nir_op_u2f64:
1952 src[0] = ac_to_integer(&ctx->ac, src[0]);
1953 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1954 break;
1955 case nir_op_f2f64:
1956 src[0] = ac_to_float(&ctx->ac, src[0]);
1957 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1958 break;
1959 case nir_op_f2f32:
1960 src[0] = ac_to_float(&ctx->ac, src[0]);
1961 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1962 break;
1963 case nir_op_u2u32:
1964 case nir_op_u2u64:
1965 src[0] = ac_to_integer(&ctx->ac, src[0]);
1966 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1967 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1968 else
1969 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1970 break;
1971 case nir_op_i2i32:
1972 case nir_op_i2i64:
1973 src[0] = ac_to_integer(&ctx->ac, src[0]);
1974 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1975 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1976 else
1977 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1978 break;
1979 case nir_op_bcsel:
1980 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1981 break;
1982 case nir_op_find_lsb:
1983 src[0] = ac_to_integer(&ctx->ac, src[0]);
1984 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1985 break;
1986 case nir_op_ufind_msb:
1987 src[0] = ac_to_integer(&ctx->ac, src[0]);
1988 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1989 break;
1990 case nir_op_ifind_msb:
1991 src[0] = ac_to_integer(&ctx->ac, src[0]);
1992 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1993 break;
1994 case nir_op_uadd_carry:
1995 src[0] = ac_to_integer(&ctx->ac, src[0]);
1996 src[1] = ac_to_integer(&ctx->ac, src[1]);
1997 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1998 break;
1999 case nir_op_usub_borrow:
2000 src[0] = ac_to_integer(&ctx->ac, src[0]);
2001 src[1] = ac_to_integer(&ctx->ac, src[1]);
2002 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
2003 break;
2004 case nir_op_b2f:
2005 result = emit_b2f(&ctx->ac, src[0]);
2006 break;
2007 case nir_op_f2b:
2008 result = emit_f2b(&ctx->ac, src[0]);
2009 break;
2010 case nir_op_b2i:
2011 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2012 break;
2013 case nir_op_i2b:
2014 src[0] = ac_to_integer(&ctx->ac, src[0]);
2015 result = emit_i2b(&ctx->ac, src[0]);
2016 break;
2017 case nir_op_fquantize2f16:
2018 result = emit_f2f16(&ctx->ac, src[0]);
2019 break;
2020 case nir_op_umul_high:
2021 src[0] = ac_to_integer(&ctx->ac, src[0]);
2022 src[1] = ac_to_integer(&ctx->ac, src[1]);
2023 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2024 break;
2025 case nir_op_imul_high:
2026 src[0] = ac_to_integer(&ctx->ac, src[0]);
2027 src[1] = ac_to_integer(&ctx->ac, src[1]);
2028 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2029 break;
2030 case nir_op_pack_half_2x16:
2031 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2032 break;
2033 case nir_op_unpack_half_2x16:
2034 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2035 break;
2036 case nir_op_fddx:
2037 case nir_op_fddy:
2038 case nir_op_fddx_fine:
2039 case nir_op_fddy_fine:
2040 case nir_op_fddx_coarse:
2041 case nir_op_fddy_coarse:
2042 result = emit_ddxy(ctx, instr->op, src[0]);
2043 break;
2044
2045 case nir_op_unpack_64_2x32_split_x: {
2046 assert(ac_get_llvm_num_components(src[0]) == 1);
2047 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2048 ctx->ac.v2i32,
2049 "");
2050 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2051 ctx->ac.i32_0, "");
2052 break;
2053 }
2054
2055 case nir_op_unpack_64_2x32_split_y: {
2056 assert(ac_get_llvm_num_components(src[0]) == 1);
2057 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2058 ctx->ac.v2i32,
2059 "");
2060 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2061 ctx->ac.i32_1, "");
2062 break;
2063 }
2064
2065 case nir_op_pack_64_2x32_split: {
2066 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2067 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2068 src[0], ctx->ac.i32_0, "");
2069 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2070 src[1], ctx->ac.i32_1, "");
2071 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2072 break;
2073 }
2074
2075 default:
2076 fprintf(stderr, "Unknown NIR alu instr: ");
2077 nir_print_instr(&instr->instr, stderr);
2078 fprintf(stderr, "\n");
2079 abort();
2080 }
2081
2082 if (result) {
2083 assert(instr->dest.dest.is_ssa);
2084 result = ac_to_integer(&ctx->ac, result);
2085 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2086 result);
2087 }
2088 }
2089
2090 static void visit_load_const(struct ac_nir_context *ctx,
2091 const nir_load_const_instr *instr)
2092 {
2093 LLVMValueRef values[4], value = NULL;
2094 LLVMTypeRef element_type =
2095 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2096
2097 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2098 switch (instr->def.bit_size) {
2099 case 32:
2100 values[i] = LLVMConstInt(element_type,
2101 instr->value.u32[i], false);
2102 break;
2103 case 64:
2104 values[i] = LLVMConstInt(element_type,
2105 instr->value.u64[i], false);
2106 break;
2107 default:
2108 fprintf(stderr,
2109 "unsupported nir load_const bit_size: %d\n",
2110 instr->def.bit_size);
2111 abort();
2112 }
2113 }
2114 if (instr->def.num_components > 1) {
2115 value = LLVMConstVector(values, instr->def.num_components);
2116 } else
2117 value = values[0];
2118
2119 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2120 }
2121
2122 static LLVMValueRef cast_ptr(struct ac_llvm_context *ctx, LLVMValueRef ptr,
2123 LLVMTypeRef type)
2124 {
2125 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2126 return LLVMBuildBitCast(ctx->builder, ptr,
2127 LLVMPointerType(type, addr_space), "");
2128 }
2129
2130 static LLVMValueRef
2131 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2132 {
2133 LLVMValueRef size =
2134 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2135 LLVMConstInt(ctx->ac.i32, 2, false), "");
2136
2137 /* VI only */
2138 if (ctx->ac.chip_class == VI && in_elements) {
2139 /* On VI, the descriptor contains the size in bytes,
2140 * but TXQ must return the size in elements.
2141 * The stride is always non-zero for resources using TXQ.
2142 */
2143 LLVMValueRef stride =
2144 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2145 ctx->ac.i32_1, "");
2146 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2147 LLVMConstInt(ctx->ac.i32, 16, false), "");
2148 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2149 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2150
2151 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2152 }
2153 return size;
2154 }
2155
2156 /**
2157 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2158 * intrinsic names).
2159 */
2160 static void build_int_type_name(
2161 LLVMTypeRef type,
2162 char *buf, unsigned bufsize)
2163 {
2164 assert(bufsize >= 6);
2165
2166 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2167 snprintf(buf, bufsize, "v%ui32",
2168 LLVMGetVectorSize(type));
2169 else
2170 strcpy(buf, "i32");
2171 }
2172
2173 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2174 struct ac_image_args *args,
2175 const nir_tex_instr *instr)
2176 {
2177 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2178 LLVMValueRef coord = args->addr;
2179 LLVMValueRef half_texel[2];
2180 LLVMValueRef compare_cube_wa = NULL;
2181 LLVMValueRef result;
2182 int c;
2183 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2184
2185 //TODO Rect
2186 {
2187 struct ac_image_args txq_args = { 0 };
2188
2189 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2190 txq_args.opcode = ac_image_get_resinfo;
2191 txq_args.dmask = 0xf;
2192 txq_args.addr = ctx->i32_0;
2193 txq_args.resource = args->resource;
2194 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2195
2196 for (c = 0; c < 2; c++) {
2197 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2198 LLVMConstInt(ctx->i32, c, false), "");
2199 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2200 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2201 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2202 LLVMConstReal(ctx->f32, -0.5), "");
2203 }
2204 }
2205
2206 LLVMValueRef orig_coords = args->addr;
2207
2208 for (c = 0; c < 2; c++) {
2209 LLVMValueRef tmp;
2210 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2211 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2212 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2213 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2214 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2215 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2216 }
2217
2218
2219 /*
2220 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2221 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2222 * workaround by sampling using a scaled type and converting.
2223 * This is taken from amdgpu-pro shaders.
2224 */
2225 /* NOTE this produces some ugly code compared to amdgpu-pro,
2226 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2227 * and then reads them back. -pro generates two selects,
2228 * one s_cmp for the descriptor rewriting
2229 * one v_cmp for the coordinate and result changes.
2230 */
2231 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2232 LLVMValueRef tmp, tmp2;
2233
2234 /* workaround 8/8/8/8 uint/sint cube gather bug */
2235 /* first detect it then change to a scaled read and f2i */
2236 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2237 tmp2 = tmp;
2238
2239 /* extract the DATA_FORMAT */
2240 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2241 LLVMConstInt(ctx->i32, 6, false), false);
2242
2243 /* is the DATA_FORMAT == 8_8_8_8 */
2244 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2245
2246 if (stype == GLSL_TYPE_UINT)
2247 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2248 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2249 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2250 else
2251 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2252 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2253 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2254
2255 /* replace the NUM FORMAT in the descriptor */
2256 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2257 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2258
2259 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2260
2261 /* don't modify the coordinates for this case */
2262 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2263 }
2264 args->addr = coord;
2265 result = ac_build_image_opcode(ctx, args);
2266
2267 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2268 LLVMValueRef tmp, tmp2;
2269
2270 /* if the cube workaround is in place, f2i the result. */
2271 for (c = 0; c < 4; c++) {
2272 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2273 if (stype == GLSL_TYPE_UINT)
2274 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2275 else
2276 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2277 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2278 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2279 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2280 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2281 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2282 }
2283 }
2284 return result;
2285 }
2286
2287 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2288 const nir_tex_instr *instr,
2289 bool lod_is_zero,
2290 struct ac_image_args *args)
2291 {
2292 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2293 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2294
2295 return ac_build_buffer_load_format(&ctx->ac,
2296 args->resource,
2297 args->addr,
2298 ctx->ac.i32_0,
2299 util_last_bit(mask),
2300 false, true);
2301 }
2302
2303 args->opcode = ac_image_sample;
2304 args->compare = instr->is_shadow;
2305
2306 switch (instr->op) {
2307 case nir_texop_txf:
2308 case nir_texop_txf_ms:
2309 case nir_texop_samples_identical:
2310 args->opcode = lod_is_zero ||
2311 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2312 ac_image_load : ac_image_load_mip;
2313 args->compare = false;
2314 args->offset = false;
2315 break;
2316 case nir_texop_txb:
2317 args->bias = true;
2318 break;
2319 case nir_texop_txl:
2320 if (lod_is_zero)
2321 args->level_zero = true;
2322 else
2323 args->lod = true;
2324 break;
2325 case nir_texop_txs:
2326 case nir_texop_query_levels:
2327 args->opcode = ac_image_get_resinfo;
2328 break;
2329 case nir_texop_tex:
2330 if (ctx->stage != MESA_SHADER_FRAGMENT)
2331 args->level_zero = true;
2332 break;
2333 case nir_texop_txd:
2334 args->deriv = true;
2335 break;
2336 case nir_texop_tg4:
2337 args->opcode = ac_image_gather4;
2338 args->level_zero = true;
2339 break;
2340 case nir_texop_lod:
2341 args->opcode = ac_image_get_lod;
2342 args->compare = false;
2343 args->offset = false;
2344 break;
2345 default:
2346 break;
2347 }
2348
2349 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2350 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2351 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2352 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2353 }
2354 }
2355 return ac_build_image_opcode(&ctx->ac, args);
2356 }
2357
2358 static LLVMValueRef
2359 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2360 unsigned desc_set, unsigned binding)
2361 {
2362 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2363 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2364 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2365 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2366 unsigned base_offset = layout->binding[binding].offset;
2367 LLVMValueRef offset, stride;
2368
2369 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2370 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2371 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2372 layout->binding[binding].dynamic_offset_offset;
2373 desc_ptr = ctx->abi.push_constants;
2374 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2375 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2376 } else
2377 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2378
2379 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2380 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
2381 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
2382
2383 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2384 desc_ptr = cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
2385 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2386
2387 return desc_ptr;
2388 }
2389
2390 static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
2391 nir_intrinsic_instr *instr)
2392 {
2393 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2394 LLVMValueRef index = get_src(ctx, instr->src[1]);
2395
2396 LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
2397 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2398 return result;
2399 }
2400
2401 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
2402 nir_intrinsic_instr *instr)
2403 {
2404 LLVMValueRef ptr, addr;
2405
2406 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2407 addr = LLVMBuildAdd(ctx->ac.builder, addr,
2408 get_src(ctx, instr->src[0]), "");
2409
2410 ptr = ac_build_gep0(&ctx->ac, ctx->abi->push_constants, addr);
2411 ptr = cast_ptr(&ctx->ac, ptr, get_def_type(ctx, &instr->dest.ssa));
2412
2413 return LLVMBuildLoad(ctx->ac.builder, ptr, "");
2414 }
2415
2416 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2417 const nir_intrinsic_instr *instr)
2418 {
2419 LLVMValueRef index = get_src(ctx, instr->src[0]);
2420
2421 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2422 }
2423
2424 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2425 {
2426 uint32_t new_mask = 0;
2427 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2428 if (mask & (1u << i))
2429 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2430 return new_mask;
2431 }
2432
2433 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2434 unsigned start, unsigned count)
2435 {
2436 LLVMTypeRef type = LLVMTypeOf(src);
2437
2438 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2439 assert(start == 0);
2440 assert(count == 1);
2441 return src;
2442 }
2443
2444 unsigned src_elements = LLVMGetVectorSize(type);
2445 assert(start < src_elements);
2446 assert(start + count <= src_elements);
2447
2448 if (start == 0 && count == src_elements)
2449 return src;
2450
2451 if (count == 1)
2452 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2453
2454 assert(count <= 8);
2455 LLVMValueRef indices[8];
2456 for (unsigned i = 0; i < count; ++i)
2457 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2458
2459 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2460 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2461 }
2462
2463 static void visit_store_ssbo(struct ac_nir_context *ctx,
2464 nir_intrinsic_instr *instr)
2465 {
2466 const char *store_name;
2467 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2468 LLVMTypeRef data_type = ctx->ac.f32;
2469 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2470 int components_32bit = elem_size_mult * instr->num_components;
2471 unsigned writemask = nir_intrinsic_write_mask(instr);
2472 LLVMValueRef base_data, base_offset;
2473 LLVMValueRef params[6];
2474
2475 params[1] = ctx->abi->load_ssbo(ctx->abi,
2476 get_src(ctx, instr->src[1]), true);
2477 params[2] = ctx->ac.i32_0; /* vindex */
2478 params[4] = ctx->ac.i1false; /* glc */
2479 params[5] = ctx->ac.i1false; /* slc */
2480
2481 if (components_32bit > 1)
2482 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2483
2484 writemask = widen_mask(writemask, elem_size_mult);
2485
2486 base_data = ac_to_float(&ctx->ac, src_data);
2487 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2488 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2489 data_type, "");
2490 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2491 while (writemask) {
2492 int start, count;
2493 LLVMValueRef data;
2494 LLVMValueRef offset;
2495
2496 u_bit_scan_consecutive_range(&writemask, &start, &count);
2497
2498 /* Due to an LLVM limitation, split 3-element writes
2499 * into a 2-element and a 1-element write. */
2500 if (count == 3) {
2501 writemask |= 1 << (start + 2);
2502 count = 2;
2503 }
2504
2505 if (count > 4) {
2506 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2507 count = 4;
2508 }
2509
2510 if (count == 4) {
2511 store_name = "llvm.amdgcn.buffer.store.v4f32";
2512 } else if (count == 2) {
2513 store_name = "llvm.amdgcn.buffer.store.v2f32";
2514
2515 } else {
2516 assert(count == 1);
2517 store_name = "llvm.amdgcn.buffer.store.f32";
2518 }
2519 data = extract_vector_range(&ctx->ac, base_data, start, count);
2520
2521 offset = base_offset;
2522 if (start != 0) {
2523 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2524 }
2525 params[0] = data;
2526 params[3] = offset;
2527 ac_build_intrinsic(&ctx->ac, store_name,
2528 ctx->ac.voidt, params, 6, 0);
2529 }
2530 }
2531
2532 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2533 const nir_intrinsic_instr *instr)
2534 {
2535 const char *name;
2536 LLVMValueRef params[6];
2537 int arg_count = 0;
2538
2539 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2540 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2541 }
2542 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2543 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2544 get_src(ctx, instr->src[0]),
2545 true);
2546 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2547 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2548 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2549
2550 switch (instr->intrinsic) {
2551 case nir_intrinsic_ssbo_atomic_add:
2552 name = "llvm.amdgcn.buffer.atomic.add";
2553 break;
2554 case nir_intrinsic_ssbo_atomic_imin:
2555 name = "llvm.amdgcn.buffer.atomic.smin";
2556 break;
2557 case nir_intrinsic_ssbo_atomic_umin:
2558 name = "llvm.amdgcn.buffer.atomic.umin";
2559 break;
2560 case nir_intrinsic_ssbo_atomic_imax:
2561 name = "llvm.amdgcn.buffer.atomic.smax";
2562 break;
2563 case nir_intrinsic_ssbo_atomic_umax:
2564 name = "llvm.amdgcn.buffer.atomic.umax";
2565 break;
2566 case nir_intrinsic_ssbo_atomic_and:
2567 name = "llvm.amdgcn.buffer.atomic.and";
2568 break;
2569 case nir_intrinsic_ssbo_atomic_or:
2570 name = "llvm.amdgcn.buffer.atomic.or";
2571 break;
2572 case nir_intrinsic_ssbo_atomic_xor:
2573 name = "llvm.amdgcn.buffer.atomic.xor";
2574 break;
2575 case nir_intrinsic_ssbo_atomic_exchange:
2576 name = "llvm.amdgcn.buffer.atomic.swap";
2577 break;
2578 case nir_intrinsic_ssbo_atomic_comp_swap:
2579 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2580 break;
2581 default:
2582 abort();
2583 }
2584
2585 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2586 }
2587
2588 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2589 const nir_intrinsic_instr *instr)
2590 {
2591 LLVMValueRef results[2];
2592 int load_components;
2593 int num_components = instr->num_components;
2594 if (instr->dest.ssa.bit_size == 64)
2595 num_components *= 2;
2596
2597 for (int i = 0; i < num_components; i += load_components) {
2598 load_components = MIN2(num_components - i, 4);
2599 const char *load_name;
2600 LLVMTypeRef data_type = ctx->ac.f32;
2601 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2602 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2603
2604 if (load_components == 3)
2605 data_type = LLVMVectorType(ctx->ac.f32, 4);
2606 else if (load_components > 1)
2607 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2608
2609 if (load_components >= 3)
2610 load_name = "llvm.amdgcn.buffer.load.v4f32";
2611 else if (load_components == 2)
2612 load_name = "llvm.amdgcn.buffer.load.v2f32";
2613 else if (load_components == 1)
2614 load_name = "llvm.amdgcn.buffer.load.f32";
2615 else
2616 unreachable("unhandled number of components");
2617
2618 LLVMValueRef params[] = {
2619 ctx->abi->load_ssbo(ctx->abi,
2620 get_src(ctx, instr->src[0]),
2621 false),
2622 ctx->ac.i32_0,
2623 offset,
2624 ctx->ac.i1false,
2625 ctx->ac.i1false,
2626 };
2627
2628 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2629 }
2630
2631 assume(results[0]);
2632 LLVMValueRef ret = results[0];
2633 if (num_components > 4 || num_components == 3) {
2634 LLVMValueRef masks[] = {
2635 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2636 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2637 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2638 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2639 };
2640
2641 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2642 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2643 results[num_components > 4 ? 1 : 0], swizzle, "");
2644 }
2645
2646 return LLVMBuildBitCast(ctx->ac.builder, ret,
2647 get_def_type(ctx, &instr->dest.ssa), "");
2648 }
2649
2650 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2651 const nir_intrinsic_instr *instr)
2652 {
2653 LLVMValueRef ret;
2654 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2655 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2656 int num_components = instr->num_components;
2657
2658 if (ctx->abi->load_ubo)
2659 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2660
2661 if (instr->dest.ssa.bit_size == 64)
2662 num_components *= 2;
2663
2664 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2665 NULL, 0, false, false, true, true);
2666 ret = trim_vector(&ctx->ac, ret, num_components);
2667 return LLVMBuildBitCast(ctx->ac.builder, ret,
2668 get_def_type(ctx, &instr->dest.ssa), "");
2669 }
2670
2671 static void
2672 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2673 bool vs_in, unsigned *vertex_index_out,
2674 LLVMValueRef *vertex_index_ref,
2675 unsigned *const_out, LLVMValueRef *indir_out)
2676 {
2677 unsigned const_offset = 0;
2678 nir_deref *tail = &deref->deref;
2679 LLVMValueRef offset = NULL;
2680
2681 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2682 tail = tail->child;
2683 nir_deref_array *deref_array = nir_deref_as_array(tail);
2684 if (vertex_index_out)
2685 *vertex_index_out = deref_array->base_offset;
2686
2687 if (vertex_index_ref) {
2688 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2689 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2690 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2691 }
2692 *vertex_index_ref = vtx;
2693 }
2694 }
2695
2696 if (deref->var->data.compact) {
2697 assert(tail->child->deref_type == nir_deref_type_array);
2698 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2699 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2700 /* We always lower indirect dereferences for "compact" array vars. */
2701 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2702
2703 const_offset = deref_array->base_offset;
2704 goto out;
2705 }
2706
2707 while (tail->child != NULL) {
2708 const struct glsl_type *parent_type = tail->type;
2709 tail = tail->child;
2710
2711 if (tail->deref_type == nir_deref_type_array) {
2712 nir_deref_array *deref_array = nir_deref_as_array(tail);
2713 LLVMValueRef index, stride, local_offset;
2714 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2715
2716 const_offset += size * deref_array->base_offset;
2717 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2718 continue;
2719
2720 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2721 index = get_src(ctx, deref_array->indirect);
2722 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2723 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2724
2725 if (offset)
2726 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2727 else
2728 offset = local_offset;
2729 } else if (tail->deref_type == nir_deref_type_struct) {
2730 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2731
2732 for (unsigned i = 0; i < deref_struct->index; i++) {
2733 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2734 const_offset += glsl_count_attribute_slots(ft, vs_in);
2735 }
2736 } else
2737 unreachable("unsupported deref type");
2738
2739 }
2740 out:
2741 if (const_offset && offset)
2742 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2743 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2744 "");
2745
2746 *const_out = const_offset;
2747 *indir_out = offset;
2748 }
2749
2750
2751 /* The offchip buffer layout for TCS->TES is
2752 *
2753 * - attribute 0 of patch 0 vertex 0
2754 * - attribute 0 of patch 0 vertex 1
2755 * - attribute 0 of patch 0 vertex 2
2756 * ...
2757 * - attribute 0 of patch 1 vertex 0
2758 * - attribute 0 of patch 1 vertex 1
2759 * ...
2760 * - attribute 1 of patch 0 vertex 0
2761 * - attribute 1 of patch 0 vertex 1
2762 * ...
2763 * - per patch attribute 0 of patch 0
2764 * - per patch attribute 0 of patch 1
2765 * ...
2766 *
2767 * Note that every attribute has 4 components.
2768 */
2769 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
2770 LLVMValueRef vertex_index,
2771 LLVMValueRef param_index)
2772 {
2773 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2774 LLVMValueRef param_stride, constant16;
2775 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2776
2777 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2778 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2779 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
2780 num_patches, "");
2781
2782 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2783 if (vertex_index) {
2784 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2785 vertices_per_patch, "");
2786
2787 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2788 vertex_index, "");
2789
2790 param_stride = total_vertices;
2791 } else {
2792 base_addr = rel_patch_id;
2793 param_stride = num_patches;
2794 }
2795
2796 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2797 LLVMBuildMul(ctx->ac.builder, param_index,
2798 param_stride, ""), "");
2799
2800 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
2801
2802 if (!vertex_index) {
2803 LLVMValueRef patch_data_offset =
2804 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2805
2806 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2807 patch_data_offset, "");
2808 }
2809 return base_addr;
2810 }
2811
2812 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
2813 unsigned param,
2814 unsigned const_index,
2815 bool is_compact,
2816 LLVMValueRef vertex_index,
2817 LLVMValueRef indir_index)
2818 {
2819 LLVMValueRef param_index;
2820
2821 if (indir_index)
2822 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
2823 indir_index, "");
2824 else {
2825 if (const_index && !is_compact)
2826 param += const_index;
2827 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2828 }
2829 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2830 }
2831
2832 static void
2833 mark_tess_output(struct radv_shader_context *ctx,
2834 bool is_patch, uint32_t param)
2835
2836 {
2837 if (is_patch) {
2838 ctx->tess_patch_outputs_written |= (1ull << param);
2839 } else
2840 ctx->tess_outputs_written |= (1ull << param);
2841 }
2842
2843 static LLVMValueRef
2844 get_dw_address(struct radv_shader_context *ctx,
2845 LLVMValueRef dw_addr,
2846 unsigned param,
2847 unsigned const_index,
2848 bool compact_const_index,
2849 LLVMValueRef vertex_index,
2850 LLVMValueRef stride,
2851 LLVMValueRef indir_index)
2852
2853 {
2854
2855 if (vertex_index) {
2856 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2857 LLVMBuildMul(ctx->ac.builder,
2858 vertex_index,
2859 stride, ""), "");
2860 }
2861
2862 if (indir_index)
2863 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2864 LLVMBuildMul(ctx->ac.builder, indir_index,
2865 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2866 else if (const_index && !compact_const_index)
2867 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2868 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2869
2870 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2871 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2872
2873 if (const_index && compact_const_index)
2874 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2875 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2876 return dw_addr;
2877 }
2878
2879 static LLVMValueRef
2880 load_tcs_varyings(struct ac_shader_abi *abi,
2881 LLVMValueRef vertex_index,
2882 LLVMValueRef indir_index,
2883 unsigned const_index,
2884 unsigned location,
2885 unsigned driver_location,
2886 unsigned component,
2887 unsigned num_components,
2888 bool is_patch,
2889 bool is_compact,
2890 bool load_input)
2891 {
2892 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2893 LLVMValueRef dw_addr, stride;
2894 LLVMValueRef value[4], result;
2895 unsigned param = shader_io_get_unique_index(location);
2896
2897 if (load_input) {
2898 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2899 dw_addr = get_tcs_in_current_patch_offset(ctx);
2900 } else {
2901 if (!is_patch) {
2902 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2903 dw_addr = get_tcs_out_current_patch_offset(ctx);
2904 } else {
2905 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2906 stride = NULL;
2907 }
2908 }
2909
2910 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2911 indir_index);
2912
2913 for (unsigned i = 0; i < num_components + component; i++) {
2914 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2915 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2916 ctx->ac.i32_1, "");
2917 }
2918 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2919 return result;
2920 }
2921
2922 static void
2923 store_tcs_output(struct ac_shader_abi *abi,
2924 LLVMValueRef vertex_index,
2925 LLVMValueRef param_index,
2926 unsigned const_index,
2927 unsigned location,
2928 unsigned driver_location,
2929 LLVMValueRef src,
2930 unsigned component,
2931 bool is_patch,
2932 bool is_compact,
2933 unsigned writemask)
2934 {
2935 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2936 LLVMValueRef dw_addr;
2937 LLVMValueRef stride = NULL;
2938 LLVMValueRef buf_addr = NULL;
2939 unsigned param;
2940 bool store_lds = true;
2941
2942 if (is_patch) {
2943 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2944 store_lds = false;
2945 } else {
2946 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2947 store_lds = false;
2948 }
2949
2950 param = shader_io_get_unique_index(location);
2951 if (location == VARYING_SLOT_CLIP_DIST0 &&
2952 is_compact && const_index > 3) {
2953 const_index -= 3;
2954 param++;
2955 }
2956
2957 if (!is_patch) {
2958 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2959 dw_addr = get_tcs_out_current_patch_offset(ctx);
2960 } else {
2961 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2962 }
2963
2964 mark_tess_output(ctx, is_patch, param);
2965
2966 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2967 param_index);
2968 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2969 vertex_index, param_index);
2970
2971 bool is_tess_factor = false;
2972 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2973 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2974 is_tess_factor = true;
2975
2976 unsigned base = is_compact ? const_index : 0;
2977 for (unsigned chan = 0; chan < 8; chan++) {
2978 if (!(writemask & (1 << chan)))
2979 continue;
2980 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2981
2982 if (store_lds || is_tess_factor) {
2983 LLVMValueRef dw_addr_chan =
2984 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2985 LLVMConstInt(ctx->ac.i32, chan, false), "");
2986 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2987 }
2988
2989 if (!is_tess_factor && writemask != 0xF)
2990 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2991 buf_addr, ctx->oc_lds,
2992 4 * (base + chan), 1, 0, true, false);
2993 }
2994
2995 if (writemask == 0xF) {
2996 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2997 buf_addr, ctx->oc_lds,
2998 (base * 4), 1, 0, true, false);
2999 }
3000 }
3001
3002 static LLVMValueRef
3003 load_tes_input(struct ac_shader_abi *abi,
3004 LLVMValueRef vertex_index,
3005 LLVMValueRef param_index,
3006 unsigned const_index,
3007 unsigned location,
3008 unsigned driver_location,
3009 unsigned component,
3010 unsigned num_components,
3011 bool is_patch,
3012 bool is_compact,
3013 bool load_input)
3014 {
3015 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3016 LLVMValueRef buf_addr;
3017 LLVMValueRef result;
3018 unsigned param = shader_io_get_unique_index(location);
3019
3020 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3021 const_index -= 3;
3022 param++;
3023 }
3024
3025 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3026 is_compact, vertex_index, param_index);
3027
3028 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3029 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
3030
3031 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3032 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3033 result = trim_vector(&ctx->ac, result, num_components);
3034 return result;
3035 }
3036
3037 static LLVMValueRef
3038 load_gs_input(struct ac_shader_abi *abi,
3039 unsigned location,
3040 unsigned driver_location,
3041 unsigned component,
3042 unsigned num_components,
3043 unsigned vertex_index,
3044 unsigned const_index,
3045 LLVMTypeRef type)
3046 {
3047 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3048 LLVMValueRef vtx_offset;
3049 unsigned param, vtx_offset_param;
3050 LLVMValueRef value[4], result;
3051
3052 vtx_offset_param = vertex_index;
3053 assert(vtx_offset_param < 6);
3054 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
3055 LLVMConstInt(ctx->ac.i32, 4, false), "");
3056
3057 param = shader_io_get_unique_index(location);
3058
3059 for (unsigned i = component; i < num_components + component; i++) {
3060 if (ctx->ac.chip_class >= GFX9) {
3061 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3062 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3063 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3064 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3065 } else {
3066 LLVMValueRef soffset =
3067 LLVMConstInt(ctx->ac.i32,
3068 (param * 4 + i + const_index) * 256,
3069 false);
3070
3071 value[i] = ac_build_buffer_load(&ctx->ac,
3072 ctx->esgs_ring, 1,
3073 ctx->ac.i32_0,
3074 vtx_offset, soffset,
3075 0, 1, 0, true, false);
3076
3077 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
3078 type, "");
3079 }
3080 }
3081 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3082 result = ac_to_integer(&ctx->ac, result);
3083 return result;
3084 }
3085
3086 static LLVMValueRef
3087 build_gep_for_deref(struct ac_nir_context *ctx,
3088 nir_deref_var *deref)
3089 {
3090 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3091 assert(entry->data);
3092 LLVMValueRef val = entry->data;
3093 nir_deref *tail = deref->deref.child;
3094 while (tail != NULL) {
3095 LLVMValueRef offset;
3096 switch (tail->deref_type) {
3097 case nir_deref_type_array: {
3098 nir_deref_array *array = nir_deref_as_array(tail);
3099 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3100 if (array->deref_array_type ==
3101 nir_deref_array_type_indirect) {
3102 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3103 get_src(ctx,
3104 array->indirect),
3105 "");
3106 }
3107 break;
3108 }
3109 case nir_deref_type_struct: {
3110 nir_deref_struct *deref_struct =
3111 nir_deref_as_struct(tail);
3112 offset = LLVMConstInt(ctx->ac.i32,
3113 deref_struct->index, 0);
3114 break;
3115 }
3116 default:
3117 unreachable("bad deref type");
3118 }
3119 val = ac_build_gep0(&ctx->ac, val, offset);
3120 tail = tail->child;
3121 }
3122 return val;
3123 }
3124
3125 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3126 nir_intrinsic_instr *instr,
3127 bool load_inputs)
3128 {
3129 LLVMValueRef result;
3130 LLVMValueRef vertex_index = NULL;
3131 LLVMValueRef indir_index = NULL;
3132 unsigned const_index = 0;
3133 unsigned location = instr->variables[0]->var->data.location;
3134 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3135 const bool is_patch = instr->variables[0]->var->data.patch;
3136 const bool is_compact = instr->variables[0]->var->data.compact;
3137
3138 get_deref_offset(ctx, instr->variables[0],
3139 false, NULL, is_patch ? NULL : &vertex_index,
3140 &const_index, &indir_index);
3141
3142 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3143 const_index, location, driver_location,
3144 instr->variables[0]->var->data.location_frac,
3145 instr->num_components,
3146 is_patch, is_compact, load_inputs);
3147 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3148 }
3149
3150 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3151 nir_intrinsic_instr *instr)
3152 {
3153 LLVMValueRef values[8];
3154 int idx = instr->variables[0]->var->data.driver_location;
3155 int ve = instr->dest.ssa.num_components;
3156 unsigned comp = instr->variables[0]->var->data.location_frac;
3157 LLVMValueRef indir_index;
3158 LLVMValueRef ret;
3159 unsigned const_index;
3160 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3161 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3162 instr->variables[0]->var->data.mode == nir_var_shader_in;
3163 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3164 &const_index, &indir_index);
3165
3166 if (instr->dest.ssa.bit_size == 64)
3167 ve *= 2;
3168
3169 switch (instr->variables[0]->var->data.mode) {
3170 case nir_var_shader_in:
3171 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3172 ctx->stage == MESA_SHADER_TESS_EVAL) {
3173 return load_tess_varyings(ctx, instr, true);
3174 }
3175
3176 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3177 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3178 LLVMValueRef indir_index;
3179 unsigned const_index, vertex_index;
3180 get_deref_offset(ctx, instr->variables[0],
3181 false, &vertex_index, NULL,
3182 &const_index, &indir_index);
3183
3184 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3185 instr->variables[0]->var->data.driver_location,
3186 instr->variables[0]->var->data.location_frac, ve,
3187 vertex_index, const_index, type);
3188 }
3189
3190 for (unsigned chan = comp; chan < ve + comp; chan++) {
3191 if (indir_index) {
3192 unsigned count = glsl_count_attribute_slots(
3193 instr->variables[0]->var->type,
3194 ctx->stage == MESA_SHADER_VERTEX);
3195 count -= chan / 4;
3196 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3197 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3198 stride, false, true);
3199
3200 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3201 tmp_vec,
3202 indir_index, "");
3203 } else
3204 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3205 }
3206 break;
3207 case nir_var_local:
3208 for (unsigned chan = 0; chan < ve; chan++) {
3209 if (indir_index) {
3210 unsigned count = glsl_count_attribute_slots(
3211 instr->variables[0]->var->type, false);
3212 count -= chan / 4;
3213 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3214 &ctx->ac, ctx->locals + idx + chan, count,
3215 stride, true, true);
3216
3217 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3218 tmp_vec,
3219 indir_index, "");
3220 } else {
3221 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3222 }
3223 }
3224 break;
3225 case nir_var_shared: {
3226 LLVMValueRef address = build_gep_for_deref(ctx,
3227 instr->variables[0]);
3228 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3229 return LLVMBuildBitCast(ctx->ac.builder, val,
3230 get_def_type(ctx, &instr->dest.ssa),
3231 "");
3232 }
3233 case nir_var_shader_out:
3234 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3235 return load_tess_varyings(ctx, instr, false);
3236 }
3237
3238 for (unsigned chan = comp; chan < ve + comp; chan++) {
3239 if (indir_index) {
3240 unsigned count = glsl_count_attribute_slots(
3241 instr->variables[0]->var->type, false);
3242 count -= chan / 4;
3243 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3244 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3245 stride, true, true);
3246
3247 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3248 tmp_vec,
3249 indir_index, "");
3250 } else {
3251 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3252 ctx->abi->outputs[idx + chan + const_index * stride],
3253 "");
3254 }
3255 }
3256 break;
3257 default:
3258 unreachable("unhandle variable mode");
3259 }
3260 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3261 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3262 }
3263
3264 static void
3265 visit_store_var(struct ac_nir_context *ctx,
3266 nir_intrinsic_instr *instr)
3267 {
3268 LLVMValueRef temp_ptr, value;
3269 int idx = instr->variables[0]->var->data.driver_location;
3270 unsigned comp = instr->variables[0]->var->data.location_frac;
3271 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3272 int writemask = instr->const_index[0] << comp;
3273 LLVMValueRef indir_index;
3274 unsigned const_index;
3275 get_deref_offset(ctx, instr->variables[0], false,
3276 NULL, NULL, &const_index, &indir_index);
3277
3278 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3279
3280 src = LLVMBuildBitCast(ctx->ac.builder, src,
3281 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3282 "");
3283
3284 writemask = widen_mask(writemask, 2);
3285 }
3286
3287 switch (instr->variables[0]->var->data.mode) {
3288 case nir_var_shader_out:
3289
3290 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3291 LLVMValueRef vertex_index = NULL;
3292 LLVMValueRef indir_index = NULL;
3293 unsigned const_index = 0;
3294 const unsigned location = instr->variables[0]->var->data.location;
3295 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3296 const unsigned comp = instr->variables[0]->var->data.location_frac;
3297 const bool is_patch = instr->variables[0]->var->data.patch;
3298 const bool is_compact = instr->variables[0]->var->data.compact;
3299
3300 get_deref_offset(ctx, instr->variables[0],
3301 false, NULL, is_patch ? NULL : &vertex_index,
3302 &const_index, &indir_index);
3303
3304 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3305 const_index, location, driver_location,
3306 src, comp, is_patch, is_compact, writemask);
3307 return;
3308 }
3309
3310 for (unsigned chan = 0; chan < 8; chan++) {
3311 int stride = 4;
3312 if (!(writemask & (1 << chan)))
3313 continue;
3314
3315 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3316
3317 if (instr->variables[0]->var->data.compact)
3318 stride = 1;
3319 if (indir_index) {
3320 unsigned count = glsl_count_attribute_slots(
3321 instr->variables[0]->var->type, false);
3322 count -= chan / 4;
3323 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3324 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3325 stride, true, true);
3326
3327 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3328 value, indir_index, "");
3329 build_store_values_extended(&ctx->ac, ctx->abi->outputs + idx + chan,
3330 count, stride, tmp_vec);
3331
3332 } else {
3333 temp_ptr = ctx->abi->outputs[idx + chan + const_index * stride];
3334
3335 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3336 }
3337 }
3338 break;
3339 case nir_var_local:
3340 for (unsigned chan = 0; chan < 8; chan++) {
3341 if (!(writemask & (1 << chan)))
3342 continue;
3343
3344 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3345 if (indir_index) {
3346 unsigned count = glsl_count_attribute_slots(
3347 instr->variables[0]->var->type, false);
3348 count -= chan / 4;
3349 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3350 &ctx->ac, ctx->locals + idx + chan, count,
3351 4, true, true);
3352
3353 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3354 value, indir_index, "");
3355 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3356 count, 4, tmp_vec);
3357 } else {
3358 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3359
3360 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3361 }
3362 }
3363 break;
3364 case nir_var_shared: {
3365 int writemask = instr->const_index[0];
3366 LLVMValueRef address = build_gep_for_deref(ctx,
3367 instr->variables[0]);
3368 LLVMValueRef val = get_src(ctx, instr->src[0]);
3369 unsigned components =
3370 glsl_get_vector_elements(
3371 nir_deref_tail(&instr->variables[0]->deref)->type);
3372 if (writemask == (1 << components) - 1) {
3373 val = LLVMBuildBitCast(
3374 ctx->ac.builder, val,
3375 LLVMGetElementType(LLVMTypeOf(address)), "");
3376 LLVMBuildStore(ctx->ac.builder, val, address);
3377 } else {
3378 for (unsigned chan = 0; chan < 4; chan++) {
3379 if (!(writemask & (1 << chan)))
3380 continue;
3381 LLVMValueRef ptr =
3382 LLVMBuildStructGEP(ctx->ac.builder,
3383 address, chan, "");
3384 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3385 chan);
3386 src = LLVMBuildBitCast(
3387 ctx->ac.builder, src,
3388 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3389 LLVMBuildStore(ctx->ac.builder, src, ptr);
3390 }
3391 }
3392 break;
3393 }
3394 default:
3395 break;
3396 }
3397 }
3398
3399 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3400 {
3401 switch (dim) {
3402 case GLSL_SAMPLER_DIM_BUF:
3403 return 1;
3404 case GLSL_SAMPLER_DIM_1D:
3405 return array ? 2 : 1;
3406 case GLSL_SAMPLER_DIM_2D:
3407 return array ? 3 : 2;
3408 case GLSL_SAMPLER_DIM_MS:
3409 return array ? 4 : 3;
3410 case GLSL_SAMPLER_DIM_3D:
3411 case GLSL_SAMPLER_DIM_CUBE:
3412 return 3;
3413 case GLSL_SAMPLER_DIM_RECT:
3414 case GLSL_SAMPLER_DIM_SUBPASS:
3415 return 2;
3416 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3417 return 3;
3418 default:
3419 break;
3420 }
3421 return 0;
3422 }
3423
3424
3425
3426 /* Adjust the sample index according to FMASK.
3427 *
3428 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3429 * which is the identity mapping. Each nibble says which physical sample
3430 * should be fetched to get that sample.
3431 *
3432 * For example, 0x11111100 means there are only 2 samples stored and
3433 * the second sample covers 3/4 of the pixel. When reading samples 0
3434 * and 1, return physical sample 0 (determined by the first two 0s
3435 * in FMASK), otherwise return physical sample 1.
3436 *
3437 * The sample index should be adjusted as follows:
3438 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3439 */
3440 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3441 LLVMValueRef coord_x, LLVMValueRef coord_y,
3442 LLVMValueRef coord_z,
3443 LLVMValueRef sample_index,
3444 LLVMValueRef fmask_desc_ptr)
3445 {
3446 LLVMValueRef fmask_load_address[4];
3447 LLVMValueRef res;
3448
3449 fmask_load_address[0] = coord_x;
3450 fmask_load_address[1] = coord_y;
3451 if (coord_z) {
3452 fmask_load_address[2] = coord_z;
3453 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3454 }
3455
3456 struct ac_image_args args = {0};
3457
3458 args.opcode = ac_image_load;
3459 args.da = coord_z ? true : false;
3460 args.resource = fmask_desc_ptr;
3461 args.dmask = 0xf;
3462 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3463
3464 res = ac_build_image_opcode(ctx, &args);
3465
3466 res = ac_to_integer(ctx, res);
3467 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3468 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3469
3470 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3471 res,
3472 ctx->i32_0, "");
3473
3474 LLVMValueRef sample_index4 =
3475 LLVMBuildMul(ctx->builder, sample_index, four, "");
3476 LLVMValueRef shifted_fmask =
3477 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3478 LLVMValueRef final_sample =
3479 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3480
3481 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3482 * resource descriptor is 0 (invalid),
3483 */
3484 LLVMValueRef fmask_desc =
3485 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3486 ctx->v8i32, "");
3487
3488 LLVMValueRef fmask_word1 =
3489 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3490 ctx->i32_1, "");
3491
3492 LLVMValueRef word1_is_nonzero =
3493 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3494 fmask_word1, ctx->i32_0, "");
3495
3496 /* Replace the MSAA sample index. */
3497 sample_index =
3498 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3499 final_sample, sample_index, "");
3500 return sample_index;
3501 }
3502
3503 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3504 const nir_intrinsic_instr *instr)
3505 {
3506 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3507
3508 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3509 LLVMValueRef coords[4];
3510 LLVMValueRef masks[] = {
3511 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3512 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3513 };
3514 LLVMValueRef res;
3515 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3516
3517 int count;
3518 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3519 bool is_array = glsl_sampler_type_is_array(type);
3520 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3521 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3522 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3523 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3524 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3525 count = image_type_to_components_count(dim, is_array);
3526
3527 if (is_ms) {
3528 LLVMValueRef fmask_load_address[3];
3529 int chan;
3530
3531 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3532 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3533 if (is_array)
3534 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3535 else
3536 fmask_load_address[2] = NULL;
3537 if (add_frag_pos) {
3538 for (chan = 0; chan < 2; ++chan)
3539 fmask_load_address[chan] =
3540 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3541 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3542 ctx->ac.i32, ""), "");
3543 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3544 }
3545 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3546 fmask_load_address[0],
3547 fmask_load_address[1],
3548 fmask_load_address[2],
3549 sample_index,
3550 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3551 }
3552 if (count == 1 && !gfx9_1d) {
3553 if (instr->src[0].ssa->num_components)
3554 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3555 else
3556 res = src0;
3557 } else {
3558 int chan;
3559 if (is_ms)
3560 count--;
3561 for (chan = 0; chan < count; ++chan) {
3562 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3563 }
3564 if (add_frag_pos) {
3565 for (chan = 0; chan < 2; ++chan)
3566 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3567 ctx->ac.i32, ""), "");
3568 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3569 count++;
3570 }
3571
3572 if (gfx9_1d) {
3573 if (is_array) {
3574 coords[2] = coords[1];
3575 coords[1] = ctx->ac.i32_0;
3576 } else
3577 coords[1] = ctx->ac.i32_0;
3578 count++;
3579 }
3580
3581 if (is_ms) {
3582 coords[count] = sample_index;
3583 count++;
3584 }
3585
3586 if (count == 3) {
3587 coords[3] = LLVMGetUndef(ctx->ac.i32);
3588 count = 4;
3589 }
3590 res = ac_build_gather_values(&ctx->ac, coords, count);
3591 }
3592 return res;
3593 }
3594
3595 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3596 const nir_intrinsic_instr *instr)
3597 {
3598 LLVMValueRef params[7];
3599 LLVMValueRef res;
3600 char intrinsic_name[64];
3601 const nir_variable *var = instr->variables[0]->var;
3602 const struct glsl_type *type = var->type;
3603
3604 if(instr->variables[0]->deref.child)
3605 type = instr->variables[0]->deref.child->type;
3606
3607 type = glsl_without_array(type);
3608
3609 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3610 if (dim == GLSL_SAMPLER_DIM_BUF) {
3611 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3612 unsigned num_channels = util_last_bit(mask);
3613 LLVMValueRef rsrc, vindex;
3614
3615 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3616 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3617 ctx->ac.i32_0, "");
3618
3619 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3620 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3621 ctx->ac.i32_0, num_channels,
3622 false, false);
3623 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3624
3625 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3626 res = ac_to_integer(&ctx->ac, res);
3627 } else {
3628 bool is_da = glsl_sampler_type_is_array(type) ||
3629 dim == GLSL_SAMPLER_DIM_CUBE ||
3630 dim == GLSL_SAMPLER_DIM_3D ||
3631 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3632 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3633 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3634 LLVMValueRef glc = ctx->ac.i1false;
3635 LLVMValueRef slc = ctx->ac.i1false;
3636
3637 params[0] = get_image_coords(ctx, instr);
3638 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3639 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3640 params[3] = glc;
3641 params[4] = slc;
3642 params[5] = ctx->ac.i1false;
3643 params[6] = da;
3644
3645 ac_get_image_intr_name("llvm.amdgcn.image.load",
3646 ctx->ac.v4f32, /* vdata */
3647 LLVMTypeOf(params[0]), /* coords */
3648 LLVMTypeOf(params[1]), /* rsrc */
3649 intrinsic_name, sizeof(intrinsic_name));
3650
3651 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3652 params, 7, AC_FUNC_ATTR_READONLY);
3653 }
3654 return ac_to_integer(&ctx->ac, res);
3655 }
3656
3657 static void visit_image_store(struct ac_nir_context *ctx,
3658 nir_intrinsic_instr *instr)
3659 {
3660 LLVMValueRef params[8];
3661 char intrinsic_name[64];
3662 const nir_variable *var = instr->variables[0]->var;
3663 const struct glsl_type *type = glsl_without_array(var->type);
3664 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3665 LLVMValueRef glc = ctx->ac.i1false;
3666 bool force_glc = ctx->ac.chip_class == SI;
3667 if (force_glc)
3668 glc = ctx->ac.i1true;
3669
3670 if (dim == GLSL_SAMPLER_DIM_BUF) {
3671 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3672 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3673 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3674 ctx->ac.i32_0, ""); /* vindex */
3675 params[3] = ctx->ac.i32_0; /* voffset */
3676 params[4] = glc; /* glc */
3677 params[5] = ctx->ac.i1false; /* slc */
3678 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3679 params, 6, 0);
3680 } else {
3681 bool is_da = glsl_sampler_type_is_array(type) ||
3682 dim == GLSL_SAMPLER_DIM_CUBE ||
3683 dim == GLSL_SAMPLER_DIM_3D;
3684 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3685 LLVMValueRef slc = ctx->ac.i1false;
3686
3687 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3688 params[1] = get_image_coords(ctx, instr); /* coords */
3689 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3690 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3691 params[4] = glc;
3692 params[5] = slc;
3693 params[6] = ctx->ac.i1false;
3694 params[7] = da;
3695
3696 ac_get_image_intr_name("llvm.amdgcn.image.store",
3697 LLVMTypeOf(params[0]), /* vdata */
3698 LLVMTypeOf(params[1]), /* coords */
3699 LLVMTypeOf(params[2]), /* rsrc */
3700 intrinsic_name, sizeof(intrinsic_name));
3701
3702 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3703 params, 8, 0);
3704 }
3705
3706 }
3707
3708 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3709 const nir_intrinsic_instr *instr)
3710 {
3711 LLVMValueRef params[7];
3712 int param_count = 0;
3713 const nir_variable *var = instr->variables[0]->var;
3714
3715 const char *atomic_name;
3716 char intrinsic_name[41];
3717 const struct glsl_type *type = glsl_without_array(var->type);
3718 MAYBE_UNUSED int length;
3719
3720 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3721
3722 switch (instr->intrinsic) {
3723 case nir_intrinsic_image_atomic_add:
3724 atomic_name = "add";
3725 break;
3726 case nir_intrinsic_image_atomic_min:
3727 atomic_name = is_unsigned ? "umin" : "smin";
3728 break;
3729 case nir_intrinsic_image_atomic_max:
3730 atomic_name = is_unsigned ? "umax" : "smax";
3731 break;
3732 case nir_intrinsic_image_atomic_and:
3733 atomic_name = "and";
3734 break;
3735 case nir_intrinsic_image_atomic_or:
3736 atomic_name = "or";
3737 break;
3738 case nir_intrinsic_image_atomic_xor:
3739 atomic_name = "xor";
3740 break;
3741 case nir_intrinsic_image_atomic_exchange:
3742 atomic_name = "swap";
3743 break;
3744 case nir_intrinsic_image_atomic_comp_swap:
3745 atomic_name = "cmpswap";
3746 break;
3747 default:
3748 abort();
3749 }
3750
3751 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3752 params[param_count++] = get_src(ctx, instr->src[3]);
3753 params[param_count++] = get_src(ctx, instr->src[2]);
3754
3755 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3756 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3757 NULL, true, true);
3758 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3759 ctx->ac.i32_0, ""); /* vindex */
3760 params[param_count++] = ctx->ac.i32_0; /* voffset */
3761 params[param_count++] = ctx->ac.i1false; /* slc */
3762
3763 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3764 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3765 } else {
3766 char coords_type[8];
3767
3768 bool da = glsl_sampler_type_is_array(type) ||
3769 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3770
3771 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3772 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3773 NULL, true, true);
3774 params[param_count++] = ctx->ac.i1false; /* r128 */
3775 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3776 params[param_count++] = ctx->ac.i1false; /* slc */
3777
3778 build_int_type_name(LLVMTypeOf(coords),
3779 coords_type, sizeof(coords_type));
3780
3781 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3782 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3783 }
3784
3785 assert(length < sizeof(intrinsic_name));
3786 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3787 }
3788
3789 static LLVMValueRef visit_image_samples(struct ac_nir_context *ctx,
3790 const nir_intrinsic_instr *instr)
3791 {
3792 const nir_variable *var = instr->variables[0]->var;
3793 const struct glsl_type *type = glsl_without_array(var->type);
3794 bool da = glsl_sampler_type_is_array(type) ||
3795 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3796 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_3D;
3797
3798 struct ac_image_args args = { 0 };
3799 args.da = da;
3800 args.dmask = 0xf;
3801 args.resource = get_sampler_desc(ctx, instr->variables[0],
3802 AC_DESC_IMAGE, NULL, true, false);
3803 args.opcode = ac_image_get_resinfo;
3804 args.addr = ctx->ac.i32_0;
3805
3806 return ac_build_image_opcode(&ctx->ac, &args);
3807 }
3808
3809 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3810 const nir_intrinsic_instr *instr)
3811 {
3812 LLVMValueRef res;
3813 const nir_variable *var = instr->variables[0]->var;
3814 const struct glsl_type *type = glsl_without_array(var->type);
3815 bool da = glsl_sampler_type_is_array(type) ||
3816 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3817 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_3D;
3818
3819 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3820 return get_buffer_size(ctx,
3821 get_sampler_desc(ctx, instr->variables[0],
3822 AC_DESC_BUFFER, NULL, true, false), true);
3823
3824 struct ac_image_args args = { 0 };
3825
3826 args.da = da;
3827 args.dmask = 0xf;
3828 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3829 args.opcode = ac_image_get_resinfo;
3830 args.addr = ctx->ac.i32_0;
3831
3832 res = ac_build_image_opcode(&ctx->ac, &args);
3833
3834 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3835
3836 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3837 glsl_sampler_type_is_array(type)) {
3838 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3839 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3840 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3841 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3842 }
3843 if (ctx->ac.chip_class >= GFX9 &&
3844 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3845 glsl_sampler_type_is_array(type)) {
3846 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3847 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3848 ctx->ac.i32_1, "");
3849
3850 }
3851 return res;
3852 }
3853
3854 #define NOOP_WAITCNT 0xf7f
3855 #define LGKM_CNT 0x07f
3856 #define VM_CNT 0xf70
3857
3858 static void emit_membar(struct ac_llvm_context *ac,
3859 const nir_intrinsic_instr *instr)
3860 {
3861 unsigned waitcnt = NOOP_WAITCNT;
3862
3863 switch (instr->intrinsic) {
3864 case nir_intrinsic_memory_barrier:
3865 case nir_intrinsic_group_memory_barrier:
3866 waitcnt &= VM_CNT & LGKM_CNT;
3867 break;
3868 case nir_intrinsic_memory_barrier_atomic_counter:
3869 case nir_intrinsic_memory_barrier_buffer:
3870 case nir_intrinsic_memory_barrier_image:
3871 waitcnt &= VM_CNT;
3872 break;
3873 case nir_intrinsic_memory_barrier_shared:
3874 waitcnt &= LGKM_CNT;
3875 break;
3876 default:
3877 break;
3878 }
3879 if (waitcnt != NOOP_WAITCNT)
3880 ac_build_waitcnt(ac, waitcnt);
3881 }
3882
3883 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3884 {
3885 /* SI only (thanks to a hw bug workaround):
3886 * The real barrier instruction isn’t needed, because an entire patch
3887 * always fits into a single wave.
3888 */
3889 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3890 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3891 return;
3892 }
3893 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3894 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3895 }
3896
3897 static void emit_discard(struct ac_nir_context *ctx,
3898 const nir_intrinsic_instr *instr)
3899 {
3900 LLVMValueRef cond;
3901
3902 if (instr->intrinsic == nir_intrinsic_discard_if) {
3903 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3904 get_src(ctx, instr->src[0]),
3905 ctx->ac.i32_0, "");
3906 } else {
3907 assert(instr->intrinsic == nir_intrinsic_discard);
3908 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3909 }
3910
3911 ac_build_kill_if_false(&ctx->ac, cond);
3912 }
3913
3914 static LLVMValueRef
3915 visit_load_helper_invocation(struct ac_nir_context *ctx)
3916 {
3917 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3918 "llvm.amdgcn.ps.live",
3919 ctx->ac.i1, NULL, 0,
3920 AC_FUNC_ATTR_READNONE);
3921 result = LLVMBuildNot(ctx->ac.builder, result, "");
3922 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3923 }
3924
3925 static LLVMValueRef
3926 visit_load_local_invocation_index(struct ac_nir_context *ctx)
3927 {
3928 LLVMValueRef result;
3929 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3930 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3931 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3932
3933 return LLVMBuildAdd(ctx->ac.builder, result, thread_id, "");
3934 }
3935
3936 static LLVMValueRef
3937 visit_load_shared(struct ac_nir_context *ctx,
3938 const nir_intrinsic_instr *instr)
3939 {
3940 LLVMValueRef values[4], derived_ptr, index, ret;
3941
3942 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
3943
3944 for (int chan = 0; chan < instr->num_components; chan++) {
3945 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3946 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
3947 values[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
3948 }
3949
3950 ret = ac_build_gather_values(&ctx->ac, values, instr->num_components);
3951 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3952 }
3953
3954 static void
3955 visit_store_shared(struct ac_nir_context *ctx,
3956 const nir_intrinsic_instr *instr)
3957 {
3958 LLVMValueRef derived_ptr, data,index;
3959 LLVMBuilderRef builder = ctx->ac.builder;
3960
3961 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
3962 LLVMValueRef src = get_src(ctx, instr->src[0]);
3963
3964 int writemask = nir_intrinsic_write_mask(instr);
3965 for (int chan = 0; chan < 4; chan++) {
3966 if (!(writemask & (1 << chan))) {
3967 continue;
3968 }
3969 data = ac_llvm_extract_elem(&ctx->ac, src, chan);
3970 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3971 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3972 LLVMBuildStore(builder, data, derived_ptr);
3973 }
3974 }
3975
3976 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
3977 const nir_intrinsic_instr *instr,
3978 LLVMValueRef ptr)
3979 {
3980 LLVMValueRef result;
3981 LLVMValueRef src = get_src(ctx, instr->src[0]);
3982
3983 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
3984 instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
3985 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3986 result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
3987 ptr, src, src1,
3988 LLVMAtomicOrderingSequentiallyConsistent,
3989 LLVMAtomicOrderingSequentiallyConsistent,
3990 false);
3991 } else {
3992 LLVMAtomicRMWBinOp op;
3993 switch (instr->intrinsic) {
3994 case nir_intrinsic_var_atomic_add:
3995 case nir_intrinsic_shared_atomic_add:
3996 op = LLVMAtomicRMWBinOpAdd;
3997 break;
3998 case nir_intrinsic_var_atomic_umin:
3999 case nir_intrinsic_shared_atomic_umin:
4000 op = LLVMAtomicRMWBinOpUMin;
4001 break;
4002 case nir_intrinsic_var_atomic_umax:
4003 case nir_intrinsic_shared_atomic_umax:
4004 op = LLVMAtomicRMWBinOpUMax;
4005 break;
4006 case nir_intrinsic_var_atomic_imin:
4007 case nir_intrinsic_shared_atomic_imin:
4008 op = LLVMAtomicRMWBinOpMin;
4009 break;
4010 case nir_intrinsic_var_atomic_imax:
4011 case nir_intrinsic_shared_atomic_imax:
4012 op = LLVMAtomicRMWBinOpMax;
4013 break;
4014 case nir_intrinsic_var_atomic_and:
4015 case nir_intrinsic_shared_atomic_and:
4016 op = LLVMAtomicRMWBinOpAnd;
4017 break;
4018 case nir_intrinsic_var_atomic_or:
4019 case nir_intrinsic_shared_atomic_or:
4020 op = LLVMAtomicRMWBinOpOr;
4021 break;
4022 case nir_intrinsic_var_atomic_xor:
4023 case nir_intrinsic_shared_atomic_xor:
4024 op = LLVMAtomicRMWBinOpXor;
4025 break;
4026 case nir_intrinsic_var_atomic_exchange:
4027 case nir_intrinsic_shared_atomic_exchange:
4028 op = LLVMAtomicRMWBinOpXchg;
4029 break;
4030 default:
4031 return NULL;
4032 }
4033
4034 result = LLVMBuildAtomicRMW(ctx->ac.builder, op, ptr, ac_to_integer(&ctx->ac, src),
4035 LLVMAtomicOrderingSequentiallyConsistent,
4036 false);
4037 }
4038 return result;
4039 }
4040
4041 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
4042 enum glsl_interp_mode interp, unsigned location)
4043 {
4044 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4045
4046 switch (interp) {
4047 case INTERP_MODE_FLAT:
4048 default:
4049 return NULL;
4050 case INTERP_MODE_SMOOTH:
4051 case INTERP_MODE_NONE:
4052 if (location == INTERP_CENTER)
4053 return ctx->persp_center;
4054 else if (location == INTERP_CENTROID)
4055 return ctx->persp_centroid;
4056 else if (location == INTERP_SAMPLE)
4057 return ctx->persp_sample;
4058 break;
4059 case INTERP_MODE_NOPERSPECTIVE:
4060 if (location == INTERP_CENTER)
4061 return ctx->linear_center;
4062 else if (location == INTERP_CENTROID)
4063 return ctx->linear_centroid;
4064 else if (location == INTERP_SAMPLE)
4065 return ctx->linear_sample;
4066 break;
4067 }
4068 return NULL;
4069 }
4070
4071 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
4072 LLVMValueRef sample_id)
4073 {
4074 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4075
4076 LLVMValueRef result;
4077 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4078
4079 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
4080 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4081
4082 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
4083 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4084
4085 return result;
4086 }
4087
4088 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4089 {
4090 LLVMValueRef values[2];
4091
4092 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0], 32);
4093 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1], 32);
4094 return ac_build_gather_values(&ctx->ac, values, 2);
4095 }
4096
4097 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4098 {
4099 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4100 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4101 ctx->options->key.fs.log2_num_samples :
4102 ctx->options->key.fs.log2_ps_iter_samples;
4103
4104 /* The bit pattern matches that used by fixed function fragment
4105 * processing. */
4106 static const uint16_t ps_iter_masks[] = {
4107 0xffff, /* not used */
4108 0x5555,
4109 0x1111,
4110 0x0101,
4111 0x0001,
4112 };
4113 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4114
4115 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4116
4117 LLVMValueRef result, sample_id;
4118 sample_id = unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4119 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4120 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4121 return result;
4122 }
4123
4124 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4125 const nir_intrinsic_instr *instr)
4126 {
4127 LLVMValueRef result[4];
4128 LLVMValueRef interp_param, attr_number;
4129 unsigned location;
4130 unsigned chan;
4131 LLVMValueRef src_c0 = NULL;
4132 LLVMValueRef src_c1 = NULL;
4133 LLVMValueRef src0 = NULL;
4134 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4135 switch (instr->intrinsic) {
4136 case nir_intrinsic_interp_var_at_centroid:
4137 location = INTERP_CENTROID;
4138 break;
4139 case nir_intrinsic_interp_var_at_sample:
4140 case nir_intrinsic_interp_var_at_offset:
4141 location = INTERP_CENTER;
4142 src0 = get_src(ctx, instr->src[0]);
4143 break;
4144 default:
4145 break;
4146 }
4147
4148 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4149 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4150 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4151 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4152 LLVMValueRef sample_position;
4153 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4154
4155 /* fetch sample ID */
4156 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4157
4158 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4159 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4160 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4161 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4162 }
4163 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4164 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4165
4166 if (location == INTERP_CENTER) {
4167 LLVMValueRef ij_out[2];
4168 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4169
4170 /*
4171 * take the I then J parameters, and the DDX/Y for it, and
4172 * calculate the IJ inputs for the interpolator.
4173 * temp1 = ddx * offset/sample.x + I;
4174 * interp_param.I = ddy * offset/sample.y + temp1;
4175 * temp1 = ddx * offset/sample.x + J;
4176 * interp_param.J = ddy * offset/sample.y + temp1;
4177 */
4178 for (unsigned i = 0; i < 2; i++) {
4179 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4180 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4181 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4182 ddxy_out, ix_ll, "");
4183 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4184 ddxy_out, iy_ll, "");
4185 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4186 interp_param, ix_ll, "");
4187 LLVMValueRef temp1, temp2;
4188
4189 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4190 ctx->ac.f32, "");
4191
4192 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4193 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4194
4195 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4196 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4197
4198 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4199 temp2, ctx->ac.i32, "");
4200 }
4201 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4202
4203 }
4204
4205 for (chan = 0; chan < 4; chan++) {
4206 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4207
4208 if (interp_param) {
4209 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4210 interp_param, ctx->ac.v2f32, "");
4211 LLVMValueRef i = LLVMBuildExtractElement(
4212 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4213 LLVMValueRef j = LLVMBuildExtractElement(
4214 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4215
4216 result[chan] = ac_build_fs_interp(&ctx->ac,
4217 llvm_chan, attr_number,
4218 ctx->abi->prim_mask, i, j);
4219 } else {
4220 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4221 LLVMConstInt(ctx->ac.i32, 2, false),
4222 llvm_chan, attr_number,
4223 ctx->abi->prim_mask);
4224 }
4225 }
4226 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4227 instr->variables[0]->var->data.location_frac);
4228 }
4229
4230 static void
4231 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4232 {
4233 LLVMValueRef gs_next_vertex;
4234 LLVMValueRef can_emit;
4235 int idx;
4236 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4237
4238 assert(stream == 0);
4239
4240 /* Write vertex attribute values to GSVS ring */
4241 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4242 ctx->gs_next_vertex,
4243 "");
4244
4245 /* If this thread has already emitted the declared maximum number of
4246 * vertices, kill it: excessive vertex emissions are not supposed to
4247 * have any effect, and GS threads have no externally observable
4248 * effects other than emitting vertices.
4249 */
4250 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4251 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4252 ac_build_kill_if_false(&ctx->ac, can_emit);
4253
4254 /* loop num outputs */
4255 idx = 0;
4256 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4257 LLVMValueRef *out_ptr = &addrs[i * 4];
4258 int length = 4;
4259 int slot = idx;
4260 int slot_inc = 1;
4261
4262 if (!(ctx->output_mask & (1ull << i)))
4263 continue;
4264
4265 if (i == VARYING_SLOT_CLIP_DIST0) {
4266 /* pack clip and cull into a single set of slots */
4267 length = ctx->num_output_clips + ctx->num_output_culls;
4268 if (length > 4)
4269 slot_inc = 2;
4270 }
4271 for (unsigned j = 0; j < length; j++) {
4272 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4273 out_ptr[j], "");
4274 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4275 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4276 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4277
4278 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4279
4280 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4281 out_val, 1,
4282 voffset, ctx->gs2vs_offset, 0,
4283 1, 1, true, true);
4284 }
4285 idx += slot_inc;
4286 }
4287
4288 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
4289 ctx->ac.i32_1, "");
4290 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
4291
4292 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4293 }
4294
4295 static void
4296 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4297 {
4298 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4299 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4300 }
4301
4302 static LLVMValueRef
4303 load_tess_coord(struct ac_shader_abi *abi)
4304 {
4305 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4306
4307 LLVMValueRef coord[4] = {
4308 ctx->tes_u,
4309 ctx->tes_v,
4310 ctx->ac.f32_0,
4311 ctx->ac.f32_0,
4312 };
4313
4314 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4315 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
4316 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
4317
4318 return ac_build_gather_values(&ctx->ac, coord, 3);
4319 }
4320
4321 static LLVMValueRef
4322 load_patch_vertices_in(struct ac_shader_abi *abi)
4323 {
4324 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4325 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4326 }
4327
4328 static void visit_intrinsic(struct ac_nir_context *ctx,
4329 nir_intrinsic_instr *instr)
4330 {
4331 LLVMValueRef result = NULL;
4332
4333 switch (instr->intrinsic) {
4334 case nir_intrinsic_ballot:
4335 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4336 break;
4337 case nir_intrinsic_read_invocation:
4338 case nir_intrinsic_read_first_invocation: {
4339 LLVMValueRef args[2];
4340
4341 /* Value */
4342 args[0] = get_src(ctx, instr->src[0]);
4343
4344 unsigned num_args;
4345 const char *intr_name;
4346 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4347 num_args = 2;
4348 intr_name = "llvm.amdgcn.readlane";
4349
4350 /* Invocation */
4351 args[1] = get_src(ctx, instr->src[1]);
4352 } else {
4353 num_args = 1;
4354 intr_name = "llvm.amdgcn.readfirstlane";
4355 }
4356
4357 /* We currently have no other way to prevent LLVM from lifting the icmp
4358 * calls to a dominating basic block.
4359 */
4360 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4361
4362 result = ac_build_intrinsic(&ctx->ac, intr_name,
4363 ctx->ac.i32, args, num_args,
4364 AC_FUNC_ATTR_READNONE |
4365 AC_FUNC_ATTR_CONVERGENT);
4366 break;
4367 }
4368 case nir_intrinsic_load_subgroup_invocation:
4369 result = ac_get_thread_id(&ctx->ac);
4370 break;
4371 case nir_intrinsic_load_work_group_id: {
4372 LLVMValueRef values[3];
4373
4374 for (int i = 0; i < 3; i++) {
4375 values[i] = ctx->abi->workgroup_ids[i] ?
4376 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4377 }
4378
4379 result = ac_build_gather_values(&ctx->ac, values, 3);
4380 break;
4381 }
4382 case nir_intrinsic_load_base_vertex: {
4383 result = ctx->abi->base_vertex;
4384 break;
4385 }
4386 case nir_intrinsic_load_local_group_size:
4387 result = ctx->abi->load_local_group_size(ctx->abi);
4388 break;
4389 case nir_intrinsic_load_vertex_id_zero_base: {
4390 result = ctx->abi->vertex_id;
4391 break;
4392 }
4393 case nir_intrinsic_load_local_invocation_id: {
4394 result = ctx->abi->local_invocation_ids;
4395 break;
4396 }
4397 case nir_intrinsic_load_base_instance:
4398 result = ctx->abi->start_instance;
4399 break;
4400 case nir_intrinsic_load_draw_id:
4401 result = ctx->abi->draw_id;
4402 break;
4403 case nir_intrinsic_load_view_index:
4404 result = ctx->abi->view_index;
4405 break;
4406 case nir_intrinsic_load_invocation_id:
4407 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4408 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4409 else
4410 result = ctx->abi->gs_invocation_id;
4411 break;
4412 case nir_intrinsic_load_primitive_id:
4413 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4414 result = ctx->abi->gs_prim_id;
4415 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4416 result = ctx->abi->tcs_patch_id;
4417 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4418 result = ctx->abi->tes_patch_id;
4419 } else
4420 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4421 break;
4422 case nir_intrinsic_load_sample_id:
4423 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4424 break;
4425 case nir_intrinsic_load_sample_pos:
4426 result = load_sample_pos(ctx);
4427 break;
4428 case nir_intrinsic_load_sample_mask_in:
4429 result = ctx->abi->load_sample_mask_in(ctx->abi);
4430 break;
4431 case nir_intrinsic_load_frag_coord: {
4432 LLVMValueRef values[4] = {
4433 ctx->abi->frag_pos[0],
4434 ctx->abi->frag_pos[1],
4435 ctx->abi->frag_pos[2],
4436 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4437 };
4438 result = ac_build_gather_values(&ctx->ac, values, 4);
4439 break;
4440 }
4441 case nir_intrinsic_load_front_face:
4442 result = ctx->abi->front_face;
4443 break;
4444 case nir_intrinsic_load_helper_invocation:
4445 result = visit_load_helper_invocation(ctx);
4446 break;
4447 case nir_intrinsic_load_instance_id:
4448 result = ctx->abi->instance_id;
4449 break;
4450 case nir_intrinsic_load_num_work_groups:
4451 result = ctx->abi->num_work_groups;
4452 break;
4453 case nir_intrinsic_load_local_invocation_index:
4454 result = visit_load_local_invocation_index(ctx);
4455 break;
4456 case nir_intrinsic_load_push_constant:
4457 result = visit_load_push_constant(ctx, instr);
4458 break;
4459 case nir_intrinsic_vulkan_resource_index: {
4460 LLVMValueRef index = get_src(ctx, instr->src[0]);
4461 unsigned desc_set = nir_intrinsic_desc_set(instr);
4462 unsigned binding = nir_intrinsic_binding(instr);
4463
4464 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4465 binding);
4466 break;
4467 }
4468 case nir_intrinsic_vulkan_resource_reindex:
4469 result = visit_vulkan_resource_reindex(ctx, instr);
4470 break;
4471 case nir_intrinsic_store_ssbo:
4472 visit_store_ssbo(ctx, instr);
4473 break;
4474 case nir_intrinsic_load_ssbo:
4475 result = visit_load_buffer(ctx, instr);
4476 break;
4477 case nir_intrinsic_ssbo_atomic_add:
4478 case nir_intrinsic_ssbo_atomic_imin:
4479 case nir_intrinsic_ssbo_atomic_umin:
4480 case nir_intrinsic_ssbo_atomic_imax:
4481 case nir_intrinsic_ssbo_atomic_umax:
4482 case nir_intrinsic_ssbo_atomic_and:
4483 case nir_intrinsic_ssbo_atomic_or:
4484 case nir_intrinsic_ssbo_atomic_xor:
4485 case nir_intrinsic_ssbo_atomic_exchange:
4486 case nir_intrinsic_ssbo_atomic_comp_swap:
4487 result = visit_atomic_ssbo(ctx, instr);
4488 break;
4489 case nir_intrinsic_load_ubo:
4490 result = visit_load_ubo_buffer(ctx, instr);
4491 break;
4492 case nir_intrinsic_get_buffer_size:
4493 result = visit_get_buffer_size(ctx, instr);
4494 break;
4495 case nir_intrinsic_load_var:
4496 result = visit_load_var(ctx, instr);
4497 break;
4498 case nir_intrinsic_store_var:
4499 visit_store_var(ctx, instr);
4500 break;
4501 case nir_intrinsic_load_shared:
4502 result = visit_load_shared(ctx, instr);
4503 break;
4504 case nir_intrinsic_store_shared:
4505 visit_store_shared(ctx, instr);
4506 break;
4507 case nir_intrinsic_image_samples:
4508 result = visit_image_samples(ctx, instr);
4509 break;
4510 case nir_intrinsic_image_load:
4511 result = visit_image_load(ctx, instr);
4512 break;
4513 case nir_intrinsic_image_store:
4514 visit_image_store(ctx, instr);
4515 break;
4516 case nir_intrinsic_image_atomic_add:
4517 case nir_intrinsic_image_atomic_min:
4518 case nir_intrinsic_image_atomic_max:
4519 case nir_intrinsic_image_atomic_and:
4520 case nir_intrinsic_image_atomic_or:
4521 case nir_intrinsic_image_atomic_xor:
4522 case nir_intrinsic_image_atomic_exchange:
4523 case nir_intrinsic_image_atomic_comp_swap:
4524 result = visit_image_atomic(ctx, instr);
4525 break;
4526 case nir_intrinsic_image_size:
4527 result = visit_image_size(ctx, instr);
4528 break;
4529 case nir_intrinsic_shader_clock:
4530 result = ac_build_shader_clock(&ctx->ac);
4531 break;
4532 case nir_intrinsic_discard:
4533 case nir_intrinsic_discard_if:
4534 emit_discard(ctx, instr);
4535 break;
4536 case nir_intrinsic_memory_barrier:
4537 case nir_intrinsic_group_memory_barrier:
4538 case nir_intrinsic_memory_barrier_atomic_counter:
4539 case nir_intrinsic_memory_barrier_buffer:
4540 case nir_intrinsic_memory_barrier_image:
4541 case nir_intrinsic_memory_barrier_shared:
4542 emit_membar(&ctx->ac, instr);
4543 break;
4544 case nir_intrinsic_barrier:
4545 emit_barrier(&ctx->ac, ctx->stage);
4546 break;
4547 case nir_intrinsic_shared_atomic_add:
4548 case nir_intrinsic_shared_atomic_imin:
4549 case nir_intrinsic_shared_atomic_umin:
4550 case nir_intrinsic_shared_atomic_imax:
4551 case nir_intrinsic_shared_atomic_umax:
4552 case nir_intrinsic_shared_atomic_and:
4553 case nir_intrinsic_shared_atomic_or:
4554 case nir_intrinsic_shared_atomic_xor:
4555 case nir_intrinsic_shared_atomic_exchange:
4556 case nir_intrinsic_shared_atomic_comp_swap: {
4557 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
4558 result = visit_var_atomic(ctx, instr, ptr);
4559 break;
4560 }
4561 case nir_intrinsic_var_atomic_add:
4562 case nir_intrinsic_var_atomic_imin:
4563 case nir_intrinsic_var_atomic_umin:
4564 case nir_intrinsic_var_atomic_imax:
4565 case nir_intrinsic_var_atomic_umax:
4566 case nir_intrinsic_var_atomic_and:
4567 case nir_intrinsic_var_atomic_or:
4568 case nir_intrinsic_var_atomic_xor:
4569 case nir_intrinsic_var_atomic_exchange:
4570 case nir_intrinsic_var_atomic_comp_swap: {
4571 LLVMValueRef ptr = build_gep_for_deref(ctx, instr->variables[0]);
4572 result = visit_var_atomic(ctx, instr, ptr);
4573 break;
4574 }
4575 case nir_intrinsic_interp_var_at_centroid:
4576 case nir_intrinsic_interp_var_at_sample:
4577 case nir_intrinsic_interp_var_at_offset:
4578 result = visit_interp(ctx, instr);
4579 break;
4580 case nir_intrinsic_emit_vertex:
4581 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->abi->outputs);
4582 break;
4583 case nir_intrinsic_end_primitive:
4584 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4585 break;
4586 case nir_intrinsic_load_tess_coord:
4587 result = ctx->abi->load_tess_coord(ctx->abi);
4588 break;
4589 case nir_intrinsic_load_tess_level_outer:
4590 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4591 break;
4592 case nir_intrinsic_load_tess_level_inner:
4593 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4594 break;
4595 case nir_intrinsic_load_patch_vertices_in:
4596 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4597 break;
4598 case nir_intrinsic_vote_all: {
4599 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4600 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4601 break;
4602 }
4603 case nir_intrinsic_vote_any: {
4604 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4605 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4606 break;
4607 }
4608 case nir_intrinsic_vote_eq: {
4609 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4610 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4611 break;
4612 }
4613 default:
4614 fprintf(stderr, "Unknown intrinsic: ");
4615 nir_print_instr(&instr->instr, stderr);
4616 fprintf(stderr, "\n");
4617 break;
4618 }
4619 if (result) {
4620 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4621 }
4622 }
4623
4624 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4625 LLVMValueRef buffer_ptr, bool write)
4626 {
4627 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4628 LLVMValueRef result;
4629
4630 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4631
4632 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4633 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4634
4635 return result;
4636 }
4637
4638 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4639 {
4640 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4641 LLVMValueRef result;
4642
4643 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4644
4645 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4646 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4647
4648 return result;
4649 }
4650
4651 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4652 unsigned descriptor_set,
4653 unsigned base_index,
4654 unsigned constant_index,
4655 LLVMValueRef index,
4656 enum ac_descriptor_type desc_type,
4657 bool image, bool write)
4658 {
4659 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4660 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4661 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4662 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4663 unsigned offset = binding->offset;
4664 unsigned stride = binding->size;
4665 unsigned type_size;
4666 LLVMBuilderRef builder = ctx->ac.builder;
4667 LLVMTypeRef type;
4668
4669 assert(base_index < layout->binding_count);
4670
4671 switch (desc_type) {
4672 case AC_DESC_IMAGE:
4673 type = ctx->ac.v8i32;
4674 type_size = 32;
4675 break;
4676 case AC_DESC_FMASK:
4677 type = ctx->ac.v8i32;
4678 offset += 32;
4679 type_size = 32;
4680 break;
4681 case AC_DESC_SAMPLER:
4682 type = ctx->ac.v4i32;
4683 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4684 offset += 64;
4685
4686 type_size = 16;
4687 break;
4688 case AC_DESC_BUFFER:
4689 type = ctx->ac.v4i32;
4690 type_size = 16;
4691 break;
4692 default:
4693 unreachable("invalid desc_type\n");
4694 }
4695
4696 offset += constant_index * stride;
4697
4698 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4699 (!index || binding->immutable_samplers_equal)) {
4700 if (binding->immutable_samplers_equal)
4701 constant_index = 0;
4702
4703 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4704
4705 LLVMValueRef constants[] = {
4706 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4707 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4708 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4709 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4710 };
4711 return ac_build_gather_values(&ctx->ac, constants, 4);
4712 }
4713
4714 assert(stride % type_size == 0);
4715
4716 if (!index)
4717 index = ctx->ac.i32_0;
4718
4719 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4720
4721 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4722 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4723
4724 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4725 }
4726
4727 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4728 const nir_deref_var *deref,
4729 enum ac_descriptor_type desc_type,
4730 const nir_tex_instr *tex_instr,
4731 bool image, bool write)
4732 {
4733 LLVMValueRef index = NULL;
4734 unsigned constant_index = 0;
4735 unsigned descriptor_set;
4736 unsigned base_index;
4737
4738 if (!deref) {
4739 assert(tex_instr && !image);
4740 descriptor_set = 0;
4741 base_index = tex_instr->sampler_index;
4742 } else {
4743 const nir_deref *tail = &deref->deref;
4744 while (tail->child) {
4745 const nir_deref_array *child = nir_deref_as_array(tail->child);
4746 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4747
4748 if (!array_size)
4749 array_size = 1;
4750
4751 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4752
4753 if (child->deref_array_type == nir_deref_array_type_indirect) {
4754 LLVMValueRef indirect = get_src(ctx, child->indirect);
4755
4756 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4757 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4758
4759 if (!index)
4760 index = indirect;
4761 else
4762 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4763 }
4764
4765 constant_index += child->base_offset * array_size;
4766
4767 tail = &child->deref;
4768 }
4769 descriptor_set = deref->var->data.descriptor_set;
4770 base_index = deref->var->data.binding;
4771 }
4772
4773 return ctx->abi->load_sampler_desc(ctx->abi,
4774 descriptor_set,
4775 base_index,
4776 constant_index, index,
4777 desc_type, image, write);
4778 }
4779
4780 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4781 struct ac_image_args *args,
4782 const nir_tex_instr *instr,
4783 nir_texop op,
4784 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4785 LLVMValueRef *param, unsigned count,
4786 unsigned dmask)
4787 {
4788 unsigned is_rect = 0;
4789 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4790
4791 if (op == nir_texop_lod)
4792 da = false;
4793 /* Pad to power of two vector */
4794 while (count < util_next_power_of_two(count))
4795 param[count++] = LLVMGetUndef(ctx->i32);
4796
4797 if (count > 1)
4798 args->addr = ac_build_gather_values(ctx, param, count);
4799 else
4800 args->addr = param[0];
4801
4802 args->resource = res_ptr;
4803 args->sampler = samp_ptr;
4804
4805 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4806 args->addr = param[0];
4807 return;
4808 }
4809
4810 args->dmask = dmask;
4811 args->unorm = is_rect;
4812 args->da = da;
4813 }
4814
4815 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4816 *
4817 * SI-CI:
4818 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4819 * filtering manually. The driver sets img7 to a mask clearing
4820 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4821 * s_and_b32 samp0, samp0, img7
4822 *
4823 * VI:
4824 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4825 */
4826 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4827 LLVMValueRef res, LLVMValueRef samp)
4828 {
4829 LLVMBuilderRef builder = ctx->ac.builder;
4830 LLVMValueRef img7, samp0;
4831
4832 if (ctx->ac.chip_class >= VI)
4833 return samp;
4834
4835 img7 = LLVMBuildExtractElement(builder, res,
4836 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4837 samp0 = LLVMBuildExtractElement(builder, samp,
4838 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4839 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4840 return LLVMBuildInsertElement(builder, samp, samp0,
4841 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4842 }
4843
4844 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4845 nir_tex_instr *instr,
4846 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4847 LLVMValueRef *fmask_ptr)
4848 {
4849 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4850 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4851 else
4852 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4853 if (samp_ptr) {
4854 if (instr->sampler)
4855 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4856 else
4857 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4858 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4859 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4860 }
4861 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4862 instr->op == nir_texop_samples_identical))
4863 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4864 }
4865
4866 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4867 LLVMValueRef coord)
4868 {
4869 coord = ac_to_float(ctx, coord);
4870 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4871 coord = ac_to_integer(ctx, coord);
4872 return coord;
4873 }
4874
4875 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4876 {
4877 LLVMValueRef result = NULL;
4878 struct ac_image_args args = { 0 };
4879 unsigned dmask = 0xf;
4880 LLVMValueRef address[16];
4881 LLVMValueRef coords[5];
4882 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4883 LLVMValueRef bias = NULL, offsets = NULL;
4884 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4885 LLVMValueRef ddx = NULL, ddy = NULL;
4886 LLVMValueRef derivs[6];
4887 unsigned chan, count = 0;
4888 unsigned const_src = 0, num_deriv_comp = 0;
4889 bool lod_is_zero = false;
4890
4891 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4892
4893 for (unsigned i = 0; i < instr->num_srcs; i++) {
4894 switch (instr->src[i].src_type) {
4895 case nir_tex_src_coord:
4896 coord = get_src(ctx, instr->src[i].src);
4897 break;
4898 case nir_tex_src_projector:
4899 break;
4900 case nir_tex_src_comparator:
4901 comparator = get_src(ctx, instr->src[i].src);
4902 break;
4903 case nir_tex_src_offset:
4904 offsets = get_src(ctx, instr->src[i].src);
4905 const_src = i;
4906 break;
4907 case nir_tex_src_bias:
4908 bias = get_src(ctx, instr->src[i].src);
4909 break;
4910 case nir_tex_src_lod: {
4911 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4912
4913 if (val && val->i32[0] == 0)
4914 lod_is_zero = true;
4915 lod = get_src(ctx, instr->src[i].src);
4916 break;
4917 }
4918 case nir_tex_src_ms_index:
4919 sample_index = get_src(ctx, instr->src[i].src);
4920 break;
4921 case nir_tex_src_ms_mcs:
4922 break;
4923 case nir_tex_src_ddx:
4924 ddx = get_src(ctx, instr->src[i].src);
4925 num_deriv_comp = instr->src[i].src.ssa->num_components;
4926 break;
4927 case nir_tex_src_ddy:
4928 ddy = get_src(ctx, instr->src[i].src);
4929 break;
4930 case nir_tex_src_texture_offset:
4931 case nir_tex_src_sampler_offset:
4932 case nir_tex_src_plane:
4933 default:
4934 break;
4935 }
4936 }
4937
4938 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4939 result = get_buffer_size(ctx, res_ptr, true);
4940 goto write_result;
4941 }
4942
4943 if (instr->op == nir_texop_texture_samples) {
4944 LLVMValueRef res, samples, is_msaa;
4945 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4946 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4947 LLVMConstInt(ctx->ac.i32, 3, false), "");
4948 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4949 LLVMConstInt(ctx->ac.i32, 28, false), "");
4950 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4951 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4952 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4953 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4954
4955 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4956 LLVMConstInt(ctx->ac.i32, 16, false), "");
4957 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4958 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4959 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4960 samples, "");
4961 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4962 ctx->ac.i32_1, "");
4963 result = samples;
4964 goto write_result;
4965 }
4966
4967 if (coord)
4968 for (chan = 0; chan < instr->coord_components; chan++)
4969 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4970
4971 if (offsets && instr->op != nir_texop_txf) {
4972 LLVMValueRef offset[3], pack;
4973 for (chan = 0; chan < 3; ++chan)
4974 offset[chan] = ctx->ac.i32_0;
4975
4976 args.offset = true;
4977 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4978 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4979 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4980 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4981 if (chan)
4982 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4983 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4984 }
4985 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4986 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4987 address[count++] = pack;
4988
4989 }
4990 /* pack LOD bias value */
4991 if (instr->op == nir_texop_txb && bias) {
4992 address[count++] = bias;
4993 }
4994
4995 /* Pack depth comparison value */
4996 if (instr->is_shadow && comparator) {
4997 LLVMValueRef z = ac_to_float(&ctx->ac,
4998 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4999
5000 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
5001 * so the depth comparison value isn't clamped for Z16 and
5002 * Z24 anymore. Do it manually here.
5003 *
5004 * It's unnecessary if the original texture format was
5005 * Z32_FLOAT, but we don't know that here.
5006 */
5007 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
5008 z = ac_build_clamp(&ctx->ac, z);
5009
5010 address[count++] = z;
5011 }
5012
5013 /* pack derivatives */
5014 if (ddx || ddy) {
5015 int num_src_deriv_channels, num_dest_deriv_channels;
5016 switch (instr->sampler_dim) {
5017 case GLSL_SAMPLER_DIM_3D:
5018 case GLSL_SAMPLER_DIM_CUBE:
5019 num_deriv_comp = 3;
5020 num_src_deriv_channels = 3;
5021 num_dest_deriv_channels = 3;
5022 break;
5023 case GLSL_SAMPLER_DIM_2D:
5024 default:
5025 num_src_deriv_channels = 2;
5026 num_dest_deriv_channels = 2;
5027 num_deriv_comp = 2;
5028 break;
5029 case GLSL_SAMPLER_DIM_1D:
5030 num_src_deriv_channels = 1;
5031 if (ctx->ac.chip_class >= GFX9) {
5032 num_dest_deriv_channels = 2;
5033 num_deriv_comp = 2;
5034 } else {
5035 num_dest_deriv_channels = 1;
5036 num_deriv_comp = 1;
5037 }
5038 break;
5039 }
5040
5041 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
5042 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
5043 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
5044 }
5045 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
5046 derivs[i] = ctx->ac.f32_0;
5047 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
5048 }
5049 }
5050
5051 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
5052 for (chan = 0; chan < instr->coord_components; chan++)
5053 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
5054 if (instr->coord_components == 3)
5055 coords[3] = LLVMGetUndef(ctx->ac.f32);
5056 ac_prepare_cube_coords(&ctx->ac,
5057 instr->op == nir_texop_txd, instr->is_array,
5058 instr->op == nir_texop_lod, coords, derivs);
5059 if (num_deriv_comp)
5060 num_deriv_comp--;
5061 }
5062
5063 if (ddx || ddy) {
5064 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
5065 address[count++] = derivs[i];
5066 }
5067
5068 /* Pack texture coordinates */
5069 if (coord) {
5070 address[count++] = coords[0];
5071 if (instr->coord_components > 1) {
5072 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
5073 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
5074 }
5075 address[count++] = coords[1];
5076 }
5077 if (instr->coord_components > 2) {
5078 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
5079 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
5080 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
5081 instr->op != nir_texop_txf) {
5082 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
5083 }
5084 address[count++] = coords[2];
5085 }
5086
5087 if (ctx->ac.chip_class >= GFX9) {
5088 LLVMValueRef filler;
5089 if (instr->op == nir_texop_txf)
5090 filler = ctx->ac.i32_0;
5091 else
5092 filler = LLVMConstReal(ctx->ac.f32, 0.5);
5093
5094 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
5095 /* No nir_texop_lod, because it does not take a slice
5096 * even with array textures. */
5097 if (instr->is_array && instr->op != nir_texop_lod ) {
5098 address[count] = address[count - 1];
5099 address[count - 1] = filler;
5100 count++;
5101 } else
5102 address[count++] = filler;
5103 }
5104 }
5105 }
5106
5107 /* Pack LOD */
5108 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5109 instr->op == nir_texop_txf)) {
5110 address[count++] = lod;
5111 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5112 address[count++] = sample_index;
5113 } else if(instr->op == nir_texop_txs) {
5114 count = 0;
5115 if (lod)
5116 address[count++] = lod;
5117 else
5118 address[count++] = ctx->ac.i32_0;
5119 }
5120
5121 for (chan = 0; chan < count; chan++) {
5122 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5123 address[chan], ctx->ac.i32, "");
5124 }
5125
5126 if (instr->op == nir_texop_samples_identical) {
5127 LLVMValueRef txf_address[4];
5128 struct ac_image_args txf_args = { 0 };
5129 unsigned txf_count = count;
5130 memcpy(txf_address, address, sizeof(txf_address));
5131
5132 if (!instr->is_array)
5133 txf_address[2] = ctx->ac.i32_0;
5134 txf_address[3] = ctx->ac.i32_0;
5135
5136 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5137 fmask_ptr, NULL,
5138 txf_address, txf_count, 0xf);
5139
5140 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5141
5142 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5143 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5144 goto write_result;
5145 }
5146
5147 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5148 instr->op != nir_texop_txs) {
5149 unsigned sample_chan = instr->is_array ? 3 : 2;
5150 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5151 address[0],
5152 address[1],
5153 instr->is_array ? address[2] : NULL,
5154 address[sample_chan],
5155 fmask_ptr);
5156 }
5157
5158 if (offsets && instr->op == nir_texop_txf) {
5159 nir_const_value *const_offset =
5160 nir_src_as_const_value(instr->src[const_src].src);
5161 int num_offsets = instr->src[const_src].src.ssa->num_components;
5162 assert(const_offset);
5163 num_offsets = MIN2(num_offsets, instr->coord_components);
5164 if (num_offsets > 2)
5165 address[2] = LLVMBuildAdd(ctx->ac.builder,
5166 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5167 if (num_offsets > 1)
5168 address[1] = LLVMBuildAdd(ctx->ac.builder,
5169 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5170 address[0] = LLVMBuildAdd(ctx->ac.builder,
5171 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5172
5173 }
5174
5175 /* TODO TG4 support */
5176 if (instr->op == nir_texop_tg4) {
5177 if (instr->is_shadow)
5178 dmask = 1;
5179 else
5180 dmask = 1 << instr->component;
5181 }
5182 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5183 res_ptr, samp_ptr, address, count, dmask);
5184
5185 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5186
5187 if (instr->op == nir_texop_query_levels)
5188 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5189 else if (instr->is_shadow && instr->is_new_style_shadow &&
5190 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5191 instr->op != nir_texop_tg4)
5192 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5193 else if (instr->op == nir_texop_txs &&
5194 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5195 instr->is_array) {
5196 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5197 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5198 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5199 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5200 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5201 } else if (ctx->ac.chip_class >= GFX9 &&
5202 instr->op == nir_texop_txs &&
5203 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5204 instr->is_array) {
5205 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5206 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5207 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5208 ctx->ac.i32_1, "");
5209 } else if (instr->dest.ssa.num_components != 4)
5210 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5211
5212 write_result:
5213 if (result) {
5214 assert(instr->dest.is_ssa);
5215 result = ac_to_integer(&ctx->ac, result);
5216 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5217 }
5218 }
5219
5220
5221 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5222 {
5223 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5224 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5225
5226 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5227 _mesa_hash_table_insert(ctx->phis, instr, result);
5228 }
5229
5230 static void visit_post_phi(struct ac_nir_context *ctx,
5231 nir_phi_instr *instr,
5232 LLVMValueRef llvm_phi)
5233 {
5234 nir_foreach_phi_src(src, instr) {
5235 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5236 LLVMValueRef llvm_src = get_src(ctx, src->src);
5237
5238 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5239 }
5240 }
5241
5242 static void phi_post_pass(struct ac_nir_context *ctx)
5243 {
5244 struct hash_entry *entry;
5245 hash_table_foreach(ctx->phis, entry) {
5246 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5247 (LLVMValueRef)entry->data);
5248 }
5249 }
5250
5251
5252 static void visit_ssa_undef(struct ac_nir_context *ctx,
5253 const nir_ssa_undef_instr *instr)
5254 {
5255 unsigned num_components = instr->def.num_components;
5256 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5257 LLVMValueRef undef;
5258
5259 if (num_components == 1)
5260 undef = LLVMGetUndef(type);
5261 else {
5262 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5263 }
5264 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5265 }
5266
5267 static void visit_jump(struct ac_nir_context *ctx,
5268 const nir_jump_instr *instr)
5269 {
5270 switch (instr->type) {
5271 case nir_jump_break:
5272 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5273 LLVMClearInsertionPosition(ctx->ac.builder);
5274 break;
5275 case nir_jump_continue:
5276 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5277 LLVMClearInsertionPosition(ctx->ac.builder);
5278 break;
5279 default:
5280 fprintf(stderr, "Unknown NIR jump instr: ");
5281 nir_print_instr(&instr->instr, stderr);
5282 fprintf(stderr, "\n");
5283 abort();
5284 }
5285 }
5286
5287 static void visit_cf_list(struct ac_nir_context *ctx,
5288 struct exec_list *list);
5289
5290 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5291 {
5292 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5293 nir_foreach_instr(instr, block)
5294 {
5295 switch (instr->type) {
5296 case nir_instr_type_alu:
5297 visit_alu(ctx, nir_instr_as_alu(instr));
5298 break;
5299 case nir_instr_type_load_const:
5300 visit_load_const(ctx, nir_instr_as_load_const(instr));
5301 break;
5302 case nir_instr_type_intrinsic:
5303 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5304 break;
5305 case nir_instr_type_tex:
5306 visit_tex(ctx, nir_instr_as_tex(instr));
5307 break;
5308 case nir_instr_type_phi:
5309 visit_phi(ctx, nir_instr_as_phi(instr));
5310 break;
5311 case nir_instr_type_ssa_undef:
5312 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5313 break;
5314 case nir_instr_type_jump:
5315 visit_jump(ctx, nir_instr_as_jump(instr));
5316 break;
5317 default:
5318 fprintf(stderr, "Unknown NIR instr type: ");
5319 nir_print_instr(instr, stderr);
5320 fprintf(stderr, "\n");
5321 abort();
5322 }
5323 }
5324
5325 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5326 }
5327
5328 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5329 {
5330 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5331
5332 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5333 LLVMBasicBlockRef merge_block =
5334 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5335 LLVMBasicBlockRef if_block =
5336 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5337 LLVMBasicBlockRef else_block = merge_block;
5338 if (!exec_list_is_empty(&if_stmt->else_list))
5339 else_block = LLVMAppendBasicBlockInContext(
5340 ctx->ac.context, fn, "");
5341
5342 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5343 ctx->ac.i32_0, "");
5344 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5345
5346 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5347 visit_cf_list(ctx, &if_stmt->then_list);
5348 if (LLVMGetInsertBlock(ctx->ac.builder))
5349 LLVMBuildBr(ctx->ac.builder, merge_block);
5350
5351 if (!exec_list_is_empty(&if_stmt->else_list)) {
5352 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5353 visit_cf_list(ctx, &if_stmt->else_list);
5354 if (LLVMGetInsertBlock(ctx->ac.builder))
5355 LLVMBuildBr(ctx->ac.builder, merge_block);
5356 }
5357
5358 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5359 }
5360
5361 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5362 {
5363 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5364 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5365 LLVMBasicBlockRef break_parent = ctx->break_block;
5366
5367 ctx->continue_block =
5368 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5369 ctx->break_block =
5370 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5371
5372 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5373 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5374 visit_cf_list(ctx, &loop->body);
5375
5376 if (LLVMGetInsertBlock(ctx->ac.builder))
5377 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5378 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5379
5380 ctx->continue_block = continue_parent;
5381 ctx->break_block = break_parent;
5382 }
5383
5384 static void visit_cf_list(struct ac_nir_context *ctx,
5385 struct exec_list *list)
5386 {
5387 foreach_list_typed(nir_cf_node, node, node, list)
5388 {
5389 switch (node->type) {
5390 case nir_cf_node_block:
5391 visit_block(ctx, nir_cf_node_as_block(node));
5392 break;
5393
5394 case nir_cf_node_if:
5395 visit_if(ctx, nir_cf_node_as_if(node));
5396 break;
5397
5398 case nir_cf_node_loop:
5399 visit_loop(ctx, nir_cf_node_as_loop(node));
5400 break;
5401
5402 default:
5403 assert(0);
5404 }
5405 }
5406 }
5407
5408 static void
5409 handle_vs_input_decl(struct radv_shader_context *ctx,
5410 struct nir_variable *variable)
5411 {
5412 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5413 LLVMValueRef t_offset;
5414 LLVMValueRef t_list;
5415 LLVMValueRef input;
5416 LLVMValueRef buffer_index;
5417 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5418 int idx = variable->data.location;
5419 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5420 uint8_t input_usage_mask =
5421 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5422 unsigned num_channels = util_last_bit(input_usage_mask);
5423
5424 variable->data.driver_location = idx * 4;
5425
5426 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5427 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5428 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
5429 ctx->abi.start_instance, "");
5430 if (ctx->options->key.vs.as_ls) {
5431 ctx->shader_info->vs.vgpr_comp_cnt =
5432 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5433 } else {
5434 ctx->shader_info->vs.vgpr_comp_cnt =
5435 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5436 }
5437 } else
5438 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
5439 ctx->abi.base_vertex, "");
5440 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5441
5442 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5443
5444 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5445 buffer_index,
5446 ctx->ac.i32_0,
5447 num_channels, false, true);
5448
5449 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5450
5451 for (unsigned chan = 0; chan < 4; chan++) {
5452 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5453 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5454 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
5455 input, llvm_chan, ""));
5456 }
5457 }
5458 }
5459
5460 static void interp_fs_input(struct radv_shader_context *ctx,
5461 unsigned attr,
5462 LLVMValueRef interp_param,
5463 LLVMValueRef prim_mask,
5464 LLVMValueRef result[4])
5465 {
5466 LLVMValueRef attr_number;
5467 unsigned chan;
5468 LLVMValueRef i, j;
5469 bool interp = interp_param != NULL;
5470
5471 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5472
5473 /* fs.constant returns the param from the middle vertex, so it's not
5474 * really useful for flat shading. It's meant to be used for custom
5475 * interpolation (but the intrinsic can't fetch from the other two
5476 * vertices).
5477 *
5478 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5479 * to do the right thing. The only reason we use fs.constant is that
5480 * fs.interp cannot be used on integers, because they can be equal
5481 * to NaN.
5482 */
5483 if (interp) {
5484 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
5485 ctx->ac.v2f32, "");
5486
5487 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5488 ctx->ac.i32_0, "");
5489 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5490 ctx->ac.i32_1, "");
5491 }
5492
5493 for (chan = 0; chan < 4; chan++) {
5494 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5495
5496 if (interp) {
5497 result[chan] = ac_build_fs_interp(&ctx->ac,
5498 llvm_chan,
5499 attr_number,
5500 prim_mask, i, j);
5501 } else {
5502 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5503 LLVMConstInt(ctx->ac.i32, 2, false),
5504 llvm_chan,
5505 attr_number,
5506 prim_mask);
5507 }
5508 }
5509 }
5510
5511 static void
5512 handle_fs_input_decl(struct radv_shader_context *ctx,
5513 struct nir_variable *variable)
5514 {
5515 int idx = variable->data.location;
5516 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5517 LLVMValueRef interp;
5518
5519 variable->data.driver_location = idx * 4;
5520 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5521
5522 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5523 unsigned interp_type;
5524 if (variable->data.sample)
5525 interp_type = INTERP_SAMPLE;
5526 else if (variable->data.centroid)
5527 interp_type = INTERP_CENTROID;
5528 else
5529 interp_type = INTERP_CENTER;
5530
5531 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5532 } else
5533 interp = NULL;
5534
5535 for (unsigned i = 0; i < attrib_count; ++i)
5536 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5537
5538 }
5539
5540 static void
5541 handle_vs_inputs(struct radv_shader_context *ctx,
5542 struct nir_shader *nir) {
5543 nir_foreach_variable(variable, &nir->inputs)
5544 handle_vs_input_decl(ctx, variable);
5545 }
5546
5547 static void
5548 prepare_interp_optimize(struct radv_shader_context *ctx,
5549 struct nir_shader *nir)
5550 {
5551 if (!ctx->options->key.fs.multisample)
5552 return;
5553
5554 bool uses_center = false;
5555 bool uses_centroid = false;
5556 nir_foreach_variable(variable, &nir->inputs) {
5557 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5558 variable->data.sample)
5559 continue;
5560
5561 if (variable->data.centroid)
5562 uses_centroid = true;
5563 else
5564 uses_center = true;
5565 }
5566
5567 if (uses_center && uses_centroid) {
5568 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5569 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5570 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5571 }
5572 }
5573
5574 static void
5575 handle_fs_inputs(struct radv_shader_context *ctx,
5576 struct nir_shader *nir)
5577 {
5578 prepare_interp_optimize(ctx, nir);
5579
5580 nir_foreach_variable(variable, &nir->inputs)
5581 handle_fs_input_decl(ctx, variable);
5582
5583 unsigned index = 0;
5584
5585 if (ctx->shader_info->info.ps.uses_input_attachments ||
5586 ctx->shader_info->info.needs_multiview_view_index)
5587 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5588
5589 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5590 LLVMValueRef interp_param;
5591 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5592
5593 if (!(ctx->input_mask & (1ull << i)))
5594 continue;
5595
5596 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5597 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5598 interp_param = *inputs;
5599 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5600 inputs);
5601
5602 if (!interp_param)
5603 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5604 ++index;
5605 } else if (i == VARYING_SLOT_POS) {
5606 for(int i = 0; i < 3; ++i)
5607 inputs[i] = ctx->abi.frag_pos[i];
5608
5609 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5610 ctx->abi.frag_pos[3]);
5611 }
5612 }
5613 ctx->shader_info->fs.num_interp = index;
5614 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5615 ctx->shader_info->fs.has_pcoord = true;
5616 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5617 ctx->shader_info->fs.prim_id_input = true;
5618 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5619 ctx->shader_info->fs.layer_input = true;
5620 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5621
5622 if (ctx->shader_info->info.needs_multiview_view_index)
5623 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5624 }
5625
5626 static LLVMValueRef
5627 ac_build_alloca(struct ac_llvm_context *ac,
5628 LLVMTypeRef type,
5629 const char *name)
5630 {
5631 LLVMBuilderRef builder = ac->builder;
5632 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5633 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5634 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5635 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5636 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5637 LLVMValueRef res;
5638
5639 if (first_instr) {
5640 LLVMPositionBuilderBefore(first_builder, first_instr);
5641 } else {
5642 LLVMPositionBuilderAtEnd(first_builder, first_block);
5643 }
5644
5645 res = LLVMBuildAlloca(first_builder, type, name);
5646 LLVMBuildStore(builder, LLVMConstNull(type), res);
5647
5648 LLVMDisposeBuilder(first_builder);
5649
5650 return res;
5651 }
5652
5653 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5654 LLVMTypeRef type,
5655 const char *name)
5656 {
5657 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5658 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5659 return ptr;
5660 }
5661
5662 static void
5663 scan_shader_output_decl(struct radv_shader_context *ctx,
5664 struct nir_variable *variable,
5665 struct nir_shader *shader,
5666 gl_shader_stage stage)
5667 {
5668 int idx = variable->data.location + variable->data.index;
5669 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5670 uint64_t mask_attribs;
5671
5672 variable->data.driver_location = idx * 4;
5673
5674 /* tess ctrl has it's own load/store paths for outputs */
5675 if (stage == MESA_SHADER_TESS_CTRL)
5676 return;
5677
5678 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5679 if (stage == MESA_SHADER_VERTEX ||
5680 stage == MESA_SHADER_TESS_EVAL ||
5681 stage == MESA_SHADER_GEOMETRY) {
5682 if (idx == VARYING_SLOT_CLIP_DIST0) {
5683 int length = shader->info.clip_distance_array_size +
5684 shader->info.cull_distance_array_size;
5685 if (stage == MESA_SHADER_VERTEX) {
5686 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5687 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5688 }
5689 if (stage == MESA_SHADER_TESS_EVAL) {
5690 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5691 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5692 }
5693
5694 if (length > 4)
5695 attrib_count = 2;
5696 else
5697 attrib_count = 1;
5698 mask_attribs = 1ull << idx;
5699 }
5700 }
5701
5702 ctx->output_mask |= mask_attribs;
5703 }
5704
5705 static void
5706 handle_shader_output_decl(struct ac_nir_context *ctx,
5707 struct nir_shader *nir,
5708 struct nir_variable *variable)
5709 {
5710 unsigned output_loc = variable->data.driver_location / 4;
5711 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5712
5713 /* tess ctrl has it's own load/store paths for outputs */
5714 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5715 return;
5716
5717 if (ctx->stage == MESA_SHADER_VERTEX ||
5718 ctx->stage == MESA_SHADER_TESS_EVAL ||
5719 ctx->stage == MESA_SHADER_GEOMETRY) {
5720 int idx = variable->data.location + variable->data.index;
5721 if (idx == VARYING_SLOT_CLIP_DIST0) {
5722 int length = nir->info.clip_distance_array_size +
5723 nir->info.cull_distance_array_size;
5724
5725 if (length > 4)
5726 attrib_count = 2;
5727 else
5728 attrib_count = 1;
5729 }
5730 }
5731
5732 for (unsigned i = 0; i < attrib_count; ++i) {
5733 for (unsigned chan = 0; chan < 4; chan++) {
5734 ctx->abi->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5735 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5736 }
5737 }
5738 }
5739
5740 static LLVMTypeRef
5741 glsl_base_to_llvm_type(struct ac_llvm_context *ac,
5742 enum glsl_base_type type)
5743 {
5744 switch (type) {
5745 case GLSL_TYPE_INT:
5746 case GLSL_TYPE_UINT:
5747 case GLSL_TYPE_BOOL:
5748 case GLSL_TYPE_SUBROUTINE:
5749 return ac->i32;
5750 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5751 return ac->f32;
5752 case GLSL_TYPE_INT64:
5753 case GLSL_TYPE_UINT64:
5754 return ac->i64;
5755 case GLSL_TYPE_DOUBLE:
5756 return ac->f64;
5757 default:
5758 unreachable("unknown GLSL type");
5759 }
5760 }
5761
5762 static LLVMTypeRef
5763 glsl_to_llvm_type(struct ac_llvm_context *ac,
5764 const struct glsl_type *type)
5765 {
5766 if (glsl_type_is_scalar(type)) {
5767 return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
5768 }
5769
5770 if (glsl_type_is_vector(type)) {
5771 return LLVMVectorType(
5772 glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
5773 glsl_get_vector_elements(type));
5774 }
5775
5776 if (glsl_type_is_matrix(type)) {
5777 return LLVMArrayType(
5778 glsl_to_llvm_type(ac, glsl_get_column_type(type)),
5779 glsl_get_matrix_columns(type));
5780 }
5781
5782 if (glsl_type_is_array(type)) {
5783 return LLVMArrayType(
5784 glsl_to_llvm_type(ac, glsl_get_array_element(type)),
5785 glsl_get_length(type));
5786 }
5787
5788 assert(glsl_type_is_struct(type));
5789
5790 LLVMTypeRef member_types[glsl_get_length(type)];
5791
5792 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5793 member_types[i] =
5794 glsl_to_llvm_type(ac,
5795 glsl_get_struct_field(type, i));
5796 }
5797
5798 return LLVMStructTypeInContext(ac->context, member_types,
5799 glsl_get_length(type), false);
5800 }
5801
5802 static void
5803 setup_locals(struct ac_nir_context *ctx,
5804 struct nir_function *func)
5805 {
5806 int i, j;
5807 ctx->num_locals = 0;
5808 nir_foreach_variable(variable, &func->impl->locals) {
5809 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5810 variable->data.driver_location = ctx->num_locals * 4;
5811 variable->data.location_frac = 0;
5812 ctx->num_locals += attrib_count;
5813 }
5814 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5815 if (!ctx->locals)
5816 return;
5817
5818 for (i = 0; i < ctx->num_locals; i++) {
5819 for (j = 0; j < 4; j++) {
5820 ctx->locals[i * 4 + j] =
5821 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5822 }
5823 }
5824 }
5825
5826 static void
5827 setup_shared(struct ac_nir_context *ctx,
5828 struct nir_shader *nir)
5829 {
5830 nir_foreach_variable(variable, &nir->shared) {
5831 LLVMValueRef shared =
5832 LLVMAddGlobalInAddressSpace(
5833 ctx->ac.module, glsl_to_llvm_type(&ctx->ac, variable->type),
5834 variable->name ? variable->name : "",
5835 AC_LOCAL_ADDR_SPACE);
5836 _mesa_hash_table_insert(ctx->vars, variable, shared);
5837 }
5838 }
5839
5840 /* Initialize arguments for the shader export intrinsic */
5841 static void
5842 si_llvm_init_export_args(struct radv_shader_context *ctx,
5843 LLVMValueRef *values,
5844 unsigned target,
5845 struct ac_export_args *args)
5846 {
5847 /* Default is 0xf. Adjusted below depending on the format. */
5848 args->enabled_channels = 0xf;
5849
5850 /* Specify whether the EXEC mask represents the valid mask */
5851 args->valid_mask = 0;
5852
5853 /* Specify whether this is the last export */
5854 args->done = 0;
5855
5856 /* Specify the target we are exporting */
5857 args->target = target;
5858
5859 args->compr = false;
5860 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5861 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5862 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5863 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5864
5865 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5866 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5867 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5868 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5869 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5870 unsigned chan;
5871
5872 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5873 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5874 unsigned bits, bool hi) = NULL;
5875
5876 switch(col_format) {
5877 case V_028714_SPI_SHADER_ZERO:
5878 args->enabled_channels = 0; /* writemask */
5879 args->target = V_008DFC_SQ_EXP_NULL;
5880 break;
5881
5882 case V_028714_SPI_SHADER_32_R:
5883 args->enabled_channels = 1;
5884 args->out[0] = values[0];
5885 break;
5886
5887 case V_028714_SPI_SHADER_32_GR:
5888 args->enabled_channels = 0x3;
5889 args->out[0] = values[0];
5890 args->out[1] = values[1];
5891 break;
5892
5893 case V_028714_SPI_SHADER_32_AR:
5894 args->enabled_channels = 0x9;
5895 args->out[0] = values[0];
5896 args->out[3] = values[3];
5897 break;
5898
5899 case V_028714_SPI_SHADER_FP16_ABGR:
5900 packf = ac_build_cvt_pkrtz_f16;
5901 break;
5902
5903 case V_028714_SPI_SHADER_UNORM16_ABGR:
5904 packf = ac_build_cvt_pknorm_u16;
5905 break;
5906
5907 case V_028714_SPI_SHADER_SNORM16_ABGR:
5908 packf = ac_build_cvt_pknorm_i16;
5909 break;
5910
5911 case V_028714_SPI_SHADER_UINT16_ABGR:
5912 packi = ac_build_cvt_pk_u16;
5913 break;
5914
5915 case V_028714_SPI_SHADER_SINT16_ABGR:
5916 packi = ac_build_cvt_pk_i16;
5917 break;
5918
5919 default:
5920 case V_028714_SPI_SHADER_32_ABGR:
5921 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5922 break;
5923 }
5924
5925 /* Pack f16 or norm_i16/u16. */
5926 if (packf) {
5927 for (chan = 0; chan < 2; chan++) {
5928 LLVMValueRef pack_args[2] = {
5929 values[2 * chan],
5930 values[2 * chan + 1]
5931 };
5932 LLVMValueRef packed;
5933
5934 packed = packf(&ctx->ac, pack_args);
5935 args->out[chan] = ac_to_float(&ctx->ac, packed);
5936 }
5937 args->compr = 1; /* COMPR flag */
5938 }
5939
5940 /* Pack i16/u16. */
5941 if (packi) {
5942 for (chan = 0; chan < 2; chan++) {
5943 LLVMValueRef pack_args[2] = {
5944 ac_to_integer(&ctx->ac, values[2 * chan]),
5945 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5946 };
5947 LLVMValueRef packed;
5948
5949 packed = packi(&ctx->ac, pack_args,
5950 is_int8 ? 8 : is_int10 ? 10 : 16,
5951 chan == 1);
5952 args->out[chan] = ac_to_float(&ctx->ac, packed);
5953 }
5954 args->compr = 1; /* COMPR flag */
5955 }
5956 return;
5957 }
5958
5959 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5960
5961 for (unsigned i = 0; i < 4; ++i)
5962 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5963 }
5964
5965 static void
5966 radv_export_param(struct radv_shader_context *ctx, unsigned index,
5967 LLVMValueRef *values)
5968 {
5969 struct ac_export_args args;
5970
5971 si_llvm_init_export_args(ctx, values,
5972 V_008DFC_SQ_EXP_PARAM + index, &args);
5973 ac_build_export(&ctx->ac, &args);
5974 }
5975
5976 static LLVMValueRef
5977 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
5978 {
5979 LLVMValueRef output =
5980 ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
5981
5982 return LLVMBuildLoad(ctx->ac.builder, output, "");
5983 }
5984
5985 static void
5986 handle_vs_outputs_post(struct radv_shader_context *ctx,
5987 bool export_prim_id,
5988 struct ac_vs_output_info *outinfo)
5989 {
5990 uint32_t param_count = 0;
5991 unsigned target;
5992 unsigned pos_idx, num_pos_exports = 0;
5993 struct ac_export_args args, pos_args[4] = {};
5994 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5995 int i;
5996
5997 if (ctx->options->key.has_multiview_view_index) {
5998 LLVMValueRef* tmp_out = &ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5999 if(!*tmp_out) {
6000 for(unsigned i = 0; i < 4; ++i)
6001 ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
6002 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
6003 }
6004
6005 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
6006 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
6007 }
6008
6009 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6010 sizeof(outinfo->vs_output_param_offset));
6011
6012 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
6013 LLVMValueRef slots[8];
6014 unsigned j;
6015
6016 if (outinfo->cull_dist_mask)
6017 outinfo->cull_dist_mask <<= ctx->num_output_clips;
6018
6019 i = VARYING_SLOT_CLIP_DIST0;
6020 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
6021 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6022
6023 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
6024 slots[i] = LLVMGetUndef(ctx->ac.f32);
6025
6026 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
6027 target = V_008DFC_SQ_EXP_POS + 3;
6028 si_llvm_init_export_args(ctx, &slots[4], target, &args);
6029 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6030 &args, sizeof(args));
6031 }
6032
6033 target = V_008DFC_SQ_EXP_POS + 2;
6034 si_llvm_init_export_args(ctx, &slots[0], target, &args);
6035 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6036 &args, sizeof(args));
6037
6038 }
6039
6040 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
6041 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
6042 for (unsigned j = 0; j < 4; j++)
6043 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
6044 }
6045 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
6046
6047 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
6048 outinfo->writes_pointsize = true;
6049 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
6050 }
6051
6052 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
6053 outinfo->writes_layer = true;
6054 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
6055 }
6056
6057 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
6058 outinfo->writes_viewport_index = true;
6059 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
6060 }
6061
6062 if (outinfo->writes_pointsize ||
6063 outinfo->writes_layer ||
6064 outinfo->writes_viewport_index) {
6065 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
6066 (outinfo->writes_layer == true ? 4 : 0));
6067 pos_args[1].valid_mask = 0;
6068 pos_args[1].done = 0;
6069 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6070 pos_args[1].compr = 0;
6071 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6072 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6073 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6074 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6075
6076 if (outinfo->writes_pointsize == true)
6077 pos_args[1].out[0] = psize_value;
6078 if (outinfo->writes_layer == true)
6079 pos_args[1].out[2] = layer_value;
6080 if (outinfo->writes_viewport_index == true) {
6081 if (ctx->options->chip_class >= GFX9) {
6082 /* GFX9 has the layer in out.z[10:0] and the viewport
6083 * index in out.z[19:16].
6084 */
6085 LLVMValueRef v = viewport_index_value;
6086 v = ac_to_integer(&ctx->ac, v);
6087 v = LLVMBuildShl(ctx->ac.builder, v,
6088 LLVMConstInt(ctx->ac.i32, 16, false),
6089 "");
6090 v = LLVMBuildOr(ctx->ac.builder, v,
6091 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6092
6093 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6094 pos_args[1].enabled_channels |= 1 << 2;
6095 } else {
6096 pos_args[1].out[3] = viewport_index_value;
6097 pos_args[1].enabled_channels |= 1 << 3;
6098 }
6099 }
6100 }
6101 for (i = 0; i < 4; i++) {
6102 if (pos_args[i].out[0])
6103 num_pos_exports++;
6104 }
6105
6106 pos_idx = 0;
6107 for (i = 0; i < 4; i++) {
6108 if (!pos_args[i].out[0])
6109 continue;
6110
6111 /* Specify the target we are exporting */
6112 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6113 if (pos_idx == num_pos_exports)
6114 pos_args[i].done = 1;
6115 ac_build_export(&ctx->ac, &pos_args[i]);
6116 }
6117
6118 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6119 LLVMValueRef values[4];
6120 if (!(ctx->output_mask & (1ull << i)))
6121 continue;
6122
6123 if (i != VARYING_SLOT_LAYER &&
6124 i != VARYING_SLOT_PRIMITIVE_ID &&
6125 i < VARYING_SLOT_VAR0)
6126 continue;
6127
6128 for (unsigned j = 0; j < 4; j++)
6129 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6130
6131 radv_export_param(ctx, param_count, values);
6132
6133 outinfo->vs_output_param_offset[i] = param_count++;
6134 }
6135
6136 if (export_prim_id) {
6137 LLVMValueRef values[4];
6138
6139 values[0] = ctx->vs_prim_id;
6140 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6141 ctx->shader_info->vs.vgpr_comp_cnt);
6142 for (unsigned j = 1; j < 4; j++)
6143 values[j] = ctx->ac.f32_0;
6144
6145 radv_export_param(ctx, param_count, values);
6146
6147 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6148 outinfo->export_prim_id = true;
6149 }
6150
6151 outinfo->pos_exports = num_pos_exports;
6152 outinfo->param_exports = param_count;
6153 }
6154
6155 static void
6156 handle_es_outputs_post(struct radv_shader_context *ctx,
6157 struct ac_es_output_info *outinfo)
6158 {
6159 int j;
6160 uint64_t max_output_written = 0;
6161 LLVMValueRef lds_base = NULL;
6162
6163 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6164 int param_index;
6165 int length = 4;
6166
6167 if (!(ctx->output_mask & (1ull << i)))
6168 continue;
6169
6170 if (i == VARYING_SLOT_CLIP_DIST0)
6171 length = ctx->num_output_clips + ctx->num_output_culls;
6172
6173 param_index = shader_io_get_unique_index(i);
6174
6175 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6176 }
6177
6178 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6179
6180 if (ctx->ac.chip_class >= GFX9) {
6181 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6182 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6183 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6184 LLVMConstInt(ctx->ac.i32, 24, false),
6185 LLVMConstInt(ctx->ac.i32, 4, false), false);
6186 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6187 LLVMBuildMul(ctx->ac.builder, wave_idx,
6188 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6189 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6190 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6191 }
6192
6193 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6194 LLVMValueRef dw_addr = NULL;
6195 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6196 int param_index;
6197 int length = 4;
6198
6199 if (!(ctx->output_mask & (1ull << i)))
6200 continue;
6201
6202 if (i == VARYING_SLOT_CLIP_DIST0)
6203 length = ctx->num_output_clips + ctx->num_output_culls;
6204
6205 param_index = shader_io_get_unique_index(i);
6206
6207 if (lds_base) {
6208 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
6209 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6210 "");
6211 }
6212 for (j = 0; j < length; j++) {
6213 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
6214 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
6215
6216 if (ctx->ac.chip_class >= GFX9) {
6217 ac_lds_store(&ctx->ac, dw_addr,
6218 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6219 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6220 } else {
6221 ac_build_buffer_store_dword(&ctx->ac,
6222 ctx->esgs_ring,
6223 out_val, 1,
6224 NULL, ctx->es2gs_offset,
6225 (4 * param_index + j) * 4,
6226 1, 1, true, true);
6227 }
6228 }
6229 }
6230 }
6231
6232 static void
6233 handle_ls_outputs_post(struct radv_shader_context *ctx)
6234 {
6235 LLVMValueRef vertex_id = ctx->rel_auto_id;
6236 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6237 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
6238 vertex_dw_stride, "");
6239
6240 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6241 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6242 int length = 4;
6243
6244 if (!(ctx->output_mask & (1ull << i)))
6245 continue;
6246
6247 if (i == VARYING_SLOT_CLIP_DIST0)
6248 length = ctx->num_output_clips + ctx->num_output_culls;
6249 int param = shader_io_get_unique_index(i);
6250 mark_tess_output(ctx, false, param);
6251 if (length > 4)
6252 mark_tess_output(ctx, false, param + 1);
6253 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
6254 LLVMConstInt(ctx->ac.i32, param * 4, false),
6255 "");
6256 for (unsigned j = 0; j < length; j++) {
6257 ac_lds_store(&ctx->ac, dw_addr,
6258 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6259 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6260 }
6261 }
6262 }
6263
6264 struct ac_build_if_state
6265 {
6266 struct radv_shader_context *ctx;
6267 LLVMValueRef condition;
6268 LLVMBasicBlockRef entry_block;
6269 LLVMBasicBlockRef true_block;
6270 LLVMBasicBlockRef false_block;
6271 LLVMBasicBlockRef merge_block;
6272 };
6273
6274 static LLVMBasicBlockRef
6275 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
6276 {
6277 LLVMBasicBlockRef current_block;
6278 LLVMBasicBlockRef next_block;
6279 LLVMBasicBlockRef new_block;
6280
6281 /* get current basic block */
6282 current_block = LLVMGetInsertBlock(ctx->ac.builder);
6283
6284 /* chqeck if there's another block after this one */
6285 next_block = LLVMGetNextBasicBlock(current_block);
6286 if (next_block) {
6287 /* insert the new block before the next block */
6288 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6289 }
6290 else {
6291 /* append new block after current block */
6292 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6293 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6294 }
6295 return new_block;
6296 }
6297
6298 static void
6299 ac_nir_build_if(struct ac_build_if_state *ifthen,
6300 struct radv_shader_context *ctx,
6301 LLVMValueRef condition)
6302 {
6303 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
6304
6305 memset(ifthen, 0, sizeof *ifthen);
6306 ifthen->ctx = ctx;
6307 ifthen->condition = condition;
6308 ifthen->entry_block = block;
6309
6310 /* create endif/merge basic block for the phi functions */
6311 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6312
6313 /* create/insert true_block before merge_block */
6314 ifthen->true_block =
6315 LLVMInsertBasicBlockInContext(ctx->context,
6316 ifthen->merge_block,
6317 "if-true-block");
6318
6319 /* successive code goes into the true block */
6320 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
6321 }
6322
6323 /**
6324 * End a conditional.
6325 */
6326 static void
6327 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6328 {
6329 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
6330
6331 /* Insert branch to the merge block from current block */
6332 LLVMBuildBr(builder, ifthen->merge_block);
6333
6334 /*
6335 * Now patch in the various branch instructions.
6336 */
6337
6338 /* Insert the conditional branch instruction at the end of entry_block */
6339 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6340 if (ifthen->false_block) {
6341 /* we have an else clause */
6342 LLVMBuildCondBr(builder, ifthen->condition,
6343 ifthen->true_block, ifthen->false_block);
6344 }
6345 else {
6346 /* no else clause */
6347 LLVMBuildCondBr(builder, ifthen->condition,
6348 ifthen->true_block, ifthen->merge_block);
6349 }
6350
6351 /* Resume building code at end of the ifthen->merge_block */
6352 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6353 }
6354
6355 static void
6356 write_tess_factors(struct radv_shader_context *ctx)
6357 {
6358 unsigned stride, outer_comps, inner_comps;
6359 struct ac_build_if_state if_ctx, inner_if_ctx;
6360 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6361 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6362 unsigned tess_inner_index, tess_outer_index;
6363 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6364 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6365 int i;
6366 emit_barrier(&ctx->ac, ctx->stage);
6367
6368 switch (ctx->options->key.tcs.primitive_mode) {
6369 case GL_ISOLINES:
6370 stride = 2;
6371 outer_comps = 2;
6372 inner_comps = 0;
6373 break;
6374 case GL_TRIANGLES:
6375 stride = 4;
6376 outer_comps = 3;
6377 inner_comps = 1;
6378 break;
6379 case GL_QUADS:
6380 stride = 6;
6381 outer_comps = 4;
6382 inner_comps = 2;
6383 break;
6384 default:
6385 return;
6386 }
6387
6388 ac_nir_build_if(&if_ctx, ctx,
6389 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6390 invocation_id, ctx->ac.i32_0, ""));
6391
6392 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6393 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6394
6395 mark_tess_output(ctx, true, tess_inner_index);
6396 mark_tess_output(ctx, true, tess_outer_index);
6397 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6398 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
6399 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6400 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
6401 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6402
6403 for (i = 0; i < 4; i++) {
6404 inner[i] = LLVMGetUndef(ctx->ac.i32);
6405 outer[i] = LLVMGetUndef(ctx->ac.i32);
6406 }
6407
6408 // LINES reverseal
6409 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6410 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6411 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6412 ctx->ac.i32_1, "");
6413 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6414 } else {
6415 for (i = 0; i < outer_comps; i++) {
6416 outer[i] = out[i] =
6417 ac_lds_load(&ctx->ac, lds_outer);
6418 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6419 ctx->ac.i32_1, "");
6420 }
6421 for (i = 0; i < inner_comps; i++) {
6422 inner[i] = out[outer_comps+i] =
6423 ac_lds_load(&ctx->ac, lds_inner);
6424 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
6425 ctx->ac.i32_1, "");
6426 }
6427 }
6428
6429 /* Convert the outputs to vectors for stores. */
6430 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6431 vec1 = NULL;
6432
6433 if (stride > 4)
6434 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6435
6436
6437 buffer = ctx->hs_ring_tess_factor;
6438 tf_base = ctx->tess_factor_offset;
6439 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
6440 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6441 unsigned tf_offset = 0;
6442
6443 if (ctx->options->chip_class <= VI) {
6444 ac_nir_build_if(&inner_if_ctx, ctx,
6445 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6446 rel_patch_id, ctx->ac.i32_0, ""));
6447
6448 /* Store the dynamic HS control word. */
6449 ac_build_buffer_store_dword(&ctx->ac, buffer,
6450 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6451 1, ctx->ac.i32_0, tf_base,
6452 0, 1, 0, true, false);
6453 tf_offset += 4;
6454
6455 ac_nir_build_endif(&inner_if_ctx);
6456 }
6457
6458 /* Store the tessellation factors. */
6459 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6460 MIN2(stride, 4), byteoffset, tf_base,
6461 tf_offset, 1, 0, true, false);
6462 if (vec1)
6463 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6464 stride - 4, byteoffset, tf_base,
6465 16 + tf_offset, 1, 0, true, false);
6466
6467 //store to offchip for TES to read - only if TES reads them
6468 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6469 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6470 LLVMValueRef tf_inner_offset;
6471 unsigned param_outer, param_inner;
6472
6473 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6474 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6475 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6476
6477 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6478 util_next_power_of_two(outer_comps));
6479
6480 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6481 outer_comps, tf_outer_offset,
6482 ctx->oc_lds, 0, 1, 0, true, false);
6483 if (inner_comps) {
6484 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6485 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6486 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6487
6488 inner_vec = inner_comps == 1 ? inner[0] :
6489 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6490 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6491 inner_comps, tf_inner_offset,
6492 ctx->oc_lds, 0, 1, 0, true, false);
6493 }
6494 }
6495 ac_nir_build_endif(&if_ctx);
6496 }
6497
6498 static void
6499 handle_tcs_outputs_post(struct radv_shader_context *ctx)
6500 {
6501 write_tess_factors(ctx);
6502 }
6503
6504 static bool
6505 si_export_mrt_color(struct radv_shader_context *ctx,
6506 LLVMValueRef *color, unsigned index, bool is_last,
6507 struct ac_export_args *args)
6508 {
6509 /* Export */
6510 si_llvm_init_export_args(ctx, color,
6511 V_008DFC_SQ_EXP_MRT + index, args);
6512
6513 if (is_last) {
6514 args->valid_mask = 1; /* whether the EXEC mask is valid */
6515 args->done = 1; /* DONE bit */
6516 } else if (!args->enabled_channels)
6517 return false; /* unnecessary NULL export */
6518
6519 return true;
6520 }
6521
6522 static void
6523 radv_export_mrt_z(struct radv_shader_context *ctx,
6524 LLVMValueRef depth, LLVMValueRef stencil,
6525 LLVMValueRef samplemask)
6526 {
6527 struct ac_export_args args;
6528
6529 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6530
6531 ac_build_export(&ctx->ac, &args);
6532 }
6533
6534 static void
6535 handle_fs_outputs_post(struct radv_shader_context *ctx)
6536 {
6537 unsigned index = 0;
6538 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6539 struct ac_export_args color_args[8];
6540
6541 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6542 LLVMValueRef values[4];
6543 bool last = false;
6544
6545 if (!(ctx->output_mask & (1ull << i)))
6546 continue;
6547
6548 if (i < FRAG_RESULT_DATA0)
6549 continue;
6550
6551 for (unsigned j = 0; j < 4; j++)
6552 values[j] = ac_to_float(&ctx->ac,
6553 radv_load_output(ctx, i, j));
6554
6555 if (!ctx->shader_info->info.ps.writes_z &&
6556 !ctx->shader_info->info.ps.writes_stencil &&
6557 !ctx->shader_info->info.ps.writes_sample_mask)
6558 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6559
6560 bool ret = si_export_mrt_color(ctx, values,
6561 i - FRAG_RESULT_DATA0,
6562 last, &color_args[index]);
6563 if (ret)
6564 index++;
6565 }
6566
6567 /* Process depth, stencil, samplemask. */
6568 if (ctx->shader_info->info.ps.writes_z) {
6569 depth = ac_to_float(&ctx->ac,
6570 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6571 }
6572 if (ctx->shader_info->info.ps.writes_stencil) {
6573 stencil = ac_to_float(&ctx->ac,
6574 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6575 }
6576 if (ctx->shader_info->info.ps.writes_sample_mask) {
6577 samplemask = ac_to_float(&ctx->ac,
6578 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6579 }
6580
6581 /* Export PS outputs. */
6582 for (unsigned i = 0; i < index; i++)
6583 ac_build_export(&ctx->ac, &color_args[i]);
6584
6585 if (depth || stencil || samplemask)
6586 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6587 else if (!index)
6588 ac_build_export_null(&ctx->ac);
6589 }
6590
6591 static void
6592 emit_gs_epilogue(struct radv_shader_context *ctx)
6593 {
6594 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6595 }
6596
6597 static void
6598 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6599 LLVMValueRef *addrs)
6600 {
6601 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
6602
6603 switch (ctx->stage) {
6604 case MESA_SHADER_VERTEX:
6605 if (ctx->options->key.vs.as_ls)
6606 handle_ls_outputs_post(ctx);
6607 else if (ctx->options->key.vs.as_es)
6608 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6609 else
6610 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6611 &ctx->shader_info->vs.outinfo);
6612 break;
6613 case MESA_SHADER_FRAGMENT:
6614 handle_fs_outputs_post(ctx);
6615 break;
6616 case MESA_SHADER_GEOMETRY:
6617 emit_gs_epilogue(ctx);
6618 break;
6619 case MESA_SHADER_TESS_CTRL:
6620 handle_tcs_outputs_post(ctx);
6621 break;
6622 case MESA_SHADER_TESS_EVAL:
6623 if (ctx->options->key.tes.as_es)
6624 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6625 else
6626 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6627 &ctx->shader_info->tes.outinfo);
6628 break;
6629 default:
6630 break;
6631 }
6632 }
6633
6634 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
6635 {
6636 LLVMPassManagerRef passmgr;
6637 /* Create the pass manager */
6638 passmgr = LLVMCreateFunctionPassManagerForModule(
6639 ctx->ac.module);
6640
6641 /* This pass should eliminate all the load and store instructions */
6642 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6643
6644 /* Add some optimization passes */
6645 LLVMAddScalarReplAggregatesPass(passmgr);
6646 LLVMAddLICMPass(passmgr);
6647 LLVMAddAggressiveDCEPass(passmgr);
6648 LLVMAddCFGSimplificationPass(passmgr);
6649 LLVMAddInstructionCombiningPass(passmgr);
6650
6651 /* Run the pass */
6652 LLVMInitializeFunctionPassManager(passmgr);
6653 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6654 LLVMFinalizeFunctionPassManager(passmgr);
6655
6656 LLVMDisposeBuilder(ctx->ac.builder);
6657 LLVMDisposePassManager(passmgr);
6658 }
6659
6660 static void
6661 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
6662 {
6663 struct ac_vs_output_info *outinfo;
6664
6665 switch (ctx->stage) {
6666 case MESA_SHADER_FRAGMENT:
6667 case MESA_SHADER_COMPUTE:
6668 case MESA_SHADER_TESS_CTRL:
6669 case MESA_SHADER_GEOMETRY:
6670 return;
6671 case MESA_SHADER_VERTEX:
6672 if (ctx->options->key.vs.as_ls ||
6673 ctx->options->key.vs.as_es)
6674 return;
6675 outinfo = &ctx->shader_info->vs.outinfo;
6676 break;
6677 case MESA_SHADER_TESS_EVAL:
6678 if (ctx->options->key.vs.as_es)
6679 return;
6680 outinfo = &ctx->shader_info->tes.outinfo;
6681 break;
6682 default:
6683 unreachable("Unhandled shader type");
6684 }
6685
6686 ac_optimize_vs_outputs(&ctx->ac,
6687 ctx->main_function,
6688 outinfo->vs_output_param_offset,
6689 VARYING_SLOT_MAX,
6690 &outinfo->param_exports);
6691 }
6692
6693 static void
6694 ac_setup_rings(struct radv_shader_context *ctx)
6695 {
6696 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6697 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6698 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6699 }
6700
6701 if (ctx->is_gs_copy_shader) {
6702 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6703 }
6704 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6705 LLVMValueRef tmp;
6706 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6707 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6708
6709 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6710
6711 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6712 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6713 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
6714 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6715 }
6716
6717 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6718 ctx->stage == MESA_SHADER_TESS_EVAL) {
6719 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6720 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6721 }
6722 }
6723
6724 static unsigned
6725 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6726 const struct nir_shader *nir)
6727 {
6728 switch (nir->info.stage) {
6729 case MESA_SHADER_TESS_CTRL:
6730 return chip_class >= CIK ? 128 : 64;
6731 case MESA_SHADER_GEOMETRY:
6732 return chip_class >= GFX9 ? 128 : 64;
6733 case MESA_SHADER_COMPUTE:
6734 break;
6735 default:
6736 return 0;
6737 }
6738
6739 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6740 nir->info.cs.local_size[1] *
6741 nir->info.cs.local_size[2];
6742 return max_workgroup_size;
6743 }
6744
6745 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6746 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
6747 {
6748 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6749 LLVMConstInt(ctx->ac.i32, 8, false),
6750 LLVMConstInt(ctx->ac.i32, 8, false), false);
6751 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6752 ctx->ac.i32_0, "");
6753 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6754 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6755 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6756 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6757 }
6758
6759 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
6760 {
6761 for(int i = 5; i >= 0; --i) {
6762 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6763 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6764 LLVMConstInt(ctx->ac.i32, 16, false), false);
6765 }
6766
6767 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6768 LLVMConstInt(ctx->ac.i32, 16, false),
6769 LLVMConstInt(ctx->ac.i32, 8, false), false);
6770 }
6771
6772 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6773 struct nir_shader *nir)
6774 {
6775 struct ac_nir_context ctx = {};
6776 struct nir_function *func;
6777
6778 ctx.ac = *ac;
6779 ctx.abi = abi;
6780
6781 ctx.stage = nir->info.stage;
6782
6783 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6784
6785 nir_foreach_variable(variable, &nir->outputs)
6786 handle_shader_output_decl(&ctx, nir, variable);
6787
6788 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6789 _mesa_key_pointer_equal);
6790 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6791 _mesa_key_pointer_equal);
6792 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6793 _mesa_key_pointer_equal);
6794
6795 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6796
6797 setup_locals(&ctx, func);
6798
6799 if (nir->info.stage == MESA_SHADER_COMPUTE)
6800 setup_shared(&ctx, nir);
6801
6802 visit_cf_list(&ctx, &func->impl->body);
6803 phi_post_pass(&ctx);
6804
6805 if (nir->info.stage != MESA_SHADER_COMPUTE)
6806 ctx.abi->emit_outputs(ctx.abi, AC_LLVM_MAX_OUTPUTS,
6807 ctx.abi->outputs);
6808
6809 free(ctx.locals);
6810 ralloc_free(ctx.defs);
6811 ralloc_free(ctx.phis);
6812 ralloc_free(ctx.vars);
6813 }
6814
6815 static
6816 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6817 struct nir_shader *const *shaders,
6818 int shader_count,
6819 struct ac_shader_variant_info *shader_info,
6820 const struct ac_nir_compiler_options *options)
6821 {
6822 struct radv_shader_context ctx = {0};
6823 unsigned i;
6824 ctx.options = options;
6825 ctx.shader_info = shader_info;
6826 ctx.context = LLVMContextCreate();
6827
6828 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6829 options->family);
6830 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6831 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6832
6833 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6834 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6835 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
6836 LLVMDisposeTargetData(data_layout);
6837 LLVMDisposeMessage(data_layout_str);
6838
6839 enum ac_float_mode float_mode =
6840 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6841 AC_FLOAT_MODE_DEFAULT;
6842
6843 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
6844
6845 memset(shader_info, 0, sizeof(*shader_info));
6846
6847 for(int i = 0; i < shader_count; ++i)
6848 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6849
6850 for (i = 0; i < AC_UD_MAX_SETS; i++)
6851 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6852 for (i = 0; i < AC_UD_MAX_UD; i++)
6853 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6854
6855 ctx.max_workgroup_size = 0;
6856 for (int i = 0; i < shader_count; ++i) {
6857 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6858 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6859 shaders[i]));
6860 }
6861
6862 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6863 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6864
6865 ctx.abi.inputs = &ctx.inputs[0];
6866 ctx.abi.emit_outputs = handle_shader_outputs_post;
6867 ctx.abi.emit_vertex = visit_emit_vertex;
6868 ctx.abi.load_ubo = radv_load_ubo;
6869 ctx.abi.load_ssbo = radv_load_ssbo;
6870 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6871 ctx.abi.load_resource = radv_load_resource;
6872 ctx.abi.clamp_shadow_reference = false;
6873
6874 if (shader_count >= 2)
6875 ac_init_exec_full_mask(&ctx.ac);
6876
6877 if (ctx.ac.chip_class == GFX9 &&
6878 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6879 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6880
6881 for(int i = 0; i < shader_count; ++i) {
6882 ctx.stage = shaders[i]->info.stage;
6883 ctx.output_mask = 0;
6884 ctx.tess_outputs_written = 0;
6885 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6886 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6887
6888 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6889 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6890 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6891 ctx.abi.load_inputs = load_gs_input;
6892 ctx.abi.emit_primitive = visit_end_primitive;
6893 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6894 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6895 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6896 ctx.abi.load_tess_varyings = load_tcs_varyings;
6897 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6898 ctx.abi.store_tcs_outputs = store_tcs_output;
6899 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6900 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6901 ctx.abi.load_tess_varyings = load_tes_input;
6902 ctx.abi.load_tess_coord = load_tess_coord;
6903 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6904 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6905 if (shader_info->info.vs.needs_instance_id) {
6906 if (ctx.options->key.vs.as_ls) {
6907 ctx.shader_info->vs.vgpr_comp_cnt =
6908 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6909 } else {
6910 ctx.shader_info->vs.vgpr_comp_cnt =
6911 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6912 }
6913 }
6914 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6915 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6916 ctx.abi.lookup_interp_param = lookup_interp_param;
6917 ctx.abi.load_sample_position = load_sample_position;
6918 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6919 }
6920
6921 if (i)
6922 emit_barrier(&ctx.ac, ctx.stage);
6923
6924 ac_setup_rings(&ctx);
6925
6926 LLVMBasicBlockRef merge_block;
6927 if (shader_count >= 2) {
6928 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6929 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6930 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6931
6932 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6933 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6934 LLVMConstInt(ctx.ac.i32, 8, false), false);
6935 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6936 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6937 thread_id, count, "");
6938 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6939
6940 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6941 }
6942
6943 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6944 handle_fs_inputs(&ctx, shaders[i]);
6945 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6946 handle_vs_inputs(&ctx, shaders[i]);
6947 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6948 prepare_gs_input_vgprs(&ctx);
6949
6950 nir_foreach_variable(variable, &shaders[i]->outputs)
6951 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6952
6953 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
6954
6955 if (shader_count >= 2) {
6956 LLVMBuildBr(ctx.ac.builder, merge_block);
6957 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6958 }
6959
6960 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6961 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6962 shaders[i]->info.cull_distance_array_size > 4;
6963 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6964 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6965 shaders[i]->info.gs.vertices_out;
6966 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6967 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6968 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6969 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6970 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6971 }
6972 }
6973
6974 LLVMBuildRetVoid(ctx.ac.builder);
6975
6976 if (options->dump_preoptir)
6977 ac_dump_module(ctx.ac.module);
6978
6979 ac_llvm_finalize_module(&ctx);
6980
6981 if (shader_count == 1)
6982 ac_nir_eliminate_const_vs_outputs(&ctx);
6983
6984 return ctx.ac.module;
6985 }
6986
6987 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6988 {
6989 unsigned *retval = (unsigned *)context;
6990 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6991 char *description = LLVMGetDiagInfoDescription(di);
6992
6993 if (severity == LLVMDSError) {
6994 *retval = 1;
6995 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6996 description);
6997 }
6998
6999 LLVMDisposeMessage(description);
7000 }
7001
7002 static unsigned ac_llvm_compile(LLVMModuleRef M,
7003 struct ac_shader_binary *binary,
7004 LLVMTargetMachineRef tm)
7005 {
7006 unsigned retval = 0;
7007 char *err;
7008 LLVMContextRef llvm_ctx;
7009 LLVMMemoryBufferRef out_buffer;
7010 unsigned buffer_size;
7011 const char *buffer_data;
7012 LLVMBool mem_err;
7013
7014 /* Setup Diagnostic Handler*/
7015 llvm_ctx = LLVMGetModuleContext(M);
7016
7017 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
7018 &retval);
7019
7020 /* Compile IR*/
7021 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
7022 &err, &out_buffer);
7023
7024 /* Process Errors/Warnings */
7025 if (mem_err) {
7026 fprintf(stderr, "%s: %s", __FUNCTION__, err);
7027 free(err);
7028 retval = 1;
7029 goto out;
7030 }
7031
7032 /* Extract Shader Code*/
7033 buffer_size = LLVMGetBufferSize(out_buffer);
7034 buffer_data = LLVMGetBufferStart(out_buffer);
7035
7036 ac_elf_read(buffer_data, buffer_size, binary);
7037
7038 /* Clean up */
7039 LLVMDisposeMemoryBuffer(out_buffer);
7040
7041 out:
7042 return retval;
7043 }
7044
7045 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
7046 LLVMModuleRef llvm_module,
7047 struct ac_shader_binary *binary,
7048 struct ac_shader_config *config,
7049 struct ac_shader_variant_info *shader_info,
7050 gl_shader_stage stage,
7051 bool dump_shader, bool supports_spill)
7052 {
7053 if (dump_shader)
7054 ac_dump_module(llvm_module);
7055
7056 memset(binary, 0, sizeof(*binary));
7057 int v = ac_llvm_compile(llvm_module, binary, tm);
7058 if (v) {
7059 fprintf(stderr, "compile failed\n");
7060 }
7061
7062 if (dump_shader)
7063 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7064
7065 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7066
7067 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7068 LLVMDisposeModule(llvm_module);
7069 LLVMContextDispose(ctx);
7070
7071 if (stage == MESA_SHADER_FRAGMENT) {
7072 shader_info->num_input_vgprs = 0;
7073 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7074 shader_info->num_input_vgprs += 2;
7075 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7076 shader_info->num_input_vgprs += 2;
7077 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7078 shader_info->num_input_vgprs += 2;
7079 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7080 shader_info->num_input_vgprs += 3;
7081 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7082 shader_info->num_input_vgprs += 2;
7083 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7084 shader_info->num_input_vgprs += 2;
7085 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7086 shader_info->num_input_vgprs += 2;
7087 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7088 shader_info->num_input_vgprs += 1;
7089 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7090 shader_info->num_input_vgprs += 1;
7091 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7092 shader_info->num_input_vgprs += 1;
7093 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7094 shader_info->num_input_vgprs += 1;
7095 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7096 shader_info->num_input_vgprs += 1;
7097 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7098 shader_info->num_input_vgprs += 1;
7099 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7100 shader_info->num_input_vgprs += 1;
7101 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7102 shader_info->num_input_vgprs += 1;
7103 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7104 shader_info->num_input_vgprs += 1;
7105 }
7106 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7107
7108 /* +3 for scratch wave offset and VCC */
7109 config->num_sgprs = MAX2(config->num_sgprs,
7110 shader_info->num_input_sgprs + 3);
7111
7112 /* Enable 64-bit and 16-bit denormals, because there is no performance
7113 * cost.
7114 *
7115 * If denormals are enabled, all floating-point output modifiers are
7116 * ignored.
7117 *
7118 * Don't enable denormals for 32-bit floats, because:
7119 * - Floating-point output modifiers would be ignored by the hw.
7120 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7121 * have to stop using those.
7122 * - SI & CI would be very slow.
7123 */
7124 config->float_mode |= V_00B028_FP_64_DENORMS;
7125 }
7126
7127 static void
7128 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7129 {
7130 switch (nir->info.stage) {
7131 case MESA_SHADER_COMPUTE:
7132 for (int i = 0; i < 3; ++i)
7133 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7134 break;
7135 case MESA_SHADER_FRAGMENT:
7136 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7137 break;
7138 case MESA_SHADER_GEOMETRY:
7139 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7140 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7141 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7142 shader_info->gs.invocations = nir->info.gs.invocations;
7143 break;
7144 case MESA_SHADER_TESS_EVAL:
7145 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7146 shader_info->tes.spacing = nir->info.tess.spacing;
7147 shader_info->tes.ccw = nir->info.tess.ccw;
7148 shader_info->tes.point_mode = nir->info.tess.point_mode;
7149 shader_info->tes.as_es = options->key.tes.as_es;
7150 break;
7151 case MESA_SHADER_TESS_CTRL:
7152 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7153 break;
7154 case MESA_SHADER_VERTEX:
7155 shader_info->vs.as_es = options->key.vs.as_es;
7156 shader_info->vs.as_ls = options->key.vs.as_ls;
7157 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7158 if (options->key.vs.as_ls)
7159 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7160 break;
7161 default:
7162 break;
7163 }
7164 }
7165
7166 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7167 struct ac_shader_binary *binary,
7168 struct ac_shader_config *config,
7169 struct ac_shader_variant_info *shader_info,
7170 struct nir_shader *const *nir,
7171 int nir_count,
7172 const struct ac_nir_compiler_options *options,
7173 bool dump_shader)
7174 {
7175
7176 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7177 options);
7178
7179 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7180 for (int i = 0; i < nir_count; ++i)
7181 ac_fill_shader_info(shader_info, nir[i], options);
7182
7183 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7184 if (options->chip_class == GFX9) {
7185 if (nir_count == 2 &&
7186 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7187 shader_info->gs.es_type = nir[0]->info.stage;
7188 }
7189 }
7190 }
7191
7192 static void
7193 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
7194 {
7195 LLVMValueRef vtx_offset =
7196 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
7197 LLVMConstInt(ctx->ac.i32, 4, false), "");
7198 int idx = 0;
7199
7200 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
7201 int length = 4;
7202 int slot = idx;
7203 int slot_inc = 1;
7204 if (!(ctx->output_mask & (1ull << i)))
7205 continue;
7206
7207 if (i == VARYING_SLOT_CLIP_DIST0) {
7208 /* unpack clip and cull from a single set of slots */
7209 length = ctx->num_output_clips + ctx->num_output_culls;
7210 if (length > 4)
7211 slot_inc = 2;
7212 }
7213
7214 for (unsigned j = 0; j < length; j++) {
7215 LLVMValueRef value, soffset;
7216
7217 soffset = LLVMConstInt(ctx->ac.i32,
7218 (slot * 4 + j) *
7219 ctx->gs_max_out_vertices * 16 * 4, false);
7220
7221 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7222 1, ctx->ac.i32_0,
7223 vtx_offset, soffset,
7224 0, 1, 1, true, false);
7225
7226 LLVMBuildStore(ctx->ac.builder,
7227 ac_to_float(&ctx->ac, value), ctx->abi.outputs[radeon_llvm_reg_index_soa(i, j)]);
7228 }
7229 idx += slot_inc;
7230 }
7231 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7232 }
7233
7234 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7235 struct nir_shader *geom_shader,
7236 struct ac_shader_binary *binary,
7237 struct ac_shader_config *config,
7238 struct ac_shader_variant_info *shader_info,
7239 const struct ac_nir_compiler_options *options,
7240 bool dump_shader)
7241 {
7242 struct radv_shader_context ctx = {0};
7243 ctx.context = LLVMContextCreate();
7244 ctx.options = options;
7245 ctx.shader_info = shader_info;
7246
7247 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7248 options->family);
7249 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7250
7251 ctx.is_gs_copy_shader = true;
7252 LLVMSetTarget(ctx.ac.module, "amdgcn--");
7253
7254 enum ac_float_mode float_mode =
7255 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7256 AC_FLOAT_MODE_DEFAULT;
7257
7258 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
7259 ctx.stage = MESA_SHADER_VERTEX;
7260
7261 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7262
7263 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7264 ac_setup_rings(&ctx);
7265
7266 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7267 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7268
7269 struct ac_nir_context nir_ctx = {};
7270 nir_ctx.ac = ctx.ac;
7271 nir_ctx.abi = &ctx.abi;
7272
7273 nir_foreach_variable(variable, &geom_shader->outputs) {
7274 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7275 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7276 }
7277
7278 ac_gs_copy_shader_emit(&ctx);
7279
7280 LLVMBuildRetVoid(ctx.ac.builder);
7281
7282 ac_llvm_finalize_module(&ctx);
7283
7284 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
7285 MESA_SHADER_VERTEX,
7286 dump_shader, options->supports_spill);
7287 }