projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv/ac: add initial pre-pass for shader info gathering
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_info.h"
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83 LLVMValueRef ls_out_layout;
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef tcs_offchip_layout;
87 LLVMValueRef tcs_out_offsets;
88 LLVMValueRef tcs_out_layout;
89 LLVMValueRef tcs_in_layout;
90 LLVMValueRef oc_lds;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tcs_patch_id;
93 LLVMValueRef tcs_rel_ids;
94 LLVMValueRef tes_rel_patch_id;
95 LLVMValueRef tes_patch_id;
96 LLVMValueRef tes_u;
97 LLVMValueRef tes_v;
98
99 LLVMValueRef gsvs_ring_stride;
100 LLVMValueRef gsvs_num_entries;
101 LLVMValueRef gs2vs_offset;
102 LLVMValueRef gs_wave_id;
103 LLVMValueRef gs_vtx_offset[6];
104 LLVMValueRef gs_prim_id, gs_invocation_id;
105
106 LLVMValueRef esgs_ring;
107 LLVMValueRef gsvs_ring;
108 LLVMValueRef hs_ring_tess_offchip;
109 LLVMValueRef hs_ring_tess_factor;
110
111 LLVMValueRef prim_mask;
112 LLVMValueRef sample_pos_offset;
113 LLVMValueRef persp_sample, persp_center, persp_centroid;
114 LLVMValueRef linear_sample, linear_center, linear_centroid;
115 LLVMValueRef front_face;
116 LLVMValueRef ancillary;
117 LLVMValueRef sample_coverage;
118 LLVMValueRef frag_pos[4];
119
120 LLVMBasicBlockRef continue_block;
121 LLVMBasicBlockRef break_block;
122
123 LLVMTypeRef i1;
124 LLVMTypeRef i8;
125 LLVMTypeRef i16;
126 LLVMTypeRef i32;
127 LLVMTypeRef i64;
128 LLVMTypeRef v2i32;
129 LLVMTypeRef v3i32;
130 LLVMTypeRef v4i32;
131 LLVMTypeRef v8i32;
132 LLVMTypeRef f64;
133 LLVMTypeRef f32;
134 LLVMTypeRef f16;
135 LLVMTypeRef v2f32;
136 LLVMTypeRef v4f32;
137 LLVMTypeRef v16i8;
138 LLVMTypeRef voidt;
139
140 LLVMValueRef i1true;
141 LLVMValueRef i1false;
142 LLVMValueRef i32zero;
143 LLVMValueRef i32one;
144 LLVMValueRef f32zero;
145 LLVMValueRef f32one;
146 LLVMValueRef v4f32empty;
147
148 unsigned uniform_md_kind;
149 LLVMValueRef empty_md;
150 gl_shader_stage stage;
151
152 LLVMValueRef lds;
153 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
154 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
155
156 LLVMValueRef shared_memory;
157 uint64_t input_mask;
158 uint64_t output_mask;
159 int num_locals;
160 LLVMValueRef *locals;
161 bool has_ddxy;
162 uint8_t num_output_clips;
163 uint8_t num_output_culls;
164
165 bool has_ds_bpermute;
166
167 bool is_gs_copy_shader;
168 LLVMValueRef gs_next_vertex;
169 unsigned gs_max_out_vertices;
170
171 unsigned tes_primitive_mode;
172 uint64_t tess_outputs_written;
173 uint64_t tess_patch_outputs_written;
174 };
175
176 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
177 nir_deref_var *deref,
178 enum desc_type desc_type);
179 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
180 {
181 return (index * 4) + chan;
182 }
183
184 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
185 {
186 /* handle patch indices separate */
187 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
188 return 0;
189 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
190 return 1;
191 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
192 return 2 + (slot - VARYING_SLOT_PATCH0);
193
194 if (slot == VARYING_SLOT_POS)
195 return 0;
196 if (slot == VARYING_SLOT_PSIZ)
197 return 1;
198 if (slot == VARYING_SLOT_CLIP_DIST0)
199 return 2;
200 /* 3 is reserved for clip dist as well */
201 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
202 return 4 + (slot - VARYING_SLOT_VAR0);
203 unreachable("illegal slot in get unique index\n");
204 }
205
206 static unsigned llvm_get_type_size(LLVMTypeRef type)
207 {
208 LLVMTypeKind kind = LLVMGetTypeKind(type);
209
210 switch (kind) {
211 case LLVMIntegerTypeKind:
212 return LLVMGetIntTypeWidth(type) / 8;
213 case LLVMFloatTypeKind:
214 return 4;
215 case LLVMPointerTypeKind:
216 return 8;
217 case LLVMVectorTypeKind:
218 return LLVMGetVectorSize(type) *
219 llvm_get_type_size(LLVMGetElementType(type));
220 default:
221 assert(0);
222 return 0;
223 }
224 }
225
226 static void set_llvm_calling_convention(LLVMValueRef func,
227 gl_shader_stage stage)
228 {
229 enum radeon_llvm_calling_convention calling_conv;
230
231 switch (stage) {
232 case MESA_SHADER_VERTEX:
233 case MESA_SHADER_TESS_CTRL:
234 case MESA_SHADER_TESS_EVAL:
235 calling_conv = RADEON_LLVM_AMDGPU_VS;
236 break;
237 case MESA_SHADER_GEOMETRY:
238 calling_conv = RADEON_LLVM_AMDGPU_GS;
239 break;
240 case MESA_SHADER_FRAGMENT:
241 calling_conv = RADEON_LLVM_AMDGPU_PS;
242 break;
243 case MESA_SHADER_COMPUTE:
244 calling_conv = RADEON_LLVM_AMDGPU_CS;
245 break;
246 default:
247 unreachable("Unhandle shader type");
248 }
249
250 LLVMSetFunctionCallConv(func, calling_conv);
251 }
252
253 static LLVMValueRef
254 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
255 LLVMBuilderRef builder, LLVMTypeRef *return_types,
256 unsigned num_return_elems, LLVMTypeRef *param_types,
257 unsigned param_count, unsigned array_params_mask,
258 unsigned sgpr_params, bool unsafe_math)
259 {
260 LLVMTypeRef main_function_type, ret_type;
261 LLVMBasicBlockRef main_function_body;
262
263 if (num_return_elems)
264 ret_type = LLVMStructTypeInContext(ctx, return_types,
265 num_return_elems, true);
266 else
267 ret_type = LLVMVoidTypeInContext(ctx);
268
269 /* Setup the function */
270 main_function_type =
271 LLVMFunctionType(ret_type, param_types, param_count, 0);
272 LLVMValueRef main_function =
273 LLVMAddFunction(module, "main", main_function_type);
274 main_function_body =
275 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
276 LLVMPositionBuilderAtEnd(builder, main_function_body);
277
278 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
279 for (unsigned i = 0; i < sgpr_params; ++i) {
280 if (array_params_mask & (1 << i)) {
281 LLVMValueRef P = LLVMGetParam(main_function, i);
282 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
283 ac_add_attr_dereferenceable(P, UINT64_MAX);
284 }
285 else {
286 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
287 }
288 }
289
290 if (unsafe_math) {
291 /* These were copied from some LLVM test. */
292 LLVMAddTargetDependentFunctionAttr(main_function,
293 "less-precise-fpmad",
294 "true");
295 LLVMAddTargetDependentFunctionAttr(main_function,
296 "no-infs-fp-math",
297 "true");
298 LLVMAddTargetDependentFunctionAttr(main_function,
299 "no-nans-fp-math",
300 "true");
301 LLVMAddTargetDependentFunctionAttr(main_function,
302 "unsafe-fp-math",
303 "true");
304 }
305 return main_function;
306 }
307
308 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
309 {
310 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
311 CONST_ADDR_SPACE);
312 }
313
314 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
315 int idx,
316 LLVMTypeRef type)
317 {
318 LLVMValueRef offset;
319 LLVMValueRef ptr;
320 int addr_space;
321
322 offset = LLVMConstInt(ctx->i32, idx * 16, false);
323
324 ptr = ctx->shared_memory;
325 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
326 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
327 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
328 return ptr;
329 }
330
331 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
332 {
333 if (t == ctx->f16 || t == ctx->i16)
334 return ctx->i16;
335 else if (t == ctx->f32 || t == ctx->i32)
336 return ctx->i32;
337 else if (t == ctx->f64 || t == ctx->i64)
338 return ctx->i64;
339 else
340 unreachable("Unhandled integer size");
341 }
342
343 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
344 {
345 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
346 LLVMTypeRef elem_type = LLVMGetElementType(t);
347 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
348 LLVMGetVectorSize(t));
349 }
350 return to_integer_type_scalar(ctx, t);
351 }
352
353 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
354 {
355 LLVMTypeRef type = LLVMTypeOf(v);
356 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
357 }
358
359 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
360 {
361 if (t == ctx->i16 || t == ctx->f16)
362 return ctx->f16;
363 else if (t == ctx->i32 || t == ctx->f32)
364 return ctx->f32;
365 else if (t == ctx->i64 || t == ctx->f64)
366 return ctx->f64;
367 else
368 unreachable("Unhandled float size");
369 }
370
371 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
372 {
373 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
374 LLVMTypeRef elem_type = LLVMGetElementType(t);
375 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
376 LLVMGetVectorSize(t));
377 }
378 return to_float_type_scalar(ctx, t);
379 }
380
381 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
382 {
383 LLVMTypeRef type = LLVMTypeOf(v);
384 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
385 }
386
387 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
388 {
389 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
390 type = LLVMGetElementType(type);
391
392 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
393 return LLVMGetIntTypeWidth(type);
394
395 if (type == ctx->f16)
396 return 16;
397 if (type == ctx->f32)
398 return 32;
399 if (type == ctx->f64)
400 return 64;
401
402 unreachable("Unhandled type kind in get_elem_bits");
403 }
404
405 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
406 LLVMValueRef param, unsigned rshift,
407 unsigned bitwidth)
408 {
409 LLVMValueRef value = param;
410 if (rshift)
411 value = LLVMBuildLShr(ctx->builder, value,
412 LLVMConstInt(ctx->i32, rshift, false), "");
413
414 if (rshift + bitwidth < 32) {
415 unsigned mask = (1 << bitwidth) - 1;
416 value = LLVMBuildAnd(ctx->builder, value,
417 LLVMConstInt(ctx->i32, mask, false), "");
418 }
419 return value;
420 }
421
422 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
423 {
424 switch (ctx->stage) {
425 case MESA_SHADER_TESS_CTRL:
426 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
427 case MESA_SHADER_TESS_EVAL:
428 return ctx->tes_rel_patch_id;
429 break;
430 default:
431 unreachable("Illegal stage");
432 }
433 }
434
435 /* Tessellation shaders pass outputs to the next shader using LDS.
436 *
437 * LS outputs = TCS inputs
438 * TCS outputs = TES inputs
439 *
440 * The LDS layout is:
441 * - TCS inputs for patch 0
442 * - TCS inputs for patch 1
443 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
444 * - ...
445 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
446 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
447 * - TCS outputs for patch 1
448 * - Per-patch TCS outputs for patch 1
449 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
450 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
451 * - ...
452 *
453 * All three shaders VS(LS), TCS, TES share the same LDS space.
454 */
455 static LLVMValueRef
456 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
457 {
458 if (ctx->stage == MESA_SHADER_VERTEX)
459 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
460 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
461 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
462 else {
463 assert(0);
464 return NULL;
465 }
466 }
467
468 static LLVMValueRef
469 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
470 {
471 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
472 }
473
474 static LLVMValueRef
475 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
476 {
477 return LLVMBuildMul(ctx->builder,
478 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
479 LLVMConstInt(ctx->i32, 4, false), "");
480 }
481
482 static LLVMValueRef
483 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
484 {
485 return LLVMBuildMul(ctx->builder,
486 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
487 LLVMConstInt(ctx->i32, 4, false), "");
488 }
489
490 static LLVMValueRef
491 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
494 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
495
496 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
497 }
498
499 static LLVMValueRef
500 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
501 {
502 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
503 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
504 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
505
506 return LLVMBuildAdd(ctx->builder, patch0_offset,
507 LLVMBuildMul(ctx->builder, patch_stride,
508 rel_patch_id, ""),
509 "");
510 }
511
512 static LLVMValueRef
513 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
514 {
515 LLVMValueRef patch0_patch_data_offset =
516 get_tcs_out_patch0_patch_data_offset(ctx);
517 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
518 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
519
520 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
521 LLVMBuildMul(ctx->builder, patch_stride,
522 rel_patch_id, ""),
523 "");
524 }
525
526 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
527 {
528 ud_info->sgpr_idx = sgpr_idx;
529 ud_info->num_sgprs = num_sgprs;
530 ud_info->indirect = false;
531 ud_info->indirect_offset = 0;
532 }
533
534 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
535 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
536 {
537 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
538 }
539
540 #if 0
541 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
542 uint32_t indirect_offset)
543 {
544 ud_info->sgpr_idx = sgpr_idx;
545 ud_info->num_sgprs = num_sgprs;
546 ud_info->indirect = true;
547 ud_info->indirect_offset = indirect_offset;
548 }
549 #endif
550
551 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
552 {
553 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
554 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
555 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
556 "tess_lds");
557 }
558
559 static void create_function(struct nir_to_llvm_context *ctx)
560 {
561 LLVMTypeRef arg_types[23];
562 unsigned arg_idx = 0;
563 unsigned array_params_mask = 0;
564 unsigned sgpr_count = 0, user_sgpr_count;
565 unsigned i;
566 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
567 unsigned user_sgpr_idx;
568 bool need_push_constants;
569 bool need_ring_offsets = false;
570
571 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
572 if (ctx->stage == MESA_SHADER_GEOMETRY ||
573 ctx->stage == MESA_SHADER_VERTEX ||
574 ctx->stage == MESA_SHADER_TESS_CTRL ||
575 ctx->stage == MESA_SHADER_TESS_EVAL ||
576 ctx->stage == MESA_SHADER_FRAGMENT ||
577 ctx->is_gs_copy_shader)
578 need_ring_offsets = true;
579
580 need_push_constants = true;
581 if (!ctx->options->layout)
582 need_push_constants = false;
583 else if (!ctx->options->layout->push_constant_size &&
584 !ctx->options->layout->dynamic_offset_count)
585 need_push_constants = false;
586
587 if (need_ring_offsets && !ctx->options->supports_spill) {
588 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* address of rings */
589 }
590
591 /* 1 for each descriptor set */
592 for (unsigned i = 0; i < num_sets; ++i) {
593 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
594 array_params_mask |= (1 << arg_idx);
595 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
596 }
597 }
598
599 if (need_push_constants) {
600 /* 1 for push constants and dynamic descriptors */
601 array_params_mask |= (1 << arg_idx);
602 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
603 }
604
605 switch (ctx->stage) {
606 case MESA_SHADER_COMPUTE:
607 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
608 user_sgpr_count = arg_idx;
609 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
610 arg_types[arg_idx++] = ctx->i32;
611 sgpr_count = arg_idx;
612
613 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
614 break;
615 case MESA_SHADER_VERTEX:
616 if (!ctx->is_gs_copy_shader) {
617 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
618 arg_types[arg_idx++] = ctx->i32; // base vertex
619 arg_types[arg_idx++] = ctx->i32; // start instance
620 arg_types[arg_idx++] = ctx->i32; // draw index
621 }
622 user_sgpr_count = arg_idx;
623 if (ctx->options->key.vs.as_es)
624 arg_types[arg_idx++] = ctx->i32; //es2gs offset
625 else if (ctx->options->key.vs.as_ls) {
626 arg_types[arg_idx++] = ctx->i32; //ls out layout
627 user_sgpr_count++;
628 }
629 sgpr_count = arg_idx;
630 arg_types[arg_idx++] = ctx->i32; // vertex id
631 if (!ctx->is_gs_copy_shader) {
632 arg_types[arg_idx++] = ctx->i32; // rel auto id
633 arg_types[arg_idx++] = ctx->i32; // vs prim id
634 arg_types[arg_idx++] = ctx->i32; // instance id
635 }
636 break;
637 case MESA_SHADER_TESS_CTRL:
638 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
639 arg_types[arg_idx++] = ctx->i32; // tcs out offsets
640 arg_types[arg_idx++] = ctx->i32; // tcs out layout
641 arg_types[arg_idx++] = ctx->i32; // tcs in layout
642 user_sgpr_count = arg_idx;
643 arg_types[arg_idx++] = ctx->i32; // param oc lds
644 arg_types[arg_idx++] = ctx->i32; // tess factor offset
645 sgpr_count = arg_idx;
646 arg_types[arg_idx++] = ctx->i32; // patch id
647 arg_types[arg_idx++] = ctx->i32; // rel ids;
648 break;
649 case MESA_SHADER_TESS_EVAL:
650 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
651 user_sgpr_count = arg_idx;
652 if (ctx->options->key.tes.as_es) {
653 arg_types[arg_idx++] = ctx->i32; // OC LDS
654 arg_types[arg_idx++] = ctx->i32; //
655 arg_types[arg_idx++] = ctx->i32; // es2gs offset
656 } else {
657 arg_types[arg_idx++] = ctx->i32; //
658 arg_types[arg_idx++] = ctx->i32; // OC LDS
659 }
660 sgpr_count = arg_idx;
661 arg_types[arg_idx++] = ctx->f32; // tes_u
662 arg_types[arg_idx++] = ctx->f32; // tes_v
663 arg_types[arg_idx++] = ctx->i32; // tes rel patch id
664 arg_types[arg_idx++] = ctx->i32; // tes patch id
665 break;
666 case MESA_SHADER_GEOMETRY:
667 arg_types[arg_idx++] = ctx->i32; // gsvs stride
668 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
669 user_sgpr_count = arg_idx;
670 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
671 arg_types[arg_idx++] = ctx->i32; // wave id
672 sgpr_count = arg_idx;
673 arg_types[arg_idx++] = ctx->i32; // vtx0
674 arg_types[arg_idx++] = ctx->i32; // vtx1
675 arg_types[arg_idx++] = ctx->i32; // prim id
676 arg_types[arg_idx++] = ctx->i32; // vtx2
677 arg_types[arg_idx++] = ctx->i32; // vtx3
678 arg_types[arg_idx++] = ctx->i32; // vtx4
679 arg_types[arg_idx++] = ctx->i32; // vtx5
680 arg_types[arg_idx++] = ctx->i32; // GS instance id
681 break;
682 case MESA_SHADER_FRAGMENT:
683 if (ctx->shader_info->info.ps.needs_sample_positions)
684 arg_types[arg_idx++] = ctx->i32; /* sample position offset */
685 user_sgpr_count = arg_idx;
686 arg_types[arg_idx++] = ctx->i32; /* prim mask */
687 sgpr_count = arg_idx;
688 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
689 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
690 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
691 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
692 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
693 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
694 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
695 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
696 arg_types[arg_idx++] = ctx->f32; /* pos x float */
697 arg_types[arg_idx++] = ctx->f32; /* pos y float */
698 arg_types[arg_idx++] = ctx->f32; /* pos z float */
699 arg_types[arg_idx++] = ctx->f32; /* pos w float */
700 arg_types[arg_idx++] = ctx->i32; /* front face */
701 arg_types[arg_idx++] = ctx->i32; /* ancillary */
702 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
703 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
704 break;
705 default:
706 unreachable("Shader stage not implemented");
707 }
708
709 ctx->main_function = create_llvm_function(
710 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
711 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
712 set_llvm_calling_convention(ctx->main_function, ctx->stage);
713
714 ctx->shader_info->num_input_sgprs = 0;
715 ctx->shader_info->num_input_vgprs = 0;
716
717 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
718 for (i = 0; i < user_sgpr_count; i++)
719 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
720
721 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
722 for (; i < sgpr_count; i++)
723 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
724
725 if (ctx->stage != MESA_SHADER_FRAGMENT)
726 for (; i < arg_idx; ++i)
727 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
728
729 arg_idx = 0;
730 user_sgpr_idx = 0;
731
732 if (ctx->options->supports_spill || need_ring_offsets) {
733 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
734 user_sgpr_idx += 2;
735 if (ctx->options->supports_spill) {
736 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
737 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
738 NULL, 0, AC_FUNC_ATTR_READNONE);
739 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
740 const_array(ctx->v16i8, 16), "");
741 } else
742 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
743 }
744
745 for (unsigned i = 0; i < num_sets; ++i) {
746 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
747 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
748 user_sgpr_idx += 2;
749 ctx->descriptor_sets[i] =
750 LLVMGetParam(ctx->main_function, arg_idx++);
751 } else
752 ctx->descriptor_sets[i] = NULL;
753 }
754
755 if (need_push_constants) {
756 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
757 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
758 user_sgpr_idx += 2;
759 }
760
761 switch (ctx->stage) {
762 case MESA_SHADER_COMPUTE:
763 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
764 user_sgpr_idx += 3;
765 ctx->num_work_groups =
766 LLVMGetParam(ctx->main_function, arg_idx++);
767 ctx->workgroup_ids =
768 LLVMGetParam(ctx->main_function, arg_idx++);
769 ctx->tg_size =
770 LLVMGetParam(ctx->main_function, arg_idx++);
771 ctx->local_invocation_ids =
772 LLVMGetParam(ctx->main_function, arg_idx++);
773 break;
774 case MESA_SHADER_VERTEX:
775 if (!ctx->is_gs_copy_shader) {
776 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
777 user_sgpr_idx += 2;
778 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
779 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
780 user_sgpr_idx += 3;
781 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
782 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
783 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
784 }
785 if (ctx->options->key.vs.as_es)
786 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
787 else if (ctx->options->key.vs.as_ls) {
788 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, user_sgpr_idx, 1);
789 user_sgpr_idx += 1;
790 ctx->ls_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
791 }
792 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
793 if (!ctx->is_gs_copy_shader) {
794 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
795 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
796 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
797 }
798 if (ctx->options->key.vs.as_ls)
799 declare_tess_lds(ctx);
800 break;
801 case MESA_SHADER_TESS_CTRL:
802 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, user_sgpr_idx, 4);
803 user_sgpr_idx += 4;
804 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
805 ctx->tcs_out_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
806 ctx->tcs_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
807 ctx->tcs_in_layout = LLVMGetParam(ctx->main_function, arg_idx++);
808 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
809 ctx->tess_factor_offset = LLVMGetParam(ctx->main_function, arg_idx++);
810 ctx->tcs_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
811 ctx->tcs_rel_ids = LLVMGetParam(ctx->main_function, arg_idx++);
812
813 declare_tess_lds(ctx);
814 break;
815 case MESA_SHADER_TESS_EVAL:
816 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, user_sgpr_idx, 1);
817 user_sgpr_idx += 1;
818 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
819 if (ctx->options->key.tes.as_es) {
820 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
821 arg_idx++;
822 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
823 } else {
824 arg_idx++;
825 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
826 }
827 ctx->tes_u = LLVMGetParam(ctx->main_function, arg_idx++);
828 ctx->tes_v = LLVMGetParam(ctx->main_function, arg_idx++);
829 ctx->tes_rel_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
830 ctx->tes_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
831 break;
832 case MESA_SHADER_GEOMETRY:
833 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
834 user_sgpr_idx += 2;
835 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
836 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
837 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
838 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
839 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
840 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
841 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
842 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
843 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
844 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
845 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
846 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
847 break;
848 case MESA_SHADER_FRAGMENT:
849 if (ctx->shader_info->info.ps.needs_sample_positions) {
850 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, user_sgpr_idx, 1);
851 user_sgpr_idx += 1;
852 ctx->sample_pos_offset = LLVMGetParam(ctx->main_function, arg_idx++);
853 }
854 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
855 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
856 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
857 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
858 arg_idx++;
859 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
860 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
861 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
862 arg_idx++; /* line stipple */
863 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
864 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
865 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
866 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
867 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
868 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
869 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
870 break;
871 default:
872 unreachable("Shader stage not implemented");
873 }
874 }
875
876 static void setup_types(struct nir_to_llvm_context *ctx)
877 {
878 LLVMValueRef args[4];
879
880 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
881 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
882 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
883 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
884 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
885 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
886 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
887 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
888 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
889 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
890 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
891 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
892 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
893 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
894 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
895 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
896
897 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
898 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
899 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
900 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
901 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
902 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
903
904 args[0] = ctx->f32zero;
905 args[1] = ctx->f32zero;
906 args[2] = ctx->f32zero;
907 args[3] = ctx->f32one;
908 ctx->v4f32empty = LLVMConstVector(args, 4);
909
910 ctx->uniform_md_kind =
911 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
912 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
913
914 args[0] = LLVMConstReal(ctx->f32, 2.5);
915 }
916
917 static int get_llvm_num_components(LLVMValueRef value)
918 {
919 LLVMTypeRef type = LLVMTypeOf(value);
920 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
921 ? LLVMGetVectorSize(type)
922 : 1;
923 return num_components;
924 }
925
926 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
927 LLVMValueRef value,
928 int index)
929 {
930 int count = get_llvm_num_components(value);
931
932 assert(index < count);
933 if (count == 1)
934 return value;
935
936 return LLVMBuildExtractElement(ctx->builder, value,
937 LLVMConstInt(ctx->i32, index, false), "");
938 }
939
940 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
941 LLVMValueRef value, unsigned count)
942 {
943 unsigned num_components = get_llvm_num_components(value);
944 if (count == num_components)
945 return value;
946
947 LLVMValueRef masks[] = {
948 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
949 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
950
951 if (count == 1)
952 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
953 "");
954
955 LLVMValueRef swizzle = LLVMConstVector(masks, count);
956 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
957 }
958
959 static void
960 build_store_values_extended(struct nir_to_llvm_context *ctx,
961 LLVMValueRef *values,
962 unsigned value_count,
963 unsigned value_stride,
964 LLVMValueRef vec)
965 {
966 LLVMBuilderRef builder = ctx->builder;
967 unsigned i;
968
969 if (value_count == 1) {
970 LLVMBuildStore(builder, vec, values[0]);
971 return;
972 }
973
974 for (i = 0; i < value_count; i++) {
975 LLVMValueRef ptr = values[i * value_stride];
976 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
977 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
978 LLVMBuildStore(builder, value, ptr);
979 }
980 }
981
982 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
983 nir_ssa_def *def)
984 {
985 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
986 if (def->num_components > 1) {
987 type = LLVMVectorType(type, def->num_components);
988 }
989 return type;
990 }
991
992 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
993 {
994 assert(src.is_ssa);
995 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
996 return (LLVMValueRef)entry->data;
997 }
998
999
1000 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
1001 struct nir_block *b)
1002 {
1003 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
1004 return (LLVMBasicBlockRef)entry->data;
1005 }
1006
1007 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
1008 nir_alu_src src,
1009 unsigned num_components)
1010 {
1011 LLVMValueRef value = get_src(ctx, src.src);
1012 bool need_swizzle = false;
1013
1014 assert(value);
1015 LLVMTypeRef type = LLVMTypeOf(value);
1016 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1017 ? LLVMGetVectorSize(type)
1018 : 1;
1019
1020 for (unsigned i = 0; i < num_components; ++i) {
1021 assert(src.swizzle[i] < src_components);
1022 if (src.swizzle[i] != i)
1023 need_swizzle = true;
1024 }
1025
1026 if (need_swizzle || num_components != src_components) {
1027 LLVMValueRef masks[] = {
1028 LLVMConstInt(ctx->i32, src.swizzle[0], false),
1029 LLVMConstInt(ctx->i32, src.swizzle[1], false),
1030 LLVMConstInt(ctx->i32, src.swizzle[2], false),
1031 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
1032
1033 if (src_components > 1 && num_components == 1) {
1034 value = LLVMBuildExtractElement(ctx->builder, value,
1035 masks[0], "");
1036 } else if (src_components == 1 && num_components > 1) {
1037 LLVMValueRef values[] = {value, value, value, value};
1038 value = ac_build_gather_values(&ctx->ac, values, num_components);
1039 } else {
1040 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1041 value = LLVMBuildShuffleVector(ctx->builder, value, value,
1042 swizzle, "");
1043 }
1044 }
1045 assert(!src.negate);
1046 assert(!src.abs);
1047 return value;
1048 }
1049
1050 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
1051 LLVMIntPredicate pred, LLVMValueRef src0,
1052 LLVMValueRef src1)
1053 {
1054 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1055 return LLVMBuildSelect(ctx->builder, result,
1056 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1057 LLVMConstInt(ctx->i32, 0, false), "");
1058 }
1059
1060 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
1061 LLVMRealPredicate pred, LLVMValueRef src0,
1062 LLVMValueRef src1)
1063 {
1064 LLVMValueRef result;
1065 src0 = to_float(ctx, src0);
1066 src1 = to_float(ctx, src1);
1067 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1068 return LLVMBuildSelect(ctx->builder, result,
1069 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1070 LLVMConstInt(ctx->i32, 0, false), "");
1071 }
1072
1073 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
1074 const char *intrin,
1075 LLVMTypeRef result_type,
1076 LLVMValueRef src0)
1077 {
1078 char name[64];
1079 LLVMValueRef params[] = {
1080 to_float(ctx, src0),
1081 };
1082
1083 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1084 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1085 }
1086
1087 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
1088 const char *intrin,
1089 LLVMTypeRef result_type,
1090 LLVMValueRef src0, LLVMValueRef src1)
1091 {
1092 char name[64];
1093 LLVMValueRef params[] = {
1094 to_float(ctx, src0),
1095 to_float(ctx, src1),
1096 };
1097
1098 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1099 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1100 }
1101
1102 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
1103 const char *intrin,
1104 LLVMTypeRef result_type,
1105 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1106 {
1107 char name[64];
1108 LLVMValueRef params[] = {
1109 to_float(ctx, src0),
1110 to_float(ctx, src1),
1111 to_float(ctx, src2),
1112 };
1113
1114 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1115 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1116 }
1117
1118 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
1119 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1120 {
1121 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1122 ctx->i32zero, "");
1123 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1124 }
1125
1126 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
1127 LLVMValueRef src0)
1128 {
1129 LLVMValueRef params[2] = {
1130 src0,
1131
1132 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1133 * add special code to check for x=0. The reason is that
1134 * the LLVM behavior for x=0 is different from what we
1135 * need here.
1136 *
1137 * The hardware already implements the correct behavior.
1138 */
1139 LLVMConstInt(ctx->i32, 1, false),
1140 };
1141 return ac_build_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1142 }
1143
1144 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
1145 LLVMValueRef src0)
1146 {
1147 return ac_build_imsb(&ctx->ac, src0, ctx->i32);
1148 }
1149
1150 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
1151 LLVMValueRef src0)
1152 {
1153 return ac_build_umsb(&ctx->ac, src0, ctx->i32);
1154 }
1155
1156 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
1157 LLVMIntPredicate pred,
1158 LLVMValueRef src0, LLVMValueRef src1)
1159 {
1160 return LLVMBuildSelect(ctx->builder,
1161 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1162 src0,
1163 src1, "");
1164
1165 }
1166 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
1167 LLVMValueRef src0)
1168 {
1169 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1170 LLVMBuildNeg(ctx->builder, src0, ""));
1171 }
1172
1173 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1174 LLVMValueRef src0)
1175 {
1176 LLVMValueRef cmp, val;
1177
1178 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1179 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1180 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1181 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1182 return val;
1183 }
1184
1185 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1186 LLVMValueRef src0)
1187 {
1188 LLVMValueRef cmp, val;
1189
1190 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1191 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1192 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1193 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1194 return val;
1195 }
1196
1197 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1198 LLVMValueRef src0)
1199 {
1200 const char *intr = "llvm.floor.f32";
1201 LLVMValueRef fsrc0 = to_float(ctx, src0);
1202 LLVMValueRef params[] = {
1203 fsrc0,
1204 };
1205 LLVMValueRef floor = ac_build_intrinsic(&ctx->ac, intr,
1206 ctx->f32, params, 1,
1207 AC_FUNC_ATTR_READNONE);
1208 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1209 }
1210
1211 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1212 const char *intrin,
1213 LLVMValueRef src0, LLVMValueRef src1)
1214 {
1215 LLVMTypeRef ret_type;
1216 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1217 LLVMValueRef res;
1218 LLVMValueRef params[] = { src0, src1 };
1219 ret_type = LLVMStructTypeInContext(ctx->context, types,
1220 2, true);
1221
1222 res = ac_build_intrinsic(&ctx->ac, intrin, ret_type,
1223 params, 2, AC_FUNC_ATTR_READNONE);
1224
1225 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1226 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1227 return res;
1228 }
1229
1230 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1231 LLVMValueRef src0)
1232 {
1233 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1234 }
1235
1236 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1237 LLVMValueRef src0, LLVMValueRef src1)
1238 {
1239 LLVMValueRef dst64, result;
1240 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1241 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1242
1243 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1244 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1245 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1246 return result;
1247 }
1248
1249 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1250 LLVMValueRef src0, LLVMValueRef src1)
1251 {
1252 LLVMValueRef dst64, result;
1253 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1254 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1255
1256 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1257 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1258 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1259 return result;
1260 }
1261
1262 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1263 bool is_signed,
1264 LLVMValueRef srcs[3])
1265 {
1266 LLVMValueRef result;
1267 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1268
1269 result = ac_build_bfe(&ctx->ac, srcs[0], srcs[1], srcs[2], is_signed);
1270 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1271 return result;
1272 }
1273
1274 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1275 LLVMValueRef src0, LLVMValueRef src1,
1276 LLVMValueRef src2, LLVMValueRef src3)
1277 {
1278 LLVMValueRef bfi_args[3], result;
1279
1280 bfi_args[0] = LLVMBuildShl(ctx->builder,
1281 LLVMBuildSub(ctx->builder,
1282 LLVMBuildShl(ctx->builder,
1283 ctx->i32one,
1284 src3, ""),
1285 ctx->i32one, ""),
1286 src2, "");
1287 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1288 bfi_args[2] = src0;
1289
1290 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1291
1292 /* Calculate:
1293 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1294 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1295 */
1296 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1297 LLVMBuildAnd(ctx->builder, bfi_args[0],
1298 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1299
1300 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1301 return result;
1302 }
1303
1304 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1305 LLVMValueRef src0)
1306 {
1307 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1308 int i;
1309 LLVMValueRef comp[2];
1310
1311 src0 = to_float(ctx, src0);
1312 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1313 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1314 for (i = 0; i < 2; i++) {
1315 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1316 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1317 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1318 }
1319
1320 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1321 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1322
1323 return comp[0];
1324 }
1325
1326 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1327 LLVMValueRef src0)
1328 {
1329 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1330 LLVMValueRef temps[2], result, val;
1331 int i;
1332
1333 for (i = 0; i < 2; i++) {
1334 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1335 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1336 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1337 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1338 }
1339
1340 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1341 ctx->i32zero, "");
1342 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1343 ctx->i32one, "");
1344 return result;
1345 }
1346
1347 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1348 nir_op op,
1349 LLVMValueRef src0)
1350 {
1351 unsigned mask;
1352 int idx;
1353 LLVMValueRef result;
1354 ctx->has_ddxy = true;
1355
1356 if (!ctx->lds && !ctx->has_ds_bpermute)
1357 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1358 LLVMArrayType(ctx->i32, 64),
1359 "ddxy_lds", LOCAL_ADDR_SPACE);
1360
1361 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1362 mask = AC_TID_MASK_LEFT;
1363 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1364 mask = AC_TID_MASK_TOP;
1365 else
1366 mask = AC_TID_MASK_TOP_LEFT;
1367
1368 /* for DDX we want to next X pixel, DDY next Y pixel. */
1369 if (op == nir_op_fddx_fine ||
1370 op == nir_op_fddx_coarse ||
1371 op == nir_op_fddx)
1372 idx = 1;
1373 else
1374 idx = 2;
1375
1376 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1377 mask, idx, ctx->lds,
1378 src0);
1379 return result;
1380 }
1381
1382 /*
1383 * this takes an I,J coordinate pair,
1384 * and works out the X and Y derivatives.
1385 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1386 */
1387 static LLVMValueRef emit_ddxy_interp(
1388 struct nir_to_llvm_context *ctx,
1389 LLVMValueRef interp_ij)
1390 {
1391 LLVMValueRef result[4], a;
1392 unsigned i;
1393
1394 for (i = 0; i < 2; i++) {
1395 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1396 LLVMConstInt(ctx->i32, i, false), "");
1397 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1398 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1399 }
1400 return ac_build_gather_values(&ctx->ac, result, 4);
1401 }
1402
1403 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1404 {
1405 LLVMValueRef src[4], result = NULL;
1406 unsigned num_components = instr->dest.dest.ssa.num_components;
1407 unsigned src_components;
1408 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1409
1410 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1411 switch (instr->op) {
1412 case nir_op_vec2:
1413 case nir_op_vec3:
1414 case nir_op_vec4:
1415 src_components = 1;
1416 break;
1417 case nir_op_pack_half_2x16:
1418 src_components = 2;
1419 break;
1420 case nir_op_unpack_half_2x16:
1421 src_components = 1;
1422 break;
1423 default:
1424 src_components = num_components;
1425 break;
1426 }
1427 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1428 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1429
1430 switch (instr->op) {
1431 case nir_op_fmov:
1432 case nir_op_imov:
1433 result = src[0];
1434 break;
1435 case nir_op_fneg:
1436 src[0] = to_float(ctx, src[0]);
1437 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1438 break;
1439 case nir_op_ineg:
1440 result = LLVMBuildNeg(ctx->builder, src[0], "");
1441 break;
1442 case nir_op_inot:
1443 result = LLVMBuildNot(ctx->builder, src[0], "");
1444 break;
1445 case nir_op_iadd:
1446 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1447 break;
1448 case nir_op_fadd:
1449 src[0] = to_float(ctx, src[0]);
1450 src[1] = to_float(ctx, src[1]);
1451 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1452 break;
1453 case nir_op_fsub:
1454 src[0] = to_float(ctx, src[0]);
1455 src[1] = to_float(ctx, src[1]);
1456 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1457 break;
1458 case nir_op_isub:
1459 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1460 break;
1461 case nir_op_imul:
1462 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1463 break;
1464 case nir_op_imod:
1465 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1466 break;
1467 case nir_op_umod:
1468 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1469 break;
1470 case nir_op_fmod:
1471 src[0] = to_float(ctx, src[0]);
1472 src[1] = to_float(ctx, src[1]);
1473 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1474 result = emit_intrin_1f_param(ctx, "llvm.floor",
1475 to_float_type(ctx, def_type), result);
1476 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1477 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1478 break;
1479 case nir_op_frem:
1480 src[0] = to_float(ctx, src[0]);
1481 src[1] = to_float(ctx, src[1]);
1482 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1483 break;
1484 case nir_op_irem:
1485 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1486 break;
1487 case nir_op_idiv:
1488 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1489 break;
1490 case nir_op_udiv:
1491 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1492 break;
1493 case nir_op_fmul:
1494 src[0] = to_float(ctx, src[0]);
1495 src[1] = to_float(ctx, src[1]);
1496 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1497 break;
1498 case nir_op_fdiv:
1499 src[0] = to_float(ctx, src[0]);
1500 src[1] = to_float(ctx, src[1]);
1501 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1502 break;
1503 case nir_op_frcp:
1504 src[0] = to_float(ctx, src[0]);
1505 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1506 break;
1507 case nir_op_iand:
1508 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1509 break;
1510 case nir_op_ior:
1511 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1512 break;
1513 case nir_op_ixor:
1514 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1515 break;
1516 case nir_op_ishl:
1517 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1518 break;
1519 case nir_op_ishr:
1520 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1521 break;
1522 case nir_op_ushr:
1523 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1524 break;
1525 case nir_op_ilt:
1526 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1527 break;
1528 case nir_op_ine:
1529 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1530 break;
1531 case nir_op_ieq:
1532 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1533 break;
1534 case nir_op_ige:
1535 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1536 break;
1537 case nir_op_ult:
1538 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1539 break;
1540 case nir_op_uge:
1541 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1542 break;
1543 case nir_op_feq:
1544 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1545 break;
1546 case nir_op_fne:
1547 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1548 break;
1549 case nir_op_flt:
1550 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1551 break;
1552 case nir_op_fge:
1553 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1554 break;
1555 case nir_op_fabs:
1556 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1557 to_float_type(ctx, def_type), src[0]);
1558 break;
1559 case nir_op_iabs:
1560 result = emit_iabs(ctx, src[0]);
1561 break;
1562 case nir_op_imax:
1563 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1564 break;
1565 case nir_op_imin:
1566 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1567 break;
1568 case nir_op_umax:
1569 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1570 break;
1571 case nir_op_umin:
1572 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1573 break;
1574 case nir_op_isign:
1575 result = emit_isign(ctx, src[0]);
1576 break;
1577 case nir_op_fsign:
1578 src[0] = to_float(ctx, src[0]);
1579 result = emit_fsign(ctx, src[0]);
1580 break;
1581 case nir_op_ffloor:
1582 result = emit_intrin_1f_param(ctx, "llvm.floor",
1583 to_float_type(ctx, def_type), src[0]);
1584 break;
1585 case nir_op_ftrunc:
1586 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1587 to_float_type(ctx, def_type), src[0]);
1588 break;
1589 case nir_op_fceil:
1590 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1591 to_float_type(ctx, def_type), src[0]);
1592 break;
1593 case nir_op_fround_even:
1594 result = emit_intrin_1f_param(ctx, "llvm.rint",
1595 to_float_type(ctx, def_type),src[0]);
1596 break;
1597 case nir_op_ffract:
1598 result = emit_ffract(ctx, src[0]);
1599 break;
1600 case nir_op_fsin:
1601 result = emit_intrin_1f_param(ctx, "llvm.sin",
1602 to_float_type(ctx, def_type), src[0]);
1603 break;
1604 case nir_op_fcos:
1605 result = emit_intrin_1f_param(ctx, "llvm.cos",
1606 to_float_type(ctx, def_type), src[0]);
1607 break;
1608 case nir_op_fsqrt:
1609 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1610 to_float_type(ctx, def_type), src[0]);
1611 break;
1612 case nir_op_fexp2:
1613 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1614 to_float_type(ctx, def_type), src[0]);
1615 break;
1616 case nir_op_flog2:
1617 result = emit_intrin_1f_param(ctx, "llvm.log2",
1618 to_float_type(ctx, def_type), src[0]);
1619 break;
1620 case nir_op_frsq:
1621 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1622 to_float_type(ctx, def_type), src[0]);
1623 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1624 break;
1625 case nir_op_fpow:
1626 result = emit_intrin_2f_param(ctx, "llvm.pow",
1627 to_float_type(ctx, def_type), src[0], src[1]);
1628 break;
1629 case nir_op_fmax:
1630 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1631 to_float_type(ctx, def_type), src[0], src[1]);
1632 break;
1633 case nir_op_fmin:
1634 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1635 to_float_type(ctx, def_type), src[0], src[1]);
1636 break;
1637 case nir_op_ffma:
1638 result = emit_intrin_3f_param(ctx, "llvm.fma",
1639 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1640 break;
1641 case nir_op_ibitfield_extract:
1642 result = emit_bitfield_extract(ctx, true, src);
1643 break;
1644 case nir_op_ubitfield_extract:
1645 result = emit_bitfield_extract(ctx, false, src);
1646 break;
1647 case nir_op_bitfield_insert:
1648 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1649 break;
1650 case nir_op_bitfield_reverse:
1651 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1652 break;
1653 case nir_op_bit_count:
1654 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1655 break;
1656 case nir_op_vec2:
1657 case nir_op_vec3:
1658 case nir_op_vec4:
1659 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1660 src[i] = to_integer(ctx, src[i]);
1661 result = ac_build_gather_values(&ctx->ac, src, num_components);
1662 break;
1663 case nir_op_f2i32:
1664 case nir_op_f2i64:
1665 src[0] = to_float(ctx, src[0]);
1666 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1667 break;
1668 case nir_op_f2u32:
1669 case nir_op_f2u64:
1670 src[0] = to_float(ctx, src[0]);
1671 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1672 break;
1673 case nir_op_i2f32:
1674 case nir_op_i2f64:
1675 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1676 break;
1677 case nir_op_u2f32:
1678 case nir_op_u2f64:
1679 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1680 break;
1681 case nir_op_f2f64:
1682 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1683 break;
1684 case nir_op_f2f32:
1685 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1686 break;
1687 case nir_op_u2u32:
1688 case nir_op_u2u64:
1689 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1690 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1691 else
1692 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1693 break;
1694 case nir_op_i2i32:
1695 case nir_op_i2i64:
1696 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1697 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1698 else
1699 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1700 break;
1701 case nir_op_bcsel:
1702 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1703 break;
1704 case nir_op_find_lsb:
1705 result = emit_find_lsb(ctx, src[0]);
1706 break;
1707 case nir_op_ufind_msb:
1708 result = emit_ufind_msb(ctx, src[0]);
1709 break;
1710 case nir_op_ifind_msb:
1711 result = emit_ifind_msb(ctx, src[0]);
1712 break;
1713 case nir_op_uadd_carry:
1714 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1715 break;
1716 case nir_op_usub_borrow:
1717 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1718 break;
1719 case nir_op_b2f:
1720 result = emit_b2f(ctx, src[0]);
1721 break;
1722 case nir_op_fquantize2f16:
1723 src[0] = to_float(ctx, src[0]);
1724 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1725 /* need to convert back up to f32 */
1726 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1727 break;
1728 case nir_op_umul_high:
1729 result = emit_umul_high(ctx, src[0], src[1]);
1730 break;
1731 case nir_op_imul_high:
1732 result = emit_imul_high(ctx, src[0], src[1]);
1733 break;
1734 case nir_op_pack_half_2x16:
1735 result = emit_pack_half_2x16(ctx, src[0]);
1736 break;
1737 case nir_op_unpack_half_2x16:
1738 result = emit_unpack_half_2x16(ctx, src[0]);
1739 break;
1740 case nir_op_fddx:
1741 case nir_op_fddy:
1742 case nir_op_fddx_fine:
1743 case nir_op_fddy_fine:
1744 case nir_op_fddx_coarse:
1745 case nir_op_fddy_coarse:
1746 result = emit_ddxy(ctx, instr->op, src[0]);
1747 break;
1748 default:
1749 fprintf(stderr, "Unknown NIR alu instr: ");
1750 nir_print_instr(&instr->instr, stderr);
1751 fprintf(stderr, "\n");
1752 abort();
1753 }
1754
1755 if (result) {
1756 assert(instr->dest.dest.is_ssa);
1757 result = to_integer(ctx, result);
1758 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1759 result);
1760 }
1761 }
1762
1763 static void visit_load_const(struct nir_to_llvm_context *ctx,
1764 nir_load_const_instr *instr)
1765 {
1766 LLVMValueRef values[4], value = NULL;
1767 LLVMTypeRef element_type =
1768 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1769
1770 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1771 switch (instr->def.bit_size) {
1772 case 32:
1773 values[i] = LLVMConstInt(element_type,
1774 instr->value.u32[i], false);
1775 break;
1776 case 64:
1777 values[i] = LLVMConstInt(element_type,
1778 instr->value.u64[i], false);
1779 break;
1780 default:
1781 fprintf(stderr,
1782 "unsupported nir load_const bit_size: %d\n",
1783 instr->def.bit_size);
1784 abort();
1785 }
1786 }
1787 if (instr->def.num_components > 1) {
1788 value = LLVMConstVector(values, instr->def.num_components);
1789 } else
1790 value = values[0];
1791
1792 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1793 }
1794
1795 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1796 LLVMTypeRef type)
1797 {
1798 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1799 return LLVMBuildBitCast(ctx->builder, ptr,
1800 LLVMPointerType(type, addr_space), "");
1801 }
1802
1803 static LLVMValueRef
1804 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1805 {
1806 LLVMValueRef size =
1807 LLVMBuildExtractElement(ctx->builder, descriptor,
1808 LLVMConstInt(ctx->i32, 2, false), "");
1809
1810 /* VI only */
1811 if (ctx->options->chip_class >= VI && in_elements) {
1812 /* On VI, the descriptor contains the size in bytes,
1813 * but TXQ must return the size in elements.
1814 * The stride is always non-zero for resources using TXQ.
1815 */
1816 LLVMValueRef stride =
1817 LLVMBuildExtractElement(ctx->builder, descriptor,
1818 LLVMConstInt(ctx->i32, 1, false), "");
1819 stride = LLVMBuildLShr(ctx->builder, stride,
1820 LLVMConstInt(ctx->i32, 16, false), "");
1821 stride = LLVMBuildAnd(ctx->builder, stride,
1822 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1823
1824 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1825 }
1826 return size;
1827 }
1828
1829 /**
1830 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1831 * intrinsic names).
1832 */
1833 static void build_int_type_name(
1834 LLVMTypeRef type,
1835 char *buf, unsigned bufsize)
1836 {
1837 assert(bufsize >= 6);
1838
1839 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1840 snprintf(buf, bufsize, "v%ui32",
1841 LLVMGetVectorSize(type));
1842 else
1843 strcpy(buf, "i32");
1844 }
1845
1846 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1847 struct ac_image_args *args,
1848 nir_tex_instr *instr)
1849 {
1850 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1851 LLVMValueRef coord = args->addr;
1852 LLVMValueRef half_texel[2];
1853 LLVMValueRef compare_cube_wa;
1854 LLVMValueRef result;
1855 int c;
1856 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1857
1858 //TODO Rect
1859 {
1860 struct ac_image_args txq_args = { 0 };
1861
1862 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1863 txq_args.opcode = ac_image_get_resinfo;
1864 txq_args.dmask = 0xf;
1865 txq_args.addr = ctx->i32zero;
1866 txq_args.resource = args->resource;
1867 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
1868
1869 for (c = 0; c < 2; c++) {
1870 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1871 LLVMConstInt(ctx->i32, c, false), "");
1872 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1873 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1874 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1875 LLVMConstReal(ctx->f32, -0.5), "");
1876 }
1877 }
1878
1879 LLVMValueRef orig_coords = args->addr;
1880
1881 for (c = 0; c < 2; c++) {
1882 LLVMValueRef tmp;
1883 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1884 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1885 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1886 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1887 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1888 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1889 }
1890
1891
1892 /*
1893 * Apparantly cube has issue with integer types that the workaround doesn't solve,
1894 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
1895 * workaround by sampling using a scaled type and converting.
1896 * This is taken from amdgpu-pro shaders.
1897 */
1898 /* NOTE this produces some ugly code compared to amdgpu-pro,
1899 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
1900 * and then reads them back. -pro generates two selects,
1901 * one s_cmp for the descriptor rewriting
1902 * one v_cmp for the coordinate and result changes.
1903 */
1904 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1905 LLVMValueRef tmp, tmp2;
1906
1907 /* workaround 8/8/8/8 uint/sint cube gather bug */
1908 /* first detect it then change to a scaled read and f2i */
1909 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
1910 tmp2 = tmp;
1911
1912 /* extract the DATA_FORMAT */
1913 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
1914 LLVMConstInt(ctx->i32, 6, false), false);
1915
1916 /* is the DATA_FORMAT == 8_8_8_8 */
1917 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
1918
1919 if (stype == GLSL_TYPE_UINT)
1920 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
1921 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
1922 LLVMConstInt(ctx->i32, 0x10000000, false), "");
1923 else
1924 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
1925 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
1926 LLVMConstInt(ctx->i32, 0x14000000, false), "");
1927
1928 /* replace the NUM FORMAT in the descriptor */
1929 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
1930 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
1931
1932 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
1933
1934 /* don't modify the coordinates for this case */
1935 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
1936 }
1937 args->addr = coord;
1938 result = ac_build_image_opcode(&ctx->ac, args);
1939
1940 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1941 LLVMValueRef tmp, tmp2;
1942
1943 /* if the cube workaround is in place, f2i the result. */
1944 for (c = 0; c < 4; c++) {
1945 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
1946 if (stype == GLSL_TYPE_UINT)
1947 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
1948 else
1949 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
1950 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1951 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
1952 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
1953 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1954 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
1955 }
1956 }
1957 return result;
1958 }
1959
1960 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1961 nir_tex_instr *instr,
1962 struct ac_image_args *args)
1963 {
1964 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
1965 return ac_build_buffer_load_format(&ctx->ac,
1966 args->resource,
1967 args->addr,
1968 LLVMConstInt(ctx->i32, 0, false),
1969 true);
1970 }
1971
1972 args->opcode = ac_image_sample;
1973 args->compare = instr->is_shadow;
1974
1975 switch (instr->op) {
1976 case nir_texop_txf:
1977 case nir_texop_txf_ms:
1978 case nir_texop_samples_identical:
1979 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
1980 args->compare = false;
1981 args->offset = false;
1982 break;
1983 case nir_texop_txb:
1984 args->bias = true;
1985 break;
1986 case nir_texop_txl:
1987 args->lod = true;
1988 break;
1989 case nir_texop_txs:
1990 case nir_texop_query_levels:
1991 args->opcode = ac_image_get_resinfo;
1992 break;
1993 case nir_texop_tex:
1994 if (ctx->stage != MESA_SHADER_FRAGMENT)
1995 args->level_zero = true;
1996 break;
1997 case nir_texop_txd:
1998 args->deriv = true;
1999 break;
2000 case nir_texop_tg4:
2001 args->opcode = ac_image_gather4;
2002 args->level_zero = true;
2003 break;
2004 case nir_texop_lod:
2005 args->opcode = ac_image_get_lod;
2006 args->compare = false;
2007 args->offset = false;
2008 break;
2009 default:
2010 break;
2011 }
2012
2013 if (instr->op == nir_texop_tg4) {
2014 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2015 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2016 return radv_lower_gather4_integer(ctx, args, instr);
2017 }
2018 }
2019 return ac_build_image_opcode(&ctx->ac, args);
2020 }
2021
2022 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2023 nir_intrinsic_instr *instr)
2024 {
2025 LLVMValueRef index = get_src(ctx, instr->src[0]);
2026 unsigned desc_set = nir_intrinsic_desc_set(instr);
2027 unsigned binding = nir_intrinsic_binding(instr);
2028 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2029 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2030 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2031 unsigned base_offset = layout->binding[binding].offset;
2032 LLVMValueRef offset, stride;
2033
2034 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2035 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2036 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2037 layout->binding[binding].dynamic_offset_offset;
2038 desc_ptr = ctx->push_constants;
2039 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2040 stride = LLVMConstInt(ctx->i32, 16, false);
2041 } else
2042 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2043
2044 offset = LLVMConstInt(ctx->i32, base_offset, false);
2045 index = LLVMBuildMul(ctx->builder, index, stride, "");
2046 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2047
2048 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2049 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2050 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2051
2052 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2053 }
2054
2055 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2056 nir_intrinsic_instr *instr)
2057 {
2058 LLVMValueRef ptr, addr;
2059
2060 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2061 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
2062
2063 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2064 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
2065
2066 return LLVMBuildLoad(ctx->builder, ptr, "");
2067 }
2068
2069 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2070 nir_intrinsic_instr *instr)
2071 {
2072 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2073
2074 return get_buffer_size(ctx, desc, false);
2075 }
2076 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2077 nir_intrinsic_instr *instr)
2078 {
2079 const char *store_name;
2080 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2081 LLVMTypeRef data_type = ctx->f32;
2082 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
2083 int components_32bit = elem_size_mult * instr->num_components;
2084 unsigned writemask = nir_intrinsic_write_mask(instr);
2085 LLVMValueRef base_data, base_offset;
2086 LLVMValueRef params[6];
2087
2088 if (ctx->stage == MESA_SHADER_FRAGMENT)
2089 ctx->shader_info->fs.writes_memory = true;
2090
2091 params[1] = get_src(ctx, instr->src[1]);
2092 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2093 params[4] = ctx->i1false; /* glc */
2094 params[5] = ctx->i1false; /* slc */
2095
2096 if (components_32bit > 1)
2097 data_type = LLVMVectorType(ctx->f32, components_32bit);
2098
2099 base_data = to_float(ctx, src_data);
2100 base_data = trim_vector(ctx, base_data, instr->num_components);
2101 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2102 data_type, "");
2103 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2104 while (writemask) {
2105 int start, count;
2106 LLVMValueRef data;
2107 LLVMValueRef offset;
2108 LLVMValueRef tmp;
2109 u_bit_scan_consecutive_range(&writemask, &start, &count);
2110
2111 /* Due to an LLVM limitation, split 3-element writes
2112 * into a 2-element and a 1-element write. */
2113 if (count == 3) {
2114 writemask |= 1 << (start + 2);
2115 count = 2;
2116 }
2117
2118 start *= elem_size_mult;
2119 count *= elem_size_mult;
2120
2121 if (count > 4) {
2122 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2123 count = 4;
2124 }
2125
2126 if (count == 4) {
2127 store_name = "llvm.amdgcn.buffer.store.v4f32";
2128 data = base_data;
2129 } else if (count == 2) {
2130 tmp = LLVMBuildExtractElement(ctx->builder,
2131 base_data, LLVMConstInt(ctx->i32, start, false), "");
2132 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2133 ctx->i32zero, "");
2134
2135 tmp = LLVMBuildExtractElement(ctx->builder,
2136 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2137 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2138 ctx->i32one, "");
2139 store_name = "llvm.amdgcn.buffer.store.v2f32";
2140
2141 } else {
2142 assert(count == 1);
2143 if (get_llvm_num_components(base_data) > 1)
2144 data = LLVMBuildExtractElement(ctx->builder, base_data,
2145 LLVMConstInt(ctx->i32, start, false), "");
2146 else
2147 data = base_data;
2148 store_name = "llvm.amdgcn.buffer.store.f32";
2149 }
2150
2151 offset = base_offset;
2152 if (start != 0) {
2153 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2154 }
2155 params[0] = data;
2156 params[3] = offset;
2157 ac_build_intrinsic(&ctx->ac, store_name,
2158 ctx->voidt, params, 6, 0);
2159 }
2160 }
2161
2162 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2163 nir_intrinsic_instr *instr)
2164 {
2165 const char *name;
2166 LLVMValueRef params[6];
2167 int arg_count = 0;
2168 if (ctx->stage == MESA_SHADER_FRAGMENT)
2169 ctx->shader_info->fs.writes_memory = true;
2170
2171 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2172 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2173 }
2174 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2175 params[arg_count++] = get_src(ctx, instr->src[0]);
2176 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2177 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2178 params[arg_count++] = ctx->i1false; /* slc */
2179
2180 switch (instr->intrinsic) {
2181 case nir_intrinsic_ssbo_atomic_add:
2182 name = "llvm.amdgcn.buffer.atomic.add";
2183 break;
2184 case nir_intrinsic_ssbo_atomic_imin:
2185 name = "llvm.amdgcn.buffer.atomic.smin";
2186 break;
2187 case nir_intrinsic_ssbo_atomic_umin:
2188 name = "llvm.amdgcn.buffer.atomic.umin";
2189 break;
2190 case nir_intrinsic_ssbo_atomic_imax:
2191 name = "llvm.amdgcn.buffer.atomic.smax";
2192 break;
2193 case nir_intrinsic_ssbo_atomic_umax:
2194 name = "llvm.amdgcn.buffer.atomic.umax";
2195 break;
2196 case nir_intrinsic_ssbo_atomic_and:
2197 name = "llvm.amdgcn.buffer.atomic.and";
2198 break;
2199 case nir_intrinsic_ssbo_atomic_or:
2200 name = "llvm.amdgcn.buffer.atomic.or";
2201 break;
2202 case nir_intrinsic_ssbo_atomic_xor:
2203 name = "llvm.amdgcn.buffer.atomic.xor";
2204 break;
2205 case nir_intrinsic_ssbo_atomic_exchange:
2206 name = "llvm.amdgcn.buffer.atomic.swap";
2207 break;
2208 case nir_intrinsic_ssbo_atomic_comp_swap:
2209 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2210 break;
2211 default:
2212 abort();
2213 }
2214
2215 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2216 }
2217
2218 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2219 nir_intrinsic_instr *instr)
2220 {
2221 LLVMValueRef results[2];
2222 int load_components;
2223 int num_components = instr->num_components;
2224 if (instr->dest.ssa.bit_size == 64)
2225 num_components *= 2;
2226
2227 for (int i = 0; i < num_components; i += load_components) {
2228 load_components = MIN2(num_components - i, 4);
2229 const char *load_name;
2230 LLVMTypeRef data_type = ctx->f32;
2231 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2232 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2233
2234 if (load_components == 3)
2235 data_type = LLVMVectorType(ctx->f32, 4);
2236 else if (load_components > 1)
2237 data_type = LLVMVectorType(ctx->f32, load_components);
2238
2239 if (load_components >= 3)
2240 load_name = "llvm.amdgcn.buffer.load.v4f32";
2241 else if (load_components == 2)
2242 load_name = "llvm.amdgcn.buffer.load.v2f32";
2243 else if (load_components == 1)
2244 load_name = "llvm.amdgcn.buffer.load.f32";
2245 else
2246 unreachable("unhandled number of components");
2247
2248 LLVMValueRef params[] = {
2249 get_src(ctx, instr->src[0]),
2250 LLVMConstInt(ctx->i32, 0, false),
2251 offset,
2252 ctx->i1false,
2253 ctx->i1false,
2254 };
2255
2256 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2257
2258 }
2259
2260 LLVMValueRef ret = results[0];
2261 if (num_components > 4 || num_components == 3) {
2262 LLVMValueRef masks[] = {
2263 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2264 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2265 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2266 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2267 };
2268
2269 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2270 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2271 results[num_components > 4 ? 1 : 0], swizzle, "");
2272 }
2273
2274 return LLVMBuildBitCast(ctx->builder, ret,
2275 get_def_type(ctx, &instr->dest.ssa), "");
2276 }
2277
2278 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2279 nir_intrinsic_instr *instr)
2280 {
2281 LLVMValueRef results[8], ret;
2282 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2283 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2284 int num_components = instr->num_components;
2285
2286 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2287
2288 if (instr->dest.ssa.bit_size == 64)
2289 num_components *= 2;
2290
2291 for (unsigned i = 0; i < num_components; ++i) {
2292 LLVMValueRef params[] = {
2293 rsrc,
2294 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2295 offset, "")
2296 };
2297 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2298 params, 2,
2299 AC_FUNC_ATTR_READNONE |
2300 AC_FUNC_ATTR_LEGACY);
2301 }
2302
2303
2304 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2305 return LLVMBuildBitCast(ctx->builder, ret,
2306 get_def_type(ctx, &instr->dest.ssa), "");
2307 }
2308
2309 static void
2310 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref_var *deref,
2311 bool vs_in, unsigned *vertex_index_out,
2312 LLVMValueRef *vertex_index_ref,
2313 unsigned *const_out, LLVMValueRef *indir_out)
2314 {
2315 unsigned const_offset = 0;
2316 nir_deref *tail = &deref->deref;
2317 LLVMValueRef offset = NULL;
2318
2319 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2320 tail = tail->child;
2321 nir_deref_array *deref_array = nir_deref_as_array(tail);
2322 if (vertex_index_out)
2323 *vertex_index_out = deref_array->base_offset;
2324
2325 if (vertex_index_ref) {
2326 LLVMValueRef vtx = LLVMConstInt(ctx->i32, deref_array->base_offset, false);
2327 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2328 vtx = LLVMBuildAdd(ctx->builder, vtx, get_src(ctx, deref_array->indirect), "");
2329 }
2330 *vertex_index_ref = vtx;
2331 }
2332 }
2333
2334 if (deref->var->data.compact) {
2335 assert(tail->child->deref_type == nir_deref_type_array);
2336 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2337 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2338 /* We always lower indirect dereferences for "compact" array vars. */
2339 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2340
2341 const_offset = deref_array->base_offset;
2342 goto out;
2343 }
2344
2345 while (tail->child != NULL) {
2346 const struct glsl_type *parent_type = tail->type;
2347 tail = tail->child;
2348
2349 if (tail->deref_type == nir_deref_type_array) {
2350 nir_deref_array *deref_array = nir_deref_as_array(tail);
2351 LLVMValueRef index, stride, local_offset;
2352 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2353
2354 const_offset += size * deref_array->base_offset;
2355 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2356 continue;
2357
2358 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2359 index = get_src(ctx, deref_array->indirect);
2360 stride = LLVMConstInt(ctx->i32, size, 0);
2361 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2362
2363 if (offset)
2364 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2365 else
2366 offset = local_offset;
2367 } else if (tail->deref_type == nir_deref_type_struct) {
2368 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2369
2370 for (unsigned i = 0; i < deref_struct->index; i++) {
2371 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2372 const_offset += glsl_count_attribute_slots(ft, vs_in);
2373 }
2374 } else
2375 unreachable("unsupported deref type");
2376
2377 }
2378 out:
2379 if (const_offset && offset)
2380 offset = LLVMBuildAdd(ctx->builder, offset,
2381 LLVMConstInt(ctx->i32, const_offset, 0),
2382 "");
2383
2384 *const_out = const_offset;
2385 *indir_out = offset;
2386 }
2387
2388 static LLVMValueRef
2389 lds_load(struct nir_to_llvm_context *ctx,
2390 LLVMValueRef dw_addr)
2391 {
2392 LLVMValueRef value;
2393 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2394 return value;
2395 }
2396
2397 static void
2398 lds_store(struct nir_to_llvm_context *ctx,
2399 LLVMValueRef dw_addr, LLVMValueRef value)
2400 {
2401 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2402 ac_build_indexed_store(&ctx->ac, ctx->lds,
2403 dw_addr, value);
2404 }
2405
2406 /* The offchip buffer layout for TCS->TES is
2407 *
2408 * - attribute 0 of patch 0 vertex 0
2409 * - attribute 0 of patch 0 vertex 1
2410 * - attribute 0 of patch 0 vertex 2
2411 * ...
2412 * - attribute 0 of patch 1 vertex 0
2413 * - attribute 0 of patch 1 vertex 1
2414 * ...
2415 * - attribute 1 of patch 0 vertex 0
2416 * - attribute 1 of patch 0 vertex 1
2417 * ...
2418 * - per patch attribute 0 of patch 0
2419 * - per patch attribute 0 of patch 1
2420 * ...
2421 *
2422 * Note that every attribute has 4 components.
2423 */
2424 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2425 LLVMValueRef vertex_index,
2426 LLVMValueRef param_index)
2427 {
2428 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2429 LLVMValueRef param_stride, constant16;
2430 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2431
2432 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2433 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2434 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2435 num_patches, "");
2436
2437 constant16 = LLVMConstInt(ctx->i32, 16, false);
2438 if (vertex_index) {
2439 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2440 vertices_per_patch, "");
2441
2442 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2443 vertex_index, "");
2444
2445 param_stride = total_vertices;
2446 } else {
2447 base_addr = rel_patch_id;
2448 param_stride = num_patches;
2449 }
2450
2451 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2452 LLVMBuildMul(ctx->builder, param_index,
2453 param_stride, ""), "");
2454
2455 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2456
2457 if (!vertex_index) {
2458 LLVMValueRef patch_data_offset =
2459 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2460
2461 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2462 patch_data_offset, "");
2463 }
2464 return base_addr;
2465 }
2466
2467 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2468 unsigned param,
2469 unsigned const_index,
2470 bool is_compact,
2471 LLVMValueRef vertex_index,
2472 LLVMValueRef indir_index)
2473 {
2474 LLVMValueRef param_index;
2475
2476 if (indir_index)
2477 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2478 indir_index, "");
2479 else {
2480 if (const_index && !is_compact)
2481 param += const_index;
2482 param_index = LLVMConstInt(ctx->i32, param, false);
2483 }
2484 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2485 }
2486
2487 static void
2488 mark_tess_output(struct nir_to_llvm_context *ctx,
2489 bool is_patch, uint32_t param)
2490
2491 {
2492 if (is_patch) {
2493 ctx->tess_patch_outputs_written |= (1ull << param);
2494 } else
2495 ctx->tess_outputs_written |= (1ull << param);
2496 }
2497
2498 static LLVMValueRef
2499 get_dw_address(struct nir_to_llvm_context *ctx,
2500 LLVMValueRef dw_addr,
2501 unsigned param,
2502 unsigned const_index,
2503 bool compact_const_index,
2504 LLVMValueRef vertex_index,
2505 LLVMValueRef stride,
2506 LLVMValueRef indir_index)
2507
2508 {
2509
2510 if (vertex_index) {
2511 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2512 LLVMBuildMul(ctx->builder,
2513 vertex_index,
2514 stride, ""), "");
2515 }
2516
2517 if (indir_index)
2518 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2519 LLVMBuildMul(ctx->builder, indir_index,
2520 LLVMConstInt(ctx->i32, 4, false), ""), "");
2521 else if (const_index && !compact_const_index)
2522 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2523 LLVMConstInt(ctx->i32, const_index, false), "");
2524
2525 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2526 LLVMConstInt(ctx->i32, param * 4, false), "");
2527
2528 if (const_index && compact_const_index)
2529 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2530 LLVMConstInt(ctx->i32, const_index, false), "");
2531 return dw_addr;
2532 }
2533
2534 static LLVMValueRef
2535 load_tcs_input(struct nir_to_llvm_context *ctx,
2536 nir_intrinsic_instr *instr)
2537 {
2538 LLVMValueRef dw_addr, stride;
2539 unsigned const_index;
2540 LLVMValueRef vertex_index;
2541 LLVMValueRef indir_index;
2542 unsigned param;
2543 LLVMValueRef value[4], result;
2544 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2545 const bool is_compact = instr->variables[0]->var->data.compact;
2546 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2547 radv_get_deref_offset(ctx, instr->variables[0],
2548 false, NULL, per_vertex ? &vertex_index : NULL,
2549 &const_index, &indir_index);
2550
2551 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2552 dw_addr = get_tcs_in_current_patch_offset(ctx);
2553 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2554 indir_index);
2555
2556 for (unsigned i = 0; i < instr->num_components; i++) {
2557 value[i] = lds_load(ctx, dw_addr);
2558 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2559 ctx->i32one, "");
2560 }
2561 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2562 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2563 return result;
2564 }
2565
2566 static LLVMValueRef
2567 load_tcs_output(struct nir_to_llvm_context *ctx,
2568 nir_intrinsic_instr *instr)
2569 {
2570 LLVMValueRef dw_addr, stride;
2571 LLVMValueRef value[4], result;
2572 LLVMValueRef vertex_index = NULL;
2573 LLVMValueRef indir_index = NULL;
2574 unsigned const_index = 0;
2575 unsigned param;
2576 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2577 const bool is_compact = instr->variables[0]->var->data.compact;
2578 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2579 radv_get_deref_offset(ctx, instr->variables[0],
2580 false, NULL, per_vertex ? &vertex_index : NULL,
2581 &const_index, &indir_index);
2582
2583 if (!instr->variables[0]->var->data.patch) {
2584 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2585 dw_addr = get_tcs_out_current_patch_offset(ctx);
2586 } else {
2587 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2588 }
2589
2590 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2591 indir_index);
2592
2593 for (unsigned i = 0; i < instr->num_components; i++) {
2594 value[i] = lds_load(ctx, dw_addr);
2595 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2596 ctx->i32one, "");
2597 }
2598 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2599 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2600 return result;
2601 }
2602
2603 static void
2604 store_tcs_output(struct nir_to_llvm_context *ctx,
2605 nir_intrinsic_instr *instr,
2606 LLVMValueRef src,
2607 unsigned writemask)
2608 {
2609 LLVMValueRef stride, dw_addr;
2610 LLVMValueRef buf_addr = NULL;
2611 LLVMValueRef vertex_index = NULL;
2612 LLVMValueRef indir_index = NULL;
2613 unsigned const_index = 0;
2614 unsigned param;
2615 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2616 const bool is_compact = instr->variables[0]->var->data.compact;
2617
2618 radv_get_deref_offset(ctx, instr->variables[0],
2619 false, NULL, per_vertex ? &vertex_index : NULL,
2620 &const_index, &indir_index);
2621
2622 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2623 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2624 is_compact && const_index > 3) {
2625 const_index -= 3;
2626 param++;
2627 }
2628
2629 if (!instr->variables[0]->var->data.patch) {
2630 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2631 dw_addr = get_tcs_out_current_patch_offset(ctx);
2632 } else {
2633 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2634 }
2635
2636 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2637
2638 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2639 indir_index);
2640 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2641 vertex_index, indir_index);
2642
2643 unsigned base = is_compact ? const_index : 0;
2644 for (unsigned chan = 0; chan < 8; chan++) {
2645 bool is_tess_factor = false;
2646 if (!(writemask & (1 << chan)))
2647 continue;
2648 LLVMValueRef value = llvm_extract_elem(ctx, src, chan);
2649
2650 lds_store(ctx, dw_addr, value);
2651
2652 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2653 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2654 is_tess_factor = true;
2655
2656 if (!is_tess_factor && writemask != 0xF)
2657 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2658 buf_addr, ctx->oc_lds,
2659 4 * (base + chan), 1, 0, true, false);
2660
2661 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2662 ctx->i32one, "");
2663 }
2664
2665 if (writemask == 0xF) {
2666 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2667 buf_addr, ctx->oc_lds,
2668 (base * 4), 1, 0, true, false);
2669 }
2670 }
2671
2672 static LLVMValueRef
2673 load_tes_input(struct nir_to_llvm_context *ctx,
2674 nir_intrinsic_instr *instr)
2675 {
2676 LLVMValueRef buf_addr;
2677 LLVMValueRef result;
2678 LLVMValueRef vertex_index = NULL;
2679 LLVMValueRef indir_index = NULL;
2680 unsigned const_index = 0;
2681 unsigned param;
2682 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2683 const bool is_compact = instr->variables[0]->var->data.compact;
2684
2685 radv_get_deref_offset(ctx, instr->variables[0],
2686 false, NULL, per_vertex ? &vertex_index : NULL,
2687 &const_index, &indir_index);
2688 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2689 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2690 is_compact && const_index > 3) {
2691 const_index -= 3;
2692 param++;
2693 }
2694 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2695 is_compact, vertex_index, indir_index);
2696
2697 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2698 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true);
2699 result = trim_vector(ctx, result, instr->num_components);
2700 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2701 return result;
2702 }
2703
2704 static LLVMValueRef
2705 load_gs_input(struct nir_to_llvm_context *ctx,
2706 nir_intrinsic_instr *instr)
2707 {
2708 LLVMValueRef indir_index, vtx_offset;
2709 unsigned const_index;
2710 LLVMValueRef args[9];
2711 unsigned param, vtx_offset_param;
2712 LLVMValueRef value[4], result;
2713 unsigned vertex_index;
2714 radv_get_deref_offset(ctx, instr->variables[0],
2715 false, &vertex_index, NULL,
2716 &const_index, &indir_index);
2717 vtx_offset_param = vertex_index;
2718 assert(vtx_offset_param < 6);
2719 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2720 LLVMConstInt(ctx->i32, 4, false), "");
2721
2722 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2723 for (unsigned i = 0; i < instr->num_components; i++) {
2724
2725 args[0] = ctx->esgs_ring;
2726 args[1] = vtx_offset;
2727 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2728 args[3] = ctx->i32zero;
2729 args[4] = ctx->i32one; /* OFFEN */
2730 args[5] = ctx->i32zero; /* IDXEN */
2731 args[6] = ctx->i32one; /* GLC */
2732 args[7] = ctx->i32zero; /* SLC */
2733 args[8] = ctx->i32zero; /* TFE */
2734
2735 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2736 ctx->i32, args, 9,
2737 AC_FUNC_ATTR_READONLY |
2738 AC_FUNC_ATTR_LEGACY);
2739 }
2740 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2741
2742 return result;
2743 }
2744
2745 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2746 nir_intrinsic_instr *instr)
2747 {
2748 LLVMValueRef values[8];
2749 int idx = instr->variables[0]->var->data.driver_location;
2750 int ve = instr->dest.ssa.num_components;
2751 LLVMValueRef indir_index;
2752 LLVMValueRef ret;
2753 unsigned const_index;
2754 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2755 instr->variables[0]->var->data.mode == nir_var_shader_in;
2756 radv_get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2757 &const_index, &indir_index);
2758
2759 if (instr->dest.ssa.bit_size == 64)
2760 ve *= 2;
2761
2762 switch (instr->variables[0]->var->data.mode) {
2763 case nir_var_shader_in:
2764 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2765 return load_tcs_input(ctx, instr);
2766 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2767 return load_tes_input(ctx, instr);
2768 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2769 return load_gs_input(ctx, instr);
2770 }
2771 for (unsigned chan = 0; chan < ve; chan++) {
2772 if (indir_index) {
2773 unsigned count = glsl_count_attribute_slots(
2774 instr->variables[0]->var->type,
2775 ctx->stage == MESA_SHADER_VERTEX);
2776 count -= chan / 4;
2777 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2778 &ctx->ac, ctx->inputs + idx + chan, count,
2779 4, false);
2780
2781 values[chan] = LLVMBuildExtractElement(ctx->builder,
2782 tmp_vec,
2783 indir_index, "");
2784 } else
2785 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2786 }
2787 break;
2788 case nir_var_local:
2789 for (unsigned chan = 0; chan < ve; chan++) {
2790 if (indir_index) {
2791 unsigned count = glsl_count_attribute_slots(
2792 instr->variables[0]->var->type, false);
2793 count -= chan / 4;
2794 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2795 &ctx->ac, ctx->locals + idx + chan, count,
2796 4, true);
2797
2798 values[chan] = LLVMBuildExtractElement(ctx->builder,
2799 tmp_vec,
2800 indir_index, "");
2801 } else {
2802 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2803 }
2804 }
2805 break;
2806 case nir_var_shader_out:
2807 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2808 return load_tcs_output(ctx, instr);
2809 for (unsigned chan = 0; chan < ve; chan++) {
2810 if (indir_index) {
2811 unsigned count = glsl_count_attribute_slots(
2812 instr->variables[0]->var->type, false);
2813 count -= chan / 4;
2814 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2815 &ctx->ac, ctx->outputs + idx + chan, count,
2816 4, true);
2817
2818 values[chan] = LLVMBuildExtractElement(ctx->builder,
2819 tmp_vec,
2820 indir_index, "");
2821 } else {
2822 values[chan] = LLVMBuildLoad(ctx->builder,
2823 ctx->outputs[idx + chan + const_index * 4],
2824 "");
2825 }
2826 }
2827 break;
2828 case nir_var_shared: {
2829 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2830 LLVMValueRef derived_ptr;
2831
2832 if (indir_index)
2833 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2834
2835 for (unsigned chan = 0; chan < ve; chan++) {
2836 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2837 if (indir_index)
2838 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2839 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2840
2841 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2842 }
2843 break;
2844 }
2845 default:
2846 unreachable("unhandle variable mode");
2847 }
2848 ret = ac_build_gather_values(&ctx->ac, values, ve);
2849 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2850 }
2851
2852 static void
2853 visit_store_var(struct nir_to_llvm_context *ctx,
2854 nir_intrinsic_instr *instr)
2855 {
2856 LLVMValueRef temp_ptr, value;
2857 int idx = instr->variables[0]->var->data.driver_location;
2858 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2859 int writemask = instr->const_index[0];
2860 LLVMValueRef indir_index;
2861 unsigned const_index;
2862 radv_get_deref_offset(ctx, instr->variables[0], false,
2863 NULL, NULL, &const_index, &indir_index);
2864
2865 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2866 int old_writemask = writemask;
2867
2868 src = LLVMBuildBitCast(ctx->builder, src,
2869 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2870 "");
2871
2872 writemask = 0;
2873 for (unsigned chan = 0; chan < 4; chan++) {
2874 if (old_writemask & (1 << chan))
2875 writemask |= 3u << (2 * chan);
2876 }
2877 }
2878
2879 switch (instr->variables[0]->var->data.mode) {
2880 case nir_var_shader_out:
2881
2882 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
2883 store_tcs_output(ctx, instr, src, writemask);
2884 return;
2885 }
2886
2887 for (unsigned chan = 0; chan < 8; chan++) {
2888 int stride = 4;
2889 if (!(writemask & (1 << chan)))
2890 continue;
2891
2892 value = llvm_extract_elem(ctx, src, chan);
2893
2894 if (instr->variables[0]->var->data.compact)
2895 stride = 1;
2896 if (indir_index) {
2897 unsigned count = glsl_count_attribute_slots(
2898 instr->variables[0]->var->type, false);
2899 count -= chan / 4;
2900 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2901 &ctx->ac, ctx->outputs + idx + chan, count,
2902 stride, true);
2903
2904 if (get_llvm_num_components(tmp_vec) > 1) {
2905 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2906 value, indir_index, "");
2907 } else
2908 tmp_vec = value;
2909 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2910 count, stride, tmp_vec);
2911
2912 } else {
2913 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2914
2915 LLVMBuildStore(ctx->builder, value, temp_ptr);
2916 }
2917 }
2918 break;
2919 case nir_var_local:
2920 for (unsigned chan = 0; chan < 8; chan++) {
2921 if (!(writemask & (1 << chan)))
2922 continue;
2923
2924 value = llvm_extract_elem(ctx, src, chan);
2925 if (indir_index) {
2926 unsigned count = glsl_count_attribute_slots(
2927 instr->variables[0]->var->type, false);
2928 count -= chan / 4;
2929 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2930 &ctx->ac, ctx->locals + idx + chan, count,
2931 4, true);
2932
2933 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2934 value, indir_index, "");
2935 build_store_values_extended(ctx, ctx->locals + idx + chan,
2936 count, 4, tmp_vec);
2937 } else {
2938 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2939
2940 LLVMBuildStore(ctx->builder, value, temp_ptr);
2941 }
2942 }
2943 break;
2944 case nir_var_shared: {
2945 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2946
2947 if (indir_index)
2948 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2949
2950 for (unsigned chan = 0; chan < 8; chan++) {
2951 if (!(writemask & (1 << chan)))
2952 continue;
2953 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2954 LLVMValueRef derived_ptr;
2955
2956 if (indir_index)
2957 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2958
2959 value = llvm_extract_elem(ctx, src, chan);
2960 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2961 LLVMBuildStore(ctx->builder,
2962 to_integer(ctx, value), derived_ptr);
2963 }
2964 break;
2965 }
2966 default:
2967 break;
2968 }
2969 }
2970
2971 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2972 {
2973 switch (dim) {
2974 case GLSL_SAMPLER_DIM_BUF:
2975 return 1;
2976 case GLSL_SAMPLER_DIM_1D:
2977 return array ? 2 : 1;
2978 case GLSL_SAMPLER_DIM_2D:
2979 return array ? 3 : 2;
2980 case GLSL_SAMPLER_DIM_MS:
2981 return array ? 4 : 3;
2982 case GLSL_SAMPLER_DIM_3D:
2983 case GLSL_SAMPLER_DIM_CUBE:
2984 return 3;
2985 case GLSL_SAMPLER_DIM_RECT:
2986 case GLSL_SAMPLER_DIM_SUBPASS:
2987 return 2;
2988 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2989 return 3;
2990 default:
2991 break;
2992 }
2993 return 0;
2994 }
2995
2996
2997
2998 /* Adjust the sample index according to FMASK.
2999 *
3000 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3001 * which is the identity mapping. Each nibble says which physical sample
3002 * should be fetched to get that sample.
3003 *
3004 * For example, 0x11111100 means there are only 2 samples stored and
3005 * the second sample covers 3/4 of the pixel. When reading samples 0
3006 * and 1, return physical sample 0 (determined by the first two 0s
3007 * in FMASK), otherwise return physical sample 1.
3008 *
3009 * The sample index should be adjusted as follows:
3010 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3011 */
3012 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
3013 LLVMValueRef coord_x, LLVMValueRef coord_y,
3014 LLVMValueRef coord_z,
3015 LLVMValueRef sample_index,
3016 LLVMValueRef fmask_desc_ptr)
3017 {
3018 LLVMValueRef fmask_load_address[4];
3019 LLVMValueRef res;
3020
3021 fmask_load_address[0] = coord_x;
3022 fmask_load_address[1] = coord_y;
3023 if (coord_z) {
3024 fmask_load_address[2] = coord_z;
3025 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3026 }
3027
3028 struct ac_image_args args = {0};
3029
3030 args.opcode = ac_image_load;
3031 args.da = coord_z ? true : false;
3032 args.resource = fmask_desc_ptr;
3033 args.dmask = 0xf;
3034 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
3035
3036 res = ac_build_image_opcode(&ctx->ac, &args);
3037
3038 res = to_integer(ctx, res);
3039 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3040 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3041
3042 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3043 res,
3044 ctx->i32zero, "");
3045
3046 LLVMValueRef sample_index4 =
3047 LLVMBuildMul(ctx->builder, sample_index, four, "");
3048 LLVMValueRef shifted_fmask =
3049 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3050 LLVMValueRef final_sample =
3051 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3052
3053 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3054 * resource descriptor is 0 (invalid),
3055 */
3056 LLVMValueRef fmask_desc =
3057 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3058 ctx->v8i32, "");
3059
3060 LLVMValueRef fmask_word1 =
3061 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3062 ctx->i32one, "");
3063
3064 LLVMValueRef word1_is_nonzero =
3065 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3066 fmask_word1, ctx->i32zero, "");
3067
3068 /* Replace the MSAA sample index. */
3069 sample_index =
3070 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3071 final_sample, sample_index, "");
3072 return sample_index;
3073 }
3074
3075 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
3076 nir_intrinsic_instr *instr)
3077 {
3078 const struct glsl_type *type = instr->variables[0]->var->type;
3079 if(instr->variables[0]->deref.child)
3080 type = instr->variables[0]->deref.child->type;
3081
3082 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3083 LLVMValueRef coords[4];
3084 LLVMValueRef masks[] = {
3085 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
3086 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
3087 };
3088 LLVMValueRef res;
3089 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
3090
3091 int count;
3092 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3093 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3094 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3095 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3096 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3097
3098 count = image_type_to_components_count(dim,
3099 glsl_sampler_type_is_array(type));
3100
3101 if (is_ms) {
3102 LLVMValueRef fmask_load_address[3];
3103 int chan;
3104
3105 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3106 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
3107 if (glsl_sampler_type_is_array(type))
3108 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
3109 else
3110 fmask_load_address[2] = NULL;
3111 if (add_frag_pos) {
3112 for (chan = 0; chan < 2; ++chan)
3113 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3114 }
3115 sample_index = adjust_sample_index_using_fmask(ctx,
3116 fmask_load_address[0],
3117 fmask_load_address[1],
3118 fmask_load_address[2],
3119 sample_index,
3120 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
3121 }
3122 if (count == 1) {
3123 if (instr->src[0].ssa->num_components)
3124 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3125 else
3126 res = src0;
3127 } else {
3128 int chan;
3129 if (is_ms)
3130 count--;
3131 for (chan = 0; chan < count; ++chan) {
3132 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
3133 }
3134
3135 if (add_frag_pos) {
3136 for (chan = 0; chan < count; ++chan)
3137 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3138 }
3139 if (is_ms) {
3140 coords[count] = sample_index;
3141 count++;
3142 }
3143
3144 if (count == 3) {
3145 coords[3] = LLVMGetUndef(ctx->i32);
3146 count = 4;
3147 }
3148 res = ac_build_gather_values(&ctx->ac, coords, count);
3149 }
3150 return res;
3151 }
3152
3153 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
3154 nir_intrinsic_instr *instr)
3155 {
3156 LLVMValueRef params[7];
3157 LLVMValueRef res;
3158 char intrinsic_name[64];
3159 const nir_variable *var = instr->variables[0]->var;
3160 const struct glsl_type *type = var->type;
3161 if(instr->variables[0]->deref.child)
3162 type = instr->variables[0]->deref.child->type;
3163
3164 type = glsl_without_array(type);
3165 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3166 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3167 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3168 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3169 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3170 params[3] = ctx->i1false; /* glc */
3171 params[4] = ctx->i1false; /* slc */
3172 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
3173 params, 5, 0);
3174
3175 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
3176 res = to_integer(ctx, res);
3177 } else {
3178 bool is_da = glsl_sampler_type_is_array(type) ||
3179 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3180 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3181 LLVMValueRef glc = ctx->i1false;
3182 LLVMValueRef slc = ctx->i1false;
3183
3184 params[0] = get_image_coords(ctx, instr);
3185 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3186 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3187 if (HAVE_LLVM <= 0x0309) {
3188 params[3] = ctx->i1false; /* r128 */
3189 params[4] = da;
3190 params[5] = glc;
3191 params[6] = slc;
3192 } else {
3193 LLVMValueRef lwe = ctx->i1false;
3194 params[3] = glc;
3195 params[4] = slc;
3196 params[5] = lwe;
3197 params[6] = da;
3198 }
3199
3200 ac_get_image_intr_name("llvm.amdgcn.image.load",
3201 ctx->v4f32, /* vdata */
3202 LLVMTypeOf(params[0]), /* coords */
3203 LLVMTypeOf(params[1]), /* rsrc */
3204 intrinsic_name, sizeof(intrinsic_name));
3205
3206 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
3207 params, 7, AC_FUNC_ATTR_READONLY);
3208 }
3209 return to_integer(ctx, res);
3210 }
3211
3212 static void visit_image_store(struct nir_to_llvm_context *ctx,
3213 nir_intrinsic_instr *instr)
3214 {
3215 LLVMValueRef params[8];
3216 char intrinsic_name[64];
3217 const nir_variable *var = instr->variables[0]->var;
3218 const struct glsl_type *type = glsl_without_array(var->type);
3219
3220 if (ctx->stage == MESA_SHADER_FRAGMENT)
3221 ctx->shader_info->fs.writes_memory = true;
3222
3223 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3224 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
3225 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3226 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3227 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3228 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3229 params[4] = ctx->i1false; /* glc */
3230 params[5] = ctx->i1false; /* slc */
3231 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
3232 params, 6, 0);
3233 } else {
3234 bool is_da = glsl_sampler_type_is_array(type) ||
3235 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3236 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3237 LLVMValueRef glc = ctx->i1false;
3238 LLVMValueRef slc = ctx->i1false;
3239
3240 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
3241 params[1] = get_image_coords(ctx, instr); /* coords */
3242 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3243 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3244 if (HAVE_LLVM <= 0x0309) {
3245 params[4] = ctx->i1false; /* r128 */
3246 params[5] = da;
3247 params[6] = glc;
3248 params[7] = slc;
3249 } else {
3250 LLVMValueRef lwe = ctx->i1false;
3251 params[4] = glc;
3252 params[5] = slc;
3253 params[6] = lwe;
3254 params[7] = da;
3255 }
3256
3257 ac_get_image_intr_name("llvm.amdgcn.image.store",
3258 LLVMTypeOf(params[0]), /* vdata */
3259 LLVMTypeOf(params[1]), /* coords */
3260 LLVMTypeOf(params[2]), /* rsrc */
3261 intrinsic_name, sizeof(intrinsic_name));
3262
3263 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
3264 params, 8, 0);
3265 }
3266
3267 }
3268
3269 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
3270 nir_intrinsic_instr *instr)
3271 {
3272 LLVMValueRef params[6];
3273 int param_count = 0;
3274 const nir_variable *var = instr->variables[0]->var;
3275
3276 const char *base_name = "llvm.amdgcn.image.atomic";
3277 const char *atomic_name;
3278 LLVMValueRef coords;
3279 char intrinsic_name[32], coords_type[8];
3280 const struct glsl_type *type = glsl_without_array(var->type);
3281
3282 if (ctx->stage == MESA_SHADER_FRAGMENT)
3283 ctx->shader_info->fs.writes_memory = true;
3284
3285 params[param_count++] = get_src(ctx, instr->src[2]);
3286 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3287 params[param_count++] = get_src(ctx, instr->src[3]);
3288
3289 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3290 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3291 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3292 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3293 params[param_count++] = ctx->i32zero; /* voffset */
3294 params[param_count++] = ctx->i1false; /* glc */
3295 params[param_count++] = ctx->i1false; /* slc */
3296 } else {
3297 bool da = glsl_sampler_type_is_array(type) ||
3298 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3299
3300 coords = params[param_count++] = get_image_coords(ctx, instr);
3301 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3302 params[param_count++] = ctx->i1false; /* r128 */
3303 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
3304 params[param_count++] = ctx->i1false; /* slc */
3305 }
3306
3307 switch (instr->intrinsic) {
3308 case nir_intrinsic_image_atomic_add:
3309 atomic_name = "add";
3310 break;
3311 case nir_intrinsic_image_atomic_min:
3312 atomic_name = "smin";
3313 break;
3314 case nir_intrinsic_image_atomic_max:
3315 atomic_name = "smax";
3316 break;
3317 case nir_intrinsic_image_atomic_and:
3318 atomic_name = "and";
3319 break;
3320 case nir_intrinsic_image_atomic_or:
3321 atomic_name = "or";
3322 break;
3323 case nir_intrinsic_image_atomic_xor:
3324 atomic_name = "xor";
3325 break;
3326 case nir_intrinsic_image_atomic_exchange:
3327 atomic_name = "swap";
3328 break;
3329 case nir_intrinsic_image_atomic_comp_swap:
3330 atomic_name = "cmpswap";
3331 break;
3332 default:
3333 abort();
3334 }
3335 build_int_type_name(LLVMTypeOf(coords),
3336 coords_type, sizeof(coords_type));
3337
3338 snprintf(intrinsic_name, sizeof(intrinsic_name),
3339 "%s.%s.%s", base_name, atomic_name, coords_type);
3340 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
3341 }
3342
3343 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
3344 nir_intrinsic_instr *instr)
3345 {
3346 LLVMValueRef res;
3347 const nir_variable *var = instr->variables[0]->var;
3348 const struct glsl_type *type = instr->variables[0]->var->type;
3349 bool da = glsl_sampler_type_is_array(var->type) ||
3350 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3351 if(instr->variables[0]->deref.child)
3352 type = instr->variables[0]->deref.child->type;
3353
3354 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3355 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
3356
3357 struct ac_image_args args = { 0 };
3358
3359 args.da = da;
3360 args.dmask = 0xf;
3361 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3362 args.opcode = ac_image_get_resinfo;
3363 args.addr = ctx->i32zero;
3364
3365 res = ac_build_image_opcode(&ctx->ac, &args);
3366
3367 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3368 glsl_sampler_type_is_array(type)) {
3369 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3370 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3371 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
3372 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3373 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
3374 }
3375 return res;
3376 }
3377
3378 #define NOOP_WAITCNT 0xf7f
3379 #define LGKM_CNT 0x07f
3380 #define VM_CNT 0xf70
3381
3382 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3383 unsigned simm16)
3384 {
3385 LLVMValueRef args[1] = {
3386 LLVMConstInt(ctx->i32, simm16, false),
3387 };
3388 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3389 ctx->voidt, args, 1, 0);
3390 }
3391
3392 static void emit_barrier(struct nir_to_llvm_context *ctx)
3393 {
3394 /* SI only (thanks to a hw bug workaround):
3395 * The real barrier instruction isn’t needed, because an entire patch
3396 * always fits into a single wave.
3397 */
3398 if (ctx->options->chip_class == SI &&
3399 ctx->stage == MESA_SHADER_TESS_CTRL) {
3400 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3401 return;
3402 }
3403 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3404 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3405 }
3406
3407 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3408 nir_intrinsic_instr *instr)
3409 {
3410 LLVMValueRef cond;
3411 ctx->shader_info->fs.can_discard = true;
3412
3413 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3414 get_src(ctx, instr->src[0]),
3415 ctx->i32zero, "");
3416
3417 cond = LLVMBuildSelect(ctx->builder, cond,
3418 LLVMConstReal(ctx->f32, -1.0f),
3419 ctx->f32zero, "");
3420 ac_build_kill(&ctx->ac, cond);
3421 }
3422
3423 static LLVMValueRef
3424 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3425 {
3426 LLVMValueRef result;
3427 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3428 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3429 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3430
3431 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3432 }
3433
3434 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3435 nir_intrinsic_instr *instr)
3436 {
3437 LLVMValueRef ptr, result;
3438 int idx = instr->variables[0]->var->data.driver_location;
3439 LLVMValueRef src = get_src(ctx, instr->src[0]);
3440 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3441
3442 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3443 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3444 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3445 ptr, src, src1,
3446 LLVMAtomicOrderingSequentiallyConsistent,
3447 LLVMAtomicOrderingSequentiallyConsistent,
3448 false);
3449 } else {
3450 LLVMAtomicRMWBinOp op;
3451 switch (instr->intrinsic) {
3452 case nir_intrinsic_var_atomic_add:
3453 op = LLVMAtomicRMWBinOpAdd;
3454 break;
3455 case nir_intrinsic_var_atomic_umin:
3456 op = LLVMAtomicRMWBinOpUMin;
3457 break;
3458 case nir_intrinsic_var_atomic_umax:
3459 op = LLVMAtomicRMWBinOpUMax;
3460 break;
3461 case nir_intrinsic_var_atomic_imin:
3462 op = LLVMAtomicRMWBinOpMin;
3463 break;
3464 case nir_intrinsic_var_atomic_imax:
3465 op = LLVMAtomicRMWBinOpMax;
3466 break;
3467 case nir_intrinsic_var_atomic_and:
3468 op = LLVMAtomicRMWBinOpAnd;
3469 break;
3470 case nir_intrinsic_var_atomic_or:
3471 op = LLVMAtomicRMWBinOpOr;
3472 break;
3473 case nir_intrinsic_var_atomic_xor:
3474 op = LLVMAtomicRMWBinOpXor;
3475 break;
3476 case nir_intrinsic_var_atomic_exchange:
3477 op = LLVMAtomicRMWBinOpXchg;
3478 break;
3479 default:
3480 return NULL;
3481 }
3482
3483 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
3484 LLVMAtomicOrderingSequentiallyConsistent,
3485 false);
3486 }
3487 return result;
3488 }
3489
3490 #define INTERP_CENTER 0
3491 #define INTERP_CENTROID 1
3492 #define INTERP_SAMPLE 2
3493
3494 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3495 enum glsl_interp_mode interp, unsigned location)
3496 {
3497 switch (interp) {
3498 case INTERP_MODE_FLAT:
3499 default:
3500 return NULL;
3501 case INTERP_MODE_SMOOTH:
3502 case INTERP_MODE_NONE:
3503 if (location == INTERP_CENTER)
3504 return ctx->persp_center;
3505 else if (location == INTERP_CENTROID)
3506 return ctx->persp_centroid;
3507 else if (location == INTERP_SAMPLE)
3508 return ctx->persp_sample;
3509 break;
3510 case INTERP_MODE_NOPERSPECTIVE:
3511 if (location == INTERP_CENTER)
3512 return ctx->linear_center;
3513 else if (location == INTERP_CENTROID)
3514 return ctx->linear_centroid;
3515 else if (location == INTERP_SAMPLE)
3516 return ctx->linear_sample;
3517 break;
3518 }
3519 return NULL;
3520 }
3521
3522 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3523 LLVMValueRef sample_id)
3524 {
3525 LLVMValueRef result;
3526 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3527
3528 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3529 const_array(ctx->v2f32, 64), "");
3530
3531 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3532 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3533
3534 return result;
3535 }
3536
3537 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3538 {
3539 LLVMValueRef values[2];
3540
3541 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
3542 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
3543 return ac_build_gather_values(&ctx->ac, values, 2);
3544 }
3545
3546 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3547 nir_intrinsic_instr *instr)
3548 {
3549 LLVMValueRef result[2];
3550 LLVMValueRef interp_param, attr_number;
3551 unsigned location;
3552 unsigned chan;
3553 LLVMValueRef src_c0, src_c1;
3554 LLVMValueRef src0;
3555 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3556 switch (instr->intrinsic) {
3557 case nir_intrinsic_interp_var_at_centroid:
3558 location = INTERP_CENTROID;
3559 break;
3560 case nir_intrinsic_interp_var_at_sample:
3561 case nir_intrinsic_interp_var_at_offset:
3562 location = INTERP_CENTER;
3563 src0 = get_src(ctx, instr->src[0]);
3564 break;
3565 default:
3566 break;
3567 }
3568
3569 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3570 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3571 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3572 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3573 LLVMValueRef sample_position;
3574 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3575
3576 /* fetch sample ID */
3577 sample_position = load_sample_position(ctx, src0);
3578
3579 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3580 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3581 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3582 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3583 }
3584 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3585 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3586
3587 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3588 LLVMValueRef ij_out[2];
3589 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3590
3591 /*
3592 * take the I then J parameters, and the DDX/Y for it, and
3593 * calculate the IJ inputs for the interpolator.
3594 * temp1 = ddx * offset/sample.x + I;
3595 * interp_param.I = ddy * offset/sample.y + temp1;
3596 * temp1 = ddx * offset/sample.x + J;
3597 * interp_param.J = ddy * offset/sample.y + temp1;
3598 */
3599 for (unsigned i = 0; i < 2; i++) {
3600 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3601 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3602 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3603 ddxy_out, ix_ll, "");
3604 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3605 ddxy_out, iy_ll, "");
3606 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3607 interp_param, ix_ll, "");
3608 LLVMValueRef temp1, temp2;
3609
3610 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3611 ctx->f32, "");
3612
3613 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3614 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3615
3616 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3617 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3618
3619 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3620 temp2, ctx->i32, "");
3621 }
3622 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3623
3624 }
3625
3626 for (chan = 0; chan < 2; chan++) {
3627 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3628
3629 if (interp_param) {
3630 interp_param = LLVMBuildBitCast(ctx->builder,
3631 interp_param, LLVMVectorType(ctx->f32, 2), "");
3632 LLVMValueRef i = LLVMBuildExtractElement(
3633 ctx->builder, interp_param, ctx->i32zero, "");
3634 LLVMValueRef j = LLVMBuildExtractElement(
3635 ctx->builder, interp_param, ctx->i32one, "");
3636
3637 result[chan] = ac_build_fs_interp(&ctx->ac,
3638 llvm_chan, attr_number,
3639 ctx->prim_mask, i, j);
3640 } else {
3641 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3642 LLVMConstInt(ctx->i32, 2, false),
3643 llvm_chan, attr_number,
3644 ctx->prim_mask);
3645 }
3646 }
3647 return ac_build_gather_values(&ctx->ac, result, 2);
3648 }
3649
3650 static void
3651 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3652 nir_intrinsic_instr *instr)
3653 {
3654 LLVMValueRef gs_next_vertex;
3655 LLVMValueRef can_emit, kill;
3656 int idx;
3657
3658 assert(instr->const_index[0] == 0);
3659 /* Write vertex attribute values to GSVS ring */
3660 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3661 ctx->gs_next_vertex,
3662 "");
3663
3664 /* If this thread has already emitted the declared maximum number of
3665 * vertices, kill it: excessive vertex emissions are not supposed to
3666 * have any effect, and GS threads have no externally observable
3667 * effects other than emitting vertices.
3668 */
3669 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3670 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3671
3672 kill = LLVMBuildSelect(ctx->builder, can_emit,
3673 LLVMConstReal(ctx->f32, 1.0f),
3674 LLVMConstReal(ctx->f32, -1.0f), "");
3675 ac_build_kill(&ctx->ac, kill);
3676
3677 /* loop num outputs */
3678 idx = 0;
3679 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3680 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3681 int length = 4;
3682 int slot = idx;
3683 int slot_inc = 1;
3684
3685 if (!(ctx->output_mask & (1ull << i)))
3686 continue;
3687
3688 if (i == VARYING_SLOT_CLIP_DIST0) {
3689 /* pack clip and cull into a single set of slots */
3690 length = ctx->num_output_clips + ctx->num_output_culls;
3691 if (length > 4)
3692 slot_inc = 2;
3693 }
3694 for (unsigned j = 0; j < length; j++) {
3695 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3696 out_ptr[j], "");
3697 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3698 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3699 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3700
3701 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3702
3703 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3704 out_val, 1,
3705 voffset, ctx->gs2vs_offset, 0,
3706 1, 1, true, true);
3707 }
3708 idx += slot_inc;
3709 }
3710
3711 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3712 ctx->i32one, "");
3713 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3714
3715 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3716 }
3717
3718 static void
3719 visit_end_primitive(struct nir_to_llvm_context *ctx,
3720 nir_intrinsic_instr *instr)
3721 {
3722 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3723 }
3724
3725 static LLVMValueRef
3726 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3727 nir_intrinsic_instr *instr)
3728 {
3729 LLVMValueRef coord[4] = {
3730 ctx->tes_u,
3731 ctx->tes_v,
3732 ctx->f32zero,
3733 ctx->f32zero,
3734 };
3735
3736 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3737 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3738 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3739
3740 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3741 return LLVMBuildBitCast(ctx->builder, result,
3742 get_def_type(ctx, &instr->dest.ssa), "");
3743 }
3744
3745 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3746 nir_intrinsic_instr *instr)
3747 {
3748 LLVMValueRef result = NULL;
3749
3750 switch (instr->intrinsic) {
3751 case nir_intrinsic_load_work_group_id: {
3752 result = ctx->workgroup_ids;
3753 break;
3754 }
3755 case nir_intrinsic_load_base_vertex: {
3756 result = ctx->base_vertex;
3757 break;
3758 }
3759 case nir_intrinsic_load_vertex_id_zero_base: {
3760 result = ctx->vertex_id;
3761 break;
3762 }
3763 case nir_intrinsic_load_local_invocation_id: {
3764 result = ctx->local_invocation_ids;
3765 break;
3766 }
3767 case nir_intrinsic_load_base_instance:
3768 result = ctx->start_instance;
3769 break;
3770 case nir_intrinsic_load_draw_id:
3771 result = ctx->draw_index;
3772 break;
3773 case nir_intrinsic_load_invocation_id:
3774 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3775 result = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
3776 else
3777 result = ctx->gs_invocation_id;
3778 break;
3779 case nir_intrinsic_load_primitive_id:
3780 if (ctx->stage == MESA_SHADER_GEOMETRY)
3781 result = ctx->gs_prim_id;
3782 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
3783 result = ctx->tcs_patch_id;
3784 else if (ctx->stage == MESA_SHADER_TESS_EVAL)
3785 result = ctx->tes_patch_id;
3786 else
3787 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3788 break;
3789 case nir_intrinsic_load_sample_id:
3790 ctx->shader_info->fs.force_persample = true;
3791 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3792 break;
3793 case nir_intrinsic_load_sample_pos:
3794 ctx->shader_info->fs.force_persample = true;
3795 result = load_sample_pos(ctx);
3796 break;
3797 case nir_intrinsic_load_sample_mask_in:
3798 result = ctx->sample_coverage;
3799 break;
3800 case nir_intrinsic_load_front_face:
3801 result = ctx->front_face;
3802 break;
3803 case nir_intrinsic_load_instance_id:
3804 result = ctx->instance_id;
3805 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3806 ctx->shader_info->vs.vgpr_comp_cnt);
3807 break;
3808 case nir_intrinsic_load_num_work_groups:
3809 result = ctx->num_work_groups;
3810 break;
3811 case nir_intrinsic_load_local_invocation_index:
3812 result = visit_load_local_invocation_index(ctx);
3813 break;
3814 case nir_intrinsic_load_push_constant:
3815 result = visit_load_push_constant(ctx, instr);
3816 break;
3817 case nir_intrinsic_vulkan_resource_index:
3818 result = visit_vulkan_resource_index(ctx, instr);
3819 break;
3820 case nir_intrinsic_store_ssbo:
3821 visit_store_ssbo(ctx, instr);
3822 break;
3823 case nir_intrinsic_load_ssbo:
3824 result = visit_load_buffer(ctx, instr);
3825 break;
3826 case nir_intrinsic_ssbo_atomic_add:
3827 case nir_intrinsic_ssbo_atomic_imin:
3828 case nir_intrinsic_ssbo_atomic_umin:
3829 case nir_intrinsic_ssbo_atomic_imax:
3830 case nir_intrinsic_ssbo_atomic_umax:
3831 case nir_intrinsic_ssbo_atomic_and:
3832 case nir_intrinsic_ssbo_atomic_or:
3833 case nir_intrinsic_ssbo_atomic_xor:
3834 case nir_intrinsic_ssbo_atomic_exchange:
3835 case nir_intrinsic_ssbo_atomic_comp_swap:
3836 result = visit_atomic_ssbo(ctx, instr);
3837 break;
3838 case nir_intrinsic_load_ubo:
3839 result = visit_load_ubo_buffer(ctx, instr);
3840 break;
3841 case nir_intrinsic_get_buffer_size:
3842 result = visit_get_buffer_size(ctx, instr);
3843 break;
3844 case nir_intrinsic_load_var:
3845 result = visit_load_var(ctx, instr);
3846 break;
3847 case nir_intrinsic_store_var:
3848 visit_store_var(ctx, instr);
3849 break;
3850 case nir_intrinsic_image_load:
3851 result = visit_image_load(ctx, instr);
3852 break;
3853 case nir_intrinsic_image_store:
3854 visit_image_store(ctx, instr);
3855 break;
3856 case nir_intrinsic_image_atomic_add:
3857 case nir_intrinsic_image_atomic_min:
3858 case nir_intrinsic_image_atomic_max:
3859 case nir_intrinsic_image_atomic_and:
3860 case nir_intrinsic_image_atomic_or:
3861 case nir_intrinsic_image_atomic_xor:
3862 case nir_intrinsic_image_atomic_exchange:
3863 case nir_intrinsic_image_atomic_comp_swap:
3864 result = visit_image_atomic(ctx, instr);
3865 break;
3866 case nir_intrinsic_image_size:
3867 result = visit_image_size(ctx, instr);
3868 break;
3869 case nir_intrinsic_discard:
3870 ctx->shader_info->fs.can_discard = true;
3871 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3872 ctx->voidt,
3873 NULL, 0, AC_FUNC_ATTR_LEGACY);
3874 break;
3875 case nir_intrinsic_discard_if:
3876 emit_discard_if(ctx, instr);
3877 break;
3878 case nir_intrinsic_memory_barrier:
3879 emit_waitcnt(ctx, VM_CNT);
3880 break;
3881 case nir_intrinsic_barrier:
3882 emit_barrier(ctx);
3883 break;
3884 case nir_intrinsic_var_atomic_add:
3885 case nir_intrinsic_var_atomic_imin:
3886 case nir_intrinsic_var_atomic_umin:
3887 case nir_intrinsic_var_atomic_imax:
3888 case nir_intrinsic_var_atomic_umax:
3889 case nir_intrinsic_var_atomic_and:
3890 case nir_intrinsic_var_atomic_or:
3891 case nir_intrinsic_var_atomic_xor:
3892 case nir_intrinsic_var_atomic_exchange:
3893 case nir_intrinsic_var_atomic_comp_swap:
3894 result = visit_var_atomic(ctx, instr);
3895 break;
3896 case nir_intrinsic_interp_var_at_centroid:
3897 case nir_intrinsic_interp_var_at_sample:
3898 case nir_intrinsic_interp_var_at_offset:
3899 result = visit_interp(ctx, instr);
3900 break;
3901 case nir_intrinsic_emit_vertex:
3902 visit_emit_vertex(ctx, instr);
3903 break;
3904 case nir_intrinsic_end_primitive:
3905 visit_end_primitive(ctx, instr);
3906 break;
3907 case nir_intrinsic_load_tess_coord:
3908 result = visit_load_tess_coord(ctx, instr);
3909 break;
3910 case nir_intrinsic_load_patch_vertices_in:
3911 result = LLVMConstInt(ctx->i32, ctx->options->key.tcs.input_vertices, false);
3912 break;
3913 default:
3914 fprintf(stderr, "Unknown intrinsic: ");
3915 nir_print_instr(&instr->instr, stderr);
3916 fprintf(stderr, "\n");
3917 break;
3918 }
3919 if (result) {
3920 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3921 }
3922 }
3923
3924 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3925 nir_deref_var *deref,
3926 enum desc_type desc_type)
3927 {
3928 unsigned desc_set = deref->var->data.descriptor_set;
3929 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3930 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3931 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3932 unsigned offset = binding->offset;
3933 unsigned stride = binding->size;
3934 unsigned type_size;
3935 LLVMBuilderRef builder = ctx->builder;
3936 LLVMTypeRef type;
3937 LLVMValueRef index = NULL;
3938 unsigned constant_index = 0;
3939
3940 assert(deref->var->data.binding < layout->binding_count);
3941
3942 switch (desc_type) {
3943 case DESC_IMAGE:
3944 type = ctx->v8i32;
3945 type_size = 32;
3946 break;
3947 case DESC_FMASK:
3948 type = ctx->v8i32;
3949 offset += 32;
3950 type_size = 32;
3951 break;
3952 case DESC_SAMPLER:
3953 type = ctx->v4i32;
3954 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3955 offset += 64;
3956
3957 type_size = 16;
3958 break;
3959 case DESC_BUFFER:
3960 type = ctx->v4i32;
3961 type_size = 16;
3962 break;
3963 default:
3964 unreachable("invalid desc_type\n");
3965 }
3966
3967 if (deref->deref.child) {
3968 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3969
3970 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3971 offset += child->base_offset * stride;
3972 if (child->deref_array_type == nir_deref_array_type_indirect) {
3973 index = get_src(ctx, child->indirect);
3974 }
3975
3976 constant_index = child->base_offset;
3977 }
3978 if (desc_type == DESC_SAMPLER && binding->immutable_samplers_offset &&
3979 (!index || binding->immutable_samplers_equal)) {
3980 if (binding->immutable_samplers_equal)
3981 constant_index = 0;
3982
3983 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
3984
3985 LLVMValueRef constants[] = {
3986 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
3987 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
3988 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
3989 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
3990 };
3991 return ac_build_gather_values(&ctx->ac, constants, 4);
3992 }
3993
3994 assert(stride % type_size == 0);
3995
3996 if (!index)
3997 index = ctx->i32zero;
3998
3999 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4000
4001 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4002 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4003
4004 return ac_build_indexed_load_const(&ctx->ac, list, index);
4005 }
4006
4007 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
4008 struct ac_image_args *args,
4009 nir_tex_instr *instr,
4010 nir_texop op,
4011 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4012 LLVMValueRef *param, unsigned count,
4013 unsigned dmask)
4014 {
4015 unsigned is_rect = 0;
4016 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4017
4018 if (op == nir_texop_lod)
4019 da = false;
4020 /* Pad to power of two vector */
4021 while (count < util_next_power_of_two(count))
4022 param[count++] = LLVMGetUndef(ctx->i32);
4023
4024 if (count > 1)
4025 args->addr = ac_build_gather_values(&ctx->ac, param, count);
4026 else
4027 args->addr = param[0];
4028
4029 args->resource = res_ptr;
4030 args->sampler = samp_ptr;
4031
4032 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4033 args->addr = param[0];
4034 return;
4035 }
4036
4037 args->dmask = dmask;
4038 args->unorm = is_rect;
4039 args->da = da;
4040 }
4041
4042 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4043 *
4044 * SI-CI:
4045 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4046 * filtering manually. The driver sets img7 to a mask clearing
4047 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4048 * s_and_b32 samp0, samp0, img7
4049 *
4050 * VI:
4051 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4052 */
4053 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
4054 LLVMValueRef res, LLVMValueRef samp)
4055 {
4056 LLVMBuilderRef builder = ctx->builder;
4057 LLVMValueRef img7, samp0;
4058
4059 if (ctx->options->chip_class >= VI)
4060 return samp;
4061
4062 img7 = LLVMBuildExtractElement(builder, res,
4063 LLVMConstInt(ctx->i32, 7, 0), "");
4064 samp0 = LLVMBuildExtractElement(builder, samp,
4065 LLVMConstInt(ctx->i32, 0, 0), "");
4066 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4067 return LLVMBuildInsertElement(builder, samp, samp0,
4068 LLVMConstInt(ctx->i32, 0, 0), "");
4069 }
4070
4071 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
4072 nir_tex_instr *instr,
4073 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4074 LLVMValueRef *fmask_ptr)
4075 {
4076 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4077 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
4078 else
4079 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
4080 if (samp_ptr) {
4081 if (instr->sampler)
4082 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
4083 else
4084 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
4085 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4086 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4087 }
4088 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4089 instr->op == nir_texop_samples_identical))
4090 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
4091 }
4092
4093 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
4094 LLVMValueRef coord)
4095 {
4096 coord = to_float(ctx, coord);
4097 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4098 coord = to_integer(ctx, coord);
4099 return coord;
4100 }
4101
4102 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
4103 {
4104 LLVMValueRef result = NULL;
4105 struct ac_image_args args = { 0 };
4106 unsigned dmask = 0xf;
4107 LLVMValueRef address[16];
4108 LLVMValueRef coords[5];
4109 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4110 LLVMValueRef bias = NULL, offsets = NULL;
4111 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4112 LLVMValueRef ddx = NULL, ddy = NULL;
4113 LLVMValueRef derivs[6];
4114 unsigned chan, count = 0;
4115 unsigned const_src = 0, num_deriv_comp = 0;
4116
4117 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4118
4119 for (unsigned i = 0; i < instr->num_srcs; i++) {
4120 switch (instr->src[i].src_type) {
4121 case nir_tex_src_coord:
4122 coord = get_src(ctx, instr->src[i].src);
4123 break;
4124 case nir_tex_src_projector:
4125 break;
4126 case nir_tex_src_comparator:
4127 comparator = get_src(ctx, instr->src[i].src);
4128 break;
4129 case nir_tex_src_offset:
4130 offsets = get_src(ctx, instr->src[i].src);
4131 const_src = i;
4132 break;
4133 case nir_tex_src_bias:
4134 bias = get_src(ctx, instr->src[i].src);
4135 break;
4136 case nir_tex_src_lod:
4137 lod = get_src(ctx, instr->src[i].src);
4138 break;
4139 case nir_tex_src_ms_index:
4140 sample_index = get_src(ctx, instr->src[i].src);
4141 break;
4142 case nir_tex_src_ms_mcs:
4143 break;
4144 case nir_tex_src_ddx:
4145 ddx = get_src(ctx, instr->src[i].src);
4146 num_deriv_comp = instr->src[i].src.ssa->num_components;
4147 break;
4148 case nir_tex_src_ddy:
4149 ddy = get_src(ctx, instr->src[i].src);
4150 break;
4151 case nir_tex_src_texture_offset:
4152 case nir_tex_src_sampler_offset:
4153 case nir_tex_src_plane:
4154 default:
4155 break;
4156 }
4157 }
4158
4159 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4160 result = get_buffer_size(ctx, res_ptr, true);
4161 goto write_result;
4162 }
4163
4164 if (instr->op == nir_texop_texture_samples) {
4165 LLVMValueRef res, samples, is_msaa;
4166 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
4167 samples = LLVMBuildExtractElement(ctx->builder, res,
4168 LLVMConstInt(ctx->i32, 3, false), "");
4169 is_msaa = LLVMBuildLShr(ctx->builder, samples,
4170 LLVMConstInt(ctx->i32, 28, false), "");
4171 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
4172 LLVMConstInt(ctx->i32, 0xe, false), "");
4173 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
4174 LLVMConstInt(ctx->i32, 0xe, false), "");
4175
4176 samples = LLVMBuildLShr(ctx->builder, samples,
4177 LLVMConstInt(ctx->i32, 16, false), "");
4178 samples = LLVMBuildAnd(ctx->builder, samples,
4179 LLVMConstInt(ctx->i32, 0xf, false), "");
4180 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
4181 samples, "");
4182 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
4183 ctx->i32one, "");
4184 result = samples;
4185 goto write_result;
4186 }
4187
4188 if (coord)
4189 for (chan = 0; chan < instr->coord_components; chan++)
4190 coords[chan] = llvm_extract_elem(ctx, coord, chan);
4191
4192 if (offsets && instr->op != nir_texop_txf) {
4193 LLVMValueRef offset[3], pack;
4194 for (chan = 0; chan < 3; ++chan)
4195 offset[chan] = ctx->i32zero;
4196
4197 args.offset = true;
4198 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4199 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
4200 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
4201 LLVMConstInt(ctx->i32, 0x3f, false), "");
4202 if (chan)
4203 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
4204 LLVMConstInt(ctx->i32, chan * 8, false), "");
4205 }
4206 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
4207 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
4208 address[count++] = pack;
4209
4210 }
4211 /* pack LOD bias value */
4212 if (instr->op == nir_texop_txb && bias) {
4213 address[count++] = bias;
4214 }
4215
4216 /* Pack depth comparison value */
4217 if (instr->is_shadow && comparator) {
4218 address[count++] = llvm_extract_elem(ctx, comparator, 0);
4219 }
4220
4221 /* pack derivatives */
4222 if (ddx || ddy) {
4223 switch (instr->sampler_dim) {
4224 case GLSL_SAMPLER_DIM_3D:
4225 case GLSL_SAMPLER_DIM_CUBE:
4226 num_deriv_comp = 3;
4227 break;
4228 case GLSL_SAMPLER_DIM_2D:
4229 default:
4230 num_deriv_comp = 2;
4231 break;
4232 case GLSL_SAMPLER_DIM_1D:
4233 num_deriv_comp = 1;
4234 break;
4235 }
4236
4237 for (unsigned i = 0; i < num_deriv_comp; i++) {
4238 derivs[i] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
4239 derivs[num_deriv_comp + i] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
4240 }
4241 }
4242
4243 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4244 if (instr->is_array && instr->op != nir_texop_lod)
4245 coords[3] = apply_round_slice(ctx, coords[3]);
4246 for (chan = 0; chan < instr->coord_components; chan++)
4247 coords[chan] = to_float(ctx, coords[chan]);
4248 if (instr->coord_components == 3)
4249 coords[3] = LLVMGetUndef(ctx->f32);
4250 ac_prepare_cube_coords(&ctx->ac,
4251 instr->op == nir_texop_txd, instr->is_array,
4252 coords, derivs);
4253 if (num_deriv_comp)
4254 num_deriv_comp--;
4255 }
4256
4257 if (ddx || ddy) {
4258 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4259 address[count++] = derivs[i];
4260 }
4261
4262 /* Pack texture coordinates */
4263 if (coord) {
4264 address[count++] = coords[0];
4265 if (instr->coord_components > 1) {
4266 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4267 coords[1] = apply_round_slice(ctx, coords[1]);
4268 }
4269 address[count++] = coords[1];
4270 }
4271 if (instr->coord_components > 2) {
4272 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4273 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4274 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4275 instr->op != nir_texop_txf) {
4276 coords[2] = apply_round_slice(ctx, coords[2]);
4277 }
4278 address[count++] = coords[2];
4279 }
4280 }
4281
4282 /* Pack LOD */
4283 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
4284 address[count++] = lod;
4285 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4286 address[count++] = sample_index;
4287 } else if(instr->op == nir_texop_txs) {
4288 count = 0;
4289 if (lod)
4290 address[count++] = lod;
4291 else
4292 address[count++] = ctx->i32zero;
4293 }
4294
4295 for (chan = 0; chan < count; chan++) {
4296 address[chan] = LLVMBuildBitCast(ctx->builder,
4297 address[chan], ctx->i32, "");
4298 }
4299
4300 if (instr->op == nir_texop_samples_identical) {
4301 LLVMValueRef txf_address[4];
4302 struct ac_image_args txf_args = { 0 };
4303 unsigned txf_count = count;
4304 memcpy(txf_address, address, sizeof(txf_address));
4305
4306 if (!instr->is_array)
4307 txf_address[2] = ctx->i32zero;
4308 txf_address[3] = ctx->i32zero;
4309
4310 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
4311 fmask_ptr, NULL,
4312 txf_address, txf_count, 0xf);
4313
4314 result = build_tex_intrinsic(ctx, instr, &txf_args);
4315
4316 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4317 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
4318 goto write_result;
4319 }
4320
4321 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4322 instr->op != nir_texop_txs) {
4323 unsigned sample_chan = instr->is_array ? 3 : 2;
4324 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
4325 address[0],
4326 address[1],
4327 instr->is_array ? address[2] : NULL,
4328 address[sample_chan],
4329 fmask_ptr);
4330 }
4331
4332 if (offsets && instr->op == nir_texop_txf) {
4333 nir_const_value *const_offset =
4334 nir_src_as_const_value(instr->src[const_src].src);
4335 int num_offsets = instr->src[const_src].src.ssa->num_components;
4336 assert(const_offset);
4337 num_offsets = MIN2(num_offsets, instr->coord_components);
4338 if (num_offsets > 2)
4339 address[2] = LLVMBuildAdd(ctx->builder,
4340 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
4341 if (num_offsets > 1)
4342 address[1] = LLVMBuildAdd(ctx->builder,
4343 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
4344 address[0] = LLVMBuildAdd(ctx->builder,
4345 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
4346
4347 }
4348
4349 /* TODO TG4 support */
4350 if (instr->op == nir_texop_tg4) {
4351 if (instr->is_shadow)
4352 dmask = 1;
4353 else
4354 dmask = 1 << instr->component;
4355 }
4356 set_tex_fetch_args(ctx, &args, instr, instr->op,
4357 res_ptr, samp_ptr, address, count, dmask);
4358
4359 result = build_tex_intrinsic(ctx, instr, &args);
4360
4361 if (instr->op == nir_texop_query_levels)
4362 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
4363 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4364 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4365 else if (instr->op == nir_texop_txs &&
4366 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4367 instr->is_array) {
4368 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
4369 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
4370 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
4371 z = LLVMBuildSDiv(ctx->builder, z, six, "");
4372 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
4373 } else if (instr->dest.ssa.num_components != 4)
4374 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
4375
4376 write_result:
4377 if (result) {
4378 assert(instr->dest.is_ssa);
4379 result = to_integer(ctx, result);
4380 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4381 }
4382 }
4383
4384
4385 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
4386 {
4387 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4388 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
4389
4390 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4391 _mesa_hash_table_insert(ctx->phis, instr, result);
4392 }
4393
4394 static void visit_post_phi(struct nir_to_llvm_context *ctx,
4395 nir_phi_instr *instr,
4396 LLVMValueRef llvm_phi)
4397 {
4398 nir_foreach_phi_src(src, instr) {
4399 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4400 LLVMValueRef llvm_src = get_src(ctx, src->src);
4401
4402 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4403 }
4404 }
4405
4406 static void phi_post_pass(struct nir_to_llvm_context *ctx)
4407 {
4408 struct hash_entry *entry;
4409 hash_table_foreach(ctx->phis, entry) {
4410 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4411 (LLVMValueRef)entry->data);
4412 }
4413 }
4414
4415
4416 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
4417 nir_ssa_undef_instr *instr)
4418 {
4419 unsigned num_components = instr->def.num_components;
4420 LLVMValueRef undef;
4421
4422 if (num_components == 1)
4423 undef = LLVMGetUndef(ctx->i32);
4424 else {
4425 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
4426 }
4427 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4428 }
4429
4430 static void visit_jump(struct nir_to_llvm_context *ctx,
4431 nir_jump_instr *instr)
4432 {
4433 switch (instr->type) {
4434 case nir_jump_break:
4435 LLVMBuildBr(ctx->builder, ctx->break_block);
4436 LLVMClearInsertionPosition(ctx->builder);
4437 break;
4438 case nir_jump_continue:
4439 LLVMBuildBr(ctx->builder, ctx->continue_block);
4440 LLVMClearInsertionPosition(ctx->builder);
4441 break;
4442 default:
4443 fprintf(stderr, "Unknown NIR jump instr: ");
4444 nir_print_instr(&instr->instr, stderr);
4445 fprintf(stderr, "\n");
4446 abort();
4447 }
4448 }
4449
4450 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4451 struct exec_list *list);
4452
4453 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
4454 {
4455 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
4456 nir_foreach_instr(instr, block)
4457 {
4458 switch (instr->type) {
4459 case nir_instr_type_alu:
4460 visit_alu(ctx, nir_instr_as_alu(instr));
4461 break;
4462 case nir_instr_type_load_const:
4463 visit_load_const(ctx, nir_instr_as_load_const(instr));
4464 break;
4465 case nir_instr_type_intrinsic:
4466 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4467 break;
4468 case nir_instr_type_tex:
4469 visit_tex(ctx, nir_instr_as_tex(instr));
4470 break;
4471 case nir_instr_type_phi:
4472 visit_phi(ctx, nir_instr_as_phi(instr));
4473 break;
4474 case nir_instr_type_ssa_undef:
4475 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4476 break;
4477 case nir_instr_type_jump:
4478 visit_jump(ctx, nir_instr_as_jump(instr));
4479 break;
4480 default:
4481 fprintf(stderr, "Unknown NIR instr type: ");
4482 nir_print_instr(instr, stderr);
4483 fprintf(stderr, "\n");
4484 abort();
4485 }
4486 }
4487
4488 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4489 }
4490
4491 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
4492 {
4493 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4494
4495 LLVMBasicBlockRef merge_block =
4496 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4497 LLVMBasicBlockRef if_block =
4498 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4499 LLVMBasicBlockRef else_block = merge_block;
4500 if (!exec_list_is_empty(&if_stmt->else_list))
4501 else_block = LLVMAppendBasicBlockInContext(
4502 ctx->context, ctx->main_function, "");
4503
4504 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
4505 LLVMConstInt(ctx->i32, 0, false), "");
4506 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
4507
4508 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
4509 visit_cf_list(ctx, &if_stmt->then_list);
4510 if (LLVMGetInsertBlock(ctx->builder))
4511 LLVMBuildBr(ctx->builder, merge_block);
4512
4513 if (!exec_list_is_empty(&if_stmt->else_list)) {
4514 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
4515 visit_cf_list(ctx, &if_stmt->else_list);
4516 if (LLVMGetInsertBlock(ctx->builder))
4517 LLVMBuildBr(ctx->builder, merge_block);
4518 }
4519
4520 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
4521 }
4522
4523 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
4524 {
4525 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4526 LLVMBasicBlockRef break_parent = ctx->break_block;
4527
4528 ctx->continue_block =
4529 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4530 ctx->break_block =
4531 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4532
4533 LLVMBuildBr(ctx->builder, ctx->continue_block);
4534 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4535 visit_cf_list(ctx, &loop->body);
4536
4537 if (LLVMGetInsertBlock(ctx->builder))
4538 LLVMBuildBr(ctx->builder, ctx->continue_block);
4539 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4540
4541 ctx->continue_block = continue_parent;
4542 ctx->break_block = break_parent;
4543 }
4544
4545 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4546 struct exec_list *list)
4547 {
4548 foreach_list_typed(nir_cf_node, node, node, list)
4549 {
4550 switch (node->type) {
4551 case nir_cf_node_block:
4552 visit_block(ctx, nir_cf_node_as_block(node));
4553 break;
4554
4555 case nir_cf_node_if:
4556 visit_if(ctx, nir_cf_node_as_if(node));
4557 break;
4558
4559 case nir_cf_node_loop:
4560 visit_loop(ctx, nir_cf_node_as_loop(node));
4561 break;
4562
4563 default:
4564 assert(0);
4565 }
4566 }
4567 }
4568
4569 static void
4570 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4571 struct nir_variable *variable)
4572 {
4573 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4574 LLVMValueRef t_offset;
4575 LLVMValueRef t_list;
4576 LLVMValueRef input;
4577 LLVMValueRef buffer_index;
4578 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4579 int idx = variable->data.location;
4580 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4581
4582 variable->data.driver_location = idx * 4;
4583
4584 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4585 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4586 ctx->start_instance, "");
4587 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4588 ctx->shader_info->vs.vgpr_comp_cnt);
4589 } else
4590 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4591 ctx->base_vertex, "");
4592
4593 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4594 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4595
4596 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4597
4598 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4599 buffer_index,
4600 LLVMConstInt(ctx->i32, 0, false),
4601 true);
4602
4603 for (unsigned chan = 0; chan < 4; chan++) {
4604 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4605 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4606 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4607 input, llvm_chan, ""));
4608 }
4609 }
4610 }
4611
4612 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4613 unsigned attr,
4614 LLVMValueRef interp_param,
4615 LLVMValueRef prim_mask,
4616 LLVMValueRef result[4])
4617 {
4618 LLVMValueRef attr_number;
4619 unsigned chan;
4620 LLVMValueRef i, j;
4621 bool interp = interp_param != NULL;
4622
4623 attr_number = LLVMConstInt(ctx->i32, attr, false);
4624
4625 /* fs.constant returns the param from the middle vertex, so it's not
4626 * really useful for flat shading. It's meant to be used for custom
4627 * interpolation (but the intrinsic can't fetch from the other two
4628 * vertices).
4629 *
4630 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4631 * to do the right thing. The only reason we use fs.constant is that
4632 * fs.interp cannot be used on integers, because they can be equal
4633 * to NaN.
4634 */
4635 if (interp) {
4636 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4637 LLVMVectorType(ctx->f32, 2), "");
4638
4639 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4640 ctx->i32zero, "");
4641 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4642 ctx->i32one, "");
4643 }
4644
4645 for (chan = 0; chan < 4; chan++) {
4646 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4647
4648 if (interp) {
4649 result[chan] = ac_build_fs_interp(&ctx->ac,
4650 llvm_chan,
4651 attr_number,
4652 prim_mask, i, j);
4653 } else {
4654 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4655 LLVMConstInt(ctx->i32, 2, false),
4656 llvm_chan,
4657 attr_number,
4658 prim_mask);
4659 }
4660 }
4661 }
4662
4663 static void
4664 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4665 struct nir_variable *variable)
4666 {
4667 int idx = variable->data.location;
4668 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4669 LLVMValueRef interp;
4670
4671 variable->data.driver_location = idx * 4;
4672 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4673
4674 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4675 unsigned interp_type;
4676 if (variable->data.sample) {
4677 interp_type = INTERP_SAMPLE;
4678 ctx->shader_info->fs.force_persample = true;
4679 } else if (variable->data.centroid)
4680 interp_type = INTERP_CENTROID;
4681 else
4682 interp_type = INTERP_CENTER;
4683
4684 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4685 } else
4686 interp = NULL;
4687
4688 for (unsigned i = 0; i < attrib_count; ++i)
4689 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4690
4691 }
4692
4693 static void
4694 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4695 struct nir_variable *variable)
4696 {
4697 switch (ctx->stage) {
4698 case MESA_SHADER_VERTEX:
4699 handle_vs_input_decl(ctx, variable);
4700 break;
4701 case MESA_SHADER_FRAGMENT:
4702 handle_fs_input_decl(ctx, variable);
4703 break;
4704 default:
4705 break;
4706 }
4707
4708 }
4709
4710 static void
4711 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4712 struct nir_shader *nir)
4713 {
4714 unsigned index = 0;
4715 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4716 LLVMValueRef interp_param;
4717 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4718
4719 if (!(ctx->input_mask & (1ull << i)))
4720 continue;
4721
4722 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4723 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4724 interp_param = *inputs;
4725 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4726 inputs);
4727
4728 if (!interp_param)
4729 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4730 ++index;
4731 } else if (i == VARYING_SLOT_POS) {
4732 for(int i = 0; i < 3; ++i)
4733 inputs[i] = ctx->frag_pos[i];
4734
4735 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4736 }
4737 }
4738 ctx->shader_info->fs.num_interp = index;
4739 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4740 ctx->shader_info->fs.has_pcoord = true;
4741 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4742 ctx->shader_info->fs.prim_id_input = true;
4743 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4744 ctx->shader_info->fs.layer_input = true;
4745 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4746 }
4747
4748 static LLVMValueRef
4749 ac_build_alloca(struct nir_to_llvm_context *ctx,
4750 LLVMTypeRef type,
4751 const char *name)
4752 {
4753 LLVMBuilderRef builder = ctx->builder;
4754 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4755 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4756 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4757 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4758 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4759 LLVMValueRef res;
4760
4761 if (first_instr) {
4762 LLVMPositionBuilderBefore(first_builder, first_instr);
4763 } else {
4764 LLVMPositionBuilderAtEnd(first_builder, first_block);
4765 }
4766
4767 res = LLVMBuildAlloca(first_builder, type, name);
4768 LLVMBuildStore(builder, LLVMConstNull(type), res);
4769
4770 LLVMDisposeBuilder(first_builder);
4771
4772 return res;
4773 }
4774
4775 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4776 LLVMTypeRef type,
4777 const char *name)
4778 {
4779 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4780 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4781 return ptr;
4782 }
4783
4784 static void
4785 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4786 struct nir_variable *variable)
4787 {
4788 int idx = variable->data.location + variable->data.index;
4789 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4790 uint64_t mask_attribs;
4791 variable->data.driver_location = idx * 4;
4792
4793 /* tess ctrl has it's own load/store paths for outputs */
4794 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4795 return;
4796
4797 mask_attribs = ((1ull << attrib_count) - 1) << idx;
4798 if (ctx->stage == MESA_SHADER_VERTEX ||
4799 ctx->stage == MESA_SHADER_TESS_EVAL ||
4800 ctx->stage == MESA_SHADER_GEOMETRY) {
4801 if (idx == VARYING_SLOT_CLIP_DIST0) {
4802 int length = ctx->num_output_clips + ctx->num_output_culls;
4803 if (ctx->stage == MESA_SHADER_VERTEX) {
4804 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4805 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4806 }
4807 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4808 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4809 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4810 }
4811
4812 if (length > 4)
4813 attrib_count = 2;
4814 else
4815 attrib_count = 1;
4816 mask_attribs = 1ull << idx;
4817 }
4818 }
4819
4820 for (unsigned i = 0; i < attrib_count; ++i) {
4821 for (unsigned chan = 0; chan < 4; chan++) {
4822 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4823 si_build_alloca_undef(ctx, ctx->f32, "");
4824 }
4825 }
4826 ctx->output_mask |= mask_attribs;
4827 }
4828
4829 static void
4830 setup_locals(struct nir_to_llvm_context *ctx,
4831 struct nir_function *func)
4832 {
4833 int i, j;
4834 ctx->num_locals = 0;
4835 nir_foreach_variable(variable, &func->impl->locals) {
4836 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4837 variable->data.driver_location = ctx->num_locals * 4;
4838 ctx->num_locals += attrib_count;
4839 }
4840 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4841 if (!ctx->locals)
4842 return;
4843
4844 for (i = 0; i < ctx->num_locals; i++) {
4845 for (j = 0; j < 4; j++) {
4846 ctx->locals[i * 4 + j] =
4847 si_build_alloca_undef(ctx, ctx->f32, "temp");
4848 }
4849 }
4850 }
4851
4852 static LLVMValueRef
4853 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4854 {
4855 v = to_float(ctx, v);
4856 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4857 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4858 }
4859
4860
4861 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4862 LLVMValueRef src0, LLVMValueRef src1)
4863 {
4864 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4865 LLVMValueRef comp[2];
4866
4867 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4868 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4869 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4870 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4871 }
4872
4873 /* Initialize arguments for the shader export intrinsic */
4874 static void
4875 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4876 LLVMValueRef *values,
4877 unsigned target,
4878 struct ac_export_args *args)
4879 {
4880 /* Default is 0xf. Adjusted below depending on the format. */
4881 args->enabled_channels = 0xf;
4882
4883 /* Specify whether the EXEC mask represents the valid mask */
4884 args->valid_mask = 0;
4885
4886 /* Specify whether this is the last export */
4887 args->done = 0;
4888
4889 /* Specify the target we are exporting */
4890 args->target = target;
4891
4892 args->compr = false;
4893 args->out[0] = LLVMGetUndef(ctx->f32);
4894 args->out[1] = LLVMGetUndef(ctx->f32);
4895 args->out[2] = LLVMGetUndef(ctx->f32);
4896 args->out[3] = LLVMGetUndef(ctx->f32);
4897
4898 if (!values)
4899 return;
4900
4901 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4902 LLVMValueRef val[4];
4903 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4904 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4905 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4906
4907 switch(col_format) {
4908 case V_028714_SPI_SHADER_ZERO:
4909 args->enabled_channels = 0; /* writemask */
4910 args->target = V_008DFC_SQ_EXP_NULL;
4911 break;
4912
4913 case V_028714_SPI_SHADER_32_R:
4914 args->enabled_channels = 1;
4915 args->out[0] = values[0];
4916 break;
4917
4918 case V_028714_SPI_SHADER_32_GR:
4919 args->enabled_channels = 0x3;
4920 args->out[0] = values[0];
4921 args->out[1] = values[1];
4922 break;
4923
4924 case V_028714_SPI_SHADER_32_AR:
4925 args->enabled_channels = 0x9;
4926 args->out[0] = values[0];
4927 args->out[3] = values[3];
4928 break;
4929
4930 case V_028714_SPI_SHADER_FP16_ABGR:
4931 args->compr = 1;
4932
4933 for (unsigned chan = 0; chan < 2; chan++) {
4934 LLVMValueRef pack_args[2] = {
4935 values[2 * chan],
4936 values[2 * chan + 1]
4937 };
4938 LLVMValueRef packed;
4939
4940 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
4941 args->out[chan] = packed;
4942 }
4943 break;
4944
4945 case V_028714_SPI_SHADER_UNORM16_ABGR:
4946 for (unsigned chan = 0; chan < 4; chan++) {
4947 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
4948 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4949 LLVMConstReal(ctx->f32, 65535), "");
4950 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4951 LLVMConstReal(ctx->f32, 0.5), "");
4952 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4953 ctx->i32, "");
4954 }
4955
4956 args->compr = 1;
4957 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4958 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4959 break;
4960
4961 case V_028714_SPI_SHADER_SNORM16_ABGR:
4962 for (unsigned chan = 0; chan < 4; chan++) {
4963 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4964 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4965 LLVMConstReal(ctx->f32, 32767), "");
4966
4967 /* If positive, add 0.5, else add -0.5. */
4968 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4969 LLVMBuildSelect(ctx->builder,
4970 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4971 val[chan], ctx->f32zero, ""),
4972 LLVMConstReal(ctx->f32, 0.5),
4973 LLVMConstReal(ctx->f32, -0.5), ""), "");
4974 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4975 }
4976
4977 args->compr = 1;
4978 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4979 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4980 break;
4981
4982 case V_028714_SPI_SHADER_UINT16_ABGR: {
4983 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4984
4985 for (unsigned chan = 0; chan < 4; chan++) {
4986 val[chan] = to_integer(ctx, values[chan]);
4987 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4988 }
4989
4990 args->compr = 1;
4991 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4992 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4993 break;
4994 }
4995
4996 case V_028714_SPI_SHADER_SINT16_ABGR: {
4997 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4998 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4999
5000 /* Clamp. */
5001 for (unsigned chan = 0; chan < 4; chan++) {
5002 val[chan] = to_integer(ctx, values[chan]);
5003 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
5004 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
5005 }
5006
5007 args->compr = 1;
5008 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5009 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5010 break;
5011 }
5012
5013 default:
5014 case V_028714_SPI_SHADER_32_ABGR:
5015 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5016 break;
5017 }
5018 } else
5019 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5020
5021 for (unsigned i = 0; i < 4; ++i)
5022 args->out[i] = to_float(ctx, args->out[i]);
5023 }
5024
5025 static void
5026 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5027 struct ac_vs_output_info *outinfo)
5028 {
5029 uint32_t param_count = 0;
5030 unsigned target;
5031 unsigned pos_idx, num_pos_exports = 0;
5032 struct ac_export_args args, pos_args[4] = {};
5033 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5034 int i;
5035
5036 outinfo->prim_id_output = 0xffffffff;
5037 outinfo->layer_output = 0xffffffff;
5038 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5039 LLVMValueRef slots[8];
5040 unsigned j;
5041
5042 if (outinfo->cull_dist_mask)
5043 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5044
5045 i = VARYING_SLOT_CLIP_DIST0;
5046 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5047 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5048 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5049
5050 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5051 slots[i] = LLVMGetUndef(ctx->f32);
5052
5053 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5054 target = V_008DFC_SQ_EXP_POS + 3;
5055 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5056 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5057 &args, sizeof(args));
5058 }
5059
5060 target = V_008DFC_SQ_EXP_POS + 2;
5061 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5062 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5063 &args, sizeof(args));
5064
5065 }
5066
5067 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5068 LLVMValueRef values[4];
5069 if (!(ctx->output_mask & (1ull << i)))
5070 continue;
5071
5072 for (unsigned j = 0; j < 4; j++)
5073 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5074 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5075
5076 if (i == VARYING_SLOT_POS) {
5077 target = V_008DFC_SQ_EXP_POS;
5078 } else if (i == VARYING_SLOT_CLIP_DIST0) {
5079 continue;
5080 } else if (i == VARYING_SLOT_PSIZ) {
5081 outinfo->writes_pointsize = true;
5082 psize_value = values[0];
5083 continue;
5084 } else if (i == VARYING_SLOT_LAYER) {
5085 outinfo->writes_layer = true;
5086 layer_value = values[0];
5087 outinfo->layer_output = param_count;
5088 target = V_008DFC_SQ_EXP_PARAM + param_count;
5089 param_count++;
5090 } else if (i == VARYING_SLOT_VIEWPORT) {
5091 outinfo->writes_viewport_index = true;
5092 viewport_index_value = values[0];
5093 continue;
5094 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5095 outinfo->prim_id_output = param_count;
5096 target = V_008DFC_SQ_EXP_PARAM + param_count;
5097 param_count++;
5098 } else if (i >= VARYING_SLOT_VAR0) {
5099 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5100 target = V_008DFC_SQ_EXP_PARAM + param_count;
5101 param_count++;
5102 }
5103
5104 si_llvm_init_export_args(ctx, values, target, &args);
5105
5106 if (target >= V_008DFC_SQ_EXP_POS &&
5107 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5108 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5109 &args, sizeof(args));
5110 } else {
5111 ac_build_export(&ctx->ac, &args);
5112 }
5113 }
5114
5115 /* We need to add the position output manually if it's missing. */
5116 if (!pos_args[0].out[0]) {
5117 pos_args[0].enabled_channels = 0xf;
5118 pos_args[0].valid_mask = 0;
5119 pos_args[0].done = 0;
5120 pos_args[0].target = V_008DFC_SQ_EXP_POS;
5121 pos_args[0].compr = 0;
5122 pos_args[0].out[0] = ctx->f32zero; /* X */
5123 pos_args[0].out[1] = ctx->f32zero; /* Y */
5124 pos_args[0].out[2] = ctx->f32zero; /* Z */
5125 pos_args[0].out[3] = ctx->f32one; /* W */
5126 }
5127
5128 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5129 (outinfo->writes_layer == true ? 4 : 0) |
5130 (outinfo->writes_viewport_index == true ? 8 : 0));
5131 if (mask) {
5132 pos_args[1].enabled_channels = mask;
5133 pos_args[1].valid_mask = 0;
5134 pos_args[1].done = 0;
5135 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5136 pos_args[1].compr = 0;
5137 pos_args[1].out[0] = ctx->f32zero; /* X */
5138 pos_args[1].out[1] = ctx->f32zero; /* Y */
5139 pos_args[1].out[2] = ctx->f32zero; /* Z */
5140 pos_args[1].out[3] = ctx->f32zero; /* W */
5141
5142 if (outinfo->writes_pointsize == true)
5143 pos_args[1].out[0] = psize_value;
5144 if (outinfo->writes_layer == true)
5145 pos_args[1].out[2] = layer_value;
5146 if (outinfo->writes_viewport_index == true)
5147 pos_args[1].out[3] = viewport_index_value;
5148 }
5149 for (i = 0; i < 4; i++) {
5150 if (pos_args[i].out[0])
5151 num_pos_exports++;
5152 }
5153
5154 pos_idx = 0;
5155 for (i = 0; i < 4; i++) {
5156 if (!pos_args[i].out[0])
5157 continue;
5158
5159 /* Specify the target we are exporting */
5160 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5161 if (pos_idx == num_pos_exports)
5162 pos_args[i].done = 1;
5163 ac_build_export(&ctx->ac, &pos_args[i]);
5164 }
5165
5166 outinfo->pos_exports = num_pos_exports;
5167 outinfo->param_exports = param_count;
5168 }
5169
5170 static void
5171 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5172 struct ac_es_output_info *outinfo)
5173 {
5174 int j;
5175 uint64_t max_output_written = 0;
5176 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5177 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5178 int param_index;
5179 int length = 4;
5180
5181 if (!(ctx->output_mask & (1ull << i)))
5182 continue;
5183
5184 if (i == VARYING_SLOT_CLIP_DIST0)
5185 length = ctx->num_output_clips + ctx->num_output_culls;
5186
5187 param_index = shader_io_get_unique_index(i);
5188
5189 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5190
5191 for (j = 0; j < length; j++) {
5192 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5193 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5194
5195 ac_build_buffer_store_dword(&ctx->ac,
5196 ctx->esgs_ring,
5197 out_val, 1,
5198 NULL, ctx->es2gs_offset,
5199 (4 * param_index + j) * 4,
5200 1, 1, true, true);
5201 }
5202 }
5203 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5204 }
5205
5206 static void
5207 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5208 {
5209 LLVMValueRef vertex_id = ctx->rel_auto_id;
5210 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5211 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5212 vertex_dw_stride, "");
5213
5214 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5215 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5216 int length = 4;
5217
5218 if (!(ctx->output_mask & (1ull << i)))
5219 continue;
5220
5221 if (i == VARYING_SLOT_CLIP_DIST0)
5222 length = ctx->num_output_clips + ctx->num_output_culls;
5223 int param = shader_io_get_unique_index(i);
5224 mark_tess_output(ctx, false, param);
5225 if (length > 4)
5226 mark_tess_output(ctx, false, param + 1);
5227 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5228 LLVMConstInt(ctx->i32, param * 4, false),
5229 "");
5230 for (unsigned j = 0; j < length; j++) {
5231 lds_store(ctx, dw_addr,
5232 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5233 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5234 }
5235 }
5236 }
5237
5238 struct ac_build_if_state
5239 {
5240 struct nir_to_llvm_context *ctx;
5241 LLVMValueRef condition;
5242 LLVMBasicBlockRef entry_block;
5243 LLVMBasicBlockRef true_block;
5244 LLVMBasicBlockRef false_block;
5245 LLVMBasicBlockRef merge_block;
5246 };
5247
5248 static LLVMBasicBlockRef
5249 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5250 {
5251 LLVMBasicBlockRef current_block;
5252 LLVMBasicBlockRef next_block;
5253 LLVMBasicBlockRef new_block;
5254
5255 /* get current basic block */
5256 current_block = LLVMGetInsertBlock(ctx->builder);
5257
5258 /* chqeck if there's another block after this one */
5259 next_block = LLVMGetNextBasicBlock(current_block);
5260 if (next_block) {
5261 /* insert the new block before the next block */
5262 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5263 }
5264 else {
5265 /* append new block after current block */
5266 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5267 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5268 }
5269 return new_block;
5270 }
5271
5272 static void
5273 ac_nir_build_if(struct ac_build_if_state *ifthen,
5274 struct nir_to_llvm_context *ctx,
5275 LLVMValueRef condition)
5276 {
5277 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5278
5279 memset(ifthen, 0, sizeof *ifthen);
5280 ifthen->ctx = ctx;
5281 ifthen->condition = condition;
5282 ifthen->entry_block = block;
5283
5284 /* create endif/merge basic block for the phi functions */
5285 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5286
5287 /* create/insert true_block before merge_block */
5288 ifthen->true_block =
5289 LLVMInsertBasicBlockInContext(ctx->context,
5290 ifthen->merge_block,
5291 "if-true-block");
5292
5293 /* successive code goes into the true block */
5294 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5295 }
5296
5297 /**
5298 * End a conditional.
5299 */
5300 static void
5301 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5302 {
5303 LLVMBuilderRef builder = ifthen->ctx->builder;
5304
5305 /* Insert branch to the merge block from current block */
5306 LLVMBuildBr(builder, ifthen->merge_block);
5307
5308 /*
5309 * Now patch in the various branch instructions.
5310 */
5311
5312 /* Insert the conditional branch instruction at the end of entry_block */
5313 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5314 if (ifthen->false_block) {
5315 /* we have an else clause */
5316 LLVMBuildCondBr(builder, ifthen->condition,
5317 ifthen->true_block, ifthen->false_block);
5318 }
5319 else {
5320 /* no else clause */
5321 LLVMBuildCondBr(builder, ifthen->condition,
5322 ifthen->true_block, ifthen->merge_block);
5323 }
5324
5325 /* Resume building code at end of the ifthen->merge_block */
5326 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5327 }
5328
5329 static void
5330 write_tess_factors(struct nir_to_llvm_context *ctx)
5331 {
5332 unsigned stride, outer_comps, inner_comps;
5333 struct ac_build_if_state if_ctx, inner_if_ctx;
5334 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5335 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5336 unsigned tess_inner_index, tess_outer_index;
5337 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5338 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5339 int i;
5340 emit_barrier(ctx);
5341
5342 switch (ctx->options->key.tcs.primitive_mode) {
5343 case GL_ISOLINES:
5344 stride = 2;
5345 outer_comps = 2;
5346 inner_comps = 0;
5347 break;
5348 case GL_TRIANGLES:
5349 stride = 4;
5350 outer_comps = 3;
5351 inner_comps = 1;
5352 break;
5353 case GL_QUADS:
5354 stride = 6;
5355 outer_comps = 4;
5356 inner_comps = 2;
5357 break;
5358 default:
5359 return;
5360 }
5361
5362 ac_nir_build_if(&if_ctx, ctx,
5363 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5364 invocation_id, ctx->i32zero, ""));
5365
5366 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5367 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5368
5369 mark_tess_output(ctx, true, tess_inner_index);
5370 mark_tess_output(ctx, true, tess_outer_index);
5371 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5372 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5373 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5374 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5375 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5376
5377 for (i = 0; i < 4; i++) {
5378 inner[i] = LLVMGetUndef(ctx->i32);
5379 outer[i] = LLVMGetUndef(ctx->i32);
5380 }
5381
5382 // LINES reverseal
5383 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5384 outer[0] = out[1] = lds_load(ctx, lds_outer);
5385 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5386 LLVMConstInt(ctx->i32, 1, false), "");
5387 outer[1] = out[0] = lds_load(ctx, lds_outer);
5388 } else {
5389 for (i = 0; i < outer_comps; i++) {
5390 outer[i] = out[i] =
5391 lds_load(ctx, lds_outer);
5392 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5393 LLVMConstInt(ctx->i32, 1, false), "");
5394 }
5395 for (i = 0; i < inner_comps; i++) {
5396 inner[i] = out[outer_comps+i] =
5397 lds_load(ctx, lds_inner);
5398 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5399 LLVMConstInt(ctx->i32, 1, false), "");
5400 }
5401 }
5402
5403 /* Convert the outputs to vectors for stores. */
5404 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5405 vec1 = NULL;
5406
5407 if (stride > 4)
5408 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5409
5410
5411 buffer = ctx->hs_ring_tess_factor;
5412 tf_base = ctx->tess_factor_offset;
5413 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5414 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5415
5416 ac_nir_build_if(&inner_if_ctx, ctx,
5417 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5418 rel_patch_id, ctx->i32zero, ""));
5419
5420 /* Store the dynamic HS control word. */
5421 ac_build_buffer_store_dword(&ctx->ac, buffer,
5422 LLVMConstInt(ctx->i32, 0x80000000, false),
5423 1, ctx->i32zero, tf_base,
5424 0, 1, 0, true, false);
5425 ac_nir_build_endif(&inner_if_ctx);
5426
5427 /* Store the tessellation factors. */
5428 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5429 MIN2(stride, 4), byteoffset, tf_base,
5430 4, 1, 0, true, false);
5431 if (vec1)
5432 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5433 stride - 4, byteoffset, tf_base,
5434 20, 1, 0, true, false);
5435
5436 //TODO store to offchip for TES to read - only if TES reads them
5437 if (1) {
5438 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5439 LLVMValueRef tf_inner_offset;
5440 unsigned param_outer, param_inner;
5441
5442 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5443 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5444 LLVMConstInt(ctx->i32, param_outer, 0));
5445
5446 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5447 util_next_power_of_two(outer_comps));
5448
5449 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5450 outer_comps, tf_outer_offset,
5451 ctx->oc_lds, 0, 1, 0, true, false);
5452 if (inner_comps) {
5453 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5454 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5455 LLVMConstInt(ctx->i32, param_inner, 0));
5456
5457 inner_vec = inner_comps == 1 ? inner[0] :
5458 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5459 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5460 inner_comps, tf_inner_offset,
5461 ctx->oc_lds, 0, 1, 0, true, false);
5462 }
5463 }
5464 ac_nir_build_endif(&if_ctx);
5465 }
5466
5467 static void
5468 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5469 {
5470 write_tess_factors(ctx);
5471 }
5472
5473 static void
5474 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5475 LLVMValueRef *color, unsigned param, bool is_last)
5476 {
5477
5478 struct ac_export_args args;
5479
5480 /* Export */
5481 si_llvm_init_export_args(ctx, color, param,
5482 &args);
5483
5484 if (is_last) {
5485 args.valid_mask = 1; /* whether the EXEC mask is valid */
5486 args.done = 1; /* DONE bit */
5487 } else if (!args.enabled_channels)
5488 return; /* unnecessary NULL export */
5489
5490 ac_build_export(&ctx->ac, &args);
5491 }
5492
5493 static void
5494 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5495 LLVMValueRef depth, LLVMValueRef stencil,
5496 LLVMValueRef samplemask)
5497 {
5498 struct ac_export_args args;
5499
5500 args.enabled_channels = 0;
5501 args.valid_mask = 1;
5502 args.done = 1;
5503 args.target = V_008DFC_SQ_EXP_MRTZ;
5504 args.compr = false;
5505
5506 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5507 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5508 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5509 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5510
5511 if (depth) {
5512 args.out[0] = depth;
5513 args.enabled_channels |= 0x1;
5514 }
5515
5516 if (stencil) {
5517 args.out[1] = stencil;
5518 args.enabled_channels |= 0x2;
5519 }
5520
5521 if (samplemask) {
5522 args.out[2] = samplemask;
5523 args.enabled_channels |= 0x4;
5524 }
5525
5526 /* SI (except OLAND) has a bug that it only looks
5527 * at the X writemask component. */
5528 if (ctx->options->chip_class == SI &&
5529 ctx->options->family != CHIP_OLAND)
5530 args.enabled_channels |= 0x1;
5531
5532 ac_build_export(&ctx->ac, &args);
5533 }
5534
5535 static void
5536 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5537 {
5538 unsigned index = 0;
5539 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5540
5541 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5542 LLVMValueRef values[4];
5543
5544 if (!(ctx->output_mask & (1ull << i)))
5545 continue;
5546
5547 if (i == FRAG_RESULT_DEPTH) {
5548 ctx->shader_info->fs.writes_z = true;
5549 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
5550 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5551 } else if (i == FRAG_RESULT_STENCIL) {
5552 ctx->shader_info->fs.writes_stencil = true;
5553 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
5554 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5555 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5556 ctx->shader_info->fs.writes_sample_mask = true;
5557 samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
5558 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5559 } else {
5560 bool last = false;
5561 for (unsigned j = 0; j < 4; j++)
5562 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5563 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5564
5565 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5566 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5567
5568 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
5569 index++;
5570 }
5571 }
5572
5573 if (depth || stencil || samplemask)
5574 si_export_mrt_z(ctx, depth, stencil, samplemask);
5575 else if (!index)
5576 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
5577
5578 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5579 }
5580
5581 static void
5582 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5583 {
5584 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5585 }
5586
5587 static void
5588 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
5589 {
5590 switch (ctx->stage) {
5591 case MESA_SHADER_VERTEX:
5592 if (ctx->options->key.vs.as_ls)
5593 handle_ls_outputs_post(ctx);
5594 else if (ctx->options->key.vs.as_es)
5595 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5596 else
5597 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
5598 break;
5599 case MESA_SHADER_FRAGMENT:
5600 handle_fs_outputs_post(ctx);
5601 break;
5602 case MESA_SHADER_GEOMETRY:
5603 emit_gs_epilogue(ctx);
5604 break;
5605 case MESA_SHADER_TESS_CTRL:
5606 handle_tcs_outputs_post(ctx);
5607 break;
5608 case MESA_SHADER_TESS_EVAL:
5609 if (ctx->options->key.tes.as_es)
5610 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
5611 else
5612 handle_vs_outputs_post(ctx, &ctx->shader_info->tes.outinfo);
5613 break;
5614 default:
5615 break;
5616 }
5617 }
5618
5619 static void
5620 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
5621 struct nir_variable *variable, uint32_t *offset, int idx)
5622 {
5623 unsigned size = glsl_count_attribute_slots(variable->type, false);
5624 variable->data.driver_location = *offset;
5625 *offset += size;
5626 }
5627
5628 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
5629 {
5630 LLVMPassManagerRef passmgr;
5631 /* Create the pass manager */
5632 passmgr = LLVMCreateFunctionPassManagerForModule(
5633 ctx->module);
5634
5635 /* This pass should eliminate all the load and store instructions */
5636 LLVMAddPromoteMemoryToRegisterPass(passmgr);
5637
5638 /* Add some optimization passes */
5639 LLVMAddScalarReplAggregatesPass(passmgr);
5640 LLVMAddLICMPass(passmgr);
5641 LLVMAddAggressiveDCEPass(passmgr);
5642 LLVMAddCFGSimplificationPass(passmgr);
5643 LLVMAddInstructionCombiningPass(passmgr);
5644
5645 /* Run the pass */
5646 LLVMInitializeFunctionPassManager(passmgr);
5647 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
5648 LLVMFinalizeFunctionPassManager(passmgr);
5649
5650 LLVMDisposeBuilder(ctx->builder);
5651 LLVMDisposePassManager(passmgr);
5652 }
5653
5654 static void
5655 ac_setup_rings(struct nir_to_llvm_context *ctx)
5656 {
5657 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
5658 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
5659 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
5660 }
5661
5662 if (ctx->is_gs_copy_shader) {
5663 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
5664 }
5665 if (ctx->stage == MESA_SHADER_GEOMETRY) {
5666 LLVMValueRef tmp;
5667 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
5668 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
5669
5670 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
5671
5672 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
5673 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
5674 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
5675 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
5676
5677 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
5678 }
5679
5680 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
5681 ctx->stage == MESA_SHADER_TESS_EVAL) {
5682 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
5683 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
5684 }
5685 }
5686
5687 static
5688 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
5689 struct nir_shader *nir,
5690 struct ac_shader_variant_info *shader_info,
5691 const struct ac_nir_compiler_options *options)
5692 {
5693 struct nir_to_llvm_context ctx = {0};
5694 struct nir_function *func;
5695 unsigned i;
5696 ctx.options = options;
5697 ctx.shader_info = shader_info;
5698 ctx.context = LLVMContextCreate();
5699 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5700
5701 ac_llvm_context_init(&ctx.ac, ctx.context);
5702 ctx.ac.module = ctx.module;
5703
5704 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
5705
5706 memset(shader_info, 0, sizeof(*shader_info));
5707
5708 ac_nir_shader_info_pass(nir, options, &shader_info->info);
5709
5710 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
5711
5712 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
5713 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
5714 LLVMSetDataLayout(ctx.module, data_layout_str);
5715 LLVMDisposeTargetData(data_layout);
5716 LLVMDisposeMessage(data_layout_str);
5717
5718 setup_types(&ctx);
5719
5720 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5721 ctx.ac.builder = ctx.builder;
5722 ctx.stage = nir->stage;
5723
5724 for (i = 0; i < AC_UD_MAX_SETS; i++)
5725 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
5726 for (i = 0; i < AC_UD_MAX_UD; i++)
5727 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
5728
5729 create_function(&ctx);
5730
5731 if (nir->stage == MESA_SHADER_COMPUTE) {
5732 int num_shared = 0;
5733 nir_foreach_variable(variable, &nir->shared)
5734 num_shared++;
5735 if (num_shared) {
5736 int idx = 0;
5737 uint32_t shared_size = 0;
5738 LLVMValueRef var;
5739 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
5740 nir_foreach_variable(variable, &nir->shared) {
5741 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
5742 idx++;
5743 }
5744
5745 shared_size *= 16;
5746 var = LLVMAddGlobalInAddressSpace(ctx.module,
5747 LLVMArrayType(ctx.i8, shared_size),
5748 "compute_lds",
5749 LOCAL_ADDR_SPACE);
5750 LLVMSetAlignment(var, 4);
5751 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
5752 }
5753 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
5754 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
5755
5756 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
5757 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
5758 ctx.tes_primitive_mode = nir->info->tess.primitive_mode;
5759 }
5760
5761 ac_setup_rings(&ctx);
5762
5763 nir_foreach_variable(variable, &nir->inputs)
5764 handle_shader_input_decl(&ctx, variable);
5765
5766 if (nir->stage == MESA_SHADER_FRAGMENT)
5767 handle_fs_inputs_pre(&ctx, nir);
5768
5769 ctx.num_output_clips = nir->info->clip_distance_array_size;
5770 ctx.num_output_culls = nir->info->cull_distance_array_size;
5771
5772 nir_foreach_variable(variable, &nir->outputs)
5773 handle_shader_output_decl(&ctx, variable);
5774
5775 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5776 _mesa_key_pointer_equal);
5777 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5778 _mesa_key_pointer_equal);
5779
5780 func = (struct nir_function *)exec_list_get_head(&nir->functions);
5781
5782 setup_locals(&ctx, func);
5783
5784 visit_cf_list(&ctx, &func->impl->body);
5785 phi_post_pass(&ctx);
5786
5787 handle_shader_outputs_post(&ctx);
5788 LLVMBuildRetVoid(ctx.builder);
5789
5790 ac_llvm_finalize_module(&ctx);
5791 free(ctx.locals);
5792 ralloc_free(ctx.defs);
5793 ralloc_free(ctx.phis);
5794
5795 if (nir->stage == MESA_SHADER_GEOMETRY) {
5796 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
5797 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
5798 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
5799 nir->info->gs.vertices_out;
5800 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
5801 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
5802 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
5803 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
5804 shader_info->vs.outputs_written = ctx.tess_outputs_written;
5805 }
5806
5807 return ctx.module;
5808 }
5809
5810 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
5811 {
5812 unsigned *retval = (unsigned *)context;
5813 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
5814 char *description = LLVMGetDiagInfoDescription(di);
5815
5816 if (severity == LLVMDSError) {
5817 *retval = 1;
5818 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
5819 description);
5820 }
5821
5822 LLVMDisposeMessage(description);
5823 }
5824
5825 static unsigned ac_llvm_compile(LLVMModuleRef M,
5826 struct ac_shader_binary *binary,
5827 LLVMTargetMachineRef tm)
5828 {
5829 unsigned retval = 0;
5830 char *err;
5831 LLVMContextRef llvm_ctx;
5832 LLVMMemoryBufferRef out_buffer;
5833 unsigned buffer_size;
5834 const char *buffer_data;
5835 LLVMBool mem_err;
5836
5837 /* Setup Diagnostic Handler*/
5838 llvm_ctx = LLVMGetModuleContext(M);
5839
5840 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
5841 &retval);
5842
5843 /* Compile IR*/
5844 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
5845 &err, &out_buffer);
5846
5847 /* Process Errors/Warnings */
5848 if (mem_err) {
5849 fprintf(stderr, "%s: %s", __FUNCTION__, err);
5850 free(err);
5851 retval = 1;
5852 goto out;
5853 }
5854
5855 /* Extract Shader Code*/
5856 buffer_size = LLVMGetBufferSize(out_buffer);
5857 buffer_data = LLVMGetBufferStart(out_buffer);
5858
5859 ac_elf_read(buffer_data, buffer_size, binary);
5860
5861 /* Clean up */
5862 LLVMDisposeMemoryBuffer(out_buffer);
5863
5864 out:
5865 return retval;
5866 }
5867
5868 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
5869 LLVMModuleRef llvm_module,
5870 struct ac_shader_binary *binary,
5871 struct ac_shader_config *config,
5872 struct ac_shader_variant_info *shader_info,
5873 gl_shader_stage stage,
5874 bool dump_shader, bool supports_spill)
5875 {
5876 if (dump_shader)
5877 ac_dump_module(llvm_module);
5878
5879 memset(binary, 0, sizeof(*binary));
5880 int v = ac_llvm_compile(llvm_module, binary, tm);
5881 if (v) {
5882 fprintf(stderr, "compile failed\n");
5883 }
5884
5885 if (dump_shader)
5886 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
5887
5888 ac_shader_binary_read_config(binary, config, 0, supports_spill);
5889
5890 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
5891 LLVMDisposeModule(llvm_module);
5892 LLVMContextDispose(ctx);
5893
5894 if (stage == MESA_SHADER_FRAGMENT) {
5895 shader_info->num_input_vgprs = 0;
5896 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
5897 shader_info->num_input_vgprs += 2;
5898 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
5899 shader_info->num_input_vgprs += 2;
5900 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
5901 shader_info->num_input_vgprs += 2;
5902 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
5903 shader_info->num_input_vgprs += 3;
5904 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
5905 shader_info->num_input_vgprs += 2;
5906 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
5907 shader_info->num_input_vgprs += 2;
5908 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
5909 shader_info->num_input_vgprs += 2;
5910 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
5911 shader_info->num_input_vgprs += 1;
5912 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
5913 shader_info->num_input_vgprs += 1;
5914 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
5915 shader_info->num_input_vgprs += 1;
5916 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5917 shader_info->num_input_vgprs += 1;
5918 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5919 shader_info->num_input_vgprs += 1;
5920 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5921 shader_info->num_input_vgprs += 1;
5922 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5923 shader_info->num_input_vgprs += 1;
5924 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5925 shader_info->num_input_vgprs += 1;
5926 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5927 shader_info->num_input_vgprs += 1;
5928 }
5929 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5930
5931 /* +3 for scratch wave offset and VCC */
5932 config->num_sgprs = MAX2(config->num_sgprs,
5933 shader_info->num_input_sgprs + 3);
5934 }
5935
5936 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5937 struct ac_shader_binary *binary,
5938 struct ac_shader_config *config,
5939 struct ac_shader_variant_info *shader_info,
5940 struct nir_shader *nir,
5941 const struct ac_nir_compiler_options *options,
5942 bool dump_shader)
5943 {
5944
5945 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5946 options);
5947
5948 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5949 switch (nir->stage) {
5950 case MESA_SHADER_COMPUTE:
5951 for (int i = 0; i < 3; ++i)
5952 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5953 break;
5954 case MESA_SHADER_FRAGMENT:
5955 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5956 break;
5957 case MESA_SHADER_GEOMETRY:
5958 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5959 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5960 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5961 shader_info->gs.invocations = nir->info->gs.invocations;
5962 break;
5963 case MESA_SHADER_TESS_EVAL:
5964 shader_info->tes.primitive_mode = nir->info->tess.primitive_mode;
5965 shader_info->tes.spacing = nir->info->tess.spacing;
5966 shader_info->tes.ccw = nir->info->tess.ccw;
5967 shader_info->tes.point_mode = nir->info->tess.point_mode;
5968 shader_info->tes.as_es = options->key.tes.as_es;
5969 break;
5970 case MESA_SHADER_TESS_CTRL:
5971 shader_info->tcs.tcs_vertices_out = nir->info->tess.tcs_vertices_out;
5972 break;
5973 case MESA_SHADER_VERTEX:
5974 shader_info->vs.as_es = options->key.vs.as_es;
5975 shader_info->vs.as_ls = options->key.vs.as_ls;
5976 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
5977 if (options->key.vs.as_ls)
5978 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
5979 break;
5980 default:
5981 break;
5982 }
5983 }
5984
5985 static void
5986 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5987 {
5988 LLVMValueRef args[9];
5989 args[0] = ctx->gsvs_ring;
5990 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5991 args[3] = ctx->i32zero;
5992 args[4] = ctx->i32one; /* OFFEN */
5993 args[5] = ctx->i32zero; /* IDXEN */
5994 args[6] = ctx->i32one; /* GLC */
5995 args[7] = ctx->i32one; /* SLC */
5996 args[8] = ctx->i32zero; /* TFE */
5997
5998 int idx = 0;
5999
6000 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6001 int length = 4;
6002 int slot = idx;
6003 int slot_inc = 1;
6004 if (!(ctx->output_mask & (1ull << i)))
6005 continue;
6006
6007 if (i == VARYING_SLOT_CLIP_DIST0) {
6008 /* unpack clip and cull from a single set of slots */
6009 length = ctx->num_output_clips + ctx->num_output_culls;
6010 if (length > 4)
6011 slot_inc = 2;
6012 }
6013
6014 for (unsigned j = 0; j < length; j++) {
6015 LLVMValueRef value;
6016 args[2] = LLVMConstInt(ctx->i32,
6017 (slot * 4 + j) *
6018 ctx->gs_max_out_vertices * 16 * 4, false);
6019
6020 value = ac_build_intrinsic(&ctx->ac,
6021 "llvm.SI.buffer.load.dword.i32.i32",
6022 ctx->i32, args, 9,
6023 AC_FUNC_ATTR_READONLY |
6024 AC_FUNC_ATTR_LEGACY);
6025
6026 LLVMBuildStore(ctx->builder,
6027 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
6028 }
6029 idx += slot_inc;
6030 }
6031 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
6032 }
6033
6034 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6035 struct nir_shader *geom_shader,
6036 struct ac_shader_binary *binary,
6037 struct ac_shader_config *config,
6038 struct ac_shader_variant_info *shader_info,
6039 const struct ac_nir_compiler_options *options,
6040 bool dump_shader)
6041 {
6042 struct nir_to_llvm_context ctx = {0};
6043 ctx.context = LLVMContextCreate();
6044 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6045 ctx.options = options;
6046 ctx.shader_info = shader_info;
6047
6048 ac_llvm_context_init(&ctx.ac, ctx.context);
6049 ctx.ac.module = ctx.module;
6050
6051 ctx.is_gs_copy_shader = true;
6052 LLVMSetTarget(ctx.module, "amdgcn--");
6053 setup_types(&ctx);
6054
6055 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6056 ctx.ac.builder = ctx.builder;
6057 ctx.stage = MESA_SHADER_VERTEX;
6058
6059 create_function(&ctx);
6060
6061 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
6062 ac_setup_rings(&ctx);
6063
6064 ctx.num_output_clips = geom_shader->info->clip_distance_array_size;
6065 ctx.num_output_culls = geom_shader->info->cull_distance_array_size;
6066
6067 nir_foreach_variable(variable, &geom_shader->outputs)
6068 handle_shader_output_decl(&ctx, variable);
6069
6070 ac_gs_copy_shader_emit(&ctx);
6071
6072 LLVMBuildRetVoid(ctx.builder);
6073
6074 ac_llvm_finalize_module(&ctx);
6075
6076 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6077 MESA_SHADER_VERTEX,
6078 dump_shader, options->supports_spill);
6079 }