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amd/common: add ac_build_waitcnt()
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids;
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tcs_patch_id;
115 LLVMValueRef tcs_rel_ids;
116 LLVMValueRef tes_rel_patch_id;
117 LLVMValueRef tes_patch_id;
118 LLVMValueRef tes_u;
119 LLVMValueRef tes_v;
120
121 LLVMValueRef gsvs_ring_stride;
122 LLVMValueRef gsvs_num_entries;
123 LLVMValueRef gs2vs_offset;
124 LLVMValueRef gs_wave_id;
125 LLVMValueRef gs_vtx_offset[6];
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 gl_shader_stage stage;
138
139 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
140
141 uint64_t input_mask;
142 uint64_t output_mask;
143 uint8_t num_output_clips;
144 uint8_t num_output_culls;
145
146 bool is_gs_copy_shader;
147 LLVMValueRef gs_next_vertex;
148 unsigned gs_max_out_vertices;
149
150 unsigned tes_primitive_mode;
151 uint64_t tess_outputs_written;
152 uint64_t tess_patch_outputs_written;
153
154 uint32_t tcs_patch_outputs_read;
155 uint64_t tcs_outputs_read;
156 };
157
158 static inline struct nir_to_llvm_context *
159 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
160 {
161 struct nir_to_llvm_context *ctx = NULL;
162 return container_of(abi, ctx, abi);
163 }
164
165 static LLVMTypeRef
166 nir2llvmtype(struct ac_nir_context *ctx,
167 const struct glsl_type *type)
168 {
169 switch (glsl_get_base_type(glsl_without_array(type))) {
170 case GLSL_TYPE_UINT:
171 case GLSL_TYPE_INT:
172 return ctx->ac.i32;
173 case GLSL_TYPE_UINT64:
174 case GLSL_TYPE_INT64:
175 return ctx->ac.i64;
176 case GLSL_TYPE_DOUBLE:
177 return ctx->ac.f64;
178 case GLSL_TYPE_FLOAT:
179 return ctx->ac.f32;
180 default:
181 assert(!"Unsupported type in nir2llvmtype()");
182 break;
183 }
184 return 0;
185 }
186
187 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
188 const nir_deref_var *deref,
189 enum ac_descriptor_type desc_type,
190 const nir_tex_instr *instr,
191 bool image, bool write);
192
193 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
194 {
195 return (index * 4) + chan;
196 }
197
198 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
199 {
200 /* handle patch indices separate */
201 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
202 return 0;
203 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
204 return 1;
205 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
206 return 2 + (slot - VARYING_SLOT_PATCH0);
207
208 if (slot == VARYING_SLOT_POS)
209 return 0;
210 if (slot == VARYING_SLOT_PSIZ)
211 return 1;
212 if (slot == VARYING_SLOT_CLIP_DIST0)
213 return 2;
214 /* 3 is reserved for clip dist as well */
215 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
216 return 4 + (slot - VARYING_SLOT_VAR0);
217 unreachable("illegal slot in get unique index\n");
218 }
219
220 static void set_llvm_calling_convention(LLVMValueRef func,
221 gl_shader_stage stage)
222 {
223 enum radeon_llvm_calling_convention calling_conv;
224
225 switch (stage) {
226 case MESA_SHADER_VERTEX:
227 case MESA_SHADER_TESS_EVAL:
228 calling_conv = RADEON_LLVM_AMDGPU_VS;
229 break;
230 case MESA_SHADER_GEOMETRY:
231 calling_conv = RADEON_LLVM_AMDGPU_GS;
232 break;
233 case MESA_SHADER_TESS_CTRL:
234 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
235 break;
236 case MESA_SHADER_FRAGMENT:
237 calling_conv = RADEON_LLVM_AMDGPU_PS;
238 break;
239 case MESA_SHADER_COMPUTE:
240 calling_conv = RADEON_LLVM_AMDGPU_CS;
241 break;
242 default:
243 unreachable("Unhandle shader type");
244 }
245
246 LLVMSetFunctionCallConv(func, calling_conv);
247 }
248
249 #define MAX_ARGS 23
250 struct arg_info {
251 LLVMTypeRef types[MAX_ARGS];
252 LLVMValueRef *assign[MAX_ARGS];
253 unsigned array_params_mask;
254 uint8_t count;
255 uint8_t user_sgpr_count;
256 uint8_t sgpr_count;
257 uint8_t num_user_sgprs_used;
258 uint8_t num_sgprs_used;
259 uint8_t num_vgprs_used;
260 };
261
262 static inline void
263 add_argument(struct arg_info *info,
264 LLVMTypeRef type, LLVMValueRef *param_ptr)
265 {
266 assert(info->count < MAX_ARGS);
267 info->assign[info->count] = param_ptr;
268 info->types[info->count] = type;
269 info->count++;
270 }
271
272 static inline void
273 add_sgpr_argument(struct arg_info *info,
274 LLVMTypeRef type, LLVMValueRef *param_ptr)
275 {
276 add_argument(info, type, param_ptr);
277 info->num_sgprs_used += ac_get_type_size(type) / 4;
278 info->sgpr_count++;
279 }
280
281 static inline void
282 add_user_sgpr_argument(struct arg_info *info,
283 LLVMTypeRef type,
284 LLVMValueRef *param_ptr)
285 {
286 add_sgpr_argument(info, type, param_ptr);
287 info->num_user_sgprs_used += ac_get_type_size(type) / 4;
288 info->user_sgpr_count++;
289 }
290
291 static inline void
292 add_vgpr_argument(struct arg_info *info,
293 LLVMTypeRef type,
294 LLVMValueRef *param_ptr)
295 {
296 add_argument(info, type, param_ptr);
297 info->num_vgprs_used += ac_get_type_size(type) / 4;
298 }
299
300 static inline void
301 add_user_sgpr_array_argument(struct arg_info *info,
302 LLVMTypeRef type,
303 LLVMValueRef *param_ptr)
304 {
305 info->array_params_mask |= (1 << info->count);
306 add_user_sgpr_argument(info, type, param_ptr);
307 }
308
309 static void assign_arguments(LLVMValueRef main_function,
310 struct arg_info *info)
311 {
312 unsigned i;
313 for (i = 0; i < info->count; i++) {
314 if (info->assign[i])
315 *info->assign[i] = LLVMGetParam(main_function, i);
316 }
317 }
318
319 static LLVMValueRef
320 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
321 LLVMBuilderRef builder, LLVMTypeRef *return_types,
322 unsigned num_return_elems,
323 struct arg_info *args,
324 unsigned max_workgroup_size,
325 bool unsafe_math)
326 {
327 LLVMTypeRef main_function_type, ret_type;
328 LLVMBasicBlockRef main_function_body;
329
330 if (num_return_elems)
331 ret_type = LLVMStructTypeInContext(ctx, return_types,
332 num_return_elems, true);
333 else
334 ret_type = LLVMVoidTypeInContext(ctx);
335
336 /* Setup the function */
337 main_function_type =
338 LLVMFunctionType(ret_type, args->types, args->count, 0);
339 LLVMValueRef main_function =
340 LLVMAddFunction(module, "main", main_function_type);
341 main_function_body =
342 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
343 LLVMPositionBuilderAtEnd(builder, main_function_body);
344
345 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
346 for (unsigned i = 0; i < args->sgpr_count; ++i) {
347 if (args->array_params_mask & (1 << i)) {
348 LLVMValueRef P = LLVMGetParam(main_function, i);
349 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
350 ac_add_attr_dereferenceable(P, UINT64_MAX);
351 }
352 else {
353 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
354 }
355 }
356
357 if (max_workgroup_size) {
358 ac_llvm_add_target_dep_function_attr(main_function,
359 "amdgpu-max-work-group-size",
360 max_workgroup_size);
361 }
362 if (unsafe_math) {
363 /* These were copied from some LLVM test. */
364 LLVMAddTargetDependentFunctionAttr(main_function,
365 "less-precise-fpmad",
366 "true");
367 LLVMAddTargetDependentFunctionAttr(main_function,
368 "no-infs-fp-math",
369 "true");
370 LLVMAddTargetDependentFunctionAttr(main_function,
371 "no-nans-fp-math",
372 "true");
373 LLVMAddTargetDependentFunctionAttr(main_function,
374 "unsafe-fp-math",
375 "true");
376 }
377 return main_function;
378 }
379
380 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
381 {
382 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
383 CONST_ADDR_SPACE);
384 }
385
386 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
387 {
388 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
389 type = LLVMGetElementType(type);
390
391 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
392 return LLVMGetIntTypeWidth(type);
393
394 if (type == ctx->f16)
395 return 16;
396 if (type == ctx->f32)
397 return 32;
398 if (type == ctx->f64)
399 return 64;
400
401 unreachable("Unhandled type kind in get_elem_bits");
402 }
403
404 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
405 LLVMValueRef param, unsigned rshift,
406 unsigned bitwidth)
407 {
408 LLVMValueRef value = param;
409 if (rshift)
410 value = LLVMBuildLShr(ctx->builder, value,
411 LLVMConstInt(ctx->i32, rshift, false), "");
412
413 if (rshift + bitwidth < 32) {
414 unsigned mask = (1 << bitwidth) - 1;
415 value = LLVMBuildAnd(ctx->builder, value,
416 LLVMConstInt(ctx->i32, mask, false), "");
417 }
418 return value;
419 }
420
421 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
422 {
423 switch (ctx->stage) {
424 case MESA_SHADER_TESS_CTRL:
425 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
426 case MESA_SHADER_TESS_EVAL:
427 return ctx->tes_rel_patch_id;
428 break;
429 default:
430 unreachable("Illegal stage");
431 }
432 }
433
434 /* Tessellation shaders pass outputs to the next shader using LDS.
435 *
436 * LS outputs = TCS inputs
437 * TCS outputs = TES inputs
438 *
439 * The LDS layout is:
440 * - TCS inputs for patch 0
441 * - TCS inputs for patch 1
442 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
443 * - ...
444 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
445 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
446 * - TCS outputs for patch 1
447 * - Per-patch TCS outputs for patch 1
448 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
449 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
450 * - ...
451 *
452 * All three shaders VS(LS), TCS, TES share the same LDS space.
453 */
454 static LLVMValueRef
455 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
456 {
457 if (ctx->stage == MESA_SHADER_VERTEX)
458 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
459 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
460 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
461 else {
462 assert(0);
463 return NULL;
464 }
465 }
466
467 static LLVMValueRef
468 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
469 {
470 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
471 }
472
473 static LLVMValueRef
474 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
475 {
476 return LLVMBuildMul(ctx->builder,
477 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
478 LLVMConstInt(ctx->ac.i32, 4, false), "");
479 }
480
481 static LLVMValueRef
482 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
483 {
484 return LLVMBuildMul(ctx->builder,
485 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
486 LLVMConstInt(ctx->ac.i32, 4, false), "");
487 }
488
489 static LLVMValueRef
490 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
491 {
492 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
493 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
494
495 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
496 }
497
498 static LLVMValueRef
499 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
500 {
501 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
502 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
503 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
504
505 return LLVMBuildAdd(ctx->builder, patch0_offset,
506 LLVMBuildMul(ctx->builder, patch_stride,
507 rel_patch_id, ""),
508 "");
509 }
510
511 static LLVMValueRef
512 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
513 {
514 LLVMValueRef patch0_patch_data_offset =
515 get_tcs_out_patch0_patch_data_offset(ctx);
516 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
517 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
518
519 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
520 LLVMBuildMul(ctx->builder, patch_stride,
521 rel_patch_id, ""),
522 "");
523 }
524
525 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
526 {
527 ud_info->sgpr_idx = *sgpr_idx;
528 ud_info->num_sgprs = num_sgprs;
529 ud_info->indirect = false;
530 ud_info->indirect_offset = 0;
531 *sgpr_idx += num_sgprs;
532 }
533
534 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
535 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
536 {
537 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
538 }
539
540
541 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
542 uint32_t indirect_offset)
543 {
544 ud_info->sgpr_idx = sgpr_idx;
545 ud_info->num_sgprs = num_sgprs;
546 ud_info->indirect = true;
547 ud_info->indirect_offset = indirect_offset;
548 }
549
550 struct user_sgpr_info {
551 bool need_ring_offsets;
552 uint8_t sgpr_count;
553 bool indirect_all_descriptor_sets;
554 };
555
556 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
557 struct user_sgpr_info *user_sgpr_info)
558 {
559 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
560
561 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
562 if (ctx->stage == MESA_SHADER_GEOMETRY ||
563 ctx->stage == MESA_SHADER_VERTEX ||
564 ctx->stage == MESA_SHADER_TESS_CTRL ||
565 ctx->stage == MESA_SHADER_TESS_EVAL ||
566 ctx->is_gs_copy_shader)
567 user_sgpr_info->need_ring_offsets = true;
568
569 if (ctx->stage == MESA_SHADER_FRAGMENT &&
570 ctx->shader_info->info.ps.needs_sample_positions)
571 user_sgpr_info->need_ring_offsets = true;
572
573 /* 2 user sgprs will nearly always be allocated for scratch/rings */
574 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
575 user_sgpr_info->sgpr_count += 2;
576 }
577
578 switch (ctx->stage) {
579 case MESA_SHADER_COMPUTE:
580 if (ctx->shader_info->info.cs.uses_grid_size)
581 user_sgpr_info->sgpr_count += 3;
582 break;
583 case MESA_SHADER_FRAGMENT:
584 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
585 break;
586 case MESA_SHADER_VERTEX:
587 if (!ctx->is_gs_copy_shader) {
588 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
589 if (ctx->shader_info->info.vs.needs_draw_id) {
590 user_sgpr_info->sgpr_count += 3;
591 } else {
592 user_sgpr_info->sgpr_count += 2;
593 }
594 }
595 if (ctx->options->key.vs.as_ls)
596 user_sgpr_info->sgpr_count++;
597 break;
598 case MESA_SHADER_TESS_CTRL:
599 user_sgpr_info->sgpr_count += 4;
600 break;
601 case MESA_SHADER_TESS_EVAL:
602 user_sgpr_info->sgpr_count += 1;
603 break;
604 case MESA_SHADER_GEOMETRY:
605 user_sgpr_info->sgpr_count += 2;
606 break;
607 default:
608 break;
609 }
610
611 if (ctx->shader_info->info.needs_push_constants)
612 user_sgpr_info->sgpr_count += 2;
613
614 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
615 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
616 user_sgpr_info->sgpr_count += 2;
617 user_sgpr_info->indirect_all_descriptor_sets = true;
618 } else {
619 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
620 }
621 }
622
623 static void
624 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
625 gl_shader_stage stage,
626 bool has_previous_stage,
627 gl_shader_stage previous_stage,
628 const struct user_sgpr_info *user_sgpr_info,
629 struct arg_info *args,
630 LLVMValueRef *desc_sets)
631 {
632 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
633 unsigned stage_mask = 1 << stage;
634 if (has_previous_stage)
635 stage_mask |= 1 << previous_stage;
636
637 /* 1 for each descriptor set */
638 if (!user_sgpr_info->indirect_all_descriptor_sets) {
639 for (unsigned i = 0; i < num_sets; ++i) {
640 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
641 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->descriptor_sets[i]);
642 }
643 }
644 } else
645 add_user_sgpr_array_argument(args, const_array(const_array(ctx->ac.i8, 1024 * 1024), 32), desc_sets);
646
647 if (ctx->shader_info->info.needs_push_constants) {
648 /* 1 for push constants and dynamic descriptors */
649 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->push_constants);
650 }
651 }
652
653 static void
654 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
655 gl_shader_stage stage,
656 bool has_previous_stage,
657 gl_shader_stage previous_stage,
658 const struct user_sgpr_info *user_sgpr_info,
659 LLVMValueRef desc_sets,
660 uint8_t *user_sgpr_idx)
661 {
662 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
663 unsigned stage_mask = 1 << stage;
664 if (has_previous_stage)
665 stage_mask |= 1 << previous_stage;
666
667 if (!user_sgpr_info->indirect_all_descriptor_sets) {
668 for (unsigned i = 0; i < num_sets; ++i) {
669 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
670 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
671 } else
672 ctx->descriptor_sets[i] = NULL;
673 }
674 } else {
675 uint32_t desc_sgpr_idx = *user_sgpr_idx;
676 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
677
678 for (unsigned i = 0; i < num_sets; ++i) {
679 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
680 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
681 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->ac.i32, i, false));
682
683 } else
684 ctx->descriptor_sets[i] = NULL;
685 }
686 ctx->shader_info->need_indirect_descriptor_sets = true;
687 }
688
689 if (ctx->shader_info->info.needs_push_constants) {
690 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
691 }
692 }
693
694 static void
695 radv_define_vs_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
696 gl_shader_stage stage,
697 bool has_previous_stage,
698 gl_shader_stage previous_stage,
699 struct arg_info *args)
700 {
701 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
702 if (ctx->shader_info->info.vs.has_vertex_buffers)
703 add_user_sgpr_argument(args, const_array(ctx->ac.v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
704 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.base_vertex); // base vertex
705 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.start_instance);// start instance
706 if (ctx->shader_info->info.vs.needs_draw_id)
707 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.draw_id); // draw id
708 }
709 }
710
711 static void
712 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
713 gl_shader_stage stage,
714 bool has_previous_stage,
715 gl_shader_stage previous_stage,
716 uint8_t *user_sgpr_idx)
717 {
718 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
719 if (ctx->shader_info->info.vs.has_vertex_buffers) {
720 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
721 }
722 unsigned vs_num = 2;
723 if (ctx->shader_info->info.vs.needs_draw_id)
724 vs_num++;
725
726 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
727 }
728 }
729
730
731 static void create_function(struct nir_to_llvm_context *ctx,
732 gl_shader_stage stage,
733 bool has_previous_stage,
734 gl_shader_stage previous_stage)
735 {
736 uint8_t user_sgpr_idx;
737 struct user_sgpr_info user_sgpr_info;
738 struct arg_info args = {};
739 LLVMValueRef desc_sets;
740
741 allocate_user_sgprs(ctx, &user_sgpr_info);
742
743 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
744 add_user_sgpr_argument(&args, const_array(ctx->ac.v4i32, 16), &ctx->ring_offsets); /* address of rings */
745 }
746
747 switch (stage) {
748 case MESA_SHADER_COMPUTE:
749 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
750 if (ctx->shader_info->info.cs.uses_grid_size) {
751 add_user_sgpr_argument(&args, ctx->ac.v3i32,
752 &ctx->num_work_groups);
753 }
754 add_sgpr_argument(&args, ctx->ac.v3i32, &ctx->workgroup_ids);
755 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
756 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tg_size);
757 add_vgpr_argument(&args, ctx->ac.v3i32, &ctx->local_invocation_ids);
758 break;
759 case MESA_SHADER_VERTEX:
760 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
761 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
762 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
763 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
764 if (ctx->options->key.vs.as_es)
765 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
766 else if (ctx->options->key.vs.as_ls)
767 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
768 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
769 if (!ctx->is_gs_copy_shader) {
770 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
771 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
772 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
773 }
774 break;
775 case MESA_SHADER_TESS_CTRL:
776 if (has_previous_stage) {
777 // First 6 system regs
778 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
779 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
780 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
781
782 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
783 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
784 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
785
786 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
787 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
788 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
789
790 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
791 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
792 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
793 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
794 if (ctx->shader_info->info.needs_multiview_view_index)
795 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
796
797 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
798 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
799 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
800 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
801 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
802 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
803 } else {
804 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
805 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
806 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
807 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
808 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
809 if (ctx->shader_info->info.needs_multiview_view_index)
810 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
811 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
812 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
813 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
814 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
815 }
816 break;
817 case MESA_SHADER_TESS_EVAL:
818 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
819 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
820 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
821 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
822 if (ctx->options->key.tes.as_es) {
823 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
824 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
825 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
826 } else {
827 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
828 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
829 }
830 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
831 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
832 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
833 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
834 break;
835 case MESA_SHADER_GEOMETRY:
836 if (has_previous_stage) {
837 // First 6 system regs
838 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // tess factor offset
839 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
840 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
841
842 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
843 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
844 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
845
846 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
847 if (previous_stage == MESA_SHADER_TESS_EVAL)
848 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
849 else
850 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
851 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
852 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
853 if (ctx->shader_info->info.needs_multiview_view_index)
854 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
855
856 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx01
857 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]); // vtx23
858 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_prim_id); // prim id
859 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_invocation_id);
860 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
861
862 if (previous_stage == MESA_SHADER_VERTEX) {
863 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
864 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
865 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
866 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
867 } else {
868 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
869 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
870 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
871 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
872 }
873 } else {
874 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
875 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
876 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
877 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
878 if (ctx->shader_info->info.needs_multiview_view_index)
879 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
880 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // gs2vs offset
881 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs_wave_id); // wave id
882 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx0
883 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[1]); // vtx1
884 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_prim_id); // prim id
885 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]);
886 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[3]);
887 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
888 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[5]);
889 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_invocation_id);
890 }
891 break;
892 case MESA_SHADER_FRAGMENT:
893 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
894 if (ctx->shader_info->info.ps.needs_sample_positions)
895 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->sample_pos_offset); /* sample position offset */
896 add_sgpr_argument(&args, ctx->ac.i32, &ctx->prim_mask); /* prim mask */
897 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_sample); /* persp sample */
898 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_center); /* persp center */
899 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_centroid); /* persp centroid */
900 add_vgpr_argument(&args, ctx->ac.v3i32, NULL); /* persp pull model */
901 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_sample); /* linear sample */
902 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_center); /* linear center */
903 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_centroid); /* linear centroid */
904 add_vgpr_argument(&args, ctx->ac.f32, NULL); /* line stipple tex */
905 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[0]); /* pos x float */
906 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[1]); /* pos y float */
907 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[2]); /* pos z float */
908 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[3]); /* pos w float */
909 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.front_face); /* front face */
910 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.ancillary); /* ancillary */
911 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.sample_coverage); /* sample coverage */
912 add_vgpr_argument(&args, ctx->ac.i32, NULL); /* fixed pt */
913 break;
914 default:
915 unreachable("Shader stage not implemented");
916 }
917
918 ctx->main_function = create_llvm_function(
919 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
920 ctx->max_workgroup_size,
921 ctx->options->unsafe_math);
922 set_llvm_calling_convention(ctx->main_function, stage);
923
924
925 ctx->shader_info->num_input_vgprs = 0;
926 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
927
928 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
929
930 if (ctx->stage != MESA_SHADER_FRAGMENT)
931 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
932
933 assign_arguments(ctx->main_function, &args);
934
935 user_sgpr_idx = 0;
936
937 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
938 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
939 if (ctx->options->supports_spill) {
940 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
941 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
942 NULL, 0, AC_FUNC_ATTR_READNONE);
943 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
944 const_array(ctx->ac.v4i32, 16), "");
945 }
946 }
947
948 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
949 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
950 if (has_previous_stage)
951 user_sgpr_idx = 0;
952
953 radv_define_common_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, desc_sets, &user_sgpr_idx);
954
955 switch (stage) {
956 case MESA_SHADER_COMPUTE:
957 if (ctx->shader_info->info.cs.uses_grid_size) {
958 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE,
959 &user_sgpr_idx, 3);
960 }
961 break;
962 case MESA_SHADER_VERTEX:
963 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
964 if (ctx->view_index)
965 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
966 if (ctx->options->key.vs.as_ls) {
967 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
968 }
969 if (ctx->options->key.vs.as_ls)
970 ac_declare_lds_as_pointer(&ctx->ac);
971 break;
972 case MESA_SHADER_TESS_CTRL:
973 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
974 if (has_previous_stage)
975 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
976 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
977 if (ctx->view_index)
978 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
979 ac_declare_lds_as_pointer(&ctx->ac);
980 break;
981 case MESA_SHADER_TESS_EVAL:
982 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
983 if (ctx->view_index)
984 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
985 break;
986 case MESA_SHADER_GEOMETRY:
987 if (has_previous_stage) {
988 if (previous_stage == MESA_SHADER_VERTEX)
989 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
990 else
991 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
992 }
993 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
994 if (ctx->view_index)
995 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
996 if (has_previous_stage)
997 ac_declare_lds_as_pointer(&ctx->ac);
998 break;
999 case MESA_SHADER_FRAGMENT:
1000 if (ctx->shader_info->info.ps.needs_sample_positions) {
1001 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
1002 }
1003 break;
1004 default:
1005 unreachable("Shader stage not implemented");
1006 }
1007
1008 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1009 }
1010
1011 static int get_llvm_num_components(LLVMValueRef value)
1012 {
1013 LLVMTypeRef type = LLVMTypeOf(value);
1014 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1015 ? LLVMGetVectorSize(type)
1016 : 1;
1017 return num_components;
1018 }
1019
1020 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1021 LLVMValueRef value,
1022 int index)
1023 {
1024 int count = get_llvm_num_components(value);
1025
1026 if (count == 1)
1027 return value;
1028
1029 return LLVMBuildExtractElement(ac->builder, value,
1030 LLVMConstInt(ac->i32, index, false), "");
1031 }
1032
1033 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1034 LLVMValueRef value, unsigned count)
1035 {
1036 unsigned num_components = get_llvm_num_components(value);
1037 if (count == num_components)
1038 return value;
1039
1040 LLVMValueRef masks[] = {
1041 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1042 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1043
1044 if (count == 1)
1045 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1046 "");
1047
1048 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1049 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1050 }
1051
1052 static void
1053 build_store_values_extended(struct ac_llvm_context *ac,
1054 LLVMValueRef *values,
1055 unsigned value_count,
1056 unsigned value_stride,
1057 LLVMValueRef vec)
1058 {
1059 LLVMBuilderRef builder = ac->builder;
1060 unsigned i;
1061
1062 for (i = 0; i < value_count; i++) {
1063 LLVMValueRef ptr = values[i * value_stride];
1064 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1065 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1066 LLVMBuildStore(builder, value, ptr);
1067 }
1068 }
1069
1070 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1071 const nir_ssa_def *def)
1072 {
1073 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1074 if (def->num_components > 1) {
1075 type = LLVMVectorType(type, def->num_components);
1076 }
1077 return type;
1078 }
1079
1080 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1081 {
1082 assert(src.is_ssa);
1083 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1084 return (LLVMValueRef)entry->data;
1085 }
1086
1087
1088 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1089 const struct nir_block *b)
1090 {
1091 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1092 return (LLVMBasicBlockRef)entry->data;
1093 }
1094
1095 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1096 nir_alu_src src,
1097 unsigned num_components)
1098 {
1099 LLVMValueRef value = get_src(ctx, src.src);
1100 bool need_swizzle = false;
1101
1102 assert(value);
1103 LLVMTypeRef type = LLVMTypeOf(value);
1104 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1105 ? LLVMGetVectorSize(type)
1106 : 1;
1107
1108 for (unsigned i = 0; i < num_components; ++i) {
1109 assert(src.swizzle[i] < src_components);
1110 if (src.swizzle[i] != i)
1111 need_swizzle = true;
1112 }
1113
1114 if (need_swizzle || num_components != src_components) {
1115 LLVMValueRef masks[] = {
1116 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1117 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1118 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1119 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1120
1121 if (src_components > 1 && num_components == 1) {
1122 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1123 masks[0], "");
1124 } else if (src_components == 1 && num_components > 1) {
1125 LLVMValueRef values[] = {value, value, value, value};
1126 value = ac_build_gather_values(&ctx->ac, values, num_components);
1127 } else {
1128 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1129 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1130 swizzle, "");
1131 }
1132 }
1133 assert(!src.negate);
1134 assert(!src.abs);
1135 return value;
1136 }
1137
1138 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1139 LLVMIntPredicate pred, LLVMValueRef src0,
1140 LLVMValueRef src1)
1141 {
1142 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1143 return LLVMBuildSelect(ctx->builder, result,
1144 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1145 ctx->i32_0, "");
1146 }
1147
1148 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1149 LLVMRealPredicate pred, LLVMValueRef src0,
1150 LLVMValueRef src1)
1151 {
1152 LLVMValueRef result;
1153 src0 = ac_to_float(ctx, src0);
1154 src1 = ac_to_float(ctx, src1);
1155 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1156 return LLVMBuildSelect(ctx->builder, result,
1157 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1158 ctx->i32_0, "");
1159 }
1160
1161 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1162 const char *intrin,
1163 LLVMTypeRef result_type,
1164 LLVMValueRef src0)
1165 {
1166 char name[64];
1167 LLVMValueRef params[] = {
1168 ac_to_float(ctx, src0),
1169 };
1170
1171 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1172 get_elem_bits(ctx, result_type));
1173 assert(length < sizeof(name));
1174 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1175 }
1176
1177 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1178 const char *intrin,
1179 LLVMTypeRef result_type,
1180 LLVMValueRef src0, LLVMValueRef src1)
1181 {
1182 char name[64];
1183 LLVMValueRef params[] = {
1184 ac_to_float(ctx, src0),
1185 ac_to_float(ctx, src1),
1186 };
1187
1188 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1189 get_elem_bits(ctx, result_type));
1190 assert(length < sizeof(name));
1191 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1192 }
1193
1194 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1195 const char *intrin,
1196 LLVMTypeRef result_type,
1197 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1198 {
1199 char name[64];
1200 LLVMValueRef params[] = {
1201 ac_to_float(ctx, src0),
1202 ac_to_float(ctx, src1),
1203 ac_to_float(ctx, src2),
1204 };
1205
1206 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1207 get_elem_bits(ctx, result_type));
1208 assert(length < sizeof(name));
1209 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1210 }
1211
1212 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1213 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1214 {
1215 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1216 ctx->i32_0, "");
1217 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1218 }
1219
1220 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1221 LLVMIntPredicate pred,
1222 LLVMValueRef src0, LLVMValueRef src1)
1223 {
1224 return LLVMBuildSelect(ctx->builder,
1225 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1226 src0,
1227 src1, "");
1228
1229 }
1230 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1231 LLVMValueRef src0)
1232 {
1233 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1234 LLVMBuildNeg(ctx->builder, src0, ""));
1235 }
1236
1237 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1238 LLVMValueRef src0)
1239 {
1240 LLVMValueRef cmp, val;
1241
1242 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1243 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1244 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1245 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1246 return val;
1247 }
1248
1249 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1250 LLVMValueRef src0)
1251 {
1252 LLVMValueRef cmp, val;
1253
1254 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1255 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1256 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1257 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1258 return val;
1259 }
1260
1261 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1262 LLVMValueRef src0)
1263 {
1264 const char *intr = "llvm.floor.f32";
1265 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1266 LLVMValueRef params[] = {
1267 fsrc0,
1268 };
1269 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1270 ctx->f32, params, 1,
1271 AC_FUNC_ATTR_READNONE);
1272 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1273 }
1274
1275 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1276 const char *intrin,
1277 LLVMValueRef src0, LLVMValueRef src1)
1278 {
1279 LLVMTypeRef ret_type;
1280 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1281 LLVMValueRef res;
1282 LLVMValueRef params[] = { src0, src1 };
1283 ret_type = LLVMStructTypeInContext(ctx->context, types,
1284 2, true);
1285
1286 res = ac_build_intrinsic(ctx, intrin, ret_type,
1287 params, 2, AC_FUNC_ATTR_READNONE);
1288
1289 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1290 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1291 return res;
1292 }
1293
1294 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1295 LLVMValueRef src0)
1296 {
1297 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1298 }
1299
1300 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1301 LLVMValueRef src0)
1302 {
1303 src0 = ac_to_float(ctx, src0);
1304 return LLVMBuildSExt(ctx->builder,
1305 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1306 ctx->i32, "");
1307 }
1308
1309 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1310 LLVMValueRef src0)
1311 {
1312 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1313 }
1314
1315 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1316 LLVMValueRef src0)
1317 {
1318 return LLVMBuildSExt(ctx->builder,
1319 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1320 ctx->i32, "");
1321 }
1322
1323 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1324 LLVMValueRef src0)
1325 {
1326 LLVMValueRef result;
1327 LLVMValueRef cond = NULL;
1328
1329 src0 = ac_to_float(&ctx->ac, src0);
1330 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1331
1332 if (ctx->options->chip_class >= VI) {
1333 LLVMValueRef args[2];
1334 /* Check if the result is a denormal - and flush to 0 if so. */
1335 args[0] = result;
1336 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1337 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1338 }
1339
1340 /* need to convert back up to f32 */
1341 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1342
1343 if (ctx->options->chip_class >= VI)
1344 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1345 else {
1346 /* for SI/CIK */
1347 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1348 * so compare the result and flush to 0 if it's smaller.
1349 */
1350 LLVMValueRef temp, cond2;
1351 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1352 ctx->ac.f32, result);
1353 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1354 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1355 temp, "");
1356 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1357 temp, ctx->ac.f32_0, "");
1358 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1359 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1360 }
1361 return result;
1362 }
1363
1364 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1365 LLVMValueRef src0, LLVMValueRef src1)
1366 {
1367 LLVMValueRef dst64, result;
1368 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1369 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1370
1371 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1372 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1373 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1374 return result;
1375 }
1376
1377 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1378 LLVMValueRef src0, LLVMValueRef src1)
1379 {
1380 LLVMValueRef dst64, result;
1381 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1382 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1383
1384 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1385 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1386 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1387 return result;
1388 }
1389
1390 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1391 bool is_signed,
1392 const LLVMValueRef srcs[3])
1393 {
1394 LLVMValueRef result;
1395 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1396
1397 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1398 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1399 return result;
1400 }
1401
1402 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1403 LLVMValueRef src0, LLVMValueRef src1,
1404 LLVMValueRef src2, LLVMValueRef src3)
1405 {
1406 LLVMValueRef bfi_args[3], result;
1407
1408 bfi_args[0] = LLVMBuildShl(ctx->builder,
1409 LLVMBuildSub(ctx->builder,
1410 LLVMBuildShl(ctx->builder,
1411 ctx->i32_1,
1412 src3, ""),
1413 ctx->i32_1, ""),
1414 src2, "");
1415 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1416 bfi_args[2] = src0;
1417
1418 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1419
1420 /* Calculate:
1421 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1422 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1423 */
1424 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1425 LLVMBuildAnd(ctx->builder, bfi_args[0],
1426 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1427
1428 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1429 return result;
1430 }
1431
1432 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1433 LLVMValueRef src0)
1434 {
1435 LLVMValueRef comp[2];
1436
1437 src0 = ac_to_float(ctx, src0);
1438 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1439 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1440
1441 return ac_build_cvt_pkrtz_f16(ctx, comp);
1442 }
1443
1444 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1445 LLVMValueRef src0)
1446 {
1447 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1448 LLVMValueRef temps[2], result, val;
1449 int i;
1450
1451 for (i = 0; i < 2; i++) {
1452 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1453 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1454 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1455 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1456 }
1457
1458 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1459 ctx->i32_0, "");
1460 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1461 ctx->i32_1, "");
1462 return result;
1463 }
1464
1465 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1466 nir_op op,
1467 LLVMValueRef src0)
1468 {
1469 unsigned mask;
1470 int idx;
1471 LLVMValueRef result;
1472
1473 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1474 mask = AC_TID_MASK_LEFT;
1475 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1476 mask = AC_TID_MASK_TOP;
1477 else
1478 mask = AC_TID_MASK_TOP_LEFT;
1479
1480 /* for DDX we want to next X pixel, DDY next Y pixel. */
1481 if (op == nir_op_fddx_fine ||
1482 op == nir_op_fddx_coarse ||
1483 op == nir_op_fddx)
1484 idx = 1;
1485 else
1486 idx = 2;
1487
1488 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1489 return result;
1490 }
1491
1492 /*
1493 * this takes an I,J coordinate pair,
1494 * and works out the X and Y derivatives.
1495 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1496 */
1497 static LLVMValueRef emit_ddxy_interp(
1498 struct ac_nir_context *ctx,
1499 LLVMValueRef interp_ij)
1500 {
1501 LLVMValueRef result[4], a;
1502 unsigned i;
1503
1504 for (i = 0; i < 2; i++) {
1505 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1506 LLVMConstInt(ctx->ac.i32, i, false), "");
1507 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1508 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1509 }
1510 return ac_build_gather_values(&ctx->ac, result, 4);
1511 }
1512
1513 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1514 {
1515 LLVMValueRef src[4], result = NULL;
1516 unsigned num_components = instr->dest.dest.ssa.num_components;
1517 unsigned src_components;
1518 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1519
1520 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1521 switch (instr->op) {
1522 case nir_op_vec2:
1523 case nir_op_vec3:
1524 case nir_op_vec4:
1525 src_components = 1;
1526 break;
1527 case nir_op_pack_half_2x16:
1528 src_components = 2;
1529 break;
1530 case nir_op_unpack_half_2x16:
1531 src_components = 1;
1532 break;
1533 default:
1534 src_components = num_components;
1535 break;
1536 }
1537 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1538 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1539
1540 switch (instr->op) {
1541 case nir_op_fmov:
1542 case nir_op_imov:
1543 result = src[0];
1544 break;
1545 case nir_op_fneg:
1546 src[0] = ac_to_float(&ctx->ac, src[0]);
1547 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1548 break;
1549 case nir_op_ineg:
1550 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1551 break;
1552 case nir_op_inot:
1553 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1554 break;
1555 case nir_op_iadd:
1556 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1557 break;
1558 case nir_op_fadd:
1559 src[0] = ac_to_float(&ctx->ac, src[0]);
1560 src[1] = ac_to_float(&ctx->ac, src[1]);
1561 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1562 break;
1563 case nir_op_fsub:
1564 src[0] = ac_to_float(&ctx->ac, src[0]);
1565 src[1] = ac_to_float(&ctx->ac, src[1]);
1566 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1567 break;
1568 case nir_op_isub:
1569 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1570 break;
1571 case nir_op_imul:
1572 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1573 break;
1574 case nir_op_imod:
1575 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1576 break;
1577 case nir_op_umod:
1578 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1579 break;
1580 case nir_op_fmod:
1581 src[0] = ac_to_float(&ctx->ac, src[0]);
1582 src[1] = ac_to_float(&ctx->ac, src[1]);
1583 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1584 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1585 ac_to_float_type(&ctx->ac, def_type), result);
1586 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1587 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1588 break;
1589 case nir_op_frem:
1590 src[0] = ac_to_float(&ctx->ac, src[0]);
1591 src[1] = ac_to_float(&ctx->ac, src[1]);
1592 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1593 break;
1594 case nir_op_irem:
1595 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1596 break;
1597 case nir_op_idiv:
1598 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1599 break;
1600 case nir_op_udiv:
1601 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1602 break;
1603 case nir_op_fmul:
1604 src[0] = ac_to_float(&ctx->ac, src[0]);
1605 src[1] = ac_to_float(&ctx->ac, src[1]);
1606 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1607 break;
1608 case nir_op_fdiv:
1609 src[0] = ac_to_float(&ctx->ac, src[0]);
1610 src[1] = ac_to_float(&ctx->ac, src[1]);
1611 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1612 break;
1613 case nir_op_frcp:
1614 src[0] = ac_to_float(&ctx->ac, src[0]);
1615 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1616 break;
1617 case nir_op_iand:
1618 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1619 break;
1620 case nir_op_ior:
1621 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1622 break;
1623 case nir_op_ixor:
1624 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1625 break;
1626 case nir_op_ishl:
1627 result = LLVMBuildShl(ctx->ac.builder, src[0],
1628 LLVMBuildZExt(ctx->ac.builder, src[1],
1629 LLVMTypeOf(src[0]), ""),
1630 "");
1631 break;
1632 case nir_op_ishr:
1633 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1634 LLVMBuildZExt(ctx->ac.builder, src[1],
1635 LLVMTypeOf(src[0]), ""),
1636 "");
1637 break;
1638 case nir_op_ushr:
1639 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1640 LLVMBuildZExt(ctx->ac.builder, src[1],
1641 LLVMTypeOf(src[0]), ""),
1642 "");
1643 break;
1644 case nir_op_ilt:
1645 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1646 break;
1647 case nir_op_ine:
1648 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1649 break;
1650 case nir_op_ieq:
1651 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1652 break;
1653 case nir_op_ige:
1654 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1655 break;
1656 case nir_op_ult:
1657 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1658 break;
1659 case nir_op_uge:
1660 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1661 break;
1662 case nir_op_feq:
1663 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1664 break;
1665 case nir_op_fne:
1666 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1667 break;
1668 case nir_op_flt:
1669 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1670 break;
1671 case nir_op_fge:
1672 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1673 break;
1674 case nir_op_fabs:
1675 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1676 ac_to_float_type(&ctx->ac, def_type), src[0]);
1677 break;
1678 case nir_op_iabs:
1679 result = emit_iabs(&ctx->ac, src[0]);
1680 break;
1681 case nir_op_imax:
1682 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1683 break;
1684 case nir_op_imin:
1685 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1686 break;
1687 case nir_op_umax:
1688 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1689 break;
1690 case nir_op_umin:
1691 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1692 break;
1693 case nir_op_isign:
1694 result = emit_isign(&ctx->ac, src[0]);
1695 break;
1696 case nir_op_fsign:
1697 src[0] = ac_to_float(&ctx->ac, src[0]);
1698 result = emit_fsign(&ctx->ac, src[0]);
1699 break;
1700 case nir_op_ffloor:
1701 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1702 ac_to_float_type(&ctx->ac, def_type), src[0]);
1703 break;
1704 case nir_op_ftrunc:
1705 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1706 ac_to_float_type(&ctx->ac, def_type), src[0]);
1707 break;
1708 case nir_op_fceil:
1709 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1710 ac_to_float_type(&ctx->ac, def_type), src[0]);
1711 break;
1712 case nir_op_fround_even:
1713 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1714 ac_to_float_type(&ctx->ac, def_type),src[0]);
1715 break;
1716 case nir_op_ffract:
1717 result = emit_ffract(&ctx->ac, src[0]);
1718 break;
1719 case nir_op_fsin:
1720 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1721 ac_to_float_type(&ctx->ac, def_type), src[0]);
1722 break;
1723 case nir_op_fcos:
1724 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1725 ac_to_float_type(&ctx->ac, def_type), src[0]);
1726 break;
1727 case nir_op_fsqrt:
1728 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1729 ac_to_float_type(&ctx->ac, def_type), src[0]);
1730 break;
1731 case nir_op_fexp2:
1732 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1733 ac_to_float_type(&ctx->ac, def_type), src[0]);
1734 break;
1735 case nir_op_flog2:
1736 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1737 ac_to_float_type(&ctx->ac, def_type), src[0]);
1738 break;
1739 case nir_op_frsq:
1740 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1741 ac_to_float_type(&ctx->ac, def_type), src[0]);
1742 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1743 break;
1744 case nir_op_fpow:
1745 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1746 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1747 break;
1748 case nir_op_fmax:
1749 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1750 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1751 if (instr->dest.dest.ssa.bit_size == 32)
1752 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1753 ac_to_float_type(&ctx->ac, def_type),
1754 result);
1755 break;
1756 case nir_op_fmin:
1757 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1758 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1759 if (instr->dest.dest.ssa.bit_size == 32)
1760 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1761 ac_to_float_type(&ctx->ac, def_type),
1762 result);
1763 break;
1764 case nir_op_ffma:
1765 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1766 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1767 break;
1768 case nir_op_ibitfield_extract:
1769 result = emit_bitfield_extract(&ctx->ac, true, src);
1770 break;
1771 case nir_op_ubitfield_extract:
1772 result = emit_bitfield_extract(&ctx->ac, false, src);
1773 break;
1774 case nir_op_bitfield_insert:
1775 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1776 break;
1777 case nir_op_bitfield_reverse:
1778 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1779 break;
1780 case nir_op_bit_count:
1781 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1782 break;
1783 case nir_op_vec2:
1784 case nir_op_vec3:
1785 case nir_op_vec4:
1786 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1787 src[i] = ac_to_integer(&ctx->ac, src[i]);
1788 result = ac_build_gather_values(&ctx->ac, src, num_components);
1789 break;
1790 case nir_op_f2i32:
1791 case nir_op_f2i64:
1792 src[0] = ac_to_float(&ctx->ac, src[0]);
1793 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1794 break;
1795 case nir_op_f2u32:
1796 case nir_op_f2u64:
1797 src[0] = ac_to_float(&ctx->ac, src[0]);
1798 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1799 break;
1800 case nir_op_i2f32:
1801 case nir_op_i2f64:
1802 src[0] = ac_to_integer(&ctx->ac, src[0]);
1803 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1804 break;
1805 case nir_op_u2f32:
1806 case nir_op_u2f64:
1807 src[0] = ac_to_integer(&ctx->ac, src[0]);
1808 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1809 break;
1810 case nir_op_f2f64:
1811 src[0] = ac_to_float(&ctx->ac, src[0]);
1812 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1813 break;
1814 case nir_op_f2f32:
1815 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1816 break;
1817 case nir_op_u2u32:
1818 case nir_op_u2u64:
1819 src[0] = ac_to_integer(&ctx->ac, src[0]);
1820 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1821 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1822 else
1823 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1824 break;
1825 case nir_op_i2i32:
1826 case nir_op_i2i64:
1827 src[0] = ac_to_integer(&ctx->ac, src[0]);
1828 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1829 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1830 else
1831 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1832 break;
1833 case nir_op_bcsel:
1834 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1835 break;
1836 case nir_op_find_lsb:
1837 src[0] = ac_to_integer(&ctx->ac, src[0]);
1838 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1839 break;
1840 case nir_op_ufind_msb:
1841 src[0] = ac_to_integer(&ctx->ac, src[0]);
1842 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1843 break;
1844 case nir_op_ifind_msb:
1845 src[0] = ac_to_integer(&ctx->ac, src[0]);
1846 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1847 break;
1848 case nir_op_uadd_carry:
1849 src[0] = ac_to_integer(&ctx->ac, src[0]);
1850 src[1] = ac_to_integer(&ctx->ac, src[1]);
1851 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1852 break;
1853 case nir_op_usub_borrow:
1854 src[0] = ac_to_integer(&ctx->ac, src[0]);
1855 src[1] = ac_to_integer(&ctx->ac, src[1]);
1856 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1857 break;
1858 case nir_op_b2f:
1859 result = emit_b2f(&ctx->ac, src[0]);
1860 break;
1861 case nir_op_f2b:
1862 result = emit_f2b(&ctx->ac, src[0]);
1863 break;
1864 case nir_op_b2i:
1865 result = emit_b2i(&ctx->ac, src[0]);
1866 break;
1867 case nir_op_i2b:
1868 src[0] = ac_to_integer(&ctx->ac, src[0]);
1869 result = emit_i2b(&ctx->ac, src[0]);
1870 break;
1871 case nir_op_fquantize2f16:
1872 result = emit_f2f16(ctx->nctx, src[0]);
1873 break;
1874 case nir_op_umul_high:
1875 src[0] = ac_to_integer(&ctx->ac, src[0]);
1876 src[1] = ac_to_integer(&ctx->ac, src[1]);
1877 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1878 break;
1879 case nir_op_imul_high:
1880 src[0] = ac_to_integer(&ctx->ac, src[0]);
1881 src[1] = ac_to_integer(&ctx->ac, src[1]);
1882 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1883 break;
1884 case nir_op_pack_half_2x16:
1885 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1886 break;
1887 case nir_op_unpack_half_2x16:
1888 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1889 break;
1890 case nir_op_fddx:
1891 case nir_op_fddy:
1892 case nir_op_fddx_fine:
1893 case nir_op_fddy_fine:
1894 case nir_op_fddx_coarse:
1895 case nir_op_fddy_coarse:
1896 result = emit_ddxy(ctx, instr->op, src[0]);
1897 break;
1898
1899 case nir_op_unpack_64_2x32_split_x: {
1900 assert(instr->src[0].src.ssa->num_components == 1);
1901 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1902 ctx->ac.v2i32,
1903 "");
1904 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1905 ctx->ac.i32_0, "");
1906 break;
1907 }
1908
1909 case nir_op_unpack_64_2x32_split_y: {
1910 assert(instr->src[0].src.ssa->num_components == 1);
1911 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1912 ctx->ac.v2i32,
1913 "");
1914 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1915 ctx->ac.i32_1, "");
1916 break;
1917 }
1918
1919 case nir_op_pack_64_2x32_split: {
1920 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
1921 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1922 src[0], ctx->ac.i32_0, "");
1923 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1924 src[1], ctx->ac.i32_1, "");
1925 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1926 break;
1927 }
1928
1929 default:
1930 fprintf(stderr, "Unknown NIR alu instr: ");
1931 nir_print_instr(&instr->instr, stderr);
1932 fprintf(stderr, "\n");
1933 abort();
1934 }
1935
1936 if (result) {
1937 assert(instr->dest.dest.is_ssa);
1938 result = ac_to_integer(&ctx->ac, result);
1939 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1940 result);
1941 }
1942 }
1943
1944 static void visit_load_const(struct ac_nir_context *ctx,
1945 const nir_load_const_instr *instr)
1946 {
1947 LLVMValueRef values[4], value = NULL;
1948 LLVMTypeRef element_type =
1949 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1950
1951 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1952 switch (instr->def.bit_size) {
1953 case 32:
1954 values[i] = LLVMConstInt(element_type,
1955 instr->value.u32[i], false);
1956 break;
1957 case 64:
1958 values[i] = LLVMConstInt(element_type,
1959 instr->value.u64[i], false);
1960 break;
1961 default:
1962 fprintf(stderr,
1963 "unsupported nir load_const bit_size: %d\n",
1964 instr->def.bit_size);
1965 abort();
1966 }
1967 }
1968 if (instr->def.num_components > 1) {
1969 value = LLVMConstVector(values, instr->def.num_components);
1970 } else
1971 value = values[0];
1972
1973 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1974 }
1975
1976 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1977 LLVMTypeRef type)
1978 {
1979 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1980 return LLVMBuildBitCast(ctx->builder, ptr,
1981 LLVMPointerType(type, addr_space), "");
1982 }
1983
1984 static LLVMValueRef
1985 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1986 {
1987 LLVMValueRef size =
1988 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1989 LLVMConstInt(ctx->ac.i32, 2, false), "");
1990
1991 /* VI only */
1992 if (ctx->ac.chip_class == VI && in_elements) {
1993 /* On VI, the descriptor contains the size in bytes,
1994 * but TXQ must return the size in elements.
1995 * The stride is always non-zero for resources using TXQ.
1996 */
1997 LLVMValueRef stride =
1998 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1999 ctx->ac.i32_1, "");
2000 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2001 LLVMConstInt(ctx->ac.i32, 16, false), "");
2002 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2003 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2004
2005 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2006 }
2007 return size;
2008 }
2009
2010 /**
2011 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2012 * intrinsic names).
2013 */
2014 static void build_int_type_name(
2015 LLVMTypeRef type,
2016 char *buf, unsigned bufsize)
2017 {
2018 assert(bufsize >= 6);
2019
2020 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2021 snprintf(buf, bufsize, "v%ui32",
2022 LLVMGetVectorSize(type));
2023 else
2024 strcpy(buf, "i32");
2025 }
2026
2027 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2028 struct ac_image_args *args,
2029 const nir_tex_instr *instr)
2030 {
2031 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2032 LLVMValueRef coord = args->addr;
2033 LLVMValueRef half_texel[2];
2034 LLVMValueRef compare_cube_wa = NULL;
2035 LLVMValueRef result;
2036 int c;
2037 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2038
2039 //TODO Rect
2040 {
2041 struct ac_image_args txq_args = { 0 };
2042
2043 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2044 txq_args.opcode = ac_image_get_resinfo;
2045 txq_args.dmask = 0xf;
2046 txq_args.addr = ctx->i32_0;
2047 txq_args.resource = args->resource;
2048 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2049
2050 for (c = 0; c < 2; c++) {
2051 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2052 LLVMConstInt(ctx->i32, c, false), "");
2053 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2054 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2055 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2056 LLVMConstReal(ctx->f32, -0.5), "");
2057 }
2058 }
2059
2060 LLVMValueRef orig_coords = args->addr;
2061
2062 for (c = 0; c < 2; c++) {
2063 LLVMValueRef tmp;
2064 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2065 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2066 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2067 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2068 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2069 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2070 }
2071
2072
2073 /*
2074 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2075 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2076 * workaround by sampling using a scaled type and converting.
2077 * This is taken from amdgpu-pro shaders.
2078 */
2079 /* NOTE this produces some ugly code compared to amdgpu-pro,
2080 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2081 * and then reads them back. -pro generates two selects,
2082 * one s_cmp for the descriptor rewriting
2083 * one v_cmp for the coordinate and result changes.
2084 */
2085 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2086 LLVMValueRef tmp, tmp2;
2087
2088 /* workaround 8/8/8/8 uint/sint cube gather bug */
2089 /* first detect it then change to a scaled read and f2i */
2090 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2091 tmp2 = tmp;
2092
2093 /* extract the DATA_FORMAT */
2094 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2095 LLVMConstInt(ctx->i32, 6, false), false);
2096
2097 /* is the DATA_FORMAT == 8_8_8_8 */
2098 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2099
2100 if (stype == GLSL_TYPE_UINT)
2101 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2102 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2103 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2104 else
2105 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2106 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2107 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2108
2109 /* replace the NUM FORMAT in the descriptor */
2110 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2111 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2112
2113 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2114
2115 /* don't modify the coordinates for this case */
2116 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2117 }
2118 args->addr = coord;
2119 result = ac_build_image_opcode(ctx, args);
2120
2121 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2122 LLVMValueRef tmp, tmp2;
2123
2124 /* if the cube workaround is in place, f2i the result. */
2125 for (c = 0; c < 4; c++) {
2126 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2127 if (stype == GLSL_TYPE_UINT)
2128 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2129 else
2130 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2131 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2132 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2133 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2134 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2135 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2136 }
2137 }
2138 return result;
2139 }
2140
2141 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2142 const nir_tex_instr *instr,
2143 bool lod_is_zero,
2144 struct ac_image_args *args)
2145 {
2146 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2147 return ac_build_buffer_load_format(&ctx->ac,
2148 args->resource,
2149 args->addr,
2150 ctx->ac.i32_0,
2151 true);
2152 }
2153
2154 args->opcode = ac_image_sample;
2155 args->compare = instr->is_shadow;
2156
2157 switch (instr->op) {
2158 case nir_texop_txf:
2159 case nir_texop_txf_ms:
2160 case nir_texop_samples_identical:
2161 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2162 args->compare = false;
2163 args->offset = false;
2164 break;
2165 case nir_texop_txb:
2166 args->bias = true;
2167 break;
2168 case nir_texop_txl:
2169 if (lod_is_zero)
2170 args->level_zero = true;
2171 else
2172 args->lod = true;
2173 break;
2174 case nir_texop_txs:
2175 case nir_texop_query_levels:
2176 args->opcode = ac_image_get_resinfo;
2177 break;
2178 case nir_texop_tex:
2179 if (ctx->stage != MESA_SHADER_FRAGMENT)
2180 args->level_zero = true;
2181 break;
2182 case nir_texop_txd:
2183 args->deriv = true;
2184 break;
2185 case nir_texop_tg4:
2186 args->opcode = ac_image_gather4;
2187 args->level_zero = true;
2188 break;
2189 case nir_texop_lod:
2190 args->opcode = ac_image_get_lod;
2191 args->compare = false;
2192 args->offset = false;
2193 break;
2194 default:
2195 break;
2196 }
2197
2198 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2199 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2200 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2201 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2202 }
2203 }
2204 return ac_build_image_opcode(&ctx->ac, args);
2205 }
2206
2207 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2208 nir_intrinsic_instr *instr)
2209 {
2210 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2211 unsigned desc_set = nir_intrinsic_desc_set(instr);
2212 unsigned binding = nir_intrinsic_binding(instr);
2213 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2214 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2215 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2216 unsigned base_offset = layout->binding[binding].offset;
2217 LLVMValueRef offset, stride;
2218
2219 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2220 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2221 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2222 layout->binding[binding].dynamic_offset_offset;
2223 desc_ptr = ctx->push_constants;
2224 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2225 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2226 } else
2227 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2228
2229 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2230 index = LLVMBuildMul(ctx->builder, index, stride, "");
2231 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2232
2233 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2234 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2235 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2236
2237 return desc_ptr;
2238 }
2239
2240 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2241 nir_intrinsic_instr *instr)
2242 {
2243 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2244 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2245
2246 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2247 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2248 return result;
2249 }
2250
2251 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2252 nir_intrinsic_instr *instr)
2253 {
2254 LLVMValueRef ptr, addr;
2255
2256 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2257 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2258
2259 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2260 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2261
2262 return LLVMBuildLoad(ctx->builder, ptr, "");
2263 }
2264
2265 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2266 const nir_intrinsic_instr *instr)
2267 {
2268 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2269
2270 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2271 }
2272 static void visit_store_ssbo(struct ac_nir_context *ctx,
2273 nir_intrinsic_instr *instr)
2274 {
2275 const char *store_name;
2276 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2277 LLVMTypeRef data_type = ctx->ac.f32;
2278 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2279 int components_32bit = elem_size_mult * instr->num_components;
2280 unsigned writemask = nir_intrinsic_write_mask(instr);
2281 LLVMValueRef base_data, base_offset;
2282 LLVMValueRef params[6];
2283
2284 params[1] = ctx->abi->load_ssbo(ctx->abi,
2285 get_src(ctx, instr->src[1]), true);
2286 params[2] = ctx->ac.i32_0; /* vindex */
2287 params[4] = ctx->ac.i1false; /* glc */
2288 params[5] = ctx->ac.i1false; /* slc */
2289
2290 if (components_32bit > 1)
2291 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2292
2293 base_data = ac_to_float(&ctx->ac, src_data);
2294 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2295 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2296 data_type, "");
2297 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2298 while (writemask) {
2299 int start, count;
2300 LLVMValueRef data;
2301 LLVMValueRef offset;
2302 LLVMValueRef tmp;
2303 u_bit_scan_consecutive_range(&writemask, &start, &count);
2304
2305 /* Due to an LLVM limitation, split 3-element writes
2306 * into a 2-element and a 1-element write. */
2307 if (count == 3) {
2308 writemask |= 1 << (start + 2);
2309 count = 2;
2310 }
2311
2312 start *= elem_size_mult;
2313 count *= elem_size_mult;
2314
2315 if (count > 4) {
2316 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2317 count = 4;
2318 }
2319
2320 if (count == 4) {
2321 store_name = "llvm.amdgcn.buffer.store.v4f32";
2322 data = base_data;
2323 } else if (count == 2) {
2324 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2325 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2326 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2327 ctx->ac.i32_0, "");
2328
2329 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2330 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2331 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2332 ctx->ac.i32_1, "");
2333 store_name = "llvm.amdgcn.buffer.store.v2f32";
2334
2335 } else {
2336 assert(count == 1);
2337 if (get_llvm_num_components(base_data) > 1)
2338 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2339 LLVMConstInt(ctx->ac.i32, start, false), "");
2340 else
2341 data = base_data;
2342 store_name = "llvm.amdgcn.buffer.store.f32";
2343 }
2344
2345 offset = base_offset;
2346 if (start != 0) {
2347 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2348 }
2349 params[0] = data;
2350 params[3] = offset;
2351 ac_build_intrinsic(&ctx->ac, store_name,
2352 ctx->ac.voidt, params, 6, 0);
2353 }
2354 }
2355
2356 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2357 const nir_intrinsic_instr *instr)
2358 {
2359 const char *name;
2360 LLVMValueRef params[6];
2361 int arg_count = 0;
2362
2363 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2364 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2365 }
2366 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2367 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2368 get_src(ctx, instr->src[0]),
2369 true);
2370 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2371 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2372 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2373
2374 switch (instr->intrinsic) {
2375 case nir_intrinsic_ssbo_atomic_add:
2376 name = "llvm.amdgcn.buffer.atomic.add";
2377 break;
2378 case nir_intrinsic_ssbo_atomic_imin:
2379 name = "llvm.amdgcn.buffer.atomic.smin";
2380 break;
2381 case nir_intrinsic_ssbo_atomic_umin:
2382 name = "llvm.amdgcn.buffer.atomic.umin";
2383 break;
2384 case nir_intrinsic_ssbo_atomic_imax:
2385 name = "llvm.amdgcn.buffer.atomic.smax";
2386 break;
2387 case nir_intrinsic_ssbo_atomic_umax:
2388 name = "llvm.amdgcn.buffer.atomic.umax";
2389 break;
2390 case nir_intrinsic_ssbo_atomic_and:
2391 name = "llvm.amdgcn.buffer.atomic.and";
2392 break;
2393 case nir_intrinsic_ssbo_atomic_or:
2394 name = "llvm.amdgcn.buffer.atomic.or";
2395 break;
2396 case nir_intrinsic_ssbo_atomic_xor:
2397 name = "llvm.amdgcn.buffer.atomic.xor";
2398 break;
2399 case nir_intrinsic_ssbo_atomic_exchange:
2400 name = "llvm.amdgcn.buffer.atomic.swap";
2401 break;
2402 case nir_intrinsic_ssbo_atomic_comp_swap:
2403 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2404 break;
2405 default:
2406 abort();
2407 }
2408
2409 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2410 }
2411
2412 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2413 const nir_intrinsic_instr *instr)
2414 {
2415 LLVMValueRef results[2];
2416 int load_components;
2417 int num_components = instr->num_components;
2418 if (instr->dest.ssa.bit_size == 64)
2419 num_components *= 2;
2420
2421 for (int i = 0; i < num_components; i += load_components) {
2422 load_components = MIN2(num_components - i, 4);
2423 const char *load_name;
2424 LLVMTypeRef data_type = ctx->ac.f32;
2425 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2426 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2427
2428 if (load_components == 3)
2429 data_type = LLVMVectorType(ctx->ac.f32, 4);
2430 else if (load_components > 1)
2431 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2432
2433 if (load_components >= 3)
2434 load_name = "llvm.amdgcn.buffer.load.v4f32";
2435 else if (load_components == 2)
2436 load_name = "llvm.amdgcn.buffer.load.v2f32";
2437 else if (load_components == 1)
2438 load_name = "llvm.amdgcn.buffer.load.f32";
2439 else
2440 unreachable("unhandled number of components");
2441
2442 LLVMValueRef params[] = {
2443 ctx->abi->load_ssbo(ctx->abi,
2444 get_src(ctx, instr->src[0]),
2445 false),
2446 ctx->ac.i32_0,
2447 offset,
2448 ctx->ac.i1false,
2449 ctx->ac.i1false,
2450 };
2451
2452 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2453
2454 }
2455
2456 assume(results[0]);
2457 LLVMValueRef ret = results[0];
2458 if (num_components > 4 || num_components == 3) {
2459 LLVMValueRef masks[] = {
2460 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2461 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2462 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2463 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2464 };
2465
2466 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2467 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2468 results[num_components > 4 ? 1 : 0], swizzle, "");
2469 }
2470
2471 return LLVMBuildBitCast(ctx->ac.builder, ret,
2472 get_def_type(ctx, &instr->dest.ssa), "");
2473 }
2474
2475 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2476 const nir_intrinsic_instr *instr)
2477 {
2478 LLVMValueRef results[8], ret;
2479 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2480 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2481 int num_components = instr->num_components;
2482
2483 if (ctx->abi->load_ubo)
2484 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2485
2486 if (instr->dest.ssa.bit_size == 64)
2487 num_components *= 2;
2488
2489 for (unsigned i = 0; i < num_components; ++i) {
2490 LLVMValueRef params[] = {
2491 rsrc,
2492 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2493 offset, "")
2494 };
2495 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2496 params, 2,
2497 AC_FUNC_ATTR_READNONE |
2498 AC_FUNC_ATTR_LEGACY);
2499 }
2500
2501
2502 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2503 return LLVMBuildBitCast(ctx->ac.builder, ret,
2504 get_def_type(ctx, &instr->dest.ssa), "");
2505 }
2506
2507 static void
2508 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2509 bool vs_in, unsigned *vertex_index_out,
2510 LLVMValueRef *vertex_index_ref,
2511 unsigned *const_out, LLVMValueRef *indir_out)
2512 {
2513 unsigned const_offset = 0;
2514 nir_deref *tail = &deref->deref;
2515 LLVMValueRef offset = NULL;
2516
2517 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2518 tail = tail->child;
2519 nir_deref_array *deref_array = nir_deref_as_array(tail);
2520 if (vertex_index_out)
2521 *vertex_index_out = deref_array->base_offset;
2522
2523 if (vertex_index_ref) {
2524 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2525 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2526 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2527 }
2528 *vertex_index_ref = vtx;
2529 }
2530 }
2531
2532 if (deref->var->data.compact) {
2533 assert(tail->child->deref_type == nir_deref_type_array);
2534 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2535 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2536 /* We always lower indirect dereferences for "compact" array vars. */
2537 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2538
2539 const_offset = deref_array->base_offset;
2540 goto out;
2541 }
2542
2543 while (tail->child != NULL) {
2544 const struct glsl_type *parent_type = tail->type;
2545 tail = tail->child;
2546
2547 if (tail->deref_type == nir_deref_type_array) {
2548 nir_deref_array *deref_array = nir_deref_as_array(tail);
2549 LLVMValueRef index, stride, local_offset;
2550 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2551
2552 const_offset += size * deref_array->base_offset;
2553 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2554 continue;
2555
2556 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2557 index = get_src(ctx, deref_array->indirect);
2558 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2559 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2560
2561 if (offset)
2562 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2563 else
2564 offset = local_offset;
2565 } else if (tail->deref_type == nir_deref_type_struct) {
2566 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2567
2568 for (unsigned i = 0; i < deref_struct->index; i++) {
2569 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2570 const_offset += glsl_count_attribute_slots(ft, vs_in);
2571 }
2572 } else
2573 unreachable("unsupported deref type");
2574
2575 }
2576 out:
2577 if (const_offset && offset)
2578 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2579 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2580 "");
2581
2582 *const_out = const_offset;
2583 *indir_out = offset;
2584 }
2585
2586
2587 /* The offchip buffer layout for TCS->TES is
2588 *
2589 * - attribute 0 of patch 0 vertex 0
2590 * - attribute 0 of patch 0 vertex 1
2591 * - attribute 0 of patch 0 vertex 2
2592 * ...
2593 * - attribute 0 of patch 1 vertex 0
2594 * - attribute 0 of patch 1 vertex 1
2595 * ...
2596 * - attribute 1 of patch 0 vertex 0
2597 * - attribute 1 of patch 0 vertex 1
2598 * ...
2599 * - per patch attribute 0 of patch 0
2600 * - per patch attribute 0 of patch 1
2601 * ...
2602 *
2603 * Note that every attribute has 4 components.
2604 */
2605 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2606 LLVMValueRef vertex_index,
2607 LLVMValueRef param_index)
2608 {
2609 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2610 LLVMValueRef param_stride, constant16;
2611 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2612
2613 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2614 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2615 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2616 num_patches, "");
2617
2618 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2619 if (vertex_index) {
2620 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2621 vertices_per_patch, "");
2622
2623 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2624 vertex_index, "");
2625
2626 param_stride = total_vertices;
2627 } else {
2628 base_addr = rel_patch_id;
2629 param_stride = num_patches;
2630 }
2631
2632 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2633 LLVMBuildMul(ctx->builder, param_index,
2634 param_stride, ""), "");
2635
2636 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2637
2638 if (!vertex_index) {
2639 LLVMValueRef patch_data_offset =
2640 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2641
2642 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2643 patch_data_offset, "");
2644 }
2645 return base_addr;
2646 }
2647
2648 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2649 unsigned param,
2650 unsigned const_index,
2651 bool is_compact,
2652 LLVMValueRef vertex_index,
2653 LLVMValueRef indir_index)
2654 {
2655 LLVMValueRef param_index;
2656
2657 if (indir_index)
2658 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2659 indir_index, "");
2660 else {
2661 if (const_index && !is_compact)
2662 param += const_index;
2663 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2664 }
2665 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2666 }
2667
2668 static void
2669 mark_tess_output(struct nir_to_llvm_context *ctx,
2670 bool is_patch, uint32_t param)
2671
2672 {
2673 if (is_patch) {
2674 ctx->tess_patch_outputs_written |= (1ull << param);
2675 } else
2676 ctx->tess_outputs_written |= (1ull << param);
2677 }
2678
2679 static LLVMValueRef
2680 get_dw_address(struct nir_to_llvm_context *ctx,
2681 LLVMValueRef dw_addr,
2682 unsigned param,
2683 unsigned const_index,
2684 bool compact_const_index,
2685 LLVMValueRef vertex_index,
2686 LLVMValueRef stride,
2687 LLVMValueRef indir_index)
2688
2689 {
2690
2691 if (vertex_index) {
2692 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2693 LLVMBuildMul(ctx->builder,
2694 vertex_index,
2695 stride, ""), "");
2696 }
2697
2698 if (indir_index)
2699 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2700 LLVMBuildMul(ctx->builder, indir_index,
2701 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2702 else if (const_index && !compact_const_index)
2703 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2704 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2705
2706 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2707 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2708
2709 if (const_index && compact_const_index)
2710 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2711 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2712 return dw_addr;
2713 }
2714
2715 static LLVMValueRef
2716 load_tcs_input(struct nir_to_llvm_context *ctx,
2717 nir_intrinsic_instr *instr)
2718 {
2719 LLVMValueRef dw_addr, stride;
2720 unsigned const_index;
2721 LLVMValueRef vertex_index;
2722 LLVMValueRef indir_index;
2723 unsigned param;
2724 LLVMValueRef value[4], result;
2725 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2726 const bool is_compact = instr->variables[0]->var->data.compact;
2727 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2728 get_deref_offset(ctx->nir, instr->variables[0],
2729 false, NULL, per_vertex ? &vertex_index : NULL,
2730 &const_index, &indir_index);
2731
2732 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2733 dw_addr = get_tcs_in_current_patch_offset(ctx);
2734 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2735 indir_index);
2736
2737 unsigned comp = instr->variables[0]->var->data.location_frac;
2738 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2739 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2740 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2741 ctx->ac.i32_1, "");
2742 }
2743 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2744 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2745 return result;
2746 }
2747
2748 static LLVMValueRef
2749 load_tcs_output(struct nir_to_llvm_context *ctx,
2750 nir_intrinsic_instr *instr)
2751 {
2752 LLVMValueRef dw_addr;
2753 LLVMValueRef stride = NULL;
2754 LLVMValueRef value[4], result;
2755 LLVMValueRef vertex_index = NULL;
2756 LLVMValueRef indir_index = NULL;
2757 unsigned const_index = 0;
2758 unsigned param;
2759 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2760 const bool is_compact = instr->variables[0]->var->data.compact;
2761 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2762 get_deref_offset(ctx->nir, instr->variables[0],
2763 false, NULL, per_vertex ? &vertex_index : NULL,
2764 &const_index, &indir_index);
2765
2766 if (!instr->variables[0]->var->data.patch) {
2767 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2768 dw_addr = get_tcs_out_current_patch_offset(ctx);
2769 } else {
2770 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2771 }
2772
2773 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2774 indir_index);
2775
2776 unsigned comp = instr->variables[0]->var->data.location_frac;
2777 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2778 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2779 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2780 ctx->ac.i32_1, "");
2781 }
2782 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2783 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2784 return result;
2785 }
2786
2787 static void
2788 store_tcs_output(struct nir_to_llvm_context *ctx,
2789 nir_intrinsic_instr *instr,
2790 LLVMValueRef src,
2791 unsigned writemask)
2792 {
2793 LLVMValueRef dw_addr;
2794 LLVMValueRef stride = NULL;
2795 LLVMValueRef buf_addr = NULL;
2796 LLVMValueRef vertex_index = NULL;
2797 LLVMValueRef indir_index = NULL;
2798 unsigned const_index = 0;
2799 unsigned param;
2800 const unsigned comp = instr->variables[0]->var->data.location_frac;
2801 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2802 const bool is_compact = instr->variables[0]->var->data.compact;
2803 bool store_lds = true;
2804
2805 if (instr->variables[0]->var->data.patch) {
2806 if (!(ctx->tcs_patch_outputs_read & (1U << instr->variables[0]->var->data.location)))
2807 store_lds = false;
2808 } else {
2809 if (!(ctx->tcs_outputs_read & (1ULL << instr->variables[0]->var->data.location)))
2810 store_lds = false;
2811 }
2812 get_deref_offset(ctx->nir, instr->variables[0],
2813 false, NULL, per_vertex ? &vertex_index : NULL,
2814 &const_index, &indir_index);
2815
2816 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2817 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2818 is_compact && const_index > 3) {
2819 const_index -= 3;
2820 param++;
2821 }
2822
2823 if (!instr->variables[0]->var->data.patch) {
2824 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2825 dw_addr = get_tcs_out_current_patch_offset(ctx);
2826 } else {
2827 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2828 }
2829
2830 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2831
2832 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2833 indir_index);
2834 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2835 vertex_index, indir_index);
2836
2837 bool is_tess_factor = false;
2838 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2839 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2840 is_tess_factor = true;
2841
2842 unsigned base = is_compact ? const_index : 0;
2843 for (unsigned chan = 0; chan < 8; chan++) {
2844 if (!(writemask & (1 << chan)))
2845 continue;
2846 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2847
2848 if (store_lds || is_tess_factor)
2849 ac_lds_store(&ctx->ac, dw_addr, value);
2850
2851 if (!is_tess_factor && writemask != 0xF)
2852 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2853 buf_addr, ctx->oc_lds,
2854 4 * (base + chan), 1, 0, true, false);
2855
2856 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2857 ctx->ac.i32_1, "");
2858 }
2859
2860 if (writemask == 0xF) {
2861 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2862 buf_addr, ctx->oc_lds,
2863 (base * 4), 1, 0, true, false);
2864 }
2865 }
2866
2867 static LLVMValueRef
2868 load_tes_input(struct nir_to_llvm_context *ctx,
2869 const nir_intrinsic_instr *instr)
2870 {
2871 LLVMValueRef buf_addr;
2872 LLVMValueRef result;
2873 LLVMValueRef vertex_index = NULL;
2874 LLVMValueRef indir_index = NULL;
2875 unsigned const_index = 0;
2876 unsigned param;
2877 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2878 const bool is_compact = instr->variables[0]->var->data.compact;
2879
2880 get_deref_offset(ctx->nir, instr->variables[0],
2881 false, NULL, per_vertex ? &vertex_index : NULL,
2882 &const_index, &indir_index);
2883 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2884 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2885 is_compact && const_index > 3) {
2886 const_index -= 3;
2887 param++;
2888 }
2889
2890 unsigned comp = instr->variables[0]->var->data.location_frac;
2891 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2892 is_compact, vertex_index, indir_index);
2893
2894 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, comp * 4, false);
2895 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2896
2897 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2898 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2899 result = trim_vector(&ctx->ac, result, instr->num_components);
2900 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2901 return result;
2902 }
2903
2904 static LLVMValueRef
2905 load_gs_input(struct ac_shader_abi *abi,
2906 unsigned location,
2907 unsigned driver_location,
2908 unsigned component,
2909 unsigned num_components,
2910 unsigned vertex_index,
2911 unsigned const_index,
2912 LLVMTypeRef type)
2913 {
2914 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2915 LLVMValueRef vtx_offset;
2916 LLVMValueRef args[9];
2917 unsigned param, vtx_offset_param;
2918 LLVMValueRef value[4], result;
2919
2920 vtx_offset_param = vertex_index;
2921 assert(vtx_offset_param < 6);
2922 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2923 LLVMConstInt(ctx->ac.i32, 4, false), "");
2924
2925 param = shader_io_get_unique_index(location);
2926
2927 for (unsigned i = component; i < num_components + component; i++) {
2928 if (ctx->ac.chip_class >= GFX9) {
2929 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
2930 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2931 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
2932 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2933 } else {
2934 args[0] = ctx->esgs_ring;
2935 args[1] = vtx_offset;
2936 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
2937 args[3] = ctx->ac.i32_0;
2938 args[4] = ctx->ac.i32_1; /* OFFEN */
2939 args[5] = ctx->ac.i32_0; /* IDXEN */
2940 args[6] = ctx->ac.i32_1; /* GLC */
2941 args[7] = ctx->ac.i32_0; /* SLC */
2942 args[8] = ctx->ac.i32_0; /* TFE */
2943
2944 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2945 ctx->ac.i32, args, 9,
2946 AC_FUNC_ATTR_READONLY |
2947 AC_FUNC_ATTR_LEGACY);
2948 }
2949 }
2950 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2951
2952 return result;
2953 }
2954
2955 static LLVMValueRef
2956 build_gep_for_deref(struct ac_nir_context *ctx,
2957 nir_deref_var *deref)
2958 {
2959 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2960 assert(entry->data);
2961 LLVMValueRef val = entry->data;
2962 nir_deref *tail = deref->deref.child;
2963 while (tail != NULL) {
2964 LLVMValueRef offset;
2965 switch (tail->deref_type) {
2966 case nir_deref_type_array: {
2967 nir_deref_array *array = nir_deref_as_array(tail);
2968 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2969 if (array->deref_array_type ==
2970 nir_deref_array_type_indirect) {
2971 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2972 get_src(ctx,
2973 array->indirect),
2974 "");
2975 }
2976 break;
2977 }
2978 case nir_deref_type_struct: {
2979 nir_deref_struct *deref_struct =
2980 nir_deref_as_struct(tail);
2981 offset = LLVMConstInt(ctx->ac.i32,
2982 deref_struct->index, 0);
2983 break;
2984 }
2985 default:
2986 unreachable("bad deref type");
2987 }
2988 val = ac_build_gep0(&ctx->ac, val, offset);
2989 tail = tail->child;
2990 }
2991 return val;
2992 }
2993
2994 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
2995 nir_intrinsic_instr *instr)
2996 {
2997 LLVMValueRef values[8];
2998 int idx = instr->variables[0]->var->data.driver_location;
2999 int ve = instr->dest.ssa.num_components;
3000 unsigned comp = instr->variables[0]->var->data.location_frac;
3001 LLVMValueRef indir_index;
3002 LLVMValueRef ret;
3003 unsigned const_index;
3004 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3005 instr->variables[0]->var->data.mode == nir_var_shader_in;
3006 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3007 &const_index, &indir_index);
3008
3009 if (instr->dest.ssa.bit_size == 64)
3010 ve *= 2;
3011
3012 switch (instr->variables[0]->var->data.mode) {
3013 case nir_var_shader_in:
3014 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3015 return load_tcs_input(ctx->nctx, instr);
3016 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3017 return load_tes_input(ctx->nctx, instr);
3018 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3019 LLVMValueRef indir_index;
3020 unsigned const_index, vertex_index;
3021 get_deref_offset(ctx, instr->variables[0],
3022 false, &vertex_index, NULL,
3023 &const_index, &indir_index);
3024 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3025 instr->variables[0]->var->data.driver_location,
3026 instr->variables[0]->var->data.location_frac, ve,
3027 vertex_index, const_index,
3028 nir2llvmtype(ctx, instr->variables[0]->var->type));
3029 }
3030
3031 for (unsigned chan = comp; chan < ve + comp; chan++) {
3032 if (indir_index) {
3033 unsigned count = glsl_count_attribute_slots(
3034 instr->variables[0]->var->type,
3035 ctx->stage == MESA_SHADER_VERTEX);
3036 count -= chan / 4;
3037 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3038 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3039 4, false, true);
3040
3041 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3042 tmp_vec,
3043 indir_index, "");
3044 } else
3045 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3046 }
3047 break;
3048 case nir_var_local:
3049 for (unsigned chan = 0; chan < ve; chan++) {
3050 if (indir_index) {
3051 unsigned count = glsl_count_attribute_slots(
3052 instr->variables[0]->var->type, false);
3053 count -= chan / 4;
3054 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3055 &ctx->ac, ctx->locals + idx + chan, count,
3056 4, true, true);
3057
3058 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3059 tmp_vec,
3060 indir_index, "");
3061 } else {
3062 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3063 }
3064 }
3065 break;
3066 case nir_var_shared: {
3067 LLVMValueRef address = build_gep_for_deref(ctx,
3068 instr->variables[0]);
3069 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3070 return LLVMBuildBitCast(ctx->ac.builder, val,
3071 get_def_type(ctx, &instr->dest.ssa),
3072 "");
3073 }
3074 case nir_var_shader_out:
3075 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3076 return load_tcs_output(ctx->nctx, instr);
3077
3078 for (unsigned chan = comp; chan < ve + comp; chan++) {
3079 if (indir_index) {
3080 unsigned count = glsl_count_attribute_slots(
3081 instr->variables[0]->var->type, false);
3082 count -= chan / 4;
3083 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3084 &ctx->ac, ctx->outputs + idx + chan, count,
3085 4, true, true);
3086
3087 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3088 tmp_vec,
3089 indir_index, "");
3090 } else {
3091 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3092 ctx->outputs[idx + chan + const_index * 4],
3093 "");
3094 }
3095 }
3096 break;
3097 default:
3098 unreachable("unhandle variable mode");
3099 }
3100 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3101 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3102 }
3103
3104 static void
3105 visit_store_var(struct ac_nir_context *ctx,
3106 nir_intrinsic_instr *instr)
3107 {
3108 LLVMValueRef temp_ptr, value;
3109 int idx = instr->variables[0]->var->data.driver_location;
3110 unsigned comp = instr->variables[0]->var->data.location_frac;
3111 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3112 int writemask = instr->const_index[0] << comp;
3113 LLVMValueRef indir_index;
3114 unsigned const_index;
3115 get_deref_offset(ctx, instr->variables[0], false,
3116 NULL, NULL, &const_index, &indir_index);
3117
3118 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3119 int old_writemask = writemask;
3120
3121 src = LLVMBuildBitCast(ctx->ac.builder, src,
3122 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3123 "");
3124
3125 writemask = 0;
3126 for (unsigned chan = 0; chan < 4; chan++) {
3127 if (old_writemask & (1 << chan))
3128 writemask |= 3u << (2 * chan);
3129 }
3130 }
3131
3132 switch (instr->variables[0]->var->data.mode) {
3133 case nir_var_shader_out:
3134
3135 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3136 store_tcs_output(ctx->nctx, instr, src, writemask);
3137 return;
3138 }
3139
3140 for (unsigned chan = 0; chan < 8; chan++) {
3141 int stride = 4;
3142 if (!(writemask & (1 << chan)))
3143 continue;
3144
3145 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3146
3147 if (instr->variables[0]->var->data.compact)
3148 stride = 1;
3149 if (indir_index) {
3150 unsigned count = glsl_count_attribute_slots(
3151 instr->variables[0]->var->type, false);
3152 count -= chan / 4;
3153 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3154 &ctx->ac, ctx->outputs + idx + chan, count,
3155 stride, true, true);
3156
3157 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3158 value, indir_index, "");
3159 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3160 count, stride, tmp_vec);
3161
3162 } else {
3163 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3164
3165 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3166 }
3167 }
3168 break;
3169 case nir_var_local:
3170 for (unsigned chan = 0; chan < 8; chan++) {
3171 if (!(writemask & (1 << chan)))
3172 continue;
3173
3174 value = llvm_extract_elem(&ctx->ac, src, chan);
3175 if (indir_index) {
3176 unsigned count = glsl_count_attribute_slots(
3177 instr->variables[0]->var->type, false);
3178 count -= chan / 4;
3179 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3180 &ctx->ac, ctx->locals + idx + chan, count,
3181 4, true, true);
3182
3183 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3184 value, indir_index, "");
3185 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3186 count, 4, tmp_vec);
3187 } else {
3188 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3189
3190 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3191 }
3192 }
3193 break;
3194 case nir_var_shared: {
3195 int writemask = instr->const_index[0];
3196 LLVMValueRef address = build_gep_for_deref(ctx,
3197 instr->variables[0]);
3198 LLVMValueRef val = get_src(ctx, instr->src[0]);
3199 unsigned components =
3200 glsl_get_vector_elements(
3201 nir_deref_tail(&instr->variables[0]->deref)->type);
3202 if (writemask == (1 << components) - 1) {
3203 val = LLVMBuildBitCast(
3204 ctx->ac.builder, val,
3205 LLVMGetElementType(LLVMTypeOf(address)), "");
3206 LLVMBuildStore(ctx->ac.builder, val, address);
3207 } else {
3208 for (unsigned chan = 0; chan < 4; chan++) {
3209 if (!(writemask & (1 << chan)))
3210 continue;
3211 LLVMValueRef ptr =
3212 LLVMBuildStructGEP(ctx->ac.builder,
3213 address, chan, "");
3214 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3215 chan);
3216 src = LLVMBuildBitCast(
3217 ctx->ac.builder, src,
3218 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3219 LLVMBuildStore(ctx->ac.builder, src, ptr);
3220 }
3221 }
3222 break;
3223 }
3224 default:
3225 break;
3226 }
3227 }
3228
3229 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3230 {
3231 switch (dim) {
3232 case GLSL_SAMPLER_DIM_BUF:
3233 return 1;
3234 case GLSL_SAMPLER_DIM_1D:
3235 return array ? 2 : 1;
3236 case GLSL_SAMPLER_DIM_2D:
3237 return array ? 3 : 2;
3238 case GLSL_SAMPLER_DIM_MS:
3239 return array ? 4 : 3;
3240 case GLSL_SAMPLER_DIM_3D:
3241 case GLSL_SAMPLER_DIM_CUBE:
3242 return 3;
3243 case GLSL_SAMPLER_DIM_RECT:
3244 case GLSL_SAMPLER_DIM_SUBPASS:
3245 return 2;
3246 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3247 return 3;
3248 default:
3249 break;
3250 }
3251 return 0;
3252 }
3253
3254
3255
3256 /* Adjust the sample index according to FMASK.
3257 *
3258 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3259 * which is the identity mapping. Each nibble says which physical sample
3260 * should be fetched to get that sample.
3261 *
3262 * For example, 0x11111100 means there are only 2 samples stored and
3263 * the second sample covers 3/4 of the pixel. When reading samples 0
3264 * and 1, return physical sample 0 (determined by the first two 0s
3265 * in FMASK), otherwise return physical sample 1.
3266 *
3267 * The sample index should be adjusted as follows:
3268 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3269 */
3270 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3271 LLVMValueRef coord_x, LLVMValueRef coord_y,
3272 LLVMValueRef coord_z,
3273 LLVMValueRef sample_index,
3274 LLVMValueRef fmask_desc_ptr)
3275 {
3276 LLVMValueRef fmask_load_address[4];
3277 LLVMValueRef res;
3278
3279 fmask_load_address[0] = coord_x;
3280 fmask_load_address[1] = coord_y;
3281 if (coord_z) {
3282 fmask_load_address[2] = coord_z;
3283 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3284 }
3285
3286 struct ac_image_args args = {0};
3287
3288 args.opcode = ac_image_load;
3289 args.da = coord_z ? true : false;
3290 args.resource = fmask_desc_ptr;
3291 args.dmask = 0xf;
3292 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3293
3294 res = ac_build_image_opcode(ctx, &args);
3295
3296 res = ac_to_integer(ctx, res);
3297 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3298 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3299
3300 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3301 res,
3302 ctx->i32_0, "");
3303
3304 LLVMValueRef sample_index4 =
3305 LLVMBuildMul(ctx->builder, sample_index, four, "");
3306 LLVMValueRef shifted_fmask =
3307 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3308 LLVMValueRef final_sample =
3309 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3310
3311 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3312 * resource descriptor is 0 (invalid),
3313 */
3314 LLVMValueRef fmask_desc =
3315 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3316 ctx->v8i32, "");
3317
3318 LLVMValueRef fmask_word1 =
3319 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3320 ctx->i32_1, "");
3321
3322 LLVMValueRef word1_is_nonzero =
3323 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3324 fmask_word1, ctx->i32_0, "");
3325
3326 /* Replace the MSAA sample index. */
3327 sample_index =
3328 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3329 final_sample, sample_index, "");
3330 return sample_index;
3331 }
3332
3333 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3334 const nir_intrinsic_instr *instr)
3335 {
3336 const struct glsl_type *type = instr->variables[0]->var->type;
3337 if(instr->variables[0]->deref.child)
3338 type = instr->variables[0]->deref.child->type;
3339
3340 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3341 LLVMValueRef coords[4];
3342 LLVMValueRef masks[] = {
3343 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3344 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3345 };
3346 LLVMValueRef res;
3347 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3348
3349 int count;
3350 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3351 bool is_array = glsl_sampler_type_is_array(type);
3352 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3353 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3354 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3355 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3356 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3357 count = image_type_to_components_count(dim, is_array);
3358
3359 if (is_ms) {
3360 LLVMValueRef fmask_load_address[3];
3361 int chan;
3362
3363 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3364 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3365 if (is_array)
3366 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3367 else
3368 fmask_load_address[2] = NULL;
3369 if (add_frag_pos) {
3370 for (chan = 0; chan < 2; ++chan)
3371 fmask_load_address[chan] =
3372 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3373 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3374 ctx->ac.i32, ""), "");
3375 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3376 }
3377 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3378 fmask_load_address[0],
3379 fmask_load_address[1],
3380 fmask_load_address[2],
3381 sample_index,
3382 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3383 }
3384 if (count == 1 && !gfx9_1d) {
3385 if (instr->src[0].ssa->num_components)
3386 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3387 else
3388 res = src0;
3389 } else {
3390 int chan;
3391 if (is_ms)
3392 count--;
3393 for (chan = 0; chan < count; ++chan) {
3394 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3395 }
3396 if (add_frag_pos) {
3397 for (chan = 0; chan < 2; ++chan)
3398 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3399 ctx->ac.i32, ""), "");
3400 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3401 count++;
3402 }
3403
3404 if (gfx9_1d) {
3405 if (is_array) {
3406 coords[2] = coords[1];
3407 coords[1] = ctx->ac.i32_0;
3408 } else
3409 coords[1] = ctx->ac.i32_0;
3410 count++;
3411 }
3412
3413 if (is_ms) {
3414 coords[count] = sample_index;
3415 count++;
3416 }
3417
3418 if (count == 3) {
3419 coords[3] = LLVMGetUndef(ctx->ac.i32);
3420 count = 4;
3421 }
3422 res = ac_build_gather_values(&ctx->ac, coords, count);
3423 }
3424 return res;
3425 }
3426
3427 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3428 const nir_intrinsic_instr *instr)
3429 {
3430 LLVMValueRef params[7];
3431 LLVMValueRef res;
3432 char intrinsic_name[64];
3433 const nir_variable *var = instr->variables[0]->var;
3434 const struct glsl_type *type = var->type;
3435
3436 if(instr->variables[0]->deref.child)
3437 type = instr->variables[0]->deref.child->type;
3438
3439 type = glsl_without_array(type);
3440 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3441 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3442 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3443 ctx->ac.i32_0, ""); /* vindex */
3444 params[2] = ctx->ac.i32_0; /* voffset */
3445 params[3] = ctx->ac.i1false; /* glc */
3446 params[4] = ctx->ac.i1false; /* slc */
3447 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3448 params, 5, 0);
3449
3450 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3451 res = ac_to_integer(&ctx->ac, res);
3452 } else {
3453 bool is_da = glsl_sampler_type_is_array(type) ||
3454 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3455 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3456 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3457 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3458 LLVMValueRef glc = ctx->ac.i1false;
3459 LLVMValueRef slc = ctx->ac.i1false;
3460
3461 params[0] = get_image_coords(ctx, instr);
3462 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3463 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3464 if (HAVE_LLVM <= 0x0309) {
3465 params[3] = ctx->ac.i1false; /* r128 */
3466 params[4] = da;
3467 params[5] = glc;
3468 params[6] = slc;
3469 } else {
3470 LLVMValueRef lwe = ctx->ac.i1false;
3471 params[3] = glc;
3472 params[4] = slc;
3473 params[5] = lwe;
3474 params[6] = da;
3475 }
3476
3477 ac_get_image_intr_name("llvm.amdgcn.image.load",
3478 ctx->ac.v4f32, /* vdata */
3479 LLVMTypeOf(params[0]), /* coords */
3480 LLVMTypeOf(params[1]), /* rsrc */
3481 intrinsic_name, sizeof(intrinsic_name));
3482
3483 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3484 params, 7, AC_FUNC_ATTR_READONLY);
3485 }
3486 return ac_to_integer(&ctx->ac, res);
3487 }
3488
3489 static void visit_image_store(struct ac_nir_context *ctx,
3490 nir_intrinsic_instr *instr)
3491 {
3492 LLVMValueRef params[8];
3493 char intrinsic_name[64];
3494 const nir_variable *var = instr->variables[0]->var;
3495 const struct glsl_type *type = glsl_without_array(var->type);
3496 LLVMValueRef glc = ctx->ac.i1false;
3497 bool force_glc = ctx->ac.chip_class == SI;
3498 if (force_glc)
3499 glc = ctx->ac.i1true;
3500
3501 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3502 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3503 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3504 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3505 ctx->ac.i32_0, ""); /* vindex */
3506 params[3] = ctx->ac.i32_0; /* voffset */
3507 params[4] = glc; /* glc */
3508 params[5] = ctx->ac.i1false; /* slc */
3509 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3510 params, 6, 0);
3511 } else {
3512 bool is_da = glsl_sampler_type_is_array(type) ||
3513 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3514 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3515 LLVMValueRef slc = ctx->ac.i1false;
3516
3517 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3518 params[1] = get_image_coords(ctx, instr); /* coords */
3519 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3520 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3521 if (HAVE_LLVM <= 0x0309) {
3522 params[4] = ctx->ac.i1false; /* r128 */
3523 params[5] = da;
3524 params[6] = glc;
3525 params[7] = slc;
3526 } else {
3527 LLVMValueRef lwe = ctx->ac.i1false;
3528 params[4] = glc;
3529 params[5] = slc;
3530 params[6] = lwe;
3531 params[7] = da;
3532 }
3533
3534 ac_get_image_intr_name("llvm.amdgcn.image.store",
3535 LLVMTypeOf(params[0]), /* vdata */
3536 LLVMTypeOf(params[1]), /* coords */
3537 LLVMTypeOf(params[2]), /* rsrc */
3538 intrinsic_name, sizeof(intrinsic_name));
3539
3540 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3541 params, 8, 0);
3542 }
3543
3544 }
3545
3546 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3547 const nir_intrinsic_instr *instr)
3548 {
3549 LLVMValueRef params[7];
3550 int param_count = 0;
3551 const nir_variable *var = instr->variables[0]->var;
3552
3553 const char *atomic_name;
3554 char intrinsic_name[41];
3555 const struct glsl_type *type = glsl_without_array(var->type);
3556 MAYBE_UNUSED int length;
3557
3558 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3559
3560 switch (instr->intrinsic) {
3561 case nir_intrinsic_image_atomic_add:
3562 atomic_name = "add";
3563 break;
3564 case nir_intrinsic_image_atomic_min:
3565 atomic_name = is_unsigned ? "umin" : "smin";
3566 break;
3567 case nir_intrinsic_image_atomic_max:
3568 atomic_name = is_unsigned ? "umax" : "smax";
3569 break;
3570 case nir_intrinsic_image_atomic_and:
3571 atomic_name = "and";
3572 break;
3573 case nir_intrinsic_image_atomic_or:
3574 atomic_name = "or";
3575 break;
3576 case nir_intrinsic_image_atomic_xor:
3577 atomic_name = "xor";
3578 break;
3579 case nir_intrinsic_image_atomic_exchange:
3580 atomic_name = "swap";
3581 break;
3582 case nir_intrinsic_image_atomic_comp_swap:
3583 atomic_name = "cmpswap";
3584 break;
3585 default:
3586 abort();
3587 }
3588
3589 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3590 params[param_count++] = get_src(ctx, instr->src[3]);
3591 params[param_count++] = get_src(ctx, instr->src[2]);
3592
3593 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3594 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3595 NULL, true, true);
3596 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3597 ctx->ac.i32_0, ""); /* vindex */
3598 params[param_count++] = ctx->ac.i32_0; /* voffset */
3599 params[param_count++] = ctx->ac.i1false; /* slc */
3600
3601 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3602 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3603 } else {
3604 char coords_type[8];
3605
3606 bool da = glsl_sampler_type_is_array(type) ||
3607 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3608
3609 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3610 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3611 NULL, true, true);
3612 params[param_count++] = ctx->ac.i1false; /* r128 */
3613 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3614 params[param_count++] = ctx->ac.i1false; /* slc */
3615
3616 build_int_type_name(LLVMTypeOf(coords),
3617 coords_type, sizeof(coords_type));
3618
3619 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3620 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3621 }
3622
3623 assert(length < sizeof(intrinsic_name));
3624 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3625 }
3626
3627 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3628 const nir_intrinsic_instr *instr)
3629 {
3630 LLVMValueRef res;
3631 const nir_variable *var = instr->variables[0]->var;
3632 const struct glsl_type *type = instr->variables[0]->var->type;
3633 bool da = glsl_sampler_type_is_array(var->type) ||
3634 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3635 if(instr->variables[0]->deref.child)
3636 type = instr->variables[0]->deref.child->type;
3637
3638 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3639 return get_buffer_size(ctx,
3640 get_sampler_desc(ctx, instr->variables[0],
3641 AC_DESC_BUFFER, NULL, true, false), true);
3642
3643 struct ac_image_args args = { 0 };
3644
3645 args.da = da;
3646 args.dmask = 0xf;
3647 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3648 args.opcode = ac_image_get_resinfo;
3649 args.addr = ctx->ac.i32_0;
3650
3651 res = ac_build_image_opcode(&ctx->ac, &args);
3652
3653 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3654
3655 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3656 glsl_sampler_type_is_array(type)) {
3657 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3658 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3659 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3660 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3661 }
3662 if (ctx->ac.chip_class >= GFX9 &&
3663 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3664 glsl_sampler_type_is_array(type)) {
3665 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3666 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3667 ctx->ac.i32_1, "");
3668
3669 }
3670 return res;
3671 }
3672
3673 #define NOOP_WAITCNT 0xf7f
3674 #define LGKM_CNT 0x07f
3675 #define VM_CNT 0xf70
3676
3677 static void emit_membar(struct nir_to_llvm_context *ctx,
3678 const nir_intrinsic_instr *instr)
3679 {
3680 unsigned waitcnt = NOOP_WAITCNT;
3681
3682 switch (instr->intrinsic) {
3683 case nir_intrinsic_memory_barrier:
3684 case nir_intrinsic_group_memory_barrier:
3685 waitcnt &= VM_CNT & LGKM_CNT;
3686 break;
3687 case nir_intrinsic_memory_barrier_atomic_counter:
3688 case nir_intrinsic_memory_barrier_buffer:
3689 case nir_intrinsic_memory_barrier_image:
3690 waitcnt &= VM_CNT;
3691 break;
3692 case nir_intrinsic_memory_barrier_shared:
3693 waitcnt &= LGKM_CNT;
3694 break;
3695 default:
3696 break;
3697 }
3698 if (waitcnt != NOOP_WAITCNT)
3699 ac_build_waitcnt(&ctx->ac, waitcnt);
3700 }
3701
3702 static void emit_barrier(struct nir_to_llvm_context *ctx)
3703 {
3704 /* SI only (thanks to a hw bug workaround):
3705 * The real barrier instruction isn’t needed, because an entire patch
3706 * always fits into a single wave.
3707 */
3708 if (ctx->options->chip_class == SI &&
3709 ctx->stage == MESA_SHADER_TESS_CTRL) {
3710 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
3711 return;
3712 }
3713 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3714 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3715 }
3716
3717 static void emit_discard_if(struct ac_nir_context *ctx,
3718 const nir_intrinsic_instr *instr)
3719 {
3720 LLVMValueRef cond;
3721
3722 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3723 get_src(ctx, instr->src[0]),
3724 ctx->ac.i32_0, "");
3725 ac_build_kill_if_false(&ctx->ac, cond);
3726 }
3727
3728 static LLVMValueRef
3729 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3730 {
3731 LLVMValueRef result;
3732 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3733 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3734 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3735
3736 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3737 }
3738
3739 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3740 const nir_intrinsic_instr *instr)
3741 {
3742 LLVMValueRef ptr, result;
3743 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3744 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3745
3746 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3747 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3748 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3749 ptr, src, src1,
3750 LLVMAtomicOrderingSequentiallyConsistent,
3751 LLVMAtomicOrderingSequentiallyConsistent,
3752 false);
3753 } else {
3754 LLVMAtomicRMWBinOp op;
3755 switch (instr->intrinsic) {
3756 case nir_intrinsic_var_atomic_add:
3757 op = LLVMAtomicRMWBinOpAdd;
3758 break;
3759 case nir_intrinsic_var_atomic_umin:
3760 op = LLVMAtomicRMWBinOpUMin;
3761 break;
3762 case nir_intrinsic_var_atomic_umax:
3763 op = LLVMAtomicRMWBinOpUMax;
3764 break;
3765 case nir_intrinsic_var_atomic_imin:
3766 op = LLVMAtomicRMWBinOpMin;
3767 break;
3768 case nir_intrinsic_var_atomic_imax:
3769 op = LLVMAtomicRMWBinOpMax;
3770 break;
3771 case nir_intrinsic_var_atomic_and:
3772 op = LLVMAtomicRMWBinOpAnd;
3773 break;
3774 case nir_intrinsic_var_atomic_or:
3775 op = LLVMAtomicRMWBinOpOr;
3776 break;
3777 case nir_intrinsic_var_atomic_xor:
3778 op = LLVMAtomicRMWBinOpXor;
3779 break;
3780 case nir_intrinsic_var_atomic_exchange:
3781 op = LLVMAtomicRMWBinOpXchg;
3782 break;
3783 default:
3784 return NULL;
3785 }
3786
3787 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3788 LLVMAtomicOrderingSequentiallyConsistent,
3789 false);
3790 }
3791 return result;
3792 }
3793
3794 #define INTERP_CENTER 0
3795 #define INTERP_CENTROID 1
3796 #define INTERP_SAMPLE 2
3797
3798 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3799 enum glsl_interp_mode interp, unsigned location)
3800 {
3801 switch (interp) {
3802 case INTERP_MODE_FLAT:
3803 default:
3804 return NULL;
3805 case INTERP_MODE_SMOOTH:
3806 case INTERP_MODE_NONE:
3807 if (location == INTERP_CENTER)
3808 return ctx->persp_center;
3809 else if (location == INTERP_CENTROID)
3810 return ctx->persp_centroid;
3811 else if (location == INTERP_SAMPLE)
3812 return ctx->persp_sample;
3813 break;
3814 case INTERP_MODE_NOPERSPECTIVE:
3815 if (location == INTERP_CENTER)
3816 return ctx->linear_center;
3817 else if (location == INTERP_CENTROID)
3818 return ctx->linear_centroid;
3819 else if (location == INTERP_SAMPLE)
3820 return ctx->linear_sample;
3821 break;
3822 }
3823 return NULL;
3824 }
3825
3826 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3827 LLVMValueRef sample_id)
3828 {
3829 LLVMValueRef result;
3830 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3831
3832 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3833 const_array(ctx->ac.v2f32, 64), "");
3834
3835 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3836 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3837
3838 return result;
3839 }
3840
3841 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3842 {
3843 LLVMValueRef values[2];
3844
3845 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3846 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3847 return ac_build_gather_values(&ctx->ac, values, 2);
3848 }
3849
3850 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3851 const nir_intrinsic_instr *instr)
3852 {
3853 LLVMValueRef result[4];
3854 LLVMValueRef interp_param, attr_number;
3855 unsigned location;
3856 unsigned chan;
3857 LLVMValueRef src_c0 = NULL;
3858 LLVMValueRef src_c1 = NULL;
3859 LLVMValueRef src0 = NULL;
3860 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3861 switch (instr->intrinsic) {
3862 case nir_intrinsic_interp_var_at_centroid:
3863 location = INTERP_CENTROID;
3864 break;
3865 case nir_intrinsic_interp_var_at_sample:
3866 case nir_intrinsic_interp_var_at_offset:
3867 location = INTERP_CENTER;
3868 src0 = get_src(ctx->nir, instr->src[0]);
3869 break;
3870 default:
3871 break;
3872 }
3873
3874 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3875 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3876 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3877 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3878 LLVMValueRef sample_position;
3879 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
3880
3881 /* fetch sample ID */
3882 sample_position = load_sample_position(ctx, src0);
3883
3884 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
3885 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3886 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
3887 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3888 }
3889 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3890 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
3891
3892 if (location == INTERP_CENTER) {
3893 LLVMValueRef ij_out[2];
3894 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3895
3896 /*
3897 * take the I then J parameters, and the DDX/Y for it, and
3898 * calculate the IJ inputs for the interpolator.
3899 * temp1 = ddx * offset/sample.x + I;
3900 * interp_param.I = ddy * offset/sample.y + temp1;
3901 * temp1 = ddx * offset/sample.x + J;
3902 * interp_param.J = ddy * offset/sample.y + temp1;
3903 */
3904 for (unsigned i = 0; i < 2; i++) {
3905 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
3906 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
3907 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3908 ddxy_out, ix_ll, "");
3909 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3910 ddxy_out, iy_ll, "");
3911 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3912 interp_param, ix_ll, "");
3913 LLVMValueRef temp1, temp2;
3914
3915 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3916 ctx->ac.f32, "");
3917
3918 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3919 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3920
3921 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3922 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3923
3924 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3925 temp2, ctx->ac.i32, "");
3926 }
3927 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3928
3929 }
3930
3931 for (chan = 0; chan < 4; chan++) {
3932 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
3933
3934 if (interp_param) {
3935 interp_param = LLVMBuildBitCast(ctx->builder,
3936 interp_param, ctx->ac.v2f32, "");
3937 LLVMValueRef i = LLVMBuildExtractElement(
3938 ctx->builder, interp_param, ctx->ac.i32_0, "");
3939 LLVMValueRef j = LLVMBuildExtractElement(
3940 ctx->builder, interp_param, ctx->ac.i32_1, "");
3941
3942 result[chan] = ac_build_fs_interp(&ctx->ac,
3943 llvm_chan, attr_number,
3944 ctx->prim_mask, i, j);
3945 } else {
3946 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3947 LLVMConstInt(ctx->ac.i32, 2, false),
3948 llvm_chan, attr_number,
3949 ctx->prim_mask);
3950 }
3951 }
3952 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
3953 instr->variables[0]->var->data.location_frac);
3954 }
3955
3956 static void
3957 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
3958 {
3959 LLVMValueRef gs_next_vertex;
3960 LLVMValueRef can_emit;
3961 int idx;
3962 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3963
3964 /* Write vertex attribute values to GSVS ring */
3965 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3966 ctx->gs_next_vertex,
3967 "");
3968
3969 /* If this thread has already emitted the declared maximum number of
3970 * vertices, kill it: excessive vertex emissions are not supposed to
3971 * have any effect, and GS threads have no externally observable
3972 * effects other than emitting vertices.
3973 */
3974 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3975 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
3976 ac_build_kill_if_false(&ctx->ac, can_emit);
3977
3978 /* loop num outputs */
3979 idx = 0;
3980 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3981 LLVMValueRef *out_ptr = &addrs[i * 4];
3982 int length = 4;
3983 int slot = idx;
3984 int slot_inc = 1;
3985
3986 if (!(ctx->output_mask & (1ull << i)))
3987 continue;
3988
3989 if (i == VARYING_SLOT_CLIP_DIST0) {
3990 /* pack clip and cull into a single set of slots */
3991 length = ctx->num_output_clips + ctx->num_output_culls;
3992 if (length > 4)
3993 slot_inc = 2;
3994 }
3995 for (unsigned j = 0; j < length; j++) {
3996 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3997 out_ptr[j], "");
3998 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3999 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4000 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4001
4002 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4003
4004 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4005 out_val, 1,
4006 voffset, ctx->gs2vs_offset, 0,
4007 1, 1, true, true);
4008 }
4009 idx += slot_inc;
4010 }
4011
4012 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4013 ctx->ac.i32_1, "");
4014 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4015
4016 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4017 }
4018
4019 static void
4020 visit_end_primitive(struct nir_to_llvm_context *ctx,
4021 const nir_intrinsic_instr *instr)
4022 {
4023 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4024 }
4025
4026 static LLVMValueRef
4027 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4028 const nir_intrinsic_instr *instr)
4029 {
4030 LLVMValueRef coord[4] = {
4031 ctx->tes_u,
4032 ctx->tes_v,
4033 ctx->ac.f32_0,
4034 ctx->ac.f32_0,
4035 };
4036
4037 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4038 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4039 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4040
4041 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4042 return LLVMBuildBitCast(ctx->builder, result,
4043 get_def_type(ctx->nir, &instr->dest.ssa), "");
4044 }
4045
4046 static void visit_intrinsic(struct ac_nir_context *ctx,
4047 nir_intrinsic_instr *instr)
4048 {
4049 LLVMValueRef result = NULL;
4050
4051 switch (instr->intrinsic) {
4052 case nir_intrinsic_load_work_group_id: {
4053 result = ctx->nctx->workgroup_ids;
4054 break;
4055 }
4056 case nir_intrinsic_load_base_vertex: {
4057 result = ctx->abi->base_vertex;
4058 break;
4059 }
4060 case nir_intrinsic_load_vertex_id_zero_base: {
4061 result = ctx->abi->vertex_id;
4062 break;
4063 }
4064 case nir_intrinsic_load_local_invocation_id: {
4065 result = ctx->nctx->local_invocation_ids;
4066 break;
4067 }
4068 case nir_intrinsic_load_base_instance:
4069 result = ctx->abi->start_instance;
4070 break;
4071 case nir_intrinsic_load_draw_id:
4072 result = ctx->abi->draw_id;
4073 break;
4074 case nir_intrinsic_load_view_index:
4075 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4076 break;
4077 case nir_intrinsic_load_invocation_id:
4078 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4079 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4080 else
4081 result = ctx->abi->gs_invocation_id;
4082 break;
4083 case nir_intrinsic_load_primitive_id:
4084 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4085 if (ctx->nctx)
4086 ctx->nctx->shader_info->gs.uses_prim_id = true;
4087 result = ctx->abi->gs_prim_id;
4088 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4089 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4090 result = ctx->nctx->tcs_patch_id;
4091 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4092 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4093 result = ctx->nctx->tes_patch_id;
4094 } else
4095 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4096 break;
4097 case nir_intrinsic_load_sample_id:
4098 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4099 break;
4100 case nir_intrinsic_load_sample_pos:
4101 result = load_sample_pos(ctx);
4102 break;
4103 case nir_intrinsic_load_sample_mask_in:
4104 result = ctx->abi->sample_coverage;
4105 break;
4106 case nir_intrinsic_load_frag_coord: {
4107 LLVMValueRef values[4] = {
4108 ctx->abi->frag_pos[0],
4109 ctx->abi->frag_pos[1],
4110 ctx->abi->frag_pos[2],
4111 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4112 };
4113 result = ac_build_gather_values(&ctx->ac, values, 4);
4114 break;
4115 }
4116 case nir_intrinsic_load_front_face:
4117 result = ctx->abi->front_face;
4118 break;
4119 case nir_intrinsic_load_instance_id:
4120 result = ctx->abi->instance_id;
4121 break;
4122 case nir_intrinsic_load_num_work_groups:
4123 result = ctx->nctx->num_work_groups;
4124 break;
4125 case nir_intrinsic_load_local_invocation_index:
4126 result = visit_load_local_invocation_index(ctx->nctx);
4127 break;
4128 case nir_intrinsic_load_push_constant:
4129 result = visit_load_push_constant(ctx->nctx, instr);
4130 break;
4131 case nir_intrinsic_vulkan_resource_index:
4132 result = visit_vulkan_resource_index(ctx->nctx, instr);
4133 break;
4134 case nir_intrinsic_vulkan_resource_reindex:
4135 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4136 break;
4137 case nir_intrinsic_store_ssbo:
4138 visit_store_ssbo(ctx, instr);
4139 break;
4140 case nir_intrinsic_load_ssbo:
4141 result = visit_load_buffer(ctx, instr);
4142 break;
4143 case nir_intrinsic_ssbo_atomic_add:
4144 case nir_intrinsic_ssbo_atomic_imin:
4145 case nir_intrinsic_ssbo_atomic_umin:
4146 case nir_intrinsic_ssbo_atomic_imax:
4147 case nir_intrinsic_ssbo_atomic_umax:
4148 case nir_intrinsic_ssbo_atomic_and:
4149 case nir_intrinsic_ssbo_atomic_or:
4150 case nir_intrinsic_ssbo_atomic_xor:
4151 case nir_intrinsic_ssbo_atomic_exchange:
4152 case nir_intrinsic_ssbo_atomic_comp_swap:
4153 result = visit_atomic_ssbo(ctx, instr);
4154 break;
4155 case nir_intrinsic_load_ubo:
4156 result = visit_load_ubo_buffer(ctx, instr);
4157 break;
4158 case nir_intrinsic_get_buffer_size:
4159 result = visit_get_buffer_size(ctx, instr);
4160 break;
4161 case nir_intrinsic_load_var:
4162 result = visit_load_var(ctx, instr);
4163 break;
4164 case nir_intrinsic_store_var:
4165 visit_store_var(ctx, instr);
4166 break;
4167 case nir_intrinsic_image_load:
4168 result = visit_image_load(ctx, instr);
4169 break;
4170 case nir_intrinsic_image_store:
4171 visit_image_store(ctx, instr);
4172 break;
4173 case nir_intrinsic_image_atomic_add:
4174 case nir_intrinsic_image_atomic_min:
4175 case nir_intrinsic_image_atomic_max:
4176 case nir_intrinsic_image_atomic_and:
4177 case nir_intrinsic_image_atomic_or:
4178 case nir_intrinsic_image_atomic_xor:
4179 case nir_intrinsic_image_atomic_exchange:
4180 case nir_intrinsic_image_atomic_comp_swap:
4181 result = visit_image_atomic(ctx, instr);
4182 break;
4183 case nir_intrinsic_image_size:
4184 result = visit_image_size(ctx, instr);
4185 break;
4186 case nir_intrinsic_discard:
4187 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4188 LLVMVoidTypeInContext(ctx->ac.context),
4189 NULL, 0, AC_FUNC_ATTR_LEGACY);
4190 break;
4191 case nir_intrinsic_discard_if:
4192 emit_discard_if(ctx, instr);
4193 break;
4194 case nir_intrinsic_memory_barrier:
4195 case nir_intrinsic_group_memory_barrier:
4196 case nir_intrinsic_memory_barrier_atomic_counter:
4197 case nir_intrinsic_memory_barrier_buffer:
4198 case nir_intrinsic_memory_barrier_image:
4199 case nir_intrinsic_memory_barrier_shared:
4200 emit_membar(ctx->nctx, instr);
4201 break;
4202 case nir_intrinsic_barrier:
4203 emit_barrier(ctx->nctx);
4204 break;
4205 case nir_intrinsic_var_atomic_add:
4206 case nir_intrinsic_var_atomic_imin:
4207 case nir_intrinsic_var_atomic_umin:
4208 case nir_intrinsic_var_atomic_imax:
4209 case nir_intrinsic_var_atomic_umax:
4210 case nir_intrinsic_var_atomic_and:
4211 case nir_intrinsic_var_atomic_or:
4212 case nir_intrinsic_var_atomic_xor:
4213 case nir_intrinsic_var_atomic_exchange:
4214 case nir_intrinsic_var_atomic_comp_swap:
4215 result = visit_var_atomic(ctx->nctx, instr);
4216 break;
4217 case nir_intrinsic_interp_var_at_centroid:
4218 case nir_intrinsic_interp_var_at_sample:
4219 case nir_intrinsic_interp_var_at_offset:
4220 result = visit_interp(ctx->nctx, instr);
4221 break;
4222 case nir_intrinsic_emit_vertex:
4223 assert(instr->const_index[0] == 0);
4224 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4225 break;
4226 case nir_intrinsic_end_primitive:
4227 visit_end_primitive(ctx->nctx, instr);
4228 break;
4229 case nir_intrinsic_load_tess_coord:
4230 result = visit_load_tess_coord(ctx->nctx, instr);
4231 break;
4232 case nir_intrinsic_load_patch_vertices_in:
4233 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4234 break;
4235 default:
4236 fprintf(stderr, "Unknown intrinsic: ");
4237 nir_print_instr(&instr->instr, stderr);
4238 fprintf(stderr, "\n");
4239 break;
4240 }
4241 if (result) {
4242 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4243 }
4244 }
4245
4246 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4247 LLVMValueRef buffer_ptr, bool write)
4248 {
4249 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4250
4251 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4252 ctx->shader_info->fs.writes_memory = true;
4253
4254 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4255 }
4256
4257 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4258 {
4259 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4260
4261 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4262 }
4263
4264 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4265 unsigned descriptor_set,
4266 unsigned base_index,
4267 unsigned constant_index,
4268 LLVMValueRef index,
4269 enum ac_descriptor_type desc_type,
4270 bool image, bool write)
4271 {
4272 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4273 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4274 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4275 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4276 unsigned offset = binding->offset;
4277 unsigned stride = binding->size;
4278 unsigned type_size;
4279 LLVMBuilderRef builder = ctx->builder;
4280 LLVMTypeRef type;
4281
4282 assert(base_index < layout->binding_count);
4283
4284 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4285 ctx->shader_info->fs.writes_memory = true;
4286
4287 switch (desc_type) {
4288 case AC_DESC_IMAGE:
4289 type = ctx->ac.v8i32;
4290 type_size = 32;
4291 break;
4292 case AC_DESC_FMASK:
4293 type = ctx->ac.v8i32;
4294 offset += 32;
4295 type_size = 32;
4296 break;
4297 case AC_DESC_SAMPLER:
4298 type = ctx->ac.v4i32;
4299 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4300 offset += 64;
4301
4302 type_size = 16;
4303 break;
4304 case AC_DESC_BUFFER:
4305 type = ctx->ac.v4i32;
4306 type_size = 16;
4307 break;
4308 default:
4309 unreachable("invalid desc_type\n");
4310 }
4311
4312 offset += constant_index * stride;
4313
4314 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4315 (!index || binding->immutable_samplers_equal)) {
4316 if (binding->immutable_samplers_equal)
4317 constant_index = 0;
4318
4319 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4320
4321 LLVMValueRef constants[] = {
4322 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4323 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4324 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4325 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4326 };
4327 return ac_build_gather_values(&ctx->ac, constants, 4);
4328 }
4329
4330 assert(stride % type_size == 0);
4331
4332 if (!index)
4333 index = ctx->ac.i32_0;
4334
4335 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4336
4337 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4338 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4339
4340 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4341 }
4342
4343 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4344 const nir_deref_var *deref,
4345 enum ac_descriptor_type desc_type,
4346 const nir_tex_instr *tex_instr,
4347 bool image, bool write)
4348 {
4349 LLVMValueRef index = NULL;
4350 unsigned constant_index = 0;
4351 unsigned descriptor_set;
4352 unsigned base_index;
4353
4354 if (!deref) {
4355 assert(tex_instr && !image);
4356 descriptor_set = 0;
4357 base_index = tex_instr->sampler_index;
4358 } else {
4359 const nir_deref *tail = &deref->deref;
4360 while (tail->child) {
4361 const nir_deref_array *child = nir_deref_as_array(tail->child);
4362 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4363
4364 if (!array_size)
4365 array_size = 1;
4366
4367 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4368
4369 if (child->deref_array_type == nir_deref_array_type_indirect) {
4370 LLVMValueRef indirect = get_src(ctx, child->indirect);
4371
4372 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4373 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4374
4375 if (!index)
4376 index = indirect;
4377 else
4378 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4379 }
4380
4381 constant_index += child->base_offset * array_size;
4382
4383 tail = &child->deref;
4384 }
4385 descriptor_set = deref->var->data.descriptor_set;
4386 base_index = deref->var->data.binding;
4387 }
4388
4389 return ctx->abi->load_sampler_desc(ctx->abi,
4390 descriptor_set,
4391 base_index,
4392 constant_index, index,
4393 desc_type, image, write);
4394 }
4395
4396 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4397 struct ac_image_args *args,
4398 const nir_tex_instr *instr,
4399 nir_texop op,
4400 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4401 LLVMValueRef *param, unsigned count,
4402 unsigned dmask)
4403 {
4404 unsigned is_rect = 0;
4405 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4406
4407 if (op == nir_texop_lod)
4408 da = false;
4409 /* Pad to power of two vector */
4410 while (count < util_next_power_of_two(count))
4411 param[count++] = LLVMGetUndef(ctx->i32);
4412
4413 if (count > 1)
4414 args->addr = ac_build_gather_values(ctx, param, count);
4415 else
4416 args->addr = param[0];
4417
4418 args->resource = res_ptr;
4419 args->sampler = samp_ptr;
4420
4421 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4422 args->addr = param[0];
4423 return;
4424 }
4425
4426 args->dmask = dmask;
4427 args->unorm = is_rect;
4428 args->da = da;
4429 }
4430
4431 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4432 *
4433 * SI-CI:
4434 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4435 * filtering manually. The driver sets img7 to a mask clearing
4436 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4437 * s_and_b32 samp0, samp0, img7
4438 *
4439 * VI:
4440 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4441 */
4442 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4443 LLVMValueRef res, LLVMValueRef samp)
4444 {
4445 LLVMBuilderRef builder = ctx->ac.builder;
4446 LLVMValueRef img7, samp0;
4447
4448 if (ctx->ac.chip_class >= VI)
4449 return samp;
4450
4451 img7 = LLVMBuildExtractElement(builder, res,
4452 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4453 samp0 = LLVMBuildExtractElement(builder, samp,
4454 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4455 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4456 return LLVMBuildInsertElement(builder, samp, samp0,
4457 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4458 }
4459
4460 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4461 nir_tex_instr *instr,
4462 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4463 LLVMValueRef *fmask_ptr)
4464 {
4465 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4466 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4467 else
4468 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4469 if (samp_ptr) {
4470 if (instr->sampler)
4471 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4472 else
4473 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4474 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4475 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4476 }
4477 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4478 instr->op == nir_texop_samples_identical))
4479 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4480 }
4481
4482 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4483 LLVMValueRef coord)
4484 {
4485 coord = ac_to_float(ctx, coord);
4486 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4487 coord = ac_to_integer(ctx, coord);
4488 return coord;
4489 }
4490
4491 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4492 {
4493 LLVMValueRef result = NULL;
4494 struct ac_image_args args = { 0 };
4495 unsigned dmask = 0xf;
4496 LLVMValueRef address[16];
4497 LLVMValueRef coords[5];
4498 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4499 LLVMValueRef bias = NULL, offsets = NULL;
4500 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4501 LLVMValueRef ddx = NULL, ddy = NULL;
4502 LLVMValueRef derivs[6];
4503 unsigned chan, count = 0;
4504 unsigned const_src = 0, num_deriv_comp = 0;
4505 bool lod_is_zero = false;
4506
4507 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4508
4509 for (unsigned i = 0; i < instr->num_srcs; i++) {
4510 switch (instr->src[i].src_type) {
4511 case nir_tex_src_coord:
4512 coord = get_src(ctx, instr->src[i].src);
4513 break;
4514 case nir_tex_src_projector:
4515 break;
4516 case nir_tex_src_comparator:
4517 comparator = get_src(ctx, instr->src[i].src);
4518 break;
4519 case nir_tex_src_offset:
4520 offsets = get_src(ctx, instr->src[i].src);
4521 const_src = i;
4522 break;
4523 case nir_tex_src_bias:
4524 bias = get_src(ctx, instr->src[i].src);
4525 break;
4526 case nir_tex_src_lod: {
4527 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4528
4529 if (val && val->i32[0] == 0)
4530 lod_is_zero = true;
4531 lod = get_src(ctx, instr->src[i].src);
4532 break;
4533 }
4534 case nir_tex_src_ms_index:
4535 sample_index = get_src(ctx, instr->src[i].src);
4536 break;
4537 case nir_tex_src_ms_mcs:
4538 break;
4539 case nir_tex_src_ddx:
4540 ddx = get_src(ctx, instr->src[i].src);
4541 num_deriv_comp = instr->src[i].src.ssa->num_components;
4542 break;
4543 case nir_tex_src_ddy:
4544 ddy = get_src(ctx, instr->src[i].src);
4545 break;
4546 case nir_tex_src_texture_offset:
4547 case nir_tex_src_sampler_offset:
4548 case nir_tex_src_plane:
4549 default:
4550 break;
4551 }
4552 }
4553
4554 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4555 result = get_buffer_size(ctx, res_ptr, true);
4556 goto write_result;
4557 }
4558
4559 if (instr->op == nir_texop_texture_samples) {
4560 LLVMValueRef res, samples, is_msaa;
4561 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4562 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4563 LLVMConstInt(ctx->ac.i32, 3, false), "");
4564 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4565 LLVMConstInt(ctx->ac.i32, 28, false), "");
4566 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4567 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4568 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4569 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4570
4571 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4572 LLVMConstInt(ctx->ac.i32, 16, false), "");
4573 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4574 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4575 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4576 samples, "");
4577 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4578 ctx->ac.i32_1, "");
4579 result = samples;
4580 goto write_result;
4581 }
4582
4583 if (coord)
4584 for (chan = 0; chan < instr->coord_components; chan++)
4585 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4586
4587 if (offsets && instr->op != nir_texop_txf) {
4588 LLVMValueRef offset[3], pack;
4589 for (chan = 0; chan < 3; ++chan)
4590 offset[chan] = ctx->ac.i32_0;
4591
4592 args.offset = true;
4593 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4594 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4595 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4596 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4597 if (chan)
4598 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4599 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4600 }
4601 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4602 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4603 address[count++] = pack;
4604
4605 }
4606 /* pack LOD bias value */
4607 if (instr->op == nir_texop_txb && bias) {
4608 address[count++] = bias;
4609 }
4610
4611 /* Pack depth comparison value */
4612 if (instr->is_shadow && comparator) {
4613 LLVMValueRef z = ac_to_float(&ctx->ac,
4614 llvm_extract_elem(&ctx->ac, comparator, 0));
4615
4616 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4617 * so the depth comparison value isn't clamped for Z16 and
4618 * Z24 anymore. Do it manually here.
4619 *
4620 * It's unnecessary if the original texture format was
4621 * Z32_FLOAT, but we don't know that here.
4622 */
4623 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4624 z = ac_build_clamp(&ctx->ac, z);
4625
4626 address[count++] = z;
4627 }
4628
4629 /* pack derivatives */
4630 if (ddx || ddy) {
4631 int num_src_deriv_channels, num_dest_deriv_channels;
4632 switch (instr->sampler_dim) {
4633 case GLSL_SAMPLER_DIM_3D:
4634 case GLSL_SAMPLER_DIM_CUBE:
4635 num_deriv_comp = 3;
4636 num_src_deriv_channels = 3;
4637 num_dest_deriv_channels = 3;
4638 break;
4639 case GLSL_SAMPLER_DIM_2D:
4640 default:
4641 num_src_deriv_channels = 2;
4642 num_dest_deriv_channels = 2;
4643 num_deriv_comp = 2;
4644 break;
4645 case GLSL_SAMPLER_DIM_1D:
4646 num_src_deriv_channels = 1;
4647 if (ctx->ac.chip_class >= GFX9) {
4648 num_dest_deriv_channels = 2;
4649 num_deriv_comp = 2;
4650 } else {
4651 num_dest_deriv_channels = 1;
4652 num_deriv_comp = 1;
4653 }
4654 break;
4655 }
4656
4657 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4658 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4659 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4660 }
4661 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4662 derivs[i] = ctx->ac.f32_0;
4663 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4664 }
4665 }
4666
4667 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4668 for (chan = 0; chan < instr->coord_components; chan++)
4669 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4670 if (instr->coord_components == 3)
4671 coords[3] = LLVMGetUndef(ctx->ac.f32);
4672 ac_prepare_cube_coords(&ctx->ac,
4673 instr->op == nir_texop_txd, instr->is_array,
4674 instr->op == nir_texop_lod, coords, derivs);
4675 if (num_deriv_comp)
4676 num_deriv_comp--;
4677 }
4678
4679 if (ddx || ddy) {
4680 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4681 address[count++] = derivs[i];
4682 }
4683
4684 /* Pack texture coordinates */
4685 if (coord) {
4686 address[count++] = coords[0];
4687 if (instr->coord_components > 1) {
4688 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4689 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4690 }
4691 address[count++] = coords[1];
4692 }
4693 if (instr->coord_components > 2) {
4694 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4695 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4696 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4697 instr->op != nir_texop_txf) {
4698 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4699 }
4700 address[count++] = coords[2];
4701 }
4702
4703 if (ctx->ac.chip_class >= GFX9) {
4704 LLVMValueRef filler;
4705 if (instr->op == nir_texop_txf)
4706 filler = ctx->ac.i32_0;
4707 else
4708 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4709
4710 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4711 /* No nir_texop_lod, because it does not take a slice
4712 * even with array textures. */
4713 if (instr->is_array && instr->op != nir_texop_lod ) {
4714 address[count] = address[count - 1];
4715 address[count - 1] = filler;
4716 count++;
4717 } else
4718 address[count++] = filler;
4719 }
4720 }
4721 }
4722
4723 /* Pack LOD */
4724 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4725 instr->op == nir_texop_txf)) {
4726 address[count++] = lod;
4727 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4728 address[count++] = sample_index;
4729 } else if(instr->op == nir_texop_txs) {
4730 count = 0;
4731 if (lod)
4732 address[count++] = lod;
4733 else
4734 address[count++] = ctx->ac.i32_0;
4735 }
4736
4737 for (chan = 0; chan < count; chan++) {
4738 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4739 address[chan], ctx->ac.i32, "");
4740 }
4741
4742 if (instr->op == nir_texop_samples_identical) {
4743 LLVMValueRef txf_address[4];
4744 struct ac_image_args txf_args = { 0 };
4745 unsigned txf_count = count;
4746 memcpy(txf_address, address, sizeof(txf_address));
4747
4748 if (!instr->is_array)
4749 txf_address[2] = ctx->ac.i32_0;
4750 txf_address[3] = ctx->ac.i32_0;
4751
4752 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4753 fmask_ptr, NULL,
4754 txf_address, txf_count, 0xf);
4755
4756 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4757
4758 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4759 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4760 goto write_result;
4761 }
4762
4763 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4764 instr->op != nir_texop_txs) {
4765 unsigned sample_chan = instr->is_array ? 3 : 2;
4766 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4767 address[0],
4768 address[1],
4769 instr->is_array ? address[2] : NULL,
4770 address[sample_chan],
4771 fmask_ptr);
4772 }
4773
4774 if (offsets && instr->op == nir_texop_txf) {
4775 nir_const_value *const_offset =
4776 nir_src_as_const_value(instr->src[const_src].src);
4777 int num_offsets = instr->src[const_src].src.ssa->num_components;
4778 assert(const_offset);
4779 num_offsets = MIN2(num_offsets, instr->coord_components);
4780 if (num_offsets > 2)
4781 address[2] = LLVMBuildAdd(ctx->ac.builder,
4782 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4783 if (num_offsets > 1)
4784 address[1] = LLVMBuildAdd(ctx->ac.builder,
4785 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4786 address[0] = LLVMBuildAdd(ctx->ac.builder,
4787 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4788
4789 }
4790
4791 /* TODO TG4 support */
4792 if (instr->op == nir_texop_tg4) {
4793 if (instr->is_shadow)
4794 dmask = 1;
4795 else
4796 dmask = 1 << instr->component;
4797 }
4798 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4799 res_ptr, samp_ptr, address, count, dmask);
4800
4801 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4802
4803 if (instr->op == nir_texop_query_levels)
4804 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4805 else if (instr->is_shadow && instr->is_new_style_shadow &&
4806 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4807 instr->op != nir_texop_tg4)
4808 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4809 else if (instr->op == nir_texop_txs &&
4810 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4811 instr->is_array) {
4812 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4813 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4814 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4815 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4816 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4817 } else if (ctx->ac.chip_class >= GFX9 &&
4818 instr->op == nir_texop_txs &&
4819 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4820 instr->is_array) {
4821 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4822 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4823 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4824 ctx->ac.i32_1, "");
4825 } else if (instr->dest.ssa.num_components != 4)
4826 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4827
4828 write_result:
4829 if (result) {
4830 assert(instr->dest.is_ssa);
4831 result = ac_to_integer(&ctx->ac, result);
4832 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4833 }
4834 }
4835
4836
4837 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4838 {
4839 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4840 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4841
4842 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4843 _mesa_hash_table_insert(ctx->phis, instr, result);
4844 }
4845
4846 static void visit_post_phi(struct ac_nir_context *ctx,
4847 nir_phi_instr *instr,
4848 LLVMValueRef llvm_phi)
4849 {
4850 nir_foreach_phi_src(src, instr) {
4851 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4852 LLVMValueRef llvm_src = get_src(ctx, src->src);
4853
4854 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4855 }
4856 }
4857
4858 static void phi_post_pass(struct ac_nir_context *ctx)
4859 {
4860 struct hash_entry *entry;
4861 hash_table_foreach(ctx->phis, entry) {
4862 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4863 (LLVMValueRef)entry->data);
4864 }
4865 }
4866
4867
4868 static void visit_ssa_undef(struct ac_nir_context *ctx,
4869 const nir_ssa_undef_instr *instr)
4870 {
4871 unsigned num_components = instr->def.num_components;
4872 LLVMValueRef undef;
4873
4874 if (num_components == 1)
4875 undef = LLVMGetUndef(ctx->ac.i32);
4876 else {
4877 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4878 }
4879 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4880 }
4881
4882 static void visit_jump(struct ac_nir_context *ctx,
4883 const nir_jump_instr *instr)
4884 {
4885 switch (instr->type) {
4886 case nir_jump_break:
4887 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4888 LLVMClearInsertionPosition(ctx->ac.builder);
4889 break;
4890 case nir_jump_continue:
4891 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4892 LLVMClearInsertionPosition(ctx->ac.builder);
4893 break;
4894 default:
4895 fprintf(stderr, "Unknown NIR jump instr: ");
4896 nir_print_instr(&instr->instr, stderr);
4897 fprintf(stderr, "\n");
4898 abort();
4899 }
4900 }
4901
4902 static void visit_cf_list(struct ac_nir_context *ctx,
4903 struct exec_list *list);
4904
4905 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4906 {
4907 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4908 nir_foreach_instr(instr, block)
4909 {
4910 switch (instr->type) {
4911 case nir_instr_type_alu:
4912 visit_alu(ctx, nir_instr_as_alu(instr));
4913 break;
4914 case nir_instr_type_load_const:
4915 visit_load_const(ctx, nir_instr_as_load_const(instr));
4916 break;
4917 case nir_instr_type_intrinsic:
4918 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4919 break;
4920 case nir_instr_type_tex:
4921 visit_tex(ctx, nir_instr_as_tex(instr));
4922 break;
4923 case nir_instr_type_phi:
4924 visit_phi(ctx, nir_instr_as_phi(instr));
4925 break;
4926 case nir_instr_type_ssa_undef:
4927 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4928 break;
4929 case nir_instr_type_jump:
4930 visit_jump(ctx, nir_instr_as_jump(instr));
4931 break;
4932 default:
4933 fprintf(stderr, "Unknown NIR instr type: ");
4934 nir_print_instr(instr, stderr);
4935 fprintf(stderr, "\n");
4936 abort();
4937 }
4938 }
4939
4940 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4941 }
4942
4943 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4944 {
4945 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4946
4947 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4948 LLVMBasicBlockRef merge_block =
4949 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4950 LLVMBasicBlockRef if_block =
4951 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4952 LLVMBasicBlockRef else_block = merge_block;
4953 if (!exec_list_is_empty(&if_stmt->else_list))
4954 else_block = LLVMAppendBasicBlockInContext(
4955 ctx->ac.context, fn, "");
4956
4957 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4958 ctx->ac.i32_0, "");
4959 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4960
4961 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4962 visit_cf_list(ctx, &if_stmt->then_list);
4963 if (LLVMGetInsertBlock(ctx->ac.builder))
4964 LLVMBuildBr(ctx->ac.builder, merge_block);
4965
4966 if (!exec_list_is_empty(&if_stmt->else_list)) {
4967 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4968 visit_cf_list(ctx, &if_stmt->else_list);
4969 if (LLVMGetInsertBlock(ctx->ac.builder))
4970 LLVMBuildBr(ctx->ac.builder, merge_block);
4971 }
4972
4973 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4974 }
4975
4976 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4977 {
4978 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4979 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4980 LLVMBasicBlockRef break_parent = ctx->break_block;
4981
4982 ctx->continue_block =
4983 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4984 ctx->break_block =
4985 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4986
4987 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4988 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4989 visit_cf_list(ctx, &loop->body);
4990
4991 if (LLVMGetInsertBlock(ctx->ac.builder))
4992 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4993 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4994
4995 ctx->continue_block = continue_parent;
4996 ctx->break_block = break_parent;
4997 }
4998
4999 static void visit_cf_list(struct ac_nir_context *ctx,
5000 struct exec_list *list)
5001 {
5002 foreach_list_typed(nir_cf_node, node, node, list)
5003 {
5004 switch (node->type) {
5005 case nir_cf_node_block:
5006 visit_block(ctx, nir_cf_node_as_block(node));
5007 break;
5008
5009 case nir_cf_node_if:
5010 visit_if(ctx, nir_cf_node_as_if(node));
5011 break;
5012
5013 case nir_cf_node_loop:
5014 visit_loop(ctx, nir_cf_node_as_loop(node));
5015 break;
5016
5017 default:
5018 assert(0);
5019 }
5020 }
5021 }
5022
5023 static void
5024 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5025 struct nir_variable *variable)
5026 {
5027 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5028 LLVMValueRef t_offset;
5029 LLVMValueRef t_list;
5030 LLVMValueRef input;
5031 LLVMValueRef buffer_index;
5032 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5033 int idx = variable->data.location;
5034 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5035
5036 variable->data.driver_location = idx * 4;
5037
5038 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5039 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5040 ctx->abi.start_instance, "");
5041 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5042 ctx->shader_info->vs.vgpr_comp_cnt);
5043 } else
5044 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5045 ctx->abi.base_vertex, "");
5046
5047 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5048 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5049
5050 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5051
5052 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5053 buffer_index,
5054 ctx->ac.i32_0,
5055 true);
5056
5057 for (unsigned chan = 0; chan < 4; chan++) {
5058 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5059 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5060 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5061 input, llvm_chan, ""));
5062 }
5063 }
5064 }
5065
5066 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5067 unsigned attr,
5068 LLVMValueRef interp_param,
5069 LLVMValueRef prim_mask,
5070 LLVMValueRef result[4])
5071 {
5072 LLVMValueRef attr_number;
5073 unsigned chan;
5074 LLVMValueRef i, j;
5075 bool interp = interp_param != NULL;
5076
5077 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5078
5079 /* fs.constant returns the param from the middle vertex, so it's not
5080 * really useful for flat shading. It's meant to be used for custom
5081 * interpolation (but the intrinsic can't fetch from the other two
5082 * vertices).
5083 *
5084 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5085 * to do the right thing. The only reason we use fs.constant is that
5086 * fs.interp cannot be used on integers, because they can be equal
5087 * to NaN.
5088 */
5089 if (interp) {
5090 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5091 ctx->ac.v2f32, "");
5092
5093 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5094 ctx->ac.i32_0, "");
5095 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5096 ctx->ac.i32_1, "");
5097 }
5098
5099 for (chan = 0; chan < 4; chan++) {
5100 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5101
5102 if (interp) {
5103 result[chan] = ac_build_fs_interp(&ctx->ac,
5104 llvm_chan,
5105 attr_number,
5106 prim_mask, i, j);
5107 } else {
5108 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5109 LLVMConstInt(ctx->ac.i32, 2, false),
5110 llvm_chan,
5111 attr_number,
5112 prim_mask);
5113 }
5114 }
5115 }
5116
5117 static void
5118 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5119 struct nir_variable *variable)
5120 {
5121 int idx = variable->data.location;
5122 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5123 LLVMValueRef interp;
5124
5125 variable->data.driver_location = idx * 4;
5126 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5127
5128 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5129 unsigned interp_type;
5130 if (variable->data.sample) {
5131 interp_type = INTERP_SAMPLE;
5132 ctx->shader_info->info.ps.force_persample = true;
5133 } else if (variable->data.centroid)
5134 interp_type = INTERP_CENTROID;
5135 else
5136 interp_type = INTERP_CENTER;
5137
5138 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5139 } else
5140 interp = NULL;
5141
5142 for (unsigned i = 0; i < attrib_count; ++i)
5143 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5144
5145 }
5146
5147 static void
5148 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5149 struct nir_shader *nir) {
5150 nir_foreach_variable(variable, &nir->inputs)
5151 handle_vs_input_decl(ctx, variable);
5152 }
5153
5154 static void
5155 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5156 struct nir_shader *nir)
5157 {
5158 if (!ctx->options->key.fs.multisample)
5159 return;
5160
5161 bool uses_center = false;
5162 bool uses_centroid = false;
5163 nir_foreach_variable(variable, &nir->inputs) {
5164 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5165 variable->data.sample)
5166 continue;
5167
5168 if (variable->data.centroid)
5169 uses_centroid = true;
5170 else
5171 uses_center = true;
5172 }
5173
5174 if (uses_center && uses_centroid) {
5175 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5176 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5177 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5178 }
5179 }
5180
5181 static void
5182 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5183 struct nir_shader *nir)
5184 {
5185 prepare_interp_optimize(ctx, nir);
5186
5187 nir_foreach_variable(variable, &nir->inputs)
5188 handle_fs_input_decl(ctx, variable);
5189
5190 unsigned index = 0;
5191
5192 if (ctx->shader_info->info.ps.uses_input_attachments ||
5193 ctx->shader_info->info.needs_multiview_view_index)
5194 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5195
5196 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5197 LLVMValueRef interp_param;
5198 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5199
5200 if (!(ctx->input_mask & (1ull << i)))
5201 continue;
5202
5203 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5204 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5205 interp_param = *inputs;
5206 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5207 inputs);
5208
5209 if (!interp_param)
5210 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5211 ++index;
5212 } else if (i == VARYING_SLOT_POS) {
5213 for(int i = 0; i < 3; ++i)
5214 inputs[i] = ctx->abi.frag_pos[i];
5215
5216 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5217 ctx->abi.frag_pos[3]);
5218 }
5219 }
5220 ctx->shader_info->fs.num_interp = index;
5221 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5222 ctx->shader_info->fs.has_pcoord = true;
5223 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5224 ctx->shader_info->fs.prim_id_input = true;
5225 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5226 ctx->shader_info->fs.layer_input = true;
5227 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5228
5229 if (ctx->shader_info->info.needs_multiview_view_index)
5230 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5231 }
5232
5233 static LLVMValueRef
5234 ac_build_alloca(struct ac_llvm_context *ac,
5235 LLVMTypeRef type,
5236 const char *name)
5237 {
5238 LLVMBuilderRef builder = ac->builder;
5239 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5240 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5241 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5242 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5243 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5244 LLVMValueRef res;
5245
5246 if (first_instr) {
5247 LLVMPositionBuilderBefore(first_builder, first_instr);
5248 } else {
5249 LLVMPositionBuilderAtEnd(first_builder, first_block);
5250 }
5251
5252 res = LLVMBuildAlloca(first_builder, type, name);
5253 LLVMBuildStore(builder, LLVMConstNull(type), res);
5254
5255 LLVMDisposeBuilder(first_builder);
5256
5257 return res;
5258 }
5259
5260 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5261 LLVMTypeRef type,
5262 const char *name)
5263 {
5264 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5265 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5266 return ptr;
5267 }
5268
5269 static void
5270 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5271 struct nir_variable *variable,
5272 struct nir_shader *shader,
5273 gl_shader_stage stage)
5274 {
5275 int idx = variable->data.location + variable->data.index;
5276 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5277 uint64_t mask_attribs;
5278
5279 variable->data.driver_location = idx * 4;
5280
5281 /* tess ctrl has it's own load/store paths for outputs */
5282 if (stage == MESA_SHADER_TESS_CTRL)
5283 return;
5284
5285 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5286 if (stage == MESA_SHADER_VERTEX ||
5287 stage == MESA_SHADER_TESS_EVAL ||
5288 stage == MESA_SHADER_GEOMETRY) {
5289 if (idx == VARYING_SLOT_CLIP_DIST0) {
5290 int length = shader->info.clip_distance_array_size +
5291 shader->info.cull_distance_array_size;
5292 if (stage == MESA_SHADER_VERTEX) {
5293 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5294 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5295 }
5296 if (stage == MESA_SHADER_TESS_EVAL) {
5297 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5298 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5299 }
5300
5301 if (length > 4)
5302 attrib_count = 2;
5303 else
5304 attrib_count = 1;
5305 mask_attribs = 1ull << idx;
5306 }
5307 }
5308
5309 ctx->output_mask |= mask_attribs;
5310 }
5311
5312 static void
5313 handle_shader_output_decl(struct ac_nir_context *ctx,
5314 struct nir_shader *nir,
5315 struct nir_variable *variable)
5316 {
5317 unsigned output_loc = variable->data.driver_location / 4;
5318 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5319
5320 /* tess ctrl has it's own load/store paths for outputs */
5321 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5322 return;
5323
5324 if (ctx->stage == MESA_SHADER_VERTEX ||
5325 ctx->stage == MESA_SHADER_TESS_EVAL ||
5326 ctx->stage == MESA_SHADER_GEOMETRY) {
5327 int idx = variable->data.location + variable->data.index;
5328 if (idx == VARYING_SLOT_CLIP_DIST0) {
5329 int length = nir->info.clip_distance_array_size +
5330 nir->info.cull_distance_array_size;
5331
5332 if (length > 4)
5333 attrib_count = 2;
5334 else
5335 attrib_count = 1;
5336 }
5337 }
5338
5339 for (unsigned i = 0; i < attrib_count; ++i) {
5340 for (unsigned chan = 0; chan < 4; chan++) {
5341 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5342 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5343 }
5344 }
5345 }
5346
5347 static LLVMTypeRef
5348 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5349 enum glsl_base_type type)
5350 {
5351 switch (type) {
5352 case GLSL_TYPE_INT:
5353 case GLSL_TYPE_UINT:
5354 case GLSL_TYPE_BOOL:
5355 case GLSL_TYPE_SUBROUTINE:
5356 return ctx->ac.i32;
5357 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5358 return ctx->ac.f32;
5359 case GLSL_TYPE_INT64:
5360 case GLSL_TYPE_UINT64:
5361 return ctx->ac.i64;
5362 case GLSL_TYPE_DOUBLE:
5363 return ctx->ac.f64;
5364 default:
5365 unreachable("unknown GLSL type");
5366 }
5367 }
5368
5369 static LLVMTypeRef
5370 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5371 const struct glsl_type *type)
5372 {
5373 if (glsl_type_is_scalar(type)) {
5374 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5375 }
5376
5377 if (glsl_type_is_vector(type)) {
5378 return LLVMVectorType(
5379 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5380 glsl_get_vector_elements(type));
5381 }
5382
5383 if (glsl_type_is_matrix(type)) {
5384 return LLVMArrayType(
5385 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5386 glsl_get_matrix_columns(type));
5387 }
5388
5389 if (glsl_type_is_array(type)) {
5390 return LLVMArrayType(
5391 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5392 glsl_get_length(type));
5393 }
5394
5395 assert(glsl_type_is_struct(type));
5396
5397 LLVMTypeRef member_types[glsl_get_length(type)];
5398
5399 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5400 member_types[i] =
5401 glsl_to_llvm_type(ctx,
5402 glsl_get_struct_field(type, i));
5403 }
5404
5405 return LLVMStructTypeInContext(ctx->context, member_types,
5406 glsl_get_length(type), false);
5407 }
5408
5409 static void
5410 setup_locals(struct ac_nir_context *ctx,
5411 struct nir_function *func)
5412 {
5413 int i, j;
5414 ctx->num_locals = 0;
5415 nir_foreach_variable(variable, &func->impl->locals) {
5416 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5417 variable->data.driver_location = ctx->num_locals * 4;
5418 ctx->num_locals += attrib_count;
5419 }
5420 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5421 if (!ctx->locals)
5422 return;
5423
5424 for (i = 0; i < ctx->num_locals; i++) {
5425 for (j = 0; j < 4; j++) {
5426 ctx->locals[i * 4 + j] =
5427 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5428 }
5429 }
5430 }
5431
5432 static void
5433 setup_shared(struct ac_nir_context *ctx,
5434 struct nir_shader *nir)
5435 {
5436 nir_foreach_variable(variable, &nir->shared) {
5437 LLVMValueRef shared =
5438 LLVMAddGlobalInAddressSpace(
5439 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5440 variable->name ? variable->name : "",
5441 LOCAL_ADDR_SPACE);
5442 _mesa_hash_table_insert(ctx->vars, variable, shared);
5443 }
5444 }
5445
5446 static LLVMValueRef
5447 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5448 {
5449 v = ac_to_float(ctx, v);
5450 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5451 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5452 }
5453
5454
5455 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5456 LLVMValueRef src0, LLVMValueRef src1)
5457 {
5458 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5459 LLVMValueRef comp[2];
5460
5461 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5462 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5463 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5464 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5465 }
5466
5467 /* Initialize arguments for the shader export intrinsic */
5468 static void
5469 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5470 LLVMValueRef *values,
5471 unsigned target,
5472 struct ac_export_args *args)
5473 {
5474 /* Default is 0xf. Adjusted below depending on the format. */
5475 args->enabled_channels = 0xf;
5476
5477 /* Specify whether the EXEC mask represents the valid mask */
5478 args->valid_mask = 0;
5479
5480 /* Specify whether this is the last export */
5481 args->done = 0;
5482
5483 /* Specify the target we are exporting */
5484 args->target = target;
5485
5486 args->compr = false;
5487 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5488 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5489 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5490 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5491
5492 if (!values)
5493 return;
5494
5495 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5496 LLVMValueRef val[4];
5497 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5498 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5499 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5500 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5501
5502 switch(col_format) {
5503 case V_028714_SPI_SHADER_ZERO:
5504 args->enabled_channels = 0; /* writemask */
5505 args->target = V_008DFC_SQ_EXP_NULL;
5506 break;
5507
5508 case V_028714_SPI_SHADER_32_R:
5509 args->enabled_channels = 1;
5510 args->out[0] = values[0];
5511 break;
5512
5513 case V_028714_SPI_SHADER_32_GR:
5514 args->enabled_channels = 0x3;
5515 args->out[0] = values[0];
5516 args->out[1] = values[1];
5517 break;
5518
5519 case V_028714_SPI_SHADER_32_AR:
5520 args->enabled_channels = 0x9;
5521 args->out[0] = values[0];
5522 args->out[3] = values[3];
5523 break;
5524
5525 case V_028714_SPI_SHADER_FP16_ABGR:
5526 args->compr = 1;
5527
5528 for (unsigned chan = 0; chan < 2; chan++) {
5529 LLVMValueRef pack_args[2] = {
5530 values[2 * chan],
5531 values[2 * chan + 1]
5532 };
5533 LLVMValueRef packed;
5534
5535 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5536 args->out[chan] = packed;
5537 }
5538 break;
5539
5540 case V_028714_SPI_SHADER_UNORM16_ABGR:
5541 for (unsigned chan = 0; chan < 4; chan++) {
5542 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5543 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5544 LLVMConstReal(ctx->ac.f32, 65535), "");
5545 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5546 LLVMConstReal(ctx->ac.f32, 0.5), "");
5547 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5548 ctx->ac.i32, "");
5549 }
5550
5551 args->compr = 1;
5552 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5553 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5554 break;
5555
5556 case V_028714_SPI_SHADER_SNORM16_ABGR:
5557 for (unsigned chan = 0; chan < 4; chan++) {
5558 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5559 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5560 LLVMConstReal(ctx->ac.f32, 32767), "");
5561
5562 /* If positive, add 0.5, else add -0.5. */
5563 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5564 LLVMBuildSelect(ctx->builder,
5565 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5566 val[chan], ctx->ac.f32_0, ""),
5567 LLVMConstReal(ctx->ac.f32, 0.5),
5568 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5569 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5570 }
5571
5572 args->compr = 1;
5573 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5574 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5575 break;
5576
5577 case V_028714_SPI_SHADER_UINT16_ABGR: {
5578 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5579 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5580 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5581
5582 for (unsigned chan = 0; chan < 4; chan++) {
5583 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5584 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5585 }
5586
5587 args->compr = 1;
5588 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5589 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5590 break;
5591 }
5592
5593 case V_028714_SPI_SHADER_SINT16_ABGR: {
5594 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5595 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5596 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5597 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5598 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5599 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5600
5601 /* Clamp. */
5602 for (unsigned chan = 0; chan < 4; chan++) {
5603 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5604 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5605 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5606 }
5607
5608 args->compr = 1;
5609 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5610 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5611 break;
5612 }
5613
5614 default:
5615 case V_028714_SPI_SHADER_32_ABGR:
5616 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5617 break;
5618 }
5619 } else
5620 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5621
5622 for (unsigned i = 0; i < 4; ++i)
5623 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5624 }
5625
5626 static void
5627 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5628 bool export_prim_id,
5629 struct ac_vs_output_info *outinfo)
5630 {
5631 uint32_t param_count = 0;
5632 unsigned target;
5633 unsigned pos_idx, num_pos_exports = 0;
5634 struct ac_export_args args, pos_args[4] = {};
5635 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5636 int i;
5637
5638 if (ctx->options->key.has_multiview_view_index) {
5639 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5640 if(!*tmp_out) {
5641 for(unsigned i = 0; i < 4; ++i)
5642 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5643 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5644 }
5645
5646 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5647 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5648 }
5649
5650 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5651 sizeof(outinfo->vs_output_param_offset));
5652
5653 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5654 LLVMValueRef slots[8];
5655 unsigned j;
5656
5657 if (outinfo->cull_dist_mask)
5658 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5659
5660 i = VARYING_SLOT_CLIP_DIST0;
5661 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5662 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5663 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5664
5665 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5666 slots[i] = LLVMGetUndef(ctx->ac.f32);
5667
5668 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5669 target = V_008DFC_SQ_EXP_POS + 3;
5670 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5671 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5672 &args, sizeof(args));
5673 }
5674
5675 target = V_008DFC_SQ_EXP_POS + 2;
5676 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5677 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5678 &args, sizeof(args));
5679
5680 }
5681
5682 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5683 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5684 for (unsigned j = 0; j < 4; j++)
5685 pos_values[j] = LLVMBuildLoad(ctx->builder,
5686 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5687 }
5688 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5689
5690 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5691 outinfo->writes_pointsize = true;
5692 psize_value = LLVMBuildLoad(ctx->builder,
5693 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5694 }
5695
5696 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5697 outinfo->writes_layer = true;
5698 layer_value = LLVMBuildLoad(ctx->builder,
5699 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5700 }
5701
5702 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5703 outinfo->writes_viewport_index = true;
5704 viewport_index_value = LLVMBuildLoad(ctx->builder,
5705 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5706 }
5707
5708 if (outinfo->writes_pointsize ||
5709 outinfo->writes_layer ||
5710 outinfo->writes_viewport_index) {
5711 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5712 (outinfo->writes_layer == true ? 4 : 0));
5713 pos_args[1].valid_mask = 0;
5714 pos_args[1].done = 0;
5715 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5716 pos_args[1].compr = 0;
5717 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5718 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5719 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5720 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5721
5722 if (outinfo->writes_pointsize == true)
5723 pos_args[1].out[0] = psize_value;
5724 if (outinfo->writes_layer == true)
5725 pos_args[1].out[2] = layer_value;
5726 if (outinfo->writes_viewport_index == true) {
5727 if (ctx->options->chip_class >= GFX9) {
5728 /* GFX9 has the layer in out.z[10:0] and the viewport
5729 * index in out.z[19:16].
5730 */
5731 LLVMValueRef v = viewport_index_value;
5732 v = ac_to_integer(&ctx->ac, v);
5733 v = LLVMBuildShl(ctx->builder, v,
5734 LLVMConstInt(ctx->ac.i32, 16, false),
5735 "");
5736 v = LLVMBuildOr(ctx->builder, v,
5737 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5738
5739 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5740 pos_args[1].enabled_channels |= 1 << 2;
5741 } else {
5742 pos_args[1].out[3] = viewport_index_value;
5743 pos_args[1].enabled_channels |= 1 << 3;
5744 }
5745 }
5746 }
5747 for (i = 0; i < 4; i++) {
5748 if (pos_args[i].out[0])
5749 num_pos_exports++;
5750 }
5751
5752 pos_idx = 0;
5753 for (i = 0; i < 4; i++) {
5754 if (!pos_args[i].out[0])
5755 continue;
5756
5757 /* Specify the target we are exporting */
5758 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5759 if (pos_idx == num_pos_exports)
5760 pos_args[i].done = 1;
5761 ac_build_export(&ctx->ac, &pos_args[i]);
5762 }
5763
5764 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5765 LLVMValueRef values[4];
5766 if (!(ctx->output_mask & (1ull << i)))
5767 continue;
5768
5769 for (unsigned j = 0; j < 4; j++)
5770 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5771 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5772
5773 if (i == VARYING_SLOT_LAYER) {
5774 target = V_008DFC_SQ_EXP_PARAM + param_count;
5775 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5776 param_count++;
5777 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5778 target = V_008DFC_SQ_EXP_PARAM + param_count;
5779 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5780 param_count++;
5781 } else if (i >= VARYING_SLOT_VAR0) {
5782 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5783 target = V_008DFC_SQ_EXP_PARAM + param_count;
5784 outinfo->vs_output_param_offset[i] = param_count;
5785 param_count++;
5786 } else
5787 continue;
5788
5789 si_llvm_init_export_args(ctx, values, target, &args);
5790
5791 if (target >= V_008DFC_SQ_EXP_POS &&
5792 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5793 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5794 &args, sizeof(args));
5795 } else {
5796 ac_build_export(&ctx->ac, &args);
5797 }
5798 }
5799
5800 if (export_prim_id) {
5801 LLVMValueRef values[4];
5802 target = V_008DFC_SQ_EXP_PARAM + param_count;
5803 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5804 param_count++;
5805
5806 values[0] = ctx->vs_prim_id;
5807 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5808 ctx->shader_info->vs.vgpr_comp_cnt);
5809 for (unsigned j = 1; j < 4; j++)
5810 values[j] = ctx->ac.f32_0;
5811 si_llvm_init_export_args(ctx, values, target, &args);
5812 ac_build_export(&ctx->ac, &args);
5813 outinfo->export_prim_id = true;
5814 }
5815
5816 outinfo->pos_exports = num_pos_exports;
5817 outinfo->param_exports = param_count;
5818 }
5819
5820 static void
5821 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5822 struct ac_es_output_info *outinfo)
5823 {
5824 int j;
5825 uint64_t max_output_written = 0;
5826 LLVMValueRef lds_base = NULL;
5827
5828 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5829 int param_index;
5830 int length = 4;
5831
5832 if (!(ctx->output_mask & (1ull << i)))
5833 continue;
5834
5835 if (i == VARYING_SLOT_CLIP_DIST0)
5836 length = ctx->num_output_clips + ctx->num_output_culls;
5837
5838 param_index = shader_io_get_unique_index(i);
5839
5840 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5841 }
5842
5843 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5844
5845 if (ctx->ac.chip_class >= GFX9) {
5846 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5847 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5848 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5849 LLVMConstInt(ctx->ac.i32, 24, false),
5850 LLVMConstInt(ctx->ac.i32, 4, false), false);
5851 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5852 LLVMBuildMul(ctx->ac.builder, wave_idx,
5853 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5854 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5855 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5856 }
5857
5858 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5859 LLVMValueRef dw_addr;
5860 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5861 int param_index;
5862 int length = 4;
5863
5864 if (!(ctx->output_mask & (1ull << i)))
5865 continue;
5866
5867 if (i == VARYING_SLOT_CLIP_DIST0)
5868 length = ctx->num_output_clips + ctx->num_output_culls;
5869
5870 param_index = shader_io_get_unique_index(i);
5871
5872 if (lds_base) {
5873 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5874 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
5875 "");
5876 }
5877 for (j = 0; j < length; j++) {
5878 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5879 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
5880
5881 if (ctx->ac.chip_class >= GFX9) {
5882 ac_lds_store(&ctx->ac, dw_addr,
5883 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5884 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5885 } else {
5886 ac_build_buffer_store_dword(&ctx->ac,
5887 ctx->esgs_ring,
5888 out_val, 1,
5889 NULL, ctx->es2gs_offset,
5890 (4 * param_index + j) * 4,
5891 1, 1, true, true);
5892 }
5893 }
5894 }
5895 }
5896
5897 static void
5898 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5899 {
5900 LLVMValueRef vertex_id = ctx->rel_auto_id;
5901 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5902 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5903 vertex_dw_stride, "");
5904
5905 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5906 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5907 int length = 4;
5908
5909 if (!(ctx->output_mask & (1ull << i)))
5910 continue;
5911
5912 if (i == VARYING_SLOT_CLIP_DIST0)
5913 length = ctx->num_output_clips + ctx->num_output_culls;
5914 int param = shader_io_get_unique_index(i);
5915 mark_tess_output(ctx, false, param);
5916 if (length > 4)
5917 mark_tess_output(ctx, false, param + 1);
5918 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5919 LLVMConstInt(ctx->ac.i32, param * 4, false),
5920 "");
5921 for (unsigned j = 0; j < length; j++) {
5922 ac_lds_store(&ctx->ac, dw_addr,
5923 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5924 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5925 }
5926 }
5927 }
5928
5929 struct ac_build_if_state
5930 {
5931 struct nir_to_llvm_context *ctx;
5932 LLVMValueRef condition;
5933 LLVMBasicBlockRef entry_block;
5934 LLVMBasicBlockRef true_block;
5935 LLVMBasicBlockRef false_block;
5936 LLVMBasicBlockRef merge_block;
5937 };
5938
5939 static LLVMBasicBlockRef
5940 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5941 {
5942 LLVMBasicBlockRef current_block;
5943 LLVMBasicBlockRef next_block;
5944 LLVMBasicBlockRef new_block;
5945
5946 /* get current basic block */
5947 current_block = LLVMGetInsertBlock(ctx->builder);
5948
5949 /* chqeck if there's another block after this one */
5950 next_block = LLVMGetNextBasicBlock(current_block);
5951 if (next_block) {
5952 /* insert the new block before the next block */
5953 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5954 }
5955 else {
5956 /* append new block after current block */
5957 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5958 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5959 }
5960 return new_block;
5961 }
5962
5963 static void
5964 ac_nir_build_if(struct ac_build_if_state *ifthen,
5965 struct nir_to_llvm_context *ctx,
5966 LLVMValueRef condition)
5967 {
5968 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5969
5970 memset(ifthen, 0, sizeof *ifthen);
5971 ifthen->ctx = ctx;
5972 ifthen->condition = condition;
5973 ifthen->entry_block = block;
5974
5975 /* create endif/merge basic block for the phi functions */
5976 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5977
5978 /* create/insert true_block before merge_block */
5979 ifthen->true_block =
5980 LLVMInsertBasicBlockInContext(ctx->context,
5981 ifthen->merge_block,
5982 "if-true-block");
5983
5984 /* successive code goes into the true block */
5985 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5986 }
5987
5988 /**
5989 * End a conditional.
5990 */
5991 static void
5992 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5993 {
5994 LLVMBuilderRef builder = ifthen->ctx->builder;
5995
5996 /* Insert branch to the merge block from current block */
5997 LLVMBuildBr(builder, ifthen->merge_block);
5998
5999 /*
6000 * Now patch in the various branch instructions.
6001 */
6002
6003 /* Insert the conditional branch instruction at the end of entry_block */
6004 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6005 if (ifthen->false_block) {
6006 /* we have an else clause */
6007 LLVMBuildCondBr(builder, ifthen->condition,
6008 ifthen->true_block, ifthen->false_block);
6009 }
6010 else {
6011 /* no else clause */
6012 LLVMBuildCondBr(builder, ifthen->condition,
6013 ifthen->true_block, ifthen->merge_block);
6014 }
6015
6016 /* Resume building code at end of the ifthen->merge_block */
6017 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6018 }
6019
6020 static void
6021 write_tess_factors(struct nir_to_llvm_context *ctx)
6022 {
6023 unsigned stride, outer_comps, inner_comps;
6024 struct ac_build_if_state if_ctx, inner_if_ctx;
6025 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6026 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6027 unsigned tess_inner_index, tess_outer_index;
6028 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6029 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6030 int i;
6031 emit_barrier(ctx);
6032
6033 switch (ctx->options->key.tcs.primitive_mode) {
6034 case GL_ISOLINES:
6035 stride = 2;
6036 outer_comps = 2;
6037 inner_comps = 0;
6038 break;
6039 case GL_TRIANGLES:
6040 stride = 4;
6041 outer_comps = 3;
6042 inner_comps = 1;
6043 break;
6044 case GL_QUADS:
6045 stride = 6;
6046 outer_comps = 4;
6047 inner_comps = 2;
6048 break;
6049 default:
6050 return;
6051 }
6052
6053 ac_nir_build_if(&if_ctx, ctx,
6054 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6055 invocation_id, ctx->ac.i32_0, ""));
6056
6057 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6058 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6059
6060 mark_tess_output(ctx, true, tess_inner_index);
6061 mark_tess_output(ctx, true, tess_outer_index);
6062 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6063 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6064 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6065 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6066 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6067
6068 for (i = 0; i < 4; i++) {
6069 inner[i] = LLVMGetUndef(ctx->ac.i32);
6070 outer[i] = LLVMGetUndef(ctx->ac.i32);
6071 }
6072
6073 // LINES reverseal
6074 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6075 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6076 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6077 ctx->ac.i32_1, "");
6078 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6079 } else {
6080 for (i = 0; i < outer_comps; i++) {
6081 outer[i] = out[i] =
6082 ac_lds_load(&ctx->ac, lds_outer);
6083 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6084 ctx->ac.i32_1, "");
6085 }
6086 for (i = 0; i < inner_comps; i++) {
6087 inner[i] = out[outer_comps+i] =
6088 ac_lds_load(&ctx->ac, lds_inner);
6089 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6090 ctx->ac.i32_1, "");
6091 }
6092 }
6093
6094 /* Convert the outputs to vectors for stores. */
6095 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6096 vec1 = NULL;
6097
6098 if (stride > 4)
6099 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6100
6101
6102 buffer = ctx->hs_ring_tess_factor;
6103 tf_base = ctx->tess_factor_offset;
6104 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6105 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6106 unsigned tf_offset = 0;
6107
6108 if (ctx->options->chip_class <= VI) {
6109 ac_nir_build_if(&inner_if_ctx, ctx,
6110 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6111 rel_patch_id, ctx->ac.i32_0, ""));
6112
6113 /* Store the dynamic HS control word. */
6114 ac_build_buffer_store_dword(&ctx->ac, buffer,
6115 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6116 1, ctx->ac.i32_0, tf_base,
6117 0, 1, 0, true, false);
6118 tf_offset += 4;
6119
6120 ac_nir_build_endif(&inner_if_ctx);
6121 }
6122
6123 /* Store the tessellation factors. */
6124 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6125 MIN2(stride, 4), byteoffset, tf_base,
6126 tf_offset, 1, 0, true, false);
6127 if (vec1)
6128 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6129 stride - 4, byteoffset, tf_base,
6130 16 + tf_offset, 1, 0, true, false);
6131
6132 //store to offchip for TES to read - only if TES reads them
6133 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6134 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6135 LLVMValueRef tf_inner_offset;
6136 unsigned param_outer, param_inner;
6137
6138 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6139 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6140 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6141
6142 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6143 util_next_power_of_two(outer_comps));
6144
6145 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6146 outer_comps, tf_outer_offset,
6147 ctx->oc_lds, 0, 1, 0, true, false);
6148 if (inner_comps) {
6149 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6150 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6151 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6152
6153 inner_vec = inner_comps == 1 ? inner[0] :
6154 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6155 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6156 inner_comps, tf_inner_offset,
6157 ctx->oc_lds, 0, 1, 0, true, false);
6158 }
6159 }
6160 ac_nir_build_endif(&if_ctx);
6161 }
6162
6163 static void
6164 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6165 {
6166 write_tess_factors(ctx);
6167 }
6168
6169 static bool
6170 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6171 LLVMValueRef *color, unsigned param, bool is_last,
6172 struct ac_export_args *args)
6173 {
6174 /* Export */
6175 si_llvm_init_export_args(ctx, color, param,
6176 args);
6177
6178 if (is_last) {
6179 args->valid_mask = 1; /* whether the EXEC mask is valid */
6180 args->done = 1; /* DONE bit */
6181 } else if (!args->enabled_channels)
6182 return false; /* unnecessary NULL export */
6183
6184 return true;
6185 }
6186
6187 static void
6188 si_export_mrt_z(struct nir_to_llvm_context *ctx,
6189 LLVMValueRef depth, LLVMValueRef stencil,
6190 LLVMValueRef samplemask)
6191 {
6192 struct ac_export_args args;
6193
6194 args.enabled_channels = 0;
6195 args.valid_mask = 1;
6196 args.done = 1;
6197 args.target = V_008DFC_SQ_EXP_MRTZ;
6198 args.compr = false;
6199
6200 args.out[0] = LLVMGetUndef(ctx->ac.f32); /* R, depth */
6201 args.out[1] = LLVMGetUndef(ctx->ac.f32); /* G, stencil test val[0:7], stencil op val[8:15] */
6202 args.out[2] = LLVMGetUndef(ctx->ac.f32); /* B, sample mask */
6203 args.out[3] = LLVMGetUndef(ctx->ac.f32); /* A, alpha to mask */
6204
6205 unsigned format = ac_get_spi_shader_z_format(depth != NULL,
6206 stencil != NULL,
6207 samplemask != NULL);
6208
6209 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
6210 assert(!depth);
6211 args.compr = 1; /* COMPR flag */
6212
6213 if (stencil) {
6214 /* Stencil should be in X[23:16]. */
6215 stencil = ac_to_integer(&ctx->ac, stencil);
6216 stencil = LLVMBuildShl(ctx->builder, stencil,
6217 LLVMConstInt(ctx->ac.i32, 16, 0), "");
6218 args.out[0] = ac_to_float(&ctx->ac, stencil);
6219 args.enabled_channels |= 0x3;
6220 }
6221 if (samplemask) {
6222 /* SampleMask should be in Y[15:0]. */
6223 args.out[1] = samplemask;
6224 args.enabled_channels |= 0xc;
6225 }
6226 } else {
6227 if (depth) {
6228 args.out[0] = depth;
6229 args.enabled_channels |= 0x1;
6230 }
6231
6232 if (stencil) {
6233 args.out[1] = stencil;
6234 args.enabled_channels |= 0x2;
6235 }
6236
6237 if (samplemask) {
6238 args.out[2] = samplemask;
6239 args.enabled_channels |= 0x4;
6240 }
6241 }
6242
6243 /* SI (except OLAND and HAINAN) has a bug that it only looks
6244 * at the X writemask component. */
6245 if (ctx->options->chip_class == SI &&
6246 ctx->options->family != CHIP_OLAND &&
6247 ctx->options->family != CHIP_HAINAN)
6248 args.enabled_channels |= 0x1;
6249
6250 ac_build_export(&ctx->ac, &args);
6251 }
6252
6253 static void
6254 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6255 {
6256 unsigned index = 0;
6257 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6258 struct ac_export_args color_args[8];
6259
6260 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6261 LLVMValueRef values[4];
6262
6263 if (!(ctx->output_mask & (1ull << i)))
6264 continue;
6265
6266 if (i == FRAG_RESULT_DEPTH) {
6267 ctx->shader_info->fs.writes_z = true;
6268 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6269 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6270 } else if (i == FRAG_RESULT_STENCIL) {
6271 ctx->shader_info->fs.writes_stencil = true;
6272 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6273 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6274 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6275 ctx->shader_info->fs.writes_sample_mask = true;
6276 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6277 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6278 } else {
6279 bool last = false;
6280 for (unsigned j = 0; j < 4; j++)
6281 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6282 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6283
6284 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6285 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6286
6287 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6288 if (ret)
6289 index++;
6290 }
6291 }
6292
6293 for (unsigned i = 0; i < index; i++)
6294 ac_build_export(&ctx->ac, &color_args[i]);
6295 if (depth || stencil || samplemask)
6296 si_export_mrt_z(ctx, depth, stencil, samplemask);
6297 else if (!index) {
6298 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6299 ac_build_export(&ctx->ac, &color_args[0]);
6300 }
6301
6302 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6303 }
6304
6305 static void
6306 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6307 {
6308 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6309 }
6310
6311 static void
6312 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6313 LLVMValueRef *addrs)
6314 {
6315 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6316
6317 switch (ctx->stage) {
6318 case MESA_SHADER_VERTEX:
6319 if (ctx->options->key.vs.as_ls)
6320 handle_ls_outputs_post(ctx);
6321 else if (ctx->options->key.vs.as_es)
6322 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6323 else
6324 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6325 &ctx->shader_info->vs.outinfo);
6326 break;
6327 case MESA_SHADER_FRAGMENT:
6328 handle_fs_outputs_post(ctx);
6329 break;
6330 case MESA_SHADER_GEOMETRY:
6331 emit_gs_epilogue(ctx);
6332 break;
6333 case MESA_SHADER_TESS_CTRL:
6334 handle_tcs_outputs_post(ctx);
6335 break;
6336 case MESA_SHADER_TESS_EVAL:
6337 if (ctx->options->key.tes.as_es)
6338 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6339 else
6340 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6341 &ctx->shader_info->tes.outinfo);
6342 break;
6343 default:
6344 break;
6345 }
6346 }
6347
6348 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6349 {
6350 LLVMPassManagerRef passmgr;
6351 /* Create the pass manager */
6352 passmgr = LLVMCreateFunctionPassManagerForModule(
6353 ctx->module);
6354
6355 /* This pass should eliminate all the load and store instructions */
6356 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6357
6358 /* Add some optimization passes */
6359 LLVMAddScalarReplAggregatesPass(passmgr);
6360 LLVMAddLICMPass(passmgr);
6361 LLVMAddAggressiveDCEPass(passmgr);
6362 LLVMAddCFGSimplificationPass(passmgr);
6363 LLVMAddInstructionCombiningPass(passmgr);
6364
6365 /* Run the pass */
6366 LLVMInitializeFunctionPassManager(passmgr);
6367 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6368 LLVMFinalizeFunctionPassManager(passmgr);
6369
6370 LLVMDisposeBuilder(ctx->builder);
6371 LLVMDisposePassManager(passmgr);
6372 }
6373
6374 static void
6375 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6376 {
6377 struct ac_vs_output_info *outinfo;
6378
6379 switch (ctx->stage) {
6380 case MESA_SHADER_FRAGMENT:
6381 case MESA_SHADER_COMPUTE:
6382 case MESA_SHADER_TESS_CTRL:
6383 case MESA_SHADER_GEOMETRY:
6384 return;
6385 case MESA_SHADER_VERTEX:
6386 if (ctx->options->key.vs.as_ls ||
6387 ctx->options->key.vs.as_es)
6388 return;
6389 outinfo = &ctx->shader_info->vs.outinfo;
6390 break;
6391 case MESA_SHADER_TESS_EVAL:
6392 if (ctx->options->key.vs.as_es)
6393 return;
6394 outinfo = &ctx->shader_info->tes.outinfo;
6395 break;
6396 default:
6397 unreachable("Unhandled shader type");
6398 }
6399
6400 ac_optimize_vs_outputs(&ctx->ac,
6401 ctx->main_function,
6402 outinfo->vs_output_param_offset,
6403 VARYING_SLOT_MAX,
6404 &outinfo->param_exports);
6405 }
6406
6407 static void
6408 ac_setup_rings(struct nir_to_llvm_context *ctx)
6409 {
6410 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6411 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6412 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6413 }
6414
6415 if (ctx->is_gs_copy_shader) {
6416 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6417 }
6418 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6419 LLVMValueRef tmp;
6420 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6421 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6422
6423 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6424
6425 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6426 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6427 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6428 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6429 }
6430
6431 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6432 ctx->stage == MESA_SHADER_TESS_EVAL) {
6433 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6434 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6435 }
6436 }
6437
6438 static unsigned
6439 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6440 const struct nir_shader *nir)
6441 {
6442 switch (nir->info.stage) {
6443 case MESA_SHADER_TESS_CTRL:
6444 return chip_class >= CIK ? 128 : 64;
6445 case MESA_SHADER_GEOMETRY:
6446 return chip_class >= GFX9 ? 128 : 64;
6447 case MESA_SHADER_COMPUTE:
6448 break;
6449 default:
6450 return 0;
6451 }
6452
6453 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6454 nir->info.cs.local_size[1] *
6455 nir->info.cs.local_size[2];
6456 return max_workgroup_size;
6457 }
6458
6459 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6460 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6461 {
6462 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6463 LLVMConstInt(ctx->ac.i32, 8, false),
6464 LLVMConstInt(ctx->ac.i32, 8, false), false);
6465 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6466 ctx->ac.i32_0, "");
6467 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6468 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6469 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6470 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6471 }
6472
6473 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6474 {
6475 for(int i = 5; i >= 0; --i) {
6476 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6477 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6478 LLVMConstInt(ctx->ac.i32, 16, false), false);
6479 }
6480
6481 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6482 LLVMConstInt(ctx->ac.i32, 16, false),
6483 LLVMConstInt(ctx->ac.i32, 8, false), false);
6484 }
6485
6486 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6487 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6488 {
6489 struct ac_nir_context ctx = {};
6490 struct nir_function *func;
6491
6492 ctx.ac = *ac;
6493 ctx.abi = abi;
6494
6495 ctx.nctx = nctx;
6496 if (nctx)
6497 nctx->nir = &ctx;
6498
6499 ctx.stage = nir->info.stage;
6500
6501 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6502
6503 nir_foreach_variable(variable, &nir->outputs)
6504 handle_shader_output_decl(&ctx, nir, variable);
6505
6506 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6507 _mesa_key_pointer_equal);
6508 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6509 _mesa_key_pointer_equal);
6510 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6511 _mesa_key_pointer_equal);
6512
6513 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6514
6515 setup_locals(&ctx, func);
6516
6517 if (nir->info.stage == MESA_SHADER_COMPUTE)
6518 setup_shared(&ctx, nir);
6519
6520 visit_cf_list(&ctx, &func->impl->body);
6521 phi_post_pass(&ctx);
6522
6523 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6524 ctx.outputs);
6525
6526 free(ctx.locals);
6527 ralloc_free(ctx.defs);
6528 ralloc_free(ctx.phis);
6529 ralloc_free(ctx.vars);
6530
6531 if (nctx)
6532 nctx->nir = NULL;
6533 }
6534
6535 static
6536 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6537 struct nir_shader *const *shaders,
6538 int shader_count,
6539 struct ac_shader_variant_info *shader_info,
6540 const struct ac_nir_compiler_options *options)
6541 {
6542 struct nir_to_llvm_context ctx = {0};
6543 unsigned i;
6544 ctx.options = options;
6545 ctx.shader_info = shader_info;
6546 ctx.context = LLVMContextCreate();
6547 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6548
6549 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6550 ctx.ac.module = ctx.module;
6551 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6552
6553 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6554 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6555 LLVMSetDataLayout(ctx.module, data_layout_str);
6556 LLVMDisposeTargetData(data_layout);
6557 LLVMDisposeMessage(data_layout_str);
6558
6559 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6560 ctx.ac.builder = ctx.builder;
6561
6562 memset(shader_info, 0, sizeof(*shader_info));
6563
6564 for(int i = 0; i < shader_count; ++i)
6565 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6566
6567 for (i = 0; i < AC_UD_MAX_SETS; i++)
6568 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6569 for (i = 0; i < AC_UD_MAX_UD; i++)
6570 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6571
6572 ctx.max_workgroup_size = 0;
6573 for (int i = 0; i < shader_count; ++i) {
6574 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6575 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6576 shaders[i]));
6577 }
6578
6579 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6580 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6581
6582 ctx.abi.inputs = &ctx.inputs[0];
6583 ctx.abi.emit_outputs = handle_shader_outputs_post;
6584 ctx.abi.emit_vertex = visit_emit_vertex;
6585 ctx.abi.load_ubo = radv_load_ubo;
6586 ctx.abi.load_ssbo = radv_load_ssbo;
6587 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6588 ctx.abi.clamp_shadow_reference = false;
6589
6590 if (shader_count >= 2)
6591 ac_init_exec_full_mask(&ctx.ac);
6592
6593 if (ctx.ac.chip_class == GFX9 &&
6594 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6595 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6596
6597 for(int i = 0; i < shader_count; ++i) {
6598 ctx.stage = shaders[i]->info.stage;
6599 ctx.output_mask = 0;
6600 ctx.tess_outputs_written = 0;
6601 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6602 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6603
6604 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6605 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6606 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6607 ctx.abi.load_inputs = load_gs_input;
6608 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6609 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6610 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6611 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6612 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6613 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6614 if (shader_info->info.vs.needs_instance_id) {
6615 ctx.shader_info->vs.vgpr_comp_cnt =
6616 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6617 }
6618 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6619 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6620 }
6621
6622 if (i)
6623 emit_barrier(&ctx);
6624
6625 ac_setup_rings(&ctx);
6626
6627 LLVMBasicBlockRef merge_block;
6628 if (shader_count >= 2) {
6629 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6630 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6631 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6632
6633 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6634 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6635 LLVMConstInt(ctx.ac.i32, 8, false), false);
6636 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6637 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6638 thread_id, count, "");
6639 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6640
6641 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6642 }
6643
6644 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6645 handle_fs_inputs(&ctx, shaders[i]);
6646 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6647 handle_vs_inputs(&ctx, shaders[i]);
6648 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6649 prepare_gs_input_vgprs(&ctx);
6650
6651 nir_foreach_variable(variable, &shaders[i]->outputs)
6652 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6653
6654 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6655
6656 if (shader_count >= 2) {
6657 LLVMBuildBr(ctx.ac.builder, merge_block);
6658 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6659 }
6660
6661 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6662 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6663 shaders[i]->info.cull_distance_array_size > 4;
6664 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6665 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6666 shaders[i]->info.gs.vertices_out;
6667 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6668 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6669 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6670 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6671 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6672 }
6673 }
6674
6675 LLVMBuildRetVoid(ctx.builder);
6676
6677 ac_llvm_finalize_module(&ctx);
6678
6679 if (shader_count == 1)
6680 ac_nir_eliminate_const_vs_outputs(&ctx);
6681
6682 return ctx.module;
6683 }
6684
6685 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6686 {
6687 unsigned *retval = (unsigned *)context;
6688 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6689 char *description = LLVMGetDiagInfoDescription(di);
6690
6691 if (severity == LLVMDSError) {
6692 *retval = 1;
6693 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6694 description);
6695 }
6696
6697 LLVMDisposeMessage(description);
6698 }
6699
6700 static unsigned ac_llvm_compile(LLVMModuleRef M,
6701 struct ac_shader_binary *binary,
6702 LLVMTargetMachineRef tm)
6703 {
6704 unsigned retval = 0;
6705 char *err;
6706 LLVMContextRef llvm_ctx;
6707 LLVMMemoryBufferRef out_buffer;
6708 unsigned buffer_size;
6709 const char *buffer_data;
6710 LLVMBool mem_err;
6711
6712 /* Setup Diagnostic Handler*/
6713 llvm_ctx = LLVMGetModuleContext(M);
6714
6715 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6716 &retval);
6717
6718 /* Compile IR*/
6719 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6720 &err, &out_buffer);
6721
6722 /* Process Errors/Warnings */
6723 if (mem_err) {
6724 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6725 free(err);
6726 retval = 1;
6727 goto out;
6728 }
6729
6730 /* Extract Shader Code*/
6731 buffer_size = LLVMGetBufferSize(out_buffer);
6732 buffer_data = LLVMGetBufferStart(out_buffer);
6733
6734 ac_elf_read(buffer_data, buffer_size, binary);
6735
6736 /* Clean up */
6737 LLVMDisposeMemoryBuffer(out_buffer);
6738
6739 out:
6740 return retval;
6741 }
6742
6743 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6744 LLVMModuleRef llvm_module,
6745 struct ac_shader_binary *binary,
6746 struct ac_shader_config *config,
6747 struct ac_shader_variant_info *shader_info,
6748 gl_shader_stage stage,
6749 bool dump_shader, bool supports_spill)
6750 {
6751 if (dump_shader)
6752 ac_dump_module(llvm_module);
6753
6754 memset(binary, 0, sizeof(*binary));
6755 int v = ac_llvm_compile(llvm_module, binary, tm);
6756 if (v) {
6757 fprintf(stderr, "compile failed\n");
6758 }
6759
6760 if (dump_shader)
6761 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6762
6763 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6764
6765 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6766 LLVMDisposeModule(llvm_module);
6767 LLVMContextDispose(ctx);
6768
6769 if (stage == MESA_SHADER_FRAGMENT) {
6770 shader_info->num_input_vgprs = 0;
6771 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6772 shader_info->num_input_vgprs += 2;
6773 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6774 shader_info->num_input_vgprs += 2;
6775 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6776 shader_info->num_input_vgprs += 2;
6777 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6778 shader_info->num_input_vgprs += 3;
6779 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6780 shader_info->num_input_vgprs += 2;
6781 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6782 shader_info->num_input_vgprs += 2;
6783 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6784 shader_info->num_input_vgprs += 2;
6785 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6786 shader_info->num_input_vgprs += 1;
6787 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6788 shader_info->num_input_vgprs += 1;
6789 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6790 shader_info->num_input_vgprs += 1;
6791 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6792 shader_info->num_input_vgprs += 1;
6793 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6794 shader_info->num_input_vgprs += 1;
6795 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6796 shader_info->num_input_vgprs += 1;
6797 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6798 shader_info->num_input_vgprs += 1;
6799 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6800 shader_info->num_input_vgprs += 1;
6801 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6802 shader_info->num_input_vgprs += 1;
6803 }
6804 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6805
6806 /* +3 for scratch wave offset and VCC */
6807 config->num_sgprs = MAX2(config->num_sgprs,
6808 shader_info->num_input_sgprs + 3);
6809 }
6810
6811 static void
6812 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6813 {
6814 switch (nir->info.stage) {
6815 case MESA_SHADER_COMPUTE:
6816 for (int i = 0; i < 3; ++i)
6817 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6818 break;
6819 case MESA_SHADER_FRAGMENT:
6820 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6821 break;
6822 case MESA_SHADER_GEOMETRY:
6823 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6824 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6825 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6826 shader_info->gs.invocations = nir->info.gs.invocations;
6827 break;
6828 case MESA_SHADER_TESS_EVAL:
6829 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6830 shader_info->tes.spacing = nir->info.tess.spacing;
6831 shader_info->tes.ccw = nir->info.tess.ccw;
6832 shader_info->tes.point_mode = nir->info.tess.point_mode;
6833 shader_info->tes.as_es = options->key.tes.as_es;
6834 break;
6835 case MESA_SHADER_TESS_CTRL:
6836 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6837 break;
6838 case MESA_SHADER_VERTEX:
6839 shader_info->vs.as_es = options->key.vs.as_es;
6840 shader_info->vs.as_ls = options->key.vs.as_ls;
6841 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6842 if (options->key.vs.as_ls)
6843 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6844 break;
6845 default:
6846 break;
6847 }
6848 }
6849
6850 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6851 struct ac_shader_binary *binary,
6852 struct ac_shader_config *config,
6853 struct ac_shader_variant_info *shader_info,
6854 struct nir_shader *const *nir,
6855 int nir_count,
6856 const struct ac_nir_compiler_options *options,
6857 bool dump_shader)
6858 {
6859
6860 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6861 options);
6862
6863 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6864 for (int i = 0; i < nir_count; ++i)
6865 ac_fill_shader_info(shader_info, nir[i], options);
6866 }
6867
6868 static void
6869 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6870 {
6871 LLVMValueRef args[9];
6872 args[0] = ctx->gsvs_ring;
6873 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6874 args[3] = ctx->ac.i32_0;
6875 args[4] = ctx->ac.i32_1; /* OFFEN */
6876 args[5] = ctx->ac.i32_0; /* IDXEN */
6877 args[6] = ctx->ac.i32_1; /* GLC */
6878 args[7] = ctx->ac.i32_1; /* SLC */
6879 args[8] = ctx->ac.i32_0; /* TFE */
6880
6881 int idx = 0;
6882
6883 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6884 int length = 4;
6885 int slot = idx;
6886 int slot_inc = 1;
6887 if (!(ctx->output_mask & (1ull << i)))
6888 continue;
6889
6890 if (i == VARYING_SLOT_CLIP_DIST0) {
6891 /* unpack clip and cull from a single set of slots */
6892 length = ctx->num_output_clips + ctx->num_output_culls;
6893 if (length > 4)
6894 slot_inc = 2;
6895 }
6896
6897 for (unsigned j = 0; j < length; j++) {
6898 LLVMValueRef value;
6899 args[2] = LLVMConstInt(ctx->ac.i32,
6900 (slot * 4 + j) *
6901 ctx->gs_max_out_vertices * 16 * 4, false);
6902
6903 value = ac_build_intrinsic(&ctx->ac,
6904 "llvm.SI.buffer.load.dword.i32.i32",
6905 ctx->ac.i32, args, 9,
6906 AC_FUNC_ATTR_READONLY |
6907 AC_FUNC_ATTR_LEGACY);
6908
6909 LLVMBuildStore(ctx->builder,
6910 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6911 }
6912 idx += slot_inc;
6913 }
6914 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6915 }
6916
6917 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6918 struct nir_shader *geom_shader,
6919 struct ac_shader_binary *binary,
6920 struct ac_shader_config *config,
6921 struct ac_shader_variant_info *shader_info,
6922 const struct ac_nir_compiler_options *options,
6923 bool dump_shader)
6924 {
6925 struct nir_to_llvm_context ctx = {0};
6926 ctx.context = LLVMContextCreate();
6927 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6928 ctx.options = options;
6929 ctx.shader_info = shader_info;
6930
6931 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6932 ctx.ac.module = ctx.module;
6933
6934 ctx.is_gs_copy_shader = true;
6935 LLVMSetTarget(ctx.module, "amdgcn--");
6936
6937 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6938 ctx.ac.builder = ctx.builder;
6939 ctx.stage = MESA_SHADER_VERTEX;
6940
6941 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
6942
6943 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6944 ac_setup_rings(&ctx);
6945
6946 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6947 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6948
6949 struct ac_nir_context nir_ctx = {};
6950 nir_ctx.ac = ctx.ac;
6951 nir_ctx.abi = &ctx.abi;
6952
6953 nir_ctx.nctx = &ctx;
6954 ctx.nir = &nir_ctx;
6955
6956 nir_foreach_variable(variable, &geom_shader->outputs) {
6957 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
6958 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6959 }
6960
6961 ac_gs_copy_shader_emit(&ctx);
6962
6963 ctx.nir = NULL;
6964
6965 LLVMBuildRetVoid(ctx.builder);
6966
6967 ac_llvm_finalize_module(&ctx);
6968
6969 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6970 MESA_SHADER_VERTEX,
6971 dump_shader, options->supports_spill);
6972 }