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radv/ac: handle invocation and primitive id intrinsics
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_util.h"
26 #include "ac_binary.h"
27 #include "sid.h"
28 #include "nir/nir.h"
29 #include "../vulkan/radv_descriptor_set.h"
30 #include "util/bitscan.h"
31 #include <llvm-c/Transforms/Scalar.h>
32
33 enum radeon_llvm_calling_convention {
34 RADEON_LLVM_AMDGPU_VS = 87,
35 RADEON_LLVM_AMDGPU_GS = 88,
36 RADEON_LLVM_AMDGPU_PS = 89,
37 RADEON_LLVM_AMDGPU_CS = 90,
38 };
39
40 #define CONST_ADDR_SPACE 2
41 #define LOCAL_ADDR_SPACE 3
42
43 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
44 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
45
46 #define SENDMSG_GS 2
47 #define SENDMSG_GS_DONE 3
48
49 #define SENDMSG_GS_OP_NOP (0 << 4)
50 #define SENDMSG_GS_OP_CUT (1 << 4)
51 #define SENDMSG_GS_OP_EMIT (2 << 4)
52 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
53
54 enum desc_type {
55 DESC_IMAGE,
56 DESC_FMASK,
57 DESC_SAMPLER,
58 DESC_BUFFER,
59 };
60
61 struct nir_to_llvm_context {
62 struct ac_llvm_context ac;
63 const struct ac_nir_compiler_options *options;
64 struct ac_shader_variant_info *shader_info;
65
66 LLVMContextRef context;
67 LLVMModuleRef module;
68 LLVMBuilderRef builder;
69 LLVMValueRef main_function;
70
71 struct hash_table *defs;
72 struct hash_table *phis;
73
74 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
75 LLVMValueRef ring_offsets;
76 LLVMValueRef push_constants;
77 LLVMValueRef num_work_groups;
78 LLVMValueRef workgroup_ids;
79 LLVMValueRef local_invocation_ids;
80 LLVMValueRef tg_size;
81
82 LLVMValueRef vertex_buffers;
83 LLVMValueRef base_vertex;
84 LLVMValueRef start_instance;
85 LLVMValueRef vertex_id;
86 LLVMValueRef rel_auto_id;
87 LLVMValueRef vs_prim_id;
88 LLVMValueRef instance_id;
89
90 LLVMValueRef es2gs_offset;
91
92 LLVMValueRef gsvs_ring_stride;
93 LLVMValueRef gsvs_num_entries;
94 LLVMValueRef gs2vs_offset;
95 LLVMValueRef gs_wave_id;
96 LLVMValueRef gs_vtx_offset[6];
97 LLVMValueRef gs_prim_id, gs_invocation_id;
98
99 LLVMValueRef esgs_ring;
100 LLVMValueRef gsvs_ring;
101
102 LLVMValueRef prim_mask;
103 LLVMValueRef sample_positions;
104 LLVMValueRef persp_sample, persp_center, persp_centroid;
105 LLVMValueRef linear_sample, linear_center, linear_centroid;
106 LLVMValueRef front_face;
107 LLVMValueRef ancillary;
108 LLVMValueRef frag_pos[4];
109
110 LLVMBasicBlockRef continue_block;
111 LLVMBasicBlockRef break_block;
112
113 LLVMTypeRef i1;
114 LLVMTypeRef i8;
115 LLVMTypeRef i16;
116 LLVMTypeRef i32;
117 LLVMTypeRef i64;
118 LLVMTypeRef v2i32;
119 LLVMTypeRef v3i32;
120 LLVMTypeRef v4i32;
121 LLVMTypeRef v8i32;
122 LLVMTypeRef f32;
123 LLVMTypeRef f16;
124 LLVMTypeRef v2f32;
125 LLVMTypeRef v4f32;
126 LLVMTypeRef v16i8;
127 LLVMTypeRef voidt;
128
129 LLVMValueRef i32zero;
130 LLVMValueRef i32one;
131 LLVMValueRef f32zero;
132 LLVMValueRef f32one;
133 LLVMValueRef v4f32empty;
134
135 unsigned range_md_kind;
136 unsigned uniform_md_kind;
137 unsigned invariant_load_md_kind;
138 LLVMValueRef empty_md;
139 gl_shader_stage stage;
140
141 LLVMValueRef lds;
142 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
143 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
144
145 LLVMValueRef shared_memory;
146 uint64_t input_mask;
147 uint64_t output_mask;
148 int num_locals;
149 LLVMValueRef *locals;
150 bool has_ddxy;
151 unsigned num_clips;
152 unsigned num_culls;
153
154 bool has_ds_bpermute;
155
156 bool is_gs_copy_shader;
157 LLVMValueRef gs_next_vertex;
158 unsigned gs_max_out_vertices;
159 };
160
161 struct ac_tex_info {
162 LLVMValueRef args[12];
163 int arg_count;
164 LLVMTypeRef dst_type;
165 bool has_offset;
166 };
167
168 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
169 nir_deref_var *deref,
170 enum desc_type desc_type);
171 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
172 {
173 return (index * 4) + chan;
174 }
175
176 static unsigned llvm_get_type_size(LLVMTypeRef type)
177 {
178 LLVMTypeKind kind = LLVMGetTypeKind(type);
179
180 switch (kind) {
181 case LLVMIntegerTypeKind:
182 return LLVMGetIntTypeWidth(type) / 8;
183 case LLVMFloatTypeKind:
184 return 4;
185 case LLVMPointerTypeKind:
186 return 8;
187 case LLVMVectorTypeKind:
188 return LLVMGetVectorSize(type) *
189 llvm_get_type_size(LLVMGetElementType(type));
190 default:
191 assert(0);
192 return 0;
193 }
194 }
195
196 static void set_llvm_calling_convention(LLVMValueRef func,
197 gl_shader_stage stage)
198 {
199 enum radeon_llvm_calling_convention calling_conv;
200
201 switch (stage) {
202 case MESA_SHADER_VERTEX:
203 case MESA_SHADER_TESS_CTRL:
204 case MESA_SHADER_TESS_EVAL:
205 calling_conv = RADEON_LLVM_AMDGPU_VS;
206 break;
207 case MESA_SHADER_GEOMETRY:
208 calling_conv = RADEON_LLVM_AMDGPU_GS;
209 break;
210 case MESA_SHADER_FRAGMENT:
211 calling_conv = RADEON_LLVM_AMDGPU_PS;
212 break;
213 case MESA_SHADER_COMPUTE:
214 calling_conv = RADEON_LLVM_AMDGPU_CS;
215 break;
216 default:
217 unreachable("Unhandle shader type");
218 }
219
220 LLVMSetFunctionCallConv(func, calling_conv);
221 }
222
223 static LLVMValueRef
224 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
225 LLVMBuilderRef builder, LLVMTypeRef *return_types,
226 unsigned num_return_elems, LLVMTypeRef *param_types,
227 unsigned param_count, unsigned array_params_mask,
228 unsigned sgpr_params, bool unsafe_math)
229 {
230 LLVMTypeRef main_function_type, ret_type;
231 LLVMBasicBlockRef main_function_body;
232
233 if (num_return_elems)
234 ret_type = LLVMStructTypeInContext(ctx, return_types,
235 num_return_elems, true);
236 else
237 ret_type = LLVMVoidTypeInContext(ctx);
238
239 /* Setup the function */
240 main_function_type =
241 LLVMFunctionType(ret_type, param_types, param_count, 0);
242 LLVMValueRef main_function =
243 LLVMAddFunction(module, "main", main_function_type);
244 main_function_body =
245 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
246 LLVMPositionBuilderAtEnd(builder, main_function_body);
247
248 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
249 for (unsigned i = 0; i < sgpr_params; ++i) {
250 if (array_params_mask & (1 << i)) {
251 LLVMValueRef P = LLVMGetParam(main_function, i);
252 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_BYVAL);
253 ac_add_attr_dereferenceable(P, UINT64_MAX);
254 }
255 else {
256 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_INREG);
257 }
258 }
259
260 if (unsafe_math) {
261 /* These were copied from some LLVM test. */
262 LLVMAddTargetDependentFunctionAttr(main_function,
263 "less-precise-fpmad",
264 "true");
265 LLVMAddTargetDependentFunctionAttr(main_function,
266 "no-infs-fp-math",
267 "true");
268 LLVMAddTargetDependentFunctionAttr(main_function,
269 "no-nans-fp-math",
270 "true");
271 LLVMAddTargetDependentFunctionAttr(main_function,
272 "unsafe-fp-math",
273 "true");
274 }
275 return main_function;
276 }
277
278 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
279 {
280 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
281 CONST_ADDR_SPACE);
282 }
283
284 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
285 int idx,
286 LLVMTypeRef type)
287 {
288 LLVMValueRef offset;
289 LLVMValueRef ptr;
290 int addr_space;
291
292 offset = LLVMConstInt(ctx->i32, idx, false);
293
294 ptr = ctx->shared_memory;
295 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
296 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
297 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
298 return ptr;
299 }
300
301 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
302 {
303 LLVMTypeRef type = LLVMTypeOf(v);
304 if (type == ctx->f32) {
305 return LLVMBuildBitCast(ctx->builder, v, ctx->i32, "");
306 } else if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
307 LLVMTypeRef elem_type = LLVMGetElementType(type);
308 if (elem_type == ctx->f32) {
309 LLVMTypeRef nt = LLVMVectorType(ctx->i32, LLVMGetVectorSize(type));
310 return LLVMBuildBitCast(ctx->builder, v, nt, "");
311 }
312 }
313 return v;
314 }
315
316 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
317 {
318 LLVMTypeRef type = LLVMTypeOf(v);
319 if (type == ctx->i32) {
320 return LLVMBuildBitCast(ctx->builder, v, ctx->f32, "");
321 } else if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
322 LLVMTypeRef elem_type = LLVMGetElementType(type);
323 if (elem_type == ctx->i32) {
324 LLVMTypeRef nt = LLVMVectorType(ctx->f32, LLVMGetVectorSize(type));
325 return LLVMBuildBitCast(ctx->builder, v, nt, "");
326 }
327 }
328 return v;
329 }
330
331 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
332 LLVMValueRef param, unsigned rshift,
333 unsigned bitwidth)
334 {
335 LLVMValueRef value = param;
336 if (rshift)
337 value = LLVMBuildLShr(ctx->builder, value,
338 LLVMConstInt(ctx->i32, rshift, false), "");
339
340 if (rshift + bitwidth < 32) {
341 unsigned mask = (1 << bitwidth) - 1;
342 value = LLVMBuildAnd(ctx->builder, value,
343 LLVMConstInt(ctx->i32, mask, false), "");
344 }
345 return value;
346 }
347
348 static LLVMValueRef build_gep0(struct nir_to_llvm_context *ctx,
349 LLVMValueRef base_ptr, LLVMValueRef index)
350 {
351 LLVMValueRef indices[2] = {
352 ctx->i32zero,
353 index,
354 };
355 return LLVMBuildGEP(ctx->builder, base_ptr,
356 indices, 2, "");
357 }
358
359 static LLVMValueRef build_indexed_load(struct nir_to_llvm_context *ctx,
360 LLVMValueRef base_ptr, LLVMValueRef index,
361 bool uniform)
362 {
363 LLVMValueRef pointer;
364 pointer = build_gep0(ctx, base_ptr, index);
365 if (uniform)
366 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
367 return LLVMBuildLoad(ctx->builder, pointer, "");
368 }
369
370 static LLVMValueRef build_indexed_load_const(struct nir_to_llvm_context *ctx,
371 LLVMValueRef base_ptr, LLVMValueRef index)
372 {
373 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
374 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
375 return result;
376 }
377
378 static void build_tbuffer_store(struct nir_to_llvm_context *ctx,
379 LLVMValueRef rsrc,
380 LLVMValueRef vdata,
381 unsigned num_channels,
382 LLVMValueRef vaddr,
383 LLVMValueRef soffset,
384 unsigned inst_offset,
385 unsigned dfmt,
386 unsigned nfmt,
387 unsigned offen,
388 unsigned idxen,
389 unsigned glc,
390 unsigned slc,
391 unsigned tfe)
392 {
393 LLVMValueRef args[] = {
394 rsrc,
395 vdata,
396 LLVMConstInt(ctx->i32, num_channels, 0),
397 vaddr,
398 soffset,
399 LLVMConstInt(ctx->i32, inst_offset, 0),
400 LLVMConstInt(ctx->i32, dfmt, 0),
401 LLVMConstInt(ctx->i32, nfmt, 0),
402 LLVMConstInt(ctx->i32, offen, 0),
403 LLVMConstInt(ctx->i32, idxen, 0),
404 LLVMConstInt(ctx->i32, glc, 0),
405 LLVMConstInt(ctx->i32, slc, 0),
406 LLVMConstInt(ctx->i32, tfe, 0)
407 };
408
409 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
410 unsigned func = CLAMP(num_channels, 1, 3) - 1;
411 const char *types[] = {"i32", "v2i32", "v4i32"};
412 char name[256];
413 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
414
415 ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->voidt,
416 args, ARRAY_SIZE(args), 0);
417
418 }
419
420 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
421 {
422 ud_info->sgpr_idx = sgpr_idx;
423 ud_info->num_sgprs = num_sgprs;
424 ud_info->indirect = false;
425 ud_info->indirect_offset = 0;
426 }
427
428 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
429 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
430 {
431 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
432 }
433
434 #if 0
435 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
436 uint32_t indirect_offset)
437 {
438 ud_info->sgpr_idx = sgpr_idx;
439 ud_info->num_sgprs = num_sgprs;
440 ud_info->indirect = true;
441 ud_info->indirect_offset = indirect_offset;
442 }
443 #endif
444
445 static void create_function(struct nir_to_llvm_context *ctx)
446 {
447 LLVMTypeRef arg_types[23];
448 unsigned arg_idx = 0;
449 unsigned array_params_mask = 0;
450 unsigned sgpr_count = 0, user_sgpr_count;
451 unsigned i;
452 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
453 unsigned user_sgpr_idx;
454 bool need_push_constants;
455 bool need_ring_offsets = false;
456
457 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
458 if (ctx->stage == MESA_SHADER_GEOMETRY ||
459 ctx->stage == MESA_SHADER_VERTEX ||
460 ctx->is_gs_copy_shader)
461 need_ring_offsets = true;
462
463 need_push_constants = true;
464 if (!ctx->options->layout)
465 need_push_constants = false;
466 else if (!ctx->options->layout->push_constant_size &&
467 !ctx->options->layout->dynamic_offset_count)
468 need_push_constants = false;
469
470 if (need_ring_offsets && !ctx->options->supports_spill) {
471 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
472 }
473
474 /* 1 for each descriptor set */
475 for (unsigned i = 0; i < num_sets; ++i) {
476 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
477 array_params_mask |= (1 << arg_idx);
478 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
479 }
480 }
481
482 if (need_push_constants) {
483 /* 1 for push constants and dynamic descriptors */
484 array_params_mask |= (1 << arg_idx);
485 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
486 }
487
488 switch (ctx->stage) {
489 case MESA_SHADER_COMPUTE:
490 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
491 user_sgpr_count = arg_idx;
492 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
493 arg_types[arg_idx++] = ctx->i32;
494 sgpr_count = arg_idx;
495
496 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
497 break;
498 case MESA_SHADER_VERTEX:
499 if (!ctx->is_gs_copy_shader) {
500 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
501 arg_types[arg_idx++] = ctx->i32; // base vertex
502 arg_types[arg_idx++] = ctx->i32; // start instance
503 }
504 user_sgpr_count = arg_idx;
505 if (ctx->options->key.vs.as_es)
506 arg_types[arg_idx++] = ctx->i32; //es2gs offset
507 sgpr_count = arg_idx;
508 arg_types[arg_idx++] = ctx->i32; // vertex id
509 if (!ctx->is_gs_copy_shader) {
510 arg_types[arg_idx++] = ctx->i32; // rel auto id
511 arg_types[arg_idx++] = ctx->i32; // vs prim id
512 arg_types[arg_idx++] = ctx->i32; // instance id
513 }
514 break;
515 case MESA_SHADER_GEOMETRY:
516 arg_types[arg_idx++] = ctx->i32; // gsvs stride
517 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
518 user_sgpr_count = arg_idx;
519 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
520 arg_types[arg_idx++] = ctx->i32; // wave id
521 sgpr_count = arg_idx;
522 arg_types[arg_idx++] = ctx->i32; // vtx0
523 arg_types[arg_idx++] = ctx->i32; // vtx1
524 arg_types[arg_idx++] = ctx->i32; // prim id
525 arg_types[arg_idx++] = ctx->i32; // vtx2
526 arg_types[arg_idx++] = ctx->i32; // vtx3
527 arg_types[arg_idx++] = ctx->i32; // vtx4
528 arg_types[arg_idx++] = ctx->i32; // vtx5
529 arg_types[arg_idx++] = ctx->i32; // GS instance id
530 break;
531 case MESA_SHADER_FRAGMENT:
532 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
533 user_sgpr_count = arg_idx;
534 arg_types[arg_idx++] = ctx->i32; /* prim mask */
535 sgpr_count = arg_idx;
536 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
537 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
538 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
539 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
540 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
541 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
542 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
543 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
544 arg_types[arg_idx++] = ctx->f32; /* pos x float */
545 arg_types[arg_idx++] = ctx->f32; /* pos y float */
546 arg_types[arg_idx++] = ctx->f32; /* pos z float */
547 arg_types[arg_idx++] = ctx->f32; /* pos w float */
548 arg_types[arg_idx++] = ctx->i32; /* front face */
549 arg_types[arg_idx++] = ctx->i32; /* ancillary */
550 arg_types[arg_idx++] = ctx->f32; /* sample coverage */
551 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
552 break;
553 default:
554 unreachable("Shader stage not implemented");
555 }
556
557 ctx->main_function = create_llvm_function(
558 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
559 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
560 set_llvm_calling_convention(ctx->main_function, ctx->stage);
561
562 ctx->shader_info->num_input_sgprs = 0;
563 ctx->shader_info->num_input_vgprs = 0;
564
565 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
566 for (i = 0; i < user_sgpr_count; i++)
567 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
568
569 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
570 for (; i < sgpr_count; i++)
571 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
572
573 if (ctx->stage != MESA_SHADER_FRAGMENT)
574 for (; i < arg_idx; ++i)
575 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
576
577 arg_idx = 0;
578 user_sgpr_idx = 0;
579
580 if (ctx->options->supports_spill || need_ring_offsets) {
581 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
582 user_sgpr_idx += 2;
583 if (ctx->options->supports_spill) {
584 ctx->ring_offsets = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
585 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
586 NULL, 0, AC_FUNC_ATTR_READNONE);
587 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
588 const_array(ctx->v16i8, 8), "");
589 } else
590 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
591 }
592
593 for (unsigned i = 0; i < num_sets; ++i) {
594 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
595 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
596 user_sgpr_idx += 2;
597 ctx->descriptor_sets[i] =
598 LLVMGetParam(ctx->main_function, arg_idx++);
599 } else
600 ctx->descriptor_sets[i] = NULL;
601 }
602
603 if (need_push_constants) {
604 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
605 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
606 user_sgpr_idx += 2;
607 }
608
609 switch (ctx->stage) {
610 case MESA_SHADER_COMPUTE:
611 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
612 user_sgpr_idx += 3;
613 ctx->num_work_groups =
614 LLVMGetParam(ctx->main_function, arg_idx++);
615 ctx->workgroup_ids =
616 LLVMGetParam(ctx->main_function, arg_idx++);
617 ctx->tg_size =
618 LLVMGetParam(ctx->main_function, arg_idx++);
619 ctx->local_invocation_ids =
620 LLVMGetParam(ctx->main_function, arg_idx++);
621 break;
622 case MESA_SHADER_VERTEX:
623 if (!ctx->is_gs_copy_shader) {
624 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
625 user_sgpr_idx += 2;
626 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
627 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 2);
628 user_sgpr_idx += 2;
629 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
630 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
631 }
632 if (ctx->options->key.vs.as_es)
633 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
634 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
635 if (!ctx->is_gs_copy_shader) {
636 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
637 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
638 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
639 }
640 break;
641 case MESA_SHADER_GEOMETRY:
642 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
643 user_sgpr_idx += 2;
644 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
645 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
646 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
647 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
648 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
649 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
650 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
651 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
652 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
653 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
654 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
655 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
656 break;
657 case MESA_SHADER_FRAGMENT:
658 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
659 user_sgpr_idx += 2;
660 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
661 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
662 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
663 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
664 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
665 arg_idx++;
666 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
667 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
668 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
669 arg_idx++; /* line stipple */
670 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
671 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
672 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
673 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
674 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
675 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
676 break;
677 default:
678 unreachable("Shader stage not implemented");
679 }
680 }
681
682 static void setup_types(struct nir_to_llvm_context *ctx)
683 {
684 LLVMValueRef args[4];
685
686 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
687 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
688 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
689 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
690 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
691 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
692 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
693 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
694 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
695 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
696 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
697 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
698 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
699 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
700 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
701
702 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
703 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
704 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
705 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
706
707 args[0] = ctx->f32zero;
708 args[1] = ctx->f32zero;
709 args[2] = ctx->f32zero;
710 args[3] = ctx->f32one;
711 ctx->v4f32empty = LLVMConstVector(args, 4);
712
713 ctx->range_md_kind = LLVMGetMDKindIDInContext(ctx->context,
714 "range", 5);
715 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(ctx->context,
716 "invariant.load", 14);
717 ctx->uniform_md_kind =
718 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
719 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
720
721 args[0] = LLVMConstReal(ctx->f32, 2.5);
722 }
723
724 static int get_llvm_num_components(LLVMValueRef value)
725 {
726 LLVMTypeRef type = LLVMTypeOf(value);
727 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
728 ? LLVMGetVectorSize(type)
729 : 1;
730 return num_components;
731 }
732
733 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
734 LLVMValueRef value,
735 int index)
736 {
737 int count = get_llvm_num_components(value);
738
739 assert(index < count);
740 if (count == 1)
741 return value;
742
743 return LLVMBuildExtractElement(ctx->builder, value,
744 LLVMConstInt(ctx->i32, index, false), "");
745 }
746
747 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
748 LLVMValueRef value, unsigned count)
749 {
750 unsigned num_components = get_llvm_num_components(value);
751 if (count == num_components)
752 return value;
753
754 LLVMValueRef masks[] = {
755 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
756 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
757
758 if (count == 1)
759 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
760 "");
761
762 LLVMValueRef swizzle = LLVMConstVector(masks, count);
763 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
764 }
765
766 static void
767 build_store_values_extended(struct nir_to_llvm_context *ctx,
768 LLVMValueRef *values,
769 unsigned value_count,
770 unsigned value_stride,
771 LLVMValueRef vec)
772 {
773 LLVMBuilderRef builder = ctx->builder;
774 unsigned i;
775
776 if (value_count == 1) {
777 LLVMBuildStore(builder, vec, values[0]);
778 return;
779 }
780
781 for (i = 0; i < value_count; i++) {
782 LLVMValueRef ptr = values[i * value_stride];
783 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
784 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
785 LLVMBuildStore(builder, value, ptr);
786 }
787 }
788
789 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
790 nir_ssa_def *def)
791 {
792 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
793 if (def->num_components > 1) {
794 type = LLVMVectorType(type, def->num_components);
795 }
796 return type;
797 }
798
799 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
800 {
801 assert(src.is_ssa);
802 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
803 return (LLVMValueRef)entry->data;
804 }
805
806
807 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
808 struct nir_block *b)
809 {
810 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
811 return (LLVMBasicBlockRef)entry->data;
812 }
813
814 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
815 nir_alu_src src,
816 unsigned num_components)
817 {
818 LLVMValueRef value = get_src(ctx, src.src);
819 bool need_swizzle = false;
820
821 assert(value);
822 LLVMTypeRef type = LLVMTypeOf(value);
823 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
824 ? LLVMGetVectorSize(type)
825 : 1;
826
827 for (unsigned i = 0; i < num_components; ++i) {
828 assert(src.swizzle[i] < src_components);
829 if (src.swizzle[i] != i)
830 need_swizzle = true;
831 }
832
833 if (need_swizzle || num_components != src_components) {
834 LLVMValueRef masks[] = {
835 LLVMConstInt(ctx->i32, src.swizzle[0], false),
836 LLVMConstInt(ctx->i32, src.swizzle[1], false),
837 LLVMConstInt(ctx->i32, src.swizzle[2], false),
838 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
839
840 if (src_components > 1 && num_components == 1) {
841 value = LLVMBuildExtractElement(ctx->builder, value,
842 masks[0], "");
843 } else if (src_components == 1 && num_components > 1) {
844 LLVMValueRef values[] = {value, value, value, value};
845 value = ac_build_gather_values(&ctx->ac, values, num_components);
846 } else {
847 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
848 value = LLVMBuildShuffleVector(ctx->builder, value, value,
849 swizzle, "");
850 }
851 }
852 assert(!src.negate);
853 assert(!src.abs);
854 return value;
855 }
856
857 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
858 LLVMIntPredicate pred, LLVMValueRef src0,
859 LLVMValueRef src1)
860 {
861 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
862 return LLVMBuildSelect(ctx->builder, result,
863 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
864 LLVMConstInt(ctx->i32, 0, false), "");
865 }
866
867 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
868 LLVMRealPredicate pred, LLVMValueRef src0,
869 LLVMValueRef src1)
870 {
871 LLVMValueRef result;
872 src0 = to_float(ctx, src0);
873 src1 = to_float(ctx, src1);
874 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
875 return LLVMBuildSelect(ctx->builder, result,
876 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
877 LLVMConstInt(ctx->i32, 0, false), "");
878 }
879
880 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
881 const char *intrin,
882 LLVMValueRef src0)
883 {
884 LLVMValueRef params[] = {
885 to_float(ctx, src0),
886 };
887 return ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->f32, params, 1, AC_FUNC_ATTR_READNONE);
888 }
889
890 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
891 const char *intrin,
892 LLVMValueRef src0, LLVMValueRef src1)
893 {
894 LLVMValueRef params[] = {
895 to_float(ctx, src0),
896 to_float(ctx, src1),
897 };
898 return ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->f32, params, 2, AC_FUNC_ATTR_READNONE);
899 }
900
901 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
902 const char *intrin,
903 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
904 {
905 LLVMValueRef params[] = {
906 to_float(ctx, src0),
907 to_float(ctx, src1),
908 to_float(ctx, src2),
909 };
910 return ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->f32, params, 3, AC_FUNC_ATTR_READNONE);
911 }
912
913 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
914 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
915 {
916 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
917 ctx->i32zero, "");
918 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
919 }
920
921 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
922 LLVMValueRef src0)
923 {
924 LLVMValueRef params[2] = {
925 src0,
926
927 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
928 * add special code to check for x=0. The reason is that
929 * the LLVM behavior for x=0 is different from what we
930 * need here.
931 *
932 * The hardware already implements the correct behavior.
933 */
934 LLVMConstInt(ctx->i32, 1, false),
935 };
936 return ac_emit_llvm_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
937 }
938
939 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
940 LLVMValueRef src0)
941 {
942 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.flbit.i32",
943 ctx->i32, &src0, 1,
944 AC_FUNC_ATTR_READNONE);
945
946 /* The HW returns the last bit index from MSB, but NIR wants
947 * the index from LSB. Invert it by doing "31 - msb". */
948 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
949 msb, "");
950
951 LLVMValueRef all_ones = LLVMConstInt(ctx->i32, -1, true);
952 LLVMValueRef cond = LLVMBuildOr(ctx->builder,
953 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
954 src0, ctx->i32zero, ""),
955 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
956 src0, all_ones, ""), "");
957
958 return LLVMBuildSelect(ctx->builder, cond, all_ones, msb, "");
959 }
960
961 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
962 LLVMValueRef src0)
963 {
964 LLVMValueRef args[2] = {
965 src0,
966 ctx->i32one,
967 };
968 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctlz.i32",
969 ctx->i32, args, ARRAY_SIZE(args),
970 AC_FUNC_ATTR_READNONE);
971
972 /* The HW returns the last bit index from MSB, but NIR wants
973 * the index from LSB. Invert it by doing "31 - msb". */
974 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
975 msb, "");
976
977 return LLVMBuildSelect(ctx->builder,
978 LLVMBuildICmp(ctx->builder, LLVMIntEQ, src0,
979 ctx->i32zero, ""),
980 LLVMConstInt(ctx->i32, -1, true), msb, "");
981 }
982
983 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
984 LLVMIntPredicate pred,
985 LLVMValueRef src0, LLVMValueRef src1)
986 {
987 return LLVMBuildSelect(ctx->builder,
988 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
989 src0,
990 src1, "");
991
992 }
993 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
994 LLVMValueRef src0)
995 {
996 return emit_minmax_int(ctx, LLVMIntSGT, src0,
997 LLVMBuildNeg(ctx->builder, src0, ""));
998 }
999
1000 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1001 LLVMValueRef src0)
1002 {
1003 LLVMValueRef cmp, val;
1004
1005 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1006 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1007 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1008 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1009 return val;
1010 }
1011
1012 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1013 LLVMValueRef src0)
1014 {
1015 LLVMValueRef cmp, val;
1016
1017 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1018 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1019 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1020 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1021 return val;
1022 }
1023
1024 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1025 LLVMValueRef src0)
1026 {
1027 const char *intr = "llvm.floor.f32";
1028 LLVMValueRef fsrc0 = to_float(ctx, src0);
1029 LLVMValueRef params[] = {
1030 fsrc0,
1031 };
1032 LLVMValueRef floor = ac_emit_llvm_intrinsic(&ctx->ac, intr,
1033 ctx->f32, params, 1,
1034 AC_FUNC_ATTR_READNONE);
1035 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1036 }
1037
1038 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1039 const char *intrin,
1040 LLVMValueRef src0, LLVMValueRef src1)
1041 {
1042 LLVMTypeRef ret_type;
1043 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1044 LLVMValueRef res;
1045 LLVMValueRef params[] = { src0, src1 };
1046 ret_type = LLVMStructTypeInContext(ctx->context, types,
1047 2, true);
1048
1049 res = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ret_type,
1050 params, 2, AC_FUNC_ATTR_READNONE);
1051
1052 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1053 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1054 return res;
1055 }
1056
1057 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1058 LLVMValueRef src0)
1059 {
1060 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1061 }
1062
1063 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1064 LLVMValueRef src0, LLVMValueRef src1)
1065 {
1066 LLVMValueRef dst64, result;
1067 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1068 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1069
1070 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1071 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1072 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1073 return result;
1074 }
1075
1076 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1077 LLVMValueRef src0, LLVMValueRef src1)
1078 {
1079 LLVMValueRef dst64, result;
1080 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1081 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1082
1083 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1084 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1085 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1086 return result;
1087 }
1088
1089 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1090 const char *intrin,
1091 LLVMValueRef srcs[3])
1092 {
1093 LLVMValueRef result;
1094 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1095 result = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->i32, srcs, 3, AC_FUNC_ATTR_READNONE);
1096
1097 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1098 return result;
1099 }
1100
1101 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1102 LLVMValueRef src0, LLVMValueRef src1,
1103 LLVMValueRef src2, LLVMValueRef src3)
1104 {
1105 LLVMValueRef bfi_args[3], result;
1106
1107 bfi_args[0] = LLVMBuildShl(ctx->builder,
1108 LLVMBuildSub(ctx->builder,
1109 LLVMBuildShl(ctx->builder,
1110 ctx->i32one,
1111 src3, ""),
1112 ctx->i32one, ""),
1113 src2, "");
1114 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1115 bfi_args[2] = src0;
1116
1117 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1118
1119 /* Calculate:
1120 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1121 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1122 */
1123 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1124 LLVMBuildAnd(ctx->builder, bfi_args[0],
1125 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1126
1127 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1128 return result;
1129 }
1130
1131 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1132 LLVMValueRef src0)
1133 {
1134 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1135 int i;
1136 LLVMValueRef comp[2];
1137
1138 src0 = to_float(ctx, src0);
1139 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1140 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1141 for (i = 0; i < 2; i++) {
1142 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1143 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1144 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1145 }
1146
1147 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1148 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1149
1150 return comp[0];
1151 }
1152
1153 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1154 LLVMValueRef src0)
1155 {
1156 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1157 LLVMValueRef temps[2], result, val;
1158 int i;
1159
1160 for (i = 0; i < 2; i++) {
1161 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1162 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1163 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1164 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1165 }
1166
1167 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1168 ctx->i32zero, "");
1169 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1170 ctx->i32one, "");
1171 return result;
1172 }
1173
1174 /**
1175 * Set range metadata on an instruction. This can only be used on load and
1176 * call instructions. If you know an instruction can only produce the values
1177 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1178 * \p lo is the minimum value inclusive.
1179 * \p hi is the maximum value exclusive.
1180 */
1181 static void set_range_metadata(struct nir_to_llvm_context *ctx,
1182 LLVMValueRef value, unsigned lo, unsigned hi)
1183 {
1184 LLVMValueRef range_md, md_args[2];
1185 LLVMTypeRef type = LLVMTypeOf(value);
1186 LLVMContextRef context = LLVMGetTypeContext(type);
1187
1188 md_args[0] = LLVMConstInt(type, lo, false);
1189 md_args[1] = LLVMConstInt(type, hi, false);
1190 range_md = LLVMMDNodeInContext(context, md_args, 2);
1191 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1192 }
1193
1194 static LLVMValueRef get_thread_id(struct nir_to_llvm_context *ctx)
1195 {
1196 LLVMValueRef tid;
1197 LLVMValueRef tid_args[2];
1198 tid_args[0] = LLVMConstInt(ctx->i32, 0xffffffff, false);
1199 tid_args[1] = ctx->i32zero;
1200 tid_args[1] = ac_emit_llvm_intrinsic(&ctx->ac,
1201 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1202 tid_args, 2, AC_FUNC_ATTR_READNONE);
1203
1204 tid = ac_emit_llvm_intrinsic(&ctx->ac,
1205 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1206 tid_args, 2, AC_FUNC_ATTR_READNONE);
1207 set_range_metadata(ctx, tid, 0, 64);
1208 return tid;
1209 }
1210
1211 /*
1212 * SI implements derivatives using the local data store (LDS)
1213 * All writes to the LDS happen in all executing threads at
1214 * the same time. TID is the Thread ID for the current
1215 * thread and is a value between 0 and 63, representing
1216 * the thread's position in the wavefront.
1217 *
1218 * For the pixel shader threads are grouped into quads of four pixels.
1219 * The TIDs of the pixels of a quad are:
1220 *
1221 * +------+------+
1222 * |4n + 0|4n + 1|
1223 * +------+------+
1224 * |4n + 2|4n + 3|
1225 * +------+------+
1226 *
1227 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
1228 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
1229 * the current pixel's column, and masking with 0xfffffffe yields the TID
1230 * of the left pixel of the current pixel's row.
1231 *
1232 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
1233 * adding 2 yields the TID of the pixel below the top pixel.
1234 */
1235 /* masks for thread ID. */
1236 #define TID_MASK_TOP_LEFT 0xfffffffc
1237 #define TID_MASK_TOP 0xfffffffd
1238 #define TID_MASK_LEFT 0xfffffffe
1239 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1240 nir_op op,
1241 LLVMValueRef src0)
1242 {
1243 LLVMValueRef tl, trbl, result;
1244 LLVMValueRef tl_tid, trbl_tid;
1245 LLVMValueRef args[2];
1246 LLVMValueRef thread_id;
1247 unsigned mask;
1248 int idx;
1249 ctx->has_ddxy = true;
1250
1251 if (!ctx->lds && !ctx->has_ds_bpermute)
1252 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1253 LLVMArrayType(ctx->i32, 64),
1254 "ddxy_lds", LOCAL_ADDR_SPACE);
1255
1256 thread_id = get_thread_id(ctx);
1257 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1258 mask = TID_MASK_LEFT;
1259 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1260 mask = TID_MASK_TOP;
1261 else
1262 mask = TID_MASK_TOP_LEFT;
1263
1264 tl_tid = LLVMBuildAnd(ctx->builder, thread_id,
1265 LLVMConstInt(ctx->i32, mask, false), "");
1266 /* for DDX we want to next X pixel, DDY next Y pixel. */
1267 if (op == nir_op_fddx_fine ||
1268 op == nir_op_fddx_coarse ||
1269 op == nir_op_fddx)
1270 idx = 1;
1271 else
1272 idx = 2;
1273
1274 trbl_tid = LLVMBuildAdd(ctx->builder, tl_tid,
1275 LLVMConstInt(ctx->i32, idx, false), "");
1276
1277 if (ctx->has_ds_bpermute) {
1278 args[0] = LLVMBuildMul(ctx->builder, tl_tid,
1279 LLVMConstInt(ctx->i32, 4, false), "");
1280 args[1] = src0;
1281 tl = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.ds.bpermute",
1282 ctx->i32, args, 2,
1283 AC_FUNC_ATTR_READNONE);
1284
1285 args[0] = LLVMBuildMul(ctx->builder, trbl_tid,
1286 LLVMConstInt(ctx->i32, 4, false), "");
1287 trbl = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.ds.bpermute",
1288 ctx->i32, args, 2,
1289 AC_FUNC_ATTR_READNONE);
1290 } else {
1291 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
1292
1293 store_ptr = build_gep0(ctx, ctx->lds, thread_id);
1294 load_ptr0 = build_gep0(ctx, ctx->lds, tl_tid);
1295 load_ptr1 = build_gep0(ctx, ctx->lds, trbl_tid);
1296
1297 LLVMBuildStore(ctx->builder, src0, store_ptr);
1298 tl = LLVMBuildLoad(ctx->builder, load_ptr0, "");
1299 trbl = LLVMBuildLoad(ctx->builder, load_ptr1, "");
1300 }
1301 tl = LLVMBuildBitCast(ctx->builder, tl, ctx->f32, "");
1302 trbl = LLVMBuildBitCast(ctx->builder, trbl, ctx->f32, "");
1303 result = LLVMBuildFSub(ctx->builder, trbl, tl, "");
1304 return result;
1305 }
1306
1307 /*
1308 * this takes an I,J coordinate pair,
1309 * and works out the X and Y derivatives.
1310 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1311 */
1312 static LLVMValueRef emit_ddxy_interp(
1313 struct nir_to_llvm_context *ctx,
1314 LLVMValueRef interp_ij)
1315 {
1316 LLVMValueRef result[4], a;
1317 unsigned i;
1318
1319 for (i = 0; i < 2; i++) {
1320 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1321 LLVMConstInt(ctx->i32, i, false), "");
1322 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1323 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1324 }
1325 return ac_build_gather_values(&ctx->ac, result, 4);
1326 }
1327
1328 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1329 {
1330 LLVMValueRef src[4], result = NULL;
1331 unsigned num_components = instr->dest.dest.ssa.num_components;
1332 unsigned src_components;
1333
1334 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1335 switch (instr->op) {
1336 case nir_op_vec2:
1337 case nir_op_vec3:
1338 case nir_op_vec4:
1339 src_components = 1;
1340 break;
1341 case nir_op_pack_half_2x16:
1342 src_components = 2;
1343 break;
1344 case nir_op_unpack_half_2x16:
1345 src_components = 1;
1346 break;
1347 default:
1348 src_components = num_components;
1349 break;
1350 }
1351 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1352 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1353
1354 switch (instr->op) {
1355 case nir_op_fmov:
1356 case nir_op_imov:
1357 result = src[0];
1358 break;
1359 case nir_op_fneg:
1360 src[0] = to_float(ctx, src[0]);
1361 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1362 break;
1363 case nir_op_ineg:
1364 result = LLVMBuildNeg(ctx->builder, src[0], "");
1365 break;
1366 case nir_op_inot:
1367 result = LLVMBuildNot(ctx->builder, src[0], "");
1368 break;
1369 case nir_op_iadd:
1370 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1371 break;
1372 case nir_op_fadd:
1373 src[0] = to_float(ctx, src[0]);
1374 src[1] = to_float(ctx, src[1]);
1375 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1376 break;
1377 case nir_op_fsub:
1378 src[0] = to_float(ctx, src[0]);
1379 src[1] = to_float(ctx, src[1]);
1380 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1381 break;
1382 case nir_op_isub:
1383 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1384 break;
1385 case nir_op_imul:
1386 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1387 break;
1388 case nir_op_imod:
1389 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1390 break;
1391 case nir_op_umod:
1392 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1393 break;
1394 case nir_op_fmod:
1395 src[0] = to_float(ctx, src[0]);
1396 src[1] = to_float(ctx, src[1]);
1397 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1398 result = emit_intrin_1f_param(ctx, "llvm.floor.f32", result);
1399 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1400 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1401 break;
1402 case nir_op_frem:
1403 src[0] = to_float(ctx, src[0]);
1404 src[1] = to_float(ctx, src[1]);
1405 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1406 break;
1407 case nir_op_irem:
1408 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1409 break;
1410 case nir_op_idiv:
1411 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1412 break;
1413 case nir_op_udiv:
1414 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1415 break;
1416 case nir_op_fmul:
1417 src[0] = to_float(ctx, src[0]);
1418 src[1] = to_float(ctx, src[1]);
1419 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1420 break;
1421 case nir_op_fdiv:
1422 src[0] = to_float(ctx, src[0]);
1423 src[1] = to_float(ctx, src[1]);
1424 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1425 break;
1426 case nir_op_frcp:
1427 src[0] = to_float(ctx, src[0]);
1428 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, src[0]);
1429 break;
1430 case nir_op_iand:
1431 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1432 break;
1433 case nir_op_ior:
1434 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1435 break;
1436 case nir_op_ixor:
1437 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1438 break;
1439 case nir_op_ishl:
1440 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1441 break;
1442 case nir_op_ishr:
1443 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1444 break;
1445 case nir_op_ushr:
1446 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1447 break;
1448 case nir_op_ilt:
1449 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1450 break;
1451 case nir_op_ine:
1452 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1453 break;
1454 case nir_op_ieq:
1455 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1456 break;
1457 case nir_op_ige:
1458 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1459 break;
1460 case nir_op_ult:
1461 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1462 break;
1463 case nir_op_uge:
1464 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1465 break;
1466 case nir_op_feq:
1467 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1468 break;
1469 case nir_op_fne:
1470 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1471 break;
1472 case nir_op_flt:
1473 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1474 break;
1475 case nir_op_fge:
1476 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1477 break;
1478 case nir_op_fabs:
1479 result = emit_intrin_1f_param(ctx, "llvm.fabs.f32", src[0]);
1480 break;
1481 case nir_op_iabs:
1482 result = emit_iabs(ctx, src[0]);
1483 break;
1484 case nir_op_imax:
1485 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1486 break;
1487 case nir_op_imin:
1488 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1489 break;
1490 case nir_op_umax:
1491 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1492 break;
1493 case nir_op_umin:
1494 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1495 break;
1496 case nir_op_isign:
1497 result = emit_isign(ctx, src[0]);
1498 break;
1499 case nir_op_fsign:
1500 src[0] = to_float(ctx, src[0]);
1501 result = emit_fsign(ctx, src[0]);
1502 break;
1503 case nir_op_ffloor:
1504 result = emit_intrin_1f_param(ctx, "llvm.floor.f32", src[0]);
1505 break;
1506 case nir_op_ftrunc:
1507 result = emit_intrin_1f_param(ctx, "llvm.trunc.f32", src[0]);
1508 break;
1509 case nir_op_fceil:
1510 result = emit_intrin_1f_param(ctx, "llvm.ceil.f32", src[0]);
1511 break;
1512 case nir_op_fround_even:
1513 result = emit_intrin_1f_param(ctx, "llvm.rint.f32", src[0]);
1514 break;
1515 case nir_op_ffract:
1516 result = emit_ffract(ctx, src[0]);
1517 break;
1518 case nir_op_fsin:
1519 result = emit_intrin_1f_param(ctx, "llvm.sin.f32", src[0]);
1520 break;
1521 case nir_op_fcos:
1522 result = emit_intrin_1f_param(ctx, "llvm.cos.f32", src[0]);
1523 break;
1524 case nir_op_fsqrt:
1525 result = emit_intrin_1f_param(ctx, "llvm.sqrt.f32", src[0]);
1526 break;
1527 case nir_op_fexp2:
1528 result = emit_intrin_1f_param(ctx, "llvm.exp2.f32", src[0]);
1529 break;
1530 case nir_op_flog2:
1531 result = emit_intrin_1f_param(ctx, "llvm.log2.f32", src[0]);
1532 break;
1533 case nir_op_frsq:
1534 result = emit_intrin_1f_param(ctx, "llvm.sqrt.f32", src[0]);
1535 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, result);
1536 break;
1537 case nir_op_fpow:
1538 result = emit_intrin_2f_param(ctx, "llvm.pow.f32", src[0], src[1]);
1539 break;
1540 case nir_op_fmax:
1541 result = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", src[0], src[1]);
1542 break;
1543 case nir_op_fmin:
1544 result = emit_intrin_2f_param(ctx, "llvm.minnum.f32", src[0], src[1]);
1545 break;
1546 case nir_op_ffma:
1547 result = emit_intrin_3f_param(ctx, "llvm.fma.f32", src[0], src[1], src[2]);
1548 break;
1549 case nir_op_ibitfield_extract:
1550 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.i32", src);
1551 break;
1552 case nir_op_ubitfield_extract:
1553 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.u32", src);
1554 break;
1555 case nir_op_bitfield_insert:
1556 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1557 break;
1558 case nir_op_bitfield_reverse:
1559 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1560 break;
1561 case nir_op_bit_count:
1562 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1563 break;
1564 case nir_op_vec2:
1565 case nir_op_vec3:
1566 case nir_op_vec4:
1567 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1568 src[i] = to_integer(ctx, src[i]);
1569 result = ac_build_gather_values(&ctx->ac, src, num_components);
1570 break;
1571 case nir_op_f2i:
1572 src[0] = to_float(ctx, src[0]);
1573 result = LLVMBuildFPToSI(ctx->builder, src[0], ctx->i32, "");
1574 break;
1575 case nir_op_f2u:
1576 src[0] = to_float(ctx, src[0]);
1577 result = LLVMBuildFPToUI(ctx->builder, src[0], ctx->i32, "");
1578 break;
1579 case nir_op_i2f:
1580 result = LLVMBuildSIToFP(ctx->builder, src[0], ctx->f32, "");
1581 break;
1582 case nir_op_u2f:
1583 result = LLVMBuildUIToFP(ctx->builder, src[0], ctx->f32, "");
1584 break;
1585 case nir_op_bcsel:
1586 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1587 break;
1588 case nir_op_find_lsb:
1589 result = emit_find_lsb(ctx, src[0]);
1590 break;
1591 case nir_op_ufind_msb:
1592 result = emit_ufind_msb(ctx, src[0]);
1593 break;
1594 case nir_op_ifind_msb:
1595 result = emit_ifind_msb(ctx, src[0]);
1596 break;
1597 case nir_op_uadd_carry:
1598 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1599 break;
1600 case nir_op_usub_borrow:
1601 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1602 break;
1603 case nir_op_b2f:
1604 result = emit_b2f(ctx, src[0]);
1605 break;
1606 case nir_op_fquantize2f16:
1607 src[0] = to_float(ctx, src[0]);
1608 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1609 /* need to convert back up to f32 */
1610 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1611 break;
1612 case nir_op_umul_high:
1613 result = emit_umul_high(ctx, src[0], src[1]);
1614 break;
1615 case nir_op_imul_high:
1616 result = emit_imul_high(ctx, src[0], src[1]);
1617 break;
1618 case nir_op_pack_half_2x16:
1619 result = emit_pack_half_2x16(ctx, src[0]);
1620 break;
1621 case nir_op_unpack_half_2x16:
1622 result = emit_unpack_half_2x16(ctx, src[0]);
1623 break;
1624 case nir_op_fddx:
1625 case nir_op_fddy:
1626 case nir_op_fddx_fine:
1627 case nir_op_fddy_fine:
1628 case nir_op_fddx_coarse:
1629 case nir_op_fddy_coarse:
1630 result = emit_ddxy(ctx, instr->op, src[0]);
1631 break;
1632 default:
1633 fprintf(stderr, "Unknown NIR alu instr: ");
1634 nir_print_instr(&instr->instr, stderr);
1635 fprintf(stderr, "\n");
1636 abort();
1637 }
1638
1639 if (result) {
1640 assert(instr->dest.dest.is_ssa);
1641 result = to_integer(ctx, result);
1642 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1643 result);
1644 }
1645 }
1646
1647 static void visit_load_const(struct nir_to_llvm_context *ctx,
1648 nir_load_const_instr *instr)
1649 {
1650 LLVMValueRef values[4], value = NULL;
1651 LLVMTypeRef element_type =
1652 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1653
1654 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1655 switch (instr->def.bit_size) {
1656 case 32:
1657 values[i] = LLVMConstInt(element_type,
1658 instr->value.u32[i], false);
1659 break;
1660 case 64:
1661 values[i] = LLVMConstInt(element_type,
1662 instr->value.u64[i], false);
1663 break;
1664 default:
1665 fprintf(stderr,
1666 "unsupported nir load_const bit_size: %d\n",
1667 instr->def.bit_size);
1668 abort();
1669 }
1670 }
1671 if (instr->def.num_components > 1) {
1672 value = LLVMConstVector(values, instr->def.num_components);
1673 } else
1674 value = values[0];
1675
1676 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1677 }
1678
1679 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1680 LLVMTypeRef type)
1681 {
1682 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1683 return LLVMBuildBitCast(ctx->builder, ptr,
1684 LLVMPointerType(type, addr_space), "");
1685 }
1686
1687 static LLVMValueRef
1688 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1689 {
1690 LLVMValueRef size =
1691 LLVMBuildExtractElement(ctx->builder, descriptor,
1692 LLVMConstInt(ctx->i32, 2, false), "");
1693
1694 /* VI only */
1695 if (ctx->options->chip_class >= VI && in_elements) {
1696 /* On VI, the descriptor contains the size in bytes,
1697 * but TXQ must return the size in elements.
1698 * The stride is always non-zero for resources using TXQ.
1699 */
1700 LLVMValueRef stride =
1701 LLVMBuildExtractElement(ctx->builder, descriptor,
1702 LLVMConstInt(ctx->i32, 1, false), "");
1703 stride = LLVMBuildLShr(ctx->builder, stride,
1704 LLVMConstInt(ctx->i32, 16, false), "");
1705 stride = LLVMBuildAnd(ctx->builder, stride,
1706 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1707
1708 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1709 }
1710 return size;
1711 }
1712
1713 /**
1714 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1715 * intrinsic names).
1716 */
1717 static void build_int_type_name(
1718 LLVMTypeRef type,
1719 char *buf, unsigned bufsize)
1720 {
1721 assert(bufsize >= 6);
1722
1723 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1724 snprintf(buf, bufsize, "v%ui32",
1725 LLVMGetVectorSize(type));
1726 else
1727 strcpy(buf, "i32");
1728 }
1729
1730 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1731 struct ac_tex_info *tinfo,
1732 nir_tex_instr *instr,
1733 const char *intr_name,
1734 unsigned coord_vgpr_index)
1735 {
1736 LLVMValueRef coord = tinfo->args[0];
1737 LLVMValueRef half_texel[2];
1738 int c;
1739
1740 //TODO Rect
1741 {
1742 LLVMValueRef txq_args[10];
1743 int txq_arg_count = 0;
1744 LLVMValueRef size;
1745 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1746 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, false);
1747 txq_args[txq_arg_count++] = tinfo->args[1];
1748 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0xf, 0); /* dmask */
1749 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* unorm */
1750 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
1751 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
1752 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
1753 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
1754 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
1755 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
1756 size = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
1757 txq_args, txq_arg_count,
1758 AC_FUNC_ATTR_READNONE);
1759
1760 for (c = 0; c < 2; c++) {
1761 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1762 LLVMConstInt(ctx->i32, c, false), "");
1763 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1764 half_texel[c] = ac_emit_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1765 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1766 LLVMConstReal(ctx->f32, -0.5), "");
1767 }
1768 }
1769
1770 for (c = 0; c < 2; c++) {
1771 LLVMValueRef tmp;
1772 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1773 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1774 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1775 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1776 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1777 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1778 }
1779
1780 tinfo->args[0] = coord;
1781 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1782 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1783
1784 }
1785
1786 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1787 nir_tex_instr *instr,
1788 struct ac_tex_info *tinfo)
1789 {
1790 const char *name = "llvm.SI.image.sample";
1791 const char *infix = "";
1792 char intr_name[127];
1793 char type[64];
1794 bool is_shadow = instr->is_shadow;
1795 bool has_offset = tinfo->has_offset;
1796 switch (instr->op) {
1797 case nir_texop_txf:
1798 case nir_texop_txf_ms:
1799 case nir_texop_samples_identical:
1800 name = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? "llvm.SI.image.load" :
1801 instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? "llvm.SI.vs.load.input" :
1802 "llvm.SI.image.load.mip";
1803 is_shadow = false;
1804 has_offset = false;
1805 break;
1806 case nir_texop_txb:
1807 infix = ".b";
1808 break;
1809 case nir_texop_txl:
1810 infix = ".l";
1811 break;
1812 case nir_texop_txs:
1813 name = "llvm.SI.getresinfo";
1814 break;
1815 case nir_texop_query_levels:
1816 name = "llvm.SI.getresinfo";
1817 break;
1818 case nir_texop_tex:
1819 if (ctx->stage != MESA_SHADER_FRAGMENT)
1820 infix = ".lz";
1821 break;
1822 case nir_texop_txd:
1823 infix = ".d";
1824 break;
1825 case nir_texop_tg4:
1826 name = "llvm.SI.gather4";
1827 infix = ".lz";
1828 break;
1829 case nir_texop_lod:
1830 name = "llvm.SI.getlod";
1831 is_shadow = false;
1832 has_offset = false;
1833 break;
1834 default:
1835 break;
1836 }
1837
1838 build_int_type_name(LLVMTypeOf(tinfo->args[0]), type, sizeof(type));
1839 sprintf(intr_name, "%s%s%s%s.%s", name, is_shadow ? ".c" : "", infix,
1840 has_offset ? ".o" : "", type);
1841
1842 if (instr->op == nir_texop_tg4) {
1843 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1844 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1845 return radv_lower_gather4_integer(ctx, tinfo, instr, intr_name,
1846 (int)has_offset + (int)is_shadow);
1847 }
1848 }
1849 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1850 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1851
1852 }
1853
1854 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1855 nir_intrinsic_instr *instr)
1856 {
1857 LLVMValueRef index = get_src(ctx, instr->src[0]);
1858 unsigned desc_set = nir_intrinsic_desc_set(instr);
1859 unsigned binding = nir_intrinsic_binding(instr);
1860 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1861 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
1862 unsigned base_offset = layout->binding[binding].offset;
1863 LLVMValueRef offset, stride;
1864
1865 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1866 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1867 desc_ptr = ctx->push_constants;
1868 base_offset = ctx->options->layout->push_constant_size;
1869 base_offset += 16 * layout->binding[binding].dynamic_offset_offset;
1870 stride = LLVMConstInt(ctx->i32, 16, false);
1871 } else
1872 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1873
1874 offset = LLVMConstInt(ctx->i32, base_offset, false);
1875 index = LLVMBuildMul(ctx->builder, index, stride, "");
1876 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1877
1878 desc_ptr = build_gep0(ctx, desc_ptr, offset);
1879 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1880 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1881
1882 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1883 }
1884
1885 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1886 nir_intrinsic_instr *instr)
1887 {
1888 LLVMValueRef ptr, addr;
1889
1890 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1891 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1892
1893 ptr = build_gep0(ctx, ctx->push_constants, addr);
1894 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1895
1896 return LLVMBuildLoad(ctx->builder, ptr, "");
1897 }
1898
1899 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1900 nir_intrinsic_instr *instr)
1901 {
1902 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1903
1904 return get_buffer_size(ctx, desc, false);
1905 }
1906 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1907 nir_intrinsic_instr *instr)
1908 {
1909 const char *store_name;
1910 LLVMTypeRef data_type = ctx->f32;
1911 unsigned writemask = nir_intrinsic_write_mask(instr);
1912 LLVMValueRef base_data, base_offset;
1913 LLVMValueRef params[6];
1914
1915 if (ctx->stage == MESA_SHADER_FRAGMENT)
1916 ctx->shader_info->fs.writes_memory = true;
1917
1918 params[1] = get_src(ctx, instr->src[1]);
1919 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1920 params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
1921 params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1922
1923 if (instr->num_components > 1)
1924 data_type = LLVMVectorType(ctx->f32, instr->num_components);
1925
1926 base_data = to_float(ctx, get_src(ctx, instr->src[0]));
1927 base_data = trim_vector(ctx, base_data, instr->num_components);
1928 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1929 data_type, "");
1930 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1931 while (writemask) {
1932 int start, count;
1933 LLVMValueRef data;
1934 LLVMValueRef offset;
1935 LLVMValueRef tmp;
1936 u_bit_scan_consecutive_range(&writemask, &start, &count);
1937
1938 /* Due to an LLVM limitation, split 3-element writes
1939 * into a 2-element and a 1-element write. */
1940 if (count == 3) {
1941 writemask |= 1 << (start + 2);
1942 count = 2;
1943 }
1944
1945 if (count == 4) {
1946 store_name = "llvm.amdgcn.buffer.store.v4f32";
1947 data = base_data;
1948 } else if (count == 2) {
1949 tmp = LLVMBuildExtractElement(ctx->builder,
1950 base_data, LLVMConstInt(ctx->i32, start, false), "");
1951 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
1952 ctx->i32zero, "");
1953
1954 tmp = LLVMBuildExtractElement(ctx->builder,
1955 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
1956 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
1957 ctx->i32one, "");
1958 store_name = "llvm.amdgcn.buffer.store.v2f32";
1959
1960 } else {
1961 assert(count == 1);
1962 if (get_llvm_num_components(base_data) > 1)
1963 data = LLVMBuildExtractElement(ctx->builder, base_data,
1964 LLVMConstInt(ctx->i32, start, false), "");
1965 else
1966 data = base_data;
1967 store_name = "llvm.amdgcn.buffer.store.f32";
1968 }
1969
1970 offset = base_offset;
1971 if (start != 0) {
1972 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
1973 }
1974 params[0] = data;
1975 params[3] = offset;
1976 ac_emit_llvm_intrinsic(&ctx->ac, store_name,
1977 ctx->voidt, params, 6, 0);
1978 }
1979 }
1980
1981 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
1982 nir_intrinsic_instr *instr)
1983 {
1984 const char *name;
1985 LLVMValueRef params[6];
1986 int arg_count = 0;
1987 if (ctx->stage == MESA_SHADER_FRAGMENT)
1988 ctx->shader_info->fs.writes_memory = true;
1989
1990 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
1991 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
1992 }
1993 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
1994 params[arg_count++] = get_src(ctx, instr->src[0]);
1995 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1996 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
1997 params[arg_count++] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1998
1999 switch (instr->intrinsic) {
2000 case nir_intrinsic_ssbo_atomic_add:
2001 name = "llvm.amdgcn.buffer.atomic.add";
2002 break;
2003 case nir_intrinsic_ssbo_atomic_imin:
2004 name = "llvm.amdgcn.buffer.atomic.smin";
2005 break;
2006 case nir_intrinsic_ssbo_atomic_umin:
2007 name = "llvm.amdgcn.buffer.atomic.umin";
2008 break;
2009 case nir_intrinsic_ssbo_atomic_imax:
2010 name = "llvm.amdgcn.buffer.atomic.smax";
2011 break;
2012 case nir_intrinsic_ssbo_atomic_umax:
2013 name = "llvm.amdgcn.buffer.atomic.umax";
2014 break;
2015 case nir_intrinsic_ssbo_atomic_and:
2016 name = "llvm.amdgcn.buffer.atomic.and";
2017 break;
2018 case nir_intrinsic_ssbo_atomic_or:
2019 name = "llvm.amdgcn.buffer.atomic.or";
2020 break;
2021 case nir_intrinsic_ssbo_atomic_xor:
2022 name = "llvm.amdgcn.buffer.atomic.xor";
2023 break;
2024 case nir_intrinsic_ssbo_atomic_exchange:
2025 name = "llvm.amdgcn.buffer.atomic.swap";
2026 break;
2027 case nir_intrinsic_ssbo_atomic_comp_swap:
2028 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2029 break;
2030 default:
2031 abort();
2032 }
2033
2034 return ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2035 }
2036
2037 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2038 nir_intrinsic_instr *instr)
2039 {
2040 const char *load_name;
2041 LLVMTypeRef data_type = ctx->f32;
2042 if (instr->num_components == 3)
2043 data_type = LLVMVectorType(ctx->f32, 4);
2044 else if (instr->num_components > 1)
2045 data_type = LLVMVectorType(ctx->f32, instr->num_components);
2046
2047 if (instr->num_components == 4 || instr->num_components == 3)
2048 load_name = "llvm.amdgcn.buffer.load.v4f32";
2049 else if (instr->num_components == 2)
2050 load_name = "llvm.amdgcn.buffer.load.v2f32";
2051 else if (instr->num_components == 1)
2052 load_name = "llvm.amdgcn.buffer.load.f32";
2053 else
2054 abort();
2055
2056 LLVMValueRef params[] = {
2057 get_src(ctx, instr->src[0]),
2058 LLVMConstInt(ctx->i32, 0, false),
2059 get_src(ctx, instr->src[1]),
2060 LLVMConstInt(ctx->i1, 0, false),
2061 LLVMConstInt(ctx->i1, 0, false),
2062 };
2063
2064 LLVMValueRef ret =
2065 ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2066
2067 if (instr->num_components == 3)
2068 ret = trim_vector(ctx, ret, 3);
2069
2070 return LLVMBuildBitCast(ctx->builder, ret,
2071 get_def_type(ctx, &instr->dest.ssa), "");
2072 }
2073
2074 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2075 nir_intrinsic_instr *instr)
2076 {
2077 LLVMValueRef results[4], ret;
2078 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2079 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2080
2081 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2082
2083 for (unsigned i = 0; i < instr->num_components; ++i) {
2084 LLVMValueRef params[] = {
2085 rsrc,
2086 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2087 offset, "")
2088 };
2089 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2090 params, 2, AC_FUNC_ATTR_READNONE);
2091 }
2092
2093
2094 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2095 return LLVMBuildBitCast(ctx->builder, ret,
2096 get_def_type(ctx, &instr->dest.ssa), "");
2097 }
2098
2099 static void
2100 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2101 bool vs_in, unsigned *const_out, LLVMValueRef *indir_out)
2102 {
2103 unsigned const_offset = 0;
2104 LLVMValueRef offset = NULL;
2105
2106
2107 while (tail->child != NULL) {
2108 const struct glsl_type *parent_type = tail->type;
2109 tail = tail->child;
2110
2111 if (tail->deref_type == nir_deref_type_array) {
2112 nir_deref_array *deref_array = nir_deref_as_array(tail);
2113 LLVMValueRef index, stride, local_offset;
2114 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2115
2116 const_offset += size * deref_array->base_offset;
2117 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2118 continue;
2119
2120 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2121 index = get_src(ctx, deref_array->indirect);
2122 stride = LLVMConstInt(ctx->i32, size, 0);
2123 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2124
2125 if (offset)
2126 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2127 else
2128 offset = local_offset;
2129 } else if (tail->deref_type == nir_deref_type_struct) {
2130 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2131
2132 for (unsigned i = 0; i < deref_struct->index; i++) {
2133 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2134 const_offset += glsl_count_attribute_slots(ft, vs_in);
2135 }
2136 } else
2137 unreachable("unsupported deref type");
2138
2139 }
2140
2141 if (const_offset && offset)
2142 offset = LLVMBuildAdd(ctx->builder, offset,
2143 LLVMConstInt(ctx->i32, const_offset, 0),
2144 "");
2145
2146 *const_out = const_offset;
2147 *indir_out = offset;
2148 }
2149
2150 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2151 nir_intrinsic_instr *instr)
2152 {
2153 LLVMValueRef values[4];
2154 int idx = instr->variables[0]->var->data.driver_location;
2155 int ve = instr->dest.ssa.num_components;
2156 LLVMValueRef indir_index;
2157 unsigned const_index;
2158 switch (instr->variables[0]->var->data.mode) {
2159 case nir_var_shader_in:
2160 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2161 ctx->stage == MESA_SHADER_VERTEX,
2162 &const_index, &indir_index);
2163 for (unsigned chan = 0; chan < ve; chan++) {
2164 if (indir_index) {
2165 unsigned count = glsl_count_attribute_slots(
2166 instr->variables[0]->var->type,
2167 ctx->stage == MESA_SHADER_VERTEX);
2168 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2169 &ctx->ac, ctx->inputs + idx + chan, count,
2170 4, false);
2171
2172 values[chan] = LLVMBuildExtractElement(ctx->builder,
2173 tmp_vec,
2174 indir_index, "");
2175 } else
2176 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2177 }
2178 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2179 break;
2180 case nir_var_local:
2181 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2182 &const_index, &indir_index);
2183 for (unsigned chan = 0; chan < ve; chan++) {
2184 if (indir_index) {
2185 unsigned count = glsl_count_attribute_slots(
2186 instr->variables[0]->var->type, false);
2187 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2188 &ctx->ac, ctx->locals + idx + chan, count,
2189 4, true);
2190
2191 values[chan] = LLVMBuildExtractElement(ctx->builder,
2192 tmp_vec,
2193 indir_index, "");
2194 } else {
2195 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2196 }
2197 }
2198 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2199 case nir_var_shader_out:
2200 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2201 &const_index, &indir_index);
2202 for (unsigned chan = 0; chan < ve; chan++) {
2203 if (indir_index) {
2204 unsigned count = glsl_count_attribute_slots(
2205 instr->variables[0]->var->type, false);
2206 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2207 &ctx->ac, ctx->outputs + idx + chan, count,
2208 4, true);
2209
2210 values[chan] = LLVMBuildExtractElement(ctx->builder,
2211 tmp_vec,
2212 indir_index, "");
2213 } else {
2214 values[chan] = LLVMBuildLoad(ctx->builder,
2215 ctx->outputs[idx + chan + const_index * 4],
2216 "");
2217 }
2218 }
2219 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2220 case nir_var_shared: {
2221 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2222 &const_index, &indir_index);
2223 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2224 LLVMValueRef derived_ptr;
2225
2226 for (unsigned chan = 0; chan < ve; chan++) {
2227 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2228 if (indir_index)
2229 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2230 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2231 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2232 }
2233 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2234 }
2235 default:
2236 break;
2237 }
2238 return NULL;
2239 }
2240
2241 static void
2242 visit_store_var(struct nir_to_llvm_context *ctx,
2243 nir_intrinsic_instr *instr)
2244 {
2245 LLVMValueRef temp_ptr, value;
2246 int idx = instr->variables[0]->var->data.driver_location;
2247 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2248 int writemask = instr->const_index[0];
2249 LLVMValueRef indir_index;
2250 unsigned const_index;
2251 switch (instr->variables[0]->var->data.mode) {
2252 case nir_var_shader_out:
2253 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2254 &const_index, &indir_index);
2255 for (unsigned chan = 0; chan < 4; chan++) {
2256 int stride = 4;
2257 if (!(writemask & (1 << chan)))
2258 continue;
2259 if (get_llvm_num_components(src) == 1)
2260 value = src;
2261 else
2262 value = LLVMBuildExtractElement(ctx->builder, src,
2263 LLVMConstInt(ctx->i32,
2264 chan, false),
2265 "");
2266
2267 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2268 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2269 stride = 1;
2270 if (indir_index) {
2271 unsigned count = glsl_count_attribute_slots(
2272 instr->variables[0]->var->type, false);
2273 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2274 &ctx->ac, ctx->outputs + idx + chan, count,
2275 stride, true);
2276
2277 if (get_llvm_num_components(tmp_vec) > 1) {
2278 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2279 value, indir_index, "");
2280 } else
2281 tmp_vec = value;
2282 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2283 count, stride, tmp_vec);
2284
2285 } else {
2286 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2287
2288 LLVMBuildStore(ctx->builder, value, temp_ptr);
2289 }
2290 }
2291 break;
2292 case nir_var_local:
2293 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2294 &const_index, &indir_index);
2295 for (unsigned chan = 0; chan < 4; chan++) {
2296 if (!(writemask & (1 << chan)))
2297 continue;
2298
2299 if (get_llvm_num_components(src) == 1)
2300 value = src;
2301 else
2302 value = LLVMBuildExtractElement(ctx->builder, src,
2303 LLVMConstInt(ctx->i32, chan, false), "");
2304 if (indir_index) {
2305 unsigned count = glsl_count_attribute_slots(
2306 instr->variables[0]->var->type, false);
2307 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2308 &ctx->ac, ctx->locals + idx + chan, count,
2309 4, true);
2310
2311 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2312 value, indir_index, "");
2313 build_store_values_extended(ctx, ctx->locals + idx + chan,
2314 count, 4, tmp_vec);
2315 } else {
2316 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2317
2318 LLVMBuildStore(ctx->builder, value, temp_ptr);
2319 }
2320 }
2321 break;
2322 case nir_var_shared: {
2323 LLVMValueRef ptr;
2324 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2325 &const_index, &indir_index);
2326
2327 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2328 LLVMValueRef derived_ptr;
2329
2330 for (unsigned chan = 0; chan < 4; chan++) {
2331 if (!(writemask & (1 << chan)))
2332 continue;
2333
2334 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2335
2336 if (get_llvm_num_components(src) == 1)
2337 value = src;
2338 else
2339 value = LLVMBuildExtractElement(ctx->builder, src,
2340 LLVMConstInt(ctx->i32,
2341 chan, false),
2342 "");
2343
2344 if (indir_index)
2345 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2346
2347 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2348 LLVMBuildStore(ctx->builder,
2349 to_integer(ctx, value), derived_ptr);
2350 }
2351 break;
2352 }
2353 default:
2354 break;
2355 }
2356 }
2357
2358 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2359 {
2360 switch (dim) {
2361 case GLSL_SAMPLER_DIM_BUF:
2362 return 1;
2363 case GLSL_SAMPLER_DIM_1D:
2364 return array ? 2 : 1;
2365 case GLSL_SAMPLER_DIM_2D:
2366 return array ? 3 : 2;
2367 case GLSL_SAMPLER_DIM_MS:
2368 return array ? 4 : 3;
2369 case GLSL_SAMPLER_DIM_3D:
2370 case GLSL_SAMPLER_DIM_CUBE:
2371 return 3;
2372 case GLSL_SAMPLER_DIM_RECT:
2373 case GLSL_SAMPLER_DIM_SUBPASS:
2374 return 2;
2375 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2376 return 3;
2377 default:
2378 break;
2379 }
2380 return 0;
2381 }
2382
2383 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2384 nir_intrinsic_instr *instr)
2385 {
2386 const struct glsl_type *type = instr->variables[0]->var->type;
2387 if(instr->variables[0]->deref.child)
2388 type = instr->variables[0]->deref.child->type;
2389
2390 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2391 LLVMValueRef coords[4];
2392 LLVMValueRef masks[] = {
2393 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2394 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2395 };
2396 LLVMValueRef res;
2397 int count;
2398 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2399 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2400 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2401 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2402 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2403
2404 count = image_type_to_components_count(dim,
2405 glsl_sampler_type_is_array(type));
2406
2407 if (count == 1) {
2408 if (instr->src[0].ssa->num_components)
2409 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2410 else
2411 res = src0;
2412 } else {
2413 int chan;
2414 if (is_ms)
2415 count--;
2416 for (chan = 0; chan < count; ++chan) {
2417 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2418 }
2419
2420 if (add_frag_pos) {
2421 for (chan = 0; chan < count; ++chan)
2422 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2423 }
2424 if (is_ms) {
2425 coords[count] = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2426 count++;
2427 }
2428
2429 if (count == 3) {
2430 coords[3] = LLVMGetUndef(ctx->i32);
2431 count = 4;
2432 }
2433 res = ac_build_gather_values(&ctx->ac, coords, count);
2434 }
2435 return res;
2436 }
2437
2438 static void build_type_name_for_intr(
2439 LLVMTypeRef type,
2440 char *buf, unsigned bufsize)
2441 {
2442 LLVMTypeRef elem_type = type;
2443
2444 assert(bufsize >= 8);
2445
2446 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
2447 int ret = snprintf(buf, bufsize, "v%u",
2448 LLVMGetVectorSize(type));
2449 if (ret < 0) {
2450 char *type_name = LLVMPrintTypeToString(type);
2451 fprintf(stderr, "Error building type name for: %s\n",
2452 type_name);
2453 return;
2454 }
2455 elem_type = LLVMGetElementType(type);
2456 buf += ret;
2457 bufsize -= ret;
2458 }
2459 switch (LLVMGetTypeKind(elem_type)) {
2460 default: break;
2461 case LLVMIntegerTypeKind:
2462 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
2463 break;
2464 case LLVMFloatTypeKind:
2465 snprintf(buf, bufsize, "f32");
2466 break;
2467 case LLVMDoubleTypeKind:
2468 snprintf(buf, bufsize, "f64");
2469 break;
2470 }
2471 }
2472
2473 static void get_image_intr_name(const char *base_name,
2474 LLVMTypeRef data_type,
2475 LLVMTypeRef coords_type,
2476 LLVMTypeRef rsrc_type,
2477 char *out_name, unsigned out_len)
2478 {
2479 char coords_type_name[8];
2480
2481 build_type_name_for_intr(coords_type, coords_type_name,
2482 sizeof(coords_type_name));
2483
2484 if (HAVE_LLVM <= 0x0309) {
2485 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
2486 } else {
2487 char data_type_name[8];
2488 char rsrc_type_name[8];
2489
2490 build_type_name_for_intr(data_type, data_type_name,
2491 sizeof(data_type_name));
2492 build_type_name_for_intr(rsrc_type, rsrc_type_name,
2493 sizeof(rsrc_type_name));
2494 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
2495 data_type_name, coords_type_name, rsrc_type_name);
2496 }
2497 }
2498
2499 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2500 nir_intrinsic_instr *instr)
2501 {
2502 LLVMValueRef params[7];
2503 LLVMValueRef res;
2504 char intrinsic_name[64];
2505 const nir_variable *var = instr->variables[0]->var;
2506 const struct glsl_type *type = var->type;
2507 if(instr->variables[0]->deref.child)
2508 type = instr->variables[0]->deref.child->type;
2509
2510 type = glsl_without_array(type);
2511 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2512 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2513 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2514 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2515 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2516 params[3] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2517 params[4] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2518 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2519 params, 5, 0);
2520
2521 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2522 res = to_integer(ctx, res);
2523 } else {
2524 bool is_da = glsl_sampler_type_is_array(type) ||
2525 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2526 LLVMValueRef da = is_da ? ctx->i32one : ctx->i32zero;
2527 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2528 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2529
2530 params[0] = get_image_coords(ctx, instr);
2531 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2532 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2533 if (HAVE_LLVM <= 0x0309) {
2534 params[3] = LLVMConstInt(ctx->i1, 0, false); /* r128 */
2535 params[4] = da;
2536 params[5] = glc;
2537 params[6] = slc;
2538 } else {
2539 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2540 params[3] = glc;
2541 params[4] = slc;
2542 params[5] = lwe;
2543 params[6] = da;
2544 }
2545
2546 get_image_intr_name("llvm.amdgcn.image.load",
2547 ctx->v4f32, /* vdata */
2548 LLVMTypeOf(params[0]), /* coords */
2549 LLVMTypeOf(params[1]), /* rsrc */
2550 intrinsic_name, sizeof(intrinsic_name));
2551
2552 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2553 params, 7, AC_FUNC_ATTR_READONLY);
2554 }
2555 return to_integer(ctx, res);
2556 }
2557
2558 static void visit_image_store(struct nir_to_llvm_context *ctx,
2559 nir_intrinsic_instr *instr)
2560 {
2561 LLVMValueRef params[8];
2562 char intrinsic_name[64];
2563 const nir_variable *var = instr->variables[0]->var;
2564 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2565 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2566 const struct glsl_type *type = glsl_without_array(var->type);
2567
2568 if (ctx->stage == MESA_SHADER_FRAGMENT)
2569 ctx->shader_info->fs.writes_memory = true;
2570
2571 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2572 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2573 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2574 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2575 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2576 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2577 params[4] = i1false; /* glc */
2578 params[5] = i1false; /* slc */
2579 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2580 params, 6, 0);
2581 } else {
2582 bool is_da = glsl_sampler_type_is_array(type) ||
2583 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2584 LLVMValueRef da = is_da ? i1true : i1false;
2585 LLVMValueRef glc = i1false;
2586 LLVMValueRef slc = i1false;
2587
2588 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2589 params[1] = get_image_coords(ctx, instr); /* coords */
2590 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2591 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2592 if (HAVE_LLVM <= 0x0309) {
2593 params[4] = i1false; /* r128 */
2594 params[5] = da;
2595 params[6] = glc;
2596 params[7] = slc;
2597 } else {
2598 LLVMValueRef lwe = i1false;
2599 params[4] = glc;
2600 params[5] = slc;
2601 params[6] = lwe;
2602 params[7] = da;
2603 }
2604
2605 get_image_intr_name("llvm.amdgcn.image.store",
2606 LLVMTypeOf(params[0]), /* vdata */
2607 LLVMTypeOf(params[1]), /* coords */
2608 LLVMTypeOf(params[2]), /* rsrc */
2609 intrinsic_name, sizeof(intrinsic_name));
2610
2611 ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2612 params, 8, 0);
2613 }
2614
2615 }
2616
2617 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2618 nir_intrinsic_instr *instr)
2619 {
2620 LLVMValueRef params[6];
2621 int param_count = 0;
2622 const nir_variable *var = instr->variables[0]->var;
2623 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2624 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2625 const char *base_name = "llvm.amdgcn.image.atomic";
2626 const char *atomic_name;
2627 LLVMValueRef coords;
2628 char intrinsic_name[32], coords_type[8];
2629 const struct glsl_type *type = glsl_without_array(var->type);
2630
2631 if (ctx->stage == MESA_SHADER_FRAGMENT)
2632 ctx->shader_info->fs.writes_memory = true;
2633
2634 params[param_count++] = get_src(ctx, instr->src[2]);
2635 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2636 params[param_count++] = get_src(ctx, instr->src[3]);
2637
2638 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2639 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2640 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2641 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2642 params[param_count++] = ctx->i32zero; /* voffset */
2643 params[param_count++] = i1false; /* glc */
2644 params[param_count++] = i1false; /* slc */
2645 } else {
2646 bool da = glsl_sampler_type_is_array(type) ||
2647 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2648
2649 coords = params[param_count++] = get_image_coords(ctx, instr);
2650 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2651 params[param_count++] = i1false; /* r128 */
2652 params[param_count++] = da ? i1true : i1false; /* da */
2653 params[param_count++] = i1false; /* slc */
2654 }
2655
2656 switch (instr->intrinsic) {
2657 case nir_intrinsic_image_atomic_add:
2658 atomic_name = "add";
2659 break;
2660 case nir_intrinsic_image_atomic_min:
2661 atomic_name = "smin";
2662 break;
2663 case nir_intrinsic_image_atomic_max:
2664 atomic_name = "smax";
2665 break;
2666 case nir_intrinsic_image_atomic_and:
2667 atomic_name = "and";
2668 break;
2669 case nir_intrinsic_image_atomic_or:
2670 atomic_name = "or";
2671 break;
2672 case nir_intrinsic_image_atomic_xor:
2673 atomic_name = "xor";
2674 break;
2675 case nir_intrinsic_image_atomic_exchange:
2676 atomic_name = "swap";
2677 break;
2678 case nir_intrinsic_image_atomic_comp_swap:
2679 atomic_name = "cmpswap";
2680 break;
2681 default:
2682 abort();
2683 }
2684 build_int_type_name(LLVMTypeOf(coords),
2685 coords_type, sizeof(coords_type));
2686
2687 snprintf(intrinsic_name, sizeof(intrinsic_name),
2688 "%s.%s.%s", base_name, atomic_name, coords_type);
2689 return ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2690 }
2691
2692 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2693 nir_intrinsic_instr *instr)
2694 {
2695 LLVMValueRef res;
2696 LLVMValueRef params[10];
2697 const nir_variable *var = instr->variables[0]->var;
2698 const struct glsl_type *type = instr->variables[0]->var->type;
2699 bool da = glsl_sampler_type_is_array(var->type) ||
2700 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2701 if(instr->variables[0]->deref.child)
2702 type = instr->variables[0]->deref.child->type;
2703
2704 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2705 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2706 params[0] = ctx->i32zero;
2707 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2708 params[2] = LLVMConstInt(ctx->i32, 15, false);
2709 params[3] = ctx->i32zero;
2710 params[4] = ctx->i32zero;
2711 params[5] = da ? ctx->i32one : ctx->i32zero;
2712 params[6] = ctx->i32zero;
2713 params[7] = ctx->i32zero;
2714 params[8] = ctx->i32zero;
2715 params[9] = ctx->i32zero;
2716
2717 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
2718 params, 10, AC_FUNC_ATTR_READNONE);
2719
2720 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2721 glsl_sampler_type_is_array(type)) {
2722 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2723 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2724 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2725 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2726 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2727 }
2728 return res;
2729 }
2730
2731 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2732 {
2733 LLVMValueRef args[1] = {
2734 LLVMConstInt(ctx->i32, 0xf70, false),
2735 };
2736 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2737 ctx->voidt, args, 1, 0);
2738 }
2739
2740 static void emit_barrier(struct nir_to_llvm_context *ctx)
2741 {
2742 // TODO tess
2743 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2744 ctx->voidt, NULL, 0, 0);
2745 }
2746
2747 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2748 nir_intrinsic_instr *instr)
2749 {
2750 LLVMValueRef cond;
2751 ctx->shader_info->fs.can_discard = true;
2752
2753 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2754 get_src(ctx, instr->src[0]),
2755 ctx->i32zero, "");
2756
2757 cond = LLVMBuildSelect(ctx->builder, cond,
2758 LLVMConstReal(ctx->f32, -1.0f),
2759 ctx->f32zero, "");
2760 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
2761 ctx->voidt,
2762 &cond, 1, 0);
2763 }
2764
2765 static LLVMValueRef
2766 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2767 {
2768 LLVMValueRef result;
2769 LLVMValueRef thread_id = get_thread_id(ctx);
2770 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2771 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2772
2773 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2774 }
2775
2776 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2777 nir_intrinsic_instr *instr)
2778 {
2779 LLVMValueRef ptr, result;
2780 int idx = instr->variables[0]->var->data.driver_location;
2781 LLVMValueRef src = get_src(ctx, instr->src[0]);
2782 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2783
2784 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2785 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2786 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2787 ptr, src, src1,
2788 LLVMAtomicOrderingSequentiallyConsistent,
2789 LLVMAtomicOrderingSequentiallyConsistent,
2790 false);
2791 } else {
2792 LLVMAtomicRMWBinOp op;
2793 switch (instr->intrinsic) {
2794 case nir_intrinsic_var_atomic_add:
2795 op = LLVMAtomicRMWBinOpAdd;
2796 break;
2797 case nir_intrinsic_var_atomic_umin:
2798 op = LLVMAtomicRMWBinOpUMin;
2799 break;
2800 case nir_intrinsic_var_atomic_umax:
2801 op = LLVMAtomicRMWBinOpUMax;
2802 break;
2803 case nir_intrinsic_var_atomic_imin:
2804 op = LLVMAtomicRMWBinOpMin;
2805 break;
2806 case nir_intrinsic_var_atomic_imax:
2807 op = LLVMAtomicRMWBinOpMax;
2808 break;
2809 case nir_intrinsic_var_atomic_and:
2810 op = LLVMAtomicRMWBinOpAnd;
2811 break;
2812 case nir_intrinsic_var_atomic_or:
2813 op = LLVMAtomicRMWBinOpOr;
2814 break;
2815 case nir_intrinsic_var_atomic_xor:
2816 op = LLVMAtomicRMWBinOpXor;
2817 break;
2818 case nir_intrinsic_var_atomic_exchange:
2819 op = LLVMAtomicRMWBinOpXchg;
2820 break;
2821 default:
2822 return NULL;
2823 }
2824
2825 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2826 LLVMAtomicOrderingSequentiallyConsistent,
2827 false);
2828 }
2829 return result;
2830 }
2831
2832 #define INTERP_CENTER 0
2833 #define INTERP_CENTROID 1
2834 #define INTERP_SAMPLE 2
2835
2836 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2837 enum glsl_interp_mode interp, unsigned location)
2838 {
2839 switch (interp) {
2840 case INTERP_MODE_FLAT:
2841 default:
2842 return NULL;
2843 case INTERP_MODE_SMOOTH:
2844 case INTERP_MODE_NONE:
2845 if (location == INTERP_CENTER)
2846 return ctx->persp_center;
2847 else if (location == INTERP_CENTROID)
2848 return ctx->persp_centroid;
2849 else if (location == INTERP_SAMPLE)
2850 return ctx->persp_sample;
2851 break;
2852 case INTERP_MODE_NOPERSPECTIVE:
2853 if (location == INTERP_CENTER)
2854 return ctx->linear_center;
2855 else if (location == INTERP_CENTROID)
2856 return ctx->linear_centroid;
2857 else if (location == INTERP_SAMPLE)
2858 return ctx->linear_sample;
2859 break;
2860 }
2861 return NULL;
2862 }
2863
2864 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
2865 LLVMValueRef sample_id)
2866 {
2867 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2868 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
2869 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
2870 LLVMValueRef result[2];
2871
2872 result[0] = build_indexed_load_const(ctx, ctx->sample_positions, offset0);
2873 result[1] = build_indexed_load_const(ctx, ctx->sample_positions, offset1);
2874
2875 return ac_build_gather_values(&ctx->ac, result, 2);
2876 }
2877
2878 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
2879 {
2880 LLVMValueRef values[2];
2881
2882 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
2883 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
2884 return ac_build_gather_values(&ctx->ac, values, 2);
2885 }
2886
2887 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
2888 nir_intrinsic_instr *instr)
2889 {
2890 LLVMValueRef result[2];
2891 LLVMValueRef interp_param, attr_number;
2892 unsigned location;
2893 unsigned chan;
2894 LLVMValueRef src_c0, src_c1;
2895 const char *intr_name;
2896 LLVMValueRef src0;
2897 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
2898 switch (instr->intrinsic) {
2899 case nir_intrinsic_interp_var_at_centroid:
2900 location = INTERP_CENTROID;
2901 break;
2902 case nir_intrinsic_interp_var_at_sample:
2903 case nir_intrinsic_interp_var_at_offset:
2904 location = INTERP_SAMPLE;
2905 src0 = get_src(ctx, instr->src[0]);
2906 break;
2907 default:
2908 break;
2909 }
2910
2911 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
2912 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
2913 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
2914 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
2915 LLVMValueRef sample_position;
2916 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
2917
2918 /* fetch sample ID */
2919 sample_position = load_sample_position(ctx, src0);
2920
2921 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
2922 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
2923 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
2924 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
2925 }
2926 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
2927 attr_number = LLVMConstInt(ctx->i32, input_index, false);
2928
2929 if (location == INTERP_SAMPLE) {
2930 LLVMValueRef ij_out[2];
2931 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
2932
2933 /*
2934 * take the I then J parameters, and the DDX/Y for it, and
2935 * calculate the IJ inputs for the interpolator.
2936 * temp1 = ddx * offset/sample.x + I;
2937 * interp_param.I = ddy * offset/sample.y + temp1;
2938 * temp1 = ddx * offset/sample.x + J;
2939 * interp_param.J = ddy * offset/sample.y + temp1;
2940 */
2941 for (unsigned i = 0; i < 2; i++) {
2942 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
2943 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
2944 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
2945 ddxy_out, ix_ll, "");
2946 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
2947 ddxy_out, iy_ll, "");
2948 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
2949 interp_param, ix_ll, "");
2950 LLVMValueRef temp1, temp2;
2951
2952 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
2953 ctx->f32, "");
2954
2955 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
2956 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
2957
2958 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
2959 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
2960
2961 ij_out[i] = LLVMBuildBitCast(ctx->builder,
2962 temp2, ctx->i32, "");
2963 }
2964 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
2965
2966 }
2967 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
2968 for (chan = 0; chan < 2; chan++) {
2969 LLVMValueRef args[4];
2970 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
2971
2972 args[0] = llvm_chan;
2973 args[1] = attr_number;
2974 args[2] = ctx->prim_mask;
2975 args[3] = interp_param;
2976 result[chan] = ac_emit_llvm_intrinsic(&ctx->ac, intr_name,
2977 ctx->f32, args, args[3] ? 4 : 3,
2978 AC_FUNC_ATTR_READNONE);
2979 }
2980 return ac_build_gather_values(&ctx->ac, result, 2);
2981 }
2982
2983 static void
2984 visit_emit_vertex(struct nir_to_llvm_context *ctx,
2985 nir_intrinsic_instr *instr)
2986 {
2987 LLVMValueRef gs_next_vertex;
2988 LLVMValueRef can_emit, kill;
2989 LLVMValueRef args[2];
2990 int idx;
2991
2992 assert(instr->const_index[0] == 0);
2993 /* Write vertex attribute values to GSVS ring */
2994 gs_next_vertex = LLVMBuildLoad(ctx->builder,
2995 ctx->gs_next_vertex,
2996 "");
2997
2998 /* If this thread has already emitted the declared maximum number of
2999 * vertices, kill it: excessive vertex emissions are not supposed to
3000 * have any effect, and GS threads have no externally observable
3001 * effects other than emitting vertices.
3002 */
3003 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3004 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3005
3006 kill = LLVMBuildSelect(ctx->builder, can_emit,
3007 LLVMConstReal(ctx->f32, 1.0f),
3008 LLVMConstReal(ctx->f32, -1.0f), "");
3009 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
3010 ctx->voidt, &kill, 1, 0);
3011
3012 /* loop num outputs */
3013 idx = 0;
3014 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3015 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3016 if (!(ctx->output_mask & (1ull << i)))
3017 continue;
3018
3019 for (unsigned j = 0; j < 4; j++) {
3020 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3021 out_ptr[j], "");
3022 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (idx * 4 + j) * ctx->gs_max_out_vertices, false);
3023 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3024 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3025
3026 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3027
3028 build_tbuffer_store(ctx, ctx->gsvs_ring,
3029 out_val, 1,
3030 voffset, ctx->gs2vs_offset, 0,
3031 V_008F0C_BUF_DATA_FORMAT_32,
3032 V_008F0C_BUF_NUM_FORMAT_UINT,
3033 1, 0, 1, 1, 0);
3034 }
3035 idx++;
3036 }
3037
3038 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3039 ctx->i32one, "");
3040 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3041 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (0 << 8), false);
3042 args[1] = ctx->gs_wave_id;
3043 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg",
3044 ctx->voidt, args, 2, 0);
3045 }
3046
3047 static void
3048 visit_end_primitive(struct nir_to_llvm_context *ctx,
3049 nir_intrinsic_instr *instr)
3050 {
3051 LLVMValueRef args[2];
3052
3053 assert(instr->const_index[0] == 0);
3054 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_CUT | SENDMSG_GS | (0 << 8), false);
3055 args[1] = ctx->gs_wave_id;
3056
3057 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg", ctx->voidt,
3058 args, 2, 0);
3059 }
3060
3061 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3062 nir_intrinsic_instr *instr)
3063 {
3064 LLVMValueRef result = NULL;
3065
3066 switch (instr->intrinsic) {
3067 case nir_intrinsic_load_work_group_id: {
3068 result = ctx->workgroup_ids;
3069 break;
3070 }
3071 case nir_intrinsic_load_base_vertex: {
3072 result = ctx->base_vertex;
3073 break;
3074 }
3075 case nir_intrinsic_load_vertex_id_zero_base: {
3076 result = ctx->vertex_id;
3077 break;
3078 }
3079 case nir_intrinsic_load_local_invocation_id: {
3080 result = ctx->local_invocation_ids;
3081 break;
3082 }
3083 case nir_intrinsic_load_base_instance:
3084 result = ctx->start_instance;
3085 break;
3086 case nir_intrinsic_load_invocation_id:
3087 result = ctx->gs_invocation_id;
3088 break;
3089 case nir_intrinsic_load_primitive_id:
3090 if (ctx->stage == MESA_SHADER_GEOMETRY)
3091 result = ctx->gs_prim_id;
3092 else
3093 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3094 break;
3095 case nir_intrinsic_load_sample_id:
3096 ctx->shader_info->fs.force_persample = true;
3097 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3098 break;
3099 case nir_intrinsic_load_sample_pos:
3100 ctx->shader_info->fs.force_persample = true;
3101 result = load_sample_pos(ctx);
3102 break;
3103 case nir_intrinsic_load_front_face:
3104 result = ctx->front_face;
3105 break;
3106 case nir_intrinsic_load_instance_id:
3107 result = ctx->instance_id;
3108 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3109 ctx->shader_info->vs.vgpr_comp_cnt);
3110 break;
3111 case nir_intrinsic_load_num_work_groups:
3112 result = ctx->num_work_groups;
3113 break;
3114 case nir_intrinsic_load_local_invocation_index:
3115 result = visit_load_local_invocation_index(ctx);
3116 break;
3117 case nir_intrinsic_load_push_constant:
3118 result = visit_load_push_constant(ctx, instr);
3119 break;
3120 case nir_intrinsic_vulkan_resource_index:
3121 result = visit_vulkan_resource_index(ctx, instr);
3122 break;
3123 case nir_intrinsic_store_ssbo:
3124 visit_store_ssbo(ctx, instr);
3125 break;
3126 case nir_intrinsic_load_ssbo:
3127 result = visit_load_buffer(ctx, instr);
3128 break;
3129 case nir_intrinsic_ssbo_atomic_add:
3130 case nir_intrinsic_ssbo_atomic_imin:
3131 case nir_intrinsic_ssbo_atomic_umin:
3132 case nir_intrinsic_ssbo_atomic_imax:
3133 case nir_intrinsic_ssbo_atomic_umax:
3134 case nir_intrinsic_ssbo_atomic_and:
3135 case nir_intrinsic_ssbo_atomic_or:
3136 case nir_intrinsic_ssbo_atomic_xor:
3137 case nir_intrinsic_ssbo_atomic_exchange:
3138 case nir_intrinsic_ssbo_atomic_comp_swap:
3139 result = visit_atomic_ssbo(ctx, instr);
3140 break;
3141 case nir_intrinsic_load_ubo:
3142 result = visit_load_ubo_buffer(ctx, instr);
3143 break;
3144 case nir_intrinsic_get_buffer_size:
3145 result = visit_get_buffer_size(ctx, instr);
3146 break;
3147 case nir_intrinsic_load_var:
3148 result = visit_load_var(ctx, instr);
3149 break;
3150 case nir_intrinsic_store_var:
3151 visit_store_var(ctx, instr);
3152 break;
3153 case nir_intrinsic_image_load:
3154 result = visit_image_load(ctx, instr);
3155 break;
3156 case nir_intrinsic_image_store:
3157 visit_image_store(ctx, instr);
3158 break;
3159 case nir_intrinsic_image_atomic_add:
3160 case nir_intrinsic_image_atomic_min:
3161 case nir_intrinsic_image_atomic_max:
3162 case nir_intrinsic_image_atomic_and:
3163 case nir_intrinsic_image_atomic_or:
3164 case nir_intrinsic_image_atomic_xor:
3165 case nir_intrinsic_image_atomic_exchange:
3166 case nir_intrinsic_image_atomic_comp_swap:
3167 result = visit_image_atomic(ctx, instr);
3168 break;
3169 case nir_intrinsic_image_size:
3170 result = visit_image_size(ctx, instr);
3171 break;
3172 case nir_intrinsic_discard:
3173 ctx->shader_info->fs.can_discard = true;
3174 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3175 ctx->voidt,
3176 NULL, 0, 0);
3177 break;
3178 case nir_intrinsic_discard_if:
3179 emit_discard_if(ctx, instr);
3180 break;
3181 case nir_intrinsic_memory_barrier:
3182 emit_waitcnt(ctx);
3183 break;
3184 case nir_intrinsic_barrier:
3185 emit_barrier(ctx);
3186 break;
3187 case nir_intrinsic_var_atomic_add:
3188 case nir_intrinsic_var_atomic_imin:
3189 case nir_intrinsic_var_atomic_umin:
3190 case nir_intrinsic_var_atomic_imax:
3191 case nir_intrinsic_var_atomic_umax:
3192 case nir_intrinsic_var_atomic_and:
3193 case nir_intrinsic_var_atomic_or:
3194 case nir_intrinsic_var_atomic_xor:
3195 case nir_intrinsic_var_atomic_exchange:
3196 case nir_intrinsic_var_atomic_comp_swap:
3197 result = visit_var_atomic(ctx, instr);
3198 break;
3199 case nir_intrinsic_interp_var_at_centroid:
3200 case nir_intrinsic_interp_var_at_sample:
3201 case nir_intrinsic_interp_var_at_offset:
3202 result = visit_interp(ctx, instr);
3203 break;
3204 case nir_intrinsic_emit_vertex:
3205 visit_emit_vertex(ctx, instr);
3206 break;
3207 case nir_intrinsic_end_primitive:
3208 visit_end_primitive(ctx, instr);
3209 break;
3210 default:
3211 fprintf(stderr, "Unknown intrinsic: ");
3212 nir_print_instr(&instr->instr, stderr);
3213 fprintf(stderr, "\n");
3214 break;
3215 }
3216 if (result) {
3217 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3218 }
3219 }
3220
3221 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3222 nir_deref_var *deref,
3223 enum desc_type desc_type)
3224 {
3225 unsigned desc_set = deref->var->data.descriptor_set;
3226 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3227 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3228 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3229 unsigned offset = binding->offset;
3230 unsigned stride = binding->size;
3231 unsigned type_size;
3232 LLVMBuilderRef builder = ctx->builder;
3233 LLVMTypeRef type;
3234 LLVMValueRef index = NULL;
3235
3236 assert(deref->var->data.binding < layout->binding_count);
3237
3238 switch (desc_type) {
3239 case DESC_IMAGE:
3240 type = ctx->v8i32;
3241 type_size = 32;
3242 break;
3243 case DESC_FMASK:
3244 type = ctx->v8i32;
3245 offset += 32;
3246 type_size = 32;
3247 break;
3248 case DESC_SAMPLER:
3249 type = ctx->v4i32;
3250 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3251 offset += 64;
3252
3253 type_size = 16;
3254 break;
3255 case DESC_BUFFER:
3256 type = ctx->v4i32;
3257 type_size = 16;
3258 break;
3259 default:
3260 unreachable("invalid desc_type\n");
3261 }
3262
3263 if (deref->deref.child) {
3264 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3265
3266 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3267 offset += child->base_offset * stride;
3268 if (child->deref_array_type == nir_deref_array_type_indirect) {
3269 index = get_src(ctx, child->indirect);
3270 }
3271 }
3272
3273 assert(stride % type_size == 0);
3274
3275 if (!index)
3276 index = ctx->i32zero;
3277
3278 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3279
3280 list = build_gep0(ctx, list, LLVMConstInt(ctx->i32, offset, 0));
3281 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3282
3283 return build_indexed_load_const(ctx, list, index);
3284 }
3285
3286 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3287 struct ac_tex_info *tinfo,
3288 nir_tex_instr *instr,
3289 nir_texop op,
3290 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3291 LLVMValueRef *param, unsigned count,
3292 unsigned dmask)
3293 {
3294 int num_args;
3295 unsigned is_rect = 0;
3296 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3297
3298 if (op == nir_texop_lod)
3299 da = false;
3300 /* Pad to power of two vector */
3301 while (count < util_next_power_of_two(count))
3302 param[count++] = LLVMGetUndef(ctx->i32);
3303
3304 if (count > 1)
3305 tinfo->args[0] = ac_build_gather_values(&ctx->ac, param, count);
3306 else
3307 tinfo->args[0] = param[0];
3308
3309 tinfo->args[1] = res_ptr;
3310 num_args = 2;
3311
3312 if (op == nir_texop_txf ||
3313 op == nir_texop_txf_ms ||
3314 op == nir_texop_query_levels ||
3315 op == nir_texop_texture_samples ||
3316 op == nir_texop_txs)
3317 tinfo->dst_type = ctx->v4i32;
3318 else {
3319 tinfo->dst_type = ctx->v4f32;
3320 tinfo->args[num_args++] = samp_ptr;
3321 }
3322
3323 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3324 tinfo->args[0] = res_ptr;
3325 tinfo->args[1] = LLVMConstInt(ctx->i32, 0, false);
3326 tinfo->args[2] = param[0];
3327 tinfo->arg_count = 3;
3328 return;
3329 }
3330
3331 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, dmask, 0);
3332 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, is_rect, 0); /* unorm */
3333 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
3334 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
3335 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
3336 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
3337 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
3338 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
3339
3340 tinfo->arg_count = num_args;
3341 }
3342
3343 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3344 *
3345 * SI-CI:
3346 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3347 * filtering manually. The driver sets img7 to a mask clearing
3348 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3349 * s_and_b32 samp0, samp0, img7
3350 *
3351 * VI:
3352 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3353 */
3354 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3355 LLVMValueRef res, LLVMValueRef samp)
3356 {
3357 LLVMBuilderRef builder = ctx->builder;
3358 LLVMValueRef img7, samp0;
3359
3360 if (ctx->options->chip_class >= VI)
3361 return samp;
3362
3363 img7 = LLVMBuildExtractElement(builder, res,
3364 LLVMConstInt(ctx->i32, 7, 0), "");
3365 samp0 = LLVMBuildExtractElement(builder, samp,
3366 LLVMConstInt(ctx->i32, 0, 0), "");
3367 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3368 return LLVMBuildInsertElement(builder, samp, samp0,
3369 LLVMConstInt(ctx->i32, 0, 0), "");
3370 }
3371
3372 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3373 nir_tex_instr *instr,
3374 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3375 LLVMValueRef *fmask_ptr)
3376 {
3377 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3378 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3379 else
3380 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3381 if (samp_ptr) {
3382 if (instr->sampler)
3383 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3384 else
3385 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3386 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3387 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3388 }
3389 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3390 instr->op == nir_texop_samples_identical))
3391 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3392 }
3393
3394 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3395 {
3396 LLVMValueRef result = NULL;
3397 struct ac_tex_info tinfo = { 0 };
3398 unsigned dmask = 0xf;
3399 LLVMValueRef address[16];
3400 LLVMValueRef coords[5];
3401 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3402 LLVMValueRef bias = NULL, offsets = NULL;
3403 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3404 LLVMValueRef ddx = NULL, ddy = NULL;
3405 LLVMValueRef derivs[6];
3406 unsigned chan, count = 0;
3407 unsigned const_src = 0, num_deriv_comp = 0;
3408
3409 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3410
3411 for (unsigned i = 0; i < instr->num_srcs; i++) {
3412 switch (instr->src[i].src_type) {
3413 case nir_tex_src_coord:
3414 coord = get_src(ctx, instr->src[i].src);
3415 break;
3416 case nir_tex_src_projector:
3417 break;
3418 case nir_tex_src_comparator:
3419 comparator = get_src(ctx, instr->src[i].src);
3420 break;
3421 case nir_tex_src_offset:
3422 offsets = get_src(ctx, instr->src[i].src);
3423 const_src = i;
3424 break;
3425 case nir_tex_src_bias:
3426 bias = get_src(ctx, instr->src[i].src);
3427 break;
3428 case nir_tex_src_lod:
3429 lod = get_src(ctx, instr->src[i].src);
3430 break;
3431 case nir_tex_src_ms_index:
3432 sample_index = get_src(ctx, instr->src[i].src);
3433 break;
3434 case nir_tex_src_ms_mcs:
3435 break;
3436 case nir_tex_src_ddx:
3437 ddx = get_src(ctx, instr->src[i].src);
3438 num_deriv_comp = instr->src[i].src.ssa->num_components;
3439 break;
3440 case nir_tex_src_ddy:
3441 ddy = get_src(ctx, instr->src[i].src);
3442 break;
3443 case nir_tex_src_texture_offset:
3444 case nir_tex_src_sampler_offset:
3445 case nir_tex_src_plane:
3446 default:
3447 break;
3448 }
3449 }
3450
3451 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3452 result = get_buffer_size(ctx, res_ptr, false);
3453 goto write_result;
3454 }
3455
3456 if (instr->op == nir_texop_texture_samples) {
3457 LLVMValueRef res, samples, is_msaa;
3458 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3459 samples = LLVMBuildExtractElement(ctx->builder, res,
3460 LLVMConstInt(ctx->i32, 3, false), "");
3461 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3462 LLVMConstInt(ctx->i32, 28, false), "");
3463 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3464 LLVMConstInt(ctx->i32, 0xe, false), "");
3465 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3466 LLVMConstInt(ctx->i32, 0xe, false), "");
3467
3468 samples = LLVMBuildLShr(ctx->builder, samples,
3469 LLVMConstInt(ctx->i32, 16, false), "");
3470 samples = LLVMBuildAnd(ctx->builder, samples,
3471 LLVMConstInt(ctx->i32, 0xf, false), "");
3472 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3473 samples, "");
3474 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3475 ctx->i32one, "");
3476 result = samples;
3477 goto write_result;
3478 }
3479
3480 if (coord)
3481 for (chan = 0; chan < instr->coord_components; chan++)
3482 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3483
3484 if (offsets && instr->op != nir_texop_txf) {
3485 LLVMValueRef offset[3], pack;
3486 for (chan = 0; chan < 3; ++chan)
3487 offset[chan] = ctx->i32zero;
3488
3489 tinfo.has_offset = true;
3490 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3491 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3492 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3493 LLVMConstInt(ctx->i32, 0x3f, false), "");
3494 if (chan)
3495 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3496 LLVMConstInt(ctx->i32, chan * 8, false), "");
3497 }
3498 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3499 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3500 address[count++] = pack;
3501
3502 }
3503 /* pack LOD bias value */
3504 if (instr->op == nir_texop_txb && bias) {
3505 address[count++] = bias;
3506 }
3507
3508 /* Pack depth comparison value */
3509 if (instr->is_shadow && comparator) {
3510 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3511 }
3512
3513 /* pack derivatives */
3514 if (ddx || ddy) {
3515 switch (instr->sampler_dim) {
3516 case GLSL_SAMPLER_DIM_3D:
3517 case GLSL_SAMPLER_DIM_CUBE:
3518 num_deriv_comp = 3;
3519 break;
3520 case GLSL_SAMPLER_DIM_2D:
3521 default:
3522 num_deriv_comp = 2;
3523 break;
3524 case GLSL_SAMPLER_DIM_1D:
3525 num_deriv_comp = 1;
3526 break;
3527 }
3528
3529 for (unsigned i = 0; i < num_deriv_comp; i++) {
3530 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3531 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3532 }
3533 }
3534
3535 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3536 for (chan = 0; chan < instr->coord_components; chan++)
3537 coords[chan] = to_float(ctx, coords[chan]);
3538 if (instr->coord_components == 3)
3539 coords[3] = LLVMGetUndef(ctx->f32);
3540 ac_prepare_cube_coords(&ctx->ac,
3541 instr->op == nir_texop_txd, instr->is_array,
3542 coords, derivs);
3543 if (num_deriv_comp)
3544 num_deriv_comp--;
3545 }
3546
3547 if (ddx || ddy) {
3548 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3549 address[count++] = derivs[i];
3550 }
3551
3552 /* Pack texture coordinates */
3553 if (coord) {
3554 address[count++] = coords[0];
3555 if (instr->coord_components > 1)
3556 address[count++] = coords[1];
3557 if (instr->coord_components > 2) {
3558 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3559 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3560 coords[2] = to_float(ctx, coords[2]);
3561 coords[2] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coords[2],
3562 1, 0);
3563 coords[2] = to_integer(ctx, coords[2]);
3564 }
3565 address[count++] = coords[2];
3566 }
3567 }
3568
3569 /* Pack LOD */
3570 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3571 address[count++] = lod;
3572 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3573 address[count++] = sample_index;
3574 } else if(instr->op == nir_texop_txs) {
3575 count = 0;
3576 if (lod)
3577 address[count++] = lod;
3578 else
3579 address[count++] = ctx->i32zero;
3580 }
3581
3582 for (chan = 0; chan < count; chan++) {
3583 address[chan] = LLVMBuildBitCast(ctx->builder,
3584 address[chan], ctx->i32, "");
3585 }
3586
3587 if (instr->op == nir_texop_samples_identical) {
3588 LLVMValueRef txf_address[4];
3589 struct ac_tex_info txf_info = { 0 };
3590 unsigned txf_count = count;
3591 memcpy(txf_address, address, sizeof(txf_address));
3592
3593 if (!instr->is_array)
3594 txf_address[2] = ctx->i32zero;
3595 txf_address[3] = ctx->i32zero;
3596
3597 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3598 fmask_ptr, NULL,
3599 txf_address, txf_count, 0xf);
3600
3601 result = build_tex_intrinsic(ctx, instr, &txf_info);
3602
3603 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3604 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3605 goto write_result;
3606 }
3607
3608 /* Adjust the sample index according to FMASK.
3609 *
3610 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3611 * which is the identity mapping. Each nibble says which physical sample
3612 * should be fetched to get that sample.
3613 *
3614 * For example, 0x11111100 means there are only 2 samples stored and
3615 * the second sample covers 3/4 of the pixel. When reading samples 0
3616 * and 1, return physical sample 0 (determined by the first two 0s
3617 * in FMASK), otherwise return physical sample 1.
3618 *
3619 * The sample index should be adjusted as follows:
3620 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3621 */
3622 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS) {
3623 LLVMValueRef txf_address[4];
3624 struct ac_tex_info txf_info = { 0 };
3625 unsigned txf_count = count;
3626 memcpy(txf_address, address, sizeof(txf_address));
3627
3628 if (!instr->is_array)
3629 txf_address[2] = ctx->i32zero;
3630 txf_address[3] = ctx->i32zero;
3631
3632 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3633 fmask_ptr, NULL,
3634 txf_address, txf_count, 0xf);
3635
3636 result = build_tex_intrinsic(ctx, instr, &txf_info);
3637 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3638 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3639
3640 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3641 result,
3642 ctx->i32zero, "");
3643
3644 unsigned sample_chan = instr->is_array ? 3 : 2;
3645
3646 LLVMValueRef sample_index4 =
3647 LLVMBuildMul(ctx->builder, address[sample_chan], four, "");
3648 LLVMValueRef shifted_fmask =
3649 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3650 LLVMValueRef final_sample =
3651 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3652
3653 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3654 * resource descriptor is 0 (invalid),
3655 */
3656 LLVMValueRef fmask_desc =
3657 LLVMBuildBitCast(ctx->builder, fmask_ptr,
3658 ctx->v8i32, "");
3659
3660 LLVMValueRef fmask_word1 =
3661 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3662 ctx->i32one, "");
3663
3664 LLVMValueRef word1_is_nonzero =
3665 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3666 fmask_word1, ctx->i32zero, "");
3667
3668 /* Replace the MSAA sample index. */
3669 address[sample_chan] =
3670 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3671 final_sample, address[sample_chan], "");
3672 }
3673
3674 if (offsets && instr->op == nir_texop_txf) {
3675 nir_const_value *const_offset =
3676 nir_src_as_const_value(instr->src[const_src].src);
3677 int num_offsets = instr->src[const_src].src.ssa->num_components;
3678 assert(const_offset);
3679 num_offsets = MIN2(num_offsets, instr->coord_components);
3680 if (num_offsets > 2)
3681 address[2] = LLVMBuildAdd(ctx->builder,
3682 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3683 if (num_offsets > 1)
3684 address[1] = LLVMBuildAdd(ctx->builder,
3685 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3686 address[0] = LLVMBuildAdd(ctx->builder,
3687 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3688
3689 }
3690
3691 /* TODO TG4 support */
3692 if (instr->op == nir_texop_tg4) {
3693 if (instr->is_shadow)
3694 dmask = 1;
3695 else
3696 dmask = 1 << instr->component;
3697 }
3698 set_tex_fetch_args(ctx, &tinfo, instr, instr->op,
3699 res_ptr, samp_ptr, address, count, dmask);
3700
3701 result = build_tex_intrinsic(ctx, instr, &tinfo);
3702
3703 if (instr->op == nir_texop_query_levels)
3704 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3705 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3706 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3707 else if (instr->op == nir_texop_txs &&
3708 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3709 instr->is_array) {
3710 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3711 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3712 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3713 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3714 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3715 } else if (instr->dest.ssa.num_components != 4)
3716 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3717
3718 write_result:
3719 if (result) {
3720 assert(instr->dest.is_ssa);
3721 result = to_integer(ctx, result);
3722 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3723 }
3724 }
3725
3726
3727 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3728 {
3729 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3730 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3731
3732 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3733 _mesa_hash_table_insert(ctx->phis, instr, result);
3734 }
3735
3736 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3737 nir_phi_instr *instr,
3738 LLVMValueRef llvm_phi)
3739 {
3740 nir_foreach_phi_src(src, instr) {
3741 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3742 LLVMValueRef llvm_src = get_src(ctx, src->src);
3743
3744 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3745 }
3746 }
3747
3748 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3749 {
3750 struct hash_entry *entry;
3751 hash_table_foreach(ctx->phis, entry) {
3752 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3753 (LLVMValueRef)entry->data);
3754 }
3755 }
3756
3757
3758 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3759 nir_ssa_undef_instr *instr)
3760 {
3761 unsigned num_components = instr->def.num_components;
3762 LLVMValueRef undef;
3763
3764 if (num_components == 1)
3765 undef = LLVMGetUndef(ctx->i32);
3766 else {
3767 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3768 }
3769 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3770 }
3771
3772 static void visit_jump(struct nir_to_llvm_context *ctx,
3773 nir_jump_instr *instr)
3774 {
3775 switch (instr->type) {
3776 case nir_jump_break:
3777 LLVMBuildBr(ctx->builder, ctx->break_block);
3778 LLVMClearInsertionPosition(ctx->builder);
3779 break;
3780 case nir_jump_continue:
3781 LLVMBuildBr(ctx->builder, ctx->continue_block);
3782 LLVMClearInsertionPosition(ctx->builder);
3783 break;
3784 default:
3785 fprintf(stderr, "Unknown NIR jump instr: ");
3786 nir_print_instr(&instr->instr, stderr);
3787 fprintf(stderr, "\n");
3788 abort();
3789 }
3790 }
3791
3792 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3793 struct exec_list *list);
3794
3795 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3796 {
3797 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3798 nir_foreach_instr(instr, block)
3799 {
3800 switch (instr->type) {
3801 case nir_instr_type_alu:
3802 visit_alu(ctx, nir_instr_as_alu(instr));
3803 break;
3804 case nir_instr_type_load_const:
3805 visit_load_const(ctx, nir_instr_as_load_const(instr));
3806 break;
3807 case nir_instr_type_intrinsic:
3808 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3809 break;
3810 case nir_instr_type_tex:
3811 visit_tex(ctx, nir_instr_as_tex(instr));
3812 break;
3813 case nir_instr_type_phi:
3814 visit_phi(ctx, nir_instr_as_phi(instr));
3815 break;
3816 case nir_instr_type_ssa_undef:
3817 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3818 break;
3819 case nir_instr_type_jump:
3820 visit_jump(ctx, nir_instr_as_jump(instr));
3821 break;
3822 default:
3823 fprintf(stderr, "Unknown NIR instr type: ");
3824 nir_print_instr(instr, stderr);
3825 fprintf(stderr, "\n");
3826 abort();
3827 }
3828 }
3829
3830 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3831 }
3832
3833 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3834 {
3835 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3836
3837 LLVMBasicBlockRef merge_block =
3838 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3839 LLVMBasicBlockRef if_block =
3840 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3841 LLVMBasicBlockRef else_block = merge_block;
3842 if (!exec_list_is_empty(&if_stmt->else_list))
3843 else_block = LLVMAppendBasicBlockInContext(
3844 ctx->context, ctx->main_function, "");
3845
3846 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3847 LLVMConstInt(ctx->i32, 0, false), "");
3848 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3849
3850 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3851 visit_cf_list(ctx, &if_stmt->then_list);
3852 if (LLVMGetInsertBlock(ctx->builder))
3853 LLVMBuildBr(ctx->builder, merge_block);
3854
3855 if (!exec_list_is_empty(&if_stmt->else_list)) {
3856 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3857 visit_cf_list(ctx, &if_stmt->else_list);
3858 if (LLVMGetInsertBlock(ctx->builder))
3859 LLVMBuildBr(ctx->builder, merge_block);
3860 }
3861
3862 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3863 }
3864
3865 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3866 {
3867 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3868 LLVMBasicBlockRef break_parent = ctx->break_block;
3869
3870 ctx->continue_block =
3871 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3872 ctx->break_block =
3873 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3874
3875 LLVMBuildBr(ctx->builder, ctx->continue_block);
3876 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
3877 visit_cf_list(ctx, &loop->body);
3878
3879 if (LLVMGetInsertBlock(ctx->builder))
3880 LLVMBuildBr(ctx->builder, ctx->continue_block);
3881 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
3882
3883 ctx->continue_block = continue_parent;
3884 ctx->break_block = break_parent;
3885 }
3886
3887 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3888 struct exec_list *list)
3889 {
3890 foreach_list_typed(nir_cf_node, node, node, list)
3891 {
3892 switch (node->type) {
3893 case nir_cf_node_block:
3894 visit_block(ctx, nir_cf_node_as_block(node));
3895 break;
3896
3897 case nir_cf_node_if:
3898 visit_if(ctx, nir_cf_node_as_if(node));
3899 break;
3900
3901 case nir_cf_node_loop:
3902 visit_loop(ctx, nir_cf_node_as_loop(node));
3903 break;
3904
3905 default:
3906 assert(0);
3907 }
3908 }
3909 }
3910
3911 static void
3912 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
3913 struct nir_variable *variable)
3914 {
3915 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
3916 LLVMValueRef t_offset;
3917 LLVMValueRef t_list;
3918 LLVMValueRef args[3];
3919 LLVMValueRef input;
3920 LLVMValueRef buffer_index;
3921 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
3922 int idx = variable->data.location;
3923 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
3924
3925 variable->data.driver_location = idx * 4;
3926
3927 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
3928 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
3929 ctx->start_instance, "");
3930 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3931 ctx->shader_info->vs.vgpr_comp_cnt);
3932 } else
3933 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
3934 ctx->base_vertex, "");
3935
3936 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
3937 t_offset = LLVMConstInt(ctx->i32, index + i, false);
3938
3939 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
3940 args[0] = t_list;
3941 args[1] = LLVMConstInt(ctx->i32, 0, false);
3942 args[2] = buffer_index;
3943 input = ac_emit_llvm_intrinsic(&ctx->ac,
3944 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
3945 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
3946
3947 for (unsigned chan = 0; chan < 4; chan++) {
3948 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3949 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
3950 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
3951 input, llvm_chan, ""));
3952 }
3953 }
3954 }
3955
3956
3957 static void interp_fs_input(struct nir_to_llvm_context *ctx,
3958 unsigned attr,
3959 LLVMValueRef interp_param,
3960 LLVMValueRef prim_mask,
3961 LLVMValueRef result[4])
3962 {
3963 const char *intr_name;
3964 LLVMValueRef attr_number;
3965 unsigned chan;
3966
3967 attr_number = LLVMConstInt(ctx->i32, attr, false);
3968
3969 /* fs.constant returns the param from the middle vertex, so it's not
3970 * really useful for flat shading. It's meant to be used for custom
3971 * interpolation (but the intrinsic can't fetch from the other two
3972 * vertices).
3973 *
3974 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
3975 * to do the right thing. The only reason we use fs.constant is that
3976 * fs.interp cannot be used on integers, because they can be equal
3977 * to NaN.
3978 */
3979 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3980
3981 for (chan = 0; chan < 4; chan++) {
3982 LLVMValueRef args[4];
3983 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3984
3985 args[0] = llvm_chan;
3986 args[1] = attr_number;
3987 args[2] = prim_mask;
3988 args[3] = interp_param;
3989 result[chan] = ac_emit_llvm_intrinsic(&ctx->ac, intr_name,
3990 ctx->f32, args, args[3] ? 4 : 3,
3991 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
3992 }
3993 }
3994
3995 static void
3996 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
3997 struct nir_variable *variable)
3998 {
3999 int idx = variable->data.location;
4000 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4001 LLVMValueRef interp;
4002
4003 variable->data.driver_location = idx * 4;
4004 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4005
4006 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4007 unsigned interp_type;
4008 if (variable->data.sample) {
4009 interp_type = INTERP_SAMPLE;
4010 ctx->shader_info->fs.force_persample = true;
4011 } else if (variable->data.centroid)
4012 interp_type = INTERP_CENTROID;
4013 else
4014 interp_type = INTERP_CENTER;
4015
4016 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4017 } else
4018 interp = NULL;
4019
4020 for (unsigned i = 0; i < attrib_count; ++i)
4021 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4022
4023 }
4024
4025 static void
4026 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4027 struct nir_variable *variable)
4028 {
4029 switch (ctx->stage) {
4030 case MESA_SHADER_VERTEX:
4031 handle_vs_input_decl(ctx, variable);
4032 break;
4033 case MESA_SHADER_FRAGMENT:
4034 handle_fs_input_decl(ctx, variable);
4035 break;
4036 default:
4037 break;
4038 }
4039
4040 }
4041
4042 static void
4043 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4044 struct nir_shader *nir)
4045 {
4046 unsigned index = 0;
4047 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4048 LLVMValueRef interp_param;
4049 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4050
4051 if (!(ctx->input_mask & (1ull << i)))
4052 continue;
4053
4054 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC) {
4055 interp_param = *inputs;
4056 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4057 inputs);
4058
4059 if (!interp_param)
4060 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4061 ++index;
4062 } else if (i == VARYING_SLOT_POS) {
4063 for(int i = 0; i < 3; ++i)
4064 inputs[i] = ctx->frag_pos[i];
4065
4066 inputs[3] = ac_emit_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4067 }
4068 }
4069 ctx->shader_info->fs.num_interp = index;
4070 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4071 ctx->shader_info->fs.has_pcoord = true;
4072 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4073 }
4074
4075 static LLVMValueRef
4076 ac_build_alloca(struct nir_to_llvm_context *ctx,
4077 LLVMTypeRef type,
4078 const char *name)
4079 {
4080 LLVMBuilderRef builder = ctx->builder;
4081 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4082 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4083 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4084 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4085 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4086 LLVMValueRef res;
4087
4088 if (first_instr) {
4089 LLVMPositionBuilderBefore(first_builder, first_instr);
4090 } else {
4091 LLVMPositionBuilderAtEnd(first_builder, first_block);
4092 }
4093
4094 res = LLVMBuildAlloca(first_builder, type, name);
4095 LLVMBuildStore(builder, LLVMConstNull(type), res);
4096
4097 LLVMDisposeBuilder(first_builder);
4098
4099 return res;
4100 }
4101
4102 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4103 LLVMTypeRef type,
4104 const char *name)
4105 {
4106 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4107 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4108 return ptr;
4109 }
4110
4111 static void
4112 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4113 struct nir_variable *variable)
4114 {
4115 int idx = variable->data.location + variable->data.index;
4116 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4117
4118 variable->data.driver_location = idx * 4;
4119
4120 if (ctx->stage == MESA_SHADER_VERTEX) {
4121
4122 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4123 idx == VARYING_SLOT_CULL_DIST0) {
4124 int length = glsl_get_length(variable->type);
4125 if (idx == VARYING_SLOT_CLIP_DIST0) {
4126 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
4127 ctx->num_clips = length;
4128 } else if (idx == VARYING_SLOT_CULL_DIST0) {
4129 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
4130 ctx->num_culls = length;
4131 }
4132 if (length > 4)
4133 attrib_count = 2;
4134 else
4135 attrib_count = 1;
4136 }
4137 }
4138
4139 for (unsigned i = 0; i < attrib_count; ++i) {
4140 for (unsigned chan = 0; chan < 4; chan++) {
4141 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4142 si_build_alloca_undef(ctx, ctx->f32, "");
4143 }
4144 }
4145 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
4146 }
4147
4148 static void
4149 setup_locals(struct nir_to_llvm_context *ctx,
4150 struct nir_function *func)
4151 {
4152 int i, j;
4153 ctx->num_locals = 0;
4154 nir_foreach_variable(variable, &func->impl->locals) {
4155 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4156 variable->data.driver_location = ctx->num_locals * 4;
4157 ctx->num_locals += attrib_count;
4158 }
4159 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4160 if (!ctx->locals)
4161 return;
4162
4163 for (i = 0; i < ctx->num_locals; i++) {
4164 for (j = 0; j < 4; j++) {
4165 ctx->locals[i * 4 + j] =
4166 si_build_alloca_undef(ctx, ctx->f32, "temp");
4167 }
4168 }
4169 }
4170
4171 static LLVMValueRef
4172 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4173 {
4174 v = to_float(ctx, v);
4175 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", v, LLVMConstReal(ctx->f32, lo));
4176 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", v, LLVMConstReal(ctx->f32, hi));
4177 }
4178
4179
4180 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4181 LLVMValueRef src0, LLVMValueRef src1)
4182 {
4183 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4184 LLVMValueRef comp[2];
4185
4186 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4187 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4188 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4189 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4190 }
4191
4192 /* Initialize arguments for the shader export intrinsic */
4193 static void
4194 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4195 LLVMValueRef *values,
4196 unsigned target,
4197 LLVMValueRef *args)
4198 {
4199 /* Default is 0xf. Adjusted below depending on the format. */
4200 args[0] = LLVMConstInt(ctx->i32, target != V_008DFC_SQ_EXP_NULL ? 0xf : 0, false);
4201 /* Specify whether the EXEC mask represents the valid mask */
4202 args[1] = LLVMConstInt(ctx->i32, 0, false);
4203
4204 /* Specify whether this is the last export */
4205 args[2] = LLVMConstInt(ctx->i32, 0, false);
4206 /* Specify the target we are exporting */
4207 args[3] = LLVMConstInt(ctx->i32, target, false);
4208
4209 args[4] = LLVMConstInt(ctx->i32, 0, false); /* COMPR flag */
4210 args[5] = LLVMGetUndef(ctx->f32);
4211 args[6] = LLVMGetUndef(ctx->f32);
4212 args[7] = LLVMGetUndef(ctx->f32);
4213 args[8] = LLVMGetUndef(ctx->f32);
4214
4215 if (!values)
4216 return;
4217
4218 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4219 LLVMValueRef val[4];
4220 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4221 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4222 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4223
4224 switch(col_format) {
4225 case V_028714_SPI_SHADER_ZERO:
4226 args[0] = LLVMConstInt(ctx->i32, 0x0, 0);
4227 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_NULL, 0);
4228 break;
4229
4230 case V_028714_SPI_SHADER_32_R:
4231 args[0] = LLVMConstInt(ctx->i32, 0x1, 0);
4232 args[5] = values[0];
4233 break;
4234
4235 case V_028714_SPI_SHADER_32_GR:
4236 args[0] = LLVMConstInt(ctx->i32, 0x3, 0);
4237 args[5] = values[0];
4238 args[6] = values[1];
4239 break;
4240
4241 case V_028714_SPI_SHADER_32_AR:
4242 args[0] = LLVMConstInt(ctx->i32, 0x9, 0);
4243 args[5] = values[0];
4244 args[8] = values[3];
4245 break;
4246
4247 case V_028714_SPI_SHADER_FP16_ABGR:
4248 args[4] = ctx->i32one;
4249
4250 for (unsigned chan = 0; chan < 2; chan++) {
4251 LLVMValueRef pack_args[2] = {
4252 values[2 * chan],
4253 values[2 * chan + 1]
4254 };
4255 LLVMValueRef packed;
4256
4257 packed = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.packf16",
4258 ctx->i32, pack_args, 2,
4259 AC_FUNC_ATTR_READNONE);
4260 args[chan + 5] = packed;
4261 }
4262 break;
4263
4264 case V_028714_SPI_SHADER_UNORM16_ABGR:
4265 for (unsigned chan = 0; chan < 4; chan++) {
4266 val[chan] = emit_float_saturate(ctx, values[chan], 0, 1);
4267 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4268 LLVMConstReal(ctx->f32, 65535), "");
4269 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4270 LLVMConstReal(ctx->f32, 0.5), "");
4271 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4272 ctx->i32, "");
4273 }
4274
4275 args[4] = ctx->i32one;
4276 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4277 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4278 break;
4279
4280 case V_028714_SPI_SHADER_SNORM16_ABGR:
4281 for (unsigned chan = 0; chan < 4; chan++) {
4282 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4283 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4284 LLVMConstReal(ctx->f32, 32767), "");
4285
4286 /* If positive, add 0.5, else add -0.5. */
4287 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4288 LLVMBuildSelect(ctx->builder,
4289 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4290 val[chan], ctx->f32zero, ""),
4291 LLVMConstReal(ctx->f32, 0.5),
4292 LLVMConstReal(ctx->f32, -0.5), ""), "");
4293 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4294 }
4295
4296 args[4] = ctx->i32one;
4297 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4298 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4299 break;
4300
4301 case V_028714_SPI_SHADER_UINT16_ABGR: {
4302 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4303
4304 for (unsigned chan = 0; chan < 4; chan++) {
4305 val[chan] = to_integer(ctx, values[chan]);
4306 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4307 }
4308
4309 args[4] = ctx->i32one;
4310 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4311 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4312 break;
4313 }
4314
4315 case V_028714_SPI_SHADER_SINT16_ABGR: {
4316 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4317 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4318
4319 /* Clamp. */
4320 for (unsigned chan = 0; chan < 4; chan++) {
4321 val[chan] = to_integer(ctx, values[chan]);
4322 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4323 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4324 }
4325
4326 args[4] = ctx->i32one;
4327 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4328 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4329 break;
4330 }
4331
4332 default:
4333 case V_028714_SPI_SHADER_32_ABGR:
4334 memcpy(&args[5], values, sizeof(values[0]) * 4);
4335 break;
4336 }
4337 } else
4338 memcpy(&args[5], values, sizeof(values[0]) * 4);
4339
4340 for (unsigned i = 5; i < 9; ++i)
4341 args[i] = to_float(ctx, args[i]);
4342 }
4343
4344 static void
4345 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4346 {
4347 uint32_t param_count = 0;
4348 unsigned target;
4349 unsigned pos_idx, num_pos_exports = 0;
4350 LLVMValueRef args[9];
4351 LLVMValueRef pos_args[4][9] = { { 0 } };
4352 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4353 int i;
4354 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4355 (1ull << VARYING_SLOT_CLIP_DIST1) |
4356 (1ull << VARYING_SLOT_CULL_DIST0) |
4357 (1ull << VARYING_SLOT_CULL_DIST1));
4358
4359 if (clip_mask) {
4360 LLVMValueRef slots[8];
4361 unsigned j;
4362
4363 if (ctx->shader_info->vs.cull_dist_mask)
4364 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_clips;
4365
4366 i = VARYING_SLOT_CLIP_DIST0;
4367 for (j = 0; j < ctx->num_clips; j++)
4368 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4369 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4370 i = VARYING_SLOT_CULL_DIST0;
4371 for (j = 0; j < ctx->num_culls; j++)
4372 slots[ctx->num_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4373 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4374
4375 for (i = ctx->num_clips + ctx->num_culls; i < 8; i++)
4376 slots[i] = LLVMGetUndef(ctx->f32);
4377
4378 if (ctx->num_clips + ctx->num_culls > 4) {
4379 target = V_008DFC_SQ_EXP_POS + 3;
4380 si_llvm_init_export_args(ctx, &slots[4], target, args);
4381 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4382 args, sizeof(args));
4383 }
4384
4385 target = V_008DFC_SQ_EXP_POS + 2;
4386 si_llvm_init_export_args(ctx, &slots[0], target, args);
4387 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4388 args, sizeof(args));
4389
4390 }
4391
4392 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4393 LLVMValueRef values[4];
4394 if (!(ctx->output_mask & (1ull << i)))
4395 continue;
4396
4397 for (unsigned j = 0; j < 4; j++)
4398 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4399 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4400
4401 if (i == VARYING_SLOT_POS) {
4402 target = V_008DFC_SQ_EXP_POS;
4403 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4404 i == VARYING_SLOT_CLIP_DIST1 ||
4405 i == VARYING_SLOT_CULL_DIST0 ||
4406 i == VARYING_SLOT_CULL_DIST1) {
4407 continue;
4408 } else if (i == VARYING_SLOT_PSIZ) {
4409 ctx->shader_info->vs.writes_pointsize = true;
4410 psize_value = values[0];
4411 continue;
4412 } else if (i == VARYING_SLOT_LAYER) {
4413 ctx->shader_info->vs.writes_layer = true;
4414 layer_value = values[0];
4415 continue;
4416 } else if (i == VARYING_SLOT_VIEWPORT) {
4417 ctx->shader_info->vs.writes_viewport_index = true;
4418 viewport_index_value = values[0];
4419 continue;
4420 } else if (i >= VARYING_SLOT_VAR0) {
4421 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4422 target = V_008DFC_SQ_EXP_PARAM + param_count;
4423 param_count++;
4424 }
4425
4426 si_llvm_init_export_args(ctx, values, target, args);
4427
4428 if (target >= V_008DFC_SQ_EXP_POS &&
4429 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4430 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4431 args, sizeof(args));
4432 } else {
4433 ac_emit_llvm_intrinsic(&ctx->ac,
4434 "llvm.SI.export",
4435 ctx->voidt,
4436 args, 9, 0);
4437 }
4438 }
4439
4440 /* We need to add the position output manually if it's missing. */
4441 if (!pos_args[0][0]) {
4442 pos_args[0][0] = LLVMConstInt(ctx->i32, 0xf, false);
4443 pos_args[0][1] = ctx->i32zero; /* EXEC mask */
4444 pos_args[0][2] = ctx->i32zero; /* last export? */
4445 pos_args[0][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS, false);
4446 pos_args[0][4] = ctx->i32zero; /* COMPR flag */
4447 pos_args[0][5] = ctx->f32zero; /* X */
4448 pos_args[0][6] = ctx->f32zero; /* Y */
4449 pos_args[0][7] = ctx->f32zero; /* Z */
4450 pos_args[0][8] = ctx->f32one; /* W */
4451 }
4452
4453 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4454 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4455 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4456 if (mask) {
4457 pos_args[1][0] = LLVMConstInt(ctx->i32, mask, false); /* writemask */
4458 pos_args[1][1] = ctx->i32zero; /* EXEC mask */
4459 pos_args[1][2] = ctx->i32zero; /* last export? */
4460 pos_args[1][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + 1, false);
4461 pos_args[1][4] = ctx->i32zero; /* COMPR flag */
4462 pos_args[1][5] = ctx->f32zero; /* X */
4463 pos_args[1][6] = ctx->f32zero; /* Y */
4464 pos_args[1][7] = ctx->f32zero; /* Z */
4465 pos_args[1][8] = ctx->f32zero; /* W */
4466
4467 if (ctx->shader_info->vs.writes_pointsize == true)
4468 pos_args[1][5] = psize_value;
4469 if (ctx->shader_info->vs.writes_layer == true)
4470 pos_args[1][7] = layer_value;
4471 if (ctx->shader_info->vs.writes_viewport_index == true)
4472 pos_args[1][8] = viewport_index_value;
4473 }
4474 for (i = 0; i < 4; i++) {
4475 if (pos_args[i][0])
4476 num_pos_exports++;
4477 }
4478
4479 pos_idx = 0;
4480 for (i = 0; i < 4; i++) {
4481 if (!pos_args[i][0])
4482 continue;
4483
4484 /* Specify the target we are exporting */
4485 pos_args[i][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + pos_idx++, false);
4486 if (pos_idx == num_pos_exports)
4487 pos_args[i][2] = ctx->i32one;
4488 ac_emit_llvm_intrinsic(&ctx->ac,
4489 "llvm.SI.export",
4490 ctx->voidt,
4491 pos_args[i], 9, 0);
4492 }
4493
4494 ctx->shader_info->vs.pos_exports = num_pos_exports;
4495 ctx->shader_info->vs.param_exports = param_count;
4496 }
4497
4498 static void
4499 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4500 LLVMValueRef *color, unsigned param, bool is_last)
4501 {
4502 LLVMValueRef args[9];
4503 /* Export */
4504 si_llvm_init_export_args(ctx, color, param,
4505 args);
4506
4507 if (is_last) {
4508 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4509 args[2] = ctx->i32one; /* DONE bit */
4510 } else if (args[0] == ctx->i32zero)
4511 return; /* unnecessary NULL export */
4512
4513 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4514 ctx->voidt, args, 9, 0);
4515 }
4516
4517 static void
4518 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4519 LLVMValueRef depth, LLVMValueRef stencil,
4520 LLVMValueRef samplemask)
4521 {
4522 LLVMValueRef args[9];
4523 unsigned mask = 0;
4524 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4525 args[2] = ctx->i32one; /* DONE bit */
4526 /* Specify the target we are exporting */
4527 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_MRTZ, false);
4528
4529 args[4] = ctx->i32zero; /* COMP flag */
4530 args[5] = LLVMGetUndef(ctx->f32); /* R, depth */
4531 args[6] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4532 args[7] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4533 args[8] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4534
4535 if (depth) {
4536 args[5] = depth;
4537 mask |= 0x1;
4538 }
4539
4540 if (stencil) {
4541 args[6] = stencil;
4542 mask |= 0x2;
4543 }
4544
4545 if (samplemask) {
4546 args[7] = samplemask;
4547 mask |= 0x04;
4548 }
4549
4550 /* SI (except OLAND) has a bug that it only looks
4551 * at the X writemask component. */
4552 if (ctx->options->chip_class == SI &&
4553 ctx->options->family != CHIP_OLAND)
4554 mask |= 0x01;
4555
4556 args[0] = LLVMConstInt(ctx->i32, mask, false);
4557 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4558 ctx->voidt, args, 9, 0);
4559 }
4560
4561 static void
4562 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4563 {
4564 unsigned index = 0;
4565 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4566
4567 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4568 LLVMValueRef values[4];
4569
4570 if (!(ctx->output_mask & (1ull << i)))
4571 continue;
4572
4573 if (i == FRAG_RESULT_DEPTH) {
4574 ctx->shader_info->fs.writes_z = true;
4575 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4576 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4577 } else if (i == FRAG_RESULT_STENCIL) {
4578 ctx->shader_info->fs.writes_stencil = true;
4579 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4580 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4581 } else {
4582 bool last = false;
4583 for (unsigned j = 0; j < 4; j++)
4584 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4585 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4586
4587 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil)
4588 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4589
4590 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4591 index++;
4592 }
4593 }
4594
4595 if (depth || stencil)
4596 si_export_mrt_z(ctx, depth, stencil, samplemask);
4597 else if (!index)
4598 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4599
4600 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4601 }
4602
4603 static void
4604 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4605 {
4606 LLVMValueRef args[2];
4607
4608 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE, false);
4609 args[1] = ctx->gs_wave_id;
4610 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg",
4611 ctx->voidt, args, 2, 0);
4612 }
4613
4614 static void
4615 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4616 {
4617 switch (ctx->stage) {
4618 case MESA_SHADER_VERTEX:
4619 handle_vs_outputs_post(ctx);
4620 break;
4621 case MESA_SHADER_FRAGMENT:
4622 handle_fs_outputs_post(ctx);
4623 break;
4624 case MESA_SHADER_GEOMETRY:
4625 emit_gs_epilogue(ctx);
4626 break;
4627 default:
4628 break;
4629 }
4630 }
4631
4632 static void
4633 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4634 struct nir_variable *variable, uint32_t *offset, int idx)
4635 {
4636 unsigned size = glsl_count_attribute_slots(variable->type, false);
4637 variable->data.driver_location = *offset;
4638 *offset += size;
4639 }
4640
4641 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4642 {
4643 LLVMPassManagerRef passmgr;
4644 /* Create the pass manager */
4645 passmgr = LLVMCreateFunctionPassManagerForModule(
4646 ctx->module);
4647
4648 /* This pass should eliminate all the load and store instructions */
4649 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4650
4651 /* Add some optimization passes */
4652 LLVMAddScalarReplAggregatesPass(passmgr);
4653 LLVMAddLICMPass(passmgr);
4654 LLVMAddAggressiveDCEPass(passmgr);
4655 LLVMAddCFGSimplificationPass(passmgr);
4656 LLVMAddInstructionCombiningPass(passmgr);
4657
4658 /* Run the pass */
4659 LLVMInitializeFunctionPassManager(passmgr);
4660 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4661 LLVMFinalizeFunctionPassManager(passmgr);
4662
4663 LLVMDisposeBuilder(ctx->builder);
4664 LLVMDisposePassManager(passmgr);
4665 }
4666
4667 static void
4668 ac_setup_rings(struct nir_to_llvm_context *ctx)
4669 {
4670 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4671 ctx->esgs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, ctx->i32one);
4672 }
4673
4674 if (ctx->is_gs_copy_shader) {
4675 ctx->gsvs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4676 }
4677 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4678 LLVMValueRef tmp;
4679 ctx->esgs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4680 ctx->gsvs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4681
4682 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4683
4684 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4685 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4686 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4687 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4688
4689 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4690 }
4691 }
4692
4693 static
4694 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4695 struct nir_shader *nir,
4696 struct ac_shader_variant_info *shader_info,
4697 const struct ac_nir_compiler_options *options)
4698 {
4699 struct nir_to_llvm_context ctx = {0};
4700 struct nir_function *func;
4701 unsigned i;
4702 ctx.options = options;
4703 ctx.shader_info = shader_info;
4704 ctx.context = LLVMContextCreate();
4705 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4706
4707 ac_llvm_context_init(&ctx.ac, ctx.context);
4708 ctx.ac.module = ctx.module;
4709
4710 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4711
4712 memset(shader_info, 0, sizeof(*shader_info));
4713
4714 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4715 setup_types(&ctx);
4716
4717 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4718 ctx.ac.builder = ctx.builder;
4719 ctx.stage = nir->stage;
4720
4721 for (i = 0; i < AC_UD_MAX_SETS; i++)
4722 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4723 for (i = 0; i < AC_UD_MAX_UD; i++)
4724 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4725
4726 create_function(&ctx);
4727
4728 if (nir->stage == MESA_SHADER_COMPUTE) {
4729 int num_shared = 0;
4730 nir_foreach_variable(variable, &nir->shared)
4731 num_shared++;
4732 if (num_shared) {
4733 int idx = 0;
4734 uint32_t shared_size = 0;
4735 LLVMValueRef var;
4736 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4737 nir_foreach_variable(variable, &nir->shared) {
4738 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4739 idx++;
4740 }
4741
4742 shared_size *= 4;
4743 var = LLVMAddGlobalInAddressSpace(ctx.module,
4744 LLVMArrayType(ctx.i8, shared_size),
4745 "compute_lds",
4746 LOCAL_ADDR_SPACE);
4747 LLVMSetAlignment(var, 4);
4748 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4749 }
4750 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4751 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4752
4753 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4754 }
4755
4756 ac_setup_rings(&ctx);
4757
4758 nir_foreach_variable(variable, &nir->inputs)
4759 handle_shader_input_decl(&ctx, variable);
4760
4761 if (nir->stage == MESA_SHADER_FRAGMENT)
4762 handle_fs_inputs_pre(&ctx, nir);
4763
4764 nir_foreach_variable(variable, &nir->outputs)
4765 handle_shader_output_decl(&ctx, variable);
4766
4767 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4768 _mesa_key_pointer_equal);
4769 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4770 _mesa_key_pointer_equal);
4771
4772 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4773
4774 setup_locals(&ctx, func);
4775
4776 visit_cf_list(&ctx, &func->impl->body);
4777 phi_post_pass(&ctx);
4778
4779 handle_shader_outputs_post(&ctx);
4780 LLVMBuildRetVoid(ctx.builder);
4781
4782 ac_llvm_finalize_module(&ctx);
4783 free(ctx.locals);
4784 ralloc_free(ctx.defs);
4785 ralloc_free(ctx.phis);
4786
4787 if (nir->stage == MESA_SHADER_GEOMETRY) {
4788 shader_info->gs.gsvs_vertex_size = util_bitcount64(ctx.output_mask) * 16;
4789 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
4790 nir->info->gs.vertices_out;
4791 }
4792 return ctx.module;
4793 }
4794
4795 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4796 {
4797 unsigned *retval = (unsigned *)context;
4798 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4799 char *description = LLVMGetDiagInfoDescription(di);
4800
4801 if (severity == LLVMDSError) {
4802 *retval = 1;
4803 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4804 description);
4805 }
4806
4807 LLVMDisposeMessage(description);
4808 }
4809
4810 static unsigned ac_llvm_compile(LLVMModuleRef M,
4811 struct ac_shader_binary *binary,
4812 LLVMTargetMachineRef tm)
4813 {
4814 unsigned retval = 0;
4815 char *err;
4816 LLVMContextRef llvm_ctx;
4817 LLVMMemoryBufferRef out_buffer;
4818 unsigned buffer_size;
4819 const char *buffer_data;
4820 LLVMBool mem_err;
4821
4822 /* Setup Diagnostic Handler*/
4823 llvm_ctx = LLVMGetModuleContext(M);
4824
4825 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4826 &retval);
4827
4828 /* Compile IR*/
4829 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
4830 &err, &out_buffer);
4831
4832 /* Process Errors/Warnings */
4833 if (mem_err) {
4834 fprintf(stderr, "%s: %s", __FUNCTION__, err);
4835 free(err);
4836 retval = 1;
4837 goto out;
4838 }
4839
4840 /* Extract Shader Code*/
4841 buffer_size = LLVMGetBufferSize(out_buffer);
4842 buffer_data = LLVMGetBufferStart(out_buffer);
4843
4844 ac_elf_read(buffer_data, buffer_size, binary);
4845
4846 /* Clean up */
4847 LLVMDisposeMemoryBuffer(out_buffer);
4848
4849 out:
4850 return retval;
4851 }
4852
4853 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
4854 LLVMModuleRef llvm_module,
4855 struct ac_shader_binary *binary,
4856 struct ac_shader_config *config,
4857 struct ac_shader_variant_info *shader_info,
4858 gl_shader_stage stage,
4859 bool dump_shader, bool supports_spill)
4860 {
4861 if (dump_shader)
4862 ac_dump_module(llvm_module);
4863
4864 memset(binary, 0, sizeof(*binary));
4865 int v = ac_llvm_compile(llvm_module, binary, tm);
4866 if (v) {
4867 fprintf(stderr, "compile failed\n");
4868 }
4869
4870 if (dump_shader)
4871 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
4872
4873 ac_shader_binary_read_config(binary, config, 0, supports_spill);
4874
4875 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4876 LLVMDisposeModule(llvm_module);
4877 LLVMContextDispose(ctx);
4878
4879 if (stage == MESA_SHADER_FRAGMENT) {
4880 shader_info->num_input_vgprs = 0;
4881 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
4882 shader_info->num_input_vgprs += 2;
4883 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
4884 shader_info->num_input_vgprs += 2;
4885 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
4886 shader_info->num_input_vgprs += 2;
4887 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
4888 shader_info->num_input_vgprs += 3;
4889 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
4890 shader_info->num_input_vgprs += 2;
4891 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
4892 shader_info->num_input_vgprs += 2;
4893 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
4894 shader_info->num_input_vgprs += 2;
4895 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
4896 shader_info->num_input_vgprs += 1;
4897 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
4898 shader_info->num_input_vgprs += 1;
4899 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
4900 shader_info->num_input_vgprs += 1;
4901 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
4902 shader_info->num_input_vgprs += 1;
4903 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
4904 shader_info->num_input_vgprs += 1;
4905 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
4906 shader_info->num_input_vgprs += 1;
4907 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
4908 shader_info->num_input_vgprs += 1;
4909 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
4910 shader_info->num_input_vgprs += 1;
4911 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
4912 shader_info->num_input_vgprs += 1;
4913 }
4914 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
4915
4916 /* +3 for scratch wave offset and VCC */
4917 config->num_sgprs = MAX2(config->num_sgprs,
4918 shader_info->num_input_sgprs + 3);
4919 }
4920
4921 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
4922 struct ac_shader_binary *binary,
4923 struct ac_shader_config *config,
4924 struct ac_shader_variant_info *shader_info,
4925 struct nir_shader *nir,
4926 const struct ac_nir_compiler_options *options,
4927 bool dump_shader)
4928 {
4929
4930 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
4931 options);
4932
4933 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
4934 switch (nir->stage) {
4935 case MESA_SHADER_COMPUTE:
4936 for (int i = 0; i < 3; ++i)
4937 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
4938 break;
4939 case MESA_SHADER_FRAGMENT:
4940 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
4941 break;
4942 case MESA_SHADER_GEOMETRY:
4943 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
4944 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
4945 shader_info->gs.output_prim = nir->info->gs.output_primitive;
4946 shader_info->gs.invocations = nir->info->gs.invocations;
4947 break;
4948 case MESA_SHADER_VERTEX:
4949 shader_info->vs.as_es = options->key.vs.as_es;
4950 break;
4951 default:
4952 break;
4953 }
4954 }
4955
4956 static void
4957 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
4958 {
4959 LLVMValueRef args[9];
4960 args[0] = ctx->gsvs_ring;
4961 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
4962 args[3] = ctx->i32zero;
4963 args[4] = ctx->i32one; /* OFFEN */
4964 args[5] = ctx->i32zero; /* IDXEN */
4965 args[6] = ctx->i32one; /* GLC */
4966 args[7] = ctx->i32one; /* SLC */
4967 args[8] = ctx->i32zero; /* TFE */
4968
4969 int idx = 0;
4970 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4971 if (!(ctx->output_mask & (1ull << i)))
4972 continue;
4973
4974 for (unsigned j = 0; j < 4; j++) {
4975 LLVMValueRef value;
4976 args[2] = LLVMConstInt(ctx->i32,
4977 (idx * 4 + j) *
4978 ctx->gs_max_out_vertices * 16 * 4, false);
4979
4980 value = ac_emit_llvm_intrinsic(&ctx->ac,
4981 "llvm.SI.buffer.load.dword.i32.i32",
4982 ctx->i32, args, 9,
4983 AC_FUNC_ATTR_READONLY);
4984
4985 LLVMBuildStore(ctx->builder,
4986 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
4987 }
4988 idx++;
4989 }
4990 handle_vs_outputs_post(ctx);
4991 }
4992
4993 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
4994 struct nir_shader *geom_shader,
4995 struct ac_shader_binary *binary,
4996 struct ac_shader_config *config,
4997 struct ac_shader_variant_info *shader_info,
4998 const struct ac_nir_compiler_options *options,
4999 bool dump_shader)
5000 {
5001 struct nir_to_llvm_context ctx = {0};
5002 ctx.context = LLVMContextCreate();
5003 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5004 ctx.options = options;
5005 ctx.shader_info = shader_info;
5006
5007 ac_llvm_context_init(&ctx.ac, ctx.context);
5008 ctx.ac.module = ctx.module;
5009
5010 ctx.is_gs_copy_shader = true;
5011 LLVMSetTarget(ctx.module, "amdgcn--");
5012 setup_types(&ctx);
5013
5014 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5015 ctx.ac.builder = ctx.builder;
5016 ctx.stage = MESA_SHADER_VERTEX;
5017
5018 create_function(&ctx);
5019
5020 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5021 ac_setup_rings(&ctx);
5022
5023 nir_foreach_variable(variable, &geom_shader->outputs)
5024 handle_shader_output_decl(&ctx, variable);
5025
5026 ac_gs_copy_shader_emit(&ctx);
5027
5028 LLVMBuildRetVoid(ctx.builder);
5029
5030 ac_llvm_finalize_module(&ctx);
5031
5032 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5033 MESA_SHADER_VERTEX,
5034 dump_shader, options->supports_spill);
5035 }