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ac/nir: generate correct instruction for atomic min/max on unsigned images
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 RADEON_LLVM_AMDGPU_HS = 93,
43 };
44
45 #define CONST_ADDR_SPACE 2
46 #define LOCAL_ADDR_SPACE 3
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
50
51 struct nir_to_llvm_context;
52
53 struct ac_nir_context {
54 struct ac_llvm_context ac;
55 struct ac_shader_abi *abi;
56
57 gl_shader_stage stage;
58
59 struct hash_table *defs;
60 struct hash_table *phis;
61 struct hash_table *vars;
62
63 LLVMValueRef main_function;
64 LLVMBasicBlockRef continue_block;
65 LLVMBasicBlockRef break_block;
66
67 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
68
69 int num_locals;
70 LLVMValueRef *locals;
71
72 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
73 };
74
75 struct nir_to_llvm_context {
76 struct ac_llvm_context ac;
77 const struct ac_nir_compiler_options *options;
78 struct ac_shader_variant_info *shader_info;
79 struct ac_shader_abi abi;
80 struct ac_nir_context *nir;
81
82 unsigned max_workgroup_size;
83 LLVMContextRef context;
84 LLVMModuleRef module;
85 LLVMBuilderRef builder;
86 LLVMValueRef main_function;
87
88 struct hash_table *defs;
89 struct hash_table *phis;
90
91 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
92 LLVMValueRef ring_offsets;
93 LLVMValueRef push_constants;
94 LLVMValueRef view_index;
95 LLVMValueRef num_work_groups;
96 LLVMValueRef workgroup_ids;
97 LLVMValueRef local_invocation_ids;
98 LLVMValueRef tg_size;
99
100 LLVMValueRef vertex_buffers;
101 LLVMValueRef rel_auto_id;
102 LLVMValueRef vs_prim_id;
103 LLVMValueRef ls_out_layout;
104 LLVMValueRef es2gs_offset;
105
106 LLVMValueRef tcs_offchip_layout;
107 LLVMValueRef tcs_out_offsets;
108 LLVMValueRef tcs_out_layout;
109 LLVMValueRef tcs_in_layout;
110 LLVMValueRef oc_lds;
111 LLVMValueRef merged_wave_info;
112 LLVMValueRef tess_factor_offset;
113 LLVMValueRef tcs_patch_id;
114 LLVMValueRef tcs_rel_ids;
115 LLVMValueRef tes_rel_patch_id;
116 LLVMValueRef tes_patch_id;
117 LLVMValueRef tes_u;
118 LLVMValueRef tes_v;
119
120 LLVMValueRef gsvs_ring_stride;
121 LLVMValueRef gsvs_num_entries;
122 LLVMValueRef gs2vs_offset;
123 LLVMValueRef gs_wave_id;
124 LLVMValueRef gs_vtx_offset[6];
125 LLVMValueRef gs_prim_id, gs_invocation_id;
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 LLVMTypeRef i1;
138 LLVMTypeRef i8;
139 LLVMTypeRef i16;
140 LLVMTypeRef i32;
141 LLVMTypeRef i64;
142 LLVMTypeRef v2i32;
143 LLVMTypeRef v3i32;
144 LLVMTypeRef v4i32;
145 LLVMTypeRef v8i32;
146 LLVMTypeRef f64;
147 LLVMTypeRef f32;
148 LLVMTypeRef f16;
149 LLVMTypeRef v2f32;
150 LLVMTypeRef v4f32;
151 LLVMTypeRef voidt;
152
153 LLVMValueRef i1true;
154 LLVMValueRef i1false;
155 LLVMValueRef i32zero;
156 LLVMValueRef i32one;
157 LLVMValueRef f32zero;
158 LLVMValueRef f32one;
159 LLVMValueRef v4f32empty;
160
161 unsigned uniform_md_kind;
162 LLVMValueRef empty_md;
163 gl_shader_stage stage;
164
165 LLVMValueRef lds;
166 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
167
168 uint64_t input_mask;
169 uint64_t output_mask;
170 uint8_t num_output_clips;
171 uint8_t num_output_culls;
172
173 bool is_gs_copy_shader;
174 LLVMValueRef gs_next_vertex;
175 unsigned gs_max_out_vertices;
176
177 unsigned tes_primitive_mode;
178 uint64_t tess_outputs_written;
179 uint64_t tess_patch_outputs_written;
180 };
181
182 static inline struct nir_to_llvm_context *
183 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
184 {
185 struct nir_to_llvm_context *ctx = NULL;
186 return container_of(abi, ctx, abi);
187 }
188
189 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
190 const nir_deref_var *deref,
191 enum ac_descriptor_type desc_type,
192 bool image, bool write);
193
194 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
195 {
196 return (index * 4) + chan;
197 }
198
199 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
200 {
201 /* handle patch indices separate */
202 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
203 return 0;
204 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
205 return 1;
206 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
207 return 2 + (slot - VARYING_SLOT_PATCH0);
208
209 if (slot == VARYING_SLOT_POS)
210 return 0;
211 if (slot == VARYING_SLOT_PSIZ)
212 return 1;
213 if (slot == VARYING_SLOT_CLIP_DIST0)
214 return 2;
215 /* 3 is reserved for clip dist as well */
216 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
217 return 4 + (slot - VARYING_SLOT_VAR0);
218 unreachable("illegal slot in get unique index\n");
219 }
220
221 static void set_llvm_calling_convention(LLVMValueRef func,
222 gl_shader_stage stage)
223 {
224 enum radeon_llvm_calling_convention calling_conv;
225
226 switch (stage) {
227 case MESA_SHADER_VERTEX:
228 case MESA_SHADER_TESS_EVAL:
229 calling_conv = RADEON_LLVM_AMDGPU_VS;
230 break;
231 case MESA_SHADER_GEOMETRY:
232 calling_conv = RADEON_LLVM_AMDGPU_GS;
233 break;
234 case MESA_SHADER_TESS_CTRL:
235 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
236 break;
237 case MESA_SHADER_FRAGMENT:
238 calling_conv = RADEON_LLVM_AMDGPU_PS;
239 break;
240 case MESA_SHADER_COMPUTE:
241 calling_conv = RADEON_LLVM_AMDGPU_CS;
242 break;
243 default:
244 unreachable("Unhandle shader type");
245 }
246
247 LLVMSetFunctionCallConv(func, calling_conv);
248 }
249
250 #define MAX_ARGS 23
251 struct arg_info {
252 LLVMTypeRef types[MAX_ARGS];
253 LLVMValueRef *assign[MAX_ARGS];
254 unsigned array_params_mask;
255 uint8_t count;
256 uint8_t user_sgpr_count;
257 uint8_t sgpr_count;
258 uint8_t num_user_sgprs_used;
259 uint8_t num_sgprs_used;
260 uint8_t num_vgprs_used;
261 };
262
263 static inline void
264 add_argument(struct arg_info *info,
265 LLVMTypeRef type, LLVMValueRef *param_ptr)
266 {
267 assert(info->count < MAX_ARGS);
268 info->assign[info->count] = param_ptr;
269 info->types[info->count] = type;
270 info->count++;
271 }
272
273 static inline void
274 add_sgpr_argument(struct arg_info *info,
275 LLVMTypeRef type, LLVMValueRef *param_ptr)
276 {
277 add_argument(info, type, param_ptr);
278 info->num_sgprs_used += ac_get_type_size(type) / 4;
279 info->sgpr_count++;
280 }
281
282 static inline void
283 add_user_sgpr_argument(struct arg_info *info,
284 LLVMTypeRef type,
285 LLVMValueRef *param_ptr)
286 {
287 add_sgpr_argument(info, type, param_ptr);
288 info->num_user_sgprs_used += ac_get_type_size(type) / 4;
289 info->user_sgpr_count++;
290 }
291
292 static inline void
293 add_vgpr_argument(struct arg_info *info,
294 LLVMTypeRef type,
295 LLVMValueRef *param_ptr)
296 {
297 add_argument(info, type, param_ptr);
298 info->num_vgprs_used += ac_get_type_size(type) / 4;
299 }
300
301 static inline void
302 add_user_sgpr_array_argument(struct arg_info *info,
303 LLVMTypeRef type,
304 LLVMValueRef *param_ptr)
305 {
306 info->array_params_mask |= (1 << info->count);
307 add_user_sgpr_argument(info, type, param_ptr);
308 }
309
310 static void assign_arguments(LLVMValueRef main_function,
311 struct arg_info *info)
312 {
313 unsigned i;
314 for (i = 0; i < info->count; i++) {
315 if (info->assign[i])
316 *info->assign[i] = LLVMGetParam(main_function, i);
317 }
318 }
319
320 static LLVMValueRef
321 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
322 LLVMBuilderRef builder, LLVMTypeRef *return_types,
323 unsigned num_return_elems,
324 struct arg_info *args,
325 unsigned max_workgroup_size,
326 bool unsafe_math)
327 {
328 LLVMTypeRef main_function_type, ret_type;
329 LLVMBasicBlockRef main_function_body;
330
331 if (num_return_elems)
332 ret_type = LLVMStructTypeInContext(ctx, return_types,
333 num_return_elems, true);
334 else
335 ret_type = LLVMVoidTypeInContext(ctx);
336
337 /* Setup the function */
338 main_function_type =
339 LLVMFunctionType(ret_type, args->types, args->count, 0);
340 LLVMValueRef main_function =
341 LLVMAddFunction(module, "main", main_function_type);
342 main_function_body =
343 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
344 LLVMPositionBuilderAtEnd(builder, main_function_body);
345
346 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
347 for (unsigned i = 0; i < args->sgpr_count; ++i) {
348 if (args->array_params_mask & (1 << i)) {
349 LLVMValueRef P = LLVMGetParam(main_function, i);
350 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
351 ac_add_attr_dereferenceable(P, UINT64_MAX);
352 }
353 else {
354 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
355 }
356 }
357
358 if (max_workgroup_size) {
359 ac_llvm_add_target_dep_function_attr(main_function,
360 "amdgpu-max-work-group-size",
361 max_workgroup_size);
362 }
363 if (unsafe_math) {
364 /* These were copied from some LLVM test. */
365 LLVMAddTargetDependentFunctionAttr(main_function,
366 "less-precise-fpmad",
367 "true");
368 LLVMAddTargetDependentFunctionAttr(main_function,
369 "no-infs-fp-math",
370 "true");
371 LLVMAddTargetDependentFunctionAttr(main_function,
372 "no-nans-fp-math",
373 "true");
374 LLVMAddTargetDependentFunctionAttr(main_function,
375 "unsafe-fp-math",
376 "true");
377 }
378 return main_function;
379 }
380
381 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
382 {
383 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
384 CONST_ADDR_SPACE);
385 }
386
387 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
388 {
389 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
390 type = LLVMGetElementType(type);
391
392 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
393 return LLVMGetIntTypeWidth(type);
394
395 if (type == ctx->f16)
396 return 16;
397 if (type == ctx->f32)
398 return 32;
399 if (type == ctx->f64)
400 return 64;
401
402 unreachable("Unhandled type kind in get_elem_bits");
403 }
404
405 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
406 LLVMValueRef param, unsigned rshift,
407 unsigned bitwidth)
408 {
409 LLVMValueRef value = param;
410 if (rshift)
411 value = LLVMBuildLShr(ctx->builder, value,
412 LLVMConstInt(ctx->i32, rshift, false), "");
413
414 if (rshift + bitwidth < 32) {
415 unsigned mask = (1 << bitwidth) - 1;
416 value = LLVMBuildAnd(ctx->builder, value,
417 LLVMConstInt(ctx->i32, mask, false), "");
418 }
419 return value;
420 }
421
422 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
423 {
424 switch (ctx->stage) {
425 case MESA_SHADER_TESS_CTRL:
426 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
427 case MESA_SHADER_TESS_EVAL:
428 return ctx->tes_rel_patch_id;
429 break;
430 default:
431 unreachable("Illegal stage");
432 }
433 }
434
435 /* Tessellation shaders pass outputs to the next shader using LDS.
436 *
437 * LS outputs = TCS inputs
438 * TCS outputs = TES inputs
439 *
440 * The LDS layout is:
441 * - TCS inputs for patch 0
442 * - TCS inputs for patch 1
443 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
444 * - ...
445 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
446 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
447 * - TCS outputs for patch 1
448 * - Per-patch TCS outputs for patch 1
449 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
450 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
451 * - ...
452 *
453 * All three shaders VS(LS), TCS, TES share the same LDS space.
454 */
455 static LLVMValueRef
456 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
457 {
458 if (ctx->stage == MESA_SHADER_VERTEX)
459 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
460 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
461 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
462 else {
463 assert(0);
464 return NULL;
465 }
466 }
467
468 static LLVMValueRef
469 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
470 {
471 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
472 }
473
474 static LLVMValueRef
475 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
476 {
477 return LLVMBuildMul(ctx->builder,
478 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
479 LLVMConstInt(ctx->i32, 4, false), "");
480 }
481
482 static LLVMValueRef
483 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
484 {
485 return LLVMBuildMul(ctx->builder,
486 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
487 LLVMConstInt(ctx->i32, 4, false), "");
488 }
489
490 static LLVMValueRef
491 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
494 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
495
496 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
497 }
498
499 static LLVMValueRef
500 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
501 {
502 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
503 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
504 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
505
506 return LLVMBuildAdd(ctx->builder, patch0_offset,
507 LLVMBuildMul(ctx->builder, patch_stride,
508 rel_patch_id, ""),
509 "");
510 }
511
512 static LLVMValueRef
513 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
514 {
515 LLVMValueRef patch0_patch_data_offset =
516 get_tcs_out_patch0_patch_data_offset(ctx);
517 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
518 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
519
520 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
521 LLVMBuildMul(ctx->builder, patch_stride,
522 rel_patch_id, ""),
523 "");
524 }
525
526 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
527 {
528 ud_info->sgpr_idx = *sgpr_idx;
529 ud_info->num_sgprs = num_sgprs;
530 ud_info->indirect = false;
531 ud_info->indirect_offset = 0;
532 *sgpr_idx += num_sgprs;
533 }
534
535 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
536 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
537 {
538 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
539 }
540
541
542 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
543 uint32_t indirect_offset)
544 {
545 ud_info->sgpr_idx = sgpr_idx;
546 ud_info->num_sgprs = num_sgprs;
547 ud_info->indirect = true;
548 ud_info->indirect_offset = indirect_offset;
549 }
550
551 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
552 {
553 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
554 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
555 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
556 "tess_lds");
557 }
558
559 struct user_sgpr_info {
560 bool need_ring_offsets;
561 uint8_t sgpr_count;
562 bool indirect_all_descriptor_sets;
563 };
564
565 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
566 struct user_sgpr_info *user_sgpr_info)
567 {
568 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
569
570 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
571 if (ctx->stage == MESA_SHADER_GEOMETRY ||
572 ctx->stage == MESA_SHADER_VERTEX ||
573 ctx->stage == MESA_SHADER_TESS_CTRL ||
574 ctx->stage == MESA_SHADER_TESS_EVAL ||
575 ctx->is_gs_copy_shader)
576 user_sgpr_info->need_ring_offsets = true;
577
578 if (ctx->stage == MESA_SHADER_FRAGMENT &&
579 ctx->shader_info->info.ps.needs_sample_positions)
580 user_sgpr_info->need_ring_offsets = true;
581
582 /* 2 user sgprs will nearly always be allocated for scratch/rings */
583 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
584 user_sgpr_info->sgpr_count += 2;
585 }
586
587 switch (ctx->stage) {
588 case MESA_SHADER_COMPUTE:
589 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
590 break;
591 case MESA_SHADER_FRAGMENT:
592 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
593 break;
594 case MESA_SHADER_VERTEX:
595 if (!ctx->is_gs_copy_shader) {
596 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
597 if (ctx->shader_info->info.vs.needs_draw_id) {
598 user_sgpr_info->sgpr_count += 3;
599 } else {
600 user_sgpr_info->sgpr_count += 2;
601 }
602 }
603 if (ctx->options->key.vs.as_ls)
604 user_sgpr_info->sgpr_count++;
605 break;
606 case MESA_SHADER_TESS_CTRL:
607 user_sgpr_info->sgpr_count += 4;
608 break;
609 case MESA_SHADER_TESS_EVAL:
610 user_sgpr_info->sgpr_count += 1;
611 break;
612 case MESA_SHADER_GEOMETRY:
613 user_sgpr_info->sgpr_count += 2;
614 break;
615 default:
616 break;
617 }
618
619 if (ctx->shader_info->info.needs_push_constants)
620 user_sgpr_info->sgpr_count += 2;
621
622 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
623 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
624 user_sgpr_info->sgpr_count += 2;
625 user_sgpr_info->indirect_all_descriptor_sets = true;
626 } else {
627 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
628 }
629 }
630
631 static void
632 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
633 gl_shader_stage stage,
634 bool has_previous_stage,
635 gl_shader_stage previous_stage,
636 const struct user_sgpr_info *user_sgpr_info,
637 struct arg_info *args,
638 LLVMValueRef *desc_sets)
639 {
640 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
641 unsigned stage_mask = 1 << stage;
642 if (has_previous_stage)
643 stage_mask |= 1 << previous_stage;
644
645 /* 1 for each descriptor set */
646 if (!user_sgpr_info->indirect_all_descriptor_sets) {
647 for (unsigned i = 0; i < num_sets; ++i) {
648 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
649 add_user_sgpr_array_argument(args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
650 }
651 }
652 } else
653 add_user_sgpr_array_argument(args, const_array(const_array(ctx->i8, 1024 * 1024), 32), desc_sets);
654
655 if (ctx->shader_info->info.needs_push_constants) {
656 /* 1 for push constants and dynamic descriptors */
657 add_user_sgpr_array_argument(args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
658 }
659 }
660
661 static void
662 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
663 gl_shader_stage stage,
664 bool has_previous_stage,
665 gl_shader_stage previous_stage,
666 const struct user_sgpr_info *user_sgpr_info,
667 LLVMValueRef desc_sets,
668 uint8_t *user_sgpr_idx)
669 {
670 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
671 unsigned stage_mask = 1 << stage;
672 if (has_previous_stage)
673 stage_mask |= 1 << previous_stage;
674
675 if (!user_sgpr_info->indirect_all_descriptor_sets) {
676 for (unsigned i = 0; i < num_sets; ++i) {
677 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
678 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
679 } else
680 ctx->descriptor_sets[i] = NULL;
681 }
682 } else {
683 uint32_t desc_sgpr_idx = *user_sgpr_idx;
684 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
685
686 for (unsigned i = 0; i < num_sets; ++i) {
687 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
688 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
689 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
690
691 } else
692 ctx->descriptor_sets[i] = NULL;
693 }
694 ctx->shader_info->need_indirect_descriptor_sets = true;
695 }
696
697 if (ctx->shader_info->info.needs_push_constants) {
698 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
699 }
700 }
701
702 static void
703 radv_define_vs_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
704 gl_shader_stage stage,
705 bool has_previous_stage,
706 gl_shader_stage previous_stage,
707 struct arg_info *args)
708 {
709 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
710 if (ctx->shader_info->info.vs.has_vertex_buffers)
711 add_user_sgpr_argument(args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
712 add_user_sgpr_argument(args, ctx->i32, &ctx->abi.base_vertex); // base vertex
713 add_user_sgpr_argument(args, ctx->i32, &ctx->abi.start_instance);// start instance
714 if (ctx->shader_info->info.vs.needs_draw_id)
715 add_user_sgpr_argument(args, ctx->i32, &ctx->abi.draw_id); // draw id
716 }
717 }
718
719 static void
720 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
721 gl_shader_stage stage,
722 bool has_previous_stage,
723 gl_shader_stage previous_stage,
724 uint8_t *user_sgpr_idx)
725 {
726 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
727 if (ctx->shader_info->info.vs.has_vertex_buffers) {
728 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
729 }
730 unsigned vs_num = 2;
731 if (ctx->shader_info->info.vs.needs_draw_id)
732 vs_num++;
733
734 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
735 }
736 }
737
738
739 static void create_function(struct nir_to_llvm_context *ctx,
740 gl_shader_stage stage,
741 bool has_previous_stage,
742 gl_shader_stage previous_stage)
743 {
744 uint8_t user_sgpr_idx;
745 struct user_sgpr_info user_sgpr_info;
746 struct arg_info args = {};
747 LLVMValueRef desc_sets;
748
749 allocate_user_sgprs(ctx, &user_sgpr_info);
750
751 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
752 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
753 }
754
755 switch (stage) {
756 case MESA_SHADER_COMPUTE:
757 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
758 if (ctx->shader_info->info.cs.grid_components_used)
759 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
760 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
761 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
762 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
763 break;
764 case MESA_SHADER_VERTEX:
765 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
766 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
767 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
768 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
769 if (ctx->options->key.vs.as_es)
770 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
771 else if (ctx->options->key.vs.as_ls)
772 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
773 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
774 if (!ctx->is_gs_copy_shader) {
775 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
776 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
777 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
778 }
779 break;
780 case MESA_SHADER_TESS_CTRL:
781 if (has_previous_stage) {
782 // First 6 system regs
783 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
784 add_sgpr_argument(&args, ctx->i32, &ctx->merged_wave_info); // merged wave info
785 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
786
787 add_sgpr_argument(&args, ctx->i32, NULL); // scratch offset
788 add_sgpr_argument(&args, ctx->i32, NULL); // unknown
789 add_sgpr_argument(&args, ctx->i32, NULL); // unknown
790
791 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
792 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
793 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
794
795 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
796 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
797 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
798 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
799 if (ctx->shader_info->info.needs_multiview_view_index)
800 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
801
802 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
803 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
804 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
805 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
806 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
807 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
808 } else {
809 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
810 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
811 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
812 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
813 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
814 if (ctx->shader_info->info.needs_multiview_view_index)
815 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
816 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
817 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
818 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
819 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
820 }
821 break;
822 case MESA_SHADER_TESS_EVAL:
823 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
824 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
825 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
826 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
827 if (ctx->options->key.tes.as_es) {
828 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
829 add_sgpr_argument(&args, ctx->i32, NULL); //
830 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
831 } else {
832 add_sgpr_argument(&args, ctx->i32, NULL); //
833 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
834 }
835 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
836 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
837 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
838 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
839 break;
840 case MESA_SHADER_GEOMETRY:
841 if (has_previous_stage) {
842 // First 6 system regs
843 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // tess factor offset
844 add_sgpr_argument(&args, ctx->i32, &ctx->merged_wave_info); // merged wave info
845 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
846
847 add_sgpr_argument(&args, ctx->i32, NULL); // scratch offset
848 add_sgpr_argument(&args, ctx->i32, NULL); // unknown
849 add_sgpr_argument(&args, ctx->i32, NULL); // unknown
850
851 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
852 if (previous_stage == MESA_SHADER_TESS_EVAL)
853 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
854 else
855 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
856 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
857 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
858 if (ctx->shader_info->info.needs_multiview_view_index)
859 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
860
861 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx01
862 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]); // vtx23
863 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
864 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
865 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
866
867 if (previous_stage == MESA_SHADER_VERTEX) {
868 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
869 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
870 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
871 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
872 } else {
873 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
874 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
875 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
876 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
877 }
878 } else {
879 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
880 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
881 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
882 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
883 if (ctx->shader_info->info.needs_multiview_view_index)
884 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
885 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
886 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
887 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
888 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
889 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
890 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
891 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
892 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
893 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
894 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
895 }
896 break;
897 case MESA_SHADER_FRAGMENT:
898 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
899 if (ctx->shader_info->info.ps.needs_sample_positions)
900 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
901 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
902 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
903 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
904 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
905 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
906 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
907 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
908 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
909 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
910 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[0]); /* pos x float */
911 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[1]); /* pos y float */
912 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[2]); /* pos z float */
913 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[3]); /* pos w float */
914 add_vgpr_argument(&args, ctx->i32, &ctx->abi.front_face); /* front face */
915 add_vgpr_argument(&args, ctx->i32, &ctx->abi.ancillary); /* ancillary */
916 add_vgpr_argument(&args, ctx->i32, &ctx->abi.sample_coverage); /* sample coverage */
917 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
918 break;
919 default:
920 unreachable("Shader stage not implemented");
921 }
922
923 ctx->main_function = create_llvm_function(
924 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
925 ctx->max_workgroup_size,
926 ctx->options->unsafe_math);
927 set_llvm_calling_convention(ctx->main_function, stage);
928
929
930 ctx->shader_info->num_input_vgprs = 0;
931 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
932
933 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
934
935 if (ctx->stage != MESA_SHADER_FRAGMENT)
936 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
937
938 assign_arguments(ctx->main_function, &args);
939
940 user_sgpr_idx = 0;
941
942 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
943 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
944 if (ctx->options->supports_spill) {
945 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
946 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
947 NULL, 0, AC_FUNC_ATTR_READNONE);
948 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
949 const_array(ctx->v4i32, 16), "");
950 }
951 }
952
953 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
954 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
955 if (has_previous_stage)
956 user_sgpr_idx = 0;
957
958 radv_define_common_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, desc_sets, &user_sgpr_idx);
959
960 switch (stage) {
961 case MESA_SHADER_COMPUTE:
962 if (ctx->shader_info->info.cs.grid_components_used) {
963 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
964 }
965 break;
966 case MESA_SHADER_VERTEX:
967 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
968 if (ctx->view_index)
969 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
970 if (ctx->options->key.vs.as_ls) {
971 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
972 }
973 if (ctx->options->key.vs.as_ls)
974 declare_tess_lds(ctx);
975 break;
976 case MESA_SHADER_TESS_CTRL:
977 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
978 if (has_previous_stage)
979 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
980 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
981 if (ctx->view_index)
982 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
983 declare_tess_lds(ctx);
984 break;
985 case MESA_SHADER_TESS_EVAL:
986 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
987 if (ctx->view_index)
988 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
989 break;
990 case MESA_SHADER_GEOMETRY:
991 if (has_previous_stage) {
992 if (previous_stage == MESA_SHADER_VERTEX)
993 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
994 else
995 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
996 }
997 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
998 if (ctx->view_index)
999 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1000 if (has_previous_stage)
1001 declare_tess_lds(ctx);
1002 break;
1003 case MESA_SHADER_FRAGMENT:
1004 if (ctx->shader_info->info.ps.needs_sample_positions) {
1005 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
1006 }
1007 break;
1008 default:
1009 unreachable("Shader stage not implemented");
1010 }
1011
1012 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1013 }
1014
1015 static void setup_types(struct nir_to_llvm_context *ctx)
1016 {
1017 LLVMValueRef args[4];
1018
1019 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
1020 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
1021 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
1022 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
1023 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
1024 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
1025 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
1026 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
1027 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
1028 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
1029 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
1030 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
1031 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
1032 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
1033 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
1034
1035 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
1036 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
1037 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
1038 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
1039 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
1040 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
1041
1042 args[0] = ctx->f32zero;
1043 args[1] = ctx->f32zero;
1044 args[2] = ctx->f32zero;
1045 args[3] = ctx->f32one;
1046 ctx->v4f32empty = LLVMConstVector(args, 4);
1047
1048 ctx->uniform_md_kind =
1049 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
1050 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
1051
1052 args[0] = LLVMConstReal(ctx->f32, 2.5);
1053 }
1054
1055 static int get_llvm_num_components(LLVMValueRef value)
1056 {
1057 LLVMTypeRef type = LLVMTypeOf(value);
1058 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1059 ? LLVMGetVectorSize(type)
1060 : 1;
1061 return num_components;
1062 }
1063
1064 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1065 LLVMValueRef value,
1066 int index)
1067 {
1068 int count = get_llvm_num_components(value);
1069
1070 if (count == 1)
1071 return value;
1072
1073 return LLVMBuildExtractElement(ac->builder, value,
1074 LLVMConstInt(ac->i32, index, false), "");
1075 }
1076
1077 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1078 LLVMValueRef value, unsigned count)
1079 {
1080 unsigned num_components = get_llvm_num_components(value);
1081 if (count == num_components)
1082 return value;
1083
1084 LLVMValueRef masks[] = {
1085 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1086 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1087
1088 if (count == 1)
1089 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1090 "");
1091
1092 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1093 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1094 }
1095
1096 static void
1097 build_store_values_extended(struct ac_llvm_context *ac,
1098 LLVMValueRef *values,
1099 unsigned value_count,
1100 unsigned value_stride,
1101 LLVMValueRef vec)
1102 {
1103 LLVMBuilderRef builder = ac->builder;
1104 unsigned i;
1105
1106 for (i = 0; i < value_count; i++) {
1107 LLVMValueRef ptr = values[i * value_stride];
1108 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1109 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1110 LLVMBuildStore(builder, value, ptr);
1111 }
1112 }
1113
1114 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1115 const nir_ssa_def *def)
1116 {
1117 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1118 if (def->num_components > 1) {
1119 type = LLVMVectorType(type, def->num_components);
1120 }
1121 return type;
1122 }
1123
1124 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1125 {
1126 assert(src.is_ssa);
1127 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1128 return (LLVMValueRef)entry->data;
1129 }
1130
1131
1132 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1133 const struct nir_block *b)
1134 {
1135 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1136 return (LLVMBasicBlockRef)entry->data;
1137 }
1138
1139 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1140 nir_alu_src src,
1141 unsigned num_components)
1142 {
1143 LLVMValueRef value = get_src(ctx, src.src);
1144 bool need_swizzle = false;
1145
1146 assert(value);
1147 LLVMTypeRef type = LLVMTypeOf(value);
1148 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1149 ? LLVMGetVectorSize(type)
1150 : 1;
1151
1152 for (unsigned i = 0; i < num_components; ++i) {
1153 assert(src.swizzle[i] < src_components);
1154 if (src.swizzle[i] != i)
1155 need_swizzle = true;
1156 }
1157
1158 if (need_swizzle || num_components != src_components) {
1159 LLVMValueRef masks[] = {
1160 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1161 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1162 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1163 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1164
1165 if (src_components > 1 && num_components == 1) {
1166 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1167 masks[0], "");
1168 } else if (src_components == 1 && num_components > 1) {
1169 LLVMValueRef values[] = {value, value, value, value};
1170 value = ac_build_gather_values(&ctx->ac, values, num_components);
1171 } else {
1172 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1173 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1174 swizzle, "");
1175 }
1176 }
1177 assert(!src.negate);
1178 assert(!src.abs);
1179 return value;
1180 }
1181
1182 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1183 LLVMIntPredicate pred, LLVMValueRef src0,
1184 LLVMValueRef src1)
1185 {
1186 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1187 return LLVMBuildSelect(ctx->builder, result,
1188 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1189 LLVMConstInt(ctx->i32, 0, false), "");
1190 }
1191
1192 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1193 LLVMRealPredicate pred, LLVMValueRef src0,
1194 LLVMValueRef src1)
1195 {
1196 LLVMValueRef result;
1197 src0 = ac_to_float(ctx, src0);
1198 src1 = ac_to_float(ctx, src1);
1199 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1200 return LLVMBuildSelect(ctx->builder, result,
1201 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1202 LLVMConstInt(ctx->i32, 0, false), "");
1203 }
1204
1205 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1206 const char *intrin,
1207 LLVMTypeRef result_type,
1208 LLVMValueRef src0)
1209 {
1210 char name[64];
1211 LLVMValueRef params[] = {
1212 ac_to_float(ctx, src0),
1213 };
1214
1215 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1216 get_elem_bits(ctx, result_type));
1217 assert(length < sizeof(name));
1218 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1219 }
1220
1221 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1222 const char *intrin,
1223 LLVMTypeRef result_type,
1224 LLVMValueRef src0, LLVMValueRef src1)
1225 {
1226 char name[64];
1227 LLVMValueRef params[] = {
1228 ac_to_float(ctx, src0),
1229 ac_to_float(ctx, src1),
1230 };
1231
1232 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1233 get_elem_bits(ctx, result_type));
1234 assert(length < sizeof(name));
1235 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1236 }
1237
1238 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1239 const char *intrin,
1240 LLVMTypeRef result_type,
1241 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1242 {
1243 char name[64];
1244 LLVMValueRef params[] = {
1245 ac_to_float(ctx, src0),
1246 ac_to_float(ctx, src1),
1247 ac_to_float(ctx, src2),
1248 };
1249
1250 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1251 get_elem_bits(ctx, result_type));
1252 assert(length < sizeof(name));
1253 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1254 }
1255
1256 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1257 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1258 {
1259 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1260 ctx->i32_0, "");
1261 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1262 }
1263
1264 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1265 LLVMValueRef src0)
1266 {
1267 LLVMValueRef params[2] = {
1268 src0,
1269
1270 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1271 * add special code to check for x=0. The reason is that
1272 * the LLVM behavior for x=0 is different from what we
1273 * need here.
1274 *
1275 * The hardware already implements the correct behavior.
1276 */
1277 LLVMConstInt(ctx->i1, 1, false),
1278 };
1279
1280 LLVMValueRef lsb = ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32,
1281 params, 2,
1282 AC_FUNC_ATTR_READNONE);
1283
1284 /* TODO: We need an intrinsic to skip this conditional. */
1285 /* Check for zero: */
1286 return LLVMBuildSelect(ctx->builder, LLVMBuildICmp(ctx->builder,
1287 LLVMIntEQ, src0,
1288 ctx->i32_0, ""),
1289 LLVMConstInt(ctx->i32, -1, 0), lsb, "");
1290 }
1291
1292 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1293 LLVMValueRef src0)
1294 {
1295 return ac_build_imsb(ctx, src0, ctx->i32);
1296 }
1297
1298 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1299 LLVMValueRef src0)
1300 {
1301 return ac_build_umsb(ctx, src0, ctx->i32);
1302 }
1303
1304 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1305 LLVMIntPredicate pred,
1306 LLVMValueRef src0, LLVMValueRef src1)
1307 {
1308 return LLVMBuildSelect(ctx->builder,
1309 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1310 src0,
1311 src1, "");
1312
1313 }
1314 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1315 LLVMValueRef src0)
1316 {
1317 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1318 LLVMBuildNeg(ctx->builder, src0, ""));
1319 }
1320
1321 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1322 LLVMValueRef src0)
1323 {
1324 LLVMValueRef cmp, val;
1325
1326 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1327 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1328 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1329 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1330 return val;
1331 }
1332
1333 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1334 LLVMValueRef src0)
1335 {
1336 LLVMValueRef cmp, val;
1337
1338 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1339 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1340 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1341 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1342 return val;
1343 }
1344
1345 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1346 LLVMValueRef src0)
1347 {
1348 const char *intr = "llvm.floor.f32";
1349 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1350 LLVMValueRef params[] = {
1351 fsrc0,
1352 };
1353 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1354 ctx->f32, params, 1,
1355 AC_FUNC_ATTR_READNONE);
1356 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1357 }
1358
1359 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1360 const char *intrin,
1361 LLVMValueRef src0, LLVMValueRef src1)
1362 {
1363 LLVMTypeRef ret_type;
1364 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1365 LLVMValueRef res;
1366 LLVMValueRef params[] = { src0, src1 };
1367 ret_type = LLVMStructTypeInContext(ctx->context, types,
1368 2, true);
1369
1370 res = ac_build_intrinsic(ctx, intrin, ret_type,
1371 params, 2, AC_FUNC_ATTR_READNONE);
1372
1373 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1374 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1375 return res;
1376 }
1377
1378 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1379 LLVMValueRef src0)
1380 {
1381 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1382 }
1383
1384 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1385 LLVMValueRef src0)
1386 {
1387 src0 = ac_to_float(ctx, src0);
1388 return LLVMBuildSExt(ctx->builder,
1389 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1390 ctx->i32, "");
1391 }
1392
1393 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1394 LLVMValueRef src0)
1395 {
1396 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1397 }
1398
1399 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1400 LLVMValueRef src0)
1401 {
1402 return LLVMBuildSExt(ctx->builder,
1403 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1404 ctx->i32, "");
1405 }
1406
1407 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1408 LLVMValueRef src0)
1409 {
1410 LLVMValueRef result;
1411 LLVMValueRef cond = NULL;
1412
1413 src0 = ac_to_float(&ctx->ac, src0);
1414 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1415
1416 if (ctx->options->chip_class >= VI) {
1417 LLVMValueRef args[2];
1418 /* Check if the result is a denormal - and flush to 0 if so. */
1419 args[0] = result;
1420 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1421 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1422 }
1423
1424 /* need to convert back up to f32 */
1425 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1426
1427 if (ctx->options->chip_class >= VI)
1428 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1429 else {
1430 /* for SI/CIK */
1431 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1432 * so compare the result and flush to 0 if it's smaller.
1433 */
1434 LLVMValueRef temp, cond2;
1435 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1436 ctx->f32, result);
1437 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1438 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1439 temp, "");
1440 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1441 temp, ctx->f32zero, "");
1442 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1443 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1444 }
1445 return result;
1446 }
1447
1448 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1449 LLVMValueRef src0, LLVMValueRef src1)
1450 {
1451 LLVMValueRef dst64, result;
1452 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1453 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1454
1455 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1456 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1457 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1458 return result;
1459 }
1460
1461 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1462 LLVMValueRef src0, LLVMValueRef src1)
1463 {
1464 LLVMValueRef dst64, result;
1465 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1466 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1467
1468 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1469 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1470 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1471 return result;
1472 }
1473
1474 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1475 bool is_signed,
1476 const LLVMValueRef srcs[3])
1477 {
1478 LLVMValueRef result;
1479 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1480
1481 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1482 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1483 return result;
1484 }
1485
1486 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1487 LLVMValueRef src0, LLVMValueRef src1,
1488 LLVMValueRef src2, LLVMValueRef src3)
1489 {
1490 LLVMValueRef bfi_args[3], result;
1491
1492 bfi_args[0] = LLVMBuildShl(ctx->builder,
1493 LLVMBuildSub(ctx->builder,
1494 LLVMBuildShl(ctx->builder,
1495 ctx->i32_1,
1496 src3, ""),
1497 ctx->i32_1, ""),
1498 src2, "");
1499 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1500 bfi_args[2] = src0;
1501
1502 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1503
1504 /* Calculate:
1505 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1506 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1507 */
1508 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1509 LLVMBuildAnd(ctx->builder, bfi_args[0],
1510 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1511
1512 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1513 return result;
1514 }
1515
1516 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1517 LLVMValueRef src0)
1518 {
1519 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1520 int i;
1521 LLVMValueRef comp[2];
1522
1523 src0 = ac_to_float(ctx, src0);
1524 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1525 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1526 for (i = 0; i < 2; i++) {
1527 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1528 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1529 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1530 }
1531
1532 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1533 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1534
1535 return comp[0];
1536 }
1537
1538 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1539 LLVMValueRef src0)
1540 {
1541 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1542 LLVMValueRef temps[2], result, val;
1543 int i;
1544
1545 for (i = 0; i < 2; i++) {
1546 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1547 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1548 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1549 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1550 }
1551
1552 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1553 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1554 ctx->i32_0, "");
1555 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1556 ctx->i32_1, "");
1557 return result;
1558 }
1559
1560 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1561 nir_op op,
1562 LLVMValueRef src0)
1563 {
1564 unsigned mask;
1565 int idx;
1566 LLVMValueRef result;
1567
1568 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1569 mask = AC_TID_MASK_LEFT;
1570 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1571 mask = AC_TID_MASK_TOP;
1572 else
1573 mask = AC_TID_MASK_TOP_LEFT;
1574
1575 /* for DDX we want to next X pixel, DDY next Y pixel. */
1576 if (op == nir_op_fddx_fine ||
1577 op == nir_op_fddx_coarse ||
1578 op == nir_op_fddx)
1579 idx = 1;
1580 else
1581 idx = 2;
1582
1583 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1584 return result;
1585 }
1586
1587 /*
1588 * this takes an I,J coordinate pair,
1589 * and works out the X and Y derivatives.
1590 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1591 */
1592 static LLVMValueRef emit_ddxy_interp(
1593 struct ac_nir_context *ctx,
1594 LLVMValueRef interp_ij)
1595 {
1596 LLVMValueRef result[4], a;
1597 unsigned i;
1598
1599 for (i = 0; i < 2; i++) {
1600 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1601 LLVMConstInt(ctx->ac.i32, i, false), "");
1602 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1603 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1604 }
1605 return ac_build_gather_values(&ctx->ac, result, 4);
1606 }
1607
1608 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1609 {
1610 LLVMValueRef src[4], result = NULL;
1611 unsigned num_components = instr->dest.dest.ssa.num_components;
1612 unsigned src_components;
1613 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1614
1615 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1616 switch (instr->op) {
1617 case nir_op_vec2:
1618 case nir_op_vec3:
1619 case nir_op_vec4:
1620 src_components = 1;
1621 break;
1622 case nir_op_pack_half_2x16:
1623 src_components = 2;
1624 break;
1625 case nir_op_unpack_half_2x16:
1626 src_components = 1;
1627 break;
1628 default:
1629 src_components = num_components;
1630 break;
1631 }
1632 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1633 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1634
1635 switch (instr->op) {
1636 case nir_op_fmov:
1637 case nir_op_imov:
1638 result = src[0];
1639 break;
1640 case nir_op_fneg:
1641 src[0] = ac_to_float(&ctx->ac, src[0]);
1642 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1643 break;
1644 case nir_op_ineg:
1645 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1646 break;
1647 case nir_op_inot:
1648 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1649 break;
1650 case nir_op_iadd:
1651 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1652 break;
1653 case nir_op_fadd:
1654 src[0] = ac_to_float(&ctx->ac, src[0]);
1655 src[1] = ac_to_float(&ctx->ac, src[1]);
1656 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1657 break;
1658 case nir_op_fsub:
1659 src[0] = ac_to_float(&ctx->ac, src[0]);
1660 src[1] = ac_to_float(&ctx->ac, src[1]);
1661 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1662 break;
1663 case nir_op_isub:
1664 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1665 break;
1666 case nir_op_imul:
1667 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1668 break;
1669 case nir_op_imod:
1670 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1671 break;
1672 case nir_op_umod:
1673 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1674 break;
1675 case nir_op_fmod:
1676 src[0] = ac_to_float(&ctx->ac, src[0]);
1677 src[1] = ac_to_float(&ctx->ac, src[1]);
1678 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1679 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1680 ac_to_float_type(&ctx->ac, def_type), result);
1681 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1682 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1683 break;
1684 case nir_op_frem:
1685 src[0] = ac_to_float(&ctx->ac, src[0]);
1686 src[1] = ac_to_float(&ctx->ac, src[1]);
1687 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1688 break;
1689 case nir_op_irem:
1690 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1691 break;
1692 case nir_op_idiv:
1693 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1694 break;
1695 case nir_op_udiv:
1696 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1697 break;
1698 case nir_op_fmul:
1699 src[0] = ac_to_float(&ctx->ac, src[0]);
1700 src[1] = ac_to_float(&ctx->ac, src[1]);
1701 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1702 break;
1703 case nir_op_fdiv:
1704 src[0] = ac_to_float(&ctx->ac, src[0]);
1705 src[1] = ac_to_float(&ctx->ac, src[1]);
1706 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1707 break;
1708 case nir_op_frcp:
1709 src[0] = ac_to_float(&ctx->ac, src[0]);
1710 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1711 break;
1712 case nir_op_iand:
1713 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1714 break;
1715 case nir_op_ior:
1716 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1717 break;
1718 case nir_op_ixor:
1719 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1720 break;
1721 case nir_op_ishl:
1722 result = LLVMBuildShl(ctx->ac.builder, src[0],
1723 LLVMBuildZExt(ctx->ac.builder, src[1],
1724 LLVMTypeOf(src[0]), ""),
1725 "");
1726 break;
1727 case nir_op_ishr:
1728 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1729 LLVMBuildZExt(ctx->ac.builder, src[1],
1730 LLVMTypeOf(src[0]), ""),
1731 "");
1732 break;
1733 case nir_op_ushr:
1734 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1735 LLVMBuildZExt(ctx->ac.builder, src[1],
1736 LLVMTypeOf(src[0]), ""),
1737 "");
1738 break;
1739 case nir_op_ilt:
1740 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1741 break;
1742 case nir_op_ine:
1743 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1744 break;
1745 case nir_op_ieq:
1746 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1747 break;
1748 case nir_op_ige:
1749 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1750 break;
1751 case nir_op_ult:
1752 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1753 break;
1754 case nir_op_uge:
1755 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1756 break;
1757 case nir_op_feq:
1758 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1759 break;
1760 case nir_op_fne:
1761 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1762 break;
1763 case nir_op_flt:
1764 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1765 break;
1766 case nir_op_fge:
1767 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1768 break;
1769 case nir_op_fabs:
1770 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1771 ac_to_float_type(&ctx->ac, def_type), src[0]);
1772 break;
1773 case nir_op_iabs:
1774 result = emit_iabs(&ctx->ac, src[0]);
1775 break;
1776 case nir_op_imax:
1777 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1778 break;
1779 case nir_op_imin:
1780 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1781 break;
1782 case nir_op_umax:
1783 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1784 break;
1785 case nir_op_umin:
1786 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1787 break;
1788 case nir_op_isign:
1789 result = emit_isign(&ctx->ac, src[0]);
1790 break;
1791 case nir_op_fsign:
1792 src[0] = ac_to_float(&ctx->ac, src[0]);
1793 result = emit_fsign(&ctx->ac, src[0]);
1794 break;
1795 case nir_op_ffloor:
1796 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1797 ac_to_float_type(&ctx->ac, def_type), src[0]);
1798 break;
1799 case nir_op_ftrunc:
1800 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1801 ac_to_float_type(&ctx->ac, def_type), src[0]);
1802 break;
1803 case nir_op_fceil:
1804 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1805 ac_to_float_type(&ctx->ac, def_type), src[0]);
1806 break;
1807 case nir_op_fround_even:
1808 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1809 ac_to_float_type(&ctx->ac, def_type),src[0]);
1810 break;
1811 case nir_op_ffract:
1812 result = emit_ffract(&ctx->ac, src[0]);
1813 break;
1814 case nir_op_fsin:
1815 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1816 ac_to_float_type(&ctx->ac, def_type), src[0]);
1817 break;
1818 case nir_op_fcos:
1819 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1820 ac_to_float_type(&ctx->ac, def_type), src[0]);
1821 break;
1822 case nir_op_fsqrt:
1823 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1824 ac_to_float_type(&ctx->ac, def_type), src[0]);
1825 break;
1826 case nir_op_fexp2:
1827 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1828 ac_to_float_type(&ctx->ac, def_type), src[0]);
1829 break;
1830 case nir_op_flog2:
1831 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1832 ac_to_float_type(&ctx->ac, def_type), src[0]);
1833 break;
1834 case nir_op_frsq:
1835 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1836 ac_to_float_type(&ctx->ac, def_type), src[0]);
1837 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1838 break;
1839 case nir_op_fpow:
1840 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1841 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1842 break;
1843 case nir_op_fmax:
1844 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1845 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1846 if (instr->dest.dest.ssa.bit_size == 32)
1847 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1848 ac_to_float_type(&ctx->ac, def_type),
1849 result);
1850 break;
1851 case nir_op_fmin:
1852 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1853 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1854 if (instr->dest.dest.ssa.bit_size == 32)
1855 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1856 ac_to_float_type(&ctx->ac, def_type),
1857 result);
1858 break;
1859 case nir_op_ffma:
1860 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1861 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1862 break;
1863 case nir_op_ibitfield_extract:
1864 result = emit_bitfield_extract(&ctx->ac, true, src);
1865 break;
1866 case nir_op_ubitfield_extract:
1867 result = emit_bitfield_extract(&ctx->ac, false, src);
1868 break;
1869 case nir_op_bitfield_insert:
1870 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1871 break;
1872 case nir_op_bitfield_reverse:
1873 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1874 break;
1875 case nir_op_bit_count:
1876 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1877 break;
1878 case nir_op_vec2:
1879 case nir_op_vec3:
1880 case nir_op_vec4:
1881 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1882 src[i] = ac_to_integer(&ctx->ac, src[i]);
1883 result = ac_build_gather_values(&ctx->ac, src, num_components);
1884 break;
1885 case nir_op_f2i32:
1886 case nir_op_f2i64:
1887 src[0] = ac_to_float(&ctx->ac, src[0]);
1888 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1889 break;
1890 case nir_op_f2u32:
1891 case nir_op_f2u64:
1892 src[0] = ac_to_float(&ctx->ac, src[0]);
1893 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1894 break;
1895 case nir_op_i2f32:
1896 case nir_op_i2f64:
1897 src[0] = ac_to_integer(&ctx->ac, src[0]);
1898 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1899 break;
1900 case nir_op_u2f32:
1901 case nir_op_u2f64:
1902 src[0] = ac_to_integer(&ctx->ac, src[0]);
1903 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1904 break;
1905 case nir_op_f2f64:
1906 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1907 break;
1908 case nir_op_f2f32:
1909 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1910 break;
1911 case nir_op_u2u32:
1912 case nir_op_u2u64:
1913 src[0] = ac_to_integer(&ctx->ac, src[0]);
1914 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1915 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1916 else
1917 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1918 break;
1919 case nir_op_i2i32:
1920 case nir_op_i2i64:
1921 src[0] = ac_to_integer(&ctx->ac, src[0]);
1922 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1923 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1924 else
1925 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1926 break;
1927 case nir_op_bcsel:
1928 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1929 break;
1930 case nir_op_find_lsb:
1931 src[0] = ac_to_integer(&ctx->ac, src[0]);
1932 result = emit_find_lsb(&ctx->ac, src[0]);
1933 break;
1934 case nir_op_ufind_msb:
1935 src[0] = ac_to_integer(&ctx->ac, src[0]);
1936 result = emit_ufind_msb(&ctx->ac, src[0]);
1937 break;
1938 case nir_op_ifind_msb:
1939 src[0] = ac_to_integer(&ctx->ac, src[0]);
1940 result = emit_ifind_msb(&ctx->ac, src[0]);
1941 break;
1942 case nir_op_uadd_carry:
1943 src[0] = ac_to_integer(&ctx->ac, src[0]);
1944 src[1] = ac_to_integer(&ctx->ac, src[1]);
1945 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1946 break;
1947 case nir_op_usub_borrow:
1948 src[0] = ac_to_integer(&ctx->ac, src[0]);
1949 src[1] = ac_to_integer(&ctx->ac, src[1]);
1950 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1951 break;
1952 case nir_op_b2f:
1953 result = emit_b2f(&ctx->ac, src[0]);
1954 break;
1955 case nir_op_f2b:
1956 result = emit_f2b(&ctx->ac, src[0]);
1957 break;
1958 case nir_op_b2i:
1959 result = emit_b2i(&ctx->ac, src[0]);
1960 break;
1961 case nir_op_i2b:
1962 src[0] = ac_to_integer(&ctx->ac, src[0]);
1963 result = emit_i2b(&ctx->ac, src[0]);
1964 break;
1965 case nir_op_fquantize2f16:
1966 result = emit_f2f16(ctx->nctx, src[0]);
1967 break;
1968 case nir_op_umul_high:
1969 src[0] = ac_to_integer(&ctx->ac, src[0]);
1970 src[1] = ac_to_integer(&ctx->ac, src[1]);
1971 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1972 break;
1973 case nir_op_imul_high:
1974 src[0] = ac_to_integer(&ctx->ac, src[0]);
1975 src[1] = ac_to_integer(&ctx->ac, src[1]);
1976 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1977 break;
1978 case nir_op_pack_half_2x16:
1979 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1980 break;
1981 case nir_op_unpack_half_2x16:
1982 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1983 break;
1984 case nir_op_fddx:
1985 case nir_op_fddy:
1986 case nir_op_fddx_fine:
1987 case nir_op_fddy_fine:
1988 case nir_op_fddx_coarse:
1989 case nir_op_fddy_coarse:
1990 result = emit_ddxy(ctx, instr->op, src[0]);
1991 break;
1992
1993 case nir_op_unpack_64_2x32_split_x: {
1994 assert(instr->src[0].src.ssa->num_components == 1);
1995 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1996 LLVMVectorType(ctx->ac.i32, 2),
1997 "");
1998 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1999 ctx->ac.i32_0, "");
2000 break;
2001 }
2002
2003 case nir_op_unpack_64_2x32_split_y: {
2004 assert(instr->src[0].src.ssa->num_components == 1);
2005 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2006 LLVMVectorType(ctx->ac.i32, 2),
2007 "");
2008 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2009 ctx->ac.i32_1, "");
2010 break;
2011 }
2012
2013 case nir_op_pack_64_2x32_split: {
2014 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
2015 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2016 src[0], ctx->ac.i32_0, "");
2017 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2018 src[1], ctx->ac.i32_1, "");
2019 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2020 break;
2021 }
2022
2023 default:
2024 fprintf(stderr, "Unknown NIR alu instr: ");
2025 nir_print_instr(&instr->instr, stderr);
2026 fprintf(stderr, "\n");
2027 abort();
2028 }
2029
2030 if (result) {
2031 assert(instr->dest.dest.is_ssa);
2032 result = ac_to_integer(&ctx->ac, result);
2033 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2034 result);
2035 }
2036 }
2037
2038 static void visit_load_const(struct ac_nir_context *ctx,
2039 const nir_load_const_instr *instr)
2040 {
2041 LLVMValueRef values[4], value = NULL;
2042 LLVMTypeRef element_type =
2043 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2044
2045 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2046 switch (instr->def.bit_size) {
2047 case 32:
2048 values[i] = LLVMConstInt(element_type,
2049 instr->value.u32[i], false);
2050 break;
2051 case 64:
2052 values[i] = LLVMConstInt(element_type,
2053 instr->value.u64[i], false);
2054 break;
2055 default:
2056 fprintf(stderr,
2057 "unsupported nir load_const bit_size: %d\n",
2058 instr->def.bit_size);
2059 abort();
2060 }
2061 }
2062 if (instr->def.num_components > 1) {
2063 value = LLVMConstVector(values, instr->def.num_components);
2064 } else
2065 value = values[0];
2066
2067 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2068 }
2069
2070 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2071 LLVMTypeRef type)
2072 {
2073 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2074 return LLVMBuildBitCast(ctx->builder, ptr,
2075 LLVMPointerType(type, addr_space), "");
2076 }
2077
2078 static LLVMValueRef
2079 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2080 {
2081 LLVMValueRef size =
2082 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2083 LLVMConstInt(ctx->ac.i32, 2, false), "");
2084
2085 /* VI only */
2086 if (ctx->ac.chip_class == VI && in_elements) {
2087 /* On VI, the descriptor contains the size in bytes,
2088 * but TXQ must return the size in elements.
2089 * The stride is always non-zero for resources using TXQ.
2090 */
2091 LLVMValueRef stride =
2092 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2093 LLVMConstInt(ctx->ac.i32, 1, false), "");
2094 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2095 LLVMConstInt(ctx->ac.i32, 16, false), "");
2096 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2097 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2098
2099 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2100 }
2101 return size;
2102 }
2103
2104 /**
2105 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2106 * intrinsic names).
2107 */
2108 static void build_int_type_name(
2109 LLVMTypeRef type,
2110 char *buf, unsigned bufsize)
2111 {
2112 assert(bufsize >= 6);
2113
2114 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2115 snprintf(buf, bufsize, "v%ui32",
2116 LLVMGetVectorSize(type));
2117 else
2118 strcpy(buf, "i32");
2119 }
2120
2121 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2122 struct ac_image_args *args,
2123 const nir_tex_instr *instr)
2124 {
2125 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2126 LLVMValueRef coord = args->addr;
2127 LLVMValueRef half_texel[2];
2128 LLVMValueRef compare_cube_wa = NULL;
2129 LLVMValueRef result;
2130 int c;
2131 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2132
2133 //TODO Rect
2134 {
2135 struct ac_image_args txq_args = { 0 };
2136
2137 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2138 txq_args.opcode = ac_image_get_resinfo;
2139 txq_args.dmask = 0xf;
2140 txq_args.addr = ctx->i32_0;
2141 txq_args.resource = args->resource;
2142 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2143
2144 for (c = 0; c < 2; c++) {
2145 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2146 LLVMConstInt(ctx->i32, c, false), "");
2147 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2148 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2149 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2150 LLVMConstReal(ctx->f32, -0.5), "");
2151 }
2152 }
2153
2154 LLVMValueRef orig_coords = args->addr;
2155
2156 for (c = 0; c < 2; c++) {
2157 LLVMValueRef tmp;
2158 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2159 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2160 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2161 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2162 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2163 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2164 }
2165
2166
2167 /*
2168 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2169 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2170 * workaround by sampling using a scaled type and converting.
2171 * This is taken from amdgpu-pro shaders.
2172 */
2173 /* NOTE this produces some ugly code compared to amdgpu-pro,
2174 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2175 * and then reads them back. -pro generates two selects,
2176 * one s_cmp for the descriptor rewriting
2177 * one v_cmp for the coordinate and result changes.
2178 */
2179 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2180 LLVMValueRef tmp, tmp2;
2181
2182 /* workaround 8/8/8/8 uint/sint cube gather bug */
2183 /* first detect it then change to a scaled read and f2i */
2184 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2185 tmp2 = tmp;
2186
2187 /* extract the DATA_FORMAT */
2188 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2189 LLVMConstInt(ctx->i32, 6, false), false);
2190
2191 /* is the DATA_FORMAT == 8_8_8_8 */
2192 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2193
2194 if (stype == GLSL_TYPE_UINT)
2195 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2196 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2197 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2198 else
2199 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2200 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2201 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2202
2203 /* replace the NUM FORMAT in the descriptor */
2204 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2205 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2206
2207 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2208
2209 /* don't modify the coordinates for this case */
2210 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2211 }
2212 args->addr = coord;
2213 result = ac_build_image_opcode(ctx, args);
2214
2215 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2216 LLVMValueRef tmp, tmp2;
2217
2218 /* if the cube workaround is in place, f2i the result. */
2219 for (c = 0; c < 4; c++) {
2220 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2221 if (stype == GLSL_TYPE_UINT)
2222 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2223 else
2224 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2225 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2226 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2227 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2228 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2229 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2230 }
2231 }
2232 return result;
2233 }
2234
2235 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2236 const nir_tex_instr *instr,
2237 bool lod_is_zero,
2238 struct ac_image_args *args)
2239 {
2240 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2241 return ac_build_buffer_load_format(&ctx->ac,
2242 args->resource,
2243 args->addr,
2244 LLVMConstInt(ctx->ac.i32, 0, false),
2245 true);
2246 }
2247
2248 args->opcode = ac_image_sample;
2249 args->compare = instr->is_shadow;
2250
2251 switch (instr->op) {
2252 case nir_texop_txf:
2253 case nir_texop_txf_ms:
2254 case nir_texop_samples_identical:
2255 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2256 args->compare = false;
2257 args->offset = false;
2258 break;
2259 case nir_texop_txb:
2260 args->bias = true;
2261 break;
2262 case nir_texop_txl:
2263 if (lod_is_zero)
2264 args->level_zero = true;
2265 else
2266 args->lod = true;
2267 break;
2268 case nir_texop_txs:
2269 case nir_texop_query_levels:
2270 args->opcode = ac_image_get_resinfo;
2271 break;
2272 case nir_texop_tex:
2273 if (ctx->stage != MESA_SHADER_FRAGMENT)
2274 args->level_zero = true;
2275 break;
2276 case nir_texop_txd:
2277 args->deriv = true;
2278 break;
2279 case nir_texop_tg4:
2280 args->opcode = ac_image_gather4;
2281 args->level_zero = true;
2282 break;
2283 case nir_texop_lod:
2284 args->opcode = ac_image_get_lod;
2285 args->compare = false;
2286 args->offset = false;
2287 break;
2288 default:
2289 break;
2290 }
2291
2292 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2293 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2294 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2295 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2296 }
2297 }
2298 return ac_build_image_opcode(&ctx->ac, args);
2299 }
2300
2301 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2302 nir_intrinsic_instr *instr)
2303 {
2304 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2305 unsigned desc_set = nir_intrinsic_desc_set(instr);
2306 unsigned binding = nir_intrinsic_binding(instr);
2307 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2308 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2309 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2310 unsigned base_offset = layout->binding[binding].offset;
2311 LLVMValueRef offset, stride;
2312
2313 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2314 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2315 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2316 layout->binding[binding].dynamic_offset_offset;
2317 desc_ptr = ctx->push_constants;
2318 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2319 stride = LLVMConstInt(ctx->i32, 16, false);
2320 } else
2321 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2322
2323 offset = LLVMConstInt(ctx->i32, base_offset, false);
2324 index = LLVMBuildMul(ctx->builder, index, stride, "");
2325 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2326
2327 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2328 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2329 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2330
2331 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2332 }
2333
2334 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2335 nir_intrinsic_instr *instr)
2336 {
2337 LLVMValueRef ptr, addr;
2338
2339 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2340 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2341
2342 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2343 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2344
2345 return LLVMBuildLoad(ctx->builder, ptr, "");
2346 }
2347
2348 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2349 const nir_intrinsic_instr *instr)
2350 {
2351 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2352
2353 return get_buffer_size(ctx, desc, false);
2354 }
2355 static void visit_store_ssbo(struct ac_nir_context *ctx,
2356 nir_intrinsic_instr *instr)
2357 {
2358 const char *store_name;
2359 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2360 LLVMTypeRef data_type = ctx->ac.f32;
2361 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2362 int components_32bit = elem_size_mult * instr->num_components;
2363 unsigned writemask = nir_intrinsic_write_mask(instr);
2364 LLVMValueRef base_data, base_offset;
2365 LLVMValueRef params[6];
2366 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2367
2368 params[1] = ctx->abi->load_ssbo(ctx->abi,
2369 get_src(ctx, instr->src[1]), true);
2370 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2371 params[4] = i1false; /* glc */
2372 params[5] = i1false; /* slc */
2373
2374 if (components_32bit > 1)
2375 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2376
2377 base_data = ac_to_float(&ctx->ac, src_data);
2378 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2379 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2380 data_type, "");
2381 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2382 while (writemask) {
2383 int start, count;
2384 LLVMValueRef data;
2385 LLVMValueRef offset;
2386 LLVMValueRef tmp;
2387 u_bit_scan_consecutive_range(&writemask, &start, &count);
2388
2389 /* Due to an LLVM limitation, split 3-element writes
2390 * into a 2-element and a 1-element write. */
2391 if (count == 3) {
2392 writemask |= 1 << (start + 2);
2393 count = 2;
2394 }
2395
2396 start *= elem_size_mult;
2397 count *= elem_size_mult;
2398
2399 if (count > 4) {
2400 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2401 count = 4;
2402 }
2403
2404 if (count == 4) {
2405 store_name = "llvm.amdgcn.buffer.store.v4f32";
2406 data = base_data;
2407 } else if (count == 2) {
2408 LLVMTypeRef v2f32 = LLVMVectorType(ctx->ac.f32, 2);
2409
2410 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2411 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2412 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(v2f32), tmp,
2413 ctx->ac.i32_0, "");
2414
2415 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2416 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2417 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2418 ctx->ac.i32_1, "");
2419 store_name = "llvm.amdgcn.buffer.store.v2f32";
2420
2421 } else {
2422 assert(count == 1);
2423 if (get_llvm_num_components(base_data) > 1)
2424 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2425 LLVMConstInt(ctx->ac.i32, start, false), "");
2426 else
2427 data = base_data;
2428 store_name = "llvm.amdgcn.buffer.store.f32";
2429 }
2430
2431 offset = base_offset;
2432 if (start != 0) {
2433 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2434 }
2435 params[0] = data;
2436 params[3] = offset;
2437 ac_build_intrinsic(&ctx->ac, store_name,
2438 ctx->ac.voidt, params, 6, 0);
2439 }
2440 }
2441
2442 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2443 const nir_intrinsic_instr *instr)
2444 {
2445 const char *name;
2446 LLVMValueRef params[6];
2447 int arg_count = 0;
2448
2449 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2450 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2451 }
2452 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2453 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2454 get_src(ctx, instr->src[0]),
2455 true);
2456 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2457 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2458 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2459
2460 switch (instr->intrinsic) {
2461 case nir_intrinsic_ssbo_atomic_add:
2462 name = "llvm.amdgcn.buffer.atomic.add";
2463 break;
2464 case nir_intrinsic_ssbo_atomic_imin:
2465 name = "llvm.amdgcn.buffer.atomic.smin";
2466 break;
2467 case nir_intrinsic_ssbo_atomic_umin:
2468 name = "llvm.amdgcn.buffer.atomic.umin";
2469 break;
2470 case nir_intrinsic_ssbo_atomic_imax:
2471 name = "llvm.amdgcn.buffer.atomic.smax";
2472 break;
2473 case nir_intrinsic_ssbo_atomic_umax:
2474 name = "llvm.amdgcn.buffer.atomic.umax";
2475 break;
2476 case nir_intrinsic_ssbo_atomic_and:
2477 name = "llvm.amdgcn.buffer.atomic.and";
2478 break;
2479 case nir_intrinsic_ssbo_atomic_or:
2480 name = "llvm.amdgcn.buffer.atomic.or";
2481 break;
2482 case nir_intrinsic_ssbo_atomic_xor:
2483 name = "llvm.amdgcn.buffer.atomic.xor";
2484 break;
2485 case nir_intrinsic_ssbo_atomic_exchange:
2486 name = "llvm.amdgcn.buffer.atomic.swap";
2487 break;
2488 case nir_intrinsic_ssbo_atomic_comp_swap:
2489 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2490 break;
2491 default:
2492 abort();
2493 }
2494
2495 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2496 }
2497
2498 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2499 const nir_intrinsic_instr *instr)
2500 {
2501 LLVMValueRef results[2];
2502 int load_components;
2503 int num_components = instr->num_components;
2504 if (instr->dest.ssa.bit_size == 64)
2505 num_components *= 2;
2506
2507 for (int i = 0; i < num_components; i += load_components) {
2508 load_components = MIN2(num_components - i, 4);
2509 const char *load_name;
2510 LLVMTypeRef data_type = ctx->ac.f32;
2511 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2512 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2513
2514 if (load_components == 3)
2515 data_type = LLVMVectorType(ctx->ac.f32, 4);
2516 else if (load_components > 1)
2517 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2518
2519 if (load_components >= 3)
2520 load_name = "llvm.amdgcn.buffer.load.v4f32";
2521 else if (load_components == 2)
2522 load_name = "llvm.amdgcn.buffer.load.v2f32";
2523 else if (load_components == 1)
2524 load_name = "llvm.amdgcn.buffer.load.f32";
2525 else
2526 unreachable("unhandled number of components");
2527
2528 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2529 LLVMValueRef params[] = {
2530 ctx->abi->load_ssbo(ctx->abi,
2531 get_src(ctx, instr->src[0]),
2532 false),
2533 LLVMConstInt(ctx->ac.i32, 0, false),
2534 offset,
2535 i1false,
2536 i1false,
2537 };
2538
2539 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2540
2541 }
2542
2543 assume(results[0]);
2544 LLVMValueRef ret = results[0];
2545 if (num_components > 4 || num_components == 3) {
2546 LLVMValueRef masks[] = {
2547 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2548 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2549 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2550 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2551 };
2552
2553 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2554 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2555 results[num_components > 4 ? 1 : 0], swizzle, "");
2556 }
2557
2558 return LLVMBuildBitCast(ctx->ac.builder, ret,
2559 get_def_type(ctx, &instr->dest.ssa), "");
2560 }
2561
2562 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2563 const nir_intrinsic_instr *instr)
2564 {
2565 LLVMValueRef results[8], ret;
2566 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2567 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2568 int num_components = instr->num_components;
2569
2570 if (ctx->abi->load_ubo)
2571 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2572
2573 if (instr->dest.ssa.bit_size == 64)
2574 num_components *= 2;
2575
2576 for (unsigned i = 0; i < num_components; ++i) {
2577 LLVMValueRef params[] = {
2578 rsrc,
2579 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2580 offset, "")
2581 };
2582 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2583 params, 2,
2584 AC_FUNC_ATTR_READNONE |
2585 AC_FUNC_ATTR_LEGACY);
2586 }
2587
2588
2589 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2590 return LLVMBuildBitCast(ctx->ac.builder, ret,
2591 get_def_type(ctx, &instr->dest.ssa), "");
2592 }
2593
2594 static void
2595 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2596 bool vs_in, unsigned *vertex_index_out,
2597 LLVMValueRef *vertex_index_ref,
2598 unsigned *const_out, LLVMValueRef *indir_out)
2599 {
2600 unsigned const_offset = 0;
2601 nir_deref *tail = &deref->deref;
2602 LLVMValueRef offset = NULL;
2603
2604 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2605 tail = tail->child;
2606 nir_deref_array *deref_array = nir_deref_as_array(tail);
2607 if (vertex_index_out)
2608 *vertex_index_out = deref_array->base_offset;
2609
2610 if (vertex_index_ref) {
2611 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2612 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2613 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2614 }
2615 *vertex_index_ref = vtx;
2616 }
2617 }
2618
2619 if (deref->var->data.compact) {
2620 assert(tail->child->deref_type == nir_deref_type_array);
2621 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2622 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2623 /* We always lower indirect dereferences for "compact" array vars. */
2624 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2625
2626 const_offset = deref_array->base_offset;
2627 goto out;
2628 }
2629
2630 while (tail->child != NULL) {
2631 const struct glsl_type *parent_type = tail->type;
2632 tail = tail->child;
2633
2634 if (tail->deref_type == nir_deref_type_array) {
2635 nir_deref_array *deref_array = nir_deref_as_array(tail);
2636 LLVMValueRef index, stride, local_offset;
2637 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2638
2639 const_offset += size * deref_array->base_offset;
2640 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2641 continue;
2642
2643 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2644 index = get_src(ctx, deref_array->indirect);
2645 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2646 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2647
2648 if (offset)
2649 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2650 else
2651 offset = local_offset;
2652 } else if (tail->deref_type == nir_deref_type_struct) {
2653 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2654
2655 for (unsigned i = 0; i < deref_struct->index; i++) {
2656 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2657 const_offset += glsl_count_attribute_slots(ft, vs_in);
2658 }
2659 } else
2660 unreachable("unsupported deref type");
2661
2662 }
2663 out:
2664 if (const_offset && offset)
2665 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2666 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2667 "");
2668
2669 *const_out = const_offset;
2670 *indir_out = offset;
2671 }
2672
2673 static LLVMValueRef
2674 lds_load(struct nir_to_llvm_context *ctx,
2675 LLVMValueRef dw_addr)
2676 {
2677 LLVMValueRef value;
2678 value = ac_build_load(&ctx->ac, ctx->lds, dw_addr);
2679 return value;
2680 }
2681
2682 static void
2683 lds_store(struct nir_to_llvm_context *ctx,
2684 LLVMValueRef dw_addr, LLVMValueRef value)
2685 {
2686 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2687 ac_build_indexed_store(&ctx->ac, ctx->lds,
2688 dw_addr, value);
2689 }
2690
2691 /* The offchip buffer layout for TCS->TES is
2692 *
2693 * - attribute 0 of patch 0 vertex 0
2694 * - attribute 0 of patch 0 vertex 1
2695 * - attribute 0 of patch 0 vertex 2
2696 * ...
2697 * - attribute 0 of patch 1 vertex 0
2698 * - attribute 0 of patch 1 vertex 1
2699 * ...
2700 * - attribute 1 of patch 0 vertex 0
2701 * - attribute 1 of patch 0 vertex 1
2702 * ...
2703 * - per patch attribute 0 of patch 0
2704 * - per patch attribute 0 of patch 1
2705 * ...
2706 *
2707 * Note that every attribute has 4 components.
2708 */
2709 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2710 LLVMValueRef vertex_index,
2711 LLVMValueRef param_index)
2712 {
2713 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2714 LLVMValueRef param_stride, constant16;
2715 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2716
2717 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2718 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2719 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2720 num_patches, "");
2721
2722 constant16 = LLVMConstInt(ctx->i32, 16, false);
2723 if (vertex_index) {
2724 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2725 vertices_per_patch, "");
2726
2727 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2728 vertex_index, "");
2729
2730 param_stride = total_vertices;
2731 } else {
2732 base_addr = rel_patch_id;
2733 param_stride = num_patches;
2734 }
2735
2736 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2737 LLVMBuildMul(ctx->builder, param_index,
2738 param_stride, ""), "");
2739
2740 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2741
2742 if (!vertex_index) {
2743 LLVMValueRef patch_data_offset =
2744 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2745
2746 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2747 patch_data_offset, "");
2748 }
2749 return base_addr;
2750 }
2751
2752 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2753 unsigned param,
2754 unsigned const_index,
2755 bool is_compact,
2756 LLVMValueRef vertex_index,
2757 LLVMValueRef indir_index)
2758 {
2759 LLVMValueRef param_index;
2760
2761 if (indir_index)
2762 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2763 indir_index, "");
2764 else {
2765 if (const_index && !is_compact)
2766 param += const_index;
2767 param_index = LLVMConstInt(ctx->i32, param, false);
2768 }
2769 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2770 }
2771
2772 static void
2773 mark_tess_output(struct nir_to_llvm_context *ctx,
2774 bool is_patch, uint32_t param)
2775
2776 {
2777 if (is_patch) {
2778 ctx->tess_patch_outputs_written |= (1ull << param);
2779 } else
2780 ctx->tess_outputs_written |= (1ull << param);
2781 }
2782
2783 static LLVMValueRef
2784 get_dw_address(struct nir_to_llvm_context *ctx,
2785 LLVMValueRef dw_addr,
2786 unsigned param,
2787 unsigned const_index,
2788 bool compact_const_index,
2789 LLVMValueRef vertex_index,
2790 LLVMValueRef stride,
2791 LLVMValueRef indir_index)
2792
2793 {
2794
2795 if (vertex_index) {
2796 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2797 LLVMBuildMul(ctx->builder,
2798 vertex_index,
2799 stride, ""), "");
2800 }
2801
2802 if (indir_index)
2803 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2804 LLVMBuildMul(ctx->builder, indir_index,
2805 LLVMConstInt(ctx->i32, 4, false), ""), "");
2806 else if (const_index && !compact_const_index)
2807 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2808 LLVMConstInt(ctx->i32, const_index, false), "");
2809
2810 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2811 LLVMConstInt(ctx->i32, param * 4, false), "");
2812
2813 if (const_index && compact_const_index)
2814 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2815 LLVMConstInt(ctx->i32, const_index, false), "");
2816 return dw_addr;
2817 }
2818
2819 static LLVMValueRef
2820 build_varying_gather_values(struct ac_llvm_context *ctx, LLVMValueRef *values,
2821 unsigned value_count, unsigned component)
2822 {
2823 LLVMValueRef vec = NULL;
2824
2825 if (value_count == 1) {
2826 return values[component];
2827 } else if (!value_count)
2828 unreachable("value_count is 0");
2829
2830 for (unsigned i = component; i < value_count + component; i++) {
2831 LLVMValueRef value = values[i];
2832
2833 if (!i)
2834 vec = LLVMGetUndef( LLVMVectorType(LLVMTypeOf(value), value_count));
2835 LLVMValueRef index = LLVMConstInt(ctx->i32, i - component, false);
2836 vec = LLVMBuildInsertElement(ctx->builder, vec, value, index, "");
2837 }
2838 return vec;
2839 }
2840
2841 static LLVMValueRef
2842 load_tcs_input(struct nir_to_llvm_context *ctx,
2843 nir_intrinsic_instr *instr)
2844 {
2845 LLVMValueRef dw_addr, stride;
2846 unsigned const_index;
2847 LLVMValueRef vertex_index;
2848 LLVMValueRef indir_index;
2849 unsigned param;
2850 LLVMValueRef value[4], result;
2851 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2852 const bool is_compact = instr->variables[0]->var->data.compact;
2853 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2854 get_deref_offset(ctx->nir, instr->variables[0],
2855 false, NULL, per_vertex ? &vertex_index : NULL,
2856 &const_index, &indir_index);
2857
2858 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2859 dw_addr = get_tcs_in_current_patch_offset(ctx);
2860 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2861 indir_index);
2862
2863 unsigned comp = instr->variables[0]->var->data.location_frac;
2864 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2865 value[i] = lds_load(ctx, dw_addr);
2866 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2867 ctx->i32one, "");
2868 }
2869 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2870 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2871 return result;
2872 }
2873
2874 static LLVMValueRef
2875 load_tcs_output(struct nir_to_llvm_context *ctx,
2876 nir_intrinsic_instr *instr)
2877 {
2878 LLVMValueRef dw_addr;
2879 LLVMValueRef stride = NULL;
2880 LLVMValueRef value[4], result;
2881 LLVMValueRef vertex_index = NULL;
2882 LLVMValueRef indir_index = NULL;
2883 unsigned const_index = 0;
2884 unsigned param;
2885 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2886 const bool is_compact = instr->variables[0]->var->data.compact;
2887 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2888 get_deref_offset(ctx->nir, instr->variables[0],
2889 false, NULL, per_vertex ? &vertex_index : NULL,
2890 &const_index, &indir_index);
2891
2892 if (!instr->variables[0]->var->data.patch) {
2893 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2894 dw_addr = get_tcs_out_current_patch_offset(ctx);
2895 } else {
2896 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2897 }
2898
2899 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2900 indir_index);
2901
2902 unsigned comp = instr->variables[0]->var->data.location_frac;
2903 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2904 value[i] = lds_load(ctx, dw_addr);
2905 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2906 ctx->i32one, "");
2907 }
2908 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2909 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2910 return result;
2911 }
2912
2913 static void
2914 store_tcs_output(struct nir_to_llvm_context *ctx,
2915 nir_intrinsic_instr *instr,
2916 LLVMValueRef src,
2917 unsigned writemask)
2918 {
2919 LLVMValueRef dw_addr;
2920 LLVMValueRef stride = NULL;
2921 LLVMValueRef buf_addr = NULL;
2922 LLVMValueRef vertex_index = NULL;
2923 LLVMValueRef indir_index = NULL;
2924 unsigned const_index = 0;
2925 unsigned param;
2926 const unsigned comp = instr->variables[0]->var->data.location_frac;
2927 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2928 const bool is_compact = instr->variables[0]->var->data.compact;
2929
2930 get_deref_offset(ctx->nir, instr->variables[0],
2931 false, NULL, per_vertex ? &vertex_index : NULL,
2932 &const_index, &indir_index);
2933
2934 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2935 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2936 is_compact && const_index > 3) {
2937 const_index -= 3;
2938 param++;
2939 }
2940
2941 if (!instr->variables[0]->var->data.patch) {
2942 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2943 dw_addr = get_tcs_out_current_patch_offset(ctx);
2944 } else {
2945 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2946 }
2947
2948 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2949
2950 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2951 indir_index);
2952 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2953 vertex_index, indir_index);
2954
2955 bool is_tess_factor = false;
2956 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2957 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2958 is_tess_factor = true;
2959
2960 unsigned base = is_compact ? const_index : 0;
2961 for (unsigned chan = 0; chan < 8; chan++) {
2962 if (!(writemask & (1 << chan)))
2963 continue;
2964 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2965
2966 lds_store(ctx, dw_addr, value);
2967
2968 if (!is_tess_factor && writemask != 0xF)
2969 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2970 buf_addr, ctx->oc_lds,
2971 4 * (base + chan), 1, 0, true, false);
2972
2973 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2974 ctx->i32one, "");
2975 }
2976
2977 if (writemask == 0xF) {
2978 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2979 buf_addr, ctx->oc_lds,
2980 (base * 4), 1, 0, true, false);
2981 }
2982 }
2983
2984 static LLVMValueRef
2985 load_tes_input(struct nir_to_llvm_context *ctx,
2986 const nir_intrinsic_instr *instr)
2987 {
2988 LLVMValueRef buf_addr;
2989 LLVMValueRef result;
2990 LLVMValueRef vertex_index = NULL;
2991 LLVMValueRef indir_index = NULL;
2992 unsigned const_index = 0;
2993 unsigned param;
2994 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2995 const bool is_compact = instr->variables[0]->var->data.compact;
2996
2997 get_deref_offset(ctx->nir, instr->variables[0],
2998 false, NULL, per_vertex ? &vertex_index : NULL,
2999 &const_index, &indir_index);
3000 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
3001 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
3002 is_compact && const_index > 3) {
3003 const_index -= 3;
3004 param++;
3005 }
3006
3007 unsigned comp = instr->variables[0]->var->data.location_frac;
3008 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3009 is_compact, vertex_index, indir_index);
3010
3011 LLVMValueRef comp_offset = LLVMConstInt(ctx->i32, comp * 4, false);
3012 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3013
3014 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
3015 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3016 result = trim_vector(&ctx->ac, result, instr->num_components);
3017 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
3018 return result;
3019 }
3020
3021 static LLVMValueRef
3022 load_gs_input(struct nir_to_llvm_context *ctx,
3023 nir_intrinsic_instr *instr)
3024 {
3025 LLVMValueRef indir_index, vtx_offset;
3026 unsigned const_index;
3027 LLVMValueRef args[9];
3028 unsigned param, vtx_offset_param;
3029 LLVMValueRef value[4], result;
3030 unsigned vertex_index;
3031 get_deref_offset(ctx->nir, instr->variables[0],
3032 false, &vertex_index, NULL,
3033 &const_index, &indir_index);
3034 vtx_offset_param = vertex_index;
3035 assert(vtx_offset_param < 6);
3036 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3037 LLVMConstInt(ctx->i32, 4, false), "");
3038
3039 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
3040
3041 unsigned comp = instr->variables[0]->var->data.location_frac;
3042 for (unsigned i = comp; i < instr->num_components + comp; i++) {
3043 if (ctx->ac.chip_class >= GFX9) {
3044 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3045 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3046 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3047 value[i] = lds_load(ctx, dw_addr);
3048 } else {
3049 args[0] = ctx->esgs_ring;
3050 args[1] = vtx_offset;
3051 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
3052 args[3] = ctx->i32zero;
3053 args[4] = ctx->i32one; /* OFFEN */
3054 args[5] = ctx->i32zero; /* IDXEN */
3055 args[6] = ctx->i32one; /* GLC */
3056 args[7] = ctx->i32zero; /* SLC */
3057 args[8] = ctx->i32zero; /* TFE */
3058
3059 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3060 ctx->i32, args, 9,
3061 AC_FUNC_ATTR_READONLY |
3062 AC_FUNC_ATTR_LEGACY);
3063 }
3064 }
3065 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
3066
3067 return result;
3068 }
3069
3070 static LLVMValueRef
3071 build_gep_for_deref(struct ac_nir_context *ctx,
3072 nir_deref_var *deref)
3073 {
3074 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3075 assert(entry->data);
3076 LLVMValueRef val = entry->data;
3077 nir_deref *tail = deref->deref.child;
3078 while (tail != NULL) {
3079 LLVMValueRef offset;
3080 switch (tail->deref_type) {
3081 case nir_deref_type_array: {
3082 nir_deref_array *array = nir_deref_as_array(tail);
3083 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3084 if (array->deref_array_type ==
3085 nir_deref_array_type_indirect) {
3086 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3087 get_src(ctx,
3088 array->indirect),
3089 "");
3090 }
3091 break;
3092 }
3093 case nir_deref_type_struct: {
3094 nir_deref_struct *deref_struct =
3095 nir_deref_as_struct(tail);
3096 offset = LLVMConstInt(ctx->ac.i32,
3097 deref_struct->index, 0);
3098 break;
3099 }
3100 default:
3101 unreachable("bad deref type");
3102 }
3103 val = ac_build_gep0(&ctx->ac, val, offset);
3104 tail = tail->child;
3105 }
3106 return val;
3107 }
3108
3109 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3110 nir_intrinsic_instr *instr)
3111 {
3112 LLVMValueRef values[8];
3113 int idx = instr->variables[0]->var->data.driver_location;
3114 int ve = instr->dest.ssa.num_components;
3115 unsigned comp = instr->variables[0]->var->data.location_frac;
3116 LLVMValueRef indir_index;
3117 LLVMValueRef ret;
3118 unsigned const_index;
3119 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3120 instr->variables[0]->var->data.mode == nir_var_shader_in;
3121 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3122 &const_index, &indir_index);
3123
3124 if (instr->dest.ssa.bit_size == 64)
3125 ve *= 2;
3126
3127 switch (instr->variables[0]->var->data.mode) {
3128 case nir_var_shader_in:
3129 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3130 return load_tcs_input(ctx->nctx, instr);
3131 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3132 return load_tes_input(ctx->nctx, instr);
3133 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3134 return load_gs_input(ctx->nctx, instr);
3135 }
3136
3137 for (unsigned chan = comp; chan < ve + comp; chan++) {
3138 if (indir_index) {
3139 unsigned count = glsl_count_attribute_slots(
3140 instr->variables[0]->var->type,
3141 ctx->stage == MESA_SHADER_VERTEX);
3142 count -= chan / 4;
3143 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3144 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3145 4, false, true);
3146
3147 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3148 tmp_vec,
3149 indir_index, "");
3150 } else
3151 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3152 }
3153 break;
3154 case nir_var_local:
3155 for (unsigned chan = 0; chan < ve; chan++) {
3156 if (indir_index) {
3157 unsigned count = glsl_count_attribute_slots(
3158 instr->variables[0]->var->type, false);
3159 count -= chan / 4;
3160 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3161 &ctx->ac, ctx->locals + idx + chan, count,
3162 4, true, true);
3163
3164 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3165 tmp_vec,
3166 indir_index, "");
3167 } else {
3168 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3169 }
3170 }
3171 break;
3172 case nir_var_shared: {
3173 LLVMValueRef address = build_gep_for_deref(ctx,
3174 instr->variables[0]);
3175 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3176 return LLVMBuildBitCast(ctx->ac.builder, val,
3177 get_def_type(ctx, &instr->dest.ssa),
3178 "");
3179 }
3180 case nir_var_shader_out:
3181 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3182 return load_tcs_output(ctx->nctx, instr);
3183
3184 for (unsigned chan = comp; chan < ve + comp; chan++) {
3185 if (indir_index) {
3186 unsigned count = glsl_count_attribute_slots(
3187 instr->variables[0]->var->type, false);
3188 count -= chan / 4;
3189 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3190 &ctx->ac, ctx->outputs + idx + chan, count,
3191 4, true, true);
3192
3193 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3194 tmp_vec,
3195 indir_index, "");
3196 } else {
3197 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3198 ctx->outputs[idx + chan + const_index * 4],
3199 "");
3200 }
3201 }
3202 break;
3203 default:
3204 unreachable("unhandle variable mode");
3205 }
3206 ret = build_varying_gather_values(&ctx->ac, values, ve, comp);
3207 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3208 }
3209
3210 static void
3211 visit_store_var(struct ac_nir_context *ctx,
3212 nir_intrinsic_instr *instr)
3213 {
3214 LLVMValueRef temp_ptr, value;
3215 int idx = instr->variables[0]->var->data.driver_location;
3216 unsigned comp = instr->variables[0]->var->data.location_frac;
3217 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3218 int writemask = instr->const_index[0] << comp;
3219 LLVMValueRef indir_index;
3220 unsigned const_index;
3221 get_deref_offset(ctx, instr->variables[0], false,
3222 NULL, NULL, &const_index, &indir_index);
3223
3224 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3225 int old_writemask = writemask;
3226
3227 src = LLVMBuildBitCast(ctx->ac.builder, src,
3228 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3229 "");
3230
3231 writemask = 0;
3232 for (unsigned chan = 0; chan < 4; chan++) {
3233 if (old_writemask & (1 << chan))
3234 writemask |= 3u << (2 * chan);
3235 }
3236 }
3237
3238 switch (instr->variables[0]->var->data.mode) {
3239 case nir_var_shader_out:
3240
3241 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3242 store_tcs_output(ctx->nctx, instr, src, writemask);
3243 return;
3244 }
3245
3246 for (unsigned chan = 0; chan < 8; chan++) {
3247 int stride = 4;
3248 if (!(writemask & (1 << chan)))
3249 continue;
3250
3251 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3252
3253 if (instr->variables[0]->var->data.compact)
3254 stride = 1;
3255 if (indir_index) {
3256 unsigned count = glsl_count_attribute_slots(
3257 instr->variables[0]->var->type, false);
3258 count -= chan / 4;
3259 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3260 &ctx->ac, ctx->outputs + idx + chan, count,
3261 stride, true, true);
3262
3263 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3264 value, indir_index, "");
3265 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3266 count, stride, tmp_vec);
3267
3268 } else {
3269 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3270
3271 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3272 }
3273 }
3274 break;
3275 case nir_var_local:
3276 for (unsigned chan = 0; chan < 8; chan++) {
3277 if (!(writemask & (1 << chan)))
3278 continue;
3279
3280 value = llvm_extract_elem(&ctx->ac, src, chan);
3281 if (indir_index) {
3282 unsigned count = glsl_count_attribute_slots(
3283 instr->variables[0]->var->type, false);
3284 count -= chan / 4;
3285 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3286 &ctx->ac, ctx->locals + idx + chan, count,
3287 4, true, true);
3288
3289 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3290 value, indir_index, "");
3291 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3292 count, 4, tmp_vec);
3293 } else {
3294 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3295
3296 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3297 }
3298 }
3299 break;
3300 case nir_var_shared: {
3301 int writemask = instr->const_index[0];
3302 LLVMValueRef address = build_gep_for_deref(ctx,
3303 instr->variables[0]);
3304 LLVMValueRef val = get_src(ctx, instr->src[0]);
3305 unsigned components =
3306 glsl_get_vector_elements(
3307 nir_deref_tail(&instr->variables[0]->deref)->type);
3308 if (writemask == (1 << components) - 1) {
3309 val = LLVMBuildBitCast(
3310 ctx->ac.builder, val,
3311 LLVMGetElementType(LLVMTypeOf(address)), "");
3312 LLVMBuildStore(ctx->ac.builder, val, address);
3313 } else {
3314 for (unsigned chan = 0; chan < 4; chan++) {
3315 if (!(writemask & (1 << chan)))
3316 continue;
3317 LLVMValueRef ptr =
3318 LLVMBuildStructGEP(ctx->ac.builder,
3319 address, chan, "");
3320 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3321 chan);
3322 src = LLVMBuildBitCast(
3323 ctx->ac.builder, src,
3324 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3325 LLVMBuildStore(ctx->ac.builder, src, ptr);
3326 }
3327 }
3328 break;
3329 }
3330 default:
3331 break;
3332 }
3333 }
3334
3335 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3336 {
3337 switch (dim) {
3338 case GLSL_SAMPLER_DIM_BUF:
3339 return 1;
3340 case GLSL_SAMPLER_DIM_1D:
3341 return array ? 2 : 1;
3342 case GLSL_SAMPLER_DIM_2D:
3343 return array ? 3 : 2;
3344 case GLSL_SAMPLER_DIM_MS:
3345 return array ? 4 : 3;
3346 case GLSL_SAMPLER_DIM_3D:
3347 case GLSL_SAMPLER_DIM_CUBE:
3348 return 3;
3349 case GLSL_SAMPLER_DIM_RECT:
3350 case GLSL_SAMPLER_DIM_SUBPASS:
3351 return 2;
3352 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3353 return 3;
3354 default:
3355 break;
3356 }
3357 return 0;
3358 }
3359
3360
3361
3362 /* Adjust the sample index according to FMASK.
3363 *
3364 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3365 * which is the identity mapping. Each nibble says which physical sample
3366 * should be fetched to get that sample.
3367 *
3368 * For example, 0x11111100 means there are only 2 samples stored and
3369 * the second sample covers 3/4 of the pixel. When reading samples 0
3370 * and 1, return physical sample 0 (determined by the first two 0s
3371 * in FMASK), otherwise return physical sample 1.
3372 *
3373 * The sample index should be adjusted as follows:
3374 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3375 */
3376 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3377 LLVMValueRef coord_x, LLVMValueRef coord_y,
3378 LLVMValueRef coord_z,
3379 LLVMValueRef sample_index,
3380 LLVMValueRef fmask_desc_ptr)
3381 {
3382 LLVMValueRef fmask_load_address[4];
3383 LLVMValueRef res;
3384
3385 fmask_load_address[0] = coord_x;
3386 fmask_load_address[1] = coord_y;
3387 if (coord_z) {
3388 fmask_load_address[2] = coord_z;
3389 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3390 }
3391
3392 struct ac_image_args args = {0};
3393
3394 args.opcode = ac_image_load;
3395 args.da = coord_z ? true : false;
3396 args.resource = fmask_desc_ptr;
3397 args.dmask = 0xf;
3398 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3399
3400 res = ac_build_image_opcode(ctx, &args);
3401
3402 res = ac_to_integer(ctx, res);
3403 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3404 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3405
3406 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3407 res,
3408 ctx->i32_0, "");
3409
3410 LLVMValueRef sample_index4 =
3411 LLVMBuildMul(ctx->builder, sample_index, four, "");
3412 LLVMValueRef shifted_fmask =
3413 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3414 LLVMValueRef final_sample =
3415 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3416
3417 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3418 * resource descriptor is 0 (invalid),
3419 */
3420 LLVMValueRef fmask_desc =
3421 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3422 ctx->v8i32, "");
3423
3424 LLVMValueRef fmask_word1 =
3425 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3426 ctx->i32_1, "");
3427
3428 LLVMValueRef word1_is_nonzero =
3429 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3430 fmask_word1, ctx->i32_0, "");
3431
3432 /* Replace the MSAA sample index. */
3433 sample_index =
3434 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3435 final_sample, sample_index, "");
3436 return sample_index;
3437 }
3438
3439 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3440 const nir_intrinsic_instr *instr)
3441 {
3442 const struct glsl_type *type = instr->variables[0]->var->type;
3443 if(instr->variables[0]->deref.child)
3444 type = instr->variables[0]->deref.child->type;
3445
3446 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3447 LLVMValueRef coords[4];
3448 LLVMValueRef masks[] = {
3449 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3450 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3451 };
3452 LLVMValueRef res;
3453 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3454
3455 int count;
3456 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3457 bool is_array = glsl_sampler_type_is_array(type);
3458 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3459 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3460 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3461 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3462 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3463 count = image_type_to_components_count(dim, is_array);
3464
3465 if (is_ms) {
3466 LLVMValueRef fmask_load_address[3];
3467 int chan;
3468
3469 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3470 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3471 if (is_array)
3472 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3473 else
3474 fmask_load_address[2] = NULL;
3475 if (add_frag_pos) {
3476 for (chan = 0; chan < 2; ++chan)
3477 fmask_load_address[chan] =
3478 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3479 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3480 ctx->ac.i32, ""), "");
3481 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3482 }
3483 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3484 fmask_load_address[0],
3485 fmask_load_address[1],
3486 fmask_load_address[2],
3487 sample_index,
3488 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, true, false));
3489 }
3490 if (count == 1 && !gfx9_1d) {
3491 if (instr->src[0].ssa->num_components)
3492 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3493 else
3494 res = src0;
3495 } else {
3496 int chan;
3497 if (is_ms)
3498 count--;
3499 for (chan = 0; chan < count; ++chan) {
3500 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3501 }
3502 if (add_frag_pos) {
3503 for (chan = 0; chan < 2; ++chan)
3504 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3505 ctx->ac.i32, ""), "");
3506 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3507 count++;
3508 }
3509
3510 if (gfx9_1d) {
3511 if (is_array) {
3512 coords[2] = coords[1];
3513 coords[1] = ctx->ac.i32_0;
3514 } else
3515 coords[1] = ctx->ac.i32_0;
3516 count++;
3517 }
3518
3519 if (is_ms) {
3520 coords[count] = sample_index;
3521 count++;
3522 }
3523
3524 if (count == 3) {
3525 coords[3] = LLVMGetUndef(ctx->ac.i32);
3526 count = 4;
3527 }
3528 res = ac_build_gather_values(&ctx->ac, coords, count);
3529 }
3530 return res;
3531 }
3532
3533 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3534 const nir_intrinsic_instr *instr)
3535 {
3536 LLVMValueRef params[7];
3537 LLVMValueRef res;
3538 char intrinsic_name[64];
3539 const nir_variable *var = instr->variables[0]->var;
3540 const struct glsl_type *type = var->type;
3541 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3542 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3543
3544 if(instr->variables[0]->deref.child)
3545 type = instr->variables[0]->deref.child->type;
3546
3547 type = glsl_without_array(type);
3548 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3549 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, false);
3550 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3551 ctx->ac.i32_0, ""); /* vindex */
3552 params[2] = ctx->ac.i32_0; /* voffset */
3553 params[3] = i1false; /* glc */
3554 params[4] = i1false; /* slc */
3555 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3556 params, 5, 0);
3557
3558 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3559 res = ac_to_integer(&ctx->ac, res);
3560 } else {
3561 bool is_da = glsl_sampler_type_is_array(type) ||
3562 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3563 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3564 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3565 LLVMValueRef da = is_da ? i1true : i1false;
3566 LLVMValueRef glc = i1false;
3567 LLVMValueRef slc = i1false;
3568
3569 params[0] = get_image_coords(ctx, instr);
3570 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3571 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3572 if (HAVE_LLVM <= 0x0309) {
3573 params[3] = i1false; /* r128 */
3574 params[4] = da;
3575 params[5] = glc;
3576 params[6] = slc;
3577 } else {
3578 LLVMValueRef lwe = i1false;
3579 params[3] = glc;
3580 params[4] = slc;
3581 params[5] = lwe;
3582 params[6] = da;
3583 }
3584
3585 ac_get_image_intr_name("llvm.amdgcn.image.load",
3586 ctx->ac.v4f32, /* vdata */
3587 LLVMTypeOf(params[0]), /* coords */
3588 LLVMTypeOf(params[1]), /* rsrc */
3589 intrinsic_name, sizeof(intrinsic_name));
3590
3591 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3592 params, 7, AC_FUNC_ATTR_READONLY);
3593 }
3594 return ac_to_integer(&ctx->ac, res);
3595 }
3596
3597 static void visit_image_store(struct ac_nir_context *ctx,
3598 nir_intrinsic_instr *instr)
3599 {
3600 LLVMValueRef params[8];
3601 char intrinsic_name[64];
3602 const nir_variable *var = instr->variables[0]->var;
3603 const struct glsl_type *type = glsl_without_array(var->type);
3604 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3605 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3606 LLVMValueRef glc = i1false;
3607 bool force_glc = ctx->ac.chip_class == SI;
3608 if (force_glc)
3609 glc = i1true;
3610
3611 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3612 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3613 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, true);
3614 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3615 ctx->ac.i32_0, ""); /* vindex */
3616 params[3] = ctx->ac.i32_0; /* voffset */
3617 params[4] = glc; /* glc */
3618 params[5] = i1false; /* slc */
3619 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3620 params, 6, 0);
3621 } else {
3622 bool is_da = glsl_sampler_type_is_array(type) ||
3623 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3624 LLVMValueRef da = is_da ? i1true : i1false;
3625 LLVMValueRef slc = i1false;
3626
3627 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3628 params[1] = get_image_coords(ctx, instr); /* coords */
3629 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, true);
3630 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3631 if (HAVE_LLVM <= 0x0309) {
3632 params[4] = i1false; /* r128 */
3633 params[5] = da;
3634 params[6] = glc;
3635 params[7] = slc;
3636 } else {
3637 LLVMValueRef lwe = i1false;
3638 params[4] = glc;
3639 params[5] = slc;
3640 params[6] = lwe;
3641 params[7] = da;
3642 }
3643
3644 ac_get_image_intr_name("llvm.amdgcn.image.store",
3645 LLVMTypeOf(params[0]), /* vdata */
3646 LLVMTypeOf(params[1]), /* coords */
3647 LLVMTypeOf(params[2]), /* rsrc */
3648 intrinsic_name, sizeof(intrinsic_name));
3649
3650 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3651 params, 8, 0);
3652 }
3653
3654 }
3655
3656 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3657 const nir_intrinsic_instr *instr)
3658 {
3659 LLVMValueRef params[7];
3660 int param_count = 0;
3661 const nir_variable *var = instr->variables[0]->var;
3662
3663 const char *atomic_name;
3664 char intrinsic_name[41];
3665 const struct glsl_type *type = glsl_without_array(var->type);
3666 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3667 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3668 MAYBE_UNUSED int length;
3669
3670 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3671
3672 switch (instr->intrinsic) {
3673 case nir_intrinsic_image_atomic_add:
3674 atomic_name = "add";
3675 break;
3676 case nir_intrinsic_image_atomic_min:
3677 atomic_name = is_unsigned ? "umin" : "smin";
3678 break;
3679 case nir_intrinsic_image_atomic_max:
3680 atomic_name = is_unsigned ? "umax" : "smax";
3681 break;
3682 case nir_intrinsic_image_atomic_and:
3683 atomic_name = "and";
3684 break;
3685 case nir_intrinsic_image_atomic_or:
3686 atomic_name = "or";
3687 break;
3688 case nir_intrinsic_image_atomic_xor:
3689 atomic_name = "xor";
3690 break;
3691 case nir_intrinsic_image_atomic_exchange:
3692 atomic_name = "swap";
3693 break;
3694 case nir_intrinsic_image_atomic_comp_swap:
3695 atomic_name = "cmpswap";
3696 break;
3697 default:
3698 abort();
3699 }
3700
3701 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3702 params[param_count++] = get_src(ctx, instr->src[3]);
3703 params[param_count++] = get_src(ctx, instr->src[2]);
3704
3705 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3706 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3707 true, true);
3708 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3709 ctx->ac.i32_0, ""); /* vindex */
3710 params[param_count++] = ctx->ac.i32_0; /* voffset */
3711 params[param_count++] = i1false; /* slc */
3712
3713 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3714 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3715 } else {
3716 char coords_type[8];
3717
3718 bool da = glsl_sampler_type_is_array(type) ||
3719 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3720
3721 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3722 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3723 true, true);
3724 params[param_count++] = i1false; /* r128 */
3725 params[param_count++] = da ? i1true : i1false; /* da */
3726 params[param_count++] = i1false; /* slc */
3727
3728 build_int_type_name(LLVMTypeOf(coords),
3729 coords_type, sizeof(coords_type));
3730
3731 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3732 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3733 }
3734
3735 assert(length < sizeof(intrinsic_name));
3736 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3737 }
3738
3739 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3740 const nir_intrinsic_instr *instr)
3741 {
3742 LLVMValueRef res;
3743 const nir_variable *var = instr->variables[0]->var;
3744 const struct glsl_type *type = instr->variables[0]->var->type;
3745 bool da = glsl_sampler_type_is_array(var->type) ||
3746 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3747 if(instr->variables[0]->deref.child)
3748 type = instr->variables[0]->deref.child->type;
3749
3750 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3751 return get_buffer_size(ctx,
3752 get_sampler_desc(ctx, instr->variables[0],
3753 AC_DESC_BUFFER, true, false), true);
3754
3755 struct ac_image_args args = { 0 };
3756
3757 args.da = da;
3758 args.dmask = 0xf;
3759 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3760 args.opcode = ac_image_get_resinfo;
3761 args.addr = ctx->ac.i32_0;
3762
3763 res = ac_build_image_opcode(&ctx->ac, &args);
3764
3765 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3766
3767 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3768 glsl_sampler_type_is_array(type)) {
3769 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3770 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3771 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3772 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3773 }
3774 if (ctx->ac.chip_class >= GFX9 &&
3775 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3776 glsl_sampler_type_is_array(type)) {
3777 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3778 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3779 ctx->ac.i32_1, "");
3780
3781 }
3782 return res;
3783 }
3784
3785 #define NOOP_WAITCNT 0xf7f
3786 #define LGKM_CNT 0x07f
3787 #define VM_CNT 0xf70
3788
3789 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3790 unsigned simm16)
3791 {
3792 LLVMValueRef args[1] = {
3793 LLVMConstInt(ctx->i32, simm16, false),
3794 };
3795 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3796 ctx->voidt, args, 1, 0);
3797 }
3798
3799 static void emit_barrier(struct nir_to_llvm_context *ctx)
3800 {
3801 /* SI only (thanks to a hw bug workaround):
3802 * The real barrier instruction isn’t needed, because an entire patch
3803 * always fits into a single wave.
3804 */
3805 if (ctx->options->chip_class == SI &&
3806 ctx->stage == MESA_SHADER_TESS_CTRL) {
3807 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3808 return;
3809 }
3810 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3811 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3812 }
3813
3814 static void emit_discard_if(struct ac_nir_context *ctx,
3815 const nir_intrinsic_instr *instr)
3816 {
3817 LLVMValueRef cond;
3818
3819 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3820 get_src(ctx, instr->src[0]),
3821 ctx->ac.i32_0, "");
3822 ac_build_kill_if_false(&ctx->ac, cond);
3823 }
3824
3825 static LLVMValueRef
3826 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3827 {
3828 LLVMValueRef result;
3829 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3830 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3831 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3832
3833 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3834 }
3835
3836 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3837 const nir_intrinsic_instr *instr)
3838 {
3839 LLVMValueRef ptr, result;
3840 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3841 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3842
3843 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3844 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3845 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3846 ptr, src, src1,
3847 LLVMAtomicOrderingSequentiallyConsistent,
3848 LLVMAtomicOrderingSequentiallyConsistent,
3849 false);
3850 } else {
3851 LLVMAtomicRMWBinOp op;
3852 switch (instr->intrinsic) {
3853 case nir_intrinsic_var_atomic_add:
3854 op = LLVMAtomicRMWBinOpAdd;
3855 break;
3856 case nir_intrinsic_var_atomic_umin:
3857 op = LLVMAtomicRMWBinOpUMin;
3858 break;
3859 case nir_intrinsic_var_atomic_umax:
3860 op = LLVMAtomicRMWBinOpUMax;
3861 break;
3862 case nir_intrinsic_var_atomic_imin:
3863 op = LLVMAtomicRMWBinOpMin;
3864 break;
3865 case nir_intrinsic_var_atomic_imax:
3866 op = LLVMAtomicRMWBinOpMax;
3867 break;
3868 case nir_intrinsic_var_atomic_and:
3869 op = LLVMAtomicRMWBinOpAnd;
3870 break;
3871 case nir_intrinsic_var_atomic_or:
3872 op = LLVMAtomicRMWBinOpOr;
3873 break;
3874 case nir_intrinsic_var_atomic_xor:
3875 op = LLVMAtomicRMWBinOpXor;
3876 break;
3877 case nir_intrinsic_var_atomic_exchange:
3878 op = LLVMAtomicRMWBinOpXchg;
3879 break;
3880 default:
3881 return NULL;
3882 }
3883
3884 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3885 LLVMAtomicOrderingSequentiallyConsistent,
3886 false);
3887 }
3888 return result;
3889 }
3890
3891 #define INTERP_CENTER 0
3892 #define INTERP_CENTROID 1
3893 #define INTERP_SAMPLE 2
3894
3895 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3896 enum glsl_interp_mode interp, unsigned location)
3897 {
3898 switch (interp) {
3899 case INTERP_MODE_FLAT:
3900 default:
3901 return NULL;
3902 case INTERP_MODE_SMOOTH:
3903 case INTERP_MODE_NONE:
3904 if (location == INTERP_CENTER)
3905 return ctx->persp_center;
3906 else if (location == INTERP_CENTROID)
3907 return ctx->persp_centroid;
3908 else if (location == INTERP_SAMPLE)
3909 return ctx->persp_sample;
3910 break;
3911 case INTERP_MODE_NOPERSPECTIVE:
3912 if (location == INTERP_CENTER)
3913 return ctx->linear_center;
3914 else if (location == INTERP_CENTROID)
3915 return ctx->linear_centroid;
3916 else if (location == INTERP_SAMPLE)
3917 return ctx->linear_sample;
3918 break;
3919 }
3920 return NULL;
3921 }
3922
3923 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3924 LLVMValueRef sample_id)
3925 {
3926 LLVMValueRef result;
3927 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3928
3929 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3930 const_array(ctx->v2f32, 64), "");
3931
3932 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3933 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3934
3935 return result;
3936 }
3937
3938 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3939 {
3940 LLVMValueRef values[2];
3941
3942 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3943 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3944 return ac_build_gather_values(&ctx->ac, values, 2);
3945 }
3946
3947 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3948 const nir_intrinsic_instr *instr)
3949 {
3950 LLVMValueRef result[4];
3951 LLVMValueRef interp_param, attr_number;
3952 unsigned location;
3953 unsigned chan;
3954 LLVMValueRef src_c0 = NULL;
3955 LLVMValueRef src_c1 = NULL;
3956 LLVMValueRef src0 = NULL;
3957 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3958 switch (instr->intrinsic) {
3959 case nir_intrinsic_interp_var_at_centroid:
3960 location = INTERP_CENTROID;
3961 break;
3962 case nir_intrinsic_interp_var_at_sample:
3963 case nir_intrinsic_interp_var_at_offset:
3964 location = INTERP_CENTER;
3965 src0 = get_src(ctx->nir, instr->src[0]);
3966 break;
3967 default:
3968 break;
3969 }
3970
3971 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3972 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3973 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3974 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3975 LLVMValueRef sample_position;
3976 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3977
3978 /* fetch sample ID */
3979 sample_position = load_sample_position(ctx, src0);
3980
3981 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3982 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3983 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3984 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3985 }
3986 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3987 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3988
3989 if (location == INTERP_CENTER) {
3990 LLVMValueRef ij_out[2];
3991 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3992
3993 /*
3994 * take the I then J parameters, and the DDX/Y for it, and
3995 * calculate the IJ inputs for the interpolator.
3996 * temp1 = ddx * offset/sample.x + I;
3997 * interp_param.I = ddy * offset/sample.y + temp1;
3998 * temp1 = ddx * offset/sample.x + J;
3999 * interp_param.J = ddy * offset/sample.y + temp1;
4000 */
4001 for (unsigned i = 0; i < 2; i++) {
4002 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
4003 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
4004 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4005 ddxy_out, ix_ll, "");
4006 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4007 ddxy_out, iy_ll, "");
4008 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4009 interp_param, ix_ll, "");
4010 LLVMValueRef temp1, temp2;
4011
4012 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4013 ctx->f32, "");
4014
4015 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4016 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4017
4018 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4019 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4020
4021 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4022 temp2, ctx->i32, "");
4023 }
4024 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4025
4026 }
4027
4028 for (chan = 0; chan < 4; chan++) {
4029 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4030
4031 if (interp_param) {
4032 interp_param = LLVMBuildBitCast(ctx->builder,
4033 interp_param, LLVMVectorType(ctx->f32, 2), "");
4034 LLVMValueRef i = LLVMBuildExtractElement(
4035 ctx->builder, interp_param, ctx->i32zero, "");
4036 LLVMValueRef j = LLVMBuildExtractElement(
4037 ctx->builder, interp_param, ctx->i32one, "");
4038
4039 result[chan] = ac_build_fs_interp(&ctx->ac,
4040 llvm_chan, attr_number,
4041 ctx->prim_mask, i, j);
4042 } else {
4043 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4044 LLVMConstInt(ctx->i32, 2, false),
4045 llvm_chan, attr_number,
4046 ctx->prim_mask);
4047 }
4048 }
4049 return build_varying_gather_values(&ctx->ac, result, instr->num_components,
4050 instr->variables[0]->var->data.location_frac);
4051 }
4052
4053 static void
4054 visit_emit_vertex(struct nir_to_llvm_context *ctx,
4055 const nir_intrinsic_instr *instr)
4056 {
4057 LLVMValueRef gs_next_vertex;
4058 LLVMValueRef can_emit;
4059 int idx;
4060
4061 assert(instr->const_index[0] == 0);
4062 /* Write vertex attribute values to GSVS ring */
4063 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4064 ctx->gs_next_vertex,
4065 "");
4066
4067 /* If this thread has already emitted the declared maximum number of
4068 * vertices, kill it: excessive vertex emissions are not supposed to
4069 * have any effect, and GS threads have no externally observable
4070 * effects other than emitting vertices.
4071 */
4072 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4073 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
4074 ac_build_kill_if_false(&ctx->ac, can_emit);
4075
4076 /* loop num outputs */
4077 idx = 0;
4078 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4079 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
4080 int length = 4;
4081 int slot = idx;
4082 int slot_inc = 1;
4083
4084 if (!(ctx->output_mask & (1ull << i)))
4085 continue;
4086
4087 if (i == VARYING_SLOT_CLIP_DIST0) {
4088 /* pack clip and cull into a single set of slots */
4089 length = ctx->num_output_clips + ctx->num_output_culls;
4090 if (length > 4)
4091 slot_inc = 2;
4092 }
4093 for (unsigned j = 0; j < length; j++) {
4094 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4095 out_ptr[j], "");
4096 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4097 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4098 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
4099
4100 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4101
4102 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4103 out_val, 1,
4104 voffset, ctx->gs2vs_offset, 0,
4105 1, 1, true, true);
4106 }
4107 idx += slot_inc;
4108 }
4109
4110 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4111 ctx->i32one, "");
4112 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4113
4114 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4115 }
4116
4117 static void
4118 visit_end_primitive(struct nir_to_llvm_context *ctx,
4119 const nir_intrinsic_instr *instr)
4120 {
4121 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4122 }
4123
4124 static LLVMValueRef
4125 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4126 const nir_intrinsic_instr *instr)
4127 {
4128 LLVMValueRef coord[4] = {
4129 ctx->tes_u,
4130 ctx->tes_v,
4131 ctx->f32zero,
4132 ctx->f32zero,
4133 };
4134
4135 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4136 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
4137 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4138
4139 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4140 return LLVMBuildBitCast(ctx->builder, result,
4141 get_def_type(ctx->nir, &instr->dest.ssa), "");
4142 }
4143
4144 static void visit_intrinsic(struct ac_nir_context *ctx,
4145 nir_intrinsic_instr *instr)
4146 {
4147 LLVMValueRef result = NULL;
4148
4149 switch (instr->intrinsic) {
4150 case nir_intrinsic_load_work_group_id: {
4151 result = ctx->nctx->workgroup_ids;
4152 break;
4153 }
4154 case nir_intrinsic_load_base_vertex: {
4155 result = ctx->abi->base_vertex;
4156 break;
4157 }
4158 case nir_intrinsic_load_vertex_id_zero_base: {
4159 result = ctx->abi->vertex_id;
4160 break;
4161 }
4162 case nir_intrinsic_load_local_invocation_id: {
4163 result = ctx->nctx->local_invocation_ids;
4164 break;
4165 }
4166 case nir_intrinsic_load_base_instance:
4167 result = ctx->abi->start_instance;
4168 break;
4169 case nir_intrinsic_load_draw_id:
4170 result = ctx->abi->draw_id;
4171 break;
4172 case nir_intrinsic_load_view_index:
4173 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4174 break;
4175 case nir_intrinsic_load_invocation_id:
4176 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4177 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4178 else
4179 result = ctx->nctx->gs_invocation_id;
4180 break;
4181 case nir_intrinsic_load_primitive_id:
4182 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4183 ctx->nctx->shader_info->gs.uses_prim_id = true;
4184 result = ctx->nctx->gs_prim_id;
4185 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4186 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4187 result = ctx->nctx->tcs_patch_id;
4188 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4189 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4190 result = ctx->nctx->tes_patch_id;
4191 } else
4192 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4193 break;
4194 case nir_intrinsic_load_sample_id:
4195 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4196 break;
4197 case nir_intrinsic_load_sample_pos:
4198 result = load_sample_pos(ctx);
4199 break;
4200 case nir_intrinsic_load_sample_mask_in:
4201 result = ctx->abi->sample_coverage;
4202 break;
4203 case nir_intrinsic_load_frag_coord: {
4204 LLVMValueRef values[4] = {
4205 ctx->abi->frag_pos[0],
4206 ctx->abi->frag_pos[1],
4207 ctx->abi->frag_pos[2],
4208 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4209 };
4210 result = ac_build_gather_values(&ctx->ac, values, 4);
4211 break;
4212 }
4213 case nir_intrinsic_load_front_face:
4214 result = ctx->abi->front_face;
4215 break;
4216 case nir_intrinsic_load_instance_id:
4217 result = ctx->abi->instance_id;
4218 break;
4219 case nir_intrinsic_load_num_work_groups:
4220 result = ctx->nctx->num_work_groups;
4221 break;
4222 case nir_intrinsic_load_local_invocation_index:
4223 result = visit_load_local_invocation_index(ctx->nctx);
4224 break;
4225 case nir_intrinsic_load_push_constant:
4226 result = visit_load_push_constant(ctx->nctx, instr);
4227 break;
4228 case nir_intrinsic_vulkan_resource_index:
4229 result = visit_vulkan_resource_index(ctx->nctx, instr);
4230 break;
4231 case nir_intrinsic_store_ssbo:
4232 visit_store_ssbo(ctx, instr);
4233 break;
4234 case nir_intrinsic_load_ssbo:
4235 result = visit_load_buffer(ctx, instr);
4236 break;
4237 case nir_intrinsic_ssbo_atomic_add:
4238 case nir_intrinsic_ssbo_atomic_imin:
4239 case nir_intrinsic_ssbo_atomic_umin:
4240 case nir_intrinsic_ssbo_atomic_imax:
4241 case nir_intrinsic_ssbo_atomic_umax:
4242 case nir_intrinsic_ssbo_atomic_and:
4243 case nir_intrinsic_ssbo_atomic_or:
4244 case nir_intrinsic_ssbo_atomic_xor:
4245 case nir_intrinsic_ssbo_atomic_exchange:
4246 case nir_intrinsic_ssbo_atomic_comp_swap:
4247 result = visit_atomic_ssbo(ctx, instr);
4248 break;
4249 case nir_intrinsic_load_ubo:
4250 result = visit_load_ubo_buffer(ctx, instr);
4251 break;
4252 case nir_intrinsic_get_buffer_size:
4253 result = visit_get_buffer_size(ctx, instr);
4254 break;
4255 case nir_intrinsic_load_var:
4256 result = visit_load_var(ctx, instr);
4257 break;
4258 case nir_intrinsic_store_var:
4259 visit_store_var(ctx, instr);
4260 break;
4261 case nir_intrinsic_image_load:
4262 result = visit_image_load(ctx, instr);
4263 break;
4264 case nir_intrinsic_image_store:
4265 visit_image_store(ctx, instr);
4266 break;
4267 case nir_intrinsic_image_atomic_add:
4268 case nir_intrinsic_image_atomic_min:
4269 case nir_intrinsic_image_atomic_max:
4270 case nir_intrinsic_image_atomic_and:
4271 case nir_intrinsic_image_atomic_or:
4272 case nir_intrinsic_image_atomic_xor:
4273 case nir_intrinsic_image_atomic_exchange:
4274 case nir_intrinsic_image_atomic_comp_swap:
4275 result = visit_image_atomic(ctx, instr);
4276 break;
4277 case nir_intrinsic_image_size:
4278 result = visit_image_size(ctx, instr);
4279 break;
4280 case nir_intrinsic_discard:
4281 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4282 LLVMVoidTypeInContext(ctx->ac.context),
4283 NULL, 0, AC_FUNC_ATTR_LEGACY);
4284 break;
4285 case nir_intrinsic_discard_if:
4286 emit_discard_if(ctx, instr);
4287 break;
4288 case nir_intrinsic_memory_barrier:
4289 emit_waitcnt(ctx->nctx, VM_CNT);
4290 break;
4291 case nir_intrinsic_barrier:
4292 emit_barrier(ctx->nctx);
4293 break;
4294 case nir_intrinsic_var_atomic_add:
4295 case nir_intrinsic_var_atomic_imin:
4296 case nir_intrinsic_var_atomic_umin:
4297 case nir_intrinsic_var_atomic_imax:
4298 case nir_intrinsic_var_atomic_umax:
4299 case nir_intrinsic_var_atomic_and:
4300 case nir_intrinsic_var_atomic_or:
4301 case nir_intrinsic_var_atomic_xor:
4302 case nir_intrinsic_var_atomic_exchange:
4303 case nir_intrinsic_var_atomic_comp_swap:
4304 result = visit_var_atomic(ctx->nctx, instr);
4305 break;
4306 case nir_intrinsic_interp_var_at_centroid:
4307 case nir_intrinsic_interp_var_at_sample:
4308 case nir_intrinsic_interp_var_at_offset:
4309 result = visit_interp(ctx->nctx, instr);
4310 break;
4311 case nir_intrinsic_emit_vertex:
4312 visit_emit_vertex(ctx->nctx, instr);
4313 break;
4314 case nir_intrinsic_end_primitive:
4315 visit_end_primitive(ctx->nctx, instr);
4316 break;
4317 case nir_intrinsic_load_tess_coord:
4318 result = visit_load_tess_coord(ctx->nctx, instr);
4319 break;
4320 case nir_intrinsic_load_patch_vertices_in:
4321 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4322 break;
4323 default:
4324 fprintf(stderr, "Unknown intrinsic: ");
4325 nir_print_instr(&instr->instr, stderr);
4326 fprintf(stderr, "\n");
4327 break;
4328 }
4329 if (result) {
4330 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4331 }
4332 }
4333
4334 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4335 LLVMValueRef buffer, bool write)
4336 {
4337 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4338
4339 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4340 ctx->shader_info->fs.writes_memory = true;
4341
4342 return buffer;
4343 }
4344
4345 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4346 unsigned descriptor_set,
4347 unsigned base_index,
4348 unsigned constant_index,
4349 LLVMValueRef index,
4350 enum ac_descriptor_type desc_type,
4351 bool image, bool write)
4352 {
4353 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4354 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4355 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4356 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4357 unsigned offset = binding->offset;
4358 unsigned stride = binding->size;
4359 unsigned type_size;
4360 LLVMBuilderRef builder = ctx->builder;
4361 LLVMTypeRef type;
4362
4363 assert(base_index < layout->binding_count);
4364
4365 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4366 ctx->shader_info->fs.writes_memory = true;
4367
4368 switch (desc_type) {
4369 case AC_DESC_IMAGE:
4370 type = ctx->v8i32;
4371 type_size = 32;
4372 break;
4373 case AC_DESC_FMASK:
4374 type = ctx->v8i32;
4375 offset += 32;
4376 type_size = 32;
4377 break;
4378 case AC_DESC_SAMPLER:
4379 type = ctx->v4i32;
4380 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4381 offset += 64;
4382
4383 type_size = 16;
4384 break;
4385 case AC_DESC_BUFFER:
4386 type = ctx->v4i32;
4387 type_size = 16;
4388 break;
4389 default:
4390 unreachable("invalid desc_type\n");
4391 }
4392
4393 offset += constant_index * stride;
4394
4395 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4396 (!index || binding->immutable_samplers_equal)) {
4397 if (binding->immutable_samplers_equal)
4398 constant_index = 0;
4399
4400 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4401
4402 LLVMValueRef constants[] = {
4403 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4404 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4405 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4406 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4407 };
4408 return ac_build_gather_values(&ctx->ac, constants, 4);
4409 }
4410
4411 assert(stride % type_size == 0);
4412
4413 if (!index)
4414 index = ctx->i32zero;
4415
4416 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4417
4418 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4419 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4420
4421 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4422 }
4423
4424 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4425 const nir_deref_var *deref,
4426 enum ac_descriptor_type desc_type,
4427 bool image, bool write)
4428 {
4429 LLVMValueRef index = NULL;
4430 unsigned constant_index = 0;
4431 const nir_deref *tail = &deref->deref;
4432
4433 while (tail->child) {
4434 const nir_deref_array *child = nir_deref_as_array(tail->child);
4435 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4436
4437 if (!array_size)
4438 array_size = 1;
4439
4440 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4441
4442 if (child->deref_array_type == nir_deref_array_type_indirect) {
4443 LLVMValueRef indirect = get_src(ctx, child->indirect);
4444
4445 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4446 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4447
4448 if (!index)
4449 index = indirect;
4450 else
4451 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4452 }
4453
4454 constant_index += child->base_offset * array_size;
4455
4456 tail = &child->deref;
4457 }
4458
4459 return ctx->abi->load_sampler_desc(ctx->abi,
4460 deref->var->data.descriptor_set,
4461 deref->var->data.binding,
4462 constant_index, index,
4463 desc_type, image, write);
4464 }
4465
4466 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4467 struct ac_image_args *args,
4468 const nir_tex_instr *instr,
4469 nir_texop op,
4470 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4471 LLVMValueRef *param, unsigned count,
4472 unsigned dmask)
4473 {
4474 unsigned is_rect = 0;
4475 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4476
4477 if (op == nir_texop_lod)
4478 da = false;
4479 /* Pad to power of two vector */
4480 while (count < util_next_power_of_two(count))
4481 param[count++] = LLVMGetUndef(ctx->i32);
4482
4483 if (count > 1)
4484 args->addr = ac_build_gather_values(ctx, param, count);
4485 else
4486 args->addr = param[0];
4487
4488 args->resource = res_ptr;
4489 args->sampler = samp_ptr;
4490
4491 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4492 args->addr = param[0];
4493 return;
4494 }
4495
4496 args->dmask = dmask;
4497 args->unorm = is_rect;
4498 args->da = da;
4499 }
4500
4501 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4502 *
4503 * SI-CI:
4504 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4505 * filtering manually. The driver sets img7 to a mask clearing
4506 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4507 * s_and_b32 samp0, samp0, img7
4508 *
4509 * VI:
4510 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4511 */
4512 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4513 LLVMValueRef res, LLVMValueRef samp)
4514 {
4515 LLVMBuilderRef builder = ctx->ac.builder;
4516 LLVMValueRef img7, samp0;
4517
4518 if (ctx->ac.chip_class >= VI)
4519 return samp;
4520
4521 img7 = LLVMBuildExtractElement(builder, res,
4522 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4523 samp0 = LLVMBuildExtractElement(builder, samp,
4524 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4525 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4526 return LLVMBuildInsertElement(builder, samp, samp0,
4527 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4528 }
4529
4530 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4531 nir_tex_instr *instr,
4532 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4533 LLVMValueRef *fmask_ptr)
4534 {
4535 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4536 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, false, false);
4537 else
4538 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, false, false);
4539 if (samp_ptr) {
4540 if (instr->sampler)
4541 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, false, false);
4542 else
4543 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, false, false);
4544 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4545 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4546 }
4547 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4548 instr->op == nir_texop_samples_identical))
4549 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, false, false);
4550 }
4551
4552 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4553 LLVMValueRef coord)
4554 {
4555 coord = ac_to_float(ctx, coord);
4556 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4557 coord = ac_to_integer(ctx, coord);
4558 return coord;
4559 }
4560
4561 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4562 {
4563 LLVMValueRef result = NULL;
4564 struct ac_image_args args = { 0 };
4565 unsigned dmask = 0xf;
4566 LLVMValueRef address[16];
4567 LLVMValueRef coords[5];
4568 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4569 LLVMValueRef bias = NULL, offsets = NULL;
4570 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4571 LLVMValueRef ddx = NULL, ddy = NULL;
4572 LLVMValueRef derivs[6];
4573 unsigned chan, count = 0;
4574 unsigned const_src = 0, num_deriv_comp = 0;
4575 bool lod_is_zero = false;
4576
4577 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4578
4579 for (unsigned i = 0; i < instr->num_srcs; i++) {
4580 switch (instr->src[i].src_type) {
4581 case nir_tex_src_coord:
4582 coord = get_src(ctx, instr->src[i].src);
4583 break;
4584 case nir_tex_src_projector:
4585 break;
4586 case nir_tex_src_comparator:
4587 comparator = get_src(ctx, instr->src[i].src);
4588 break;
4589 case nir_tex_src_offset:
4590 offsets = get_src(ctx, instr->src[i].src);
4591 const_src = i;
4592 break;
4593 case nir_tex_src_bias:
4594 bias = get_src(ctx, instr->src[i].src);
4595 break;
4596 case nir_tex_src_lod: {
4597 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4598
4599 if (val && val->i32[0] == 0)
4600 lod_is_zero = true;
4601 lod = get_src(ctx, instr->src[i].src);
4602 break;
4603 }
4604 case nir_tex_src_ms_index:
4605 sample_index = get_src(ctx, instr->src[i].src);
4606 break;
4607 case nir_tex_src_ms_mcs:
4608 break;
4609 case nir_tex_src_ddx:
4610 ddx = get_src(ctx, instr->src[i].src);
4611 num_deriv_comp = instr->src[i].src.ssa->num_components;
4612 break;
4613 case nir_tex_src_ddy:
4614 ddy = get_src(ctx, instr->src[i].src);
4615 break;
4616 case nir_tex_src_texture_offset:
4617 case nir_tex_src_sampler_offset:
4618 case nir_tex_src_plane:
4619 default:
4620 break;
4621 }
4622 }
4623
4624 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4625 result = get_buffer_size(ctx, res_ptr, true);
4626 goto write_result;
4627 }
4628
4629 if (instr->op == nir_texop_texture_samples) {
4630 LLVMValueRef res, samples, is_msaa;
4631 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4632 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4633 LLVMConstInt(ctx->ac.i32, 3, false), "");
4634 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4635 LLVMConstInt(ctx->ac.i32, 28, false), "");
4636 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4637 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4638 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4639 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4640
4641 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4642 LLVMConstInt(ctx->ac.i32, 16, false), "");
4643 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4644 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4645 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4646 samples, "");
4647 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4648 ctx->ac.i32_1, "");
4649 result = samples;
4650 goto write_result;
4651 }
4652
4653 if (coord)
4654 for (chan = 0; chan < instr->coord_components; chan++)
4655 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4656
4657 if (offsets && instr->op != nir_texop_txf) {
4658 LLVMValueRef offset[3], pack;
4659 for (chan = 0; chan < 3; ++chan)
4660 offset[chan] = ctx->ac.i32_0;
4661
4662 args.offset = true;
4663 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4664 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4665 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4666 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4667 if (chan)
4668 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4669 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4670 }
4671 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4672 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4673 address[count++] = pack;
4674
4675 }
4676 /* pack LOD bias value */
4677 if (instr->op == nir_texop_txb && bias) {
4678 address[count++] = bias;
4679 }
4680
4681 /* Pack depth comparison value */
4682 if (instr->is_shadow && comparator) {
4683 LLVMValueRef z = ac_to_float(&ctx->ac,
4684 llvm_extract_elem(&ctx->ac, comparator, 0));
4685
4686 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4687 * so the depth comparison value isn't clamped for Z16 and
4688 * Z24 anymore. Do it manually here.
4689 *
4690 * It's unnecessary if the original texture format was
4691 * Z32_FLOAT, but we don't know that here.
4692 */
4693 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4694 z = ac_build_clamp(&ctx->ac, z);
4695
4696 address[count++] = z;
4697 }
4698
4699 /* pack derivatives */
4700 if (ddx || ddy) {
4701 int num_src_deriv_channels, num_dest_deriv_channels;
4702 switch (instr->sampler_dim) {
4703 case GLSL_SAMPLER_DIM_3D:
4704 case GLSL_SAMPLER_DIM_CUBE:
4705 num_deriv_comp = 3;
4706 num_src_deriv_channels = 3;
4707 num_dest_deriv_channels = 3;
4708 break;
4709 case GLSL_SAMPLER_DIM_2D:
4710 default:
4711 num_src_deriv_channels = 2;
4712 num_dest_deriv_channels = 2;
4713 num_deriv_comp = 2;
4714 break;
4715 case GLSL_SAMPLER_DIM_1D:
4716 num_src_deriv_channels = 1;
4717 if (ctx->ac.chip_class >= GFX9) {
4718 num_dest_deriv_channels = 2;
4719 num_deriv_comp = 2;
4720 } else {
4721 num_dest_deriv_channels = 1;
4722 num_deriv_comp = 1;
4723 }
4724 break;
4725 }
4726
4727 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4728 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4729 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4730 }
4731 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4732 derivs[i] = ctx->ac.f32_0;
4733 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4734 }
4735 }
4736
4737 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4738 for (chan = 0; chan < instr->coord_components; chan++)
4739 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4740 if (instr->coord_components == 3)
4741 coords[3] = LLVMGetUndef(ctx->ac.f32);
4742 ac_prepare_cube_coords(&ctx->ac,
4743 instr->op == nir_texop_txd, instr->is_array,
4744 instr->op == nir_texop_lod, coords, derivs);
4745 if (num_deriv_comp)
4746 num_deriv_comp--;
4747 }
4748
4749 if (ddx || ddy) {
4750 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4751 address[count++] = derivs[i];
4752 }
4753
4754 /* Pack texture coordinates */
4755 if (coord) {
4756 address[count++] = coords[0];
4757 if (instr->coord_components > 1) {
4758 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4759 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4760 }
4761 address[count++] = coords[1];
4762 }
4763 if (instr->coord_components > 2) {
4764 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4765 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4766 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4767 instr->op != nir_texop_txf) {
4768 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4769 }
4770 address[count++] = coords[2];
4771 }
4772
4773 if (ctx->ac.chip_class >= GFX9) {
4774 LLVMValueRef filler;
4775 if (instr->op == nir_texop_txf)
4776 filler = ctx->ac.i32_0;
4777 else
4778 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4779
4780 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4781 /* No nir_texop_lod, because it does not take a slice
4782 * even with array textures. */
4783 if (instr->is_array && instr->op != nir_texop_lod ) {
4784 address[count] = address[count - 1];
4785 address[count - 1] = filler;
4786 count++;
4787 } else
4788 address[count++] = filler;
4789 }
4790 }
4791 }
4792
4793 /* Pack LOD */
4794 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4795 instr->op == nir_texop_txf)) {
4796 address[count++] = lod;
4797 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4798 address[count++] = sample_index;
4799 } else if(instr->op == nir_texop_txs) {
4800 count = 0;
4801 if (lod)
4802 address[count++] = lod;
4803 else
4804 address[count++] = ctx->ac.i32_0;
4805 }
4806
4807 for (chan = 0; chan < count; chan++) {
4808 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4809 address[chan], ctx->ac.i32, "");
4810 }
4811
4812 if (instr->op == nir_texop_samples_identical) {
4813 LLVMValueRef txf_address[4];
4814 struct ac_image_args txf_args = { 0 };
4815 unsigned txf_count = count;
4816 memcpy(txf_address, address, sizeof(txf_address));
4817
4818 if (!instr->is_array)
4819 txf_address[2] = ctx->ac.i32_0;
4820 txf_address[3] = ctx->ac.i32_0;
4821
4822 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4823 fmask_ptr, NULL,
4824 txf_address, txf_count, 0xf);
4825
4826 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4827
4828 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4829 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4830 goto write_result;
4831 }
4832
4833 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4834 instr->op != nir_texop_txs) {
4835 unsigned sample_chan = instr->is_array ? 3 : 2;
4836 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4837 address[0],
4838 address[1],
4839 instr->is_array ? address[2] : NULL,
4840 address[sample_chan],
4841 fmask_ptr);
4842 }
4843
4844 if (offsets && instr->op == nir_texop_txf) {
4845 nir_const_value *const_offset =
4846 nir_src_as_const_value(instr->src[const_src].src);
4847 int num_offsets = instr->src[const_src].src.ssa->num_components;
4848 assert(const_offset);
4849 num_offsets = MIN2(num_offsets, instr->coord_components);
4850 if (num_offsets > 2)
4851 address[2] = LLVMBuildAdd(ctx->ac.builder,
4852 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4853 if (num_offsets > 1)
4854 address[1] = LLVMBuildAdd(ctx->ac.builder,
4855 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4856 address[0] = LLVMBuildAdd(ctx->ac.builder,
4857 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4858
4859 }
4860
4861 /* TODO TG4 support */
4862 if (instr->op == nir_texop_tg4) {
4863 if (instr->is_shadow)
4864 dmask = 1;
4865 else
4866 dmask = 1 << instr->component;
4867 }
4868 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4869 res_ptr, samp_ptr, address, count, dmask);
4870
4871 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4872
4873 if (instr->op == nir_texop_query_levels)
4874 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4875 else if (instr->is_shadow && instr->is_new_style_shadow &&
4876 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4877 instr->op != nir_texop_tg4)
4878 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4879 else if (instr->op == nir_texop_txs &&
4880 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4881 instr->is_array) {
4882 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4883 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4884 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4885 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4886 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4887 } else if (ctx->ac.chip_class >= GFX9 &&
4888 instr->op == nir_texop_txs &&
4889 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4890 instr->is_array) {
4891 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4892 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4893 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4894 ctx->ac.i32_1, "");
4895 } else if (instr->dest.ssa.num_components != 4)
4896 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4897
4898 write_result:
4899 if (result) {
4900 assert(instr->dest.is_ssa);
4901 result = ac_to_integer(&ctx->ac, result);
4902 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4903 }
4904 }
4905
4906
4907 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4908 {
4909 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4910 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4911
4912 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4913 _mesa_hash_table_insert(ctx->phis, instr, result);
4914 }
4915
4916 static void visit_post_phi(struct ac_nir_context *ctx,
4917 nir_phi_instr *instr,
4918 LLVMValueRef llvm_phi)
4919 {
4920 nir_foreach_phi_src(src, instr) {
4921 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4922 LLVMValueRef llvm_src = get_src(ctx, src->src);
4923
4924 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4925 }
4926 }
4927
4928 static void phi_post_pass(struct ac_nir_context *ctx)
4929 {
4930 struct hash_entry *entry;
4931 hash_table_foreach(ctx->phis, entry) {
4932 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4933 (LLVMValueRef)entry->data);
4934 }
4935 }
4936
4937
4938 static void visit_ssa_undef(struct ac_nir_context *ctx,
4939 const nir_ssa_undef_instr *instr)
4940 {
4941 unsigned num_components = instr->def.num_components;
4942 LLVMValueRef undef;
4943
4944 if (num_components == 1)
4945 undef = LLVMGetUndef(ctx->ac.i32);
4946 else {
4947 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4948 }
4949 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4950 }
4951
4952 static void visit_jump(struct ac_nir_context *ctx,
4953 const nir_jump_instr *instr)
4954 {
4955 switch (instr->type) {
4956 case nir_jump_break:
4957 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4958 LLVMClearInsertionPosition(ctx->ac.builder);
4959 break;
4960 case nir_jump_continue:
4961 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4962 LLVMClearInsertionPosition(ctx->ac.builder);
4963 break;
4964 default:
4965 fprintf(stderr, "Unknown NIR jump instr: ");
4966 nir_print_instr(&instr->instr, stderr);
4967 fprintf(stderr, "\n");
4968 abort();
4969 }
4970 }
4971
4972 static void visit_cf_list(struct ac_nir_context *ctx,
4973 struct exec_list *list);
4974
4975 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4976 {
4977 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4978 nir_foreach_instr(instr, block)
4979 {
4980 switch (instr->type) {
4981 case nir_instr_type_alu:
4982 visit_alu(ctx, nir_instr_as_alu(instr));
4983 break;
4984 case nir_instr_type_load_const:
4985 visit_load_const(ctx, nir_instr_as_load_const(instr));
4986 break;
4987 case nir_instr_type_intrinsic:
4988 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4989 break;
4990 case nir_instr_type_tex:
4991 visit_tex(ctx, nir_instr_as_tex(instr));
4992 break;
4993 case nir_instr_type_phi:
4994 visit_phi(ctx, nir_instr_as_phi(instr));
4995 break;
4996 case nir_instr_type_ssa_undef:
4997 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4998 break;
4999 case nir_instr_type_jump:
5000 visit_jump(ctx, nir_instr_as_jump(instr));
5001 break;
5002 default:
5003 fprintf(stderr, "Unknown NIR instr type: ");
5004 nir_print_instr(instr, stderr);
5005 fprintf(stderr, "\n");
5006 abort();
5007 }
5008 }
5009
5010 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5011 }
5012
5013 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5014 {
5015 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5016
5017 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5018 LLVMBasicBlockRef merge_block =
5019 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5020 LLVMBasicBlockRef if_block =
5021 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5022 LLVMBasicBlockRef else_block = merge_block;
5023 if (!exec_list_is_empty(&if_stmt->else_list))
5024 else_block = LLVMAppendBasicBlockInContext(
5025 ctx->ac.context, fn, "");
5026
5027 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5028 LLVMConstInt(ctx->ac.i32, 0, false), "");
5029 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5030
5031 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5032 visit_cf_list(ctx, &if_stmt->then_list);
5033 if (LLVMGetInsertBlock(ctx->ac.builder))
5034 LLVMBuildBr(ctx->ac.builder, merge_block);
5035
5036 if (!exec_list_is_empty(&if_stmt->else_list)) {
5037 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5038 visit_cf_list(ctx, &if_stmt->else_list);
5039 if (LLVMGetInsertBlock(ctx->ac.builder))
5040 LLVMBuildBr(ctx->ac.builder, merge_block);
5041 }
5042
5043 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5044 }
5045
5046 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5047 {
5048 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5049 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5050 LLVMBasicBlockRef break_parent = ctx->break_block;
5051
5052 ctx->continue_block =
5053 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5054 ctx->break_block =
5055 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5056
5057 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5058 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5059 visit_cf_list(ctx, &loop->body);
5060
5061 if (LLVMGetInsertBlock(ctx->ac.builder))
5062 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5063 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5064
5065 ctx->continue_block = continue_parent;
5066 ctx->break_block = break_parent;
5067 }
5068
5069 static void visit_cf_list(struct ac_nir_context *ctx,
5070 struct exec_list *list)
5071 {
5072 foreach_list_typed(nir_cf_node, node, node, list)
5073 {
5074 switch (node->type) {
5075 case nir_cf_node_block:
5076 visit_block(ctx, nir_cf_node_as_block(node));
5077 break;
5078
5079 case nir_cf_node_if:
5080 visit_if(ctx, nir_cf_node_as_if(node));
5081 break;
5082
5083 case nir_cf_node_loop:
5084 visit_loop(ctx, nir_cf_node_as_loop(node));
5085 break;
5086
5087 default:
5088 assert(0);
5089 }
5090 }
5091 }
5092
5093 static void
5094 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5095 struct nir_variable *variable)
5096 {
5097 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5098 LLVMValueRef t_offset;
5099 LLVMValueRef t_list;
5100 LLVMValueRef input;
5101 LLVMValueRef buffer_index;
5102 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5103 int idx = variable->data.location;
5104 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5105
5106 variable->data.driver_location = idx * 4;
5107
5108 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5109 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5110 ctx->abi.start_instance, "");
5111 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5112 ctx->shader_info->vs.vgpr_comp_cnt);
5113 } else
5114 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5115 ctx->abi.base_vertex, "");
5116
5117 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5118 t_offset = LLVMConstInt(ctx->i32, index + i, false);
5119
5120 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5121
5122 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5123 buffer_index,
5124 LLVMConstInt(ctx->i32, 0, false),
5125 true);
5126
5127 for (unsigned chan = 0; chan < 4; chan++) {
5128 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
5129 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5130 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5131 input, llvm_chan, ""));
5132 }
5133 }
5134 }
5135
5136 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5137 unsigned attr,
5138 LLVMValueRef interp_param,
5139 LLVMValueRef prim_mask,
5140 LLVMValueRef result[4])
5141 {
5142 LLVMValueRef attr_number;
5143 unsigned chan;
5144 LLVMValueRef i, j;
5145 bool interp = interp_param != NULL;
5146
5147 attr_number = LLVMConstInt(ctx->i32, attr, false);
5148
5149 /* fs.constant returns the param from the middle vertex, so it's not
5150 * really useful for flat shading. It's meant to be used for custom
5151 * interpolation (but the intrinsic can't fetch from the other two
5152 * vertices).
5153 *
5154 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5155 * to do the right thing. The only reason we use fs.constant is that
5156 * fs.interp cannot be used on integers, because they can be equal
5157 * to NaN.
5158 */
5159 if (interp) {
5160 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5161 LLVMVectorType(ctx->f32, 2), "");
5162
5163 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5164 ctx->i32zero, "");
5165 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5166 ctx->i32one, "");
5167 }
5168
5169 for (chan = 0; chan < 4; chan++) {
5170 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
5171
5172 if (interp) {
5173 result[chan] = ac_build_fs_interp(&ctx->ac,
5174 llvm_chan,
5175 attr_number,
5176 prim_mask, i, j);
5177 } else {
5178 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5179 LLVMConstInt(ctx->i32, 2, false),
5180 llvm_chan,
5181 attr_number,
5182 prim_mask);
5183 }
5184 }
5185 }
5186
5187 static void
5188 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5189 struct nir_variable *variable)
5190 {
5191 int idx = variable->data.location;
5192 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5193 LLVMValueRef interp;
5194
5195 variable->data.driver_location = idx * 4;
5196 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5197
5198 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5199 unsigned interp_type;
5200 if (variable->data.sample) {
5201 interp_type = INTERP_SAMPLE;
5202 ctx->shader_info->info.ps.force_persample = true;
5203 } else if (variable->data.centroid)
5204 interp_type = INTERP_CENTROID;
5205 else
5206 interp_type = INTERP_CENTER;
5207
5208 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5209 } else
5210 interp = NULL;
5211
5212 for (unsigned i = 0; i < attrib_count; ++i)
5213 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5214
5215 }
5216
5217 static void
5218 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5219 struct nir_shader *nir) {
5220 nir_foreach_variable(variable, &nir->inputs)
5221 handle_vs_input_decl(ctx, variable);
5222 }
5223
5224 static void
5225 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5226 struct nir_shader *nir)
5227 {
5228 if (!ctx->options->key.fs.multisample)
5229 return;
5230
5231 bool uses_center = false;
5232 bool uses_centroid = false;
5233 nir_foreach_variable(variable, &nir->inputs) {
5234 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5235 variable->data.sample)
5236 continue;
5237
5238 if (variable->data.centroid)
5239 uses_centroid = true;
5240 else
5241 uses_center = true;
5242 }
5243
5244 if (uses_center && uses_centroid) {
5245 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5246 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5247 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5248 }
5249 }
5250
5251 static void
5252 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5253 struct nir_shader *nir)
5254 {
5255 prepare_interp_optimize(ctx, nir);
5256
5257 nir_foreach_variable(variable, &nir->inputs)
5258 handle_fs_input_decl(ctx, variable);
5259
5260 unsigned index = 0;
5261
5262 if (ctx->shader_info->info.ps.uses_input_attachments ||
5263 ctx->shader_info->info.needs_multiview_view_index)
5264 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5265
5266 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5267 LLVMValueRef interp_param;
5268 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5269
5270 if (!(ctx->input_mask & (1ull << i)))
5271 continue;
5272
5273 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5274 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5275 interp_param = *inputs;
5276 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5277 inputs);
5278
5279 if (!interp_param)
5280 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5281 ++index;
5282 } else if (i == VARYING_SLOT_POS) {
5283 for(int i = 0; i < 3; ++i)
5284 inputs[i] = ctx->abi.frag_pos[i];
5285
5286 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one,
5287 ctx->abi.frag_pos[3]);
5288 }
5289 }
5290 ctx->shader_info->fs.num_interp = index;
5291 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5292 ctx->shader_info->fs.has_pcoord = true;
5293 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5294 ctx->shader_info->fs.prim_id_input = true;
5295 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5296 ctx->shader_info->fs.layer_input = true;
5297 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5298
5299 if (ctx->shader_info->info.needs_multiview_view_index)
5300 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5301 }
5302
5303 static LLVMValueRef
5304 ac_build_alloca(struct ac_llvm_context *ac,
5305 LLVMTypeRef type,
5306 const char *name)
5307 {
5308 LLVMBuilderRef builder = ac->builder;
5309 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5310 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5311 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5312 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5313 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5314 LLVMValueRef res;
5315
5316 if (first_instr) {
5317 LLVMPositionBuilderBefore(first_builder, first_instr);
5318 } else {
5319 LLVMPositionBuilderAtEnd(first_builder, first_block);
5320 }
5321
5322 res = LLVMBuildAlloca(first_builder, type, name);
5323 LLVMBuildStore(builder, LLVMConstNull(type), res);
5324
5325 LLVMDisposeBuilder(first_builder);
5326
5327 return res;
5328 }
5329
5330 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5331 LLVMTypeRef type,
5332 const char *name)
5333 {
5334 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5335 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5336 return ptr;
5337 }
5338
5339 static void
5340 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5341 struct nir_variable *variable,
5342 struct nir_shader *shader,
5343 gl_shader_stage stage)
5344 {
5345 int idx = variable->data.location + variable->data.index;
5346 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5347 uint64_t mask_attribs;
5348
5349 variable->data.driver_location = idx * 4;
5350
5351 /* tess ctrl has it's own load/store paths for outputs */
5352 if (stage == MESA_SHADER_TESS_CTRL)
5353 return;
5354
5355 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5356 if (stage == MESA_SHADER_VERTEX ||
5357 stage == MESA_SHADER_TESS_EVAL ||
5358 stage == MESA_SHADER_GEOMETRY) {
5359 if (idx == VARYING_SLOT_CLIP_DIST0) {
5360 int length = shader->info.clip_distance_array_size +
5361 shader->info.cull_distance_array_size;
5362 if (stage == MESA_SHADER_VERTEX) {
5363 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5364 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5365 }
5366 if (stage == MESA_SHADER_TESS_EVAL) {
5367 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5368 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5369 }
5370
5371 if (length > 4)
5372 attrib_count = 2;
5373 else
5374 attrib_count = 1;
5375 mask_attribs = 1ull << idx;
5376 }
5377 }
5378
5379 ctx->output_mask |= mask_attribs;
5380 }
5381
5382 static void
5383 handle_shader_output_decl(struct ac_nir_context *ctx,
5384 struct nir_shader *nir,
5385 struct nir_variable *variable)
5386 {
5387 unsigned output_loc = variable->data.driver_location / 4;
5388 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5389
5390 /* tess ctrl has it's own load/store paths for outputs */
5391 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5392 return;
5393
5394 if (ctx->stage == MESA_SHADER_VERTEX ||
5395 ctx->stage == MESA_SHADER_TESS_EVAL ||
5396 ctx->stage == MESA_SHADER_GEOMETRY) {
5397 int idx = variable->data.location + variable->data.index;
5398 if (idx == VARYING_SLOT_CLIP_DIST0) {
5399 int length = nir->info.clip_distance_array_size +
5400 nir->info.cull_distance_array_size;
5401
5402 if (length > 4)
5403 attrib_count = 2;
5404 else
5405 attrib_count = 1;
5406 }
5407 }
5408
5409 for (unsigned i = 0; i < attrib_count; ++i) {
5410 for (unsigned chan = 0; chan < 4; chan++) {
5411 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5412 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5413 }
5414 }
5415 }
5416
5417 static LLVMTypeRef
5418 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5419 enum glsl_base_type type)
5420 {
5421 switch (type) {
5422 case GLSL_TYPE_INT:
5423 case GLSL_TYPE_UINT:
5424 case GLSL_TYPE_BOOL:
5425 case GLSL_TYPE_SUBROUTINE:
5426 return ctx->i32;
5427 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5428 return ctx->f32;
5429 case GLSL_TYPE_INT64:
5430 case GLSL_TYPE_UINT64:
5431 return ctx->i64;
5432 case GLSL_TYPE_DOUBLE:
5433 return ctx->f64;
5434 default:
5435 unreachable("unknown GLSL type");
5436 }
5437 }
5438
5439 static LLVMTypeRef
5440 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5441 const struct glsl_type *type)
5442 {
5443 if (glsl_type_is_scalar(type)) {
5444 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5445 }
5446
5447 if (glsl_type_is_vector(type)) {
5448 return LLVMVectorType(
5449 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5450 glsl_get_vector_elements(type));
5451 }
5452
5453 if (glsl_type_is_matrix(type)) {
5454 return LLVMArrayType(
5455 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5456 glsl_get_matrix_columns(type));
5457 }
5458
5459 if (glsl_type_is_array(type)) {
5460 return LLVMArrayType(
5461 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5462 glsl_get_length(type));
5463 }
5464
5465 assert(glsl_type_is_struct(type));
5466
5467 LLVMTypeRef member_types[glsl_get_length(type)];
5468
5469 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5470 member_types[i] =
5471 glsl_to_llvm_type(ctx,
5472 glsl_get_struct_field(type, i));
5473 }
5474
5475 return LLVMStructTypeInContext(ctx->context, member_types,
5476 glsl_get_length(type), false);
5477 }
5478
5479 static void
5480 setup_locals(struct ac_nir_context *ctx,
5481 struct nir_function *func)
5482 {
5483 int i, j;
5484 ctx->num_locals = 0;
5485 nir_foreach_variable(variable, &func->impl->locals) {
5486 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5487 variable->data.driver_location = ctx->num_locals * 4;
5488 ctx->num_locals += attrib_count;
5489 }
5490 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5491 if (!ctx->locals)
5492 return;
5493
5494 for (i = 0; i < ctx->num_locals; i++) {
5495 for (j = 0; j < 4; j++) {
5496 ctx->locals[i * 4 + j] =
5497 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5498 }
5499 }
5500 }
5501
5502 static void
5503 setup_shared(struct ac_nir_context *ctx,
5504 struct nir_shader *nir)
5505 {
5506 nir_foreach_variable(variable, &nir->shared) {
5507 LLVMValueRef shared =
5508 LLVMAddGlobalInAddressSpace(
5509 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5510 variable->name ? variable->name : "",
5511 LOCAL_ADDR_SPACE);
5512 _mesa_hash_table_insert(ctx->vars, variable, shared);
5513 }
5514 }
5515
5516 static LLVMValueRef
5517 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5518 {
5519 v = ac_to_float(ctx, v);
5520 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5521 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5522 }
5523
5524
5525 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5526 LLVMValueRef src0, LLVMValueRef src1)
5527 {
5528 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5529 LLVMValueRef comp[2];
5530
5531 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5532 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5533 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5534 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5535 }
5536
5537 /* Initialize arguments for the shader export intrinsic */
5538 static void
5539 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5540 LLVMValueRef *values,
5541 unsigned target,
5542 struct ac_export_args *args)
5543 {
5544 /* Default is 0xf. Adjusted below depending on the format. */
5545 args->enabled_channels = 0xf;
5546
5547 /* Specify whether the EXEC mask represents the valid mask */
5548 args->valid_mask = 0;
5549
5550 /* Specify whether this is the last export */
5551 args->done = 0;
5552
5553 /* Specify the target we are exporting */
5554 args->target = target;
5555
5556 args->compr = false;
5557 args->out[0] = LLVMGetUndef(ctx->f32);
5558 args->out[1] = LLVMGetUndef(ctx->f32);
5559 args->out[2] = LLVMGetUndef(ctx->f32);
5560 args->out[3] = LLVMGetUndef(ctx->f32);
5561
5562 if (!values)
5563 return;
5564
5565 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5566 LLVMValueRef val[4];
5567 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5568 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5569 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5570 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5571
5572 switch(col_format) {
5573 case V_028714_SPI_SHADER_ZERO:
5574 args->enabled_channels = 0; /* writemask */
5575 args->target = V_008DFC_SQ_EXP_NULL;
5576 break;
5577
5578 case V_028714_SPI_SHADER_32_R:
5579 args->enabled_channels = 1;
5580 args->out[0] = values[0];
5581 break;
5582
5583 case V_028714_SPI_SHADER_32_GR:
5584 args->enabled_channels = 0x3;
5585 args->out[0] = values[0];
5586 args->out[1] = values[1];
5587 break;
5588
5589 case V_028714_SPI_SHADER_32_AR:
5590 args->enabled_channels = 0x9;
5591 args->out[0] = values[0];
5592 args->out[3] = values[3];
5593 break;
5594
5595 case V_028714_SPI_SHADER_FP16_ABGR:
5596 args->compr = 1;
5597
5598 for (unsigned chan = 0; chan < 2; chan++) {
5599 LLVMValueRef pack_args[2] = {
5600 values[2 * chan],
5601 values[2 * chan + 1]
5602 };
5603 LLVMValueRef packed;
5604
5605 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5606 args->out[chan] = packed;
5607 }
5608 break;
5609
5610 case V_028714_SPI_SHADER_UNORM16_ABGR:
5611 for (unsigned chan = 0; chan < 4; chan++) {
5612 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5613 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5614 LLVMConstReal(ctx->f32, 65535), "");
5615 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5616 LLVMConstReal(ctx->f32, 0.5), "");
5617 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5618 ctx->i32, "");
5619 }
5620
5621 args->compr = 1;
5622 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5623 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5624 break;
5625
5626 case V_028714_SPI_SHADER_SNORM16_ABGR:
5627 for (unsigned chan = 0; chan < 4; chan++) {
5628 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5629 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5630 LLVMConstReal(ctx->f32, 32767), "");
5631
5632 /* If positive, add 0.5, else add -0.5. */
5633 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5634 LLVMBuildSelect(ctx->builder,
5635 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5636 val[chan], ctx->f32zero, ""),
5637 LLVMConstReal(ctx->f32, 0.5),
5638 LLVMConstReal(ctx->f32, -0.5), ""), "");
5639 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5640 }
5641
5642 args->compr = 1;
5643 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5644 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5645 break;
5646
5647 case V_028714_SPI_SHADER_UINT16_ABGR: {
5648 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5649 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5650 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
5651
5652 for (unsigned chan = 0; chan < 4; chan++) {
5653 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5654 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5655 }
5656
5657 args->compr = 1;
5658 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5659 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5660 break;
5661 }
5662
5663 case V_028714_SPI_SHADER_SINT16_ABGR: {
5664 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5665 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5666 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
5667 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5668 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->i32one;
5669 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
5670
5671 /* Clamp. */
5672 for (unsigned chan = 0; chan < 4; chan++) {
5673 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5674 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5675 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5676 }
5677
5678 args->compr = 1;
5679 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5680 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5681 break;
5682 }
5683
5684 default:
5685 case V_028714_SPI_SHADER_32_ABGR:
5686 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5687 break;
5688 }
5689 } else
5690 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5691
5692 for (unsigned i = 0; i < 4; ++i)
5693 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5694 }
5695
5696 static void
5697 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5698 bool export_prim_id,
5699 struct ac_vs_output_info *outinfo)
5700 {
5701 uint32_t param_count = 0;
5702 unsigned target;
5703 unsigned pos_idx, num_pos_exports = 0;
5704 struct ac_export_args args, pos_args[4] = {};
5705 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5706 int i;
5707
5708 if (ctx->options->key.has_multiview_view_index) {
5709 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5710 if(!*tmp_out) {
5711 for(unsigned i = 0; i < 4; ++i)
5712 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5713 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5714 }
5715
5716 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5717 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5718 }
5719
5720 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5721 sizeof(outinfo->vs_output_param_offset));
5722
5723 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5724 LLVMValueRef slots[8];
5725 unsigned j;
5726
5727 if (outinfo->cull_dist_mask)
5728 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5729
5730 i = VARYING_SLOT_CLIP_DIST0;
5731 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5732 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5733 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5734
5735 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5736 slots[i] = LLVMGetUndef(ctx->f32);
5737
5738 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5739 target = V_008DFC_SQ_EXP_POS + 3;
5740 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5741 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5742 &args, sizeof(args));
5743 }
5744
5745 target = V_008DFC_SQ_EXP_POS + 2;
5746 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5747 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5748 &args, sizeof(args));
5749
5750 }
5751
5752 LLVMValueRef pos_values[4] = {ctx->f32zero, ctx->f32zero, ctx->f32zero, ctx->f32one};
5753 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5754 for (unsigned j = 0; j < 4; j++)
5755 pos_values[j] = LLVMBuildLoad(ctx->builder,
5756 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5757 }
5758 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5759
5760 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5761 outinfo->writes_pointsize = true;
5762 psize_value = LLVMBuildLoad(ctx->builder,
5763 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5764 }
5765
5766 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5767 outinfo->writes_layer = true;
5768 layer_value = LLVMBuildLoad(ctx->builder,
5769 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5770 }
5771
5772 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5773 outinfo->writes_viewport_index = true;
5774 viewport_index_value = LLVMBuildLoad(ctx->builder,
5775 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5776 }
5777
5778 if (outinfo->writes_pointsize ||
5779 outinfo->writes_layer ||
5780 outinfo->writes_viewport_index) {
5781 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5782 (outinfo->writes_layer == true ? 4 : 0));
5783 pos_args[1].valid_mask = 0;
5784 pos_args[1].done = 0;
5785 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5786 pos_args[1].compr = 0;
5787 pos_args[1].out[0] = ctx->f32zero; /* X */
5788 pos_args[1].out[1] = ctx->f32zero; /* Y */
5789 pos_args[1].out[2] = ctx->f32zero; /* Z */
5790 pos_args[1].out[3] = ctx->f32zero; /* W */
5791
5792 if (outinfo->writes_pointsize == true)
5793 pos_args[1].out[0] = psize_value;
5794 if (outinfo->writes_layer == true)
5795 pos_args[1].out[2] = layer_value;
5796 if (outinfo->writes_viewport_index == true) {
5797 if (ctx->options->chip_class >= GFX9) {
5798 /* GFX9 has the layer in out.z[10:0] and the viewport
5799 * index in out.z[19:16].
5800 */
5801 LLVMValueRef v = viewport_index_value;
5802 v = ac_to_integer(&ctx->ac, v);
5803 v = LLVMBuildShl(ctx->builder, v,
5804 LLVMConstInt(ctx->i32, 16, false),
5805 "");
5806 v = LLVMBuildOr(ctx->builder, v,
5807 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5808
5809 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5810 pos_args[1].enabled_channels |= 1 << 2;
5811 } else {
5812 pos_args[1].out[3] = viewport_index_value;
5813 pos_args[1].enabled_channels |= 1 << 3;
5814 }
5815 }
5816 }
5817 for (i = 0; i < 4; i++) {
5818 if (pos_args[i].out[0])
5819 num_pos_exports++;
5820 }
5821
5822 pos_idx = 0;
5823 for (i = 0; i < 4; i++) {
5824 if (!pos_args[i].out[0])
5825 continue;
5826
5827 /* Specify the target we are exporting */
5828 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5829 if (pos_idx == num_pos_exports)
5830 pos_args[i].done = 1;
5831 ac_build_export(&ctx->ac, &pos_args[i]);
5832 }
5833
5834 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5835 LLVMValueRef values[4];
5836 if (!(ctx->output_mask & (1ull << i)))
5837 continue;
5838
5839 for (unsigned j = 0; j < 4; j++)
5840 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5841 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5842
5843 if (i == VARYING_SLOT_LAYER) {
5844 target = V_008DFC_SQ_EXP_PARAM + param_count;
5845 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5846 param_count++;
5847 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5848 target = V_008DFC_SQ_EXP_PARAM + param_count;
5849 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5850 param_count++;
5851 } else if (i >= VARYING_SLOT_VAR0) {
5852 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5853 target = V_008DFC_SQ_EXP_PARAM + param_count;
5854 outinfo->vs_output_param_offset[i] = param_count;
5855 param_count++;
5856 } else
5857 continue;
5858
5859 si_llvm_init_export_args(ctx, values, target, &args);
5860
5861 if (target >= V_008DFC_SQ_EXP_POS &&
5862 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5863 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5864 &args, sizeof(args));
5865 } else {
5866 ac_build_export(&ctx->ac, &args);
5867 }
5868 }
5869
5870 if (export_prim_id) {
5871 LLVMValueRef values[4];
5872 target = V_008DFC_SQ_EXP_PARAM + param_count;
5873 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5874 param_count++;
5875
5876 values[0] = ctx->vs_prim_id;
5877 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5878 ctx->shader_info->vs.vgpr_comp_cnt);
5879 for (unsigned j = 1; j < 4; j++)
5880 values[j] = ctx->f32zero;
5881 si_llvm_init_export_args(ctx, values, target, &args);
5882 ac_build_export(&ctx->ac, &args);
5883 outinfo->export_prim_id = true;
5884 }
5885
5886 outinfo->pos_exports = num_pos_exports;
5887 outinfo->param_exports = param_count;
5888 }
5889
5890 static void
5891 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5892 struct ac_es_output_info *outinfo)
5893 {
5894 int j;
5895 uint64_t max_output_written = 0;
5896 LLVMValueRef lds_base = NULL;
5897
5898 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5899 int param_index;
5900 int length = 4;
5901
5902 if (!(ctx->output_mask & (1ull << i)))
5903 continue;
5904
5905 if (i == VARYING_SLOT_CLIP_DIST0)
5906 length = ctx->num_output_clips + ctx->num_output_culls;
5907
5908 param_index = shader_io_get_unique_index(i);
5909
5910 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5911 }
5912
5913 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5914
5915 if (ctx->ac.chip_class >= GFX9) {
5916 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5917 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5918 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5919 LLVMConstInt(ctx->ac.i32, 24, false),
5920 LLVMConstInt(ctx->ac.i32, 4, false), false);
5921 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5922 LLVMBuildMul(ctx->ac.builder, wave_idx,
5923 LLVMConstInt(ctx->i32, 64, false), ""), "");
5924 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5925 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
5926 }
5927
5928 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5929 LLVMValueRef dw_addr;
5930 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5931 int param_index;
5932 int length = 4;
5933
5934 if (!(ctx->output_mask & (1ull << i)))
5935 continue;
5936
5937 if (i == VARYING_SLOT_CLIP_DIST0)
5938 length = ctx->num_output_clips + ctx->num_output_culls;
5939
5940 param_index = shader_io_get_unique_index(i);
5941
5942 if (lds_base) {
5943 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5944 LLVMConstInt(ctx->i32, param_index * 4, false),
5945 "");
5946 }
5947 for (j = 0; j < length; j++) {
5948 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5949 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5950
5951 if (ctx->ac.chip_class >= GFX9) {
5952 lds_store(ctx, dw_addr,
5953 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5954 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5955 } else {
5956 ac_build_buffer_store_dword(&ctx->ac,
5957 ctx->esgs_ring,
5958 out_val, 1,
5959 NULL, ctx->es2gs_offset,
5960 (4 * param_index + j) * 4,
5961 1, 1, true, true);
5962 }
5963 }
5964 }
5965 }
5966
5967 static void
5968 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5969 {
5970 LLVMValueRef vertex_id = ctx->rel_auto_id;
5971 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5972 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5973 vertex_dw_stride, "");
5974
5975 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5976 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5977 int length = 4;
5978
5979 if (!(ctx->output_mask & (1ull << i)))
5980 continue;
5981
5982 if (i == VARYING_SLOT_CLIP_DIST0)
5983 length = ctx->num_output_clips + ctx->num_output_culls;
5984 int param = shader_io_get_unique_index(i);
5985 mark_tess_output(ctx, false, param);
5986 if (length > 4)
5987 mark_tess_output(ctx, false, param + 1);
5988 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5989 LLVMConstInt(ctx->i32, param * 4, false),
5990 "");
5991 for (unsigned j = 0; j < length; j++) {
5992 lds_store(ctx, dw_addr,
5993 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5994 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5995 }
5996 }
5997 }
5998
5999 struct ac_build_if_state
6000 {
6001 struct nir_to_llvm_context *ctx;
6002 LLVMValueRef condition;
6003 LLVMBasicBlockRef entry_block;
6004 LLVMBasicBlockRef true_block;
6005 LLVMBasicBlockRef false_block;
6006 LLVMBasicBlockRef merge_block;
6007 };
6008
6009 static LLVMBasicBlockRef
6010 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6011 {
6012 LLVMBasicBlockRef current_block;
6013 LLVMBasicBlockRef next_block;
6014 LLVMBasicBlockRef new_block;
6015
6016 /* get current basic block */
6017 current_block = LLVMGetInsertBlock(ctx->builder);
6018
6019 /* chqeck if there's another block after this one */
6020 next_block = LLVMGetNextBasicBlock(current_block);
6021 if (next_block) {
6022 /* insert the new block before the next block */
6023 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6024 }
6025 else {
6026 /* append new block after current block */
6027 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6028 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6029 }
6030 return new_block;
6031 }
6032
6033 static void
6034 ac_nir_build_if(struct ac_build_if_state *ifthen,
6035 struct nir_to_llvm_context *ctx,
6036 LLVMValueRef condition)
6037 {
6038 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6039
6040 memset(ifthen, 0, sizeof *ifthen);
6041 ifthen->ctx = ctx;
6042 ifthen->condition = condition;
6043 ifthen->entry_block = block;
6044
6045 /* create endif/merge basic block for the phi functions */
6046 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6047
6048 /* create/insert true_block before merge_block */
6049 ifthen->true_block =
6050 LLVMInsertBasicBlockInContext(ctx->context,
6051 ifthen->merge_block,
6052 "if-true-block");
6053
6054 /* successive code goes into the true block */
6055 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6056 }
6057
6058 /**
6059 * End a conditional.
6060 */
6061 static void
6062 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6063 {
6064 LLVMBuilderRef builder = ifthen->ctx->builder;
6065
6066 /* Insert branch to the merge block from current block */
6067 LLVMBuildBr(builder, ifthen->merge_block);
6068
6069 /*
6070 * Now patch in the various branch instructions.
6071 */
6072
6073 /* Insert the conditional branch instruction at the end of entry_block */
6074 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6075 if (ifthen->false_block) {
6076 /* we have an else clause */
6077 LLVMBuildCondBr(builder, ifthen->condition,
6078 ifthen->true_block, ifthen->false_block);
6079 }
6080 else {
6081 /* no else clause */
6082 LLVMBuildCondBr(builder, ifthen->condition,
6083 ifthen->true_block, ifthen->merge_block);
6084 }
6085
6086 /* Resume building code at end of the ifthen->merge_block */
6087 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6088 }
6089
6090 static void
6091 write_tess_factors(struct nir_to_llvm_context *ctx)
6092 {
6093 unsigned stride, outer_comps, inner_comps;
6094 struct ac_build_if_state if_ctx, inner_if_ctx;
6095 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6096 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6097 unsigned tess_inner_index, tess_outer_index;
6098 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6099 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6100 int i;
6101 emit_barrier(ctx);
6102
6103 switch (ctx->options->key.tcs.primitive_mode) {
6104 case GL_ISOLINES:
6105 stride = 2;
6106 outer_comps = 2;
6107 inner_comps = 0;
6108 break;
6109 case GL_TRIANGLES:
6110 stride = 4;
6111 outer_comps = 3;
6112 inner_comps = 1;
6113 break;
6114 case GL_QUADS:
6115 stride = 6;
6116 outer_comps = 4;
6117 inner_comps = 2;
6118 break;
6119 default:
6120 return;
6121 }
6122
6123 ac_nir_build_if(&if_ctx, ctx,
6124 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6125 invocation_id, ctx->i32zero, ""));
6126
6127 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6128 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6129
6130 mark_tess_output(ctx, true, tess_inner_index);
6131 mark_tess_output(ctx, true, tess_outer_index);
6132 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6133 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6134 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
6135 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6136 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
6137
6138 for (i = 0; i < 4; i++) {
6139 inner[i] = LLVMGetUndef(ctx->i32);
6140 outer[i] = LLVMGetUndef(ctx->i32);
6141 }
6142
6143 // LINES reverseal
6144 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6145 outer[0] = out[1] = lds_load(ctx, lds_outer);
6146 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6147 LLVMConstInt(ctx->i32, 1, false), "");
6148 outer[1] = out[0] = lds_load(ctx, lds_outer);
6149 } else {
6150 for (i = 0; i < outer_comps; i++) {
6151 outer[i] = out[i] =
6152 lds_load(ctx, lds_outer);
6153 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6154 LLVMConstInt(ctx->i32, 1, false), "");
6155 }
6156 for (i = 0; i < inner_comps; i++) {
6157 inner[i] = out[outer_comps+i] =
6158 lds_load(ctx, lds_inner);
6159 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6160 LLVMConstInt(ctx->i32, 1, false), "");
6161 }
6162 }
6163
6164 /* Convert the outputs to vectors for stores. */
6165 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6166 vec1 = NULL;
6167
6168 if (stride > 4)
6169 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6170
6171
6172 buffer = ctx->hs_ring_tess_factor;
6173 tf_base = ctx->tess_factor_offset;
6174 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6175 LLVMConstInt(ctx->i32, 4 * stride, false), "");
6176 unsigned tf_offset = 0;
6177
6178 if (ctx->options->chip_class <= VI) {
6179 ac_nir_build_if(&inner_if_ctx, ctx,
6180 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6181 rel_patch_id, ctx->i32zero, ""));
6182
6183 /* Store the dynamic HS control word. */
6184 ac_build_buffer_store_dword(&ctx->ac, buffer,
6185 LLVMConstInt(ctx->i32, 0x80000000, false),
6186 1, ctx->i32zero, tf_base,
6187 0, 1, 0, true, false);
6188 tf_offset += 4;
6189
6190 ac_nir_build_endif(&inner_if_ctx);
6191 }
6192
6193 /* Store the tessellation factors. */
6194 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6195 MIN2(stride, 4), byteoffset, tf_base,
6196 tf_offset, 1, 0, true, false);
6197 if (vec1)
6198 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6199 stride - 4, byteoffset, tf_base,
6200 16 + tf_offset, 1, 0, true, false);
6201
6202 //store to offchip for TES to read - only if TES reads them
6203 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6204 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6205 LLVMValueRef tf_inner_offset;
6206 unsigned param_outer, param_inner;
6207
6208 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6209 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6210 LLVMConstInt(ctx->i32, param_outer, 0));
6211
6212 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6213 util_next_power_of_two(outer_comps));
6214
6215 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6216 outer_comps, tf_outer_offset,
6217 ctx->oc_lds, 0, 1, 0, true, false);
6218 if (inner_comps) {
6219 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6220 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6221 LLVMConstInt(ctx->i32, param_inner, 0));
6222
6223 inner_vec = inner_comps == 1 ? inner[0] :
6224 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6225 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6226 inner_comps, tf_inner_offset,
6227 ctx->oc_lds, 0, 1, 0, true, false);
6228 }
6229 }
6230 ac_nir_build_endif(&if_ctx);
6231 }
6232
6233 static void
6234 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6235 {
6236 write_tess_factors(ctx);
6237 }
6238
6239 static bool
6240 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6241 LLVMValueRef *color, unsigned param, bool is_last,
6242 struct ac_export_args *args)
6243 {
6244 /* Export */
6245 si_llvm_init_export_args(ctx, color, param,
6246 args);
6247
6248 if (is_last) {
6249 args->valid_mask = 1; /* whether the EXEC mask is valid */
6250 args->done = 1; /* DONE bit */
6251 } else if (!args->enabled_channels)
6252 return false; /* unnecessary NULL export */
6253
6254 return true;
6255 }
6256
6257 static void
6258 si_export_mrt_z(struct nir_to_llvm_context *ctx,
6259 LLVMValueRef depth, LLVMValueRef stencil,
6260 LLVMValueRef samplemask)
6261 {
6262 struct ac_export_args args;
6263
6264 args.enabled_channels = 0;
6265 args.valid_mask = 1;
6266 args.done = 1;
6267 args.target = V_008DFC_SQ_EXP_MRTZ;
6268 args.compr = false;
6269
6270 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
6271 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
6272 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
6273 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
6274
6275 if (depth) {
6276 args.out[0] = depth;
6277 args.enabled_channels |= 0x1;
6278 }
6279
6280 if (stencil) {
6281 args.out[1] = stencil;
6282 args.enabled_channels |= 0x2;
6283 }
6284
6285 if (samplemask) {
6286 args.out[2] = samplemask;
6287 args.enabled_channels |= 0x4;
6288 }
6289
6290 /* SI (except OLAND and HAINAN) has a bug that it only looks
6291 * at the X writemask component. */
6292 if (ctx->options->chip_class == SI &&
6293 ctx->options->family != CHIP_OLAND &&
6294 ctx->options->family != CHIP_HAINAN)
6295 args.enabled_channels |= 0x1;
6296
6297 ac_build_export(&ctx->ac, &args);
6298 }
6299
6300 static void
6301 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6302 {
6303 unsigned index = 0;
6304 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6305 struct ac_export_args color_args[8];
6306
6307 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6308 LLVMValueRef values[4];
6309
6310 if (!(ctx->output_mask & (1ull << i)))
6311 continue;
6312
6313 if (i == FRAG_RESULT_DEPTH) {
6314 ctx->shader_info->fs.writes_z = true;
6315 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6316 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6317 } else if (i == FRAG_RESULT_STENCIL) {
6318 ctx->shader_info->fs.writes_stencil = true;
6319 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6320 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6321 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6322 ctx->shader_info->fs.writes_sample_mask = true;
6323 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6324 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6325 } else {
6326 bool last = false;
6327 for (unsigned j = 0; j < 4; j++)
6328 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6329 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6330
6331 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6332 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6333
6334 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6335 if (ret)
6336 index++;
6337 }
6338 }
6339
6340 for (unsigned i = 0; i < index; i++)
6341 ac_build_export(&ctx->ac, &color_args[i]);
6342 if (depth || stencil || samplemask)
6343 si_export_mrt_z(ctx, depth, stencil, samplemask);
6344 else if (!index) {
6345 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6346 ac_build_export(&ctx->ac, &color_args[0]);
6347 }
6348
6349 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6350 }
6351
6352 static void
6353 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6354 {
6355 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6356 }
6357
6358 static void
6359 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6360 LLVMValueRef *addrs)
6361 {
6362 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6363
6364 switch (ctx->stage) {
6365 case MESA_SHADER_VERTEX:
6366 if (ctx->options->key.vs.as_ls)
6367 handle_ls_outputs_post(ctx);
6368 else if (ctx->options->key.vs.as_es)
6369 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6370 else
6371 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6372 &ctx->shader_info->vs.outinfo);
6373 break;
6374 case MESA_SHADER_FRAGMENT:
6375 handle_fs_outputs_post(ctx);
6376 break;
6377 case MESA_SHADER_GEOMETRY:
6378 emit_gs_epilogue(ctx);
6379 break;
6380 case MESA_SHADER_TESS_CTRL:
6381 handle_tcs_outputs_post(ctx);
6382 break;
6383 case MESA_SHADER_TESS_EVAL:
6384 if (ctx->options->key.tes.as_es)
6385 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6386 else
6387 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6388 &ctx->shader_info->tes.outinfo);
6389 break;
6390 default:
6391 break;
6392 }
6393 }
6394
6395 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6396 {
6397 LLVMPassManagerRef passmgr;
6398 /* Create the pass manager */
6399 passmgr = LLVMCreateFunctionPassManagerForModule(
6400 ctx->module);
6401
6402 /* This pass should eliminate all the load and store instructions */
6403 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6404
6405 /* Add some optimization passes */
6406 LLVMAddScalarReplAggregatesPass(passmgr);
6407 LLVMAddLICMPass(passmgr);
6408 LLVMAddAggressiveDCEPass(passmgr);
6409 LLVMAddCFGSimplificationPass(passmgr);
6410 LLVMAddInstructionCombiningPass(passmgr);
6411
6412 /* Run the pass */
6413 LLVMInitializeFunctionPassManager(passmgr);
6414 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6415 LLVMFinalizeFunctionPassManager(passmgr);
6416
6417 LLVMDisposeBuilder(ctx->builder);
6418 LLVMDisposePassManager(passmgr);
6419 }
6420
6421 static void
6422 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6423 {
6424 struct ac_vs_output_info *outinfo;
6425
6426 switch (ctx->stage) {
6427 case MESA_SHADER_FRAGMENT:
6428 case MESA_SHADER_COMPUTE:
6429 case MESA_SHADER_TESS_CTRL:
6430 case MESA_SHADER_GEOMETRY:
6431 return;
6432 case MESA_SHADER_VERTEX:
6433 if (ctx->options->key.vs.as_ls ||
6434 ctx->options->key.vs.as_es)
6435 return;
6436 outinfo = &ctx->shader_info->vs.outinfo;
6437 break;
6438 case MESA_SHADER_TESS_EVAL:
6439 if (ctx->options->key.vs.as_es)
6440 return;
6441 outinfo = &ctx->shader_info->tes.outinfo;
6442 break;
6443 default:
6444 unreachable("Unhandled shader type");
6445 }
6446
6447 ac_optimize_vs_outputs(&ctx->ac,
6448 ctx->main_function,
6449 outinfo->vs_output_param_offset,
6450 VARYING_SLOT_MAX,
6451 &outinfo->param_exports);
6452 }
6453
6454 static void
6455 ac_setup_rings(struct nir_to_llvm_context *ctx)
6456 {
6457 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6458 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6459 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
6460 }
6461
6462 if (ctx->is_gs_copy_shader) {
6463 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
6464 }
6465 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6466 LLVMValueRef tmp;
6467 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
6468 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
6469
6470 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6471
6472 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
6473 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
6474 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6475 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
6476 }
6477
6478 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6479 ctx->stage == MESA_SHADER_TESS_EVAL) {
6480 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6481 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6482 }
6483 }
6484
6485 static unsigned
6486 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6487 const struct nir_shader *nir)
6488 {
6489 switch (nir->info.stage) {
6490 case MESA_SHADER_TESS_CTRL:
6491 return chip_class >= CIK ? 128 : 64;
6492 case MESA_SHADER_GEOMETRY:
6493 return chip_class >= GFX9 ? 128 : 64;
6494 case MESA_SHADER_COMPUTE:
6495 break;
6496 default:
6497 return 0;
6498 }
6499
6500 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6501 nir->info.cs.local_size[1] *
6502 nir->info.cs.local_size[2];
6503 return max_workgroup_size;
6504 }
6505
6506 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6507 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6508 {
6509 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6510 LLVMConstInt(ctx->ac.i32, 8, false),
6511 LLVMConstInt(ctx->ac.i32, 8, false), false);
6512 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6513 LLVMConstInt(ctx->ac.i32, 0, false), "");
6514 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6515 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6516 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6517 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6518 }
6519
6520 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6521 {
6522 for(int i = 5; i >= 0; --i) {
6523 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6524 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6525 LLVMConstInt(ctx->ac.i32, 16, false), false);
6526 }
6527
6528 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6529 LLVMConstInt(ctx->ac.i32, 16, false),
6530 LLVMConstInt(ctx->ac.i32, 8, false), false);
6531 }
6532
6533 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6534 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6535 {
6536 struct ac_nir_context ctx = {};
6537 struct nir_function *func;
6538
6539 ctx.ac = *ac;
6540 ctx.abi = abi;
6541
6542 ctx.nctx = nctx;
6543 if (nctx)
6544 nctx->nir = &ctx;
6545
6546 ctx.stage = nir->info.stage;
6547
6548 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6549
6550 nir_foreach_variable(variable, &nir->outputs)
6551 handle_shader_output_decl(&ctx, nir, variable);
6552
6553 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6554 _mesa_key_pointer_equal);
6555 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6556 _mesa_key_pointer_equal);
6557 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6558 _mesa_key_pointer_equal);
6559
6560 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6561
6562 setup_locals(&ctx, func);
6563
6564 if (nir->info.stage == MESA_SHADER_COMPUTE)
6565 setup_shared(&ctx, nir);
6566
6567 visit_cf_list(&ctx, &func->impl->body);
6568 phi_post_pass(&ctx);
6569
6570 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6571 ctx.outputs);
6572
6573 free(ctx.locals);
6574 ralloc_free(ctx.defs);
6575 ralloc_free(ctx.phis);
6576 ralloc_free(ctx.vars);
6577
6578 if (nctx)
6579 nctx->nir = NULL;
6580 }
6581
6582 static
6583 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6584 struct nir_shader *const *shaders,
6585 int shader_count,
6586 struct ac_shader_variant_info *shader_info,
6587 const struct ac_nir_compiler_options *options)
6588 {
6589 struct nir_to_llvm_context ctx = {0};
6590 unsigned i;
6591 ctx.options = options;
6592 ctx.shader_info = shader_info;
6593 ctx.context = LLVMContextCreate();
6594 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6595
6596 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6597 ctx.ac.module = ctx.module;
6598 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6599
6600 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6601 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6602 LLVMSetDataLayout(ctx.module, data_layout_str);
6603 LLVMDisposeTargetData(data_layout);
6604 LLVMDisposeMessage(data_layout_str);
6605
6606 setup_types(&ctx);
6607 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6608 ctx.ac.builder = ctx.builder;
6609
6610 memset(shader_info, 0, sizeof(*shader_info));
6611
6612 for(int i = 0; i < shader_count; ++i)
6613 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6614
6615 for (i = 0; i < AC_UD_MAX_SETS; i++)
6616 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6617 for (i = 0; i < AC_UD_MAX_UD; i++)
6618 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6619
6620 ctx.max_workgroup_size = 0;
6621 for (int i = 0; i < shader_count; ++i) {
6622 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6623 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6624 shaders[i]));
6625 }
6626
6627 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6628 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6629
6630 ctx.abi.inputs = &ctx.inputs[0];
6631 ctx.abi.emit_outputs = handle_shader_outputs_post;
6632 ctx.abi.load_ssbo = radv_load_ssbo;
6633 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6634 ctx.abi.clamp_shadow_reference = false;
6635
6636 if (shader_count >= 2)
6637 ac_init_exec_full_mask(&ctx.ac);
6638
6639 if (ctx.ac.chip_class == GFX9 &&
6640 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6641 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6642
6643 for(int i = 0; i < shader_count; ++i) {
6644 ctx.stage = shaders[i]->info.stage;
6645 ctx.output_mask = 0;
6646 ctx.tess_outputs_written = 0;
6647 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6648 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6649
6650 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6651 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.i32, "gs_next_vertex");
6652
6653 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6654 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6655 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6656 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6657 if (shader_info->info.vs.needs_instance_id) {
6658 ctx.shader_info->vs.vgpr_comp_cnt =
6659 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6660 }
6661 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6662 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6663 }
6664
6665 if (i)
6666 emit_barrier(&ctx);
6667
6668 ac_setup_rings(&ctx);
6669
6670 LLVMBasicBlockRef merge_block;
6671 if (shader_count >= 2) {
6672 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6673 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6674 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6675
6676 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6677 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6678 LLVMConstInt(ctx.ac.i32, 8, false), false);
6679 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6680 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6681 thread_id, count, "");
6682 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6683
6684 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6685 }
6686
6687 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6688 handle_fs_inputs(&ctx, shaders[i]);
6689 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6690 handle_vs_inputs(&ctx, shaders[i]);
6691 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6692 prepare_gs_input_vgprs(&ctx);
6693
6694 nir_foreach_variable(variable, &shaders[i]->outputs)
6695 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6696
6697 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6698
6699 if (shader_count >= 2) {
6700 LLVMBuildBr(ctx.ac.builder, merge_block);
6701 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6702 }
6703
6704 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6705 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6706 shaders[i]->info.cull_distance_array_size > 4;
6707 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6708 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6709 shaders[i]->info.gs.vertices_out;
6710 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6711 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6712 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6713 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6714 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6715 }
6716 }
6717
6718 LLVMBuildRetVoid(ctx.builder);
6719
6720 ac_llvm_finalize_module(&ctx);
6721
6722 if (shader_count == 1)
6723 ac_nir_eliminate_const_vs_outputs(&ctx);
6724
6725 return ctx.module;
6726 }
6727
6728 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6729 {
6730 unsigned *retval = (unsigned *)context;
6731 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6732 char *description = LLVMGetDiagInfoDescription(di);
6733
6734 if (severity == LLVMDSError) {
6735 *retval = 1;
6736 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6737 description);
6738 }
6739
6740 LLVMDisposeMessage(description);
6741 }
6742
6743 static unsigned ac_llvm_compile(LLVMModuleRef M,
6744 struct ac_shader_binary *binary,
6745 LLVMTargetMachineRef tm)
6746 {
6747 unsigned retval = 0;
6748 char *err;
6749 LLVMContextRef llvm_ctx;
6750 LLVMMemoryBufferRef out_buffer;
6751 unsigned buffer_size;
6752 const char *buffer_data;
6753 LLVMBool mem_err;
6754
6755 /* Setup Diagnostic Handler*/
6756 llvm_ctx = LLVMGetModuleContext(M);
6757
6758 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6759 &retval);
6760
6761 /* Compile IR*/
6762 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6763 &err, &out_buffer);
6764
6765 /* Process Errors/Warnings */
6766 if (mem_err) {
6767 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6768 free(err);
6769 retval = 1;
6770 goto out;
6771 }
6772
6773 /* Extract Shader Code*/
6774 buffer_size = LLVMGetBufferSize(out_buffer);
6775 buffer_data = LLVMGetBufferStart(out_buffer);
6776
6777 ac_elf_read(buffer_data, buffer_size, binary);
6778
6779 /* Clean up */
6780 LLVMDisposeMemoryBuffer(out_buffer);
6781
6782 out:
6783 return retval;
6784 }
6785
6786 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6787 LLVMModuleRef llvm_module,
6788 struct ac_shader_binary *binary,
6789 struct ac_shader_config *config,
6790 struct ac_shader_variant_info *shader_info,
6791 gl_shader_stage stage,
6792 bool dump_shader, bool supports_spill)
6793 {
6794 if (dump_shader)
6795 ac_dump_module(llvm_module);
6796
6797 memset(binary, 0, sizeof(*binary));
6798 int v = ac_llvm_compile(llvm_module, binary, tm);
6799 if (v) {
6800 fprintf(stderr, "compile failed\n");
6801 }
6802
6803 if (dump_shader)
6804 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6805
6806 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6807
6808 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6809 LLVMDisposeModule(llvm_module);
6810 LLVMContextDispose(ctx);
6811
6812 if (stage == MESA_SHADER_FRAGMENT) {
6813 shader_info->num_input_vgprs = 0;
6814 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6815 shader_info->num_input_vgprs += 2;
6816 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6817 shader_info->num_input_vgprs += 2;
6818 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6819 shader_info->num_input_vgprs += 2;
6820 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6821 shader_info->num_input_vgprs += 3;
6822 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6823 shader_info->num_input_vgprs += 2;
6824 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6825 shader_info->num_input_vgprs += 2;
6826 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6827 shader_info->num_input_vgprs += 2;
6828 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6829 shader_info->num_input_vgprs += 1;
6830 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6831 shader_info->num_input_vgprs += 1;
6832 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6833 shader_info->num_input_vgprs += 1;
6834 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6835 shader_info->num_input_vgprs += 1;
6836 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6837 shader_info->num_input_vgprs += 1;
6838 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6839 shader_info->num_input_vgprs += 1;
6840 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6841 shader_info->num_input_vgprs += 1;
6842 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6843 shader_info->num_input_vgprs += 1;
6844 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6845 shader_info->num_input_vgprs += 1;
6846 }
6847 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6848
6849 /* +3 for scratch wave offset and VCC */
6850 config->num_sgprs = MAX2(config->num_sgprs,
6851 shader_info->num_input_sgprs + 3);
6852 }
6853
6854 static void
6855 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6856 {
6857 switch (nir->info.stage) {
6858 case MESA_SHADER_COMPUTE:
6859 for (int i = 0; i < 3; ++i)
6860 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6861 break;
6862 case MESA_SHADER_FRAGMENT:
6863 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6864 break;
6865 case MESA_SHADER_GEOMETRY:
6866 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6867 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6868 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6869 shader_info->gs.invocations = nir->info.gs.invocations;
6870 break;
6871 case MESA_SHADER_TESS_EVAL:
6872 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6873 shader_info->tes.spacing = nir->info.tess.spacing;
6874 shader_info->tes.ccw = nir->info.tess.ccw;
6875 shader_info->tes.point_mode = nir->info.tess.point_mode;
6876 shader_info->tes.as_es = options->key.tes.as_es;
6877 break;
6878 case MESA_SHADER_TESS_CTRL:
6879 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6880 break;
6881 case MESA_SHADER_VERTEX:
6882 shader_info->vs.as_es = options->key.vs.as_es;
6883 shader_info->vs.as_ls = options->key.vs.as_ls;
6884 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6885 if (options->key.vs.as_ls)
6886 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6887 break;
6888 default:
6889 break;
6890 }
6891 }
6892
6893 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6894 struct ac_shader_binary *binary,
6895 struct ac_shader_config *config,
6896 struct ac_shader_variant_info *shader_info,
6897 struct nir_shader *const *nir,
6898 int nir_count,
6899 const struct ac_nir_compiler_options *options,
6900 bool dump_shader)
6901 {
6902
6903 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6904 options);
6905
6906 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6907 for (int i = 0; i < nir_count; ++i)
6908 ac_fill_shader_info(shader_info, nir[i], options);
6909 }
6910
6911 static void
6912 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6913 {
6914 LLVMValueRef args[9];
6915 args[0] = ctx->gsvs_ring;
6916 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6917 args[3] = ctx->i32zero;
6918 args[4] = ctx->i32one; /* OFFEN */
6919 args[5] = ctx->i32zero; /* IDXEN */
6920 args[6] = ctx->i32one; /* GLC */
6921 args[7] = ctx->i32one; /* SLC */
6922 args[8] = ctx->i32zero; /* TFE */
6923
6924 int idx = 0;
6925
6926 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6927 int length = 4;
6928 int slot = idx;
6929 int slot_inc = 1;
6930 if (!(ctx->output_mask & (1ull << i)))
6931 continue;
6932
6933 if (i == VARYING_SLOT_CLIP_DIST0) {
6934 /* unpack clip and cull from a single set of slots */
6935 length = ctx->num_output_clips + ctx->num_output_culls;
6936 if (length > 4)
6937 slot_inc = 2;
6938 }
6939
6940 for (unsigned j = 0; j < length; j++) {
6941 LLVMValueRef value;
6942 args[2] = LLVMConstInt(ctx->i32,
6943 (slot * 4 + j) *
6944 ctx->gs_max_out_vertices * 16 * 4, false);
6945
6946 value = ac_build_intrinsic(&ctx->ac,
6947 "llvm.SI.buffer.load.dword.i32.i32",
6948 ctx->i32, args, 9,
6949 AC_FUNC_ATTR_READONLY |
6950 AC_FUNC_ATTR_LEGACY);
6951
6952 LLVMBuildStore(ctx->builder,
6953 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6954 }
6955 idx += slot_inc;
6956 }
6957 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6958 }
6959
6960 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6961 struct nir_shader *geom_shader,
6962 struct ac_shader_binary *binary,
6963 struct ac_shader_config *config,
6964 struct ac_shader_variant_info *shader_info,
6965 const struct ac_nir_compiler_options *options,
6966 bool dump_shader)
6967 {
6968 struct nir_to_llvm_context ctx = {0};
6969 ctx.context = LLVMContextCreate();
6970 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6971 ctx.options = options;
6972 ctx.shader_info = shader_info;
6973
6974 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6975 ctx.ac.module = ctx.module;
6976
6977 ctx.is_gs_copy_shader = true;
6978 LLVMSetTarget(ctx.module, "amdgcn--");
6979 setup_types(&ctx);
6980
6981 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6982 ctx.ac.builder = ctx.builder;
6983 ctx.stage = MESA_SHADER_VERTEX;
6984
6985 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
6986
6987 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6988 ac_setup_rings(&ctx);
6989
6990 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6991 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6992
6993 struct ac_nir_context nir_ctx = {};
6994 nir_ctx.ac = ctx.ac;
6995 nir_ctx.abi = &ctx.abi;
6996
6997 nir_ctx.nctx = &ctx;
6998 ctx.nir = &nir_ctx;
6999
7000 nir_foreach_variable(variable, &geom_shader->outputs) {
7001 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7002 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7003 }
7004
7005 ac_gs_copy_shader_emit(&ctx);
7006
7007 ctx.nir = NULL;
7008
7009 LLVMBuildRetVoid(ctx.builder);
7010
7011 ac_llvm_finalize_module(&ctx);
7012
7013 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7014 MESA_SHADER_VERTEX,
7015 dump_shader, options->supports_spill);
7016 }