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ac/nir: pass ac_nir_context to emit_ddxy
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 };
43
44 #define CONST_ADDR_SPACE 2
45 #define LOCAL_ADDR_SPACE 3
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct nir_to_llvm_context;
51
52 struct ac_nir_context {
53 struct ac_llvm_context ac;
54 struct ac_shader_abi *abi;
55
56 gl_shader_stage stage;
57
58 struct hash_table *defs;
59 struct hash_table *phis;
60 struct hash_table *vars;
61
62 LLVMValueRef main_function;
63 LLVMBasicBlockRef continue_block;
64 LLVMBasicBlockRef break_block;
65
66 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
67
68 int num_locals;
69 LLVMValueRef *locals;
70
71 LLVMValueRef ddxy_lds;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef num_work_groups;
96 LLVMValueRef workgroup_ids;
97 LLVMValueRef local_invocation_ids;
98 LLVMValueRef tg_size;
99
100 LLVMValueRef vertex_buffers;
101 LLVMValueRef rel_auto_id;
102 LLVMValueRef vs_prim_id;
103 LLVMValueRef ls_out_layout;
104 LLVMValueRef es2gs_offset;
105
106 LLVMValueRef tcs_offchip_layout;
107 LLVMValueRef tcs_out_offsets;
108 LLVMValueRef tcs_out_layout;
109 LLVMValueRef tcs_in_layout;
110 LLVMValueRef oc_lds;
111 LLVMValueRef tess_factor_offset;
112 LLVMValueRef tcs_patch_id;
113 LLVMValueRef tcs_rel_ids;
114 LLVMValueRef tes_rel_patch_id;
115 LLVMValueRef tes_patch_id;
116 LLVMValueRef tes_u;
117 LLVMValueRef tes_v;
118
119 LLVMValueRef gsvs_ring_stride;
120 LLVMValueRef gsvs_num_entries;
121 LLVMValueRef gs2vs_offset;
122 LLVMValueRef gs_wave_id;
123 LLVMValueRef gs_vtx_offset[6];
124 LLVMValueRef gs_prim_id, gs_invocation_id;
125
126 LLVMValueRef esgs_ring;
127 LLVMValueRef gsvs_ring;
128 LLVMValueRef hs_ring_tess_offchip;
129 LLVMValueRef hs_ring_tess_factor;
130
131 LLVMValueRef prim_mask;
132 LLVMValueRef sample_pos_offset;
133 LLVMValueRef persp_sample, persp_center, persp_centroid;
134 LLVMValueRef linear_sample, linear_center, linear_centroid;
135 LLVMValueRef front_face;
136 LLVMValueRef ancillary;
137 LLVMValueRef sample_coverage;
138 LLVMValueRef frag_pos[4];
139
140 LLVMTypeRef i1;
141 LLVMTypeRef i8;
142 LLVMTypeRef i16;
143 LLVMTypeRef i32;
144 LLVMTypeRef i64;
145 LLVMTypeRef v2i32;
146 LLVMTypeRef v3i32;
147 LLVMTypeRef v4i32;
148 LLVMTypeRef v8i32;
149 LLVMTypeRef f64;
150 LLVMTypeRef f32;
151 LLVMTypeRef f16;
152 LLVMTypeRef v2f32;
153 LLVMTypeRef v4f32;
154 LLVMTypeRef voidt;
155
156 LLVMValueRef i1true;
157 LLVMValueRef i1false;
158 LLVMValueRef i32zero;
159 LLVMValueRef i32one;
160 LLVMValueRef f32zero;
161 LLVMValueRef f32one;
162 LLVMValueRef v4f32empty;
163
164 unsigned uniform_md_kind;
165 LLVMValueRef empty_md;
166 gl_shader_stage stage;
167
168 LLVMValueRef lds;
169 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
170
171 uint64_t input_mask;
172 uint64_t output_mask;
173 uint8_t num_output_clips;
174 uint8_t num_output_culls;
175
176 bool is_gs_copy_shader;
177 LLVMValueRef gs_next_vertex;
178 unsigned gs_max_out_vertices;
179
180 unsigned tes_primitive_mode;
181 uint64_t tess_outputs_written;
182 uint64_t tess_patch_outputs_written;
183 };
184
185 static inline struct nir_to_llvm_context *
186 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
187 {
188 struct nir_to_llvm_context *ctx = NULL;
189 return container_of(abi, ctx, abi);
190 }
191
192 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
193 const nir_deref_var *deref,
194 enum ac_descriptor_type desc_type,
195 bool image, bool write);
196
197 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
198 {
199 return (index * 4) + chan;
200 }
201
202 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
203 {
204 /* handle patch indices separate */
205 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
206 return 0;
207 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
208 return 1;
209 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
210 return 2 + (slot - VARYING_SLOT_PATCH0);
211
212 if (slot == VARYING_SLOT_POS)
213 return 0;
214 if (slot == VARYING_SLOT_PSIZ)
215 return 1;
216 if (slot == VARYING_SLOT_CLIP_DIST0)
217 return 2;
218 /* 3 is reserved for clip dist as well */
219 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
220 return 4 + (slot - VARYING_SLOT_VAR0);
221 unreachable("illegal slot in get unique index\n");
222 }
223
224 static unsigned llvm_get_type_size(LLVMTypeRef type)
225 {
226 LLVMTypeKind kind = LLVMGetTypeKind(type);
227
228 switch (kind) {
229 case LLVMIntegerTypeKind:
230 return LLVMGetIntTypeWidth(type) / 8;
231 case LLVMFloatTypeKind:
232 return 4;
233 case LLVMPointerTypeKind:
234 return 8;
235 case LLVMVectorTypeKind:
236 return LLVMGetVectorSize(type) *
237 llvm_get_type_size(LLVMGetElementType(type));
238 default:
239 assert(0);
240 return 0;
241 }
242 }
243
244 static void set_llvm_calling_convention(LLVMValueRef func,
245 gl_shader_stage stage)
246 {
247 enum radeon_llvm_calling_convention calling_conv;
248
249 switch (stage) {
250 case MESA_SHADER_VERTEX:
251 case MESA_SHADER_TESS_CTRL:
252 case MESA_SHADER_TESS_EVAL:
253 calling_conv = RADEON_LLVM_AMDGPU_VS;
254 break;
255 case MESA_SHADER_GEOMETRY:
256 calling_conv = RADEON_LLVM_AMDGPU_GS;
257 break;
258 case MESA_SHADER_FRAGMENT:
259 calling_conv = RADEON_LLVM_AMDGPU_PS;
260 break;
261 case MESA_SHADER_COMPUTE:
262 calling_conv = RADEON_LLVM_AMDGPU_CS;
263 break;
264 default:
265 unreachable("Unhandle shader type");
266 }
267
268 LLVMSetFunctionCallConv(func, calling_conv);
269 }
270
271 #define MAX_ARGS 23
272 struct arg_info {
273 LLVMTypeRef types[MAX_ARGS];
274 LLVMValueRef *assign[MAX_ARGS];
275 unsigned array_params_mask;
276 uint8_t count;
277 uint8_t user_sgpr_count;
278 uint8_t sgpr_count;
279 uint8_t num_user_sgprs_used;
280 uint8_t num_sgprs_used;
281 uint8_t num_vgprs_used;
282 };
283
284 static inline void
285 add_argument(struct arg_info *info,
286 LLVMTypeRef type, LLVMValueRef *param_ptr)
287 {
288 assert(info->count < MAX_ARGS);
289 info->assign[info->count] = param_ptr;
290 info->types[info->count] = type;
291 info->count++;
292 }
293
294 static inline void
295 add_sgpr_argument(struct arg_info *info,
296 LLVMTypeRef type, LLVMValueRef *param_ptr)
297 {
298 add_argument(info, type, param_ptr);
299 info->num_sgprs_used += llvm_get_type_size(type) / 4;
300 info->sgpr_count++;
301 }
302
303 static inline void
304 add_user_sgpr_argument(struct arg_info *info,
305 LLVMTypeRef type,
306 LLVMValueRef *param_ptr)
307 {
308 add_sgpr_argument(info, type, param_ptr);
309 info->num_user_sgprs_used += llvm_get_type_size(type) / 4;
310 info->user_sgpr_count++;
311 }
312
313 static inline void
314 add_vgpr_argument(struct arg_info *info,
315 LLVMTypeRef type,
316 LLVMValueRef *param_ptr)
317 {
318 add_argument(info, type, param_ptr);
319 info->num_vgprs_used += llvm_get_type_size(type) / 4;
320 }
321
322 static inline void
323 add_user_sgpr_array_argument(struct arg_info *info,
324 LLVMTypeRef type,
325 LLVMValueRef *param_ptr)
326 {
327 info->array_params_mask |= (1 << info->count);
328 add_user_sgpr_argument(info, type, param_ptr);
329 }
330
331 static void assign_arguments(LLVMValueRef main_function,
332 struct arg_info *info)
333 {
334 unsigned i;
335 for (i = 0; i < info->count; i++) {
336 if (info->assign[i])
337 *info->assign[i] = LLVMGetParam(main_function, i);
338 }
339 }
340
341 static LLVMValueRef
342 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
343 LLVMBuilderRef builder, LLVMTypeRef *return_types,
344 unsigned num_return_elems,
345 struct arg_info *args,
346 unsigned max_workgroup_size,
347 bool unsafe_math)
348 {
349 LLVMTypeRef main_function_type, ret_type;
350 LLVMBasicBlockRef main_function_body;
351
352 if (num_return_elems)
353 ret_type = LLVMStructTypeInContext(ctx, return_types,
354 num_return_elems, true);
355 else
356 ret_type = LLVMVoidTypeInContext(ctx);
357
358 /* Setup the function */
359 main_function_type =
360 LLVMFunctionType(ret_type, args->types, args->count, 0);
361 LLVMValueRef main_function =
362 LLVMAddFunction(module, "main", main_function_type);
363 main_function_body =
364 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
365 LLVMPositionBuilderAtEnd(builder, main_function_body);
366
367 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
368 for (unsigned i = 0; i < args->sgpr_count; ++i) {
369 if (args->array_params_mask & (1 << i)) {
370 LLVMValueRef P = LLVMGetParam(main_function, i);
371 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
372 ac_add_attr_dereferenceable(P, UINT64_MAX);
373 }
374 else {
375 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
376 }
377 }
378
379 if (max_workgroup_size) {
380 ac_llvm_add_target_dep_function_attr(main_function,
381 "amdgpu-max-work-group-size",
382 max_workgroup_size);
383 }
384 if (unsafe_math) {
385 /* These were copied from some LLVM test. */
386 LLVMAddTargetDependentFunctionAttr(main_function,
387 "less-precise-fpmad",
388 "true");
389 LLVMAddTargetDependentFunctionAttr(main_function,
390 "no-infs-fp-math",
391 "true");
392 LLVMAddTargetDependentFunctionAttr(main_function,
393 "no-nans-fp-math",
394 "true");
395 LLVMAddTargetDependentFunctionAttr(main_function,
396 "unsafe-fp-math",
397 "true");
398 }
399 return main_function;
400 }
401
402 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
403 {
404 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
405 CONST_ADDR_SPACE);
406 }
407
408 static LLVMTypeRef to_integer_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
409 {
410 if (t == ctx->f16 || t == ctx->i16)
411 return ctx->i16;
412 else if (t == ctx->f32 || t == ctx->i32)
413 return ctx->i32;
414 else if (t == ctx->f64 || t == ctx->i64)
415 return ctx->i64;
416 else
417 unreachable("Unhandled integer size");
418 }
419
420 static LLVMTypeRef to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
421 {
422 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
423 LLVMTypeRef elem_type = LLVMGetElementType(t);
424 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
425 LLVMGetVectorSize(t));
426 }
427 return to_integer_type_scalar(ctx, t);
428 }
429
430 static LLVMValueRef to_integer(struct ac_llvm_context *ctx, LLVMValueRef v)
431 {
432 LLVMTypeRef type = LLVMTypeOf(v);
433 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
434 }
435
436 static LLVMTypeRef to_float_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
437 {
438 if (t == ctx->i16 || t == ctx->f16)
439 return ctx->f16;
440 else if (t == ctx->i32 || t == ctx->f32)
441 return ctx->f32;
442 else if (t == ctx->i64 || t == ctx->f64)
443 return ctx->f64;
444 else
445 unreachable("Unhandled float size");
446 }
447
448 static LLVMTypeRef to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
449 {
450 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
451 LLVMTypeRef elem_type = LLVMGetElementType(t);
452 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
453 LLVMGetVectorSize(t));
454 }
455 return to_float_type_scalar(ctx, t);
456 }
457
458 static LLVMValueRef to_float(struct ac_llvm_context *ctx, LLVMValueRef v)
459 {
460 LLVMTypeRef type = LLVMTypeOf(v);
461 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
462 }
463
464 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
465 {
466 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
467 type = LLVMGetElementType(type);
468
469 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
470 return LLVMGetIntTypeWidth(type);
471
472 if (type == ctx->f16)
473 return 16;
474 if (type == ctx->f32)
475 return 32;
476 if (type == ctx->f64)
477 return 64;
478
479 unreachable("Unhandled type kind in get_elem_bits");
480 }
481
482 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
483 LLVMValueRef param, unsigned rshift,
484 unsigned bitwidth)
485 {
486 LLVMValueRef value = param;
487 if (rshift)
488 value = LLVMBuildLShr(ctx->builder, value,
489 LLVMConstInt(ctx->i32, rshift, false), "");
490
491 if (rshift + bitwidth < 32) {
492 unsigned mask = (1 << bitwidth) - 1;
493 value = LLVMBuildAnd(ctx->builder, value,
494 LLVMConstInt(ctx->i32, mask, false), "");
495 }
496 return value;
497 }
498
499 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
500 {
501 switch (ctx->stage) {
502 case MESA_SHADER_TESS_CTRL:
503 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
504 case MESA_SHADER_TESS_EVAL:
505 return ctx->tes_rel_patch_id;
506 break;
507 default:
508 unreachable("Illegal stage");
509 }
510 }
511
512 /* Tessellation shaders pass outputs to the next shader using LDS.
513 *
514 * LS outputs = TCS inputs
515 * TCS outputs = TES inputs
516 *
517 * The LDS layout is:
518 * - TCS inputs for patch 0
519 * - TCS inputs for patch 1
520 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
521 * - ...
522 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
523 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
524 * - TCS outputs for patch 1
525 * - Per-patch TCS outputs for patch 1
526 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
527 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
528 * - ...
529 *
530 * All three shaders VS(LS), TCS, TES share the same LDS space.
531 */
532 static LLVMValueRef
533 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
534 {
535 if (ctx->stage == MESA_SHADER_VERTEX)
536 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
537 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
538 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
539 else {
540 assert(0);
541 return NULL;
542 }
543 }
544
545 static LLVMValueRef
546 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
547 {
548 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
549 }
550
551 static LLVMValueRef
552 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
553 {
554 return LLVMBuildMul(ctx->builder,
555 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
556 LLVMConstInt(ctx->i32, 4, false), "");
557 }
558
559 static LLVMValueRef
560 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
561 {
562 return LLVMBuildMul(ctx->builder,
563 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
564 LLVMConstInt(ctx->i32, 4, false), "");
565 }
566
567 static LLVMValueRef
568 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
569 {
570 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
571 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
572
573 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
574 }
575
576 static LLVMValueRef
577 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
578 {
579 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
580 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
581 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
582
583 return LLVMBuildAdd(ctx->builder, patch0_offset,
584 LLVMBuildMul(ctx->builder, patch_stride,
585 rel_patch_id, ""),
586 "");
587 }
588
589 static LLVMValueRef
590 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
591 {
592 LLVMValueRef patch0_patch_data_offset =
593 get_tcs_out_patch0_patch_data_offset(ctx);
594 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
595 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
596
597 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
598 LLVMBuildMul(ctx->builder, patch_stride,
599 rel_patch_id, ""),
600 "");
601 }
602
603 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
604 {
605 ud_info->sgpr_idx = *sgpr_idx;
606 ud_info->num_sgprs = num_sgprs;
607 ud_info->indirect = false;
608 ud_info->indirect_offset = 0;
609 *sgpr_idx += num_sgprs;
610 }
611
612 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
613 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
614 {
615 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
616 }
617
618
619 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
620 uint32_t indirect_offset)
621 {
622 ud_info->sgpr_idx = sgpr_idx;
623 ud_info->num_sgprs = num_sgprs;
624 ud_info->indirect = true;
625 ud_info->indirect_offset = indirect_offset;
626 }
627
628 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
629 {
630 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
631 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
632 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
633 "tess_lds");
634 }
635
636 struct user_sgpr_info {
637 bool need_ring_offsets;
638 uint8_t sgpr_count;
639 bool indirect_all_descriptor_sets;
640 };
641
642 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
643 struct user_sgpr_info *user_sgpr_info)
644 {
645 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
646
647 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
648 if (ctx->stage == MESA_SHADER_GEOMETRY ||
649 ctx->stage == MESA_SHADER_VERTEX ||
650 ctx->stage == MESA_SHADER_TESS_CTRL ||
651 ctx->stage == MESA_SHADER_TESS_EVAL ||
652 ctx->is_gs_copy_shader)
653 user_sgpr_info->need_ring_offsets = true;
654
655 if (ctx->stage == MESA_SHADER_FRAGMENT &&
656 ctx->shader_info->info.ps.needs_sample_positions)
657 user_sgpr_info->need_ring_offsets = true;
658
659 /* 2 user sgprs will nearly always be allocated for scratch/rings */
660 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
661 user_sgpr_info->sgpr_count += 2;
662 }
663
664 switch (ctx->stage) {
665 case MESA_SHADER_COMPUTE:
666 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
667 break;
668 case MESA_SHADER_FRAGMENT:
669 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
670 break;
671 case MESA_SHADER_VERTEX:
672 if (!ctx->is_gs_copy_shader) {
673 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
674 if (ctx->shader_info->info.vs.needs_draw_id) {
675 user_sgpr_info->sgpr_count += 3;
676 } else {
677 user_sgpr_info->sgpr_count += 2;
678 }
679 }
680 if (ctx->options->key.vs.as_ls)
681 user_sgpr_info->sgpr_count++;
682 break;
683 case MESA_SHADER_TESS_CTRL:
684 user_sgpr_info->sgpr_count += 4;
685 break;
686 case MESA_SHADER_TESS_EVAL:
687 user_sgpr_info->sgpr_count += 1;
688 break;
689 case MESA_SHADER_GEOMETRY:
690 user_sgpr_info->sgpr_count += 2;
691 break;
692 default:
693 break;
694 }
695
696 if (ctx->shader_info->info.needs_push_constants)
697 user_sgpr_info->sgpr_count += 2;
698
699 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
700 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
701 user_sgpr_info->sgpr_count += 2;
702 user_sgpr_info->indirect_all_descriptor_sets = true;
703 } else {
704 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
705 }
706 }
707
708 static void create_function(struct nir_to_llvm_context *ctx)
709 {
710 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
711 uint8_t user_sgpr_idx;
712 struct user_sgpr_info user_sgpr_info;
713 struct arg_info args = {};
714 LLVMValueRef desc_sets;
715
716 allocate_user_sgprs(ctx, &user_sgpr_info);
717 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
718 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
719 }
720
721 /* 1 for each descriptor set */
722 if (!user_sgpr_info.indirect_all_descriptor_sets) {
723 for (unsigned i = 0; i < num_sets; ++i) {
724 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
725 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
726 }
727 }
728 } else
729 add_user_sgpr_array_argument(&args, const_array(const_array(ctx->i8, 1024 * 1024), 32), &desc_sets);
730
731 if (ctx->shader_info->info.needs_push_constants) {
732 /* 1 for push constants and dynamic descriptors */
733 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
734 }
735
736 switch (ctx->stage) {
737 case MESA_SHADER_COMPUTE:
738 if (ctx->shader_info->info.cs.grid_components_used)
739 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
740 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
741 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
742 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
743 break;
744 case MESA_SHADER_VERTEX:
745 if (!ctx->is_gs_copy_shader) {
746 if (ctx->shader_info->info.vs.has_vertex_buffers)
747 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
748 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.base_vertex); // base vertex
749 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.start_instance);// start instance
750 if (ctx->shader_info->info.vs.needs_draw_id)
751 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.draw_id); // draw id
752 }
753 if (ctx->options->key.vs.as_es)
754 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
755 else if (ctx->options->key.vs.as_ls)
756 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
757 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
758 if (!ctx->is_gs_copy_shader) {
759 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
760 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
761 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
762 }
763 break;
764 case MESA_SHADER_TESS_CTRL:
765 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
766 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
767 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
768 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
769 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
770 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
771 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
772 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
773 break;
774 case MESA_SHADER_TESS_EVAL:
775 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
776 if (ctx->options->key.tes.as_es) {
777 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
778 add_sgpr_argument(&args, ctx->i32, NULL); //
779 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
780 } else {
781 add_sgpr_argument(&args, ctx->i32, NULL); //
782 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
783 }
784 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
785 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
786 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
787 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
788 break;
789 case MESA_SHADER_GEOMETRY:
790 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
791 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
792 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
793 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
794 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
795 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
796 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
797 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
798 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
799 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
800 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
801 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
802 break;
803 case MESA_SHADER_FRAGMENT:
804 if (ctx->shader_info->info.ps.needs_sample_positions)
805 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
806 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
807 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
808 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
809 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
810 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
811 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
812 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
813 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
814 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
815 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[0]); /* pos x float */
816 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[1]); /* pos y float */
817 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[2]); /* pos z float */
818 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[3]); /* pos w float */
819 add_vgpr_argument(&args, ctx->i32, &ctx->front_face); /* front face */
820 add_vgpr_argument(&args, ctx->i32, &ctx->ancillary); /* ancillary */
821 add_vgpr_argument(&args, ctx->i32, &ctx->sample_coverage); /* sample coverage */
822 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
823 break;
824 default:
825 unreachable("Shader stage not implemented");
826 }
827
828 ctx->main_function = create_llvm_function(
829 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
830 ctx->max_workgroup_size,
831 ctx->options->unsafe_math);
832 set_llvm_calling_convention(ctx->main_function, ctx->stage);
833
834
835 ctx->shader_info->num_input_vgprs = 0;
836 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs =
837 ctx->options->supports_spill ? 2 : 0;
838
839 ctx->shader_info->num_user_sgprs += args.num_user_sgprs_used;
840 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
841
842 if (ctx->stage != MESA_SHADER_FRAGMENT)
843 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
844
845 assign_arguments(ctx->main_function, &args);
846
847 user_sgpr_idx = 0;
848
849 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
850 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
851 if (ctx->options->supports_spill) {
852 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
853 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
854 NULL, 0, AC_FUNC_ATTR_READNONE);
855 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
856 const_array(ctx->v4i32, 16), "");
857 }
858 }
859
860 if (!user_sgpr_info.indirect_all_descriptor_sets) {
861 for (unsigned i = 0; i < num_sets; ++i) {
862 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
863 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
864 } else
865 ctx->descriptor_sets[i] = NULL;
866 }
867 } else {
868 uint32_t desc_sgpr_idx = user_sgpr_idx;
869 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
870
871 for (unsigned i = 0; i < num_sets; ++i) {
872 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
873 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
874 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
875
876 } else
877 ctx->descriptor_sets[i] = NULL;
878 }
879 ctx->shader_info->need_indirect_descriptor_sets = true;
880 }
881
882 if (ctx->shader_info->info.needs_push_constants) {
883 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
884 }
885
886 switch (ctx->stage) {
887 case MESA_SHADER_COMPUTE:
888 if (ctx->shader_info->info.cs.grid_components_used) {
889 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
890 }
891 break;
892 case MESA_SHADER_VERTEX:
893 if (!ctx->is_gs_copy_shader) {
894 if (ctx->shader_info->info.vs.has_vertex_buffers) {
895 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
896 }
897 unsigned vs_num = 2;
898 if (ctx->shader_info->info.vs.needs_draw_id)
899 vs_num++;
900
901 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
902 }
903 if (ctx->options->key.vs.as_ls) {
904 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
905 }
906 if (ctx->options->key.vs.as_ls)
907 declare_tess_lds(ctx);
908 break;
909 case MESA_SHADER_TESS_CTRL:
910 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
911 declare_tess_lds(ctx);
912 break;
913 case MESA_SHADER_TESS_EVAL:
914 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
915 break;
916 case MESA_SHADER_GEOMETRY:
917 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
918 break;
919 case MESA_SHADER_FRAGMENT:
920 if (ctx->shader_info->info.ps.needs_sample_positions) {
921 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
922 }
923 break;
924 default:
925 unreachable("Shader stage not implemented");
926 }
927 }
928
929 static void setup_types(struct nir_to_llvm_context *ctx)
930 {
931 LLVMValueRef args[4];
932
933 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
934 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
935 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
936 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
937 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
938 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
939 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
940 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
941 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
942 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
943 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
944 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
945 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
946 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
947 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
948
949 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
950 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
951 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
952 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
953 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
954 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
955
956 args[0] = ctx->f32zero;
957 args[1] = ctx->f32zero;
958 args[2] = ctx->f32zero;
959 args[3] = ctx->f32one;
960 ctx->v4f32empty = LLVMConstVector(args, 4);
961
962 ctx->uniform_md_kind =
963 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
964 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
965
966 args[0] = LLVMConstReal(ctx->f32, 2.5);
967 }
968
969 static int get_llvm_num_components(LLVMValueRef value)
970 {
971 LLVMTypeRef type = LLVMTypeOf(value);
972 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
973 ? LLVMGetVectorSize(type)
974 : 1;
975 return num_components;
976 }
977
978 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
979 LLVMValueRef value,
980 int index)
981 {
982 int count = get_llvm_num_components(value);
983
984 assert(index < count);
985 if (count == 1)
986 return value;
987
988 return LLVMBuildExtractElement(ac->builder, value,
989 LLVMConstInt(ac->i32, index, false), "");
990 }
991
992 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
993 LLVMValueRef value, unsigned count)
994 {
995 unsigned num_components = get_llvm_num_components(value);
996 if (count == num_components)
997 return value;
998
999 LLVMValueRef masks[] = {
1000 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1001 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1002
1003 if (count == 1)
1004 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1005 "");
1006
1007 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1008 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1009 }
1010
1011 static void
1012 build_store_values_extended(struct ac_llvm_context *ac,
1013 LLVMValueRef *values,
1014 unsigned value_count,
1015 unsigned value_stride,
1016 LLVMValueRef vec)
1017 {
1018 LLVMBuilderRef builder = ac->builder;
1019 unsigned i;
1020
1021 if (value_count == 1) {
1022 LLVMBuildStore(builder, vec, values[0]);
1023 return;
1024 }
1025
1026 for (i = 0; i < value_count; i++) {
1027 LLVMValueRef ptr = values[i * value_stride];
1028 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1029 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1030 LLVMBuildStore(builder, value, ptr);
1031 }
1032 }
1033
1034 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1035 const nir_ssa_def *def)
1036 {
1037 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1038 if (def->num_components > 1) {
1039 type = LLVMVectorType(type, def->num_components);
1040 }
1041 return type;
1042 }
1043
1044 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1045 {
1046 assert(src.is_ssa);
1047 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1048 return (LLVMValueRef)entry->data;
1049 }
1050
1051
1052 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1053 const struct nir_block *b)
1054 {
1055 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1056 return (LLVMBasicBlockRef)entry->data;
1057 }
1058
1059 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1060 nir_alu_src src,
1061 unsigned num_components)
1062 {
1063 LLVMValueRef value = get_src(ctx, src.src);
1064 bool need_swizzle = false;
1065
1066 assert(value);
1067 LLVMTypeRef type = LLVMTypeOf(value);
1068 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1069 ? LLVMGetVectorSize(type)
1070 : 1;
1071
1072 for (unsigned i = 0; i < num_components; ++i) {
1073 assert(src.swizzle[i] < src_components);
1074 if (src.swizzle[i] != i)
1075 need_swizzle = true;
1076 }
1077
1078 if (need_swizzle || num_components != src_components) {
1079 LLVMValueRef masks[] = {
1080 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1081 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1082 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1083 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1084
1085 if (src_components > 1 && num_components == 1) {
1086 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1087 masks[0], "");
1088 } else if (src_components == 1 && num_components > 1) {
1089 LLVMValueRef values[] = {value, value, value, value};
1090 value = ac_build_gather_values(&ctx->ac, values, num_components);
1091 } else {
1092 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1093 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1094 swizzle, "");
1095 }
1096 }
1097 assert(!src.negate);
1098 assert(!src.abs);
1099 return value;
1100 }
1101
1102 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1103 LLVMIntPredicate pred, LLVMValueRef src0,
1104 LLVMValueRef src1)
1105 {
1106 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1107 return LLVMBuildSelect(ctx->builder, result,
1108 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1109 LLVMConstInt(ctx->i32, 0, false), "");
1110 }
1111
1112 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1113 LLVMRealPredicate pred, LLVMValueRef src0,
1114 LLVMValueRef src1)
1115 {
1116 LLVMValueRef result;
1117 src0 = to_float(ctx, src0);
1118 src1 = to_float(ctx, src1);
1119 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1120 return LLVMBuildSelect(ctx->builder, result,
1121 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1122 LLVMConstInt(ctx->i32, 0, false), "");
1123 }
1124
1125 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1126 const char *intrin,
1127 LLVMTypeRef result_type,
1128 LLVMValueRef src0)
1129 {
1130 char name[64];
1131 LLVMValueRef params[] = {
1132 to_float(ctx, src0),
1133 };
1134
1135 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1136 get_elem_bits(ctx, result_type));
1137 assert(length < sizeof(name));
1138 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1139 }
1140
1141 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1142 const char *intrin,
1143 LLVMTypeRef result_type,
1144 LLVMValueRef src0, LLVMValueRef src1)
1145 {
1146 char name[64];
1147 LLVMValueRef params[] = {
1148 to_float(ctx, src0),
1149 to_float(ctx, src1),
1150 };
1151
1152 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1153 get_elem_bits(ctx, result_type));
1154 assert(length < sizeof(name));
1155 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1156 }
1157
1158 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1159 const char *intrin,
1160 LLVMTypeRef result_type,
1161 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1162 {
1163 char name[64];
1164 LLVMValueRef params[] = {
1165 to_float(ctx, src0),
1166 to_float(ctx, src1),
1167 to_float(ctx, src2),
1168 };
1169
1170 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1171 get_elem_bits(ctx, result_type));
1172 assert(length < sizeof(name));
1173 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1174 }
1175
1176 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1177 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1178 {
1179 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1180 ctx->i32_0, "");
1181 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1182 }
1183
1184 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1185 LLVMValueRef src0)
1186 {
1187 LLVMValueRef params[2] = {
1188 src0,
1189
1190 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1191 * add special code to check for x=0. The reason is that
1192 * the LLVM behavior for x=0 is different from what we
1193 * need here.
1194 *
1195 * The hardware already implements the correct behavior.
1196 */
1197 LLVMConstInt(ctx->i1, 1, false),
1198 };
1199 return ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1200 }
1201
1202 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1203 LLVMValueRef src0)
1204 {
1205 return ac_build_imsb(ctx, src0, ctx->i32);
1206 }
1207
1208 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1209 LLVMValueRef src0)
1210 {
1211 return ac_build_umsb(ctx, src0, ctx->i32);
1212 }
1213
1214 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1215 LLVMIntPredicate pred,
1216 LLVMValueRef src0, LLVMValueRef src1)
1217 {
1218 return LLVMBuildSelect(ctx->builder,
1219 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1220 src0,
1221 src1, "");
1222
1223 }
1224 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1225 LLVMValueRef src0)
1226 {
1227 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1228 LLVMBuildNeg(ctx->builder, src0, ""));
1229 }
1230
1231 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1232 LLVMValueRef src0)
1233 {
1234 LLVMValueRef cmp, val;
1235
1236 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1237 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1238 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1239 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1240 return val;
1241 }
1242
1243 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1244 LLVMValueRef src0)
1245 {
1246 LLVMValueRef cmp, val;
1247
1248 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1249 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1250 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1251 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1252 return val;
1253 }
1254
1255 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1256 LLVMValueRef src0)
1257 {
1258 const char *intr = "llvm.floor.f32";
1259 LLVMValueRef fsrc0 = to_float(ctx, src0);
1260 LLVMValueRef params[] = {
1261 fsrc0,
1262 };
1263 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1264 ctx->f32, params, 1,
1265 AC_FUNC_ATTR_READNONE);
1266 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1267 }
1268
1269 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1270 const char *intrin,
1271 LLVMValueRef src0, LLVMValueRef src1)
1272 {
1273 LLVMTypeRef ret_type;
1274 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1275 LLVMValueRef res;
1276 LLVMValueRef params[] = { src0, src1 };
1277 ret_type = LLVMStructTypeInContext(ctx->context, types,
1278 2, true);
1279
1280 res = ac_build_intrinsic(ctx, intrin, ret_type,
1281 params, 2, AC_FUNC_ATTR_READNONE);
1282
1283 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1284 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1285 return res;
1286 }
1287
1288 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1289 LLVMValueRef src0)
1290 {
1291 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1292 }
1293
1294 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1295 LLVMValueRef src0)
1296 {
1297 src0 = to_float(ctx, src0);
1298 return LLVMBuildSExt(ctx->builder,
1299 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1300 ctx->i32, "");
1301 }
1302
1303 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1304 LLVMValueRef src0)
1305 {
1306 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1307 }
1308
1309 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1310 LLVMValueRef src0)
1311 {
1312 return LLVMBuildSExt(ctx->builder,
1313 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1314 ctx->i32, "");
1315 }
1316
1317 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1318 LLVMValueRef src0)
1319 {
1320 LLVMValueRef result;
1321 LLVMValueRef cond;
1322
1323 src0 = to_float(&ctx->ac, src0);
1324 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1325
1326 /* TODO SI/CIK options here */
1327 if (ctx->options->chip_class >= VI) {
1328 LLVMValueRef args[2];
1329 /* Check if the result is a denormal - and flush to 0 if so. */
1330 args[0] = result;
1331 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1332 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1333 }
1334
1335 /* need to convert back up to f32 */
1336 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1337
1338 if (ctx->options->chip_class >= VI)
1339 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1340
1341 return result;
1342 }
1343
1344 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1345 LLVMValueRef src0, LLVMValueRef src1)
1346 {
1347 LLVMValueRef dst64, result;
1348 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1349 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1350
1351 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1352 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1353 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1354 return result;
1355 }
1356
1357 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1358 LLVMValueRef src0, LLVMValueRef src1)
1359 {
1360 LLVMValueRef dst64, result;
1361 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1362 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1363
1364 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1365 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1366 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1367 return result;
1368 }
1369
1370 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1371 bool is_signed,
1372 const LLVMValueRef srcs[3])
1373 {
1374 LLVMValueRef result;
1375 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1376
1377 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1378 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1379 return result;
1380 }
1381
1382 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1383 LLVMValueRef src0, LLVMValueRef src1,
1384 LLVMValueRef src2, LLVMValueRef src3)
1385 {
1386 LLVMValueRef bfi_args[3], result;
1387
1388 bfi_args[0] = LLVMBuildShl(ctx->builder,
1389 LLVMBuildSub(ctx->builder,
1390 LLVMBuildShl(ctx->builder,
1391 ctx->i32_1,
1392 src3, ""),
1393 ctx->i32_1, ""),
1394 src2, "");
1395 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1396 bfi_args[2] = src0;
1397
1398 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1399
1400 /* Calculate:
1401 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1402 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1403 */
1404 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1405 LLVMBuildAnd(ctx->builder, bfi_args[0],
1406 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1407
1408 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1409 return result;
1410 }
1411
1412 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1413 LLVMValueRef src0)
1414 {
1415 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1416 int i;
1417 LLVMValueRef comp[2];
1418
1419 src0 = to_float(ctx, src0);
1420 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1421 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1422 for (i = 0; i < 2; i++) {
1423 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1424 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1425 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1426 }
1427
1428 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1429 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1430
1431 return comp[0];
1432 }
1433
1434 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1435 LLVMValueRef src0)
1436 {
1437 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1438 LLVMValueRef temps[2], result, val;
1439 int i;
1440
1441 for (i = 0; i < 2; i++) {
1442 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1443 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1444 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1445 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1446 }
1447
1448 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1449 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1450 ctx->i32_0, "");
1451 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1452 ctx->i32_1, "");
1453 return result;
1454 }
1455
1456 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1457 nir_op op,
1458 LLVMValueRef src0)
1459 {
1460 unsigned mask;
1461 int idx;
1462 LLVMValueRef result;
1463 bool has_ds_bpermute = ctx->abi->chip_class >= VI;
1464
1465 if (!ctx->ddxy_lds && !has_ds_bpermute)
1466 ctx->ddxy_lds = LLVMAddGlobalInAddressSpace(ctx->ac.module,
1467 LLVMArrayType(ctx->ac.i32, 64),
1468 "ddxy_lds", LOCAL_ADDR_SPACE);
1469
1470 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1471 mask = AC_TID_MASK_LEFT;
1472 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1473 mask = AC_TID_MASK_TOP;
1474 else
1475 mask = AC_TID_MASK_TOP_LEFT;
1476
1477 /* for DDX we want to next X pixel, DDY next Y pixel. */
1478 if (op == nir_op_fddx_fine ||
1479 op == nir_op_fddx_coarse ||
1480 op == nir_op_fddx)
1481 idx = 1;
1482 else
1483 idx = 2;
1484
1485 result = ac_build_ddxy(&ctx->ac, has_ds_bpermute,
1486 mask, idx, ctx->ddxy_lds,
1487 src0);
1488 return result;
1489 }
1490
1491 /*
1492 * this takes an I,J coordinate pair,
1493 * and works out the X and Y derivatives.
1494 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1495 */
1496 static LLVMValueRef emit_ddxy_interp(
1497 struct ac_nir_context *ctx,
1498 LLVMValueRef interp_ij)
1499 {
1500 LLVMValueRef result[4], a;
1501 unsigned i;
1502
1503 for (i = 0; i < 2; i++) {
1504 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1505 LLVMConstInt(ctx->ac.i32, i, false), "");
1506 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1507 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1508 }
1509 return ac_build_gather_values(&ctx->ac, result, 4);
1510 }
1511
1512 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1513 {
1514 LLVMValueRef src[4], result = NULL;
1515 unsigned num_components = instr->dest.dest.ssa.num_components;
1516 unsigned src_components;
1517 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1518
1519 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1520 switch (instr->op) {
1521 case nir_op_vec2:
1522 case nir_op_vec3:
1523 case nir_op_vec4:
1524 src_components = 1;
1525 break;
1526 case nir_op_pack_half_2x16:
1527 src_components = 2;
1528 break;
1529 case nir_op_unpack_half_2x16:
1530 src_components = 1;
1531 break;
1532 default:
1533 src_components = num_components;
1534 break;
1535 }
1536 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1537 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1538
1539 switch (instr->op) {
1540 case nir_op_fmov:
1541 case nir_op_imov:
1542 result = src[0];
1543 break;
1544 case nir_op_fneg:
1545 src[0] = to_float(&ctx->ac, src[0]);
1546 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1547 break;
1548 case nir_op_ineg:
1549 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1550 break;
1551 case nir_op_inot:
1552 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1553 break;
1554 case nir_op_iadd:
1555 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1556 break;
1557 case nir_op_fadd:
1558 src[0] = to_float(&ctx->ac, src[0]);
1559 src[1] = to_float(&ctx->ac, src[1]);
1560 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1561 break;
1562 case nir_op_fsub:
1563 src[0] = to_float(&ctx->ac, src[0]);
1564 src[1] = to_float(&ctx->ac, src[1]);
1565 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1566 break;
1567 case nir_op_isub:
1568 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1569 break;
1570 case nir_op_imul:
1571 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1572 break;
1573 case nir_op_imod:
1574 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1575 break;
1576 case nir_op_umod:
1577 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1578 break;
1579 case nir_op_fmod:
1580 src[0] = to_float(&ctx->ac, src[0]);
1581 src[1] = to_float(&ctx->ac, src[1]);
1582 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1583 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1584 to_float_type(&ctx->ac, def_type), result);
1585 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1586 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1587 break;
1588 case nir_op_frem:
1589 src[0] = to_float(&ctx->ac, src[0]);
1590 src[1] = to_float(&ctx->ac, src[1]);
1591 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1592 break;
1593 case nir_op_irem:
1594 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1595 break;
1596 case nir_op_idiv:
1597 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1598 break;
1599 case nir_op_udiv:
1600 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1601 break;
1602 case nir_op_fmul:
1603 src[0] = to_float(&ctx->ac, src[0]);
1604 src[1] = to_float(&ctx->ac, src[1]);
1605 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1606 break;
1607 case nir_op_fdiv:
1608 src[0] = to_float(&ctx->ac, src[0]);
1609 src[1] = to_float(&ctx->ac, src[1]);
1610 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1611 break;
1612 case nir_op_frcp:
1613 src[0] = to_float(&ctx->ac, src[0]);
1614 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1615 break;
1616 case nir_op_iand:
1617 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1618 break;
1619 case nir_op_ior:
1620 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1621 break;
1622 case nir_op_ixor:
1623 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1624 break;
1625 case nir_op_ishl:
1626 result = LLVMBuildShl(ctx->ac.builder, src[0],
1627 LLVMBuildZExt(ctx->ac.builder, src[1],
1628 LLVMTypeOf(src[0]), ""),
1629 "");
1630 break;
1631 case nir_op_ishr:
1632 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1633 LLVMBuildZExt(ctx->ac.builder, src[1],
1634 LLVMTypeOf(src[0]), ""),
1635 "");
1636 break;
1637 case nir_op_ushr:
1638 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1639 LLVMBuildZExt(ctx->ac.builder, src[1],
1640 LLVMTypeOf(src[0]), ""),
1641 "");
1642 break;
1643 case nir_op_ilt:
1644 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1645 break;
1646 case nir_op_ine:
1647 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1648 break;
1649 case nir_op_ieq:
1650 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1651 break;
1652 case nir_op_ige:
1653 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1654 break;
1655 case nir_op_ult:
1656 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1657 break;
1658 case nir_op_uge:
1659 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1660 break;
1661 case nir_op_feq:
1662 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1663 break;
1664 case nir_op_fne:
1665 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1666 break;
1667 case nir_op_flt:
1668 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1669 break;
1670 case nir_op_fge:
1671 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1672 break;
1673 case nir_op_fabs:
1674 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1675 to_float_type(&ctx->ac, def_type), src[0]);
1676 break;
1677 case nir_op_iabs:
1678 result = emit_iabs(&ctx->ac, src[0]);
1679 break;
1680 case nir_op_imax:
1681 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1682 break;
1683 case nir_op_imin:
1684 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1685 break;
1686 case nir_op_umax:
1687 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1688 break;
1689 case nir_op_umin:
1690 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1691 break;
1692 case nir_op_isign:
1693 result = emit_isign(&ctx->ac, src[0]);
1694 break;
1695 case nir_op_fsign:
1696 src[0] = to_float(&ctx->ac, src[0]);
1697 result = emit_fsign(&ctx->ac, src[0]);
1698 break;
1699 case nir_op_ffloor:
1700 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1701 to_float_type(&ctx->ac, def_type), src[0]);
1702 break;
1703 case nir_op_ftrunc:
1704 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1705 to_float_type(&ctx->ac, def_type), src[0]);
1706 break;
1707 case nir_op_fceil:
1708 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1709 to_float_type(&ctx->ac, def_type), src[0]);
1710 break;
1711 case nir_op_fround_even:
1712 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1713 to_float_type(&ctx->ac, def_type),src[0]);
1714 break;
1715 case nir_op_ffract:
1716 result = emit_ffract(&ctx->ac, src[0]);
1717 break;
1718 case nir_op_fsin:
1719 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1720 to_float_type(&ctx->ac, def_type), src[0]);
1721 break;
1722 case nir_op_fcos:
1723 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1724 to_float_type(&ctx->ac, def_type), src[0]);
1725 break;
1726 case nir_op_fsqrt:
1727 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1728 to_float_type(&ctx->ac, def_type), src[0]);
1729 break;
1730 case nir_op_fexp2:
1731 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1732 to_float_type(&ctx->ac, def_type), src[0]);
1733 break;
1734 case nir_op_flog2:
1735 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1736 to_float_type(&ctx->ac, def_type), src[0]);
1737 break;
1738 case nir_op_frsq:
1739 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1740 to_float_type(&ctx->ac, def_type), src[0]);
1741 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1742 break;
1743 case nir_op_fpow:
1744 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1745 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1746 break;
1747 case nir_op_fmax:
1748 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1749 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1750 if (instr->dest.dest.ssa.bit_size == 32)
1751 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1752 to_float_type(&ctx->ac, def_type),
1753 result);
1754 break;
1755 case nir_op_fmin:
1756 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1757 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1758 if (instr->dest.dest.ssa.bit_size == 32)
1759 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1760 to_float_type(&ctx->ac, def_type),
1761 result);
1762 break;
1763 case nir_op_ffma:
1764 result = emit_intrin_3f_param(&ctx->ac, "llvm.fma",
1765 to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1766 break;
1767 case nir_op_ibitfield_extract:
1768 result = emit_bitfield_extract(&ctx->ac, true, src);
1769 break;
1770 case nir_op_ubitfield_extract:
1771 result = emit_bitfield_extract(&ctx->ac, false, src);
1772 break;
1773 case nir_op_bitfield_insert:
1774 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1775 break;
1776 case nir_op_bitfield_reverse:
1777 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1778 break;
1779 case nir_op_bit_count:
1780 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1781 break;
1782 case nir_op_vec2:
1783 case nir_op_vec3:
1784 case nir_op_vec4:
1785 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1786 src[i] = to_integer(&ctx->ac, src[i]);
1787 result = ac_build_gather_values(&ctx->ac, src, num_components);
1788 break;
1789 case nir_op_f2i32:
1790 case nir_op_f2i64:
1791 src[0] = to_float(&ctx->ac, src[0]);
1792 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1793 break;
1794 case nir_op_f2u32:
1795 case nir_op_f2u64:
1796 src[0] = to_float(&ctx->ac, src[0]);
1797 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1798 break;
1799 case nir_op_i2f32:
1800 case nir_op_i2f64:
1801 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1802 break;
1803 case nir_op_u2f32:
1804 case nir_op_u2f64:
1805 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1806 break;
1807 case nir_op_f2f64:
1808 result = LLVMBuildFPExt(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1809 break;
1810 case nir_op_f2f32:
1811 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1812 break;
1813 case nir_op_u2u32:
1814 case nir_op_u2u64:
1815 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1816 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1817 else
1818 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1819 break;
1820 case nir_op_i2i32:
1821 case nir_op_i2i64:
1822 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1823 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1824 else
1825 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1826 break;
1827 case nir_op_bcsel:
1828 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1829 break;
1830 case nir_op_find_lsb:
1831 result = emit_find_lsb(&ctx->ac, src[0]);
1832 break;
1833 case nir_op_ufind_msb:
1834 result = emit_ufind_msb(&ctx->ac, src[0]);
1835 break;
1836 case nir_op_ifind_msb:
1837 result = emit_ifind_msb(&ctx->ac, src[0]);
1838 break;
1839 case nir_op_uadd_carry:
1840 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1841 break;
1842 case nir_op_usub_borrow:
1843 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1844 break;
1845 case nir_op_b2f:
1846 result = emit_b2f(&ctx->ac, src[0]);
1847 break;
1848 case nir_op_f2b:
1849 result = emit_f2b(&ctx->ac, src[0]);
1850 break;
1851 case nir_op_b2i:
1852 result = emit_b2i(&ctx->ac, src[0]);
1853 break;
1854 case nir_op_i2b:
1855 result = emit_i2b(&ctx->ac, src[0]);
1856 break;
1857 case nir_op_fquantize2f16:
1858 result = emit_f2f16(ctx->nctx, src[0]);
1859 break;
1860 case nir_op_umul_high:
1861 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1862 break;
1863 case nir_op_imul_high:
1864 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1865 break;
1866 case nir_op_pack_half_2x16:
1867 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1868 break;
1869 case nir_op_unpack_half_2x16:
1870 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1871 break;
1872 case nir_op_fddx:
1873 case nir_op_fddy:
1874 case nir_op_fddx_fine:
1875 case nir_op_fddy_fine:
1876 case nir_op_fddx_coarse:
1877 case nir_op_fddy_coarse:
1878 result = emit_ddxy(ctx, instr->op, src[0]);
1879 break;
1880
1881 case nir_op_unpack_64_2x32_split_x: {
1882 assert(instr->src[0].src.ssa->num_components == 1);
1883 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1884 LLVMVectorType(ctx->ac.i32, 2),
1885 "");
1886 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1887 ctx->ac.i32_0, "");
1888 break;
1889 }
1890
1891 case nir_op_unpack_64_2x32_split_y: {
1892 assert(instr->src[0].src.ssa->num_components == 1);
1893 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1894 LLVMVectorType(ctx->ac.i32, 2),
1895 "");
1896 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1897 ctx->ac.i32_0, "");
1898 break;
1899 }
1900
1901 case nir_op_pack_64_2x32_split: {
1902 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
1903 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1904 src[0], ctx->ac.i32_0, "");
1905 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1906 src[1], ctx->ac.i32_1, "");
1907 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1908 break;
1909 }
1910
1911 default:
1912 fprintf(stderr, "Unknown NIR alu instr: ");
1913 nir_print_instr(&instr->instr, stderr);
1914 fprintf(stderr, "\n");
1915 abort();
1916 }
1917
1918 if (result) {
1919 assert(instr->dest.dest.is_ssa);
1920 result = to_integer(&ctx->ac, result);
1921 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1922 result);
1923 }
1924 }
1925
1926 static void visit_load_const(struct ac_nir_context *ctx,
1927 const nir_load_const_instr *instr)
1928 {
1929 LLVMValueRef values[4], value = NULL;
1930 LLVMTypeRef element_type =
1931 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1932
1933 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1934 switch (instr->def.bit_size) {
1935 case 32:
1936 values[i] = LLVMConstInt(element_type,
1937 instr->value.u32[i], false);
1938 break;
1939 case 64:
1940 values[i] = LLVMConstInt(element_type,
1941 instr->value.u64[i], false);
1942 break;
1943 default:
1944 fprintf(stderr,
1945 "unsupported nir load_const bit_size: %d\n",
1946 instr->def.bit_size);
1947 abort();
1948 }
1949 }
1950 if (instr->def.num_components > 1) {
1951 value = LLVMConstVector(values, instr->def.num_components);
1952 } else
1953 value = values[0];
1954
1955 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1956 }
1957
1958 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1959 LLVMTypeRef type)
1960 {
1961 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1962 return LLVMBuildBitCast(ctx->builder, ptr,
1963 LLVMPointerType(type, addr_space), "");
1964 }
1965
1966 static LLVMValueRef
1967 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1968 {
1969 LLVMValueRef size =
1970 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1971 LLVMConstInt(ctx->ac.i32, 2, false), "");
1972
1973 /* VI only */
1974 if (ctx->abi->chip_class >= VI && in_elements) {
1975 /* On VI, the descriptor contains the size in bytes,
1976 * but TXQ must return the size in elements.
1977 * The stride is always non-zero for resources using TXQ.
1978 */
1979 LLVMValueRef stride =
1980 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1981 LLVMConstInt(ctx->ac.i32, 1, false), "");
1982 stride = LLVMBuildLShr(ctx->ac.builder, stride,
1983 LLVMConstInt(ctx->ac.i32, 16, false), "");
1984 stride = LLVMBuildAnd(ctx->ac.builder, stride,
1985 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
1986
1987 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
1988 }
1989 return size;
1990 }
1991
1992 /**
1993 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1994 * intrinsic names).
1995 */
1996 static void build_int_type_name(
1997 LLVMTypeRef type,
1998 char *buf, unsigned bufsize)
1999 {
2000 assert(bufsize >= 6);
2001
2002 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2003 snprintf(buf, bufsize, "v%ui32",
2004 LLVMGetVectorSize(type));
2005 else
2006 strcpy(buf, "i32");
2007 }
2008
2009 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2010 struct ac_image_args *args,
2011 const nir_tex_instr *instr)
2012 {
2013 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2014 LLVMValueRef coord = args->addr;
2015 LLVMValueRef half_texel[2];
2016 LLVMValueRef compare_cube_wa;
2017 LLVMValueRef result;
2018 int c;
2019 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2020
2021 //TODO Rect
2022 {
2023 struct ac_image_args txq_args = { 0 };
2024
2025 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2026 txq_args.opcode = ac_image_get_resinfo;
2027 txq_args.dmask = 0xf;
2028 txq_args.addr = ctx->i32_0;
2029 txq_args.resource = args->resource;
2030 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2031
2032 for (c = 0; c < 2; c++) {
2033 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2034 LLVMConstInt(ctx->i32, c, false), "");
2035 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2036 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2037 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2038 LLVMConstReal(ctx->f32, -0.5), "");
2039 }
2040 }
2041
2042 LLVMValueRef orig_coords = args->addr;
2043
2044 for (c = 0; c < 2; c++) {
2045 LLVMValueRef tmp;
2046 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2047 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2048 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2049 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2050 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2051 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2052 }
2053
2054
2055 /*
2056 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2057 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2058 * workaround by sampling using a scaled type and converting.
2059 * This is taken from amdgpu-pro shaders.
2060 */
2061 /* NOTE this produces some ugly code compared to amdgpu-pro,
2062 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2063 * and then reads them back. -pro generates two selects,
2064 * one s_cmp for the descriptor rewriting
2065 * one v_cmp for the coordinate and result changes.
2066 */
2067 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2068 LLVMValueRef tmp, tmp2;
2069
2070 /* workaround 8/8/8/8 uint/sint cube gather bug */
2071 /* first detect it then change to a scaled read and f2i */
2072 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2073 tmp2 = tmp;
2074
2075 /* extract the DATA_FORMAT */
2076 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2077 LLVMConstInt(ctx->i32, 6, false), false);
2078
2079 /* is the DATA_FORMAT == 8_8_8_8 */
2080 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2081
2082 if (stype == GLSL_TYPE_UINT)
2083 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2084 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2085 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2086 else
2087 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2088 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2089 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2090
2091 /* replace the NUM FORMAT in the descriptor */
2092 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2093 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2094
2095 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2096
2097 /* don't modify the coordinates for this case */
2098 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2099 }
2100 args->addr = coord;
2101 result = ac_build_image_opcode(ctx, args);
2102
2103 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2104 LLVMValueRef tmp, tmp2;
2105
2106 /* if the cube workaround is in place, f2i the result. */
2107 for (c = 0; c < 4; c++) {
2108 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2109 if (stype == GLSL_TYPE_UINT)
2110 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2111 else
2112 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2113 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2114 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2115 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2116 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2117 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2118 }
2119 }
2120 return result;
2121 }
2122
2123 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2124 const nir_tex_instr *instr,
2125 bool lod_is_zero,
2126 struct ac_image_args *args)
2127 {
2128 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2129 return ac_build_buffer_load_format(&ctx->ac,
2130 args->resource,
2131 args->addr,
2132 LLVMConstInt(ctx->ac.i32, 0, false),
2133 true);
2134 }
2135
2136 args->opcode = ac_image_sample;
2137 args->compare = instr->is_shadow;
2138
2139 switch (instr->op) {
2140 case nir_texop_txf:
2141 case nir_texop_txf_ms:
2142 case nir_texop_samples_identical:
2143 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2144 args->compare = false;
2145 args->offset = false;
2146 break;
2147 case nir_texop_txb:
2148 args->bias = true;
2149 break;
2150 case nir_texop_txl:
2151 if (lod_is_zero)
2152 args->level_zero = true;
2153 else
2154 args->lod = true;
2155 break;
2156 case nir_texop_txs:
2157 case nir_texop_query_levels:
2158 args->opcode = ac_image_get_resinfo;
2159 break;
2160 case nir_texop_tex:
2161 if (ctx->stage != MESA_SHADER_FRAGMENT)
2162 args->level_zero = true;
2163 break;
2164 case nir_texop_txd:
2165 args->deriv = true;
2166 break;
2167 case nir_texop_tg4:
2168 args->opcode = ac_image_gather4;
2169 args->level_zero = true;
2170 break;
2171 case nir_texop_lod:
2172 args->opcode = ac_image_get_lod;
2173 args->compare = false;
2174 args->offset = false;
2175 break;
2176 default:
2177 break;
2178 }
2179
2180 if (instr->op == nir_texop_tg4) {
2181 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2182 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2183 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2184 }
2185 }
2186 return ac_build_image_opcode(&ctx->ac, args);
2187 }
2188
2189 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2190 nir_intrinsic_instr *instr)
2191 {
2192 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2193 unsigned desc_set = nir_intrinsic_desc_set(instr);
2194 unsigned binding = nir_intrinsic_binding(instr);
2195 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2196 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2197 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2198 unsigned base_offset = layout->binding[binding].offset;
2199 LLVMValueRef offset, stride;
2200
2201 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2202 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2203 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2204 layout->binding[binding].dynamic_offset_offset;
2205 desc_ptr = ctx->push_constants;
2206 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2207 stride = LLVMConstInt(ctx->i32, 16, false);
2208 } else
2209 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2210
2211 offset = LLVMConstInt(ctx->i32, base_offset, false);
2212 index = LLVMBuildMul(ctx->builder, index, stride, "");
2213 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2214
2215 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2216 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2217 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2218
2219 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2220 }
2221
2222 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2223 nir_intrinsic_instr *instr)
2224 {
2225 LLVMValueRef ptr, addr;
2226
2227 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2228 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2229
2230 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2231 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2232
2233 return LLVMBuildLoad(ctx->builder, ptr, "");
2234 }
2235
2236 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2237 const nir_intrinsic_instr *instr)
2238 {
2239 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2240
2241 return get_buffer_size(ctx, desc, false);
2242 }
2243 static void visit_store_ssbo(struct ac_nir_context *ctx,
2244 nir_intrinsic_instr *instr)
2245 {
2246 const char *store_name;
2247 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2248 LLVMTypeRef data_type = ctx->ac.f32;
2249 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2250 int components_32bit = elem_size_mult * instr->num_components;
2251 unsigned writemask = nir_intrinsic_write_mask(instr);
2252 LLVMValueRef base_data, base_offset;
2253 LLVMValueRef params[6];
2254 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2255
2256 params[1] = ctx->abi->load_ssbo(ctx->abi,
2257 get_src(ctx, instr->src[1]), true);
2258 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2259 params[4] = i1false; /* glc */
2260 params[5] = i1false; /* slc */
2261
2262 if (components_32bit > 1)
2263 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2264
2265 base_data = to_float(&ctx->ac, src_data);
2266 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2267 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2268 data_type, "");
2269 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2270 while (writemask) {
2271 int start, count;
2272 LLVMValueRef data;
2273 LLVMValueRef offset;
2274 LLVMValueRef tmp;
2275 u_bit_scan_consecutive_range(&writemask, &start, &count);
2276
2277 /* Due to an LLVM limitation, split 3-element writes
2278 * into a 2-element and a 1-element write. */
2279 if (count == 3) {
2280 writemask |= 1 << (start + 2);
2281 count = 2;
2282 }
2283
2284 start *= elem_size_mult;
2285 count *= elem_size_mult;
2286
2287 if (count > 4) {
2288 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2289 count = 4;
2290 }
2291
2292 if (count == 4) {
2293 store_name = "llvm.amdgcn.buffer.store.v4f32";
2294 data = base_data;
2295 } else if (count == 2) {
2296 LLVMTypeRef v2f32 = LLVMVectorType(ctx->ac.f32, 2);
2297
2298 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2299 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2300 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(v2f32), tmp,
2301 ctx->ac.i32_0, "");
2302
2303 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2304 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2305 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2306 ctx->ac.i32_1, "");
2307 store_name = "llvm.amdgcn.buffer.store.v2f32";
2308
2309 } else {
2310 assert(count == 1);
2311 if (get_llvm_num_components(base_data) > 1)
2312 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2313 LLVMConstInt(ctx->ac.i32, start, false), "");
2314 else
2315 data = base_data;
2316 store_name = "llvm.amdgcn.buffer.store.f32";
2317 }
2318
2319 offset = base_offset;
2320 if (start != 0) {
2321 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2322 }
2323 params[0] = data;
2324 params[3] = offset;
2325 ac_build_intrinsic(&ctx->ac, store_name,
2326 ctx->ac.voidt, params, 6, 0);
2327 }
2328 }
2329
2330 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2331 const nir_intrinsic_instr *instr)
2332 {
2333 const char *name;
2334 LLVMValueRef params[6];
2335 int arg_count = 0;
2336
2337 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2338 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2339 }
2340 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2341 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2342 get_src(ctx, instr->src[0]),
2343 true);
2344 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2345 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2346 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2347
2348 switch (instr->intrinsic) {
2349 case nir_intrinsic_ssbo_atomic_add:
2350 name = "llvm.amdgcn.buffer.atomic.add";
2351 break;
2352 case nir_intrinsic_ssbo_atomic_imin:
2353 name = "llvm.amdgcn.buffer.atomic.smin";
2354 break;
2355 case nir_intrinsic_ssbo_atomic_umin:
2356 name = "llvm.amdgcn.buffer.atomic.umin";
2357 break;
2358 case nir_intrinsic_ssbo_atomic_imax:
2359 name = "llvm.amdgcn.buffer.atomic.smax";
2360 break;
2361 case nir_intrinsic_ssbo_atomic_umax:
2362 name = "llvm.amdgcn.buffer.atomic.umax";
2363 break;
2364 case nir_intrinsic_ssbo_atomic_and:
2365 name = "llvm.amdgcn.buffer.atomic.and";
2366 break;
2367 case nir_intrinsic_ssbo_atomic_or:
2368 name = "llvm.amdgcn.buffer.atomic.or";
2369 break;
2370 case nir_intrinsic_ssbo_atomic_xor:
2371 name = "llvm.amdgcn.buffer.atomic.xor";
2372 break;
2373 case nir_intrinsic_ssbo_atomic_exchange:
2374 name = "llvm.amdgcn.buffer.atomic.swap";
2375 break;
2376 case nir_intrinsic_ssbo_atomic_comp_swap:
2377 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2378 break;
2379 default:
2380 abort();
2381 }
2382
2383 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2384 }
2385
2386 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2387 const nir_intrinsic_instr *instr)
2388 {
2389 LLVMValueRef results[2];
2390 int load_components;
2391 int num_components = instr->num_components;
2392 if (instr->dest.ssa.bit_size == 64)
2393 num_components *= 2;
2394
2395 for (int i = 0; i < num_components; i += load_components) {
2396 load_components = MIN2(num_components - i, 4);
2397 const char *load_name;
2398 LLVMTypeRef data_type = ctx->ac.f32;
2399 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2400 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2401
2402 if (load_components == 3)
2403 data_type = LLVMVectorType(ctx->ac.f32, 4);
2404 else if (load_components > 1)
2405 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2406
2407 if (load_components >= 3)
2408 load_name = "llvm.amdgcn.buffer.load.v4f32";
2409 else if (load_components == 2)
2410 load_name = "llvm.amdgcn.buffer.load.v2f32";
2411 else if (load_components == 1)
2412 load_name = "llvm.amdgcn.buffer.load.f32";
2413 else
2414 unreachable("unhandled number of components");
2415
2416 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2417 LLVMValueRef params[] = {
2418 ctx->abi->load_ssbo(ctx->abi,
2419 get_src(ctx, instr->src[0]),
2420 false),
2421 LLVMConstInt(ctx->ac.i32, 0, false),
2422 offset,
2423 i1false,
2424 i1false,
2425 };
2426
2427 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2428
2429 }
2430
2431 LLVMValueRef ret = results[0];
2432 if (num_components > 4 || num_components == 3) {
2433 LLVMValueRef masks[] = {
2434 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2435 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2436 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2437 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2438 };
2439
2440 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2441 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2442 results[num_components > 4 ? 1 : 0], swizzle, "");
2443 }
2444
2445 return LLVMBuildBitCast(ctx->ac.builder, ret,
2446 get_def_type(ctx, &instr->dest.ssa), "");
2447 }
2448
2449 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2450 const nir_intrinsic_instr *instr)
2451 {
2452 LLVMValueRef results[8], ret;
2453 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2454 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2455 int num_components = instr->num_components;
2456
2457 if (ctx->abi->load_ubo)
2458 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2459
2460 if (instr->dest.ssa.bit_size == 64)
2461 num_components *= 2;
2462
2463 for (unsigned i = 0; i < num_components; ++i) {
2464 LLVMValueRef params[] = {
2465 rsrc,
2466 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2467 offset, "")
2468 };
2469 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2470 params, 2,
2471 AC_FUNC_ATTR_READNONE |
2472 AC_FUNC_ATTR_LEGACY);
2473 }
2474
2475
2476 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2477 return LLVMBuildBitCast(ctx->ac.builder, ret,
2478 get_def_type(ctx, &instr->dest.ssa), "");
2479 }
2480
2481 static void
2482 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2483 bool vs_in, unsigned *vertex_index_out,
2484 LLVMValueRef *vertex_index_ref,
2485 unsigned *const_out, LLVMValueRef *indir_out)
2486 {
2487 unsigned const_offset = 0;
2488 nir_deref *tail = &deref->deref;
2489 LLVMValueRef offset = NULL;
2490
2491 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2492 tail = tail->child;
2493 nir_deref_array *deref_array = nir_deref_as_array(tail);
2494 if (vertex_index_out)
2495 *vertex_index_out = deref_array->base_offset;
2496
2497 if (vertex_index_ref) {
2498 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2499 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2500 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2501 }
2502 *vertex_index_ref = vtx;
2503 }
2504 }
2505
2506 if (deref->var->data.compact) {
2507 assert(tail->child->deref_type == nir_deref_type_array);
2508 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2509 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2510 /* We always lower indirect dereferences for "compact" array vars. */
2511 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2512
2513 const_offset = deref_array->base_offset;
2514 goto out;
2515 }
2516
2517 while (tail->child != NULL) {
2518 const struct glsl_type *parent_type = tail->type;
2519 tail = tail->child;
2520
2521 if (tail->deref_type == nir_deref_type_array) {
2522 nir_deref_array *deref_array = nir_deref_as_array(tail);
2523 LLVMValueRef index, stride, local_offset;
2524 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2525
2526 const_offset += size * deref_array->base_offset;
2527 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2528 continue;
2529
2530 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2531 index = get_src(ctx, deref_array->indirect);
2532 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2533 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2534
2535 if (offset)
2536 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2537 else
2538 offset = local_offset;
2539 } else if (tail->deref_type == nir_deref_type_struct) {
2540 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2541
2542 for (unsigned i = 0; i < deref_struct->index; i++) {
2543 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2544 const_offset += glsl_count_attribute_slots(ft, vs_in);
2545 }
2546 } else
2547 unreachable("unsupported deref type");
2548
2549 }
2550 out:
2551 if (const_offset && offset)
2552 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2553 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2554 "");
2555
2556 *const_out = const_offset;
2557 *indir_out = offset;
2558 }
2559
2560 static LLVMValueRef
2561 lds_load(struct nir_to_llvm_context *ctx,
2562 LLVMValueRef dw_addr)
2563 {
2564 LLVMValueRef value;
2565 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2566 return value;
2567 }
2568
2569 static void
2570 lds_store(struct nir_to_llvm_context *ctx,
2571 LLVMValueRef dw_addr, LLVMValueRef value)
2572 {
2573 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2574 ac_build_indexed_store(&ctx->ac, ctx->lds,
2575 dw_addr, value);
2576 }
2577
2578 /* The offchip buffer layout for TCS->TES is
2579 *
2580 * - attribute 0 of patch 0 vertex 0
2581 * - attribute 0 of patch 0 vertex 1
2582 * - attribute 0 of patch 0 vertex 2
2583 * ...
2584 * - attribute 0 of patch 1 vertex 0
2585 * - attribute 0 of patch 1 vertex 1
2586 * ...
2587 * - attribute 1 of patch 0 vertex 0
2588 * - attribute 1 of patch 0 vertex 1
2589 * ...
2590 * - per patch attribute 0 of patch 0
2591 * - per patch attribute 0 of patch 1
2592 * ...
2593 *
2594 * Note that every attribute has 4 components.
2595 */
2596 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2597 LLVMValueRef vertex_index,
2598 LLVMValueRef param_index)
2599 {
2600 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2601 LLVMValueRef param_stride, constant16;
2602 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2603
2604 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2605 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2606 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2607 num_patches, "");
2608
2609 constant16 = LLVMConstInt(ctx->i32, 16, false);
2610 if (vertex_index) {
2611 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2612 vertices_per_patch, "");
2613
2614 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2615 vertex_index, "");
2616
2617 param_stride = total_vertices;
2618 } else {
2619 base_addr = rel_patch_id;
2620 param_stride = num_patches;
2621 }
2622
2623 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2624 LLVMBuildMul(ctx->builder, param_index,
2625 param_stride, ""), "");
2626
2627 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2628
2629 if (!vertex_index) {
2630 LLVMValueRef patch_data_offset =
2631 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2632
2633 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2634 patch_data_offset, "");
2635 }
2636 return base_addr;
2637 }
2638
2639 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2640 unsigned param,
2641 unsigned const_index,
2642 bool is_compact,
2643 LLVMValueRef vertex_index,
2644 LLVMValueRef indir_index)
2645 {
2646 LLVMValueRef param_index;
2647
2648 if (indir_index)
2649 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2650 indir_index, "");
2651 else {
2652 if (const_index && !is_compact)
2653 param += const_index;
2654 param_index = LLVMConstInt(ctx->i32, param, false);
2655 }
2656 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2657 }
2658
2659 static void
2660 mark_tess_output(struct nir_to_llvm_context *ctx,
2661 bool is_patch, uint32_t param)
2662
2663 {
2664 if (is_patch) {
2665 ctx->tess_patch_outputs_written |= (1ull << param);
2666 } else
2667 ctx->tess_outputs_written |= (1ull << param);
2668 }
2669
2670 static LLVMValueRef
2671 get_dw_address(struct nir_to_llvm_context *ctx,
2672 LLVMValueRef dw_addr,
2673 unsigned param,
2674 unsigned const_index,
2675 bool compact_const_index,
2676 LLVMValueRef vertex_index,
2677 LLVMValueRef stride,
2678 LLVMValueRef indir_index)
2679
2680 {
2681
2682 if (vertex_index) {
2683 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2684 LLVMBuildMul(ctx->builder,
2685 vertex_index,
2686 stride, ""), "");
2687 }
2688
2689 if (indir_index)
2690 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2691 LLVMBuildMul(ctx->builder, indir_index,
2692 LLVMConstInt(ctx->i32, 4, false), ""), "");
2693 else if (const_index && !compact_const_index)
2694 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2695 LLVMConstInt(ctx->i32, const_index, false), "");
2696
2697 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2698 LLVMConstInt(ctx->i32, param * 4, false), "");
2699
2700 if (const_index && compact_const_index)
2701 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2702 LLVMConstInt(ctx->i32, const_index, false), "");
2703 return dw_addr;
2704 }
2705
2706 static LLVMValueRef
2707 load_tcs_input(struct nir_to_llvm_context *ctx,
2708 nir_intrinsic_instr *instr)
2709 {
2710 LLVMValueRef dw_addr, stride;
2711 unsigned const_index;
2712 LLVMValueRef vertex_index;
2713 LLVMValueRef indir_index;
2714 unsigned param;
2715 LLVMValueRef value[4], result;
2716 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2717 const bool is_compact = instr->variables[0]->var->data.compact;
2718 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2719 get_deref_offset(ctx->nir, instr->variables[0],
2720 false, NULL, per_vertex ? &vertex_index : NULL,
2721 &const_index, &indir_index);
2722
2723 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2724 dw_addr = get_tcs_in_current_patch_offset(ctx);
2725 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2726 indir_index);
2727
2728 for (unsigned i = 0; i < instr->num_components; i++) {
2729 value[i] = lds_load(ctx, dw_addr);
2730 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2731 ctx->i32one, "");
2732 }
2733 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2734 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2735 return result;
2736 }
2737
2738 static LLVMValueRef
2739 load_tcs_output(struct nir_to_llvm_context *ctx,
2740 nir_intrinsic_instr *instr)
2741 {
2742 LLVMValueRef dw_addr, stride;
2743 LLVMValueRef value[4], result;
2744 LLVMValueRef vertex_index = NULL;
2745 LLVMValueRef indir_index = NULL;
2746 unsigned const_index = 0;
2747 unsigned param;
2748 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2749 const bool is_compact = instr->variables[0]->var->data.compact;
2750 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2751 get_deref_offset(ctx->nir, instr->variables[0],
2752 false, NULL, per_vertex ? &vertex_index : NULL,
2753 &const_index, &indir_index);
2754
2755 if (!instr->variables[0]->var->data.patch) {
2756 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2757 dw_addr = get_tcs_out_current_patch_offset(ctx);
2758 } else {
2759 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2760 }
2761
2762 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2763 indir_index);
2764
2765 for (unsigned i = 0; i < instr->num_components; i++) {
2766 value[i] = lds_load(ctx, dw_addr);
2767 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2768 ctx->i32one, "");
2769 }
2770 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2771 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2772 return result;
2773 }
2774
2775 static void
2776 store_tcs_output(struct nir_to_llvm_context *ctx,
2777 nir_intrinsic_instr *instr,
2778 LLVMValueRef src,
2779 unsigned writemask)
2780 {
2781 LLVMValueRef stride, dw_addr;
2782 LLVMValueRef buf_addr = NULL;
2783 LLVMValueRef vertex_index = NULL;
2784 LLVMValueRef indir_index = NULL;
2785 unsigned const_index = 0;
2786 unsigned param;
2787 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2788 const bool is_compact = instr->variables[0]->var->data.compact;
2789
2790 get_deref_offset(ctx->nir, instr->variables[0],
2791 false, NULL, per_vertex ? &vertex_index : NULL,
2792 &const_index, &indir_index);
2793
2794 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2795 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2796 is_compact && const_index > 3) {
2797 const_index -= 3;
2798 param++;
2799 }
2800
2801 if (!instr->variables[0]->var->data.patch) {
2802 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2803 dw_addr = get_tcs_out_current_patch_offset(ctx);
2804 } else {
2805 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2806 }
2807
2808 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2809
2810 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2811 indir_index);
2812 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2813 vertex_index, indir_index);
2814
2815 unsigned base = is_compact ? const_index : 0;
2816 for (unsigned chan = 0; chan < 8; chan++) {
2817 bool is_tess_factor = false;
2818 if (!(writemask & (1 << chan)))
2819 continue;
2820 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan);
2821
2822 lds_store(ctx, dw_addr, value);
2823
2824 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2825 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2826 is_tess_factor = true;
2827
2828 if (!is_tess_factor && writemask != 0xF)
2829 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2830 buf_addr, ctx->oc_lds,
2831 4 * (base + chan), 1, 0, true, false);
2832
2833 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2834 ctx->i32one, "");
2835 }
2836
2837 if (writemask == 0xF) {
2838 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2839 buf_addr, ctx->oc_lds,
2840 (base * 4), 1, 0, true, false);
2841 }
2842 }
2843
2844 static LLVMValueRef
2845 load_tes_input(struct nir_to_llvm_context *ctx,
2846 const nir_intrinsic_instr *instr)
2847 {
2848 LLVMValueRef buf_addr;
2849 LLVMValueRef result;
2850 LLVMValueRef vertex_index = NULL;
2851 LLVMValueRef indir_index = NULL;
2852 unsigned const_index = 0;
2853 unsigned param;
2854 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2855 const bool is_compact = instr->variables[0]->var->data.compact;
2856
2857 get_deref_offset(ctx->nir, instr->variables[0],
2858 false, NULL, per_vertex ? &vertex_index : NULL,
2859 &const_index, &indir_index);
2860 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2861 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2862 is_compact && const_index > 3) {
2863 const_index -= 3;
2864 param++;
2865 }
2866 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2867 is_compact, vertex_index, indir_index);
2868
2869 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2870 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2871 result = trim_vector(&ctx->ac, result, instr->num_components);
2872 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2873 return result;
2874 }
2875
2876 static LLVMValueRef
2877 load_gs_input(struct nir_to_llvm_context *ctx,
2878 nir_intrinsic_instr *instr)
2879 {
2880 LLVMValueRef indir_index, vtx_offset;
2881 unsigned const_index;
2882 LLVMValueRef args[9];
2883 unsigned param, vtx_offset_param;
2884 LLVMValueRef value[4], result;
2885 unsigned vertex_index;
2886 get_deref_offset(ctx->nir, instr->variables[0],
2887 false, &vertex_index, NULL,
2888 &const_index, &indir_index);
2889 vtx_offset_param = vertex_index;
2890 assert(vtx_offset_param < 6);
2891 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2892 LLVMConstInt(ctx->i32, 4, false), "");
2893
2894 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2895 for (unsigned i = 0; i < instr->num_components; i++) {
2896
2897 args[0] = ctx->esgs_ring;
2898 args[1] = vtx_offset;
2899 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2900 args[3] = ctx->i32zero;
2901 args[4] = ctx->i32one; /* OFFEN */
2902 args[5] = ctx->i32zero; /* IDXEN */
2903 args[6] = ctx->i32one; /* GLC */
2904 args[7] = ctx->i32zero; /* SLC */
2905 args[8] = ctx->i32zero; /* TFE */
2906
2907 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2908 ctx->i32, args, 9,
2909 AC_FUNC_ATTR_READONLY |
2910 AC_FUNC_ATTR_LEGACY);
2911 }
2912 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2913
2914 return result;
2915 }
2916
2917 static LLVMValueRef
2918 build_gep_for_deref(struct ac_nir_context *ctx,
2919 nir_deref_var *deref)
2920 {
2921 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2922 assert(entry->data);
2923 LLVMValueRef val = entry->data;
2924 nir_deref *tail = deref->deref.child;
2925 while (tail != NULL) {
2926 LLVMValueRef offset;
2927 switch (tail->deref_type) {
2928 case nir_deref_type_array: {
2929 nir_deref_array *array = nir_deref_as_array(tail);
2930 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2931 if (array->deref_array_type ==
2932 nir_deref_array_type_indirect) {
2933 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2934 get_src(ctx,
2935 array->indirect),
2936 "");
2937 }
2938 break;
2939 }
2940 case nir_deref_type_struct: {
2941 nir_deref_struct *deref_struct =
2942 nir_deref_as_struct(tail);
2943 offset = LLVMConstInt(ctx->ac.i32,
2944 deref_struct->index, 0);
2945 break;
2946 }
2947 default:
2948 unreachable("bad deref type");
2949 }
2950 val = ac_build_gep0(&ctx->ac, val, offset);
2951 tail = tail->child;
2952 }
2953 return val;
2954 }
2955
2956 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
2957 nir_intrinsic_instr *instr)
2958 {
2959 LLVMValueRef values[8];
2960 int idx = instr->variables[0]->var->data.driver_location;
2961 int ve = instr->dest.ssa.num_components;
2962 LLVMValueRef indir_index;
2963 LLVMValueRef ret;
2964 unsigned const_index;
2965 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2966 instr->variables[0]->var->data.mode == nir_var_shader_in;
2967 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2968 &const_index, &indir_index);
2969
2970 if (instr->dest.ssa.bit_size == 64)
2971 ve *= 2;
2972
2973 switch (instr->variables[0]->var->data.mode) {
2974 case nir_var_shader_in:
2975 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2976 return load_tcs_input(ctx->nctx, instr);
2977 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2978 return load_tes_input(ctx->nctx, instr);
2979 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2980 return load_gs_input(ctx->nctx, instr);
2981 }
2982 for (unsigned chan = 0; chan < ve; chan++) {
2983 if (indir_index) {
2984 unsigned count = glsl_count_attribute_slots(
2985 instr->variables[0]->var->type,
2986 ctx->stage == MESA_SHADER_VERTEX);
2987 count -= chan / 4;
2988 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2989 &ctx->ac, ctx->abi->inputs + idx + chan, count,
2990 4, false);
2991
2992 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
2993 tmp_vec,
2994 indir_index, "");
2995 } else
2996 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
2997 }
2998 break;
2999 case nir_var_local:
3000 for (unsigned chan = 0; chan < ve; chan++) {
3001 if (indir_index) {
3002 unsigned count = glsl_count_attribute_slots(
3003 instr->variables[0]->var->type, false);
3004 count -= chan / 4;
3005 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3006 &ctx->ac, ctx->locals + idx + chan, count,
3007 4, true);
3008
3009 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3010 tmp_vec,
3011 indir_index, "");
3012 } else {
3013 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3014 }
3015 }
3016 break;
3017 case nir_var_shared: {
3018 LLVMValueRef address = build_gep_for_deref(ctx,
3019 instr->variables[0]);
3020 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3021 return LLVMBuildBitCast(ctx->ac.builder, val,
3022 get_def_type(ctx, &instr->dest.ssa),
3023 "");
3024 }
3025 case nir_var_shader_out:
3026 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3027 return load_tcs_output(ctx->nctx, instr);
3028 for (unsigned chan = 0; chan < ve; chan++) {
3029 if (indir_index) {
3030 unsigned count = glsl_count_attribute_slots(
3031 instr->variables[0]->var->type, false);
3032 count -= chan / 4;
3033 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3034 &ctx->ac, ctx->outputs + idx + chan, count,
3035 4, true);
3036
3037 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3038 tmp_vec,
3039 indir_index, "");
3040 } else {
3041 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3042 ctx->outputs[idx + chan + const_index * 4],
3043 "");
3044 }
3045 }
3046 break;
3047 default:
3048 unreachable("unhandle variable mode");
3049 }
3050 ret = ac_build_gather_values(&ctx->ac, values, ve);
3051 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3052 }
3053
3054 static void
3055 visit_store_var(struct ac_nir_context *ctx,
3056 nir_intrinsic_instr *instr)
3057 {
3058 LLVMValueRef temp_ptr, value;
3059 int idx = instr->variables[0]->var->data.driver_location;
3060 LLVMValueRef src = to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3061 int writemask = instr->const_index[0];
3062 LLVMValueRef indir_index;
3063 unsigned const_index;
3064 get_deref_offset(ctx, instr->variables[0], false,
3065 NULL, NULL, &const_index, &indir_index);
3066
3067 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3068 int old_writemask = writemask;
3069
3070 src = LLVMBuildBitCast(ctx->ac.builder, src,
3071 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3072 "");
3073
3074 writemask = 0;
3075 for (unsigned chan = 0; chan < 4; chan++) {
3076 if (old_writemask & (1 << chan))
3077 writemask |= 3u << (2 * chan);
3078 }
3079 }
3080
3081 switch (instr->variables[0]->var->data.mode) {
3082 case nir_var_shader_out:
3083
3084 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3085 store_tcs_output(ctx->nctx, instr, src, writemask);
3086 return;
3087 }
3088
3089 for (unsigned chan = 0; chan < 8; chan++) {
3090 int stride = 4;
3091 if (!(writemask & (1 << chan)))
3092 continue;
3093
3094 value = llvm_extract_elem(&ctx->ac, src, chan);
3095
3096 if (instr->variables[0]->var->data.compact)
3097 stride = 1;
3098 if (indir_index) {
3099 unsigned count = glsl_count_attribute_slots(
3100 instr->variables[0]->var->type, false);
3101 count -= chan / 4;
3102 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3103 &ctx->ac, ctx->outputs + idx + chan, count,
3104 stride, true);
3105
3106 if (get_llvm_num_components(tmp_vec) > 1) {
3107 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3108 value, indir_index, "");
3109 } else
3110 tmp_vec = value;
3111 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3112 count, stride, tmp_vec);
3113
3114 } else {
3115 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3116
3117 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3118 }
3119 }
3120 break;
3121 case nir_var_local:
3122 for (unsigned chan = 0; chan < 8; chan++) {
3123 if (!(writemask & (1 << chan)))
3124 continue;
3125
3126 value = llvm_extract_elem(&ctx->ac, src, chan);
3127 if (indir_index) {
3128 unsigned count = glsl_count_attribute_slots(
3129 instr->variables[0]->var->type, false);
3130 count -= chan / 4;
3131 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3132 &ctx->ac, ctx->locals + idx + chan, count,
3133 4, true);
3134
3135 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3136 value, indir_index, "");
3137 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3138 count, 4, tmp_vec);
3139 } else {
3140 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3141
3142 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3143 }
3144 }
3145 break;
3146 case nir_var_shared: {
3147 int writemask = instr->const_index[0];
3148 LLVMValueRef address = build_gep_for_deref(ctx,
3149 instr->variables[0]);
3150 LLVMValueRef val = get_src(ctx, instr->src[0]);
3151 unsigned components =
3152 glsl_get_vector_elements(
3153 nir_deref_tail(&instr->variables[0]->deref)->type);
3154 if (writemask == (1 << components) - 1) {
3155 val = LLVMBuildBitCast(
3156 ctx->ac.builder, val,
3157 LLVMGetElementType(LLVMTypeOf(address)), "");
3158 LLVMBuildStore(ctx->ac.builder, val, address);
3159 } else {
3160 for (unsigned chan = 0; chan < 4; chan++) {
3161 if (!(writemask & (1 << chan)))
3162 continue;
3163 LLVMValueRef ptr =
3164 LLVMBuildStructGEP(ctx->ac.builder,
3165 address, chan, "");
3166 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3167 chan);
3168 src = LLVMBuildBitCast(
3169 ctx->ac.builder, src,
3170 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3171 LLVMBuildStore(ctx->ac.builder, src, ptr);
3172 }
3173 }
3174 break;
3175 }
3176 default:
3177 break;
3178 }
3179 }
3180
3181 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3182 {
3183 switch (dim) {
3184 case GLSL_SAMPLER_DIM_BUF:
3185 return 1;
3186 case GLSL_SAMPLER_DIM_1D:
3187 return array ? 2 : 1;
3188 case GLSL_SAMPLER_DIM_2D:
3189 return array ? 3 : 2;
3190 case GLSL_SAMPLER_DIM_MS:
3191 return array ? 4 : 3;
3192 case GLSL_SAMPLER_DIM_3D:
3193 case GLSL_SAMPLER_DIM_CUBE:
3194 return 3;
3195 case GLSL_SAMPLER_DIM_RECT:
3196 case GLSL_SAMPLER_DIM_SUBPASS:
3197 return 2;
3198 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3199 return 3;
3200 default:
3201 break;
3202 }
3203 return 0;
3204 }
3205
3206
3207
3208 /* Adjust the sample index according to FMASK.
3209 *
3210 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3211 * which is the identity mapping. Each nibble says which physical sample
3212 * should be fetched to get that sample.
3213 *
3214 * For example, 0x11111100 means there are only 2 samples stored and
3215 * the second sample covers 3/4 of the pixel. When reading samples 0
3216 * and 1, return physical sample 0 (determined by the first two 0s
3217 * in FMASK), otherwise return physical sample 1.
3218 *
3219 * The sample index should be adjusted as follows:
3220 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3221 */
3222 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3223 LLVMValueRef coord_x, LLVMValueRef coord_y,
3224 LLVMValueRef coord_z,
3225 LLVMValueRef sample_index,
3226 LLVMValueRef fmask_desc_ptr)
3227 {
3228 LLVMValueRef fmask_load_address[4];
3229 LLVMValueRef res;
3230
3231 fmask_load_address[0] = coord_x;
3232 fmask_load_address[1] = coord_y;
3233 if (coord_z) {
3234 fmask_load_address[2] = coord_z;
3235 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3236 }
3237
3238 struct ac_image_args args = {0};
3239
3240 args.opcode = ac_image_load;
3241 args.da = coord_z ? true : false;
3242 args.resource = fmask_desc_ptr;
3243 args.dmask = 0xf;
3244 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3245
3246 res = ac_build_image_opcode(ctx, &args);
3247
3248 res = to_integer(ctx, res);
3249 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3250 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3251
3252 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3253 res,
3254 ctx->i32_0, "");
3255
3256 LLVMValueRef sample_index4 =
3257 LLVMBuildMul(ctx->builder, sample_index, four, "");
3258 LLVMValueRef shifted_fmask =
3259 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3260 LLVMValueRef final_sample =
3261 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3262
3263 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3264 * resource descriptor is 0 (invalid),
3265 */
3266 LLVMValueRef fmask_desc =
3267 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3268 ctx->v8i32, "");
3269
3270 LLVMValueRef fmask_word1 =
3271 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3272 ctx->i32_1, "");
3273
3274 LLVMValueRef word1_is_nonzero =
3275 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3276 fmask_word1, ctx->i32_0, "");
3277
3278 /* Replace the MSAA sample index. */
3279 sample_index =
3280 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3281 final_sample, sample_index, "");
3282 return sample_index;
3283 }
3284
3285 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3286 const nir_intrinsic_instr *instr)
3287 {
3288 const struct glsl_type *type = instr->variables[0]->var->type;
3289 if(instr->variables[0]->deref.child)
3290 type = instr->variables[0]->deref.child->type;
3291
3292 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3293 LLVMValueRef coords[4];
3294 LLVMValueRef masks[] = {
3295 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3296 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3297 };
3298 LLVMValueRef res;
3299 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3300
3301 int count;
3302 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3303 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3304 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3305 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3306 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3307
3308 count = image_type_to_components_count(dim,
3309 glsl_sampler_type_is_array(type));
3310
3311 if (is_ms) {
3312 LLVMValueRef fmask_load_address[3];
3313 int chan;
3314
3315 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3316 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3317 if (glsl_sampler_type_is_array(type))
3318 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3319 else
3320 fmask_load_address[2] = NULL;
3321 if (add_frag_pos) {
3322 for (chan = 0; chan < 2; ++chan)
3323 fmask_load_address[chan] = LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->nctx->frag_pos[chan], ctx->ac.i32, ""), "");
3324 }
3325 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3326 fmask_load_address[0],
3327 fmask_load_address[1],
3328 fmask_load_address[2],
3329 sample_index,
3330 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, true, false));
3331 }
3332 if (count == 1) {
3333 if (instr->src[0].ssa->num_components)
3334 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3335 else
3336 res = src0;
3337 } else {
3338 int chan;
3339 if (is_ms)
3340 count--;
3341 for (chan = 0; chan < count; ++chan) {
3342 coords[chan] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[chan], "");
3343 }
3344
3345 if (add_frag_pos) {
3346 for (chan = 0; chan < count; ++chan)
3347 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->nctx->frag_pos[chan], ctx->ac.i32, ""), "");
3348 }
3349 if (is_ms) {
3350 coords[count] = sample_index;
3351 count++;
3352 }
3353
3354 if (count == 3) {
3355 coords[3] = LLVMGetUndef(ctx->ac.i32);
3356 count = 4;
3357 }
3358 res = ac_build_gather_values(&ctx->ac, coords, count);
3359 }
3360 return res;
3361 }
3362
3363 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3364 const nir_intrinsic_instr *instr)
3365 {
3366 LLVMValueRef params[7];
3367 LLVMValueRef res;
3368 char intrinsic_name[64];
3369 const nir_variable *var = instr->variables[0]->var;
3370 const struct glsl_type *type = var->type;
3371 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3372 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3373
3374 if(instr->variables[0]->deref.child)
3375 type = instr->variables[0]->deref.child->type;
3376
3377 type = glsl_without_array(type);
3378 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3379 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, false);
3380 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3381 ctx->ac.i32_0, ""); /* vindex */
3382 params[2] = ctx->ac.i32_0; /* voffset */
3383 params[3] = i1false; /* glc */
3384 params[4] = i1false; /* slc */
3385 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3386 params, 5, 0);
3387
3388 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3389 res = to_integer(&ctx->ac, res);
3390 } else {
3391 bool is_da = glsl_sampler_type_is_array(type) ||
3392 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3393 LLVMValueRef da = is_da ? i1true : i1false;
3394 LLVMValueRef glc = i1false;
3395 LLVMValueRef slc = i1false;
3396
3397 params[0] = get_image_coords(ctx, instr);
3398 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3399 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3400 if (HAVE_LLVM <= 0x0309) {
3401 params[3] = i1false; /* r128 */
3402 params[4] = da;
3403 params[5] = glc;
3404 params[6] = slc;
3405 } else {
3406 LLVMValueRef lwe = i1false;
3407 params[3] = glc;
3408 params[4] = slc;
3409 params[5] = lwe;
3410 params[6] = da;
3411 }
3412
3413 ac_get_image_intr_name("llvm.amdgcn.image.load",
3414 ctx->ac.v4f32, /* vdata */
3415 LLVMTypeOf(params[0]), /* coords */
3416 LLVMTypeOf(params[1]), /* rsrc */
3417 intrinsic_name, sizeof(intrinsic_name));
3418
3419 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3420 params, 7, AC_FUNC_ATTR_READONLY);
3421 }
3422 return to_integer(&ctx->ac, res);
3423 }
3424
3425 static void visit_image_store(struct ac_nir_context *ctx,
3426 nir_intrinsic_instr *instr)
3427 {
3428 LLVMValueRef params[8];
3429 char intrinsic_name[64];
3430 const nir_variable *var = instr->variables[0]->var;
3431 const struct glsl_type *type = glsl_without_array(var->type);
3432 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3433 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3434 LLVMValueRef glc = i1false;
3435 bool force_glc = ctx->abi->chip_class == SI;
3436 if (force_glc)
3437 glc = i1true;
3438
3439 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3440 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3441 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, true);
3442 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3443 ctx->ac.i32_0, ""); /* vindex */
3444 params[3] = ctx->ac.i32_0; /* voffset */
3445 params[4] = glc; /* glc */
3446 params[5] = i1false; /* slc */
3447 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3448 params, 6, 0);
3449 } else {
3450 bool is_da = glsl_sampler_type_is_array(type) ||
3451 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3452 LLVMValueRef da = is_da ? i1true : i1false;
3453 LLVMValueRef slc = i1false;
3454
3455 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3456 params[1] = get_image_coords(ctx, instr); /* coords */
3457 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, true);
3458 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3459 if (HAVE_LLVM <= 0x0309) {
3460 params[4] = i1false; /* r128 */
3461 params[5] = da;
3462 params[6] = glc;
3463 params[7] = slc;
3464 } else {
3465 LLVMValueRef lwe = i1false;
3466 params[4] = glc;
3467 params[5] = slc;
3468 params[6] = lwe;
3469 params[7] = da;
3470 }
3471
3472 ac_get_image_intr_name("llvm.amdgcn.image.store",
3473 LLVMTypeOf(params[0]), /* vdata */
3474 LLVMTypeOf(params[1]), /* coords */
3475 LLVMTypeOf(params[2]), /* rsrc */
3476 intrinsic_name, sizeof(intrinsic_name));
3477
3478 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3479 params, 8, 0);
3480 }
3481
3482 }
3483
3484 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3485 const nir_intrinsic_instr *instr)
3486 {
3487 LLVMValueRef params[6];
3488 int param_count = 0;
3489 const nir_variable *var = instr->variables[0]->var;
3490
3491 const char *atomic_name;
3492 char intrinsic_name[41];
3493 const struct glsl_type *type = glsl_without_array(var->type);
3494 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3495 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3496 MAYBE_UNUSED int length;
3497
3498 switch (instr->intrinsic) {
3499 case nir_intrinsic_image_atomic_add:
3500 atomic_name = "add";
3501 break;
3502 case nir_intrinsic_image_atomic_min:
3503 atomic_name = "smin";
3504 break;
3505 case nir_intrinsic_image_atomic_max:
3506 atomic_name = "smax";
3507 break;
3508 case nir_intrinsic_image_atomic_and:
3509 atomic_name = "and";
3510 break;
3511 case nir_intrinsic_image_atomic_or:
3512 atomic_name = "or";
3513 break;
3514 case nir_intrinsic_image_atomic_xor:
3515 atomic_name = "xor";
3516 break;
3517 case nir_intrinsic_image_atomic_exchange:
3518 atomic_name = "swap";
3519 break;
3520 case nir_intrinsic_image_atomic_comp_swap:
3521 atomic_name = "cmpswap";
3522 break;
3523 default:
3524 abort();
3525 }
3526
3527 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3528 params[param_count++] = get_src(ctx, instr->src[3]);
3529 params[param_count++] = get_src(ctx, instr->src[2]);
3530
3531 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3532 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3533 true, true);
3534 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3535 ctx->ac.i32_0, ""); /* vindex */
3536 params[param_count++] = ctx->ac.i32_0; /* voffset */
3537 params[param_count++] = i1false; /* slc */
3538
3539 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3540 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3541 } else {
3542 char coords_type[8];
3543
3544 bool da = glsl_sampler_type_is_array(type) ||
3545 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3546
3547 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3548 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3549 true, true);
3550 params[param_count++] = i1false; /* r128 */
3551 params[param_count++] = da ? i1true : i1false; /* da */
3552 params[param_count++] = i1false; /* slc */
3553
3554 build_int_type_name(LLVMTypeOf(coords),
3555 coords_type, sizeof(coords_type));
3556
3557 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3558 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3559 }
3560
3561 assert(length < sizeof(intrinsic_name));
3562 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3563 }
3564
3565 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3566 const nir_intrinsic_instr *instr)
3567 {
3568 LLVMValueRef res;
3569 const nir_variable *var = instr->variables[0]->var;
3570 const struct glsl_type *type = instr->variables[0]->var->type;
3571 bool da = glsl_sampler_type_is_array(var->type) ||
3572 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3573 if(instr->variables[0]->deref.child)
3574 type = instr->variables[0]->deref.child->type;
3575
3576 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3577 return get_buffer_size(ctx,
3578 get_sampler_desc(ctx, instr->variables[0],
3579 AC_DESC_BUFFER, true, false), true);
3580
3581 struct ac_image_args args = { 0 };
3582
3583 args.da = da;
3584 args.dmask = 0xf;
3585 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3586 args.opcode = ac_image_get_resinfo;
3587 args.addr = ctx->ac.i32_0;
3588
3589 res = ac_build_image_opcode(&ctx->ac, &args);
3590
3591 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3592 glsl_sampler_type_is_array(type)) {
3593 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3594 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3595 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3596 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3597 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3598 }
3599 return res;
3600 }
3601
3602 #define NOOP_WAITCNT 0xf7f
3603 #define LGKM_CNT 0x07f
3604 #define VM_CNT 0xf70
3605
3606 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3607 unsigned simm16)
3608 {
3609 LLVMValueRef args[1] = {
3610 LLVMConstInt(ctx->i32, simm16, false),
3611 };
3612 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3613 ctx->voidt, args, 1, 0);
3614 }
3615
3616 static void emit_barrier(struct nir_to_llvm_context *ctx)
3617 {
3618 /* SI only (thanks to a hw bug workaround):
3619 * The real barrier instruction isn’t needed, because an entire patch
3620 * always fits into a single wave.
3621 */
3622 if (ctx->options->chip_class == SI &&
3623 ctx->stage == MESA_SHADER_TESS_CTRL) {
3624 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3625 return;
3626 }
3627 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3628 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3629 }
3630
3631 static void emit_discard_if(struct ac_nir_context *ctx,
3632 const nir_intrinsic_instr *instr)
3633 {
3634 LLVMValueRef cond;
3635
3636 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
3637 get_src(ctx, instr->src[0]),
3638 ctx->ac.i32_0, "");
3639
3640 cond = LLVMBuildSelect(ctx->ac.builder, cond,
3641 LLVMConstReal(ctx->ac.f32, -1.0f),
3642 ctx->ac.f32_0, "");
3643 ac_build_kill(&ctx->ac, cond);
3644 }
3645
3646 static LLVMValueRef
3647 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3648 {
3649 LLVMValueRef result;
3650 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3651 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3652 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3653
3654 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3655 }
3656
3657 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3658 const nir_intrinsic_instr *instr)
3659 {
3660 LLVMValueRef ptr, result;
3661 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3662 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3663
3664 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3665 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3666 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3667 ptr, src, src1,
3668 LLVMAtomicOrderingSequentiallyConsistent,
3669 LLVMAtomicOrderingSequentiallyConsistent,
3670 false);
3671 } else {
3672 LLVMAtomicRMWBinOp op;
3673 switch (instr->intrinsic) {
3674 case nir_intrinsic_var_atomic_add:
3675 op = LLVMAtomicRMWBinOpAdd;
3676 break;
3677 case nir_intrinsic_var_atomic_umin:
3678 op = LLVMAtomicRMWBinOpUMin;
3679 break;
3680 case nir_intrinsic_var_atomic_umax:
3681 op = LLVMAtomicRMWBinOpUMax;
3682 break;
3683 case nir_intrinsic_var_atomic_imin:
3684 op = LLVMAtomicRMWBinOpMin;
3685 break;
3686 case nir_intrinsic_var_atomic_imax:
3687 op = LLVMAtomicRMWBinOpMax;
3688 break;
3689 case nir_intrinsic_var_atomic_and:
3690 op = LLVMAtomicRMWBinOpAnd;
3691 break;
3692 case nir_intrinsic_var_atomic_or:
3693 op = LLVMAtomicRMWBinOpOr;
3694 break;
3695 case nir_intrinsic_var_atomic_xor:
3696 op = LLVMAtomicRMWBinOpXor;
3697 break;
3698 case nir_intrinsic_var_atomic_exchange:
3699 op = LLVMAtomicRMWBinOpXchg;
3700 break;
3701 default:
3702 return NULL;
3703 }
3704
3705 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(&ctx->ac, src),
3706 LLVMAtomicOrderingSequentiallyConsistent,
3707 false);
3708 }
3709 return result;
3710 }
3711
3712 #define INTERP_CENTER 0
3713 #define INTERP_CENTROID 1
3714 #define INTERP_SAMPLE 2
3715
3716 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3717 enum glsl_interp_mode interp, unsigned location)
3718 {
3719 switch (interp) {
3720 case INTERP_MODE_FLAT:
3721 default:
3722 return NULL;
3723 case INTERP_MODE_SMOOTH:
3724 case INTERP_MODE_NONE:
3725 if (location == INTERP_CENTER)
3726 return ctx->persp_center;
3727 else if (location == INTERP_CENTROID)
3728 return ctx->persp_centroid;
3729 else if (location == INTERP_SAMPLE)
3730 return ctx->persp_sample;
3731 break;
3732 case INTERP_MODE_NOPERSPECTIVE:
3733 if (location == INTERP_CENTER)
3734 return ctx->linear_center;
3735 else if (location == INTERP_CENTROID)
3736 return ctx->linear_centroid;
3737 else if (location == INTERP_SAMPLE)
3738 return ctx->linear_sample;
3739 break;
3740 }
3741 return NULL;
3742 }
3743
3744 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3745 LLVMValueRef sample_id)
3746 {
3747 LLVMValueRef result;
3748 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3749
3750 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3751 const_array(ctx->v2f32, 64), "");
3752
3753 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3754 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3755
3756 return result;
3757 }
3758
3759 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3760 {
3761 LLVMValueRef values[2];
3762
3763 values[0] = emit_ffract(&ctx->ac, ctx->frag_pos[0]);
3764 values[1] = emit_ffract(&ctx->ac, ctx->frag_pos[1]);
3765 return ac_build_gather_values(&ctx->ac, values, 2);
3766 }
3767
3768 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3769 const nir_intrinsic_instr *instr)
3770 {
3771 LLVMValueRef result[2];
3772 LLVMValueRef interp_param, attr_number;
3773 unsigned location;
3774 unsigned chan;
3775 LLVMValueRef src_c0, src_c1;
3776 LLVMValueRef src0;
3777 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3778 switch (instr->intrinsic) {
3779 case nir_intrinsic_interp_var_at_centroid:
3780 location = INTERP_CENTROID;
3781 break;
3782 case nir_intrinsic_interp_var_at_sample:
3783 case nir_intrinsic_interp_var_at_offset:
3784 location = INTERP_CENTER;
3785 src0 = get_src(ctx->nir, instr->src[0]);
3786 break;
3787 default:
3788 break;
3789 }
3790
3791 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3792 src_c0 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3793 src_c1 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3794 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3795 LLVMValueRef sample_position;
3796 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3797
3798 /* fetch sample ID */
3799 sample_position = load_sample_position(ctx, src0);
3800
3801 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3802 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3803 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3804 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3805 }
3806 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3807 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3808
3809 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3810 LLVMValueRef ij_out[2];
3811 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3812
3813 /*
3814 * take the I then J parameters, and the DDX/Y for it, and
3815 * calculate the IJ inputs for the interpolator.
3816 * temp1 = ddx * offset/sample.x + I;
3817 * interp_param.I = ddy * offset/sample.y + temp1;
3818 * temp1 = ddx * offset/sample.x + J;
3819 * interp_param.J = ddy * offset/sample.y + temp1;
3820 */
3821 for (unsigned i = 0; i < 2; i++) {
3822 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3823 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3824 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3825 ddxy_out, ix_ll, "");
3826 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3827 ddxy_out, iy_ll, "");
3828 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3829 interp_param, ix_ll, "");
3830 LLVMValueRef temp1, temp2;
3831
3832 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3833 ctx->f32, "");
3834
3835 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3836 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3837
3838 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3839 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3840
3841 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3842 temp2, ctx->i32, "");
3843 }
3844 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3845
3846 }
3847
3848 for (chan = 0; chan < 2; chan++) {
3849 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3850
3851 if (interp_param) {
3852 interp_param = LLVMBuildBitCast(ctx->builder,
3853 interp_param, LLVMVectorType(ctx->f32, 2), "");
3854 LLVMValueRef i = LLVMBuildExtractElement(
3855 ctx->builder, interp_param, ctx->i32zero, "");
3856 LLVMValueRef j = LLVMBuildExtractElement(
3857 ctx->builder, interp_param, ctx->i32one, "");
3858
3859 result[chan] = ac_build_fs_interp(&ctx->ac,
3860 llvm_chan, attr_number,
3861 ctx->prim_mask, i, j);
3862 } else {
3863 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3864 LLVMConstInt(ctx->i32, 2, false),
3865 llvm_chan, attr_number,
3866 ctx->prim_mask);
3867 }
3868 }
3869 return ac_build_gather_values(&ctx->ac, result, 2);
3870 }
3871
3872 static void
3873 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3874 const nir_intrinsic_instr *instr)
3875 {
3876 LLVMValueRef gs_next_vertex;
3877 LLVMValueRef can_emit, kill;
3878 int idx;
3879
3880 assert(instr->const_index[0] == 0);
3881 /* Write vertex attribute values to GSVS ring */
3882 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3883 ctx->gs_next_vertex,
3884 "");
3885
3886 /* If this thread has already emitted the declared maximum number of
3887 * vertices, kill it: excessive vertex emissions are not supposed to
3888 * have any effect, and GS threads have no externally observable
3889 * effects other than emitting vertices.
3890 */
3891 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3892 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3893
3894 kill = LLVMBuildSelect(ctx->builder, can_emit,
3895 LLVMConstReal(ctx->f32, 1.0f),
3896 LLVMConstReal(ctx->f32, -1.0f), "");
3897 ac_build_kill(&ctx->ac, kill);
3898
3899 /* loop num outputs */
3900 idx = 0;
3901 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3902 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
3903 int length = 4;
3904 int slot = idx;
3905 int slot_inc = 1;
3906
3907 if (!(ctx->output_mask & (1ull << i)))
3908 continue;
3909
3910 if (i == VARYING_SLOT_CLIP_DIST0) {
3911 /* pack clip and cull into a single set of slots */
3912 length = ctx->num_output_clips + ctx->num_output_culls;
3913 if (length > 4)
3914 slot_inc = 2;
3915 }
3916 for (unsigned j = 0; j < length; j++) {
3917 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3918 out_ptr[j], "");
3919 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3920 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3921 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3922
3923 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3924
3925 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3926 out_val, 1,
3927 voffset, ctx->gs2vs_offset, 0,
3928 1, 1, true, true);
3929 }
3930 idx += slot_inc;
3931 }
3932
3933 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3934 ctx->i32one, "");
3935 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3936
3937 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3938 }
3939
3940 static void
3941 visit_end_primitive(struct nir_to_llvm_context *ctx,
3942 const nir_intrinsic_instr *instr)
3943 {
3944 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3945 }
3946
3947 static LLVMValueRef
3948 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3949 const nir_intrinsic_instr *instr)
3950 {
3951 LLVMValueRef coord[4] = {
3952 ctx->tes_u,
3953 ctx->tes_v,
3954 ctx->f32zero,
3955 ctx->f32zero,
3956 };
3957
3958 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3959 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3960 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3961
3962 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3963 return LLVMBuildBitCast(ctx->builder, result,
3964 get_def_type(ctx->nir, &instr->dest.ssa), "");
3965 }
3966
3967 static void visit_intrinsic(struct ac_nir_context *ctx,
3968 nir_intrinsic_instr *instr)
3969 {
3970 LLVMValueRef result = NULL;
3971
3972 switch (instr->intrinsic) {
3973 case nir_intrinsic_load_work_group_id: {
3974 result = ctx->nctx->workgroup_ids;
3975 break;
3976 }
3977 case nir_intrinsic_load_base_vertex: {
3978 result = ctx->abi->base_vertex;
3979 break;
3980 }
3981 case nir_intrinsic_load_vertex_id_zero_base: {
3982 result = ctx->abi->vertex_id;
3983 break;
3984 }
3985 case nir_intrinsic_load_local_invocation_id: {
3986 result = ctx->nctx->local_invocation_ids;
3987 break;
3988 }
3989 case nir_intrinsic_load_base_instance:
3990 result = ctx->abi->start_instance;
3991 break;
3992 case nir_intrinsic_load_draw_id:
3993 result = ctx->abi->draw_id;
3994 break;
3995 case nir_intrinsic_load_invocation_id:
3996 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3997 result = unpack_param(ctx->nctx, ctx->nctx->tcs_rel_ids, 8, 5);
3998 else
3999 result = ctx->nctx->gs_invocation_id;
4000 break;
4001 case nir_intrinsic_load_primitive_id:
4002 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4003 ctx->nctx->shader_info->gs.uses_prim_id = true;
4004 result = ctx->nctx->gs_prim_id;
4005 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4006 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4007 result = ctx->nctx->tcs_patch_id;
4008 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4009 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4010 result = ctx->nctx->tes_patch_id;
4011 } else
4012 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4013 break;
4014 case nir_intrinsic_load_sample_id:
4015 ctx->nctx->shader_info->fs.force_persample = true;
4016 result = unpack_param(ctx->nctx, ctx->nctx->ancillary, 8, 4);
4017 break;
4018 case nir_intrinsic_load_sample_pos:
4019 ctx->nctx->shader_info->fs.force_persample = true;
4020 result = load_sample_pos(ctx->nctx);
4021 break;
4022 case nir_intrinsic_load_sample_mask_in:
4023 result = ctx->nctx->sample_coverage;
4024 break;
4025 case nir_intrinsic_load_front_face:
4026 result = ctx->nctx->front_face;
4027 break;
4028 case nir_intrinsic_load_instance_id:
4029 result = ctx->abi->instance_id;
4030 break;
4031 case nir_intrinsic_load_num_work_groups:
4032 result = ctx->nctx->num_work_groups;
4033 break;
4034 case nir_intrinsic_load_local_invocation_index:
4035 result = visit_load_local_invocation_index(ctx->nctx);
4036 break;
4037 case nir_intrinsic_load_push_constant:
4038 result = visit_load_push_constant(ctx->nctx, instr);
4039 break;
4040 case nir_intrinsic_vulkan_resource_index:
4041 result = visit_vulkan_resource_index(ctx->nctx, instr);
4042 break;
4043 case nir_intrinsic_store_ssbo:
4044 visit_store_ssbo(ctx, instr);
4045 break;
4046 case nir_intrinsic_load_ssbo:
4047 result = visit_load_buffer(ctx, instr);
4048 break;
4049 case nir_intrinsic_ssbo_atomic_add:
4050 case nir_intrinsic_ssbo_atomic_imin:
4051 case nir_intrinsic_ssbo_atomic_umin:
4052 case nir_intrinsic_ssbo_atomic_imax:
4053 case nir_intrinsic_ssbo_atomic_umax:
4054 case nir_intrinsic_ssbo_atomic_and:
4055 case nir_intrinsic_ssbo_atomic_or:
4056 case nir_intrinsic_ssbo_atomic_xor:
4057 case nir_intrinsic_ssbo_atomic_exchange:
4058 case nir_intrinsic_ssbo_atomic_comp_swap:
4059 result = visit_atomic_ssbo(ctx, instr);
4060 break;
4061 case nir_intrinsic_load_ubo:
4062 result = visit_load_ubo_buffer(ctx, instr);
4063 break;
4064 case nir_intrinsic_get_buffer_size:
4065 result = visit_get_buffer_size(ctx, instr);
4066 break;
4067 case nir_intrinsic_load_var:
4068 result = visit_load_var(ctx, instr);
4069 break;
4070 case nir_intrinsic_store_var:
4071 visit_store_var(ctx, instr);
4072 break;
4073 case nir_intrinsic_image_load:
4074 result = visit_image_load(ctx, instr);
4075 break;
4076 case nir_intrinsic_image_store:
4077 visit_image_store(ctx, instr);
4078 break;
4079 case nir_intrinsic_image_atomic_add:
4080 case nir_intrinsic_image_atomic_min:
4081 case nir_intrinsic_image_atomic_max:
4082 case nir_intrinsic_image_atomic_and:
4083 case nir_intrinsic_image_atomic_or:
4084 case nir_intrinsic_image_atomic_xor:
4085 case nir_intrinsic_image_atomic_exchange:
4086 case nir_intrinsic_image_atomic_comp_swap:
4087 result = visit_image_atomic(ctx, instr);
4088 break;
4089 case nir_intrinsic_image_size:
4090 result = visit_image_size(ctx, instr);
4091 break;
4092 case nir_intrinsic_discard:
4093 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4094 LLVMVoidTypeInContext(ctx->ac.context),
4095 NULL, 0, AC_FUNC_ATTR_LEGACY);
4096 break;
4097 case nir_intrinsic_discard_if:
4098 emit_discard_if(ctx, instr);
4099 break;
4100 case nir_intrinsic_memory_barrier:
4101 emit_waitcnt(ctx->nctx, VM_CNT);
4102 break;
4103 case nir_intrinsic_barrier:
4104 emit_barrier(ctx->nctx);
4105 break;
4106 case nir_intrinsic_var_atomic_add:
4107 case nir_intrinsic_var_atomic_imin:
4108 case nir_intrinsic_var_atomic_umin:
4109 case nir_intrinsic_var_atomic_imax:
4110 case nir_intrinsic_var_atomic_umax:
4111 case nir_intrinsic_var_atomic_and:
4112 case nir_intrinsic_var_atomic_or:
4113 case nir_intrinsic_var_atomic_xor:
4114 case nir_intrinsic_var_atomic_exchange:
4115 case nir_intrinsic_var_atomic_comp_swap:
4116 result = visit_var_atomic(ctx->nctx, instr);
4117 break;
4118 case nir_intrinsic_interp_var_at_centroid:
4119 case nir_intrinsic_interp_var_at_sample:
4120 case nir_intrinsic_interp_var_at_offset:
4121 result = visit_interp(ctx->nctx, instr);
4122 break;
4123 case nir_intrinsic_emit_vertex:
4124 visit_emit_vertex(ctx->nctx, instr);
4125 break;
4126 case nir_intrinsic_end_primitive:
4127 visit_end_primitive(ctx->nctx, instr);
4128 break;
4129 case nir_intrinsic_load_tess_coord:
4130 result = visit_load_tess_coord(ctx->nctx, instr);
4131 break;
4132 case nir_intrinsic_load_patch_vertices_in:
4133 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4134 break;
4135 default:
4136 fprintf(stderr, "Unknown intrinsic: ");
4137 nir_print_instr(&instr->instr, stderr);
4138 fprintf(stderr, "\n");
4139 break;
4140 }
4141 if (result) {
4142 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4143 }
4144 }
4145
4146 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4147 LLVMValueRef buffer, bool write)
4148 {
4149 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4150
4151 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4152 ctx->shader_info->fs.writes_memory = true;
4153
4154 return buffer;
4155 }
4156
4157 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4158 unsigned descriptor_set,
4159 unsigned base_index,
4160 unsigned constant_index,
4161 LLVMValueRef index,
4162 enum ac_descriptor_type desc_type,
4163 bool image, bool write)
4164 {
4165 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4166 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4167 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4168 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4169 unsigned offset = binding->offset;
4170 unsigned stride = binding->size;
4171 unsigned type_size;
4172 LLVMBuilderRef builder = ctx->builder;
4173 LLVMTypeRef type;
4174
4175 assert(base_index < layout->binding_count);
4176
4177 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4178 ctx->shader_info->fs.writes_memory = true;
4179
4180 switch (desc_type) {
4181 case AC_DESC_IMAGE:
4182 type = ctx->v8i32;
4183 type_size = 32;
4184 break;
4185 case AC_DESC_FMASK:
4186 type = ctx->v8i32;
4187 offset += 32;
4188 type_size = 32;
4189 break;
4190 case AC_DESC_SAMPLER:
4191 type = ctx->v4i32;
4192 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4193 offset += 64;
4194
4195 type_size = 16;
4196 break;
4197 case AC_DESC_BUFFER:
4198 type = ctx->v4i32;
4199 type_size = 16;
4200 break;
4201 default:
4202 unreachable("invalid desc_type\n");
4203 }
4204
4205 offset += constant_index * stride;
4206
4207 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4208 (!index || binding->immutable_samplers_equal)) {
4209 if (binding->immutable_samplers_equal)
4210 constant_index = 0;
4211
4212 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4213
4214 LLVMValueRef constants[] = {
4215 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4216 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4217 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4218 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4219 };
4220 return ac_build_gather_values(&ctx->ac, constants, 4);
4221 }
4222
4223 assert(stride % type_size == 0);
4224
4225 if (!index)
4226 index = ctx->i32zero;
4227
4228 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4229
4230 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4231 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4232
4233 return ac_build_indexed_load_const(&ctx->ac, list, index);
4234 }
4235
4236 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4237 const nir_deref_var *deref,
4238 enum ac_descriptor_type desc_type,
4239 bool image, bool write)
4240 {
4241 LLVMValueRef index = NULL;
4242 unsigned constant_index = 0;
4243 const nir_deref *tail = &deref->deref;
4244
4245 while (tail->child) {
4246 const nir_deref_array *child = nir_deref_as_array(tail->child);
4247 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4248
4249 if (!array_size)
4250 array_size = 1;
4251
4252 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4253
4254 if (child->deref_array_type == nir_deref_array_type_indirect) {
4255 LLVMValueRef indirect = get_src(ctx, child->indirect);
4256
4257 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4258 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4259
4260 if (!index)
4261 index = indirect;
4262 else
4263 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4264 }
4265
4266 constant_index += child->base_offset * array_size;
4267
4268 tail = &child->deref;
4269 }
4270
4271 return ctx->abi->load_sampler_desc(ctx->abi,
4272 deref->var->data.descriptor_set,
4273 deref->var->data.binding,
4274 constant_index, index,
4275 desc_type, image, write);
4276 }
4277
4278 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4279 struct ac_image_args *args,
4280 const nir_tex_instr *instr,
4281 nir_texop op,
4282 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4283 LLVMValueRef *param, unsigned count,
4284 unsigned dmask)
4285 {
4286 unsigned is_rect = 0;
4287 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4288
4289 if (op == nir_texop_lod)
4290 da = false;
4291 /* Pad to power of two vector */
4292 while (count < util_next_power_of_two(count))
4293 param[count++] = LLVMGetUndef(ctx->i32);
4294
4295 if (count > 1)
4296 args->addr = ac_build_gather_values(ctx, param, count);
4297 else
4298 args->addr = param[0];
4299
4300 args->resource = res_ptr;
4301 args->sampler = samp_ptr;
4302
4303 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4304 args->addr = param[0];
4305 return;
4306 }
4307
4308 args->dmask = dmask;
4309 args->unorm = is_rect;
4310 args->da = da;
4311 }
4312
4313 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4314 *
4315 * SI-CI:
4316 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4317 * filtering manually. The driver sets img7 to a mask clearing
4318 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4319 * s_and_b32 samp0, samp0, img7
4320 *
4321 * VI:
4322 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4323 */
4324 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4325 LLVMValueRef res, LLVMValueRef samp)
4326 {
4327 LLVMBuilderRef builder = ctx->ac.builder;
4328 LLVMValueRef img7, samp0;
4329
4330 if (ctx->abi->chip_class >= VI)
4331 return samp;
4332
4333 img7 = LLVMBuildExtractElement(builder, res,
4334 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4335 samp0 = LLVMBuildExtractElement(builder, samp,
4336 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4337 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4338 return LLVMBuildInsertElement(builder, samp, samp0,
4339 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4340 }
4341
4342 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4343 nir_tex_instr *instr,
4344 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4345 LLVMValueRef *fmask_ptr)
4346 {
4347 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4348 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, false, false);
4349 else
4350 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, false, false);
4351 if (samp_ptr) {
4352 if (instr->sampler)
4353 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, false, false);
4354 else
4355 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, false, false);
4356 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4357 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4358 }
4359 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4360 instr->op == nir_texop_samples_identical))
4361 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, false, false);
4362 }
4363
4364 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4365 LLVMValueRef coord)
4366 {
4367 coord = to_float(ctx, coord);
4368 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4369 coord = to_integer(ctx, coord);
4370 return coord;
4371 }
4372
4373 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4374 {
4375 LLVMValueRef result = NULL;
4376 struct ac_image_args args = { 0 };
4377 unsigned dmask = 0xf;
4378 LLVMValueRef address[16];
4379 LLVMValueRef coords[5];
4380 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4381 LLVMValueRef bias = NULL, offsets = NULL;
4382 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4383 LLVMValueRef ddx = NULL, ddy = NULL;
4384 LLVMValueRef derivs[6];
4385 unsigned chan, count = 0;
4386 unsigned const_src = 0, num_deriv_comp = 0;
4387 bool lod_is_zero = false;
4388
4389 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4390
4391 for (unsigned i = 0; i < instr->num_srcs; i++) {
4392 switch (instr->src[i].src_type) {
4393 case nir_tex_src_coord:
4394 coord = get_src(ctx, instr->src[i].src);
4395 break;
4396 case nir_tex_src_projector:
4397 break;
4398 case nir_tex_src_comparator:
4399 comparator = get_src(ctx, instr->src[i].src);
4400 break;
4401 case nir_tex_src_offset:
4402 offsets = get_src(ctx, instr->src[i].src);
4403 const_src = i;
4404 break;
4405 case nir_tex_src_bias:
4406 bias = get_src(ctx, instr->src[i].src);
4407 break;
4408 case nir_tex_src_lod: {
4409 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4410
4411 if (val && val->i32[0] == 0)
4412 lod_is_zero = true;
4413 lod = get_src(ctx, instr->src[i].src);
4414 break;
4415 }
4416 case nir_tex_src_ms_index:
4417 sample_index = get_src(ctx, instr->src[i].src);
4418 break;
4419 case nir_tex_src_ms_mcs:
4420 break;
4421 case nir_tex_src_ddx:
4422 ddx = get_src(ctx, instr->src[i].src);
4423 num_deriv_comp = instr->src[i].src.ssa->num_components;
4424 break;
4425 case nir_tex_src_ddy:
4426 ddy = get_src(ctx, instr->src[i].src);
4427 break;
4428 case nir_tex_src_texture_offset:
4429 case nir_tex_src_sampler_offset:
4430 case nir_tex_src_plane:
4431 default:
4432 break;
4433 }
4434 }
4435
4436 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4437 result = get_buffer_size(ctx, res_ptr, true);
4438 goto write_result;
4439 }
4440
4441 if (instr->op == nir_texop_texture_samples) {
4442 LLVMValueRef res, samples, is_msaa;
4443 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4444 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4445 LLVMConstInt(ctx->ac.i32, 3, false), "");
4446 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4447 LLVMConstInt(ctx->ac.i32, 28, false), "");
4448 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4449 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4450 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4451 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4452
4453 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4454 LLVMConstInt(ctx->ac.i32, 16, false), "");
4455 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4456 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4457 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4458 samples, "");
4459 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4460 ctx->ac.i32_1, "");
4461 result = samples;
4462 goto write_result;
4463 }
4464
4465 if (coord)
4466 for (chan = 0; chan < instr->coord_components; chan++)
4467 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4468
4469 if (offsets && instr->op != nir_texop_txf) {
4470 LLVMValueRef offset[3], pack;
4471 for (chan = 0; chan < 3; ++chan)
4472 offset[chan] = ctx->ac.i32_0;
4473
4474 args.offset = true;
4475 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4476 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4477 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4478 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4479 if (chan)
4480 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4481 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4482 }
4483 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4484 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4485 address[count++] = pack;
4486
4487 }
4488 /* pack LOD bias value */
4489 if (instr->op == nir_texop_txb && bias) {
4490 address[count++] = bias;
4491 }
4492
4493 /* Pack depth comparison value */
4494 if (instr->is_shadow && comparator) {
4495 address[count++] = llvm_extract_elem(&ctx->ac, comparator, 0);
4496 }
4497
4498 /* pack derivatives */
4499 if (ddx || ddy) {
4500 switch (instr->sampler_dim) {
4501 case GLSL_SAMPLER_DIM_3D:
4502 case GLSL_SAMPLER_DIM_CUBE:
4503 num_deriv_comp = 3;
4504 break;
4505 case GLSL_SAMPLER_DIM_2D:
4506 default:
4507 num_deriv_comp = 2;
4508 break;
4509 case GLSL_SAMPLER_DIM_1D:
4510 num_deriv_comp = 1;
4511 break;
4512 }
4513
4514 for (unsigned i = 0; i < num_deriv_comp; i++) {
4515 derivs[i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4516 derivs[num_deriv_comp + i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4517 }
4518 }
4519
4520 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4521 if (instr->is_array && instr->op != nir_texop_lod)
4522 coords[3] = apply_round_slice(&ctx->ac, coords[3]);
4523 for (chan = 0; chan < instr->coord_components; chan++)
4524 coords[chan] = to_float(&ctx->ac, coords[chan]);
4525 if (instr->coord_components == 3)
4526 coords[3] = LLVMGetUndef(ctx->ac.f32);
4527 ac_prepare_cube_coords(&ctx->ac,
4528 instr->op == nir_texop_txd, instr->is_array,
4529 coords, derivs);
4530 if (num_deriv_comp)
4531 num_deriv_comp--;
4532 }
4533
4534 if (ddx || ddy) {
4535 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4536 address[count++] = derivs[i];
4537 }
4538
4539 /* Pack texture coordinates */
4540 if (coord) {
4541 address[count++] = coords[0];
4542 if (instr->coord_components > 1) {
4543 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4544 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4545 }
4546 address[count++] = coords[1];
4547 }
4548 if (instr->coord_components > 2) {
4549 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4550 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4551 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4552 instr->op != nir_texop_txf) {
4553 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4554 }
4555 address[count++] = coords[2];
4556 }
4557 }
4558
4559 /* Pack LOD */
4560 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4561 instr->op == nir_texop_txf)) {
4562 address[count++] = lod;
4563 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4564 address[count++] = sample_index;
4565 } else if(instr->op == nir_texop_txs) {
4566 count = 0;
4567 if (lod)
4568 address[count++] = lod;
4569 else
4570 address[count++] = ctx->ac.i32_0;
4571 }
4572
4573 for (chan = 0; chan < count; chan++) {
4574 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4575 address[chan], ctx->ac.i32, "");
4576 }
4577
4578 if (instr->op == nir_texop_samples_identical) {
4579 LLVMValueRef txf_address[4];
4580 struct ac_image_args txf_args = { 0 };
4581 unsigned txf_count = count;
4582 memcpy(txf_address, address, sizeof(txf_address));
4583
4584 if (!instr->is_array)
4585 txf_address[2] = ctx->ac.i32_0;
4586 txf_address[3] = ctx->ac.i32_0;
4587
4588 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4589 fmask_ptr, NULL,
4590 txf_address, txf_count, 0xf);
4591
4592 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4593
4594 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4595 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4596 goto write_result;
4597 }
4598
4599 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4600 instr->op != nir_texop_txs) {
4601 unsigned sample_chan = instr->is_array ? 3 : 2;
4602 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4603 address[0],
4604 address[1],
4605 instr->is_array ? address[2] : NULL,
4606 address[sample_chan],
4607 fmask_ptr);
4608 }
4609
4610 if (offsets && instr->op == nir_texop_txf) {
4611 nir_const_value *const_offset =
4612 nir_src_as_const_value(instr->src[const_src].src);
4613 int num_offsets = instr->src[const_src].src.ssa->num_components;
4614 assert(const_offset);
4615 num_offsets = MIN2(num_offsets, instr->coord_components);
4616 if (num_offsets > 2)
4617 address[2] = LLVMBuildAdd(ctx->ac.builder,
4618 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4619 if (num_offsets > 1)
4620 address[1] = LLVMBuildAdd(ctx->ac.builder,
4621 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4622 address[0] = LLVMBuildAdd(ctx->ac.builder,
4623 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4624
4625 }
4626
4627 /* TODO TG4 support */
4628 if (instr->op == nir_texop_tg4) {
4629 if (instr->is_shadow)
4630 dmask = 1;
4631 else
4632 dmask = 1 << instr->component;
4633 }
4634 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4635 res_ptr, samp_ptr, address, count, dmask);
4636
4637 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4638
4639 if (instr->op == nir_texop_query_levels)
4640 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4641 else if (instr->is_shadow && instr->is_new_style_shadow &&
4642 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4643 instr->op != nir_texop_tg4)
4644 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4645 else if (instr->op == nir_texop_txs &&
4646 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4647 instr->is_array) {
4648 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4649 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4650 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4651 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4652 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4653 } else if (instr->dest.ssa.num_components != 4)
4654 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4655
4656 write_result:
4657 if (result) {
4658 assert(instr->dest.is_ssa);
4659 result = to_integer(&ctx->ac, result);
4660 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4661 }
4662 }
4663
4664
4665 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4666 {
4667 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4668 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4669
4670 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4671 _mesa_hash_table_insert(ctx->phis, instr, result);
4672 }
4673
4674 static void visit_post_phi(struct ac_nir_context *ctx,
4675 nir_phi_instr *instr,
4676 LLVMValueRef llvm_phi)
4677 {
4678 nir_foreach_phi_src(src, instr) {
4679 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4680 LLVMValueRef llvm_src = get_src(ctx, src->src);
4681
4682 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4683 }
4684 }
4685
4686 static void phi_post_pass(struct ac_nir_context *ctx)
4687 {
4688 struct hash_entry *entry;
4689 hash_table_foreach(ctx->phis, entry) {
4690 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4691 (LLVMValueRef)entry->data);
4692 }
4693 }
4694
4695
4696 static void visit_ssa_undef(struct ac_nir_context *ctx,
4697 const nir_ssa_undef_instr *instr)
4698 {
4699 unsigned num_components = instr->def.num_components;
4700 LLVMValueRef undef;
4701
4702 if (num_components == 1)
4703 undef = LLVMGetUndef(ctx->ac.i32);
4704 else {
4705 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4706 }
4707 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4708 }
4709
4710 static void visit_jump(struct ac_nir_context *ctx,
4711 const nir_jump_instr *instr)
4712 {
4713 switch (instr->type) {
4714 case nir_jump_break:
4715 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4716 LLVMClearInsertionPosition(ctx->ac.builder);
4717 break;
4718 case nir_jump_continue:
4719 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4720 LLVMClearInsertionPosition(ctx->ac.builder);
4721 break;
4722 default:
4723 fprintf(stderr, "Unknown NIR jump instr: ");
4724 nir_print_instr(&instr->instr, stderr);
4725 fprintf(stderr, "\n");
4726 abort();
4727 }
4728 }
4729
4730 static void visit_cf_list(struct ac_nir_context *ctx,
4731 struct exec_list *list);
4732
4733 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4734 {
4735 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4736 nir_foreach_instr(instr, block)
4737 {
4738 switch (instr->type) {
4739 case nir_instr_type_alu:
4740 visit_alu(ctx, nir_instr_as_alu(instr));
4741 break;
4742 case nir_instr_type_load_const:
4743 visit_load_const(ctx, nir_instr_as_load_const(instr));
4744 break;
4745 case nir_instr_type_intrinsic:
4746 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4747 break;
4748 case nir_instr_type_tex:
4749 visit_tex(ctx, nir_instr_as_tex(instr));
4750 break;
4751 case nir_instr_type_phi:
4752 visit_phi(ctx, nir_instr_as_phi(instr));
4753 break;
4754 case nir_instr_type_ssa_undef:
4755 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4756 break;
4757 case nir_instr_type_jump:
4758 visit_jump(ctx, nir_instr_as_jump(instr));
4759 break;
4760 default:
4761 fprintf(stderr, "Unknown NIR instr type: ");
4762 nir_print_instr(instr, stderr);
4763 fprintf(stderr, "\n");
4764 abort();
4765 }
4766 }
4767
4768 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4769 }
4770
4771 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4772 {
4773 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4774
4775 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4776 LLVMBasicBlockRef merge_block =
4777 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4778 LLVMBasicBlockRef if_block =
4779 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4780 LLVMBasicBlockRef else_block = merge_block;
4781 if (!exec_list_is_empty(&if_stmt->else_list))
4782 else_block = LLVMAppendBasicBlockInContext(
4783 ctx->ac.context, fn, "");
4784
4785 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4786 LLVMConstInt(ctx->ac.i32, 0, false), "");
4787 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4788
4789 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4790 visit_cf_list(ctx, &if_stmt->then_list);
4791 if (LLVMGetInsertBlock(ctx->ac.builder))
4792 LLVMBuildBr(ctx->ac.builder, merge_block);
4793
4794 if (!exec_list_is_empty(&if_stmt->else_list)) {
4795 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4796 visit_cf_list(ctx, &if_stmt->else_list);
4797 if (LLVMGetInsertBlock(ctx->ac.builder))
4798 LLVMBuildBr(ctx->ac.builder, merge_block);
4799 }
4800
4801 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4802 }
4803
4804 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4805 {
4806 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4807 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4808 LLVMBasicBlockRef break_parent = ctx->break_block;
4809
4810 ctx->continue_block =
4811 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4812 ctx->break_block =
4813 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4814
4815 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4816 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4817 visit_cf_list(ctx, &loop->body);
4818
4819 if (LLVMGetInsertBlock(ctx->ac.builder))
4820 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4821 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4822
4823 ctx->continue_block = continue_parent;
4824 ctx->break_block = break_parent;
4825 }
4826
4827 static void visit_cf_list(struct ac_nir_context *ctx,
4828 struct exec_list *list)
4829 {
4830 foreach_list_typed(nir_cf_node, node, node, list)
4831 {
4832 switch (node->type) {
4833 case nir_cf_node_block:
4834 visit_block(ctx, nir_cf_node_as_block(node));
4835 break;
4836
4837 case nir_cf_node_if:
4838 visit_if(ctx, nir_cf_node_as_if(node));
4839 break;
4840
4841 case nir_cf_node_loop:
4842 visit_loop(ctx, nir_cf_node_as_loop(node));
4843 break;
4844
4845 default:
4846 assert(0);
4847 }
4848 }
4849 }
4850
4851 static void
4852 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4853 struct nir_variable *variable)
4854 {
4855 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4856 LLVMValueRef t_offset;
4857 LLVMValueRef t_list;
4858 LLVMValueRef input;
4859 LLVMValueRef buffer_index;
4860 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4861 int idx = variable->data.location;
4862 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4863
4864 variable->data.driver_location = idx * 4;
4865
4866 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4867 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
4868 ctx->abi.start_instance, "");
4869 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4870 ctx->shader_info->vs.vgpr_comp_cnt);
4871 } else
4872 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
4873 ctx->abi.base_vertex, "");
4874
4875 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4876 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4877
4878 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4879
4880 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4881 buffer_index,
4882 LLVMConstInt(ctx->i32, 0, false),
4883 true);
4884
4885 for (unsigned chan = 0; chan < 4; chan++) {
4886 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4887 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4888 to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
4889 input, llvm_chan, ""));
4890 }
4891 }
4892 }
4893
4894 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4895 unsigned attr,
4896 LLVMValueRef interp_param,
4897 LLVMValueRef prim_mask,
4898 LLVMValueRef result[4])
4899 {
4900 LLVMValueRef attr_number;
4901 unsigned chan;
4902 LLVMValueRef i, j;
4903 bool interp = interp_param != NULL;
4904
4905 attr_number = LLVMConstInt(ctx->i32, attr, false);
4906
4907 /* fs.constant returns the param from the middle vertex, so it's not
4908 * really useful for flat shading. It's meant to be used for custom
4909 * interpolation (but the intrinsic can't fetch from the other two
4910 * vertices).
4911 *
4912 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4913 * to do the right thing. The only reason we use fs.constant is that
4914 * fs.interp cannot be used on integers, because they can be equal
4915 * to NaN.
4916 */
4917 if (interp) {
4918 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4919 LLVMVectorType(ctx->f32, 2), "");
4920
4921 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4922 ctx->i32zero, "");
4923 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4924 ctx->i32one, "");
4925 }
4926
4927 for (chan = 0; chan < 4; chan++) {
4928 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4929
4930 if (interp) {
4931 result[chan] = ac_build_fs_interp(&ctx->ac,
4932 llvm_chan,
4933 attr_number,
4934 prim_mask, i, j);
4935 } else {
4936 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4937 LLVMConstInt(ctx->i32, 2, false),
4938 llvm_chan,
4939 attr_number,
4940 prim_mask);
4941 }
4942 }
4943 }
4944
4945 static void
4946 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4947 struct nir_variable *variable)
4948 {
4949 int idx = variable->data.location;
4950 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4951 LLVMValueRef interp;
4952
4953 variable->data.driver_location = idx * 4;
4954 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4955
4956 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4957 unsigned interp_type;
4958 if (variable->data.sample) {
4959 interp_type = INTERP_SAMPLE;
4960 ctx->shader_info->fs.force_persample = true;
4961 } else if (variable->data.centroid)
4962 interp_type = INTERP_CENTROID;
4963 else
4964 interp_type = INTERP_CENTER;
4965
4966 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4967 } else
4968 interp = NULL;
4969
4970 for (unsigned i = 0; i < attrib_count; ++i)
4971 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4972
4973 }
4974
4975 static void
4976 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4977 struct nir_variable *variable)
4978 {
4979 switch (ctx->stage) {
4980 case MESA_SHADER_VERTEX:
4981 handle_vs_input_decl(ctx, variable);
4982 break;
4983 case MESA_SHADER_FRAGMENT:
4984 handle_fs_input_decl(ctx, variable);
4985 break;
4986 default:
4987 break;
4988 }
4989
4990 }
4991
4992 static void
4993 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4994 struct nir_shader *nir)
4995 {
4996 unsigned index = 0;
4997 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4998 LLVMValueRef interp_param;
4999 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5000
5001 if (!(ctx->input_mask & (1ull << i)))
5002 continue;
5003
5004 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5005 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5006 interp_param = *inputs;
5007 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5008 inputs);
5009
5010 if (!interp_param)
5011 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5012 ++index;
5013 } else if (i == VARYING_SLOT_POS) {
5014 for(int i = 0; i < 3; ++i)
5015 inputs[i] = ctx->frag_pos[i];
5016
5017 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
5018 }
5019 }
5020 ctx->shader_info->fs.num_interp = index;
5021 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5022 ctx->shader_info->fs.has_pcoord = true;
5023 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5024 ctx->shader_info->fs.prim_id_input = true;
5025 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5026 ctx->shader_info->fs.layer_input = true;
5027 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5028 }
5029
5030 static LLVMValueRef
5031 ac_build_alloca(struct ac_llvm_context *ac,
5032 LLVMTypeRef type,
5033 const char *name)
5034 {
5035 LLVMBuilderRef builder = ac->builder;
5036 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5037 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5038 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5039 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5040 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5041 LLVMValueRef res;
5042
5043 if (first_instr) {
5044 LLVMPositionBuilderBefore(first_builder, first_instr);
5045 } else {
5046 LLVMPositionBuilderAtEnd(first_builder, first_block);
5047 }
5048
5049 res = LLVMBuildAlloca(first_builder, type, name);
5050 LLVMBuildStore(builder, LLVMConstNull(type), res);
5051
5052 LLVMDisposeBuilder(first_builder);
5053
5054 return res;
5055 }
5056
5057 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5058 LLVMTypeRef type,
5059 const char *name)
5060 {
5061 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5062 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5063 return ptr;
5064 }
5065
5066 static void
5067 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5068 struct nir_variable *variable)
5069 {
5070 int idx = variable->data.location + variable->data.index;
5071 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5072 uint64_t mask_attribs;
5073
5074 variable->data.driver_location = idx * 4;
5075
5076 /* tess ctrl has it's own load/store paths for outputs */
5077 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5078 return;
5079
5080 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5081 if (ctx->stage == MESA_SHADER_VERTEX ||
5082 ctx->stage == MESA_SHADER_TESS_EVAL ||
5083 ctx->stage == MESA_SHADER_GEOMETRY) {
5084 if (idx == VARYING_SLOT_CLIP_DIST0) {
5085 int length = ctx->num_output_clips + ctx->num_output_culls;
5086 if (ctx->stage == MESA_SHADER_VERTEX) {
5087 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5088 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5089 }
5090 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5091 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5092 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5093 }
5094
5095 if (length > 4)
5096 attrib_count = 2;
5097 else
5098 attrib_count = 1;
5099 mask_attribs = 1ull << idx;
5100 }
5101 }
5102
5103 ctx->output_mask |= mask_attribs;
5104 }
5105
5106 static void
5107 handle_shader_output_decl(struct ac_nir_context *ctx,
5108 struct nir_shader *nir,
5109 struct nir_variable *variable)
5110 {
5111 unsigned output_loc = variable->data.driver_location / 4;
5112 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5113
5114 /* tess ctrl has it's own load/store paths for outputs */
5115 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5116 return;
5117
5118 if (ctx->stage == MESA_SHADER_VERTEX ||
5119 ctx->stage == MESA_SHADER_TESS_EVAL ||
5120 ctx->stage == MESA_SHADER_GEOMETRY) {
5121 int idx = variable->data.location + variable->data.index;
5122 if (idx == VARYING_SLOT_CLIP_DIST0) {
5123 int length = nir->info.clip_distance_array_size +
5124 nir->info.cull_distance_array_size;
5125
5126 if (length > 4)
5127 attrib_count = 2;
5128 else
5129 attrib_count = 1;
5130 }
5131 }
5132
5133 for (unsigned i = 0; i < attrib_count; ++i) {
5134 for (unsigned chan = 0; chan < 4; chan++) {
5135 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5136 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5137 }
5138 }
5139 }
5140
5141 static LLVMTypeRef
5142 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5143 enum glsl_base_type type)
5144 {
5145 switch (type) {
5146 case GLSL_TYPE_INT:
5147 case GLSL_TYPE_UINT:
5148 case GLSL_TYPE_BOOL:
5149 case GLSL_TYPE_SUBROUTINE:
5150 return ctx->i32;
5151 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5152 return ctx->f32;
5153 case GLSL_TYPE_INT64:
5154 case GLSL_TYPE_UINT64:
5155 return ctx->i64;
5156 case GLSL_TYPE_DOUBLE:
5157 return ctx->f64;
5158 default:
5159 unreachable("unknown GLSL type");
5160 }
5161 }
5162
5163 static LLVMTypeRef
5164 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5165 const struct glsl_type *type)
5166 {
5167 if (glsl_type_is_scalar(type)) {
5168 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5169 }
5170
5171 if (glsl_type_is_vector(type)) {
5172 return LLVMVectorType(
5173 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5174 glsl_get_vector_elements(type));
5175 }
5176
5177 if (glsl_type_is_matrix(type)) {
5178 return LLVMArrayType(
5179 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5180 glsl_get_matrix_columns(type));
5181 }
5182
5183 if (glsl_type_is_array(type)) {
5184 return LLVMArrayType(
5185 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5186 glsl_get_length(type));
5187 }
5188
5189 assert(glsl_type_is_struct(type));
5190
5191 LLVMTypeRef member_types[glsl_get_length(type)];
5192
5193 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5194 member_types[i] =
5195 glsl_to_llvm_type(ctx,
5196 glsl_get_struct_field(type, i));
5197 }
5198
5199 return LLVMStructTypeInContext(ctx->context, member_types,
5200 glsl_get_length(type), false);
5201 }
5202
5203 static void
5204 setup_locals(struct ac_nir_context *ctx,
5205 struct nir_function *func)
5206 {
5207 int i, j;
5208 ctx->num_locals = 0;
5209 nir_foreach_variable(variable, &func->impl->locals) {
5210 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5211 variable->data.driver_location = ctx->num_locals * 4;
5212 ctx->num_locals += attrib_count;
5213 }
5214 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5215 if (!ctx->locals)
5216 return;
5217
5218 for (i = 0; i < ctx->num_locals; i++) {
5219 for (j = 0; j < 4; j++) {
5220 ctx->locals[i * 4 + j] =
5221 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5222 }
5223 }
5224 }
5225
5226 static void
5227 setup_shared(struct ac_nir_context *ctx,
5228 struct nir_shader *nir)
5229 {
5230 nir_foreach_variable(variable, &nir->shared) {
5231 LLVMValueRef shared =
5232 LLVMAddGlobalInAddressSpace(
5233 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5234 variable->name ? variable->name : "",
5235 LOCAL_ADDR_SPACE);
5236 _mesa_hash_table_insert(ctx->vars, variable, shared);
5237 }
5238 }
5239
5240 static LLVMValueRef
5241 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5242 {
5243 v = to_float(ctx, v);
5244 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5245 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5246 }
5247
5248
5249 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5250 LLVMValueRef src0, LLVMValueRef src1)
5251 {
5252 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5253 LLVMValueRef comp[2];
5254
5255 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5256 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5257 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5258 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5259 }
5260
5261 /* Initialize arguments for the shader export intrinsic */
5262 static void
5263 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5264 LLVMValueRef *values,
5265 unsigned target,
5266 struct ac_export_args *args)
5267 {
5268 /* Default is 0xf. Adjusted below depending on the format. */
5269 args->enabled_channels = 0xf;
5270
5271 /* Specify whether the EXEC mask represents the valid mask */
5272 args->valid_mask = 0;
5273
5274 /* Specify whether this is the last export */
5275 args->done = 0;
5276
5277 /* Specify the target we are exporting */
5278 args->target = target;
5279
5280 args->compr = false;
5281 args->out[0] = LLVMGetUndef(ctx->f32);
5282 args->out[1] = LLVMGetUndef(ctx->f32);
5283 args->out[2] = LLVMGetUndef(ctx->f32);
5284 args->out[3] = LLVMGetUndef(ctx->f32);
5285
5286 if (!values)
5287 return;
5288
5289 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5290 LLVMValueRef val[4];
5291 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5292 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5293 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5294
5295 switch(col_format) {
5296 case V_028714_SPI_SHADER_ZERO:
5297 args->enabled_channels = 0; /* writemask */
5298 args->target = V_008DFC_SQ_EXP_NULL;
5299 break;
5300
5301 case V_028714_SPI_SHADER_32_R:
5302 args->enabled_channels = 1;
5303 args->out[0] = values[0];
5304 break;
5305
5306 case V_028714_SPI_SHADER_32_GR:
5307 args->enabled_channels = 0x3;
5308 args->out[0] = values[0];
5309 args->out[1] = values[1];
5310 break;
5311
5312 case V_028714_SPI_SHADER_32_AR:
5313 args->enabled_channels = 0x9;
5314 args->out[0] = values[0];
5315 args->out[3] = values[3];
5316 break;
5317
5318 case V_028714_SPI_SHADER_FP16_ABGR:
5319 args->compr = 1;
5320
5321 for (unsigned chan = 0; chan < 2; chan++) {
5322 LLVMValueRef pack_args[2] = {
5323 values[2 * chan],
5324 values[2 * chan + 1]
5325 };
5326 LLVMValueRef packed;
5327
5328 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5329 args->out[chan] = packed;
5330 }
5331 break;
5332
5333 case V_028714_SPI_SHADER_UNORM16_ABGR:
5334 for (unsigned chan = 0; chan < 4; chan++) {
5335 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5336 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5337 LLVMConstReal(ctx->f32, 65535), "");
5338 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5339 LLVMConstReal(ctx->f32, 0.5), "");
5340 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5341 ctx->i32, "");
5342 }
5343
5344 args->compr = 1;
5345 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5346 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5347 break;
5348
5349 case V_028714_SPI_SHADER_SNORM16_ABGR:
5350 for (unsigned chan = 0; chan < 4; chan++) {
5351 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5352 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5353 LLVMConstReal(ctx->f32, 32767), "");
5354
5355 /* If positive, add 0.5, else add -0.5. */
5356 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5357 LLVMBuildSelect(ctx->builder,
5358 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5359 val[chan], ctx->f32zero, ""),
5360 LLVMConstReal(ctx->f32, 0.5),
5361 LLVMConstReal(ctx->f32, -0.5), ""), "");
5362 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5363 }
5364
5365 args->compr = 1;
5366 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5367 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5368 break;
5369
5370 case V_028714_SPI_SHADER_UINT16_ABGR: {
5371 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
5372
5373 for (unsigned chan = 0; chan < 4; chan++) {
5374 val[chan] = to_integer(&ctx->ac, values[chan]);
5375 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], max);
5376 }
5377
5378 args->compr = 1;
5379 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5380 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5381 break;
5382 }
5383
5384 case V_028714_SPI_SHADER_SINT16_ABGR: {
5385 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5386 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5387
5388 /* Clamp. */
5389 for (unsigned chan = 0; chan < 4; chan++) {
5390 val[chan] = to_integer(&ctx->ac, values[chan]);
5391 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], max);
5392 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], min);
5393 }
5394
5395 args->compr = 1;
5396 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5397 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5398 break;
5399 }
5400
5401 default:
5402 case V_028714_SPI_SHADER_32_ABGR:
5403 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5404 break;
5405 }
5406 } else
5407 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5408
5409 for (unsigned i = 0; i < 4; ++i)
5410 args->out[i] = to_float(&ctx->ac, args->out[i]);
5411 }
5412
5413 static void
5414 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5415 bool export_prim_id,
5416 struct ac_vs_output_info *outinfo)
5417 {
5418 uint32_t param_count = 0;
5419 unsigned target;
5420 unsigned pos_idx, num_pos_exports = 0;
5421 struct ac_export_args args, pos_args[4] = {};
5422 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5423 int i;
5424
5425 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5426 sizeof(outinfo->vs_output_param_offset));
5427
5428 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5429 LLVMValueRef slots[8];
5430 unsigned j;
5431
5432 if (outinfo->cull_dist_mask)
5433 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5434
5435 i = VARYING_SLOT_CLIP_DIST0;
5436 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5437 slots[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5438 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5439
5440 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5441 slots[i] = LLVMGetUndef(ctx->f32);
5442
5443 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5444 target = V_008DFC_SQ_EXP_POS + 3;
5445 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5446 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5447 &args, sizeof(args));
5448 }
5449
5450 target = V_008DFC_SQ_EXP_POS + 2;
5451 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5452 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5453 &args, sizeof(args));
5454
5455 }
5456
5457 LLVMValueRef pos_values[4] = {ctx->f32zero, ctx->f32zero, ctx->f32zero, ctx->f32one};
5458 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5459 for (unsigned j = 0; j < 4; j++)
5460 pos_values[j] = LLVMBuildLoad(ctx->builder,
5461 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5462 }
5463 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5464
5465 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5466 outinfo->writes_pointsize = true;
5467 psize_value = LLVMBuildLoad(ctx->builder,
5468 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5469 }
5470
5471 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5472 outinfo->writes_layer = true;
5473 layer_value = LLVMBuildLoad(ctx->builder,
5474 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5475 }
5476
5477 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5478 outinfo->writes_viewport_index = true;
5479 viewport_index_value = LLVMBuildLoad(ctx->builder,
5480 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5481 }
5482
5483 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5484 (outinfo->writes_layer == true ? 4 : 0) |
5485 (outinfo->writes_viewport_index == true ? 8 : 0));
5486 if (mask) {
5487 pos_args[1].enabled_channels = mask;
5488 pos_args[1].valid_mask = 0;
5489 pos_args[1].done = 0;
5490 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5491 pos_args[1].compr = 0;
5492 pos_args[1].out[0] = ctx->f32zero; /* X */
5493 pos_args[1].out[1] = ctx->f32zero; /* Y */
5494 pos_args[1].out[2] = ctx->f32zero; /* Z */
5495 pos_args[1].out[3] = ctx->f32zero; /* W */
5496
5497 if (outinfo->writes_pointsize == true)
5498 pos_args[1].out[0] = psize_value;
5499 if (outinfo->writes_layer == true)
5500 pos_args[1].out[2] = layer_value;
5501 if (outinfo->writes_viewport_index == true)
5502 pos_args[1].out[3] = viewport_index_value;
5503 }
5504 for (i = 0; i < 4; i++) {
5505 if (pos_args[i].out[0])
5506 num_pos_exports++;
5507 }
5508
5509 pos_idx = 0;
5510 for (i = 0; i < 4; i++) {
5511 if (!pos_args[i].out[0])
5512 continue;
5513
5514 /* Specify the target we are exporting */
5515 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5516 if (pos_idx == num_pos_exports)
5517 pos_args[i].done = 1;
5518 ac_build_export(&ctx->ac, &pos_args[i]);
5519 }
5520
5521 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5522 LLVMValueRef values[4];
5523 if (!(ctx->output_mask & (1ull << i)))
5524 continue;
5525
5526 for (unsigned j = 0; j < 4; j++)
5527 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5528 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5529
5530 if (i == VARYING_SLOT_LAYER) {
5531 target = V_008DFC_SQ_EXP_PARAM + param_count;
5532 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5533 param_count++;
5534 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5535 target = V_008DFC_SQ_EXP_PARAM + param_count;
5536 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5537 param_count++;
5538 } else if (i >= VARYING_SLOT_VAR0) {
5539 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5540 target = V_008DFC_SQ_EXP_PARAM + param_count;
5541 outinfo->vs_output_param_offset[i] = param_count;
5542 param_count++;
5543 } else
5544 continue;
5545
5546 si_llvm_init_export_args(ctx, values, target, &args);
5547
5548 if (target >= V_008DFC_SQ_EXP_POS &&
5549 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5550 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5551 &args, sizeof(args));
5552 } else {
5553 ac_build_export(&ctx->ac, &args);
5554 }
5555 }
5556
5557 if (export_prim_id) {
5558 LLVMValueRef values[4];
5559 target = V_008DFC_SQ_EXP_PARAM + param_count;
5560 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5561 param_count++;
5562
5563 values[0] = ctx->vs_prim_id;
5564 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5565 ctx->shader_info->vs.vgpr_comp_cnt);
5566 for (unsigned j = 1; j < 4; j++)
5567 values[j] = ctx->f32zero;
5568 si_llvm_init_export_args(ctx, values, target, &args);
5569 ac_build_export(&ctx->ac, &args);
5570 outinfo->export_prim_id = true;
5571 }
5572
5573 outinfo->pos_exports = num_pos_exports;
5574 outinfo->param_exports = param_count;
5575 }
5576
5577 static void
5578 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5579 struct ac_es_output_info *outinfo)
5580 {
5581 int j;
5582 uint64_t max_output_written = 0;
5583 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5584 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5585 int param_index;
5586 int length = 4;
5587
5588 if (!(ctx->output_mask & (1ull << i)))
5589 continue;
5590
5591 if (i == VARYING_SLOT_CLIP_DIST0)
5592 length = ctx->num_output_clips + ctx->num_output_culls;
5593
5594 param_index = shader_io_get_unique_index(i);
5595
5596 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5597
5598 for (j = 0; j < length; j++) {
5599 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5600 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5601
5602 ac_build_buffer_store_dword(&ctx->ac,
5603 ctx->esgs_ring,
5604 out_val, 1,
5605 NULL, ctx->es2gs_offset,
5606 (4 * param_index + j) * 4,
5607 1, 1, true, true);
5608 }
5609 }
5610 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5611 }
5612
5613 static void
5614 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5615 {
5616 LLVMValueRef vertex_id = ctx->rel_auto_id;
5617 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5618 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5619 vertex_dw_stride, "");
5620
5621 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5622 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5623 int length = 4;
5624
5625 if (!(ctx->output_mask & (1ull << i)))
5626 continue;
5627
5628 if (i == VARYING_SLOT_CLIP_DIST0)
5629 length = ctx->num_output_clips + ctx->num_output_culls;
5630 int param = shader_io_get_unique_index(i);
5631 mark_tess_output(ctx, false, param);
5632 if (length > 4)
5633 mark_tess_output(ctx, false, param + 1);
5634 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5635 LLVMConstInt(ctx->i32, param * 4, false),
5636 "");
5637 for (unsigned j = 0; j < length; j++) {
5638 lds_store(ctx, dw_addr,
5639 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5640 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5641 }
5642 }
5643 }
5644
5645 struct ac_build_if_state
5646 {
5647 struct nir_to_llvm_context *ctx;
5648 LLVMValueRef condition;
5649 LLVMBasicBlockRef entry_block;
5650 LLVMBasicBlockRef true_block;
5651 LLVMBasicBlockRef false_block;
5652 LLVMBasicBlockRef merge_block;
5653 };
5654
5655 static LLVMBasicBlockRef
5656 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5657 {
5658 LLVMBasicBlockRef current_block;
5659 LLVMBasicBlockRef next_block;
5660 LLVMBasicBlockRef new_block;
5661
5662 /* get current basic block */
5663 current_block = LLVMGetInsertBlock(ctx->builder);
5664
5665 /* chqeck if there's another block after this one */
5666 next_block = LLVMGetNextBasicBlock(current_block);
5667 if (next_block) {
5668 /* insert the new block before the next block */
5669 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5670 }
5671 else {
5672 /* append new block after current block */
5673 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5674 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5675 }
5676 return new_block;
5677 }
5678
5679 static void
5680 ac_nir_build_if(struct ac_build_if_state *ifthen,
5681 struct nir_to_llvm_context *ctx,
5682 LLVMValueRef condition)
5683 {
5684 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5685
5686 memset(ifthen, 0, sizeof *ifthen);
5687 ifthen->ctx = ctx;
5688 ifthen->condition = condition;
5689 ifthen->entry_block = block;
5690
5691 /* create endif/merge basic block for the phi functions */
5692 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5693
5694 /* create/insert true_block before merge_block */
5695 ifthen->true_block =
5696 LLVMInsertBasicBlockInContext(ctx->context,
5697 ifthen->merge_block,
5698 "if-true-block");
5699
5700 /* successive code goes into the true block */
5701 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5702 }
5703
5704 /**
5705 * End a conditional.
5706 */
5707 static void
5708 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5709 {
5710 LLVMBuilderRef builder = ifthen->ctx->builder;
5711
5712 /* Insert branch to the merge block from current block */
5713 LLVMBuildBr(builder, ifthen->merge_block);
5714
5715 /*
5716 * Now patch in the various branch instructions.
5717 */
5718
5719 /* Insert the conditional branch instruction at the end of entry_block */
5720 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5721 if (ifthen->false_block) {
5722 /* we have an else clause */
5723 LLVMBuildCondBr(builder, ifthen->condition,
5724 ifthen->true_block, ifthen->false_block);
5725 }
5726 else {
5727 /* no else clause */
5728 LLVMBuildCondBr(builder, ifthen->condition,
5729 ifthen->true_block, ifthen->merge_block);
5730 }
5731
5732 /* Resume building code at end of the ifthen->merge_block */
5733 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5734 }
5735
5736 static void
5737 write_tess_factors(struct nir_to_llvm_context *ctx)
5738 {
5739 unsigned stride, outer_comps, inner_comps;
5740 struct ac_build_if_state if_ctx, inner_if_ctx;
5741 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5742 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5743 unsigned tess_inner_index, tess_outer_index;
5744 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5745 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5746 int i;
5747 emit_barrier(ctx);
5748
5749 switch (ctx->options->key.tcs.primitive_mode) {
5750 case GL_ISOLINES:
5751 stride = 2;
5752 outer_comps = 2;
5753 inner_comps = 0;
5754 break;
5755 case GL_TRIANGLES:
5756 stride = 4;
5757 outer_comps = 3;
5758 inner_comps = 1;
5759 break;
5760 case GL_QUADS:
5761 stride = 6;
5762 outer_comps = 4;
5763 inner_comps = 2;
5764 break;
5765 default:
5766 return;
5767 }
5768
5769 ac_nir_build_if(&if_ctx, ctx,
5770 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5771 invocation_id, ctx->i32zero, ""));
5772
5773 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5774 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5775
5776 mark_tess_output(ctx, true, tess_inner_index);
5777 mark_tess_output(ctx, true, tess_outer_index);
5778 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5779 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5780 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5781 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5782 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5783
5784 for (i = 0; i < 4; i++) {
5785 inner[i] = LLVMGetUndef(ctx->i32);
5786 outer[i] = LLVMGetUndef(ctx->i32);
5787 }
5788
5789 // LINES reverseal
5790 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5791 outer[0] = out[1] = lds_load(ctx, lds_outer);
5792 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5793 LLVMConstInt(ctx->i32, 1, false), "");
5794 outer[1] = out[0] = lds_load(ctx, lds_outer);
5795 } else {
5796 for (i = 0; i < outer_comps; i++) {
5797 outer[i] = out[i] =
5798 lds_load(ctx, lds_outer);
5799 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5800 LLVMConstInt(ctx->i32, 1, false), "");
5801 }
5802 for (i = 0; i < inner_comps; i++) {
5803 inner[i] = out[outer_comps+i] =
5804 lds_load(ctx, lds_inner);
5805 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5806 LLVMConstInt(ctx->i32, 1, false), "");
5807 }
5808 }
5809
5810 /* Convert the outputs to vectors for stores. */
5811 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5812 vec1 = NULL;
5813
5814 if (stride > 4)
5815 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5816
5817
5818 buffer = ctx->hs_ring_tess_factor;
5819 tf_base = ctx->tess_factor_offset;
5820 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5821 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5822
5823 ac_nir_build_if(&inner_if_ctx, ctx,
5824 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5825 rel_patch_id, ctx->i32zero, ""));
5826
5827 /* Store the dynamic HS control word. */
5828 ac_build_buffer_store_dword(&ctx->ac, buffer,
5829 LLVMConstInt(ctx->i32, 0x80000000, false),
5830 1, ctx->i32zero, tf_base,
5831 0, 1, 0, true, false);
5832 ac_nir_build_endif(&inner_if_ctx);
5833
5834 /* Store the tessellation factors. */
5835 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5836 MIN2(stride, 4), byteoffset, tf_base,
5837 4, 1, 0, true, false);
5838 if (vec1)
5839 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5840 stride - 4, byteoffset, tf_base,
5841 20, 1, 0, true, false);
5842
5843 //TODO store to offchip for TES to read - only if TES reads them
5844 if (1) {
5845 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5846 LLVMValueRef tf_inner_offset;
5847 unsigned param_outer, param_inner;
5848
5849 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5850 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5851 LLVMConstInt(ctx->i32, param_outer, 0));
5852
5853 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5854 util_next_power_of_two(outer_comps));
5855
5856 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5857 outer_comps, tf_outer_offset,
5858 ctx->oc_lds, 0, 1, 0, true, false);
5859 if (inner_comps) {
5860 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5861 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5862 LLVMConstInt(ctx->i32, param_inner, 0));
5863
5864 inner_vec = inner_comps == 1 ? inner[0] :
5865 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5866 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5867 inner_comps, tf_inner_offset,
5868 ctx->oc_lds, 0, 1, 0, true, false);
5869 }
5870 }
5871 ac_nir_build_endif(&if_ctx);
5872 }
5873
5874 static void
5875 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5876 {
5877 write_tess_factors(ctx);
5878 }
5879
5880 static bool
5881 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5882 LLVMValueRef *color, unsigned param, bool is_last,
5883 struct ac_export_args *args)
5884 {
5885 /* Export */
5886 si_llvm_init_export_args(ctx, color, param,
5887 args);
5888
5889 if (is_last) {
5890 args->valid_mask = 1; /* whether the EXEC mask is valid */
5891 args->done = 1; /* DONE bit */
5892 } else if (!args->enabled_channels)
5893 return false; /* unnecessary NULL export */
5894
5895 return true;
5896 }
5897
5898 static void
5899 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5900 LLVMValueRef depth, LLVMValueRef stencil,
5901 LLVMValueRef samplemask)
5902 {
5903 struct ac_export_args args;
5904
5905 args.enabled_channels = 0;
5906 args.valid_mask = 1;
5907 args.done = 1;
5908 args.target = V_008DFC_SQ_EXP_MRTZ;
5909 args.compr = false;
5910
5911 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5912 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5913 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5914 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5915
5916 if (depth) {
5917 args.out[0] = depth;
5918 args.enabled_channels |= 0x1;
5919 }
5920
5921 if (stencil) {
5922 args.out[1] = stencil;
5923 args.enabled_channels |= 0x2;
5924 }
5925
5926 if (samplemask) {
5927 args.out[2] = samplemask;
5928 args.enabled_channels |= 0x4;
5929 }
5930
5931 /* SI (except OLAND and HAINAN) has a bug that it only looks
5932 * at the X writemask component. */
5933 if (ctx->options->chip_class == SI &&
5934 ctx->options->family != CHIP_OLAND &&
5935 ctx->options->family != CHIP_HAINAN)
5936 args.enabled_channels |= 0x1;
5937
5938 ac_build_export(&ctx->ac, &args);
5939 }
5940
5941 static void
5942 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5943 {
5944 unsigned index = 0;
5945 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5946 struct ac_export_args color_args[8];
5947
5948 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5949 LLVMValueRef values[4];
5950
5951 if (!(ctx->output_mask & (1ull << i)))
5952 continue;
5953
5954 if (i == FRAG_RESULT_DEPTH) {
5955 ctx->shader_info->fs.writes_z = true;
5956 depth = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5957 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5958 } else if (i == FRAG_RESULT_STENCIL) {
5959 ctx->shader_info->fs.writes_stencil = true;
5960 stencil = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5961 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5962 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5963 ctx->shader_info->fs.writes_sample_mask = true;
5964 samplemask = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5965 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5966 } else {
5967 bool last = false;
5968 for (unsigned j = 0; j < 4; j++)
5969 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5970 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5971
5972 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5973 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5974
5975 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
5976 if (ret)
5977 index++;
5978 }
5979 }
5980
5981 for (unsigned i = 0; i < index; i++)
5982 ac_build_export(&ctx->ac, &color_args[i]);
5983 if (depth || stencil || samplemask)
5984 si_export_mrt_z(ctx, depth, stencil, samplemask);
5985 else if (!index) {
5986 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
5987 ac_build_export(&ctx->ac, &color_args[0]);
5988 }
5989
5990 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5991 }
5992
5993 static void
5994 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5995 {
5996 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5997 }
5998
5999 static void
6000 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6001 LLVMValueRef *addrs)
6002 {
6003 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6004
6005 switch (ctx->stage) {
6006 case MESA_SHADER_VERTEX:
6007 if (ctx->options->key.vs.as_ls)
6008 handle_ls_outputs_post(ctx);
6009 else if (ctx->options->key.vs.as_es)
6010 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6011 else
6012 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6013 &ctx->shader_info->vs.outinfo);
6014 break;
6015 case MESA_SHADER_FRAGMENT:
6016 handle_fs_outputs_post(ctx);
6017 break;
6018 case MESA_SHADER_GEOMETRY:
6019 emit_gs_epilogue(ctx);
6020 break;
6021 case MESA_SHADER_TESS_CTRL:
6022 handle_tcs_outputs_post(ctx);
6023 break;
6024 case MESA_SHADER_TESS_EVAL:
6025 if (ctx->options->key.tes.as_es)
6026 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6027 else
6028 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6029 &ctx->shader_info->tes.outinfo);
6030 break;
6031 default:
6032 break;
6033 }
6034 }
6035
6036 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6037 {
6038 LLVMPassManagerRef passmgr;
6039 /* Create the pass manager */
6040 passmgr = LLVMCreateFunctionPassManagerForModule(
6041 ctx->module);
6042
6043 /* This pass should eliminate all the load and store instructions */
6044 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6045
6046 /* Add some optimization passes */
6047 LLVMAddScalarReplAggregatesPass(passmgr);
6048 LLVMAddLICMPass(passmgr);
6049 LLVMAddAggressiveDCEPass(passmgr);
6050 LLVMAddCFGSimplificationPass(passmgr);
6051 LLVMAddInstructionCombiningPass(passmgr);
6052
6053 /* Run the pass */
6054 LLVMInitializeFunctionPassManager(passmgr);
6055 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6056 LLVMFinalizeFunctionPassManager(passmgr);
6057
6058 LLVMDisposeBuilder(ctx->builder);
6059 LLVMDisposePassManager(passmgr);
6060 }
6061
6062 static void
6063 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6064 {
6065 struct ac_vs_output_info *outinfo;
6066
6067 switch (ctx->stage) {
6068 case MESA_SHADER_FRAGMENT:
6069 case MESA_SHADER_COMPUTE:
6070 case MESA_SHADER_TESS_CTRL:
6071 case MESA_SHADER_GEOMETRY:
6072 return;
6073 case MESA_SHADER_VERTEX:
6074 if (ctx->options->key.vs.as_ls ||
6075 ctx->options->key.vs.as_es)
6076 return;
6077 outinfo = &ctx->shader_info->vs.outinfo;
6078 break;
6079 case MESA_SHADER_TESS_EVAL:
6080 if (ctx->options->key.vs.as_es)
6081 return;
6082 outinfo = &ctx->shader_info->tes.outinfo;
6083 break;
6084 default:
6085 unreachable("Unhandled shader type");
6086 }
6087
6088 ac_optimize_vs_outputs(&ctx->ac,
6089 ctx->main_function,
6090 outinfo->vs_output_param_offset,
6091 VARYING_SLOT_MAX,
6092 &outinfo->param_exports);
6093 }
6094
6095 static void
6096 ac_setup_rings(struct nir_to_llvm_context *ctx)
6097 {
6098 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6099 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6100 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
6101 }
6102
6103 if (ctx->is_gs_copy_shader) {
6104 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
6105 }
6106 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6107 LLVMValueRef tmp;
6108 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
6109 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
6110
6111 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6112
6113 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
6114 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
6115 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6116 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
6117 }
6118
6119 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6120 ctx->stage == MESA_SHADER_TESS_EVAL) {
6121 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6122 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6123 }
6124 }
6125
6126 static unsigned
6127 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6128 const struct nir_shader *nir)
6129 {
6130 switch (nir->stage) {
6131 case MESA_SHADER_TESS_CTRL:
6132 return chip_class >= CIK ? 128 : 64;
6133 case MESA_SHADER_GEOMETRY:
6134 return 64;
6135 case MESA_SHADER_COMPUTE:
6136 break;
6137 default:
6138 return 0;
6139 }
6140
6141 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6142 nir->info.cs.local_size[1] *
6143 nir->info.cs.local_size[2];
6144 return max_workgroup_size;
6145 }
6146
6147 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6148 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6149 {
6150 struct ac_nir_context ctx = {};
6151 struct nir_function *func;
6152
6153 ctx.ac = *ac;
6154 ctx.abi = abi;
6155
6156 ctx.nctx = nctx;
6157 if (nctx)
6158 nctx->nir = &ctx;
6159
6160 ctx.stage = nir->stage;
6161
6162 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6163
6164 nir_foreach_variable(variable, &nir->outputs)
6165 handle_shader_output_decl(&ctx, nir, variable);
6166
6167 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6168 _mesa_key_pointer_equal);
6169 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6170 _mesa_key_pointer_equal);
6171 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6172 _mesa_key_pointer_equal);
6173
6174 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6175
6176 setup_locals(&ctx, func);
6177
6178 if (nir->stage == MESA_SHADER_COMPUTE)
6179 setup_shared(&ctx, nir);
6180
6181 visit_cf_list(&ctx, &func->impl->body);
6182 phi_post_pass(&ctx);
6183
6184 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6185 ctx.outputs);
6186
6187 free(ctx.locals);
6188 ralloc_free(ctx.defs);
6189 ralloc_free(ctx.phis);
6190 ralloc_free(ctx.vars);
6191
6192 if (nctx)
6193 nctx->nir = NULL;
6194 }
6195
6196 static
6197 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6198 struct nir_shader *nir,
6199 struct ac_shader_variant_info *shader_info,
6200 const struct ac_nir_compiler_options *options)
6201 {
6202 struct nir_to_llvm_context ctx = {0};
6203 unsigned i;
6204 ctx.options = options;
6205 ctx.shader_info = shader_info;
6206 ctx.context = LLVMContextCreate();
6207 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6208
6209 ac_llvm_context_init(&ctx.ac, ctx.context);
6210 ctx.ac.module = ctx.module;
6211
6212 memset(shader_info, 0, sizeof(*shader_info));
6213
6214 ac_nir_shader_info_pass(nir, options, &shader_info->info);
6215
6216 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6217
6218 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6219 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6220 LLVMSetDataLayout(ctx.module, data_layout_str);
6221 LLVMDisposeTargetData(data_layout);
6222 LLVMDisposeMessage(data_layout_str);
6223
6224 setup_types(&ctx);
6225
6226 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6227 ctx.ac.builder = ctx.builder;
6228 ctx.stage = nir->stage;
6229 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
6230
6231 for (i = 0; i < AC_UD_MAX_SETS; i++)
6232 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6233 for (i = 0; i < AC_UD_MAX_UD; i++)
6234 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6235
6236 create_function(&ctx);
6237
6238 if (nir->stage == MESA_SHADER_GEOMETRY) {
6239 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.i32, "gs_next_vertex");
6240
6241 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
6242 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
6243 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
6244 } else if (nir->stage == MESA_SHADER_VERTEX) {
6245 if (shader_info->info.vs.needs_instance_id) {
6246 ctx.shader_info->vs.vgpr_comp_cnt =
6247 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6248 }
6249 } else if (nir->stage == MESA_SHADER_FRAGMENT) {
6250 shader_info->fs.can_discard = nir->info.fs.uses_discard;
6251 }
6252
6253 ac_setup_rings(&ctx);
6254
6255 ctx.num_output_clips = nir->info.clip_distance_array_size;
6256 ctx.num_output_culls = nir->info.cull_distance_array_size;
6257
6258 nir_foreach_variable(variable, &nir->inputs)
6259 handle_shader_input_decl(&ctx, variable);
6260
6261 if (nir->stage == MESA_SHADER_FRAGMENT)
6262 handle_fs_inputs_pre(&ctx, nir);
6263
6264 ctx.abi.chip_class = options->chip_class;
6265 ctx.abi.inputs = &ctx.inputs[0];
6266 ctx.abi.emit_outputs = handle_shader_outputs_post;
6267 ctx.abi.load_ssbo = radv_load_ssbo;
6268 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6269
6270 nir_foreach_variable(variable, &nir->outputs)
6271 scan_shader_output_decl(&ctx, variable);
6272
6273 ac_nir_translate(&ctx.ac, &ctx.abi, nir, &ctx);
6274
6275 LLVMBuildRetVoid(ctx.builder);
6276
6277 ac_llvm_finalize_module(&ctx);
6278
6279 ac_nir_eliminate_const_vs_outputs(&ctx);
6280
6281 if (nir->stage == MESA_SHADER_GEOMETRY) {
6282 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
6283 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6284 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6285 nir->info.gs.vertices_out;
6286 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
6287 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6288 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6289 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6290 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6291 }
6292
6293 return ctx.module;
6294 }
6295
6296 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6297 {
6298 unsigned *retval = (unsigned *)context;
6299 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6300 char *description = LLVMGetDiagInfoDescription(di);
6301
6302 if (severity == LLVMDSError) {
6303 *retval = 1;
6304 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6305 description);
6306 }
6307
6308 LLVMDisposeMessage(description);
6309 }
6310
6311 static unsigned ac_llvm_compile(LLVMModuleRef M,
6312 struct ac_shader_binary *binary,
6313 LLVMTargetMachineRef tm)
6314 {
6315 unsigned retval = 0;
6316 char *err;
6317 LLVMContextRef llvm_ctx;
6318 LLVMMemoryBufferRef out_buffer;
6319 unsigned buffer_size;
6320 const char *buffer_data;
6321 LLVMBool mem_err;
6322
6323 /* Setup Diagnostic Handler*/
6324 llvm_ctx = LLVMGetModuleContext(M);
6325
6326 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6327 &retval);
6328
6329 /* Compile IR*/
6330 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6331 &err, &out_buffer);
6332
6333 /* Process Errors/Warnings */
6334 if (mem_err) {
6335 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6336 free(err);
6337 retval = 1;
6338 goto out;
6339 }
6340
6341 /* Extract Shader Code*/
6342 buffer_size = LLVMGetBufferSize(out_buffer);
6343 buffer_data = LLVMGetBufferStart(out_buffer);
6344
6345 ac_elf_read(buffer_data, buffer_size, binary);
6346
6347 /* Clean up */
6348 LLVMDisposeMemoryBuffer(out_buffer);
6349
6350 out:
6351 return retval;
6352 }
6353
6354 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6355 LLVMModuleRef llvm_module,
6356 struct ac_shader_binary *binary,
6357 struct ac_shader_config *config,
6358 struct ac_shader_variant_info *shader_info,
6359 gl_shader_stage stage,
6360 bool dump_shader, bool supports_spill)
6361 {
6362 if (dump_shader)
6363 ac_dump_module(llvm_module);
6364
6365 memset(binary, 0, sizeof(*binary));
6366 int v = ac_llvm_compile(llvm_module, binary, tm);
6367 if (v) {
6368 fprintf(stderr, "compile failed\n");
6369 }
6370
6371 if (dump_shader)
6372 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6373
6374 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6375
6376 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6377 LLVMDisposeModule(llvm_module);
6378 LLVMContextDispose(ctx);
6379
6380 if (stage == MESA_SHADER_FRAGMENT) {
6381 shader_info->num_input_vgprs = 0;
6382 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6383 shader_info->num_input_vgprs += 2;
6384 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6385 shader_info->num_input_vgprs += 2;
6386 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6387 shader_info->num_input_vgprs += 2;
6388 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6389 shader_info->num_input_vgprs += 3;
6390 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6391 shader_info->num_input_vgprs += 2;
6392 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6393 shader_info->num_input_vgprs += 2;
6394 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6395 shader_info->num_input_vgprs += 2;
6396 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6397 shader_info->num_input_vgprs += 1;
6398 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6399 shader_info->num_input_vgprs += 1;
6400 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6401 shader_info->num_input_vgprs += 1;
6402 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6403 shader_info->num_input_vgprs += 1;
6404 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6405 shader_info->num_input_vgprs += 1;
6406 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6407 shader_info->num_input_vgprs += 1;
6408 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6409 shader_info->num_input_vgprs += 1;
6410 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6411 shader_info->num_input_vgprs += 1;
6412 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6413 shader_info->num_input_vgprs += 1;
6414 }
6415 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6416
6417 /* +3 for scratch wave offset and VCC */
6418 config->num_sgprs = MAX2(config->num_sgprs,
6419 shader_info->num_input_sgprs + 3);
6420 }
6421
6422 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6423 struct ac_shader_binary *binary,
6424 struct ac_shader_config *config,
6425 struct ac_shader_variant_info *shader_info,
6426 struct nir_shader *nir,
6427 const struct ac_nir_compiler_options *options,
6428 bool dump_shader)
6429 {
6430
6431 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6432 options);
6433
6434 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6435 switch (nir->stage) {
6436 case MESA_SHADER_COMPUTE:
6437 for (int i = 0; i < 3; ++i)
6438 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6439 break;
6440 case MESA_SHADER_FRAGMENT:
6441 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6442 break;
6443 case MESA_SHADER_GEOMETRY:
6444 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6445 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6446 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6447 shader_info->gs.invocations = nir->info.gs.invocations;
6448 break;
6449 case MESA_SHADER_TESS_EVAL:
6450 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6451 shader_info->tes.spacing = nir->info.tess.spacing;
6452 shader_info->tes.ccw = nir->info.tess.ccw;
6453 shader_info->tes.point_mode = nir->info.tess.point_mode;
6454 shader_info->tes.as_es = options->key.tes.as_es;
6455 break;
6456 case MESA_SHADER_TESS_CTRL:
6457 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6458 break;
6459 case MESA_SHADER_VERTEX:
6460 shader_info->vs.as_es = options->key.vs.as_es;
6461 shader_info->vs.as_ls = options->key.vs.as_ls;
6462 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6463 if (options->key.vs.as_ls)
6464 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6465 break;
6466 default:
6467 break;
6468 }
6469 }
6470
6471 static void
6472 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6473 {
6474 LLVMValueRef args[9];
6475 args[0] = ctx->gsvs_ring;
6476 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6477 args[3] = ctx->i32zero;
6478 args[4] = ctx->i32one; /* OFFEN */
6479 args[5] = ctx->i32zero; /* IDXEN */
6480 args[6] = ctx->i32one; /* GLC */
6481 args[7] = ctx->i32one; /* SLC */
6482 args[8] = ctx->i32zero; /* TFE */
6483
6484 int idx = 0;
6485
6486 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6487 int length = 4;
6488 int slot = idx;
6489 int slot_inc = 1;
6490 if (!(ctx->output_mask & (1ull << i)))
6491 continue;
6492
6493 if (i == VARYING_SLOT_CLIP_DIST0) {
6494 /* unpack clip and cull from a single set of slots */
6495 length = ctx->num_output_clips + ctx->num_output_culls;
6496 if (length > 4)
6497 slot_inc = 2;
6498 }
6499
6500 for (unsigned j = 0; j < length; j++) {
6501 LLVMValueRef value;
6502 args[2] = LLVMConstInt(ctx->i32,
6503 (slot * 4 + j) *
6504 ctx->gs_max_out_vertices * 16 * 4, false);
6505
6506 value = ac_build_intrinsic(&ctx->ac,
6507 "llvm.SI.buffer.load.dword.i32.i32",
6508 ctx->i32, args, 9,
6509 AC_FUNC_ATTR_READONLY |
6510 AC_FUNC_ATTR_LEGACY);
6511
6512 LLVMBuildStore(ctx->builder,
6513 to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6514 }
6515 idx += slot_inc;
6516 }
6517 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6518 }
6519
6520 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6521 struct nir_shader *geom_shader,
6522 struct ac_shader_binary *binary,
6523 struct ac_shader_config *config,
6524 struct ac_shader_variant_info *shader_info,
6525 const struct ac_nir_compiler_options *options,
6526 bool dump_shader)
6527 {
6528 struct nir_to_llvm_context ctx = {0};
6529 ctx.context = LLVMContextCreate();
6530 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6531 ctx.options = options;
6532 ctx.shader_info = shader_info;
6533
6534 ac_llvm_context_init(&ctx.ac, ctx.context);
6535 ctx.ac.module = ctx.module;
6536
6537 ctx.is_gs_copy_shader = true;
6538 LLVMSetTarget(ctx.module, "amdgcn--");
6539 setup_types(&ctx);
6540
6541 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6542 ctx.ac.builder = ctx.builder;
6543 ctx.stage = MESA_SHADER_VERTEX;
6544
6545 create_function(&ctx);
6546
6547 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6548 ac_setup_rings(&ctx);
6549
6550 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6551 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6552
6553 struct ac_nir_context nir_ctx = {};
6554 nir_ctx.ac = ctx.ac;
6555 nir_ctx.abi = &ctx.abi;
6556
6557 nir_ctx.nctx = &ctx;
6558 ctx.nir = &nir_ctx;
6559
6560 nir_foreach_variable(variable, &geom_shader->outputs) {
6561 scan_shader_output_decl(&ctx, variable);
6562 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6563 }
6564
6565 ac_gs_copy_shader_emit(&ctx);
6566
6567 ctx.nir = NULL;
6568
6569 LLVMBuildRetVoid(ctx.builder);
6570
6571 ac_llvm_finalize_module(&ctx);
6572
6573 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6574 MESA_SHADER_VERTEX,
6575 dump_shader, options->supports_spill);
6576 }