2 * Copyright © 2016 Bas Nieuwenhuizen
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
37 enum radeon_llvm_calling_convention
{
38 RADEON_LLVM_AMDGPU_VS
= 87,
39 RADEON_LLVM_AMDGPU_GS
= 88,
40 RADEON_LLVM_AMDGPU_PS
= 89,
41 RADEON_LLVM_AMDGPU_CS
= 90,
42 RADEON_LLVM_AMDGPU_HS
= 93,
45 #define CONST_ADDR_SPACE 2
46 #define LOCAL_ADDR_SPACE 3
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51 struct nir_to_llvm_context
;
53 struct ac_nir_context
{
54 struct ac_llvm_context ac
;
55 struct ac_shader_abi
*abi
;
57 gl_shader_stage stage
;
59 struct hash_table
*defs
;
60 struct hash_table
*phis
;
61 struct hash_table
*vars
;
63 LLVMValueRef main_function
;
64 LLVMBasicBlockRef continue_block
;
65 LLVMBasicBlockRef break_block
;
67 LLVMValueRef outputs
[RADEON_LLVM_MAX_OUTPUTS
* 4];
72 struct nir_to_llvm_context
*nctx
; /* TODO get rid of this */
75 struct nir_to_llvm_context
{
76 struct ac_llvm_context ac
;
77 const struct ac_nir_compiler_options
*options
;
78 struct ac_shader_variant_info
*shader_info
;
79 struct ac_shader_abi abi
;
80 struct ac_nir_context
*nir
;
82 unsigned max_workgroup_size
;
83 LLVMContextRef context
;
85 LLVMBuilderRef builder
;
86 LLVMValueRef main_function
;
88 struct hash_table
*defs
;
89 struct hash_table
*phis
;
91 LLVMValueRef descriptor_sets
[AC_UD_MAX_SETS
];
92 LLVMValueRef ring_offsets
;
93 LLVMValueRef push_constants
;
94 LLVMValueRef view_index
;
95 LLVMValueRef num_work_groups
;
96 LLVMValueRef workgroup_ids
;
97 LLVMValueRef local_invocation_ids
;
100 LLVMValueRef vertex_buffers
;
101 LLVMValueRef rel_auto_id
;
102 LLVMValueRef vs_prim_id
;
103 LLVMValueRef ls_out_layout
;
104 LLVMValueRef es2gs_offset
;
106 LLVMValueRef tcs_offchip_layout
;
107 LLVMValueRef tcs_out_offsets
;
108 LLVMValueRef tcs_out_layout
;
109 LLVMValueRef tcs_in_layout
;
111 LLVMValueRef merged_wave_info
;
112 LLVMValueRef tess_factor_offset
;
113 LLVMValueRef tcs_patch_id
;
114 LLVMValueRef tcs_rel_ids
;
115 LLVMValueRef tes_rel_patch_id
;
116 LLVMValueRef tes_patch_id
;
120 LLVMValueRef gsvs_ring_stride
;
121 LLVMValueRef gsvs_num_entries
;
122 LLVMValueRef gs2vs_offset
;
123 LLVMValueRef gs_wave_id
;
124 LLVMValueRef gs_vtx_offset
[6];
125 LLVMValueRef gs_prim_id
, gs_invocation_id
;
127 LLVMValueRef esgs_ring
;
128 LLVMValueRef gsvs_ring
;
129 LLVMValueRef hs_ring_tess_offchip
;
130 LLVMValueRef hs_ring_tess_factor
;
132 LLVMValueRef prim_mask
;
133 LLVMValueRef sample_pos_offset
;
134 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
135 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
154 LLVMValueRef i1false
;
155 LLVMValueRef i32zero
;
157 LLVMValueRef f32zero
;
159 LLVMValueRef v4f32empty
;
161 unsigned uniform_md_kind
;
162 LLVMValueRef empty_md
;
163 gl_shader_stage stage
;
166 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
169 uint64_t output_mask
;
170 uint8_t num_output_clips
;
171 uint8_t num_output_culls
;
173 bool is_gs_copy_shader
;
174 LLVMValueRef gs_next_vertex
;
175 unsigned gs_max_out_vertices
;
177 unsigned tes_primitive_mode
;
178 uint64_t tess_outputs_written
;
179 uint64_t tess_patch_outputs_written
;
182 static inline struct nir_to_llvm_context
*
183 nir_to_llvm_context_from_abi(struct ac_shader_abi
*abi
)
185 struct nir_to_llvm_context
*ctx
= NULL
;
186 return container_of(abi
, ctx
, abi
);
189 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
190 const nir_deref_var
*deref
,
191 enum ac_descriptor_type desc_type
,
192 bool image
, bool write
);
194 static unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
)
196 return (index
* 4) + chan
;
199 static unsigned shader_io_get_unique_index(gl_varying_slot slot
)
201 /* handle patch indices separate */
202 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
204 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
206 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
207 return 2 + (slot
- VARYING_SLOT_PATCH0
);
209 if (slot
== VARYING_SLOT_POS
)
211 if (slot
== VARYING_SLOT_PSIZ
)
213 if (slot
== VARYING_SLOT_CLIP_DIST0
)
215 /* 3 is reserved for clip dist as well */
216 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
217 return 4 + (slot
- VARYING_SLOT_VAR0
);
218 unreachable("illegal slot in get unique index\n");
221 static void set_llvm_calling_convention(LLVMValueRef func
,
222 gl_shader_stage stage
)
224 enum radeon_llvm_calling_convention calling_conv
;
227 case MESA_SHADER_VERTEX
:
228 case MESA_SHADER_TESS_EVAL
:
229 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
231 case MESA_SHADER_GEOMETRY
:
232 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
234 case MESA_SHADER_TESS_CTRL
:
235 calling_conv
= HAVE_LLVM
>= 0x0500 ? RADEON_LLVM_AMDGPU_HS
: RADEON_LLVM_AMDGPU_VS
;
237 case MESA_SHADER_FRAGMENT
:
238 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
240 case MESA_SHADER_COMPUTE
:
241 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
244 unreachable("Unhandle shader type");
247 LLVMSetFunctionCallConv(func
, calling_conv
);
252 LLVMTypeRef types
[MAX_ARGS
];
253 LLVMValueRef
*assign
[MAX_ARGS
];
254 unsigned array_params_mask
;
256 uint8_t user_sgpr_count
;
258 uint8_t num_user_sgprs_used
;
259 uint8_t num_sgprs_used
;
260 uint8_t num_vgprs_used
;
264 add_argument(struct arg_info
*info
,
265 LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
267 assert(info
->count
< MAX_ARGS
);
268 info
->assign
[info
->count
] = param_ptr
;
269 info
->types
[info
->count
] = type
;
274 add_sgpr_argument(struct arg_info
*info
,
275 LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
277 add_argument(info
, type
, param_ptr
);
278 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
283 add_user_sgpr_argument(struct arg_info
*info
,
285 LLVMValueRef
*param_ptr
)
287 add_sgpr_argument(info
, type
, param_ptr
);
288 info
->num_user_sgprs_used
+= ac_get_type_size(type
) / 4;
289 info
->user_sgpr_count
++;
293 add_vgpr_argument(struct arg_info
*info
,
295 LLVMValueRef
*param_ptr
)
297 add_argument(info
, type
, param_ptr
);
298 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
302 add_user_sgpr_array_argument(struct arg_info
*info
,
304 LLVMValueRef
*param_ptr
)
306 info
->array_params_mask
|= (1 << info
->count
);
307 add_user_sgpr_argument(info
, type
, param_ptr
);
310 static void assign_arguments(LLVMValueRef main_function
,
311 struct arg_info
*info
)
314 for (i
= 0; i
< info
->count
; i
++) {
316 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
321 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
322 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
323 unsigned num_return_elems
,
324 struct arg_info
*args
,
325 unsigned max_workgroup_size
,
328 LLVMTypeRef main_function_type
, ret_type
;
329 LLVMBasicBlockRef main_function_body
;
331 if (num_return_elems
)
332 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
333 num_return_elems
, true);
335 ret_type
= LLVMVoidTypeInContext(ctx
);
337 /* Setup the function */
339 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
340 LLVMValueRef main_function
=
341 LLVMAddFunction(module
, "main", main_function_type
);
343 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
344 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
346 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
347 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
348 if (args
->array_params_mask
& (1 << i
)) {
349 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
350 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_BYVAL
);
351 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
354 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
358 if (max_workgroup_size
) {
359 ac_llvm_add_target_dep_function_attr(main_function
,
360 "amdgpu-max-work-group-size",
364 /* These were copied from some LLVM test. */
365 LLVMAddTargetDependentFunctionAttr(main_function
,
366 "less-precise-fpmad",
368 LLVMAddTargetDependentFunctionAttr(main_function
,
371 LLVMAddTargetDependentFunctionAttr(main_function
,
374 LLVMAddTargetDependentFunctionAttr(main_function
,
378 return main_function
;
381 static LLVMTypeRef
const_array(LLVMTypeRef elem_type
, int num_elements
)
383 return LLVMPointerType(LLVMArrayType(elem_type
, num_elements
),
387 static int get_elem_bits(struct ac_llvm_context
*ctx
, LLVMTypeRef type
)
389 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
390 type
= LLVMGetElementType(type
);
392 if (LLVMGetTypeKind(type
) == LLVMIntegerTypeKind
)
393 return LLVMGetIntTypeWidth(type
);
395 if (type
== ctx
->f16
)
397 if (type
== ctx
->f32
)
399 if (type
== ctx
->f64
)
402 unreachable("Unhandled type kind in get_elem_bits");
405 static LLVMValueRef
unpack_param(struct ac_llvm_context
*ctx
,
406 LLVMValueRef param
, unsigned rshift
,
409 LLVMValueRef value
= param
;
411 value
= LLVMBuildLShr(ctx
->builder
, value
,
412 LLVMConstInt(ctx
->i32
, rshift
, false), "");
414 if (rshift
+ bitwidth
< 32) {
415 unsigned mask
= (1 << bitwidth
) - 1;
416 value
= LLVMBuildAnd(ctx
->builder
, value
,
417 LLVMConstInt(ctx
->i32
, mask
, false), "");
422 static LLVMValueRef
get_rel_patch_id(struct nir_to_llvm_context
*ctx
)
424 switch (ctx
->stage
) {
425 case MESA_SHADER_TESS_CTRL
:
426 return unpack_param(&ctx
->ac
, ctx
->tcs_rel_ids
, 0, 8);
427 case MESA_SHADER_TESS_EVAL
:
428 return ctx
->tes_rel_patch_id
;
431 unreachable("Illegal stage");
435 /* Tessellation shaders pass outputs to the next shader using LDS.
437 * LS outputs = TCS inputs
438 * TCS outputs = TES inputs
441 * - TCS inputs for patch 0
442 * - TCS inputs for patch 1
443 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
445 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
446 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
447 * - TCS outputs for patch 1
448 * - Per-patch TCS outputs for patch 1
449 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
450 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
453 * All three shaders VS(LS), TCS, TES share the same LDS space.
456 get_tcs_in_patch_stride(struct nir_to_llvm_context
*ctx
)
458 if (ctx
->stage
== MESA_SHADER_VERTEX
)
459 return unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 0, 13);
460 else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
461 return unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 0, 13);
469 get_tcs_out_patch_stride(struct nir_to_llvm_context
*ctx
)
471 return unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 0, 13);
475 get_tcs_out_patch0_offset(struct nir_to_llvm_context
*ctx
)
477 return LLVMBuildMul(ctx
->builder
,
478 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 0, 16),
479 LLVMConstInt(ctx
->i32
, 4, false), "");
483 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context
*ctx
)
485 return LLVMBuildMul(ctx
->builder
,
486 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 16, 16),
487 LLVMConstInt(ctx
->i32
, 4, false), "");
491 get_tcs_in_current_patch_offset(struct nir_to_llvm_context
*ctx
)
493 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
494 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
496 return LLVMBuildMul(ctx
->builder
, patch_stride
, rel_patch_id
, "");
500 get_tcs_out_current_patch_offset(struct nir_to_llvm_context
*ctx
)
502 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
503 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
504 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
506 return LLVMBuildAdd(ctx
->builder
, patch0_offset
,
507 LLVMBuildMul(ctx
->builder
, patch_stride
,
513 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context
*ctx
)
515 LLVMValueRef patch0_patch_data_offset
=
516 get_tcs_out_patch0_patch_data_offset(ctx
);
517 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
518 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
520 return LLVMBuildAdd(ctx
->builder
, patch0_patch_data_offset
,
521 LLVMBuildMul(ctx
->builder
, patch_stride
,
526 static void set_userdata_location(struct ac_userdata_info
*ud_info
, uint8_t *sgpr_idx
, uint8_t num_sgprs
)
528 ud_info
->sgpr_idx
= *sgpr_idx
;
529 ud_info
->num_sgprs
= num_sgprs
;
530 ud_info
->indirect
= false;
531 ud_info
->indirect_offset
= 0;
532 *sgpr_idx
+= num_sgprs
;
535 static void set_userdata_location_shader(struct nir_to_llvm_context
*ctx
,
536 int idx
, uint8_t *sgpr_idx
, uint8_t num_sgprs
)
538 set_userdata_location(&ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
], sgpr_idx
, num_sgprs
);
542 static void set_userdata_location_indirect(struct ac_userdata_info
*ud_info
, uint8_t sgpr_idx
, uint8_t num_sgprs
,
543 uint32_t indirect_offset
)
545 ud_info
->sgpr_idx
= sgpr_idx
;
546 ud_info
->num_sgprs
= num_sgprs
;
547 ud_info
->indirect
= true;
548 ud_info
->indirect_offset
= indirect_offset
;
551 static void declare_tess_lds(struct nir_to_llvm_context
*ctx
)
553 unsigned lds_size
= ctx
->options
->chip_class
>= CIK
? 65536 : 32768;
554 ctx
->lds
= LLVMBuildIntToPtr(ctx
->builder
, ctx
->i32zero
,
555 LLVMPointerType(LLVMArrayType(ctx
->i32
, lds_size
/ 4), LOCAL_ADDR_SPACE
),
559 struct user_sgpr_info
{
560 bool need_ring_offsets
;
562 bool indirect_all_descriptor_sets
;
565 static void allocate_user_sgprs(struct nir_to_llvm_context
*ctx
,
566 struct user_sgpr_info
*user_sgpr_info
)
568 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
570 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
571 if (ctx
->stage
== MESA_SHADER_GEOMETRY
||
572 ctx
->stage
== MESA_SHADER_VERTEX
||
573 ctx
->stage
== MESA_SHADER_TESS_CTRL
||
574 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
575 ctx
->is_gs_copy_shader
)
576 user_sgpr_info
->need_ring_offsets
= true;
578 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&&
579 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
580 user_sgpr_info
->need_ring_offsets
= true;
582 /* 2 user sgprs will nearly always be allocated for scratch/rings */
583 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
584 user_sgpr_info
->sgpr_count
+= 2;
587 switch (ctx
->stage
) {
588 case MESA_SHADER_COMPUTE
:
589 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.cs
.grid_components_used
;
591 case MESA_SHADER_FRAGMENT
:
592 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
594 case MESA_SHADER_VERTEX
:
595 if (!ctx
->is_gs_copy_shader
) {
596 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.vs
.has_vertex_buffers
? 2 : 0;
597 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
598 user_sgpr_info
->sgpr_count
+= 3;
600 user_sgpr_info
->sgpr_count
+= 2;
603 if (ctx
->options
->key
.vs
.as_ls
)
604 user_sgpr_info
->sgpr_count
++;
606 case MESA_SHADER_TESS_CTRL
:
607 user_sgpr_info
->sgpr_count
+= 4;
609 case MESA_SHADER_TESS_EVAL
:
610 user_sgpr_info
->sgpr_count
+= 1;
612 case MESA_SHADER_GEOMETRY
:
613 user_sgpr_info
->sgpr_count
+= 2;
619 if (ctx
->shader_info
->info
.needs_push_constants
)
620 user_sgpr_info
->sgpr_count
+= 2;
622 uint32_t remaining_sgprs
= 16 - user_sgpr_info
->sgpr_count
;
623 if (remaining_sgprs
/ 2 < util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
)) {
624 user_sgpr_info
->sgpr_count
+= 2;
625 user_sgpr_info
->indirect_all_descriptor_sets
= true;
627 user_sgpr_info
->sgpr_count
+= util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
) * 2;
632 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context
*ctx
,
633 gl_shader_stage stage
,
634 bool has_previous_stage
,
635 gl_shader_stage previous_stage
,
636 const struct user_sgpr_info
*user_sgpr_info
,
637 struct arg_info
*args
,
638 LLVMValueRef
*desc_sets
)
640 unsigned num_sets
= ctx
->options
->layout
? ctx
->options
->layout
->num_sets
: 0;
641 unsigned stage_mask
= 1 << stage
;
642 if (has_previous_stage
)
643 stage_mask
|= 1 << previous_stage
;
645 /* 1 for each descriptor set */
646 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
647 for (unsigned i
= 0; i
< num_sets
; ++i
) {
648 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
649 add_user_sgpr_array_argument(args
, const_array(ctx
->i8
, 1024 * 1024), &ctx
->descriptor_sets
[i
]);
653 add_user_sgpr_array_argument(args
, const_array(const_array(ctx
->i8
, 1024 * 1024), 32), desc_sets
);
655 if (ctx
->shader_info
->info
.needs_push_constants
) {
656 /* 1 for push constants and dynamic descriptors */
657 add_user_sgpr_array_argument(args
, const_array(ctx
->i8
, 1024 * 1024), &ctx
->push_constants
);
662 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context
*ctx
,
663 gl_shader_stage stage
,
664 bool has_previous_stage
,
665 gl_shader_stage previous_stage
,
666 const struct user_sgpr_info
*user_sgpr_info
,
667 LLVMValueRef desc_sets
,
668 uint8_t *user_sgpr_idx
)
670 unsigned num_sets
= ctx
->options
->layout
? ctx
->options
->layout
->num_sets
: 0;
671 unsigned stage_mask
= 1 << stage
;
672 if (has_previous_stage
)
673 stage_mask
|= 1 << previous_stage
;
675 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
676 for (unsigned i
= 0; i
< num_sets
; ++i
) {
677 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
678 set_userdata_location(&ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[i
], user_sgpr_idx
, 2);
680 ctx
->descriptor_sets
[i
] = NULL
;
683 uint32_t desc_sgpr_idx
= *user_sgpr_idx
;
684 set_userdata_location_shader(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
, user_sgpr_idx
, 2);
686 for (unsigned i
= 0; i
< num_sets
; ++i
) {
687 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
688 set_userdata_location_indirect(&ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[i
], desc_sgpr_idx
, 2, i
* 8);
689 ctx
->descriptor_sets
[i
] = ac_build_load_to_sgpr(&ctx
->ac
, desc_sets
, LLVMConstInt(ctx
->i32
, i
, false));
692 ctx
->descriptor_sets
[i
] = NULL
;
694 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
697 if (ctx
->shader_info
->info
.needs_push_constants
) {
698 set_userdata_location_shader(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
, 2);
703 radv_define_vs_user_sgprs_phase1(struct nir_to_llvm_context
*ctx
,
704 gl_shader_stage stage
,
705 bool has_previous_stage
,
706 gl_shader_stage previous_stage
,
707 struct arg_info
*args
)
709 if (!ctx
->is_gs_copy_shader
&& (stage
== MESA_SHADER_VERTEX
|| (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
710 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
)
711 add_user_sgpr_argument(args
, const_array(ctx
->v4i32
, 16), &ctx
->vertex_buffers
); /* vertex buffers */
712 add_user_sgpr_argument(args
, ctx
->i32
, &ctx
->abi
.base_vertex
); // base vertex
713 add_user_sgpr_argument(args
, ctx
->i32
, &ctx
->abi
.start_instance
);// start instance
714 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
715 add_user_sgpr_argument(args
, ctx
->i32
, &ctx
->abi
.draw_id
); // draw id
720 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context
*ctx
,
721 gl_shader_stage stage
,
722 bool has_previous_stage
,
723 gl_shader_stage previous_stage
,
724 uint8_t *user_sgpr_idx
)
726 if (!ctx
->is_gs_copy_shader
&& (stage
== MESA_SHADER_VERTEX
|| (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
727 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
728 set_userdata_location_shader(ctx
, AC_UD_VS_VERTEX_BUFFERS
, user_sgpr_idx
, 2);
731 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
734 set_userdata_location_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
, user_sgpr_idx
, vs_num
);
739 static void create_function(struct nir_to_llvm_context
*ctx
,
740 gl_shader_stage stage
,
741 bool has_previous_stage
,
742 gl_shader_stage previous_stage
)
744 uint8_t user_sgpr_idx
;
745 struct user_sgpr_info user_sgpr_info
;
746 struct arg_info args
= {};
747 LLVMValueRef desc_sets
;
749 allocate_user_sgprs(ctx
, &user_sgpr_info
);
751 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
752 add_user_sgpr_argument(&args
, const_array(ctx
->v4i32
, 16), &ctx
->ring_offsets
); /* address of rings */
756 case MESA_SHADER_COMPUTE
:
757 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
758 if (ctx
->shader_info
->info
.cs
.grid_components_used
)
759 add_user_sgpr_argument(&args
, LLVMVectorType(ctx
->i32
, ctx
->shader_info
->info
.cs
.grid_components_used
), &ctx
->num_work_groups
); /* grid size */
760 add_sgpr_argument(&args
, LLVMVectorType(ctx
->i32
, 3), &ctx
->workgroup_ids
);
761 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->tg_size
);
762 add_vgpr_argument(&args
, LLVMVectorType(ctx
->i32
, 3), &ctx
->local_invocation_ids
);
764 case MESA_SHADER_VERTEX
:
765 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
766 radv_define_vs_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &args
);
767 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
768 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->view_index
);
769 if (ctx
->options
->key
.vs
.as_es
)
770 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->es2gs_offset
); // es2gs offset
771 else if (ctx
->options
->key
.vs
.as_ls
)
772 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->ls_out_layout
); // ls out layout
773 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->abi
.vertex_id
); // vertex id
774 if (!ctx
->is_gs_copy_shader
) {
775 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->rel_auto_id
); // rel auto id
776 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->vs_prim_id
); // vs prim id
777 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->abi
.instance_id
); // instance id
780 case MESA_SHADER_TESS_CTRL
:
781 if (has_previous_stage
) {
782 // First 6 system regs
783 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->oc_lds
); // param oc lds
784 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->merged_wave_info
); // merged wave info
785 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->tess_factor_offset
); // tess factor offset
787 add_sgpr_argument(&args
, ctx
->i32
, NULL
); // scratch offset
788 add_sgpr_argument(&args
, ctx
->i32
, NULL
); // unknown
789 add_sgpr_argument(&args
, ctx
->i32
, NULL
); // unknown
791 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
792 radv_define_vs_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &args
);
793 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->ls_out_layout
); // ls out layout
795 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_offchip_layout
); // tcs offchip layout
796 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_out_offsets
); // tcs out offsets
797 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_out_layout
); // tcs out layout
798 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_in_layout
); // tcs in layout
799 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
800 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->view_index
);
802 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_patch_id
); // patch id
803 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_rel_ids
); // rel ids;
804 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->abi
.vertex_id
); // vertex id
805 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->rel_auto_id
); // rel auto id
806 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->vs_prim_id
); // vs prim id
807 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->abi
.instance_id
); // instance id
809 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
810 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_offchip_layout
); // tcs offchip layout
811 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_out_offsets
); // tcs out offsets
812 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_out_layout
); // tcs out layout
813 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_in_layout
); // tcs in layout
814 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
815 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->view_index
);
816 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->oc_lds
); // param oc lds
817 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->tess_factor_offset
); // tess factor offset
818 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_patch_id
); // patch id
819 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_rel_ids
); // rel ids;
822 case MESA_SHADER_TESS_EVAL
:
823 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
824 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_offchip_layout
); // tcs offchip layout
825 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
826 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->view_index
);
827 if (ctx
->options
->key
.tes
.as_es
) {
828 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->oc_lds
); // OC LDS
829 add_sgpr_argument(&args
, ctx
->i32
, NULL
); //
830 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->es2gs_offset
); // es2gs offset
832 add_sgpr_argument(&args
, ctx
->i32
, NULL
); //
833 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->oc_lds
); // OC LDS
835 add_vgpr_argument(&args
, ctx
->f32
, &ctx
->tes_u
); // tes_u
836 add_vgpr_argument(&args
, ctx
->f32
, &ctx
->tes_v
); // tes_v
837 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->tes_rel_patch_id
); // tes rel patch id
838 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->tes_patch_id
); // tes patch id
840 case MESA_SHADER_GEOMETRY
:
841 if (has_previous_stage
) {
842 // First 6 system regs
843 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->gs2vs_offset
); // tess factor offset
844 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->merged_wave_info
); // merged wave info
845 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->oc_lds
); // param oc lds
847 add_sgpr_argument(&args
, ctx
->i32
, NULL
); // scratch offset
848 add_sgpr_argument(&args
, ctx
->i32
, NULL
); // unknown
849 add_sgpr_argument(&args
, ctx
->i32
, NULL
); // unknown
851 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
852 if (previous_stage
== MESA_SHADER_TESS_EVAL
)
853 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_offchip_layout
); // tcs offchip layout
855 radv_define_vs_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &args
);
856 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->gsvs_ring_stride
); // gsvs stride
857 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->gsvs_num_entries
); // gsvs num entires
858 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
859 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->view_index
);
861 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_vtx_offset
[0]); // vtx01
862 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_vtx_offset
[2]); // vtx23
863 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_prim_id
); // prim id
864 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_invocation_id
);
865 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_vtx_offset
[4]);
867 if (previous_stage
== MESA_SHADER_VERTEX
) {
868 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->abi
.vertex_id
); // vertex id
869 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->rel_auto_id
); // rel auto id
870 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->vs_prim_id
); // vs prim id
871 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->abi
.instance_id
); // instance id
873 add_vgpr_argument(&args
, ctx
->f32
, &ctx
->tes_u
); // tes_u
874 add_vgpr_argument(&args
, ctx
->f32
, &ctx
->tes_v
); // tes_v
875 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->tes_rel_patch_id
); // tes rel patch id
876 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->tes_patch_id
); // tes patch id
879 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
880 radv_define_vs_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &args
);
881 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->gsvs_ring_stride
); // gsvs stride
882 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->gsvs_num_entries
); // gsvs num entires
883 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
884 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->view_index
);
885 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->gs2vs_offset
); // gs2vs offset
886 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->gs_wave_id
); // wave id
887 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_vtx_offset
[0]); // vtx0
888 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_vtx_offset
[1]); // vtx1
889 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_prim_id
); // prim id
890 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_vtx_offset
[2]);
891 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_vtx_offset
[3]);
892 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_vtx_offset
[4]);
893 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_vtx_offset
[5]);
894 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_invocation_id
);
897 case MESA_SHADER_FRAGMENT
:
898 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
899 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
)
900 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->sample_pos_offset
); /* sample position offset */
901 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->prim_mask
); /* prim mask */
902 add_vgpr_argument(&args
, ctx
->v2i32
, &ctx
->persp_sample
); /* persp sample */
903 add_vgpr_argument(&args
, ctx
->v2i32
, &ctx
->persp_center
); /* persp center */
904 add_vgpr_argument(&args
, ctx
->v2i32
, &ctx
->persp_centroid
); /* persp centroid */
905 add_vgpr_argument(&args
, ctx
->v3i32
, NULL
); /* persp pull model */
906 add_vgpr_argument(&args
, ctx
->v2i32
, &ctx
->linear_sample
); /* linear sample */
907 add_vgpr_argument(&args
, ctx
->v2i32
, &ctx
->linear_center
); /* linear center */
908 add_vgpr_argument(&args
, ctx
->v2i32
, &ctx
->linear_centroid
); /* linear centroid */
909 add_vgpr_argument(&args
, ctx
->f32
, NULL
); /* line stipple tex */
910 add_vgpr_argument(&args
, ctx
->f32
, &ctx
->abi
.frag_pos
[0]); /* pos x float */
911 add_vgpr_argument(&args
, ctx
->f32
, &ctx
->abi
.frag_pos
[1]); /* pos y float */
912 add_vgpr_argument(&args
, ctx
->f32
, &ctx
->abi
.frag_pos
[2]); /* pos z float */
913 add_vgpr_argument(&args
, ctx
->f32
, &ctx
->abi
.frag_pos
[3]); /* pos w float */
914 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->abi
.front_face
); /* front face */
915 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->abi
.ancillary
); /* ancillary */
916 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->abi
.sample_coverage
); /* sample coverage */
917 add_vgpr_argument(&args
, ctx
->i32
, NULL
); /* fixed pt */
920 unreachable("Shader stage not implemented");
923 ctx
->main_function
= create_llvm_function(
924 ctx
->context
, ctx
->module
, ctx
->builder
, NULL
, 0, &args
,
925 ctx
->max_workgroup_size
,
926 ctx
->options
->unsafe_math
);
927 set_llvm_calling_convention(ctx
->main_function
, stage
);
930 ctx
->shader_info
->num_input_vgprs
= 0;
931 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
933 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
935 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
936 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
938 assign_arguments(ctx
->main_function
, &args
);
942 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
943 set_userdata_location_shader(ctx
, AC_UD_SCRATCH_RING_OFFSETS
, &user_sgpr_idx
, 2);
944 if (ctx
->options
->supports_spill
) {
945 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
946 LLVMPointerType(ctx
->i8
, CONST_ADDR_SPACE
),
947 NULL
, 0, AC_FUNC_ATTR_READNONE
);
948 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->builder
, ctx
->ring_offsets
,
949 const_array(ctx
->v4i32
, 16), "");
953 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
954 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
955 if (has_previous_stage
)
958 radv_define_common_user_sgprs_phase2(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
961 case MESA_SHADER_COMPUTE
:
962 if (ctx
->shader_info
->info
.cs
.grid_components_used
) {
963 set_userdata_location_shader(ctx
, AC_UD_CS_GRID_SIZE
, &user_sgpr_idx
, ctx
->shader_info
->info
.cs
.grid_components_used
);
966 case MESA_SHADER_VERTEX
:
967 radv_define_vs_user_sgprs_phase2(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_idx
);
969 set_userdata_location_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
970 if (ctx
->options
->key
.vs
.as_ls
) {
971 set_userdata_location_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
, &user_sgpr_idx
, 1);
973 if (ctx
->options
->key
.vs
.as_ls
)
974 declare_tess_lds(ctx
);
976 case MESA_SHADER_TESS_CTRL
:
977 radv_define_vs_user_sgprs_phase2(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_idx
);
978 if (has_previous_stage
)
979 set_userdata_location_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
, &user_sgpr_idx
, 1);
980 set_userdata_location_shader(ctx
, AC_UD_TCS_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 4);
982 set_userdata_location_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
983 declare_tess_lds(ctx
);
985 case MESA_SHADER_TESS_EVAL
:
986 set_userdata_location_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 1);
988 set_userdata_location_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
990 case MESA_SHADER_GEOMETRY
:
991 if (has_previous_stage
) {
992 if (previous_stage
== MESA_SHADER_VERTEX
)
993 radv_define_vs_user_sgprs_phase2(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_idx
);
995 set_userdata_location_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 1);
997 set_userdata_location_shader(ctx
, AC_UD_GS_VS_RING_STRIDE_ENTRIES
, &user_sgpr_idx
, 2);
999 set_userdata_location_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1000 if (has_previous_stage
)
1001 declare_tess_lds(ctx
);
1003 case MESA_SHADER_FRAGMENT
:
1004 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
) {
1005 set_userdata_location_shader(ctx
, AC_UD_PS_SAMPLE_POS_OFFSET
, &user_sgpr_idx
, 1);
1009 unreachable("Shader stage not implemented");
1012 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1015 static void setup_types(struct nir_to_llvm_context
*ctx
)
1017 LLVMValueRef args
[4];
1019 ctx
->voidt
= LLVMVoidTypeInContext(ctx
->context
);
1020 ctx
->i1
= LLVMIntTypeInContext(ctx
->context
, 1);
1021 ctx
->i8
= LLVMIntTypeInContext(ctx
->context
, 8);
1022 ctx
->i16
= LLVMIntTypeInContext(ctx
->context
, 16);
1023 ctx
->i32
= LLVMIntTypeInContext(ctx
->context
, 32);
1024 ctx
->i64
= LLVMIntTypeInContext(ctx
->context
, 64);
1025 ctx
->v2i32
= LLVMVectorType(ctx
->i32
, 2);
1026 ctx
->v3i32
= LLVMVectorType(ctx
->i32
, 3);
1027 ctx
->v4i32
= LLVMVectorType(ctx
->i32
, 4);
1028 ctx
->v8i32
= LLVMVectorType(ctx
->i32
, 8);
1029 ctx
->f32
= LLVMFloatTypeInContext(ctx
->context
);
1030 ctx
->f16
= LLVMHalfTypeInContext(ctx
->context
);
1031 ctx
->f64
= LLVMDoubleTypeInContext(ctx
->context
);
1032 ctx
->v2f32
= LLVMVectorType(ctx
->f32
, 2);
1033 ctx
->v4f32
= LLVMVectorType(ctx
->f32
, 4);
1035 ctx
->i1false
= LLVMConstInt(ctx
->i1
, 0, false);
1036 ctx
->i1true
= LLVMConstInt(ctx
->i1
, 1, false);
1037 ctx
->i32zero
= LLVMConstInt(ctx
->i32
, 0, false);
1038 ctx
->i32one
= LLVMConstInt(ctx
->i32
, 1, false);
1039 ctx
->f32zero
= LLVMConstReal(ctx
->f32
, 0.0);
1040 ctx
->f32one
= LLVMConstReal(ctx
->f32
, 1.0);
1042 args
[0] = ctx
->f32zero
;
1043 args
[1] = ctx
->f32zero
;
1044 args
[2] = ctx
->f32zero
;
1045 args
[3] = ctx
->f32one
;
1046 ctx
->v4f32empty
= LLVMConstVector(args
, 4);
1048 ctx
->uniform_md_kind
=
1049 LLVMGetMDKindIDInContext(ctx
->context
, "amdgpu.uniform", 14);
1050 ctx
->empty_md
= LLVMMDNodeInContext(ctx
->context
, NULL
, 0);
1052 args
[0] = LLVMConstReal(ctx
->f32
, 2.5);
1055 static int get_llvm_num_components(LLVMValueRef value
)
1057 LLVMTypeRef type
= LLVMTypeOf(value
);
1058 unsigned num_components
= LLVMGetTypeKind(type
) == LLVMVectorTypeKind
1059 ? LLVMGetVectorSize(type
)
1061 return num_components
;
1064 static LLVMValueRef
llvm_extract_elem(struct ac_llvm_context
*ac
,
1068 int count
= get_llvm_num_components(value
);
1070 assert(index
< count
);
1074 return LLVMBuildExtractElement(ac
->builder
, value
,
1075 LLVMConstInt(ac
->i32
, index
, false), "");
1078 static LLVMValueRef
trim_vector(struct ac_llvm_context
*ctx
,
1079 LLVMValueRef value
, unsigned count
)
1081 unsigned num_components
= get_llvm_num_components(value
);
1082 if (count
== num_components
)
1085 LLVMValueRef masks
[] = {
1086 LLVMConstInt(ctx
->i32
, 0, false), LLVMConstInt(ctx
->i32
, 1, false),
1087 LLVMConstInt(ctx
->i32
, 2, false), LLVMConstInt(ctx
->i32
, 3, false)};
1090 return LLVMBuildExtractElement(ctx
->builder
, value
, masks
[0],
1093 LLVMValueRef swizzle
= LLVMConstVector(masks
, count
);
1094 return LLVMBuildShuffleVector(ctx
->builder
, value
, value
, swizzle
, "");
1098 build_store_values_extended(struct ac_llvm_context
*ac
,
1099 LLVMValueRef
*values
,
1100 unsigned value_count
,
1101 unsigned value_stride
,
1104 LLVMBuilderRef builder
= ac
->builder
;
1107 for (i
= 0; i
< value_count
; i
++) {
1108 LLVMValueRef ptr
= values
[i
* value_stride
];
1109 LLVMValueRef index
= LLVMConstInt(ac
->i32
, i
, false);
1110 LLVMValueRef value
= LLVMBuildExtractElement(builder
, vec
, index
, "");
1111 LLVMBuildStore(builder
, value
, ptr
);
1115 static LLVMTypeRef
get_def_type(struct ac_nir_context
*ctx
,
1116 const nir_ssa_def
*def
)
1118 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, def
->bit_size
);
1119 if (def
->num_components
> 1) {
1120 type
= LLVMVectorType(type
, def
->num_components
);
1125 static LLVMValueRef
get_src(struct ac_nir_context
*nir
, nir_src src
)
1128 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, src
.ssa
);
1129 return (LLVMValueRef
)entry
->data
;
1133 static LLVMBasicBlockRef
get_block(struct ac_nir_context
*nir
,
1134 const struct nir_block
*b
)
1136 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, b
);
1137 return (LLVMBasicBlockRef
)entry
->data
;
1140 static LLVMValueRef
get_alu_src(struct ac_nir_context
*ctx
,
1142 unsigned num_components
)
1144 LLVMValueRef value
= get_src(ctx
, src
.src
);
1145 bool need_swizzle
= false;
1148 LLVMTypeRef type
= LLVMTypeOf(value
);
1149 unsigned src_components
= LLVMGetTypeKind(type
) == LLVMVectorTypeKind
1150 ? LLVMGetVectorSize(type
)
1153 for (unsigned i
= 0; i
< num_components
; ++i
) {
1154 assert(src
.swizzle
[i
] < src_components
);
1155 if (src
.swizzle
[i
] != i
)
1156 need_swizzle
= true;
1159 if (need_swizzle
|| num_components
!= src_components
) {
1160 LLVMValueRef masks
[] = {
1161 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[0], false),
1162 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[1], false),
1163 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[2], false),
1164 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[3], false)};
1166 if (src_components
> 1 && num_components
== 1) {
1167 value
= LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
1169 } else if (src_components
== 1 && num_components
> 1) {
1170 LLVMValueRef values
[] = {value
, value
, value
, value
};
1171 value
= ac_build_gather_values(&ctx
->ac
, values
, num_components
);
1173 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
1174 value
= LLVMBuildShuffleVector(ctx
->ac
.builder
, value
, value
,
1178 assert(!src
.negate
);
1183 static LLVMValueRef
emit_int_cmp(struct ac_llvm_context
*ctx
,
1184 LLVMIntPredicate pred
, LLVMValueRef src0
,
1187 LLVMValueRef result
= LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, "");
1188 return LLVMBuildSelect(ctx
->builder
, result
,
1189 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1190 LLVMConstInt(ctx
->i32
, 0, false), "");
1193 static LLVMValueRef
emit_float_cmp(struct ac_llvm_context
*ctx
,
1194 LLVMRealPredicate pred
, LLVMValueRef src0
,
1197 LLVMValueRef result
;
1198 src0
= ac_to_float(ctx
, src0
);
1199 src1
= ac_to_float(ctx
, src1
);
1200 result
= LLVMBuildFCmp(ctx
->builder
, pred
, src0
, src1
, "");
1201 return LLVMBuildSelect(ctx
->builder
, result
,
1202 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1203 LLVMConstInt(ctx
->i32
, 0, false), "");
1206 static LLVMValueRef
emit_intrin_1f_param(struct ac_llvm_context
*ctx
,
1208 LLVMTypeRef result_type
,
1212 LLVMValueRef params
[] = {
1213 ac_to_float(ctx
, src0
),
1216 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1217 get_elem_bits(ctx
, result_type
));
1218 assert(length
< sizeof(name
));
1219 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 1, AC_FUNC_ATTR_READNONE
);
1222 static LLVMValueRef
emit_intrin_2f_param(struct ac_llvm_context
*ctx
,
1224 LLVMTypeRef result_type
,
1225 LLVMValueRef src0
, LLVMValueRef src1
)
1228 LLVMValueRef params
[] = {
1229 ac_to_float(ctx
, src0
),
1230 ac_to_float(ctx
, src1
),
1233 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1234 get_elem_bits(ctx
, result_type
));
1235 assert(length
< sizeof(name
));
1236 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 2, AC_FUNC_ATTR_READNONE
);
1239 static LLVMValueRef
emit_intrin_3f_param(struct ac_llvm_context
*ctx
,
1241 LLVMTypeRef result_type
,
1242 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1245 LLVMValueRef params
[] = {
1246 ac_to_float(ctx
, src0
),
1247 ac_to_float(ctx
, src1
),
1248 ac_to_float(ctx
, src2
),
1251 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1252 get_elem_bits(ctx
, result_type
));
1253 assert(length
< sizeof(name
));
1254 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 3, AC_FUNC_ATTR_READNONE
);
1257 static LLVMValueRef
emit_bcsel(struct ac_llvm_context
*ctx
,
1258 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1260 LLVMValueRef v
= LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
,
1262 return LLVMBuildSelect(ctx
->builder
, v
, src1
, src2
, "");
1265 static LLVMValueRef
emit_find_lsb(struct ac_llvm_context
*ctx
,
1268 LLVMValueRef params
[2] = {
1271 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1272 * add special code to check for x=0. The reason is that
1273 * the LLVM behavior for x=0 is different from what we
1276 * The hardware already implements the correct behavior.
1278 LLVMConstInt(ctx
->i1
, 1, false),
1281 LLVMValueRef lsb
= ac_build_intrinsic(ctx
, "llvm.cttz.i32", ctx
->i32
,
1283 AC_FUNC_ATTR_READNONE
);
1285 /* TODO: We need an intrinsic to skip this conditional. */
1286 /* Check for zero: */
1287 return LLVMBuildSelect(ctx
->builder
, LLVMBuildICmp(ctx
->builder
,
1290 LLVMConstInt(ctx
->i32
, -1, 0), lsb
, "");
1293 static LLVMValueRef
emit_ifind_msb(struct ac_llvm_context
*ctx
,
1296 return ac_build_imsb(ctx
, src0
, ctx
->i32
);
1299 static LLVMValueRef
emit_ufind_msb(struct ac_llvm_context
*ctx
,
1302 return ac_build_umsb(ctx
, src0
, ctx
->i32
);
1305 static LLVMValueRef
emit_minmax_int(struct ac_llvm_context
*ctx
,
1306 LLVMIntPredicate pred
,
1307 LLVMValueRef src0
, LLVMValueRef src1
)
1309 return LLVMBuildSelect(ctx
->builder
,
1310 LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, ""),
1315 static LLVMValueRef
emit_iabs(struct ac_llvm_context
*ctx
,
1318 return emit_minmax_int(ctx
, LLVMIntSGT
, src0
,
1319 LLVMBuildNeg(ctx
->builder
, src0
, ""));
1322 static LLVMValueRef
emit_fsign(struct ac_llvm_context
*ctx
,
1325 LLVMValueRef cmp
, val
;
1327 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGT
, src0
, ctx
->f32_0
, "");
1328 val
= LLVMBuildSelect(ctx
->builder
, cmp
, ctx
->f32_1
, src0
, "");
1329 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
, val
, ctx
->f32_0
, "");
1330 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstReal(ctx
->f32
, -1.0), "");
1334 static LLVMValueRef
emit_isign(struct ac_llvm_context
*ctx
,
1337 LLVMValueRef cmp
, val
;
1339 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGT
, src0
, ctx
->i32_0
, "");
1340 val
= LLVMBuildSelect(ctx
->builder
, cmp
, ctx
->i32_1
, src0
, "");
1341 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGE
, val
, ctx
->i32_0
, "");
1342 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstInt(ctx
->i32
, -1, true), "");
1346 static LLVMValueRef
emit_ffract(struct ac_llvm_context
*ctx
,
1349 const char *intr
= "llvm.floor.f32";
1350 LLVMValueRef fsrc0
= ac_to_float(ctx
, src0
);
1351 LLVMValueRef params
[] = {
1354 LLVMValueRef floor
= ac_build_intrinsic(ctx
, intr
,
1355 ctx
->f32
, params
, 1,
1356 AC_FUNC_ATTR_READNONE
);
1357 return LLVMBuildFSub(ctx
->builder
, fsrc0
, floor
, "");
1360 static LLVMValueRef
emit_uint_carry(struct ac_llvm_context
*ctx
,
1362 LLVMValueRef src0
, LLVMValueRef src1
)
1364 LLVMTypeRef ret_type
;
1365 LLVMTypeRef types
[] = { ctx
->i32
, ctx
->i1
};
1367 LLVMValueRef params
[] = { src0
, src1
};
1368 ret_type
= LLVMStructTypeInContext(ctx
->context
, types
,
1371 res
= ac_build_intrinsic(ctx
, intrin
, ret_type
,
1372 params
, 2, AC_FUNC_ATTR_READNONE
);
1374 res
= LLVMBuildExtractValue(ctx
->builder
, res
, 1, "");
1375 res
= LLVMBuildZExt(ctx
->builder
, res
, ctx
->i32
, "");
1379 static LLVMValueRef
emit_b2f(struct ac_llvm_context
*ctx
,
1382 return LLVMBuildAnd(ctx
->builder
, src0
, LLVMBuildBitCast(ctx
->builder
, LLVMConstReal(ctx
->f32
, 1.0), ctx
->i32
, ""), "");
1385 static LLVMValueRef
emit_f2b(struct ac_llvm_context
*ctx
,
1388 src0
= ac_to_float(ctx
, src0
);
1389 return LLVMBuildSExt(ctx
->builder
,
1390 LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
, src0
, ctx
->f32_0
, ""),
1394 static LLVMValueRef
emit_b2i(struct ac_llvm_context
*ctx
,
1397 return LLVMBuildAnd(ctx
->builder
, src0
, ctx
->i32_1
, "");
1400 static LLVMValueRef
emit_i2b(struct ac_llvm_context
*ctx
,
1403 return LLVMBuildSExt(ctx
->builder
,
1404 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
, ctx
->i32_0
, ""),
1408 static LLVMValueRef
emit_f2f16(struct nir_to_llvm_context
*ctx
,
1411 LLVMValueRef result
;
1412 LLVMValueRef cond
= NULL
;
1414 src0
= ac_to_float(&ctx
->ac
, src0
);
1415 result
= LLVMBuildFPTrunc(ctx
->builder
, src0
, ctx
->f16
, "");
1417 if (ctx
->options
->chip_class
>= VI
) {
1418 LLVMValueRef args
[2];
1419 /* Check if the result is a denormal - and flush to 0 if so. */
1421 args
[1] = LLVMConstInt(ctx
->i32
, N_SUBNORMAL
| P_SUBNORMAL
, false);
1422 cond
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.class.f16", ctx
->i1
, args
, 2, AC_FUNC_ATTR_READNONE
);
1425 /* need to convert back up to f32 */
1426 result
= LLVMBuildFPExt(ctx
->builder
, result
, ctx
->f32
, "");
1428 if (ctx
->options
->chip_class
>= VI
)
1429 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->f32zero
, result
, "");
1432 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1433 * so compare the result and flush to 0 if it's smaller.
1435 LLVMValueRef temp
, cond2
;
1436 temp
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1438 cond
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUGT
,
1439 LLVMBuildBitCast(ctx
->builder
, LLVMConstInt(ctx
->i32
, 0x38800000, false), ctx
->f32
, ""),
1441 cond2
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
,
1442 temp
, ctx
->f32zero
, "");
1443 cond
= LLVMBuildAnd(ctx
->builder
, cond
, cond2
, "");
1444 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->f32zero
, result
, "");
1449 static LLVMValueRef
emit_umul_high(struct ac_llvm_context
*ctx
,
1450 LLVMValueRef src0
, LLVMValueRef src1
)
1452 LLVMValueRef dst64
, result
;
1453 src0
= LLVMBuildZExt(ctx
->builder
, src0
, ctx
->i64
, "");
1454 src1
= LLVMBuildZExt(ctx
->builder
, src1
, ctx
->i64
, "");
1456 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1457 dst64
= LLVMBuildLShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1458 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1462 static LLVMValueRef
emit_imul_high(struct ac_llvm_context
*ctx
,
1463 LLVMValueRef src0
, LLVMValueRef src1
)
1465 LLVMValueRef dst64
, result
;
1466 src0
= LLVMBuildSExt(ctx
->builder
, src0
, ctx
->i64
, "");
1467 src1
= LLVMBuildSExt(ctx
->builder
, src1
, ctx
->i64
, "");
1469 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1470 dst64
= LLVMBuildAShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1471 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1475 static LLVMValueRef
emit_bitfield_extract(struct ac_llvm_context
*ctx
,
1477 const LLVMValueRef srcs
[3])
1479 LLVMValueRef result
;
1480 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, srcs
[2], LLVMConstInt(ctx
->i32
, 32, false), "");
1482 result
= ac_build_bfe(ctx
, srcs
[0], srcs
[1], srcs
[2], is_signed
);
1483 result
= LLVMBuildSelect(ctx
->builder
, icond
, srcs
[0], result
, "");
1487 static LLVMValueRef
emit_bitfield_insert(struct ac_llvm_context
*ctx
,
1488 LLVMValueRef src0
, LLVMValueRef src1
,
1489 LLVMValueRef src2
, LLVMValueRef src3
)
1491 LLVMValueRef bfi_args
[3], result
;
1493 bfi_args
[0] = LLVMBuildShl(ctx
->builder
,
1494 LLVMBuildSub(ctx
->builder
,
1495 LLVMBuildShl(ctx
->builder
,
1500 bfi_args
[1] = LLVMBuildShl(ctx
->builder
, src1
, src2
, "");
1503 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, src3
, LLVMConstInt(ctx
->i32
, 32, false), "");
1506 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1507 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1509 result
= LLVMBuildXor(ctx
->builder
, bfi_args
[2],
1510 LLVMBuildAnd(ctx
->builder
, bfi_args
[0],
1511 LLVMBuildXor(ctx
->builder
, bfi_args
[1], bfi_args
[2], ""), ""), "");
1513 result
= LLVMBuildSelect(ctx
->builder
, icond
, src1
, result
, "");
1517 static LLVMValueRef
emit_pack_half_2x16(struct ac_llvm_context
*ctx
,
1520 LLVMValueRef const16
= LLVMConstInt(ctx
->i32
, 16, false);
1522 LLVMValueRef comp
[2];
1524 src0
= ac_to_float(ctx
, src0
);
1525 comp
[0] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_0
, "");
1526 comp
[1] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_1
, "");
1527 for (i
= 0; i
< 2; i
++) {
1528 comp
[i
] = LLVMBuildFPTrunc(ctx
->builder
, comp
[i
], ctx
->f16
, "");
1529 comp
[i
] = LLVMBuildBitCast(ctx
->builder
, comp
[i
], ctx
->i16
, "");
1530 comp
[i
] = LLVMBuildZExt(ctx
->builder
, comp
[i
], ctx
->i32
, "");
1533 comp
[1] = LLVMBuildShl(ctx
->builder
, comp
[1], const16
, "");
1534 comp
[0] = LLVMBuildOr(ctx
->builder
, comp
[0], comp
[1], "");
1539 static LLVMValueRef
emit_unpack_half_2x16(struct ac_llvm_context
*ctx
,
1542 LLVMValueRef const16
= LLVMConstInt(ctx
->i32
, 16, false);
1543 LLVMValueRef temps
[2], result
, val
;
1546 for (i
= 0; i
< 2; i
++) {
1547 val
= i
== 1 ? LLVMBuildLShr(ctx
->builder
, src0
, const16
, "") : src0
;
1548 val
= LLVMBuildTrunc(ctx
->builder
, val
, ctx
->i16
, "");
1549 val
= LLVMBuildBitCast(ctx
->builder
, val
, ctx
->f16
, "");
1550 temps
[i
] = LLVMBuildFPExt(ctx
->builder
, val
, ctx
->f32
, "");
1553 LLVMTypeRef v2f32
= LLVMVectorType(ctx
->f32
, 2);
1554 result
= LLVMBuildInsertElement(ctx
->builder
, LLVMGetUndef(v2f32
), temps
[0],
1556 result
= LLVMBuildInsertElement(ctx
->builder
, result
, temps
[1],
1561 static LLVMValueRef
emit_ddxy(struct ac_nir_context
*ctx
,
1567 LLVMValueRef result
;
1569 if (op
== nir_op_fddx_fine
|| op
== nir_op_fddx
)
1570 mask
= AC_TID_MASK_LEFT
;
1571 else if (op
== nir_op_fddy_fine
|| op
== nir_op_fddy
)
1572 mask
= AC_TID_MASK_TOP
;
1574 mask
= AC_TID_MASK_TOP_LEFT
;
1576 /* for DDX we want to next X pixel, DDY next Y pixel. */
1577 if (op
== nir_op_fddx_fine
||
1578 op
== nir_op_fddx_coarse
||
1584 result
= ac_build_ddxy(&ctx
->ac
, mask
, idx
, src0
);
1589 * this takes an I,J coordinate pair,
1590 * and works out the X and Y derivatives.
1591 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1593 static LLVMValueRef
emit_ddxy_interp(
1594 struct ac_nir_context
*ctx
,
1595 LLVMValueRef interp_ij
)
1597 LLVMValueRef result
[4], a
;
1600 for (i
= 0; i
< 2; i
++) {
1601 a
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_ij
,
1602 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
1603 result
[i
] = emit_ddxy(ctx
, nir_op_fddx
, a
);
1604 result
[2+i
] = emit_ddxy(ctx
, nir_op_fddy
, a
);
1606 return ac_build_gather_values(&ctx
->ac
, result
, 4);
1609 static void visit_alu(struct ac_nir_context
*ctx
, const nir_alu_instr
*instr
)
1611 LLVMValueRef src
[4], result
= NULL
;
1612 unsigned num_components
= instr
->dest
.dest
.ssa
.num_components
;
1613 unsigned src_components
;
1614 LLVMTypeRef def_type
= get_def_type(ctx
, &instr
->dest
.dest
.ssa
);
1616 assert(nir_op_infos
[instr
->op
].num_inputs
<= ARRAY_SIZE(src
));
1617 switch (instr
->op
) {
1623 case nir_op_pack_half_2x16
:
1626 case nir_op_unpack_half_2x16
:
1630 src_components
= num_components
;
1633 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1634 src
[i
] = get_alu_src(ctx
, instr
->src
[i
], src_components
);
1636 switch (instr
->op
) {
1642 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1643 result
= LLVMBuildFNeg(ctx
->ac
.builder
, src
[0], "");
1646 result
= LLVMBuildNeg(ctx
->ac
.builder
, src
[0], "");
1649 result
= LLVMBuildNot(ctx
->ac
.builder
, src
[0], "");
1652 result
= LLVMBuildAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1655 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1656 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1657 result
= LLVMBuildFAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1660 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1661 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1662 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1665 result
= LLVMBuildSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1668 result
= LLVMBuildMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1671 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1674 result
= LLVMBuildURem(ctx
->ac
.builder
, src
[0], src
[1], "");
1677 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1678 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1679 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1680 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1681 ac_to_float_type(&ctx
->ac
, def_type
), result
);
1682 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[1] , result
, "");
1683 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], result
, "");
1686 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1687 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1688 result
= LLVMBuildFRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1691 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1694 result
= LLVMBuildSDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1697 result
= LLVMBuildUDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1700 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1701 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1702 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1705 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1706 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1707 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1710 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1711 result
= ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, src
[0]);
1714 result
= LLVMBuildAnd(ctx
->ac
.builder
, src
[0], src
[1], "");
1717 result
= LLVMBuildOr(ctx
->ac
.builder
, src
[0], src
[1], "");
1720 result
= LLVMBuildXor(ctx
->ac
.builder
, src
[0], src
[1], "");
1723 result
= LLVMBuildShl(ctx
->ac
.builder
, src
[0],
1724 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1725 LLVMTypeOf(src
[0]), ""),
1729 result
= LLVMBuildAShr(ctx
->ac
.builder
, src
[0],
1730 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1731 LLVMTypeOf(src
[0]), ""),
1735 result
= LLVMBuildLShr(ctx
->ac
.builder
, src
[0],
1736 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1737 LLVMTypeOf(src
[0]), ""),
1741 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1744 result
= emit_int_cmp(&ctx
->ac
, LLVMIntNE
, src
[0], src
[1]);
1747 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, src
[0], src
[1]);
1750 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSGE
, src
[0], src
[1]);
1753 result
= emit_int_cmp(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1756 result
= emit_int_cmp(&ctx
->ac
, LLVMIntUGE
, src
[0], src
[1]);
1759 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUEQ
, src
[0], src
[1]);
1762 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUNE
, src
[0], src
[1]);
1765 result
= emit_float_cmp(&ctx
->ac
, LLVMRealULT
, src
[0], src
[1]);
1768 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUGE
, src
[0], src
[1]);
1771 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1772 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1775 result
= emit_iabs(&ctx
->ac
, src
[0]);
1778 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, src
[0], src
[1]);
1781 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1784 result
= emit_minmax_int(&ctx
->ac
, LLVMIntUGT
, src
[0], src
[1]);
1787 result
= emit_minmax_int(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1790 result
= emit_isign(&ctx
->ac
, src
[0]);
1793 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1794 result
= emit_fsign(&ctx
->ac
, src
[0]);
1797 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1798 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1801 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.trunc",
1802 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1805 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.ceil",
1806 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1808 case nir_op_fround_even
:
1809 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.rint",
1810 ac_to_float_type(&ctx
->ac
, def_type
),src
[0]);
1813 result
= emit_ffract(&ctx
->ac
, src
[0]);
1816 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sin",
1817 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1820 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.cos",
1821 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1824 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1825 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1828 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.exp2",
1829 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1832 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.log2",
1833 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1836 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1837 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1838 result
= ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, result
);
1841 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.pow",
1842 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1845 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.maxnum",
1846 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1847 if (instr
->dest
.dest
.ssa
.bit_size
== 32)
1848 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1849 ac_to_float_type(&ctx
->ac
, def_type
),
1853 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.minnum",
1854 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1855 if (instr
->dest
.dest
.ssa
.bit_size
== 32)
1856 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1857 ac_to_float_type(&ctx
->ac
, def_type
),
1861 result
= emit_intrin_3f_param(&ctx
->ac
, "llvm.fmuladd",
1862 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1], src
[2]);
1864 case nir_op_ibitfield_extract
:
1865 result
= emit_bitfield_extract(&ctx
->ac
, true, src
);
1867 case nir_op_ubitfield_extract
:
1868 result
= emit_bitfield_extract(&ctx
->ac
, false, src
);
1870 case nir_op_bitfield_insert
:
1871 result
= emit_bitfield_insert(&ctx
->ac
, src
[0], src
[1], src
[2], src
[3]);
1873 case nir_op_bitfield_reverse
:
1874 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.bitreverse.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1876 case nir_op_bit_count
:
1877 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1882 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1883 src
[i
] = ac_to_integer(&ctx
->ac
, src
[i
]);
1884 result
= ac_build_gather_values(&ctx
->ac
, src
, num_components
);
1888 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1889 result
= LLVMBuildFPToSI(ctx
->ac
.builder
, src
[0], def_type
, "");
1893 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1894 result
= LLVMBuildFPToUI(ctx
->ac
.builder
, src
[0], def_type
, "");
1898 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1899 result
= LLVMBuildSIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1903 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1904 result
= LLVMBuildUIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1907 result
= LLVMBuildFPExt(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1910 result
= LLVMBuildFPTrunc(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1914 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1915 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1916 result
= LLVMBuildZExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1918 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1922 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1923 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1924 result
= LLVMBuildSExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1926 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1929 result
= emit_bcsel(&ctx
->ac
, src
[0], src
[1], src
[2]);
1931 case nir_op_find_lsb
:
1932 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1933 result
= emit_find_lsb(&ctx
->ac
, src
[0]);
1935 case nir_op_ufind_msb
:
1936 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1937 result
= emit_ufind_msb(&ctx
->ac
, src
[0]);
1939 case nir_op_ifind_msb
:
1940 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1941 result
= emit_ifind_msb(&ctx
->ac
, src
[0]);
1943 case nir_op_uadd_carry
:
1944 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1945 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1946 result
= emit_uint_carry(&ctx
->ac
, "llvm.uadd.with.overflow.i32", src
[0], src
[1]);
1948 case nir_op_usub_borrow
:
1949 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1950 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1951 result
= emit_uint_carry(&ctx
->ac
, "llvm.usub.with.overflow.i32", src
[0], src
[1]);
1954 result
= emit_b2f(&ctx
->ac
, src
[0]);
1957 result
= emit_f2b(&ctx
->ac
, src
[0]);
1960 result
= emit_b2i(&ctx
->ac
, src
[0]);
1963 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1964 result
= emit_i2b(&ctx
->ac
, src
[0]);
1966 case nir_op_fquantize2f16
:
1967 result
= emit_f2f16(ctx
->nctx
, src
[0]);
1969 case nir_op_umul_high
:
1970 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1971 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1972 result
= emit_umul_high(&ctx
->ac
, src
[0], src
[1]);
1974 case nir_op_imul_high
:
1975 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1976 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1977 result
= emit_imul_high(&ctx
->ac
, src
[0], src
[1]);
1979 case nir_op_pack_half_2x16
:
1980 result
= emit_pack_half_2x16(&ctx
->ac
, src
[0]);
1982 case nir_op_unpack_half_2x16
:
1983 result
= emit_unpack_half_2x16(&ctx
->ac
, src
[0]);
1987 case nir_op_fddx_fine
:
1988 case nir_op_fddy_fine
:
1989 case nir_op_fddx_coarse
:
1990 case nir_op_fddy_coarse
:
1991 result
= emit_ddxy(ctx
, instr
->op
, src
[0]);
1994 case nir_op_unpack_64_2x32_split_x
: {
1995 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
1996 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
1997 LLVMVectorType(ctx
->ac
.i32
, 2),
1999 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2004 case nir_op_unpack_64_2x32_split_y
: {
2005 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
2006 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
2007 LLVMVectorType(ctx
->ac
.i32
, 2),
2009 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2014 case nir_op_pack_64_2x32_split
: {
2015 LLVMValueRef tmp
= LLVMGetUndef(LLVMVectorType(ctx
->ac
.i32
, 2));
2016 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2017 src
[0], ctx
->ac
.i32_0
, "");
2018 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2019 src
[1], ctx
->ac
.i32_1
, "");
2020 result
= LLVMBuildBitCast(ctx
->ac
.builder
, tmp
, ctx
->ac
.i64
, "");
2025 fprintf(stderr
, "Unknown NIR alu instr: ");
2026 nir_print_instr(&instr
->instr
, stderr
);
2027 fprintf(stderr
, "\n");
2032 assert(instr
->dest
.dest
.is_ssa
);
2033 result
= ac_to_integer(&ctx
->ac
, result
);
2034 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.dest
.ssa
,
2039 static void visit_load_const(struct ac_nir_context
*ctx
,
2040 const nir_load_const_instr
*instr
)
2042 LLVMValueRef values
[4], value
= NULL
;
2043 LLVMTypeRef element_type
=
2044 LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
2046 for (unsigned i
= 0; i
< instr
->def
.num_components
; ++i
) {
2047 switch (instr
->def
.bit_size
) {
2049 values
[i
] = LLVMConstInt(element_type
,
2050 instr
->value
.u32
[i
], false);
2053 values
[i
] = LLVMConstInt(element_type
,
2054 instr
->value
.u64
[i
], false);
2058 "unsupported nir load_const bit_size: %d\n",
2059 instr
->def
.bit_size
);
2063 if (instr
->def
.num_components
> 1) {
2064 value
= LLVMConstVector(values
, instr
->def
.num_components
);
2068 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, value
);
2071 static LLVMValueRef
cast_ptr(struct nir_to_llvm_context
*ctx
, LLVMValueRef ptr
,
2074 int addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
2075 return LLVMBuildBitCast(ctx
->builder
, ptr
,
2076 LLVMPointerType(type
, addr_space
), "");
2080 get_buffer_size(struct ac_nir_context
*ctx
, LLVMValueRef descriptor
, bool in_elements
)
2083 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2084 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
2087 if (ctx
->ac
.chip_class
== VI
&& in_elements
) {
2088 /* On VI, the descriptor contains the size in bytes,
2089 * but TXQ must return the size in elements.
2090 * The stride is always non-zero for resources using TXQ.
2092 LLVMValueRef stride
=
2093 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2094 LLVMConstInt(ctx
->ac
.i32
, 1, false), "");
2095 stride
= LLVMBuildLShr(ctx
->ac
.builder
, stride
,
2096 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
2097 stride
= LLVMBuildAnd(ctx
->ac
.builder
, stride
,
2098 LLVMConstInt(ctx
->ac
.i32
, 0x3fff, false), "");
2100 size
= LLVMBuildUDiv(ctx
->ac
.builder
, size
, stride
, "");
2106 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2109 static void build_int_type_name(
2111 char *buf
, unsigned bufsize
)
2113 assert(bufsize
>= 6);
2115 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
2116 snprintf(buf
, bufsize
, "v%ui32",
2117 LLVMGetVectorSize(type
));
2122 static LLVMValueRef
radv_lower_gather4_integer(struct ac_llvm_context
*ctx
,
2123 struct ac_image_args
*args
,
2124 const nir_tex_instr
*instr
)
2126 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2127 LLVMValueRef coord
= args
->addr
;
2128 LLVMValueRef half_texel
[2];
2129 LLVMValueRef compare_cube_wa
= NULL
;
2130 LLVMValueRef result
;
2132 unsigned coord_vgpr_index
= (unsigned)args
->offset
+ (unsigned)args
->compare
;
2136 struct ac_image_args txq_args
= { 0 };
2138 txq_args
.da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
2139 txq_args
.opcode
= ac_image_get_resinfo
;
2140 txq_args
.dmask
= 0xf;
2141 txq_args
.addr
= ctx
->i32_0
;
2142 txq_args
.resource
= args
->resource
;
2143 LLVMValueRef size
= ac_build_image_opcode(ctx
, &txq_args
);
2145 for (c
= 0; c
< 2; c
++) {
2146 half_texel
[c
] = LLVMBuildExtractElement(ctx
->builder
, size
,
2147 LLVMConstInt(ctx
->i32
, c
, false), "");
2148 half_texel
[c
] = LLVMBuildUIToFP(ctx
->builder
, half_texel
[c
], ctx
->f32
, "");
2149 half_texel
[c
] = ac_build_fdiv(ctx
, ctx
->f32_1
, half_texel
[c
]);
2150 half_texel
[c
] = LLVMBuildFMul(ctx
->builder
, half_texel
[c
],
2151 LLVMConstReal(ctx
->f32
, -0.5), "");
2155 LLVMValueRef orig_coords
= args
->addr
;
2157 for (c
= 0; c
< 2; c
++) {
2159 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, coord_vgpr_index
+ c
, 0);
2160 tmp
= LLVMBuildExtractElement(ctx
->builder
, coord
, index
, "");
2161 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2162 tmp
= LLVMBuildFAdd(ctx
->builder
, tmp
, half_texel
[c
], "");
2163 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2164 coord
= LLVMBuildInsertElement(ctx
->builder
, coord
, tmp
, index
, "");
2169 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2170 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2171 * workaround by sampling using a scaled type and converting.
2172 * This is taken from amdgpu-pro shaders.
2174 /* NOTE this produces some ugly code compared to amdgpu-pro,
2175 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2176 * and then reads them back. -pro generates two selects,
2177 * one s_cmp for the descriptor rewriting
2178 * one v_cmp for the coordinate and result changes.
2180 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2181 LLVMValueRef tmp
, tmp2
;
2183 /* workaround 8/8/8/8 uint/sint cube gather bug */
2184 /* first detect it then change to a scaled read and f2i */
2185 tmp
= LLVMBuildExtractElement(ctx
->builder
, args
->resource
, ctx
->i32_1
, "");
2188 /* extract the DATA_FORMAT */
2189 tmp
= ac_build_bfe(ctx
, tmp
, LLVMConstInt(ctx
->i32
, 20, false),
2190 LLVMConstInt(ctx
->i32
, 6, false), false);
2192 /* is the DATA_FORMAT == 8_8_8_8 */
2193 compare_cube_wa
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, tmp
, LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false), "");
2195 if (stype
== GLSL_TYPE_UINT
)
2196 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2197 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0x8000000, false),
2198 LLVMConstInt(ctx
->i32
, 0x10000000, false), "");
2200 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2201 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0xc000000, false),
2202 LLVMConstInt(ctx
->i32
, 0x14000000, false), "");
2204 /* replace the NUM FORMAT in the descriptor */
2205 tmp2
= LLVMBuildAnd(ctx
->builder
, tmp2
, LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false), "");
2206 tmp2
= LLVMBuildOr(ctx
->builder
, tmp2
, tmp
, "");
2208 args
->resource
= LLVMBuildInsertElement(ctx
->builder
, args
->resource
, tmp2
, ctx
->i32_1
, "");
2210 /* don't modify the coordinates for this case */
2211 coord
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, orig_coords
, coord
, "");
2214 result
= ac_build_image_opcode(ctx
, args
);
2216 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2217 LLVMValueRef tmp
, tmp2
;
2219 /* if the cube workaround is in place, f2i the result. */
2220 for (c
= 0; c
< 4; c
++) {
2221 tmp
= LLVMBuildExtractElement(ctx
->builder
, result
, LLVMConstInt(ctx
->i32
, c
, false), "");
2222 if (stype
== GLSL_TYPE_UINT
)
2223 tmp2
= LLVMBuildFPToUI(ctx
->builder
, tmp
, ctx
->i32
, "");
2225 tmp2
= LLVMBuildFPToSI(ctx
->builder
, tmp
, ctx
->i32
, "");
2226 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2227 tmp2
= LLVMBuildBitCast(ctx
->builder
, tmp2
, ctx
->i32
, "");
2228 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, tmp2
, tmp
, "");
2229 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2230 result
= LLVMBuildInsertElement(ctx
->builder
, result
, tmp
, LLVMConstInt(ctx
->i32
, c
, false), "");
2236 static LLVMValueRef
build_tex_intrinsic(struct ac_nir_context
*ctx
,
2237 const nir_tex_instr
*instr
,
2239 struct ac_image_args
*args
)
2241 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
2242 return ac_build_buffer_load_format(&ctx
->ac
,
2245 LLVMConstInt(ctx
->ac
.i32
, 0, false),
2249 args
->opcode
= ac_image_sample
;
2250 args
->compare
= instr
->is_shadow
;
2252 switch (instr
->op
) {
2254 case nir_texop_txf_ms
:
2255 case nir_texop_samples_identical
:
2256 args
->opcode
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
? ac_image_load
: ac_image_load_mip
;
2257 args
->compare
= false;
2258 args
->offset
= false;
2265 args
->level_zero
= true;
2270 case nir_texop_query_levels
:
2271 args
->opcode
= ac_image_get_resinfo
;
2274 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
2275 args
->level_zero
= true;
2281 args
->opcode
= ac_image_gather4
;
2282 args
->level_zero
= true;
2285 args
->opcode
= ac_image_get_lod
;
2286 args
->compare
= false;
2287 args
->offset
= false;
2293 if (instr
->op
== nir_texop_tg4
&& ctx
->ac
.chip_class
<= VI
) {
2294 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2295 if (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
) {
2296 return radv_lower_gather4_integer(&ctx
->ac
, args
, instr
);
2299 return ac_build_image_opcode(&ctx
->ac
, args
);
2302 static LLVMValueRef
visit_vulkan_resource_index(struct nir_to_llvm_context
*ctx
,
2303 nir_intrinsic_instr
*instr
)
2305 LLVMValueRef index
= get_src(ctx
->nir
, instr
->src
[0]);
2306 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
2307 unsigned binding
= nir_intrinsic_binding(instr
);
2308 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
2309 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
2310 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
2311 unsigned base_offset
= layout
->binding
[binding
].offset
;
2312 LLVMValueRef offset
, stride
;
2314 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
2315 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
2316 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
2317 layout
->binding
[binding
].dynamic_offset_offset
;
2318 desc_ptr
= ctx
->push_constants
;
2319 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
2320 stride
= LLVMConstInt(ctx
->i32
, 16, false);
2322 stride
= LLVMConstInt(ctx
->i32
, layout
->binding
[binding
].size
, false);
2324 offset
= LLVMConstInt(ctx
->i32
, base_offset
, false);
2325 index
= LLVMBuildMul(ctx
->builder
, index
, stride
, "");
2326 offset
= LLVMBuildAdd(ctx
->builder
, offset
, index
, "");
2328 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
2329 desc_ptr
= cast_ptr(ctx
, desc_ptr
, ctx
->v4i32
);
2330 LLVMSetMetadata(desc_ptr
, ctx
->uniform_md_kind
, ctx
->empty_md
);
2332 return LLVMBuildLoad(ctx
->builder
, desc_ptr
, "");
2335 static LLVMValueRef
visit_load_push_constant(struct nir_to_llvm_context
*ctx
,
2336 nir_intrinsic_instr
*instr
)
2338 LLVMValueRef ptr
, addr
;
2340 addr
= LLVMConstInt(ctx
->i32
, nir_intrinsic_base(instr
), 0);
2341 addr
= LLVMBuildAdd(ctx
->builder
, addr
, get_src(ctx
->nir
, instr
->src
[0]), "");
2343 ptr
= ac_build_gep0(&ctx
->ac
, ctx
->push_constants
, addr
);
2344 ptr
= cast_ptr(ctx
, ptr
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
));
2346 return LLVMBuildLoad(ctx
->builder
, ptr
, "");
2349 static LLVMValueRef
visit_get_buffer_size(struct ac_nir_context
*ctx
,
2350 const nir_intrinsic_instr
*instr
)
2352 LLVMValueRef desc
= get_src(ctx
, instr
->src
[0]);
2354 return get_buffer_size(ctx
, desc
, false);
2356 static void visit_store_ssbo(struct ac_nir_context
*ctx
,
2357 nir_intrinsic_instr
*instr
)
2359 const char *store_name
;
2360 LLVMValueRef src_data
= get_src(ctx
, instr
->src
[0]);
2361 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2362 int elem_size_mult
= get_elem_bits(&ctx
->ac
, LLVMTypeOf(src_data
)) / 32;
2363 int components_32bit
= elem_size_mult
* instr
->num_components
;
2364 unsigned writemask
= nir_intrinsic_write_mask(instr
);
2365 LLVMValueRef base_data
, base_offset
;
2366 LLVMValueRef params
[6];
2367 LLVMValueRef i1false
= LLVMConstInt(ctx
->ac
.i1
, 0, false);
2369 params
[1] = ctx
->abi
->load_ssbo(ctx
->abi
,
2370 get_src(ctx
, instr
->src
[1]), true);
2371 params
[2] = LLVMConstInt(ctx
->ac
.i32
, 0, false); /* vindex */
2372 params
[4] = i1false
; /* glc */
2373 params
[5] = i1false
; /* slc */
2375 if (components_32bit
> 1)
2376 data_type
= LLVMVectorType(ctx
->ac
.f32
, components_32bit
);
2378 base_data
= ac_to_float(&ctx
->ac
, src_data
);
2379 base_data
= trim_vector(&ctx
->ac
, base_data
, instr
->num_components
);
2380 base_data
= LLVMBuildBitCast(ctx
->ac
.builder
, base_data
,
2382 base_offset
= get_src(ctx
, instr
->src
[2]); /* voffset */
2386 LLVMValueRef offset
;
2388 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
2390 /* Due to an LLVM limitation, split 3-element writes
2391 * into a 2-element and a 1-element write. */
2393 writemask
|= 1 << (start
+ 2);
2397 start
*= elem_size_mult
;
2398 count
*= elem_size_mult
;
2401 writemask
|= ((1u << (count
- 4)) - 1u) << (start
+ 4);
2406 store_name
= "llvm.amdgcn.buffer.store.v4f32";
2408 } else if (count
== 2) {
2409 LLVMTypeRef v2f32
= LLVMVectorType(ctx
->ac
.f32
, 2);
2411 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
2412 base_data
, LLVMConstInt(ctx
->ac
.i32
, start
, false), "");
2413 data
= LLVMBuildInsertElement(ctx
->ac
.builder
, LLVMGetUndef(v2f32
), tmp
,
2416 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
2417 base_data
, LLVMConstInt(ctx
->ac
.i32
, start
+ 1, false), "");
2418 data
= LLVMBuildInsertElement(ctx
->ac
.builder
, data
, tmp
,
2420 store_name
= "llvm.amdgcn.buffer.store.v2f32";
2424 if (get_llvm_num_components(base_data
) > 1)
2425 data
= LLVMBuildExtractElement(ctx
->ac
.builder
, base_data
,
2426 LLVMConstInt(ctx
->ac
.i32
, start
, false), "");
2429 store_name
= "llvm.amdgcn.buffer.store.f32";
2432 offset
= base_offset
;
2434 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, LLVMConstInt(ctx
->ac
.i32
, start
* 4, false), "");
2438 ac_build_intrinsic(&ctx
->ac
, store_name
,
2439 ctx
->ac
.voidt
, params
, 6, 0);
2443 static LLVMValueRef
visit_atomic_ssbo(struct ac_nir_context
*ctx
,
2444 const nir_intrinsic_instr
*instr
)
2447 LLVMValueRef params
[6];
2450 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
) {
2451 params
[arg_count
++] = llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[3]), 0);
2453 params
[arg_count
++] = llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[2]), 0);
2454 params
[arg_count
++] = ctx
->abi
->load_ssbo(ctx
->abi
,
2455 get_src(ctx
, instr
->src
[0]),
2457 params
[arg_count
++] = LLVMConstInt(ctx
->ac
.i32
, 0, false); /* vindex */
2458 params
[arg_count
++] = get_src(ctx
, instr
->src
[1]); /* voffset */
2459 params
[arg_count
++] = LLVMConstInt(ctx
->ac
.i1
, 0, false); /* slc */
2461 switch (instr
->intrinsic
) {
2462 case nir_intrinsic_ssbo_atomic_add
:
2463 name
= "llvm.amdgcn.buffer.atomic.add";
2465 case nir_intrinsic_ssbo_atomic_imin
:
2466 name
= "llvm.amdgcn.buffer.atomic.smin";
2468 case nir_intrinsic_ssbo_atomic_umin
:
2469 name
= "llvm.amdgcn.buffer.atomic.umin";
2471 case nir_intrinsic_ssbo_atomic_imax
:
2472 name
= "llvm.amdgcn.buffer.atomic.smax";
2474 case nir_intrinsic_ssbo_atomic_umax
:
2475 name
= "llvm.amdgcn.buffer.atomic.umax";
2477 case nir_intrinsic_ssbo_atomic_and
:
2478 name
= "llvm.amdgcn.buffer.atomic.and";
2480 case nir_intrinsic_ssbo_atomic_or
:
2481 name
= "llvm.amdgcn.buffer.atomic.or";
2483 case nir_intrinsic_ssbo_atomic_xor
:
2484 name
= "llvm.amdgcn.buffer.atomic.xor";
2486 case nir_intrinsic_ssbo_atomic_exchange
:
2487 name
= "llvm.amdgcn.buffer.atomic.swap";
2489 case nir_intrinsic_ssbo_atomic_comp_swap
:
2490 name
= "llvm.amdgcn.buffer.atomic.cmpswap";
2496 return ac_build_intrinsic(&ctx
->ac
, name
, ctx
->ac
.i32
, params
, arg_count
, 0);
2499 static LLVMValueRef
visit_load_buffer(struct ac_nir_context
*ctx
,
2500 const nir_intrinsic_instr
*instr
)
2502 LLVMValueRef results
[2];
2503 int load_components
;
2504 int num_components
= instr
->num_components
;
2505 if (instr
->dest
.ssa
.bit_size
== 64)
2506 num_components
*= 2;
2508 for (int i
= 0; i
< num_components
; i
+= load_components
) {
2509 load_components
= MIN2(num_components
- i
, 4);
2510 const char *load_name
;
2511 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2512 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, i
* 4, false);
2513 offset
= LLVMBuildAdd(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[1]), offset
, "");
2515 if (load_components
== 3)
2516 data_type
= LLVMVectorType(ctx
->ac
.f32
, 4);
2517 else if (load_components
> 1)
2518 data_type
= LLVMVectorType(ctx
->ac
.f32
, load_components
);
2520 if (load_components
>= 3)
2521 load_name
= "llvm.amdgcn.buffer.load.v4f32";
2522 else if (load_components
== 2)
2523 load_name
= "llvm.amdgcn.buffer.load.v2f32";
2524 else if (load_components
== 1)
2525 load_name
= "llvm.amdgcn.buffer.load.f32";
2527 unreachable("unhandled number of components");
2529 LLVMValueRef i1false
= LLVMConstInt(ctx
->ac
.i1
, 0, false);
2530 LLVMValueRef params
[] = {
2531 ctx
->abi
->load_ssbo(ctx
->abi
,
2532 get_src(ctx
, instr
->src
[0]),
2534 LLVMConstInt(ctx
->ac
.i32
, 0, false),
2540 results
[i
] = ac_build_intrinsic(&ctx
->ac
, load_name
, data_type
, params
, 5, 0);
2544 LLVMValueRef ret
= results
[0];
2545 if (num_components
> 4 || num_components
== 3) {
2546 LLVMValueRef masks
[] = {
2547 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
2548 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
2549 LLVMConstInt(ctx
->ac
.i32
, 4, false), LLVMConstInt(ctx
->ac
.i32
, 5, false),
2550 LLVMConstInt(ctx
->ac
.i32
, 6, false), LLVMConstInt(ctx
->ac
.i32
, 7, false)
2553 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
2554 ret
= LLVMBuildShuffleVector(ctx
->ac
.builder
, results
[0],
2555 results
[num_components
> 4 ? 1 : 0], swizzle
, "");
2558 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2559 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2562 static LLVMValueRef
visit_load_ubo_buffer(struct ac_nir_context
*ctx
,
2563 const nir_intrinsic_instr
*instr
)
2565 LLVMValueRef results
[8], ret
;
2566 LLVMValueRef rsrc
= get_src(ctx
, instr
->src
[0]);
2567 LLVMValueRef offset
= get_src(ctx
, instr
->src
[1]);
2568 int num_components
= instr
->num_components
;
2570 if (ctx
->abi
->load_ubo
)
2571 rsrc
= ctx
->abi
->load_ubo(ctx
->abi
, rsrc
);
2573 if (instr
->dest
.ssa
.bit_size
== 64)
2574 num_components
*= 2;
2576 for (unsigned i
= 0; i
< num_components
; ++i
) {
2577 LLVMValueRef params
[] = {
2579 LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, 4 * i
, 0),
2582 results
[i
] = ac_build_intrinsic(&ctx
->ac
, "llvm.SI.load.const.v4i32", ctx
->ac
.f32
,
2584 AC_FUNC_ATTR_READNONE
|
2585 AC_FUNC_ATTR_LEGACY
);
2589 ret
= ac_build_gather_values(&ctx
->ac
, results
, instr
->num_components
);
2590 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2591 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2595 get_deref_offset(struct ac_nir_context
*ctx
, nir_deref_var
*deref
,
2596 bool vs_in
, unsigned *vertex_index_out
,
2597 LLVMValueRef
*vertex_index_ref
,
2598 unsigned *const_out
, LLVMValueRef
*indir_out
)
2600 unsigned const_offset
= 0;
2601 nir_deref
*tail
= &deref
->deref
;
2602 LLVMValueRef offset
= NULL
;
2604 if (vertex_index_out
!= NULL
|| vertex_index_ref
!= NULL
) {
2606 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2607 if (vertex_index_out
)
2608 *vertex_index_out
= deref_array
->base_offset
;
2610 if (vertex_index_ref
) {
2611 LLVMValueRef vtx
= LLVMConstInt(ctx
->ac
.i32
, deref_array
->base_offset
, false);
2612 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
2613 vtx
= LLVMBuildAdd(ctx
->ac
.builder
, vtx
, get_src(ctx
, deref_array
->indirect
), "");
2615 *vertex_index_ref
= vtx
;
2619 if (deref
->var
->data
.compact
) {
2620 assert(tail
->child
->deref_type
== nir_deref_type_array
);
2621 assert(glsl_type_is_scalar(glsl_without_array(deref
->var
->type
)));
2622 nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
2623 /* We always lower indirect dereferences for "compact" array vars. */
2624 assert(deref_array
->deref_array_type
== nir_deref_array_type_direct
);
2626 const_offset
= deref_array
->base_offset
;
2630 while (tail
->child
!= NULL
) {
2631 const struct glsl_type
*parent_type
= tail
->type
;
2634 if (tail
->deref_type
== nir_deref_type_array
) {
2635 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2636 LLVMValueRef index
, stride
, local_offset
;
2637 unsigned size
= glsl_count_attribute_slots(tail
->type
, vs_in
);
2639 const_offset
+= size
* deref_array
->base_offset
;
2640 if (deref_array
->deref_array_type
== nir_deref_array_type_direct
)
2643 assert(deref_array
->deref_array_type
== nir_deref_array_type_indirect
);
2644 index
= get_src(ctx
, deref_array
->indirect
);
2645 stride
= LLVMConstInt(ctx
->ac
.i32
, size
, 0);
2646 local_offset
= LLVMBuildMul(ctx
->ac
.builder
, stride
, index
, "");
2649 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, local_offset
, "");
2651 offset
= local_offset
;
2652 } else if (tail
->deref_type
== nir_deref_type_struct
) {
2653 nir_deref_struct
*deref_struct
= nir_deref_as_struct(tail
);
2655 for (unsigned i
= 0; i
< deref_struct
->index
; i
++) {
2656 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
2657 const_offset
+= glsl_count_attribute_slots(ft
, vs_in
);
2660 unreachable("unsupported deref type");
2664 if (const_offset
&& offset
)
2665 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
2666 LLVMConstInt(ctx
->ac
.i32
, const_offset
, 0),
2669 *const_out
= const_offset
;
2670 *indir_out
= offset
;
2674 lds_load(struct nir_to_llvm_context
*ctx
,
2675 LLVMValueRef dw_addr
)
2678 value
= ac_build_load(&ctx
->ac
, ctx
->lds
, dw_addr
);
2683 lds_store(struct nir_to_llvm_context
*ctx
,
2684 LLVMValueRef dw_addr
, LLVMValueRef value
)
2686 value
= LLVMBuildBitCast(ctx
->builder
, value
, ctx
->i32
, "");
2687 ac_build_indexed_store(&ctx
->ac
, ctx
->lds
,
2691 /* The offchip buffer layout for TCS->TES is
2693 * - attribute 0 of patch 0 vertex 0
2694 * - attribute 0 of patch 0 vertex 1
2695 * - attribute 0 of patch 0 vertex 2
2697 * - attribute 0 of patch 1 vertex 0
2698 * - attribute 0 of patch 1 vertex 1
2700 * - attribute 1 of patch 0 vertex 0
2701 * - attribute 1 of patch 0 vertex 1
2703 * - per patch attribute 0 of patch 0
2704 * - per patch attribute 0 of patch 1
2707 * Note that every attribute has 4 components.
2709 static LLVMValueRef
get_tcs_tes_buffer_address(struct nir_to_llvm_context
*ctx
,
2710 LLVMValueRef vertex_index
,
2711 LLVMValueRef param_index
)
2713 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
2714 LLVMValueRef param_stride
, constant16
;
2715 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
2717 vertices_per_patch
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 9, 6);
2718 num_patches
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 0, 9);
2719 total_vertices
= LLVMBuildMul(ctx
->builder
, vertices_per_patch
,
2722 constant16
= LLVMConstInt(ctx
->i32
, 16, false);
2724 base_addr
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
2725 vertices_per_patch
, "");
2727 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2730 param_stride
= total_vertices
;
2732 base_addr
= rel_patch_id
;
2733 param_stride
= num_patches
;
2736 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2737 LLVMBuildMul(ctx
->builder
, param_index
,
2738 param_stride
, ""), "");
2740 base_addr
= LLVMBuildMul(ctx
->builder
, base_addr
, constant16
, "");
2742 if (!vertex_index
) {
2743 LLVMValueRef patch_data_offset
=
2744 unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 16, 16);
2746 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2747 patch_data_offset
, "");
2752 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct nir_to_llvm_context
*ctx
,
2754 unsigned const_index
,
2756 LLVMValueRef vertex_index
,
2757 LLVMValueRef indir_index
)
2759 LLVMValueRef param_index
;
2762 param_index
= LLVMBuildAdd(ctx
->builder
, LLVMConstInt(ctx
->i32
, param
, false),
2765 if (const_index
&& !is_compact
)
2766 param
+= const_index
;
2767 param_index
= LLVMConstInt(ctx
->i32
, param
, false);
2769 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
2773 mark_tess_output(struct nir_to_llvm_context
*ctx
,
2774 bool is_patch
, uint32_t param
)
2778 ctx
->tess_patch_outputs_written
|= (1ull << param
);
2780 ctx
->tess_outputs_written
|= (1ull << param
);
2784 get_dw_address(struct nir_to_llvm_context
*ctx
,
2785 LLVMValueRef dw_addr
,
2787 unsigned const_index
,
2788 bool compact_const_index
,
2789 LLVMValueRef vertex_index
,
2790 LLVMValueRef stride
,
2791 LLVMValueRef indir_index
)
2796 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2797 LLVMBuildMul(ctx
->builder
,
2803 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2804 LLVMBuildMul(ctx
->builder
, indir_index
,
2805 LLVMConstInt(ctx
->i32
, 4, false), ""), "");
2806 else if (const_index
&& !compact_const_index
)
2807 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2808 LLVMConstInt(ctx
->i32
, const_index
, false), "");
2810 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2811 LLVMConstInt(ctx
->i32
, param
* 4, false), "");
2813 if (const_index
&& compact_const_index
)
2814 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2815 LLVMConstInt(ctx
->i32
, const_index
, false), "");
2820 load_tcs_input(struct nir_to_llvm_context
*ctx
,
2821 nir_intrinsic_instr
*instr
)
2823 LLVMValueRef dw_addr
, stride
;
2824 unsigned const_index
;
2825 LLVMValueRef vertex_index
;
2826 LLVMValueRef indir_index
;
2828 LLVMValueRef value
[4], result
;
2829 const bool per_vertex
= nir_is_per_vertex_io(instr
->variables
[0]->var
, ctx
->stage
);
2830 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
2831 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2832 get_deref_offset(ctx
->nir
, instr
->variables
[0],
2833 false, NULL
, per_vertex
? &vertex_index
: NULL
,
2834 &const_index
, &indir_index
);
2836 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 13, 8);
2837 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
2838 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2841 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2842 value
[i
] = lds_load(ctx
, dw_addr
);
2843 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2846 result
= ac_build_gather_values(&ctx
->ac
, value
, instr
->num_components
);
2847 result
= LLVMBuildBitCast(ctx
->builder
, result
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
2852 load_tcs_output(struct nir_to_llvm_context
*ctx
,
2853 nir_intrinsic_instr
*instr
)
2855 LLVMValueRef dw_addr
;
2856 LLVMValueRef stride
= NULL
;
2857 LLVMValueRef value
[4], result
;
2858 LLVMValueRef vertex_index
= NULL
;
2859 LLVMValueRef indir_index
= NULL
;
2860 unsigned const_index
= 0;
2862 const bool per_vertex
= nir_is_per_vertex_io(instr
->variables
[0]->var
, ctx
->stage
);
2863 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
2864 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2865 get_deref_offset(ctx
->nir
, instr
->variables
[0],
2866 false, NULL
, per_vertex
? &vertex_index
: NULL
,
2867 &const_index
, &indir_index
);
2869 if (!instr
->variables
[0]->var
->data
.patch
) {
2870 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
2871 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2873 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2876 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2879 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2880 value
[i
] = lds_load(ctx
, dw_addr
);
2881 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2884 result
= ac_build_gather_values(&ctx
->ac
, value
, instr
->num_components
);
2885 result
= LLVMBuildBitCast(ctx
->builder
, result
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
2890 store_tcs_output(struct nir_to_llvm_context
*ctx
,
2891 nir_intrinsic_instr
*instr
,
2895 LLVMValueRef dw_addr
;
2896 LLVMValueRef stride
= NULL
;
2897 LLVMValueRef buf_addr
= NULL
;
2898 LLVMValueRef vertex_index
= NULL
;
2899 LLVMValueRef indir_index
= NULL
;
2900 unsigned const_index
= 0;
2902 const bool per_vertex
= nir_is_per_vertex_io(instr
->variables
[0]->var
, ctx
->stage
);
2903 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
2905 get_deref_offset(ctx
->nir
, instr
->variables
[0],
2906 false, NULL
, per_vertex
? &vertex_index
: NULL
,
2907 &const_index
, &indir_index
);
2909 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2910 if (instr
->variables
[0]->var
->data
.location
== VARYING_SLOT_CLIP_DIST0
&&
2911 is_compact
&& const_index
> 3) {
2916 if (!instr
->variables
[0]->var
->data
.patch
) {
2917 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
2918 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2920 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2923 mark_tess_output(ctx
, instr
->variables
[0]->var
->data
.patch
, param
);
2925 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2927 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
2928 vertex_index
, indir_index
);
2930 bool is_tess_factor
= false;
2931 if (instr
->variables
[0]->var
->data
.location
== VARYING_SLOT_TESS_LEVEL_INNER
||
2932 instr
->variables
[0]->var
->data
.location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
2933 is_tess_factor
= true;
2935 unsigned base
= is_compact
? const_index
: 0;
2936 for (unsigned chan
= 0; chan
< 8; chan
++) {
2937 if (!(writemask
& (1 << chan
)))
2939 LLVMValueRef value
= llvm_extract_elem(&ctx
->ac
, src
, chan
);
2941 lds_store(ctx
, dw_addr
, value
);
2943 if (!is_tess_factor
&& writemask
!= 0xF)
2944 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
2945 buf_addr
, ctx
->oc_lds
,
2946 4 * (base
+ chan
), 1, 0, true, false);
2948 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2952 if (writemask
== 0xF) {
2953 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
2954 buf_addr
, ctx
->oc_lds
,
2955 (base
* 4), 1, 0, true, false);
2960 load_tes_input(struct nir_to_llvm_context
*ctx
,
2961 const nir_intrinsic_instr
*instr
)
2963 LLVMValueRef buf_addr
;
2964 LLVMValueRef result
;
2965 LLVMValueRef vertex_index
= NULL
;
2966 LLVMValueRef indir_index
= NULL
;
2967 unsigned const_index
= 0;
2969 const bool per_vertex
= nir_is_per_vertex_io(instr
->variables
[0]->var
, ctx
->stage
);
2970 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
2972 get_deref_offset(ctx
->nir
, instr
->variables
[0],
2973 false, NULL
, per_vertex
? &vertex_index
: NULL
,
2974 &const_index
, &indir_index
);
2975 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2976 if (instr
->variables
[0]->var
->data
.location
== VARYING_SLOT_CLIP_DIST0
&&
2977 is_compact
&& const_index
> 3) {
2981 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
2982 is_compact
, vertex_index
, indir_index
);
2984 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, instr
->num_components
, NULL
,
2985 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
2986 result
= trim_vector(&ctx
->ac
, result
, instr
->num_components
);
2987 result
= LLVMBuildBitCast(ctx
->builder
, result
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
2992 load_gs_input(struct nir_to_llvm_context
*ctx
,
2993 nir_intrinsic_instr
*instr
)
2995 LLVMValueRef indir_index
, vtx_offset
;
2996 unsigned const_index
;
2997 LLVMValueRef args
[9];
2998 unsigned param
, vtx_offset_param
;
2999 LLVMValueRef value
[4], result
;
3000 unsigned vertex_index
;
3001 get_deref_offset(ctx
->nir
, instr
->variables
[0],
3002 false, &vertex_index
, NULL
,
3003 &const_index
, &indir_index
);
3004 vtx_offset_param
= vertex_index
;
3005 assert(vtx_offset_param
< 6);
3006 vtx_offset
= LLVMBuildMul(ctx
->builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
3007 LLVMConstInt(ctx
->i32
, 4, false), "");
3009 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
3010 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3011 if (ctx
->ac
.chip_class
>= GFX9
) {
3012 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
3013 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
3014 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
3015 value
[i
] = lds_load(ctx
, dw_addr
);
3017 args
[0] = ctx
->esgs_ring
;
3018 args
[1] = vtx_offset
;
3019 args
[2] = LLVMConstInt(ctx
->i32
, (param
* 4 + i
+ const_index
) * 256, false);
3020 args
[3] = ctx
->i32zero
;
3021 args
[4] = ctx
->i32one
; /* OFFEN */
3022 args
[5] = ctx
->i32zero
; /* IDXEN */
3023 args
[6] = ctx
->i32one
; /* GLC */
3024 args
[7] = ctx
->i32zero
; /* SLC */
3025 args
[8] = ctx
->i32zero
; /* TFE */
3027 value
[i
] = ac_build_intrinsic(&ctx
->ac
, "llvm.SI.buffer.load.dword.i32.i32",
3029 AC_FUNC_ATTR_READONLY
|
3030 AC_FUNC_ATTR_LEGACY
);
3033 result
= ac_build_gather_values(&ctx
->ac
, value
, instr
->num_components
);
3039 build_gep_for_deref(struct ac_nir_context
*ctx
,
3040 nir_deref_var
*deref
)
3042 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->vars
, deref
->var
);
3043 assert(entry
->data
);
3044 LLVMValueRef val
= entry
->data
;
3045 nir_deref
*tail
= deref
->deref
.child
;
3046 while (tail
!= NULL
) {
3047 LLVMValueRef offset
;
3048 switch (tail
->deref_type
) {
3049 case nir_deref_type_array
: {
3050 nir_deref_array
*array
= nir_deref_as_array(tail
);
3051 offset
= LLVMConstInt(ctx
->ac
.i32
, array
->base_offset
, 0);
3052 if (array
->deref_array_type
==
3053 nir_deref_array_type_indirect
) {
3054 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
3061 case nir_deref_type_struct
: {
3062 nir_deref_struct
*deref_struct
=
3063 nir_deref_as_struct(tail
);
3064 offset
= LLVMConstInt(ctx
->ac
.i32
,
3065 deref_struct
->index
, 0);
3069 unreachable("bad deref type");
3071 val
= ac_build_gep0(&ctx
->ac
, val
, offset
);
3077 static LLVMValueRef
visit_load_var(struct ac_nir_context
*ctx
,
3078 nir_intrinsic_instr
*instr
)
3080 LLVMValueRef values
[8];
3081 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3082 int ve
= instr
->dest
.ssa
.num_components
;
3083 LLVMValueRef indir_index
;
3085 unsigned const_index
;
3086 bool vs_in
= ctx
->stage
== MESA_SHADER_VERTEX
&&
3087 instr
->variables
[0]->var
->data
.mode
== nir_var_shader_in
;
3088 get_deref_offset(ctx
, instr
->variables
[0], vs_in
, NULL
, NULL
,
3089 &const_index
, &indir_index
);
3091 if (instr
->dest
.ssa
.bit_size
== 64)
3094 switch (instr
->variables
[0]->var
->data
.mode
) {
3095 case nir_var_shader_in
:
3096 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
3097 return load_tcs_input(ctx
->nctx
, instr
);
3098 if (ctx
->stage
== MESA_SHADER_TESS_EVAL
)
3099 return load_tes_input(ctx
->nctx
, instr
);
3100 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3101 return load_gs_input(ctx
->nctx
, instr
);
3103 for (unsigned chan
= 0; chan
< ve
; chan
++) {
3105 unsigned count
= glsl_count_attribute_slots(
3106 instr
->variables
[0]->var
->type
,
3107 ctx
->stage
== MESA_SHADER_VERTEX
);
3109 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3110 &ctx
->ac
, ctx
->abi
->inputs
+ idx
+ chan
, count
,
3113 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3117 values
[chan
] = ctx
->abi
->inputs
[idx
+ chan
+ const_index
* 4];
3121 for (unsigned chan
= 0; chan
< ve
; chan
++) {
3123 unsigned count
= glsl_count_attribute_slots(
3124 instr
->variables
[0]->var
->type
, false);
3126 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3127 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3130 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3134 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, ctx
->locals
[idx
+ chan
+ const_index
* 4], "");
3138 case nir_var_shared
: {
3139 LLVMValueRef address
= build_gep_for_deref(ctx
,
3140 instr
->variables
[0]);
3141 LLVMValueRef val
= LLVMBuildLoad(ctx
->ac
.builder
, address
, "");
3142 return LLVMBuildBitCast(ctx
->ac
.builder
, val
,
3143 get_def_type(ctx
, &instr
->dest
.ssa
),
3146 case nir_var_shader_out
:
3147 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
3148 return load_tcs_output(ctx
->nctx
, instr
);
3149 for (unsigned chan
= 0; chan
< ve
; chan
++) {
3151 unsigned count
= glsl_count_attribute_slots(
3152 instr
->variables
[0]->var
->type
, false);
3154 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3155 &ctx
->ac
, ctx
->outputs
+ idx
+ chan
, count
,
3158 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3162 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
,
3163 ctx
->outputs
[idx
+ chan
+ const_index
* 4],
3169 unreachable("unhandle variable mode");
3171 ret
= ac_build_gather_values(&ctx
->ac
, values
, ve
);
3172 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3176 visit_store_var(struct ac_nir_context
*ctx
,
3177 nir_intrinsic_instr
*instr
)
3179 LLVMValueRef temp_ptr
, value
;
3180 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3181 LLVMValueRef src
= ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
3182 int writemask
= instr
->const_index
[0];
3183 LLVMValueRef indir_index
;
3184 unsigned const_index
;
3185 get_deref_offset(ctx
, instr
->variables
[0], false,
3186 NULL
, NULL
, &const_index
, &indir_index
);
3188 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
)) == 64) {
3189 int old_writemask
= writemask
;
3191 src
= LLVMBuildBitCast(ctx
->ac
.builder
, src
,
3192 LLVMVectorType(ctx
->ac
.f32
, get_llvm_num_components(src
) * 2),
3196 for (unsigned chan
= 0; chan
< 4; chan
++) {
3197 if (old_writemask
& (1 << chan
))
3198 writemask
|= 3u << (2 * chan
);
3202 switch (instr
->variables
[0]->var
->data
.mode
) {
3203 case nir_var_shader_out
:
3205 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3206 store_tcs_output(ctx
->nctx
, instr
, src
, writemask
);
3210 for (unsigned chan
= 0; chan
< 8; chan
++) {
3212 if (!(writemask
& (1 << chan
)))
3215 value
= llvm_extract_elem(&ctx
->ac
, src
, chan
);
3217 if (instr
->variables
[0]->var
->data
.compact
)
3220 unsigned count
= glsl_count_attribute_slots(
3221 instr
->variables
[0]->var
->type
, false);
3223 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3224 &ctx
->ac
, ctx
->outputs
+ idx
+ chan
, count
,
3225 stride
, true, true);
3227 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3228 value
, indir_index
, "");
3229 build_store_values_extended(&ctx
->ac
, ctx
->outputs
+ idx
+ chan
,
3230 count
, stride
, tmp_vec
);
3233 temp_ptr
= ctx
->outputs
[idx
+ chan
+ const_index
* stride
];
3235 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3240 for (unsigned chan
= 0; chan
< 8; chan
++) {
3241 if (!(writemask
& (1 << chan
)))
3244 value
= llvm_extract_elem(&ctx
->ac
, src
, chan
);
3246 unsigned count
= glsl_count_attribute_slots(
3247 instr
->variables
[0]->var
->type
, false);
3249 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3250 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3253 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3254 value
, indir_index
, "");
3255 build_store_values_extended(&ctx
->ac
, ctx
->locals
+ idx
+ chan
,
3258 temp_ptr
= ctx
->locals
[idx
+ chan
+ const_index
* 4];
3260 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3264 case nir_var_shared
: {
3265 int writemask
= instr
->const_index
[0];
3266 LLVMValueRef address
= build_gep_for_deref(ctx
,
3267 instr
->variables
[0]);
3268 LLVMValueRef val
= get_src(ctx
, instr
->src
[0]);
3269 unsigned components
=
3270 glsl_get_vector_elements(
3271 nir_deref_tail(&instr
->variables
[0]->deref
)->type
);
3272 if (writemask
== (1 << components
) - 1) {
3273 val
= LLVMBuildBitCast(
3274 ctx
->ac
.builder
, val
,
3275 LLVMGetElementType(LLVMTypeOf(address
)), "");
3276 LLVMBuildStore(ctx
->ac
.builder
, val
, address
);
3278 for (unsigned chan
= 0; chan
< 4; chan
++) {
3279 if (!(writemask
& (1 << chan
)))
3282 LLVMBuildStructGEP(ctx
->ac
.builder
,
3284 LLVMValueRef src
= llvm_extract_elem(&ctx
->ac
, val
,
3286 src
= LLVMBuildBitCast(
3287 ctx
->ac
.builder
, src
,
3288 LLVMGetElementType(LLVMTypeOf(ptr
)), "");
3289 LLVMBuildStore(ctx
->ac
.builder
, src
, ptr
);
3299 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
3302 case GLSL_SAMPLER_DIM_BUF
:
3304 case GLSL_SAMPLER_DIM_1D
:
3305 return array
? 2 : 1;
3306 case GLSL_SAMPLER_DIM_2D
:
3307 return array
? 3 : 2;
3308 case GLSL_SAMPLER_DIM_MS
:
3309 return array
? 4 : 3;
3310 case GLSL_SAMPLER_DIM_3D
:
3311 case GLSL_SAMPLER_DIM_CUBE
:
3313 case GLSL_SAMPLER_DIM_RECT
:
3314 case GLSL_SAMPLER_DIM_SUBPASS
:
3316 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
3326 /* Adjust the sample index according to FMASK.
3328 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3329 * which is the identity mapping. Each nibble says which physical sample
3330 * should be fetched to get that sample.
3332 * For example, 0x11111100 means there are only 2 samples stored and
3333 * the second sample covers 3/4 of the pixel. When reading samples 0
3334 * and 1, return physical sample 0 (determined by the first two 0s
3335 * in FMASK), otherwise return physical sample 1.
3337 * The sample index should be adjusted as follows:
3338 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3340 static LLVMValueRef
adjust_sample_index_using_fmask(struct ac_llvm_context
*ctx
,
3341 LLVMValueRef coord_x
, LLVMValueRef coord_y
,
3342 LLVMValueRef coord_z
,
3343 LLVMValueRef sample_index
,
3344 LLVMValueRef fmask_desc_ptr
)
3346 LLVMValueRef fmask_load_address
[4];
3349 fmask_load_address
[0] = coord_x
;
3350 fmask_load_address
[1] = coord_y
;
3352 fmask_load_address
[2] = coord_z
;
3353 fmask_load_address
[3] = LLVMGetUndef(ctx
->i32
);
3356 struct ac_image_args args
= {0};
3358 args
.opcode
= ac_image_load
;
3359 args
.da
= coord_z
? true : false;
3360 args
.resource
= fmask_desc_ptr
;
3362 args
.addr
= ac_build_gather_values(ctx
, fmask_load_address
, coord_z
? 4 : 2);
3364 res
= ac_build_image_opcode(ctx
, &args
);
3366 res
= ac_to_integer(ctx
, res
);
3367 LLVMValueRef four
= LLVMConstInt(ctx
->i32
, 4, false);
3368 LLVMValueRef F
= LLVMConstInt(ctx
->i32
, 0xf, false);
3370 LLVMValueRef fmask
= LLVMBuildExtractElement(ctx
->builder
,
3374 LLVMValueRef sample_index4
=
3375 LLVMBuildMul(ctx
->builder
, sample_index
, four
, "");
3376 LLVMValueRef shifted_fmask
=
3377 LLVMBuildLShr(ctx
->builder
, fmask
, sample_index4
, "");
3378 LLVMValueRef final_sample
=
3379 LLVMBuildAnd(ctx
->builder
, shifted_fmask
, F
, "");
3381 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3382 * resource descriptor is 0 (invalid),
3384 LLVMValueRef fmask_desc
=
3385 LLVMBuildBitCast(ctx
->builder
, fmask_desc_ptr
,
3388 LLVMValueRef fmask_word1
=
3389 LLVMBuildExtractElement(ctx
->builder
, fmask_desc
,
3392 LLVMValueRef word1_is_nonzero
=
3393 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
,
3394 fmask_word1
, ctx
->i32_0
, "");
3396 /* Replace the MSAA sample index. */
3398 LLVMBuildSelect(ctx
->builder
, word1_is_nonzero
,
3399 final_sample
, sample_index
, "");
3400 return sample_index
;
3403 static LLVMValueRef
get_image_coords(struct ac_nir_context
*ctx
,
3404 const nir_intrinsic_instr
*instr
)
3406 const struct glsl_type
*type
= instr
->variables
[0]->var
->type
;
3407 if(instr
->variables
[0]->deref
.child
)
3408 type
= instr
->variables
[0]->deref
.child
->type
;
3410 LLVMValueRef src0
= get_src(ctx
, instr
->src
[0]);
3411 LLVMValueRef coords
[4];
3412 LLVMValueRef masks
[] = {
3413 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
3414 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
3417 LLVMValueRef sample_index
= llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[1]), 0);
3420 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3421 bool is_array
= glsl_sampler_type_is_array(type
);
3422 bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3423 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3424 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
||
3425 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3426 bool gfx9_1d
= ctx
->ac
.chip_class
>= GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
3427 count
= image_type_to_components_count(dim
, is_array
);
3430 LLVMValueRef fmask_load_address
[3];
3433 fmask_load_address
[0] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3434 fmask_load_address
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[1], "");
3436 fmask_load_address
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[2], "");
3438 fmask_load_address
[2] = NULL
;
3440 for (chan
= 0; chan
< 2; ++chan
)
3441 fmask_load_address
[chan
] =
3442 LLVMBuildAdd(ctx
->ac
.builder
, fmask_load_address
[chan
],
3443 LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3444 ctx
->ac
.i32
, ""), "");
3445 fmask_load_address
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3447 sample_index
= adjust_sample_index_using_fmask(&ctx
->ac
,
3448 fmask_load_address
[0],
3449 fmask_load_address
[1],
3450 fmask_load_address
[2],
3452 get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_FMASK
, true, false));
3454 if (count
== 1 && !gfx9_1d
) {
3455 if (instr
->src
[0].ssa
->num_components
)
3456 res
= LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3463 for (chan
= 0; chan
< count
; ++chan
) {
3464 coords
[chan
] = llvm_extract_elem(&ctx
->ac
, src0
, chan
);
3467 for (chan
= 0; chan
< 2; ++chan
)
3468 coords
[chan
] = LLVMBuildAdd(ctx
->ac
.builder
, coords
[chan
], LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3469 ctx
->ac
.i32
, ""), "");
3470 coords
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3476 coords
[2] = coords
[1];
3477 coords
[1] = ctx
->ac
.i32_0
;
3479 coords
[1] = ctx
->ac
.i32_0
;
3484 coords
[count
] = sample_index
;
3489 coords
[3] = LLVMGetUndef(ctx
->ac
.i32
);
3492 res
= ac_build_gather_values(&ctx
->ac
, coords
, count
);
3497 static LLVMValueRef
visit_image_load(struct ac_nir_context
*ctx
,
3498 const nir_intrinsic_instr
*instr
)
3500 LLVMValueRef params
[7];
3502 char intrinsic_name
[64];
3503 const nir_variable
*var
= instr
->variables
[0]->var
;
3504 const struct glsl_type
*type
= var
->type
;
3505 LLVMValueRef i1false
= LLVMConstInt(ctx
->ac
.i1
, 0, false);
3506 LLVMValueRef i1true
= LLVMConstInt(ctx
->ac
.i1
, 1, false);
3508 if(instr
->variables
[0]->deref
.child
)
3509 type
= instr
->variables
[0]->deref
.child
->type
;
3511 type
= glsl_without_array(type
);
3512 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3513 params
[0] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, true, false);
3514 params
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3515 ctx
->ac
.i32_0
, ""); /* vindex */
3516 params
[2] = ctx
->ac
.i32_0
; /* voffset */
3517 params
[3] = i1false
; /* glc */
3518 params
[4] = i1false
; /* slc */
3519 res
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.load.format.v4f32", ctx
->ac
.v4f32
,
3522 res
= trim_vector(&ctx
->ac
, res
, instr
->dest
.ssa
.num_components
);
3523 res
= ac_to_integer(&ctx
->ac
, res
);
3525 bool is_da
= glsl_sampler_type_is_array(type
) ||
3526 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
||
3527 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_SUBPASS
||
3528 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_SUBPASS_MS
;
3529 LLVMValueRef da
= is_da
? i1true
: i1false
;
3530 LLVMValueRef glc
= i1false
;
3531 LLVMValueRef slc
= i1false
;
3533 params
[0] = get_image_coords(ctx
, instr
);
3534 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, true, false);
3535 params
[2] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3536 if (HAVE_LLVM
<= 0x0309) {
3537 params
[3] = i1false
; /* r128 */
3542 LLVMValueRef lwe
= i1false
;
3549 ac_get_image_intr_name("llvm.amdgcn.image.load",
3550 ctx
->ac
.v4f32
, /* vdata */
3551 LLVMTypeOf(params
[0]), /* coords */
3552 LLVMTypeOf(params
[1]), /* rsrc */
3553 intrinsic_name
, sizeof(intrinsic_name
));
3555 res
= ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.v4f32
,
3556 params
, 7, AC_FUNC_ATTR_READONLY
);
3558 return ac_to_integer(&ctx
->ac
, res
);
3561 static void visit_image_store(struct ac_nir_context
*ctx
,
3562 nir_intrinsic_instr
*instr
)
3564 LLVMValueRef params
[8];
3565 char intrinsic_name
[64];
3566 const nir_variable
*var
= instr
->variables
[0]->var
;
3567 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3568 LLVMValueRef i1false
= LLVMConstInt(ctx
->ac
.i1
, 0, false);
3569 LLVMValueRef i1true
= LLVMConstInt(ctx
->ac
.i1
, 1, false);
3570 LLVMValueRef glc
= i1false
;
3571 bool force_glc
= ctx
->ac
.chip_class
== SI
;
3575 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3576 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2])); /* data */
3577 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, true, true);
3578 params
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3579 ctx
->ac
.i32_0
, ""); /* vindex */
3580 params
[3] = ctx
->ac
.i32_0
; /* voffset */
3581 params
[4] = glc
; /* glc */
3582 params
[5] = i1false
; /* slc */
3583 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.store.format.v4f32", ctx
->ac
.voidt
,
3586 bool is_da
= glsl_sampler_type_is_array(type
) ||
3587 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
;
3588 LLVMValueRef da
= is_da
? i1true
: i1false
;
3589 LLVMValueRef slc
= i1false
;
3591 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2]));
3592 params
[1] = get_image_coords(ctx
, instr
); /* coords */
3593 params
[2] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, true, true);
3594 params
[3] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3595 if (HAVE_LLVM
<= 0x0309) {
3596 params
[4] = i1false
; /* r128 */
3601 LLVMValueRef lwe
= i1false
;
3608 ac_get_image_intr_name("llvm.amdgcn.image.store",
3609 LLVMTypeOf(params
[0]), /* vdata */
3610 LLVMTypeOf(params
[1]), /* coords */
3611 LLVMTypeOf(params
[2]), /* rsrc */
3612 intrinsic_name
, sizeof(intrinsic_name
));
3614 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.voidt
,
3620 static LLVMValueRef
visit_image_atomic(struct ac_nir_context
*ctx
,
3621 const nir_intrinsic_instr
*instr
)
3623 LLVMValueRef params
[7];
3624 int param_count
= 0;
3625 const nir_variable
*var
= instr
->variables
[0]->var
;
3627 const char *atomic_name
;
3628 char intrinsic_name
[41];
3629 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3630 LLVMValueRef i1false
= LLVMConstInt(ctx
->ac
.i1
, 0, false);
3631 LLVMValueRef i1true
= LLVMConstInt(ctx
->ac
.i1
, 1, false);
3632 MAYBE_UNUSED
int length
;
3634 switch (instr
->intrinsic
) {
3635 case nir_intrinsic_image_atomic_add
:
3636 atomic_name
= "add";
3638 case nir_intrinsic_image_atomic_min
:
3639 atomic_name
= "smin";
3641 case nir_intrinsic_image_atomic_max
:
3642 atomic_name
= "smax";
3644 case nir_intrinsic_image_atomic_and
:
3645 atomic_name
= "and";
3647 case nir_intrinsic_image_atomic_or
:
3650 case nir_intrinsic_image_atomic_xor
:
3651 atomic_name
= "xor";
3653 case nir_intrinsic_image_atomic_exchange
:
3654 atomic_name
= "swap";
3656 case nir_intrinsic_image_atomic_comp_swap
:
3657 atomic_name
= "cmpswap";
3663 if (instr
->intrinsic
== nir_intrinsic_image_atomic_comp_swap
)
3664 params
[param_count
++] = get_src(ctx
, instr
->src
[3]);
3665 params
[param_count
++] = get_src(ctx
, instr
->src
[2]);
3667 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3668 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
,
3670 params
[param_count
++] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3671 ctx
->ac
.i32_0
, ""); /* vindex */
3672 params
[param_count
++] = ctx
->ac
.i32_0
; /* voffset */
3673 params
[param_count
++] = i1false
; /* slc */
3675 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3676 "llvm.amdgcn.buffer.atomic.%s", atomic_name
);
3678 char coords_type
[8];
3680 bool da
= glsl_sampler_type_is_array(type
) ||
3681 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
;
3683 LLVMValueRef coords
= params
[param_count
++] = get_image_coords(ctx
, instr
);
3684 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
,
3686 params
[param_count
++] = i1false
; /* r128 */
3687 params
[param_count
++] = da
? i1true
: i1false
; /* da */
3688 params
[param_count
++] = i1false
; /* slc */
3690 build_int_type_name(LLVMTypeOf(coords
),
3691 coords_type
, sizeof(coords_type
));
3693 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3694 "llvm.amdgcn.image.atomic.%s.%s", atomic_name
, coords_type
);
3697 assert(length
< sizeof(intrinsic_name
));
3698 return ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.i32
, params
, param_count
, 0);
3701 static LLVMValueRef
visit_image_size(struct ac_nir_context
*ctx
,
3702 const nir_intrinsic_instr
*instr
)
3705 const nir_variable
*var
= instr
->variables
[0]->var
;
3706 const struct glsl_type
*type
= instr
->variables
[0]->var
->type
;
3707 bool da
= glsl_sampler_type_is_array(var
->type
) ||
3708 glsl_get_sampler_dim(var
->type
) == GLSL_SAMPLER_DIM_CUBE
;
3709 if(instr
->variables
[0]->deref
.child
)
3710 type
= instr
->variables
[0]->deref
.child
->type
;
3712 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
)
3713 return get_buffer_size(ctx
,
3714 get_sampler_desc(ctx
, instr
->variables
[0],
3715 AC_DESC_BUFFER
, true, false), true);
3717 struct ac_image_args args
= { 0 };
3721 args
.resource
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, true, false);
3722 args
.opcode
= ac_image_get_resinfo
;
3723 args
.addr
= ctx
->ac
.i32_0
;
3725 res
= ac_build_image_opcode(&ctx
->ac
, &args
);
3727 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
3729 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
3730 glsl_sampler_type_is_array(type
)) {
3731 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
3732 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3733 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
3734 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, z
, two
, "");
3736 if (ctx
->ac
.chip_class
>= GFX9
&&
3737 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
3738 glsl_sampler_type_is_array(type
)) {
3739 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3740 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, layers
,
3747 #define NOOP_WAITCNT 0xf7f
3748 #define LGKM_CNT 0x07f
3749 #define VM_CNT 0xf70
3751 static void emit_waitcnt(struct nir_to_llvm_context
*ctx
,
3754 LLVMValueRef args
[1] = {
3755 LLVMConstInt(ctx
->i32
, simm16
, false),
3757 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.s.waitcnt",
3758 ctx
->voidt
, args
, 1, 0);
3761 static void emit_barrier(struct nir_to_llvm_context
*ctx
)
3763 /* SI only (thanks to a hw bug workaround):
3764 * The real barrier instruction isn’t needed, because an entire patch
3765 * always fits into a single wave.
3767 if (ctx
->options
->chip_class
== SI
&&
3768 ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3769 emit_waitcnt(ctx
, LGKM_CNT
& VM_CNT
);
3772 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.s.barrier",
3773 ctx
->voidt
, NULL
, 0, AC_FUNC_ATTR_CONVERGENT
);
3776 static void emit_discard_if(struct ac_nir_context
*ctx
,
3777 const nir_intrinsic_instr
*instr
)
3781 cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
,
3782 get_src(ctx
, instr
->src
[0]),
3785 cond
= LLVMBuildSelect(ctx
->ac
.builder
, cond
,
3786 LLVMConstReal(ctx
->ac
.f32
, -1.0f
),
3788 ac_build_kill(&ctx
->ac
, cond
);
3792 visit_load_local_invocation_index(struct nir_to_llvm_context
*ctx
)
3794 LLVMValueRef result
;
3795 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
->ac
);
3796 result
= LLVMBuildAnd(ctx
->builder
, ctx
->tg_size
,
3797 LLVMConstInt(ctx
->i32
, 0xfc0, false), "");
3799 return LLVMBuildAdd(ctx
->builder
, result
, thread_id
, "");
3802 static LLVMValueRef
visit_var_atomic(struct nir_to_llvm_context
*ctx
,
3803 const nir_intrinsic_instr
*instr
)
3805 LLVMValueRef ptr
, result
;
3806 LLVMValueRef src
= get_src(ctx
->nir
, instr
->src
[0]);
3807 ptr
= build_gep_for_deref(ctx
->nir
, instr
->variables
[0]);
3809 if (instr
->intrinsic
== nir_intrinsic_var_atomic_comp_swap
) {
3810 LLVMValueRef src1
= get_src(ctx
->nir
, instr
->src
[1]);
3811 result
= LLVMBuildAtomicCmpXchg(ctx
->builder
,
3813 LLVMAtomicOrderingSequentiallyConsistent
,
3814 LLVMAtomicOrderingSequentiallyConsistent
,
3817 LLVMAtomicRMWBinOp op
;
3818 switch (instr
->intrinsic
) {
3819 case nir_intrinsic_var_atomic_add
:
3820 op
= LLVMAtomicRMWBinOpAdd
;
3822 case nir_intrinsic_var_atomic_umin
:
3823 op
= LLVMAtomicRMWBinOpUMin
;
3825 case nir_intrinsic_var_atomic_umax
:
3826 op
= LLVMAtomicRMWBinOpUMax
;
3828 case nir_intrinsic_var_atomic_imin
:
3829 op
= LLVMAtomicRMWBinOpMin
;
3831 case nir_intrinsic_var_atomic_imax
:
3832 op
= LLVMAtomicRMWBinOpMax
;
3834 case nir_intrinsic_var_atomic_and
:
3835 op
= LLVMAtomicRMWBinOpAnd
;
3837 case nir_intrinsic_var_atomic_or
:
3838 op
= LLVMAtomicRMWBinOpOr
;
3840 case nir_intrinsic_var_atomic_xor
:
3841 op
= LLVMAtomicRMWBinOpXor
;
3843 case nir_intrinsic_var_atomic_exchange
:
3844 op
= LLVMAtomicRMWBinOpXchg
;
3850 result
= LLVMBuildAtomicRMW(ctx
->builder
, op
, ptr
, ac_to_integer(&ctx
->ac
, src
),
3851 LLVMAtomicOrderingSequentiallyConsistent
,
3857 #define INTERP_CENTER 0
3858 #define INTERP_CENTROID 1
3859 #define INTERP_SAMPLE 2
3861 static LLVMValueRef
lookup_interp_param(struct nir_to_llvm_context
*ctx
,
3862 enum glsl_interp_mode interp
, unsigned location
)
3865 case INTERP_MODE_FLAT
:
3868 case INTERP_MODE_SMOOTH
:
3869 case INTERP_MODE_NONE
:
3870 if (location
== INTERP_CENTER
)
3871 return ctx
->persp_center
;
3872 else if (location
== INTERP_CENTROID
)
3873 return ctx
->persp_centroid
;
3874 else if (location
== INTERP_SAMPLE
)
3875 return ctx
->persp_sample
;
3877 case INTERP_MODE_NOPERSPECTIVE
:
3878 if (location
== INTERP_CENTER
)
3879 return ctx
->linear_center
;
3880 else if (location
== INTERP_CENTROID
)
3881 return ctx
->linear_centroid
;
3882 else if (location
== INTERP_SAMPLE
)
3883 return ctx
->linear_sample
;
3889 static LLVMValueRef
load_sample_position(struct nir_to_llvm_context
*ctx
,
3890 LLVMValueRef sample_id
)
3892 LLVMValueRef result
;
3893 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->i32
, RING_PS_SAMPLE_POSITIONS
, false));
3895 ptr
= LLVMBuildBitCast(ctx
->builder
, ptr
,
3896 const_array(ctx
->v2f32
, 64), "");
3898 sample_id
= LLVMBuildAdd(ctx
->builder
, sample_id
, ctx
->sample_pos_offset
, "");
3899 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
3904 static LLVMValueRef
load_sample_pos(struct ac_nir_context
*ctx
)
3906 LLVMValueRef values
[2];
3908 values
[0] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[0]);
3909 values
[1] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[1]);
3910 return ac_build_gather_values(&ctx
->ac
, values
, 2);
3913 static LLVMValueRef
visit_interp(struct nir_to_llvm_context
*ctx
,
3914 const nir_intrinsic_instr
*instr
)
3916 LLVMValueRef result
[2];
3917 LLVMValueRef interp_param
, attr_number
;
3920 LLVMValueRef src_c0
= NULL
;
3921 LLVMValueRef src_c1
= NULL
;
3922 LLVMValueRef src0
= NULL
;
3923 int input_index
= instr
->variables
[0]->var
->data
.location
- VARYING_SLOT_VAR0
;
3924 switch (instr
->intrinsic
) {
3925 case nir_intrinsic_interp_var_at_centroid
:
3926 location
= INTERP_CENTROID
;
3928 case nir_intrinsic_interp_var_at_sample
:
3929 case nir_intrinsic_interp_var_at_offset
:
3930 location
= INTERP_CENTER
;
3931 src0
= get_src(ctx
->nir
, instr
->src
[0]);
3937 if (instr
->intrinsic
== nir_intrinsic_interp_var_at_offset
) {
3938 src_c0
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32zero
, ""));
3939 src_c1
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32one
, ""));
3940 } else if (instr
->intrinsic
== nir_intrinsic_interp_var_at_sample
) {
3941 LLVMValueRef sample_position
;
3942 LLVMValueRef halfval
= LLVMConstReal(ctx
->f32
, 0.5f
);
3944 /* fetch sample ID */
3945 sample_position
= load_sample_position(ctx
, src0
);
3947 src_c0
= LLVMBuildExtractElement(ctx
->builder
, sample_position
, ctx
->i32zero
, "");
3948 src_c0
= LLVMBuildFSub(ctx
->builder
, src_c0
, halfval
, "");
3949 src_c1
= LLVMBuildExtractElement(ctx
->builder
, sample_position
, ctx
->i32one
, "");
3950 src_c1
= LLVMBuildFSub(ctx
->builder
, src_c1
, halfval
, "");
3952 interp_param
= lookup_interp_param(ctx
, instr
->variables
[0]->var
->data
.interpolation
, location
);
3953 attr_number
= LLVMConstInt(ctx
->i32
, input_index
, false);
3955 if (location
== INTERP_CENTER
) {
3956 LLVMValueRef ij_out
[2];
3957 LLVMValueRef ddxy_out
= emit_ddxy_interp(ctx
->nir
, interp_param
);
3960 * take the I then J parameters, and the DDX/Y for it, and
3961 * calculate the IJ inputs for the interpolator.
3962 * temp1 = ddx * offset/sample.x + I;
3963 * interp_param.I = ddy * offset/sample.y + temp1;
3964 * temp1 = ddx * offset/sample.x + J;
3965 * interp_param.J = ddy * offset/sample.y + temp1;
3967 for (unsigned i
= 0; i
< 2; i
++) {
3968 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->i32
, i
, false);
3969 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->i32
, i
+ 2, false);
3970 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->builder
,
3971 ddxy_out
, ix_ll
, "");
3972 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->builder
,
3973 ddxy_out
, iy_ll
, "");
3974 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->builder
,
3975 interp_param
, ix_ll
, "");
3976 LLVMValueRef temp1
, temp2
;
3978 interp_el
= LLVMBuildBitCast(ctx
->builder
, interp_el
,
3981 temp1
= LLVMBuildFMul(ctx
->builder
, ddx_el
, src_c0
, "");
3982 temp1
= LLVMBuildFAdd(ctx
->builder
, temp1
, interp_el
, "");
3984 temp2
= LLVMBuildFMul(ctx
->builder
, ddy_el
, src_c1
, "");
3985 temp2
= LLVMBuildFAdd(ctx
->builder
, temp2
, temp1
, "");
3987 ij_out
[i
] = LLVMBuildBitCast(ctx
->builder
,
3988 temp2
, ctx
->i32
, "");
3990 interp_param
= ac_build_gather_values(&ctx
->ac
, ij_out
, 2);
3994 for (chan
= 0; chan
< 2; chan
++) {
3995 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->i32
, chan
, false);
3998 interp_param
= LLVMBuildBitCast(ctx
->builder
,
3999 interp_param
, LLVMVectorType(ctx
->f32
, 2), "");
4000 LLVMValueRef i
= LLVMBuildExtractElement(
4001 ctx
->builder
, interp_param
, ctx
->i32zero
, "");
4002 LLVMValueRef j
= LLVMBuildExtractElement(
4003 ctx
->builder
, interp_param
, ctx
->i32one
, "");
4005 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
4006 llvm_chan
, attr_number
,
4007 ctx
->prim_mask
, i
, j
);
4009 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
4010 LLVMConstInt(ctx
->i32
, 2, false),
4011 llvm_chan
, attr_number
,
4015 return ac_build_gather_values(&ctx
->ac
, result
, 2);
4019 visit_emit_vertex(struct nir_to_llvm_context
*ctx
,
4020 const nir_intrinsic_instr
*instr
)
4022 LLVMValueRef gs_next_vertex
;
4023 LLVMValueRef can_emit
, kill
;
4026 assert(instr
->const_index
[0] == 0);
4027 /* Write vertex attribute values to GSVS ring */
4028 gs_next_vertex
= LLVMBuildLoad(ctx
->builder
,
4029 ctx
->gs_next_vertex
,
4032 /* If this thread has already emitted the declared maximum number of
4033 * vertices, kill it: excessive vertex emissions are not supposed to
4034 * have any effect, and GS threads have no externally observable
4035 * effects other than emitting vertices.
4037 can_emit
= LLVMBuildICmp(ctx
->builder
, LLVMIntULT
, gs_next_vertex
,
4038 LLVMConstInt(ctx
->i32
, ctx
->gs_max_out_vertices
, false), "");
4040 kill
= LLVMBuildSelect(ctx
->builder
, can_emit
,
4041 LLVMConstReal(ctx
->f32
, 1.0f
),
4042 LLVMConstReal(ctx
->f32
, -1.0f
), "");
4043 ac_build_kill(&ctx
->ac
, kill
);
4045 /* loop num outputs */
4047 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
4048 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
4053 if (!(ctx
->output_mask
& (1ull << i
)))
4056 if (i
== VARYING_SLOT_CLIP_DIST0
) {
4057 /* pack clip and cull into a single set of slots */
4058 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
4062 for (unsigned j
= 0; j
< length
; j
++) {
4063 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
,
4065 LLVMValueRef voffset
= LLVMConstInt(ctx
->i32
, (slot
* 4 + j
) * ctx
->gs_max_out_vertices
, false);
4066 voffset
= LLVMBuildAdd(ctx
->builder
, voffset
, gs_next_vertex
, "");
4067 voffset
= LLVMBuildMul(ctx
->builder
, voffset
, LLVMConstInt(ctx
->i32
, 4, false), "");
4069 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->i32
, "");
4071 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->gsvs_ring
,
4073 voffset
, ctx
->gs2vs_offset
, 0,
4079 gs_next_vertex
= LLVMBuildAdd(ctx
->builder
, gs_next_vertex
,
4081 LLVMBuildStore(ctx
->builder
, gs_next_vertex
, ctx
->gs_next_vertex
);
4083 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
4087 visit_end_primitive(struct nir_to_llvm_context
*ctx
,
4088 const nir_intrinsic_instr
*instr
)
4090 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
4094 visit_load_tess_coord(struct nir_to_llvm_context
*ctx
,
4095 const nir_intrinsic_instr
*instr
)
4097 LLVMValueRef coord
[4] = {
4104 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
4105 coord
[2] = LLVMBuildFSub(ctx
->builder
, ctx
->f32one
,
4106 LLVMBuildFAdd(ctx
->builder
, coord
[0], coord
[1], ""), "");
4108 LLVMValueRef result
= ac_build_gather_values(&ctx
->ac
, coord
, instr
->num_components
);
4109 return LLVMBuildBitCast(ctx
->builder
, result
,
4110 get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
4113 static void visit_intrinsic(struct ac_nir_context
*ctx
,
4114 nir_intrinsic_instr
*instr
)
4116 LLVMValueRef result
= NULL
;
4118 switch (instr
->intrinsic
) {
4119 case nir_intrinsic_load_work_group_id
: {
4120 result
= ctx
->nctx
->workgroup_ids
;
4123 case nir_intrinsic_load_base_vertex
: {
4124 result
= ctx
->abi
->base_vertex
;
4127 case nir_intrinsic_load_vertex_id_zero_base
: {
4128 result
= ctx
->abi
->vertex_id
;
4131 case nir_intrinsic_load_local_invocation_id
: {
4132 result
= ctx
->nctx
->local_invocation_ids
;
4135 case nir_intrinsic_load_base_instance
:
4136 result
= ctx
->abi
->start_instance
;
4138 case nir_intrinsic_load_draw_id
:
4139 result
= ctx
->abi
->draw_id
;
4141 case nir_intrinsic_load_view_index
:
4142 result
= ctx
->nctx
->view_index
? ctx
->nctx
->view_index
: ctx
->ac
.i32_0
;
4144 case nir_intrinsic_load_invocation_id
:
4145 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
4146 result
= unpack_param(&ctx
->ac
, ctx
->nctx
->tcs_rel_ids
, 8, 5);
4148 result
= ctx
->nctx
->gs_invocation_id
;
4150 case nir_intrinsic_load_primitive_id
:
4151 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
4152 ctx
->nctx
->shader_info
->gs
.uses_prim_id
= true;
4153 result
= ctx
->nctx
->gs_prim_id
;
4154 } else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
4155 ctx
->nctx
->shader_info
->tcs
.uses_prim_id
= true;
4156 result
= ctx
->nctx
->tcs_patch_id
;
4157 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4158 ctx
->nctx
->shader_info
->tcs
.uses_prim_id
= true;
4159 result
= ctx
->nctx
->tes_patch_id
;
4161 fprintf(stderr
, "Unknown primitive id intrinsic: %d", ctx
->stage
);
4163 case nir_intrinsic_load_sample_id
:
4164 result
= unpack_param(&ctx
->ac
, ctx
->abi
->ancillary
, 8, 4);
4166 case nir_intrinsic_load_sample_pos
:
4167 result
= load_sample_pos(ctx
);
4169 case nir_intrinsic_load_sample_mask_in
:
4170 result
= ctx
->abi
->sample_coverage
;
4172 case nir_intrinsic_load_frag_coord
: {
4173 LLVMValueRef values
[4] = {
4174 ctx
->abi
->frag_pos
[0],
4175 ctx
->abi
->frag_pos
[1],
4176 ctx
->abi
->frag_pos
[2],
4177 ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, ctx
->abi
->frag_pos
[3])
4179 result
= ac_build_gather_values(&ctx
->ac
, values
, 4);
4182 case nir_intrinsic_load_front_face
:
4183 result
= ctx
->abi
->front_face
;
4185 case nir_intrinsic_load_instance_id
:
4186 result
= ctx
->abi
->instance_id
;
4188 case nir_intrinsic_load_num_work_groups
:
4189 result
= ctx
->nctx
->num_work_groups
;
4191 case nir_intrinsic_load_local_invocation_index
:
4192 result
= visit_load_local_invocation_index(ctx
->nctx
);
4194 case nir_intrinsic_load_push_constant
:
4195 result
= visit_load_push_constant(ctx
->nctx
, instr
);
4197 case nir_intrinsic_vulkan_resource_index
:
4198 result
= visit_vulkan_resource_index(ctx
->nctx
, instr
);
4200 case nir_intrinsic_store_ssbo
:
4201 visit_store_ssbo(ctx
, instr
);
4203 case nir_intrinsic_load_ssbo
:
4204 result
= visit_load_buffer(ctx
, instr
);
4206 case nir_intrinsic_ssbo_atomic_add
:
4207 case nir_intrinsic_ssbo_atomic_imin
:
4208 case nir_intrinsic_ssbo_atomic_umin
:
4209 case nir_intrinsic_ssbo_atomic_imax
:
4210 case nir_intrinsic_ssbo_atomic_umax
:
4211 case nir_intrinsic_ssbo_atomic_and
:
4212 case nir_intrinsic_ssbo_atomic_or
:
4213 case nir_intrinsic_ssbo_atomic_xor
:
4214 case nir_intrinsic_ssbo_atomic_exchange
:
4215 case nir_intrinsic_ssbo_atomic_comp_swap
:
4216 result
= visit_atomic_ssbo(ctx
, instr
);
4218 case nir_intrinsic_load_ubo
:
4219 result
= visit_load_ubo_buffer(ctx
, instr
);
4221 case nir_intrinsic_get_buffer_size
:
4222 result
= visit_get_buffer_size(ctx
, instr
);
4224 case nir_intrinsic_load_var
:
4225 result
= visit_load_var(ctx
, instr
);
4227 case nir_intrinsic_store_var
:
4228 visit_store_var(ctx
, instr
);
4230 case nir_intrinsic_image_load
:
4231 result
= visit_image_load(ctx
, instr
);
4233 case nir_intrinsic_image_store
:
4234 visit_image_store(ctx
, instr
);
4236 case nir_intrinsic_image_atomic_add
:
4237 case nir_intrinsic_image_atomic_min
:
4238 case nir_intrinsic_image_atomic_max
:
4239 case nir_intrinsic_image_atomic_and
:
4240 case nir_intrinsic_image_atomic_or
:
4241 case nir_intrinsic_image_atomic_xor
:
4242 case nir_intrinsic_image_atomic_exchange
:
4243 case nir_intrinsic_image_atomic_comp_swap
:
4244 result
= visit_image_atomic(ctx
, instr
);
4246 case nir_intrinsic_image_size
:
4247 result
= visit_image_size(ctx
, instr
);
4249 case nir_intrinsic_discard
:
4250 ac_build_intrinsic(&ctx
->ac
, "llvm.AMDGPU.kilp",
4251 LLVMVoidTypeInContext(ctx
->ac
.context
),
4252 NULL
, 0, AC_FUNC_ATTR_LEGACY
);
4254 case nir_intrinsic_discard_if
:
4255 emit_discard_if(ctx
, instr
);
4257 case nir_intrinsic_memory_barrier
:
4258 emit_waitcnt(ctx
->nctx
, VM_CNT
);
4260 case nir_intrinsic_barrier
:
4261 emit_barrier(ctx
->nctx
);
4263 case nir_intrinsic_var_atomic_add
:
4264 case nir_intrinsic_var_atomic_imin
:
4265 case nir_intrinsic_var_atomic_umin
:
4266 case nir_intrinsic_var_atomic_imax
:
4267 case nir_intrinsic_var_atomic_umax
:
4268 case nir_intrinsic_var_atomic_and
:
4269 case nir_intrinsic_var_atomic_or
:
4270 case nir_intrinsic_var_atomic_xor
:
4271 case nir_intrinsic_var_atomic_exchange
:
4272 case nir_intrinsic_var_atomic_comp_swap
:
4273 result
= visit_var_atomic(ctx
->nctx
, instr
);
4275 case nir_intrinsic_interp_var_at_centroid
:
4276 case nir_intrinsic_interp_var_at_sample
:
4277 case nir_intrinsic_interp_var_at_offset
:
4278 result
= visit_interp(ctx
->nctx
, instr
);
4280 case nir_intrinsic_emit_vertex
:
4281 visit_emit_vertex(ctx
->nctx
, instr
);
4283 case nir_intrinsic_end_primitive
:
4284 visit_end_primitive(ctx
->nctx
, instr
);
4286 case nir_intrinsic_load_tess_coord
:
4287 result
= visit_load_tess_coord(ctx
->nctx
, instr
);
4289 case nir_intrinsic_load_patch_vertices_in
:
4290 result
= LLVMConstInt(ctx
->ac
.i32
, ctx
->nctx
->options
->key
.tcs
.input_vertices
, false);
4293 fprintf(stderr
, "Unknown intrinsic: ");
4294 nir_print_instr(&instr
->instr
, stderr
);
4295 fprintf(stderr
, "\n");
4299 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4303 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
4304 LLVMValueRef buffer
, bool write
)
4306 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4308 if (write
&& ctx
->stage
== MESA_SHADER_FRAGMENT
)
4309 ctx
->shader_info
->fs
.writes_memory
= true;
4314 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
4315 unsigned descriptor_set
,
4316 unsigned base_index
,
4317 unsigned constant_index
,
4319 enum ac_descriptor_type desc_type
,
4320 bool image
, bool write
)
4322 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4323 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
4324 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
4325 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
4326 unsigned offset
= binding
->offset
;
4327 unsigned stride
= binding
->size
;
4329 LLVMBuilderRef builder
= ctx
->builder
;
4332 assert(base_index
< layout
->binding_count
);
4334 if (write
&& ctx
->stage
== MESA_SHADER_FRAGMENT
)
4335 ctx
->shader_info
->fs
.writes_memory
= true;
4337 switch (desc_type
) {
4347 case AC_DESC_SAMPLER
:
4349 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
4354 case AC_DESC_BUFFER
:
4359 unreachable("invalid desc_type\n");
4362 offset
+= constant_index
* stride
;
4364 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
4365 (!index
|| binding
->immutable_samplers_equal
)) {
4366 if (binding
->immutable_samplers_equal
)
4369 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
4371 LLVMValueRef constants
[] = {
4372 LLVMConstInt(ctx
->i32
, samplers
[constant_index
* 4 + 0], 0),
4373 LLVMConstInt(ctx
->i32
, samplers
[constant_index
* 4 + 1], 0),
4374 LLVMConstInt(ctx
->i32
, samplers
[constant_index
* 4 + 2], 0),
4375 LLVMConstInt(ctx
->i32
, samplers
[constant_index
* 4 + 3], 0),
4377 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
4380 assert(stride
% type_size
== 0);
4383 index
= ctx
->i32zero
;
4385 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, stride
/ type_size
, 0), "");
4387 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->i32
, offset
, 0));
4388 list
= LLVMBuildPointerCast(builder
, list
, const_array(type
, 0), "");
4390 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
4393 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
4394 const nir_deref_var
*deref
,
4395 enum ac_descriptor_type desc_type
,
4396 bool image
, bool write
)
4398 LLVMValueRef index
= NULL
;
4399 unsigned constant_index
= 0;
4400 const nir_deref
*tail
= &deref
->deref
;
4402 while (tail
->child
) {
4403 const nir_deref_array
*child
= nir_deref_as_array(tail
->child
);
4404 unsigned array_size
= glsl_get_aoa_size(tail
->child
->type
);
4409 assert(child
->deref_array_type
!= nir_deref_array_type_wildcard
);
4411 if (child
->deref_array_type
== nir_deref_array_type_indirect
) {
4412 LLVMValueRef indirect
= get_src(ctx
, child
->indirect
);
4414 indirect
= LLVMBuildMul(ctx
->ac
.builder
, indirect
,
4415 LLVMConstInt(ctx
->ac
.i32
, array_size
, false), "");
4420 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
, indirect
, "");
4423 constant_index
+= child
->base_offset
* array_size
;
4425 tail
= &child
->deref
;
4428 return ctx
->abi
->load_sampler_desc(ctx
->abi
,
4429 deref
->var
->data
.descriptor_set
,
4430 deref
->var
->data
.binding
,
4431 constant_index
, index
,
4432 desc_type
, image
, write
);
4435 static void set_tex_fetch_args(struct ac_llvm_context
*ctx
,
4436 struct ac_image_args
*args
,
4437 const nir_tex_instr
*instr
,
4439 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
4440 LLVMValueRef
*param
, unsigned count
,
4443 unsigned is_rect
= 0;
4444 bool da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
4446 if (op
== nir_texop_lod
)
4448 /* Pad to power of two vector */
4449 while (count
< util_next_power_of_two(count
))
4450 param
[count
++] = LLVMGetUndef(ctx
->i32
);
4453 args
->addr
= ac_build_gather_values(ctx
, param
, count
);
4455 args
->addr
= param
[0];
4457 args
->resource
= res_ptr
;
4458 args
->sampler
= samp_ptr
;
4460 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
&& op
== nir_texop_txf
) {
4461 args
->addr
= param
[0];
4465 args
->dmask
= dmask
;
4466 args
->unorm
= is_rect
;
4470 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4473 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4474 * filtering manually. The driver sets img7 to a mask clearing
4475 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4476 * s_and_b32 samp0, samp0, img7
4479 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4481 static LLVMValueRef
sici_fix_sampler_aniso(struct ac_nir_context
*ctx
,
4482 LLVMValueRef res
, LLVMValueRef samp
)
4484 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4485 LLVMValueRef img7
, samp0
;
4487 if (ctx
->ac
.chip_class
>= VI
)
4490 img7
= LLVMBuildExtractElement(builder
, res
,
4491 LLVMConstInt(ctx
->ac
.i32
, 7, 0), "");
4492 samp0
= LLVMBuildExtractElement(builder
, samp
,
4493 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4494 samp0
= LLVMBuildAnd(builder
, samp0
, img7
, "");
4495 return LLVMBuildInsertElement(builder
, samp
, samp0
,
4496 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4499 static void tex_fetch_ptrs(struct ac_nir_context
*ctx
,
4500 nir_tex_instr
*instr
,
4501 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
4502 LLVMValueRef
*fmask_ptr
)
4504 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4505 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_BUFFER
, false, false);
4507 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_IMAGE
, false, false);
4510 *samp_ptr
= get_sampler_desc(ctx
, instr
->sampler
, AC_DESC_SAMPLER
, false, false);
4512 *samp_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_SAMPLER
, false, false);
4513 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
)
4514 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
4516 if (fmask_ptr
&& !instr
->sampler
&& (instr
->op
== nir_texop_txf_ms
||
4517 instr
->op
== nir_texop_samples_identical
))
4518 *fmask_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_FMASK
, false, false);
4521 static LLVMValueRef
apply_round_slice(struct ac_llvm_context
*ctx
,
4524 coord
= ac_to_float(ctx
, coord
);
4525 coord
= ac_build_intrinsic(ctx
, "llvm.rint.f32", ctx
->f32
, &coord
, 1, 0);
4526 coord
= ac_to_integer(ctx
, coord
);
4530 static void visit_tex(struct ac_nir_context
*ctx
, nir_tex_instr
*instr
)
4532 LLVMValueRef result
= NULL
;
4533 struct ac_image_args args
= { 0 };
4534 unsigned dmask
= 0xf;
4535 LLVMValueRef address
[16];
4536 LLVMValueRef coords
[5];
4537 LLVMValueRef coord
= NULL
, lod
= NULL
, comparator
= NULL
;
4538 LLVMValueRef bias
= NULL
, offsets
= NULL
;
4539 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
, sample_index
= NULL
;
4540 LLVMValueRef ddx
= NULL
, ddy
= NULL
;
4541 LLVMValueRef derivs
[6];
4542 unsigned chan
, count
= 0;
4543 unsigned const_src
= 0, num_deriv_comp
= 0;
4544 bool lod_is_zero
= false;
4546 tex_fetch_ptrs(ctx
, instr
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4548 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4549 switch (instr
->src
[i
].src_type
) {
4550 case nir_tex_src_coord
:
4551 coord
= get_src(ctx
, instr
->src
[i
].src
);
4553 case nir_tex_src_projector
:
4555 case nir_tex_src_comparator
:
4556 comparator
= get_src(ctx
, instr
->src
[i
].src
);
4558 case nir_tex_src_offset
:
4559 offsets
= get_src(ctx
, instr
->src
[i
].src
);
4562 case nir_tex_src_bias
:
4563 bias
= get_src(ctx
, instr
->src
[i
].src
);
4565 case nir_tex_src_lod
: {
4566 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
4568 if (val
&& val
->i32
[0] == 0)
4570 lod
= get_src(ctx
, instr
->src
[i
].src
);
4573 case nir_tex_src_ms_index
:
4574 sample_index
= get_src(ctx
, instr
->src
[i
].src
);
4576 case nir_tex_src_ms_mcs
:
4578 case nir_tex_src_ddx
:
4579 ddx
= get_src(ctx
, instr
->src
[i
].src
);
4580 num_deriv_comp
= instr
->src
[i
].src
.ssa
->num_components
;
4582 case nir_tex_src_ddy
:
4583 ddy
= get_src(ctx
, instr
->src
[i
].src
);
4585 case nir_tex_src_texture_offset
:
4586 case nir_tex_src_sampler_offset
:
4587 case nir_tex_src_plane
:
4593 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
4594 result
= get_buffer_size(ctx
, res_ptr
, true);
4598 if (instr
->op
== nir_texop_texture_samples
) {
4599 LLVMValueRef res
, samples
, is_msaa
;
4600 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->ac
.v8i32
, "");
4601 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
4602 LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
4603 is_msaa
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4604 LLVMConstInt(ctx
->ac
.i32
, 28, false), "");
4605 is_msaa
= LLVMBuildAnd(ctx
->ac
.builder
, is_msaa
,
4606 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4607 is_msaa
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, is_msaa
,
4608 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4610 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4611 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
4612 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
4613 LLVMConstInt(ctx
->ac
.i32
, 0xf, false), "");
4614 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->ac
.i32_1
,
4616 samples
= LLVMBuildSelect(ctx
->ac
.builder
, is_msaa
, samples
,
4623 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4624 coords
[chan
] = llvm_extract_elem(&ctx
->ac
, coord
, chan
);
4626 if (offsets
&& instr
->op
!= nir_texop_txf
) {
4627 LLVMValueRef offset
[3], pack
;
4628 for (chan
= 0; chan
< 3; ++chan
)
4629 offset
[chan
] = ctx
->ac
.i32_0
;
4632 for (chan
= 0; chan
< get_llvm_num_components(offsets
); chan
++) {
4633 offset
[chan
] = llvm_extract_elem(&ctx
->ac
, offsets
, chan
);
4634 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
4635 LLVMConstInt(ctx
->ac
.i32
, 0x3f, false), "");
4637 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
4638 LLVMConstInt(ctx
->ac
.i32
, chan
* 8, false), "");
4640 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
4641 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
4642 address
[count
++] = pack
;
4645 /* pack LOD bias value */
4646 if (instr
->op
== nir_texop_txb
&& bias
) {
4647 address
[count
++] = bias
;
4650 /* Pack depth comparison value */
4651 if (instr
->is_shadow
&& comparator
) {
4652 LLVMValueRef z
= ac_to_float(&ctx
->ac
,
4653 llvm_extract_elem(&ctx
->ac
, comparator
, 0));
4655 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4656 * so the depth comparison value isn't clamped for Z16 and
4657 * Z24 anymore. Do it manually here.
4659 * It's unnecessary if the original texture format was
4660 * Z32_FLOAT, but we don't know that here.
4662 if (ctx
->ac
.chip_class
== VI
)
4663 z
= ac_build_clamp(&ctx
->ac
, z
);
4665 address
[count
++] = z
;
4668 /* pack derivatives */
4670 int num_src_deriv_channels
, num_dest_deriv_channels
;
4671 switch (instr
->sampler_dim
) {
4672 case GLSL_SAMPLER_DIM_3D
:
4673 case GLSL_SAMPLER_DIM_CUBE
:
4675 num_src_deriv_channels
= 3;
4676 num_dest_deriv_channels
= 3;
4678 case GLSL_SAMPLER_DIM_2D
:
4680 num_src_deriv_channels
= 2;
4681 num_dest_deriv_channels
= 2;
4684 case GLSL_SAMPLER_DIM_1D
:
4685 num_src_deriv_channels
= 1;
4686 if (ctx
->ac
.chip_class
>= GFX9
) {
4687 num_dest_deriv_channels
= 2;
4690 num_dest_deriv_channels
= 1;
4696 for (unsigned i
= 0; i
< num_src_deriv_channels
; i
++) {
4697 derivs
[i
] = ac_to_float(&ctx
->ac
, llvm_extract_elem(&ctx
->ac
, ddx
, i
));
4698 derivs
[num_dest_deriv_channels
+ i
] = ac_to_float(&ctx
->ac
, llvm_extract_elem(&ctx
->ac
, ddy
, i
));
4700 for (unsigned i
= num_src_deriv_channels
; i
< num_dest_deriv_channels
; i
++) {
4701 derivs
[i
] = ctx
->ac
.f32_0
;
4702 derivs
[num_dest_deriv_channels
+ i
] = ctx
->ac
.f32_0
;
4706 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& coord
) {
4707 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4708 coords
[chan
] = ac_to_float(&ctx
->ac
, coords
[chan
]);
4709 if (instr
->coord_components
== 3)
4710 coords
[3] = LLVMGetUndef(ctx
->ac
.f32
);
4711 ac_prepare_cube_coords(&ctx
->ac
,
4712 instr
->op
== nir_texop_txd
, instr
->is_array
,
4713 instr
->op
== nir_texop_lod
, coords
, derivs
);
4719 for (unsigned i
= 0; i
< num_deriv_comp
* 2; i
++)
4720 address
[count
++] = derivs
[i
];
4723 /* Pack texture coordinates */
4725 address
[count
++] = coords
[0];
4726 if (instr
->coord_components
> 1) {
4727 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& instr
->is_array
&& instr
->op
!= nir_texop_txf
) {
4728 coords
[1] = apply_round_slice(&ctx
->ac
, coords
[1]);
4730 address
[count
++] = coords
[1];
4732 if (instr
->coord_components
> 2) {
4733 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4734 if (instr
->sampler_dim
!= GLSL_SAMPLER_DIM_3D
&&
4735 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_CUBE
&&
4736 instr
->op
!= nir_texop_txf
) {
4737 coords
[2] = apply_round_slice(&ctx
->ac
, coords
[2]);
4739 address
[count
++] = coords
[2];
4742 if (ctx
->ac
.chip_class
>= GFX9
) {
4743 LLVMValueRef filler
;
4744 if (instr
->op
== nir_texop_txf
)
4745 filler
= ctx
->ac
.i32_0
;
4747 filler
= LLVMConstReal(ctx
->ac
.f32
, 0.5);
4749 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
) {
4750 /* No nir_texop_lod, because it does not take a slice
4751 * even with array textures. */
4752 if (instr
->is_array
&& instr
->op
!= nir_texop_lod
) {
4753 address
[count
] = address
[count
- 1];
4754 address
[count
- 1] = filler
;
4757 address
[count
++] = filler
;
4763 if (lod
&& ((instr
->op
== nir_texop_txl
&& !lod_is_zero
) ||
4764 instr
->op
== nir_texop_txf
)) {
4765 address
[count
++] = lod
;
4766 } else if (instr
->op
== nir_texop_txf_ms
&& sample_index
) {
4767 address
[count
++] = sample_index
;
4768 } else if(instr
->op
== nir_texop_txs
) {
4771 address
[count
++] = lod
;
4773 address
[count
++] = ctx
->ac
.i32_0
;
4776 for (chan
= 0; chan
< count
; chan
++) {
4777 address
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
,
4778 address
[chan
], ctx
->ac
.i32
, "");
4781 if (instr
->op
== nir_texop_samples_identical
) {
4782 LLVMValueRef txf_address
[4];
4783 struct ac_image_args txf_args
= { 0 };
4784 unsigned txf_count
= count
;
4785 memcpy(txf_address
, address
, sizeof(txf_address
));
4787 if (!instr
->is_array
)
4788 txf_address
[2] = ctx
->ac
.i32_0
;
4789 txf_address
[3] = ctx
->ac
.i32_0
;
4791 set_tex_fetch_args(&ctx
->ac
, &txf_args
, instr
, nir_texop_txf
,
4793 txf_address
, txf_count
, 0xf);
4795 result
= build_tex_intrinsic(ctx
, instr
, false, &txf_args
);
4797 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
4798 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, result
, ctx
->ac
.i32_0
);
4802 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
&&
4803 instr
->op
!= nir_texop_txs
) {
4804 unsigned sample_chan
= instr
->is_array
? 3 : 2;
4805 address
[sample_chan
] = adjust_sample_index_using_fmask(&ctx
->ac
,
4808 instr
->is_array
? address
[2] : NULL
,
4809 address
[sample_chan
],
4813 if (offsets
&& instr
->op
== nir_texop_txf
) {
4814 nir_const_value
*const_offset
=
4815 nir_src_as_const_value(instr
->src
[const_src
].src
);
4816 int num_offsets
= instr
->src
[const_src
].src
.ssa
->num_components
;
4817 assert(const_offset
);
4818 num_offsets
= MIN2(num_offsets
, instr
->coord_components
);
4819 if (num_offsets
> 2)
4820 address
[2] = LLVMBuildAdd(ctx
->ac
.builder
,
4821 address
[2], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[2], false), "");
4822 if (num_offsets
> 1)
4823 address
[1] = LLVMBuildAdd(ctx
->ac
.builder
,
4824 address
[1], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[1], false), "");
4825 address
[0] = LLVMBuildAdd(ctx
->ac
.builder
,
4826 address
[0], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[0], false), "");
4830 /* TODO TG4 support */
4831 if (instr
->op
== nir_texop_tg4
) {
4832 if (instr
->is_shadow
)
4835 dmask
= 1 << instr
->component
;
4837 set_tex_fetch_args(&ctx
->ac
, &args
, instr
, instr
->op
,
4838 res_ptr
, samp_ptr
, address
, count
, dmask
);
4840 result
= build_tex_intrinsic(ctx
, instr
, lod_is_zero
, &args
);
4842 if (instr
->op
== nir_texop_query_levels
)
4843 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
4844 else if (instr
->is_shadow
&& instr
->is_new_style_shadow
&&
4845 instr
->op
!= nir_texop_txs
&& instr
->op
!= nir_texop_lod
&&
4846 instr
->op
!= nir_texop_tg4
)
4847 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
4848 else if (instr
->op
== nir_texop_txs
&&
4849 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
4851 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
4852 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
4853 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
4854 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
4855 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, z
, two
, "");
4856 } else if (ctx
->ac
.chip_class
>= GFX9
&&
4857 instr
->op
== nir_texop_txs
&&
4858 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
4860 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
4861 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
4862 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, layers
,
4864 } else if (instr
->dest
.ssa
.num_components
!= 4)
4865 result
= trim_vector(&ctx
->ac
, result
, instr
->dest
.ssa
.num_components
);
4869 assert(instr
->dest
.is_ssa
);
4870 result
= ac_to_integer(&ctx
->ac
, result
);
4871 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4876 static void visit_phi(struct ac_nir_context
*ctx
, nir_phi_instr
*instr
)
4878 LLVMTypeRef type
= get_def_type(ctx
, &instr
->dest
.ssa
);
4879 LLVMValueRef result
= LLVMBuildPhi(ctx
->ac
.builder
, type
, "");
4881 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4882 _mesa_hash_table_insert(ctx
->phis
, instr
, result
);
4885 static void visit_post_phi(struct ac_nir_context
*ctx
,
4886 nir_phi_instr
*instr
,
4887 LLVMValueRef llvm_phi
)
4889 nir_foreach_phi_src(src
, instr
) {
4890 LLVMBasicBlockRef block
= get_block(ctx
, src
->pred
);
4891 LLVMValueRef llvm_src
= get_src(ctx
, src
->src
);
4893 LLVMAddIncoming(llvm_phi
, &llvm_src
, &block
, 1);
4897 static void phi_post_pass(struct ac_nir_context
*ctx
)
4899 struct hash_entry
*entry
;
4900 hash_table_foreach(ctx
->phis
, entry
) {
4901 visit_post_phi(ctx
, (nir_phi_instr
*)entry
->key
,
4902 (LLVMValueRef
)entry
->data
);
4907 static void visit_ssa_undef(struct ac_nir_context
*ctx
,
4908 const nir_ssa_undef_instr
*instr
)
4910 unsigned num_components
= instr
->def
.num_components
;
4913 if (num_components
== 1)
4914 undef
= LLVMGetUndef(ctx
->ac
.i32
);
4916 undef
= LLVMGetUndef(LLVMVectorType(ctx
->ac
.i32
, num_components
));
4918 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, undef
);
4921 static void visit_jump(struct ac_nir_context
*ctx
,
4922 const nir_jump_instr
*instr
)
4924 switch (instr
->type
) {
4925 case nir_jump_break
:
4926 LLVMBuildBr(ctx
->ac
.builder
, ctx
->break_block
);
4927 LLVMClearInsertionPosition(ctx
->ac
.builder
);
4929 case nir_jump_continue
:
4930 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
4931 LLVMClearInsertionPosition(ctx
->ac
.builder
);
4934 fprintf(stderr
, "Unknown NIR jump instr: ");
4935 nir_print_instr(&instr
->instr
, stderr
);
4936 fprintf(stderr
, "\n");
4941 static void visit_cf_list(struct ac_nir_context
*ctx
,
4942 struct exec_list
*list
);
4944 static void visit_block(struct ac_nir_context
*ctx
, nir_block
*block
)
4946 LLVMBasicBlockRef llvm_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
4947 nir_foreach_instr(instr
, block
)
4949 switch (instr
->type
) {
4950 case nir_instr_type_alu
:
4951 visit_alu(ctx
, nir_instr_as_alu(instr
));
4953 case nir_instr_type_load_const
:
4954 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
4956 case nir_instr_type_intrinsic
:
4957 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
4959 case nir_instr_type_tex
:
4960 visit_tex(ctx
, nir_instr_as_tex(instr
));
4962 case nir_instr_type_phi
:
4963 visit_phi(ctx
, nir_instr_as_phi(instr
));
4965 case nir_instr_type_ssa_undef
:
4966 visit_ssa_undef(ctx
, nir_instr_as_ssa_undef(instr
));
4968 case nir_instr_type_jump
:
4969 visit_jump(ctx
, nir_instr_as_jump(instr
));
4972 fprintf(stderr
, "Unknown NIR instr type: ");
4973 nir_print_instr(instr
, stderr
);
4974 fprintf(stderr
, "\n");
4979 _mesa_hash_table_insert(ctx
->defs
, block
, llvm_block
);
4982 static void visit_if(struct ac_nir_context
*ctx
, nir_if
*if_stmt
)
4984 LLVMValueRef value
= get_src(ctx
, if_stmt
->condition
);
4986 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
4987 LLVMBasicBlockRef merge_block
=
4988 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
4989 LLVMBasicBlockRef if_block
=
4990 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
4991 LLVMBasicBlockRef else_block
= merge_block
;
4992 if (!exec_list_is_empty(&if_stmt
->else_list
))
4993 else_block
= LLVMAppendBasicBlockInContext(
4994 ctx
->ac
.context
, fn
, "");
4996 LLVMValueRef cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
, value
,
4997 LLVMConstInt(ctx
->ac
.i32
, 0, false), "");
4998 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, if_block
, else_block
);
5000 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, if_block
);
5001 visit_cf_list(ctx
, &if_stmt
->then_list
);
5002 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5003 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
5005 if (!exec_list_is_empty(&if_stmt
->else_list
)) {
5006 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, else_block
);
5007 visit_cf_list(ctx
, &if_stmt
->else_list
);
5008 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5009 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
5012 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
5015 static void visit_loop(struct ac_nir_context
*ctx
, nir_loop
*loop
)
5017 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
5018 LLVMBasicBlockRef continue_parent
= ctx
->continue_block
;
5019 LLVMBasicBlockRef break_parent
= ctx
->break_block
;
5021 ctx
->continue_block
=
5022 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5024 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5026 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5027 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->continue_block
);
5028 visit_cf_list(ctx
, &loop
->body
);
5030 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5031 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5032 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->break_block
);
5034 ctx
->continue_block
= continue_parent
;
5035 ctx
->break_block
= break_parent
;
5038 static void visit_cf_list(struct ac_nir_context
*ctx
,
5039 struct exec_list
*list
)
5041 foreach_list_typed(nir_cf_node
, node
, node
, list
)
5043 switch (node
->type
) {
5044 case nir_cf_node_block
:
5045 visit_block(ctx
, nir_cf_node_as_block(node
));
5048 case nir_cf_node_if
:
5049 visit_if(ctx
, nir_cf_node_as_if(node
));
5052 case nir_cf_node_loop
:
5053 visit_loop(ctx
, nir_cf_node_as_loop(node
));
5063 handle_vs_input_decl(struct nir_to_llvm_context
*ctx
,
5064 struct nir_variable
*variable
)
5066 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
5067 LLVMValueRef t_offset
;
5068 LLVMValueRef t_list
;
5070 LLVMValueRef buffer_index
;
5071 int index
= variable
->data
.location
- VERT_ATTRIB_GENERIC0
;
5072 int idx
= variable
->data
.location
;
5073 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
5075 variable
->data
.driver_location
= idx
* 4;
5077 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << index
)) {
5078 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.instance_id
,
5079 ctx
->abi
.start_instance
, "");
5080 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(3,
5081 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5083 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.vertex_id
,
5084 ctx
->abi
.base_vertex
, "");
5086 for (unsigned i
= 0; i
< attrib_count
; ++i
, ++idx
) {
5087 t_offset
= LLVMConstInt(ctx
->i32
, index
+ i
, false);
5089 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
5091 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
5093 LLVMConstInt(ctx
->i32
, 0, false),
5096 for (unsigned chan
= 0; chan
< 4; chan
++) {
5097 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->i32
, chan
, false);
5098 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
, chan
)] =
5099 ac_to_integer(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
,
5100 input
, llvm_chan
, ""));
5105 static void interp_fs_input(struct nir_to_llvm_context
*ctx
,
5107 LLVMValueRef interp_param
,
5108 LLVMValueRef prim_mask
,
5109 LLVMValueRef result
[4])
5111 LLVMValueRef attr_number
;
5114 bool interp
= interp_param
!= NULL
;
5116 attr_number
= LLVMConstInt(ctx
->i32
, attr
, false);
5118 /* fs.constant returns the param from the middle vertex, so it's not
5119 * really useful for flat shading. It's meant to be used for custom
5120 * interpolation (but the intrinsic can't fetch from the other two
5123 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5124 * to do the right thing. The only reason we use fs.constant is that
5125 * fs.interp cannot be used on integers, because they can be equal
5129 interp_param
= LLVMBuildBitCast(ctx
->builder
, interp_param
,
5130 LLVMVectorType(ctx
->f32
, 2), "");
5132 i
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
5134 j
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
5138 for (chan
= 0; chan
< 4; chan
++) {
5139 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->i32
, chan
, false);
5142 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
5147 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
5148 LLVMConstInt(ctx
->i32
, 2, false),
5157 handle_fs_input_decl(struct nir_to_llvm_context
*ctx
,
5158 struct nir_variable
*variable
)
5160 int idx
= variable
->data
.location
;
5161 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5162 LLVMValueRef interp
;
5164 variable
->data
.driver_location
= idx
* 4;
5165 ctx
->input_mask
|= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
5167 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
5168 unsigned interp_type
;
5169 if (variable
->data
.sample
) {
5170 interp_type
= INTERP_SAMPLE
;
5171 ctx
->shader_info
->info
.ps
.force_persample
= true;
5172 } else if (variable
->data
.centroid
)
5173 interp_type
= INTERP_CENTROID
;
5175 interp_type
= INTERP_CENTER
;
5177 interp
= lookup_interp_param(ctx
, variable
->data
.interpolation
, interp_type
);
5181 for (unsigned i
= 0; i
< attrib_count
; ++i
)
5182 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
5187 handle_vs_inputs(struct nir_to_llvm_context
*ctx
,
5188 struct nir_shader
*nir
) {
5189 nir_foreach_variable(variable
, &nir
->inputs
)
5190 handle_vs_input_decl(ctx
, variable
);
5194 prepare_interp_optimize(struct nir_to_llvm_context
*ctx
,
5195 struct nir_shader
*nir
)
5197 if (!ctx
->options
->key
.fs
.multisample
)
5200 bool uses_center
= false;
5201 bool uses_centroid
= false;
5202 nir_foreach_variable(variable
, &nir
->inputs
) {
5203 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
5204 variable
->data
.sample
)
5207 if (variable
->data
.centroid
)
5208 uses_centroid
= true;
5213 if (uses_center
&& uses_centroid
) {
5214 LLVMValueRef sel
= LLVMBuildICmp(ctx
->builder
, LLVMIntSLT
, ctx
->prim_mask
, ctx
->ac
.i32_0
, "");
5215 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
5216 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
5221 handle_fs_inputs(struct nir_to_llvm_context
*ctx
,
5222 struct nir_shader
*nir
)
5224 prepare_interp_optimize(ctx
, nir
);
5226 nir_foreach_variable(variable
, &nir
->inputs
)
5227 handle_fs_input_decl(ctx
, variable
);
5231 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
5232 ctx
->shader_info
->info
.needs_multiview_view_index
)
5233 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
5235 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
5236 LLVMValueRef interp_param
;
5237 LLVMValueRef
*inputs
= ctx
->inputs
+radeon_llvm_reg_index_soa(i
, 0);
5239 if (!(ctx
->input_mask
& (1ull << i
)))
5242 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
5243 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
5244 interp_param
= *inputs
;
5245 interp_fs_input(ctx
, index
, interp_param
, ctx
->prim_mask
,
5249 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
5251 } else if (i
== VARYING_SLOT_POS
) {
5252 for(int i
= 0; i
< 3; ++i
)
5253 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
5255 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->f32one
,
5256 ctx
->abi
.frag_pos
[3]);
5259 ctx
->shader_info
->fs
.num_interp
= index
;
5260 if (ctx
->input_mask
& (1 << VARYING_SLOT_PNTC
))
5261 ctx
->shader_info
->fs
.has_pcoord
= true;
5262 if (ctx
->input_mask
& (1 << VARYING_SLOT_PRIMITIVE_ID
))
5263 ctx
->shader_info
->fs
.prim_id_input
= true;
5264 if (ctx
->input_mask
& (1 << VARYING_SLOT_LAYER
))
5265 ctx
->shader_info
->fs
.layer_input
= true;
5266 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
5268 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
5269 ctx
->view_index
= ctx
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5273 ac_build_alloca(struct ac_llvm_context
*ac
,
5277 LLVMBuilderRef builder
= ac
->builder
;
5278 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(builder
);
5279 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
5280 LLVMBasicBlockRef first_block
= LLVMGetEntryBasicBlock(function
);
5281 LLVMValueRef first_instr
= LLVMGetFirstInstruction(first_block
);
5282 LLVMBuilderRef first_builder
= LLVMCreateBuilderInContext(ac
->context
);
5286 LLVMPositionBuilderBefore(first_builder
, first_instr
);
5288 LLVMPositionBuilderAtEnd(first_builder
, first_block
);
5291 res
= LLVMBuildAlloca(first_builder
, type
, name
);
5292 LLVMBuildStore(builder
, LLVMConstNull(type
), res
);
5294 LLVMDisposeBuilder(first_builder
);
5299 static LLVMValueRef
si_build_alloca_undef(struct ac_llvm_context
*ac
,
5303 LLVMValueRef ptr
= ac_build_alloca(ac
, type
, name
);
5304 LLVMBuildStore(ac
->builder
, LLVMGetUndef(type
), ptr
);
5309 scan_shader_output_decl(struct nir_to_llvm_context
*ctx
,
5310 struct nir_variable
*variable
,
5311 struct nir_shader
*shader
,
5312 gl_shader_stage stage
)
5314 int idx
= variable
->data
.location
+ variable
->data
.index
;
5315 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5316 uint64_t mask_attribs
;
5318 variable
->data
.driver_location
= idx
* 4;
5320 /* tess ctrl has it's own load/store paths for outputs */
5321 if (stage
== MESA_SHADER_TESS_CTRL
)
5324 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
5325 if (stage
== MESA_SHADER_VERTEX
||
5326 stage
== MESA_SHADER_TESS_EVAL
||
5327 stage
== MESA_SHADER_GEOMETRY
) {
5328 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5329 int length
= shader
->info
.clip_distance_array_size
+
5330 shader
->info
.cull_distance_array_size
;
5331 if (stage
== MESA_SHADER_VERTEX
) {
5332 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5333 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5335 if (stage
== MESA_SHADER_TESS_EVAL
) {
5336 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5337 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5344 mask_attribs
= 1ull << idx
;
5348 ctx
->output_mask
|= mask_attribs
;
5352 handle_shader_output_decl(struct ac_nir_context
*ctx
,
5353 struct nir_shader
*nir
,
5354 struct nir_variable
*variable
)
5356 unsigned output_loc
= variable
->data
.driver_location
/ 4;
5357 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5359 /* tess ctrl has it's own load/store paths for outputs */
5360 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
5363 if (ctx
->stage
== MESA_SHADER_VERTEX
||
5364 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
5365 ctx
->stage
== MESA_SHADER_GEOMETRY
) {
5366 int idx
= variable
->data
.location
+ variable
->data
.index
;
5367 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5368 int length
= nir
->info
.clip_distance_array_size
+
5369 nir
->info
.cull_distance_array_size
;
5378 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
5379 for (unsigned chan
= 0; chan
< 4; chan
++) {
5380 ctx
->outputs
[radeon_llvm_reg_index_soa(output_loc
+ i
, chan
)] =
5381 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5387 glsl_base_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5388 enum glsl_base_type type
)
5392 case GLSL_TYPE_UINT
:
5393 case GLSL_TYPE_BOOL
:
5394 case GLSL_TYPE_SUBROUTINE
:
5396 case GLSL_TYPE_FLOAT
: /* TODO handle mediump */
5398 case GLSL_TYPE_INT64
:
5399 case GLSL_TYPE_UINT64
:
5401 case GLSL_TYPE_DOUBLE
:
5404 unreachable("unknown GLSL type");
5409 glsl_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5410 const struct glsl_type
*type
)
5412 if (glsl_type_is_scalar(type
)) {
5413 return glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
));
5416 if (glsl_type_is_vector(type
)) {
5417 return LLVMVectorType(
5418 glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
)),
5419 glsl_get_vector_elements(type
));
5422 if (glsl_type_is_matrix(type
)) {
5423 return LLVMArrayType(
5424 glsl_to_llvm_type(ctx
, glsl_get_column_type(type
)),
5425 glsl_get_matrix_columns(type
));
5428 if (glsl_type_is_array(type
)) {
5429 return LLVMArrayType(
5430 glsl_to_llvm_type(ctx
, glsl_get_array_element(type
)),
5431 glsl_get_length(type
));
5434 assert(glsl_type_is_struct(type
));
5436 LLVMTypeRef member_types
[glsl_get_length(type
)];
5438 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
5440 glsl_to_llvm_type(ctx
,
5441 glsl_get_struct_field(type
, i
));
5444 return LLVMStructTypeInContext(ctx
->context
, member_types
,
5445 glsl_get_length(type
), false);
5449 setup_locals(struct ac_nir_context
*ctx
,
5450 struct nir_function
*func
)
5453 ctx
->num_locals
= 0;
5454 nir_foreach_variable(variable
, &func
->impl
->locals
) {
5455 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5456 variable
->data
.driver_location
= ctx
->num_locals
* 4;
5457 ctx
->num_locals
+= attrib_count
;
5459 ctx
->locals
= malloc(4 * ctx
->num_locals
* sizeof(LLVMValueRef
));
5463 for (i
= 0; i
< ctx
->num_locals
; i
++) {
5464 for (j
= 0; j
< 4; j
++) {
5465 ctx
->locals
[i
* 4 + j
] =
5466 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "temp");
5472 setup_shared(struct ac_nir_context
*ctx
,
5473 struct nir_shader
*nir
)
5475 nir_foreach_variable(variable
, &nir
->shared
) {
5476 LLVMValueRef shared
=
5477 LLVMAddGlobalInAddressSpace(
5478 ctx
->ac
.module
, glsl_to_llvm_type(ctx
->nctx
, variable
->type
),
5479 variable
->name
? variable
->name
: "",
5481 _mesa_hash_table_insert(ctx
->vars
, variable
, shared
);
5486 emit_float_saturate(struct ac_llvm_context
*ctx
, LLVMValueRef v
, float lo
, float hi
)
5488 v
= ac_to_float(ctx
, v
);
5489 v
= emit_intrin_2f_param(ctx
, "llvm.maxnum", ctx
->f32
, v
, LLVMConstReal(ctx
->f32
, lo
));
5490 return emit_intrin_2f_param(ctx
, "llvm.minnum", ctx
->f32
, v
, LLVMConstReal(ctx
->f32
, hi
));
5494 static LLVMValueRef
emit_pack_int16(struct nir_to_llvm_context
*ctx
,
5495 LLVMValueRef src0
, LLVMValueRef src1
)
5497 LLVMValueRef const16
= LLVMConstInt(ctx
->i32
, 16, false);
5498 LLVMValueRef comp
[2];
5500 comp
[0] = LLVMBuildAnd(ctx
->builder
, src0
, LLVMConstInt(ctx
-> i32
, 65535, 0), "");
5501 comp
[1] = LLVMBuildAnd(ctx
->builder
, src1
, LLVMConstInt(ctx
-> i32
, 65535, 0), "");
5502 comp
[1] = LLVMBuildShl(ctx
->builder
, comp
[1], const16
, "");
5503 return LLVMBuildOr(ctx
->builder
, comp
[0], comp
[1], "");
5506 /* Initialize arguments for the shader export intrinsic */
5508 si_llvm_init_export_args(struct nir_to_llvm_context
*ctx
,
5509 LLVMValueRef
*values
,
5511 struct ac_export_args
*args
)
5513 /* Default is 0xf. Adjusted below depending on the format. */
5514 args
->enabled_channels
= 0xf;
5516 /* Specify whether the EXEC mask represents the valid mask */
5517 args
->valid_mask
= 0;
5519 /* Specify whether this is the last export */
5522 /* Specify the target we are exporting */
5523 args
->target
= target
;
5525 args
->compr
= false;
5526 args
->out
[0] = LLVMGetUndef(ctx
->f32
);
5527 args
->out
[1] = LLVMGetUndef(ctx
->f32
);
5528 args
->out
[2] = LLVMGetUndef(ctx
->f32
);
5529 args
->out
[3] = LLVMGetUndef(ctx
->f32
);
5534 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& target
>= V_008DFC_SQ_EXP_MRT
) {
5535 LLVMValueRef val
[4];
5536 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
5537 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
5538 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
5539 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
5541 switch(col_format
) {
5542 case V_028714_SPI_SHADER_ZERO
:
5543 args
->enabled_channels
= 0; /* writemask */
5544 args
->target
= V_008DFC_SQ_EXP_NULL
;
5547 case V_028714_SPI_SHADER_32_R
:
5548 args
->enabled_channels
= 1;
5549 args
->out
[0] = values
[0];
5552 case V_028714_SPI_SHADER_32_GR
:
5553 args
->enabled_channels
= 0x3;
5554 args
->out
[0] = values
[0];
5555 args
->out
[1] = values
[1];
5558 case V_028714_SPI_SHADER_32_AR
:
5559 args
->enabled_channels
= 0x9;
5560 args
->out
[0] = values
[0];
5561 args
->out
[3] = values
[3];
5564 case V_028714_SPI_SHADER_FP16_ABGR
:
5567 for (unsigned chan
= 0; chan
< 2; chan
++) {
5568 LLVMValueRef pack_args
[2] = {
5570 values
[2 * chan
+ 1]
5572 LLVMValueRef packed
;
5574 packed
= ac_build_cvt_pkrtz_f16(&ctx
->ac
, pack_args
);
5575 args
->out
[chan
] = packed
;
5579 case V_028714_SPI_SHADER_UNORM16_ABGR
:
5580 for (unsigned chan
= 0; chan
< 4; chan
++) {
5581 val
[chan
] = ac_build_clamp(&ctx
->ac
, values
[chan
]);
5582 val
[chan
] = LLVMBuildFMul(ctx
->builder
, val
[chan
],
5583 LLVMConstReal(ctx
->f32
, 65535), "");
5584 val
[chan
] = LLVMBuildFAdd(ctx
->builder
, val
[chan
],
5585 LLVMConstReal(ctx
->f32
, 0.5), "");
5586 val
[chan
] = LLVMBuildFPToUI(ctx
->builder
, val
[chan
],
5591 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5592 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5595 case V_028714_SPI_SHADER_SNORM16_ABGR
:
5596 for (unsigned chan
= 0; chan
< 4; chan
++) {
5597 val
[chan
] = emit_float_saturate(&ctx
->ac
, values
[chan
], -1, 1);
5598 val
[chan
] = LLVMBuildFMul(ctx
->builder
, val
[chan
],
5599 LLVMConstReal(ctx
->f32
, 32767), "");
5601 /* If positive, add 0.5, else add -0.5. */
5602 val
[chan
] = LLVMBuildFAdd(ctx
->builder
, val
[chan
],
5603 LLVMBuildSelect(ctx
->builder
,
5604 LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
,
5605 val
[chan
], ctx
->f32zero
, ""),
5606 LLVMConstReal(ctx
->f32
, 0.5),
5607 LLVMConstReal(ctx
->f32
, -0.5), ""), "");
5608 val
[chan
] = LLVMBuildFPToSI(ctx
->builder
, val
[chan
], ctx
->i32
, "");
5612 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5613 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5616 case V_028714_SPI_SHADER_UINT16_ABGR
: {
5617 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->i32
,
5618 is_int8
? 255 : is_int10
? 1023 : 65535, 0);
5619 LLVMValueRef max_alpha
= !is_int10
? max_rgb
: LLVMConstInt(ctx
->i32
, 3, 0);
5621 for (unsigned chan
= 0; chan
< 4; chan
++) {
5622 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
5623 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntULT
, val
[chan
], chan
== 3 ? max_alpha
: max_rgb
);
5627 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5628 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5632 case V_028714_SPI_SHADER_SINT16_ABGR
: {
5633 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->i32
,
5634 is_int8
? 127 : is_int10
? 511 : 32767, 0);
5635 LLVMValueRef min_rgb
= LLVMConstInt(ctx
->i32
,
5636 is_int8
? -128 : is_int10
? -512 : -32768, 0);
5637 LLVMValueRef max_alpha
= !is_int10
? max_rgb
: ctx
->i32one
;
5638 LLVMValueRef min_alpha
= !is_int10
? min_rgb
: LLVMConstInt(ctx
->i32
, -2, 0);
5641 for (unsigned chan
= 0; chan
< 4; chan
++) {
5642 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
5643 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, val
[chan
], chan
== 3 ? max_alpha
: max_rgb
);
5644 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, val
[chan
], chan
== 3 ? min_alpha
: min_rgb
);
5648 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5649 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5654 case V_028714_SPI_SHADER_32_ABGR
:
5655 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5659 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5661 for (unsigned i
= 0; i
< 4; ++i
)
5662 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
5666 handle_vs_outputs_post(struct nir_to_llvm_context
*ctx
,
5667 bool export_prim_id
,
5668 struct ac_vs_output_info
*outinfo
)
5670 uint32_t param_count
= 0;
5672 unsigned pos_idx
, num_pos_exports
= 0;
5673 struct ac_export_args args
, pos_args
[4] = {};
5674 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
5677 if (ctx
->options
->key
.has_multiview_view_index
) {
5678 LLVMValueRef
* tmp_out
= &ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5680 for(unsigned i
= 0; i
< 4; ++i
)
5681 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
5682 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5685 LLVMBuildStore(ctx
->builder
, ac_to_float(&ctx
->ac
, ctx
->view_index
), *tmp_out
);
5686 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
5689 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
5690 sizeof(outinfo
->vs_output_param_offset
));
5692 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
5693 LLVMValueRef slots
[8];
5696 if (outinfo
->cull_dist_mask
)
5697 outinfo
->cull_dist_mask
<<= ctx
->num_output_clips
;
5699 i
= VARYING_SLOT_CLIP_DIST0
;
5700 for (j
= 0; j
< ctx
->num_output_clips
+ ctx
->num_output_culls
; j
++)
5701 slots
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5702 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
5704 for (i
= ctx
->num_output_clips
+ ctx
->num_output_culls
; i
< 8; i
++)
5705 slots
[i
] = LLVMGetUndef(ctx
->f32
);
5707 if (ctx
->num_output_clips
+ ctx
->num_output_culls
> 4) {
5708 target
= V_008DFC_SQ_EXP_POS
+ 3;
5709 si_llvm_init_export_args(ctx
, &slots
[4], target
, &args
);
5710 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5711 &args
, sizeof(args
));
5714 target
= V_008DFC_SQ_EXP_POS
+ 2;
5715 si_llvm_init_export_args(ctx
, &slots
[0], target
, &args
);
5716 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5717 &args
, sizeof(args
));
5721 LLVMValueRef pos_values
[4] = {ctx
->f32zero
, ctx
->f32zero
, ctx
->f32zero
, ctx
->f32one
};
5722 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
5723 for (unsigned j
= 0; j
< 4; j
++)
5724 pos_values
[j
] = LLVMBuildLoad(ctx
->builder
,
5725 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_POS
, j
)], "");
5727 si_llvm_init_export_args(ctx
, pos_values
, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
5729 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
5730 outinfo
->writes_pointsize
= true;
5731 psize_value
= LLVMBuildLoad(ctx
->builder
,
5732 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ
, 0)], "");
5735 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
5736 outinfo
->writes_layer
= true;
5737 layer_value
= LLVMBuildLoad(ctx
->builder
,
5738 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)], "");
5741 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
5742 outinfo
->writes_viewport_index
= true;
5743 viewport_index_value
= LLVMBuildLoad(ctx
->builder
,
5744 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT
, 0)], "");
5747 if (outinfo
->writes_pointsize
||
5748 outinfo
->writes_layer
||
5749 outinfo
->writes_viewport_index
) {
5750 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
5751 (outinfo
->writes_layer
== true ? 4 : 0));
5752 pos_args
[1].valid_mask
= 0;
5753 pos_args
[1].done
= 0;
5754 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
5755 pos_args
[1].compr
= 0;
5756 pos_args
[1].out
[0] = ctx
->f32zero
; /* X */
5757 pos_args
[1].out
[1] = ctx
->f32zero
; /* Y */
5758 pos_args
[1].out
[2] = ctx
->f32zero
; /* Z */
5759 pos_args
[1].out
[3] = ctx
->f32zero
; /* W */
5761 if (outinfo
->writes_pointsize
== true)
5762 pos_args
[1].out
[0] = psize_value
;
5763 if (outinfo
->writes_layer
== true)
5764 pos_args
[1].out
[2] = layer_value
;
5765 if (outinfo
->writes_viewport_index
== true) {
5766 if (ctx
->options
->chip_class
>= GFX9
) {
5767 /* GFX9 has the layer in out.z[10:0] and the viewport
5768 * index in out.z[19:16].
5770 LLVMValueRef v
= viewport_index_value
;
5771 v
= ac_to_integer(&ctx
->ac
, v
);
5772 v
= LLVMBuildShl(ctx
->builder
, v
,
5773 LLVMConstInt(ctx
->i32
, 16, false),
5775 v
= LLVMBuildOr(ctx
->builder
, v
,
5776 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
5778 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
5779 pos_args
[1].enabled_channels
|= 1 << 2;
5781 pos_args
[1].out
[3] = viewport_index_value
;
5782 pos_args
[1].enabled_channels
|= 1 << 3;
5786 for (i
= 0; i
< 4; i
++) {
5787 if (pos_args
[i
].out
[0])
5792 for (i
= 0; i
< 4; i
++) {
5793 if (!pos_args
[i
].out
[0])
5796 /* Specify the target we are exporting */
5797 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
5798 if (pos_idx
== num_pos_exports
)
5799 pos_args
[i
].done
= 1;
5800 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
5803 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5804 LLVMValueRef values
[4];
5805 if (!(ctx
->output_mask
& (1ull << i
)))
5808 for (unsigned j
= 0; j
< 4; j
++)
5809 values
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5810 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
5812 if (i
== VARYING_SLOT_LAYER
) {
5813 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5814 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = param_count
;
5816 } else if (i
== VARYING_SLOT_PRIMITIVE_ID
) {
5817 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5818 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
5820 } else if (i
>= VARYING_SLOT_VAR0
) {
5821 outinfo
->export_mask
|= 1u << (i
- VARYING_SLOT_VAR0
);
5822 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5823 outinfo
->vs_output_param_offset
[i
] = param_count
;
5828 si_llvm_init_export_args(ctx
, values
, target
, &args
);
5830 if (target
>= V_008DFC_SQ_EXP_POS
&&
5831 target
<= (V_008DFC_SQ_EXP_POS
+ 3)) {
5832 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5833 &args
, sizeof(args
));
5835 ac_build_export(&ctx
->ac
, &args
);
5839 if (export_prim_id
) {
5840 LLVMValueRef values
[4];
5841 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5842 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
5845 values
[0] = ctx
->vs_prim_id
;
5846 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
5847 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5848 for (unsigned j
= 1; j
< 4; j
++)
5849 values
[j
] = ctx
->f32zero
;
5850 si_llvm_init_export_args(ctx
, values
, target
, &args
);
5851 ac_build_export(&ctx
->ac
, &args
);
5852 outinfo
->export_prim_id
= true;
5855 outinfo
->pos_exports
= num_pos_exports
;
5856 outinfo
->param_exports
= param_count
;
5860 handle_es_outputs_post(struct nir_to_llvm_context
*ctx
,
5861 struct ac_es_output_info
*outinfo
)
5864 uint64_t max_output_written
= 0;
5865 LLVMValueRef lds_base
= NULL
;
5867 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5871 if (!(ctx
->output_mask
& (1ull << i
)))
5874 if (i
== VARYING_SLOT_CLIP_DIST0
)
5875 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
5877 param_index
= shader_io_get_unique_index(i
);
5879 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
5882 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
5884 if (ctx
->ac
.chip_class
>= GFX9
) {
5885 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
5886 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
5887 LLVMValueRef wave_idx
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
5888 LLVMConstInt(ctx
->ac
.i32
, 24, false),
5889 LLVMConstInt(ctx
->ac
.i32
, 4, false), false);
5890 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
5891 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
5892 LLVMConstInt(ctx
->i32
, 64, false), ""), "");
5893 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
5894 LLVMConstInt(ctx
->i32
, itemsize_dw
, 0), "");
5897 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5898 LLVMValueRef dw_addr
;
5899 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
5903 if (!(ctx
->output_mask
& (1ull << i
)))
5906 if (i
== VARYING_SLOT_CLIP_DIST0
)
5907 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
5909 param_index
= shader_io_get_unique_index(i
);
5912 dw_addr
= LLVMBuildAdd(ctx
->builder
, lds_base
,
5913 LLVMConstInt(ctx
->i32
, param_index
* 4, false),
5916 for (j
= 0; j
< length
; j
++) {
5917 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], "");
5918 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->i32
, "");
5920 if (ctx
->ac
.chip_class
>= GFX9
) {
5921 lds_store(ctx
, dw_addr
,
5922 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
5923 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->i32one
, "");
5925 ac_build_buffer_store_dword(&ctx
->ac
,
5928 NULL
, ctx
->es2gs_offset
,
5929 (4 * param_index
+ j
) * 4,
5937 handle_ls_outputs_post(struct nir_to_llvm_context
*ctx
)
5939 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
5940 LLVMValueRef vertex_dw_stride
= unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 13, 8);
5941 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->builder
, vertex_id
,
5942 vertex_dw_stride
, "");
5944 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5945 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
5948 if (!(ctx
->output_mask
& (1ull << i
)))
5951 if (i
== VARYING_SLOT_CLIP_DIST0
)
5952 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
5953 int param
= shader_io_get_unique_index(i
);
5954 mark_tess_output(ctx
, false, param
);
5956 mark_tess_output(ctx
, false, param
+ 1);
5957 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->builder
, base_dw_addr
,
5958 LLVMConstInt(ctx
->i32
, param
* 4, false),
5960 for (unsigned j
= 0; j
< length
; j
++) {
5961 lds_store(ctx
, dw_addr
,
5962 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
5963 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->i32one
, "");
5968 struct ac_build_if_state
5970 struct nir_to_llvm_context
*ctx
;
5971 LLVMValueRef condition
;
5972 LLVMBasicBlockRef entry_block
;
5973 LLVMBasicBlockRef true_block
;
5974 LLVMBasicBlockRef false_block
;
5975 LLVMBasicBlockRef merge_block
;
5978 static LLVMBasicBlockRef
5979 ac_build_insert_new_block(struct nir_to_llvm_context
*ctx
, const char *name
)
5981 LLVMBasicBlockRef current_block
;
5982 LLVMBasicBlockRef next_block
;
5983 LLVMBasicBlockRef new_block
;
5985 /* get current basic block */
5986 current_block
= LLVMGetInsertBlock(ctx
->builder
);
5988 /* chqeck if there's another block after this one */
5989 next_block
= LLVMGetNextBasicBlock(current_block
);
5991 /* insert the new block before the next block */
5992 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
5995 /* append new block after current block */
5996 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
5997 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
6003 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
6004 struct nir_to_llvm_context
*ctx
,
6005 LLVMValueRef condition
)
6007 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->builder
);
6009 memset(ifthen
, 0, sizeof *ifthen
);
6011 ifthen
->condition
= condition
;
6012 ifthen
->entry_block
= block
;
6014 /* create endif/merge basic block for the phi functions */
6015 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
6017 /* create/insert true_block before merge_block */
6018 ifthen
->true_block
=
6019 LLVMInsertBasicBlockInContext(ctx
->context
,
6020 ifthen
->merge_block
,
6023 /* successive code goes into the true block */
6024 LLVMPositionBuilderAtEnd(ctx
->builder
, ifthen
->true_block
);
6028 * End a conditional.
6031 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
6033 LLVMBuilderRef builder
= ifthen
->ctx
->builder
;
6035 /* Insert branch to the merge block from current block */
6036 LLVMBuildBr(builder
, ifthen
->merge_block
);
6039 * Now patch in the various branch instructions.
6042 /* Insert the conditional branch instruction at the end of entry_block */
6043 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
6044 if (ifthen
->false_block
) {
6045 /* we have an else clause */
6046 LLVMBuildCondBr(builder
, ifthen
->condition
,
6047 ifthen
->true_block
, ifthen
->false_block
);
6050 /* no else clause */
6051 LLVMBuildCondBr(builder
, ifthen
->condition
,
6052 ifthen
->true_block
, ifthen
->merge_block
);
6055 /* Resume building code at end of the ifthen->merge_block */
6056 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
6060 write_tess_factors(struct nir_to_llvm_context
*ctx
)
6062 unsigned stride
, outer_comps
, inner_comps
;
6063 struct ac_build_if_state if_ctx
, inner_if_ctx
;
6064 LLVMValueRef invocation_id
= unpack_param(&ctx
->ac
, ctx
->tcs_rel_ids
, 8, 5);
6065 LLVMValueRef rel_patch_id
= unpack_param(&ctx
->ac
, ctx
->tcs_rel_ids
, 0, 8);
6066 unsigned tess_inner_index
, tess_outer_index
;
6067 LLVMValueRef lds_base
, lds_inner
, lds_outer
, byteoffset
, buffer
;
6068 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
6072 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
6092 ac_nir_build_if(&if_ctx
, ctx
,
6093 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
6094 invocation_id
, ctx
->i32zero
, ""));
6096 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6097 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6099 mark_tess_output(ctx
, true, tess_inner_index
);
6100 mark_tess_output(ctx
, true, tess_outer_index
);
6101 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
6102 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6103 LLVMConstInt(ctx
->i32
, tess_inner_index
* 4, false), "");
6104 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6105 LLVMConstInt(ctx
->i32
, tess_outer_index
* 4, false), "");
6107 for (i
= 0; i
< 4; i
++) {
6108 inner
[i
] = LLVMGetUndef(ctx
->i32
);
6109 outer
[i
] = LLVMGetUndef(ctx
->i32
);
6113 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
6114 outer
[0] = out
[1] = lds_load(ctx
, lds_outer
);
6115 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
6116 LLVMConstInt(ctx
->i32
, 1, false), "");
6117 outer
[1] = out
[0] = lds_load(ctx
, lds_outer
);
6119 for (i
= 0; i
< outer_comps
; i
++) {
6121 lds_load(ctx
, lds_outer
);
6122 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
6123 LLVMConstInt(ctx
->i32
, 1, false), "");
6125 for (i
= 0; i
< inner_comps
; i
++) {
6126 inner
[i
] = out
[outer_comps
+i
] =
6127 lds_load(ctx
, lds_inner
);
6128 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_inner
,
6129 LLVMConstInt(ctx
->i32
, 1, false), "");
6133 /* Convert the outputs to vectors for stores. */
6134 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
6138 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
6141 buffer
= ctx
->hs_ring_tess_factor
;
6142 tf_base
= ctx
->tess_factor_offset
;
6143 byteoffset
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
6144 LLVMConstInt(ctx
->i32
, 4 * stride
, false), "");
6145 unsigned tf_offset
= 0;
6147 if (ctx
->options
->chip_class
<= VI
) {
6148 ac_nir_build_if(&inner_if_ctx
, ctx
,
6149 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
6150 rel_patch_id
, ctx
->i32zero
, ""));
6152 /* Store the dynamic HS control word. */
6153 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
6154 LLVMConstInt(ctx
->i32
, 0x80000000, false),
6155 1, ctx
->i32zero
, tf_base
,
6156 0, 1, 0, true, false);
6159 ac_nir_build_endif(&inner_if_ctx
);
6162 /* Store the tessellation factors. */
6163 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
6164 MIN2(stride
, 4), byteoffset
, tf_base
,
6165 tf_offset
, 1, 0, true, false);
6167 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
6168 stride
- 4, byteoffset
, tf_base
,
6169 16 + tf_offset
, 1, 0, true, false);
6171 //store to offchip for TES to read - only if TES reads them
6172 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
6173 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
6174 LLVMValueRef tf_inner_offset
;
6175 unsigned param_outer
, param_inner
;
6177 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6178 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6179 LLVMConstInt(ctx
->i32
, param_outer
, 0));
6181 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
6182 util_next_power_of_two(outer_comps
));
6184 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
6185 outer_comps
, tf_outer_offset
,
6186 ctx
->oc_lds
, 0, 1, 0, true, false);
6188 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6189 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6190 LLVMConstInt(ctx
->i32
, param_inner
, 0));
6192 inner_vec
= inner_comps
== 1 ? inner
[0] :
6193 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
6194 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
6195 inner_comps
, tf_inner_offset
,
6196 ctx
->oc_lds
, 0, 1, 0, true, false);
6199 ac_nir_build_endif(&if_ctx
);
6203 handle_tcs_outputs_post(struct nir_to_llvm_context
*ctx
)
6205 write_tess_factors(ctx
);
6209 si_export_mrt_color(struct nir_to_llvm_context
*ctx
,
6210 LLVMValueRef
*color
, unsigned param
, bool is_last
,
6211 struct ac_export_args
*args
)
6214 si_llvm_init_export_args(ctx
, color
, param
,
6218 args
->valid_mask
= 1; /* whether the EXEC mask is valid */
6219 args
->done
= 1; /* DONE bit */
6220 } else if (!args
->enabled_channels
)
6221 return false; /* unnecessary NULL export */
6227 si_export_mrt_z(struct nir_to_llvm_context
*ctx
,
6228 LLVMValueRef depth
, LLVMValueRef stencil
,
6229 LLVMValueRef samplemask
)
6231 struct ac_export_args args
;
6233 args
.enabled_channels
= 0;
6234 args
.valid_mask
= 1;
6236 args
.target
= V_008DFC_SQ_EXP_MRTZ
;
6239 args
.out
[0] = LLVMGetUndef(ctx
->f32
); /* R, depth */
6240 args
.out
[1] = LLVMGetUndef(ctx
->f32
); /* G, stencil test val[0:7], stencil op val[8:15] */
6241 args
.out
[2] = LLVMGetUndef(ctx
->f32
); /* B, sample mask */
6242 args
.out
[3] = LLVMGetUndef(ctx
->f32
); /* A, alpha to mask */
6245 args
.out
[0] = depth
;
6246 args
.enabled_channels
|= 0x1;
6250 args
.out
[1] = stencil
;
6251 args
.enabled_channels
|= 0x2;
6255 args
.out
[2] = samplemask
;
6256 args
.enabled_channels
|= 0x4;
6259 /* SI (except OLAND and HAINAN) has a bug that it only looks
6260 * at the X writemask component. */
6261 if (ctx
->options
->chip_class
== SI
&&
6262 ctx
->options
->family
!= CHIP_OLAND
&&
6263 ctx
->options
->family
!= CHIP_HAINAN
)
6264 args
.enabled_channels
|= 0x1;
6266 ac_build_export(&ctx
->ac
, &args
);
6270 handle_fs_outputs_post(struct nir_to_llvm_context
*ctx
)
6273 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
6274 struct ac_export_args color_args
[8];
6276 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6277 LLVMValueRef values
[4];
6279 if (!(ctx
->output_mask
& (1ull << i
)))
6282 if (i
== FRAG_RESULT_DEPTH
) {
6283 ctx
->shader_info
->fs
.writes_z
= true;
6284 depth
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6285 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6286 } else if (i
== FRAG_RESULT_STENCIL
) {
6287 ctx
->shader_info
->fs
.writes_stencil
= true;
6288 stencil
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6289 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6290 } else if (i
== FRAG_RESULT_SAMPLE_MASK
) {
6291 ctx
->shader_info
->fs
.writes_sample_mask
= true;
6292 samplemask
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6293 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6296 for (unsigned j
= 0; j
< 4; j
++)
6297 values
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6298 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
6300 if (!ctx
->shader_info
->fs
.writes_z
&& !ctx
->shader_info
->fs
.writes_stencil
&& !ctx
->shader_info
->fs
.writes_sample_mask
)
6301 last
= ctx
->output_mask
<= ((1ull << (i
+ 1)) - 1);
6303 bool ret
= si_export_mrt_color(ctx
, values
, V_008DFC_SQ_EXP_MRT
+ (i
- FRAG_RESULT_DATA0
), last
, &color_args
[index
]);
6309 for (unsigned i
= 0; i
< index
; i
++)
6310 ac_build_export(&ctx
->ac
, &color_args
[i
]);
6311 if (depth
|| stencil
|| samplemask
)
6312 si_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
6314 si_export_mrt_color(ctx
, NULL
, V_008DFC_SQ_EXP_NULL
, true, &color_args
[0]);
6315 ac_build_export(&ctx
->ac
, &color_args
[0]);
6318 ctx
->shader_info
->fs
.output_mask
= index
? ((1ull << index
) - 1) : 0;
6322 emit_gs_epilogue(struct nir_to_llvm_context
*ctx
)
6324 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
6328 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
6329 LLVMValueRef
*addrs
)
6331 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
6333 switch (ctx
->stage
) {
6334 case MESA_SHADER_VERTEX
:
6335 if (ctx
->options
->key
.vs
.as_ls
)
6336 handle_ls_outputs_post(ctx
);
6337 else if (ctx
->options
->key
.vs
.as_es
)
6338 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
6340 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
6341 &ctx
->shader_info
->vs
.outinfo
);
6343 case MESA_SHADER_FRAGMENT
:
6344 handle_fs_outputs_post(ctx
);
6346 case MESA_SHADER_GEOMETRY
:
6347 emit_gs_epilogue(ctx
);
6349 case MESA_SHADER_TESS_CTRL
:
6350 handle_tcs_outputs_post(ctx
);
6352 case MESA_SHADER_TESS_EVAL
:
6353 if (ctx
->options
->key
.tes
.as_es
)
6354 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
6356 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
6357 &ctx
->shader_info
->tes
.outinfo
);
6364 static void ac_llvm_finalize_module(struct nir_to_llvm_context
* ctx
)
6366 LLVMPassManagerRef passmgr
;
6367 /* Create the pass manager */
6368 passmgr
= LLVMCreateFunctionPassManagerForModule(
6371 /* This pass should eliminate all the load and store instructions */
6372 LLVMAddPromoteMemoryToRegisterPass(passmgr
);
6374 /* Add some optimization passes */
6375 LLVMAddScalarReplAggregatesPass(passmgr
);
6376 LLVMAddLICMPass(passmgr
);
6377 LLVMAddAggressiveDCEPass(passmgr
);
6378 LLVMAddCFGSimplificationPass(passmgr
);
6379 LLVMAddInstructionCombiningPass(passmgr
);
6382 LLVMInitializeFunctionPassManager(passmgr
);
6383 LLVMRunFunctionPassManager(passmgr
, ctx
->main_function
);
6384 LLVMFinalizeFunctionPassManager(passmgr
);
6386 LLVMDisposeBuilder(ctx
->builder
);
6387 LLVMDisposePassManager(passmgr
);
6391 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context
*ctx
)
6393 struct ac_vs_output_info
*outinfo
;
6395 switch (ctx
->stage
) {
6396 case MESA_SHADER_FRAGMENT
:
6397 case MESA_SHADER_COMPUTE
:
6398 case MESA_SHADER_TESS_CTRL
:
6399 case MESA_SHADER_GEOMETRY
:
6401 case MESA_SHADER_VERTEX
:
6402 if (ctx
->options
->key
.vs
.as_ls
||
6403 ctx
->options
->key
.vs
.as_es
)
6405 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
6407 case MESA_SHADER_TESS_EVAL
:
6408 if (ctx
->options
->key
.vs
.as_es
)
6410 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
6413 unreachable("Unhandled shader type");
6416 ac_optimize_vs_outputs(&ctx
->ac
,
6418 outinfo
->vs_output_param_offset
,
6420 &outinfo
->param_exports
);
6424 ac_setup_rings(struct nir_to_llvm_context
*ctx
)
6426 if ((ctx
->stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_es
) ||
6427 (ctx
->stage
== MESA_SHADER_TESS_EVAL
&& ctx
->options
->key
.tes
.as_es
)) {
6428 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->i32
, RING_ESGS_VS
, false));
6431 if (ctx
->is_gs_copy_shader
) {
6432 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->i32
, RING_GSVS_VS
, false));
6434 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
6436 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->i32
, RING_ESGS_GS
, false));
6437 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->i32
, RING_GSVS_GS
, false));
6439 ctx
->gsvs_ring
= LLVMBuildBitCast(ctx
->builder
, ctx
->gsvs_ring
, ctx
->v4i32
, "");
6441 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->gsvs_num_entries
, LLVMConstInt(ctx
->i32
, 2, false), "");
6442 tmp
= LLVMBuildExtractElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->i32one
, "");
6443 tmp
= LLVMBuildOr(ctx
->builder
, tmp
, ctx
->gsvs_ring_stride
, "");
6444 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, tmp
, ctx
->i32one
, "");
6447 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
6448 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
6449 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->i32
, RING_HS_TESS_OFFCHIP
, false));
6450 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->i32
, RING_HS_TESS_FACTOR
, false));
6455 ac_nir_get_max_workgroup_size(enum chip_class chip_class
,
6456 const struct nir_shader
*nir
)
6458 switch (nir
->info
.stage
) {
6459 case MESA_SHADER_TESS_CTRL
:
6460 return chip_class
>= CIK
? 128 : 64;
6461 case MESA_SHADER_GEOMETRY
:
6462 return chip_class
>= GFX9
? 128 : 64;
6463 case MESA_SHADER_COMPUTE
:
6469 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
6470 nir
->info
.cs
.local_size
[1] *
6471 nir
->info
.cs
.local_size
[2];
6472 return max_workgroup_size
;
6475 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6476 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context
*ctx
)
6478 LLVMValueRef count
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6479 LLVMConstInt(ctx
->ac
.i32
, 8, false),
6480 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6481 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
6482 LLVMConstInt(ctx
->ac
.i32
, 0, false), "");
6483 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
6484 ctx
->vs_prim_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.vertex_id
, ctx
->vs_prim_id
, "");
6485 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->tcs_rel_ids
, ctx
->rel_auto_id
, "");
6486 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->tcs_patch_id
, ctx
->abi
.vertex_id
, "");
6489 static void prepare_gs_input_vgprs(struct nir_to_llvm_context
*ctx
)
6491 for(int i
= 5; i
>= 0; --i
) {
6492 ctx
->gs_vtx_offset
[i
] = ac_build_bfe(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
6493 LLVMConstInt(ctx
->ac
.i32
, (i
& 1) * 16, false),
6494 LLVMConstInt(ctx
->ac
.i32
, 16, false), false);
6497 ctx
->gs_wave_id
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6498 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6499 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6502 void ac_nir_translate(struct ac_llvm_context
*ac
, struct ac_shader_abi
*abi
,
6503 struct nir_shader
*nir
, struct nir_to_llvm_context
*nctx
)
6505 struct ac_nir_context ctx
= {};
6506 struct nir_function
*func
;
6515 ctx
.stage
= nir
->info
.stage
;
6517 ctx
.main_function
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6519 nir_foreach_variable(variable
, &nir
->outputs
)
6520 handle_shader_output_decl(&ctx
, nir
, variable
);
6522 ctx
.defs
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6523 _mesa_key_pointer_equal
);
6524 ctx
.phis
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6525 _mesa_key_pointer_equal
);
6526 ctx
.vars
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6527 _mesa_key_pointer_equal
);
6529 func
= (struct nir_function
*)exec_list_get_head(&nir
->functions
);
6531 setup_locals(&ctx
, func
);
6533 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
6534 setup_shared(&ctx
, nir
);
6536 visit_cf_list(&ctx
, &func
->impl
->body
);
6537 phi_post_pass(&ctx
);
6539 ctx
.abi
->emit_outputs(ctx
.abi
, RADEON_LLVM_MAX_OUTPUTS
,
6543 ralloc_free(ctx
.defs
);
6544 ralloc_free(ctx
.phis
);
6545 ralloc_free(ctx
.vars
);
6552 LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm
,
6553 struct nir_shader
*const *shaders
,
6555 struct ac_shader_variant_info
*shader_info
,
6556 const struct ac_nir_compiler_options
*options
)
6558 struct nir_to_llvm_context ctx
= {0};
6560 ctx
.options
= options
;
6561 ctx
.shader_info
= shader_info
;
6562 ctx
.context
= LLVMContextCreate();
6563 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
6565 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
);
6566 ctx
.ac
.module
= ctx
.module
;
6567 LLVMSetTarget(ctx
.module
, options
->supports_spill
? "amdgcn-mesa-mesa3d" : "amdgcn--");
6569 LLVMTargetDataRef data_layout
= LLVMCreateTargetDataLayout(tm
);
6570 char *data_layout_str
= LLVMCopyStringRepOfTargetData(data_layout
);
6571 LLVMSetDataLayout(ctx
.module
, data_layout_str
);
6572 LLVMDisposeTargetData(data_layout
);
6573 LLVMDisposeMessage(data_layout_str
);
6576 ctx
.builder
= LLVMCreateBuilderInContext(ctx
.context
);
6577 ctx
.ac
.builder
= ctx
.builder
;
6579 memset(shader_info
, 0, sizeof(*shader_info
));
6581 for(int i
= 0; i
< shader_count
; ++i
)
6582 ac_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
6584 for (i
= 0; i
< AC_UD_MAX_SETS
; i
++)
6585 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
6586 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
6587 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
6589 ctx
.max_workgroup_size
= 0;
6590 for (int i
= 0; i
< shader_count
; ++i
) {
6591 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
6592 ac_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
6596 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
6597 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
6599 ctx
.abi
.inputs
= &ctx
.inputs
[0];
6600 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
6601 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
6602 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
6604 if (shader_count
>= 2)
6605 ac_init_exec_full_mask(&ctx
.ac
);
6607 if (ctx
.ac
.chip_class
== GFX9
&&
6608 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
6609 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
6611 for(int i
= 0; i
< shader_count
; ++i
) {
6612 ctx
.stage
= shaders
[i
]->info
.stage
;
6613 ctx
.output_mask
= 0;
6614 ctx
.tess_outputs_written
= 0;
6615 ctx
.num_output_clips
= shaders
[i
]->info
.clip_distance_array_size
;
6616 ctx
.num_output_culls
= shaders
[i
]->info
.cull_distance_array_size
;
6618 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6619 ctx
.gs_next_vertex
= ac_build_alloca(&ctx
.ac
, ctx
.i32
, "gs_next_vertex");
6621 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
6622 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
6623 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
6624 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
6625 if (shader_info
->info
.vs
.needs_instance_id
) {
6626 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6627 MAX2(3, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6629 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
6630 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
6636 ac_setup_rings(&ctx
);
6638 LLVMBasicBlockRef merge_block
;
6639 if (shader_count
>= 2) {
6640 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6641 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6642 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6644 LLVMValueRef count
= ac_build_bfe(&ctx
.ac
, ctx
.merged_wave_info
,
6645 LLVMConstInt(ctx
.ac
.i32
, 8 * i
, false),
6646 LLVMConstInt(ctx
.ac
.i32
, 8, false), false);
6647 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
6648 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
6649 thread_id
, count
, "");
6650 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
6652 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
6655 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
6656 handle_fs_inputs(&ctx
, shaders
[i
]);
6657 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
6658 handle_vs_inputs(&ctx
, shaders
[i
]);
6659 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
6660 prepare_gs_input_vgprs(&ctx
);
6662 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
6663 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
6665 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
], &ctx
);
6667 if (shader_count
>= 2) {
6668 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
6669 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
6672 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6673 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
6674 shaders
[i
]->info
.cull_distance_array_size
> 4;
6675 shader_info
->gs
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
6676 shader_info
->gs
.max_gsvs_emit_size
= shader_info
->gs
.gsvs_vertex_size
*
6677 shaders
[i
]->info
.gs
.vertices_out
;
6678 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6679 shader_info
->tcs
.outputs_written
= ctx
.tess_outputs_written
;
6680 shader_info
->tcs
.patch_outputs_written
= ctx
.tess_patch_outputs_written
;
6681 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&& ctx
.options
->key
.vs
.as_ls
) {
6682 shader_info
->vs
.outputs_written
= ctx
.tess_outputs_written
;
6686 LLVMBuildRetVoid(ctx
.builder
);
6688 ac_llvm_finalize_module(&ctx
);
6690 if (shader_count
== 1)
6691 ac_nir_eliminate_const_vs_outputs(&ctx
);
6696 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
6698 unsigned *retval
= (unsigned *)context
;
6699 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
6700 char *description
= LLVMGetDiagInfoDescription(di
);
6702 if (severity
== LLVMDSError
) {
6704 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
6708 LLVMDisposeMessage(description
);
6711 static unsigned ac_llvm_compile(LLVMModuleRef M
,
6712 struct ac_shader_binary
*binary
,
6713 LLVMTargetMachineRef tm
)
6715 unsigned retval
= 0;
6717 LLVMContextRef llvm_ctx
;
6718 LLVMMemoryBufferRef out_buffer
;
6719 unsigned buffer_size
;
6720 const char *buffer_data
;
6723 /* Setup Diagnostic Handler*/
6724 llvm_ctx
= LLVMGetModuleContext(M
);
6726 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
6730 mem_err
= LLVMTargetMachineEmitToMemoryBuffer(tm
, M
, LLVMObjectFile
,
6733 /* Process Errors/Warnings */
6735 fprintf(stderr
, "%s: %s", __FUNCTION__
, err
);
6741 /* Extract Shader Code*/
6742 buffer_size
= LLVMGetBufferSize(out_buffer
);
6743 buffer_data
= LLVMGetBufferStart(out_buffer
);
6745 ac_elf_read(buffer_data
, buffer_size
, binary
);
6748 LLVMDisposeMemoryBuffer(out_buffer
);
6754 static void ac_compile_llvm_module(LLVMTargetMachineRef tm
,
6755 LLVMModuleRef llvm_module
,
6756 struct ac_shader_binary
*binary
,
6757 struct ac_shader_config
*config
,
6758 struct ac_shader_variant_info
*shader_info
,
6759 gl_shader_stage stage
,
6760 bool dump_shader
, bool supports_spill
)
6763 ac_dump_module(llvm_module
);
6765 memset(binary
, 0, sizeof(*binary
));
6766 int v
= ac_llvm_compile(llvm_module
, binary
, tm
);
6768 fprintf(stderr
, "compile failed\n");
6772 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
6774 ac_shader_binary_read_config(binary
, config
, 0, supports_spill
);
6776 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
6777 LLVMDisposeModule(llvm_module
);
6778 LLVMContextDispose(ctx
);
6780 if (stage
== MESA_SHADER_FRAGMENT
) {
6781 shader_info
->num_input_vgprs
= 0;
6782 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
6783 shader_info
->num_input_vgprs
+= 2;
6784 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
6785 shader_info
->num_input_vgprs
+= 2;
6786 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
6787 shader_info
->num_input_vgprs
+= 2;
6788 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
6789 shader_info
->num_input_vgprs
+= 3;
6790 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
6791 shader_info
->num_input_vgprs
+= 2;
6792 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
6793 shader_info
->num_input_vgprs
+= 2;
6794 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
6795 shader_info
->num_input_vgprs
+= 2;
6796 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
6797 shader_info
->num_input_vgprs
+= 1;
6798 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
6799 shader_info
->num_input_vgprs
+= 1;
6800 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
6801 shader_info
->num_input_vgprs
+= 1;
6802 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
6803 shader_info
->num_input_vgprs
+= 1;
6804 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
6805 shader_info
->num_input_vgprs
+= 1;
6806 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
6807 shader_info
->num_input_vgprs
+= 1;
6808 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
6809 shader_info
->num_input_vgprs
+= 1;
6810 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
6811 shader_info
->num_input_vgprs
+= 1;
6812 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
6813 shader_info
->num_input_vgprs
+= 1;
6815 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
6817 /* +3 for scratch wave offset and VCC */
6818 config
->num_sgprs
= MAX2(config
->num_sgprs
,
6819 shader_info
->num_input_sgprs
+ 3);
6823 ac_fill_shader_info(struct ac_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct ac_nir_compiler_options
*options
)
6825 switch (nir
->info
.stage
) {
6826 case MESA_SHADER_COMPUTE
:
6827 for (int i
= 0; i
< 3; ++i
)
6828 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
6830 case MESA_SHADER_FRAGMENT
:
6831 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
6833 case MESA_SHADER_GEOMETRY
:
6834 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
6835 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
6836 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
6837 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
6839 case MESA_SHADER_TESS_EVAL
:
6840 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
6841 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
6842 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
6843 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
6844 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
6846 case MESA_SHADER_TESS_CTRL
:
6847 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
6849 case MESA_SHADER_VERTEX
:
6850 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
6851 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
6852 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6853 if (options
->key
.vs
.as_ls
)
6854 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
6861 void ac_compile_nir_shader(LLVMTargetMachineRef tm
,
6862 struct ac_shader_binary
*binary
,
6863 struct ac_shader_config
*config
,
6864 struct ac_shader_variant_info
*shader_info
,
6865 struct nir_shader
*const *nir
,
6867 const struct ac_nir_compiler_options
*options
,
6871 LLVMModuleRef llvm_module
= ac_translate_nir_to_llvm(tm
, nir
, nir_count
, shader_info
,
6874 ac_compile_llvm_module(tm
, llvm_module
, binary
, config
, shader_info
, nir
[0]->info
.stage
, dump_shader
, options
->supports_spill
);
6875 for (int i
= 0; i
< nir_count
; ++i
)
6876 ac_fill_shader_info(shader_info
, nir
[i
], options
);
6880 ac_gs_copy_shader_emit(struct nir_to_llvm_context
*ctx
)
6882 LLVMValueRef args
[9];
6883 args
[0] = ctx
->gsvs_ring
;
6884 args
[1] = LLVMBuildMul(ctx
->builder
, ctx
->abi
.vertex_id
, LLVMConstInt(ctx
->i32
, 4, false), "");
6885 args
[3] = ctx
->i32zero
;
6886 args
[4] = ctx
->i32one
; /* OFFEN */
6887 args
[5] = ctx
->i32zero
; /* IDXEN */
6888 args
[6] = ctx
->i32one
; /* GLC */
6889 args
[7] = ctx
->i32one
; /* SLC */
6890 args
[8] = ctx
->i32zero
; /* TFE */
6894 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6898 if (!(ctx
->output_mask
& (1ull << i
)))
6901 if (i
== VARYING_SLOT_CLIP_DIST0
) {
6902 /* unpack clip and cull from a single set of slots */
6903 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6908 for (unsigned j
= 0; j
< length
; j
++) {
6910 args
[2] = LLVMConstInt(ctx
->i32
,
6912 ctx
->gs_max_out_vertices
* 16 * 4, false);
6914 value
= ac_build_intrinsic(&ctx
->ac
,
6915 "llvm.SI.buffer.load.dword.i32.i32",
6917 AC_FUNC_ATTR_READONLY
|
6918 AC_FUNC_ATTR_LEGACY
);
6920 LLVMBuildStore(ctx
->builder
,
6921 ac_to_float(&ctx
->ac
, value
), ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)]);
6925 handle_vs_outputs_post(ctx
, false, &ctx
->shader_info
->vs
.outinfo
);
6928 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm
,
6929 struct nir_shader
*geom_shader
,
6930 struct ac_shader_binary
*binary
,
6931 struct ac_shader_config
*config
,
6932 struct ac_shader_variant_info
*shader_info
,
6933 const struct ac_nir_compiler_options
*options
,
6936 struct nir_to_llvm_context ctx
= {0};
6937 ctx
.context
= LLVMContextCreate();
6938 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
6939 ctx
.options
= options
;
6940 ctx
.shader_info
= shader_info
;
6942 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
);
6943 ctx
.ac
.module
= ctx
.module
;
6945 ctx
.is_gs_copy_shader
= true;
6946 LLVMSetTarget(ctx
.module
, "amdgcn--");
6949 ctx
.builder
= LLVMCreateBuilderInContext(ctx
.context
);
6950 ctx
.ac
.builder
= ctx
.builder
;
6951 ctx
.stage
= MESA_SHADER_VERTEX
;
6953 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
6955 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
6956 ac_setup_rings(&ctx
);
6958 ctx
.num_output_clips
= geom_shader
->info
.clip_distance_array_size
;
6959 ctx
.num_output_culls
= geom_shader
->info
.cull_distance_array_size
;
6961 struct ac_nir_context nir_ctx
= {};
6962 nir_ctx
.ac
= ctx
.ac
;
6963 nir_ctx
.abi
= &ctx
.abi
;
6965 nir_ctx
.nctx
= &ctx
;
6968 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
6969 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
6970 handle_shader_output_decl(&nir_ctx
, geom_shader
, variable
);
6973 ac_gs_copy_shader_emit(&ctx
);
6977 LLVMBuildRetVoid(ctx
.builder
);
6979 ac_llvm_finalize_module(&ctx
);
6981 ac_compile_llvm_module(tm
, ctx
.module
, binary
, config
, shader_info
,
6983 dump_shader
, options
->supports_spill
);