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radv/ac: use bitfield extract new intrinsics.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef gsvs_ring_stride;
87 LLVMValueRef gsvs_num_entries;
88 LLVMValueRef gs2vs_offset;
89 LLVMValueRef gs_wave_id;
90 LLVMValueRef gs_vtx_offset[6];
91 LLVMValueRef gs_prim_id, gs_invocation_id;
92
93 LLVMValueRef esgs_ring;
94 LLVMValueRef gsvs_ring;
95
96 LLVMValueRef prim_mask;
97 LLVMValueRef sample_positions;
98 LLVMValueRef persp_sample, persp_center, persp_centroid;
99 LLVMValueRef linear_sample, linear_center, linear_centroid;
100 LLVMValueRef front_face;
101 LLVMValueRef ancillary;
102 LLVMValueRef sample_coverage;
103 LLVMValueRef frag_pos[4];
104
105 LLVMBasicBlockRef continue_block;
106 LLVMBasicBlockRef break_block;
107
108 LLVMTypeRef i1;
109 LLVMTypeRef i8;
110 LLVMTypeRef i16;
111 LLVMTypeRef i32;
112 LLVMTypeRef i64;
113 LLVMTypeRef v2i32;
114 LLVMTypeRef v3i32;
115 LLVMTypeRef v4i32;
116 LLVMTypeRef v8i32;
117 LLVMTypeRef f64;
118 LLVMTypeRef f32;
119 LLVMTypeRef f16;
120 LLVMTypeRef v2f32;
121 LLVMTypeRef v4f32;
122 LLVMTypeRef v16i8;
123 LLVMTypeRef voidt;
124
125 LLVMValueRef i32zero;
126 LLVMValueRef i32one;
127 LLVMValueRef f32zero;
128 LLVMValueRef f32one;
129 LLVMValueRef v4f32empty;
130
131 unsigned uniform_md_kind;
132 LLVMValueRef empty_md;
133 gl_shader_stage stage;
134
135 LLVMValueRef lds;
136 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
137 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
138
139 LLVMValueRef shared_memory;
140 uint64_t input_mask;
141 uint64_t output_mask;
142 int num_locals;
143 LLVMValueRef *locals;
144 bool has_ddxy;
145 uint8_t num_input_clips;
146 uint8_t num_input_culls;
147 uint8_t num_output_clips;
148 uint8_t num_output_culls;
149
150 bool has_ds_bpermute;
151
152 bool is_gs_copy_shader;
153 LLVMValueRef gs_next_vertex;
154 unsigned gs_max_out_vertices;
155 };
156
157 struct ac_tex_info {
158 LLVMValueRef args[12];
159 int arg_count;
160 LLVMTypeRef dst_type;
161 bool has_offset;
162 };
163
164 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
165 nir_deref_var *deref,
166 enum desc_type desc_type);
167 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
168 {
169 return (index * 4) + chan;
170 }
171
172 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
173 {
174 if (slot == VARYING_SLOT_POS)
175 return 0;
176 if (slot == VARYING_SLOT_PSIZ)
177 return 1;
178 if (slot == VARYING_SLOT_CLIP_DIST0 ||
179 slot == VARYING_SLOT_CULL_DIST0)
180 return 2;
181 if (slot == VARYING_SLOT_CLIP_DIST1 ||
182 slot == VARYING_SLOT_CULL_DIST1)
183 return 3;
184 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
185 return 4 + (slot - VARYING_SLOT_VAR0);
186 unreachable("illegal slot in get unique index\n");
187 }
188
189 static unsigned llvm_get_type_size(LLVMTypeRef type)
190 {
191 LLVMTypeKind kind = LLVMGetTypeKind(type);
192
193 switch (kind) {
194 case LLVMIntegerTypeKind:
195 return LLVMGetIntTypeWidth(type) / 8;
196 case LLVMFloatTypeKind:
197 return 4;
198 case LLVMPointerTypeKind:
199 return 8;
200 case LLVMVectorTypeKind:
201 return LLVMGetVectorSize(type) *
202 llvm_get_type_size(LLVMGetElementType(type));
203 default:
204 assert(0);
205 return 0;
206 }
207 }
208
209 static void set_llvm_calling_convention(LLVMValueRef func,
210 gl_shader_stage stage)
211 {
212 enum radeon_llvm_calling_convention calling_conv;
213
214 switch (stage) {
215 case MESA_SHADER_VERTEX:
216 case MESA_SHADER_TESS_CTRL:
217 case MESA_SHADER_TESS_EVAL:
218 calling_conv = RADEON_LLVM_AMDGPU_VS;
219 break;
220 case MESA_SHADER_GEOMETRY:
221 calling_conv = RADEON_LLVM_AMDGPU_GS;
222 break;
223 case MESA_SHADER_FRAGMENT:
224 calling_conv = RADEON_LLVM_AMDGPU_PS;
225 break;
226 case MESA_SHADER_COMPUTE:
227 calling_conv = RADEON_LLVM_AMDGPU_CS;
228 break;
229 default:
230 unreachable("Unhandle shader type");
231 }
232
233 LLVMSetFunctionCallConv(func, calling_conv);
234 }
235
236 static LLVMValueRef
237 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
238 LLVMBuilderRef builder, LLVMTypeRef *return_types,
239 unsigned num_return_elems, LLVMTypeRef *param_types,
240 unsigned param_count, unsigned array_params_mask,
241 unsigned sgpr_params, bool unsafe_math)
242 {
243 LLVMTypeRef main_function_type, ret_type;
244 LLVMBasicBlockRef main_function_body;
245
246 if (num_return_elems)
247 ret_type = LLVMStructTypeInContext(ctx, return_types,
248 num_return_elems, true);
249 else
250 ret_type = LLVMVoidTypeInContext(ctx);
251
252 /* Setup the function */
253 main_function_type =
254 LLVMFunctionType(ret_type, param_types, param_count, 0);
255 LLVMValueRef main_function =
256 LLVMAddFunction(module, "main", main_function_type);
257 main_function_body =
258 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
259 LLVMPositionBuilderAtEnd(builder, main_function_body);
260
261 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
262 for (unsigned i = 0; i < sgpr_params; ++i) {
263 if (array_params_mask & (1 << i)) {
264 LLVMValueRef P = LLVMGetParam(main_function, i);
265 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
266 ac_add_attr_dereferenceable(P, UINT64_MAX);
267 }
268 else {
269 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
270 }
271 }
272
273 if (unsafe_math) {
274 /* These were copied from some LLVM test. */
275 LLVMAddTargetDependentFunctionAttr(main_function,
276 "less-precise-fpmad",
277 "true");
278 LLVMAddTargetDependentFunctionAttr(main_function,
279 "no-infs-fp-math",
280 "true");
281 LLVMAddTargetDependentFunctionAttr(main_function,
282 "no-nans-fp-math",
283 "true");
284 LLVMAddTargetDependentFunctionAttr(main_function,
285 "unsafe-fp-math",
286 "true");
287 }
288 return main_function;
289 }
290
291 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
292 {
293 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
294 CONST_ADDR_SPACE);
295 }
296
297 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
298 int idx,
299 LLVMTypeRef type)
300 {
301 LLVMValueRef offset;
302 LLVMValueRef ptr;
303 int addr_space;
304
305 offset = LLVMConstInt(ctx->i32, idx, false);
306
307 ptr = ctx->shared_memory;
308 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
309 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
310 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
311 return ptr;
312 }
313
314 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
315 {
316 if (t == ctx->f16 || t == ctx->i16)
317 return ctx->i16;
318 else if (t == ctx->f32 || t == ctx->i32)
319 return ctx->i32;
320 else if (t == ctx->f64 || t == ctx->i64)
321 return ctx->i64;
322 else
323 unreachable("Unhandled integer size");
324 }
325
326 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
327 {
328 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
329 LLVMTypeRef elem_type = LLVMGetElementType(t);
330 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
331 LLVMGetVectorSize(t));
332 }
333 return to_integer_type_scalar(ctx, t);
334 }
335
336 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
337 {
338 LLVMTypeRef type = LLVMTypeOf(v);
339 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
340 }
341
342 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
343 {
344 if (t == ctx->i16 || t == ctx->f16)
345 return ctx->f16;
346 else if (t == ctx->i32 || t == ctx->f32)
347 return ctx->f32;
348 else if (t == ctx->i64 || t == ctx->f64)
349 return ctx->f64;
350 else
351 unreachable("Unhandled float size");
352 }
353
354 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
355 {
356 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
357 LLVMTypeRef elem_type = LLVMGetElementType(t);
358 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
359 LLVMGetVectorSize(t));
360 }
361 return to_float_type_scalar(ctx, t);
362 }
363
364 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
365 {
366 LLVMTypeRef type = LLVMTypeOf(v);
367 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
368 }
369
370 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
371 {
372 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
373 type = LLVMGetElementType(type);
374
375 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
376 return LLVMGetIntTypeWidth(type);
377
378 if (type == ctx->f16)
379 return 16;
380 if (type == ctx->f32)
381 return 32;
382 if (type == ctx->f64)
383 return 64;
384
385 unreachable("Unhandled type kind in get_elem_bits");
386 }
387
388 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
389 LLVMValueRef param, unsigned rshift,
390 unsigned bitwidth)
391 {
392 LLVMValueRef value = param;
393 if (rshift)
394 value = LLVMBuildLShr(ctx->builder, value,
395 LLVMConstInt(ctx->i32, rshift, false), "");
396
397 if (rshift + bitwidth < 32) {
398 unsigned mask = (1 << bitwidth) - 1;
399 value = LLVMBuildAnd(ctx->builder, value,
400 LLVMConstInt(ctx->i32, mask, false), "");
401 }
402 return value;
403 }
404
405 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
406 {
407 ud_info->sgpr_idx = sgpr_idx;
408 ud_info->num_sgprs = num_sgprs;
409 ud_info->indirect = false;
410 ud_info->indirect_offset = 0;
411 }
412
413 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
414 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
415 {
416 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
417 }
418
419 #if 0
420 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
421 uint32_t indirect_offset)
422 {
423 ud_info->sgpr_idx = sgpr_idx;
424 ud_info->num_sgprs = num_sgprs;
425 ud_info->indirect = true;
426 ud_info->indirect_offset = indirect_offset;
427 }
428 #endif
429
430 static void create_function(struct nir_to_llvm_context *ctx)
431 {
432 LLVMTypeRef arg_types[23];
433 unsigned arg_idx = 0;
434 unsigned array_params_mask = 0;
435 unsigned sgpr_count = 0, user_sgpr_count;
436 unsigned i;
437 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
438 unsigned user_sgpr_idx;
439 bool need_push_constants;
440 bool need_ring_offsets = false;
441
442 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
443 if (ctx->stage == MESA_SHADER_GEOMETRY ||
444 ctx->stage == MESA_SHADER_VERTEX ||
445 ctx->is_gs_copy_shader)
446 need_ring_offsets = true;
447
448 need_push_constants = true;
449 if (!ctx->options->layout)
450 need_push_constants = false;
451 else if (!ctx->options->layout->push_constant_size &&
452 !ctx->options->layout->dynamic_offset_count)
453 need_push_constants = false;
454
455 if (need_ring_offsets && !ctx->options->supports_spill) {
456 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
457 }
458
459 /* 1 for each descriptor set */
460 for (unsigned i = 0; i < num_sets; ++i) {
461 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
462 array_params_mask |= (1 << arg_idx);
463 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
464 }
465 }
466
467 if (need_push_constants) {
468 /* 1 for push constants and dynamic descriptors */
469 array_params_mask |= (1 << arg_idx);
470 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
471 }
472
473 switch (ctx->stage) {
474 case MESA_SHADER_COMPUTE:
475 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
476 user_sgpr_count = arg_idx;
477 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
478 arg_types[arg_idx++] = ctx->i32;
479 sgpr_count = arg_idx;
480
481 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
482 break;
483 case MESA_SHADER_VERTEX:
484 if (!ctx->is_gs_copy_shader) {
485 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
486 arg_types[arg_idx++] = ctx->i32; // base vertex
487 arg_types[arg_idx++] = ctx->i32; // start instance
488 arg_types[arg_idx++] = ctx->i32; // draw index
489 }
490 user_sgpr_count = arg_idx;
491 if (ctx->options->key.vs.as_es)
492 arg_types[arg_idx++] = ctx->i32; //es2gs offset
493 sgpr_count = arg_idx;
494 arg_types[arg_idx++] = ctx->i32; // vertex id
495 if (!ctx->is_gs_copy_shader) {
496 arg_types[arg_idx++] = ctx->i32; // rel auto id
497 arg_types[arg_idx++] = ctx->i32; // vs prim id
498 arg_types[arg_idx++] = ctx->i32; // instance id
499 }
500 break;
501 case MESA_SHADER_GEOMETRY:
502 arg_types[arg_idx++] = ctx->i32; // gsvs stride
503 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
504 user_sgpr_count = arg_idx;
505 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
506 arg_types[arg_idx++] = ctx->i32; // wave id
507 sgpr_count = arg_idx;
508 arg_types[arg_idx++] = ctx->i32; // vtx0
509 arg_types[arg_idx++] = ctx->i32; // vtx1
510 arg_types[arg_idx++] = ctx->i32; // prim id
511 arg_types[arg_idx++] = ctx->i32; // vtx2
512 arg_types[arg_idx++] = ctx->i32; // vtx3
513 arg_types[arg_idx++] = ctx->i32; // vtx4
514 arg_types[arg_idx++] = ctx->i32; // vtx5
515 arg_types[arg_idx++] = ctx->i32; // GS instance id
516 break;
517 case MESA_SHADER_FRAGMENT:
518 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
519 user_sgpr_count = arg_idx;
520 arg_types[arg_idx++] = ctx->i32; /* prim mask */
521 sgpr_count = arg_idx;
522 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
523 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
524 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
525 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
526 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
527 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
528 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
529 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
530 arg_types[arg_idx++] = ctx->f32; /* pos x float */
531 arg_types[arg_idx++] = ctx->f32; /* pos y float */
532 arg_types[arg_idx++] = ctx->f32; /* pos z float */
533 arg_types[arg_idx++] = ctx->f32; /* pos w float */
534 arg_types[arg_idx++] = ctx->i32; /* front face */
535 arg_types[arg_idx++] = ctx->i32; /* ancillary */
536 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
537 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
538 break;
539 default:
540 unreachable("Shader stage not implemented");
541 }
542
543 ctx->main_function = create_llvm_function(
544 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
545 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
546 set_llvm_calling_convention(ctx->main_function, ctx->stage);
547
548 ctx->shader_info->num_input_sgprs = 0;
549 ctx->shader_info->num_input_vgprs = 0;
550
551 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
552 for (i = 0; i < user_sgpr_count; i++)
553 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
554
555 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
556 for (; i < sgpr_count; i++)
557 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
558
559 if (ctx->stage != MESA_SHADER_FRAGMENT)
560 for (; i < arg_idx; ++i)
561 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
562
563 arg_idx = 0;
564 user_sgpr_idx = 0;
565
566 if (ctx->options->supports_spill || need_ring_offsets) {
567 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
568 user_sgpr_idx += 2;
569 if (ctx->options->supports_spill) {
570 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
571 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
572 NULL, 0, AC_FUNC_ATTR_READNONE);
573 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
574 const_array(ctx->v16i8, 8), "");
575 } else
576 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
577 }
578
579 for (unsigned i = 0; i < num_sets; ++i) {
580 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
581 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
582 user_sgpr_idx += 2;
583 ctx->descriptor_sets[i] =
584 LLVMGetParam(ctx->main_function, arg_idx++);
585 } else
586 ctx->descriptor_sets[i] = NULL;
587 }
588
589 if (need_push_constants) {
590 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
591 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
592 user_sgpr_idx += 2;
593 }
594
595 switch (ctx->stage) {
596 case MESA_SHADER_COMPUTE:
597 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
598 user_sgpr_idx += 3;
599 ctx->num_work_groups =
600 LLVMGetParam(ctx->main_function, arg_idx++);
601 ctx->workgroup_ids =
602 LLVMGetParam(ctx->main_function, arg_idx++);
603 ctx->tg_size =
604 LLVMGetParam(ctx->main_function, arg_idx++);
605 ctx->local_invocation_ids =
606 LLVMGetParam(ctx->main_function, arg_idx++);
607 break;
608 case MESA_SHADER_VERTEX:
609 if (!ctx->is_gs_copy_shader) {
610 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
611 user_sgpr_idx += 2;
612 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
613 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
614 user_sgpr_idx += 3;
615 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
616 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
617 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
618 }
619 if (ctx->options->key.vs.as_es)
620 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
621 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
622 if (!ctx->is_gs_copy_shader) {
623 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
624 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
625 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
626 }
627 break;
628 case MESA_SHADER_GEOMETRY:
629 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
630 user_sgpr_idx += 2;
631 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
632 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
633 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
634 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
635 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
636 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
637 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
638 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
639 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
640 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
641 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
642 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
643 break;
644 case MESA_SHADER_FRAGMENT:
645 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
646 user_sgpr_idx += 2;
647 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
648 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
649 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
650 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
651 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
652 arg_idx++;
653 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
654 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
655 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
656 arg_idx++; /* line stipple */
657 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
658 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
659 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
660 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
661 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
662 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
663 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
664 break;
665 default:
666 unreachable("Shader stage not implemented");
667 }
668 }
669
670 static void setup_types(struct nir_to_llvm_context *ctx)
671 {
672 LLVMValueRef args[4];
673
674 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
675 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
676 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
677 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
678 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
679 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
680 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
681 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
682 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
683 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
684 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
685 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
686 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
687 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
688 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
689 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
690
691 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
692 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
693 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
694 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
695
696 args[0] = ctx->f32zero;
697 args[1] = ctx->f32zero;
698 args[2] = ctx->f32zero;
699 args[3] = ctx->f32one;
700 ctx->v4f32empty = LLVMConstVector(args, 4);
701
702 ctx->uniform_md_kind =
703 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
704 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
705
706 args[0] = LLVMConstReal(ctx->f32, 2.5);
707 }
708
709 static int get_llvm_num_components(LLVMValueRef value)
710 {
711 LLVMTypeRef type = LLVMTypeOf(value);
712 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
713 ? LLVMGetVectorSize(type)
714 : 1;
715 return num_components;
716 }
717
718 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
719 LLVMValueRef value,
720 int index)
721 {
722 int count = get_llvm_num_components(value);
723
724 assert(index < count);
725 if (count == 1)
726 return value;
727
728 return LLVMBuildExtractElement(ctx->builder, value,
729 LLVMConstInt(ctx->i32, index, false), "");
730 }
731
732 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
733 LLVMValueRef value, unsigned count)
734 {
735 unsigned num_components = get_llvm_num_components(value);
736 if (count == num_components)
737 return value;
738
739 LLVMValueRef masks[] = {
740 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
741 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
742
743 if (count == 1)
744 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
745 "");
746
747 LLVMValueRef swizzle = LLVMConstVector(masks, count);
748 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
749 }
750
751 static void
752 build_store_values_extended(struct nir_to_llvm_context *ctx,
753 LLVMValueRef *values,
754 unsigned value_count,
755 unsigned value_stride,
756 LLVMValueRef vec)
757 {
758 LLVMBuilderRef builder = ctx->builder;
759 unsigned i;
760
761 if (value_count == 1) {
762 LLVMBuildStore(builder, vec, values[0]);
763 return;
764 }
765
766 for (i = 0; i < value_count; i++) {
767 LLVMValueRef ptr = values[i * value_stride];
768 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
769 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
770 LLVMBuildStore(builder, value, ptr);
771 }
772 }
773
774 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
775 nir_ssa_def *def)
776 {
777 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
778 if (def->num_components > 1) {
779 type = LLVMVectorType(type, def->num_components);
780 }
781 return type;
782 }
783
784 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
785 {
786 assert(src.is_ssa);
787 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
788 return (LLVMValueRef)entry->data;
789 }
790
791
792 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
793 struct nir_block *b)
794 {
795 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
796 return (LLVMBasicBlockRef)entry->data;
797 }
798
799 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
800 nir_alu_src src,
801 unsigned num_components)
802 {
803 LLVMValueRef value = get_src(ctx, src.src);
804 bool need_swizzle = false;
805
806 assert(value);
807 LLVMTypeRef type = LLVMTypeOf(value);
808 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
809 ? LLVMGetVectorSize(type)
810 : 1;
811
812 for (unsigned i = 0; i < num_components; ++i) {
813 assert(src.swizzle[i] < src_components);
814 if (src.swizzle[i] != i)
815 need_swizzle = true;
816 }
817
818 if (need_swizzle || num_components != src_components) {
819 LLVMValueRef masks[] = {
820 LLVMConstInt(ctx->i32, src.swizzle[0], false),
821 LLVMConstInt(ctx->i32, src.swizzle[1], false),
822 LLVMConstInt(ctx->i32, src.swizzle[2], false),
823 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
824
825 if (src_components > 1 && num_components == 1) {
826 value = LLVMBuildExtractElement(ctx->builder, value,
827 masks[0], "");
828 } else if (src_components == 1 && num_components > 1) {
829 LLVMValueRef values[] = {value, value, value, value};
830 value = ac_build_gather_values(&ctx->ac, values, num_components);
831 } else {
832 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
833 value = LLVMBuildShuffleVector(ctx->builder, value, value,
834 swizzle, "");
835 }
836 }
837 assert(!src.negate);
838 assert(!src.abs);
839 return value;
840 }
841
842 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
843 LLVMIntPredicate pred, LLVMValueRef src0,
844 LLVMValueRef src1)
845 {
846 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
847 return LLVMBuildSelect(ctx->builder, result,
848 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
849 LLVMConstInt(ctx->i32, 0, false), "");
850 }
851
852 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
853 LLVMRealPredicate pred, LLVMValueRef src0,
854 LLVMValueRef src1)
855 {
856 LLVMValueRef result;
857 src0 = to_float(ctx, src0);
858 src1 = to_float(ctx, src1);
859 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
860 return LLVMBuildSelect(ctx->builder, result,
861 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
862 LLVMConstInt(ctx->i32, 0, false), "");
863 }
864
865 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
866 const char *intrin,
867 LLVMTypeRef result_type,
868 LLVMValueRef src0)
869 {
870 char name[64];
871 LLVMValueRef params[] = {
872 to_float(ctx, src0),
873 };
874
875 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
876 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
877 }
878
879 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
880 const char *intrin,
881 LLVMTypeRef result_type,
882 LLVMValueRef src0, LLVMValueRef src1)
883 {
884 char name[64];
885 LLVMValueRef params[] = {
886 to_float(ctx, src0),
887 to_float(ctx, src1),
888 };
889
890 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
891 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
892 }
893
894 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
895 const char *intrin,
896 LLVMTypeRef result_type,
897 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
898 {
899 char name[64];
900 LLVMValueRef params[] = {
901 to_float(ctx, src0),
902 to_float(ctx, src1),
903 to_float(ctx, src2),
904 };
905
906 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
907 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
908 }
909
910 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
911 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
912 {
913 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
914 ctx->i32zero, "");
915 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
916 }
917
918 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
919 LLVMValueRef src0)
920 {
921 LLVMValueRef params[2] = {
922 src0,
923
924 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
925 * add special code to check for x=0. The reason is that
926 * the LLVM behavior for x=0 is different from what we
927 * need here.
928 *
929 * The hardware already implements the correct behavior.
930 */
931 LLVMConstInt(ctx->i32, 1, false),
932 };
933 return ac_build_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
934 }
935
936 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
937 LLVMValueRef src0)
938 {
939 return ac_build_imsb(&ctx->ac, src0, ctx->i32);
940 }
941
942 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
943 LLVMValueRef src0)
944 {
945 return ac_build_umsb(&ctx->ac, src0, ctx->i32);
946 }
947
948 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
949 LLVMIntPredicate pred,
950 LLVMValueRef src0, LLVMValueRef src1)
951 {
952 return LLVMBuildSelect(ctx->builder,
953 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
954 src0,
955 src1, "");
956
957 }
958 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
959 LLVMValueRef src0)
960 {
961 return emit_minmax_int(ctx, LLVMIntSGT, src0,
962 LLVMBuildNeg(ctx->builder, src0, ""));
963 }
964
965 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
966 LLVMValueRef src0)
967 {
968 LLVMValueRef cmp, val;
969
970 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
971 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
972 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
973 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
974 return val;
975 }
976
977 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
978 LLVMValueRef src0)
979 {
980 LLVMValueRef cmp, val;
981
982 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
983 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
984 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
985 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
986 return val;
987 }
988
989 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
990 LLVMValueRef src0)
991 {
992 const char *intr = "llvm.floor.f32";
993 LLVMValueRef fsrc0 = to_float(ctx, src0);
994 LLVMValueRef params[] = {
995 fsrc0,
996 };
997 LLVMValueRef floor = ac_build_intrinsic(&ctx->ac, intr,
998 ctx->f32, params, 1,
999 AC_FUNC_ATTR_READNONE);
1000 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1001 }
1002
1003 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1004 const char *intrin,
1005 LLVMValueRef src0, LLVMValueRef src1)
1006 {
1007 LLVMTypeRef ret_type;
1008 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1009 LLVMValueRef res;
1010 LLVMValueRef params[] = { src0, src1 };
1011 ret_type = LLVMStructTypeInContext(ctx->context, types,
1012 2, true);
1013
1014 res = ac_build_intrinsic(&ctx->ac, intrin, ret_type,
1015 params, 2, AC_FUNC_ATTR_READNONE);
1016
1017 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1018 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1019 return res;
1020 }
1021
1022 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1023 LLVMValueRef src0)
1024 {
1025 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1026 }
1027
1028 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1029 LLVMValueRef src0, LLVMValueRef src1)
1030 {
1031 LLVMValueRef dst64, result;
1032 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1033 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1034
1035 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1036 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1037 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1038 return result;
1039 }
1040
1041 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1042 LLVMValueRef src0, LLVMValueRef src1)
1043 {
1044 LLVMValueRef dst64, result;
1045 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1046 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1047
1048 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1049 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1050 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1051 return result;
1052 }
1053
1054 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1055 bool is_signed,
1056 LLVMValueRef srcs[3])
1057 {
1058 LLVMValueRef result;
1059 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1060
1061 result = ac_build_bfe(&ctx->ac, srcs[0], srcs[1], srcs[2], is_signed);
1062 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1063 return result;
1064 }
1065
1066 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1067 LLVMValueRef src0, LLVMValueRef src1,
1068 LLVMValueRef src2, LLVMValueRef src3)
1069 {
1070 LLVMValueRef bfi_args[3], result;
1071
1072 bfi_args[0] = LLVMBuildShl(ctx->builder,
1073 LLVMBuildSub(ctx->builder,
1074 LLVMBuildShl(ctx->builder,
1075 ctx->i32one,
1076 src3, ""),
1077 ctx->i32one, ""),
1078 src2, "");
1079 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1080 bfi_args[2] = src0;
1081
1082 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1083
1084 /* Calculate:
1085 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1086 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1087 */
1088 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1089 LLVMBuildAnd(ctx->builder, bfi_args[0],
1090 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1091
1092 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1093 return result;
1094 }
1095
1096 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1097 LLVMValueRef src0)
1098 {
1099 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1100 int i;
1101 LLVMValueRef comp[2];
1102
1103 src0 = to_float(ctx, src0);
1104 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1105 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1106 for (i = 0; i < 2; i++) {
1107 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1108 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1109 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1110 }
1111
1112 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1113 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1114
1115 return comp[0];
1116 }
1117
1118 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1119 LLVMValueRef src0)
1120 {
1121 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1122 LLVMValueRef temps[2], result, val;
1123 int i;
1124
1125 for (i = 0; i < 2; i++) {
1126 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1127 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1128 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1129 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1130 }
1131
1132 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1133 ctx->i32zero, "");
1134 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1135 ctx->i32one, "");
1136 return result;
1137 }
1138
1139 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1140 nir_op op,
1141 LLVMValueRef src0)
1142 {
1143 unsigned mask;
1144 int idx;
1145 LLVMValueRef result;
1146 ctx->has_ddxy = true;
1147
1148 if (!ctx->lds && !ctx->has_ds_bpermute)
1149 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1150 LLVMArrayType(ctx->i32, 64),
1151 "ddxy_lds", LOCAL_ADDR_SPACE);
1152
1153 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1154 mask = AC_TID_MASK_LEFT;
1155 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1156 mask = AC_TID_MASK_TOP;
1157 else
1158 mask = AC_TID_MASK_TOP_LEFT;
1159
1160 /* for DDX we want to next X pixel, DDY next Y pixel. */
1161 if (op == nir_op_fddx_fine ||
1162 op == nir_op_fddx_coarse ||
1163 op == nir_op_fddx)
1164 idx = 1;
1165 else
1166 idx = 2;
1167
1168 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1169 mask, idx, ctx->lds,
1170 src0);
1171 return result;
1172 }
1173
1174 /*
1175 * this takes an I,J coordinate pair,
1176 * and works out the X and Y derivatives.
1177 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1178 */
1179 static LLVMValueRef emit_ddxy_interp(
1180 struct nir_to_llvm_context *ctx,
1181 LLVMValueRef interp_ij)
1182 {
1183 LLVMValueRef result[4], a;
1184 unsigned i;
1185
1186 for (i = 0; i < 2; i++) {
1187 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1188 LLVMConstInt(ctx->i32, i, false), "");
1189 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1190 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1191 }
1192 return ac_build_gather_values(&ctx->ac, result, 4);
1193 }
1194
1195 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1196 {
1197 LLVMValueRef src[4], result = NULL;
1198 unsigned num_components = instr->dest.dest.ssa.num_components;
1199 unsigned src_components;
1200 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1201
1202 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1203 switch (instr->op) {
1204 case nir_op_vec2:
1205 case nir_op_vec3:
1206 case nir_op_vec4:
1207 src_components = 1;
1208 break;
1209 case nir_op_pack_half_2x16:
1210 src_components = 2;
1211 break;
1212 case nir_op_unpack_half_2x16:
1213 src_components = 1;
1214 break;
1215 default:
1216 src_components = num_components;
1217 break;
1218 }
1219 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1220 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1221
1222 switch (instr->op) {
1223 case nir_op_fmov:
1224 case nir_op_imov:
1225 result = src[0];
1226 break;
1227 case nir_op_fneg:
1228 src[0] = to_float(ctx, src[0]);
1229 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1230 break;
1231 case nir_op_ineg:
1232 result = LLVMBuildNeg(ctx->builder, src[0], "");
1233 break;
1234 case nir_op_inot:
1235 result = LLVMBuildNot(ctx->builder, src[0], "");
1236 break;
1237 case nir_op_iadd:
1238 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1239 break;
1240 case nir_op_fadd:
1241 src[0] = to_float(ctx, src[0]);
1242 src[1] = to_float(ctx, src[1]);
1243 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1244 break;
1245 case nir_op_fsub:
1246 src[0] = to_float(ctx, src[0]);
1247 src[1] = to_float(ctx, src[1]);
1248 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1249 break;
1250 case nir_op_isub:
1251 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1252 break;
1253 case nir_op_imul:
1254 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1255 break;
1256 case nir_op_imod:
1257 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1258 break;
1259 case nir_op_umod:
1260 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1261 break;
1262 case nir_op_fmod:
1263 src[0] = to_float(ctx, src[0]);
1264 src[1] = to_float(ctx, src[1]);
1265 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1266 result = emit_intrin_1f_param(ctx, "llvm.floor",
1267 to_float_type(ctx, def_type), result);
1268 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1269 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1270 break;
1271 case nir_op_frem:
1272 src[0] = to_float(ctx, src[0]);
1273 src[1] = to_float(ctx, src[1]);
1274 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1275 break;
1276 case nir_op_irem:
1277 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1278 break;
1279 case nir_op_idiv:
1280 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1281 break;
1282 case nir_op_udiv:
1283 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1284 break;
1285 case nir_op_fmul:
1286 src[0] = to_float(ctx, src[0]);
1287 src[1] = to_float(ctx, src[1]);
1288 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1289 break;
1290 case nir_op_fdiv:
1291 src[0] = to_float(ctx, src[0]);
1292 src[1] = to_float(ctx, src[1]);
1293 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1294 break;
1295 case nir_op_frcp:
1296 src[0] = to_float(ctx, src[0]);
1297 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1298 break;
1299 case nir_op_iand:
1300 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1301 break;
1302 case nir_op_ior:
1303 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1304 break;
1305 case nir_op_ixor:
1306 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1307 break;
1308 case nir_op_ishl:
1309 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1310 break;
1311 case nir_op_ishr:
1312 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1313 break;
1314 case nir_op_ushr:
1315 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1316 break;
1317 case nir_op_ilt:
1318 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1319 break;
1320 case nir_op_ine:
1321 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1322 break;
1323 case nir_op_ieq:
1324 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1325 break;
1326 case nir_op_ige:
1327 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1328 break;
1329 case nir_op_ult:
1330 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1331 break;
1332 case nir_op_uge:
1333 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1334 break;
1335 case nir_op_feq:
1336 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1337 break;
1338 case nir_op_fne:
1339 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1340 break;
1341 case nir_op_flt:
1342 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1343 break;
1344 case nir_op_fge:
1345 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1346 break;
1347 case nir_op_fabs:
1348 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1349 to_float_type(ctx, def_type), src[0]);
1350 break;
1351 case nir_op_iabs:
1352 result = emit_iabs(ctx, src[0]);
1353 break;
1354 case nir_op_imax:
1355 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1356 break;
1357 case nir_op_imin:
1358 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1359 break;
1360 case nir_op_umax:
1361 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1362 break;
1363 case nir_op_umin:
1364 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1365 break;
1366 case nir_op_isign:
1367 result = emit_isign(ctx, src[0]);
1368 break;
1369 case nir_op_fsign:
1370 src[0] = to_float(ctx, src[0]);
1371 result = emit_fsign(ctx, src[0]);
1372 break;
1373 case nir_op_ffloor:
1374 result = emit_intrin_1f_param(ctx, "llvm.floor",
1375 to_float_type(ctx, def_type), src[0]);
1376 break;
1377 case nir_op_ftrunc:
1378 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1379 to_float_type(ctx, def_type), src[0]);
1380 break;
1381 case nir_op_fceil:
1382 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1383 to_float_type(ctx, def_type), src[0]);
1384 break;
1385 case nir_op_fround_even:
1386 result = emit_intrin_1f_param(ctx, "llvm.rint",
1387 to_float_type(ctx, def_type),src[0]);
1388 break;
1389 case nir_op_ffract:
1390 result = emit_ffract(ctx, src[0]);
1391 break;
1392 case nir_op_fsin:
1393 result = emit_intrin_1f_param(ctx, "llvm.sin",
1394 to_float_type(ctx, def_type), src[0]);
1395 break;
1396 case nir_op_fcos:
1397 result = emit_intrin_1f_param(ctx, "llvm.cos",
1398 to_float_type(ctx, def_type), src[0]);
1399 break;
1400 case nir_op_fsqrt:
1401 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1402 to_float_type(ctx, def_type), src[0]);
1403 break;
1404 case nir_op_fexp2:
1405 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1406 to_float_type(ctx, def_type), src[0]);
1407 break;
1408 case nir_op_flog2:
1409 result = emit_intrin_1f_param(ctx, "llvm.log2",
1410 to_float_type(ctx, def_type), src[0]);
1411 break;
1412 case nir_op_frsq:
1413 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1414 to_float_type(ctx, def_type), src[0]);
1415 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1416 break;
1417 case nir_op_fpow:
1418 result = emit_intrin_2f_param(ctx, "llvm.pow",
1419 to_float_type(ctx, def_type), src[0], src[1]);
1420 break;
1421 case nir_op_fmax:
1422 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1423 to_float_type(ctx, def_type), src[0], src[1]);
1424 break;
1425 case nir_op_fmin:
1426 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1427 to_float_type(ctx, def_type), src[0], src[1]);
1428 break;
1429 case nir_op_ffma:
1430 result = emit_intrin_3f_param(ctx, "llvm.fma",
1431 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1432 break;
1433 case nir_op_ibitfield_extract:
1434 result = emit_bitfield_extract(ctx, true, src);
1435 break;
1436 case nir_op_ubitfield_extract:
1437 result = emit_bitfield_extract(ctx, false, src);
1438 break;
1439 case nir_op_bitfield_insert:
1440 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1441 break;
1442 case nir_op_bitfield_reverse:
1443 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1444 break;
1445 case nir_op_bit_count:
1446 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1447 break;
1448 case nir_op_vec2:
1449 case nir_op_vec3:
1450 case nir_op_vec4:
1451 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1452 src[i] = to_integer(ctx, src[i]);
1453 result = ac_build_gather_values(&ctx->ac, src, num_components);
1454 break;
1455 case nir_op_d2i:
1456 case nir_op_f2i:
1457 src[0] = to_float(ctx, src[0]);
1458 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1459 break;
1460 case nir_op_d2u:
1461 case nir_op_f2u:
1462 src[0] = to_float(ctx, src[0]);
1463 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1464 break;
1465 case nir_op_i2d:
1466 case nir_op_i2f:
1467 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1468 break;
1469 case nir_op_u2d:
1470 case nir_op_u2f:
1471 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1472 break;
1473 case nir_op_f2d:
1474 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1475 break;
1476 case nir_op_d2f:
1477 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1478 break;
1479 case nir_op_u2u32:
1480 case nir_op_u2u64:
1481 case nir_op_u2i32:
1482 case nir_op_u2i64:
1483 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1484 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1485 else
1486 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1487 break;
1488 case nir_op_i2u32:
1489 case nir_op_i2u64:
1490 case nir_op_i2i32:
1491 case nir_op_i2i64:
1492 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1493 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1494 else
1495 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1496 break;
1497 case nir_op_bcsel:
1498 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1499 break;
1500 case nir_op_find_lsb:
1501 result = emit_find_lsb(ctx, src[0]);
1502 break;
1503 case nir_op_ufind_msb:
1504 result = emit_ufind_msb(ctx, src[0]);
1505 break;
1506 case nir_op_ifind_msb:
1507 result = emit_ifind_msb(ctx, src[0]);
1508 break;
1509 case nir_op_uadd_carry:
1510 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1511 break;
1512 case nir_op_usub_borrow:
1513 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1514 break;
1515 case nir_op_b2f:
1516 result = emit_b2f(ctx, src[0]);
1517 break;
1518 case nir_op_fquantize2f16:
1519 src[0] = to_float(ctx, src[0]);
1520 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1521 /* need to convert back up to f32 */
1522 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1523 break;
1524 case nir_op_umul_high:
1525 result = emit_umul_high(ctx, src[0], src[1]);
1526 break;
1527 case nir_op_imul_high:
1528 result = emit_imul_high(ctx, src[0], src[1]);
1529 break;
1530 case nir_op_pack_half_2x16:
1531 result = emit_pack_half_2x16(ctx, src[0]);
1532 break;
1533 case nir_op_unpack_half_2x16:
1534 result = emit_unpack_half_2x16(ctx, src[0]);
1535 break;
1536 case nir_op_fddx:
1537 case nir_op_fddy:
1538 case nir_op_fddx_fine:
1539 case nir_op_fddy_fine:
1540 case nir_op_fddx_coarse:
1541 case nir_op_fddy_coarse:
1542 result = emit_ddxy(ctx, instr->op, src[0]);
1543 break;
1544 default:
1545 fprintf(stderr, "Unknown NIR alu instr: ");
1546 nir_print_instr(&instr->instr, stderr);
1547 fprintf(stderr, "\n");
1548 abort();
1549 }
1550
1551 if (result) {
1552 assert(instr->dest.dest.is_ssa);
1553 result = to_integer(ctx, result);
1554 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1555 result);
1556 }
1557 }
1558
1559 static void visit_load_const(struct nir_to_llvm_context *ctx,
1560 nir_load_const_instr *instr)
1561 {
1562 LLVMValueRef values[4], value = NULL;
1563 LLVMTypeRef element_type =
1564 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1565
1566 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1567 switch (instr->def.bit_size) {
1568 case 32:
1569 values[i] = LLVMConstInt(element_type,
1570 instr->value.u32[i], false);
1571 break;
1572 case 64:
1573 values[i] = LLVMConstInt(element_type,
1574 instr->value.u64[i], false);
1575 break;
1576 default:
1577 fprintf(stderr,
1578 "unsupported nir load_const bit_size: %d\n",
1579 instr->def.bit_size);
1580 abort();
1581 }
1582 }
1583 if (instr->def.num_components > 1) {
1584 value = LLVMConstVector(values, instr->def.num_components);
1585 } else
1586 value = values[0];
1587
1588 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1589 }
1590
1591 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1592 LLVMTypeRef type)
1593 {
1594 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1595 return LLVMBuildBitCast(ctx->builder, ptr,
1596 LLVMPointerType(type, addr_space), "");
1597 }
1598
1599 static LLVMValueRef
1600 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1601 {
1602 LLVMValueRef size =
1603 LLVMBuildExtractElement(ctx->builder, descriptor,
1604 LLVMConstInt(ctx->i32, 2, false), "");
1605
1606 /* VI only */
1607 if (ctx->options->chip_class >= VI && in_elements) {
1608 /* On VI, the descriptor contains the size in bytes,
1609 * but TXQ must return the size in elements.
1610 * The stride is always non-zero for resources using TXQ.
1611 */
1612 LLVMValueRef stride =
1613 LLVMBuildExtractElement(ctx->builder, descriptor,
1614 LLVMConstInt(ctx->i32, 1, false), "");
1615 stride = LLVMBuildLShr(ctx->builder, stride,
1616 LLVMConstInt(ctx->i32, 16, false), "");
1617 stride = LLVMBuildAnd(ctx->builder, stride,
1618 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1619
1620 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1621 }
1622 return size;
1623 }
1624
1625 /**
1626 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1627 * intrinsic names).
1628 */
1629 static void build_int_type_name(
1630 LLVMTypeRef type,
1631 char *buf, unsigned bufsize)
1632 {
1633 assert(bufsize >= 6);
1634
1635 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1636 snprintf(buf, bufsize, "v%ui32",
1637 LLVMGetVectorSize(type));
1638 else
1639 strcpy(buf, "i32");
1640 }
1641
1642 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1643 struct ac_tex_info *tinfo,
1644 nir_tex_instr *instr,
1645 const char *intr_name,
1646 unsigned coord_vgpr_index)
1647 {
1648 LLVMValueRef coord = tinfo->args[0];
1649 LLVMValueRef half_texel[2];
1650 int c;
1651
1652 //TODO Rect
1653 {
1654 LLVMValueRef txq_args[10];
1655 int txq_arg_count = 0;
1656 LLVMValueRef size;
1657 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1658 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, false);
1659 txq_args[txq_arg_count++] = tinfo->args[1];
1660 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0xf, 0); /* dmask */
1661 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* unorm */
1662 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
1663 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
1664 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
1665 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
1666 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
1667 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
1668 size = ac_build_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
1669 txq_args, txq_arg_count,
1670 AC_FUNC_ATTR_READNONE |
1671 AC_FUNC_ATTR_LEGACY);
1672
1673 for (c = 0; c < 2; c++) {
1674 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1675 LLVMConstInt(ctx->i32, c, false), "");
1676 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1677 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1678 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1679 LLVMConstReal(ctx->f32, -0.5), "");
1680 }
1681 }
1682
1683 for (c = 0; c < 2; c++) {
1684 LLVMValueRef tmp;
1685 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1686 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1687 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1688 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1689 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1690 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1691 }
1692
1693 tinfo->args[0] = coord;
1694 return ac_build_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1695 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND |
1696 AC_FUNC_ATTR_LEGACY);
1697
1698 }
1699
1700 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1701 nir_tex_instr *instr,
1702 struct ac_tex_info *tinfo)
1703 {
1704 const char *name = "llvm.SI.image.sample";
1705 const char *infix = "";
1706 char intr_name[127];
1707 char type[64];
1708 bool is_shadow = instr->is_shadow;
1709 bool has_offset = tinfo->has_offset;
1710 switch (instr->op) {
1711 case nir_texop_txf:
1712 case nir_texop_txf_ms:
1713 case nir_texop_samples_identical:
1714 name = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? "llvm.SI.image.load" :
1715 instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? "llvm.SI.vs.load.input" :
1716 "llvm.SI.image.load.mip";
1717 is_shadow = false;
1718 has_offset = false;
1719 break;
1720 case nir_texop_txb:
1721 infix = ".b";
1722 break;
1723 case nir_texop_txl:
1724 infix = ".l";
1725 break;
1726 case nir_texop_txs:
1727 name = "llvm.SI.getresinfo";
1728 break;
1729 case nir_texop_query_levels:
1730 name = "llvm.SI.getresinfo";
1731 break;
1732 case nir_texop_tex:
1733 if (ctx->stage != MESA_SHADER_FRAGMENT)
1734 infix = ".lz";
1735 break;
1736 case nir_texop_txd:
1737 infix = ".d";
1738 break;
1739 case nir_texop_tg4:
1740 name = "llvm.SI.gather4";
1741 infix = ".lz";
1742 break;
1743 case nir_texop_lod:
1744 name = "llvm.SI.getlod";
1745 is_shadow = false;
1746 has_offset = false;
1747 break;
1748 default:
1749 break;
1750 }
1751
1752 build_int_type_name(LLVMTypeOf(tinfo->args[0]), type, sizeof(type));
1753 sprintf(intr_name, "%s%s%s%s.%s", name, is_shadow ? ".c" : "", infix,
1754 has_offset ? ".o" : "", type);
1755
1756 if (instr->op == nir_texop_tg4) {
1757 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1758 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1759 return radv_lower_gather4_integer(ctx, tinfo, instr, intr_name,
1760 (int)has_offset + (int)is_shadow);
1761 }
1762 }
1763 return ac_build_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1764 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND |
1765 AC_FUNC_ATTR_LEGACY);
1766
1767 }
1768
1769 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1770 nir_intrinsic_instr *instr)
1771 {
1772 LLVMValueRef index = get_src(ctx, instr->src[0]);
1773 unsigned desc_set = nir_intrinsic_desc_set(instr);
1774 unsigned binding = nir_intrinsic_binding(instr);
1775 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1776 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
1777 unsigned base_offset = layout->binding[binding].offset;
1778 LLVMValueRef offset, stride;
1779
1780 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1781 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1782 desc_ptr = ctx->push_constants;
1783 base_offset = ctx->options->layout->push_constant_size;
1784 base_offset += 16 * layout->binding[binding].dynamic_offset_offset;
1785 stride = LLVMConstInt(ctx->i32, 16, false);
1786 } else
1787 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1788
1789 offset = LLVMConstInt(ctx->i32, base_offset, false);
1790 index = LLVMBuildMul(ctx->builder, index, stride, "");
1791 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1792
1793 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1794 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1795 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1796
1797 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1798 }
1799
1800 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1801 nir_intrinsic_instr *instr)
1802 {
1803 LLVMValueRef ptr, addr;
1804
1805 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1806 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1807
1808 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
1809 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1810
1811 return LLVMBuildLoad(ctx->builder, ptr, "");
1812 }
1813
1814 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1815 nir_intrinsic_instr *instr)
1816 {
1817 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1818
1819 return get_buffer_size(ctx, desc, false);
1820 }
1821 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1822 nir_intrinsic_instr *instr)
1823 {
1824 const char *store_name;
1825 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
1826 LLVMTypeRef data_type = ctx->f32;
1827 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
1828 int components_32bit = elem_size_mult * instr->num_components;
1829 unsigned writemask = nir_intrinsic_write_mask(instr);
1830 LLVMValueRef base_data, base_offset;
1831 LLVMValueRef params[6];
1832
1833 if (ctx->stage == MESA_SHADER_FRAGMENT)
1834 ctx->shader_info->fs.writes_memory = true;
1835
1836 params[1] = get_src(ctx, instr->src[1]);
1837 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1838 params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
1839 params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1840
1841 if (components_32bit > 1)
1842 data_type = LLVMVectorType(ctx->f32, components_32bit);
1843
1844 base_data = to_float(ctx, src_data);
1845 base_data = trim_vector(ctx, base_data, instr->num_components);
1846 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1847 data_type, "");
1848 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1849 while (writemask) {
1850 int start, count;
1851 LLVMValueRef data;
1852 LLVMValueRef offset;
1853 LLVMValueRef tmp;
1854 u_bit_scan_consecutive_range(&writemask, &start, &count);
1855
1856 /* Due to an LLVM limitation, split 3-element writes
1857 * into a 2-element and a 1-element write. */
1858 if (count == 3) {
1859 writemask |= 1 << (start + 2);
1860 count = 2;
1861 }
1862
1863 start *= elem_size_mult;
1864 count *= elem_size_mult;
1865
1866 if (count > 4) {
1867 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
1868 count = 4;
1869 }
1870
1871 if (count == 4) {
1872 store_name = "llvm.amdgcn.buffer.store.v4f32";
1873 data = base_data;
1874 } else if (count == 2) {
1875 tmp = LLVMBuildExtractElement(ctx->builder,
1876 base_data, LLVMConstInt(ctx->i32, start, false), "");
1877 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
1878 ctx->i32zero, "");
1879
1880 tmp = LLVMBuildExtractElement(ctx->builder,
1881 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
1882 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
1883 ctx->i32one, "");
1884 store_name = "llvm.amdgcn.buffer.store.v2f32";
1885
1886 } else {
1887 assert(count == 1);
1888 if (get_llvm_num_components(base_data) > 1)
1889 data = LLVMBuildExtractElement(ctx->builder, base_data,
1890 LLVMConstInt(ctx->i32, start, false), "");
1891 else
1892 data = base_data;
1893 store_name = "llvm.amdgcn.buffer.store.f32";
1894 }
1895
1896 offset = base_offset;
1897 if (start != 0) {
1898 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
1899 }
1900 params[0] = data;
1901 params[3] = offset;
1902 ac_build_intrinsic(&ctx->ac, store_name,
1903 ctx->voidt, params, 6, 0);
1904 }
1905 }
1906
1907 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
1908 nir_intrinsic_instr *instr)
1909 {
1910 const char *name;
1911 LLVMValueRef params[6];
1912 int arg_count = 0;
1913 if (ctx->stage == MESA_SHADER_FRAGMENT)
1914 ctx->shader_info->fs.writes_memory = true;
1915
1916 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
1917 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
1918 }
1919 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
1920 params[arg_count++] = get_src(ctx, instr->src[0]);
1921 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1922 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
1923 params[arg_count++] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1924
1925 switch (instr->intrinsic) {
1926 case nir_intrinsic_ssbo_atomic_add:
1927 name = "llvm.amdgcn.buffer.atomic.add";
1928 break;
1929 case nir_intrinsic_ssbo_atomic_imin:
1930 name = "llvm.amdgcn.buffer.atomic.smin";
1931 break;
1932 case nir_intrinsic_ssbo_atomic_umin:
1933 name = "llvm.amdgcn.buffer.atomic.umin";
1934 break;
1935 case nir_intrinsic_ssbo_atomic_imax:
1936 name = "llvm.amdgcn.buffer.atomic.smax";
1937 break;
1938 case nir_intrinsic_ssbo_atomic_umax:
1939 name = "llvm.amdgcn.buffer.atomic.umax";
1940 break;
1941 case nir_intrinsic_ssbo_atomic_and:
1942 name = "llvm.amdgcn.buffer.atomic.and";
1943 break;
1944 case nir_intrinsic_ssbo_atomic_or:
1945 name = "llvm.amdgcn.buffer.atomic.or";
1946 break;
1947 case nir_intrinsic_ssbo_atomic_xor:
1948 name = "llvm.amdgcn.buffer.atomic.xor";
1949 break;
1950 case nir_intrinsic_ssbo_atomic_exchange:
1951 name = "llvm.amdgcn.buffer.atomic.swap";
1952 break;
1953 case nir_intrinsic_ssbo_atomic_comp_swap:
1954 name = "llvm.amdgcn.buffer.atomic.cmpswap";
1955 break;
1956 default:
1957 abort();
1958 }
1959
1960 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
1961 }
1962
1963 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
1964 nir_intrinsic_instr *instr)
1965 {
1966 LLVMValueRef results[2];
1967 int load_components;
1968 int num_components = instr->num_components;
1969 if (instr->dest.ssa.bit_size == 64)
1970 num_components *= 2;
1971
1972 for (int i = 0; i < num_components; i += load_components) {
1973 load_components = MIN2(num_components - i, 4);
1974 const char *load_name;
1975 LLVMTypeRef data_type = ctx->f32;
1976 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
1977 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
1978
1979 if (load_components == 3)
1980 data_type = LLVMVectorType(ctx->f32, 4);
1981 else if (load_components > 1)
1982 data_type = LLVMVectorType(ctx->f32, load_components);
1983
1984 if (load_components >= 3)
1985 load_name = "llvm.amdgcn.buffer.load.v4f32";
1986 else if (load_components == 2)
1987 load_name = "llvm.amdgcn.buffer.load.v2f32";
1988 else if (load_components == 1)
1989 load_name = "llvm.amdgcn.buffer.load.f32";
1990 else
1991 unreachable("unhandled number of components");
1992
1993 LLVMValueRef params[] = {
1994 get_src(ctx, instr->src[0]),
1995 LLVMConstInt(ctx->i32, 0, false),
1996 offset,
1997 LLVMConstInt(ctx->i1, 0, false),
1998 LLVMConstInt(ctx->i1, 0, false),
1999 };
2000
2001 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2002
2003 }
2004
2005 LLVMValueRef ret = results[0];
2006 if (num_components > 4 || num_components == 3) {
2007 LLVMValueRef masks[] = {
2008 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2009 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2010 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2011 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2012 };
2013
2014 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2015 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2016 results[num_components > 4 ? 1 : 0], swizzle, "");
2017 }
2018
2019 return LLVMBuildBitCast(ctx->builder, ret,
2020 get_def_type(ctx, &instr->dest.ssa), "");
2021 }
2022
2023 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2024 nir_intrinsic_instr *instr)
2025 {
2026 LLVMValueRef results[8], ret;
2027 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2028 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2029 int num_components = instr->num_components;
2030
2031 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2032
2033 if (instr->dest.ssa.bit_size == 64)
2034 num_components *= 2;
2035
2036 for (unsigned i = 0; i < num_components; ++i) {
2037 LLVMValueRef params[] = {
2038 rsrc,
2039 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2040 offset, "")
2041 };
2042 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2043 params, 2,
2044 AC_FUNC_ATTR_READNONE |
2045 AC_FUNC_ATTR_LEGACY);
2046 }
2047
2048
2049 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2050 return LLVMBuildBitCast(ctx->builder, ret,
2051 get_def_type(ctx, &instr->dest.ssa), "");
2052 }
2053
2054 static void
2055 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2056 bool vs_in, unsigned *vertex_index_out,
2057 unsigned *const_out, LLVMValueRef *indir_out)
2058 {
2059 unsigned const_offset = 0;
2060 LLVMValueRef offset = NULL;
2061
2062 if (vertex_index_out != NULL) {
2063 tail = tail->child;
2064 nir_deref_array *deref_array = nir_deref_as_array(tail);
2065 *vertex_index_out = deref_array->base_offset;
2066 }
2067
2068 while (tail->child != NULL) {
2069 const struct glsl_type *parent_type = tail->type;
2070 tail = tail->child;
2071
2072 if (tail->deref_type == nir_deref_type_array) {
2073 nir_deref_array *deref_array = nir_deref_as_array(tail);
2074 LLVMValueRef index, stride, local_offset;
2075 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2076
2077 const_offset += size * deref_array->base_offset;
2078 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2079 continue;
2080
2081 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2082 index = get_src(ctx, deref_array->indirect);
2083 stride = LLVMConstInt(ctx->i32, size, 0);
2084 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2085
2086 if (offset)
2087 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2088 else
2089 offset = local_offset;
2090 } else if (tail->deref_type == nir_deref_type_struct) {
2091 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2092
2093 for (unsigned i = 0; i < deref_struct->index; i++) {
2094 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2095 const_offset += glsl_count_attribute_slots(ft, vs_in);
2096 }
2097 } else
2098 unreachable("unsupported deref type");
2099
2100 }
2101
2102 if (const_offset && offset)
2103 offset = LLVMBuildAdd(ctx->builder, offset,
2104 LLVMConstInt(ctx->i32, const_offset, 0),
2105 "");
2106
2107 *const_out = const_offset;
2108 *indir_out = offset;
2109 }
2110
2111 static LLVMValueRef
2112 load_gs_input(struct nir_to_llvm_context *ctx,
2113 nir_intrinsic_instr *instr)
2114 {
2115 LLVMValueRef indir_index, vtx_offset;
2116 unsigned const_index;
2117 LLVMValueRef args[9];
2118 unsigned param, vtx_offset_param;
2119 LLVMValueRef value[4], result;
2120 unsigned vertex_index;
2121 unsigned cull_offset = 0;
2122 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2123 false, &vertex_index,
2124 &const_index, &indir_index);
2125 vtx_offset_param = vertex_index;
2126 assert(vtx_offset_param < 6);
2127 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2128 LLVMConstInt(ctx->i32, 4, false), "");
2129
2130 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2131 if (instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2132 cull_offset += ctx->num_input_clips;
2133 for (unsigned i = 0; i < instr->num_components; i++) {
2134
2135 args[0] = ctx->esgs_ring;
2136 args[1] = vtx_offset;
2137 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index + cull_offset) * 256, false);
2138 args[3] = ctx->i32zero;
2139 args[4] = ctx->i32one; /* OFFEN */
2140 args[5] = ctx->i32zero; /* IDXEN */
2141 args[6] = ctx->i32one; /* GLC */
2142 args[7] = ctx->i32zero; /* SLC */
2143 args[8] = ctx->i32zero; /* TFE */
2144
2145 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2146 ctx->i32, args, 9,
2147 AC_FUNC_ATTR_READONLY |
2148 AC_FUNC_ATTR_LEGACY);
2149 }
2150 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2151
2152 return result;
2153 }
2154
2155 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2156 nir_intrinsic_instr *instr)
2157 {
2158 LLVMValueRef values[8];
2159 int idx = instr->variables[0]->var->data.driver_location;
2160 int ve = instr->dest.ssa.num_components;
2161 LLVMValueRef indir_index;
2162 LLVMValueRef ret;
2163 unsigned const_index;
2164 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2165 instr->variables[0]->var->data.mode == nir_var_shader_in;
2166 radv_get_deref_offset(ctx, &instr->variables[0]->deref, vs_in, NULL,
2167 &const_index, &indir_index);
2168
2169 if (instr->dest.ssa.bit_size == 64)
2170 ve *= 2;
2171
2172 switch (instr->variables[0]->var->data.mode) {
2173 case nir_var_shader_in:
2174 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2175 return load_gs_input(ctx, instr);
2176 }
2177 for (unsigned chan = 0; chan < ve; chan++) {
2178 if (indir_index) {
2179 unsigned count = glsl_count_attribute_slots(
2180 instr->variables[0]->var->type,
2181 ctx->stage == MESA_SHADER_VERTEX);
2182 count -= chan / 4;
2183 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2184 &ctx->ac, ctx->inputs + idx + chan, count,
2185 4, false);
2186
2187 values[chan] = LLVMBuildExtractElement(ctx->builder,
2188 tmp_vec,
2189 indir_index, "");
2190 } else
2191 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2192 }
2193 break;
2194 case nir_var_local:
2195 for (unsigned chan = 0; chan < ve; chan++) {
2196 if (indir_index) {
2197 unsigned count = glsl_count_attribute_slots(
2198 instr->variables[0]->var->type, false);
2199 count -= chan / 4;
2200 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2201 &ctx->ac, ctx->locals + idx + chan, count,
2202 4, true);
2203
2204 values[chan] = LLVMBuildExtractElement(ctx->builder,
2205 tmp_vec,
2206 indir_index, "");
2207 } else {
2208 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2209 }
2210 }
2211 break;
2212 case nir_var_shader_out:
2213 for (unsigned chan = 0; chan < ve; chan++) {
2214 if (indir_index) {
2215 unsigned count = glsl_count_attribute_slots(
2216 instr->variables[0]->var->type, false);
2217 count -= chan / 4;
2218 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2219 &ctx->ac, ctx->outputs + idx + chan, count,
2220 4, true);
2221
2222 values[chan] = LLVMBuildExtractElement(ctx->builder,
2223 tmp_vec,
2224 indir_index, "");
2225 } else {
2226 values[chan] = LLVMBuildLoad(ctx->builder,
2227 ctx->outputs[idx + chan + const_index * 4],
2228 "");
2229 }
2230 }
2231 break;
2232 case nir_var_shared: {
2233 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2234 LLVMValueRef derived_ptr;
2235
2236 if (indir_index)
2237 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2238
2239 for (unsigned chan = 0; chan < ve; chan++) {
2240 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2241 if (indir_index)
2242 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2243 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2244
2245 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2246 }
2247 break;
2248 }
2249 default:
2250 unreachable("unhandle variable mode");
2251 }
2252 ret = ac_build_gather_values(&ctx->ac, values, ve);
2253 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2254 }
2255
2256 static void
2257 visit_store_var(struct nir_to_llvm_context *ctx,
2258 nir_intrinsic_instr *instr)
2259 {
2260 LLVMValueRef temp_ptr, value;
2261 int idx = instr->variables[0]->var->data.driver_location;
2262 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2263 int writemask = instr->const_index[0];
2264 LLVMValueRef indir_index;
2265 unsigned const_index;
2266 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2267 NULL, &const_index, &indir_index);
2268
2269 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2270 int old_writemask = writemask;
2271
2272 src = LLVMBuildBitCast(ctx->builder, src,
2273 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2274 "");
2275
2276 writemask = 0;
2277 for (unsigned chan = 0; chan < 4; chan++) {
2278 if (old_writemask & (1 << chan))
2279 writemask |= 3u << (2 * chan);
2280 }
2281 }
2282
2283 switch (instr->variables[0]->var->data.mode) {
2284 case nir_var_shader_out:
2285 for (unsigned chan = 0; chan < 8; chan++) {
2286 int stride = 4;
2287 if (!(writemask & (1 << chan)))
2288 continue;
2289
2290 value = llvm_extract_elem(ctx, src, chan);
2291
2292 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2293 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2294 stride = 1;
2295 if (indir_index) {
2296 unsigned count = glsl_count_attribute_slots(
2297 instr->variables[0]->var->type, false);
2298 count -= chan / 4;
2299 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2300 &ctx->ac, ctx->outputs + idx + chan, count,
2301 stride, true);
2302
2303 if (get_llvm_num_components(tmp_vec) > 1) {
2304 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2305 value, indir_index, "");
2306 } else
2307 tmp_vec = value;
2308 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2309 count, stride, tmp_vec);
2310
2311 } else {
2312 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2313
2314 LLVMBuildStore(ctx->builder, value, temp_ptr);
2315 }
2316 }
2317 break;
2318 case nir_var_local:
2319 for (unsigned chan = 0; chan < 8; chan++) {
2320 if (!(writemask & (1 << chan)))
2321 continue;
2322
2323 value = llvm_extract_elem(ctx, src, chan);
2324 if (indir_index) {
2325 unsigned count = glsl_count_attribute_slots(
2326 instr->variables[0]->var->type, false);
2327 count -= chan / 4;
2328 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2329 &ctx->ac, ctx->locals + idx + chan, count,
2330 4, true);
2331
2332 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2333 value, indir_index, "");
2334 build_store_values_extended(ctx, ctx->locals + idx + chan,
2335 count, 4, tmp_vec);
2336 } else {
2337 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2338
2339 LLVMBuildStore(ctx->builder, value, temp_ptr);
2340 }
2341 }
2342 break;
2343 case nir_var_shared: {
2344 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2345
2346 if (indir_index)
2347 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2348
2349 for (unsigned chan = 0; chan < 8; chan++) {
2350 if (!(writemask & (1 << chan)))
2351 continue;
2352 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2353 LLVMValueRef derived_ptr;
2354
2355 if (indir_index)
2356 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2357
2358 value = llvm_extract_elem(ctx, src, chan);
2359 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2360 LLVMBuildStore(ctx->builder,
2361 to_integer(ctx, value), derived_ptr);
2362 }
2363 break;
2364 }
2365 default:
2366 break;
2367 }
2368 }
2369
2370 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2371 {
2372 switch (dim) {
2373 case GLSL_SAMPLER_DIM_BUF:
2374 return 1;
2375 case GLSL_SAMPLER_DIM_1D:
2376 return array ? 2 : 1;
2377 case GLSL_SAMPLER_DIM_2D:
2378 return array ? 3 : 2;
2379 case GLSL_SAMPLER_DIM_MS:
2380 return array ? 4 : 3;
2381 case GLSL_SAMPLER_DIM_3D:
2382 case GLSL_SAMPLER_DIM_CUBE:
2383 return 3;
2384 case GLSL_SAMPLER_DIM_RECT:
2385 case GLSL_SAMPLER_DIM_SUBPASS:
2386 return 2;
2387 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2388 return 3;
2389 default:
2390 break;
2391 }
2392 return 0;
2393 }
2394
2395
2396 static void get_image_intr_name(const char *base_name,
2397 LLVMTypeRef data_type,
2398 LLVMTypeRef coords_type,
2399 LLVMTypeRef rsrc_type,
2400 char *out_name, unsigned out_len)
2401 {
2402 char coords_type_name[8];
2403
2404 ac_build_type_name_for_intr(coords_type, coords_type_name,
2405 sizeof(coords_type_name));
2406
2407 if (HAVE_LLVM <= 0x0309) {
2408 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
2409 } else {
2410 char data_type_name[8];
2411 char rsrc_type_name[8];
2412
2413 ac_build_type_name_for_intr(data_type, data_type_name,
2414 sizeof(data_type_name));
2415 ac_build_type_name_for_intr(rsrc_type, rsrc_type_name,
2416 sizeof(rsrc_type_name));
2417 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
2418 data_type_name, coords_type_name, rsrc_type_name);
2419 }
2420 }
2421
2422 /* Adjust the sample index according to FMASK.
2423 *
2424 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2425 * which is the identity mapping. Each nibble says which physical sample
2426 * should be fetched to get that sample.
2427 *
2428 * For example, 0x11111100 means there are only 2 samples stored and
2429 * the second sample covers 3/4 of the pixel. When reading samples 0
2430 * and 1, return physical sample 0 (determined by the first two 0s
2431 * in FMASK), otherwise return physical sample 1.
2432 *
2433 * The sample index should be adjusted as follows:
2434 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2435 */
2436 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
2437 LLVMValueRef coord_x, LLVMValueRef coord_y,
2438 LLVMValueRef coord_z,
2439 LLVMValueRef sample_index,
2440 LLVMValueRef fmask_desc_ptr)
2441 {
2442 LLVMValueRef fmask_load_address[4], params[7];
2443 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2444 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2445 LLVMValueRef da = coord_z ? ctx->i32one : ctx->i32zero;
2446 LLVMValueRef res;
2447 char intrinsic_name[64];
2448
2449 fmask_load_address[0] = coord_x;
2450 fmask_load_address[1] = coord_y;
2451 if (coord_z) {
2452 fmask_load_address[2] = coord_z;
2453 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
2454 }
2455
2456 params[0] = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
2457 params[1] = fmask_desc_ptr;
2458 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2459 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2460 params[3] = glc;
2461 params[4] = slc;
2462 params[5] = lwe;
2463 params[6] = da;
2464
2465 get_image_intr_name("llvm.amdgcn.image.load",
2466 ctx->v4f32, /* vdata */
2467 LLVMTypeOf(params[0]), /* coords */
2468 LLVMTypeOf(params[1]), /* rsrc */
2469 intrinsic_name, sizeof(intrinsic_name));
2470
2471 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2472 params, 7, AC_FUNC_ATTR_READONLY);
2473
2474 res = to_integer(ctx, res);
2475 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
2476 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
2477
2478 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
2479 res,
2480 ctx->i32zero, "");
2481
2482 LLVMValueRef sample_index4 =
2483 LLVMBuildMul(ctx->builder, sample_index, four, "");
2484 LLVMValueRef shifted_fmask =
2485 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
2486 LLVMValueRef final_sample =
2487 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
2488
2489 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2490 * resource descriptor is 0 (invalid),
2491 */
2492 LLVMValueRef fmask_desc =
2493 LLVMBuildBitCast(ctx->builder, params[1],
2494 ctx->v8i32, "");
2495
2496 LLVMValueRef fmask_word1 =
2497 LLVMBuildExtractElement(ctx->builder, fmask_desc,
2498 ctx->i32one, "");
2499
2500 LLVMValueRef word1_is_nonzero =
2501 LLVMBuildICmp(ctx->builder, LLVMIntNE,
2502 fmask_word1, ctx->i32zero, "");
2503
2504 /* Replace the MSAA sample index. */
2505 sample_index =
2506 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
2507 final_sample, sample_index, "");
2508 return sample_index;
2509 }
2510
2511 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2512 nir_intrinsic_instr *instr)
2513 {
2514 const struct glsl_type *type = instr->variables[0]->var->type;
2515 if(instr->variables[0]->deref.child)
2516 type = instr->variables[0]->deref.child->type;
2517
2518 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2519 LLVMValueRef coords[4];
2520 LLVMValueRef masks[] = {
2521 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2522 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2523 };
2524 LLVMValueRef res;
2525 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2526
2527 int count;
2528 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2529 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2530 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2531 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2532 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2533
2534 count = image_type_to_components_count(dim,
2535 glsl_sampler_type_is_array(type));
2536
2537 if (is_ms) {
2538 LLVMValueRef fmask_load_address[3];
2539 int chan;
2540
2541 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2542 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
2543 if (glsl_sampler_type_is_array(type))
2544 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
2545 else
2546 fmask_load_address[2] = NULL;
2547 if (add_frag_pos) {
2548 for (chan = 0; chan < 2; ++chan)
2549 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2550 }
2551 sample_index = adjust_sample_index_using_fmask(ctx,
2552 fmask_load_address[0],
2553 fmask_load_address[1],
2554 fmask_load_address[2],
2555 sample_index,
2556 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
2557 }
2558 if (count == 1) {
2559 if (instr->src[0].ssa->num_components)
2560 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2561 else
2562 res = src0;
2563 } else {
2564 int chan;
2565 if (is_ms)
2566 count--;
2567 for (chan = 0; chan < count; ++chan) {
2568 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2569 }
2570
2571 if (add_frag_pos) {
2572 for (chan = 0; chan < count; ++chan)
2573 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2574 }
2575 if (is_ms) {
2576 coords[count] = sample_index;
2577 count++;
2578 }
2579
2580 if (count == 3) {
2581 coords[3] = LLVMGetUndef(ctx->i32);
2582 count = 4;
2583 }
2584 res = ac_build_gather_values(&ctx->ac, coords, count);
2585 }
2586 return res;
2587 }
2588
2589 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2590 nir_intrinsic_instr *instr)
2591 {
2592 LLVMValueRef params[7];
2593 LLVMValueRef res;
2594 char intrinsic_name[64];
2595 const nir_variable *var = instr->variables[0]->var;
2596 const struct glsl_type *type = var->type;
2597 if(instr->variables[0]->deref.child)
2598 type = instr->variables[0]->deref.child->type;
2599
2600 type = glsl_without_array(type);
2601 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2602 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2603 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2604 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2605 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2606 params[3] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2607 params[4] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2608 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2609 params, 5, 0);
2610
2611 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2612 res = to_integer(ctx, res);
2613 } else {
2614 bool is_da = glsl_sampler_type_is_array(type) ||
2615 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2616 LLVMValueRef da = is_da ? ctx->i32one : ctx->i32zero;
2617 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2618 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2619
2620 params[0] = get_image_coords(ctx, instr);
2621 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2622 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2623 if (HAVE_LLVM <= 0x0309) {
2624 params[3] = LLVMConstInt(ctx->i1, 0, false); /* r128 */
2625 params[4] = da;
2626 params[5] = glc;
2627 params[6] = slc;
2628 } else {
2629 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2630 params[3] = glc;
2631 params[4] = slc;
2632 params[5] = lwe;
2633 params[6] = da;
2634 }
2635
2636 get_image_intr_name("llvm.amdgcn.image.load",
2637 ctx->v4f32, /* vdata */
2638 LLVMTypeOf(params[0]), /* coords */
2639 LLVMTypeOf(params[1]), /* rsrc */
2640 intrinsic_name, sizeof(intrinsic_name));
2641
2642 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2643 params, 7, AC_FUNC_ATTR_READONLY);
2644 }
2645 return to_integer(ctx, res);
2646 }
2647
2648 static void visit_image_store(struct nir_to_llvm_context *ctx,
2649 nir_intrinsic_instr *instr)
2650 {
2651 LLVMValueRef params[8];
2652 char intrinsic_name[64];
2653 const nir_variable *var = instr->variables[0]->var;
2654 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2655 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2656 const struct glsl_type *type = glsl_without_array(var->type);
2657
2658 if (ctx->stage == MESA_SHADER_FRAGMENT)
2659 ctx->shader_info->fs.writes_memory = true;
2660
2661 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2662 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2663 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2664 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2665 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2666 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2667 params[4] = i1false; /* glc */
2668 params[5] = i1false; /* slc */
2669 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2670 params, 6, 0);
2671 } else {
2672 bool is_da = glsl_sampler_type_is_array(type) ||
2673 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2674 LLVMValueRef da = is_da ? i1true : i1false;
2675 LLVMValueRef glc = i1false;
2676 LLVMValueRef slc = i1false;
2677
2678 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2679 params[1] = get_image_coords(ctx, instr); /* coords */
2680 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2681 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2682 if (HAVE_LLVM <= 0x0309) {
2683 params[4] = i1false; /* r128 */
2684 params[5] = da;
2685 params[6] = glc;
2686 params[7] = slc;
2687 } else {
2688 LLVMValueRef lwe = i1false;
2689 params[4] = glc;
2690 params[5] = slc;
2691 params[6] = lwe;
2692 params[7] = da;
2693 }
2694
2695 get_image_intr_name("llvm.amdgcn.image.store",
2696 LLVMTypeOf(params[0]), /* vdata */
2697 LLVMTypeOf(params[1]), /* coords */
2698 LLVMTypeOf(params[2]), /* rsrc */
2699 intrinsic_name, sizeof(intrinsic_name));
2700
2701 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2702 params, 8, 0);
2703 }
2704
2705 }
2706
2707 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2708 nir_intrinsic_instr *instr)
2709 {
2710 LLVMValueRef params[6];
2711 int param_count = 0;
2712 const nir_variable *var = instr->variables[0]->var;
2713 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2714 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2715 const char *base_name = "llvm.amdgcn.image.atomic";
2716 const char *atomic_name;
2717 LLVMValueRef coords;
2718 char intrinsic_name[32], coords_type[8];
2719 const struct glsl_type *type = glsl_without_array(var->type);
2720
2721 if (ctx->stage == MESA_SHADER_FRAGMENT)
2722 ctx->shader_info->fs.writes_memory = true;
2723
2724 params[param_count++] = get_src(ctx, instr->src[2]);
2725 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2726 params[param_count++] = get_src(ctx, instr->src[3]);
2727
2728 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2729 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2730 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2731 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2732 params[param_count++] = ctx->i32zero; /* voffset */
2733 params[param_count++] = i1false; /* glc */
2734 params[param_count++] = i1false; /* slc */
2735 } else {
2736 bool da = glsl_sampler_type_is_array(type) ||
2737 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2738
2739 coords = params[param_count++] = get_image_coords(ctx, instr);
2740 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2741 params[param_count++] = i1false; /* r128 */
2742 params[param_count++] = da ? i1true : i1false; /* da */
2743 params[param_count++] = i1false; /* slc */
2744 }
2745
2746 switch (instr->intrinsic) {
2747 case nir_intrinsic_image_atomic_add:
2748 atomic_name = "add";
2749 break;
2750 case nir_intrinsic_image_atomic_min:
2751 atomic_name = "smin";
2752 break;
2753 case nir_intrinsic_image_atomic_max:
2754 atomic_name = "smax";
2755 break;
2756 case nir_intrinsic_image_atomic_and:
2757 atomic_name = "and";
2758 break;
2759 case nir_intrinsic_image_atomic_or:
2760 atomic_name = "or";
2761 break;
2762 case nir_intrinsic_image_atomic_xor:
2763 atomic_name = "xor";
2764 break;
2765 case nir_intrinsic_image_atomic_exchange:
2766 atomic_name = "swap";
2767 break;
2768 case nir_intrinsic_image_atomic_comp_swap:
2769 atomic_name = "cmpswap";
2770 break;
2771 default:
2772 abort();
2773 }
2774 build_int_type_name(LLVMTypeOf(coords),
2775 coords_type, sizeof(coords_type));
2776
2777 snprintf(intrinsic_name, sizeof(intrinsic_name),
2778 "%s.%s.%s", base_name, atomic_name, coords_type);
2779 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2780 }
2781
2782 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2783 nir_intrinsic_instr *instr)
2784 {
2785 LLVMValueRef res;
2786 LLVMValueRef params[10];
2787 const nir_variable *var = instr->variables[0]->var;
2788 const struct glsl_type *type = instr->variables[0]->var->type;
2789 bool da = glsl_sampler_type_is_array(var->type) ||
2790 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2791 if(instr->variables[0]->deref.child)
2792 type = instr->variables[0]->deref.child->type;
2793
2794 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2795 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2796 params[0] = ctx->i32zero;
2797 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2798 params[2] = LLVMConstInt(ctx->i32, 15, false);
2799 params[3] = ctx->i32zero;
2800 params[4] = ctx->i32zero;
2801 params[5] = da ? ctx->i32one : ctx->i32zero;
2802 params[6] = ctx->i32zero;
2803 params[7] = ctx->i32zero;
2804 params[8] = ctx->i32zero;
2805 params[9] = ctx->i32zero;
2806
2807 res = ac_build_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
2808 params, 10,
2809 AC_FUNC_ATTR_READNONE |
2810 AC_FUNC_ATTR_LEGACY);
2811
2812 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2813 glsl_sampler_type_is_array(type)) {
2814 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2815 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2816 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2817 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2818 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2819 }
2820 return res;
2821 }
2822
2823 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2824 {
2825 LLVMValueRef args[1] = {
2826 LLVMConstInt(ctx->i32, 0xf70, false),
2827 };
2828 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2829 ctx->voidt, args, 1, 0);
2830 }
2831
2832 static void emit_barrier(struct nir_to_llvm_context *ctx)
2833 {
2834 // TODO tess
2835 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2836 ctx->voidt, NULL, 0, 0);
2837 }
2838
2839 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2840 nir_intrinsic_instr *instr)
2841 {
2842 LLVMValueRef cond;
2843 ctx->shader_info->fs.can_discard = true;
2844
2845 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2846 get_src(ctx, instr->src[0]),
2847 ctx->i32zero, "");
2848
2849 cond = LLVMBuildSelect(ctx->builder, cond,
2850 LLVMConstReal(ctx->f32, -1.0f),
2851 ctx->f32zero, "");
2852 ac_build_kill(&ctx->ac, cond);
2853 }
2854
2855 static LLVMValueRef
2856 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2857 {
2858 LLVMValueRef result;
2859 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
2860 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2861 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2862
2863 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2864 }
2865
2866 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2867 nir_intrinsic_instr *instr)
2868 {
2869 LLVMValueRef ptr, result;
2870 int idx = instr->variables[0]->var->data.driver_location;
2871 LLVMValueRef src = get_src(ctx, instr->src[0]);
2872 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2873
2874 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2875 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2876 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2877 ptr, src, src1,
2878 LLVMAtomicOrderingSequentiallyConsistent,
2879 LLVMAtomicOrderingSequentiallyConsistent,
2880 false);
2881 } else {
2882 LLVMAtomicRMWBinOp op;
2883 switch (instr->intrinsic) {
2884 case nir_intrinsic_var_atomic_add:
2885 op = LLVMAtomicRMWBinOpAdd;
2886 break;
2887 case nir_intrinsic_var_atomic_umin:
2888 op = LLVMAtomicRMWBinOpUMin;
2889 break;
2890 case nir_intrinsic_var_atomic_umax:
2891 op = LLVMAtomicRMWBinOpUMax;
2892 break;
2893 case nir_intrinsic_var_atomic_imin:
2894 op = LLVMAtomicRMWBinOpMin;
2895 break;
2896 case nir_intrinsic_var_atomic_imax:
2897 op = LLVMAtomicRMWBinOpMax;
2898 break;
2899 case nir_intrinsic_var_atomic_and:
2900 op = LLVMAtomicRMWBinOpAnd;
2901 break;
2902 case nir_intrinsic_var_atomic_or:
2903 op = LLVMAtomicRMWBinOpOr;
2904 break;
2905 case nir_intrinsic_var_atomic_xor:
2906 op = LLVMAtomicRMWBinOpXor;
2907 break;
2908 case nir_intrinsic_var_atomic_exchange:
2909 op = LLVMAtomicRMWBinOpXchg;
2910 break;
2911 default:
2912 return NULL;
2913 }
2914
2915 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2916 LLVMAtomicOrderingSequentiallyConsistent,
2917 false);
2918 }
2919 return result;
2920 }
2921
2922 #define INTERP_CENTER 0
2923 #define INTERP_CENTROID 1
2924 #define INTERP_SAMPLE 2
2925
2926 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2927 enum glsl_interp_mode interp, unsigned location)
2928 {
2929 switch (interp) {
2930 case INTERP_MODE_FLAT:
2931 default:
2932 return NULL;
2933 case INTERP_MODE_SMOOTH:
2934 case INTERP_MODE_NONE:
2935 if (location == INTERP_CENTER)
2936 return ctx->persp_center;
2937 else if (location == INTERP_CENTROID)
2938 return ctx->persp_centroid;
2939 else if (location == INTERP_SAMPLE)
2940 return ctx->persp_sample;
2941 break;
2942 case INTERP_MODE_NOPERSPECTIVE:
2943 if (location == INTERP_CENTER)
2944 return ctx->linear_center;
2945 else if (location == INTERP_CENTROID)
2946 return ctx->linear_centroid;
2947 else if (location == INTERP_SAMPLE)
2948 return ctx->linear_sample;
2949 break;
2950 }
2951 return NULL;
2952 }
2953
2954 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
2955 LLVMValueRef sample_id)
2956 {
2957 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2958 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
2959 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
2960 LLVMValueRef result[2];
2961
2962 result[0] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset0);
2963 result[1] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset1);
2964
2965 return ac_build_gather_values(&ctx->ac, result, 2);
2966 }
2967
2968 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
2969 {
2970 LLVMValueRef values[2];
2971
2972 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
2973 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
2974 return ac_build_gather_values(&ctx->ac, values, 2);
2975 }
2976
2977 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
2978 nir_intrinsic_instr *instr)
2979 {
2980 LLVMValueRef result[2];
2981 LLVMValueRef interp_param, attr_number;
2982 unsigned location;
2983 unsigned chan;
2984 LLVMValueRef src_c0, src_c1;
2985 LLVMValueRef src0;
2986 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
2987 switch (instr->intrinsic) {
2988 case nir_intrinsic_interp_var_at_centroid:
2989 location = INTERP_CENTROID;
2990 break;
2991 case nir_intrinsic_interp_var_at_sample:
2992 location = INTERP_SAMPLE;
2993 src0 = get_src(ctx, instr->src[0]);
2994 break;
2995 case nir_intrinsic_interp_var_at_offset:
2996 location = INTERP_CENTER;
2997 src0 = get_src(ctx, instr->src[0]);
2998 default:
2999 break;
3000 }
3001
3002 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3003 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3004 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3005 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3006 LLVMValueRef sample_position;
3007 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3008
3009 /* fetch sample ID */
3010 sample_position = load_sample_position(ctx, src0);
3011
3012 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3013 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3014 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3015 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3016 }
3017 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3018 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3019
3020 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3021 LLVMValueRef ij_out[2];
3022 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3023
3024 /*
3025 * take the I then J parameters, and the DDX/Y for it, and
3026 * calculate the IJ inputs for the interpolator.
3027 * temp1 = ddx * offset/sample.x + I;
3028 * interp_param.I = ddy * offset/sample.y + temp1;
3029 * temp1 = ddx * offset/sample.x + J;
3030 * interp_param.J = ddy * offset/sample.y + temp1;
3031 */
3032 for (unsigned i = 0; i < 2; i++) {
3033 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3034 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3035 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3036 ddxy_out, ix_ll, "");
3037 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3038 ddxy_out, iy_ll, "");
3039 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3040 interp_param, ix_ll, "");
3041 LLVMValueRef temp1, temp2;
3042
3043 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3044 ctx->f32, "");
3045
3046 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3047 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3048
3049 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3050 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3051
3052 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3053 temp2, ctx->i32, "");
3054 }
3055 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3056
3057 }
3058
3059 for (chan = 0; chan < 2; chan++) {
3060 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3061
3062 if (interp_param) {
3063 interp_param = LLVMBuildBitCast(ctx->builder,
3064 interp_param, LLVMVectorType(ctx->f32, 2), "");
3065 LLVMValueRef i = LLVMBuildExtractElement(
3066 ctx->builder, interp_param, ctx->i32zero, "");
3067 LLVMValueRef j = LLVMBuildExtractElement(
3068 ctx->builder, interp_param, ctx->i32one, "");
3069
3070 result[chan] = ac_build_fs_interp(&ctx->ac,
3071 llvm_chan, attr_number,
3072 ctx->prim_mask, i, j);
3073 } else {
3074 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3075 LLVMConstInt(ctx->i32, 2, false),
3076 llvm_chan, attr_number,
3077 ctx->prim_mask);
3078 }
3079 }
3080 return ac_build_gather_values(&ctx->ac, result, 2);
3081 }
3082
3083 static void
3084 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3085 nir_intrinsic_instr *instr)
3086 {
3087 LLVMValueRef gs_next_vertex;
3088 LLVMValueRef can_emit, kill;
3089 int idx;
3090 int clip_cull_slot = -1;
3091 assert(instr->const_index[0] == 0);
3092 /* Write vertex attribute values to GSVS ring */
3093 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3094 ctx->gs_next_vertex,
3095 "");
3096
3097 /* If this thread has already emitted the declared maximum number of
3098 * vertices, kill it: excessive vertex emissions are not supposed to
3099 * have any effect, and GS threads have no externally observable
3100 * effects other than emitting vertices.
3101 */
3102 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3103 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3104
3105 kill = LLVMBuildSelect(ctx->builder, can_emit,
3106 LLVMConstReal(ctx->f32, 1.0f),
3107 LLVMConstReal(ctx->f32, -1.0f), "");
3108 ac_build_kill(&ctx->ac, kill);
3109
3110 /* loop num outputs */
3111 idx = 0;
3112 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3113 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3114 int length = 4;
3115 int start = 0;
3116 int slot = idx;
3117 int slot_inc = 1;
3118
3119 if (!(ctx->output_mask & (1ull << i)))
3120 continue;
3121
3122 if (i == VARYING_SLOT_CLIP_DIST1 ||
3123 i == VARYING_SLOT_CULL_DIST1)
3124 continue;
3125
3126 if (i == VARYING_SLOT_CLIP_DIST0 ||
3127 i == VARYING_SLOT_CULL_DIST0) {
3128 /* pack clip and cull into a single set of slots */
3129 if (clip_cull_slot == -1) {
3130 clip_cull_slot = idx;
3131 if (ctx->num_output_clips + ctx->num_output_culls > 4)
3132 slot_inc = 2;
3133 } else {
3134 slot = clip_cull_slot;
3135 slot_inc = 0;
3136 }
3137 if (i == VARYING_SLOT_CLIP_DIST0)
3138 length = ctx->num_output_clips;
3139 if (i == VARYING_SLOT_CULL_DIST0) {
3140 start = ctx->num_output_clips;
3141 length = ctx->num_output_culls;
3142 }
3143 }
3144 for (unsigned j = 0; j < length; j++) {
3145 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3146 out_ptr[j], "");
3147 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j + start) * ctx->gs_max_out_vertices, false);
3148 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3149 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3150
3151 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3152
3153 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3154 out_val, 1,
3155 voffset, ctx->gs2vs_offset, 0,
3156 1, 1, true, true);
3157 }
3158 idx += slot_inc;
3159 }
3160
3161 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3162 ctx->i32one, "");
3163 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3164
3165 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3166 }
3167
3168 static void
3169 visit_end_primitive(struct nir_to_llvm_context *ctx,
3170 nir_intrinsic_instr *instr)
3171 {
3172 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3173 }
3174
3175 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3176 nir_intrinsic_instr *instr)
3177 {
3178 LLVMValueRef result = NULL;
3179
3180 switch (instr->intrinsic) {
3181 case nir_intrinsic_load_work_group_id: {
3182 result = ctx->workgroup_ids;
3183 break;
3184 }
3185 case nir_intrinsic_load_base_vertex: {
3186 result = ctx->base_vertex;
3187 break;
3188 }
3189 case nir_intrinsic_load_vertex_id_zero_base: {
3190 result = ctx->vertex_id;
3191 break;
3192 }
3193 case nir_intrinsic_load_local_invocation_id: {
3194 result = ctx->local_invocation_ids;
3195 break;
3196 }
3197 case nir_intrinsic_load_base_instance:
3198 result = ctx->start_instance;
3199 break;
3200 case nir_intrinsic_load_draw_id:
3201 result = ctx->draw_index;
3202 break;
3203 case nir_intrinsic_load_invocation_id:
3204 result = ctx->gs_invocation_id;
3205 break;
3206 case nir_intrinsic_load_primitive_id:
3207 if (ctx->stage == MESA_SHADER_GEOMETRY)
3208 result = ctx->gs_prim_id;
3209 else
3210 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3211 break;
3212 case nir_intrinsic_load_sample_id:
3213 ctx->shader_info->fs.force_persample = true;
3214 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3215 break;
3216 case nir_intrinsic_load_sample_pos:
3217 ctx->shader_info->fs.force_persample = true;
3218 result = load_sample_pos(ctx);
3219 break;
3220 case nir_intrinsic_load_sample_mask_in:
3221 result = ctx->sample_coverage;
3222 break;
3223 case nir_intrinsic_load_front_face:
3224 result = ctx->front_face;
3225 break;
3226 case nir_intrinsic_load_instance_id:
3227 result = ctx->instance_id;
3228 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3229 ctx->shader_info->vs.vgpr_comp_cnt);
3230 break;
3231 case nir_intrinsic_load_num_work_groups:
3232 result = ctx->num_work_groups;
3233 break;
3234 case nir_intrinsic_load_local_invocation_index:
3235 result = visit_load_local_invocation_index(ctx);
3236 break;
3237 case nir_intrinsic_load_push_constant:
3238 result = visit_load_push_constant(ctx, instr);
3239 break;
3240 case nir_intrinsic_vulkan_resource_index:
3241 result = visit_vulkan_resource_index(ctx, instr);
3242 break;
3243 case nir_intrinsic_store_ssbo:
3244 visit_store_ssbo(ctx, instr);
3245 break;
3246 case nir_intrinsic_load_ssbo:
3247 result = visit_load_buffer(ctx, instr);
3248 break;
3249 case nir_intrinsic_ssbo_atomic_add:
3250 case nir_intrinsic_ssbo_atomic_imin:
3251 case nir_intrinsic_ssbo_atomic_umin:
3252 case nir_intrinsic_ssbo_atomic_imax:
3253 case nir_intrinsic_ssbo_atomic_umax:
3254 case nir_intrinsic_ssbo_atomic_and:
3255 case nir_intrinsic_ssbo_atomic_or:
3256 case nir_intrinsic_ssbo_atomic_xor:
3257 case nir_intrinsic_ssbo_atomic_exchange:
3258 case nir_intrinsic_ssbo_atomic_comp_swap:
3259 result = visit_atomic_ssbo(ctx, instr);
3260 break;
3261 case nir_intrinsic_load_ubo:
3262 result = visit_load_ubo_buffer(ctx, instr);
3263 break;
3264 case nir_intrinsic_get_buffer_size:
3265 result = visit_get_buffer_size(ctx, instr);
3266 break;
3267 case nir_intrinsic_load_var:
3268 result = visit_load_var(ctx, instr);
3269 break;
3270 case nir_intrinsic_store_var:
3271 visit_store_var(ctx, instr);
3272 break;
3273 case nir_intrinsic_image_load:
3274 result = visit_image_load(ctx, instr);
3275 break;
3276 case nir_intrinsic_image_store:
3277 visit_image_store(ctx, instr);
3278 break;
3279 case nir_intrinsic_image_atomic_add:
3280 case nir_intrinsic_image_atomic_min:
3281 case nir_intrinsic_image_atomic_max:
3282 case nir_intrinsic_image_atomic_and:
3283 case nir_intrinsic_image_atomic_or:
3284 case nir_intrinsic_image_atomic_xor:
3285 case nir_intrinsic_image_atomic_exchange:
3286 case nir_intrinsic_image_atomic_comp_swap:
3287 result = visit_image_atomic(ctx, instr);
3288 break;
3289 case nir_intrinsic_image_size:
3290 result = visit_image_size(ctx, instr);
3291 break;
3292 case nir_intrinsic_discard:
3293 ctx->shader_info->fs.can_discard = true;
3294 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3295 ctx->voidt,
3296 NULL, 0, AC_FUNC_ATTR_LEGACY);
3297 break;
3298 case nir_intrinsic_discard_if:
3299 emit_discard_if(ctx, instr);
3300 break;
3301 case nir_intrinsic_memory_barrier:
3302 emit_waitcnt(ctx);
3303 break;
3304 case nir_intrinsic_barrier:
3305 emit_barrier(ctx);
3306 break;
3307 case nir_intrinsic_var_atomic_add:
3308 case nir_intrinsic_var_atomic_imin:
3309 case nir_intrinsic_var_atomic_umin:
3310 case nir_intrinsic_var_atomic_imax:
3311 case nir_intrinsic_var_atomic_umax:
3312 case nir_intrinsic_var_atomic_and:
3313 case nir_intrinsic_var_atomic_or:
3314 case nir_intrinsic_var_atomic_xor:
3315 case nir_intrinsic_var_atomic_exchange:
3316 case nir_intrinsic_var_atomic_comp_swap:
3317 result = visit_var_atomic(ctx, instr);
3318 break;
3319 case nir_intrinsic_interp_var_at_centroid:
3320 case nir_intrinsic_interp_var_at_sample:
3321 case nir_intrinsic_interp_var_at_offset:
3322 result = visit_interp(ctx, instr);
3323 break;
3324 case nir_intrinsic_emit_vertex:
3325 visit_emit_vertex(ctx, instr);
3326 break;
3327 case nir_intrinsic_end_primitive:
3328 visit_end_primitive(ctx, instr);
3329 break;
3330 default:
3331 fprintf(stderr, "Unknown intrinsic: ");
3332 nir_print_instr(&instr->instr, stderr);
3333 fprintf(stderr, "\n");
3334 break;
3335 }
3336 if (result) {
3337 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3338 }
3339 }
3340
3341 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3342 nir_deref_var *deref,
3343 enum desc_type desc_type)
3344 {
3345 unsigned desc_set = deref->var->data.descriptor_set;
3346 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3347 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3348 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3349 unsigned offset = binding->offset;
3350 unsigned stride = binding->size;
3351 unsigned type_size;
3352 LLVMBuilderRef builder = ctx->builder;
3353 LLVMTypeRef type;
3354 LLVMValueRef index = NULL;
3355 unsigned constant_index = 0;
3356
3357 assert(deref->var->data.binding < layout->binding_count);
3358
3359 switch (desc_type) {
3360 case DESC_IMAGE:
3361 type = ctx->v8i32;
3362 type_size = 32;
3363 break;
3364 case DESC_FMASK:
3365 type = ctx->v8i32;
3366 offset += 32;
3367 type_size = 32;
3368 break;
3369 case DESC_SAMPLER:
3370 type = ctx->v4i32;
3371 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3372 offset += 64;
3373
3374 type_size = 16;
3375 break;
3376 case DESC_BUFFER:
3377 type = ctx->v4i32;
3378 type_size = 16;
3379 break;
3380 default:
3381 unreachable("invalid desc_type\n");
3382 }
3383
3384 if (deref->deref.child) {
3385 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3386
3387 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3388 offset += child->base_offset * stride;
3389 if (child->deref_array_type == nir_deref_array_type_indirect) {
3390 index = get_src(ctx, child->indirect);
3391 }
3392
3393 constant_index = child->base_offset;
3394 }
3395 if (desc_type == DESC_SAMPLER && binding->immutable_samplers &&
3396 (!index || binding->immutable_samplers_equal)) {
3397 if (binding->immutable_samplers_equal)
3398 constant_index = 0;
3399
3400 LLVMValueRef constants[] = {
3401 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 0], 0),
3402 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 1], 0),
3403 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 2], 0),
3404 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 3], 0),
3405 };
3406 return ac_build_gather_values(&ctx->ac, constants, 4);
3407 }
3408
3409 assert(stride % type_size == 0);
3410
3411 if (!index)
3412 index = ctx->i32zero;
3413
3414 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3415
3416 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
3417 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3418
3419 return ac_build_indexed_load_const(&ctx->ac, list, index);
3420 }
3421
3422 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3423 struct ac_tex_info *tinfo,
3424 nir_tex_instr *instr,
3425 nir_texop op,
3426 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3427 LLVMValueRef *param, unsigned count,
3428 unsigned dmask)
3429 {
3430 int num_args;
3431 unsigned is_rect = 0;
3432 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3433
3434 if (op == nir_texop_lod)
3435 da = false;
3436 /* Pad to power of two vector */
3437 while (count < util_next_power_of_two(count))
3438 param[count++] = LLVMGetUndef(ctx->i32);
3439
3440 if (count > 1)
3441 tinfo->args[0] = ac_build_gather_values(&ctx->ac, param, count);
3442 else
3443 tinfo->args[0] = param[0];
3444
3445 tinfo->args[1] = res_ptr;
3446 num_args = 2;
3447
3448 if (op == nir_texop_txf ||
3449 op == nir_texop_txf_ms ||
3450 op == nir_texop_query_levels ||
3451 op == nir_texop_texture_samples ||
3452 op == nir_texop_txs)
3453 tinfo->dst_type = ctx->v4i32;
3454 else {
3455 tinfo->dst_type = ctx->v4f32;
3456 tinfo->args[num_args++] = samp_ptr;
3457 }
3458
3459 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3460 tinfo->args[0] = res_ptr;
3461 tinfo->args[1] = LLVMConstInt(ctx->i32, 0, false);
3462 tinfo->args[2] = param[0];
3463 tinfo->arg_count = 3;
3464 return;
3465 }
3466
3467 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, dmask, 0);
3468 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, is_rect, 0); /* unorm */
3469 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
3470 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
3471 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
3472 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
3473 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
3474 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
3475
3476 tinfo->arg_count = num_args;
3477 }
3478
3479 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3480 *
3481 * SI-CI:
3482 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3483 * filtering manually. The driver sets img7 to a mask clearing
3484 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3485 * s_and_b32 samp0, samp0, img7
3486 *
3487 * VI:
3488 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3489 */
3490 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3491 LLVMValueRef res, LLVMValueRef samp)
3492 {
3493 LLVMBuilderRef builder = ctx->builder;
3494 LLVMValueRef img7, samp0;
3495
3496 if (ctx->options->chip_class >= VI)
3497 return samp;
3498
3499 img7 = LLVMBuildExtractElement(builder, res,
3500 LLVMConstInt(ctx->i32, 7, 0), "");
3501 samp0 = LLVMBuildExtractElement(builder, samp,
3502 LLVMConstInt(ctx->i32, 0, 0), "");
3503 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3504 return LLVMBuildInsertElement(builder, samp, samp0,
3505 LLVMConstInt(ctx->i32, 0, 0), "");
3506 }
3507
3508 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3509 nir_tex_instr *instr,
3510 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3511 LLVMValueRef *fmask_ptr)
3512 {
3513 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3514 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3515 else
3516 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3517 if (samp_ptr) {
3518 if (instr->sampler)
3519 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3520 else
3521 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3522 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3523 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3524 }
3525 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3526 instr->op == nir_texop_samples_identical))
3527 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3528 }
3529
3530 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
3531 LLVMValueRef coord)
3532 {
3533 coord = to_float(ctx, coord);
3534 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
3535 coord = to_integer(ctx, coord);
3536 return coord;
3537 }
3538
3539 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3540 {
3541 LLVMValueRef result = NULL;
3542 struct ac_tex_info tinfo = { 0 };
3543 unsigned dmask = 0xf;
3544 LLVMValueRef address[16];
3545 LLVMValueRef coords[5];
3546 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3547 LLVMValueRef bias = NULL, offsets = NULL;
3548 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3549 LLVMValueRef ddx = NULL, ddy = NULL;
3550 LLVMValueRef derivs[6];
3551 unsigned chan, count = 0;
3552 unsigned const_src = 0, num_deriv_comp = 0;
3553
3554 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3555
3556 for (unsigned i = 0; i < instr->num_srcs; i++) {
3557 switch (instr->src[i].src_type) {
3558 case nir_tex_src_coord:
3559 coord = get_src(ctx, instr->src[i].src);
3560 break;
3561 case nir_tex_src_projector:
3562 break;
3563 case nir_tex_src_comparator:
3564 comparator = get_src(ctx, instr->src[i].src);
3565 break;
3566 case nir_tex_src_offset:
3567 offsets = get_src(ctx, instr->src[i].src);
3568 const_src = i;
3569 break;
3570 case nir_tex_src_bias:
3571 bias = get_src(ctx, instr->src[i].src);
3572 break;
3573 case nir_tex_src_lod:
3574 lod = get_src(ctx, instr->src[i].src);
3575 break;
3576 case nir_tex_src_ms_index:
3577 sample_index = get_src(ctx, instr->src[i].src);
3578 break;
3579 case nir_tex_src_ms_mcs:
3580 break;
3581 case nir_tex_src_ddx:
3582 ddx = get_src(ctx, instr->src[i].src);
3583 num_deriv_comp = instr->src[i].src.ssa->num_components;
3584 break;
3585 case nir_tex_src_ddy:
3586 ddy = get_src(ctx, instr->src[i].src);
3587 break;
3588 case nir_tex_src_texture_offset:
3589 case nir_tex_src_sampler_offset:
3590 case nir_tex_src_plane:
3591 default:
3592 break;
3593 }
3594 }
3595
3596 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3597 result = get_buffer_size(ctx, res_ptr, true);
3598 goto write_result;
3599 }
3600
3601 if (instr->op == nir_texop_texture_samples) {
3602 LLVMValueRef res, samples, is_msaa;
3603 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3604 samples = LLVMBuildExtractElement(ctx->builder, res,
3605 LLVMConstInt(ctx->i32, 3, false), "");
3606 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3607 LLVMConstInt(ctx->i32, 28, false), "");
3608 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3609 LLVMConstInt(ctx->i32, 0xe, false), "");
3610 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3611 LLVMConstInt(ctx->i32, 0xe, false), "");
3612
3613 samples = LLVMBuildLShr(ctx->builder, samples,
3614 LLVMConstInt(ctx->i32, 16, false), "");
3615 samples = LLVMBuildAnd(ctx->builder, samples,
3616 LLVMConstInt(ctx->i32, 0xf, false), "");
3617 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3618 samples, "");
3619 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3620 ctx->i32one, "");
3621 result = samples;
3622 goto write_result;
3623 }
3624
3625 if (coord)
3626 for (chan = 0; chan < instr->coord_components; chan++)
3627 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3628
3629 if (offsets && instr->op != nir_texop_txf) {
3630 LLVMValueRef offset[3], pack;
3631 for (chan = 0; chan < 3; ++chan)
3632 offset[chan] = ctx->i32zero;
3633
3634 tinfo.has_offset = true;
3635 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3636 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3637 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3638 LLVMConstInt(ctx->i32, 0x3f, false), "");
3639 if (chan)
3640 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3641 LLVMConstInt(ctx->i32, chan * 8, false), "");
3642 }
3643 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3644 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3645 address[count++] = pack;
3646
3647 }
3648 /* pack LOD bias value */
3649 if (instr->op == nir_texop_txb && bias) {
3650 address[count++] = bias;
3651 }
3652
3653 /* Pack depth comparison value */
3654 if (instr->is_shadow && comparator) {
3655 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3656 }
3657
3658 /* pack derivatives */
3659 if (ddx || ddy) {
3660 switch (instr->sampler_dim) {
3661 case GLSL_SAMPLER_DIM_3D:
3662 case GLSL_SAMPLER_DIM_CUBE:
3663 num_deriv_comp = 3;
3664 break;
3665 case GLSL_SAMPLER_DIM_2D:
3666 default:
3667 num_deriv_comp = 2;
3668 break;
3669 case GLSL_SAMPLER_DIM_1D:
3670 num_deriv_comp = 1;
3671 break;
3672 }
3673
3674 for (unsigned i = 0; i < num_deriv_comp; i++) {
3675 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3676 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3677 }
3678 }
3679
3680 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3681 for (chan = 0; chan < instr->coord_components; chan++)
3682 coords[chan] = to_float(ctx, coords[chan]);
3683 if (instr->coord_components == 3)
3684 coords[3] = LLVMGetUndef(ctx->f32);
3685 ac_prepare_cube_coords(&ctx->ac,
3686 instr->op == nir_texop_txd, instr->is_array,
3687 coords, derivs);
3688 if (num_deriv_comp)
3689 num_deriv_comp--;
3690 }
3691
3692 if (ddx || ddy) {
3693 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3694 address[count++] = derivs[i];
3695 }
3696
3697 /* Pack texture coordinates */
3698 if (coord) {
3699 address[count++] = coords[0];
3700 if (instr->coord_components > 1) {
3701 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
3702 coords[1] = apply_round_slice(ctx, coords[1]);
3703 }
3704 address[count++] = coords[1];
3705 }
3706 if (instr->coord_components > 2) {
3707 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3708 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3709 coords[2] = apply_round_slice(ctx, coords[2]);
3710 }
3711 address[count++] = coords[2];
3712 }
3713 }
3714
3715 /* Pack LOD */
3716 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3717 address[count++] = lod;
3718 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3719 address[count++] = sample_index;
3720 } else if(instr->op == nir_texop_txs) {
3721 count = 0;
3722 if (lod)
3723 address[count++] = lod;
3724 else
3725 address[count++] = ctx->i32zero;
3726 }
3727
3728 for (chan = 0; chan < count; chan++) {
3729 address[chan] = LLVMBuildBitCast(ctx->builder,
3730 address[chan], ctx->i32, "");
3731 }
3732
3733 if (instr->op == nir_texop_samples_identical) {
3734 LLVMValueRef txf_address[4];
3735 struct ac_tex_info txf_info = { 0 };
3736 unsigned txf_count = count;
3737 memcpy(txf_address, address, sizeof(txf_address));
3738
3739 if (!instr->is_array)
3740 txf_address[2] = ctx->i32zero;
3741 txf_address[3] = ctx->i32zero;
3742
3743 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3744 fmask_ptr, NULL,
3745 txf_address, txf_count, 0xf);
3746
3747 result = build_tex_intrinsic(ctx, instr, &txf_info);
3748
3749 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3750 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3751 goto write_result;
3752 }
3753
3754 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
3755 instr->op != nir_texop_txs) {
3756 unsigned sample_chan = instr->is_array ? 3 : 2;
3757 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
3758 address[0],
3759 address[1],
3760 instr->is_array ? address[2] : NULL,
3761 address[sample_chan],
3762 fmask_ptr);
3763 }
3764
3765 if (offsets && instr->op == nir_texop_txf) {
3766 nir_const_value *const_offset =
3767 nir_src_as_const_value(instr->src[const_src].src);
3768 int num_offsets = instr->src[const_src].src.ssa->num_components;
3769 assert(const_offset);
3770 num_offsets = MIN2(num_offsets, instr->coord_components);
3771 if (num_offsets > 2)
3772 address[2] = LLVMBuildAdd(ctx->builder,
3773 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3774 if (num_offsets > 1)
3775 address[1] = LLVMBuildAdd(ctx->builder,
3776 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3777 address[0] = LLVMBuildAdd(ctx->builder,
3778 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3779
3780 }
3781
3782 /* TODO TG4 support */
3783 if (instr->op == nir_texop_tg4) {
3784 if (instr->is_shadow)
3785 dmask = 1;
3786 else
3787 dmask = 1 << instr->component;
3788 }
3789 set_tex_fetch_args(ctx, &tinfo, instr, instr->op,
3790 res_ptr, samp_ptr, address, count, dmask);
3791
3792 result = build_tex_intrinsic(ctx, instr, &tinfo);
3793
3794 if (instr->op == nir_texop_query_levels)
3795 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3796 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3797 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3798 else if (instr->op == nir_texop_txs &&
3799 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3800 instr->is_array) {
3801 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3802 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3803 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3804 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3805 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3806 } else if (instr->dest.ssa.num_components != 4)
3807 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3808
3809 write_result:
3810 if (result) {
3811 assert(instr->dest.is_ssa);
3812 result = to_integer(ctx, result);
3813 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3814 }
3815 }
3816
3817
3818 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3819 {
3820 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3821 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3822
3823 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3824 _mesa_hash_table_insert(ctx->phis, instr, result);
3825 }
3826
3827 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3828 nir_phi_instr *instr,
3829 LLVMValueRef llvm_phi)
3830 {
3831 nir_foreach_phi_src(src, instr) {
3832 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3833 LLVMValueRef llvm_src = get_src(ctx, src->src);
3834
3835 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3836 }
3837 }
3838
3839 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3840 {
3841 struct hash_entry *entry;
3842 hash_table_foreach(ctx->phis, entry) {
3843 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3844 (LLVMValueRef)entry->data);
3845 }
3846 }
3847
3848
3849 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3850 nir_ssa_undef_instr *instr)
3851 {
3852 unsigned num_components = instr->def.num_components;
3853 LLVMValueRef undef;
3854
3855 if (num_components == 1)
3856 undef = LLVMGetUndef(ctx->i32);
3857 else {
3858 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3859 }
3860 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3861 }
3862
3863 static void visit_jump(struct nir_to_llvm_context *ctx,
3864 nir_jump_instr *instr)
3865 {
3866 switch (instr->type) {
3867 case nir_jump_break:
3868 LLVMBuildBr(ctx->builder, ctx->break_block);
3869 LLVMClearInsertionPosition(ctx->builder);
3870 break;
3871 case nir_jump_continue:
3872 LLVMBuildBr(ctx->builder, ctx->continue_block);
3873 LLVMClearInsertionPosition(ctx->builder);
3874 break;
3875 default:
3876 fprintf(stderr, "Unknown NIR jump instr: ");
3877 nir_print_instr(&instr->instr, stderr);
3878 fprintf(stderr, "\n");
3879 abort();
3880 }
3881 }
3882
3883 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3884 struct exec_list *list);
3885
3886 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3887 {
3888 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3889 nir_foreach_instr(instr, block)
3890 {
3891 switch (instr->type) {
3892 case nir_instr_type_alu:
3893 visit_alu(ctx, nir_instr_as_alu(instr));
3894 break;
3895 case nir_instr_type_load_const:
3896 visit_load_const(ctx, nir_instr_as_load_const(instr));
3897 break;
3898 case nir_instr_type_intrinsic:
3899 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3900 break;
3901 case nir_instr_type_tex:
3902 visit_tex(ctx, nir_instr_as_tex(instr));
3903 break;
3904 case nir_instr_type_phi:
3905 visit_phi(ctx, nir_instr_as_phi(instr));
3906 break;
3907 case nir_instr_type_ssa_undef:
3908 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3909 break;
3910 case nir_instr_type_jump:
3911 visit_jump(ctx, nir_instr_as_jump(instr));
3912 break;
3913 default:
3914 fprintf(stderr, "Unknown NIR instr type: ");
3915 nir_print_instr(instr, stderr);
3916 fprintf(stderr, "\n");
3917 abort();
3918 }
3919 }
3920
3921 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3922 }
3923
3924 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3925 {
3926 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3927
3928 LLVMBasicBlockRef merge_block =
3929 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3930 LLVMBasicBlockRef if_block =
3931 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3932 LLVMBasicBlockRef else_block = merge_block;
3933 if (!exec_list_is_empty(&if_stmt->else_list))
3934 else_block = LLVMAppendBasicBlockInContext(
3935 ctx->context, ctx->main_function, "");
3936
3937 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3938 LLVMConstInt(ctx->i32, 0, false), "");
3939 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3940
3941 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3942 visit_cf_list(ctx, &if_stmt->then_list);
3943 if (LLVMGetInsertBlock(ctx->builder))
3944 LLVMBuildBr(ctx->builder, merge_block);
3945
3946 if (!exec_list_is_empty(&if_stmt->else_list)) {
3947 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3948 visit_cf_list(ctx, &if_stmt->else_list);
3949 if (LLVMGetInsertBlock(ctx->builder))
3950 LLVMBuildBr(ctx->builder, merge_block);
3951 }
3952
3953 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3954 }
3955
3956 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3957 {
3958 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3959 LLVMBasicBlockRef break_parent = ctx->break_block;
3960
3961 ctx->continue_block =
3962 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3963 ctx->break_block =
3964 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3965
3966 LLVMBuildBr(ctx->builder, ctx->continue_block);
3967 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
3968 visit_cf_list(ctx, &loop->body);
3969
3970 if (LLVMGetInsertBlock(ctx->builder))
3971 LLVMBuildBr(ctx->builder, ctx->continue_block);
3972 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
3973
3974 ctx->continue_block = continue_parent;
3975 ctx->break_block = break_parent;
3976 }
3977
3978 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3979 struct exec_list *list)
3980 {
3981 foreach_list_typed(nir_cf_node, node, node, list)
3982 {
3983 switch (node->type) {
3984 case nir_cf_node_block:
3985 visit_block(ctx, nir_cf_node_as_block(node));
3986 break;
3987
3988 case nir_cf_node_if:
3989 visit_if(ctx, nir_cf_node_as_if(node));
3990 break;
3991
3992 case nir_cf_node_loop:
3993 visit_loop(ctx, nir_cf_node_as_loop(node));
3994 break;
3995
3996 default:
3997 assert(0);
3998 }
3999 }
4000 }
4001
4002 static void
4003 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4004 struct nir_variable *variable)
4005 {
4006 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4007 LLVMValueRef t_offset;
4008 LLVMValueRef t_list;
4009 LLVMValueRef args[3];
4010 LLVMValueRef input;
4011 LLVMValueRef buffer_index;
4012 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4013 int idx = variable->data.location;
4014 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4015
4016 variable->data.driver_location = idx * 4;
4017
4018 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4019 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4020 ctx->start_instance, "");
4021 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4022 ctx->shader_info->vs.vgpr_comp_cnt);
4023 } else
4024 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4025 ctx->base_vertex, "");
4026
4027 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4028 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4029
4030 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4031 args[0] = t_list;
4032 args[1] = LLVMConstInt(ctx->i32, 0, false);
4033 args[2] = buffer_index;
4034 input = ac_build_intrinsic(&ctx->ac,
4035 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
4036 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND |
4037 AC_FUNC_ATTR_LEGACY);
4038
4039 for (unsigned chan = 0; chan < 4; chan++) {
4040 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4041 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4042 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4043 input, llvm_chan, ""));
4044 }
4045 }
4046 }
4047
4048 static void
4049 handle_gs_input_decl(struct nir_to_llvm_context *ctx,
4050 struct nir_variable *variable)
4051 {
4052 int idx = variable->data.location;
4053
4054 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4055 idx == VARYING_SLOT_CULL_DIST0) {
4056 int length = glsl_get_length(glsl_get_array_element(variable->type));
4057 if (idx == VARYING_SLOT_CLIP_DIST0)
4058 ctx->num_input_clips = length;
4059 else
4060 ctx->num_input_culls = length;
4061 }
4062 }
4063
4064 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4065 unsigned attr,
4066 LLVMValueRef interp_param,
4067 LLVMValueRef prim_mask,
4068 LLVMValueRef result[4])
4069 {
4070 LLVMValueRef attr_number;
4071 unsigned chan;
4072 LLVMValueRef i, j;
4073 bool interp = interp_param != NULL;
4074
4075 attr_number = LLVMConstInt(ctx->i32, attr, false);
4076
4077 /* fs.constant returns the param from the middle vertex, so it's not
4078 * really useful for flat shading. It's meant to be used for custom
4079 * interpolation (but the intrinsic can't fetch from the other two
4080 * vertices).
4081 *
4082 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4083 * to do the right thing. The only reason we use fs.constant is that
4084 * fs.interp cannot be used on integers, because they can be equal
4085 * to NaN.
4086 */
4087 if (interp) {
4088 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4089 LLVMVectorType(ctx->f32, 2), "");
4090
4091 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4092 ctx->i32zero, "");
4093 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4094 ctx->i32one, "");
4095 }
4096
4097 for (chan = 0; chan < 4; chan++) {
4098 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4099
4100 if (interp) {
4101 result[chan] = ac_build_fs_interp(&ctx->ac,
4102 llvm_chan,
4103 attr_number,
4104 prim_mask, i, j);
4105 } else {
4106 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4107 LLVMConstInt(ctx->i32, 2, false),
4108 llvm_chan,
4109 attr_number,
4110 prim_mask);
4111 }
4112 }
4113 }
4114
4115 static void
4116 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4117 struct nir_variable *variable)
4118 {
4119 int idx = variable->data.location;
4120 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4121 LLVMValueRef interp;
4122
4123 variable->data.driver_location = idx * 4;
4124 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4125
4126 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4127 unsigned interp_type;
4128 if (variable->data.sample) {
4129 interp_type = INTERP_SAMPLE;
4130 ctx->shader_info->fs.force_persample = true;
4131 } else if (variable->data.centroid)
4132 interp_type = INTERP_CENTROID;
4133 else
4134 interp_type = INTERP_CENTER;
4135
4136 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4137 } else
4138 interp = NULL;
4139
4140 for (unsigned i = 0; i < attrib_count; ++i)
4141 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4142
4143 }
4144
4145 static void
4146 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4147 struct nir_variable *variable)
4148 {
4149 switch (ctx->stage) {
4150 case MESA_SHADER_VERTEX:
4151 handle_vs_input_decl(ctx, variable);
4152 break;
4153 case MESA_SHADER_FRAGMENT:
4154 handle_fs_input_decl(ctx, variable);
4155 break;
4156 case MESA_SHADER_GEOMETRY:
4157 handle_gs_input_decl(ctx, variable);
4158 break;
4159 default:
4160 break;
4161 }
4162
4163 }
4164
4165 static void
4166 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4167 struct nir_shader *nir)
4168 {
4169 unsigned index = 0;
4170 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4171 LLVMValueRef interp_param;
4172 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4173
4174 if (!(ctx->input_mask & (1ull << i)))
4175 continue;
4176
4177 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4178 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4179 interp_param = *inputs;
4180 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4181 inputs);
4182
4183 if (!interp_param)
4184 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4185 ++index;
4186 } else if (i == VARYING_SLOT_POS) {
4187 for(int i = 0; i < 3; ++i)
4188 inputs[i] = ctx->frag_pos[i];
4189
4190 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4191 }
4192 }
4193 ctx->shader_info->fs.num_interp = index;
4194 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4195 ctx->shader_info->fs.has_pcoord = true;
4196 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4197 ctx->shader_info->fs.prim_id_input = true;
4198 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4199 ctx->shader_info->fs.layer_input = true;
4200 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4201 }
4202
4203 static LLVMValueRef
4204 ac_build_alloca(struct nir_to_llvm_context *ctx,
4205 LLVMTypeRef type,
4206 const char *name)
4207 {
4208 LLVMBuilderRef builder = ctx->builder;
4209 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4210 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4211 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4212 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4213 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4214 LLVMValueRef res;
4215
4216 if (first_instr) {
4217 LLVMPositionBuilderBefore(first_builder, first_instr);
4218 } else {
4219 LLVMPositionBuilderAtEnd(first_builder, first_block);
4220 }
4221
4222 res = LLVMBuildAlloca(first_builder, type, name);
4223 LLVMBuildStore(builder, LLVMConstNull(type), res);
4224
4225 LLVMDisposeBuilder(first_builder);
4226
4227 return res;
4228 }
4229
4230 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4231 LLVMTypeRef type,
4232 const char *name)
4233 {
4234 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4235 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4236 return ptr;
4237 }
4238
4239 static void
4240 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4241 struct nir_variable *variable)
4242 {
4243 int idx = variable->data.location + variable->data.index;
4244 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4245
4246 variable->data.driver_location = idx * 4;
4247
4248 if (ctx->stage == MESA_SHADER_VERTEX ||
4249 ctx->stage == MESA_SHADER_GEOMETRY) {
4250 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4251 idx == VARYING_SLOT_CULL_DIST0) {
4252 int length = glsl_get_length(variable->type);
4253 if (idx == VARYING_SLOT_CLIP_DIST0) {
4254 if (ctx->stage == MESA_SHADER_VERTEX)
4255 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
4256 ctx->num_output_clips = length;
4257 } else if (idx == VARYING_SLOT_CULL_DIST0) {
4258 if (ctx->stage == MESA_SHADER_VERTEX)
4259 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
4260 ctx->num_output_culls = length;
4261 }
4262 if (length > 4)
4263 attrib_count = 2;
4264 else
4265 attrib_count = 1;
4266 }
4267 }
4268
4269 for (unsigned i = 0; i < attrib_count; ++i) {
4270 for (unsigned chan = 0; chan < 4; chan++) {
4271 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4272 si_build_alloca_undef(ctx, ctx->f32, "");
4273 }
4274 }
4275 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
4276 }
4277
4278 static void
4279 setup_locals(struct nir_to_llvm_context *ctx,
4280 struct nir_function *func)
4281 {
4282 int i, j;
4283 ctx->num_locals = 0;
4284 nir_foreach_variable(variable, &func->impl->locals) {
4285 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4286 variable->data.driver_location = ctx->num_locals * 4;
4287 ctx->num_locals += attrib_count;
4288 }
4289 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4290 if (!ctx->locals)
4291 return;
4292
4293 for (i = 0; i < ctx->num_locals; i++) {
4294 for (j = 0; j < 4; j++) {
4295 ctx->locals[i * 4 + j] =
4296 si_build_alloca_undef(ctx, ctx->f32, "temp");
4297 }
4298 }
4299 }
4300
4301 static LLVMValueRef
4302 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4303 {
4304 v = to_float(ctx, v);
4305 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4306 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4307 }
4308
4309
4310 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4311 LLVMValueRef src0, LLVMValueRef src1)
4312 {
4313 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4314 LLVMValueRef comp[2];
4315
4316 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4317 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4318 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4319 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4320 }
4321
4322 /* Initialize arguments for the shader export intrinsic */
4323 static void
4324 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4325 LLVMValueRef *values,
4326 unsigned target,
4327 struct ac_export_args *args)
4328 {
4329 /* Default is 0xf. Adjusted below depending on the format. */
4330 args->enabled_channels = 0xf;
4331
4332 /* Specify whether the EXEC mask represents the valid mask */
4333 args->valid_mask = 0;
4334
4335 /* Specify whether this is the last export */
4336 args->done = 0;
4337
4338 /* Specify the target we are exporting */
4339 args->target = target;
4340
4341 args->compr = false;
4342 args->out[0] = LLVMGetUndef(ctx->f32);
4343 args->out[1] = LLVMGetUndef(ctx->f32);
4344 args->out[2] = LLVMGetUndef(ctx->f32);
4345 args->out[3] = LLVMGetUndef(ctx->f32);
4346
4347 if (!values)
4348 return;
4349
4350 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4351 LLVMValueRef val[4];
4352 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4353 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4354 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4355
4356 switch(col_format) {
4357 case V_028714_SPI_SHADER_ZERO:
4358 args->enabled_channels = 0; /* writemask */
4359 args->target = V_008DFC_SQ_EXP_NULL;
4360 break;
4361
4362 case V_028714_SPI_SHADER_32_R:
4363 args->enabled_channels = 1;
4364 args->out[0] = values[0];
4365 break;
4366
4367 case V_028714_SPI_SHADER_32_GR:
4368 args->enabled_channels = 0x3;
4369 args->out[0] = values[0];
4370 args->out[1] = values[1];
4371 break;
4372
4373 case V_028714_SPI_SHADER_32_AR:
4374 args->enabled_channels = 0x9;
4375 args->out[0] = values[0];
4376 args->out[3] = values[3];
4377 break;
4378
4379 case V_028714_SPI_SHADER_FP16_ABGR:
4380 args->compr = 1;
4381
4382 for (unsigned chan = 0; chan < 2; chan++) {
4383 LLVMValueRef pack_args[2] = {
4384 values[2 * chan],
4385 values[2 * chan + 1]
4386 };
4387 LLVMValueRef packed;
4388
4389 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
4390 args->out[chan] = packed;
4391 }
4392 break;
4393
4394 case V_028714_SPI_SHADER_UNORM16_ABGR:
4395 for (unsigned chan = 0; chan < 4; chan++) {
4396 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
4397 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4398 LLVMConstReal(ctx->f32, 65535), "");
4399 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4400 LLVMConstReal(ctx->f32, 0.5), "");
4401 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4402 ctx->i32, "");
4403 }
4404
4405 args->compr = 1;
4406 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4407 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4408 break;
4409
4410 case V_028714_SPI_SHADER_SNORM16_ABGR:
4411 for (unsigned chan = 0; chan < 4; chan++) {
4412 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4413 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4414 LLVMConstReal(ctx->f32, 32767), "");
4415
4416 /* If positive, add 0.5, else add -0.5. */
4417 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4418 LLVMBuildSelect(ctx->builder,
4419 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4420 val[chan], ctx->f32zero, ""),
4421 LLVMConstReal(ctx->f32, 0.5),
4422 LLVMConstReal(ctx->f32, -0.5), ""), "");
4423 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4424 }
4425
4426 args->compr = 1;
4427 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4428 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4429 break;
4430
4431 case V_028714_SPI_SHADER_UINT16_ABGR: {
4432 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4433
4434 for (unsigned chan = 0; chan < 4; chan++) {
4435 val[chan] = to_integer(ctx, values[chan]);
4436 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4437 }
4438
4439 args->compr = 1;
4440 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4441 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4442 break;
4443 }
4444
4445 case V_028714_SPI_SHADER_SINT16_ABGR: {
4446 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4447 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4448
4449 /* Clamp. */
4450 for (unsigned chan = 0; chan < 4; chan++) {
4451 val[chan] = to_integer(ctx, values[chan]);
4452 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4453 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4454 }
4455
4456 args->compr = 1;
4457 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4458 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4459 break;
4460 }
4461
4462 default:
4463 case V_028714_SPI_SHADER_32_ABGR:
4464 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
4465 break;
4466 }
4467 } else
4468 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
4469
4470 for (unsigned i = 0; i < 4; ++i)
4471 args->out[i] = to_float(ctx, args->out[i]);
4472 }
4473
4474 static void
4475 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4476 {
4477 uint32_t param_count = 0;
4478 unsigned target;
4479 unsigned pos_idx, num_pos_exports = 0;
4480 struct ac_export_args args, pos_args[4] = {};
4481 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4482 int i;
4483 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4484 (1ull << VARYING_SLOT_CLIP_DIST1) |
4485 (1ull << VARYING_SLOT_CULL_DIST0) |
4486 (1ull << VARYING_SLOT_CULL_DIST1));
4487
4488 ctx->shader_info->vs.prim_id_output = 0xffffffff;
4489 ctx->shader_info->vs.layer_output = 0xffffffff;
4490 if (clip_mask) {
4491 LLVMValueRef slots[8];
4492 unsigned j;
4493
4494 if (ctx->shader_info->vs.cull_dist_mask)
4495 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_output_clips;
4496
4497 i = VARYING_SLOT_CLIP_DIST0;
4498 for (j = 0; j < ctx->num_output_clips; j++)
4499 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4500 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4501 i = VARYING_SLOT_CULL_DIST0;
4502 for (j = 0; j < ctx->num_output_culls; j++)
4503 slots[ctx->num_output_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4504 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4505
4506 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
4507 slots[i] = LLVMGetUndef(ctx->f32);
4508
4509 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
4510 target = V_008DFC_SQ_EXP_POS + 3;
4511 si_llvm_init_export_args(ctx, &slots[4], target, &args);
4512 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
4513 &args, sizeof(args));
4514 }
4515
4516 target = V_008DFC_SQ_EXP_POS + 2;
4517 si_llvm_init_export_args(ctx, &slots[0], target, &args);
4518 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
4519 &args, sizeof(args));
4520
4521 }
4522
4523 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4524 LLVMValueRef values[4];
4525 if (!(ctx->output_mask & (1ull << i)))
4526 continue;
4527
4528 for (unsigned j = 0; j < 4; j++)
4529 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4530 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4531
4532 if (i == VARYING_SLOT_POS) {
4533 target = V_008DFC_SQ_EXP_POS;
4534 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4535 i == VARYING_SLOT_CLIP_DIST1 ||
4536 i == VARYING_SLOT_CULL_DIST0 ||
4537 i == VARYING_SLOT_CULL_DIST1) {
4538 continue;
4539 } else if (i == VARYING_SLOT_PSIZ) {
4540 ctx->shader_info->vs.writes_pointsize = true;
4541 psize_value = values[0];
4542 continue;
4543 } else if (i == VARYING_SLOT_LAYER) {
4544 ctx->shader_info->vs.writes_layer = true;
4545 layer_value = values[0];
4546 ctx->shader_info->vs.layer_output = param_count;
4547 target = V_008DFC_SQ_EXP_PARAM + param_count;
4548 param_count++;
4549 } else if (i == VARYING_SLOT_VIEWPORT) {
4550 ctx->shader_info->vs.writes_viewport_index = true;
4551 viewport_index_value = values[0];
4552 continue;
4553 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
4554 ctx->shader_info->vs.prim_id_output = param_count;
4555 target = V_008DFC_SQ_EXP_PARAM + param_count;
4556 param_count++;
4557 } else if (i >= VARYING_SLOT_VAR0) {
4558 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4559 target = V_008DFC_SQ_EXP_PARAM + param_count;
4560 param_count++;
4561 }
4562
4563 si_llvm_init_export_args(ctx, values, target, &args);
4564
4565 if (target >= V_008DFC_SQ_EXP_POS &&
4566 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4567 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
4568 &args, sizeof(args));
4569 } else {
4570 ac_build_export(&ctx->ac, &args);
4571 }
4572 }
4573
4574 /* We need to add the position output manually if it's missing. */
4575 if (!pos_args[0].out[0]) {
4576 pos_args[0].enabled_channels = 0xf;
4577 pos_args[0].valid_mask = 0;
4578 pos_args[0].done = 0;
4579 pos_args[0].target = V_008DFC_SQ_EXP_POS;
4580 pos_args[0].compr = 0;
4581 pos_args[0].out[0] = ctx->f32zero; /* X */
4582 pos_args[0].out[1] = ctx->f32zero; /* Y */
4583 pos_args[0].out[2] = ctx->f32zero; /* Z */
4584 pos_args[0].out[3] = ctx->f32one; /* W */
4585 }
4586
4587 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4588 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4589 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4590 if (mask) {
4591 pos_args[1].enabled_channels = mask;
4592 pos_args[1].valid_mask = 0;
4593 pos_args[1].done = 0;
4594 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
4595 pos_args[1].compr = 0;
4596 pos_args[1].out[0] = ctx->f32zero; /* X */
4597 pos_args[1].out[1] = ctx->f32zero; /* Y */
4598 pos_args[1].out[2] = ctx->f32zero; /* Z */
4599 pos_args[1].out[3] = ctx->f32zero; /* W */
4600
4601 if (ctx->shader_info->vs.writes_pointsize == true)
4602 pos_args[1].out[0] = psize_value;
4603 if (ctx->shader_info->vs.writes_layer == true)
4604 pos_args[1].out[2] = layer_value;
4605 if (ctx->shader_info->vs.writes_viewport_index == true)
4606 pos_args[1].out[3] = viewport_index_value;
4607 }
4608 for (i = 0; i < 4; i++) {
4609 if (pos_args[i].out[0])
4610 num_pos_exports++;
4611 }
4612
4613 pos_idx = 0;
4614 for (i = 0; i < 4; i++) {
4615 if (!pos_args[i].out[0])
4616 continue;
4617
4618 /* Specify the target we are exporting */
4619 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
4620 if (pos_idx == num_pos_exports)
4621 pos_args[i].done = 1;
4622 ac_build_export(&ctx->ac, &pos_args[i]);
4623 }
4624
4625 ctx->shader_info->vs.pos_exports = num_pos_exports;
4626 ctx->shader_info->vs.param_exports = param_count;
4627 }
4628
4629 static void
4630 handle_es_outputs_post(struct nir_to_llvm_context *ctx)
4631 {
4632 int j;
4633 uint64_t max_output_written = 0;
4634 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4635 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
4636 int param_index;
4637 int length = 4;
4638 int start = 0;
4639 if (!(ctx->output_mask & (1ull << i)))
4640 continue;
4641
4642 if (i == VARYING_SLOT_CLIP_DIST0) {
4643 length = ctx->num_output_clips;
4644 } else if (i == VARYING_SLOT_CULL_DIST0) {
4645 start = ctx->num_output_clips;
4646 length = ctx->num_output_culls;
4647 }
4648 param_index = shader_io_get_unique_index(i);
4649
4650 if (param_index > max_output_written)
4651 max_output_written = param_index;
4652
4653 for (j = 0; j < length; j++) {
4654 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
4655 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4656
4657 ac_build_buffer_store_dword(&ctx->ac,
4658 ctx->esgs_ring,
4659 out_val, 1,
4660 NULL, ctx->es2gs_offset,
4661 (4 * param_index + j + start) * 4,
4662 1, 1, true, true);
4663 }
4664 }
4665 ctx->shader_info->vs.esgs_itemsize = (max_output_written + 1) * 16;
4666 }
4667
4668 static void
4669 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4670 LLVMValueRef *color, unsigned param, bool is_last)
4671 {
4672
4673 struct ac_export_args args;
4674
4675 /* Export */
4676 si_llvm_init_export_args(ctx, color, param,
4677 &args);
4678
4679 if (is_last) {
4680 args.valid_mask = 1; /* whether the EXEC mask is valid */
4681 args.done = 1; /* DONE bit */
4682 } else if (!args.enabled_channels)
4683 return; /* unnecessary NULL export */
4684
4685 ac_build_export(&ctx->ac, &args);
4686 }
4687
4688 static void
4689 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4690 LLVMValueRef depth, LLVMValueRef stencil,
4691 LLVMValueRef samplemask)
4692 {
4693 LLVMValueRef args[9];
4694 unsigned mask = 0;
4695 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4696 args[2] = ctx->i32one; /* DONE bit */
4697 /* Specify the target we are exporting */
4698 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_MRTZ, false);
4699
4700 args[4] = ctx->i32zero; /* COMP flag */
4701 args[5] = LLVMGetUndef(ctx->f32); /* R, depth */
4702 args[6] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4703 args[7] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4704 args[8] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4705
4706 if (depth) {
4707 args[5] = depth;
4708 mask |= 0x1;
4709 }
4710
4711 if (stencil) {
4712 args[6] = stencil;
4713 mask |= 0x2;
4714 }
4715
4716 if (samplemask) {
4717 args[7] = samplemask;
4718 mask |= 0x04;
4719 }
4720
4721 /* SI (except OLAND) has a bug that it only looks
4722 * at the X writemask component. */
4723 if (ctx->options->chip_class == SI &&
4724 ctx->options->family != CHIP_OLAND)
4725 mask |= 0x01;
4726
4727 args[0] = LLVMConstInt(ctx->i32, mask, false);
4728 ac_build_intrinsic(&ctx->ac, "llvm.SI.export",
4729 ctx->voidt, args, 9,
4730 AC_FUNC_ATTR_LEGACY);
4731 }
4732
4733 static void
4734 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4735 {
4736 unsigned index = 0;
4737 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4738
4739 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4740 LLVMValueRef values[4];
4741
4742 if (!(ctx->output_mask & (1ull << i)))
4743 continue;
4744
4745 if (i == FRAG_RESULT_DEPTH) {
4746 ctx->shader_info->fs.writes_z = true;
4747 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4748 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4749 } else if (i == FRAG_RESULT_STENCIL) {
4750 ctx->shader_info->fs.writes_stencil = true;
4751 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4752 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4753 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
4754 ctx->shader_info->fs.writes_sample_mask = true;
4755 samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
4756 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4757 } else {
4758 bool last = false;
4759 for (unsigned j = 0; j < 4; j++)
4760 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4761 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4762
4763 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
4764 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4765
4766 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4767 index++;
4768 }
4769 }
4770
4771 if (depth || stencil || samplemask)
4772 si_export_mrt_z(ctx, depth, stencil, samplemask);
4773 else if (!index)
4774 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4775
4776 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4777 }
4778
4779 static void
4780 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4781 {
4782 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
4783 }
4784
4785 static void
4786 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4787 {
4788 switch (ctx->stage) {
4789 case MESA_SHADER_VERTEX:
4790 if (ctx->options->key.vs.as_es)
4791 handle_es_outputs_post(ctx);
4792 else
4793 handle_vs_outputs_post(ctx);
4794 break;
4795 case MESA_SHADER_FRAGMENT:
4796 handle_fs_outputs_post(ctx);
4797 break;
4798 case MESA_SHADER_GEOMETRY:
4799 emit_gs_epilogue(ctx);
4800 break;
4801 default:
4802 break;
4803 }
4804 }
4805
4806 static void
4807 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4808 struct nir_variable *variable, uint32_t *offset, int idx)
4809 {
4810 unsigned size = glsl_count_attribute_slots(variable->type, false);
4811 variable->data.driver_location = *offset;
4812 *offset += size;
4813 }
4814
4815 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4816 {
4817 LLVMPassManagerRef passmgr;
4818 /* Create the pass manager */
4819 passmgr = LLVMCreateFunctionPassManagerForModule(
4820 ctx->module);
4821
4822 /* This pass should eliminate all the load and store instructions */
4823 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4824
4825 /* Add some optimization passes */
4826 LLVMAddScalarReplAggregatesPass(passmgr);
4827 LLVMAddLICMPass(passmgr);
4828 LLVMAddAggressiveDCEPass(passmgr);
4829 LLVMAddCFGSimplificationPass(passmgr);
4830 LLVMAddInstructionCombiningPass(passmgr);
4831
4832 /* Run the pass */
4833 LLVMInitializeFunctionPassManager(passmgr);
4834 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4835 LLVMFinalizeFunctionPassManager(passmgr);
4836
4837 LLVMDisposeBuilder(ctx->builder);
4838 LLVMDisposePassManager(passmgr);
4839 }
4840
4841 static void
4842 ac_setup_rings(struct nir_to_llvm_context *ctx)
4843 {
4844 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4845 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, ctx->i32one);
4846 }
4847
4848 if (ctx->is_gs_copy_shader) {
4849 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4850 }
4851 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4852 LLVMValueRef tmp;
4853 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4854 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4855
4856 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4857
4858 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4859 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4860 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4861 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4862
4863 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4864 }
4865 }
4866
4867 static
4868 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4869 struct nir_shader *nir,
4870 struct ac_shader_variant_info *shader_info,
4871 const struct ac_nir_compiler_options *options)
4872 {
4873 struct nir_to_llvm_context ctx = {0};
4874 struct nir_function *func;
4875 unsigned i;
4876 ctx.options = options;
4877 ctx.shader_info = shader_info;
4878 ctx.context = LLVMContextCreate();
4879 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4880
4881 ac_llvm_context_init(&ctx.ac, ctx.context);
4882 ctx.ac.module = ctx.module;
4883
4884 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4885
4886 memset(shader_info, 0, sizeof(*shader_info));
4887
4888 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4889 setup_types(&ctx);
4890
4891 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4892 ctx.ac.builder = ctx.builder;
4893 ctx.stage = nir->stage;
4894
4895 for (i = 0; i < AC_UD_MAX_SETS; i++)
4896 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4897 for (i = 0; i < AC_UD_MAX_UD; i++)
4898 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4899
4900 create_function(&ctx);
4901
4902 if (nir->stage == MESA_SHADER_COMPUTE) {
4903 int num_shared = 0;
4904 nir_foreach_variable(variable, &nir->shared)
4905 num_shared++;
4906 if (num_shared) {
4907 int idx = 0;
4908 uint32_t shared_size = 0;
4909 LLVMValueRef var;
4910 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4911 nir_foreach_variable(variable, &nir->shared) {
4912 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4913 idx++;
4914 }
4915
4916 shared_size *= 16;
4917 var = LLVMAddGlobalInAddressSpace(ctx.module,
4918 LLVMArrayType(ctx.i8, shared_size),
4919 "compute_lds",
4920 LOCAL_ADDR_SPACE);
4921 LLVMSetAlignment(var, 4);
4922 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4923 }
4924 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4925 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4926
4927 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4928 }
4929
4930 ac_setup_rings(&ctx);
4931
4932 nir_foreach_variable(variable, &nir->inputs)
4933 handle_shader_input_decl(&ctx, variable);
4934
4935 if (nir->stage == MESA_SHADER_FRAGMENT)
4936 handle_fs_inputs_pre(&ctx, nir);
4937
4938 nir_foreach_variable(variable, &nir->outputs)
4939 handle_shader_output_decl(&ctx, variable);
4940
4941 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4942 _mesa_key_pointer_equal);
4943 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4944 _mesa_key_pointer_equal);
4945
4946 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4947
4948 setup_locals(&ctx, func);
4949
4950 visit_cf_list(&ctx, &func->impl->body);
4951 phi_post_pass(&ctx);
4952
4953 handle_shader_outputs_post(&ctx);
4954 LLVMBuildRetVoid(ctx.builder);
4955
4956 ac_llvm_finalize_module(&ctx);
4957 free(ctx.locals);
4958 ralloc_free(ctx.defs);
4959 ralloc_free(ctx.phis);
4960
4961 if (nir->stage == MESA_SHADER_GEOMETRY) {
4962 shader_info->gs.gsvs_vertex_size = util_bitcount64(ctx.output_mask) * 16;
4963 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
4964 nir->info->gs.vertices_out;
4965 }
4966 return ctx.module;
4967 }
4968
4969 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4970 {
4971 unsigned *retval = (unsigned *)context;
4972 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4973 char *description = LLVMGetDiagInfoDescription(di);
4974
4975 if (severity == LLVMDSError) {
4976 *retval = 1;
4977 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4978 description);
4979 }
4980
4981 LLVMDisposeMessage(description);
4982 }
4983
4984 static unsigned ac_llvm_compile(LLVMModuleRef M,
4985 struct ac_shader_binary *binary,
4986 LLVMTargetMachineRef tm)
4987 {
4988 unsigned retval = 0;
4989 char *err;
4990 LLVMContextRef llvm_ctx;
4991 LLVMMemoryBufferRef out_buffer;
4992 unsigned buffer_size;
4993 const char *buffer_data;
4994 LLVMBool mem_err;
4995
4996 /* Setup Diagnostic Handler*/
4997 llvm_ctx = LLVMGetModuleContext(M);
4998
4999 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
5000 &retval);
5001
5002 /* Compile IR*/
5003 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
5004 &err, &out_buffer);
5005
5006 /* Process Errors/Warnings */
5007 if (mem_err) {
5008 fprintf(stderr, "%s: %s", __FUNCTION__, err);
5009 free(err);
5010 retval = 1;
5011 goto out;
5012 }
5013
5014 /* Extract Shader Code*/
5015 buffer_size = LLVMGetBufferSize(out_buffer);
5016 buffer_data = LLVMGetBufferStart(out_buffer);
5017
5018 ac_elf_read(buffer_data, buffer_size, binary);
5019
5020 /* Clean up */
5021 LLVMDisposeMemoryBuffer(out_buffer);
5022
5023 out:
5024 return retval;
5025 }
5026
5027 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
5028 LLVMModuleRef llvm_module,
5029 struct ac_shader_binary *binary,
5030 struct ac_shader_config *config,
5031 struct ac_shader_variant_info *shader_info,
5032 gl_shader_stage stage,
5033 bool dump_shader, bool supports_spill)
5034 {
5035 if (dump_shader)
5036 ac_dump_module(llvm_module);
5037
5038 memset(binary, 0, sizeof(*binary));
5039 int v = ac_llvm_compile(llvm_module, binary, tm);
5040 if (v) {
5041 fprintf(stderr, "compile failed\n");
5042 }
5043
5044 if (dump_shader)
5045 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
5046
5047 ac_shader_binary_read_config(binary, config, 0, supports_spill);
5048
5049 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
5050 LLVMDisposeModule(llvm_module);
5051 LLVMContextDispose(ctx);
5052
5053 if (stage == MESA_SHADER_FRAGMENT) {
5054 shader_info->num_input_vgprs = 0;
5055 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
5056 shader_info->num_input_vgprs += 2;
5057 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
5058 shader_info->num_input_vgprs += 2;
5059 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
5060 shader_info->num_input_vgprs += 2;
5061 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
5062 shader_info->num_input_vgprs += 3;
5063 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
5064 shader_info->num_input_vgprs += 2;
5065 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
5066 shader_info->num_input_vgprs += 2;
5067 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
5068 shader_info->num_input_vgprs += 2;
5069 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
5070 shader_info->num_input_vgprs += 1;
5071 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
5072 shader_info->num_input_vgprs += 1;
5073 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
5074 shader_info->num_input_vgprs += 1;
5075 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5076 shader_info->num_input_vgprs += 1;
5077 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5078 shader_info->num_input_vgprs += 1;
5079 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5080 shader_info->num_input_vgprs += 1;
5081 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5082 shader_info->num_input_vgprs += 1;
5083 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5084 shader_info->num_input_vgprs += 1;
5085 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5086 shader_info->num_input_vgprs += 1;
5087 }
5088 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5089
5090 /* +3 for scratch wave offset and VCC */
5091 config->num_sgprs = MAX2(config->num_sgprs,
5092 shader_info->num_input_sgprs + 3);
5093 }
5094
5095 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5096 struct ac_shader_binary *binary,
5097 struct ac_shader_config *config,
5098 struct ac_shader_variant_info *shader_info,
5099 struct nir_shader *nir,
5100 const struct ac_nir_compiler_options *options,
5101 bool dump_shader)
5102 {
5103
5104 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5105 options);
5106
5107 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5108 switch (nir->stage) {
5109 case MESA_SHADER_COMPUTE:
5110 for (int i = 0; i < 3; ++i)
5111 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5112 break;
5113 case MESA_SHADER_FRAGMENT:
5114 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5115 break;
5116 case MESA_SHADER_GEOMETRY:
5117 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5118 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5119 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5120 shader_info->gs.invocations = nir->info->gs.invocations;
5121 break;
5122 case MESA_SHADER_VERTEX:
5123 shader_info->vs.as_es = options->key.vs.as_es;
5124 break;
5125 default:
5126 break;
5127 }
5128 }
5129
5130 static void
5131 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5132 {
5133 LLVMValueRef args[9];
5134 args[0] = ctx->gsvs_ring;
5135 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5136 args[3] = ctx->i32zero;
5137 args[4] = ctx->i32one; /* OFFEN */
5138 args[5] = ctx->i32zero; /* IDXEN */
5139 args[6] = ctx->i32one; /* GLC */
5140 args[7] = ctx->i32one; /* SLC */
5141 args[8] = ctx->i32zero; /* TFE */
5142
5143 int idx = 0;
5144 int clip_cull_slot = -1;
5145 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5146 int length = 4;
5147 int start = 0;
5148 int slot = idx;
5149 int slot_inc = 1;
5150 if (!(ctx->output_mask & (1ull << i)))
5151 continue;
5152
5153 if (i == VARYING_SLOT_CLIP_DIST1 ||
5154 i == VARYING_SLOT_CULL_DIST1)
5155 continue;
5156
5157 if (i == VARYING_SLOT_CLIP_DIST0 ||
5158 i == VARYING_SLOT_CULL_DIST0) {
5159 /* unpack clip and cull from a single set of slots */
5160 if (clip_cull_slot == -1) {
5161 clip_cull_slot = idx;
5162 if (ctx->num_output_clips + ctx->num_output_culls > 4)
5163 slot_inc = 2;
5164 } else {
5165 slot = clip_cull_slot;
5166 slot_inc = 0;
5167 }
5168 if (i == VARYING_SLOT_CLIP_DIST0)
5169 length = ctx->num_output_clips;
5170 if (i == VARYING_SLOT_CULL_DIST0) {
5171 start = ctx->num_output_clips;
5172 length = ctx->num_output_culls;
5173 }
5174 }
5175
5176 for (unsigned j = 0; j < length; j++) {
5177 LLVMValueRef value;
5178 args[2] = LLVMConstInt(ctx->i32,
5179 (slot * 4 + j + start) *
5180 ctx->gs_max_out_vertices * 16 * 4, false);
5181
5182 value = ac_build_intrinsic(&ctx->ac,
5183 "llvm.SI.buffer.load.dword.i32.i32",
5184 ctx->i32, args, 9,
5185 AC_FUNC_ATTR_READONLY |
5186 AC_FUNC_ATTR_LEGACY);
5187
5188 LLVMBuildStore(ctx->builder,
5189 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
5190 }
5191 idx += slot_inc;
5192 }
5193 handle_vs_outputs_post(ctx);
5194 }
5195
5196 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5197 struct nir_shader *geom_shader,
5198 struct ac_shader_binary *binary,
5199 struct ac_shader_config *config,
5200 struct ac_shader_variant_info *shader_info,
5201 const struct ac_nir_compiler_options *options,
5202 bool dump_shader)
5203 {
5204 struct nir_to_llvm_context ctx = {0};
5205 ctx.context = LLVMContextCreate();
5206 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5207 ctx.options = options;
5208 ctx.shader_info = shader_info;
5209
5210 ac_llvm_context_init(&ctx.ac, ctx.context);
5211 ctx.ac.module = ctx.module;
5212
5213 ctx.is_gs_copy_shader = true;
5214 LLVMSetTarget(ctx.module, "amdgcn--");
5215 setup_types(&ctx);
5216
5217 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5218 ctx.ac.builder = ctx.builder;
5219 ctx.stage = MESA_SHADER_VERTEX;
5220
5221 create_function(&ctx);
5222
5223 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5224 ac_setup_rings(&ctx);
5225
5226 nir_foreach_variable(variable, &geom_shader->outputs)
5227 handle_shader_output_decl(&ctx, variable);
5228
5229 ac_gs_copy_shader_emit(&ctx);
5230
5231 LLVMBuildRetVoid(ctx.builder);
5232
5233 ac_llvm_finalize_module(&ctx);
5234
5235 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5236 MESA_SHADER_VERTEX,
5237 dump_shader, options->supports_spill);
5238 }