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radv: start conditionalising vertex inputs. (v2)
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_info.h"
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83 LLVMValueRef ls_out_layout;
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef tcs_offchip_layout;
87 LLVMValueRef tcs_out_offsets;
88 LLVMValueRef tcs_out_layout;
89 LLVMValueRef tcs_in_layout;
90 LLVMValueRef oc_lds;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tcs_patch_id;
93 LLVMValueRef tcs_rel_ids;
94 LLVMValueRef tes_rel_patch_id;
95 LLVMValueRef tes_patch_id;
96 LLVMValueRef tes_u;
97 LLVMValueRef tes_v;
98
99 LLVMValueRef gsvs_ring_stride;
100 LLVMValueRef gsvs_num_entries;
101 LLVMValueRef gs2vs_offset;
102 LLVMValueRef gs_wave_id;
103 LLVMValueRef gs_vtx_offset[6];
104 LLVMValueRef gs_prim_id, gs_invocation_id;
105
106 LLVMValueRef esgs_ring;
107 LLVMValueRef gsvs_ring;
108 LLVMValueRef hs_ring_tess_offchip;
109 LLVMValueRef hs_ring_tess_factor;
110
111 LLVMValueRef prim_mask;
112 LLVMValueRef sample_pos_offset;
113 LLVMValueRef persp_sample, persp_center, persp_centroid;
114 LLVMValueRef linear_sample, linear_center, linear_centroid;
115 LLVMValueRef front_face;
116 LLVMValueRef ancillary;
117 LLVMValueRef sample_coverage;
118 LLVMValueRef frag_pos[4];
119
120 LLVMBasicBlockRef continue_block;
121 LLVMBasicBlockRef break_block;
122
123 LLVMTypeRef i1;
124 LLVMTypeRef i8;
125 LLVMTypeRef i16;
126 LLVMTypeRef i32;
127 LLVMTypeRef i64;
128 LLVMTypeRef v2i32;
129 LLVMTypeRef v3i32;
130 LLVMTypeRef v4i32;
131 LLVMTypeRef v8i32;
132 LLVMTypeRef f64;
133 LLVMTypeRef f32;
134 LLVMTypeRef f16;
135 LLVMTypeRef v2f32;
136 LLVMTypeRef v4f32;
137 LLVMTypeRef v16i8;
138 LLVMTypeRef voidt;
139
140 LLVMValueRef i1true;
141 LLVMValueRef i1false;
142 LLVMValueRef i32zero;
143 LLVMValueRef i32one;
144 LLVMValueRef f32zero;
145 LLVMValueRef f32one;
146 LLVMValueRef v4f32empty;
147
148 unsigned uniform_md_kind;
149 LLVMValueRef empty_md;
150 gl_shader_stage stage;
151
152 LLVMValueRef lds;
153 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
154 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
155
156 LLVMValueRef shared_memory;
157 uint64_t input_mask;
158 uint64_t output_mask;
159 int num_locals;
160 LLVMValueRef *locals;
161 bool has_ddxy;
162 uint8_t num_output_clips;
163 uint8_t num_output_culls;
164
165 bool has_ds_bpermute;
166
167 bool is_gs_copy_shader;
168 LLVMValueRef gs_next_vertex;
169 unsigned gs_max_out_vertices;
170
171 unsigned tes_primitive_mode;
172 uint64_t tess_outputs_written;
173 uint64_t tess_patch_outputs_written;
174 };
175
176 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
177 nir_deref_var *deref,
178 enum desc_type desc_type);
179 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
180 {
181 return (index * 4) + chan;
182 }
183
184 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
185 {
186 /* handle patch indices separate */
187 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
188 return 0;
189 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
190 return 1;
191 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
192 return 2 + (slot - VARYING_SLOT_PATCH0);
193
194 if (slot == VARYING_SLOT_POS)
195 return 0;
196 if (slot == VARYING_SLOT_PSIZ)
197 return 1;
198 if (slot == VARYING_SLOT_CLIP_DIST0)
199 return 2;
200 /* 3 is reserved for clip dist as well */
201 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
202 return 4 + (slot - VARYING_SLOT_VAR0);
203 unreachable("illegal slot in get unique index\n");
204 }
205
206 static unsigned llvm_get_type_size(LLVMTypeRef type)
207 {
208 LLVMTypeKind kind = LLVMGetTypeKind(type);
209
210 switch (kind) {
211 case LLVMIntegerTypeKind:
212 return LLVMGetIntTypeWidth(type) / 8;
213 case LLVMFloatTypeKind:
214 return 4;
215 case LLVMPointerTypeKind:
216 return 8;
217 case LLVMVectorTypeKind:
218 return LLVMGetVectorSize(type) *
219 llvm_get_type_size(LLVMGetElementType(type));
220 default:
221 assert(0);
222 return 0;
223 }
224 }
225
226 static void set_llvm_calling_convention(LLVMValueRef func,
227 gl_shader_stage stage)
228 {
229 enum radeon_llvm_calling_convention calling_conv;
230
231 switch (stage) {
232 case MESA_SHADER_VERTEX:
233 case MESA_SHADER_TESS_CTRL:
234 case MESA_SHADER_TESS_EVAL:
235 calling_conv = RADEON_LLVM_AMDGPU_VS;
236 break;
237 case MESA_SHADER_GEOMETRY:
238 calling_conv = RADEON_LLVM_AMDGPU_GS;
239 break;
240 case MESA_SHADER_FRAGMENT:
241 calling_conv = RADEON_LLVM_AMDGPU_PS;
242 break;
243 case MESA_SHADER_COMPUTE:
244 calling_conv = RADEON_LLVM_AMDGPU_CS;
245 break;
246 default:
247 unreachable("Unhandle shader type");
248 }
249
250 LLVMSetFunctionCallConv(func, calling_conv);
251 }
252
253 static LLVMValueRef
254 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
255 LLVMBuilderRef builder, LLVMTypeRef *return_types,
256 unsigned num_return_elems, LLVMTypeRef *param_types,
257 unsigned param_count, unsigned array_params_mask,
258 unsigned sgpr_params, bool unsafe_math)
259 {
260 LLVMTypeRef main_function_type, ret_type;
261 LLVMBasicBlockRef main_function_body;
262
263 if (num_return_elems)
264 ret_type = LLVMStructTypeInContext(ctx, return_types,
265 num_return_elems, true);
266 else
267 ret_type = LLVMVoidTypeInContext(ctx);
268
269 /* Setup the function */
270 main_function_type =
271 LLVMFunctionType(ret_type, param_types, param_count, 0);
272 LLVMValueRef main_function =
273 LLVMAddFunction(module, "main", main_function_type);
274 main_function_body =
275 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
276 LLVMPositionBuilderAtEnd(builder, main_function_body);
277
278 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
279 for (unsigned i = 0; i < sgpr_params; ++i) {
280 if (array_params_mask & (1 << i)) {
281 LLVMValueRef P = LLVMGetParam(main_function, i);
282 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
283 ac_add_attr_dereferenceable(P, UINT64_MAX);
284 }
285 else {
286 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
287 }
288 }
289
290 if (unsafe_math) {
291 /* These were copied from some LLVM test. */
292 LLVMAddTargetDependentFunctionAttr(main_function,
293 "less-precise-fpmad",
294 "true");
295 LLVMAddTargetDependentFunctionAttr(main_function,
296 "no-infs-fp-math",
297 "true");
298 LLVMAddTargetDependentFunctionAttr(main_function,
299 "no-nans-fp-math",
300 "true");
301 LLVMAddTargetDependentFunctionAttr(main_function,
302 "unsafe-fp-math",
303 "true");
304 }
305 return main_function;
306 }
307
308 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
309 {
310 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
311 CONST_ADDR_SPACE);
312 }
313
314 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
315 int idx,
316 LLVMTypeRef type)
317 {
318 LLVMValueRef offset;
319 LLVMValueRef ptr;
320 int addr_space;
321
322 offset = LLVMConstInt(ctx->i32, idx * 16, false);
323
324 ptr = ctx->shared_memory;
325 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
326 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
327 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
328 return ptr;
329 }
330
331 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
332 {
333 if (t == ctx->f16 || t == ctx->i16)
334 return ctx->i16;
335 else if (t == ctx->f32 || t == ctx->i32)
336 return ctx->i32;
337 else if (t == ctx->f64 || t == ctx->i64)
338 return ctx->i64;
339 else
340 unreachable("Unhandled integer size");
341 }
342
343 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
344 {
345 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
346 LLVMTypeRef elem_type = LLVMGetElementType(t);
347 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
348 LLVMGetVectorSize(t));
349 }
350 return to_integer_type_scalar(ctx, t);
351 }
352
353 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
354 {
355 LLVMTypeRef type = LLVMTypeOf(v);
356 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
357 }
358
359 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
360 {
361 if (t == ctx->i16 || t == ctx->f16)
362 return ctx->f16;
363 else if (t == ctx->i32 || t == ctx->f32)
364 return ctx->f32;
365 else if (t == ctx->i64 || t == ctx->f64)
366 return ctx->f64;
367 else
368 unreachable("Unhandled float size");
369 }
370
371 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
372 {
373 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
374 LLVMTypeRef elem_type = LLVMGetElementType(t);
375 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
376 LLVMGetVectorSize(t));
377 }
378 return to_float_type_scalar(ctx, t);
379 }
380
381 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
382 {
383 LLVMTypeRef type = LLVMTypeOf(v);
384 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
385 }
386
387 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
388 {
389 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
390 type = LLVMGetElementType(type);
391
392 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
393 return LLVMGetIntTypeWidth(type);
394
395 if (type == ctx->f16)
396 return 16;
397 if (type == ctx->f32)
398 return 32;
399 if (type == ctx->f64)
400 return 64;
401
402 unreachable("Unhandled type kind in get_elem_bits");
403 }
404
405 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
406 LLVMValueRef param, unsigned rshift,
407 unsigned bitwidth)
408 {
409 LLVMValueRef value = param;
410 if (rshift)
411 value = LLVMBuildLShr(ctx->builder, value,
412 LLVMConstInt(ctx->i32, rshift, false), "");
413
414 if (rshift + bitwidth < 32) {
415 unsigned mask = (1 << bitwidth) - 1;
416 value = LLVMBuildAnd(ctx->builder, value,
417 LLVMConstInt(ctx->i32, mask, false), "");
418 }
419 return value;
420 }
421
422 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
423 {
424 switch (ctx->stage) {
425 case MESA_SHADER_TESS_CTRL:
426 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
427 case MESA_SHADER_TESS_EVAL:
428 return ctx->tes_rel_patch_id;
429 break;
430 default:
431 unreachable("Illegal stage");
432 }
433 }
434
435 /* Tessellation shaders pass outputs to the next shader using LDS.
436 *
437 * LS outputs = TCS inputs
438 * TCS outputs = TES inputs
439 *
440 * The LDS layout is:
441 * - TCS inputs for patch 0
442 * - TCS inputs for patch 1
443 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
444 * - ...
445 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
446 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
447 * - TCS outputs for patch 1
448 * - Per-patch TCS outputs for patch 1
449 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
450 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
451 * - ...
452 *
453 * All three shaders VS(LS), TCS, TES share the same LDS space.
454 */
455 static LLVMValueRef
456 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
457 {
458 if (ctx->stage == MESA_SHADER_VERTEX)
459 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
460 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
461 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
462 else {
463 assert(0);
464 return NULL;
465 }
466 }
467
468 static LLVMValueRef
469 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
470 {
471 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
472 }
473
474 static LLVMValueRef
475 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
476 {
477 return LLVMBuildMul(ctx->builder,
478 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
479 LLVMConstInt(ctx->i32, 4, false), "");
480 }
481
482 static LLVMValueRef
483 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
484 {
485 return LLVMBuildMul(ctx->builder,
486 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
487 LLVMConstInt(ctx->i32, 4, false), "");
488 }
489
490 static LLVMValueRef
491 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
494 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
495
496 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
497 }
498
499 static LLVMValueRef
500 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
501 {
502 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
503 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
504 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
505
506 return LLVMBuildAdd(ctx->builder, patch0_offset,
507 LLVMBuildMul(ctx->builder, patch_stride,
508 rel_patch_id, ""),
509 "");
510 }
511
512 static LLVMValueRef
513 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
514 {
515 LLVMValueRef patch0_patch_data_offset =
516 get_tcs_out_patch0_patch_data_offset(ctx);
517 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
518 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
519
520 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
521 LLVMBuildMul(ctx->builder, patch_stride,
522 rel_patch_id, ""),
523 "");
524 }
525
526 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
527 {
528 ud_info->sgpr_idx = sgpr_idx;
529 ud_info->num_sgprs = num_sgprs;
530 ud_info->indirect = false;
531 ud_info->indirect_offset = 0;
532 }
533
534 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
535 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
536 {
537 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
538 }
539
540 #if 0
541 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
542 uint32_t indirect_offset)
543 {
544 ud_info->sgpr_idx = sgpr_idx;
545 ud_info->num_sgprs = num_sgprs;
546 ud_info->indirect = true;
547 ud_info->indirect_offset = indirect_offset;
548 }
549 #endif
550
551 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
552 {
553 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
554 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
555 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
556 "tess_lds");
557 }
558
559 static void create_function(struct nir_to_llvm_context *ctx)
560 {
561 LLVMTypeRef arg_types[23];
562 unsigned arg_idx = 0;
563 unsigned array_params_mask = 0;
564 unsigned sgpr_count = 0, user_sgpr_count;
565 unsigned i;
566 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
567 unsigned user_sgpr_idx;
568 bool need_push_constants;
569 bool need_ring_offsets = false;
570
571 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
572 if (ctx->stage == MESA_SHADER_GEOMETRY ||
573 ctx->stage == MESA_SHADER_VERTEX ||
574 ctx->stage == MESA_SHADER_TESS_CTRL ||
575 ctx->stage == MESA_SHADER_TESS_EVAL ||
576 ctx->stage == MESA_SHADER_FRAGMENT ||
577 ctx->is_gs_copy_shader)
578 need_ring_offsets = true;
579
580 need_push_constants = true;
581 if (!ctx->options->layout)
582 need_push_constants = false;
583 else if (!ctx->options->layout->push_constant_size &&
584 !ctx->options->layout->dynamic_offset_count)
585 need_push_constants = false;
586
587 if (need_ring_offsets && !ctx->options->supports_spill) {
588 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* address of rings */
589 }
590
591 /* 1 for each descriptor set */
592 for (unsigned i = 0; i < num_sets; ++i) {
593 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
594 array_params_mask |= (1 << arg_idx);
595 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
596 }
597 }
598
599 if (need_push_constants) {
600 /* 1 for push constants and dynamic descriptors */
601 array_params_mask |= (1 << arg_idx);
602 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
603 }
604
605 switch (ctx->stage) {
606 case MESA_SHADER_COMPUTE:
607 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
608 user_sgpr_count = arg_idx;
609 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
610 arg_types[arg_idx++] = ctx->i32;
611 sgpr_count = arg_idx;
612
613 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
614 break;
615 case MESA_SHADER_VERTEX:
616 if (!ctx->is_gs_copy_shader) {
617 if (ctx->shader_info->info.vs.has_vertex_buffers)
618 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
619 arg_types[arg_idx++] = ctx->i32; // base vertex
620 arg_types[arg_idx++] = ctx->i32; // start instance
621 if (ctx->shader_info->info.vs.needs_draw_id)
622 arg_types[arg_idx++] = ctx->i32; // draw index
623 }
624 user_sgpr_count = arg_idx;
625 if (ctx->options->key.vs.as_es)
626 arg_types[arg_idx++] = ctx->i32; //es2gs offset
627 else if (ctx->options->key.vs.as_ls) {
628 arg_types[arg_idx++] = ctx->i32; //ls out layout
629 user_sgpr_count++;
630 }
631 sgpr_count = arg_idx;
632 arg_types[arg_idx++] = ctx->i32; // vertex id
633 if (!ctx->is_gs_copy_shader) {
634 arg_types[arg_idx++] = ctx->i32; // rel auto id
635 arg_types[arg_idx++] = ctx->i32; // vs prim id
636 arg_types[arg_idx++] = ctx->i32; // instance id
637 }
638 break;
639 case MESA_SHADER_TESS_CTRL:
640 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
641 arg_types[arg_idx++] = ctx->i32; // tcs out offsets
642 arg_types[arg_idx++] = ctx->i32; // tcs out layout
643 arg_types[arg_idx++] = ctx->i32; // tcs in layout
644 user_sgpr_count = arg_idx;
645 arg_types[arg_idx++] = ctx->i32; // param oc lds
646 arg_types[arg_idx++] = ctx->i32; // tess factor offset
647 sgpr_count = arg_idx;
648 arg_types[arg_idx++] = ctx->i32; // patch id
649 arg_types[arg_idx++] = ctx->i32; // rel ids;
650 break;
651 case MESA_SHADER_TESS_EVAL:
652 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
653 user_sgpr_count = arg_idx;
654 if (ctx->options->key.tes.as_es) {
655 arg_types[arg_idx++] = ctx->i32; // OC LDS
656 arg_types[arg_idx++] = ctx->i32; //
657 arg_types[arg_idx++] = ctx->i32; // es2gs offset
658 } else {
659 arg_types[arg_idx++] = ctx->i32; //
660 arg_types[arg_idx++] = ctx->i32; // OC LDS
661 }
662 sgpr_count = arg_idx;
663 arg_types[arg_idx++] = ctx->f32; // tes_u
664 arg_types[arg_idx++] = ctx->f32; // tes_v
665 arg_types[arg_idx++] = ctx->i32; // tes rel patch id
666 arg_types[arg_idx++] = ctx->i32; // tes patch id
667 break;
668 case MESA_SHADER_GEOMETRY:
669 arg_types[arg_idx++] = ctx->i32; // gsvs stride
670 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
671 user_sgpr_count = arg_idx;
672 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
673 arg_types[arg_idx++] = ctx->i32; // wave id
674 sgpr_count = arg_idx;
675 arg_types[arg_idx++] = ctx->i32; // vtx0
676 arg_types[arg_idx++] = ctx->i32; // vtx1
677 arg_types[arg_idx++] = ctx->i32; // prim id
678 arg_types[arg_idx++] = ctx->i32; // vtx2
679 arg_types[arg_idx++] = ctx->i32; // vtx3
680 arg_types[arg_idx++] = ctx->i32; // vtx4
681 arg_types[arg_idx++] = ctx->i32; // vtx5
682 arg_types[arg_idx++] = ctx->i32; // GS instance id
683 break;
684 case MESA_SHADER_FRAGMENT:
685 if (ctx->shader_info->info.ps.needs_sample_positions)
686 arg_types[arg_idx++] = ctx->i32; /* sample position offset */
687 user_sgpr_count = arg_idx;
688 arg_types[arg_idx++] = ctx->i32; /* prim mask */
689 sgpr_count = arg_idx;
690 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
691 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
692 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
693 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
694 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
695 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
696 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
697 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
698 arg_types[arg_idx++] = ctx->f32; /* pos x float */
699 arg_types[arg_idx++] = ctx->f32; /* pos y float */
700 arg_types[arg_idx++] = ctx->f32; /* pos z float */
701 arg_types[arg_idx++] = ctx->f32; /* pos w float */
702 arg_types[arg_idx++] = ctx->i32; /* front face */
703 arg_types[arg_idx++] = ctx->i32; /* ancillary */
704 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
705 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
706 break;
707 default:
708 unreachable("Shader stage not implemented");
709 }
710
711 ctx->main_function = create_llvm_function(
712 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
713 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
714 set_llvm_calling_convention(ctx->main_function, ctx->stage);
715
716 ctx->shader_info->num_input_sgprs = 0;
717 ctx->shader_info->num_input_vgprs = 0;
718
719 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
720 for (i = 0; i < user_sgpr_count; i++)
721 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
722
723 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
724 for (; i < sgpr_count; i++)
725 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
726
727 if (ctx->stage != MESA_SHADER_FRAGMENT)
728 for (; i < arg_idx; ++i)
729 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
730
731 arg_idx = 0;
732 user_sgpr_idx = 0;
733
734 if (ctx->options->supports_spill || need_ring_offsets) {
735 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
736 user_sgpr_idx += 2;
737 if (ctx->options->supports_spill) {
738 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
739 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
740 NULL, 0, AC_FUNC_ATTR_READNONE);
741 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
742 const_array(ctx->v16i8, 16), "");
743 } else
744 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
745 }
746
747 for (unsigned i = 0; i < num_sets; ++i) {
748 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
749 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
750 user_sgpr_idx += 2;
751 ctx->descriptor_sets[i] =
752 LLVMGetParam(ctx->main_function, arg_idx++);
753 } else
754 ctx->descriptor_sets[i] = NULL;
755 }
756
757 if (need_push_constants) {
758 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
759 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
760 user_sgpr_idx += 2;
761 }
762
763 switch (ctx->stage) {
764 case MESA_SHADER_COMPUTE:
765 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
766 user_sgpr_idx += 3;
767 ctx->num_work_groups =
768 LLVMGetParam(ctx->main_function, arg_idx++);
769 ctx->workgroup_ids =
770 LLVMGetParam(ctx->main_function, arg_idx++);
771 ctx->tg_size =
772 LLVMGetParam(ctx->main_function, arg_idx++);
773 ctx->local_invocation_ids =
774 LLVMGetParam(ctx->main_function, arg_idx++);
775 break;
776 case MESA_SHADER_VERTEX:
777 if (!ctx->is_gs_copy_shader) {
778 if (ctx->shader_info->info.vs.has_vertex_buffers) {
779 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
780 user_sgpr_idx += 2;
781 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
782 }
783 unsigned vs_num = 2;
784 if (ctx->shader_info->info.vs.needs_draw_id)
785 vs_num++;
786
787 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
788 user_sgpr_idx += vs_num;
789
790 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
791 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
792 if (ctx->shader_info->info.vs.needs_draw_id)
793 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
794 }
795 if (ctx->options->key.vs.as_es)
796 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
797 else if (ctx->options->key.vs.as_ls) {
798 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, user_sgpr_idx, 1);
799 user_sgpr_idx += 1;
800 ctx->ls_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
801 }
802 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
803 if (!ctx->is_gs_copy_shader) {
804 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
805 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
806 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
807 }
808 if (ctx->options->key.vs.as_ls)
809 declare_tess_lds(ctx);
810 break;
811 case MESA_SHADER_TESS_CTRL:
812 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, user_sgpr_idx, 4);
813 user_sgpr_idx += 4;
814 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
815 ctx->tcs_out_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
816 ctx->tcs_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
817 ctx->tcs_in_layout = LLVMGetParam(ctx->main_function, arg_idx++);
818 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
819 ctx->tess_factor_offset = LLVMGetParam(ctx->main_function, arg_idx++);
820 ctx->tcs_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
821 ctx->tcs_rel_ids = LLVMGetParam(ctx->main_function, arg_idx++);
822
823 declare_tess_lds(ctx);
824 break;
825 case MESA_SHADER_TESS_EVAL:
826 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, user_sgpr_idx, 1);
827 user_sgpr_idx += 1;
828 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
829 if (ctx->options->key.tes.as_es) {
830 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
831 arg_idx++;
832 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
833 } else {
834 arg_idx++;
835 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
836 }
837 ctx->tes_u = LLVMGetParam(ctx->main_function, arg_idx++);
838 ctx->tes_v = LLVMGetParam(ctx->main_function, arg_idx++);
839 ctx->tes_rel_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
840 ctx->tes_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
841 break;
842 case MESA_SHADER_GEOMETRY:
843 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
844 user_sgpr_idx += 2;
845 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
846 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
847 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
848 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
849 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
850 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
851 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
852 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
853 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
854 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
855 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
856 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
857 break;
858 case MESA_SHADER_FRAGMENT:
859 if (ctx->shader_info->info.ps.needs_sample_positions) {
860 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, user_sgpr_idx, 1);
861 user_sgpr_idx += 1;
862 ctx->sample_pos_offset = LLVMGetParam(ctx->main_function, arg_idx++);
863 }
864 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
865 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
866 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
867 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
868 arg_idx++;
869 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
870 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
871 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
872 arg_idx++; /* line stipple */
873 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
874 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
875 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
876 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
877 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
878 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
879 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
880 break;
881 default:
882 unreachable("Shader stage not implemented");
883 }
884 }
885
886 static void setup_types(struct nir_to_llvm_context *ctx)
887 {
888 LLVMValueRef args[4];
889
890 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
891 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
892 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
893 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
894 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
895 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
896 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
897 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
898 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
899 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
900 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
901 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
902 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
903 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
904 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
905 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
906
907 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
908 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
909 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
910 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
911 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
912 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
913
914 args[0] = ctx->f32zero;
915 args[1] = ctx->f32zero;
916 args[2] = ctx->f32zero;
917 args[3] = ctx->f32one;
918 ctx->v4f32empty = LLVMConstVector(args, 4);
919
920 ctx->uniform_md_kind =
921 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
922 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
923
924 args[0] = LLVMConstReal(ctx->f32, 2.5);
925 }
926
927 static int get_llvm_num_components(LLVMValueRef value)
928 {
929 LLVMTypeRef type = LLVMTypeOf(value);
930 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
931 ? LLVMGetVectorSize(type)
932 : 1;
933 return num_components;
934 }
935
936 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
937 LLVMValueRef value,
938 int index)
939 {
940 int count = get_llvm_num_components(value);
941
942 assert(index < count);
943 if (count == 1)
944 return value;
945
946 return LLVMBuildExtractElement(ctx->builder, value,
947 LLVMConstInt(ctx->i32, index, false), "");
948 }
949
950 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
951 LLVMValueRef value, unsigned count)
952 {
953 unsigned num_components = get_llvm_num_components(value);
954 if (count == num_components)
955 return value;
956
957 LLVMValueRef masks[] = {
958 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
959 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
960
961 if (count == 1)
962 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
963 "");
964
965 LLVMValueRef swizzle = LLVMConstVector(masks, count);
966 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
967 }
968
969 static void
970 build_store_values_extended(struct nir_to_llvm_context *ctx,
971 LLVMValueRef *values,
972 unsigned value_count,
973 unsigned value_stride,
974 LLVMValueRef vec)
975 {
976 LLVMBuilderRef builder = ctx->builder;
977 unsigned i;
978
979 if (value_count == 1) {
980 LLVMBuildStore(builder, vec, values[0]);
981 return;
982 }
983
984 for (i = 0; i < value_count; i++) {
985 LLVMValueRef ptr = values[i * value_stride];
986 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
987 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
988 LLVMBuildStore(builder, value, ptr);
989 }
990 }
991
992 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
993 nir_ssa_def *def)
994 {
995 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
996 if (def->num_components > 1) {
997 type = LLVMVectorType(type, def->num_components);
998 }
999 return type;
1000 }
1001
1002 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
1003 {
1004 assert(src.is_ssa);
1005 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
1006 return (LLVMValueRef)entry->data;
1007 }
1008
1009
1010 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
1011 struct nir_block *b)
1012 {
1013 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
1014 return (LLVMBasicBlockRef)entry->data;
1015 }
1016
1017 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
1018 nir_alu_src src,
1019 unsigned num_components)
1020 {
1021 LLVMValueRef value = get_src(ctx, src.src);
1022 bool need_swizzle = false;
1023
1024 assert(value);
1025 LLVMTypeRef type = LLVMTypeOf(value);
1026 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1027 ? LLVMGetVectorSize(type)
1028 : 1;
1029
1030 for (unsigned i = 0; i < num_components; ++i) {
1031 assert(src.swizzle[i] < src_components);
1032 if (src.swizzle[i] != i)
1033 need_swizzle = true;
1034 }
1035
1036 if (need_swizzle || num_components != src_components) {
1037 LLVMValueRef masks[] = {
1038 LLVMConstInt(ctx->i32, src.swizzle[0], false),
1039 LLVMConstInt(ctx->i32, src.swizzle[1], false),
1040 LLVMConstInt(ctx->i32, src.swizzle[2], false),
1041 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
1042
1043 if (src_components > 1 && num_components == 1) {
1044 value = LLVMBuildExtractElement(ctx->builder, value,
1045 masks[0], "");
1046 } else if (src_components == 1 && num_components > 1) {
1047 LLVMValueRef values[] = {value, value, value, value};
1048 value = ac_build_gather_values(&ctx->ac, values, num_components);
1049 } else {
1050 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1051 value = LLVMBuildShuffleVector(ctx->builder, value, value,
1052 swizzle, "");
1053 }
1054 }
1055 assert(!src.negate);
1056 assert(!src.abs);
1057 return value;
1058 }
1059
1060 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
1061 LLVMIntPredicate pred, LLVMValueRef src0,
1062 LLVMValueRef src1)
1063 {
1064 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1065 return LLVMBuildSelect(ctx->builder, result,
1066 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1067 LLVMConstInt(ctx->i32, 0, false), "");
1068 }
1069
1070 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
1071 LLVMRealPredicate pred, LLVMValueRef src0,
1072 LLVMValueRef src1)
1073 {
1074 LLVMValueRef result;
1075 src0 = to_float(ctx, src0);
1076 src1 = to_float(ctx, src1);
1077 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1078 return LLVMBuildSelect(ctx->builder, result,
1079 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1080 LLVMConstInt(ctx->i32, 0, false), "");
1081 }
1082
1083 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
1084 const char *intrin,
1085 LLVMTypeRef result_type,
1086 LLVMValueRef src0)
1087 {
1088 char name[64];
1089 LLVMValueRef params[] = {
1090 to_float(ctx, src0),
1091 };
1092
1093 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1094 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1095 }
1096
1097 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
1098 const char *intrin,
1099 LLVMTypeRef result_type,
1100 LLVMValueRef src0, LLVMValueRef src1)
1101 {
1102 char name[64];
1103 LLVMValueRef params[] = {
1104 to_float(ctx, src0),
1105 to_float(ctx, src1),
1106 };
1107
1108 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1109 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1110 }
1111
1112 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
1113 const char *intrin,
1114 LLVMTypeRef result_type,
1115 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1116 {
1117 char name[64];
1118 LLVMValueRef params[] = {
1119 to_float(ctx, src0),
1120 to_float(ctx, src1),
1121 to_float(ctx, src2),
1122 };
1123
1124 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1125 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1126 }
1127
1128 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
1129 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1130 {
1131 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1132 ctx->i32zero, "");
1133 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1134 }
1135
1136 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
1137 LLVMValueRef src0)
1138 {
1139 LLVMValueRef params[2] = {
1140 src0,
1141
1142 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1143 * add special code to check for x=0. The reason is that
1144 * the LLVM behavior for x=0 is different from what we
1145 * need here.
1146 *
1147 * The hardware already implements the correct behavior.
1148 */
1149 LLVMConstInt(ctx->i32, 1, false),
1150 };
1151 return ac_build_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1152 }
1153
1154 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
1155 LLVMValueRef src0)
1156 {
1157 return ac_build_imsb(&ctx->ac, src0, ctx->i32);
1158 }
1159
1160 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
1161 LLVMValueRef src0)
1162 {
1163 return ac_build_umsb(&ctx->ac, src0, ctx->i32);
1164 }
1165
1166 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
1167 LLVMIntPredicate pred,
1168 LLVMValueRef src0, LLVMValueRef src1)
1169 {
1170 return LLVMBuildSelect(ctx->builder,
1171 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1172 src0,
1173 src1, "");
1174
1175 }
1176 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
1177 LLVMValueRef src0)
1178 {
1179 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1180 LLVMBuildNeg(ctx->builder, src0, ""));
1181 }
1182
1183 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1184 LLVMValueRef src0)
1185 {
1186 LLVMValueRef cmp, val;
1187
1188 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1189 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1190 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1191 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1192 return val;
1193 }
1194
1195 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1196 LLVMValueRef src0)
1197 {
1198 LLVMValueRef cmp, val;
1199
1200 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1201 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1202 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1203 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1204 return val;
1205 }
1206
1207 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1208 LLVMValueRef src0)
1209 {
1210 const char *intr = "llvm.floor.f32";
1211 LLVMValueRef fsrc0 = to_float(ctx, src0);
1212 LLVMValueRef params[] = {
1213 fsrc0,
1214 };
1215 LLVMValueRef floor = ac_build_intrinsic(&ctx->ac, intr,
1216 ctx->f32, params, 1,
1217 AC_FUNC_ATTR_READNONE);
1218 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1219 }
1220
1221 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1222 const char *intrin,
1223 LLVMValueRef src0, LLVMValueRef src1)
1224 {
1225 LLVMTypeRef ret_type;
1226 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1227 LLVMValueRef res;
1228 LLVMValueRef params[] = { src0, src1 };
1229 ret_type = LLVMStructTypeInContext(ctx->context, types,
1230 2, true);
1231
1232 res = ac_build_intrinsic(&ctx->ac, intrin, ret_type,
1233 params, 2, AC_FUNC_ATTR_READNONE);
1234
1235 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1236 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1237 return res;
1238 }
1239
1240 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1241 LLVMValueRef src0)
1242 {
1243 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1244 }
1245
1246 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1247 LLVMValueRef src0, LLVMValueRef src1)
1248 {
1249 LLVMValueRef dst64, result;
1250 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1251 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1252
1253 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1254 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1255 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1256 return result;
1257 }
1258
1259 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1260 LLVMValueRef src0, LLVMValueRef src1)
1261 {
1262 LLVMValueRef dst64, result;
1263 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1264 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1265
1266 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1267 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1268 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1269 return result;
1270 }
1271
1272 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1273 bool is_signed,
1274 LLVMValueRef srcs[3])
1275 {
1276 LLVMValueRef result;
1277 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1278
1279 result = ac_build_bfe(&ctx->ac, srcs[0], srcs[1], srcs[2], is_signed);
1280 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1281 return result;
1282 }
1283
1284 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1285 LLVMValueRef src0, LLVMValueRef src1,
1286 LLVMValueRef src2, LLVMValueRef src3)
1287 {
1288 LLVMValueRef bfi_args[3], result;
1289
1290 bfi_args[0] = LLVMBuildShl(ctx->builder,
1291 LLVMBuildSub(ctx->builder,
1292 LLVMBuildShl(ctx->builder,
1293 ctx->i32one,
1294 src3, ""),
1295 ctx->i32one, ""),
1296 src2, "");
1297 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1298 bfi_args[2] = src0;
1299
1300 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1301
1302 /* Calculate:
1303 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1304 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1305 */
1306 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1307 LLVMBuildAnd(ctx->builder, bfi_args[0],
1308 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1309
1310 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1311 return result;
1312 }
1313
1314 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1315 LLVMValueRef src0)
1316 {
1317 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1318 int i;
1319 LLVMValueRef comp[2];
1320
1321 src0 = to_float(ctx, src0);
1322 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1323 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1324 for (i = 0; i < 2; i++) {
1325 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1326 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1327 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1328 }
1329
1330 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1331 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1332
1333 return comp[0];
1334 }
1335
1336 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1337 LLVMValueRef src0)
1338 {
1339 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1340 LLVMValueRef temps[2], result, val;
1341 int i;
1342
1343 for (i = 0; i < 2; i++) {
1344 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1345 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1346 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1347 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1348 }
1349
1350 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1351 ctx->i32zero, "");
1352 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1353 ctx->i32one, "");
1354 return result;
1355 }
1356
1357 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1358 nir_op op,
1359 LLVMValueRef src0)
1360 {
1361 unsigned mask;
1362 int idx;
1363 LLVMValueRef result;
1364 ctx->has_ddxy = true;
1365
1366 if (!ctx->lds && !ctx->has_ds_bpermute)
1367 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1368 LLVMArrayType(ctx->i32, 64),
1369 "ddxy_lds", LOCAL_ADDR_SPACE);
1370
1371 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1372 mask = AC_TID_MASK_LEFT;
1373 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1374 mask = AC_TID_MASK_TOP;
1375 else
1376 mask = AC_TID_MASK_TOP_LEFT;
1377
1378 /* for DDX we want to next X pixel, DDY next Y pixel. */
1379 if (op == nir_op_fddx_fine ||
1380 op == nir_op_fddx_coarse ||
1381 op == nir_op_fddx)
1382 idx = 1;
1383 else
1384 idx = 2;
1385
1386 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1387 mask, idx, ctx->lds,
1388 src0);
1389 return result;
1390 }
1391
1392 /*
1393 * this takes an I,J coordinate pair,
1394 * and works out the X and Y derivatives.
1395 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1396 */
1397 static LLVMValueRef emit_ddxy_interp(
1398 struct nir_to_llvm_context *ctx,
1399 LLVMValueRef interp_ij)
1400 {
1401 LLVMValueRef result[4], a;
1402 unsigned i;
1403
1404 for (i = 0; i < 2; i++) {
1405 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1406 LLVMConstInt(ctx->i32, i, false), "");
1407 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1408 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1409 }
1410 return ac_build_gather_values(&ctx->ac, result, 4);
1411 }
1412
1413 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1414 {
1415 LLVMValueRef src[4], result = NULL;
1416 unsigned num_components = instr->dest.dest.ssa.num_components;
1417 unsigned src_components;
1418 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1419
1420 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1421 switch (instr->op) {
1422 case nir_op_vec2:
1423 case nir_op_vec3:
1424 case nir_op_vec4:
1425 src_components = 1;
1426 break;
1427 case nir_op_pack_half_2x16:
1428 src_components = 2;
1429 break;
1430 case nir_op_unpack_half_2x16:
1431 src_components = 1;
1432 break;
1433 default:
1434 src_components = num_components;
1435 break;
1436 }
1437 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1438 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1439
1440 switch (instr->op) {
1441 case nir_op_fmov:
1442 case nir_op_imov:
1443 result = src[0];
1444 break;
1445 case nir_op_fneg:
1446 src[0] = to_float(ctx, src[0]);
1447 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1448 break;
1449 case nir_op_ineg:
1450 result = LLVMBuildNeg(ctx->builder, src[0], "");
1451 break;
1452 case nir_op_inot:
1453 result = LLVMBuildNot(ctx->builder, src[0], "");
1454 break;
1455 case nir_op_iadd:
1456 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1457 break;
1458 case nir_op_fadd:
1459 src[0] = to_float(ctx, src[0]);
1460 src[1] = to_float(ctx, src[1]);
1461 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1462 break;
1463 case nir_op_fsub:
1464 src[0] = to_float(ctx, src[0]);
1465 src[1] = to_float(ctx, src[1]);
1466 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1467 break;
1468 case nir_op_isub:
1469 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1470 break;
1471 case nir_op_imul:
1472 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1473 break;
1474 case nir_op_imod:
1475 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1476 break;
1477 case nir_op_umod:
1478 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1479 break;
1480 case nir_op_fmod:
1481 src[0] = to_float(ctx, src[0]);
1482 src[1] = to_float(ctx, src[1]);
1483 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1484 result = emit_intrin_1f_param(ctx, "llvm.floor",
1485 to_float_type(ctx, def_type), result);
1486 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1487 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1488 break;
1489 case nir_op_frem:
1490 src[0] = to_float(ctx, src[0]);
1491 src[1] = to_float(ctx, src[1]);
1492 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1493 break;
1494 case nir_op_irem:
1495 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1496 break;
1497 case nir_op_idiv:
1498 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1499 break;
1500 case nir_op_udiv:
1501 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1502 break;
1503 case nir_op_fmul:
1504 src[0] = to_float(ctx, src[0]);
1505 src[1] = to_float(ctx, src[1]);
1506 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1507 break;
1508 case nir_op_fdiv:
1509 src[0] = to_float(ctx, src[0]);
1510 src[1] = to_float(ctx, src[1]);
1511 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1512 break;
1513 case nir_op_frcp:
1514 src[0] = to_float(ctx, src[0]);
1515 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1516 break;
1517 case nir_op_iand:
1518 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1519 break;
1520 case nir_op_ior:
1521 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1522 break;
1523 case nir_op_ixor:
1524 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1525 break;
1526 case nir_op_ishl:
1527 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1528 break;
1529 case nir_op_ishr:
1530 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1531 break;
1532 case nir_op_ushr:
1533 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1534 break;
1535 case nir_op_ilt:
1536 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1537 break;
1538 case nir_op_ine:
1539 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1540 break;
1541 case nir_op_ieq:
1542 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1543 break;
1544 case nir_op_ige:
1545 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1546 break;
1547 case nir_op_ult:
1548 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1549 break;
1550 case nir_op_uge:
1551 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1552 break;
1553 case nir_op_feq:
1554 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1555 break;
1556 case nir_op_fne:
1557 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1558 break;
1559 case nir_op_flt:
1560 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1561 break;
1562 case nir_op_fge:
1563 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1564 break;
1565 case nir_op_fabs:
1566 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1567 to_float_type(ctx, def_type), src[0]);
1568 break;
1569 case nir_op_iabs:
1570 result = emit_iabs(ctx, src[0]);
1571 break;
1572 case nir_op_imax:
1573 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1574 break;
1575 case nir_op_imin:
1576 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1577 break;
1578 case nir_op_umax:
1579 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1580 break;
1581 case nir_op_umin:
1582 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1583 break;
1584 case nir_op_isign:
1585 result = emit_isign(ctx, src[0]);
1586 break;
1587 case nir_op_fsign:
1588 src[0] = to_float(ctx, src[0]);
1589 result = emit_fsign(ctx, src[0]);
1590 break;
1591 case nir_op_ffloor:
1592 result = emit_intrin_1f_param(ctx, "llvm.floor",
1593 to_float_type(ctx, def_type), src[0]);
1594 break;
1595 case nir_op_ftrunc:
1596 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1597 to_float_type(ctx, def_type), src[0]);
1598 break;
1599 case nir_op_fceil:
1600 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1601 to_float_type(ctx, def_type), src[0]);
1602 break;
1603 case nir_op_fround_even:
1604 result = emit_intrin_1f_param(ctx, "llvm.rint",
1605 to_float_type(ctx, def_type),src[0]);
1606 break;
1607 case nir_op_ffract:
1608 result = emit_ffract(ctx, src[0]);
1609 break;
1610 case nir_op_fsin:
1611 result = emit_intrin_1f_param(ctx, "llvm.sin",
1612 to_float_type(ctx, def_type), src[0]);
1613 break;
1614 case nir_op_fcos:
1615 result = emit_intrin_1f_param(ctx, "llvm.cos",
1616 to_float_type(ctx, def_type), src[0]);
1617 break;
1618 case nir_op_fsqrt:
1619 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1620 to_float_type(ctx, def_type), src[0]);
1621 break;
1622 case nir_op_fexp2:
1623 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1624 to_float_type(ctx, def_type), src[0]);
1625 break;
1626 case nir_op_flog2:
1627 result = emit_intrin_1f_param(ctx, "llvm.log2",
1628 to_float_type(ctx, def_type), src[0]);
1629 break;
1630 case nir_op_frsq:
1631 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1632 to_float_type(ctx, def_type), src[0]);
1633 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1634 break;
1635 case nir_op_fpow:
1636 result = emit_intrin_2f_param(ctx, "llvm.pow",
1637 to_float_type(ctx, def_type), src[0], src[1]);
1638 break;
1639 case nir_op_fmax:
1640 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1641 to_float_type(ctx, def_type), src[0], src[1]);
1642 break;
1643 case nir_op_fmin:
1644 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1645 to_float_type(ctx, def_type), src[0], src[1]);
1646 break;
1647 case nir_op_ffma:
1648 result = emit_intrin_3f_param(ctx, "llvm.fma",
1649 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1650 break;
1651 case nir_op_ibitfield_extract:
1652 result = emit_bitfield_extract(ctx, true, src);
1653 break;
1654 case nir_op_ubitfield_extract:
1655 result = emit_bitfield_extract(ctx, false, src);
1656 break;
1657 case nir_op_bitfield_insert:
1658 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1659 break;
1660 case nir_op_bitfield_reverse:
1661 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1662 break;
1663 case nir_op_bit_count:
1664 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1665 break;
1666 case nir_op_vec2:
1667 case nir_op_vec3:
1668 case nir_op_vec4:
1669 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1670 src[i] = to_integer(ctx, src[i]);
1671 result = ac_build_gather_values(&ctx->ac, src, num_components);
1672 break;
1673 case nir_op_f2i32:
1674 case nir_op_f2i64:
1675 src[0] = to_float(ctx, src[0]);
1676 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1677 break;
1678 case nir_op_f2u32:
1679 case nir_op_f2u64:
1680 src[0] = to_float(ctx, src[0]);
1681 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1682 break;
1683 case nir_op_i2f32:
1684 case nir_op_i2f64:
1685 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1686 break;
1687 case nir_op_u2f32:
1688 case nir_op_u2f64:
1689 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1690 break;
1691 case nir_op_f2f64:
1692 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1693 break;
1694 case nir_op_f2f32:
1695 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1696 break;
1697 case nir_op_u2u32:
1698 case nir_op_u2u64:
1699 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1700 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1701 else
1702 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1703 break;
1704 case nir_op_i2i32:
1705 case nir_op_i2i64:
1706 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1707 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1708 else
1709 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1710 break;
1711 case nir_op_bcsel:
1712 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1713 break;
1714 case nir_op_find_lsb:
1715 result = emit_find_lsb(ctx, src[0]);
1716 break;
1717 case nir_op_ufind_msb:
1718 result = emit_ufind_msb(ctx, src[0]);
1719 break;
1720 case nir_op_ifind_msb:
1721 result = emit_ifind_msb(ctx, src[0]);
1722 break;
1723 case nir_op_uadd_carry:
1724 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1725 break;
1726 case nir_op_usub_borrow:
1727 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1728 break;
1729 case nir_op_b2f:
1730 result = emit_b2f(ctx, src[0]);
1731 break;
1732 case nir_op_fquantize2f16:
1733 src[0] = to_float(ctx, src[0]);
1734 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1735 /* need to convert back up to f32 */
1736 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1737 break;
1738 case nir_op_umul_high:
1739 result = emit_umul_high(ctx, src[0], src[1]);
1740 break;
1741 case nir_op_imul_high:
1742 result = emit_imul_high(ctx, src[0], src[1]);
1743 break;
1744 case nir_op_pack_half_2x16:
1745 result = emit_pack_half_2x16(ctx, src[0]);
1746 break;
1747 case nir_op_unpack_half_2x16:
1748 result = emit_unpack_half_2x16(ctx, src[0]);
1749 break;
1750 case nir_op_fddx:
1751 case nir_op_fddy:
1752 case nir_op_fddx_fine:
1753 case nir_op_fddy_fine:
1754 case nir_op_fddx_coarse:
1755 case nir_op_fddy_coarse:
1756 result = emit_ddxy(ctx, instr->op, src[0]);
1757 break;
1758 default:
1759 fprintf(stderr, "Unknown NIR alu instr: ");
1760 nir_print_instr(&instr->instr, stderr);
1761 fprintf(stderr, "\n");
1762 abort();
1763 }
1764
1765 if (result) {
1766 assert(instr->dest.dest.is_ssa);
1767 result = to_integer(ctx, result);
1768 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1769 result);
1770 }
1771 }
1772
1773 static void visit_load_const(struct nir_to_llvm_context *ctx,
1774 nir_load_const_instr *instr)
1775 {
1776 LLVMValueRef values[4], value = NULL;
1777 LLVMTypeRef element_type =
1778 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1779
1780 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1781 switch (instr->def.bit_size) {
1782 case 32:
1783 values[i] = LLVMConstInt(element_type,
1784 instr->value.u32[i], false);
1785 break;
1786 case 64:
1787 values[i] = LLVMConstInt(element_type,
1788 instr->value.u64[i], false);
1789 break;
1790 default:
1791 fprintf(stderr,
1792 "unsupported nir load_const bit_size: %d\n",
1793 instr->def.bit_size);
1794 abort();
1795 }
1796 }
1797 if (instr->def.num_components > 1) {
1798 value = LLVMConstVector(values, instr->def.num_components);
1799 } else
1800 value = values[0];
1801
1802 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1803 }
1804
1805 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1806 LLVMTypeRef type)
1807 {
1808 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1809 return LLVMBuildBitCast(ctx->builder, ptr,
1810 LLVMPointerType(type, addr_space), "");
1811 }
1812
1813 static LLVMValueRef
1814 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1815 {
1816 LLVMValueRef size =
1817 LLVMBuildExtractElement(ctx->builder, descriptor,
1818 LLVMConstInt(ctx->i32, 2, false), "");
1819
1820 /* VI only */
1821 if (ctx->options->chip_class >= VI && in_elements) {
1822 /* On VI, the descriptor contains the size in bytes,
1823 * but TXQ must return the size in elements.
1824 * The stride is always non-zero for resources using TXQ.
1825 */
1826 LLVMValueRef stride =
1827 LLVMBuildExtractElement(ctx->builder, descriptor,
1828 LLVMConstInt(ctx->i32, 1, false), "");
1829 stride = LLVMBuildLShr(ctx->builder, stride,
1830 LLVMConstInt(ctx->i32, 16, false), "");
1831 stride = LLVMBuildAnd(ctx->builder, stride,
1832 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1833
1834 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1835 }
1836 return size;
1837 }
1838
1839 /**
1840 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1841 * intrinsic names).
1842 */
1843 static void build_int_type_name(
1844 LLVMTypeRef type,
1845 char *buf, unsigned bufsize)
1846 {
1847 assert(bufsize >= 6);
1848
1849 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1850 snprintf(buf, bufsize, "v%ui32",
1851 LLVMGetVectorSize(type));
1852 else
1853 strcpy(buf, "i32");
1854 }
1855
1856 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1857 struct ac_image_args *args,
1858 nir_tex_instr *instr)
1859 {
1860 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1861 LLVMValueRef coord = args->addr;
1862 LLVMValueRef half_texel[2];
1863 LLVMValueRef compare_cube_wa;
1864 LLVMValueRef result;
1865 int c;
1866 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1867
1868 //TODO Rect
1869 {
1870 struct ac_image_args txq_args = { 0 };
1871
1872 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1873 txq_args.opcode = ac_image_get_resinfo;
1874 txq_args.dmask = 0xf;
1875 txq_args.addr = ctx->i32zero;
1876 txq_args.resource = args->resource;
1877 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
1878
1879 for (c = 0; c < 2; c++) {
1880 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1881 LLVMConstInt(ctx->i32, c, false), "");
1882 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1883 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1884 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1885 LLVMConstReal(ctx->f32, -0.5), "");
1886 }
1887 }
1888
1889 LLVMValueRef orig_coords = args->addr;
1890
1891 for (c = 0; c < 2; c++) {
1892 LLVMValueRef tmp;
1893 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1894 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1895 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1896 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1897 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1898 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1899 }
1900
1901
1902 /*
1903 * Apparantly cube has issue with integer types that the workaround doesn't solve,
1904 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
1905 * workaround by sampling using a scaled type and converting.
1906 * This is taken from amdgpu-pro shaders.
1907 */
1908 /* NOTE this produces some ugly code compared to amdgpu-pro,
1909 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
1910 * and then reads them back. -pro generates two selects,
1911 * one s_cmp for the descriptor rewriting
1912 * one v_cmp for the coordinate and result changes.
1913 */
1914 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1915 LLVMValueRef tmp, tmp2;
1916
1917 /* workaround 8/8/8/8 uint/sint cube gather bug */
1918 /* first detect it then change to a scaled read and f2i */
1919 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
1920 tmp2 = tmp;
1921
1922 /* extract the DATA_FORMAT */
1923 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
1924 LLVMConstInt(ctx->i32, 6, false), false);
1925
1926 /* is the DATA_FORMAT == 8_8_8_8 */
1927 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
1928
1929 if (stype == GLSL_TYPE_UINT)
1930 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
1931 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
1932 LLVMConstInt(ctx->i32, 0x10000000, false), "");
1933 else
1934 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
1935 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
1936 LLVMConstInt(ctx->i32, 0x14000000, false), "");
1937
1938 /* replace the NUM FORMAT in the descriptor */
1939 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
1940 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
1941
1942 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
1943
1944 /* don't modify the coordinates for this case */
1945 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
1946 }
1947 args->addr = coord;
1948 result = ac_build_image_opcode(&ctx->ac, args);
1949
1950 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1951 LLVMValueRef tmp, tmp2;
1952
1953 /* if the cube workaround is in place, f2i the result. */
1954 for (c = 0; c < 4; c++) {
1955 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
1956 if (stype == GLSL_TYPE_UINT)
1957 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
1958 else
1959 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
1960 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1961 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
1962 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
1963 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1964 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
1965 }
1966 }
1967 return result;
1968 }
1969
1970 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1971 nir_tex_instr *instr,
1972 struct ac_image_args *args)
1973 {
1974 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
1975 return ac_build_buffer_load_format(&ctx->ac,
1976 args->resource,
1977 args->addr,
1978 LLVMConstInt(ctx->i32, 0, false),
1979 true);
1980 }
1981
1982 args->opcode = ac_image_sample;
1983 args->compare = instr->is_shadow;
1984
1985 switch (instr->op) {
1986 case nir_texop_txf:
1987 case nir_texop_txf_ms:
1988 case nir_texop_samples_identical:
1989 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
1990 args->compare = false;
1991 args->offset = false;
1992 break;
1993 case nir_texop_txb:
1994 args->bias = true;
1995 break;
1996 case nir_texop_txl:
1997 args->lod = true;
1998 break;
1999 case nir_texop_txs:
2000 case nir_texop_query_levels:
2001 args->opcode = ac_image_get_resinfo;
2002 break;
2003 case nir_texop_tex:
2004 if (ctx->stage != MESA_SHADER_FRAGMENT)
2005 args->level_zero = true;
2006 break;
2007 case nir_texop_txd:
2008 args->deriv = true;
2009 break;
2010 case nir_texop_tg4:
2011 args->opcode = ac_image_gather4;
2012 args->level_zero = true;
2013 break;
2014 case nir_texop_lod:
2015 args->opcode = ac_image_get_lod;
2016 args->compare = false;
2017 args->offset = false;
2018 break;
2019 default:
2020 break;
2021 }
2022
2023 if (instr->op == nir_texop_tg4) {
2024 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2025 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2026 return radv_lower_gather4_integer(ctx, args, instr);
2027 }
2028 }
2029 return ac_build_image_opcode(&ctx->ac, args);
2030 }
2031
2032 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2033 nir_intrinsic_instr *instr)
2034 {
2035 LLVMValueRef index = get_src(ctx, instr->src[0]);
2036 unsigned desc_set = nir_intrinsic_desc_set(instr);
2037 unsigned binding = nir_intrinsic_binding(instr);
2038 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2039 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2040 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2041 unsigned base_offset = layout->binding[binding].offset;
2042 LLVMValueRef offset, stride;
2043
2044 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2045 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2046 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2047 layout->binding[binding].dynamic_offset_offset;
2048 desc_ptr = ctx->push_constants;
2049 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2050 stride = LLVMConstInt(ctx->i32, 16, false);
2051 } else
2052 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2053
2054 offset = LLVMConstInt(ctx->i32, base_offset, false);
2055 index = LLVMBuildMul(ctx->builder, index, stride, "");
2056 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2057
2058 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2059 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2060 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2061
2062 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2063 }
2064
2065 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2066 nir_intrinsic_instr *instr)
2067 {
2068 LLVMValueRef ptr, addr;
2069
2070 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2071 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
2072
2073 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2074 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
2075
2076 return LLVMBuildLoad(ctx->builder, ptr, "");
2077 }
2078
2079 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2080 nir_intrinsic_instr *instr)
2081 {
2082 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2083
2084 return get_buffer_size(ctx, desc, false);
2085 }
2086 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2087 nir_intrinsic_instr *instr)
2088 {
2089 const char *store_name;
2090 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2091 LLVMTypeRef data_type = ctx->f32;
2092 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
2093 int components_32bit = elem_size_mult * instr->num_components;
2094 unsigned writemask = nir_intrinsic_write_mask(instr);
2095 LLVMValueRef base_data, base_offset;
2096 LLVMValueRef params[6];
2097
2098 if (ctx->stage == MESA_SHADER_FRAGMENT)
2099 ctx->shader_info->fs.writes_memory = true;
2100
2101 params[1] = get_src(ctx, instr->src[1]);
2102 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2103 params[4] = ctx->i1false; /* glc */
2104 params[5] = ctx->i1false; /* slc */
2105
2106 if (components_32bit > 1)
2107 data_type = LLVMVectorType(ctx->f32, components_32bit);
2108
2109 base_data = to_float(ctx, src_data);
2110 base_data = trim_vector(ctx, base_data, instr->num_components);
2111 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2112 data_type, "");
2113 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2114 while (writemask) {
2115 int start, count;
2116 LLVMValueRef data;
2117 LLVMValueRef offset;
2118 LLVMValueRef tmp;
2119 u_bit_scan_consecutive_range(&writemask, &start, &count);
2120
2121 /* Due to an LLVM limitation, split 3-element writes
2122 * into a 2-element and a 1-element write. */
2123 if (count == 3) {
2124 writemask |= 1 << (start + 2);
2125 count = 2;
2126 }
2127
2128 start *= elem_size_mult;
2129 count *= elem_size_mult;
2130
2131 if (count > 4) {
2132 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2133 count = 4;
2134 }
2135
2136 if (count == 4) {
2137 store_name = "llvm.amdgcn.buffer.store.v4f32";
2138 data = base_data;
2139 } else if (count == 2) {
2140 tmp = LLVMBuildExtractElement(ctx->builder,
2141 base_data, LLVMConstInt(ctx->i32, start, false), "");
2142 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2143 ctx->i32zero, "");
2144
2145 tmp = LLVMBuildExtractElement(ctx->builder,
2146 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2147 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2148 ctx->i32one, "");
2149 store_name = "llvm.amdgcn.buffer.store.v2f32";
2150
2151 } else {
2152 assert(count == 1);
2153 if (get_llvm_num_components(base_data) > 1)
2154 data = LLVMBuildExtractElement(ctx->builder, base_data,
2155 LLVMConstInt(ctx->i32, start, false), "");
2156 else
2157 data = base_data;
2158 store_name = "llvm.amdgcn.buffer.store.f32";
2159 }
2160
2161 offset = base_offset;
2162 if (start != 0) {
2163 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2164 }
2165 params[0] = data;
2166 params[3] = offset;
2167 ac_build_intrinsic(&ctx->ac, store_name,
2168 ctx->voidt, params, 6, 0);
2169 }
2170 }
2171
2172 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2173 nir_intrinsic_instr *instr)
2174 {
2175 const char *name;
2176 LLVMValueRef params[6];
2177 int arg_count = 0;
2178 if (ctx->stage == MESA_SHADER_FRAGMENT)
2179 ctx->shader_info->fs.writes_memory = true;
2180
2181 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2182 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2183 }
2184 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2185 params[arg_count++] = get_src(ctx, instr->src[0]);
2186 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2187 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2188 params[arg_count++] = ctx->i1false; /* slc */
2189
2190 switch (instr->intrinsic) {
2191 case nir_intrinsic_ssbo_atomic_add:
2192 name = "llvm.amdgcn.buffer.atomic.add";
2193 break;
2194 case nir_intrinsic_ssbo_atomic_imin:
2195 name = "llvm.amdgcn.buffer.atomic.smin";
2196 break;
2197 case nir_intrinsic_ssbo_atomic_umin:
2198 name = "llvm.amdgcn.buffer.atomic.umin";
2199 break;
2200 case nir_intrinsic_ssbo_atomic_imax:
2201 name = "llvm.amdgcn.buffer.atomic.smax";
2202 break;
2203 case nir_intrinsic_ssbo_atomic_umax:
2204 name = "llvm.amdgcn.buffer.atomic.umax";
2205 break;
2206 case nir_intrinsic_ssbo_atomic_and:
2207 name = "llvm.amdgcn.buffer.atomic.and";
2208 break;
2209 case nir_intrinsic_ssbo_atomic_or:
2210 name = "llvm.amdgcn.buffer.atomic.or";
2211 break;
2212 case nir_intrinsic_ssbo_atomic_xor:
2213 name = "llvm.amdgcn.buffer.atomic.xor";
2214 break;
2215 case nir_intrinsic_ssbo_atomic_exchange:
2216 name = "llvm.amdgcn.buffer.atomic.swap";
2217 break;
2218 case nir_intrinsic_ssbo_atomic_comp_swap:
2219 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2220 break;
2221 default:
2222 abort();
2223 }
2224
2225 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2226 }
2227
2228 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2229 nir_intrinsic_instr *instr)
2230 {
2231 LLVMValueRef results[2];
2232 int load_components;
2233 int num_components = instr->num_components;
2234 if (instr->dest.ssa.bit_size == 64)
2235 num_components *= 2;
2236
2237 for (int i = 0; i < num_components; i += load_components) {
2238 load_components = MIN2(num_components - i, 4);
2239 const char *load_name;
2240 LLVMTypeRef data_type = ctx->f32;
2241 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2242 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2243
2244 if (load_components == 3)
2245 data_type = LLVMVectorType(ctx->f32, 4);
2246 else if (load_components > 1)
2247 data_type = LLVMVectorType(ctx->f32, load_components);
2248
2249 if (load_components >= 3)
2250 load_name = "llvm.amdgcn.buffer.load.v4f32";
2251 else if (load_components == 2)
2252 load_name = "llvm.amdgcn.buffer.load.v2f32";
2253 else if (load_components == 1)
2254 load_name = "llvm.amdgcn.buffer.load.f32";
2255 else
2256 unreachable("unhandled number of components");
2257
2258 LLVMValueRef params[] = {
2259 get_src(ctx, instr->src[0]),
2260 LLVMConstInt(ctx->i32, 0, false),
2261 offset,
2262 ctx->i1false,
2263 ctx->i1false,
2264 };
2265
2266 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2267
2268 }
2269
2270 LLVMValueRef ret = results[0];
2271 if (num_components > 4 || num_components == 3) {
2272 LLVMValueRef masks[] = {
2273 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2274 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2275 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2276 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2277 };
2278
2279 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2280 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2281 results[num_components > 4 ? 1 : 0], swizzle, "");
2282 }
2283
2284 return LLVMBuildBitCast(ctx->builder, ret,
2285 get_def_type(ctx, &instr->dest.ssa), "");
2286 }
2287
2288 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2289 nir_intrinsic_instr *instr)
2290 {
2291 LLVMValueRef results[8], ret;
2292 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2293 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2294 int num_components = instr->num_components;
2295
2296 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2297
2298 if (instr->dest.ssa.bit_size == 64)
2299 num_components *= 2;
2300
2301 for (unsigned i = 0; i < num_components; ++i) {
2302 LLVMValueRef params[] = {
2303 rsrc,
2304 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2305 offset, "")
2306 };
2307 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2308 params, 2,
2309 AC_FUNC_ATTR_READNONE |
2310 AC_FUNC_ATTR_LEGACY);
2311 }
2312
2313
2314 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2315 return LLVMBuildBitCast(ctx->builder, ret,
2316 get_def_type(ctx, &instr->dest.ssa), "");
2317 }
2318
2319 static void
2320 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref_var *deref,
2321 bool vs_in, unsigned *vertex_index_out,
2322 LLVMValueRef *vertex_index_ref,
2323 unsigned *const_out, LLVMValueRef *indir_out)
2324 {
2325 unsigned const_offset = 0;
2326 nir_deref *tail = &deref->deref;
2327 LLVMValueRef offset = NULL;
2328
2329 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2330 tail = tail->child;
2331 nir_deref_array *deref_array = nir_deref_as_array(tail);
2332 if (vertex_index_out)
2333 *vertex_index_out = deref_array->base_offset;
2334
2335 if (vertex_index_ref) {
2336 LLVMValueRef vtx = LLVMConstInt(ctx->i32, deref_array->base_offset, false);
2337 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2338 vtx = LLVMBuildAdd(ctx->builder, vtx, get_src(ctx, deref_array->indirect), "");
2339 }
2340 *vertex_index_ref = vtx;
2341 }
2342 }
2343
2344 if (deref->var->data.compact) {
2345 assert(tail->child->deref_type == nir_deref_type_array);
2346 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2347 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2348 /* We always lower indirect dereferences for "compact" array vars. */
2349 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2350
2351 const_offset = deref_array->base_offset;
2352 goto out;
2353 }
2354
2355 while (tail->child != NULL) {
2356 const struct glsl_type *parent_type = tail->type;
2357 tail = tail->child;
2358
2359 if (tail->deref_type == nir_deref_type_array) {
2360 nir_deref_array *deref_array = nir_deref_as_array(tail);
2361 LLVMValueRef index, stride, local_offset;
2362 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2363
2364 const_offset += size * deref_array->base_offset;
2365 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2366 continue;
2367
2368 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2369 index = get_src(ctx, deref_array->indirect);
2370 stride = LLVMConstInt(ctx->i32, size, 0);
2371 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2372
2373 if (offset)
2374 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2375 else
2376 offset = local_offset;
2377 } else if (tail->deref_type == nir_deref_type_struct) {
2378 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2379
2380 for (unsigned i = 0; i < deref_struct->index; i++) {
2381 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2382 const_offset += glsl_count_attribute_slots(ft, vs_in);
2383 }
2384 } else
2385 unreachable("unsupported deref type");
2386
2387 }
2388 out:
2389 if (const_offset && offset)
2390 offset = LLVMBuildAdd(ctx->builder, offset,
2391 LLVMConstInt(ctx->i32, const_offset, 0),
2392 "");
2393
2394 *const_out = const_offset;
2395 *indir_out = offset;
2396 }
2397
2398 static LLVMValueRef
2399 lds_load(struct nir_to_llvm_context *ctx,
2400 LLVMValueRef dw_addr)
2401 {
2402 LLVMValueRef value;
2403 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2404 return value;
2405 }
2406
2407 static void
2408 lds_store(struct nir_to_llvm_context *ctx,
2409 LLVMValueRef dw_addr, LLVMValueRef value)
2410 {
2411 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2412 ac_build_indexed_store(&ctx->ac, ctx->lds,
2413 dw_addr, value);
2414 }
2415
2416 /* The offchip buffer layout for TCS->TES is
2417 *
2418 * - attribute 0 of patch 0 vertex 0
2419 * - attribute 0 of patch 0 vertex 1
2420 * - attribute 0 of patch 0 vertex 2
2421 * ...
2422 * - attribute 0 of patch 1 vertex 0
2423 * - attribute 0 of patch 1 vertex 1
2424 * ...
2425 * - attribute 1 of patch 0 vertex 0
2426 * - attribute 1 of patch 0 vertex 1
2427 * ...
2428 * - per patch attribute 0 of patch 0
2429 * - per patch attribute 0 of patch 1
2430 * ...
2431 *
2432 * Note that every attribute has 4 components.
2433 */
2434 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2435 LLVMValueRef vertex_index,
2436 LLVMValueRef param_index)
2437 {
2438 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2439 LLVMValueRef param_stride, constant16;
2440 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2441
2442 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2443 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2444 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2445 num_patches, "");
2446
2447 constant16 = LLVMConstInt(ctx->i32, 16, false);
2448 if (vertex_index) {
2449 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2450 vertices_per_patch, "");
2451
2452 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2453 vertex_index, "");
2454
2455 param_stride = total_vertices;
2456 } else {
2457 base_addr = rel_patch_id;
2458 param_stride = num_patches;
2459 }
2460
2461 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2462 LLVMBuildMul(ctx->builder, param_index,
2463 param_stride, ""), "");
2464
2465 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2466
2467 if (!vertex_index) {
2468 LLVMValueRef patch_data_offset =
2469 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2470
2471 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2472 patch_data_offset, "");
2473 }
2474 return base_addr;
2475 }
2476
2477 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2478 unsigned param,
2479 unsigned const_index,
2480 bool is_compact,
2481 LLVMValueRef vertex_index,
2482 LLVMValueRef indir_index)
2483 {
2484 LLVMValueRef param_index;
2485
2486 if (indir_index)
2487 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2488 indir_index, "");
2489 else {
2490 if (const_index && !is_compact)
2491 param += const_index;
2492 param_index = LLVMConstInt(ctx->i32, param, false);
2493 }
2494 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2495 }
2496
2497 static void
2498 mark_tess_output(struct nir_to_llvm_context *ctx,
2499 bool is_patch, uint32_t param)
2500
2501 {
2502 if (is_patch) {
2503 ctx->tess_patch_outputs_written |= (1ull << param);
2504 } else
2505 ctx->tess_outputs_written |= (1ull << param);
2506 }
2507
2508 static LLVMValueRef
2509 get_dw_address(struct nir_to_llvm_context *ctx,
2510 LLVMValueRef dw_addr,
2511 unsigned param,
2512 unsigned const_index,
2513 bool compact_const_index,
2514 LLVMValueRef vertex_index,
2515 LLVMValueRef stride,
2516 LLVMValueRef indir_index)
2517
2518 {
2519
2520 if (vertex_index) {
2521 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2522 LLVMBuildMul(ctx->builder,
2523 vertex_index,
2524 stride, ""), "");
2525 }
2526
2527 if (indir_index)
2528 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2529 LLVMBuildMul(ctx->builder, indir_index,
2530 LLVMConstInt(ctx->i32, 4, false), ""), "");
2531 else if (const_index && !compact_const_index)
2532 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2533 LLVMConstInt(ctx->i32, const_index, false), "");
2534
2535 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2536 LLVMConstInt(ctx->i32, param * 4, false), "");
2537
2538 if (const_index && compact_const_index)
2539 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2540 LLVMConstInt(ctx->i32, const_index, false), "");
2541 return dw_addr;
2542 }
2543
2544 static LLVMValueRef
2545 load_tcs_input(struct nir_to_llvm_context *ctx,
2546 nir_intrinsic_instr *instr)
2547 {
2548 LLVMValueRef dw_addr, stride;
2549 unsigned const_index;
2550 LLVMValueRef vertex_index;
2551 LLVMValueRef indir_index;
2552 unsigned param;
2553 LLVMValueRef value[4], result;
2554 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2555 const bool is_compact = instr->variables[0]->var->data.compact;
2556 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2557 radv_get_deref_offset(ctx, instr->variables[0],
2558 false, NULL, per_vertex ? &vertex_index : NULL,
2559 &const_index, &indir_index);
2560
2561 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2562 dw_addr = get_tcs_in_current_patch_offset(ctx);
2563 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2564 indir_index);
2565
2566 for (unsigned i = 0; i < instr->num_components; i++) {
2567 value[i] = lds_load(ctx, dw_addr);
2568 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2569 ctx->i32one, "");
2570 }
2571 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2572 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2573 return result;
2574 }
2575
2576 static LLVMValueRef
2577 load_tcs_output(struct nir_to_llvm_context *ctx,
2578 nir_intrinsic_instr *instr)
2579 {
2580 LLVMValueRef dw_addr, stride;
2581 LLVMValueRef value[4], result;
2582 LLVMValueRef vertex_index = NULL;
2583 LLVMValueRef indir_index = NULL;
2584 unsigned const_index = 0;
2585 unsigned param;
2586 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2587 const bool is_compact = instr->variables[0]->var->data.compact;
2588 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2589 radv_get_deref_offset(ctx, instr->variables[0],
2590 false, NULL, per_vertex ? &vertex_index : NULL,
2591 &const_index, &indir_index);
2592
2593 if (!instr->variables[0]->var->data.patch) {
2594 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2595 dw_addr = get_tcs_out_current_patch_offset(ctx);
2596 } else {
2597 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2598 }
2599
2600 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2601 indir_index);
2602
2603 for (unsigned i = 0; i < instr->num_components; i++) {
2604 value[i] = lds_load(ctx, dw_addr);
2605 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2606 ctx->i32one, "");
2607 }
2608 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2609 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2610 return result;
2611 }
2612
2613 static void
2614 store_tcs_output(struct nir_to_llvm_context *ctx,
2615 nir_intrinsic_instr *instr,
2616 LLVMValueRef src,
2617 unsigned writemask)
2618 {
2619 LLVMValueRef stride, dw_addr;
2620 LLVMValueRef buf_addr = NULL;
2621 LLVMValueRef vertex_index = NULL;
2622 LLVMValueRef indir_index = NULL;
2623 unsigned const_index = 0;
2624 unsigned param;
2625 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2626 const bool is_compact = instr->variables[0]->var->data.compact;
2627
2628 radv_get_deref_offset(ctx, instr->variables[0],
2629 false, NULL, per_vertex ? &vertex_index : NULL,
2630 &const_index, &indir_index);
2631
2632 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2633 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2634 is_compact && const_index > 3) {
2635 const_index -= 3;
2636 param++;
2637 }
2638
2639 if (!instr->variables[0]->var->data.patch) {
2640 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2641 dw_addr = get_tcs_out_current_patch_offset(ctx);
2642 } else {
2643 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2644 }
2645
2646 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2647
2648 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2649 indir_index);
2650 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2651 vertex_index, indir_index);
2652
2653 unsigned base = is_compact ? const_index : 0;
2654 for (unsigned chan = 0; chan < 8; chan++) {
2655 bool is_tess_factor = false;
2656 if (!(writemask & (1 << chan)))
2657 continue;
2658 LLVMValueRef value = llvm_extract_elem(ctx, src, chan);
2659
2660 lds_store(ctx, dw_addr, value);
2661
2662 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2663 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2664 is_tess_factor = true;
2665
2666 if (!is_tess_factor && writemask != 0xF)
2667 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2668 buf_addr, ctx->oc_lds,
2669 4 * (base + chan), 1, 0, true, false);
2670
2671 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2672 ctx->i32one, "");
2673 }
2674
2675 if (writemask == 0xF) {
2676 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2677 buf_addr, ctx->oc_lds,
2678 (base * 4), 1, 0, true, false);
2679 }
2680 }
2681
2682 static LLVMValueRef
2683 load_tes_input(struct nir_to_llvm_context *ctx,
2684 nir_intrinsic_instr *instr)
2685 {
2686 LLVMValueRef buf_addr;
2687 LLVMValueRef result;
2688 LLVMValueRef vertex_index = NULL;
2689 LLVMValueRef indir_index = NULL;
2690 unsigned const_index = 0;
2691 unsigned param;
2692 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2693 const bool is_compact = instr->variables[0]->var->data.compact;
2694
2695 radv_get_deref_offset(ctx, instr->variables[0],
2696 false, NULL, per_vertex ? &vertex_index : NULL,
2697 &const_index, &indir_index);
2698 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2699 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2700 is_compact && const_index > 3) {
2701 const_index -= 3;
2702 param++;
2703 }
2704 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2705 is_compact, vertex_index, indir_index);
2706
2707 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2708 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true);
2709 result = trim_vector(ctx, result, instr->num_components);
2710 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2711 return result;
2712 }
2713
2714 static LLVMValueRef
2715 load_gs_input(struct nir_to_llvm_context *ctx,
2716 nir_intrinsic_instr *instr)
2717 {
2718 LLVMValueRef indir_index, vtx_offset;
2719 unsigned const_index;
2720 LLVMValueRef args[9];
2721 unsigned param, vtx_offset_param;
2722 LLVMValueRef value[4], result;
2723 unsigned vertex_index;
2724 radv_get_deref_offset(ctx, instr->variables[0],
2725 false, &vertex_index, NULL,
2726 &const_index, &indir_index);
2727 vtx_offset_param = vertex_index;
2728 assert(vtx_offset_param < 6);
2729 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2730 LLVMConstInt(ctx->i32, 4, false), "");
2731
2732 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2733 for (unsigned i = 0; i < instr->num_components; i++) {
2734
2735 args[0] = ctx->esgs_ring;
2736 args[1] = vtx_offset;
2737 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2738 args[3] = ctx->i32zero;
2739 args[4] = ctx->i32one; /* OFFEN */
2740 args[5] = ctx->i32zero; /* IDXEN */
2741 args[6] = ctx->i32one; /* GLC */
2742 args[7] = ctx->i32zero; /* SLC */
2743 args[8] = ctx->i32zero; /* TFE */
2744
2745 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2746 ctx->i32, args, 9,
2747 AC_FUNC_ATTR_READONLY |
2748 AC_FUNC_ATTR_LEGACY);
2749 }
2750 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2751
2752 return result;
2753 }
2754
2755 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2756 nir_intrinsic_instr *instr)
2757 {
2758 LLVMValueRef values[8];
2759 int idx = instr->variables[0]->var->data.driver_location;
2760 int ve = instr->dest.ssa.num_components;
2761 LLVMValueRef indir_index;
2762 LLVMValueRef ret;
2763 unsigned const_index;
2764 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2765 instr->variables[0]->var->data.mode == nir_var_shader_in;
2766 radv_get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2767 &const_index, &indir_index);
2768
2769 if (instr->dest.ssa.bit_size == 64)
2770 ve *= 2;
2771
2772 switch (instr->variables[0]->var->data.mode) {
2773 case nir_var_shader_in:
2774 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2775 return load_tcs_input(ctx, instr);
2776 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2777 return load_tes_input(ctx, instr);
2778 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2779 return load_gs_input(ctx, instr);
2780 }
2781 for (unsigned chan = 0; chan < ve; chan++) {
2782 if (indir_index) {
2783 unsigned count = glsl_count_attribute_slots(
2784 instr->variables[0]->var->type,
2785 ctx->stage == MESA_SHADER_VERTEX);
2786 count -= chan / 4;
2787 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2788 &ctx->ac, ctx->inputs + idx + chan, count,
2789 4, false);
2790
2791 values[chan] = LLVMBuildExtractElement(ctx->builder,
2792 tmp_vec,
2793 indir_index, "");
2794 } else
2795 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2796 }
2797 break;
2798 case nir_var_local:
2799 for (unsigned chan = 0; chan < ve; chan++) {
2800 if (indir_index) {
2801 unsigned count = glsl_count_attribute_slots(
2802 instr->variables[0]->var->type, false);
2803 count -= chan / 4;
2804 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2805 &ctx->ac, ctx->locals + idx + chan, count,
2806 4, true);
2807
2808 values[chan] = LLVMBuildExtractElement(ctx->builder,
2809 tmp_vec,
2810 indir_index, "");
2811 } else {
2812 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2813 }
2814 }
2815 break;
2816 case nir_var_shader_out:
2817 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2818 return load_tcs_output(ctx, instr);
2819 for (unsigned chan = 0; chan < ve; chan++) {
2820 if (indir_index) {
2821 unsigned count = glsl_count_attribute_slots(
2822 instr->variables[0]->var->type, false);
2823 count -= chan / 4;
2824 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2825 &ctx->ac, ctx->outputs + idx + chan, count,
2826 4, true);
2827
2828 values[chan] = LLVMBuildExtractElement(ctx->builder,
2829 tmp_vec,
2830 indir_index, "");
2831 } else {
2832 values[chan] = LLVMBuildLoad(ctx->builder,
2833 ctx->outputs[idx + chan + const_index * 4],
2834 "");
2835 }
2836 }
2837 break;
2838 case nir_var_shared: {
2839 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2840 LLVMValueRef derived_ptr;
2841
2842 if (indir_index)
2843 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2844
2845 for (unsigned chan = 0; chan < ve; chan++) {
2846 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2847 if (indir_index)
2848 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2849 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2850
2851 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2852 }
2853 break;
2854 }
2855 default:
2856 unreachable("unhandle variable mode");
2857 }
2858 ret = ac_build_gather_values(&ctx->ac, values, ve);
2859 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2860 }
2861
2862 static void
2863 visit_store_var(struct nir_to_llvm_context *ctx,
2864 nir_intrinsic_instr *instr)
2865 {
2866 LLVMValueRef temp_ptr, value;
2867 int idx = instr->variables[0]->var->data.driver_location;
2868 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2869 int writemask = instr->const_index[0];
2870 LLVMValueRef indir_index;
2871 unsigned const_index;
2872 radv_get_deref_offset(ctx, instr->variables[0], false,
2873 NULL, NULL, &const_index, &indir_index);
2874
2875 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2876 int old_writemask = writemask;
2877
2878 src = LLVMBuildBitCast(ctx->builder, src,
2879 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2880 "");
2881
2882 writemask = 0;
2883 for (unsigned chan = 0; chan < 4; chan++) {
2884 if (old_writemask & (1 << chan))
2885 writemask |= 3u << (2 * chan);
2886 }
2887 }
2888
2889 switch (instr->variables[0]->var->data.mode) {
2890 case nir_var_shader_out:
2891
2892 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
2893 store_tcs_output(ctx, instr, src, writemask);
2894 return;
2895 }
2896
2897 for (unsigned chan = 0; chan < 8; chan++) {
2898 int stride = 4;
2899 if (!(writemask & (1 << chan)))
2900 continue;
2901
2902 value = llvm_extract_elem(ctx, src, chan);
2903
2904 if (instr->variables[0]->var->data.compact)
2905 stride = 1;
2906 if (indir_index) {
2907 unsigned count = glsl_count_attribute_slots(
2908 instr->variables[0]->var->type, false);
2909 count -= chan / 4;
2910 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2911 &ctx->ac, ctx->outputs + idx + chan, count,
2912 stride, true);
2913
2914 if (get_llvm_num_components(tmp_vec) > 1) {
2915 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2916 value, indir_index, "");
2917 } else
2918 tmp_vec = value;
2919 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2920 count, stride, tmp_vec);
2921
2922 } else {
2923 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2924
2925 LLVMBuildStore(ctx->builder, value, temp_ptr);
2926 }
2927 }
2928 break;
2929 case nir_var_local:
2930 for (unsigned chan = 0; chan < 8; chan++) {
2931 if (!(writemask & (1 << chan)))
2932 continue;
2933
2934 value = llvm_extract_elem(ctx, src, chan);
2935 if (indir_index) {
2936 unsigned count = glsl_count_attribute_slots(
2937 instr->variables[0]->var->type, false);
2938 count -= chan / 4;
2939 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2940 &ctx->ac, ctx->locals + idx + chan, count,
2941 4, true);
2942
2943 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2944 value, indir_index, "");
2945 build_store_values_extended(ctx, ctx->locals + idx + chan,
2946 count, 4, tmp_vec);
2947 } else {
2948 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2949
2950 LLVMBuildStore(ctx->builder, value, temp_ptr);
2951 }
2952 }
2953 break;
2954 case nir_var_shared: {
2955 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2956
2957 if (indir_index)
2958 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2959
2960 for (unsigned chan = 0; chan < 8; chan++) {
2961 if (!(writemask & (1 << chan)))
2962 continue;
2963 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2964 LLVMValueRef derived_ptr;
2965
2966 if (indir_index)
2967 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2968
2969 value = llvm_extract_elem(ctx, src, chan);
2970 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2971 LLVMBuildStore(ctx->builder,
2972 to_integer(ctx, value), derived_ptr);
2973 }
2974 break;
2975 }
2976 default:
2977 break;
2978 }
2979 }
2980
2981 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2982 {
2983 switch (dim) {
2984 case GLSL_SAMPLER_DIM_BUF:
2985 return 1;
2986 case GLSL_SAMPLER_DIM_1D:
2987 return array ? 2 : 1;
2988 case GLSL_SAMPLER_DIM_2D:
2989 return array ? 3 : 2;
2990 case GLSL_SAMPLER_DIM_MS:
2991 return array ? 4 : 3;
2992 case GLSL_SAMPLER_DIM_3D:
2993 case GLSL_SAMPLER_DIM_CUBE:
2994 return 3;
2995 case GLSL_SAMPLER_DIM_RECT:
2996 case GLSL_SAMPLER_DIM_SUBPASS:
2997 return 2;
2998 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2999 return 3;
3000 default:
3001 break;
3002 }
3003 return 0;
3004 }
3005
3006
3007
3008 /* Adjust the sample index according to FMASK.
3009 *
3010 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3011 * which is the identity mapping. Each nibble says which physical sample
3012 * should be fetched to get that sample.
3013 *
3014 * For example, 0x11111100 means there are only 2 samples stored and
3015 * the second sample covers 3/4 of the pixel. When reading samples 0
3016 * and 1, return physical sample 0 (determined by the first two 0s
3017 * in FMASK), otherwise return physical sample 1.
3018 *
3019 * The sample index should be adjusted as follows:
3020 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3021 */
3022 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
3023 LLVMValueRef coord_x, LLVMValueRef coord_y,
3024 LLVMValueRef coord_z,
3025 LLVMValueRef sample_index,
3026 LLVMValueRef fmask_desc_ptr)
3027 {
3028 LLVMValueRef fmask_load_address[4];
3029 LLVMValueRef res;
3030
3031 fmask_load_address[0] = coord_x;
3032 fmask_load_address[1] = coord_y;
3033 if (coord_z) {
3034 fmask_load_address[2] = coord_z;
3035 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3036 }
3037
3038 struct ac_image_args args = {0};
3039
3040 args.opcode = ac_image_load;
3041 args.da = coord_z ? true : false;
3042 args.resource = fmask_desc_ptr;
3043 args.dmask = 0xf;
3044 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
3045
3046 res = ac_build_image_opcode(&ctx->ac, &args);
3047
3048 res = to_integer(ctx, res);
3049 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3050 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3051
3052 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3053 res,
3054 ctx->i32zero, "");
3055
3056 LLVMValueRef sample_index4 =
3057 LLVMBuildMul(ctx->builder, sample_index, four, "");
3058 LLVMValueRef shifted_fmask =
3059 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3060 LLVMValueRef final_sample =
3061 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3062
3063 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3064 * resource descriptor is 0 (invalid),
3065 */
3066 LLVMValueRef fmask_desc =
3067 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3068 ctx->v8i32, "");
3069
3070 LLVMValueRef fmask_word1 =
3071 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3072 ctx->i32one, "");
3073
3074 LLVMValueRef word1_is_nonzero =
3075 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3076 fmask_word1, ctx->i32zero, "");
3077
3078 /* Replace the MSAA sample index. */
3079 sample_index =
3080 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3081 final_sample, sample_index, "");
3082 return sample_index;
3083 }
3084
3085 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
3086 nir_intrinsic_instr *instr)
3087 {
3088 const struct glsl_type *type = instr->variables[0]->var->type;
3089 if(instr->variables[0]->deref.child)
3090 type = instr->variables[0]->deref.child->type;
3091
3092 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3093 LLVMValueRef coords[4];
3094 LLVMValueRef masks[] = {
3095 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
3096 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
3097 };
3098 LLVMValueRef res;
3099 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
3100
3101 int count;
3102 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3103 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3104 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3105 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3106 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3107
3108 count = image_type_to_components_count(dim,
3109 glsl_sampler_type_is_array(type));
3110
3111 if (is_ms) {
3112 LLVMValueRef fmask_load_address[3];
3113 int chan;
3114
3115 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3116 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
3117 if (glsl_sampler_type_is_array(type))
3118 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
3119 else
3120 fmask_load_address[2] = NULL;
3121 if (add_frag_pos) {
3122 for (chan = 0; chan < 2; ++chan)
3123 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3124 }
3125 sample_index = adjust_sample_index_using_fmask(ctx,
3126 fmask_load_address[0],
3127 fmask_load_address[1],
3128 fmask_load_address[2],
3129 sample_index,
3130 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
3131 }
3132 if (count == 1) {
3133 if (instr->src[0].ssa->num_components)
3134 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3135 else
3136 res = src0;
3137 } else {
3138 int chan;
3139 if (is_ms)
3140 count--;
3141 for (chan = 0; chan < count; ++chan) {
3142 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
3143 }
3144
3145 if (add_frag_pos) {
3146 for (chan = 0; chan < count; ++chan)
3147 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3148 }
3149 if (is_ms) {
3150 coords[count] = sample_index;
3151 count++;
3152 }
3153
3154 if (count == 3) {
3155 coords[3] = LLVMGetUndef(ctx->i32);
3156 count = 4;
3157 }
3158 res = ac_build_gather_values(&ctx->ac, coords, count);
3159 }
3160 return res;
3161 }
3162
3163 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
3164 nir_intrinsic_instr *instr)
3165 {
3166 LLVMValueRef params[7];
3167 LLVMValueRef res;
3168 char intrinsic_name[64];
3169 const nir_variable *var = instr->variables[0]->var;
3170 const struct glsl_type *type = var->type;
3171 if(instr->variables[0]->deref.child)
3172 type = instr->variables[0]->deref.child->type;
3173
3174 type = glsl_without_array(type);
3175 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3176 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3177 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3178 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3179 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3180 params[3] = ctx->i1false; /* glc */
3181 params[4] = ctx->i1false; /* slc */
3182 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
3183 params, 5, 0);
3184
3185 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
3186 res = to_integer(ctx, res);
3187 } else {
3188 bool is_da = glsl_sampler_type_is_array(type) ||
3189 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3190 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3191 LLVMValueRef glc = ctx->i1false;
3192 LLVMValueRef slc = ctx->i1false;
3193
3194 params[0] = get_image_coords(ctx, instr);
3195 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3196 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3197 if (HAVE_LLVM <= 0x0309) {
3198 params[3] = ctx->i1false; /* r128 */
3199 params[4] = da;
3200 params[5] = glc;
3201 params[6] = slc;
3202 } else {
3203 LLVMValueRef lwe = ctx->i1false;
3204 params[3] = glc;
3205 params[4] = slc;
3206 params[5] = lwe;
3207 params[6] = da;
3208 }
3209
3210 ac_get_image_intr_name("llvm.amdgcn.image.load",
3211 ctx->v4f32, /* vdata */
3212 LLVMTypeOf(params[0]), /* coords */
3213 LLVMTypeOf(params[1]), /* rsrc */
3214 intrinsic_name, sizeof(intrinsic_name));
3215
3216 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
3217 params, 7, AC_FUNC_ATTR_READONLY);
3218 }
3219 return to_integer(ctx, res);
3220 }
3221
3222 static void visit_image_store(struct nir_to_llvm_context *ctx,
3223 nir_intrinsic_instr *instr)
3224 {
3225 LLVMValueRef params[8];
3226 char intrinsic_name[64];
3227 const nir_variable *var = instr->variables[0]->var;
3228 const struct glsl_type *type = glsl_without_array(var->type);
3229
3230 if (ctx->stage == MESA_SHADER_FRAGMENT)
3231 ctx->shader_info->fs.writes_memory = true;
3232
3233 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3234 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
3235 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3236 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3237 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3238 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3239 params[4] = ctx->i1false; /* glc */
3240 params[5] = ctx->i1false; /* slc */
3241 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
3242 params, 6, 0);
3243 } else {
3244 bool is_da = glsl_sampler_type_is_array(type) ||
3245 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3246 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3247 LLVMValueRef glc = ctx->i1false;
3248 LLVMValueRef slc = ctx->i1false;
3249
3250 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
3251 params[1] = get_image_coords(ctx, instr); /* coords */
3252 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3253 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3254 if (HAVE_LLVM <= 0x0309) {
3255 params[4] = ctx->i1false; /* r128 */
3256 params[5] = da;
3257 params[6] = glc;
3258 params[7] = slc;
3259 } else {
3260 LLVMValueRef lwe = ctx->i1false;
3261 params[4] = glc;
3262 params[5] = slc;
3263 params[6] = lwe;
3264 params[7] = da;
3265 }
3266
3267 ac_get_image_intr_name("llvm.amdgcn.image.store",
3268 LLVMTypeOf(params[0]), /* vdata */
3269 LLVMTypeOf(params[1]), /* coords */
3270 LLVMTypeOf(params[2]), /* rsrc */
3271 intrinsic_name, sizeof(intrinsic_name));
3272
3273 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
3274 params, 8, 0);
3275 }
3276
3277 }
3278
3279 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
3280 nir_intrinsic_instr *instr)
3281 {
3282 LLVMValueRef params[6];
3283 int param_count = 0;
3284 const nir_variable *var = instr->variables[0]->var;
3285
3286 const char *base_name = "llvm.amdgcn.image.atomic";
3287 const char *atomic_name;
3288 LLVMValueRef coords;
3289 char intrinsic_name[32], coords_type[8];
3290 const struct glsl_type *type = glsl_without_array(var->type);
3291
3292 if (ctx->stage == MESA_SHADER_FRAGMENT)
3293 ctx->shader_info->fs.writes_memory = true;
3294
3295 params[param_count++] = get_src(ctx, instr->src[2]);
3296 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3297 params[param_count++] = get_src(ctx, instr->src[3]);
3298
3299 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3300 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3301 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3302 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3303 params[param_count++] = ctx->i32zero; /* voffset */
3304 params[param_count++] = ctx->i1false; /* glc */
3305 params[param_count++] = ctx->i1false; /* slc */
3306 } else {
3307 bool da = glsl_sampler_type_is_array(type) ||
3308 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3309
3310 coords = params[param_count++] = get_image_coords(ctx, instr);
3311 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3312 params[param_count++] = ctx->i1false; /* r128 */
3313 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
3314 params[param_count++] = ctx->i1false; /* slc */
3315 }
3316
3317 switch (instr->intrinsic) {
3318 case nir_intrinsic_image_atomic_add:
3319 atomic_name = "add";
3320 break;
3321 case nir_intrinsic_image_atomic_min:
3322 atomic_name = "smin";
3323 break;
3324 case nir_intrinsic_image_atomic_max:
3325 atomic_name = "smax";
3326 break;
3327 case nir_intrinsic_image_atomic_and:
3328 atomic_name = "and";
3329 break;
3330 case nir_intrinsic_image_atomic_or:
3331 atomic_name = "or";
3332 break;
3333 case nir_intrinsic_image_atomic_xor:
3334 atomic_name = "xor";
3335 break;
3336 case nir_intrinsic_image_atomic_exchange:
3337 atomic_name = "swap";
3338 break;
3339 case nir_intrinsic_image_atomic_comp_swap:
3340 atomic_name = "cmpswap";
3341 break;
3342 default:
3343 abort();
3344 }
3345 build_int_type_name(LLVMTypeOf(coords),
3346 coords_type, sizeof(coords_type));
3347
3348 snprintf(intrinsic_name, sizeof(intrinsic_name),
3349 "%s.%s.%s", base_name, atomic_name, coords_type);
3350 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
3351 }
3352
3353 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
3354 nir_intrinsic_instr *instr)
3355 {
3356 LLVMValueRef res;
3357 const nir_variable *var = instr->variables[0]->var;
3358 const struct glsl_type *type = instr->variables[0]->var->type;
3359 bool da = glsl_sampler_type_is_array(var->type) ||
3360 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3361 if(instr->variables[0]->deref.child)
3362 type = instr->variables[0]->deref.child->type;
3363
3364 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3365 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
3366
3367 struct ac_image_args args = { 0 };
3368
3369 args.da = da;
3370 args.dmask = 0xf;
3371 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3372 args.opcode = ac_image_get_resinfo;
3373 args.addr = ctx->i32zero;
3374
3375 res = ac_build_image_opcode(&ctx->ac, &args);
3376
3377 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3378 glsl_sampler_type_is_array(type)) {
3379 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3380 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3381 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
3382 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3383 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
3384 }
3385 return res;
3386 }
3387
3388 #define NOOP_WAITCNT 0xf7f
3389 #define LGKM_CNT 0x07f
3390 #define VM_CNT 0xf70
3391
3392 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3393 unsigned simm16)
3394 {
3395 LLVMValueRef args[1] = {
3396 LLVMConstInt(ctx->i32, simm16, false),
3397 };
3398 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3399 ctx->voidt, args, 1, 0);
3400 }
3401
3402 static void emit_barrier(struct nir_to_llvm_context *ctx)
3403 {
3404 /* SI only (thanks to a hw bug workaround):
3405 * The real barrier instruction isn’t needed, because an entire patch
3406 * always fits into a single wave.
3407 */
3408 if (ctx->options->chip_class == SI &&
3409 ctx->stage == MESA_SHADER_TESS_CTRL) {
3410 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3411 return;
3412 }
3413 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3414 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3415 }
3416
3417 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3418 nir_intrinsic_instr *instr)
3419 {
3420 LLVMValueRef cond;
3421 ctx->shader_info->fs.can_discard = true;
3422
3423 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3424 get_src(ctx, instr->src[0]),
3425 ctx->i32zero, "");
3426
3427 cond = LLVMBuildSelect(ctx->builder, cond,
3428 LLVMConstReal(ctx->f32, -1.0f),
3429 ctx->f32zero, "");
3430 ac_build_kill(&ctx->ac, cond);
3431 }
3432
3433 static LLVMValueRef
3434 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3435 {
3436 LLVMValueRef result;
3437 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3438 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3439 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3440
3441 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3442 }
3443
3444 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3445 nir_intrinsic_instr *instr)
3446 {
3447 LLVMValueRef ptr, result;
3448 int idx = instr->variables[0]->var->data.driver_location;
3449 LLVMValueRef src = get_src(ctx, instr->src[0]);
3450 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3451
3452 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3453 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3454 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3455 ptr, src, src1,
3456 LLVMAtomicOrderingSequentiallyConsistent,
3457 LLVMAtomicOrderingSequentiallyConsistent,
3458 false);
3459 } else {
3460 LLVMAtomicRMWBinOp op;
3461 switch (instr->intrinsic) {
3462 case nir_intrinsic_var_atomic_add:
3463 op = LLVMAtomicRMWBinOpAdd;
3464 break;
3465 case nir_intrinsic_var_atomic_umin:
3466 op = LLVMAtomicRMWBinOpUMin;
3467 break;
3468 case nir_intrinsic_var_atomic_umax:
3469 op = LLVMAtomicRMWBinOpUMax;
3470 break;
3471 case nir_intrinsic_var_atomic_imin:
3472 op = LLVMAtomicRMWBinOpMin;
3473 break;
3474 case nir_intrinsic_var_atomic_imax:
3475 op = LLVMAtomicRMWBinOpMax;
3476 break;
3477 case nir_intrinsic_var_atomic_and:
3478 op = LLVMAtomicRMWBinOpAnd;
3479 break;
3480 case nir_intrinsic_var_atomic_or:
3481 op = LLVMAtomicRMWBinOpOr;
3482 break;
3483 case nir_intrinsic_var_atomic_xor:
3484 op = LLVMAtomicRMWBinOpXor;
3485 break;
3486 case nir_intrinsic_var_atomic_exchange:
3487 op = LLVMAtomicRMWBinOpXchg;
3488 break;
3489 default:
3490 return NULL;
3491 }
3492
3493 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
3494 LLVMAtomicOrderingSequentiallyConsistent,
3495 false);
3496 }
3497 return result;
3498 }
3499
3500 #define INTERP_CENTER 0
3501 #define INTERP_CENTROID 1
3502 #define INTERP_SAMPLE 2
3503
3504 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3505 enum glsl_interp_mode interp, unsigned location)
3506 {
3507 switch (interp) {
3508 case INTERP_MODE_FLAT:
3509 default:
3510 return NULL;
3511 case INTERP_MODE_SMOOTH:
3512 case INTERP_MODE_NONE:
3513 if (location == INTERP_CENTER)
3514 return ctx->persp_center;
3515 else if (location == INTERP_CENTROID)
3516 return ctx->persp_centroid;
3517 else if (location == INTERP_SAMPLE)
3518 return ctx->persp_sample;
3519 break;
3520 case INTERP_MODE_NOPERSPECTIVE:
3521 if (location == INTERP_CENTER)
3522 return ctx->linear_center;
3523 else if (location == INTERP_CENTROID)
3524 return ctx->linear_centroid;
3525 else if (location == INTERP_SAMPLE)
3526 return ctx->linear_sample;
3527 break;
3528 }
3529 return NULL;
3530 }
3531
3532 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3533 LLVMValueRef sample_id)
3534 {
3535 LLVMValueRef result;
3536 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3537
3538 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3539 const_array(ctx->v2f32, 64), "");
3540
3541 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3542 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3543
3544 return result;
3545 }
3546
3547 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3548 {
3549 LLVMValueRef values[2];
3550
3551 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
3552 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
3553 return ac_build_gather_values(&ctx->ac, values, 2);
3554 }
3555
3556 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3557 nir_intrinsic_instr *instr)
3558 {
3559 LLVMValueRef result[2];
3560 LLVMValueRef interp_param, attr_number;
3561 unsigned location;
3562 unsigned chan;
3563 LLVMValueRef src_c0, src_c1;
3564 LLVMValueRef src0;
3565 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3566 switch (instr->intrinsic) {
3567 case nir_intrinsic_interp_var_at_centroid:
3568 location = INTERP_CENTROID;
3569 break;
3570 case nir_intrinsic_interp_var_at_sample:
3571 case nir_intrinsic_interp_var_at_offset:
3572 location = INTERP_CENTER;
3573 src0 = get_src(ctx, instr->src[0]);
3574 break;
3575 default:
3576 break;
3577 }
3578
3579 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3580 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3581 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3582 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3583 LLVMValueRef sample_position;
3584 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3585
3586 /* fetch sample ID */
3587 sample_position = load_sample_position(ctx, src0);
3588
3589 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3590 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3591 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3592 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3593 }
3594 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3595 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3596
3597 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3598 LLVMValueRef ij_out[2];
3599 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3600
3601 /*
3602 * take the I then J parameters, and the DDX/Y for it, and
3603 * calculate the IJ inputs for the interpolator.
3604 * temp1 = ddx * offset/sample.x + I;
3605 * interp_param.I = ddy * offset/sample.y + temp1;
3606 * temp1 = ddx * offset/sample.x + J;
3607 * interp_param.J = ddy * offset/sample.y + temp1;
3608 */
3609 for (unsigned i = 0; i < 2; i++) {
3610 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3611 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3612 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3613 ddxy_out, ix_ll, "");
3614 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3615 ddxy_out, iy_ll, "");
3616 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3617 interp_param, ix_ll, "");
3618 LLVMValueRef temp1, temp2;
3619
3620 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3621 ctx->f32, "");
3622
3623 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3624 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3625
3626 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3627 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3628
3629 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3630 temp2, ctx->i32, "");
3631 }
3632 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3633
3634 }
3635
3636 for (chan = 0; chan < 2; chan++) {
3637 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3638
3639 if (interp_param) {
3640 interp_param = LLVMBuildBitCast(ctx->builder,
3641 interp_param, LLVMVectorType(ctx->f32, 2), "");
3642 LLVMValueRef i = LLVMBuildExtractElement(
3643 ctx->builder, interp_param, ctx->i32zero, "");
3644 LLVMValueRef j = LLVMBuildExtractElement(
3645 ctx->builder, interp_param, ctx->i32one, "");
3646
3647 result[chan] = ac_build_fs_interp(&ctx->ac,
3648 llvm_chan, attr_number,
3649 ctx->prim_mask, i, j);
3650 } else {
3651 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3652 LLVMConstInt(ctx->i32, 2, false),
3653 llvm_chan, attr_number,
3654 ctx->prim_mask);
3655 }
3656 }
3657 return ac_build_gather_values(&ctx->ac, result, 2);
3658 }
3659
3660 static void
3661 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3662 nir_intrinsic_instr *instr)
3663 {
3664 LLVMValueRef gs_next_vertex;
3665 LLVMValueRef can_emit, kill;
3666 int idx;
3667
3668 assert(instr->const_index[0] == 0);
3669 /* Write vertex attribute values to GSVS ring */
3670 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3671 ctx->gs_next_vertex,
3672 "");
3673
3674 /* If this thread has already emitted the declared maximum number of
3675 * vertices, kill it: excessive vertex emissions are not supposed to
3676 * have any effect, and GS threads have no externally observable
3677 * effects other than emitting vertices.
3678 */
3679 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3680 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3681
3682 kill = LLVMBuildSelect(ctx->builder, can_emit,
3683 LLVMConstReal(ctx->f32, 1.0f),
3684 LLVMConstReal(ctx->f32, -1.0f), "");
3685 ac_build_kill(&ctx->ac, kill);
3686
3687 /* loop num outputs */
3688 idx = 0;
3689 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3690 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3691 int length = 4;
3692 int slot = idx;
3693 int slot_inc = 1;
3694
3695 if (!(ctx->output_mask & (1ull << i)))
3696 continue;
3697
3698 if (i == VARYING_SLOT_CLIP_DIST0) {
3699 /* pack clip and cull into a single set of slots */
3700 length = ctx->num_output_clips + ctx->num_output_culls;
3701 if (length > 4)
3702 slot_inc = 2;
3703 }
3704 for (unsigned j = 0; j < length; j++) {
3705 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3706 out_ptr[j], "");
3707 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3708 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3709 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3710
3711 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3712
3713 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3714 out_val, 1,
3715 voffset, ctx->gs2vs_offset, 0,
3716 1, 1, true, true);
3717 }
3718 idx += slot_inc;
3719 }
3720
3721 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3722 ctx->i32one, "");
3723 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3724
3725 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3726 }
3727
3728 static void
3729 visit_end_primitive(struct nir_to_llvm_context *ctx,
3730 nir_intrinsic_instr *instr)
3731 {
3732 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3733 }
3734
3735 static LLVMValueRef
3736 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3737 nir_intrinsic_instr *instr)
3738 {
3739 LLVMValueRef coord[4] = {
3740 ctx->tes_u,
3741 ctx->tes_v,
3742 ctx->f32zero,
3743 ctx->f32zero,
3744 };
3745
3746 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3747 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3748 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3749
3750 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3751 return LLVMBuildBitCast(ctx->builder, result,
3752 get_def_type(ctx, &instr->dest.ssa), "");
3753 }
3754
3755 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3756 nir_intrinsic_instr *instr)
3757 {
3758 LLVMValueRef result = NULL;
3759
3760 switch (instr->intrinsic) {
3761 case nir_intrinsic_load_work_group_id: {
3762 result = ctx->workgroup_ids;
3763 break;
3764 }
3765 case nir_intrinsic_load_base_vertex: {
3766 result = ctx->base_vertex;
3767 break;
3768 }
3769 case nir_intrinsic_load_vertex_id_zero_base: {
3770 result = ctx->vertex_id;
3771 break;
3772 }
3773 case nir_intrinsic_load_local_invocation_id: {
3774 result = ctx->local_invocation_ids;
3775 break;
3776 }
3777 case nir_intrinsic_load_base_instance:
3778 result = ctx->start_instance;
3779 break;
3780 case nir_intrinsic_load_draw_id:
3781 result = ctx->draw_index;
3782 break;
3783 case nir_intrinsic_load_invocation_id:
3784 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3785 result = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
3786 else
3787 result = ctx->gs_invocation_id;
3788 break;
3789 case nir_intrinsic_load_primitive_id:
3790 if (ctx->stage == MESA_SHADER_GEOMETRY)
3791 result = ctx->gs_prim_id;
3792 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
3793 result = ctx->tcs_patch_id;
3794 else if (ctx->stage == MESA_SHADER_TESS_EVAL)
3795 result = ctx->tes_patch_id;
3796 else
3797 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3798 break;
3799 case nir_intrinsic_load_sample_id:
3800 ctx->shader_info->fs.force_persample = true;
3801 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3802 break;
3803 case nir_intrinsic_load_sample_pos:
3804 ctx->shader_info->fs.force_persample = true;
3805 result = load_sample_pos(ctx);
3806 break;
3807 case nir_intrinsic_load_sample_mask_in:
3808 result = ctx->sample_coverage;
3809 break;
3810 case nir_intrinsic_load_front_face:
3811 result = ctx->front_face;
3812 break;
3813 case nir_intrinsic_load_instance_id:
3814 result = ctx->instance_id;
3815 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3816 ctx->shader_info->vs.vgpr_comp_cnt);
3817 break;
3818 case nir_intrinsic_load_num_work_groups:
3819 result = ctx->num_work_groups;
3820 break;
3821 case nir_intrinsic_load_local_invocation_index:
3822 result = visit_load_local_invocation_index(ctx);
3823 break;
3824 case nir_intrinsic_load_push_constant:
3825 result = visit_load_push_constant(ctx, instr);
3826 break;
3827 case nir_intrinsic_vulkan_resource_index:
3828 result = visit_vulkan_resource_index(ctx, instr);
3829 break;
3830 case nir_intrinsic_store_ssbo:
3831 visit_store_ssbo(ctx, instr);
3832 break;
3833 case nir_intrinsic_load_ssbo:
3834 result = visit_load_buffer(ctx, instr);
3835 break;
3836 case nir_intrinsic_ssbo_atomic_add:
3837 case nir_intrinsic_ssbo_atomic_imin:
3838 case nir_intrinsic_ssbo_atomic_umin:
3839 case nir_intrinsic_ssbo_atomic_imax:
3840 case nir_intrinsic_ssbo_atomic_umax:
3841 case nir_intrinsic_ssbo_atomic_and:
3842 case nir_intrinsic_ssbo_atomic_or:
3843 case nir_intrinsic_ssbo_atomic_xor:
3844 case nir_intrinsic_ssbo_atomic_exchange:
3845 case nir_intrinsic_ssbo_atomic_comp_swap:
3846 result = visit_atomic_ssbo(ctx, instr);
3847 break;
3848 case nir_intrinsic_load_ubo:
3849 result = visit_load_ubo_buffer(ctx, instr);
3850 break;
3851 case nir_intrinsic_get_buffer_size:
3852 result = visit_get_buffer_size(ctx, instr);
3853 break;
3854 case nir_intrinsic_load_var:
3855 result = visit_load_var(ctx, instr);
3856 break;
3857 case nir_intrinsic_store_var:
3858 visit_store_var(ctx, instr);
3859 break;
3860 case nir_intrinsic_image_load:
3861 result = visit_image_load(ctx, instr);
3862 break;
3863 case nir_intrinsic_image_store:
3864 visit_image_store(ctx, instr);
3865 break;
3866 case nir_intrinsic_image_atomic_add:
3867 case nir_intrinsic_image_atomic_min:
3868 case nir_intrinsic_image_atomic_max:
3869 case nir_intrinsic_image_atomic_and:
3870 case nir_intrinsic_image_atomic_or:
3871 case nir_intrinsic_image_atomic_xor:
3872 case nir_intrinsic_image_atomic_exchange:
3873 case nir_intrinsic_image_atomic_comp_swap:
3874 result = visit_image_atomic(ctx, instr);
3875 break;
3876 case nir_intrinsic_image_size:
3877 result = visit_image_size(ctx, instr);
3878 break;
3879 case nir_intrinsic_discard:
3880 ctx->shader_info->fs.can_discard = true;
3881 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3882 ctx->voidt,
3883 NULL, 0, AC_FUNC_ATTR_LEGACY);
3884 break;
3885 case nir_intrinsic_discard_if:
3886 emit_discard_if(ctx, instr);
3887 break;
3888 case nir_intrinsic_memory_barrier:
3889 emit_waitcnt(ctx, VM_CNT);
3890 break;
3891 case nir_intrinsic_barrier:
3892 emit_barrier(ctx);
3893 break;
3894 case nir_intrinsic_var_atomic_add:
3895 case nir_intrinsic_var_atomic_imin:
3896 case nir_intrinsic_var_atomic_umin:
3897 case nir_intrinsic_var_atomic_imax:
3898 case nir_intrinsic_var_atomic_umax:
3899 case nir_intrinsic_var_atomic_and:
3900 case nir_intrinsic_var_atomic_or:
3901 case nir_intrinsic_var_atomic_xor:
3902 case nir_intrinsic_var_atomic_exchange:
3903 case nir_intrinsic_var_atomic_comp_swap:
3904 result = visit_var_atomic(ctx, instr);
3905 break;
3906 case nir_intrinsic_interp_var_at_centroid:
3907 case nir_intrinsic_interp_var_at_sample:
3908 case nir_intrinsic_interp_var_at_offset:
3909 result = visit_interp(ctx, instr);
3910 break;
3911 case nir_intrinsic_emit_vertex:
3912 visit_emit_vertex(ctx, instr);
3913 break;
3914 case nir_intrinsic_end_primitive:
3915 visit_end_primitive(ctx, instr);
3916 break;
3917 case nir_intrinsic_load_tess_coord:
3918 result = visit_load_tess_coord(ctx, instr);
3919 break;
3920 case nir_intrinsic_load_patch_vertices_in:
3921 result = LLVMConstInt(ctx->i32, ctx->options->key.tcs.input_vertices, false);
3922 break;
3923 default:
3924 fprintf(stderr, "Unknown intrinsic: ");
3925 nir_print_instr(&instr->instr, stderr);
3926 fprintf(stderr, "\n");
3927 break;
3928 }
3929 if (result) {
3930 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3931 }
3932 }
3933
3934 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3935 nir_deref_var *deref,
3936 enum desc_type desc_type)
3937 {
3938 unsigned desc_set = deref->var->data.descriptor_set;
3939 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3940 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3941 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3942 unsigned offset = binding->offset;
3943 unsigned stride = binding->size;
3944 unsigned type_size;
3945 LLVMBuilderRef builder = ctx->builder;
3946 LLVMTypeRef type;
3947 LLVMValueRef index = NULL;
3948 unsigned constant_index = 0;
3949
3950 assert(deref->var->data.binding < layout->binding_count);
3951
3952 switch (desc_type) {
3953 case DESC_IMAGE:
3954 type = ctx->v8i32;
3955 type_size = 32;
3956 break;
3957 case DESC_FMASK:
3958 type = ctx->v8i32;
3959 offset += 32;
3960 type_size = 32;
3961 break;
3962 case DESC_SAMPLER:
3963 type = ctx->v4i32;
3964 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3965 offset += 64;
3966
3967 type_size = 16;
3968 break;
3969 case DESC_BUFFER:
3970 type = ctx->v4i32;
3971 type_size = 16;
3972 break;
3973 default:
3974 unreachable("invalid desc_type\n");
3975 }
3976
3977 if (deref->deref.child) {
3978 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3979
3980 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3981 offset += child->base_offset * stride;
3982 if (child->deref_array_type == nir_deref_array_type_indirect) {
3983 index = get_src(ctx, child->indirect);
3984 }
3985
3986 constant_index = child->base_offset;
3987 }
3988 if (desc_type == DESC_SAMPLER && binding->immutable_samplers_offset &&
3989 (!index || binding->immutable_samplers_equal)) {
3990 if (binding->immutable_samplers_equal)
3991 constant_index = 0;
3992
3993 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
3994
3995 LLVMValueRef constants[] = {
3996 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
3997 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
3998 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
3999 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4000 };
4001 return ac_build_gather_values(&ctx->ac, constants, 4);
4002 }
4003
4004 assert(stride % type_size == 0);
4005
4006 if (!index)
4007 index = ctx->i32zero;
4008
4009 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4010
4011 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4012 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4013
4014 return ac_build_indexed_load_const(&ctx->ac, list, index);
4015 }
4016
4017 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
4018 struct ac_image_args *args,
4019 nir_tex_instr *instr,
4020 nir_texop op,
4021 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4022 LLVMValueRef *param, unsigned count,
4023 unsigned dmask)
4024 {
4025 unsigned is_rect = 0;
4026 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4027
4028 if (op == nir_texop_lod)
4029 da = false;
4030 /* Pad to power of two vector */
4031 while (count < util_next_power_of_two(count))
4032 param[count++] = LLVMGetUndef(ctx->i32);
4033
4034 if (count > 1)
4035 args->addr = ac_build_gather_values(&ctx->ac, param, count);
4036 else
4037 args->addr = param[0];
4038
4039 args->resource = res_ptr;
4040 args->sampler = samp_ptr;
4041
4042 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4043 args->addr = param[0];
4044 return;
4045 }
4046
4047 args->dmask = dmask;
4048 args->unorm = is_rect;
4049 args->da = da;
4050 }
4051
4052 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4053 *
4054 * SI-CI:
4055 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4056 * filtering manually. The driver sets img7 to a mask clearing
4057 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4058 * s_and_b32 samp0, samp0, img7
4059 *
4060 * VI:
4061 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4062 */
4063 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
4064 LLVMValueRef res, LLVMValueRef samp)
4065 {
4066 LLVMBuilderRef builder = ctx->builder;
4067 LLVMValueRef img7, samp0;
4068
4069 if (ctx->options->chip_class >= VI)
4070 return samp;
4071
4072 img7 = LLVMBuildExtractElement(builder, res,
4073 LLVMConstInt(ctx->i32, 7, 0), "");
4074 samp0 = LLVMBuildExtractElement(builder, samp,
4075 LLVMConstInt(ctx->i32, 0, 0), "");
4076 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4077 return LLVMBuildInsertElement(builder, samp, samp0,
4078 LLVMConstInt(ctx->i32, 0, 0), "");
4079 }
4080
4081 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
4082 nir_tex_instr *instr,
4083 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4084 LLVMValueRef *fmask_ptr)
4085 {
4086 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4087 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
4088 else
4089 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
4090 if (samp_ptr) {
4091 if (instr->sampler)
4092 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
4093 else
4094 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
4095 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4096 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4097 }
4098 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4099 instr->op == nir_texop_samples_identical))
4100 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
4101 }
4102
4103 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
4104 LLVMValueRef coord)
4105 {
4106 coord = to_float(ctx, coord);
4107 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4108 coord = to_integer(ctx, coord);
4109 return coord;
4110 }
4111
4112 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
4113 {
4114 LLVMValueRef result = NULL;
4115 struct ac_image_args args = { 0 };
4116 unsigned dmask = 0xf;
4117 LLVMValueRef address[16];
4118 LLVMValueRef coords[5];
4119 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4120 LLVMValueRef bias = NULL, offsets = NULL;
4121 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4122 LLVMValueRef ddx = NULL, ddy = NULL;
4123 LLVMValueRef derivs[6];
4124 unsigned chan, count = 0;
4125 unsigned const_src = 0, num_deriv_comp = 0;
4126
4127 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4128
4129 for (unsigned i = 0; i < instr->num_srcs; i++) {
4130 switch (instr->src[i].src_type) {
4131 case nir_tex_src_coord:
4132 coord = get_src(ctx, instr->src[i].src);
4133 break;
4134 case nir_tex_src_projector:
4135 break;
4136 case nir_tex_src_comparator:
4137 comparator = get_src(ctx, instr->src[i].src);
4138 break;
4139 case nir_tex_src_offset:
4140 offsets = get_src(ctx, instr->src[i].src);
4141 const_src = i;
4142 break;
4143 case nir_tex_src_bias:
4144 bias = get_src(ctx, instr->src[i].src);
4145 break;
4146 case nir_tex_src_lod:
4147 lod = get_src(ctx, instr->src[i].src);
4148 break;
4149 case nir_tex_src_ms_index:
4150 sample_index = get_src(ctx, instr->src[i].src);
4151 break;
4152 case nir_tex_src_ms_mcs:
4153 break;
4154 case nir_tex_src_ddx:
4155 ddx = get_src(ctx, instr->src[i].src);
4156 num_deriv_comp = instr->src[i].src.ssa->num_components;
4157 break;
4158 case nir_tex_src_ddy:
4159 ddy = get_src(ctx, instr->src[i].src);
4160 break;
4161 case nir_tex_src_texture_offset:
4162 case nir_tex_src_sampler_offset:
4163 case nir_tex_src_plane:
4164 default:
4165 break;
4166 }
4167 }
4168
4169 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4170 result = get_buffer_size(ctx, res_ptr, true);
4171 goto write_result;
4172 }
4173
4174 if (instr->op == nir_texop_texture_samples) {
4175 LLVMValueRef res, samples, is_msaa;
4176 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
4177 samples = LLVMBuildExtractElement(ctx->builder, res,
4178 LLVMConstInt(ctx->i32, 3, false), "");
4179 is_msaa = LLVMBuildLShr(ctx->builder, samples,
4180 LLVMConstInt(ctx->i32, 28, false), "");
4181 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
4182 LLVMConstInt(ctx->i32, 0xe, false), "");
4183 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
4184 LLVMConstInt(ctx->i32, 0xe, false), "");
4185
4186 samples = LLVMBuildLShr(ctx->builder, samples,
4187 LLVMConstInt(ctx->i32, 16, false), "");
4188 samples = LLVMBuildAnd(ctx->builder, samples,
4189 LLVMConstInt(ctx->i32, 0xf, false), "");
4190 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
4191 samples, "");
4192 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
4193 ctx->i32one, "");
4194 result = samples;
4195 goto write_result;
4196 }
4197
4198 if (coord)
4199 for (chan = 0; chan < instr->coord_components; chan++)
4200 coords[chan] = llvm_extract_elem(ctx, coord, chan);
4201
4202 if (offsets && instr->op != nir_texop_txf) {
4203 LLVMValueRef offset[3], pack;
4204 for (chan = 0; chan < 3; ++chan)
4205 offset[chan] = ctx->i32zero;
4206
4207 args.offset = true;
4208 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4209 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
4210 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
4211 LLVMConstInt(ctx->i32, 0x3f, false), "");
4212 if (chan)
4213 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
4214 LLVMConstInt(ctx->i32, chan * 8, false), "");
4215 }
4216 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
4217 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
4218 address[count++] = pack;
4219
4220 }
4221 /* pack LOD bias value */
4222 if (instr->op == nir_texop_txb && bias) {
4223 address[count++] = bias;
4224 }
4225
4226 /* Pack depth comparison value */
4227 if (instr->is_shadow && comparator) {
4228 address[count++] = llvm_extract_elem(ctx, comparator, 0);
4229 }
4230
4231 /* pack derivatives */
4232 if (ddx || ddy) {
4233 switch (instr->sampler_dim) {
4234 case GLSL_SAMPLER_DIM_3D:
4235 case GLSL_SAMPLER_DIM_CUBE:
4236 num_deriv_comp = 3;
4237 break;
4238 case GLSL_SAMPLER_DIM_2D:
4239 default:
4240 num_deriv_comp = 2;
4241 break;
4242 case GLSL_SAMPLER_DIM_1D:
4243 num_deriv_comp = 1;
4244 break;
4245 }
4246
4247 for (unsigned i = 0; i < num_deriv_comp; i++) {
4248 derivs[i] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
4249 derivs[num_deriv_comp + i] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
4250 }
4251 }
4252
4253 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4254 if (instr->is_array && instr->op != nir_texop_lod)
4255 coords[3] = apply_round_slice(ctx, coords[3]);
4256 for (chan = 0; chan < instr->coord_components; chan++)
4257 coords[chan] = to_float(ctx, coords[chan]);
4258 if (instr->coord_components == 3)
4259 coords[3] = LLVMGetUndef(ctx->f32);
4260 ac_prepare_cube_coords(&ctx->ac,
4261 instr->op == nir_texop_txd, instr->is_array,
4262 coords, derivs);
4263 if (num_deriv_comp)
4264 num_deriv_comp--;
4265 }
4266
4267 if (ddx || ddy) {
4268 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4269 address[count++] = derivs[i];
4270 }
4271
4272 /* Pack texture coordinates */
4273 if (coord) {
4274 address[count++] = coords[0];
4275 if (instr->coord_components > 1) {
4276 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4277 coords[1] = apply_round_slice(ctx, coords[1]);
4278 }
4279 address[count++] = coords[1];
4280 }
4281 if (instr->coord_components > 2) {
4282 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4283 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4284 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4285 instr->op != nir_texop_txf) {
4286 coords[2] = apply_round_slice(ctx, coords[2]);
4287 }
4288 address[count++] = coords[2];
4289 }
4290 }
4291
4292 /* Pack LOD */
4293 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
4294 address[count++] = lod;
4295 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4296 address[count++] = sample_index;
4297 } else if(instr->op == nir_texop_txs) {
4298 count = 0;
4299 if (lod)
4300 address[count++] = lod;
4301 else
4302 address[count++] = ctx->i32zero;
4303 }
4304
4305 for (chan = 0; chan < count; chan++) {
4306 address[chan] = LLVMBuildBitCast(ctx->builder,
4307 address[chan], ctx->i32, "");
4308 }
4309
4310 if (instr->op == nir_texop_samples_identical) {
4311 LLVMValueRef txf_address[4];
4312 struct ac_image_args txf_args = { 0 };
4313 unsigned txf_count = count;
4314 memcpy(txf_address, address, sizeof(txf_address));
4315
4316 if (!instr->is_array)
4317 txf_address[2] = ctx->i32zero;
4318 txf_address[3] = ctx->i32zero;
4319
4320 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
4321 fmask_ptr, NULL,
4322 txf_address, txf_count, 0xf);
4323
4324 result = build_tex_intrinsic(ctx, instr, &txf_args);
4325
4326 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4327 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
4328 goto write_result;
4329 }
4330
4331 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4332 instr->op != nir_texop_txs) {
4333 unsigned sample_chan = instr->is_array ? 3 : 2;
4334 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
4335 address[0],
4336 address[1],
4337 instr->is_array ? address[2] : NULL,
4338 address[sample_chan],
4339 fmask_ptr);
4340 }
4341
4342 if (offsets && instr->op == nir_texop_txf) {
4343 nir_const_value *const_offset =
4344 nir_src_as_const_value(instr->src[const_src].src);
4345 int num_offsets = instr->src[const_src].src.ssa->num_components;
4346 assert(const_offset);
4347 num_offsets = MIN2(num_offsets, instr->coord_components);
4348 if (num_offsets > 2)
4349 address[2] = LLVMBuildAdd(ctx->builder,
4350 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
4351 if (num_offsets > 1)
4352 address[1] = LLVMBuildAdd(ctx->builder,
4353 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
4354 address[0] = LLVMBuildAdd(ctx->builder,
4355 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
4356
4357 }
4358
4359 /* TODO TG4 support */
4360 if (instr->op == nir_texop_tg4) {
4361 if (instr->is_shadow)
4362 dmask = 1;
4363 else
4364 dmask = 1 << instr->component;
4365 }
4366 set_tex_fetch_args(ctx, &args, instr, instr->op,
4367 res_ptr, samp_ptr, address, count, dmask);
4368
4369 result = build_tex_intrinsic(ctx, instr, &args);
4370
4371 if (instr->op == nir_texop_query_levels)
4372 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
4373 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4374 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4375 else if (instr->op == nir_texop_txs &&
4376 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4377 instr->is_array) {
4378 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
4379 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
4380 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
4381 z = LLVMBuildSDiv(ctx->builder, z, six, "");
4382 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
4383 } else if (instr->dest.ssa.num_components != 4)
4384 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
4385
4386 write_result:
4387 if (result) {
4388 assert(instr->dest.is_ssa);
4389 result = to_integer(ctx, result);
4390 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4391 }
4392 }
4393
4394
4395 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
4396 {
4397 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4398 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
4399
4400 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4401 _mesa_hash_table_insert(ctx->phis, instr, result);
4402 }
4403
4404 static void visit_post_phi(struct nir_to_llvm_context *ctx,
4405 nir_phi_instr *instr,
4406 LLVMValueRef llvm_phi)
4407 {
4408 nir_foreach_phi_src(src, instr) {
4409 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4410 LLVMValueRef llvm_src = get_src(ctx, src->src);
4411
4412 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4413 }
4414 }
4415
4416 static void phi_post_pass(struct nir_to_llvm_context *ctx)
4417 {
4418 struct hash_entry *entry;
4419 hash_table_foreach(ctx->phis, entry) {
4420 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4421 (LLVMValueRef)entry->data);
4422 }
4423 }
4424
4425
4426 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
4427 nir_ssa_undef_instr *instr)
4428 {
4429 unsigned num_components = instr->def.num_components;
4430 LLVMValueRef undef;
4431
4432 if (num_components == 1)
4433 undef = LLVMGetUndef(ctx->i32);
4434 else {
4435 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
4436 }
4437 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4438 }
4439
4440 static void visit_jump(struct nir_to_llvm_context *ctx,
4441 nir_jump_instr *instr)
4442 {
4443 switch (instr->type) {
4444 case nir_jump_break:
4445 LLVMBuildBr(ctx->builder, ctx->break_block);
4446 LLVMClearInsertionPosition(ctx->builder);
4447 break;
4448 case nir_jump_continue:
4449 LLVMBuildBr(ctx->builder, ctx->continue_block);
4450 LLVMClearInsertionPosition(ctx->builder);
4451 break;
4452 default:
4453 fprintf(stderr, "Unknown NIR jump instr: ");
4454 nir_print_instr(&instr->instr, stderr);
4455 fprintf(stderr, "\n");
4456 abort();
4457 }
4458 }
4459
4460 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4461 struct exec_list *list);
4462
4463 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
4464 {
4465 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
4466 nir_foreach_instr(instr, block)
4467 {
4468 switch (instr->type) {
4469 case nir_instr_type_alu:
4470 visit_alu(ctx, nir_instr_as_alu(instr));
4471 break;
4472 case nir_instr_type_load_const:
4473 visit_load_const(ctx, nir_instr_as_load_const(instr));
4474 break;
4475 case nir_instr_type_intrinsic:
4476 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4477 break;
4478 case nir_instr_type_tex:
4479 visit_tex(ctx, nir_instr_as_tex(instr));
4480 break;
4481 case nir_instr_type_phi:
4482 visit_phi(ctx, nir_instr_as_phi(instr));
4483 break;
4484 case nir_instr_type_ssa_undef:
4485 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4486 break;
4487 case nir_instr_type_jump:
4488 visit_jump(ctx, nir_instr_as_jump(instr));
4489 break;
4490 default:
4491 fprintf(stderr, "Unknown NIR instr type: ");
4492 nir_print_instr(instr, stderr);
4493 fprintf(stderr, "\n");
4494 abort();
4495 }
4496 }
4497
4498 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4499 }
4500
4501 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
4502 {
4503 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4504
4505 LLVMBasicBlockRef merge_block =
4506 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4507 LLVMBasicBlockRef if_block =
4508 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4509 LLVMBasicBlockRef else_block = merge_block;
4510 if (!exec_list_is_empty(&if_stmt->else_list))
4511 else_block = LLVMAppendBasicBlockInContext(
4512 ctx->context, ctx->main_function, "");
4513
4514 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
4515 LLVMConstInt(ctx->i32, 0, false), "");
4516 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
4517
4518 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
4519 visit_cf_list(ctx, &if_stmt->then_list);
4520 if (LLVMGetInsertBlock(ctx->builder))
4521 LLVMBuildBr(ctx->builder, merge_block);
4522
4523 if (!exec_list_is_empty(&if_stmt->else_list)) {
4524 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
4525 visit_cf_list(ctx, &if_stmt->else_list);
4526 if (LLVMGetInsertBlock(ctx->builder))
4527 LLVMBuildBr(ctx->builder, merge_block);
4528 }
4529
4530 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
4531 }
4532
4533 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
4534 {
4535 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4536 LLVMBasicBlockRef break_parent = ctx->break_block;
4537
4538 ctx->continue_block =
4539 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4540 ctx->break_block =
4541 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4542
4543 LLVMBuildBr(ctx->builder, ctx->continue_block);
4544 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4545 visit_cf_list(ctx, &loop->body);
4546
4547 if (LLVMGetInsertBlock(ctx->builder))
4548 LLVMBuildBr(ctx->builder, ctx->continue_block);
4549 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4550
4551 ctx->continue_block = continue_parent;
4552 ctx->break_block = break_parent;
4553 }
4554
4555 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4556 struct exec_list *list)
4557 {
4558 foreach_list_typed(nir_cf_node, node, node, list)
4559 {
4560 switch (node->type) {
4561 case nir_cf_node_block:
4562 visit_block(ctx, nir_cf_node_as_block(node));
4563 break;
4564
4565 case nir_cf_node_if:
4566 visit_if(ctx, nir_cf_node_as_if(node));
4567 break;
4568
4569 case nir_cf_node_loop:
4570 visit_loop(ctx, nir_cf_node_as_loop(node));
4571 break;
4572
4573 default:
4574 assert(0);
4575 }
4576 }
4577 }
4578
4579 static void
4580 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4581 struct nir_variable *variable)
4582 {
4583 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4584 LLVMValueRef t_offset;
4585 LLVMValueRef t_list;
4586 LLVMValueRef input;
4587 LLVMValueRef buffer_index;
4588 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4589 int idx = variable->data.location;
4590 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4591
4592 variable->data.driver_location = idx * 4;
4593
4594 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4595 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4596 ctx->start_instance, "");
4597 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4598 ctx->shader_info->vs.vgpr_comp_cnt);
4599 } else
4600 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4601 ctx->base_vertex, "");
4602
4603 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4604 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4605
4606 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4607
4608 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4609 buffer_index,
4610 LLVMConstInt(ctx->i32, 0, false),
4611 true);
4612
4613 for (unsigned chan = 0; chan < 4; chan++) {
4614 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4615 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4616 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4617 input, llvm_chan, ""));
4618 }
4619 }
4620 }
4621
4622 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4623 unsigned attr,
4624 LLVMValueRef interp_param,
4625 LLVMValueRef prim_mask,
4626 LLVMValueRef result[4])
4627 {
4628 LLVMValueRef attr_number;
4629 unsigned chan;
4630 LLVMValueRef i, j;
4631 bool interp = interp_param != NULL;
4632
4633 attr_number = LLVMConstInt(ctx->i32, attr, false);
4634
4635 /* fs.constant returns the param from the middle vertex, so it's not
4636 * really useful for flat shading. It's meant to be used for custom
4637 * interpolation (but the intrinsic can't fetch from the other two
4638 * vertices).
4639 *
4640 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4641 * to do the right thing. The only reason we use fs.constant is that
4642 * fs.interp cannot be used on integers, because they can be equal
4643 * to NaN.
4644 */
4645 if (interp) {
4646 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4647 LLVMVectorType(ctx->f32, 2), "");
4648
4649 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4650 ctx->i32zero, "");
4651 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4652 ctx->i32one, "");
4653 }
4654
4655 for (chan = 0; chan < 4; chan++) {
4656 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4657
4658 if (interp) {
4659 result[chan] = ac_build_fs_interp(&ctx->ac,
4660 llvm_chan,
4661 attr_number,
4662 prim_mask, i, j);
4663 } else {
4664 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4665 LLVMConstInt(ctx->i32, 2, false),
4666 llvm_chan,
4667 attr_number,
4668 prim_mask);
4669 }
4670 }
4671 }
4672
4673 static void
4674 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4675 struct nir_variable *variable)
4676 {
4677 int idx = variable->data.location;
4678 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4679 LLVMValueRef interp;
4680
4681 variable->data.driver_location = idx * 4;
4682 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4683
4684 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4685 unsigned interp_type;
4686 if (variable->data.sample) {
4687 interp_type = INTERP_SAMPLE;
4688 ctx->shader_info->fs.force_persample = true;
4689 } else if (variable->data.centroid)
4690 interp_type = INTERP_CENTROID;
4691 else
4692 interp_type = INTERP_CENTER;
4693
4694 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4695 } else
4696 interp = NULL;
4697
4698 for (unsigned i = 0; i < attrib_count; ++i)
4699 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4700
4701 }
4702
4703 static void
4704 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4705 struct nir_variable *variable)
4706 {
4707 switch (ctx->stage) {
4708 case MESA_SHADER_VERTEX:
4709 handle_vs_input_decl(ctx, variable);
4710 break;
4711 case MESA_SHADER_FRAGMENT:
4712 handle_fs_input_decl(ctx, variable);
4713 break;
4714 default:
4715 break;
4716 }
4717
4718 }
4719
4720 static void
4721 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4722 struct nir_shader *nir)
4723 {
4724 unsigned index = 0;
4725 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4726 LLVMValueRef interp_param;
4727 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4728
4729 if (!(ctx->input_mask & (1ull << i)))
4730 continue;
4731
4732 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4733 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4734 interp_param = *inputs;
4735 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4736 inputs);
4737
4738 if (!interp_param)
4739 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4740 ++index;
4741 } else if (i == VARYING_SLOT_POS) {
4742 for(int i = 0; i < 3; ++i)
4743 inputs[i] = ctx->frag_pos[i];
4744
4745 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4746 }
4747 }
4748 ctx->shader_info->fs.num_interp = index;
4749 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4750 ctx->shader_info->fs.has_pcoord = true;
4751 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4752 ctx->shader_info->fs.prim_id_input = true;
4753 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4754 ctx->shader_info->fs.layer_input = true;
4755 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4756 }
4757
4758 static LLVMValueRef
4759 ac_build_alloca(struct nir_to_llvm_context *ctx,
4760 LLVMTypeRef type,
4761 const char *name)
4762 {
4763 LLVMBuilderRef builder = ctx->builder;
4764 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4765 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4766 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4767 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4768 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4769 LLVMValueRef res;
4770
4771 if (first_instr) {
4772 LLVMPositionBuilderBefore(first_builder, first_instr);
4773 } else {
4774 LLVMPositionBuilderAtEnd(first_builder, first_block);
4775 }
4776
4777 res = LLVMBuildAlloca(first_builder, type, name);
4778 LLVMBuildStore(builder, LLVMConstNull(type), res);
4779
4780 LLVMDisposeBuilder(first_builder);
4781
4782 return res;
4783 }
4784
4785 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4786 LLVMTypeRef type,
4787 const char *name)
4788 {
4789 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4790 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4791 return ptr;
4792 }
4793
4794 static void
4795 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4796 struct nir_variable *variable)
4797 {
4798 int idx = variable->data.location + variable->data.index;
4799 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4800 uint64_t mask_attribs;
4801 variable->data.driver_location = idx * 4;
4802
4803 /* tess ctrl has it's own load/store paths for outputs */
4804 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4805 return;
4806
4807 mask_attribs = ((1ull << attrib_count) - 1) << idx;
4808 if (ctx->stage == MESA_SHADER_VERTEX ||
4809 ctx->stage == MESA_SHADER_TESS_EVAL ||
4810 ctx->stage == MESA_SHADER_GEOMETRY) {
4811 if (idx == VARYING_SLOT_CLIP_DIST0) {
4812 int length = ctx->num_output_clips + ctx->num_output_culls;
4813 if (ctx->stage == MESA_SHADER_VERTEX) {
4814 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4815 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4816 }
4817 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4818 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4819 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4820 }
4821
4822 if (length > 4)
4823 attrib_count = 2;
4824 else
4825 attrib_count = 1;
4826 mask_attribs = 1ull << idx;
4827 }
4828 }
4829
4830 for (unsigned i = 0; i < attrib_count; ++i) {
4831 for (unsigned chan = 0; chan < 4; chan++) {
4832 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4833 si_build_alloca_undef(ctx, ctx->f32, "");
4834 }
4835 }
4836 ctx->output_mask |= mask_attribs;
4837 }
4838
4839 static void
4840 setup_locals(struct nir_to_llvm_context *ctx,
4841 struct nir_function *func)
4842 {
4843 int i, j;
4844 ctx->num_locals = 0;
4845 nir_foreach_variable(variable, &func->impl->locals) {
4846 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4847 variable->data.driver_location = ctx->num_locals * 4;
4848 ctx->num_locals += attrib_count;
4849 }
4850 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4851 if (!ctx->locals)
4852 return;
4853
4854 for (i = 0; i < ctx->num_locals; i++) {
4855 for (j = 0; j < 4; j++) {
4856 ctx->locals[i * 4 + j] =
4857 si_build_alloca_undef(ctx, ctx->f32, "temp");
4858 }
4859 }
4860 }
4861
4862 static LLVMValueRef
4863 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4864 {
4865 v = to_float(ctx, v);
4866 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4867 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4868 }
4869
4870
4871 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4872 LLVMValueRef src0, LLVMValueRef src1)
4873 {
4874 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4875 LLVMValueRef comp[2];
4876
4877 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4878 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4879 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4880 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4881 }
4882
4883 /* Initialize arguments for the shader export intrinsic */
4884 static void
4885 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4886 LLVMValueRef *values,
4887 unsigned target,
4888 struct ac_export_args *args)
4889 {
4890 /* Default is 0xf. Adjusted below depending on the format. */
4891 args->enabled_channels = 0xf;
4892
4893 /* Specify whether the EXEC mask represents the valid mask */
4894 args->valid_mask = 0;
4895
4896 /* Specify whether this is the last export */
4897 args->done = 0;
4898
4899 /* Specify the target we are exporting */
4900 args->target = target;
4901
4902 args->compr = false;
4903 args->out[0] = LLVMGetUndef(ctx->f32);
4904 args->out[1] = LLVMGetUndef(ctx->f32);
4905 args->out[2] = LLVMGetUndef(ctx->f32);
4906 args->out[3] = LLVMGetUndef(ctx->f32);
4907
4908 if (!values)
4909 return;
4910
4911 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4912 LLVMValueRef val[4];
4913 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4914 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4915 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4916
4917 switch(col_format) {
4918 case V_028714_SPI_SHADER_ZERO:
4919 args->enabled_channels = 0; /* writemask */
4920 args->target = V_008DFC_SQ_EXP_NULL;
4921 break;
4922
4923 case V_028714_SPI_SHADER_32_R:
4924 args->enabled_channels = 1;
4925 args->out[0] = values[0];
4926 break;
4927
4928 case V_028714_SPI_SHADER_32_GR:
4929 args->enabled_channels = 0x3;
4930 args->out[0] = values[0];
4931 args->out[1] = values[1];
4932 break;
4933
4934 case V_028714_SPI_SHADER_32_AR:
4935 args->enabled_channels = 0x9;
4936 args->out[0] = values[0];
4937 args->out[3] = values[3];
4938 break;
4939
4940 case V_028714_SPI_SHADER_FP16_ABGR:
4941 args->compr = 1;
4942
4943 for (unsigned chan = 0; chan < 2; chan++) {
4944 LLVMValueRef pack_args[2] = {
4945 values[2 * chan],
4946 values[2 * chan + 1]
4947 };
4948 LLVMValueRef packed;
4949
4950 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
4951 args->out[chan] = packed;
4952 }
4953 break;
4954
4955 case V_028714_SPI_SHADER_UNORM16_ABGR:
4956 for (unsigned chan = 0; chan < 4; chan++) {
4957 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
4958 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4959 LLVMConstReal(ctx->f32, 65535), "");
4960 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4961 LLVMConstReal(ctx->f32, 0.5), "");
4962 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4963 ctx->i32, "");
4964 }
4965
4966 args->compr = 1;
4967 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4968 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4969 break;
4970
4971 case V_028714_SPI_SHADER_SNORM16_ABGR:
4972 for (unsigned chan = 0; chan < 4; chan++) {
4973 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4974 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4975 LLVMConstReal(ctx->f32, 32767), "");
4976
4977 /* If positive, add 0.5, else add -0.5. */
4978 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4979 LLVMBuildSelect(ctx->builder,
4980 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4981 val[chan], ctx->f32zero, ""),
4982 LLVMConstReal(ctx->f32, 0.5),
4983 LLVMConstReal(ctx->f32, -0.5), ""), "");
4984 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4985 }
4986
4987 args->compr = 1;
4988 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4989 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4990 break;
4991
4992 case V_028714_SPI_SHADER_UINT16_ABGR: {
4993 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4994
4995 for (unsigned chan = 0; chan < 4; chan++) {
4996 val[chan] = to_integer(ctx, values[chan]);
4997 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4998 }
4999
5000 args->compr = 1;
5001 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5002 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5003 break;
5004 }
5005
5006 case V_028714_SPI_SHADER_SINT16_ABGR: {
5007 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5008 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5009
5010 /* Clamp. */
5011 for (unsigned chan = 0; chan < 4; chan++) {
5012 val[chan] = to_integer(ctx, values[chan]);
5013 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
5014 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
5015 }
5016
5017 args->compr = 1;
5018 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5019 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5020 break;
5021 }
5022
5023 default:
5024 case V_028714_SPI_SHADER_32_ABGR:
5025 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5026 break;
5027 }
5028 } else
5029 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5030
5031 for (unsigned i = 0; i < 4; ++i)
5032 args->out[i] = to_float(ctx, args->out[i]);
5033 }
5034
5035 static void
5036 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5037 struct ac_vs_output_info *outinfo)
5038 {
5039 uint32_t param_count = 0;
5040 unsigned target;
5041 unsigned pos_idx, num_pos_exports = 0;
5042 struct ac_export_args args, pos_args[4] = {};
5043 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5044 int i;
5045
5046 outinfo->prim_id_output = 0xffffffff;
5047 outinfo->layer_output = 0xffffffff;
5048 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5049 LLVMValueRef slots[8];
5050 unsigned j;
5051
5052 if (outinfo->cull_dist_mask)
5053 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5054
5055 i = VARYING_SLOT_CLIP_DIST0;
5056 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5057 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5058 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5059
5060 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5061 slots[i] = LLVMGetUndef(ctx->f32);
5062
5063 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5064 target = V_008DFC_SQ_EXP_POS + 3;
5065 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5066 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5067 &args, sizeof(args));
5068 }
5069
5070 target = V_008DFC_SQ_EXP_POS + 2;
5071 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5072 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5073 &args, sizeof(args));
5074
5075 }
5076
5077 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5078 LLVMValueRef values[4];
5079 if (!(ctx->output_mask & (1ull << i)))
5080 continue;
5081
5082 for (unsigned j = 0; j < 4; j++)
5083 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5084 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5085
5086 if (i == VARYING_SLOT_POS) {
5087 target = V_008DFC_SQ_EXP_POS;
5088 } else if (i == VARYING_SLOT_CLIP_DIST0) {
5089 continue;
5090 } else if (i == VARYING_SLOT_PSIZ) {
5091 outinfo->writes_pointsize = true;
5092 psize_value = values[0];
5093 continue;
5094 } else if (i == VARYING_SLOT_LAYER) {
5095 outinfo->writes_layer = true;
5096 layer_value = values[0];
5097 outinfo->layer_output = param_count;
5098 target = V_008DFC_SQ_EXP_PARAM + param_count;
5099 param_count++;
5100 } else if (i == VARYING_SLOT_VIEWPORT) {
5101 outinfo->writes_viewport_index = true;
5102 viewport_index_value = values[0];
5103 continue;
5104 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5105 outinfo->prim_id_output = param_count;
5106 target = V_008DFC_SQ_EXP_PARAM + param_count;
5107 param_count++;
5108 } else if (i >= VARYING_SLOT_VAR0) {
5109 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5110 target = V_008DFC_SQ_EXP_PARAM + param_count;
5111 param_count++;
5112 }
5113
5114 si_llvm_init_export_args(ctx, values, target, &args);
5115
5116 if (target >= V_008DFC_SQ_EXP_POS &&
5117 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5118 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5119 &args, sizeof(args));
5120 } else {
5121 ac_build_export(&ctx->ac, &args);
5122 }
5123 }
5124
5125 /* We need to add the position output manually if it's missing. */
5126 if (!pos_args[0].out[0]) {
5127 pos_args[0].enabled_channels = 0xf;
5128 pos_args[0].valid_mask = 0;
5129 pos_args[0].done = 0;
5130 pos_args[0].target = V_008DFC_SQ_EXP_POS;
5131 pos_args[0].compr = 0;
5132 pos_args[0].out[0] = ctx->f32zero; /* X */
5133 pos_args[0].out[1] = ctx->f32zero; /* Y */
5134 pos_args[0].out[2] = ctx->f32zero; /* Z */
5135 pos_args[0].out[3] = ctx->f32one; /* W */
5136 }
5137
5138 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5139 (outinfo->writes_layer == true ? 4 : 0) |
5140 (outinfo->writes_viewport_index == true ? 8 : 0));
5141 if (mask) {
5142 pos_args[1].enabled_channels = mask;
5143 pos_args[1].valid_mask = 0;
5144 pos_args[1].done = 0;
5145 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5146 pos_args[1].compr = 0;
5147 pos_args[1].out[0] = ctx->f32zero; /* X */
5148 pos_args[1].out[1] = ctx->f32zero; /* Y */
5149 pos_args[1].out[2] = ctx->f32zero; /* Z */
5150 pos_args[1].out[3] = ctx->f32zero; /* W */
5151
5152 if (outinfo->writes_pointsize == true)
5153 pos_args[1].out[0] = psize_value;
5154 if (outinfo->writes_layer == true)
5155 pos_args[1].out[2] = layer_value;
5156 if (outinfo->writes_viewport_index == true)
5157 pos_args[1].out[3] = viewport_index_value;
5158 }
5159 for (i = 0; i < 4; i++) {
5160 if (pos_args[i].out[0])
5161 num_pos_exports++;
5162 }
5163
5164 pos_idx = 0;
5165 for (i = 0; i < 4; i++) {
5166 if (!pos_args[i].out[0])
5167 continue;
5168
5169 /* Specify the target we are exporting */
5170 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5171 if (pos_idx == num_pos_exports)
5172 pos_args[i].done = 1;
5173 ac_build_export(&ctx->ac, &pos_args[i]);
5174 }
5175
5176 outinfo->pos_exports = num_pos_exports;
5177 outinfo->param_exports = param_count;
5178 }
5179
5180 static void
5181 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5182 struct ac_es_output_info *outinfo)
5183 {
5184 int j;
5185 uint64_t max_output_written = 0;
5186 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5187 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5188 int param_index;
5189 int length = 4;
5190
5191 if (!(ctx->output_mask & (1ull << i)))
5192 continue;
5193
5194 if (i == VARYING_SLOT_CLIP_DIST0)
5195 length = ctx->num_output_clips + ctx->num_output_culls;
5196
5197 param_index = shader_io_get_unique_index(i);
5198
5199 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5200
5201 for (j = 0; j < length; j++) {
5202 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5203 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5204
5205 ac_build_buffer_store_dword(&ctx->ac,
5206 ctx->esgs_ring,
5207 out_val, 1,
5208 NULL, ctx->es2gs_offset,
5209 (4 * param_index + j) * 4,
5210 1, 1, true, true);
5211 }
5212 }
5213 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5214 }
5215
5216 static void
5217 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5218 {
5219 LLVMValueRef vertex_id = ctx->rel_auto_id;
5220 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5221 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5222 vertex_dw_stride, "");
5223
5224 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5225 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5226 int length = 4;
5227
5228 if (!(ctx->output_mask & (1ull << i)))
5229 continue;
5230
5231 if (i == VARYING_SLOT_CLIP_DIST0)
5232 length = ctx->num_output_clips + ctx->num_output_culls;
5233 int param = shader_io_get_unique_index(i);
5234 mark_tess_output(ctx, false, param);
5235 if (length > 4)
5236 mark_tess_output(ctx, false, param + 1);
5237 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5238 LLVMConstInt(ctx->i32, param * 4, false),
5239 "");
5240 for (unsigned j = 0; j < length; j++) {
5241 lds_store(ctx, dw_addr,
5242 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5243 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5244 }
5245 }
5246 }
5247
5248 struct ac_build_if_state
5249 {
5250 struct nir_to_llvm_context *ctx;
5251 LLVMValueRef condition;
5252 LLVMBasicBlockRef entry_block;
5253 LLVMBasicBlockRef true_block;
5254 LLVMBasicBlockRef false_block;
5255 LLVMBasicBlockRef merge_block;
5256 };
5257
5258 static LLVMBasicBlockRef
5259 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5260 {
5261 LLVMBasicBlockRef current_block;
5262 LLVMBasicBlockRef next_block;
5263 LLVMBasicBlockRef new_block;
5264
5265 /* get current basic block */
5266 current_block = LLVMGetInsertBlock(ctx->builder);
5267
5268 /* chqeck if there's another block after this one */
5269 next_block = LLVMGetNextBasicBlock(current_block);
5270 if (next_block) {
5271 /* insert the new block before the next block */
5272 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5273 }
5274 else {
5275 /* append new block after current block */
5276 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5277 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5278 }
5279 return new_block;
5280 }
5281
5282 static void
5283 ac_nir_build_if(struct ac_build_if_state *ifthen,
5284 struct nir_to_llvm_context *ctx,
5285 LLVMValueRef condition)
5286 {
5287 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5288
5289 memset(ifthen, 0, sizeof *ifthen);
5290 ifthen->ctx = ctx;
5291 ifthen->condition = condition;
5292 ifthen->entry_block = block;
5293
5294 /* create endif/merge basic block for the phi functions */
5295 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5296
5297 /* create/insert true_block before merge_block */
5298 ifthen->true_block =
5299 LLVMInsertBasicBlockInContext(ctx->context,
5300 ifthen->merge_block,
5301 "if-true-block");
5302
5303 /* successive code goes into the true block */
5304 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5305 }
5306
5307 /**
5308 * End a conditional.
5309 */
5310 static void
5311 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5312 {
5313 LLVMBuilderRef builder = ifthen->ctx->builder;
5314
5315 /* Insert branch to the merge block from current block */
5316 LLVMBuildBr(builder, ifthen->merge_block);
5317
5318 /*
5319 * Now patch in the various branch instructions.
5320 */
5321
5322 /* Insert the conditional branch instruction at the end of entry_block */
5323 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5324 if (ifthen->false_block) {
5325 /* we have an else clause */
5326 LLVMBuildCondBr(builder, ifthen->condition,
5327 ifthen->true_block, ifthen->false_block);
5328 }
5329 else {
5330 /* no else clause */
5331 LLVMBuildCondBr(builder, ifthen->condition,
5332 ifthen->true_block, ifthen->merge_block);
5333 }
5334
5335 /* Resume building code at end of the ifthen->merge_block */
5336 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5337 }
5338
5339 static void
5340 write_tess_factors(struct nir_to_llvm_context *ctx)
5341 {
5342 unsigned stride, outer_comps, inner_comps;
5343 struct ac_build_if_state if_ctx, inner_if_ctx;
5344 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5345 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5346 unsigned tess_inner_index, tess_outer_index;
5347 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5348 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5349 int i;
5350 emit_barrier(ctx);
5351
5352 switch (ctx->options->key.tcs.primitive_mode) {
5353 case GL_ISOLINES:
5354 stride = 2;
5355 outer_comps = 2;
5356 inner_comps = 0;
5357 break;
5358 case GL_TRIANGLES:
5359 stride = 4;
5360 outer_comps = 3;
5361 inner_comps = 1;
5362 break;
5363 case GL_QUADS:
5364 stride = 6;
5365 outer_comps = 4;
5366 inner_comps = 2;
5367 break;
5368 default:
5369 return;
5370 }
5371
5372 ac_nir_build_if(&if_ctx, ctx,
5373 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5374 invocation_id, ctx->i32zero, ""));
5375
5376 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5377 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5378
5379 mark_tess_output(ctx, true, tess_inner_index);
5380 mark_tess_output(ctx, true, tess_outer_index);
5381 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5382 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5383 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5384 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5385 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5386
5387 for (i = 0; i < 4; i++) {
5388 inner[i] = LLVMGetUndef(ctx->i32);
5389 outer[i] = LLVMGetUndef(ctx->i32);
5390 }
5391
5392 // LINES reverseal
5393 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5394 outer[0] = out[1] = lds_load(ctx, lds_outer);
5395 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5396 LLVMConstInt(ctx->i32, 1, false), "");
5397 outer[1] = out[0] = lds_load(ctx, lds_outer);
5398 } else {
5399 for (i = 0; i < outer_comps; i++) {
5400 outer[i] = out[i] =
5401 lds_load(ctx, lds_outer);
5402 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5403 LLVMConstInt(ctx->i32, 1, false), "");
5404 }
5405 for (i = 0; i < inner_comps; i++) {
5406 inner[i] = out[outer_comps+i] =
5407 lds_load(ctx, lds_inner);
5408 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5409 LLVMConstInt(ctx->i32, 1, false), "");
5410 }
5411 }
5412
5413 /* Convert the outputs to vectors for stores. */
5414 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5415 vec1 = NULL;
5416
5417 if (stride > 4)
5418 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5419
5420
5421 buffer = ctx->hs_ring_tess_factor;
5422 tf_base = ctx->tess_factor_offset;
5423 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5424 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5425
5426 ac_nir_build_if(&inner_if_ctx, ctx,
5427 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5428 rel_patch_id, ctx->i32zero, ""));
5429
5430 /* Store the dynamic HS control word. */
5431 ac_build_buffer_store_dword(&ctx->ac, buffer,
5432 LLVMConstInt(ctx->i32, 0x80000000, false),
5433 1, ctx->i32zero, tf_base,
5434 0, 1, 0, true, false);
5435 ac_nir_build_endif(&inner_if_ctx);
5436
5437 /* Store the tessellation factors. */
5438 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5439 MIN2(stride, 4), byteoffset, tf_base,
5440 4, 1, 0, true, false);
5441 if (vec1)
5442 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5443 stride - 4, byteoffset, tf_base,
5444 20, 1, 0, true, false);
5445
5446 //TODO store to offchip for TES to read - only if TES reads them
5447 if (1) {
5448 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5449 LLVMValueRef tf_inner_offset;
5450 unsigned param_outer, param_inner;
5451
5452 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5453 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5454 LLVMConstInt(ctx->i32, param_outer, 0));
5455
5456 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5457 util_next_power_of_two(outer_comps));
5458
5459 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5460 outer_comps, tf_outer_offset,
5461 ctx->oc_lds, 0, 1, 0, true, false);
5462 if (inner_comps) {
5463 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5464 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5465 LLVMConstInt(ctx->i32, param_inner, 0));
5466
5467 inner_vec = inner_comps == 1 ? inner[0] :
5468 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5469 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5470 inner_comps, tf_inner_offset,
5471 ctx->oc_lds, 0, 1, 0, true, false);
5472 }
5473 }
5474 ac_nir_build_endif(&if_ctx);
5475 }
5476
5477 static void
5478 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5479 {
5480 write_tess_factors(ctx);
5481 }
5482
5483 static void
5484 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5485 LLVMValueRef *color, unsigned param, bool is_last)
5486 {
5487
5488 struct ac_export_args args;
5489
5490 /* Export */
5491 si_llvm_init_export_args(ctx, color, param,
5492 &args);
5493
5494 if (is_last) {
5495 args.valid_mask = 1; /* whether the EXEC mask is valid */
5496 args.done = 1; /* DONE bit */
5497 } else if (!args.enabled_channels)
5498 return; /* unnecessary NULL export */
5499
5500 ac_build_export(&ctx->ac, &args);
5501 }
5502
5503 static void
5504 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5505 LLVMValueRef depth, LLVMValueRef stencil,
5506 LLVMValueRef samplemask)
5507 {
5508 struct ac_export_args args;
5509
5510 args.enabled_channels = 0;
5511 args.valid_mask = 1;
5512 args.done = 1;
5513 args.target = V_008DFC_SQ_EXP_MRTZ;
5514 args.compr = false;
5515
5516 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5517 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5518 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5519 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5520
5521 if (depth) {
5522 args.out[0] = depth;
5523 args.enabled_channels |= 0x1;
5524 }
5525
5526 if (stencil) {
5527 args.out[1] = stencil;
5528 args.enabled_channels |= 0x2;
5529 }
5530
5531 if (samplemask) {
5532 args.out[2] = samplemask;
5533 args.enabled_channels |= 0x4;
5534 }
5535
5536 /* SI (except OLAND) has a bug that it only looks
5537 * at the X writemask component. */
5538 if (ctx->options->chip_class == SI &&
5539 ctx->options->family != CHIP_OLAND)
5540 args.enabled_channels |= 0x1;
5541
5542 ac_build_export(&ctx->ac, &args);
5543 }
5544
5545 static void
5546 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5547 {
5548 unsigned index = 0;
5549 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5550
5551 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5552 LLVMValueRef values[4];
5553
5554 if (!(ctx->output_mask & (1ull << i)))
5555 continue;
5556
5557 if (i == FRAG_RESULT_DEPTH) {
5558 ctx->shader_info->fs.writes_z = true;
5559 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
5560 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5561 } else if (i == FRAG_RESULT_STENCIL) {
5562 ctx->shader_info->fs.writes_stencil = true;
5563 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
5564 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5565 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5566 ctx->shader_info->fs.writes_sample_mask = true;
5567 samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
5568 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5569 } else {
5570 bool last = false;
5571 for (unsigned j = 0; j < 4; j++)
5572 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5573 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5574
5575 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5576 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5577
5578 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
5579 index++;
5580 }
5581 }
5582
5583 if (depth || stencil || samplemask)
5584 si_export_mrt_z(ctx, depth, stencil, samplemask);
5585 else if (!index)
5586 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
5587
5588 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5589 }
5590
5591 static void
5592 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5593 {
5594 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5595 }
5596
5597 static void
5598 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
5599 {
5600 switch (ctx->stage) {
5601 case MESA_SHADER_VERTEX:
5602 if (ctx->options->key.vs.as_ls)
5603 handle_ls_outputs_post(ctx);
5604 else if (ctx->options->key.vs.as_es)
5605 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5606 else
5607 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
5608 break;
5609 case MESA_SHADER_FRAGMENT:
5610 handle_fs_outputs_post(ctx);
5611 break;
5612 case MESA_SHADER_GEOMETRY:
5613 emit_gs_epilogue(ctx);
5614 break;
5615 case MESA_SHADER_TESS_CTRL:
5616 handle_tcs_outputs_post(ctx);
5617 break;
5618 case MESA_SHADER_TESS_EVAL:
5619 if (ctx->options->key.tes.as_es)
5620 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
5621 else
5622 handle_vs_outputs_post(ctx, &ctx->shader_info->tes.outinfo);
5623 break;
5624 default:
5625 break;
5626 }
5627 }
5628
5629 static void
5630 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
5631 struct nir_variable *variable, uint32_t *offset, int idx)
5632 {
5633 unsigned size = glsl_count_attribute_slots(variable->type, false);
5634 variable->data.driver_location = *offset;
5635 *offset += size;
5636 }
5637
5638 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
5639 {
5640 LLVMPassManagerRef passmgr;
5641 /* Create the pass manager */
5642 passmgr = LLVMCreateFunctionPassManagerForModule(
5643 ctx->module);
5644
5645 /* This pass should eliminate all the load and store instructions */
5646 LLVMAddPromoteMemoryToRegisterPass(passmgr);
5647
5648 /* Add some optimization passes */
5649 LLVMAddScalarReplAggregatesPass(passmgr);
5650 LLVMAddLICMPass(passmgr);
5651 LLVMAddAggressiveDCEPass(passmgr);
5652 LLVMAddCFGSimplificationPass(passmgr);
5653 LLVMAddInstructionCombiningPass(passmgr);
5654
5655 /* Run the pass */
5656 LLVMInitializeFunctionPassManager(passmgr);
5657 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
5658 LLVMFinalizeFunctionPassManager(passmgr);
5659
5660 LLVMDisposeBuilder(ctx->builder);
5661 LLVMDisposePassManager(passmgr);
5662 }
5663
5664 static void
5665 ac_setup_rings(struct nir_to_llvm_context *ctx)
5666 {
5667 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
5668 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
5669 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
5670 }
5671
5672 if (ctx->is_gs_copy_shader) {
5673 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
5674 }
5675 if (ctx->stage == MESA_SHADER_GEOMETRY) {
5676 LLVMValueRef tmp;
5677 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
5678 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
5679
5680 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
5681
5682 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
5683 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
5684 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
5685 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
5686
5687 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
5688 }
5689
5690 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
5691 ctx->stage == MESA_SHADER_TESS_EVAL) {
5692 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
5693 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
5694 }
5695 }
5696
5697 static
5698 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
5699 struct nir_shader *nir,
5700 struct ac_shader_variant_info *shader_info,
5701 const struct ac_nir_compiler_options *options)
5702 {
5703 struct nir_to_llvm_context ctx = {0};
5704 struct nir_function *func;
5705 unsigned i;
5706 ctx.options = options;
5707 ctx.shader_info = shader_info;
5708 ctx.context = LLVMContextCreate();
5709 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5710
5711 ac_llvm_context_init(&ctx.ac, ctx.context);
5712 ctx.ac.module = ctx.module;
5713
5714 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
5715
5716 memset(shader_info, 0, sizeof(*shader_info));
5717
5718 ac_nir_shader_info_pass(nir, options, &shader_info->info);
5719
5720 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
5721
5722 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
5723 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
5724 LLVMSetDataLayout(ctx.module, data_layout_str);
5725 LLVMDisposeTargetData(data_layout);
5726 LLVMDisposeMessage(data_layout_str);
5727
5728 setup_types(&ctx);
5729
5730 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5731 ctx.ac.builder = ctx.builder;
5732 ctx.stage = nir->stage;
5733
5734 for (i = 0; i < AC_UD_MAX_SETS; i++)
5735 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
5736 for (i = 0; i < AC_UD_MAX_UD; i++)
5737 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
5738
5739 create_function(&ctx);
5740
5741 if (nir->stage == MESA_SHADER_COMPUTE) {
5742 int num_shared = 0;
5743 nir_foreach_variable(variable, &nir->shared)
5744 num_shared++;
5745 if (num_shared) {
5746 int idx = 0;
5747 uint32_t shared_size = 0;
5748 LLVMValueRef var;
5749 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
5750 nir_foreach_variable(variable, &nir->shared) {
5751 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
5752 idx++;
5753 }
5754
5755 shared_size *= 16;
5756 var = LLVMAddGlobalInAddressSpace(ctx.module,
5757 LLVMArrayType(ctx.i8, shared_size),
5758 "compute_lds",
5759 LOCAL_ADDR_SPACE);
5760 LLVMSetAlignment(var, 4);
5761 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
5762 }
5763 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
5764 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
5765
5766 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
5767 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
5768 ctx.tes_primitive_mode = nir->info->tess.primitive_mode;
5769 }
5770
5771 ac_setup_rings(&ctx);
5772
5773 nir_foreach_variable(variable, &nir->inputs)
5774 handle_shader_input_decl(&ctx, variable);
5775
5776 if (nir->stage == MESA_SHADER_FRAGMENT)
5777 handle_fs_inputs_pre(&ctx, nir);
5778
5779 ctx.num_output_clips = nir->info->clip_distance_array_size;
5780 ctx.num_output_culls = nir->info->cull_distance_array_size;
5781
5782 nir_foreach_variable(variable, &nir->outputs)
5783 handle_shader_output_decl(&ctx, variable);
5784
5785 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5786 _mesa_key_pointer_equal);
5787 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5788 _mesa_key_pointer_equal);
5789
5790 func = (struct nir_function *)exec_list_get_head(&nir->functions);
5791
5792 setup_locals(&ctx, func);
5793
5794 visit_cf_list(&ctx, &func->impl->body);
5795 phi_post_pass(&ctx);
5796
5797 handle_shader_outputs_post(&ctx);
5798 LLVMBuildRetVoid(ctx.builder);
5799
5800 ac_llvm_finalize_module(&ctx);
5801 free(ctx.locals);
5802 ralloc_free(ctx.defs);
5803 ralloc_free(ctx.phis);
5804
5805 if (nir->stage == MESA_SHADER_GEOMETRY) {
5806 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
5807 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
5808 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
5809 nir->info->gs.vertices_out;
5810 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
5811 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
5812 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
5813 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
5814 shader_info->vs.outputs_written = ctx.tess_outputs_written;
5815 }
5816
5817 return ctx.module;
5818 }
5819
5820 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
5821 {
5822 unsigned *retval = (unsigned *)context;
5823 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
5824 char *description = LLVMGetDiagInfoDescription(di);
5825
5826 if (severity == LLVMDSError) {
5827 *retval = 1;
5828 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
5829 description);
5830 }
5831
5832 LLVMDisposeMessage(description);
5833 }
5834
5835 static unsigned ac_llvm_compile(LLVMModuleRef M,
5836 struct ac_shader_binary *binary,
5837 LLVMTargetMachineRef tm)
5838 {
5839 unsigned retval = 0;
5840 char *err;
5841 LLVMContextRef llvm_ctx;
5842 LLVMMemoryBufferRef out_buffer;
5843 unsigned buffer_size;
5844 const char *buffer_data;
5845 LLVMBool mem_err;
5846
5847 /* Setup Diagnostic Handler*/
5848 llvm_ctx = LLVMGetModuleContext(M);
5849
5850 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
5851 &retval);
5852
5853 /* Compile IR*/
5854 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
5855 &err, &out_buffer);
5856
5857 /* Process Errors/Warnings */
5858 if (mem_err) {
5859 fprintf(stderr, "%s: %s", __FUNCTION__, err);
5860 free(err);
5861 retval = 1;
5862 goto out;
5863 }
5864
5865 /* Extract Shader Code*/
5866 buffer_size = LLVMGetBufferSize(out_buffer);
5867 buffer_data = LLVMGetBufferStart(out_buffer);
5868
5869 ac_elf_read(buffer_data, buffer_size, binary);
5870
5871 /* Clean up */
5872 LLVMDisposeMemoryBuffer(out_buffer);
5873
5874 out:
5875 return retval;
5876 }
5877
5878 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
5879 LLVMModuleRef llvm_module,
5880 struct ac_shader_binary *binary,
5881 struct ac_shader_config *config,
5882 struct ac_shader_variant_info *shader_info,
5883 gl_shader_stage stage,
5884 bool dump_shader, bool supports_spill)
5885 {
5886 if (dump_shader)
5887 ac_dump_module(llvm_module);
5888
5889 memset(binary, 0, sizeof(*binary));
5890 int v = ac_llvm_compile(llvm_module, binary, tm);
5891 if (v) {
5892 fprintf(stderr, "compile failed\n");
5893 }
5894
5895 if (dump_shader)
5896 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
5897
5898 ac_shader_binary_read_config(binary, config, 0, supports_spill);
5899
5900 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
5901 LLVMDisposeModule(llvm_module);
5902 LLVMContextDispose(ctx);
5903
5904 if (stage == MESA_SHADER_FRAGMENT) {
5905 shader_info->num_input_vgprs = 0;
5906 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
5907 shader_info->num_input_vgprs += 2;
5908 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
5909 shader_info->num_input_vgprs += 2;
5910 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
5911 shader_info->num_input_vgprs += 2;
5912 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
5913 shader_info->num_input_vgprs += 3;
5914 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
5915 shader_info->num_input_vgprs += 2;
5916 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
5917 shader_info->num_input_vgprs += 2;
5918 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
5919 shader_info->num_input_vgprs += 2;
5920 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
5921 shader_info->num_input_vgprs += 1;
5922 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
5923 shader_info->num_input_vgprs += 1;
5924 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
5925 shader_info->num_input_vgprs += 1;
5926 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5927 shader_info->num_input_vgprs += 1;
5928 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5929 shader_info->num_input_vgprs += 1;
5930 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5931 shader_info->num_input_vgprs += 1;
5932 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5933 shader_info->num_input_vgprs += 1;
5934 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5935 shader_info->num_input_vgprs += 1;
5936 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5937 shader_info->num_input_vgprs += 1;
5938 }
5939 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5940
5941 /* +3 for scratch wave offset and VCC */
5942 config->num_sgprs = MAX2(config->num_sgprs,
5943 shader_info->num_input_sgprs + 3);
5944 }
5945
5946 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5947 struct ac_shader_binary *binary,
5948 struct ac_shader_config *config,
5949 struct ac_shader_variant_info *shader_info,
5950 struct nir_shader *nir,
5951 const struct ac_nir_compiler_options *options,
5952 bool dump_shader)
5953 {
5954
5955 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5956 options);
5957
5958 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5959 switch (nir->stage) {
5960 case MESA_SHADER_COMPUTE:
5961 for (int i = 0; i < 3; ++i)
5962 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5963 break;
5964 case MESA_SHADER_FRAGMENT:
5965 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5966 break;
5967 case MESA_SHADER_GEOMETRY:
5968 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5969 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5970 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5971 shader_info->gs.invocations = nir->info->gs.invocations;
5972 break;
5973 case MESA_SHADER_TESS_EVAL:
5974 shader_info->tes.primitive_mode = nir->info->tess.primitive_mode;
5975 shader_info->tes.spacing = nir->info->tess.spacing;
5976 shader_info->tes.ccw = nir->info->tess.ccw;
5977 shader_info->tes.point_mode = nir->info->tess.point_mode;
5978 shader_info->tes.as_es = options->key.tes.as_es;
5979 break;
5980 case MESA_SHADER_TESS_CTRL:
5981 shader_info->tcs.tcs_vertices_out = nir->info->tess.tcs_vertices_out;
5982 break;
5983 case MESA_SHADER_VERTEX:
5984 shader_info->vs.as_es = options->key.vs.as_es;
5985 shader_info->vs.as_ls = options->key.vs.as_ls;
5986 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
5987 if (options->key.vs.as_ls)
5988 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
5989 break;
5990 default:
5991 break;
5992 }
5993 }
5994
5995 static void
5996 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5997 {
5998 LLVMValueRef args[9];
5999 args[0] = ctx->gsvs_ring;
6000 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6001 args[3] = ctx->i32zero;
6002 args[4] = ctx->i32one; /* OFFEN */
6003 args[5] = ctx->i32zero; /* IDXEN */
6004 args[6] = ctx->i32one; /* GLC */
6005 args[7] = ctx->i32one; /* SLC */
6006 args[8] = ctx->i32zero; /* TFE */
6007
6008 int idx = 0;
6009
6010 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6011 int length = 4;
6012 int slot = idx;
6013 int slot_inc = 1;
6014 if (!(ctx->output_mask & (1ull << i)))
6015 continue;
6016
6017 if (i == VARYING_SLOT_CLIP_DIST0) {
6018 /* unpack clip and cull from a single set of slots */
6019 length = ctx->num_output_clips + ctx->num_output_culls;
6020 if (length > 4)
6021 slot_inc = 2;
6022 }
6023
6024 for (unsigned j = 0; j < length; j++) {
6025 LLVMValueRef value;
6026 args[2] = LLVMConstInt(ctx->i32,
6027 (slot * 4 + j) *
6028 ctx->gs_max_out_vertices * 16 * 4, false);
6029
6030 value = ac_build_intrinsic(&ctx->ac,
6031 "llvm.SI.buffer.load.dword.i32.i32",
6032 ctx->i32, args, 9,
6033 AC_FUNC_ATTR_READONLY |
6034 AC_FUNC_ATTR_LEGACY);
6035
6036 LLVMBuildStore(ctx->builder,
6037 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
6038 }
6039 idx += slot_inc;
6040 }
6041 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
6042 }
6043
6044 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6045 struct nir_shader *geom_shader,
6046 struct ac_shader_binary *binary,
6047 struct ac_shader_config *config,
6048 struct ac_shader_variant_info *shader_info,
6049 const struct ac_nir_compiler_options *options,
6050 bool dump_shader)
6051 {
6052 struct nir_to_llvm_context ctx = {0};
6053 ctx.context = LLVMContextCreate();
6054 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6055 ctx.options = options;
6056 ctx.shader_info = shader_info;
6057
6058 ac_llvm_context_init(&ctx.ac, ctx.context);
6059 ctx.ac.module = ctx.module;
6060
6061 ctx.is_gs_copy_shader = true;
6062 LLVMSetTarget(ctx.module, "amdgcn--");
6063 setup_types(&ctx);
6064
6065 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6066 ctx.ac.builder = ctx.builder;
6067 ctx.stage = MESA_SHADER_VERTEX;
6068
6069 create_function(&ctx);
6070
6071 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
6072 ac_setup_rings(&ctx);
6073
6074 ctx.num_output_clips = geom_shader->info->clip_distance_array_size;
6075 ctx.num_output_culls = geom_shader->info->cull_distance_array_size;
6076
6077 nir_foreach_variable(variable, &geom_shader->outputs)
6078 handle_shader_output_decl(&ctx, variable);
6079
6080 ac_gs_copy_shader_emit(&ctx);
6081
6082 LLVMBuildRetVoid(ctx.builder);
6083
6084 ac_llvm_finalize_module(&ctx);
6085
6086 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6087 MESA_SHADER_VERTEX,
6088 dump_shader, options->supports_spill);
6089 }