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amd/common: replace add_user_sgpr_argument() by add_arg()
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tcs_patch_id;
115 LLVMValueRef tcs_rel_ids;
116 LLVMValueRef tes_rel_patch_id;
117 LLVMValueRef tes_patch_id;
118 LLVMValueRef tes_u;
119 LLVMValueRef tes_v;
120
121 LLVMValueRef gsvs_ring_stride;
122 LLVMValueRef gsvs_num_entries;
123 LLVMValueRef gs2vs_offset;
124 LLVMValueRef gs_wave_id;
125 LLVMValueRef gs_vtx_offset[6];
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 gl_shader_stage stage;
138
139 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
140
141 uint64_t input_mask;
142 uint64_t output_mask;
143 uint8_t num_output_clips;
144 uint8_t num_output_culls;
145
146 bool is_gs_copy_shader;
147 LLVMValueRef gs_next_vertex;
148 unsigned gs_max_out_vertices;
149
150 unsigned tes_primitive_mode;
151 uint64_t tess_outputs_written;
152 uint64_t tess_patch_outputs_written;
153
154 uint32_t tcs_patch_outputs_read;
155 uint64_t tcs_outputs_read;
156 };
157
158 static inline struct nir_to_llvm_context *
159 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
160 {
161 struct nir_to_llvm_context *ctx = NULL;
162 return container_of(abi, ctx, abi);
163 }
164
165 static LLVMTypeRef
166 nir2llvmtype(struct ac_nir_context *ctx,
167 const struct glsl_type *type)
168 {
169 switch (glsl_get_base_type(glsl_without_array(type))) {
170 case GLSL_TYPE_UINT:
171 case GLSL_TYPE_INT:
172 return ctx->ac.i32;
173 case GLSL_TYPE_UINT64:
174 case GLSL_TYPE_INT64:
175 return ctx->ac.i64;
176 case GLSL_TYPE_DOUBLE:
177 return ctx->ac.f64;
178 case GLSL_TYPE_FLOAT:
179 return ctx->ac.f32;
180 default:
181 assert(!"Unsupported type in nir2llvmtype()");
182 break;
183 }
184 return 0;
185 }
186
187 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
188 const nir_deref_var *deref,
189 enum ac_descriptor_type desc_type,
190 const nir_tex_instr *instr,
191 bool image, bool write);
192
193 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
194 {
195 return (index * 4) + chan;
196 }
197
198 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
199 {
200 /* handle patch indices separate */
201 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
202 return 0;
203 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
204 return 1;
205 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
206 return 2 + (slot - VARYING_SLOT_PATCH0);
207
208 if (slot == VARYING_SLOT_POS)
209 return 0;
210 if (slot == VARYING_SLOT_PSIZ)
211 return 1;
212 if (slot == VARYING_SLOT_CLIP_DIST0)
213 return 2;
214 /* 3 is reserved for clip dist as well */
215 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
216 return 4 + (slot - VARYING_SLOT_VAR0);
217 unreachable("illegal slot in get unique index\n");
218 }
219
220 static void set_llvm_calling_convention(LLVMValueRef func,
221 gl_shader_stage stage)
222 {
223 enum radeon_llvm_calling_convention calling_conv;
224
225 switch (stage) {
226 case MESA_SHADER_VERTEX:
227 case MESA_SHADER_TESS_EVAL:
228 calling_conv = RADEON_LLVM_AMDGPU_VS;
229 break;
230 case MESA_SHADER_GEOMETRY:
231 calling_conv = RADEON_LLVM_AMDGPU_GS;
232 break;
233 case MESA_SHADER_TESS_CTRL:
234 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
235 break;
236 case MESA_SHADER_FRAGMENT:
237 calling_conv = RADEON_LLVM_AMDGPU_PS;
238 break;
239 case MESA_SHADER_COMPUTE:
240 calling_conv = RADEON_LLVM_AMDGPU_CS;
241 break;
242 default:
243 unreachable("Unhandle shader type");
244 }
245
246 LLVMSetFunctionCallConv(func, calling_conv);
247 }
248
249 #define MAX_ARGS 23
250 struct arg_info {
251 LLVMTypeRef types[MAX_ARGS];
252 LLVMValueRef *assign[MAX_ARGS];
253 unsigned array_params_mask;
254 uint8_t count;
255 uint8_t sgpr_count;
256 uint8_t num_sgprs_used;
257 uint8_t num_vgprs_used;
258 };
259
260 enum ac_arg_regfile {
261 ARG_SGPR,
262 ARG_VGPR,
263 };
264
265 static void
266 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
267 LLVMValueRef *param_ptr)
268 {
269 assert(info->count < MAX_ARGS);
270
271 info->assign[info->count] = param_ptr;
272 info->types[info->count] = type;
273 info->count++;
274
275 if (regfile == ARG_SGPR) {
276 info->num_sgprs_used += ac_get_type_size(type) / 4;
277 info->sgpr_count++;
278 } else {
279 assert(regfile == ARG_VGPR);
280 info->num_vgprs_used += ac_get_type_size(type) / 4;
281 }
282 }
283
284 static inline void
285 add_argument(struct arg_info *info,
286 LLVMTypeRef type, LLVMValueRef *param_ptr)
287 {
288 assert(info->count < MAX_ARGS);
289 info->assign[info->count] = param_ptr;
290 info->types[info->count] = type;
291 info->count++;
292 }
293
294 static inline void
295 add_sgpr_argument(struct arg_info *info,
296 LLVMTypeRef type, LLVMValueRef *param_ptr)
297 {
298 add_argument(info, type, param_ptr);
299 info->num_sgprs_used += ac_get_type_size(type) / 4;
300 info->sgpr_count++;
301 }
302
303 static inline void
304 add_user_sgpr_array_argument(struct arg_info *info,
305 LLVMTypeRef type,
306 LLVMValueRef *param_ptr)
307 {
308 info->array_params_mask |= (1 << info->count);
309 add_arg(info, ARG_SGPR, type, param_ptr);
310 }
311
312 static void assign_arguments(LLVMValueRef main_function,
313 struct arg_info *info)
314 {
315 unsigned i;
316 for (i = 0; i < info->count; i++) {
317 if (info->assign[i])
318 *info->assign[i] = LLVMGetParam(main_function, i);
319 }
320 }
321
322 static LLVMValueRef
323 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
324 LLVMBuilderRef builder, LLVMTypeRef *return_types,
325 unsigned num_return_elems,
326 struct arg_info *args,
327 unsigned max_workgroup_size,
328 bool unsafe_math)
329 {
330 LLVMTypeRef main_function_type, ret_type;
331 LLVMBasicBlockRef main_function_body;
332
333 if (num_return_elems)
334 ret_type = LLVMStructTypeInContext(ctx, return_types,
335 num_return_elems, true);
336 else
337 ret_type = LLVMVoidTypeInContext(ctx);
338
339 /* Setup the function */
340 main_function_type =
341 LLVMFunctionType(ret_type, args->types, args->count, 0);
342 LLVMValueRef main_function =
343 LLVMAddFunction(module, "main", main_function_type);
344 main_function_body =
345 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
346 LLVMPositionBuilderAtEnd(builder, main_function_body);
347
348 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
349 for (unsigned i = 0; i < args->sgpr_count; ++i) {
350 if (args->array_params_mask & (1 << i)) {
351 LLVMValueRef P = LLVMGetParam(main_function, i);
352 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
353 ac_add_attr_dereferenceable(P, UINT64_MAX);
354 }
355 else {
356 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
357 }
358 }
359
360 if (max_workgroup_size) {
361 ac_llvm_add_target_dep_function_attr(main_function,
362 "amdgpu-max-work-group-size",
363 max_workgroup_size);
364 }
365 if (unsafe_math) {
366 /* These were copied from some LLVM test. */
367 LLVMAddTargetDependentFunctionAttr(main_function,
368 "less-precise-fpmad",
369 "true");
370 LLVMAddTargetDependentFunctionAttr(main_function,
371 "no-infs-fp-math",
372 "true");
373 LLVMAddTargetDependentFunctionAttr(main_function,
374 "no-nans-fp-math",
375 "true");
376 LLVMAddTargetDependentFunctionAttr(main_function,
377 "unsafe-fp-math",
378 "true");
379 }
380 return main_function;
381 }
382
383 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
384 {
385 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
386 CONST_ADDR_SPACE);
387 }
388
389 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
390 {
391 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
392 type = LLVMGetElementType(type);
393
394 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
395 return LLVMGetIntTypeWidth(type);
396
397 if (type == ctx->f16)
398 return 16;
399 if (type == ctx->f32)
400 return 32;
401 if (type == ctx->f64)
402 return 64;
403
404 unreachable("Unhandled type kind in get_elem_bits");
405 }
406
407 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
408 LLVMValueRef param, unsigned rshift,
409 unsigned bitwidth)
410 {
411 LLVMValueRef value = param;
412 if (rshift)
413 value = LLVMBuildLShr(ctx->builder, value,
414 LLVMConstInt(ctx->i32, rshift, false), "");
415
416 if (rshift + bitwidth < 32) {
417 unsigned mask = (1 << bitwidth) - 1;
418 value = LLVMBuildAnd(ctx->builder, value,
419 LLVMConstInt(ctx->i32, mask, false), "");
420 }
421 return value;
422 }
423
424 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
425 {
426 switch (ctx->stage) {
427 case MESA_SHADER_TESS_CTRL:
428 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
429 case MESA_SHADER_TESS_EVAL:
430 return ctx->tes_rel_patch_id;
431 break;
432 default:
433 unreachable("Illegal stage");
434 }
435 }
436
437 /* Tessellation shaders pass outputs to the next shader using LDS.
438 *
439 * LS outputs = TCS inputs
440 * TCS outputs = TES inputs
441 *
442 * The LDS layout is:
443 * - TCS inputs for patch 0
444 * - TCS inputs for patch 1
445 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
446 * - ...
447 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
448 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
449 * - TCS outputs for patch 1
450 * - Per-patch TCS outputs for patch 1
451 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
452 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
453 * - ...
454 *
455 * All three shaders VS(LS), TCS, TES share the same LDS space.
456 */
457 static LLVMValueRef
458 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
459 {
460 if (ctx->stage == MESA_SHADER_VERTEX)
461 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
462 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
463 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
464 else {
465 assert(0);
466 return NULL;
467 }
468 }
469
470 static LLVMValueRef
471 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
472 {
473 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
474 }
475
476 static LLVMValueRef
477 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
478 {
479 return LLVMBuildMul(ctx->builder,
480 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
481 LLVMConstInt(ctx->ac.i32, 4, false), "");
482 }
483
484 static LLVMValueRef
485 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
486 {
487 return LLVMBuildMul(ctx->builder,
488 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
489 LLVMConstInt(ctx->ac.i32, 4, false), "");
490 }
491
492 static LLVMValueRef
493 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
494 {
495 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
496 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
497
498 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
499 }
500
501 static LLVMValueRef
502 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
503 {
504 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
505 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
506 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
507
508 return LLVMBuildAdd(ctx->builder, patch0_offset,
509 LLVMBuildMul(ctx->builder, patch_stride,
510 rel_patch_id, ""),
511 "");
512 }
513
514 static LLVMValueRef
515 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
516 {
517 LLVMValueRef patch0_patch_data_offset =
518 get_tcs_out_patch0_patch_data_offset(ctx);
519 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
520 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
521
522 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
523 LLVMBuildMul(ctx->builder, patch_stride,
524 rel_patch_id, ""),
525 "");
526 }
527
528 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
529 {
530 ud_info->sgpr_idx = *sgpr_idx;
531 ud_info->num_sgprs = num_sgprs;
532 ud_info->indirect = false;
533 ud_info->indirect_offset = 0;
534 *sgpr_idx += num_sgprs;
535 }
536
537 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
538 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
539 {
540 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
541 }
542
543
544 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
545 uint32_t indirect_offset)
546 {
547 ud_info->sgpr_idx = sgpr_idx;
548 ud_info->num_sgprs = num_sgprs;
549 ud_info->indirect = true;
550 ud_info->indirect_offset = indirect_offset;
551 }
552
553 struct user_sgpr_info {
554 bool need_ring_offsets;
555 uint8_t sgpr_count;
556 bool indirect_all_descriptor_sets;
557 };
558
559 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
560 struct user_sgpr_info *user_sgpr_info)
561 {
562 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
563
564 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
565 if (ctx->stage == MESA_SHADER_GEOMETRY ||
566 ctx->stage == MESA_SHADER_VERTEX ||
567 ctx->stage == MESA_SHADER_TESS_CTRL ||
568 ctx->stage == MESA_SHADER_TESS_EVAL ||
569 ctx->is_gs_copy_shader)
570 user_sgpr_info->need_ring_offsets = true;
571
572 if (ctx->stage == MESA_SHADER_FRAGMENT &&
573 ctx->shader_info->info.ps.needs_sample_positions)
574 user_sgpr_info->need_ring_offsets = true;
575
576 /* 2 user sgprs will nearly always be allocated for scratch/rings */
577 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
578 user_sgpr_info->sgpr_count += 2;
579 }
580
581 switch (ctx->stage) {
582 case MESA_SHADER_COMPUTE:
583 if (ctx->shader_info->info.cs.uses_grid_size)
584 user_sgpr_info->sgpr_count += 3;
585 break;
586 case MESA_SHADER_FRAGMENT:
587 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
588 break;
589 case MESA_SHADER_VERTEX:
590 if (!ctx->is_gs_copy_shader) {
591 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
592 if (ctx->shader_info->info.vs.needs_draw_id) {
593 user_sgpr_info->sgpr_count += 3;
594 } else {
595 user_sgpr_info->sgpr_count += 2;
596 }
597 }
598 if (ctx->options->key.vs.as_ls)
599 user_sgpr_info->sgpr_count++;
600 break;
601 case MESA_SHADER_TESS_CTRL:
602 user_sgpr_info->sgpr_count += 4;
603 break;
604 case MESA_SHADER_TESS_EVAL:
605 user_sgpr_info->sgpr_count += 1;
606 break;
607 case MESA_SHADER_GEOMETRY:
608 user_sgpr_info->sgpr_count += 2;
609 break;
610 default:
611 break;
612 }
613
614 if (ctx->shader_info->info.needs_push_constants)
615 user_sgpr_info->sgpr_count += 2;
616
617 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
618 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
619 user_sgpr_info->sgpr_count += 2;
620 user_sgpr_info->indirect_all_descriptor_sets = true;
621 } else {
622 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
623 }
624 }
625
626 static void
627 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
628 gl_shader_stage stage,
629 bool has_previous_stage,
630 gl_shader_stage previous_stage,
631 const struct user_sgpr_info *user_sgpr_info,
632 LLVMValueRef desc_sets,
633 uint8_t *user_sgpr_idx)
634 {
635 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
636 unsigned stage_mask = 1 << stage;
637 if (has_previous_stage)
638 stage_mask |= 1 << previous_stage;
639
640 if (!user_sgpr_info->indirect_all_descriptor_sets) {
641 for (unsigned i = 0; i < num_sets; ++i) {
642 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
643 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
644 } else
645 ctx->descriptor_sets[i] = NULL;
646 }
647 } else {
648 uint32_t desc_sgpr_idx = *user_sgpr_idx;
649 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
650
651 for (unsigned i = 0; i < num_sets; ++i) {
652 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
653 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
654 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->ac.i32, i, false));
655
656 } else
657 ctx->descriptor_sets[i] = NULL;
658 }
659 ctx->shader_info->need_indirect_descriptor_sets = true;
660 }
661
662 if (ctx->shader_info->info.needs_push_constants) {
663 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
664 }
665 }
666
667
668 static void
669 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
670 gl_shader_stage stage,
671 bool has_previous_stage,
672 gl_shader_stage previous_stage,
673 uint8_t *user_sgpr_idx)
674 {
675 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
676 if (ctx->shader_info->info.vs.has_vertex_buffers) {
677 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
678 }
679 unsigned vs_num = 2;
680 if (ctx->shader_info->info.vs.needs_draw_id)
681 vs_num++;
682
683 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
684 }
685 }
686
687 static void
688 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
689 gl_shader_stage stage,
690 bool has_previous_stage,
691 gl_shader_stage previous_stage,
692 const struct user_sgpr_info *user_sgpr_info,
693 struct arg_info *args,
694 LLVMValueRef *desc_sets)
695 {
696 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
697 unsigned num_sets = ctx->options->layout ?
698 ctx->options->layout->num_sets : 0;
699 unsigned stage_mask = 1 << stage;
700
701 if (has_previous_stage)
702 stage_mask |= 1 << previous_stage;
703
704 /* 1 for each descriptor set */
705 if (!user_sgpr_info->indirect_all_descriptor_sets) {
706 for (unsigned i = 0; i < num_sets; ++i) {
707 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
708 add_user_sgpr_array_argument(args, type,
709 &ctx->descriptor_sets[i]);
710 }
711 }
712 } else {
713 add_user_sgpr_array_argument(args, const_array(type, 32),
714 desc_sets);
715 }
716
717 if (ctx->shader_info->info.needs_push_constants) {
718 /* 1 for push constants and dynamic descriptors */
719 add_user_sgpr_array_argument(args, type,
720 &ctx->push_constants);
721 }
722 }
723
724 static void
725 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
726 gl_shader_stage stage,
727 bool has_previous_stage,
728 gl_shader_stage previous_stage,
729 struct arg_info *args)
730 {
731 if (!ctx->is_gs_copy_shader &&
732 (stage == MESA_SHADER_VERTEX ||
733 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
734 if (ctx->shader_info->info.vs.has_vertex_buffers) {
735 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
736 &ctx->vertex_buffers);
737 }
738 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
739 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
740 if (ctx->shader_info->info.vs.needs_draw_id) {
741 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
742 }
743 }
744 }
745
746 static void
747 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
748 {
749 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
750 if (!ctx->is_gs_copy_shader) {
751 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
752 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
753 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
754 }
755 }
756
757 static void
758 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
759 {
760 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
761 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
762 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
763 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_patch_id);
764 }
765
766 static void create_function(struct nir_to_llvm_context *ctx,
767 gl_shader_stage stage,
768 bool has_previous_stage,
769 gl_shader_stage previous_stage)
770 {
771 uint8_t user_sgpr_idx;
772 struct user_sgpr_info user_sgpr_info;
773 struct arg_info args = {};
774 LLVMValueRef desc_sets;
775
776 allocate_user_sgprs(ctx, &user_sgpr_info);
777
778 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
779 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
780 &ctx->ring_offsets);
781 }
782
783 switch (stage) {
784 case MESA_SHADER_COMPUTE:
785 declare_global_input_sgprs(ctx, stage, has_previous_stage,
786 previous_stage, &user_sgpr_info,
787 &args, &desc_sets);
788
789 if (ctx->shader_info->info.cs.uses_grid_size) {
790 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
791 &ctx->num_work_groups);
792 }
793
794 for (int i = 0; i < 3; i++) {
795 ctx->workgroup_ids[i] = NULL;
796 if (ctx->shader_info->info.cs.uses_block_id[i]) {
797 add_sgpr_argument(&args, ctx->ac.i32,
798 &ctx->workgroup_ids[i]);
799 }
800 }
801
802 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
803 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tg_size);
804 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
805 &ctx->local_invocation_ids);
806 break;
807 case MESA_SHADER_VERTEX:
808 declare_global_input_sgprs(ctx, stage, has_previous_stage,
809 previous_stage, &user_sgpr_info,
810 &args, &desc_sets);
811 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
812 previous_stage, &args);
813
814 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
816 if (ctx->options->key.vs.as_es)
817 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
818 else if (ctx->options->key.vs.as_ls)
819 add_arg(&args, ARG_SGPR, ctx->ac.i32,
820 &ctx->ls_out_layout);
821
822 declare_vs_input_vgprs(ctx, &args);
823 break;
824 case MESA_SHADER_TESS_CTRL:
825 if (has_previous_stage) {
826 // First 6 system regs
827 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
828 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
829 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
830
831 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
832 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
833 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
834
835 declare_global_input_sgprs(ctx, stage,
836 has_previous_stage,
837 previous_stage,
838 &user_sgpr_info, &args,
839 &desc_sets);
840 declare_vs_specific_input_sgprs(ctx, stage,
841 has_previous_stage,
842 previous_stage, &args);
843
844 add_arg(&args, ARG_SGPR, ctx->ac.i32,
845 &ctx->ls_out_layout);
846
847 add_arg(&args, ARG_SGPR, ctx->ac.i32,
848 &ctx->tcs_offchip_layout);
849 add_arg(&args, ARG_SGPR, ctx->ac.i32,
850 &ctx->tcs_out_offsets);
851 add_arg(&args, ARG_SGPR, ctx->ac.i32,
852 &ctx->tcs_out_layout);
853 add_arg(&args, ARG_SGPR, ctx->ac.i32,
854 &ctx->tcs_in_layout);
855 if (ctx->shader_info->info.needs_multiview_view_index)
856 add_arg(&args, ARG_SGPR, ctx->ac.i32,
857 &ctx->view_index);
858
859 add_arg(&args, ARG_VGPR, ctx->ac.i32,
860 &ctx->tcs_patch_id);
861 add_arg(&args, ARG_VGPR, ctx->ac.i32,
862 &ctx->tcs_rel_ids);
863
864 declare_vs_input_vgprs(ctx, &args);
865 } else {
866 declare_global_input_sgprs(ctx, stage,
867 has_previous_stage,
868 previous_stage,
869 &user_sgpr_info, &args,
870 &desc_sets);
871
872 add_arg(&args, ARG_SGPR, ctx->ac.i32,
873 &ctx->tcs_offchip_layout);
874 add_arg(&args, ARG_SGPR, ctx->ac.i32,
875 &ctx->tcs_out_offsets);
876 add_arg(&args, ARG_SGPR, ctx->ac.i32,
877 &ctx->tcs_out_layout);
878 add_arg(&args, ARG_SGPR, ctx->ac.i32,
879 &ctx->tcs_in_layout);
880 if (ctx->shader_info->info.needs_multiview_view_index)
881 add_arg(&args, ARG_SGPR, ctx->ac.i32,
882 &ctx->view_index);
883
884 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
885 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
886 add_arg(&args, ARG_VGPR, ctx->ac.i32,
887 &ctx->tcs_patch_id);
888 add_arg(&args, ARG_VGPR, ctx->ac.i32,
889 &ctx->tcs_rel_ids);
890 }
891 break;
892 case MESA_SHADER_TESS_EVAL:
893 declare_global_input_sgprs(ctx, stage, has_previous_stage,
894 previous_stage, &user_sgpr_info,
895 &args, &desc_sets);
896
897 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
898 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
900
901 if (ctx->options->key.tes.as_es) {
902 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
903 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
904 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
905 } else {
906 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
907 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
908 }
909 declare_tes_input_vgprs(ctx, &args);
910 break;
911 case MESA_SHADER_GEOMETRY:
912 if (has_previous_stage) {
913 // First 6 system regs
914 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // tess factor offset
915 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
916 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
917
918 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
919 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
920 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
921
922 declare_global_input_sgprs(ctx, stage,
923 has_previous_stage,
924 previous_stage,
925 &user_sgpr_info, &args,
926 &desc_sets);
927
928 if (previous_stage == MESA_SHADER_TESS_EVAL) {
929 add_arg(&args, ARG_SGPR, ctx->ac.i32,
930 &ctx->tcs_offchip_layout);
931 } else {
932 declare_vs_specific_input_sgprs(ctx, stage,
933 has_previous_stage,
934 previous_stage,
935 &args);
936 }
937
938 add_arg(&args, ARG_SGPR, ctx->ac.i32,
939 &ctx->gsvs_ring_stride);
940 add_arg(&args, ARG_SGPR, ctx->ac.i32,
941 &ctx->gsvs_num_entries);
942 if (ctx->shader_info->info.needs_multiview_view_index)
943 add_arg(&args, ARG_SGPR, ctx->ac.i32,
944 &ctx->view_index);
945
946 add_arg(&args, ARG_VGPR, ctx->ac.i32,
947 &ctx->gs_vtx_offset[0]);
948 add_arg(&args, ARG_VGPR, ctx->ac.i32,
949 &ctx->gs_vtx_offset[2]);
950 add_arg(&args, ARG_VGPR, ctx->ac.i32,
951 &ctx->abi.gs_prim_id);
952 add_arg(&args, ARG_VGPR, ctx->ac.i32,
953 &ctx->abi.gs_invocation_id);
954 add_arg(&args, ARG_VGPR, ctx->ac.i32,
955 &ctx->gs_vtx_offset[4]);
956
957 if (previous_stage == MESA_SHADER_VERTEX) {
958 declare_vs_input_vgprs(ctx, &args);
959 } else {
960 declare_tes_input_vgprs(ctx, &args);
961 }
962 } else {
963 declare_global_input_sgprs(ctx, stage,
964 has_previous_stage,
965 previous_stage,
966 &user_sgpr_info, &args,
967 &desc_sets);
968
969 add_arg(&args, ARG_SGPR, ctx->ac.i32,
970 &ctx->gsvs_ring_stride);
971 add_arg(&args, ARG_SGPR, ctx->ac.i32,
972 &ctx->gsvs_num_entries);
973 if (ctx->shader_info->info.needs_multiview_view_index)
974 add_arg(&args, ARG_SGPR, ctx->ac.i32,
975 &ctx->view_index);
976
977 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // gs2vs offset
978 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs_wave_id); // wave id
979 add_arg(&args, ARG_VGPR, ctx->ac.i32,
980 &ctx->gs_vtx_offset[0]);
981 add_arg(&args, ARG_VGPR, ctx->ac.i32,
982 &ctx->gs_vtx_offset[1]);
983 add_arg(&args, ARG_VGPR, ctx->ac.i32,
984 &ctx->abi.gs_prim_id);
985 add_arg(&args, ARG_VGPR, ctx->ac.i32,
986 &ctx->gs_vtx_offset[2]);
987 add_arg(&args, ARG_VGPR, ctx->ac.i32,
988 &ctx->gs_vtx_offset[3]);
989 add_arg(&args, ARG_VGPR, ctx->ac.i32,
990 &ctx->gs_vtx_offset[4]);
991 add_arg(&args, ARG_VGPR, ctx->ac.i32,
992 &ctx->gs_vtx_offset[5]);
993 add_arg(&args, ARG_VGPR, ctx->ac.i32,
994 &ctx->abi.gs_invocation_id);
995 }
996 break;
997 case MESA_SHADER_FRAGMENT:
998 declare_global_input_sgprs(ctx, stage, has_previous_stage,
999 previous_stage, &user_sgpr_info,
1000 &args, &desc_sets);
1001
1002 if (ctx->shader_info->info.ps.needs_sample_positions)
1003 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1004 &ctx->sample_pos_offset);
1005
1006 add_sgpr_argument(&args, ctx->ac.i32, &ctx->prim_mask); /* prim mask */
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1009 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1010 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1011 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1012 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1013 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1014 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1015 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1016 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1017 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1018 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1019 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1020 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1021 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1022 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1023 break;
1024 default:
1025 unreachable("Shader stage not implemented");
1026 }
1027
1028 ctx->main_function = create_llvm_function(
1029 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1030 ctx->max_workgroup_size,
1031 ctx->options->unsafe_math);
1032 set_llvm_calling_convention(ctx->main_function, stage);
1033
1034
1035 ctx->shader_info->num_input_vgprs = 0;
1036 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1037
1038 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1039
1040 if (ctx->stage != MESA_SHADER_FRAGMENT)
1041 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1042
1043 assign_arguments(ctx->main_function, &args);
1044
1045 user_sgpr_idx = 0;
1046
1047 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1048 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
1049 if (ctx->options->supports_spill) {
1050 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1051 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1052 NULL, 0, AC_FUNC_ATTR_READNONE);
1053 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1054 const_array(ctx->ac.v4i32, 16), "");
1055 }
1056 }
1057
1058 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1059 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1060 if (has_previous_stage)
1061 user_sgpr_idx = 0;
1062
1063 radv_define_common_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, desc_sets, &user_sgpr_idx);
1064
1065 switch (stage) {
1066 case MESA_SHADER_COMPUTE:
1067 if (ctx->shader_info->info.cs.uses_grid_size) {
1068 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE,
1069 &user_sgpr_idx, 3);
1070 }
1071 break;
1072 case MESA_SHADER_VERTEX:
1073 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
1074 if (ctx->view_index)
1075 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1076 if (ctx->options->key.vs.as_ls) {
1077 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
1078 }
1079 if (ctx->options->key.vs.as_ls)
1080 ac_declare_lds_as_pointer(&ctx->ac);
1081 break;
1082 case MESA_SHADER_TESS_CTRL:
1083 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
1084 if (has_previous_stage)
1085 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
1086 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1087 if (ctx->view_index)
1088 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1089 ac_declare_lds_as_pointer(&ctx->ac);
1090 break;
1091 case MESA_SHADER_TESS_EVAL:
1092 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1093 if (ctx->view_index)
1094 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1095 break;
1096 case MESA_SHADER_GEOMETRY:
1097 if (has_previous_stage) {
1098 if (previous_stage == MESA_SHADER_VERTEX)
1099 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
1100 else
1101 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1102 }
1103 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
1104 if (ctx->view_index)
1105 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1106 if (has_previous_stage)
1107 ac_declare_lds_as_pointer(&ctx->ac);
1108 break;
1109 case MESA_SHADER_FRAGMENT:
1110 if (ctx->shader_info->info.ps.needs_sample_positions) {
1111 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
1112 }
1113 break;
1114 default:
1115 unreachable("Shader stage not implemented");
1116 }
1117
1118 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1119 }
1120
1121 static int get_llvm_num_components(LLVMValueRef value)
1122 {
1123 LLVMTypeRef type = LLVMTypeOf(value);
1124 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1125 ? LLVMGetVectorSize(type)
1126 : 1;
1127 return num_components;
1128 }
1129
1130 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1131 LLVMValueRef value,
1132 int index)
1133 {
1134 int count = get_llvm_num_components(value);
1135
1136 if (count == 1)
1137 return value;
1138
1139 return LLVMBuildExtractElement(ac->builder, value,
1140 LLVMConstInt(ac->i32, index, false), "");
1141 }
1142
1143 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1144 LLVMValueRef value, unsigned count)
1145 {
1146 unsigned num_components = get_llvm_num_components(value);
1147 if (count == num_components)
1148 return value;
1149
1150 LLVMValueRef masks[] = {
1151 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1152 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1153
1154 if (count == 1)
1155 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1156 "");
1157
1158 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1159 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1160 }
1161
1162 static void
1163 build_store_values_extended(struct ac_llvm_context *ac,
1164 LLVMValueRef *values,
1165 unsigned value_count,
1166 unsigned value_stride,
1167 LLVMValueRef vec)
1168 {
1169 LLVMBuilderRef builder = ac->builder;
1170 unsigned i;
1171
1172 for (i = 0; i < value_count; i++) {
1173 LLVMValueRef ptr = values[i * value_stride];
1174 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1175 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1176 LLVMBuildStore(builder, value, ptr);
1177 }
1178 }
1179
1180 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1181 const nir_ssa_def *def)
1182 {
1183 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1184 if (def->num_components > 1) {
1185 type = LLVMVectorType(type, def->num_components);
1186 }
1187 return type;
1188 }
1189
1190 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1191 {
1192 assert(src.is_ssa);
1193 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1194 return (LLVMValueRef)entry->data;
1195 }
1196
1197
1198 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1199 const struct nir_block *b)
1200 {
1201 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1202 return (LLVMBasicBlockRef)entry->data;
1203 }
1204
1205 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1206 nir_alu_src src,
1207 unsigned num_components)
1208 {
1209 LLVMValueRef value = get_src(ctx, src.src);
1210 bool need_swizzle = false;
1211
1212 assert(value);
1213 LLVMTypeRef type = LLVMTypeOf(value);
1214 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1215 ? LLVMGetVectorSize(type)
1216 : 1;
1217
1218 for (unsigned i = 0; i < num_components; ++i) {
1219 assert(src.swizzle[i] < src_components);
1220 if (src.swizzle[i] != i)
1221 need_swizzle = true;
1222 }
1223
1224 if (need_swizzle || num_components != src_components) {
1225 LLVMValueRef masks[] = {
1226 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1227 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1228 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1229 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1230
1231 if (src_components > 1 && num_components == 1) {
1232 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1233 masks[0], "");
1234 } else if (src_components == 1 && num_components > 1) {
1235 LLVMValueRef values[] = {value, value, value, value};
1236 value = ac_build_gather_values(&ctx->ac, values, num_components);
1237 } else {
1238 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1239 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1240 swizzle, "");
1241 }
1242 }
1243 assert(!src.negate);
1244 assert(!src.abs);
1245 return value;
1246 }
1247
1248 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1249 LLVMIntPredicate pred, LLVMValueRef src0,
1250 LLVMValueRef src1)
1251 {
1252 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1253 return LLVMBuildSelect(ctx->builder, result,
1254 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1255 ctx->i32_0, "");
1256 }
1257
1258 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1259 LLVMRealPredicate pred, LLVMValueRef src0,
1260 LLVMValueRef src1)
1261 {
1262 LLVMValueRef result;
1263 src0 = ac_to_float(ctx, src0);
1264 src1 = ac_to_float(ctx, src1);
1265 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1266 return LLVMBuildSelect(ctx->builder, result,
1267 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1268 ctx->i32_0, "");
1269 }
1270
1271 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1272 const char *intrin,
1273 LLVMTypeRef result_type,
1274 LLVMValueRef src0)
1275 {
1276 char name[64];
1277 LLVMValueRef params[] = {
1278 ac_to_float(ctx, src0),
1279 };
1280
1281 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1282 get_elem_bits(ctx, result_type));
1283 assert(length < sizeof(name));
1284 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1285 }
1286
1287 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1288 const char *intrin,
1289 LLVMTypeRef result_type,
1290 LLVMValueRef src0, LLVMValueRef src1)
1291 {
1292 char name[64];
1293 LLVMValueRef params[] = {
1294 ac_to_float(ctx, src0),
1295 ac_to_float(ctx, src1),
1296 };
1297
1298 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1299 get_elem_bits(ctx, result_type));
1300 assert(length < sizeof(name));
1301 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1302 }
1303
1304 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1305 const char *intrin,
1306 LLVMTypeRef result_type,
1307 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1308 {
1309 char name[64];
1310 LLVMValueRef params[] = {
1311 ac_to_float(ctx, src0),
1312 ac_to_float(ctx, src1),
1313 ac_to_float(ctx, src2),
1314 };
1315
1316 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1317 get_elem_bits(ctx, result_type));
1318 assert(length < sizeof(name));
1319 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1320 }
1321
1322 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1323 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1324 {
1325 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1326 ctx->i32_0, "");
1327 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1328 }
1329
1330 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1331 LLVMIntPredicate pred,
1332 LLVMValueRef src0, LLVMValueRef src1)
1333 {
1334 return LLVMBuildSelect(ctx->builder,
1335 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1336 src0,
1337 src1, "");
1338
1339 }
1340 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1341 LLVMValueRef src0)
1342 {
1343 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1344 LLVMBuildNeg(ctx->builder, src0, ""));
1345 }
1346
1347 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1348 LLVMValueRef src0)
1349 {
1350 LLVMValueRef cmp, val;
1351
1352 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1353 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1354 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1355 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1356 return val;
1357 }
1358
1359 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1360 LLVMValueRef src0)
1361 {
1362 LLVMValueRef cmp, val;
1363
1364 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1365 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1366 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1367 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1368 return val;
1369 }
1370
1371 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1372 LLVMValueRef src0)
1373 {
1374 const char *intr = "llvm.floor.f32";
1375 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1376 LLVMValueRef params[] = {
1377 fsrc0,
1378 };
1379 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1380 ctx->f32, params, 1,
1381 AC_FUNC_ATTR_READNONE);
1382 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1383 }
1384
1385 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1386 const char *intrin,
1387 LLVMValueRef src0, LLVMValueRef src1)
1388 {
1389 LLVMTypeRef ret_type;
1390 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1391 LLVMValueRef res;
1392 LLVMValueRef params[] = { src0, src1 };
1393 ret_type = LLVMStructTypeInContext(ctx->context, types,
1394 2, true);
1395
1396 res = ac_build_intrinsic(ctx, intrin, ret_type,
1397 params, 2, AC_FUNC_ATTR_READNONE);
1398
1399 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1400 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1401 return res;
1402 }
1403
1404 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1405 LLVMValueRef src0)
1406 {
1407 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1408 }
1409
1410 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1411 LLVMValueRef src0)
1412 {
1413 src0 = ac_to_float(ctx, src0);
1414 return LLVMBuildSExt(ctx->builder,
1415 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1416 ctx->i32, "");
1417 }
1418
1419 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1420 LLVMValueRef src0)
1421 {
1422 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1423 }
1424
1425 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1426 LLVMValueRef src0)
1427 {
1428 return LLVMBuildSExt(ctx->builder,
1429 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1430 ctx->i32, "");
1431 }
1432
1433 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1434 LLVMValueRef src0)
1435 {
1436 LLVMValueRef result;
1437 LLVMValueRef cond = NULL;
1438
1439 src0 = ac_to_float(&ctx->ac, src0);
1440 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1441
1442 if (ctx->options->chip_class >= VI) {
1443 LLVMValueRef args[2];
1444 /* Check if the result is a denormal - and flush to 0 if so. */
1445 args[0] = result;
1446 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1447 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1448 }
1449
1450 /* need to convert back up to f32 */
1451 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1452
1453 if (ctx->options->chip_class >= VI)
1454 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1455 else {
1456 /* for SI/CIK */
1457 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1458 * so compare the result and flush to 0 if it's smaller.
1459 */
1460 LLVMValueRef temp, cond2;
1461 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1462 ctx->ac.f32, result);
1463 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1464 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1465 temp, "");
1466 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1467 temp, ctx->ac.f32_0, "");
1468 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1469 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1470 }
1471 return result;
1472 }
1473
1474 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1475 LLVMValueRef src0, LLVMValueRef src1)
1476 {
1477 LLVMValueRef dst64, result;
1478 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1479 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1480
1481 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1482 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1483 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1484 return result;
1485 }
1486
1487 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1488 LLVMValueRef src0, LLVMValueRef src1)
1489 {
1490 LLVMValueRef dst64, result;
1491 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1492 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1493
1494 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1495 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1496 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1497 return result;
1498 }
1499
1500 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1501 bool is_signed,
1502 const LLVMValueRef srcs[3])
1503 {
1504 LLVMValueRef result;
1505 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1506
1507 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1508 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1509 return result;
1510 }
1511
1512 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1513 LLVMValueRef src0, LLVMValueRef src1,
1514 LLVMValueRef src2, LLVMValueRef src3)
1515 {
1516 LLVMValueRef bfi_args[3], result;
1517
1518 bfi_args[0] = LLVMBuildShl(ctx->builder,
1519 LLVMBuildSub(ctx->builder,
1520 LLVMBuildShl(ctx->builder,
1521 ctx->i32_1,
1522 src3, ""),
1523 ctx->i32_1, ""),
1524 src2, "");
1525 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1526 bfi_args[2] = src0;
1527
1528 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1529
1530 /* Calculate:
1531 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1532 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1533 */
1534 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1535 LLVMBuildAnd(ctx->builder, bfi_args[0],
1536 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1537
1538 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1539 return result;
1540 }
1541
1542 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1543 LLVMValueRef src0)
1544 {
1545 LLVMValueRef comp[2];
1546
1547 src0 = ac_to_float(ctx, src0);
1548 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1549 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1550
1551 return ac_build_cvt_pkrtz_f16(ctx, comp);
1552 }
1553
1554 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1555 LLVMValueRef src0)
1556 {
1557 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1558 LLVMValueRef temps[2], result, val;
1559 int i;
1560
1561 for (i = 0; i < 2; i++) {
1562 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1563 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1564 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1565 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1566 }
1567
1568 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1569 ctx->i32_0, "");
1570 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1571 ctx->i32_1, "");
1572 return result;
1573 }
1574
1575 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1576 nir_op op,
1577 LLVMValueRef src0)
1578 {
1579 unsigned mask;
1580 int idx;
1581 LLVMValueRef result;
1582
1583 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1584 mask = AC_TID_MASK_LEFT;
1585 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1586 mask = AC_TID_MASK_TOP;
1587 else
1588 mask = AC_TID_MASK_TOP_LEFT;
1589
1590 /* for DDX we want to next X pixel, DDY next Y pixel. */
1591 if (op == nir_op_fddx_fine ||
1592 op == nir_op_fddx_coarse ||
1593 op == nir_op_fddx)
1594 idx = 1;
1595 else
1596 idx = 2;
1597
1598 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1599 return result;
1600 }
1601
1602 /*
1603 * this takes an I,J coordinate pair,
1604 * and works out the X and Y derivatives.
1605 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1606 */
1607 static LLVMValueRef emit_ddxy_interp(
1608 struct ac_nir_context *ctx,
1609 LLVMValueRef interp_ij)
1610 {
1611 LLVMValueRef result[4], a;
1612 unsigned i;
1613
1614 for (i = 0; i < 2; i++) {
1615 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1616 LLVMConstInt(ctx->ac.i32, i, false), "");
1617 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1618 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1619 }
1620 return ac_build_gather_values(&ctx->ac, result, 4);
1621 }
1622
1623 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1624 {
1625 LLVMValueRef src[4], result = NULL;
1626 unsigned num_components = instr->dest.dest.ssa.num_components;
1627 unsigned src_components;
1628 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1629
1630 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1631 switch (instr->op) {
1632 case nir_op_vec2:
1633 case nir_op_vec3:
1634 case nir_op_vec4:
1635 src_components = 1;
1636 break;
1637 case nir_op_pack_half_2x16:
1638 src_components = 2;
1639 break;
1640 case nir_op_unpack_half_2x16:
1641 src_components = 1;
1642 break;
1643 default:
1644 src_components = num_components;
1645 break;
1646 }
1647 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1648 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1649
1650 switch (instr->op) {
1651 case nir_op_fmov:
1652 case nir_op_imov:
1653 result = src[0];
1654 break;
1655 case nir_op_fneg:
1656 src[0] = ac_to_float(&ctx->ac, src[0]);
1657 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1658 break;
1659 case nir_op_ineg:
1660 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1661 break;
1662 case nir_op_inot:
1663 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1664 break;
1665 case nir_op_iadd:
1666 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1667 break;
1668 case nir_op_fadd:
1669 src[0] = ac_to_float(&ctx->ac, src[0]);
1670 src[1] = ac_to_float(&ctx->ac, src[1]);
1671 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1672 break;
1673 case nir_op_fsub:
1674 src[0] = ac_to_float(&ctx->ac, src[0]);
1675 src[1] = ac_to_float(&ctx->ac, src[1]);
1676 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1677 break;
1678 case nir_op_isub:
1679 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1680 break;
1681 case nir_op_imul:
1682 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1683 break;
1684 case nir_op_imod:
1685 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1686 break;
1687 case nir_op_umod:
1688 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1689 break;
1690 case nir_op_fmod:
1691 src[0] = ac_to_float(&ctx->ac, src[0]);
1692 src[1] = ac_to_float(&ctx->ac, src[1]);
1693 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1694 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1695 ac_to_float_type(&ctx->ac, def_type), result);
1696 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1697 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1698 break;
1699 case nir_op_frem:
1700 src[0] = ac_to_float(&ctx->ac, src[0]);
1701 src[1] = ac_to_float(&ctx->ac, src[1]);
1702 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1703 break;
1704 case nir_op_irem:
1705 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1706 break;
1707 case nir_op_idiv:
1708 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1709 break;
1710 case nir_op_udiv:
1711 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1712 break;
1713 case nir_op_fmul:
1714 src[0] = ac_to_float(&ctx->ac, src[0]);
1715 src[1] = ac_to_float(&ctx->ac, src[1]);
1716 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1717 break;
1718 case nir_op_fdiv:
1719 src[0] = ac_to_float(&ctx->ac, src[0]);
1720 src[1] = ac_to_float(&ctx->ac, src[1]);
1721 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1722 break;
1723 case nir_op_frcp:
1724 src[0] = ac_to_float(&ctx->ac, src[0]);
1725 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1726 break;
1727 case nir_op_iand:
1728 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1729 break;
1730 case nir_op_ior:
1731 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1732 break;
1733 case nir_op_ixor:
1734 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1735 break;
1736 case nir_op_ishl:
1737 result = LLVMBuildShl(ctx->ac.builder, src[0],
1738 LLVMBuildZExt(ctx->ac.builder, src[1],
1739 LLVMTypeOf(src[0]), ""),
1740 "");
1741 break;
1742 case nir_op_ishr:
1743 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1744 LLVMBuildZExt(ctx->ac.builder, src[1],
1745 LLVMTypeOf(src[0]), ""),
1746 "");
1747 break;
1748 case nir_op_ushr:
1749 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1750 LLVMBuildZExt(ctx->ac.builder, src[1],
1751 LLVMTypeOf(src[0]), ""),
1752 "");
1753 break;
1754 case nir_op_ilt:
1755 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1756 break;
1757 case nir_op_ine:
1758 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1759 break;
1760 case nir_op_ieq:
1761 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1762 break;
1763 case nir_op_ige:
1764 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1765 break;
1766 case nir_op_ult:
1767 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1768 break;
1769 case nir_op_uge:
1770 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1771 break;
1772 case nir_op_feq:
1773 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1774 break;
1775 case nir_op_fne:
1776 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1777 break;
1778 case nir_op_flt:
1779 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1780 break;
1781 case nir_op_fge:
1782 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1783 break;
1784 case nir_op_fabs:
1785 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1786 ac_to_float_type(&ctx->ac, def_type), src[0]);
1787 break;
1788 case nir_op_iabs:
1789 result = emit_iabs(&ctx->ac, src[0]);
1790 break;
1791 case nir_op_imax:
1792 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1793 break;
1794 case nir_op_imin:
1795 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1796 break;
1797 case nir_op_umax:
1798 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1799 break;
1800 case nir_op_umin:
1801 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1802 break;
1803 case nir_op_isign:
1804 result = emit_isign(&ctx->ac, src[0]);
1805 break;
1806 case nir_op_fsign:
1807 src[0] = ac_to_float(&ctx->ac, src[0]);
1808 result = emit_fsign(&ctx->ac, src[0]);
1809 break;
1810 case nir_op_ffloor:
1811 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1812 ac_to_float_type(&ctx->ac, def_type), src[0]);
1813 break;
1814 case nir_op_ftrunc:
1815 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1816 ac_to_float_type(&ctx->ac, def_type), src[0]);
1817 break;
1818 case nir_op_fceil:
1819 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1820 ac_to_float_type(&ctx->ac, def_type), src[0]);
1821 break;
1822 case nir_op_fround_even:
1823 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1824 ac_to_float_type(&ctx->ac, def_type),src[0]);
1825 break;
1826 case nir_op_ffract:
1827 result = emit_ffract(&ctx->ac, src[0]);
1828 break;
1829 case nir_op_fsin:
1830 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1831 ac_to_float_type(&ctx->ac, def_type), src[0]);
1832 break;
1833 case nir_op_fcos:
1834 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1835 ac_to_float_type(&ctx->ac, def_type), src[0]);
1836 break;
1837 case nir_op_fsqrt:
1838 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1839 ac_to_float_type(&ctx->ac, def_type), src[0]);
1840 break;
1841 case nir_op_fexp2:
1842 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1843 ac_to_float_type(&ctx->ac, def_type), src[0]);
1844 break;
1845 case nir_op_flog2:
1846 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1847 ac_to_float_type(&ctx->ac, def_type), src[0]);
1848 break;
1849 case nir_op_frsq:
1850 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1851 ac_to_float_type(&ctx->ac, def_type), src[0]);
1852 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1853 break;
1854 case nir_op_fpow:
1855 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1856 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1857 break;
1858 case nir_op_fmax:
1859 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1860 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1861 if (instr->dest.dest.ssa.bit_size == 32)
1862 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1863 ac_to_float_type(&ctx->ac, def_type),
1864 result);
1865 break;
1866 case nir_op_fmin:
1867 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1868 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1869 if (instr->dest.dest.ssa.bit_size == 32)
1870 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1871 ac_to_float_type(&ctx->ac, def_type),
1872 result);
1873 break;
1874 case nir_op_ffma:
1875 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1876 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1877 break;
1878 case nir_op_ibitfield_extract:
1879 result = emit_bitfield_extract(&ctx->ac, true, src);
1880 break;
1881 case nir_op_ubitfield_extract:
1882 result = emit_bitfield_extract(&ctx->ac, false, src);
1883 break;
1884 case nir_op_bitfield_insert:
1885 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1886 break;
1887 case nir_op_bitfield_reverse:
1888 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1889 break;
1890 case nir_op_bit_count:
1891 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1892 break;
1893 case nir_op_vec2:
1894 case nir_op_vec3:
1895 case nir_op_vec4:
1896 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1897 src[i] = ac_to_integer(&ctx->ac, src[i]);
1898 result = ac_build_gather_values(&ctx->ac, src, num_components);
1899 break;
1900 case nir_op_f2i32:
1901 case nir_op_f2i64:
1902 src[0] = ac_to_float(&ctx->ac, src[0]);
1903 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1904 break;
1905 case nir_op_f2u32:
1906 case nir_op_f2u64:
1907 src[0] = ac_to_float(&ctx->ac, src[0]);
1908 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1909 break;
1910 case nir_op_i2f32:
1911 case nir_op_i2f64:
1912 src[0] = ac_to_integer(&ctx->ac, src[0]);
1913 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1914 break;
1915 case nir_op_u2f32:
1916 case nir_op_u2f64:
1917 src[0] = ac_to_integer(&ctx->ac, src[0]);
1918 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1919 break;
1920 case nir_op_f2f64:
1921 src[0] = ac_to_float(&ctx->ac, src[0]);
1922 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1923 break;
1924 case nir_op_f2f32:
1925 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1926 break;
1927 case nir_op_u2u32:
1928 case nir_op_u2u64:
1929 src[0] = ac_to_integer(&ctx->ac, src[0]);
1930 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1931 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1932 else
1933 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1934 break;
1935 case nir_op_i2i32:
1936 case nir_op_i2i64:
1937 src[0] = ac_to_integer(&ctx->ac, src[0]);
1938 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1939 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1940 else
1941 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1942 break;
1943 case nir_op_bcsel:
1944 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1945 break;
1946 case nir_op_find_lsb:
1947 src[0] = ac_to_integer(&ctx->ac, src[0]);
1948 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1949 break;
1950 case nir_op_ufind_msb:
1951 src[0] = ac_to_integer(&ctx->ac, src[0]);
1952 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1953 break;
1954 case nir_op_ifind_msb:
1955 src[0] = ac_to_integer(&ctx->ac, src[0]);
1956 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1957 break;
1958 case nir_op_uadd_carry:
1959 src[0] = ac_to_integer(&ctx->ac, src[0]);
1960 src[1] = ac_to_integer(&ctx->ac, src[1]);
1961 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1962 break;
1963 case nir_op_usub_borrow:
1964 src[0] = ac_to_integer(&ctx->ac, src[0]);
1965 src[1] = ac_to_integer(&ctx->ac, src[1]);
1966 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1967 break;
1968 case nir_op_b2f:
1969 result = emit_b2f(&ctx->ac, src[0]);
1970 break;
1971 case nir_op_f2b:
1972 result = emit_f2b(&ctx->ac, src[0]);
1973 break;
1974 case nir_op_b2i:
1975 result = emit_b2i(&ctx->ac, src[0]);
1976 break;
1977 case nir_op_i2b:
1978 src[0] = ac_to_integer(&ctx->ac, src[0]);
1979 result = emit_i2b(&ctx->ac, src[0]);
1980 break;
1981 case nir_op_fquantize2f16:
1982 result = emit_f2f16(ctx->nctx, src[0]);
1983 break;
1984 case nir_op_umul_high:
1985 src[0] = ac_to_integer(&ctx->ac, src[0]);
1986 src[1] = ac_to_integer(&ctx->ac, src[1]);
1987 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1988 break;
1989 case nir_op_imul_high:
1990 src[0] = ac_to_integer(&ctx->ac, src[0]);
1991 src[1] = ac_to_integer(&ctx->ac, src[1]);
1992 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1993 break;
1994 case nir_op_pack_half_2x16:
1995 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1996 break;
1997 case nir_op_unpack_half_2x16:
1998 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1999 break;
2000 case nir_op_fddx:
2001 case nir_op_fddy:
2002 case nir_op_fddx_fine:
2003 case nir_op_fddy_fine:
2004 case nir_op_fddx_coarse:
2005 case nir_op_fddy_coarse:
2006 result = emit_ddxy(ctx, instr->op, src[0]);
2007 break;
2008
2009 case nir_op_unpack_64_2x32_split_x: {
2010 assert(instr->src[0].src.ssa->num_components == 1);
2011 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2012 ctx->ac.v2i32,
2013 "");
2014 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2015 ctx->ac.i32_0, "");
2016 break;
2017 }
2018
2019 case nir_op_unpack_64_2x32_split_y: {
2020 assert(instr->src[0].src.ssa->num_components == 1);
2021 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2022 ctx->ac.v2i32,
2023 "");
2024 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2025 ctx->ac.i32_1, "");
2026 break;
2027 }
2028
2029 case nir_op_pack_64_2x32_split: {
2030 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2031 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2032 src[0], ctx->ac.i32_0, "");
2033 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2034 src[1], ctx->ac.i32_1, "");
2035 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2036 break;
2037 }
2038
2039 default:
2040 fprintf(stderr, "Unknown NIR alu instr: ");
2041 nir_print_instr(&instr->instr, stderr);
2042 fprintf(stderr, "\n");
2043 abort();
2044 }
2045
2046 if (result) {
2047 assert(instr->dest.dest.is_ssa);
2048 result = ac_to_integer(&ctx->ac, result);
2049 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2050 result);
2051 }
2052 }
2053
2054 static void visit_load_const(struct ac_nir_context *ctx,
2055 const nir_load_const_instr *instr)
2056 {
2057 LLVMValueRef values[4], value = NULL;
2058 LLVMTypeRef element_type =
2059 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2060
2061 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2062 switch (instr->def.bit_size) {
2063 case 32:
2064 values[i] = LLVMConstInt(element_type,
2065 instr->value.u32[i], false);
2066 break;
2067 case 64:
2068 values[i] = LLVMConstInt(element_type,
2069 instr->value.u64[i], false);
2070 break;
2071 default:
2072 fprintf(stderr,
2073 "unsupported nir load_const bit_size: %d\n",
2074 instr->def.bit_size);
2075 abort();
2076 }
2077 }
2078 if (instr->def.num_components > 1) {
2079 value = LLVMConstVector(values, instr->def.num_components);
2080 } else
2081 value = values[0];
2082
2083 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2084 }
2085
2086 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2087 LLVMTypeRef type)
2088 {
2089 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2090 return LLVMBuildBitCast(ctx->builder, ptr,
2091 LLVMPointerType(type, addr_space), "");
2092 }
2093
2094 static LLVMValueRef
2095 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2096 {
2097 LLVMValueRef size =
2098 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2099 LLVMConstInt(ctx->ac.i32, 2, false), "");
2100
2101 /* VI only */
2102 if (ctx->ac.chip_class == VI && in_elements) {
2103 /* On VI, the descriptor contains the size in bytes,
2104 * but TXQ must return the size in elements.
2105 * The stride is always non-zero for resources using TXQ.
2106 */
2107 LLVMValueRef stride =
2108 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2109 ctx->ac.i32_1, "");
2110 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2111 LLVMConstInt(ctx->ac.i32, 16, false), "");
2112 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2113 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2114
2115 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2116 }
2117 return size;
2118 }
2119
2120 /**
2121 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2122 * intrinsic names).
2123 */
2124 static void build_int_type_name(
2125 LLVMTypeRef type,
2126 char *buf, unsigned bufsize)
2127 {
2128 assert(bufsize >= 6);
2129
2130 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2131 snprintf(buf, bufsize, "v%ui32",
2132 LLVMGetVectorSize(type));
2133 else
2134 strcpy(buf, "i32");
2135 }
2136
2137 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2138 struct ac_image_args *args,
2139 const nir_tex_instr *instr)
2140 {
2141 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2142 LLVMValueRef coord = args->addr;
2143 LLVMValueRef half_texel[2];
2144 LLVMValueRef compare_cube_wa = NULL;
2145 LLVMValueRef result;
2146 int c;
2147 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2148
2149 //TODO Rect
2150 {
2151 struct ac_image_args txq_args = { 0 };
2152
2153 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2154 txq_args.opcode = ac_image_get_resinfo;
2155 txq_args.dmask = 0xf;
2156 txq_args.addr = ctx->i32_0;
2157 txq_args.resource = args->resource;
2158 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2159
2160 for (c = 0; c < 2; c++) {
2161 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2162 LLVMConstInt(ctx->i32, c, false), "");
2163 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2164 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2165 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2166 LLVMConstReal(ctx->f32, -0.5), "");
2167 }
2168 }
2169
2170 LLVMValueRef orig_coords = args->addr;
2171
2172 for (c = 0; c < 2; c++) {
2173 LLVMValueRef tmp;
2174 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2175 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2176 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2177 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2178 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2179 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2180 }
2181
2182
2183 /*
2184 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2185 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2186 * workaround by sampling using a scaled type and converting.
2187 * This is taken from amdgpu-pro shaders.
2188 */
2189 /* NOTE this produces some ugly code compared to amdgpu-pro,
2190 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2191 * and then reads them back. -pro generates two selects,
2192 * one s_cmp for the descriptor rewriting
2193 * one v_cmp for the coordinate and result changes.
2194 */
2195 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2196 LLVMValueRef tmp, tmp2;
2197
2198 /* workaround 8/8/8/8 uint/sint cube gather bug */
2199 /* first detect it then change to a scaled read and f2i */
2200 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2201 tmp2 = tmp;
2202
2203 /* extract the DATA_FORMAT */
2204 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2205 LLVMConstInt(ctx->i32, 6, false), false);
2206
2207 /* is the DATA_FORMAT == 8_8_8_8 */
2208 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2209
2210 if (stype == GLSL_TYPE_UINT)
2211 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2212 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2213 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2214 else
2215 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2216 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2217 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2218
2219 /* replace the NUM FORMAT in the descriptor */
2220 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2221 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2222
2223 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2224
2225 /* don't modify the coordinates for this case */
2226 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2227 }
2228 args->addr = coord;
2229 result = ac_build_image_opcode(ctx, args);
2230
2231 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2232 LLVMValueRef tmp, tmp2;
2233
2234 /* if the cube workaround is in place, f2i the result. */
2235 for (c = 0; c < 4; c++) {
2236 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2237 if (stype == GLSL_TYPE_UINT)
2238 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2239 else
2240 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2241 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2242 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2243 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2244 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2245 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2246 }
2247 }
2248 return result;
2249 }
2250
2251 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2252 const nir_tex_instr *instr,
2253 bool lod_is_zero,
2254 struct ac_image_args *args)
2255 {
2256 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2257 return ac_build_buffer_load_format(&ctx->ac,
2258 args->resource,
2259 args->addr,
2260 ctx->ac.i32_0,
2261 true);
2262 }
2263
2264 args->opcode = ac_image_sample;
2265 args->compare = instr->is_shadow;
2266
2267 switch (instr->op) {
2268 case nir_texop_txf:
2269 case nir_texop_txf_ms:
2270 case nir_texop_samples_identical:
2271 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2272 args->compare = false;
2273 args->offset = false;
2274 break;
2275 case nir_texop_txb:
2276 args->bias = true;
2277 break;
2278 case nir_texop_txl:
2279 if (lod_is_zero)
2280 args->level_zero = true;
2281 else
2282 args->lod = true;
2283 break;
2284 case nir_texop_txs:
2285 case nir_texop_query_levels:
2286 args->opcode = ac_image_get_resinfo;
2287 break;
2288 case nir_texop_tex:
2289 if (ctx->stage != MESA_SHADER_FRAGMENT)
2290 args->level_zero = true;
2291 break;
2292 case nir_texop_txd:
2293 args->deriv = true;
2294 break;
2295 case nir_texop_tg4:
2296 args->opcode = ac_image_gather4;
2297 args->level_zero = true;
2298 break;
2299 case nir_texop_lod:
2300 args->opcode = ac_image_get_lod;
2301 args->compare = false;
2302 args->offset = false;
2303 break;
2304 default:
2305 break;
2306 }
2307
2308 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2309 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2310 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2311 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2312 }
2313 }
2314 return ac_build_image_opcode(&ctx->ac, args);
2315 }
2316
2317 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2318 nir_intrinsic_instr *instr)
2319 {
2320 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2321 unsigned desc_set = nir_intrinsic_desc_set(instr);
2322 unsigned binding = nir_intrinsic_binding(instr);
2323 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2324 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2325 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2326 unsigned base_offset = layout->binding[binding].offset;
2327 LLVMValueRef offset, stride;
2328
2329 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2330 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2331 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2332 layout->binding[binding].dynamic_offset_offset;
2333 desc_ptr = ctx->push_constants;
2334 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2335 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2336 } else
2337 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2338
2339 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2340 index = LLVMBuildMul(ctx->builder, index, stride, "");
2341 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2342
2343 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2344 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2345 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2346
2347 return desc_ptr;
2348 }
2349
2350 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2351 nir_intrinsic_instr *instr)
2352 {
2353 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2354 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2355
2356 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2357 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2358 return result;
2359 }
2360
2361 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2362 nir_intrinsic_instr *instr)
2363 {
2364 LLVMValueRef ptr, addr;
2365
2366 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2367 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2368
2369 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2370 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2371
2372 return LLVMBuildLoad(ctx->builder, ptr, "");
2373 }
2374
2375 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2376 const nir_intrinsic_instr *instr)
2377 {
2378 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2379
2380 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2381 }
2382 static void visit_store_ssbo(struct ac_nir_context *ctx,
2383 nir_intrinsic_instr *instr)
2384 {
2385 const char *store_name;
2386 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2387 LLVMTypeRef data_type = ctx->ac.f32;
2388 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2389 int components_32bit = elem_size_mult * instr->num_components;
2390 unsigned writemask = nir_intrinsic_write_mask(instr);
2391 LLVMValueRef base_data, base_offset;
2392 LLVMValueRef params[6];
2393
2394 params[1] = ctx->abi->load_ssbo(ctx->abi,
2395 get_src(ctx, instr->src[1]), true);
2396 params[2] = ctx->ac.i32_0; /* vindex */
2397 params[4] = ctx->ac.i1false; /* glc */
2398 params[5] = ctx->ac.i1false; /* slc */
2399
2400 if (components_32bit > 1)
2401 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2402
2403 base_data = ac_to_float(&ctx->ac, src_data);
2404 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2405 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2406 data_type, "");
2407 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2408 while (writemask) {
2409 int start, count;
2410 LLVMValueRef data;
2411 LLVMValueRef offset;
2412 LLVMValueRef tmp;
2413 u_bit_scan_consecutive_range(&writemask, &start, &count);
2414
2415 /* Due to an LLVM limitation, split 3-element writes
2416 * into a 2-element and a 1-element write. */
2417 if (count == 3) {
2418 writemask |= 1 << (start + 2);
2419 count = 2;
2420 }
2421
2422 start *= elem_size_mult;
2423 count *= elem_size_mult;
2424
2425 if (count > 4) {
2426 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2427 count = 4;
2428 }
2429
2430 if (count == 4) {
2431 store_name = "llvm.amdgcn.buffer.store.v4f32";
2432 data = base_data;
2433 } else if (count == 2) {
2434 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2435 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2436 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2437 ctx->ac.i32_0, "");
2438
2439 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2440 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2441 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2442 ctx->ac.i32_1, "");
2443 store_name = "llvm.amdgcn.buffer.store.v2f32";
2444
2445 } else {
2446 assert(count == 1);
2447 if (get_llvm_num_components(base_data) > 1)
2448 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2449 LLVMConstInt(ctx->ac.i32, start, false), "");
2450 else
2451 data = base_data;
2452 store_name = "llvm.amdgcn.buffer.store.f32";
2453 }
2454
2455 offset = base_offset;
2456 if (start != 0) {
2457 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2458 }
2459 params[0] = data;
2460 params[3] = offset;
2461 ac_build_intrinsic(&ctx->ac, store_name,
2462 ctx->ac.voidt, params, 6, 0);
2463 }
2464 }
2465
2466 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2467 const nir_intrinsic_instr *instr)
2468 {
2469 const char *name;
2470 LLVMValueRef params[6];
2471 int arg_count = 0;
2472
2473 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2474 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2475 }
2476 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2477 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2478 get_src(ctx, instr->src[0]),
2479 true);
2480 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2481 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2482 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2483
2484 switch (instr->intrinsic) {
2485 case nir_intrinsic_ssbo_atomic_add:
2486 name = "llvm.amdgcn.buffer.atomic.add";
2487 break;
2488 case nir_intrinsic_ssbo_atomic_imin:
2489 name = "llvm.amdgcn.buffer.atomic.smin";
2490 break;
2491 case nir_intrinsic_ssbo_atomic_umin:
2492 name = "llvm.amdgcn.buffer.atomic.umin";
2493 break;
2494 case nir_intrinsic_ssbo_atomic_imax:
2495 name = "llvm.amdgcn.buffer.atomic.smax";
2496 break;
2497 case nir_intrinsic_ssbo_atomic_umax:
2498 name = "llvm.amdgcn.buffer.atomic.umax";
2499 break;
2500 case nir_intrinsic_ssbo_atomic_and:
2501 name = "llvm.amdgcn.buffer.atomic.and";
2502 break;
2503 case nir_intrinsic_ssbo_atomic_or:
2504 name = "llvm.amdgcn.buffer.atomic.or";
2505 break;
2506 case nir_intrinsic_ssbo_atomic_xor:
2507 name = "llvm.amdgcn.buffer.atomic.xor";
2508 break;
2509 case nir_intrinsic_ssbo_atomic_exchange:
2510 name = "llvm.amdgcn.buffer.atomic.swap";
2511 break;
2512 case nir_intrinsic_ssbo_atomic_comp_swap:
2513 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2514 break;
2515 default:
2516 abort();
2517 }
2518
2519 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2520 }
2521
2522 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2523 const nir_intrinsic_instr *instr)
2524 {
2525 LLVMValueRef results[2];
2526 int load_components;
2527 int num_components = instr->num_components;
2528 if (instr->dest.ssa.bit_size == 64)
2529 num_components *= 2;
2530
2531 for (int i = 0; i < num_components; i += load_components) {
2532 load_components = MIN2(num_components - i, 4);
2533 const char *load_name;
2534 LLVMTypeRef data_type = ctx->ac.f32;
2535 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2536 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2537
2538 if (load_components == 3)
2539 data_type = LLVMVectorType(ctx->ac.f32, 4);
2540 else if (load_components > 1)
2541 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2542
2543 if (load_components >= 3)
2544 load_name = "llvm.amdgcn.buffer.load.v4f32";
2545 else if (load_components == 2)
2546 load_name = "llvm.amdgcn.buffer.load.v2f32";
2547 else if (load_components == 1)
2548 load_name = "llvm.amdgcn.buffer.load.f32";
2549 else
2550 unreachable("unhandled number of components");
2551
2552 LLVMValueRef params[] = {
2553 ctx->abi->load_ssbo(ctx->abi,
2554 get_src(ctx, instr->src[0]),
2555 false),
2556 ctx->ac.i32_0,
2557 offset,
2558 ctx->ac.i1false,
2559 ctx->ac.i1false,
2560 };
2561
2562 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2563
2564 }
2565
2566 assume(results[0]);
2567 LLVMValueRef ret = results[0];
2568 if (num_components > 4 || num_components == 3) {
2569 LLVMValueRef masks[] = {
2570 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2571 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2572 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2573 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2574 };
2575
2576 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2577 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2578 results[num_components > 4 ? 1 : 0], swizzle, "");
2579 }
2580
2581 return LLVMBuildBitCast(ctx->ac.builder, ret,
2582 get_def_type(ctx, &instr->dest.ssa), "");
2583 }
2584
2585 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2586 const nir_intrinsic_instr *instr)
2587 {
2588 LLVMValueRef results[8], ret;
2589 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2590 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2591 int num_components = instr->num_components;
2592
2593 if (ctx->abi->load_ubo)
2594 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2595
2596 if (instr->dest.ssa.bit_size == 64)
2597 num_components *= 2;
2598
2599 for (unsigned i = 0; i < num_components; ++i) {
2600 LLVMValueRef params[] = {
2601 rsrc,
2602 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2603 offset, "")
2604 };
2605 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2606 params, 2,
2607 AC_FUNC_ATTR_READNONE |
2608 AC_FUNC_ATTR_LEGACY);
2609 }
2610
2611
2612 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2613 return LLVMBuildBitCast(ctx->ac.builder, ret,
2614 get_def_type(ctx, &instr->dest.ssa), "");
2615 }
2616
2617 static void
2618 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2619 bool vs_in, unsigned *vertex_index_out,
2620 LLVMValueRef *vertex_index_ref,
2621 unsigned *const_out, LLVMValueRef *indir_out)
2622 {
2623 unsigned const_offset = 0;
2624 nir_deref *tail = &deref->deref;
2625 LLVMValueRef offset = NULL;
2626
2627 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2628 tail = tail->child;
2629 nir_deref_array *deref_array = nir_deref_as_array(tail);
2630 if (vertex_index_out)
2631 *vertex_index_out = deref_array->base_offset;
2632
2633 if (vertex_index_ref) {
2634 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2635 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2636 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2637 }
2638 *vertex_index_ref = vtx;
2639 }
2640 }
2641
2642 if (deref->var->data.compact) {
2643 assert(tail->child->deref_type == nir_deref_type_array);
2644 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2645 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2646 /* We always lower indirect dereferences for "compact" array vars. */
2647 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2648
2649 const_offset = deref_array->base_offset;
2650 goto out;
2651 }
2652
2653 while (tail->child != NULL) {
2654 const struct glsl_type *parent_type = tail->type;
2655 tail = tail->child;
2656
2657 if (tail->deref_type == nir_deref_type_array) {
2658 nir_deref_array *deref_array = nir_deref_as_array(tail);
2659 LLVMValueRef index, stride, local_offset;
2660 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2661
2662 const_offset += size * deref_array->base_offset;
2663 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2664 continue;
2665
2666 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2667 index = get_src(ctx, deref_array->indirect);
2668 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2669 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2670
2671 if (offset)
2672 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2673 else
2674 offset = local_offset;
2675 } else if (tail->deref_type == nir_deref_type_struct) {
2676 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2677
2678 for (unsigned i = 0; i < deref_struct->index; i++) {
2679 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2680 const_offset += glsl_count_attribute_slots(ft, vs_in);
2681 }
2682 } else
2683 unreachable("unsupported deref type");
2684
2685 }
2686 out:
2687 if (const_offset && offset)
2688 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2689 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2690 "");
2691
2692 *const_out = const_offset;
2693 *indir_out = offset;
2694 }
2695
2696
2697 /* The offchip buffer layout for TCS->TES is
2698 *
2699 * - attribute 0 of patch 0 vertex 0
2700 * - attribute 0 of patch 0 vertex 1
2701 * - attribute 0 of patch 0 vertex 2
2702 * ...
2703 * - attribute 0 of patch 1 vertex 0
2704 * - attribute 0 of patch 1 vertex 1
2705 * ...
2706 * - attribute 1 of patch 0 vertex 0
2707 * - attribute 1 of patch 0 vertex 1
2708 * ...
2709 * - per patch attribute 0 of patch 0
2710 * - per patch attribute 0 of patch 1
2711 * ...
2712 *
2713 * Note that every attribute has 4 components.
2714 */
2715 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2716 LLVMValueRef vertex_index,
2717 LLVMValueRef param_index)
2718 {
2719 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2720 LLVMValueRef param_stride, constant16;
2721 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2722
2723 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2724 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2725 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2726 num_patches, "");
2727
2728 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2729 if (vertex_index) {
2730 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2731 vertices_per_patch, "");
2732
2733 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2734 vertex_index, "");
2735
2736 param_stride = total_vertices;
2737 } else {
2738 base_addr = rel_patch_id;
2739 param_stride = num_patches;
2740 }
2741
2742 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2743 LLVMBuildMul(ctx->builder, param_index,
2744 param_stride, ""), "");
2745
2746 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2747
2748 if (!vertex_index) {
2749 LLVMValueRef patch_data_offset =
2750 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2751
2752 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2753 patch_data_offset, "");
2754 }
2755 return base_addr;
2756 }
2757
2758 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2759 unsigned param,
2760 unsigned const_index,
2761 bool is_compact,
2762 LLVMValueRef vertex_index,
2763 LLVMValueRef indir_index)
2764 {
2765 LLVMValueRef param_index;
2766
2767 if (indir_index)
2768 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2769 indir_index, "");
2770 else {
2771 if (const_index && !is_compact)
2772 param += const_index;
2773 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2774 }
2775 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2776 }
2777
2778 static void
2779 mark_tess_output(struct nir_to_llvm_context *ctx,
2780 bool is_patch, uint32_t param)
2781
2782 {
2783 if (is_patch) {
2784 ctx->tess_patch_outputs_written |= (1ull << param);
2785 } else
2786 ctx->tess_outputs_written |= (1ull << param);
2787 }
2788
2789 static LLVMValueRef
2790 get_dw_address(struct nir_to_llvm_context *ctx,
2791 LLVMValueRef dw_addr,
2792 unsigned param,
2793 unsigned const_index,
2794 bool compact_const_index,
2795 LLVMValueRef vertex_index,
2796 LLVMValueRef stride,
2797 LLVMValueRef indir_index)
2798
2799 {
2800
2801 if (vertex_index) {
2802 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2803 LLVMBuildMul(ctx->builder,
2804 vertex_index,
2805 stride, ""), "");
2806 }
2807
2808 if (indir_index)
2809 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2810 LLVMBuildMul(ctx->builder, indir_index,
2811 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2812 else if (const_index && !compact_const_index)
2813 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2814 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2815
2816 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2817 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2818
2819 if (const_index && compact_const_index)
2820 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2821 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2822 return dw_addr;
2823 }
2824
2825 static LLVMValueRef
2826 load_tcs_input(struct nir_to_llvm_context *ctx,
2827 nir_intrinsic_instr *instr)
2828 {
2829 LLVMValueRef dw_addr, stride;
2830 unsigned const_index;
2831 LLVMValueRef vertex_index;
2832 LLVMValueRef indir_index;
2833 unsigned param;
2834 LLVMValueRef value[4], result;
2835 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2836 const bool is_compact = instr->variables[0]->var->data.compact;
2837 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2838 get_deref_offset(ctx->nir, instr->variables[0],
2839 false, NULL, per_vertex ? &vertex_index : NULL,
2840 &const_index, &indir_index);
2841
2842 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2843 dw_addr = get_tcs_in_current_patch_offset(ctx);
2844 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2845 indir_index);
2846
2847 unsigned comp = instr->variables[0]->var->data.location_frac;
2848 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2849 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2850 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2851 ctx->ac.i32_1, "");
2852 }
2853 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2854 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2855 return result;
2856 }
2857
2858 static LLVMValueRef
2859 load_tcs_output(struct nir_to_llvm_context *ctx,
2860 nir_intrinsic_instr *instr)
2861 {
2862 LLVMValueRef dw_addr;
2863 LLVMValueRef stride = NULL;
2864 LLVMValueRef value[4], result;
2865 LLVMValueRef vertex_index = NULL;
2866 LLVMValueRef indir_index = NULL;
2867 unsigned const_index = 0;
2868 unsigned param;
2869 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2870 const bool is_compact = instr->variables[0]->var->data.compact;
2871 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2872 get_deref_offset(ctx->nir, instr->variables[0],
2873 false, NULL, per_vertex ? &vertex_index : NULL,
2874 &const_index, &indir_index);
2875
2876 if (!instr->variables[0]->var->data.patch) {
2877 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2878 dw_addr = get_tcs_out_current_patch_offset(ctx);
2879 } else {
2880 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2881 }
2882
2883 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2884 indir_index);
2885
2886 unsigned comp = instr->variables[0]->var->data.location_frac;
2887 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2888 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2889 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2890 ctx->ac.i32_1, "");
2891 }
2892 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2893 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2894 return result;
2895 }
2896
2897 static void
2898 store_tcs_output(struct nir_to_llvm_context *ctx,
2899 nir_intrinsic_instr *instr,
2900 LLVMValueRef src,
2901 unsigned writemask)
2902 {
2903 LLVMValueRef dw_addr;
2904 LLVMValueRef stride = NULL;
2905 LLVMValueRef buf_addr = NULL;
2906 LLVMValueRef vertex_index = NULL;
2907 LLVMValueRef indir_index = NULL;
2908 unsigned const_index = 0;
2909 unsigned param;
2910 const unsigned comp = instr->variables[0]->var->data.location_frac;
2911 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2912 const bool is_compact = instr->variables[0]->var->data.compact;
2913 bool store_lds = true;
2914
2915 if (instr->variables[0]->var->data.patch) {
2916 if (!(ctx->tcs_patch_outputs_read & (1U << (instr->variables[0]->var->data.location - VARYING_SLOT_PATCH0))))
2917 store_lds = false;
2918 } else {
2919 if (!(ctx->tcs_outputs_read & (1ULL << instr->variables[0]->var->data.location)))
2920 store_lds = false;
2921 }
2922 get_deref_offset(ctx->nir, instr->variables[0],
2923 false, NULL, per_vertex ? &vertex_index : NULL,
2924 &const_index, &indir_index);
2925
2926 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2927 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2928 is_compact && const_index > 3) {
2929 const_index -= 3;
2930 param++;
2931 }
2932
2933 if (!instr->variables[0]->var->data.patch) {
2934 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2935 dw_addr = get_tcs_out_current_patch_offset(ctx);
2936 } else {
2937 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2938 }
2939
2940 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2941
2942 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2943 indir_index);
2944 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2945 vertex_index, indir_index);
2946
2947 bool is_tess_factor = false;
2948 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2949 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2950 is_tess_factor = true;
2951
2952 unsigned base = is_compact ? const_index : 0;
2953 for (unsigned chan = 0; chan < 8; chan++) {
2954 if (!(writemask & (1 << chan)))
2955 continue;
2956 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2957
2958 if (store_lds || is_tess_factor)
2959 ac_lds_store(&ctx->ac, dw_addr, value);
2960
2961 if (!is_tess_factor && writemask != 0xF)
2962 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2963 buf_addr, ctx->oc_lds,
2964 4 * (base + chan), 1, 0, true, false);
2965
2966 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2967 ctx->ac.i32_1, "");
2968 }
2969
2970 if (writemask == 0xF) {
2971 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2972 buf_addr, ctx->oc_lds,
2973 (base * 4), 1, 0, true, false);
2974 }
2975 }
2976
2977 static LLVMValueRef
2978 load_tes_input(struct nir_to_llvm_context *ctx,
2979 const nir_intrinsic_instr *instr)
2980 {
2981 LLVMValueRef buf_addr;
2982 LLVMValueRef result;
2983 LLVMValueRef vertex_index = NULL;
2984 LLVMValueRef indir_index = NULL;
2985 unsigned const_index = 0;
2986 unsigned param;
2987 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2988 const bool is_compact = instr->variables[0]->var->data.compact;
2989
2990 get_deref_offset(ctx->nir, instr->variables[0],
2991 false, NULL, per_vertex ? &vertex_index : NULL,
2992 &const_index, &indir_index);
2993 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2994 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2995 is_compact && const_index > 3) {
2996 const_index -= 3;
2997 param++;
2998 }
2999
3000 unsigned comp = instr->variables[0]->var->data.location_frac;
3001 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3002 is_compact, vertex_index, indir_index);
3003
3004 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, comp * 4, false);
3005 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3006
3007 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
3008 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3009 result = trim_vector(&ctx->ac, result, instr->num_components);
3010 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
3011 return result;
3012 }
3013
3014 static LLVMValueRef
3015 load_gs_input(struct ac_shader_abi *abi,
3016 unsigned location,
3017 unsigned driver_location,
3018 unsigned component,
3019 unsigned num_components,
3020 unsigned vertex_index,
3021 unsigned const_index,
3022 LLVMTypeRef type)
3023 {
3024 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3025 LLVMValueRef vtx_offset;
3026 LLVMValueRef args[9];
3027 unsigned param, vtx_offset_param;
3028 LLVMValueRef value[4], result;
3029
3030 vtx_offset_param = vertex_index;
3031 assert(vtx_offset_param < 6);
3032 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3033 LLVMConstInt(ctx->ac.i32, 4, false), "");
3034
3035 param = shader_io_get_unique_index(location);
3036
3037 for (unsigned i = component; i < num_components + component; i++) {
3038 if (ctx->ac.chip_class >= GFX9) {
3039 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3040 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3041 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3042 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3043 } else {
3044 args[0] = ctx->esgs_ring;
3045 args[1] = vtx_offset;
3046 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3047 args[3] = ctx->ac.i32_0;
3048 args[4] = ctx->ac.i32_1; /* OFFEN */
3049 args[5] = ctx->ac.i32_0; /* IDXEN */
3050 args[6] = ctx->ac.i32_1; /* GLC */
3051 args[7] = ctx->ac.i32_0; /* SLC */
3052 args[8] = ctx->ac.i32_0; /* TFE */
3053
3054 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3055 ctx->ac.i32, args, 9,
3056 AC_FUNC_ATTR_READONLY |
3057 AC_FUNC_ATTR_LEGACY);
3058 }
3059 }
3060 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3061
3062 return result;
3063 }
3064
3065 static LLVMValueRef
3066 build_gep_for_deref(struct ac_nir_context *ctx,
3067 nir_deref_var *deref)
3068 {
3069 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3070 assert(entry->data);
3071 LLVMValueRef val = entry->data;
3072 nir_deref *tail = deref->deref.child;
3073 while (tail != NULL) {
3074 LLVMValueRef offset;
3075 switch (tail->deref_type) {
3076 case nir_deref_type_array: {
3077 nir_deref_array *array = nir_deref_as_array(tail);
3078 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3079 if (array->deref_array_type ==
3080 nir_deref_array_type_indirect) {
3081 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3082 get_src(ctx,
3083 array->indirect),
3084 "");
3085 }
3086 break;
3087 }
3088 case nir_deref_type_struct: {
3089 nir_deref_struct *deref_struct =
3090 nir_deref_as_struct(tail);
3091 offset = LLVMConstInt(ctx->ac.i32,
3092 deref_struct->index, 0);
3093 break;
3094 }
3095 default:
3096 unreachable("bad deref type");
3097 }
3098 val = ac_build_gep0(&ctx->ac, val, offset);
3099 tail = tail->child;
3100 }
3101 return val;
3102 }
3103
3104 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3105 nir_intrinsic_instr *instr)
3106 {
3107 LLVMValueRef values[8];
3108 int idx = instr->variables[0]->var->data.driver_location;
3109 int ve = instr->dest.ssa.num_components;
3110 unsigned comp = instr->variables[0]->var->data.location_frac;
3111 LLVMValueRef indir_index;
3112 LLVMValueRef ret;
3113 unsigned const_index;
3114 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3115 instr->variables[0]->var->data.mode == nir_var_shader_in;
3116 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3117 &const_index, &indir_index);
3118
3119 if (instr->dest.ssa.bit_size == 64)
3120 ve *= 2;
3121
3122 switch (instr->variables[0]->var->data.mode) {
3123 case nir_var_shader_in:
3124 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3125 return load_tcs_input(ctx->nctx, instr);
3126 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3127 return load_tes_input(ctx->nctx, instr);
3128 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3129 LLVMValueRef indir_index;
3130 unsigned const_index, vertex_index;
3131 get_deref_offset(ctx, instr->variables[0],
3132 false, &vertex_index, NULL,
3133 &const_index, &indir_index);
3134 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3135 instr->variables[0]->var->data.driver_location,
3136 instr->variables[0]->var->data.location_frac, ve,
3137 vertex_index, const_index,
3138 nir2llvmtype(ctx, instr->variables[0]->var->type));
3139 }
3140
3141 for (unsigned chan = comp; chan < ve + comp; chan++) {
3142 if (indir_index) {
3143 unsigned count = glsl_count_attribute_slots(
3144 instr->variables[0]->var->type,
3145 ctx->stage == MESA_SHADER_VERTEX);
3146 count -= chan / 4;
3147 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3148 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3149 4, false, true);
3150
3151 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3152 tmp_vec,
3153 indir_index, "");
3154 } else
3155 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3156 }
3157 break;
3158 case nir_var_local:
3159 for (unsigned chan = 0; chan < ve; chan++) {
3160 if (indir_index) {
3161 unsigned count = glsl_count_attribute_slots(
3162 instr->variables[0]->var->type, false);
3163 count -= chan / 4;
3164 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3165 &ctx->ac, ctx->locals + idx + chan, count,
3166 4, true, true);
3167
3168 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3169 tmp_vec,
3170 indir_index, "");
3171 } else {
3172 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3173 }
3174 }
3175 break;
3176 case nir_var_shared: {
3177 LLVMValueRef address = build_gep_for_deref(ctx,
3178 instr->variables[0]);
3179 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3180 return LLVMBuildBitCast(ctx->ac.builder, val,
3181 get_def_type(ctx, &instr->dest.ssa),
3182 "");
3183 }
3184 case nir_var_shader_out:
3185 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3186 return load_tcs_output(ctx->nctx, instr);
3187
3188 for (unsigned chan = comp; chan < ve + comp; chan++) {
3189 if (indir_index) {
3190 unsigned count = glsl_count_attribute_slots(
3191 instr->variables[0]->var->type, false);
3192 count -= chan / 4;
3193 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3194 &ctx->ac, ctx->outputs + idx + chan, count,
3195 4, true, true);
3196
3197 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3198 tmp_vec,
3199 indir_index, "");
3200 } else {
3201 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3202 ctx->outputs[idx + chan + const_index * 4],
3203 "");
3204 }
3205 }
3206 break;
3207 default:
3208 unreachable("unhandle variable mode");
3209 }
3210 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3211 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3212 }
3213
3214 static void
3215 visit_store_var(struct ac_nir_context *ctx,
3216 nir_intrinsic_instr *instr)
3217 {
3218 LLVMValueRef temp_ptr, value;
3219 int idx = instr->variables[0]->var->data.driver_location;
3220 unsigned comp = instr->variables[0]->var->data.location_frac;
3221 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3222 int writemask = instr->const_index[0] << comp;
3223 LLVMValueRef indir_index;
3224 unsigned const_index;
3225 get_deref_offset(ctx, instr->variables[0], false,
3226 NULL, NULL, &const_index, &indir_index);
3227
3228 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3229 int old_writemask = writemask;
3230
3231 src = LLVMBuildBitCast(ctx->ac.builder, src,
3232 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3233 "");
3234
3235 writemask = 0;
3236 for (unsigned chan = 0; chan < 4; chan++) {
3237 if (old_writemask & (1 << chan))
3238 writemask |= 3u << (2 * chan);
3239 }
3240 }
3241
3242 switch (instr->variables[0]->var->data.mode) {
3243 case nir_var_shader_out:
3244
3245 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3246 store_tcs_output(ctx->nctx, instr, src, writemask);
3247 return;
3248 }
3249
3250 for (unsigned chan = 0; chan < 8; chan++) {
3251 int stride = 4;
3252 if (!(writemask & (1 << chan)))
3253 continue;
3254
3255 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3256
3257 if (instr->variables[0]->var->data.compact)
3258 stride = 1;
3259 if (indir_index) {
3260 unsigned count = glsl_count_attribute_slots(
3261 instr->variables[0]->var->type, false);
3262 count -= chan / 4;
3263 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3264 &ctx->ac, ctx->outputs + idx + chan, count,
3265 stride, true, true);
3266
3267 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3268 value, indir_index, "");
3269 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3270 count, stride, tmp_vec);
3271
3272 } else {
3273 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3274
3275 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3276 }
3277 }
3278 break;
3279 case nir_var_local:
3280 for (unsigned chan = 0; chan < 8; chan++) {
3281 if (!(writemask & (1 << chan)))
3282 continue;
3283
3284 value = llvm_extract_elem(&ctx->ac, src, chan);
3285 if (indir_index) {
3286 unsigned count = glsl_count_attribute_slots(
3287 instr->variables[0]->var->type, false);
3288 count -= chan / 4;
3289 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3290 &ctx->ac, ctx->locals + idx + chan, count,
3291 4, true, true);
3292
3293 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3294 value, indir_index, "");
3295 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3296 count, 4, tmp_vec);
3297 } else {
3298 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3299
3300 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3301 }
3302 }
3303 break;
3304 case nir_var_shared: {
3305 int writemask = instr->const_index[0];
3306 LLVMValueRef address = build_gep_for_deref(ctx,
3307 instr->variables[0]);
3308 LLVMValueRef val = get_src(ctx, instr->src[0]);
3309 unsigned components =
3310 glsl_get_vector_elements(
3311 nir_deref_tail(&instr->variables[0]->deref)->type);
3312 if (writemask == (1 << components) - 1) {
3313 val = LLVMBuildBitCast(
3314 ctx->ac.builder, val,
3315 LLVMGetElementType(LLVMTypeOf(address)), "");
3316 LLVMBuildStore(ctx->ac.builder, val, address);
3317 } else {
3318 for (unsigned chan = 0; chan < 4; chan++) {
3319 if (!(writemask & (1 << chan)))
3320 continue;
3321 LLVMValueRef ptr =
3322 LLVMBuildStructGEP(ctx->ac.builder,
3323 address, chan, "");
3324 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3325 chan);
3326 src = LLVMBuildBitCast(
3327 ctx->ac.builder, src,
3328 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3329 LLVMBuildStore(ctx->ac.builder, src, ptr);
3330 }
3331 }
3332 break;
3333 }
3334 default:
3335 break;
3336 }
3337 }
3338
3339 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3340 {
3341 switch (dim) {
3342 case GLSL_SAMPLER_DIM_BUF:
3343 return 1;
3344 case GLSL_SAMPLER_DIM_1D:
3345 return array ? 2 : 1;
3346 case GLSL_SAMPLER_DIM_2D:
3347 return array ? 3 : 2;
3348 case GLSL_SAMPLER_DIM_MS:
3349 return array ? 4 : 3;
3350 case GLSL_SAMPLER_DIM_3D:
3351 case GLSL_SAMPLER_DIM_CUBE:
3352 return 3;
3353 case GLSL_SAMPLER_DIM_RECT:
3354 case GLSL_SAMPLER_DIM_SUBPASS:
3355 return 2;
3356 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3357 return 3;
3358 default:
3359 break;
3360 }
3361 return 0;
3362 }
3363
3364
3365
3366 /* Adjust the sample index according to FMASK.
3367 *
3368 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3369 * which is the identity mapping. Each nibble says which physical sample
3370 * should be fetched to get that sample.
3371 *
3372 * For example, 0x11111100 means there are only 2 samples stored and
3373 * the second sample covers 3/4 of the pixel. When reading samples 0
3374 * and 1, return physical sample 0 (determined by the first two 0s
3375 * in FMASK), otherwise return physical sample 1.
3376 *
3377 * The sample index should be adjusted as follows:
3378 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3379 */
3380 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3381 LLVMValueRef coord_x, LLVMValueRef coord_y,
3382 LLVMValueRef coord_z,
3383 LLVMValueRef sample_index,
3384 LLVMValueRef fmask_desc_ptr)
3385 {
3386 LLVMValueRef fmask_load_address[4];
3387 LLVMValueRef res;
3388
3389 fmask_load_address[0] = coord_x;
3390 fmask_load_address[1] = coord_y;
3391 if (coord_z) {
3392 fmask_load_address[2] = coord_z;
3393 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3394 }
3395
3396 struct ac_image_args args = {0};
3397
3398 args.opcode = ac_image_load;
3399 args.da = coord_z ? true : false;
3400 args.resource = fmask_desc_ptr;
3401 args.dmask = 0xf;
3402 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3403
3404 res = ac_build_image_opcode(ctx, &args);
3405
3406 res = ac_to_integer(ctx, res);
3407 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3408 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3409
3410 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3411 res,
3412 ctx->i32_0, "");
3413
3414 LLVMValueRef sample_index4 =
3415 LLVMBuildMul(ctx->builder, sample_index, four, "");
3416 LLVMValueRef shifted_fmask =
3417 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3418 LLVMValueRef final_sample =
3419 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3420
3421 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3422 * resource descriptor is 0 (invalid),
3423 */
3424 LLVMValueRef fmask_desc =
3425 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3426 ctx->v8i32, "");
3427
3428 LLVMValueRef fmask_word1 =
3429 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3430 ctx->i32_1, "");
3431
3432 LLVMValueRef word1_is_nonzero =
3433 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3434 fmask_word1, ctx->i32_0, "");
3435
3436 /* Replace the MSAA sample index. */
3437 sample_index =
3438 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3439 final_sample, sample_index, "");
3440 return sample_index;
3441 }
3442
3443 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3444 const nir_intrinsic_instr *instr)
3445 {
3446 const struct glsl_type *type = instr->variables[0]->var->type;
3447 if(instr->variables[0]->deref.child)
3448 type = instr->variables[0]->deref.child->type;
3449
3450 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3451 LLVMValueRef coords[4];
3452 LLVMValueRef masks[] = {
3453 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3454 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3455 };
3456 LLVMValueRef res;
3457 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3458
3459 int count;
3460 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3461 bool is_array = glsl_sampler_type_is_array(type);
3462 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3463 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3464 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3465 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3466 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3467 count = image_type_to_components_count(dim, is_array);
3468
3469 if (is_ms) {
3470 LLVMValueRef fmask_load_address[3];
3471 int chan;
3472
3473 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3474 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3475 if (is_array)
3476 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3477 else
3478 fmask_load_address[2] = NULL;
3479 if (add_frag_pos) {
3480 for (chan = 0; chan < 2; ++chan)
3481 fmask_load_address[chan] =
3482 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3483 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3484 ctx->ac.i32, ""), "");
3485 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3486 }
3487 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3488 fmask_load_address[0],
3489 fmask_load_address[1],
3490 fmask_load_address[2],
3491 sample_index,
3492 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3493 }
3494 if (count == 1 && !gfx9_1d) {
3495 if (instr->src[0].ssa->num_components)
3496 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3497 else
3498 res = src0;
3499 } else {
3500 int chan;
3501 if (is_ms)
3502 count--;
3503 for (chan = 0; chan < count; ++chan) {
3504 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3505 }
3506 if (add_frag_pos) {
3507 for (chan = 0; chan < 2; ++chan)
3508 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3509 ctx->ac.i32, ""), "");
3510 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3511 count++;
3512 }
3513
3514 if (gfx9_1d) {
3515 if (is_array) {
3516 coords[2] = coords[1];
3517 coords[1] = ctx->ac.i32_0;
3518 } else
3519 coords[1] = ctx->ac.i32_0;
3520 count++;
3521 }
3522
3523 if (is_ms) {
3524 coords[count] = sample_index;
3525 count++;
3526 }
3527
3528 if (count == 3) {
3529 coords[3] = LLVMGetUndef(ctx->ac.i32);
3530 count = 4;
3531 }
3532 res = ac_build_gather_values(&ctx->ac, coords, count);
3533 }
3534 return res;
3535 }
3536
3537 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3538 const nir_intrinsic_instr *instr)
3539 {
3540 LLVMValueRef params[7];
3541 LLVMValueRef res;
3542 char intrinsic_name[64];
3543 const nir_variable *var = instr->variables[0]->var;
3544 const struct glsl_type *type = var->type;
3545
3546 if(instr->variables[0]->deref.child)
3547 type = instr->variables[0]->deref.child->type;
3548
3549 type = glsl_without_array(type);
3550 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3551 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3552 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3553 ctx->ac.i32_0, ""); /* vindex */
3554 params[2] = ctx->ac.i32_0; /* voffset */
3555 params[3] = ctx->ac.i1false; /* glc */
3556 params[4] = ctx->ac.i1false; /* slc */
3557 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3558 params, 5, 0);
3559
3560 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3561 res = ac_to_integer(&ctx->ac, res);
3562 } else {
3563 bool is_da = glsl_sampler_type_is_array(type) ||
3564 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3565 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3566 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3567 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3568 LLVMValueRef glc = ctx->ac.i1false;
3569 LLVMValueRef slc = ctx->ac.i1false;
3570
3571 params[0] = get_image_coords(ctx, instr);
3572 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3573 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3574 if (HAVE_LLVM <= 0x0309) {
3575 params[3] = ctx->ac.i1false; /* r128 */
3576 params[4] = da;
3577 params[5] = glc;
3578 params[6] = slc;
3579 } else {
3580 LLVMValueRef lwe = ctx->ac.i1false;
3581 params[3] = glc;
3582 params[4] = slc;
3583 params[5] = lwe;
3584 params[6] = da;
3585 }
3586
3587 ac_get_image_intr_name("llvm.amdgcn.image.load",
3588 ctx->ac.v4f32, /* vdata */
3589 LLVMTypeOf(params[0]), /* coords */
3590 LLVMTypeOf(params[1]), /* rsrc */
3591 intrinsic_name, sizeof(intrinsic_name));
3592
3593 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3594 params, 7, AC_FUNC_ATTR_READONLY);
3595 }
3596 return ac_to_integer(&ctx->ac, res);
3597 }
3598
3599 static void visit_image_store(struct ac_nir_context *ctx,
3600 nir_intrinsic_instr *instr)
3601 {
3602 LLVMValueRef params[8];
3603 char intrinsic_name[64];
3604 const nir_variable *var = instr->variables[0]->var;
3605 const struct glsl_type *type = glsl_without_array(var->type);
3606 LLVMValueRef glc = ctx->ac.i1false;
3607 bool force_glc = ctx->ac.chip_class == SI;
3608 if (force_glc)
3609 glc = ctx->ac.i1true;
3610
3611 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3612 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3613 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3614 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3615 ctx->ac.i32_0, ""); /* vindex */
3616 params[3] = ctx->ac.i32_0; /* voffset */
3617 params[4] = glc; /* glc */
3618 params[5] = ctx->ac.i1false; /* slc */
3619 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3620 params, 6, 0);
3621 } else {
3622 bool is_da = glsl_sampler_type_is_array(type) ||
3623 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3624 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3625 LLVMValueRef slc = ctx->ac.i1false;
3626
3627 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3628 params[1] = get_image_coords(ctx, instr); /* coords */
3629 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3630 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3631 if (HAVE_LLVM <= 0x0309) {
3632 params[4] = ctx->ac.i1false; /* r128 */
3633 params[5] = da;
3634 params[6] = glc;
3635 params[7] = slc;
3636 } else {
3637 LLVMValueRef lwe = ctx->ac.i1false;
3638 params[4] = glc;
3639 params[5] = slc;
3640 params[6] = lwe;
3641 params[7] = da;
3642 }
3643
3644 ac_get_image_intr_name("llvm.amdgcn.image.store",
3645 LLVMTypeOf(params[0]), /* vdata */
3646 LLVMTypeOf(params[1]), /* coords */
3647 LLVMTypeOf(params[2]), /* rsrc */
3648 intrinsic_name, sizeof(intrinsic_name));
3649
3650 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3651 params, 8, 0);
3652 }
3653
3654 }
3655
3656 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3657 const nir_intrinsic_instr *instr)
3658 {
3659 LLVMValueRef params[7];
3660 int param_count = 0;
3661 const nir_variable *var = instr->variables[0]->var;
3662
3663 const char *atomic_name;
3664 char intrinsic_name[41];
3665 const struct glsl_type *type = glsl_without_array(var->type);
3666 MAYBE_UNUSED int length;
3667
3668 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3669
3670 switch (instr->intrinsic) {
3671 case nir_intrinsic_image_atomic_add:
3672 atomic_name = "add";
3673 break;
3674 case nir_intrinsic_image_atomic_min:
3675 atomic_name = is_unsigned ? "umin" : "smin";
3676 break;
3677 case nir_intrinsic_image_atomic_max:
3678 atomic_name = is_unsigned ? "umax" : "smax";
3679 break;
3680 case nir_intrinsic_image_atomic_and:
3681 atomic_name = "and";
3682 break;
3683 case nir_intrinsic_image_atomic_or:
3684 atomic_name = "or";
3685 break;
3686 case nir_intrinsic_image_atomic_xor:
3687 atomic_name = "xor";
3688 break;
3689 case nir_intrinsic_image_atomic_exchange:
3690 atomic_name = "swap";
3691 break;
3692 case nir_intrinsic_image_atomic_comp_swap:
3693 atomic_name = "cmpswap";
3694 break;
3695 default:
3696 abort();
3697 }
3698
3699 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3700 params[param_count++] = get_src(ctx, instr->src[3]);
3701 params[param_count++] = get_src(ctx, instr->src[2]);
3702
3703 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3704 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3705 NULL, true, true);
3706 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3707 ctx->ac.i32_0, ""); /* vindex */
3708 params[param_count++] = ctx->ac.i32_0; /* voffset */
3709 params[param_count++] = ctx->ac.i1false; /* slc */
3710
3711 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3712 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3713 } else {
3714 char coords_type[8];
3715
3716 bool da = glsl_sampler_type_is_array(type) ||
3717 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3718
3719 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3720 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3721 NULL, true, true);
3722 params[param_count++] = ctx->ac.i1false; /* r128 */
3723 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3724 params[param_count++] = ctx->ac.i1false; /* slc */
3725
3726 build_int_type_name(LLVMTypeOf(coords),
3727 coords_type, sizeof(coords_type));
3728
3729 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3730 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3731 }
3732
3733 assert(length < sizeof(intrinsic_name));
3734 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3735 }
3736
3737 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3738 const nir_intrinsic_instr *instr)
3739 {
3740 LLVMValueRef res;
3741 const nir_variable *var = instr->variables[0]->var;
3742 const struct glsl_type *type = instr->variables[0]->var->type;
3743 bool da = glsl_sampler_type_is_array(var->type) ||
3744 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3745 if(instr->variables[0]->deref.child)
3746 type = instr->variables[0]->deref.child->type;
3747
3748 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3749 return get_buffer_size(ctx,
3750 get_sampler_desc(ctx, instr->variables[0],
3751 AC_DESC_BUFFER, NULL, true, false), true);
3752
3753 struct ac_image_args args = { 0 };
3754
3755 args.da = da;
3756 args.dmask = 0xf;
3757 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3758 args.opcode = ac_image_get_resinfo;
3759 args.addr = ctx->ac.i32_0;
3760
3761 res = ac_build_image_opcode(&ctx->ac, &args);
3762
3763 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3764
3765 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3766 glsl_sampler_type_is_array(type)) {
3767 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3768 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3769 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3770 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3771 }
3772 if (ctx->ac.chip_class >= GFX9 &&
3773 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3774 glsl_sampler_type_is_array(type)) {
3775 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3776 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3777 ctx->ac.i32_1, "");
3778
3779 }
3780 return res;
3781 }
3782
3783 #define NOOP_WAITCNT 0xf7f
3784 #define LGKM_CNT 0x07f
3785 #define VM_CNT 0xf70
3786
3787 static void emit_membar(struct nir_to_llvm_context *ctx,
3788 const nir_intrinsic_instr *instr)
3789 {
3790 unsigned waitcnt = NOOP_WAITCNT;
3791
3792 switch (instr->intrinsic) {
3793 case nir_intrinsic_memory_barrier:
3794 case nir_intrinsic_group_memory_barrier:
3795 waitcnt &= VM_CNT & LGKM_CNT;
3796 break;
3797 case nir_intrinsic_memory_barrier_atomic_counter:
3798 case nir_intrinsic_memory_barrier_buffer:
3799 case nir_intrinsic_memory_barrier_image:
3800 waitcnt &= VM_CNT;
3801 break;
3802 case nir_intrinsic_memory_barrier_shared:
3803 waitcnt &= LGKM_CNT;
3804 break;
3805 default:
3806 break;
3807 }
3808 if (waitcnt != NOOP_WAITCNT)
3809 ac_build_waitcnt(&ctx->ac, waitcnt);
3810 }
3811
3812 static void emit_barrier(struct nir_to_llvm_context *ctx)
3813 {
3814 /* SI only (thanks to a hw bug workaround):
3815 * The real barrier instruction isn’t needed, because an entire patch
3816 * always fits into a single wave.
3817 */
3818 if (ctx->options->chip_class == SI &&
3819 ctx->stage == MESA_SHADER_TESS_CTRL) {
3820 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
3821 return;
3822 }
3823 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3824 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3825 }
3826
3827 static void emit_discard_if(struct ac_nir_context *ctx,
3828 const nir_intrinsic_instr *instr)
3829 {
3830 LLVMValueRef cond;
3831
3832 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3833 get_src(ctx, instr->src[0]),
3834 ctx->ac.i32_0, "");
3835 ac_build_kill_if_false(&ctx->ac, cond);
3836 }
3837
3838 static LLVMValueRef
3839 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3840 {
3841 LLVMValueRef result;
3842 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3843 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3844 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3845
3846 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3847 }
3848
3849 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3850 const nir_intrinsic_instr *instr)
3851 {
3852 LLVMValueRef ptr, result;
3853 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3854 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3855
3856 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3857 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3858 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3859 ptr, src, src1,
3860 LLVMAtomicOrderingSequentiallyConsistent,
3861 LLVMAtomicOrderingSequentiallyConsistent,
3862 false);
3863 } else {
3864 LLVMAtomicRMWBinOp op;
3865 switch (instr->intrinsic) {
3866 case nir_intrinsic_var_atomic_add:
3867 op = LLVMAtomicRMWBinOpAdd;
3868 break;
3869 case nir_intrinsic_var_atomic_umin:
3870 op = LLVMAtomicRMWBinOpUMin;
3871 break;
3872 case nir_intrinsic_var_atomic_umax:
3873 op = LLVMAtomicRMWBinOpUMax;
3874 break;
3875 case nir_intrinsic_var_atomic_imin:
3876 op = LLVMAtomicRMWBinOpMin;
3877 break;
3878 case nir_intrinsic_var_atomic_imax:
3879 op = LLVMAtomicRMWBinOpMax;
3880 break;
3881 case nir_intrinsic_var_atomic_and:
3882 op = LLVMAtomicRMWBinOpAnd;
3883 break;
3884 case nir_intrinsic_var_atomic_or:
3885 op = LLVMAtomicRMWBinOpOr;
3886 break;
3887 case nir_intrinsic_var_atomic_xor:
3888 op = LLVMAtomicRMWBinOpXor;
3889 break;
3890 case nir_intrinsic_var_atomic_exchange:
3891 op = LLVMAtomicRMWBinOpXchg;
3892 break;
3893 default:
3894 return NULL;
3895 }
3896
3897 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3898 LLVMAtomicOrderingSequentiallyConsistent,
3899 false);
3900 }
3901 return result;
3902 }
3903
3904 #define INTERP_CENTER 0
3905 #define INTERP_CENTROID 1
3906 #define INTERP_SAMPLE 2
3907
3908 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3909 enum glsl_interp_mode interp, unsigned location)
3910 {
3911 switch (interp) {
3912 case INTERP_MODE_FLAT:
3913 default:
3914 return NULL;
3915 case INTERP_MODE_SMOOTH:
3916 case INTERP_MODE_NONE:
3917 if (location == INTERP_CENTER)
3918 return ctx->persp_center;
3919 else if (location == INTERP_CENTROID)
3920 return ctx->persp_centroid;
3921 else if (location == INTERP_SAMPLE)
3922 return ctx->persp_sample;
3923 break;
3924 case INTERP_MODE_NOPERSPECTIVE:
3925 if (location == INTERP_CENTER)
3926 return ctx->linear_center;
3927 else if (location == INTERP_CENTROID)
3928 return ctx->linear_centroid;
3929 else if (location == INTERP_SAMPLE)
3930 return ctx->linear_sample;
3931 break;
3932 }
3933 return NULL;
3934 }
3935
3936 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3937 LLVMValueRef sample_id)
3938 {
3939 LLVMValueRef result;
3940 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3941
3942 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3943 const_array(ctx->ac.v2f32, 64), "");
3944
3945 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3946 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3947
3948 return result;
3949 }
3950
3951 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3952 {
3953 LLVMValueRef values[2];
3954
3955 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3956 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3957 return ac_build_gather_values(&ctx->ac, values, 2);
3958 }
3959
3960 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3961 const nir_intrinsic_instr *instr)
3962 {
3963 LLVMValueRef result[4];
3964 LLVMValueRef interp_param, attr_number;
3965 unsigned location;
3966 unsigned chan;
3967 LLVMValueRef src_c0 = NULL;
3968 LLVMValueRef src_c1 = NULL;
3969 LLVMValueRef src0 = NULL;
3970 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3971 switch (instr->intrinsic) {
3972 case nir_intrinsic_interp_var_at_centroid:
3973 location = INTERP_CENTROID;
3974 break;
3975 case nir_intrinsic_interp_var_at_sample:
3976 case nir_intrinsic_interp_var_at_offset:
3977 location = INTERP_CENTER;
3978 src0 = get_src(ctx->nir, instr->src[0]);
3979 break;
3980 default:
3981 break;
3982 }
3983
3984 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3985 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3986 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3987 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3988 LLVMValueRef sample_position;
3989 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
3990
3991 /* fetch sample ID */
3992 sample_position = load_sample_position(ctx, src0);
3993
3994 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
3995 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3996 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
3997 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3998 }
3999 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4000 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4001
4002 if (location == INTERP_CENTER) {
4003 LLVMValueRef ij_out[2];
4004 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4005
4006 /*
4007 * take the I then J parameters, and the DDX/Y for it, and
4008 * calculate the IJ inputs for the interpolator.
4009 * temp1 = ddx * offset/sample.x + I;
4010 * interp_param.I = ddy * offset/sample.y + temp1;
4011 * temp1 = ddx * offset/sample.x + J;
4012 * interp_param.J = ddy * offset/sample.y + temp1;
4013 */
4014 for (unsigned i = 0; i < 2; i++) {
4015 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4016 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4017 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4018 ddxy_out, ix_ll, "");
4019 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4020 ddxy_out, iy_ll, "");
4021 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4022 interp_param, ix_ll, "");
4023 LLVMValueRef temp1, temp2;
4024
4025 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4026 ctx->ac.f32, "");
4027
4028 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4029 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4030
4031 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4032 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4033
4034 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4035 temp2, ctx->ac.i32, "");
4036 }
4037 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4038
4039 }
4040
4041 for (chan = 0; chan < 4; chan++) {
4042 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4043
4044 if (interp_param) {
4045 interp_param = LLVMBuildBitCast(ctx->builder,
4046 interp_param, ctx->ac.v2f32, "");
4047 LLVMValueRef i = LLVMBuildExtractElement(
4048 ctx->builder, interp_param, ctx->ac.i32_0, "");
4049 LLVMValueRef j = LLVMBuildExtractElement(
4050 ctx->builder, interp_param, ctx->ac.i32_1, "");
4051
4052 result[chan] = ac_build_fs_interp(&ctx->ac,
4053 llvm_chan, attr_number,
4054 ctx->prim_mask, i, j);
4055 } else {
4056 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4057 LLVMConstInt(ctx->ac.i32, 2, false),
4058 llvm_chan, attr_number,
4059 ctx->prim_mask);
4060 }
4061 }
4062 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4063 instr->variables[0]->var->data.location_frac);
4064 }
4065
4066 static void
4067 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4068 {
4069 LLVMValueRef gs_next_vertex;
4070 LLVMValueRef can_emit;
4071 int idx;
4072 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4073
4074 /* Write vertex attribute values to GSVS ring */
4075 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4076 ctx->gs_next_vertex,
4077 "");
4078
4079 /* If this thread has already emitted the declared maximum number of
4080 * vertices, kill it: excessive vertex emissions are not supposed to
4081 * have any effect, and GS threads have no externally observable
4082 * effects other than emitting vertices.
4083 */
4084 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4085 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4086 ac_build_kill_if_false(&ctx->ac, can_emit);
4087
4088 /* loop num outputs */
4089 idx = 0;
4090 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4091 LLVMValueRef *out_ptr = &addrs[i * 4];
4092 int length = 4;
4093 int slot = idx;
4094 int slot_inc = 1;
4095
4096 if (!(ctx->output_mask & (1ull << i)))
4097 continue;
4098
4099 if (i == VARYING_SLOT_CLIP_DIST0) {
4100 /* pack clip and cull into a single set of slots */
4101 length = ctx->num_output_clips + ctx->num_output_culls;
4102 if (length > 4)
4103 slot_inc = 2;
4104 }
4105 for (unsigned j = 0; j < length; j++) {
4106 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4107 out_ptr[j], "");
4108 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4109 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4110 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4111
4112 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4113
4114 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4115 out_val, 1,
4116 voffset, ctx->gs2vs_offset, 0,
4117 1, 1, true, true);
4118 }
4119 idx += slot_inc;
4120 }
4121
4122 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4123 ctx->ac.i32_1, "");
4124 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4125
4126 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4127 }
4128
4129 static void
4130 visit_end_primitive(struct nir_to_llvm_context *ctx,
4131 const nir_intrinsic_instr *instr)
4132 {
4133 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4134 }
4135
4136 static LLVMValueRef
4137 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4138 const nir_intrinsic_instr *instr)
4139 {
4140 LLVMValueRef coord[4] = {
4141 ctx->tes_u,
4142 ctx->tes_v,
4143 ctx->ac.f32_0,
4144 ctx->ac.f32_0,
4145 };
4146
4147 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4148 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4149 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4150
4151 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4152 return LLVMBuildBitCast(ctx->builder, result,
4153 get_def_type(ctx->nir, &instr->dest.ssa), "");
4154 }
4155
4156 static void visit_intrinsic(struct ac_nir_context *ctx,
4157 nir_intrinsic_instr *instr)
4158 {
4159 LLVMValueRef result = NULL;
4160
4161 switch (instr->intrinsic) {
4162 case nir_intrinsic_load_work_group_id: {
4163 LLVMValueRef values[3];
4164
4165 for (int i = 0; i < 3; i++) {
4166 values[i] = ctx->nctx->workgroup_ids[i] ?
4167 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4168 }
4169
4170 result = ac_build_gather_values(&ctx->ac, values, 3);
4171 break;
4172 }
4173 case nir_intrinsic_load_base_vertex: {
4174 result = ctx->abi->base_vertex;
4175 break;
4176 }
4177 case nir_intrinsic_load_vertex_id_zero_base: {
4178 result = ctx->abi->vertex_id;
4179 break;
4180 }
4181 case nir_intrinsic_load_local_invocation_id: {
4182 result = ctx->nctx->local_invocation_ids;
4183 break;
4184 }
4185 case nir_intrinsic_load_base_instance:
4186 result = ctx->abi->start_instance;
4187 break;
4188 case nir_intrinsic_load_draw_id:
4189 result = ctx->abi->draw_id;
4190 break;
4191 case nir_intrinsic_load_view_index:
4192 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4193 break;
4194 case nir_intrinsic_load_invocation_id:
4195 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4196 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4197 else
4198 result = ctx->abi->gs_invocation_id;
4199 break;
4200 case nir_intrinsic_load_primitive_id:
4201 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4202 if (ctx->nctx)
4203 ctx->nctx->shader_info->gs.uses_prim_id = true;
4204 result = ctx->abi->gs_prim_id;
4205 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4206 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4207 result = ctx->nctx->tcs_patch_id;
4208 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4209 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4210 result = ctx->nctx->tes_patch_id;
4211 } else
4212 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4213 break;
4214 case nir_intrinsic_load_sample_id:
4215 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4216 break;
4217 case nir_intrinsic_load_sample_pos:
4218 result = load_sample_pos(ctx);
4219 break;
4220 case nir_intrinsic_load_sample_mask_in:
4221 result = ctx->abi->sample_coverage;
4222 break;
4223 case nir_intrinsic_load_frag_coord: {
4224 LLVMValueRef values[4] = {
4225 ctx->abi->frag_pos[0],
4226 ctx->abi->frag_pos[1],
4227 ctx->abi->frag_pos[2],
4228 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4229 };
4230 result = ac_build_gather_values(&ctx->ac, values, 4);
4231 break;
4232 }
4233 case nir_intrinsic_load_front_face:
4234 result = ctx->abi->front_face;
4235 break;
4236 case nir_intrinsic_load_instance_id:
4237 result = ctx->abi->instance_id;
4238 break;
4239 case nir_intrinsic_load_num_work_groups:
4240 result = ctx->nctx->num_work_groups;
4241 break;
4242 case nir_intrinsic_load_local_invocation_index:
4243 result = visit_load_local_invocation_index(ctx->nctx);
4244 break;
4245 case nir_intrinsic_load_push_constant:
4246 result = visit_load_push_constant(ctx->nctx, instr);
4247 break;
4248 case nir_intrinsic_vulkan_resource_index:
4249 result = visit_vulkan_resource_index(ctx->nctx, instr);
4250 break;
4251 case nir_intrinsic_vulkan_resource_reindex:
4252 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4253 break;
4254 case nir_intrinsic_store_ssbo:
4255 visit_store_ssbo(ctx, instr);
4256 break;
4257 case nir_intrinsic_load_ssbo:
4258 result = visit_load_buffer(ctx, instr);
4259 break;
4260 case nir_intrinsic_ssbo_atomic_add:
4261 case nir_intrinsic_ssbo_atomic_imin:
4262 case nir_intrinsic_ssbo_atomic_umin:
4263 case nir_intrinsic_ssbo_atomic_imax:
4264 case nir_intrinsic_ssbo_atomic_umax:
4265 case nir_intrinsic_ssbo_atomic_and:
4266 case nir_intrinsic_ssbo_atomic_or:
4267 case nir_intrinsic_ssbo_atomic_xor:
4268 case nir_intrinsic_ssbo_atomic_exchange:
4269 case nir_intrinsic_ssbo_atomic_comp_swap:
4270 result = visit_atomic_ssbo(ctx, instr);
4271 break;
4272 case nir_intrinsic_load_ubo:
4273 result = visit_load_ubo_buffer(ctx, instr);
4274 break;
4275 case nir_intrinsic_get_buffer_size:
4276 result = visit_get_buffer_size(ctx, instr);
4277 break;
4278 case nir_intrinsic_load_var:
4279 result = visit_load_var(ctx, instr);
4280 break;
4281 case nir_intrinsic_store_var:
4282 visit_store_var(ctx, instr);
4283 break;
4284 case nir_intrinsic_image_load:
4285 result = visit_image_load(ctx, instr);
4286 break;
4287 case nir_intrinsic_image_store:
4288 visit_image_store(ctx, instr);
4289 break;
4290 case nir_intrinsic_image_atomic_add:
4291 case nir_intrinsic_image_atomic_min:
4292 case nir_intrinsic_image_atomic_max:
4293 case nir_intrinsic_image_atomic_and:
4294 case nir_intrinsic_image_atomic_or:
4295 case nir_intrinsic_image_atomic_xor:
4296 case nir_intrinsic_image_atomic_exchange:
4297 case nir_intrinsic_image_atomic_comp_swap:
4298 result = visit_image_atomic(ctx, instr);
4299 break;
4300 case nir_intrinsic_image_size:
4301 result = visit_image_size(ctx, instr);
4302 break;
4303 case nir_intrinsic_discard:
4304 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4305 LLVMVoidTypeInContext(ctx->ac.context),
4306 NULL, 0, AC_FUNC_ATTR_LEGACY);
4307 break;
4308 case nir_intrinsic_discard_if:
4309 emit_discard_if(ctx, instr);
4310 break;
4311 case nir_intrinsic_memory_barrier:
4312 case nir_intrinsic_group_memory_barrier:
4313 case nir_intrinsic_memory_barrier_atomic_counter:
4314 case nir_intrinsic_memory_barrier_buffer:
4315 case nir_intrinsic_memory_barrier_image:
4316 case nir_intrinsic_memory_barrier_shared:
4317 emit_membar(ctx->nctx, instr);
4318 break;
4319 case nir_intrinsic_barrier:
4320 emit_barrier(ctx->nctx);
4321 break;
4322 case nir_intrinsic_var_atomic_add:
4323 case nir_intrinsic_var_atomic_imin:
4324 case nir_intrinsic_var_atomic_umin:
4325 case nir_intrinsic_var_atomic_imax:
4326 case nir_intrinsic_var_atomic_umax:
4327 case nir_intrinsic_var_atomic_and:
4328 case nir_intrinsic_var_atomic_or:
4329 case nir_intrinsic_var_atomic_xor:
4330 case nir_intrinsic_var_atomic_exchange:
4331 case nir_intrinsic_var_atomic_comp_swap:
4332 result = visit_var_atomic(ctx->nctx, instr);
4333 break;
4334 case nir_intrinsic_interp_var_at_centroid:
4335 case nir_intrinsic_interp_var_at_sample:
4336 case nir_intrinsic_interp_var_at_offset:
4337 result = visit_interp(ctx->nctx, instr);
4338 break;
4339 case nir_intrinsic_emit_vertex:
4340 assert(instr->const_index[0] == 0);
4341 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4342 break;
4343 case nir_intrinsic_end_primitive:
4344 visit_end_primitive(ctx->nctx, instr);
4345 break;
4346 case nir_intrinsic_load_tess_coord:
4347 result = visit_load_tess_coord(ctx->nctx, instr);
4348 break;
4349 case nir_intrinsic_load_patch_vertices_in:
4350 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4351 break;
4352 default:
4353 fprintf(stderr, "Unknown intrinsic: ");
4354 nir_print_instr(&instr->instr, stderr);
4355 fprintf(stderr, "\n");
4356 break;
4357 }
4358 if (result) {
4359 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4360 }
4361 }
4362
4363 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4364 LLVMValueRef buffer_ptr, bool write)
4365 {
4366 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4367
4368 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4369 ctx->shader_info->fs.writes_memory = true;
4370
4371 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4372 }
4373
4374 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4375 {
4376 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4377
4378 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4379 }
4380
4381 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4382 unsigned descriptor_set,
4383 unsigned base_index,
4384 unsigned constant_index,
4385 LLVMValueRef index,
4386 enum ac_descriptor_type desc_type,
4387 bool image, bool write)
4388 {
4389 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4390 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4391 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4392 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4393 unsigned offset = binding->offset;
4394 unsigned stride = binding->size;
4395 unsigned type_size;
4396 LLVMBuilderRef builder = ctx->builder;
4397 LLVMTypeRef type;
4398
4399 assert(base_index < layout->binding_count);
4400
4401 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4402 ctx->shader_info->fs.writes_memory = true;
4403
4404 switch (desc_type) {
4405 case AC_DESC_IMAGE:
4406 type = ctx->ac.v8i32;
4407 type_size = 32;
4408 break;
4409 case AC_DESC_FMASK:
4410 type = ctx->ac.v8i32;
4411 offset += 32;
4412 type_size = 32;
4413 break;
4414 case AC_DESC_SAMPLER:
4415 type = ctx->ac.v4i32;
4416 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4417 offset += 64;
4418
4419 type_size = 16;
4420 break;
4421 case AC_DESC_BUFFER:
4422 type = ctx->ac.v4i32;
4423 type_size = 16;
4424 break;
4425 default:
4426 unreachable("invalid desc_type\n");
4427 }
4428
4429 offset += constant_index * stride;
4430
4431 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4432 (!index || binding->immutable_samplers_equal)) {
4433 if (binding->immutable_samplers_equal)
4434 constant_index = 0;
4435
4436 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4437
4438 LLVMValueRef constants[] = {
4439 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4440 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4441 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4442 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4443 };
4444 return ac_build_gather_values(&ctx->ac, constants, 4);
4445 }
4446
4447 assert(stride % type_size == 0);
4448
4449 if (!index)
4450 index = ctx->ac.i32_0;
4451
4452 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4453
4454 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4455 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4456
4457 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4458 }
4459
4460 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4461 const nir_deref_var *deref,
4462 enum ac_descriptor_type desc_type,
4463 const nir_tex_instr *tex_instr,
4464 bool image, bool write)
4465 {
4466 LLVMValueRef index = NULL;
4467 unsigned constant_index = 0;
4468 unsigned descriptor_set;
4469 unsigned base_index;
4470
4471 if (!deref) {
4472 assert(tex_instr && !image);
4473 descriptor_set = 0;
4474 base_index = tex_instr->sampler_index;
4475 } else {
4476 const nir_deref *tail = &deref->deref;
4477 while (tail->child) {
4478 const nir_deref_array *child = nir_deref_as_array(tail->child);
4479 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4480
4481 if (!array_size)
4482 array_size = 1;
4483
4484 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4485
4486 if (child->deref_array_type == nir_deref_array_type_indirect) {
4487 LLVMValueRef indirect = get_src(ctx, child->indirect);
4488
4489 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4490 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4491
4492 if (!index)
4493 index = indirect;
4494 else
4495 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4496 }
4497
4498 constant_index += child->base_offset * array_size;
4499
4500 tail = &child->deref;
4501 }
4502 descriptor_set = deref->var->data.descriptor_set;
4503 base_index = deref->var->data.binding;
4504 }
4505
4506 return ctx->abi->load_sampler_desc(ctx->abi,
4507 descriptor_set,
4508 base_index,
4509 constant_index, index,
4510 desc_type, image, write);
4511 }
4512
4513 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4514 struct ac_image_args *args,
4515 const nir_tex_instr *instr,
4516 nir_texop op,
4517 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4518 LLVMValueRef *param, unsigned count,
4519 unsigned dmask)
4520 {
4521 unsigned is_rect = 0;
4522 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4523
4524 if (op == nir_texop_lod)
4525 da = false;
4526 /* Pad to power of two vector */
4527 while (count < util_next_power_of_two(count))
4528 param[count++] = LLVMGetUndef(ctx->i32);
4529
4530 if (count > 1)
4531 args->addr = ac_build_gather_values(ctx, param, count);
4532 else
4533 args->addr = param[0];
4534
4535 args->resource = res_ptr;
4536 args->sampler = samp_ptr;
4537
4538 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4539 args->addr = param[0];
4540 return;
4541 }
4542
4543 args->dmask = dmask;
4544 args->unorm = is_rect;
4545 args->da = da;
4546 }
4547
4548 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4549 *
4550 * SI-CI:
4551 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4552 * filtering manually. The driver sets img7 to a mask clearing
4553 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4554 * s_and_b32 samp0, samp0, img7
4555 *
4556 * VI:
4557 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4558 */
4559 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4560 LLVMValueRef res, LLVMValueRef samp)
4561 {
4562 LLVMBuilderRef builder = ctx->ac.builder;
4563 LLVMValueRef img7, samp0;
4564
4565 if (ctx->ac.chip_class >= VI)
4566 return samp;
4567
4568 img7 = LLVMBuildExtractElement(builder, res,
4569 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4570 samp0 = LLVMBuildExtractElement(builder, samp,
4571 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4572 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4573 return LLVMBuildInsertElement(builder, samp, samp0,
4574 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4575 }
4576
4577 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4578 nir_tex_instr *instr,
4579 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4580 LLVMValueRef *fmask_ptr)
4581 {
4582 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4583 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4584 else
4585 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4586 if (samp_ptr) {
4587 if (instr->sampler)
4588 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4589 else
4590 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4591 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4592 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4593 }
4594 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4595 instr->op == nir_texop_samples_identical))
4596 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4597 }
4598
4599 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4600 LLVMValueRef coord)
4601 {
4602 coord = ac_to_float(ctx, coord);
4603 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4604 coord = ac_to_integer(ctx, coord);
4605 return coord;
4606 }
4607
4608 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4609 {
4610 LLVMValueRef result = NULL;
4611 struct ac_image_args args = { 0 };
4612 unsigned dmask = 0xf;
4613 LLVMValueRef address[16];
4614 LLVMValueRef coords[5];
4615 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4616 LLVMValueRef bias = NULL, offsets = NULL;
4617 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4618 LLVMValueRef ddx = NULL, ddy = NULL;
4619 LLVMValueRef derivs[6];
4620 unsigned chan, count = 0;
4621 unsigned const_src = 0, num_deriv_comp = 0;
4622 bool lod_is_zero = false;
4623
4624 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4625
4626 for (unsigned i = 0; i < instr->num_srcs; i++) {
4627 switch (instr->src[i].src_type) {
4628 case nir_tex_src_coord:
4629 coord = get_src(ctx, instr->src[i].src);
4630 break;
4631 case nir_tex_src_projector:
4632 break;
4633 case nir_tex_src_comparator:
4634 comparator = get_src(ctx, instr->src[i].src);
4635 break;
4636 case nir_tex_src_offset:
4637 offsets = get_src(ctx, instr->src[i].src);
4638 const_src = i;
4639 break;
4640 case nir_tex_src_bias:
4641 bias = get_src(ctx, instr->src[i].src);
4642 break;
4643 case nir_tex_src_lod: {
4644 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4645
4646 if (val && val->i32[0] == 0)
4647 lod_is_zero = true;
4648 lod = get_src(ctx, instr->src[i].src);
4649 break;
4650 }
4651 case nir_tex_src_ms_index:
4652 sample_index = get_src(ctx, instr->src[i].src);
4653 break;
4654 case nir_tex_src_ms_mcs:
4655 break;
4656 case nir_tex_src_ddx:
4657 ddx = get_src(ctx, instr->src[i].src);
4658 num_deriv_comp = instr->src[i].src.ssa->num_components;
4659 break;
4660 case nir_tex_src_ddy:
4661 ddy = get_src(ctx, instr->src[i].src);
4662 break;
4663 case nir_tex_src_texture_offset:
4664 case nir_tex_src_sampler_offset:
4665 case nir_tex_src_plane:
4666 default:
4667 break;
4668 }
4669 }
4670
4671 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4672 result = get_buffer_size(ctx, res_ptr, true);
4673 goto write_result;
4674 }
4675
4676 if (instr->op == nir_texop_texture_samples) {
4677 LLVMValueRef res, samples, is_msaa;
4678 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4679 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4680 LLVMConstInt(ctx->ac.i32, 3, false), "");
4681 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4682 LLVMConstInt(ctx->ac.i32, 28, false), "");
4683 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4684 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4685 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4686 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4687
4688 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4689 LLVMConstInt(ctx->ac.i32, 16, false), "");
4690 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4691 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4692 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4693 samples, "");
4694 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4695 ctx->ac.i32_1, "");
4696 result = samples;
4697 goto write_result;
4698 }
4699
4700 if (coord)
4701 for (chan = 0; chan < instr->coord_components; chan++)
4702 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4703
4704 if (offsets && instr->op != nir_texop_txf) {
4705 LLVMValueRef offset[3], pack;
4706 for (chan = 0; chan < 3; ++chan)
4707 offset[chan] = ctx->ac.i32_0;
4708
4709 args.offset = true;
4710 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4711 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4712 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4713 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4714 if (chan)
4715 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4716 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4717 }
4718 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4719 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4720 address[count++] = pack;
4721
4722 }
4723 /* pack LOD bias value */
4724 if (instr->op == nir_texop_txb && bias) {
4725 address[count++] = bias;
4726 }
4727
4728 /* Pack depth comparison value */
4729 if (instr->is_shadow && comparator) {
4730 LLVMValueRef z = ac_to_float(&ctx->ac,
4731 llvm_extract_elem(&ctx->ac, comparator, 0));
4732
4733 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4734 * so the depth comparison value isn't clamped for Z16 and
4735 * Z24 anymore. Do it manually here.
4736 *
4737 * It's unnecessary if the original texture format was
4738 * Z32_FLOAT, but we don't know that here.
4739 */
4740 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4741 z = ac_build_clamp(&ctx->ac, z);
4742
4743 address[count++] = z;
4744 }
4745
4746 /* pack derivatives */
4747 if (ddx || ddy) {
4748 int num_src_deriv_channels, num_dest_deriv_channels;
4749 switch (instr->sampler_dim) {
4750 case GLSL_SAMPLER_DIM_3D:
4751 case GLSL_SAMPLER_DIM_CUBE:
4752 num_deriv_comp = 3;
4753 num_src_deriv_channels = 3;
4754 num_dest_deriv_channels = 3;
4755 break;
4756 case GLSL_SAMPLER_DIM_2D:
4757 default:
4758 num_src_deriv_channels = 2;
4759 num_dest_deriv_channels = 2;
4760 num_deriv_comp = 2;
4761 break;
4762 case GLSL_SAMPLER_DIM_1D:
4763 num_src_deriv_channels = 1;
4764 if (ctx->ac.chip_class >= GFX9) {
4765 num_dest_deriv_channels = 2;
4766 num_deriv_comp = 2;
4767 } else {
4768 num_dest_deriv_channels = 1;
4769 num_deriv_comp = 1;
4770 }
4771 break;
4772 }
4773
4774 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4775 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4776 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4777 }
4778 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4779 derivs[i] = ctx->ac.f32_0;
4780 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4781 }
4782 }
4783
4784 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4785 for (chan = 0; chan < instr->coord_components; chan++)
4786 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4787 if (instr->coord_components == 3)
4788 coords[3] = LLVMGetUndef(ctx->ac.f32);
4789 ac_prepare_cube_coords(&ctx->ac,
4790 instr->op == nir_texop_txd, instr->is_array,
4791 instr->op == nir_texop_lod, coords, derivs);
4792 if (num_deriv_comp)
4793 num_deriv_comp--;
4794 }
4795
4796 if (ddx || ddy) {
4797 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4798 address[count++] = derivs[i];
4799 }
4800
4801 /* Pack texture coordinates */
4802 if (coord) {
4803 address[count++] = coords[0];
4804 if (instr->coord_components > 1) {
4805 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4806 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4807 }
4808 address[count++] = coords[1];
4809 }
4810 if (instr->coord_components > 2) {
4811 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4812 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4813 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4814 instr->op != nir_texop_txf) {
4815 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4816 }
4817 address[count++] = coords[2];
4818 }
4819
4820 if (ctx->ac.chip_class >= GFX9) {
4821 LLVMValueRef filler;
4822 if (instr->op == nir_texop_txf)
4823 filler = ctx->ac.i32_0;
4824 else
4825 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4826
4827 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4828 /* No nir_texop_lod, because it does not take a slice
4829 * even with array textures. */
4830 if (instr->is_array && instr->op != nir_texop_lod ) {
4831 address[count] = address[count - 1];
4832 address[count - 1] = filler;
4833 count++;
4834 } else
4835 address[count++] = filler;
4836 }
4837 }
4838 }
4839
4840 /* Pack LOD */
4841 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4842 instr->op == nir_texop_txf)) {
4843 address[count++] = lod;
4844 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4845 address[count++] = sample_index;
4846 } else if(instr->op == nir_texop_txs) {
4847 count = 0;
4848 if (lod)
4849 address[count++] = lod;
4850 else
4851 address[count++] = ctx->ac.i32_0;
4852 }
4853
4854 for (chan = 0; chan < count; chan++) {
4855 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4856 address[chan], ctx->ac.i32, "");
4857 }
4858
4859 if (instr->op == nir_texop_samples_identical) {
4860 LLVMValueRef txf_address[4];
4861 struct ac_image_args txf_args = { 0 };
4862 unsigned txf_count = count;
4863 memcpy(txf_address, address, sizeof(txf_address));
4864
4865 if (!instr->is_array)
4866 txf_address[2] = ctx->ac.i32_0;
4867 txf_address[3] = ctx->ac.i32_0;
4868
4869 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4870 fmask_ptr, NULL,
4871 txf_address, txf_count, 0xf);
4872
4873 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4874
4875 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4876 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4877 goto write_result;
4878 }
4879
4880 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4881 instr->op != nir_texop_txs) {
4882 unsigned sample_chan = instr->is_array ? 3 : 2;
4883 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4884 address[0],
4885 address[1],
4886 instr->is_array ? address[2] : NULL,
4887 address[sample_chan],
4888 fmask_ptr);
4889 }
4890
4891 if (offsets && instr->op == nir_texop_txf) {
4892 nir_const_value *const_offset =
4893 nir_src_as_const_value(instr->src[const_src].src);
4894 int num_offsets = instr->src[const_src].src.ssa->num_components;
4895 assert(const_offset);
4896 num_offsets = MIN2(num_offsets, instr->coord_components);
4897 if (num_offsets > 2)
4898 address[2] = LLVMBuildAdd(ctx->ac.builder,
4899 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4900 if (num_offsets > 1)
4901 address[1] = LLVMBuildAdd(ctx->ac.builder,
4902 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4903 address[0] = LLVMBuildAdd(ctx->ac.builder,
4904 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4905
4906 }
4907
4908 /* TODO TG4 support */
4909 if (instr->op == nir_texop_tg4) {
4910 if (instr->is_shadow)
4911 dmask = 1;
4912 else
4913 dmask = 1 << instr->component;
4914 }
4915 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4916 res_ptr, samp_ptr, address, count, dmask);
4917
4918 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4919
4920 if (instr->op == nir_texop_query_levels)
4921 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4922 else if (instr->is_shadow && instr->is_new_style_shadow &&
4923 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4924 instr->op != nir_texop_tg4)
4925 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4926 else if (instr->op == nir_texop_txs &&
4927 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4928 instr->is_array) {
4929 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4930 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4931 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4932 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4933 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4934 } else if (ctx->ac.chip_class >= GFX9 &&
4935 instr->op == nir_texop_txs &&
4936 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4937 instr->is_array) {
4938 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4939 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4940 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4941 ctx->ac.i32_1, "");
4942 } else if (instr->dest.ssa.num_components != 4)
4943 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4944
4945 write_result:
4946 if (result) {
4947 assert(instr->dest.is_ssa);
4948 result = ac_to_integer(&ctx->ac, result);
4949 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4950 }
4951 }
4952
4953
4954 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4955 {
4956 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4957 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4958
4959 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4960 _mesa_hash_table_insert(ctx->phis, instr, result);
4961 }
4962
4963 static void visit_post_phi(struct ac_nir_context *ctx,
4964 nir_phi_instr *instr,
4965 LLVMValueRef llvm_phi)
4966 {
4967 nir_foreach_phi_src(src, instr) {
4968 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4969 LLVMValueRef llvm_src = get_src(ctx, src->src);
4970
4971 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4972 }
4973 }
4974
4975 static void phi_post_pass(struct ac_nir_context *ctx)
4976 {
4977 struct hash_entry *entry;
4978 hash_table_foreach(ctx->phis, entry) {
4979 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4980 (LLVMValueRef)entry->data);
4981 }
4982 }
4983
4984
4985 static void visit_ssa_undef(struct ac_nir_context *ctx,
4986 const nir_ssa_undef_instr *instr)
4987 {
4988 unsigned num_components = instr->def.num_components;
4989 LLVMValueRef undef;
4990
4991 if (num_components == 1)
4992 undef = LLVMGetUndef(ctx->ac.i32);
4993 else {
4994 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4995 }
4996 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4997 }
4998
4999 static void visit_jump(struct ac_nir_context *ctx,
5000 const nir_jump_instr *instr)
5001 {
5002 switch (instr->type) {
5003 case nir_jump_break:
5004 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5005 LLVMClearInsertionPosition(ctx->ac.builder);
5006 break;
5007 case nir_jump_continue:
5008 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5009 LLVMClearInsertionPosition(ctx->ac.builder);
5010 break;
5011 default:
5012 fprintf(stderr, "Unknown NIR jump instr: ");
5013 nir_print_instr(&instr->instr, stderr);
5014 fprintf(stderr, "\n");
5015 abort();
5016 }
5017 }
5018
5019 static void visit_cf_list(struct ac_nir_context *ctx,
5020 struct exec_list *list);
5021
5022 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5023 {
5024 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5025 nir_foreach_instr(instr, block)
5026 {
5027 switch (instr->type) {
5028 case nir_instr_type_alu:
5029 visit_alu(ctx, nir_instr_as_alu(instr));
5030 break;
5031 case nir_instr_type_load_const:
5032 visit_load_const(ctx, nir_instr_as_load_const(instr));
5033 break;
5034 case nir_instr_type_intrinsic:
5035 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5036 break;
5037 case nir_instr_type_tex:
5038 visit_tex(ctx, nir_instr_as_tex(instr));
5039 break;
5040 case nir_instr_type_phi:
5041 visit_phi(ctx, nir_instr_as_phi(instr));
5042 break;
5043 case nir_instr_type_ssa_undef:
5044 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5045 break;
5046 case nir_instr_type_jump:
5047 visit_jump(ctx, nir_instr_as_jump(instr));
5048 break;
5049 default:
5050 fprintf(stderr, "Unknown NIR instr type: ");
5051 nir_print_instr(instr, stderr);
5052 fprintf(stderr, "\n");
5053 abort();
5054 }
5055 }
5056
5057 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5058 }
5059
5060 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5061 {
5062 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5063
5064 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5065 LLVMBasicBlockRef merge_block =
5066 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5067 LLVMBasicBlockRef if_block =
5068 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5069 LLVMBasicBlockRef else_block = merge_block;
5070 if (!exec_list_is_empty(&if_stmt->else_list))
5071 else_block = LLVMAppendBasicBlockInContext(
5072 ctx->ac.context, fn, "");
5073
5074 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5075 ctx->ac.i32_0, "");
5076 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5077
5078 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5079 visit_cf_list(ctx, &if_stmt->then_list);
5080 if (LLVMGetInsertBlock(ctx->ac.builder))
5081 LLVMBuildBr(ctx->ac.builder, merge_block);
5082
5083 if (!exec_list_is_empty(&if_stmt->else_list)) {
5084 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5085 visit_cf_list(ctx, &if_stmt->else_list);
5086 if (LLVMGetInsertBlock(ctx->ac.builder))
5087 LLVMBuildBr(ctx->ac.builder, merge_block);
5088 }
5089
5090 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5091 }
5092
5093 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5094 {
5095 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5096 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5097 LLVMBasicBlockRef break_parent = ctx->break_block;
5098
5099 ctx->continue_block =
5100 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5101 ctx->break_block =
5102 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5103
5104 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5105 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5106 visit_cf_list(ctx, &loop->body);
5107
5108 if (LLVMGetInsertBlock(ctx->ac.builder))
5109 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5110 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5111
5112 ctx->continue_block = continue_parent;
5113 ctx->break_block = break_parent;
5114 }
5115
5116 static void visit_cf_list(struct ac_nir_context *ctx,
5117 struct exec_list *list)
5118 {
5119 foreach_list_typed(nir_cf_node, node, node, list)
5120 {
5121 switch (node->type) {
5122 case nir_cf_node_block:
5123 visit_block(ctx, nir_cf_node_as_block(node));
5124 break;
5125
5126 case nir_cf_node_if:
5127 visit_if(ctx, nir_cf_node_as_if(node));
5128 break;
5129
5130 case nir_cf_node_loop:
5131 visit_loop(ctx, nir_cf_node_as_loop(node));
5132 break;
5133
5134 default:
5135 assert(0);
5136 }
5137 }
5138 }
5139
5140 static void
5141 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5142 struct nir_variable *variable)
5143 {
5144 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5145 LLVMValueRef t_offset;
5146 LLVMValueRef t_list;
5147 LLVMValueRef input;
5148 LLVMValueRef buffer_index;
5149 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5150 int idx = variable->data.location;
5151 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5152
5153 variable->data.driver_location = idx * 4;
5154
5155 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5156 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5157 ctx->abi.start_instance, "");
5158 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5159 ctx->shader_info->vs.vgpr_comp_cnt);
5160 } else
5161 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5162 ctx->abi.base_vertex, "");
5163
5164 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5165 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5166
5167 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5168
5169 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5170 buffer_index,
5171 ctx->ac.i32_0,
5172 true);
5173
5174 for (unsigned chan = 0; chan < 4; chan++) {
5175 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5176 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5177 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5178 input, llvm_chan, ""));
5179 }
5180 }
5181 }
5182
5183 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5184 unsigned attr,
5185 LLVMValueRef interp_param,
5186 LLVMValueRef prim_mask,
5187 LLVMValueRef result[4])
5188 {
5189 LLVMValueRef attr_number;
5190 unsigned chan;
5191 LLVMValueRef i, j;
5192 bool interp = interp_param != NULL;
5193
5194 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5195
5196 /* fs.constant returns the param from the middle vertex, so it's not
5197 * really useful for flat shading. It's meant to be used for custom
5198 * interpolation (but the intrinsic can't fetch from the other two
5199 * vertices).
5200 *
5201 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5202 * to do the right thing. The only reason we use fs.constant is that
5203 * fs.interp cannot be used on integers, because they can be equal
5204 * to NaN.
5205 */
5206 if (interp) {
5207 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5208 ctx->ac.v2f32, "");
5209
5210 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5211 ctx->ac.i32_0, "");
5212 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5213 ctx->ac.i32_1, "");
5214 }
5215
5216 for (chan = 0; chan < 4; chan++) {
5217 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5218
5219 if (interp) {
5220 result[chan] = ac_build_fs_interp(&ctx->ac,
5221 llvm_chan,
5222 attr_number,
5223 prim_mask, i, j);
5224 } else {
5225 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5226 LLVMConstInt(ctx->ac.i32, 2, false),
5227 llvm_chan,
5228 attr_number,
5229 prim_mask);
5230 }
5231 }
5232 }
5233
5234 static void
5235 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5236 struct nir_variable *variable)
5237 {
5238 int idx = variable->data.location;
5239 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5240 LLVMValueRef interp;
5241
5242 variable->data.driver_location = idx * 4;
5243 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5244
5245 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5246 unsigned interp_type;
5247 if (variable->data.sample) {
5248 interp_type = INTERP_SAMPLE;
5249 ctx->shader_info->info.ps.force_persample = true;
5250 } else if (variable->data.centroid)
5251 interp_type = INTERP_CENTROID;
5252 else
5253 interp_type = INTERP_CENTER;
5254
5255 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5256 } else
5257 interp = NULL;
5258
5259 for (unsigned i = 0; i < attrib_count; ++i)
5260 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5261
5262 }
5263
5264 static void
5265 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5266 struct nir_shader *nir) {
5267 nir_foreach_variable(variable, &nir->inputs)
5268 handle_vs_input_decl(ctx, variable);
5269 }
5270
5271 static void
5272 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5273 struct nir_shader *nir)
5274 {
5275 if (!ctx->options->key.fs.multisample)
5276 return;
5277
5278 bool uses_center = false;
5279 bool uses_centroid = false;
5280 nir_foreach_variable(variable, &nir->inputs) {
5281 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5282 variable->data.sample)
5283 continue;
5284
5285 if (variable->data.centroid)
5286 uses_centroid = true;
5287 else
5288 uses_center = true;
5289 }
5290
5291 if (uses_center && uses_centroid) {
5292 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5293 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5294 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5295 }
5296 }
5297
5298 static void
5299 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5300 struct nir_shader *nir)
5301 {
5302 prepare_interp_optimize(ctx, nir);
5303
5304 nir_foreach_variable(variable, &nir->inputs)
5305 handle_fs_input_decl(ctx, variable);
5306
5307 unsigned index = 0;
5308
5309 if (ctx->shader_info->info.ps.uses_input_attachments ||
5310 ctx->shader_info->info.needs_multiview_view_index)
5311 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5312
5313 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5314 LLVMValueRef interp_param;
5315 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5316
5317 if (!(ctx->input_mask & (1ull << i)))
5318 continue;
5319
5320 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5321 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5322 interp_param = *inputs;
5323 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5324 inputs);
5325
5326 if (!interp_param)
5327 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5328 ++index;
5329 } else if (i == VARYING_SLOT_POS) {
5330 for(int i = 0; i < 3; ++i)
5331 inputs[i] = ctx->abi.frag_pos[i];
5332
5333 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5334 ctx->abi.frag_pos[3]);
5335 }
5336 }
5337 ctx->shader_info->fs.num_interp = index;
5338 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5339 ctx->shader_info->fs.has_pcoord = true;
5340 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5341 ctx->shader_info->fs.prim_id_input = true;
5342 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5343 ctx->shader_info->fs.layer_input = true;
5344 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5345
5346 if (ctx->shader_info->info.needs_multiview_view_index)
5347 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5348 }
5349
5350 static LLVMValueRef
5351 ac_build_alloca(struct ac_llvm_context *ac,
5352 LLVMTypeRef type,
5353 const char *name)
5354 {
5355 LLVMBuilderRef builder = ac->builder;
5356 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5357 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5358 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5359 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5360 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5361 LLVMValueRef res;
5362
5363 if (first_instr) {
5364 LLVMPositionBuilderBefore(first_builder, first_instr);
5365 } else {
5366 LLVMPositionBuilderAtEnd(first_builder, first_block);
5367 }
5368
5369 res = LLVMBuildAlloca(first_builder, type, name);
5370 LLVMBuildStore(builder, LLVMConstNull(type), res);
5371
5372 LLVMDisposeBuilder(first_builder);
5373
5374 return res;
5375 }
5376
5377 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5378 LLVMTypeRef type,
5379 const char *name)
5380 {
5381 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5382 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5383 return ptr;
5384 }
5385
5386 static void
5387 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5388 struct nir_variable *variable,
5389 struct nir_shader *shader,
5390 gl_shader_stage stage)
5391 {
5392 int idx = variable->data.location + variable->data.index;
5393 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5394 uint64_t mask_attribs;
5395
5396 variable->data.driver_location = idx * 4;
5397
5398 /* tess ctrl has it's own load/store paths for outputs */
5399 if (stage == MESA_SHADER_TESS_CTRL)
5400 return;
5401
5402 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5403 if (stage == MESA_SHADER_VERTEX ||
5404 stage == MESA_SHADER_TESS_EVAL ||
5405 stage == MESA_SHADER_GEOMETRY) {
5406 if (idx == VARYING_SLOT_CLIP_DIST0) {
5407 int length = shader->info.clip_distance_array_size +
5408 shader->info.cull_distance_array_size;
5409 if (stage == MESA_SHADER_VERTEX) {
5410 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5411 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5412 }
5413 if (stage == MESA_SHADER_TESS_EVAL) {
5414 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5415 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5416 }
5417
5418 if (length > 4)
5419 attrib_count = 2;
5420 else
5421 attrib_count = 1;
5422 mask_attribs = 1ull << idx;
5423 }
5424 }
5425
5426 ctx->output_mask |= mask_attribs;
5427 }
5428
5429 static void
5430 handle_shader_output_decl(struct ac_nir_context *ctx,
5431 struct nir_shader *nir,
5432 struct nir_variable *variable)
5433 {
5434 unsigned output_loc = variable->data.driver_location / 4;
5435 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5436
5437 /* tess ctrl has it's own load/store paths for outputs */
5438 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5439 return;
5440
5441 if (ctx->stage == MESA_SHADER_VERTEX ||
5442 ctx->stage == MESA_SHADER_TESS_EVAL ||
5443 ctx->stage == MESA_SHADER_GEOMETRY) {
5444 int idx = variable->data.location + variable->data.index;
5445 if (idx == VARYING_SLOT_CLIP_DIST0) {
5446 int length = nir->info.clip_distance_array_size +
5447 nir->info.cull_distance_array_size;
5448
5449 if (length > 4)
5450 attrib_count = 2;
5451 else
5452 attrib_count = 1;
5453 }
5454 }
5455
5456 for (unsigned i = 0; i < attrib_count; ++i) {
5457 for (unsigned chan = 0; chan < 4; chan++) {
5458 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5459 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5460 }
5461 }
5462 }
5463
5464 static LLVMTypeRef
5465 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5466 enum glsl_base_type type)
5467 {
5468 switch (type) {
5469 case GLSL_TYPE_INT:
5470 case GLSL_TYPE_UINT:
5471 case GLSL_TYPE_BOOL:
5472 case GLSL_TYPE_SUBROUTINE:
5473 return ctx->ac.i32;
5474 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5475 return ctx->ac.f32;
5476 case GLSL_TYPE_INT64:
5477 case GLSL_TYPE_UINT64:
5478 return ctx->ac.i64;
5479 case GLSL_TYPE_DOUBLE:
5480 return ctx->ac.f64;
5481 default:
5482 unreachable("unknown GLSL type");
5483 }
5484 }
5485
5486 static LLVMTypeRef
5487 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5488 const struct glsl_type *type)
5489 {
5490 if (glsl_type_is_scalar(type)) {
5491 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5492 }
5493
5494 if (glsl_type_is_vector(type)) {
5495 return LLVMVectorType(
5496 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5497 glsl_get_vector_elements(type));
5498 }
5499
5500 if (glsl_type_is_matrix(type)) {
5501 return LLVMArrayType(
5502 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5503 glsl_get_matrix_columns(type));
5504 }
5505
5506 if (glsl_type_is_array(type)) {
5507 return LLVMArrayType(
5508 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5509 glsl_get_length(type));
5510 }
5511
5512 assert(glsl_type_is_struct(type));
5513
5514 LLVMTypeRef member_types[glsl_get_length(type)];
5515
5516 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5517 member_types[i] =
5518 glsl_to_llvm_type(ctx,
5519 glsl_get_struct_field(type, i));
5520 }
5521
5522 return LLVMStructTypeInContext(ctx->context, member_types,
5523 glsl_get_length(type), false);
5524 }
5525
5526 static void
5527 setup_locals(struct ac_nir_context *ctx,
5528 struct nir_function *func)
5529 {
5530 int i, j;
5531 ctx->num_locals = 0;
5532 nir_foreach_variable(variable, &func->impl->locals) {
5533 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5534 variable->data.driver_location = ctx->num_locals * 4;
5535 ctx->num_locals += attrib_count;
5536 }
5537 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5538 if (!ctx->locals)
5539 return;
5540
5541 for (i = 0; i < ctx->num_locals; i++) {
5542 for (j = 0; j < 4; j++) {
5543 ctx->locals[i * 4 + j] =
5544 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5545 }
5546 }
5547 }
5548
5549 static void
5550 setup_shared(struct ac_nir_context *ctx,
5551 struct nir_shader *nir)
5552 {
5553 nir_foreach_variable(variable, &nir->shared) {
5554 LLVMValueRef shared =
5555 LLVMAddGlobalInAddressSpace(
5556 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5557 variable->name ? variable->name : "",
5558 LOCAL_ADDR_SPACE);
5559 _mesa_hash_table_insert(ctx->vars, variable, shared);
5560 }
5561 }
5562
5563 static LLVMValueRef
5564 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5565 {
5566 v = ac_to_float(ctx, v);
5567 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5568 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5569 }
5570
5571
5572 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5573 LLVMValueRef src0, LLVMValueRef src1)
5574 {
5575 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5576 LLVMValueRef comp[2];
5577
5578 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5579 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5580 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5581 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5582 }
5583
5584 /* Initialize arguments for the shader export intrinsic */
5585 static void
5586 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5587 LLVMValueRef *values,
5588 unsigned target,
5589 struct ac_export_args *args)
5590 {
5591 /* Default is 0xf. Adjusted below depending on the format. */
5592 args->enabled_channels = 0xf;
5593
5594 /* Specify whether the EXEC mask represents the valid mask */
5595 args->valid_mask = 0;
5596
5597 /* Specify whether this is the last export */
5598 args->done = 0;
5599
5600 /* Specify the target we are exporting */
5601 args->target = target;
5602
5603 args->compr = false;
5604 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5605 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5606 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5607 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5608
5609 if (!values)
5610 return;
5611
5612 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5613 LLVMValueRef val[4];
5614 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5615 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5616 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5617 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5618
5619 switch(col_format) {
5620 case V_028714_SPI_SHADER_ZERO:
5621 args->enabled_channels = 0; /* writemask */
5622 args->target = V_008DFC_SQ_EXP_NULL;
5623 break;
5624
5625 case V_028714_SPI_SHADER_32_R:
5626 args->enabled_channels = 1;
5627 args->out[0] = values[0];
5628 break;
5629
5630 case V_028714_SPI_SHADER_32_GR:
5631 args->enabled_channels = 0x3;
5632 args->out[0] = values[0];
5633 args->out[1] = values[1];
5634 break;
5635
5636 case V_028714_SPI_SHADER_32_AR:
5637 args->enabled_channels = 0x9;
5638 args->out[0] = values[0];
5639 args->out[3] = values[3];
5640 break;
5641
5642 case V_028714_SPI_SHADER_FP16_ABGR:
5643 args->compr = 1;
5644
5645 for (unsigned chan = 0; chan < 2; chan++) {
5646 LLVMValueRef pack_args[2] = {
5647 values[2 * chan],
5648 values[2 * chan + 1]
5649 };
5650 LLVMValueRef packed;
5651
5652 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5653 args->out[chan] = packed;
5654 }
5655 break;
5656
5657 case V_028714_SPI_SHADER_UNORM16_ABGR:
5658 for (unsigned chan = 0; chan < 4; chan++) {
5659 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5660 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5661 LLVMConstReal(ctx->ac.f32, 65535), "");
5662 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5663 LLVMConstReal(ctx->ac.f32, 0.5), "");
5664 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5665 ctx->ac.i32, "");
5666 }
5667
5668 args->compr = 1;
5669 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5670 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5671 break;
5672
5673 case V_028714_SPI_SHADER_SNORM16_ABGR:
5674 for (unsigned chan = 0; chan < 4; chan++) {
5675 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5676 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5677 LLVMConstReal(ctx->ac.f32, 32767), "");
5678
5679 /* If positive, add 0.5, else add -0.5. */
5680 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5681 LLVMBuildSelect(ctx->builder,
5682 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5683 val[chan], ctx->ac.f32_0, ""),
5684 LLVMConstReal(ctx->ac.f32, 0.5),
5685 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5686 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5687 }
5688
5689 args->compr = 1;
5690 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5691 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5692 break;
5693
5694 case V_028714_SPI_SHADER_UINT16_ABGR: {
5695 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5696 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5697 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5698
5699 for (unsigned chan = 0; chan < 4; chan++) {
5700 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5701 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5702 }
5703
5704 args->compr = 1;
5705 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5706 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5707 break;
5708 }
5709
5710 case V_028714_SPI_SHADER_SINT16_ABGR: {
5711 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5712 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5713 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5714 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5715 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5716 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5717
5718 /* Clamp. */
5719 for (unsigned chan = 0; chan < 4; chan++) {
5720 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5721 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5722 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5723 }
5724
5725 args->compr = 1;
5726 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5727 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5728 break;
5729 }
5730
5731 default:
5732 case V_028714_SPI_SHADER_32_ABGR:
5733 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5734 break;
5735 }
5736 } else
5737 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5738
5739 for (unsigned i = 0; i < 4; ++i)
5740 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5741 }
5742
5743 static void
5744 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5745 bool export_prim_id,
5746 struct ac_vs_output_info *outinfo)
5747 {
5748 uint32_t param_count = 0;
5749 unsigned target;
5750 unsigned pos_idx, num_pos_exports = 0;
5751 struct ac_export_args args, pos_args[4] = {};
5752 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5753 int i;
5754
5755 if (ctx->options->key.has_multiview_view_index) {
5756 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5757 if(!*tmp_out) {
5758 for(unsigned i = 0; i < 4; ++i)
5759 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5760 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5761 }
5762
5763 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5764 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5765 }
5766
5767 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5768 sizeof(outinfo->vs_output_param_offset));
5769
5770 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5771 LLVMValueRef slots[8];
5772 unsigned j;
5773
5774 if (outinfo->cull_dist_mask)
5775 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5776
5777 i = VARYING_SLOT_CLIP_DIST0;
5778 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5779 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5780 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5781
5782 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5783 slots[i] = LLVMGetUndef(ctx->ac.f32);
5784
5785 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5786 target = V_008DFC_SQ_EXP_POS + 3;
5787 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5788 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5789 &args, sizeof(args));
5790 }
5791
5792 target = V_008DFC_SQ_EXP_POS + 2;
5793 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5794 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5795 &args, sizeof(args));
5796
5797 }
5798
5799 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5800 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5801 for (unsigned j = 0; j < 4; j++)
5802 pos_values[j] = LLVMBuildLoad(ctx->builder,
5803 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5804 }
5805 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5806
5807 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5808 outinfo->writes_pointsize = true;
5809 psize_value = LLVMBuildLoad(ctx->builder,
5810 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5811 }
5812
5813 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5814 outinfo->writes_layer = true;
5815 layer_value = LLVMBuildLoad(ctx->builder,
5816 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5817 }
5818
5819 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5820 outinfo->writes_viewport_index = true;
5821 viewport_index_value = LLVMBuildLoad(ctx->builder,
5822 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5823 }
5824
5825 if (outinfo->writes_pointsize ||
5826 outinfo->writes_layer ||
5827 outinfo->writes_viewport_index) {
5828 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5829 (outinfo->writes_layer == true ? 4 : 0));
5830 pos_args[1].valid_mask = 0;
5831 pos_args[1].done = 0;
5832 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5833 pos_args[1].compr = 0;
5834 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5835 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5836 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5837 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5838
5839 if (outinfo->writes_pointsize == true)
5840 pos_args[1].out[0] = psize_value;
5841 if (outinfo->writes_layer == true)
5842 pos_args[1].out[2] = layer_value;
5843 if (outinfo->writes_viewport_index == true) {
5844 if (ctx->options->chip_class >= GFX9) {
5845 /* GFX9 has the layer in out.z[10:0] and the viewport
5846 * index in out.z[19:16].
5847 */
5848 LLVMValueRef v = viewport_index_value;
5849 v = ac_to_integer(&ctx->ac, v);
5850 v = LLVMBuildShl(ctx->builder, v,
5851 LLVMConstInt(ctx->ac.i32, 16, false),
5852 "");
5853 v = LLVMBuildOr(ctx->builder, v,
5854 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5855
5856 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5857 pos_args[1].enabled_channels |= 1 << 2;
5858 } else {
5859 pos_args[1].out[3] = viewport_index_value;
5860 pos_args[1].enabled_channels |= 1 << 3;
5861 }
5862 }
5863 }
5864 for (i = 0; i < 4; i++) {
5865 if (pos_args[i].out[0])
5866 num_pos_exports++;
5867 }
5868
5869 pos_idx = 0;
5870 for (i = 0; i < 4; i++) {
5871 if (!pos_args[i].out[0])
5872 continue;
5873
5874 /* Specify the target we are exporting */
5875 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5876 if (pos_idx == num_pos_exports)
5877 pos_args[i].done = 1;
5878 ac_build_export(&ctx->ac, &pos_args[i]);
5879 }
5880
5881 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5882 LLVMValueRef values[4];
5883 if (!(ctx->output_mask & (1ull << i)))
5884 continue;
5885
5886 for (unsigned j = 0; j < 4; j++)
5887 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5888 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5889
5890 if (i == VARYING_SLOT_LAYER) {
5891 target = V_008DFC_SQ_EXP_PARAM + param_count;
5892 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5893 param_count++;
5894 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5895 target = V_008DFC_SQ_EXP_PARAM + param_count;
5896 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5897 param_count++;
5898 } else if (i >= VARYING_SLOT_VAR0) {
5899 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5900 target = V_008DFC_SQ_EXP_PARAM + param_count;
5901 outinfo->vs_output_param_offset[i] = param_count;
5902 param_count++;
5903 } else
5904 continue;
5905
5906 si_llvm_init_export_args(ctx, values, target, &args);
5907
5908 if (target >= V_008DFC_SQ_EXP_POS &&
5909 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5910 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5911 &args, sizeof(args));
5912 } else {
5913 ac_build_export(&ctx->ac, &args);
5914 }
5915 }
5916
5917 if (export_prim_id) {
5918 LLVMValueRef values[4];
5919 target = V_008DFC_SQ_EXP_PARAM + param_count;
5920 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5921 param_count++;
5922
5923 values[0] = ctx->vs_prim_id;
5924 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5925 ctx->shader_info->vs.vgpr_comp_cnt);
5926 for (unsigned j = 1; j < 4; j++)
5927 values[j] = ctx->ac.f32_0;
5928 si_llvm_init_export_args(ctx, values, target, &args);
5929 ac_build_export(&ctx->ac, &args);
5930 outinfo->export_prim_id = true;
5931 }
5932
5933 outinfo->pos_exports = num_pos_exports;
5934 outinfo->param_exports = param_count;
5935 }
5936
5937 static void
5938 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5939 struct ac_es_output_info *outinfo)
5940 {
5941 int j;
5942 uint64_t max_output_written = 0;
5943 LLVMValueRef lds_base = NULL;
5944
5945 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5946 int param_index;
5947 int length = 4;
5948
5949 if (!(ctx->output_mask & (1ull << i)))
5950 continue;
5951
5952 if (i == VARYING_SLOT_CLIP_DIST0)
5953 length = ctx->num_output_clips + ctx->num_output_culls;
5954
5955 param_index = shader_io_get_unique_index(i);
5956
5957 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5958 }
5959
5960 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5961
5962 if (ctx->ac.chip_class >= GFX9) {
5963 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5964 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5965 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5966 LLVMConstInt(ctx->ac.i32, 24, false),
5967 LLVMConstInt(ctx->ac.i32, 4, false), false);
5968 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5969 LLVMBuildMul(ctx->ac.builder, wave_idx,
5970 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5971 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5972 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5973 }
5974
5975 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5976 LLVMValueRef dw_addr;
5977 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5978 int param_index;
5979 int length = 4;
5980
5981 if (!(ctx->output_mask & (1ull << i)))
5982 continue;
5983
5984 if (i == VARYING_SLOT_CLIP_DIST0)
5985 length = ctx->num_output_clips + ctx->num_output_culls;
5986
5987 param_index = shader_io_get_unique_index(i);
5988
5989 if (lds_base) {
5990 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5991 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
5992 "");
5993 }
5994 for (j = 0; j < length; j++) {
5995 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5996 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
5997
5998 if (ctx->ac.chip_class >= GFX9) {
5999 ac_lds_store(&ctx->ac, dw_addr,
6000 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6001 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6002 } else {
6003 ac_build_buffer_store_dword(&ctx->ac,
6004 ctx->esgs_ring,
6005 out_val, 1,
6006 NULL, ctx->es2gs_offset,
6007 (4 * param_index + j) * 4,
6008 1, 1, true, true);
6009 }
6010 }
6011 }
6012 }
6013
6014 static void
6015 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6016 {
6017 LLVMValueRef vertex_id = ctx->rel_auto_id;
6018 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6019 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6020 vertex_dw_stride, "");
6021
6022 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6023 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6024 int length = 4;
6025
6026 if (!(ctx->output_mask & (1ull << i)))
6027 continue;
6028
6029 if (i == VARYING_SLOT_CLIP_DIST0)
6030 length = ctx->num_output_clips + ctx->num_output_culls;
6031 int param = shader_io_get_unique_index(i);
6032 mark_tess_output(ctx, false, param);
6033 if (length > 4)
6034 mark_tess_output(ctx, false, param + 1);
6035 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6036 LLVMConstInt(ctx->ac.i32, param * 4, false),
6037 "");
6038 for (unsigned j = 0; j < length; j++) {
6039 ac_lds_store(&ctx->ac, dw_addr,
6040 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6041 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6042 }
6043 }
6044 }
6045
6046 struct ac_build_if_state
6047 {
6048 struct nir_to_llvm_context *ctx;
6049 LLVMValueRef condition;
6050 LLVMBasicBlockRef entry_block;
6051 LLVMBasicBlockRef true_block;
6052 LLVMBasicBlockRef false_block;
6053 LLVMBasicBlockRef merge_block;
6054 };
6055
6056 static LLVMBasicBlockRef
6057 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6058 {
6059 LLVMBasicBlockRef current_block;
6060 LLVMBasicBlockRef next_block;
6061 LLVMBasicBlockRef new_block;
6062
6063 /* get current basic block */
6064 current_block = LLVMGetInsertBlock(ctx->builder);
6065
6066 /* chqeck if there's another block after this one */
6067 next_block = LLVMGetNextBasicBlock(current_block);
6068 if (next_block) {
6069 /* insert the new block before the next block */
6070 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6071 }
6072 else {
6073 /* append new block after current block */
6074 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6075 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6076 }
6077 return new_block;
6078 }
6079
6080 static void
6081 ac_nir_build_if(struct ac_build_if_state *ifthen,
6082 struct nir_to_llvm_context *ctx,
6083 LLVMValueRef condition)
6084 {
6085 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6086
6087 memset(ifthen, 0, sizeof *ifthen);
6088 ifthen->ctx = ctx;
6089 ifthen->condition = condition;
6090 ifthen->entry_block = block;
6091
6092 /* create endif/merge basic block for the phi functions */
6093 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6094
6095 /* create/insert true_block before merge_block */
6096 ifthen->true_block =
6097 LLVMInsertBasicBlockInContext(ctx->context,
6098 ifthen->merge_block,
6099 "if-true-block");
6100
6101 /* successive code goes into the true block */
6102 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6103 }
6104
6105 /**
6106 * End a conditional.
6107 */
6108 static void
6109 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6110 {
6111 LLVMBuilderRef builder = ifthen->ctx->builder;
6112
6113 /* Insert branch to the merge block from current block */
6114 LLVMBuildBr(builder, ifthen->merge_block);
6115
6116 /*
6117 * Now patch in the various branch instructions.
6118 */
6119
6120 /* Insert the conditional branch instruction at the end of entry_block */
6121 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6122 if (ifthen->false_block) {
6123 /* we have an else clause */
6124 LLVMBuildCondBr(builder, ifthen->condition,
6125 ifthen->true_block, ifthen->false_block);
6126 }
6127 else {
6128 /* no else clause */
6129 LLVMBuildCondBr(builder, ifthen->condition,
6130 ifthen->true_block, ifthen->merge_block);
6131 }
6132
6133 /* Resume building code at end of the ifthen->merge_block */
6134 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6135 }
6136
6137 static void
6138 write_tess_factors(struct nir_to_llvm_context *ctx)
6139 {
6140 unsigned stride, outer_comps, inner_comps;
6141 struct ac_build_if_state if_ctx, inner_if_ctx;
6142 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6143 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6144 unsigned tess_inner_index, tess_outer_index;
6145 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6146 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6147 int i;
6148 emit_barrier(ctx);
6149
6150 switch (ctx->options->key.tcs.primitive_mode) {
6151 case GL_ISOLINES:
6152 stride = 2;
6153 outer_comps = 2;
6154 inner_comps = 0;
6155 break;
6156 case GL_TRIANGLES:
6157 stride = 4;
6158 outer_comps = 3;
6159 inner_comps = 1;
6160 break;
6161 case GL_QUADS:
6162 stride = 6;
6163 outer_comps = 4;
6164 inner_comps = 2;
6165 break;
6166 default:
6167 return;
6168 }
6169
6170 ac_nir_build_if(&if_ctx, ctx,
6171 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6172 invocation_id, ctx->ac.i32_0, ""));
6173
6174 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6175 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6176
6177 mark_tess_output(ctx, true, tess_inner_index);
6178 mark_tess_output(ctx, true, tess_outer_index);
6179 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6180 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6181 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6182 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6183 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6184
6185 for (i = 0; i < 4; i++) {
6186 inner[i] = LLVMGetUndef(ctx->ac.i32);
6187 outer[i] = LLVMGetUndef(ctx->ac.i32);
6188 }
6189
6190 // LINES reverseal
6191 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6192 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6193 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6194 ctx->ac.i32_1, "");
6195 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6196 } else {
6197 for (i = 0; i < outer_comps; i++) {
6198 outer[i] = out[i] =
6199 ac_lds_load(&ctx->ac, lds_outer);
6200 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6201 ctx->ac.i32_1, "");
6202 }
6203 for (i = 0; i < inner_comps; i++) {
6204 inner[i] = out[outer_comps+i] =
6205 ac_lds_load(&ctx->ac, lds_inner);
6206 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6207 ctx->ac.i32_1, "");
6208 }
6209 }
6210
6211 /* Convert the outputs to vectors for stores. */
6212 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6213 vec1 = NULL;
6214
6215 if (stride > 4)
6216 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6217
6218
6219 buffer = ctx->hs_ring_tess_factor;
6220 tf_base = ctx->tess_factor_offset;
6221 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6222 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6223 unsigned tf_offset = 0;
6224
6225 if (ctx->options->chip_class <= VI) {
6226 ac_nir_build_if(&inner_if_ctx, ctx,
6227 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6228 rel_patch_id, ctx->ac.i32_0, ""));
6229
6230 /* Store the dynamic HS control word. */
6231 ac_build_buffer_store_dword(&ctx->ac, buffer,
6232 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6233 1, ctx->ac.i32_0, tf_base,
6234 0, 1, 0, true, false);
6235 tf_offset += 4;
6236
6237 ac_nir_build_endif(&inner_if_ctx);
6238 }
6239
6240 /* Store the tessellation factors. */
6241 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6242 MIN2(stride, 4), byteoffset, tf_base,
6243 tf_offset, 1, 0, true, false);
6244 if (vec1)
6245 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6246 stride - 4, byteoffset, tf_base,
6247 16 + tf_offset, 1, 0, true, false);
6248
6249 //store to offchip for TES to read - only if TES reads them
6250 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6251 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6252 LLVMValueRef tf_inner_offset;
6253 unsigned param_outer, param_inner;
6254
6255 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6256 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6257 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6258
6259 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6260 util_next_power_of_two(outer_comps));
6261
6262 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6263 outer_comps, tf_outer_offset,
6264 ctx->oc_lds, 0, 1, 0, true, false);
6265 if (inner_comps) {
6266 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6267 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6268 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6269
6270 inner_vec = inner_comps == 1 ? inner[0] :
6271 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6272 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6273 inner_comps, tf_inner_offset,
6274 ctx->oc_lds, 0, 1, 0, true, false);
6275 }
6276 }
6277 ac_nir_build_endif(&if_ctx);
6278 }
6279
6280 static void
6281 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6282 {
6283 write_tess_factors(ctx);
6284 }
6285
6286 static bool
6287 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6288 LLVMValueRef *color, unsigned param, bool is_last,
6289 struct ac_export_args *args)
6290 {
6291 /* Export */
6292 si_llvm_init_export_args(ctx, color, param,
6293 args);
6294
6295 if (is_last) {
6296 args->valid_mask = 1; /* whether the EXEC mask is valid */
6297 args->done = 1; /* DONE bit */
6298 } else if (!args->enabled_channels)
6299 return false; /* unnecessary NULL export */
6300
6301 return true;
6302 }
6303
6304 static void
6305 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6306 LLVMValueRef depth, LLVMValueRef stencil,
6307 LLVMValueRef samplemask)
6308 {
6309 struct ac_export_args args;
6310
6311 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6312
6313 ac_build_export(&ctx->ac, &args);
6314 }
6315
6316 static void
6317 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6318 {
6319 unsigned index = 0;
6320 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6321 struct ac_export_args color_args[8];
6322
6323 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6324 LLVMValueRef values[4];
6325
6326 if (!(ctx->output_mask & (1ull << i)))
6327 continue;
6328
6329 if (i == FRAG_RESULT_DEPTH) {
6330 ctx->shader_info->fs.writes_z = true;
6331 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6332 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6333 } else if (i == FRAG_RESULT_STENCIL) {
6334 ctx->shader_info->fs.writes_stencil = true;
6335 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6336 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6337 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6338 ctx->shader_info->fs.writes_sample_mask = true;
6339 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6340 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6341 } else {
6342 bool last = false;
6343 for (unsigned j = 0; j < 4; j++)
6344 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6345 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6346
6347 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6348 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6349
6350 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6351 if (ret)
6352 index++;
6353 }
6354 }
6355
6356 for (unsigned i = 0; i < index; i++)
6357 ac_build_export(&ctx->ac, &color_args[i]);
6358 if (depth || stencil || samplemask)
6359 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6360 else if (!index) {
6361 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6362 ac_build_export(&ctx->ac, &color_args[0]);
6363 }
6364
6365 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6366 }
6367
6368 static void
6369 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6370 {
6371 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6372 }
6373
6374 static void
6375 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6376 LLVMValueRef *addrs)
6377 {
6378 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6379
6380 switch (ctx->stage) {
6381 case MESA_SHADER_VERTEX:
6382 if (ctx->options->key.vs.as_ls)
6383 handle_ls_outputs_post(ctx);
6384 else if (ctx->options->key.vs.as_es)
6385 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6386 else
6387 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6388 &ctx->shader_info->vs.outinfo);
6389 break;
6390 case MESA_SHADER_FRAGMENT:
6391 handle_fs_outputs_post(ctx);
6392 break;
6393 case MESA_SHADER_GEOMETRY:
6394 emit_gs_epilogue(ctx);
6395 break;
6396 case MESA_SHADER_TESS_CTRL:
6397 handle_tcs_outputs_post(ctx);
6398 break;
6399 case MESA_SHADER_TESS_EVAL:
6400 if (ctx->options->key.tes.as_es)
6401 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6402 else
6403 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6404 &ctx->shader_info->tes.outinfo);
6405 break;
6406 default:
6407 break;
6408 }
6409 }
6410
6411 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6412 {
6413 LLVMPassManagerRef passmgr;
6414 /* Create the pass manager */
6415 passmgr = LLVMCreateFunctionPassManagerForModule(
6416 ctx->module);
6417
6418 /* This pass should eliminate all the load and store instructions */
6419 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6420
6421 /* Add some optimization passes */
6422 LLVMAddScalarReplAggregatesPass(passmgr);
6423 LLVMAddLICMPass(passmgr);
6424 LLVMAddAggressiveDCEPass(passmgr);
6425 LLVMAddCFGSimplificationPass(passmgr);
6426 LLVMAddInstructionCombiningPass(passmgr);
6427
6428 /* Run the pass */
6429 LLVMInitializeFunctionPassManager(passmgr);
6430 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6431 LLVMFinalizeFunctionPassManager(passmgr);
6432
6433 LLVMDisposeBuilder(ctx->builder);
6434 LLVMDisposePassManager(passmgr);
6435 }
6436
6437 static void
6438 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6439 {
6440 struct ac_vs_output_info *outinfo;
6441
6442 switch (ctx->stage) {
6443 case MESA_SHADER_FRAGMENT:
6444 case MESA_SHADER_COMPUTE:
6445 case MESA_SHADER_TESS_CTRL:
6446 case MESA_SHADER_GEOMETRY:
6447 return;
6448 case MESA_SHADER_VERTEX:
6449 if (ctx->options->key.vs.as_ls ||
6450 ctx->options->key.vs.as_es)
6451 return;
6452 outinfo = &ctx->shader_info->vs.outinfo;
6453 break;
6454 case MESA_SHADER_TESS_EVAL:
6455 if (ctx->options->key.vs.as_es)
6456 return;
6457 outinfo = &ctx->shader_info->tes.outinfo;
6458 break;
6459 default:
6460 unreachable("Unhandled shader type");
6461 }
6462
6463 ac_optimize_vs_outputs(&ctx->ac,
6464 ctx->main_function,
6465 outinfo->vs_output_param_offset,
6466 VARYING_SLOT_MAX,
6467 &outinfo->param_exports);
6468 }
6469
6470 static void
6471 ac_setup_rings(struct nir_to_llvm_context *ctx)
6472 {
6473 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6474 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6475 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6476 }
6477
6478 if (ctx->is_gs_copy_shader) {
6479 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6480 }
6481 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6482 LLVMValueRef tmp;
6483 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6484 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6485
6486 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6487
6488 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6489 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6490 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6491 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6492 }
6493
6494 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6495 ctx->stage == MESA_SHADER_TESS_EVAL) {
6496 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6497 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6498 }
6499 }
6500
6501 static unsigned
6502 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6503 const struct nir_shader *nir)
6504 {
6505 switch (nir->info.stage) {
6506 case MESA_SHADER_TESS_CTRL:
6507 return chip_class >= CIK ? 128 : 64;
6508 case MESA_SHADER_GEOMETRY:
6509 return chip_class >= GFX9 ? 128 : 64;
6510 case MESA_SHADER_COMPUTE:
6511 break;
6512 default:
6513 return 0;
6514 }
6515
6516 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6517 nir->info.cs.local_size[1] *
6518 nir->info.cs.local_size[2];
6519 return max_workgroup_size;
6520 }
6521
6522 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6523 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6524 {
6525 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6526 LLVMConstInt(ctx->ac.i32, 8, false),
6527 LLVMConstInt(ctx->ac.i32, 8, false), false);
6528 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6529 ctx->ac.i32_0, "");
6530 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6531 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6532 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6533 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6534 }
6535
6536 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6537 {
6538 for(int i = 5; i >= 0; --i) {
6539 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6540 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6541 LLVMConstInt(ctx->ac.i32, 16, false), false);
6542 }
6543
6544 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6545 LLVMConstInt(ctx->ac.i32, 16, false),
6546 LLVMConstInt(ctx->ac.i32, 8, false), false);
6547 }
6548
6549 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6550 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6551 {
6552 struct ac_nir_context ctx = {};
6553 struct nir_function *func;
6554
6555 ctx.ac = *ac;
6556 ctx.abi = abi;
6557
6558 ctx.nctx = nctx;
6559 if (nctx)
6560 nctx->nir = &ctx;
6561
6562 ctx.stage = nir->info.stage;
6563
6564 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6565
6566 nir_foreach_variable(variable, &nir->outputs)
6567 handle_shader_output_decl(&ctx, nir, variable);
6568
6569 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6570 _mesa_key_pointer_equal);
6571 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6572 _mesa_key_pointer_equal);
6573 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6574 _mesa_key_pointer_equal);
6575
6576 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6577
6578 setup_locals(&ctx, func);
6579
6580 if (nir->info.stage == MESA_SHADER_COMPUTE)
6581 setup_shared(&ctx, nir);
6582
6583 visit_cf_list(&ctx, &func->impl->body);
6584 phi_post_pass(&ctx);
6585
6586 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6587 ctx.outputs);
6588
6589 free(ctx.locals);
6590 ralloc_free(ctx.defs);
6591 ralloc_free(ctx.phis);
6592 ralloc_free(ctx.vars);
6593
6594 if (nctx)
6595 nctx->nir = NULL;
6596 }
6597
6598 static
6599 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6600 struct nir_shader *const *shaders,
6601 int shader_count,
6602 struct ac_shader_variant_info *shader_info,
6603 const struct ac_nir_compiler_options *options)
6604 {
6605 struct nir_to_llvm_context ctx = {0};
6606 unsigned i;
6607 ctx.options = options;
6608 ctx.shader_info = shader_info;
6609 ctx.context = LLVMContextCreate();
6610 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6611
6612 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6613 options->family);
6614 ctx.ac.module = ctx.module;
6615 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6616
6617 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6618 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6619 LLVMSetDataLayout(ctx.module, data_layout_str);
6620 LLVMDisposeTargetData(data_layout);
6621 LLVMDisposeMessage(data_layout_str);
6622
6623 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6624 ctx.ac.builder = ctx.builder;
6625
6626 memset(shader_info, 0, sizeof(*shader_info));
6627
6628 for(int i = 0; i < shader_count; ++i)
6629 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6630
6631 for (i = 0; i < AC_UD_MAX_SETS; i++)
6632 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6633 for (i = 0; i < AC_UD_MAX_UD; i++)
6634 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6635
6636 ctx.max_workgroup_size = 0;
6637 for (int i = 0; i < shader_count; ++i) {
6638 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6639 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6640 shaders[i]));
6641 }
6642
6643 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6644 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6645
6646 ctx.abi.inputs = &ctx.inputs[0];
6647 ctx.abi.emit_outputs = handle_shader_outputs_post;
6648 ctx.abi.emit_vertex = visit_emit_vertex;
6649 ctx.abi.load_ubo = radv_load_ubo;
6650 ctx.abi.load_ssbo = radv_load_ssbo;
6651 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6652 ctx.abi.clamp_shadow_reference = false;
6653
6654 if (shader_count >= 2)
6655 ac_init_exec_full_mask(&ctx.ac);
6656
6657 if (ctx.ac.chip_class == GFX9 &&
6658 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6659 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6660
6661 for(int i = 0; i < shader_count; ++i) {
6662 ctx.stage = shaders[i]->info.stage;
6663 ctx.output_mask = 0;
6664 ctx.tess_outputs_written = 0;
6665 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6666 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6667
6668 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6669 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6670 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6671 ctx.abi.load_inputs = load_gs_input;
6672 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6673 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6674 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6675 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6676 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6677 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6678 if (shader_info->info.vs.needs_instance_id) {
6679 ctx.shader_info->vs.vgpr_comp_cnt =
6680 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6681 }
6682 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6683 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6684 }
6685
6686 if (i)
6687 emit_barrier(&ctx);
6688
6689 ac_setup_rings(&ctx);
6690
6691 LLVMBasicBlockRef merge_block;
6692 if (shader_count >= 2) {
6693 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6694 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6695 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6696
6697 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6698 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6699 LLVMConstInt(ctx.ac.i32, 8, false), false);
6700 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6701 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6702 thread_id, count, "");
6703 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6704
6705 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6706 }
6707
6708 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6709 handle_fs_inputs(&ctx, shaders[i]);
6710 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6711 handle_vs_inputs(&ctx, shaders[i]);
6712 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6713 prepare_gs_input_vgprs(&ctx);
6714
6715 nir_foreach_variable(variable, &shaders[i]->outputs)
6716 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6717
6718 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6719
6720 if (shader_count >= 2) {
6721 LLVMBuildBr(ctx.ac.builder, merge_block);
6722 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6723 }
6724
6725 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6726 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6727 shaders[i]->info.cull_distance_array_size > 4;
6728 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6729 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6730 shaders[i]->info.gs.vertices_out;
6731 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6732 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6733 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6734 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6735 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6736 }
6737 }
6738
6739 LLVMBuildRetVoid(ctx.builder);
6740
6741 ac_llvm_finalize_module(&ctx);
6742
6743 if (shader_count == 1)
6744 ac_nir_eliminate_const_vs_outputs(&ctx);
6745
6746 return ctx.module;
6747 }
6748
6749 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6750 {
6751 unsigned *retval = (unsigned *)context;
6752 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6753 char *description = LLVMGetDiagInfoDescription(di);
6754
6755 if (severity == LLVMDSError) {
6756 *retval = 1;
6757 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6758 description);
6759 }
6760
6761 LLVMDisposeMessage(description);
6762 }
6763
6764 static unsigned ac_llvm_compile(LLVMModuleRef M,
6765 struct ac_shader_binary *binary,
6766 LLVMTargetMachineRef tm)
6767 {
6768 unsigned retval = 0;
6769 char *err;
6770 LLVMContextRef llvm_ctx;
6771 LLVMMemoryBufferRef out_buffer;
6772 unsigned buffer_size;
6773 const char *buffer_data;
6774 LLVMBool mem_err;
6775
6776 /* Setup Diagnostic Handler*/
6777 llvm_ctx = LLVMGetModuleContext(M);
6778
6779 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6780 &retval);
6781
6782 /* Compile IR*/
6783 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6784 &err, &out_buffer);
6785
6786 /* Process Errors/Warnings */
6787 if (mem_err) {
6788 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6789 free(err);
6790 retval = 1;
6791 goto out;
6792 }
6793
6794 /* Extract Shader Code*/
6795 buffer_size = LLVMGetBufferSize(out_buffer);
6796 buffer_data = LLVMGetBufferStart(out_buffer);
6797
6798 ac_elf_read(buffer_data, buffer_size, binary);
6799
6800 /* Clean up */
6801 LLVMDisposeMemoryBuffer(out_buffer);
6802
6803 out:
6804 return retval;
6805 }
6806
6807 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6808 LLVMModuleRef llvm_module,
6809 struct ac_shader_binary *binary,
6810 struct ac_shader_config *config,
6811 struct ac_shader_variant_info *shader_info,
6812 gl_shader_stage stage,
6813 bool dump_shader, bool supports_spill)
6814 {
6815 if (dump_shader)
6816 ac_dump_module(llvm_module);
6817
6818 memset(binary, 0, sizeof(*binary));
6819 int v = ac_llvm_compile(llvm_module, binary, tm);
6820 if (v) {
6821 fprintf(stderr, "compile failed\n");
6822 }
6823
6824 if (dump_shader)
6825 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6826
6827 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6828
6829 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6830 LLVMDisposeModule(llvm_module);
6831 LLVMContextDispose(ctx);
6832
6833 if (stage == MESA_SHADER_FRAGMENT) {
6834 shader_info->num_input_vgprs = 0;
6835 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6836 shader_info->num_input_vgprs += 2;
6837 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6838 shader_info->num_input_vgprs += 2;
6839 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6840 shader_info->num_input_vgprs += 2;
6841 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6842 shader_info->num_input_vgprs += 3;
6843 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6844 shader_info->num_input_vgprs += 2;
6845 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6846 shader_info->num_input_vgprs += 2;
6847 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6848 shader_info->num_input_vgprs += 2;
6849 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6850 shader_info->num_input_vgprs += 1;
6851 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6852 shader_info->num_input_vgprs += 1;
6853 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6854 shader_info->num_input_vgprs += 1;
6855 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6856 shader_info->num_input_vgprs += 1;
6857 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6858 shader_info->num_input_vgprs += 1;
6859 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6860 shader_info->num_input_vgprs += 1;
6861 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6862 shader_info->num_input_vgprs += 1;
6863 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6864 shader_info->num_input_vgprs += 1;
6865 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6866 shader_info->num_input_vgprs += 1;
6867 }
6868 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6869
6870 /* +3 for scratch wave offset and VCC */
6871 config->num_sgprs = MAX2(config->num_sgprs,
6872 shader_info->num_input_sgprs + 3);
6873 }
6874
6875 static void
6876 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6877 {
6878 switch (nir->info.stage) {
6879 case MESA_SHADER_COMPUTE:
6880 for (int i = 0; i < 3; ++i)
6881 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6882 break;
6883 case MESA_SHADER_FRAGMENT:
6884 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6885 break;
6886 case MESA_SHADER_GEOMETRY:
6887 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6888 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6889 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6890 shader_info->gs.invocations = nir->info.gs.invocations;
6891 break;
6892 case MESA_SHADER_TESS_EVAL:
6893 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6894 shader_info->tes.spacing = nir->info.tess.spacing;
6895 shader_info->tes.ccw = nir->info.tess.ccw;
6896 shader_info->tes.point_mode = nir->info.tess.point_mode;
6897 shader_info->tes.as_es = options->key.tes.as_es;
6898 break;
6899 case MESA_SHADER_TESS_CTRL:
6900 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6901 break;
6902 case MESA_SHADER_VERTEX:
6903 shader_info->vs.as_es = options->key.vs.as_es;
6904 shader_info->vs.as_ls = options->key.vs.as_ls;
6905 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6906 if (options->key.vs.as_ls)
6907 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6908 break;
6909 default:
6910 break;
6911 }
6912 }
6913
6914 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6915 struct ac_shader_binary *binary,
6916 struct ac_shader_config *config,
6917 struct ac_shader_variant_info *shader_info,
6918 struct nir_shader *const *nir,
6919 int nir_count,
6920 const struct ac_nir_compiler_options *options,
6921 bool dump_shader)
6922 {
6923
6924 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6925 options);
6926
6927 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6928 for (int i = 0; i < nir_count; ++i)
6929 ac_fill_shader_info(shader_info, nir[i], options);
6930 }
6931
6932 static void
6933 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6934 {
6935 LLVMValueRef args[9];
6936 args[0] = ctx->gsvs_ring;
6937 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6938 args[3] = ctx->ac.i32_0;
6939 args[4] = ctx->ac.i32_1; /* OFFEN */
6940 args[5] = ctx->ac.i32_0; /* IDXEN */
6941 args[6] = ctx->ac.i32_1; /* GLC */
6942 args[7] = ctx->ac.i32_1; /* SLC */
6943 args[8] = ctx->ac.i32_0; /* TFE */
6944
6945 int idx = 0;
6946
6947 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6948 int length = 4;
6949 int slot = idx;
6950 int slot_inc = 1;
6951 if (!(ctx->output_mask & (1ull << i)))
6952 continue;
6953
6954 if (i == VARYING_SLOT_CLIP_DIST0) {
6955 /* unpack clip and cull from a single set of slots */
6956 length = ctx->num_output_clips + ctx->num_output_culls;
6957 if (length > 4)
6958 slot_inc = 2;
6959 }
6960
6961 for (unsigned j = 0; j < length; j++) {
6962 LLVMValueRef value;
6963 args[2] = LLVMConstInt(ctx->ac.i32,
6964 (slot * 4 + j) *
6965 ctx->gs_max_out_vertices * 16 * 4, false);
6966
6967 value = ac_build_intrinsic(&ctx->ac,
6968 "llvm.SI.buffer.load.dword.i32.i32",
6969 ctx->ac.i32, args, 9,
6970 AC_FUNC_ATTR_READONLY |
6971 AC_FUNC_ATTR_LEGACY);
6972
6973 LLVMBuildStore(ctx->builder,
6974 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6975 }
6976 idx += slot_inc;
6977 }
6978 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6979 }
6980
6981 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6982 struct nir_shader *geom_shader,
6983 struct ac_shader_binary *binary,
6984 struct ac_shader_config *config,
6985 struct ac_shader_variant_info *shader_info,
6986 const struct ac_nir_compiler_options *options,
6987 bool dump_shader)
6988 {
6989 struct nir_to_llvm_context ctx = {0};
6990 ctx.context = LLVMContextCreate();
6991 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6992 ctx.options = options;
6993 ctx.shader_info = shader_info;
6994
6995 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6996 options->family);
6997 ctx.ac.module = ctx.module;
6998
6999 ctx.is_gs_copy_shader = true;
7000 LLVMSetTarget(ctx.module, "amdgcn--");
7001
7002 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
7003 ctx.ac.builder = ctx.builder;
7004 ctx.stage = MESA_SHADER_VERTEX;
7005
7006 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7007
7008 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7009 ac_setup_rings(&ctx);
7010
7011 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7012 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7013
7014 struct ac_nir_context nir_ctx = {};
7015 nir_ctx.ac = ctx.ac;
7016 nir_ctx.abi = &ctx.abi;
7017
7018 nir_ctx.nctx = &ctx;
7019 ctx.nir = &nir_ctx;
7020
7021 nir_foreach_variable(variable, &geom_shader->outputs) {
7022 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7023 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7024 }
7025
7026 ac_gs_copy_shader_emit(&ctx);
7027
7028 ctx.nir = NULL;
7029
7030 LLVMBuildRetVoid(ctx.builder);
7031
7032 ac_llvm_finalize_module(&ctx);
7033
7034 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7035 MESA_SHADER_VERTEX,
7036 dump_shader, options->supports_spill);
7037 }